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j2.patch 51 KB

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  1. diff -Nur binutils-2.28.orig/bfd/archures.c binutils-2.28/bfd/archures.c
  2. --- binutils-2.28.orig/bfd/archures.c 2017-03-02 09:23:53.000000000 +0100
  3. +++ binutils-2.28/bfd/archures.c 2017-03-09 05:45:38.004728034 +0100
  4. @@ -310,10 +310,12 @@
  5. .#define bfd_mach_sh_dsp 0x2d
  6. .#define bfd_mach_sh2a 0x2a
  7. .#define bfd_mach_sh2a_nofpu 0x2b
  8. +.#define bfd_mach_shj2 0x2c
  9. .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
  10. .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
  11. .#define bfd_mach_sh2a_or_sh4 0x2a3
  12. .#define bfd_mach_sh2a_or_sh3e 0x2a4
  13. +.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
  14. .#define bfd_mach_sh2e 0x2e
  15. .#define bfd_mach_sh3 0x30
  16. .#define bfd_mach_sh3_nommu 0x31
  17. diff -Nur binutils-2.28.orig/bfd/bfd-in2.h binutils-2.28/bfd/bfd-in2.h
  18. --- binutils-2.28.orig/bfd/bfd-in2.h 2017-03-02 09:23:53.000000000 +0100
  19. +++ binutils-2.28/bfd/bfd-in2.h 2017-03-09 05:45:38.008728189 +0100
  20. @@ -2154,10 +2154,12 @@
  21. #define bfd_mach_sh_dsp 0x2d
  22. #define bfd_mach_sh2a 0x2a
  23. #define bfd_mach_sh2a_nofpu 0x2b
  24. +#define bfd_mach_shj2 0x2c
  25. #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
  26. #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
  27. #define bfd_mach_sh2a_or_sh4 0x2a3
  28. #define bfd_mach_sh2a_or_sh3e 0x2a4
  29. +#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
  30. #define bfd_mach_sh2e 0x2e
  31. #define bfd_mach_sh3 0x30
  32. #define bfd_mach_sh3_nommu 0x31
  33. diff -Nur binutils-2.28.orig/bfd/cpu-sh.c binutils-2.28/bfd/cpu-sh.c
  34. --- binutils-2.28.orig/bfd/cpu-sh.c 2017-03-02 09:23:53.000000000 +0100
  35. +++ binutils-2.28/bfd/cpu-sh.c 2017-03-09 05:45:38.008728189 +0100
  36. @@ -44,7 +44,9 @@
  37. #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
  38. #define SH2A_OR_SH4_NEXT arch_info_struct + 18
  39. #define SH2A_OR_SH3E_NEXT arch_info_struct + 19
  40. -#define SH64_NEXT NULL
  41. +#define SH64_NEXT arch_info_struct + 20
  42. +#define SHJ2_NEXT arch_info_struct + 21
  43. +#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
  44. static const bfd_arch_info_type arch_info_struct[] =
  45. {
  46. @@ -348,6 +350,36 @@
  47. bfd_arch_default_fill,
  48. SH64_NEXT
  49. },
  50. + {
  51. + 32, /* 32 bits in a word. */
  52. + 32, /* 32 bits in an address. */
  53. + 8, /* 8 bits in a byte. */
  54. + bfd_arch_sh,
  55. + bfd_mach_shj2,
  56. + "sh", /* Architecture name. . */
  57. + "j2", /* Machine name. */
  58. + 1,
  59. + FALSE, /* Not the default. */
  60. + bfd_default_compatible,
  61. + bfd_default_scan,
  62. + bfd_arch_default_fill,
  63. + SHJ2_NEXT
  64. + },
  65. + {
  66. + 32, /* 32 bits in a word. */
  67. + 32, /* 32 bits in an address. */
  68. + 8, /* 8 bits in a byte. */
  69. + bfd_arch_sh,
  70. + bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
  71. + "sh", /* Architecture name. . */
  72. + "sh2a-or-sh3e-or-j2", /* Machine name. */
  73. + 1,
  74. + FALSE, /* Not the default. */
  75. + bfd_default_compatible,
  76. + bfd_default_scan,
  77. + bfd_arch_default_fill,
  78. + SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
  79. + },
  80. };
  81. const bfd_arch_info_type bfd_sh_arch =
  82. @@ -398,6 +430,8 @@
  83. { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
  84. { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
  85. { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
  86. + { bfd_mach_shj2, arch_shj2, arch_shj2_up },
  87. + { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
  88. { 0, 0, 0 } /* Terminator. */
  89. };
  90. diff -Nur binutils-2.28.orig/binutils/readelf.c binutils-2.28/binutils/readelf.c
  91. --- binutils-2.28.orig/binutils/readelf.c 2017-03-02 09:23:53.000000000 +0100
  92. +++ binutils-2.28/binutils/readelf.c 2017-03-09 05:45:40.720833187 +0100
  93. @@ -3362,6 +3362,8 @@
  94. case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
  95. case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
  96. case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
  97. + case EF_SHJ2: strcat (buf, ", j2"); break;
  98. + case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
  99. default: strcat (buf, _(", unknown ISA")); break;
  100. }
  101. diff -Nur binutils-2.28.orig/gas/config/tc-sh.c binutils-2.28/gas/config/tc-sh.c
  102. --- binutils-2.28.orig/gas/config/tc-sh.c 2017-03-02 09:23:53.000000000 +0100
  103. +++ binutils-2.28/gas/config/tc-sh.c 2017-03-09 05:45:40.720833187 +0100
  104. @@ -1648,6 +1648,8 @@
  105. ptr++;
  106. }
  107. get_operand (&ptr, operand + 2);
  108. + if (strcmp (info->name,"cas") == 0)
  109. + operand[2].type = A_IND_0;
  110. }
  111. else
  112. {
  113. @@ -2187,7 +2189,10 @@
  114. goto fail;
  115. reg_m = 4;
  116. break;
  117. -
  118. + case A_IND_0:
  119. + if (user->reg != 0)
  120. + goto fail;
  121. + break;
  122. default:
  123. printf (_("unhandled %d\n"), arg);
  124. goto fail;
  125. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
  126. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2015-11-13 09:27:41.000000000 +0100
  127. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2017-03-09 05:45:40.720833187 +0100
  128. @@ -12,8 +12,6 @@
  129. sh2a_nofpu_or_sh3_nommu:
  130. ! Instructions introduced into sh2a-nofpu-or-sh3-nommu
  131. pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
  132. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  133. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  134. ! Instructions inherited from ancestors: sh sh2
  135. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  136. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
  137. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  138. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2017-03-09 05:45:40.720833187 +0100
  139. @@ -12,7 +12,7 @@
  140. sh2a_nofpu_or_sh4_nommu_nofpu:
  141. ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
  142. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
  143. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
  144. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  145. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  146. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  147. @@ -119,8 +119,8 @@
  148. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  149. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  150. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  151. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  152. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  153. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  154. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  155. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  156. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  157. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  158. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
  159. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  160. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2017-03-09 05:45:40.720833187 +0100
  161. @@ -64,7 +64,7 @@
  162. movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
  163. movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
  164. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
  165. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
  166. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  167. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  168. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  169. @@ -171,8 +171,8 @@
  170. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  171. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  172. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  173. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  174. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  175. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  176. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  177. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  178. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  179. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  180. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
  181. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2015-11-13 09:27:41.000000000 +0100
  182. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2017-03-09 05:45:40.720833187 +0100
  183. @@ -13,7 +13,7 @@
  184. ! Instructions introduced into sh2a-or-sh3e
  185. fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
  186. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
  187. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
  188. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  189. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  190. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  191. @@ -124,8 +124,8 @@
  192. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  193. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  194. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  195. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  196. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  197. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  198. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  199. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  200. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  201. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  202. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
  203. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2015-11-13 09:27:41.000000000 +0100
  204. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2017-03-09 05:45:40.720833187 +0100
  205. @@ -39,7 +39,7 @@
  206. fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
  207. ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
  208. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
  209. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
  210. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  211. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  212. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  213. @@ -150,8 +150,8 @@
  214. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  215. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  216. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  217. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  218. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  219. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  220. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  221. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  222. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  223. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  224. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a.s
  225. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a.s 2015-11-13 09:27:41.000000000 +0100
  226. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a.s 2017-03-09 05:45:40.724833342 +0100
  227. @@ -16,7 +16,7 @@
  228. fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
  229. fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
  230. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
  231. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
  232. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  233. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  234. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  235. @@ -140,8 +140,8 @@
  236. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  237. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  238. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  239. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  240. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  241. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  242. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  243. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  244. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  245. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  246. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3-dsp.s
  247. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2015-11-13 09:27:41.000000000 +0100
  248. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3-dsp.s 2017-03-09 05:45:40.724833342 +0100
  249. @@ -12,7 +12,7 @@
  250. sh3_dsp:
  251. ! Instructions introduced into sh3-dsp
  252. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
  253. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
  254. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  255. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  256. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  257. @@ -152,8 +152,8 @@
  258. setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
  259. repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
  260. repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
  261. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  262. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  263. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  264. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  265. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  266. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  267. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  268. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3e.s
  269. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3e.s 2015-11-13 09:27:41.000000000 +0100
  270. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3e.s 2017-03-09 05:45:40.724833342 +0100
  271. @@ -12,7 +12,7 @@
  272. sh3e:
  273. ! Instructions introduced into sh3e
  274. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
  275. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
  276. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  277. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  278. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  279. @@ -132,8 +132,8 @@
  280. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  281. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  282. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  283. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  284. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  285. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  286. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  287. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  288. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  289. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  290. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3-nommu.s
  291. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2015-11-13 09:27:41.000000000 +0100
  292. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3-nommu.s 2017-03-09 05:45:40.724833342 +0100
  293. @@ -26,7 +26,7 @@
  294. stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
  295. stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
  296. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
  297. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
  298. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  299. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  300. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  301. @@ -133,8 +133,8 @@
  302. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  303. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  304. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  305. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  306. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  307. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  308. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  309. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  310. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  311. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  312. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3.s
  313. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3.s 2015-11-13 09:27:41.000000000 +0100
  314. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3.s 2017-03-09 05:45:40.724833342 +0100
  315. @@ -13,7 +13,7 @@
  316. ! Instructions introduced into sh3
  317. ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
  318. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
  319. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
  320. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  321. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  322. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  323. @@ -128,8 +128,8 @@
  324. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  325. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  326. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  327. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  328. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  329. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  330. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  331. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  332. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  333. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  334. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4al-dsp.s
  335. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2015-11-13 09:27:41.000000000 +0100
  336. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2017-03-09 05:45:40.724833342 +0100
  337. @@ -48,7 +48,7 @@
  338. dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
  339. dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
  340. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  341. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  342. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  343. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  344. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  345. @@ -202,8 +202,8 @@
  346. setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
  347. repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
  348. repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
  349. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  350. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  351. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  352. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  353. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  354. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  355. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  356. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
  357. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  358. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2017-03-09 05:45:40.724833342 +0100
  359. @@ -19,7 +19,7 @@
  360. prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
  361. synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
  362. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
  363. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
  364. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  365. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  366. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  367. @@ -143,8 +143,8 @@
  368. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  369. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  370. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  371. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  372. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  373. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  374. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  375. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  376. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  377. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  378. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4a.s
  379. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a.s 2015-11-13 09:27:41.000000000 +0100
  380. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4a.s 2017-03-09 05:45:40.724833342 +0100
  381. @@ -13,7 +13,7 @@
  382. ! Instructions introduced into sh4a
  383. fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
  384. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  385. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  386. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  387. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  388. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  389. @@ -147,8 +147,8 @@
  390. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  391. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  392. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  393. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  394. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  395. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  396. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  397. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  398. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  399. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  400. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nofpu.s
  401. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  402. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2017-03-09 05:45:40.724833342 +0100
  403. @@ -12,7 +12,7 @@
  404. sh4_nofpu:
  405. ! Instructions introduced into sh4-nofpu
  406. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
  407. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
  408. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  409. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  410. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  411. @@ -136,8 +136,8 @@
  412. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  413. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  414. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  415. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  416. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  417. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  418. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  419. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  420. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  421. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  422. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
  423. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  424. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2017-03-09 05:45:40.724833342 +0100
  425. @@ -24,7 +24,7 @@
  426. stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
  427. stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
  428. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
  429. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
  430. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  431. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  432. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  433. @@ -139,8 +139,8 @@
  434. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  435. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  436. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  437. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  438. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  439. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  440. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  441. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  442. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  443. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  444. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4.s
  445. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4.s 2015-11-13 09:27:41.000000000 +0100
  446. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4.s 2017-03-09 05:45:40.724833342 +0100
  447. @@ -17,7 +17,7 @@
  448. fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
  449. ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
  450. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
  451. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
  452. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  453. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  454. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  455. @@ -145,8 +145,8 @@
  456. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  457. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  458. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  459. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  460. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  461. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  462. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  463. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  464. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  465. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  466. diff -Nur binutils-2.28.orig/include/elf/sh.h binutils-2.28/include/elf/sh.h
  467. --- binutils-2.28.orig/include/elf/sh.h 2017-03-02 09:23:54.000000000 +0100
  468. +++ binutils-2.28/include/elf/sh.h 2017-03-09 05:45:40.724833342 +0100
  469. @@ -39,6 +39,7 @@
  470. #define EF_SH2E 11
  471. #define EF_SH4A 12
  472. #define EF_SH2A 13
  473. +#define EF_SHJ2 14
  474. #define EF_SH4_NOFPU 16
  475. #define EF_SH4A_NOFPU 17
  476. @@ -50,6 +51,7 @@
  477. #define EF_SH2A_SH3_NOFPU 22
  478. #define EF_SH2A_SH4 23
  479. #define EF_SH2A_SH3E 24
  480. +#define EF_SH2A_SH3_SHJ2 25
  481. /* This one can only mix in objects from other EF_SH5 objects. */
  482. #define EF_SH5 10
  483. @@ -72,7 +74,8 @@
  484. /* EF_SH2E */ bfd_mach_sh2e , \
  485. /* EF_SH4A */ bfd_mach_sh4a , \
  486. /* EF_SH2A */ bfd_mach_sh2a , \
  487. -/* 14, 15 */ 0, 0, \
  488. +/* EF_SHJ2 */ bfd_mach_shj2 , \
  489. +/* 15 */ 0, \
  490. /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
  491. /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
  492. /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
  493. @@ -81,7 +84,8 @@
  494. /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
  495. /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
  496. /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
  497. -/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
  498. +/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
  499. +/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
  500. /* Convert arch_sh* into EF_SH*. */
  501. int sh_find_elf_flags (unsigned int arch_set);
  502. diff -Nur binutils-2.28.orig/opcodes/sh-dis.c binutils-2.28/opcodes/sh-dis.c
  503. --- binutils-2.28.orig/opcodes/sh-dis.c 2017-03-02 09:23:54.000000000 +0100
  504. +++ binutils-2.28/opcodes/sh-dis.c 2017-03-09 05:45:46.017038228 +0100
  505. @@ -870,6 +870,9 @@
  506. case XMTRX_M4:
  507. fprintf_fn (stream, "xmtrx");
  508. break;
  509. + case A_IND_0:
  510. + fprintf_fn (stream, "@r0");
  511. + break;
  512. default:
  513. abort ();
  514. }
  515. diff -Nur binutils-2.28.orig/opcodes/sh-opc.h binutils-2.28/opcodes/sh-opc.h
  516. --- binutils-2.28.orig/opcodes/sh-opc.h 2017-03-02 09:23:54.000000000 +0100
  517. +++ binutils-2.28/opcodes/sh-opc.h 2017-03-09 05:45:46.017038228 +0100
  518. @@ -191,7 +191,8 @@
  519. FPUL_N,
  520. FPUL_M,
  521. FPSCR_N,
  522. - FPSCR_M
  523. + FPSCR_M,
  524. + A_IND_0
  525. }
  526. sh_arg_type;
  527. @@ -218,9 +219,11 @@
  528. #define arch_sh4_base (1 << 5)
  529. #define arch_sh4a_base (1 << 6)
  530. #define arch_sh2a_base (1 << 7)
  531. -#define arch_sh_base_mask MASK (0, 7)
  532. +#define arch_shj2_base (1 << 8)
  533. +#define arch_sh2a_sh3_shj2_base (1 << 9)
  534. +#define arch_sh_base_mask MASK (0, 9)
  535. -/* Bits 8 ... 24 are currently free. */
  536. +/* Bits 10 ... 24 are currently free. */
  537. /* This is an annotation on instruction types, but we
  538. abuse the arch field in instructions to denote it. */
  539. @@ -258,6 +261,8 @@
  540. #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
  541. #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
  542. #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
  543. +#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
  544. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
  545. #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
  546. #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
  547. @@ -322,7 +327,8 @@
  548. #define arch_sh2_up (arch_sh2 \
  549. | arch_sh2e_up \
  550. | arch_sh2a_nofpu_or_sh3_nommu_up \
  551. - | arch_sh_dsp_up)
  552. + | arch_sh_dsp_up \
  553. + | arch_shj2_up)
  554. #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
  555. | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
  556. | arch_sh2a_or_sh3e_up \
  557. @@ -348,6 +354,12 @@
  558. #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
  559. | arch_sh4a_up \
  560. | arch_sh4al_dsp_up)
  561. +#define arch_shj2_up ( arch_shj2)
  562. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
  563. + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
  564. + | arch_sh2a_or_sh3e_up \
  565. + | arch_sh3_nommu_up \
  566. + | arch_shj2_up)
  567. /* Right branches. */
  568. #define arch_sh2e_up (arch_sh2e \
  569. @@ -716,9 +728,9 @@
  570. /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
  571. -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
  572. +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
  573. -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
  574. +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
  575. /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
  576. @@ -1196,7 +1208,7 @@
  577. {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
  578. /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
  579. {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
  580. -
  581. + /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
  582. { 0, {0}, {0}, 0 }
  583. };