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930-avr32_support.patch 740 KB

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  1. --- a/gcc/builtins.c
  2. +++ b/gcc/builtins.c
  3. @@ -11108,7 +11108,7 @@ validate_gimple_arglist (const_gimple ca
  4. do
  5. {
  6. - code = va_arg (ap, enum tree_code);
  7. + code = va_arg (ap, int);
  8. switch (code)
  9. {
  10. case 0:
  11. --- a/gcc/calls.c
  12. +++ b/gcc/calls.c
  13. @@ -3447,7 +3447,7 @@ emit_library_call_value_1 (int retval, r
  14. for (; count < nargs; count++)
  15. {
  16. rtx val = va_arg (p, rtx);
  17. - enum machine_mode mode = va_arg (p, enum machine_mode);
  18. + enum machine_mode mode = va_arg (p, int);
  19. /* We cannot convert the arg value to the mode the library wants here;
  20. must do it earlier where we know the signedness of the arg. */
  21. --- /dev/null
  22. +++ b/gcc/config/avr32/avr32.c
  23. @@ -0,0 +1,8060 @@
  24. +/*
  25. + Target hooks and helper functions for AVR32.
  26. + Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation.
  27. +
  28. + This file is part of GCC.
  29. +
  30. + This program is free software; you can redistribute it and/or modify
  31. + it under the terms of the GNU General Public License as published by
  32. + the Free Software Foundation; either version 2 of the License, or
  33. + (at your option) any later version.
  34. +
  35. + This program is distributed in the hope that it will be useful,
  36. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  37. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  38. + GNU General Public License for more details.
  39. +
  40. + You should have received a copy of the GNU General Public License
  41. + along with this program; if not, write to the Free Software
  42. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  43. +
  44. +#include "config.h"
  45. +#include "system.h"
  46. +#include "coretypes.h"
  47. +#include "tm.h"
  48. +#include "rtl.h"
  49. +#include "tree.h"
  50. +#include "obstack.h"
  51. +#include "regs.h"
  52. +#include "hard-reg-set.h"
  53. +#include "real.h"
  54. +#include "insn-config.h"
  55. +#include "conditions.h"
  56. +#include "output.h"
  57. +#include "insn-attr.h"
  58. +#include "flags.h"
  59. +#include "reload.h"
  60. +#include "function.h"
  61. +#include "expr.h"
  62. +#include "optabs.h"
  63. +#include "toplev.h"
  64. +#include "recog.h"
  65. +#include "ggc.h"
  66. +#include "except.h"
  67. +#include "c-pragma.h"
  68. +#include "integrate.h"
  69. +#include "tm_p.h"
  70. +#include "langhooks.h"
  71. +#include "hooks.h"
  72. +#include "df.h"
  73. +
  74. +#include "target.h"
  75. +#include "target-def.h"
  76. +
  77. +#include <ctype.h>
  78. +
  79. +
  80. +
  81. +/* Global variables. */
  82. +typedef struct minipool_node Mnode;
  83. +typedef struct minipool_fixup Mfix;
  84. +
  85. +/* Obstack for minipool constant handling. */
  86. +static struct obstack minipool_obstack;
  87. +static char *minipool_startobj;
  88. +static rtx minipool_vector_label;
  89. +
  90. +/* True if we are currently building a constant table. */
  91. +int making_const_table;
  92. +
  93. +tree fndecl_attribute_args = NULL_TREE;
  94. +
  95. +
  96. +/* Function prototypes. */
  97. +static unsigned long avr32_isr_value (tree);
  98. +static unsigned long avr32_compute_func_type (void);
  99. +static tree avr32_handle_isr_attribute (tree *, tree, tree, int, bool *);
  100. +static tree avr32_handle_acall_attribute (tree *, tree, tree, int, bool *);
  101. +static tree avr32_handle_fndecl_attribute (tree * node, tree name, tree args,
  102. + int flags, bool * no_add_attrs);
  103. +static void avr32_reorg (void);
  104. +bool avr32_return_in_msb (tree type);
  105. +bool avr32_vector_mode_supported (enum machine_mode mode);
  106. +static void avr32_init_libfuncs (void);
  107. +static void avr32_file_end (void);
  108. +static void flashvault_decl_list_add (unsigned int vector_num, const char *name);
  109. +
  110. +
  111. +
  112. +static void
  113. +avr32_add_gc_roots (void)
  114. +{
  115. + gcc_obstack_init (&minipool_obstack);
  116. + minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
  117. +}
  118. +
  119. +
  120. +/* List of all known AVR32 parts */
  121. +static const struct part_type_s avr32_part_types[] = {
  122. + /* name, part_type, architecture type, macro */
  123. + {"none", PART_TYPE_AVR32_NONE, ARCH_TYPE_AVR32_AP, "__AVR32__"},
  124. + {"ap7000", PART_TYPE_AVR32_AP7000, ARCH_TYPE_AVR32_AP, "__AVR32_AP7000__"},
  125. + {"ap7001", PART_TYPE_AVR32_AP7001, ARCH_TYPE_AVR32_AP, "__AVR32_AP7001__"},
  126. + {"ap7002", PART_TYPE_AVR32_AP7002, ARCH_TYPE_AVR32_AP, "__AVR32_AP7002__"},
  127. + {"ap7200", PART_TYPE_AVR32_AP7200, ARCH_TYPE_AVR32_AP, "__AVR32_AP7200__"},
  128. + {"uc3a0128", PART_TYPE_AVR32_UC3A0128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0128__"},
  129. + {"uc3a0256", PART_TYPE_AVR32_UC3A0256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0256__"},
  130. + {"uc3a0512", PART_TYPE_AVR32_UC3A0512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0512__"},
  131. + {"uc3a0512es", PART_TYPE_AVR32_UC3A0512ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3A0512ES__"},
  132. + {"uc3a1128", PART_TYPE_AVR32_UC3A1128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1128__"},
  133. + {"uc3a1256", PART_TYPE_AVR32_UC3A1256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1256__"},
  134. + {"uc3a1512", PART_TYPE_AVR32_UC3A1512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1512__"},
  135. + {"uc3a1512es", PART_TYPE_AVR32_UC3A1512ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3A1512ES__"},
  136. + {"uc3a3revd", PART_TYPE_AVR32_UC3A3REVD, ARCH_TYPE_AVR32_UCR2NOMUL, "__AVR32_UC3A3256S__"},
  137. + {"uc3a364", PART_TYPE_AVR32_UC3A364, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A364__"},
  138. + {"uc3a364s", PART_TYPE_AVR32_UC3A364S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A364S__"},
  139. + {"uc3a3128", PART_TYPE_AVR32_UC3A3128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3128__"},
  140. + {"uc3a3128s", PART_TYPE_AVR32_UC3A3128S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3128S__"},
  141. + {"uc3a3256", PART_TYPE_AVR32_UC3A3256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3256__"},
  142. + {"uc3a3256s", PART_TYPE_AVR32_UC3A3256S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3256S__"},
  143. + {"uc3a464", PART_TYPE_AVR32_UC3A464, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A464__"},
  144. + {"uc3a464s", PART_TYPE_AVR32_UC3A464S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A464S__"},
  145. + {"uc3a4128", PART_TYPE_AVR32_UC3A4128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4128__"},
  146. + {"uc3a4128s", PART_TYPE_AVR32_UC3A4128S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4128S__"},
  147. + {"uc3a4256", PART_TYPE_AVR32_UC3A4256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4256__"},
  148. + {"uc3a4256s", PART_TYPE_AVR32_UC3A4256S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4256S__"},
  149. + {"uc3b064", PART_TYPE_AVR32_UC3B064, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B064__"},
  150. + {"uc3b0128", PART_TYPE_AVR32_UC3B0128, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0128__"},
  151. + {"uc3b0256", PART_TYPE_AVR32_UC3B0256, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0256__"},
  152. + {"uc3b0256es", PART_TYPE_AVR32_UC3B0256ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0256ES__"},
  153. + {"uc3b0512", PART_TYPE_AVR32_UC3B0512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B0512__"},
  154. + {"uc3b0512revc", PART_TYPE_AVR32_UC3B0512REVC, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B0512REVC__"},
  155. + {"uc3b164", PART_TYPE_AVR32_UC3B164, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B164__"},
  156. + {"uc3b1128", PART_TYPE_AVR32_UC3B1128, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1128__"},
  157. + {"uc3b1256", PART_TYPE_AVR32_UC3B1256, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1256__"},
  158. + {"uc3b1256es", PART_TYPE_AVR32_UC3B1256ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1256ES__"},
  159. + {"uc3b1512", PART_TYPE_AVR32_UC3B1512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B1512__"},
  160. + {"uc3b1512revc", PART_TYPE_AVR32_UC3B1512REVC, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B1512REVC__"},
  161. + {"uc64d3", PART_TYPE_AVR32_UC64D3, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64D3__"},
  162. + {"uc128d3", PART_TYPE_AVR32_UC128D3, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128D3__"},
  163. + {"uc64d4", PART_TYPE_AVR32_UC64D4, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64D4__"},
  164. + {"uc128d4", PART_TYPE_AVR32_UC128D4, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128D4__"},
  165. + {"uc3c0512crevc", PART_TYPE_AVR32_UC3C0512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C0512CREVC__"},
  166. + {"uc3c1512crevc", PART_TYPE_AVR32_UC3C1512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C1512CREVC__"},
  167. + {"uc3c2512crevc", PART_TYPE_AVR32_UC3C2512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C2512CREVC__"},
  168. + {"uc3l0256", PART_TYPE_AVR32_UC3L0256, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L0256__"},
  169. + {"uc3l0128", PART_TYPE_AVR32_UC3L0128, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L0128__"},
  170. + {"uc3l064", PART_TYPE_AVR32_UC3L064, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L064__"},
  171. + {"uc3l032", PART_TYPE_AVR32_UC3L032, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L032__"},
  172. + {"uc3l016", PART_TYPE_AVR32_UC3L016, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L016__"},
  173. + {"uc3l064revb", PART_TYPE_AVR32_UC3L064REVB, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L064REVB__"},
  174. + {"uc64l3u", PART_TYPE_AVR32_UC64L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64L3U__"},
  175. + {"uc128l3u", PART_TYPE_AVR32_UC128L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128L3U__"},
  176. + {"uc256l3u", PART_TYPE_AVR32_UC256L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC256L3U__"},
  177. + {"uc64l4u", PART_TYPE_AVR32_UC64L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64L4U__"},
  178. + {"uc128l4u", PART_TYPE_AVR32_UC128L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128L4U__"},
  179. + {"uc256l4u", PART_TYPE_AVR32_UC256L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC256L4U__"},
  180. + {"uc3c064c", PART_TYPE_AVR32_UC3C064C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C064C__"},
  181. + {"uc3c0128c", PART_TYPE_AVR32_UC3C0128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0128C__"},
  182. + {"uc3c0256c", PART_TYPE_AVR32_UC3C0256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0256C__"},
  183. + {"uc3c0512c", PART_TYPE_AVR32_UC3C0512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0512C__"},
  184. + {"uc3c164c", PART_TYPE_AVR32_UC3C164C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C164C__"},
  185. + {"uc3c1128c", PART_TYPE_AVR32_UC3C1128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1128C__"},
  186. + {"uc3c1256c", PART_TYPE_AVR32_UC3C1256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1256C__"},
  187. + {"uc3c1512c", PART_TYPE_AVR32_UC3C1512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1512C__"},
  188. + {"uc3c264c", PART_TYPE_AVR32_UC3C264C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C264C__"},
  189. + {"uc3c2128c", PART_TYPE_AVR32_UC3C2128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2128C__"},
  190. + {"uc3c2256c", PART_TYPE_AVR32_UC3C2256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2256C__"},
  191. + {"uc3c2512c", PART_TYPE_AVR32_UC3C2512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2512C__"},
  192. + {"mxt768e", PART_TYPE_AVR32_MXT768E, ARCH_TYPE_AVR32_UCR3, "__AVR32_MXT768E__"},
  193. + {NULL, 0, 0, NULL}
  194. +};
  195. +
  196. +/* List of all known AVR32 architectures */
  197. +static const struct arch_type_s avr32_arch_types[] = {
  198. + /* name, architecture type, microarchitecture type, feature flags, macro */
  199. + {"ap", ARCH_TYPE_AVR32_AP, UARCH_TYPE_AVR32B,
  200. + (FLAG_AVR32_HAS_DSP
  201. + | FLAG_AVR32_HAS_SIMD
  202. + | FLAG_AVR32_HAS_UNALIGNED_WORD
  203. + | FLAG_AVR32_HAS_BRANCH_PRED | FLAG_AVR32_HAS_RETURN_STACK
  204. + | FLAG_AVR32_HAS_CACHES),
  205. + "__AVR32_AP__"},
  206. + {"ucr1", ARCH_TYPE_AVR32_UCR1, UARCH_TYPE_AVR32A,
  207. + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW),
  208. + "__AVR32_UC__=1"},
  209. + {"ucr2", ARCH_TYPE_AVR32_UCR2, UARCH_TYPE_AVR32A,
  210. + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW
  211. + | FLAG_AVR32_HAS_V2_INSNS),
  212. + "__AVR32_UC__=2"},
  213. + {"ucr2nomul", ARCH_TYPE_AVR32_UCR2NOMUL, UARCH_TYPE_AVR32A,
  214. + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW
  215. + | FLAG_AVR32_HAS_V2_INSNS | FLAG_AVR32_HAS_NO_MUL_INSNS),
  216. + "__AVR32_UC__=2"},
  217. + {"ucr3", ARCH_TYPE_AVR32_UCR3, UARCH_TYPE_AVR32A,
  218. + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW
  219. + | FLAG_AVR32_HAS_V2_INSNS),
  220. + "__AVR32_UC__=3"},
  221. + {"ucr3fp", ARCH_TYPE_AVR32_UCR3FP, UARCH_TYPE_AVR32A,
  222. + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW | FLAG_AVR32_HAS_FPU
  223. + | FLAG_AVR32_HAS_V2_INSNS),
  224. + "__AVR32_UC__=3"},
  225. + {NULL, 0, 0, 0, NULL}
  226. +};
  227. +
  228. +/* Default arch name */
  229. +const char *avr32_arch_name = "none";
  230. +const char *avr32_part_name = "none";
  231. +
  232. +const struct part_type_s *avr32_part;
  233. +const struct arch_type_s *avr32_arch;
  234. +
  235. +
  236. +/* FIXME: needs to use GC. */
  237. +struct flashvault_decl_list
  238. +{
  239. + struct flashvault_decl_list *next;
  240. + unsigned int vector_num;
  241. + const char *name;
  242. +};
  243. +
  244. +static struct flashvault_decl_list *flashvault_decl_list_head = NULL;
  245. +
  246. +
  247. +/* Set default target_flags. */
  248. +#undef TARGET_DEFAULT_TARGET_FLAGS
  249. +#define TARGET_DEFAULT_TARGET_FLAGS \
  250. + (MASK_HAS_ASM_ADDR_PSEUDOS | MASK_MD_REORG_OPTIMIZATION | MASK_COND_EXEC_BEFORE_RELOAD)
  251. +
  252. +void
  253. +avr32_optimization_options (int level, int size)
  254. +{
  255. + if (AVR32_ALWAYS_PIC)
  256. + flag_pic = 1;
  257. +
  258. + /* Enable section anchors if optimization is enabled. */
  259. + if (level > 0 || size)
  260. + flag_section_anchors = 2;
  261. +}
  262. +
  263. +
  264. +/* Override command line options */
  265. +void
  266. +avr32_override_options (void)
  267. +{
  268. + const struct part_type_s *part;
  269. + const struct arch_type_s *arch;
  270. +
  271. + /*Add backward compability*/
  272. + if (strcmp ("uc", avr32_arch_name)== 0)
  273. + {
  274. + fprintf (stderr, "Warning: Deprecated arch `%s' specified. "
  275. + "Please use '-march=ucr1' instead. "
  276. + "Converting to arch 'ucr1'\n",
  277. + avr32_arch_name);
  278. + avr32_arch_name="ucr1";
  279. + }
  280. +
  281. + /* Check if arch type is set. */
  282. + for (arch = avr32_arch_types; arch->name; arch++)
  283. + {
  284. + if (strcmp (arch->name, avr32_arch_name) == 0)
  285. + break;
  286. + }
  287. + avr32_arch = arch;
  288. +
  289. + if (!arch->name && strcmp("none", avr32_arch_name) != 0)
  290. + {
  291. + fprintf (stderr, "Unknown arch `%s' specified\n"
  292. + "Known arch names:\n"
  293. + "\tuc (deprecated)\n",
  294. + avr32_arch_name);
  295. + for (arch = avr32_arch_types; arch->name; arch++)
  296. + fprintf (stderr, "\t%s\n", arch->name);
  297. + avr32_arch = &avr32_arch_types[ARCH_TYPE_AVR32_AP];
  298. + }
  299. +
  300. + /* Check if part type is set. */
  301. + for (part = avr32_part_types; part->name; part++)
  302. + if (strcmp (part->name, avr32_part_name) == 0)
  303. + break;
  304. +
  305. + avr32_part = part;
  306. + if (!part->name)
  307. + {
  308. + fprintf (stderr, "Unknown part `%s' specified\nKnown part names:\n",
  309. + avr32_part_name);
  310. + for (part = avr32_part_types; part->name; part++)
  311. + {
  312. + if (strcmp("none", part->name) != 0)
  313. + fprintf (stderr, "\t%s\n", part->name);
  314. + }
  315. + /* Set default to NONE*/
  316. + avr32_part = &avr32_part_types[PART_TYPE_AVR32_NONE];
  317. + }
  318. +
  319. + /* NB! option -march= overrides option -mpart
  320. + * if both are used at the same time */
  321. + if (!arch->name)
  322. + avr32_arch = &avr32_arch_types[avr32_part->arch_type];
  323. +
  324. + /* If optimization level is two or greater, then align start of loops to a
  325. + word boundary since this will allow folding the first insn of the loop.
  326. + Do this only for targets supporting branch prediction. */
  327. + if (optimize >= 2 && TARGET_BRANCH_PRED)
  328. + align_loops = 2;
  329. +
  330. +
  331. + /* Enable fast-float library if unsafe math optimizations
  332. + are used. */
  333. + if (flag_unsafe_math_optimizations)
  334. + target_flags |= MASK_FAST_FLOAT;
  335. +
  336. + /* Check if we should set avr32_imm_in_const_pool
  337. + based on if caches are present or not. */
  338. + if ( avr32_imm_in_const_pool == -1 )
  339. + {
  340. + if ( TARGET_CACHES )
  341. + avr32_imm_in_const_pool = 1;
  342. + else
  343. + avr32_imm_in_const_pool = 0;
  344. + }
  345. +
  346. + if (TARGET_NO_PIC)
  347. + flag_pic = 0;
  348. + avr32_add_gc_roots ();
  349. +}
  350. +
  351. +
  352. +/*
  353. +If defined, a function that outputs the assembler code for entry to a
  354. +function. The prologue is responsible for setting up the stack frame,
  355. +initializing the frame pointer register, saving registers that must be
  356. +saved, and allocating size additional bytes of storage for the
  357. +local variables. size is an integer. file is a stdio
  358. +stream to which the assembler code should be output.
  359. +
  360. +The label for the beginning of the function need not be output by this
  361. +macro. That has already been done when the macro is run.
  362. +
  363. +To determine which registers to save, the macro can refer to the array
  364. +regs_ever_live: element r is nonzero if hard register
  365. +r is used anywhere within the function. This implies the function
  366. +prologue should save register r, provided it is not one of the
  367. +call-used registers. (TARGET_ASM_FUNCTION_EPILOGUE must likewise use
  368. +regs_ever_live.)
  369. +
  370. +On machines that have ``register windows'', the function entry code does
  371. +not save on the stack the registers that are in the windows, even if
  372. +they are supposed to be preserved by function calls; instead it takes
  373. +appropriate steps to ``push'' the register stack, if any non-call-used
  374. +registers are used in the function.
  375. +
  376. +On machines where functions may or may not have frame-pointers, the
  377. +function entry code must vary accordingly; it must set up the frame
  378. +pointer if one is wanted, and not otherwise. To determine whether a
  379. +frame pointer is in wanted, the macro can refer to the variable
  380. +frame_pointer_needed. The variable's value will be 1 at run
  381. +time in a function that needs a frame pointer. (see Elimination).
  382. +
  383. +The function entry code is responsible for allocating any stack space
  384. +required for the function. This stack space consists of the regions
  385. +listed below. In most cases, these regions are allocated in the
  386. +order listed, with the last listed region closest to the top of the
  387. +stack (the lowest address if STACK_GROWS_DOWNWARD is defined, and
  388. +the highest address if it is not defined). You can use a different order
  389. +for a machine if doing so is more convenient or required for
  390. +compatibility reasons. Except in cases where required by standard
  391. +or by a debugger, there is no reason why the stack layout used by GCC
  392. +need agree with that used by other compilers for a machine.
  393. +*/
  394. +
  395. +#undef TARGET_ASM_FUNCTION_PROLOGUE
  396. +#define TARGET_ASM_FUNCTION_PROLOGUE avr32_target_asm_function_prologue
  397. +
  398. +#undef TARGET_ASM_FILE_END
  399. +#define TARGET_ASM_FILE_END avr32_file_end
  400. +
  401. +#undef TARGET_DEFAULT_SHORT_ENUMS
  402. +#define TARGET_DEFAULT_SHORT_ENUMS hook_bool_void_false
  403. +
  404. +#undef TARGET_PROMOTE_FUNCTION_ARGS
  405. +#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
  406. +
  407. +#undef TARGET_PROMOTE_FUNCTION_RETURN
  408. +#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
  409. +
  410. +#undef TARGET_PROMOTE_PROTOTYPES
  411. +#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
  412. +
  413. +#undef TARGET_MUST_PASS_IN_STACK
  414. +#define TARGET_MUST_PASS_IN_STACK avr32_must_pass_in_stack
  415. +
  416. +#undef TARGET_PASS_BY_REFERENCE
  417. +#define TARGET_PASS_BY_REFERENCE avr32_pass_by_reference
  418. +
  419. +#undef TARGET_STRICT_ARGUMENT_NAMING
  420. +#define TARGET_STRICT_ARGUMENT_NAMING avr32_strict_argument_naming
  421. +
  422. +#undef TARGET_VECTOR_MODE_SUPPORTED_P
  423. +#define TARGET_VECTOR_MODE_SUPPORTED_P avr32_vector_mode_supported
  424. +
  425. +#undef TARGET_RETURN_IN_MEMORY
  426. +#define TARGET_RETURN_IN_MEMORY avr32_return_in_memory
  427. +
  428. +#undef TARGET_RETURN_IN_MSB
  429. +#define TARGET_RETURN_IN_MSB avr32_return_in_msb
  430. +
  431. +#undef TARGET_ENCODE_SECTION_INFO
  432. +#define TARGET_ENCODE_SECTION_INFO avr32_encode_section_info
  433. +
  434. +#undef TARGET_ARG_PARTIAL_BYTES
  435. +#define TARGET_ARG_PARTIAL_BYTES avr32_arg_partial_bytes
  436. +
  437. +#undef TARGET_STRIP_NAME_ENCODING
  438. +#define TARGET_STRIP_NAME_ENCODING avr32_strip_name_encoding
  439. +
  440. +#define streq(string1, string2) (strcmp (string1, string2) == 0)
  441. +
  442. +#undef TARGET_NARROW_VOLATILE_BITFIELD
  443. +#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
  444. +
  445. +#undef TARGET_ATTRIBUTE_TABLE
  446. +#define TARGET_ATTRIBUTE_TABLE avr32_attribute_table
  447. +
  448. +#undef TARGET_COMP_TYPE_ATTRIBUTES
  449. +#define TARGET_COMP_TYPE_ATTRIBUTES avr32_comp_type_attributes
  450. +
  451. +
  452. +#undef TARGET_RTX_COSTS
  453. +#define TARGET_RTX_COSTS avr32_rtx_costs
  454. +
  455. +#undef TARGET_CANNOT_FORCE_CONST_MEM
  456. +#define TARGET_CANNOT_FORCE_CONST_MEM avr32_cannot_force_const_mem
  457. +
  458. +#undef TARGET_ASM_INTEGER
  459. +#define TARGET_ASM_INTEGER avr32_assemble_integer
  460. +
  461. +#undef TARGET_FUNCTION_VALUE
  462. +#define TARGET_FUNCTION_VALUE avr32_function_value
  463. +
  464. +#undef TARGET_MIN_ANCHOR_OFFSET
  465. +#define TARGET_MIN_ANCHOR_OFFSET (0)
  466. +
  467. +#undef TARGET_MAX_ANCHOR_OFFSET
  468. +#define TARGET_MAX_ANCHOR_OFFSET ((1 << 15) - 1)
  469. +#undef TARGET_SECONDARY_RELOAD
  470. +#define TARGET_SECONDARY_RELOAD avr32_secondary_reload
  471. +
  472. +
  473. +/*
  474. + * Defining the option, -mlist-devices to list the devices supported by gcc.
  475. + * This option should be used while printing target-help to list all the
  476. + * supported devices.
  477. + */
  478. +#undef TARGET_HELP
  479. +#define TARGET_HELP avr32_target_help
  480. +
  481. +void avr32_target_help ()
  482. +{
  483. + if (avr32_list_supported_parts)
  484. + {
  485. + const struct part_type_s *list;
  486. + fprintf (stdout, "List of parts supported by avr32-gcc:\n");
  487. + for (list = avr32_part_types; list->name; list++)
  488. + {
  489. + if (strcmp("none", list->name) != 0)
  490. + fprintf (stdout, "%-20s%s\n", list->name, list->macro);
  491. + }
  492. + fprintf (stdout, "\n\n");
  493. + }
  494. +}
  495. +
  496. +enum reg_class
  497. +avr32_secondary_reload (bool in_p, rtx x, enum reg_class class,
  498. + enum machine_mode mode, secondary_reload_info *sri)
  499. +{
  500. +
  501. + if ( avr32_rmw_memory_operand (x, mode) )
  502. + {
  503. + if (!in_p)
  504. + sri->icode = CODE_FOR_reload_out_rmw_memory_operand;
  505. + else
  506. + sri->icode = CODE_FOR_reload_in_rmw_memory_operand;
  507. + }
  508. + return NO_REGS;
  509. +
  510. +}
  511. +/*
  512. + * Switches to the appropriate section for output of constant pool
  513. + * entry x in mode. You can assume that x is some kind of constant in
  514. + * RTL. The argument mode is redundant except in the case of a
  515. + * const_int rtx. Select the section by calling readonly_data_ section
  516. + * or one of the alternatives for other sections. align is the
  517. + * constant alignment in bits.
  518. + *
  519. + * The default version of this function takes care of putting symbolic
  520. + * constants in flag_ pic mode in data_section and everything else in
  521. + * readonly_data_section.
  522. + */
  523. +//#undef TARGET_ASM_SELECT_RTX_SECTION
  524. +//#define TARGET_ASM_SELECT_RTX_SECTION avr32_select_rtx_section
  525. +
  526. +
  527. +/*
  528. + * If non-null, this hook performs a target-specific pass over the
  529. + * instruction stream. The compiler will run it at all optimization
  530. + * levels, just before the point at which it normally does
  531. + * delayed-branch scheduling.
  532. + *
  533. + * The exact purpose of the hook varies from target to target. Some
  534. + * use it to do transformations that are necessary for correctness,
  535. + * such as laying out in-function constant pools or avoiding hardware
  536. + * hazards. Others use it as an opportunity to do some
  537. + * machine-dependent optimizations.
  538. + *
  539. + * You need not implement the hook if it has nothing to do. The
  540. + * default definition is null.
  541. + */
  542. +#undef TARGET_MACHINE_DEPENDENT_REORG
  543. +#define TARGET_MACHINE_DEPENDENT_REORG avr32_reorg
  544. +
  545. +/* Target hook for assembling integer objects.
  546. + Need to handle integer vectors */
  547. +static bool
  548. +avr32_assemble_integer (rtx x, unsigned int size, int aligned_p)
  549. +{
  550. + if (avr32_vector_mode_supported (GET_MODE (x)))
  551. + {
  552. + int i, units;
  553. +
  554. + if (GET_CODE (x) != CONST_VECTOR)
  555. + abort ();
  556. +
  557. + units = CONST_VECTOR_NUNITS (x);
  558. +
  559. + switch (GET_MODE (x))
  560. + {
  561. + case V2HImode:
  562. + size = 2;
  563. + break;
  564. + case V4QImode:
  565. + size = 1;
  566. + break;
  567. + default:
  568. + abort ();
  569. + }
  570. +
  571. + for (i = 0; i < units; i++)
  572. + {
  573. + rtx elt;
  574. +
  575. + elt = CONST_VECTOR_ELT (x, i);
  576. + assemble_integer (elt, size, i == 0 ? 32 : size * BITS_PER_UNIT, 1);
  577. + }
  578. +
  579. + return true;
  580. + }
  581. +
  582. + return default_assemble_integer (x, size, aligned_p);
  583. +}
  584. +
  585. +
  586. +/*
  587. + * This target hook describes the relative costs of RTL expressions.
  588. + *
  589. + * The cost may depend on the precise form of the expression, which is
  590. + * available for examination in x, and the rtx code of the expression
  591. + * in which it is contained, found in outer_code. code is the
  592. + * expression code--redundant, since it can be obtained with GET_CODE
  593. + * (x).
  594. + *
  595. + * In implementing this hook, you can use the construct COSTS_N_INSNS
  596. + * (n) to specify a cost equal to n fast instructions.
  597. + *
  598. + * On entry to the hook, *total contains a default estimate for the
  599. + * cost of the expression. The hook should modify this value as
  600. + * necessary. Traditionally, the default costs are COSTS_N_INSNS (5)
  601. + * for multiplications, COSTS_N_INSNS (7) for division and modulus
  602. + * operations, and COSTS_N_INSNS (1) for all other operations.
  603. + *
  604. + * When optimizing for code size, i.e. when optimize_size is non-zero,
  605. + * this target hook should be used to estimate the relative size cost
  606. + * of an expression, again relative to COSTS_N_INSNS.
  607. + *
  608. + * The hook returns true when all subexpressions of x have been
  609. + * processed, and false when rtx_cost should recurse.
  610. + */
  611. +
  612. +/* Worker routine for avr32_rtx_costs. */
  613. +static inline int
  614. +avr32_rtx_costs_1 (rtx x, enum rtx_code code ATTRIBUTE_UNUSED,
  615. + enum rtx_code outer ATTRIBUTE_UNUSED)
  616. +{
  617. + enum machine_mode mode = GET_MODE (x);
  618. +
  619. + switch (GET_CODE (x))
  620. + {
  621. + case MEM:
  622. + /* Using pre decrement / post increment memory operations on the
  623. + avr32_uc architecture means that two writebacks must be performed
  624. + and hence two cycles are needed. */
  625. + if (!optimize_size
  626. + && GET_MODE_SIZE (mode) <= 2 * UNITS_PER_WORD
  627. + && TARGET_ARCH_UC
  628. + && (GET_CODE (XEXP (x, 0)) == PRE_DEC
  629. + || GET_CODE (XEXP (x, 0)) == POST_INC))
  630. + return COSTS_N_INSNS (5);
  631. +
  632. + /* Memory costs quite a lot for the first word, but subsequent words
  633. + load at the equivalent of a single insn each. */
  634. + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
  635. + return COSTS_N_INSNS (3 + (GET_MODE_SIZE (mode) / UNITS_PER_WORD));
  636. +
  637. + return COSTS_N_INSNS (4);
  638. + case SYMBOL_REF:
  639. + case CONST:
  640. + /* These are valid for the pseudo insns: lda.w and call which operates
  641. + on direct addresses. We assume that the cost of a lda.w is the same
  642. + as the cost of a ld.w insn. */
  643. + return (outer == SET) ? COSTS_N_INSNS (4) : COSTS_N_INSNS (1);
  644. + case DIV:
  645. + case MOD:
  646. + case UDIV:
  647. + case UMOD:
  648. + return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16);
  649. +
  650. + case ROTATE:
  651. + case ROTATERT:
  652. + if (mode == TImode)
  653. + return COSTS_N_INSNS (100);
  654. +
  655. + if (mode == DImode)
  656. + return COSTS_N_INSNS (10);
  657. + return COSTS_N_INSNS (4);
  658. + case ASHIFT:
  659. + case LSHIFTRT:
  660. + case ASHIFTRT:
  661. + case NOT:
  662. + if (mode == TImode)
  663. + return COSTS_N_INSNS (10);
  664. +
  665. + if (mode == DImode)
  666. + return COSTS_N_INSNS (4);
  667. + return COSTS_N_INSNS (1);
  668. + case PLUS:
  669. + case MINUS:
  670. + case NEG:
  671. + case COMPARE:
  672. + case ABS:
  673. + if (GET_MODE_CLASS (mode) == MODE_FLOAT)
  674. + return COSTS_N_INSNS (100);
  675. +
  676. + if (mode == TImode)
  677. + return COSTS_N_INSNS (50);
  678. +
  679. + if (mode == DImode)
  680. + return COSTS_N_INSNS (2);
  681. + return COSTS_N_INSNS (1);
  682. +
  683. + case MULT:
  684. + {
  685. + if (GET_MODE_CLASS (mode) == MODE_FLOAT)
  686. + return COSTS_N_INSNS (300);
  687. +
  688. + if (mode == TImode)
  689. + return COSTS_N_INSNS (16);
  690. +
  691. + if (mode == DImode)
  692. + return COSTS_N_INSNS (4);
  693. +
  694. + if (mode == HImode)
  695. + return COSTS_N_INSNS (2);
  696. +
  697. + return COSTS_N_INSNS (3);
  698. + }
  699. + case IF_THEN_ELSE:
  700. + if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
  701. + return COSTS_N_INSNS (4);
  702. + return COSTS_N_INSNS (1);
  703. + case SIGN_EXTEND:
  704. + case ZERO_EXTEND:
  705. + /* Sign/Zero extensions of registers cost quite much since these
  706. + instrcutions only take one register operand which means that gcc
  707. + often must insert some move instrcutions */
  708. + if (mode == QImode || mode == HImode)
  709. + return (COSTS_N_INSNS (GET_CODE (XEXP (x, 0)) == MEM ? 0 : 1));
  710. + return COSTS_N_INSNS (4);
  711. + case UNSPEC:
  712. + /* divmod operations */
  713. + if (XINT (x, 1) == UNSPEC_UDIVMODSI4_INTERNAL
  714. + || XINT (x, 1) == UNSPEC_DIVMODSI4_INTERNAL)
  715. + {
  716. + return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16);
  717. + }
  718. + /* Fallthrough */
  719. + default:
  720. + return COSTS_N_INSNS (1);
  721. + }
  722. +}
  723. +
  724. +
  725. +static bool
  726. +avr32_rtx_costs (rtx x, int code, int outer_code, int *total)
  727. +{
  728. + *total = avr32_rtx_costs_1 (x, code, outer_code);
  729. + return true;
  730. +}
  731. +
  732. +
  733. +bool
  734. +avr32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
  735. +{
  736. + /* Do not want symbols in the constant pool when compiling pic or if using
  737. + address pseudo instructions. */
  738. + return ((flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS)
  739. + && avr32_find_symbol (x) != NULL_RTX);
  740. +}
  741. +
  742. +
  743. +/* Table of machine attributes. */
  744. +const struct attribute_spec avr32_attribute_table[] = {
  745. + /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
  746. + /* Interrupt Service Routines have special prologue and epilogue
  747. + requirements. */
  748. + {"isr", 0, 1, false, false, false, avr32_handle_isr_attribute},
  749. + {"interrupt", 0, 1, false, false, false, avr32_handle_isr_attribute},
  750. + {"acall", 0, 1, false, true, true, avr32_handle_acall_attribute},
  751. + {"naked", 0, 0, true, false, false, avr32_handle_fndecl_attribute},
  752. + {"rmw_addressable", 0, 0, true, false, false, NULL},
  753. + {"flashvault", 0, 1, true, false, false, avr32_handle_fndecl_attribute},
  754. + {"flashvault_impl", 0, 1, true, false, false, avr32_handle_fndecl_attribute},
  755. + {NULL, 0, 0, false, false, false, NULL}
  756. +};
  757. +
  758. +
  759. +typedef struct
  760. +{
  761. + const char *const arg;
  762. + const unsigned long return_value;
  763. +}
  764. +isr_attribute_arg;
  765. +
  766. +
  767. +static const isr_attribute_arg isr_attribute_args[] = {
  768. + {"FULL", AVR32_FT_ISR_FULL},
  769. + {"full", AVR32_FT_ISR_FULL},
  770. + {"HALF", AVR32_FT_ISR_HALF},
  771. + {"half", AVR32_FT_ISR_HALF},
  772. + {"NONE", AVR32_FT_ISR_NONE},
  773. + {"none", AVR32_FT_ISR_NONE},
  774. + {"UNDEF", AVR32_FT_ISR_NONE},
  775. + {"undef", AVR32_FT_ISR_NONE},
  776. + {"SWI", AVR32_FT_ISR_NONE},
  777. + {"swi", AVR32_FT_ISR_NONE},
  778. + {NULL, AVR32_FT_ISR_NONE}
  779. +};
  780. +
  781. +
  782. +/* Returns the (interrupt) function type of the current
  783. + function, or AVR32_FT_UNKNOWN if the type cannot be determined. */
  784. +static unsigned long
  785. +avr32_isr_value (tree argument)
  786. +{
  787. + const isr_attribute_arg *ptr;
  788. + const char *arg;
  789. +
  790. + /* No argument - default to ISR_NONE. */
  791. + if (argument == NULL_TREE)
  792. + return AVR32_FT_ISR_NONE;
  793. +
  794. + /* Get the value of the argument. */
  795. + if (TREE_VALUE (argument) == NULL_TREE
  796. + || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
  797. + return AVR32_FT_UNKNOWN;
  798. +
  799. + arg = TREE_STRING_POINTER (TREE_VALUE (argument));
  800. +
  801. + /* Check it against the list of known arguments. */
  802. + for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
  803. + if (streq (arg, ptr->arg))
  804. + return ptr->return_value;
  805. +
  806. + /* An unrecognized interrupt type. */
  807. + return AVR32_FT_UNKNOWN;
  808. +}
  809. +
  810. +
  811. +/*
  812. +These hooks specify assembly directives for creating certain kinds
  813. +of integer object. The TARGET_ASM_BYTE_OP directive creates a
  814. +byte-sized object, the TARGET_ASM_ALIGNED_HI_OP one creates an
  815. +aligned two-byte object, and so on. Any of the hooks may be
  816. +NULL, indicating that no suitable directive is available.
  817. +
  818. +The compiler will print these strings at the start of a new line,
  819. +followed immediately by the object's initial value. In most cases,
  820. +the string should contain a tab, a pseudo-op, and then another tab.
  821. +*/
  822. +#undef TARGET_ASM_BYTE_OP
  823. +#define TARGET_ASM_BYTE_OP "\t.byte\t"
  824. +#undef TARGET_ASM_ALIGNED_HI_OP
  825. +#define TARGET_ASM_ALIGNED_HI_OP "\t.align 1\n\t.short\t"
  826. +#undef TARGET_ASM_ALIGNED_SI_OP
  827. +#define TARGET_ASM_ALIGNED_SI_OP "\t.align 2\n\t.int\t"
  828. +#undef TARGET_ASM_ALIGNED_DI_OP
  829. +#define TARGET_ASM_ALIGNED_DI_OP NULL
  830. +#undef TARGET_ASM_ALIGNED_TI_OP
  831. +#define TARGET_ASM_ALIGNED_TI_OP NULL
  832. +#undef TARGET_ASM_UNALIGNED_HI_OP
  833. +#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
  834. +#undef TARGET_ASM_UNALIGNED_SI_OP
  835. +#define TARGET_ASM_UNALIGNED_SI_OP "\t.int\t"
  836. +#undef TARGET_ASM_UNALIGNED_DI_OP
  837. +#define TARGET_ASM_UNALIGNED_DI_OP NULL
  838. +#undef TARGET_ASM_UNALIGNED_TI_OP
  839. +#define TARGET_ASM_UNALIGNED_TI_OP NULL
  840. +
  841. +#undef TARGET_ASM_OUTPUT_MI_THUNK
  842. +#define TARGET_ASM_OUTPUT_MI_THUNK avr32_output_mi_thunk
  843. +
  844. +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
  845. +#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
  846. +
  847. +
  848. +static void
  849. +avr32_output_mi_thunk (FILE * file,
  850. + tree thunk ATTRIBUTE_UNUSED,
  851. + HOST_WIDE_INT delta,
  852. + HOST_WIDE_INT vcall_offset, tree function)
  853. + {
  854. + int mi_delta = delta;
  855. + int this_regno =
  856. + (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) ?
  857. + INTERNAL_REGNUM (11) : INTERNAL_REGNUM (12));
  858. +
  859. +
  860. + if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21")
  861. + || vcall_offset)
  862. + {
  863. + fputs ("\tpushm\tlr\n", file);
  864. + }
  865. +
  866. +
  867. + if (mi_delta != 0)
  868. + {
  869. + if (avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21"))
  870. + {
  871. + fprintf (file, "\tsub\t%s, %d\n", reg_names[this_regno], -mi_delta);
  872. + }
  873. + else
  874. + {
  875. + /* Immediate is larger than k21 we must make us a temp register by
  876. + pushing a register to the stack. */
  877. + fprintf (file, "\tmov\tlr, lo(%d)\n", mi_delta);
  878. + fprintf (file, "\torh\tlr, hi(%d)\n", mi_delta);
  879. + fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]);
  880. + }
  881. + }
  882. +
  883. +
  884. + if (vcall_offset != 0)
  885. + {
  886. + fprintf (file, "\tld.w\tlr, %s[0]\n", reg_names[this_regno]);
  887. + fprintf (file, "\tld.w\tlr, lr[%i]\n", (int) vcall_offset);
  888. + fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]);
  889. + }
  890. +
  891. +
  892. + if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21")
  893. + || vcall_offset)
  894. + {
  895. + fputs ("\tpopm\tlr\n", file);
  896. + }
  897. +
  898. + /* Jump to the function. We assume that we can use an rjmp since the
  899. + function to jump to is local and probably not too far away from
  900. + the thunk. If this assumption proves to be wrong we could implement
  901. + this jump by calculating the offset between the jump source and destination
  902. + and put this in the constant pool and then perform an add to pc.
  903. + This would also be legitimate PIC code. But for now we hope that an rjmp
  904. + will be sufficient...
  905. + */
  906. + fputs ("\trjmp\t", file);
  907. + assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
  908. + fputc ('\n', file);
  909. + }
  910. +
  911. +
  912. +/* Implements target hook vector_mode_supported. */
  913. +bool
  914. +avr32_vector_mode_supported (enum machine_mode mode)
  915. +{
  916. + if ((mode == V2HImode) || (mode == V4QImode))
  917. + return true;
  918. +
  919. + return false;
  920. +}
  921. +
  922. +
  923. +#undef TARGET_INIT_LIBFUNCS
  924. +#define TARGET_INIT_LIBFUNCS avr32_init_libfuncs
  925. +
  926. +#undef TARGET_INIT_BUILTINS
  927. +#define TARGET_INIT_BUILTINS avr32_init_builtins
  928. +
  929. +#undef TARGET_EXPAND_BUILTIN
  930. +#define TARGET_EXPAND_BUILTIN avr32_expand_builtin
  931. +
  932. +tree int_ftype_int, int_ftype_void, short_ftype_short, void_ftype_int_int,
  933. + void_ftype_ptr_int;
  934. +tree void_ftype_int, void_ftype_ulong, void_ftype_void, int_ftype_ptr_int;
  935. +tree short_ftype_short, int_ftype_int_short, int_ftype_short_short,
  936. + short_ftype_short_short;
  937. +tree int_ftype_int_int, longlong_ftype_int_short, longlong_ftype_short_short;
  938. +tree void_ftype_int_int_int_int_int, void_ftype_int_int_int;
  939. +tree longlong_ftype_int_int, void_ftype_int_int_longlong;
  940. +tree int_ftype_int_int_int, longlong_ftype_longlong_int_short;
  941. +tree longlong_ftype_longlong_short_short, int_ftype_int_short_short;
  942. +
  943. +#define def_builtin(NAME, TYPE, CODE) \
  944. + add_builtin_function ((NAME), (TYPE), (CODE), \
  945. + BUILT_IN_MD, NULL, NULL_TREE)
  946. +
  947. +#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
  948. + do \
  949. + { \
  950. + if ((MASK)) \
  951. + add_builtin_function ((NAME), (TYPE), (CODE), \
  952. + BUILT_IN_MD, NULL, NULL_TREE); \
  953. + } \
  954. + while (0)
  955. +
  956. +struct builtin_description
  957. +{
  958. + const unsigned int mask;
  959. + const enum insn_code icode;
  960. + const char *const name;
  961. + const int code;
  962. + const enum rtx_code comparison;
  963. + const unsigned int flag;
  964. + const tree *ftype;
  965. +};
  966. +
  967. +static const struct builtin_description bdesc_2arg[] = {
  968. +
  969. +#define DSP_BUILTIN(code, builtin, ftype) \
  970. + { 1, CODE_FOR_##code, "__builtin_" #code , \
  971. + AVR32_BUILTIN_##builtin, 0, 0, ftype }
  972. +
  973. + DSP_BUILTIN (mulsathh_h, MULSATHH_H, &short_ftype_short_short),
  974. + DSP_BUILTIN (mulsathh_w, MULSATHH_W, &int_ftype_short_short),
  975. + DSP_BUILTIN (mulsatrndhh_h, MULSATRNDHH_H, &short_ftype_short_short),
  976. + DSP_BUILTIN (mulsatrndwh_w, MULSATRNDWH_W, &int_ftype_int_short),
  977. + DSP_BUILTIN (mulsatwh_w, MULSATWH_W, &int_ftype_int_short),
  978. + DSP_BUILTIN (satadd_h, SATADD_H, &short_ftype_short_short),
  979. + DSP_BUILTIN (satsub_h, SATSUB_H, &short_ftype_short_short),
  980. + DSP_BUILTIN (satadd_w, SATADD_W, &int_ftype_int_int),
  981. + DSP_BUILTIN (satsub_w, SATSUB_W, &int_ftype_int_int),
  982. + DSP_BUILTIN (mulwh_d, MULWH_D, &longlong_ftype_int_short),
  983. + DSP_BUILTIN (mulnwh_d, MULNWH_D, &longlong_ftype_int_short)
  984. +};
  985. +
  986. +
  987. +void
  988. +avr32_init_builtins (void)
  989. +{
  990. + unsigned int i;
  991. + const struct builtin_description *d;
  992. + tree endlink = void_list_node;
  993. + tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
  994. + tree longlong_endlink =
  995. + tree_cons (NULL_TREE, long_long_integer_type_node, endlink);
  996. + tree short_endlink =
  997. + tree_cons (NULL_TREE, short_integer_type_node, endlink);
  998. + tree void_endlink = tree_cons (NULL_TREE, void_type_node, endlink);
  999. +
  1000. + /* int func (int) */
  1001. + int_ftype_int = build_function_type (integer_type_node, int_endlink);
  1002. +
  1003. + /* short func (short) */
  1004. + short_ftype_short
  1005. + = build_function_type (short_integer_type_node, short_endlink);
  1006. +
  1007. + /* short func (short, short) */
  1008. + short_ftype_short_short
  1009. + = build_function_type (short_integer_type_node,
  1010. + tree_cons (NULL_TREE, short_integer_type_node,
  1011. + short_endlink));
  1012. +
  1013. + /* long long func (long long, short, short) */
  1014. + longlong_ftype_longlong_short_short
  1015. + = build_function_type (long_long_integer_type_node,
  1016. + tree_cons (NULL_TREE, long_long_integer_type_node,
  1017. + tree_cons (NULL_TREE,
  1018. + short_integer_type_node,
  1019. + short_endlink)));
  1020. +
  1021. + /* long long func (short, short) */
  1022. + longlong_ftype_short_short
  1023. + = build_function_type (long_long_integer_type_node,
  1024. + tree_cons (NULL_TREE, short_integer_type_node,
  1025. + short_endlink));
  1026. +
  1027. + /* int func (int, int) */
  1028. + int_ftype_int_int
  1029. + = build_function_type (integer_type_node,
  1030. + tree_cons (NULL_TREE, integer_type_node,
  1031. + int_endlink));
  1032. +
  1033. + /* long long func (int, int) */
  1034. + longlong_ftype_int_int
  1035. + = build_function_type (long_long_integer_type_node,
  1036. + tree_cons (NULL_TREE, integer_type_node,
  1037. + int_endlink));
  1038. +
  1039. + /* long long int func (long long, int, short) */
  1040. + longlong_ftype_longlong_int_short
  1041. + = build_function_type (long_long_integer_type_node,
  1042. + tree_cons (NULL_TREE, long_long_integer_type_node,
  1043. + tree_cons (NULL_TREE, integer_type_node,
  1044. + short_endlink)));
  1045. +
  1046. + /* long long int func (int, short) */
  1047. + longlong_ftype_int_short
  1048. + = build_function_type (long_long_integer_type_node,
  1049. + tree_cons (NULL_TREE, integer_type_node,
  1050. + short_endlink));
  1051. +
  1052. + /* int func (int, short, short) */
  1053. + int_ftype_int_short_short
  1054. + = build_function_type (integer_type_node,
  1055. + tree_cons (NULL_TREE, integer_type_node,
  1056. + tree_cons (NULL_TREE,
  1057. + short_integer_type_node,
  1058. + short_endlink)));
  1059. +
  1060. + /* int func (short, short) */
  1061. + int_ftype_short_short
  1062. + = build_function_type (integer_type_node,
  1063. + tree_cons (NULL_TREE, short_integer_type_node,
  1064. + short_endlink));
  1065. +
  1066. + /* int func (int, short) */
  1067. + int_ftype_int_short
  1068. + = build_function_type (integer_type_node,
  1069. + tree_cons (NULL_TREE, integer_type_node,
  1070. + short_endlink));
  1071. +
  1072. + /* void func (int, int) */
  1073. + void_ftype_int_int
  1074. + = build_function_type (void_type_node,
  1075. + tree_cons (NULL_TREE, integer_type_node,
  1076. + int_endlink));
  1077. +
  1078. + /* void func (int, int, int) */
  1079. + void_ftype_int_int_int
  1080. + = build_function_type (void_type_node,
  1081. + tree_cons (NULL_TREE, integer_type_node,
  1082. + tree_cons (NULL_TREE, integer_type_node,
  1083. + int_endlink)));
  1084. +
  1085. + /* void func (int, int, long long) */
  1086. + void_ftype_int_int_longlong
  1087. + = build_function_type (void_type_node,
  1088. + tree_cons (NULL_TREE, integer_type_node,
  1089. + tree_cons (NULL_TREE, integer_type_node,
  1090. + longlong_endlink)));
  1091. +
  1092. + /* void func (int, int, int, int, int) */
  1093. + void_ftype_int_int_int_int_int
  1094. + = build_function_type (void_type_node,
  1095. + tree_cons (NULL_TREE, integer_type_node,
  1096. + tree_cons (NULL_TREE, integer_type_node,
  1097. + tree_cons (NULL_TREE,
  1098. + integer_type_node,
  1099. + tree_cons
  1100. + (NULL_TREE,
  1101. + integer_type_node,
  1102. + int_endlink)))));
  1103. +
  1104. + /* void func (void *, int) */
  1105. + void_ftype_ptr_int
  1106. + = build_function_type (void_type_node,
  1107. + tree_cons (NULL_TREE, ptr_type_node, int_endlink));
  1108. +
  1109. + /* void func (int) */
  1110. + void_ftype_int = build_function_type (void_type_node, int_endlink);
  1111. +
  1112. + /* void func (ulong) */
  1113. + void_ftype_ulong = build_function_type_list (void_type_node,
  1114. + long_unsigned_type_node, NULL_TREE);
  1115. +
  1116. + /* void func (void) */
  1117. + void_ftype_void = build_function_type (void_type_node, void_endlink);
  1118. +
  1119. + /* int func (void) */
  1120. + int_ftype_void = build_function_type (integer_type_node, void_endlink);
  1121. +
  1122. + /* int func (void *, int) */
  1123. + int_ftype_ptr_int
  1124. + = build_function_type (integer_type_node,
  1125. + tree_cons (NULL_TREE, ptr_type_node, int_endlink));
  1126. +
  1127. + /* int func (int, int, int) */
  1128. + int_ftype_int_int_int
  1129. + = build_function_type (integer_type_node,
  1130. + tree_cons (NULL_TREE, integer_type_node,
  1131. + tree_cons (NULL_TREE, integer_type_node,
  1132. + int_endlink)));
  1133. +
  1134. + /* Initialize avr32 builtins. */
  1135. + def_builtin ("__builtin_mfsr", int_ftype_int, AVR32_BUILTIN_MFSR);
  1136. + def_builtin ("__builtin_mtsr", void_ftype_int_int, AVR32_BUILTIN_MTSR);
  1137. + def_builtin ("__builtin_mfdr", int_ftype_int, AVR32_BUILTIN_MFDR);
  1138. + def_builtin ("__builtin_mtdr", void_ftype_int_int, AVR32_BUILTIN_MTDR);
  1139. + def_builtin ("__builtin_cache", void_ftype_ptr_int, AVR32_BUILTIN_CACHE);
  1140. + def_builtin ("__builtin_sync", void_ftype_int, AVR32_BUILTIN_SYNC);
  1141. + def_builtin ("__builtin_ssrf", void_ftype_int, AVR32_BUILTIN_SSRF);
  1142. + def_builtin ("__builtin_csrf", void_ftype_int, AVR32_BUILTIN_CSRF);
  1143. + def_builtin ("__builtin_tlbr", void_ftype_void, AVR32_BUILTIN_TLBR);
  1144. + def_builtin ("__builtin_tlbs", void_ftype_void, AVR32_BUILTIN_TLBS);
  1145. + def_builtin ("__builtin_tlbw", void_ftype_void, AVR32_BUILTIN_TLBW);
  1146. + def_builtin ("__builtin_breakpoint", void_ftype_void,
  1147. + AVR32_BUILTIN_BREAKPOINT);
  1148. + def_builtin ("__builtin_xchg", int_ftype_ptr_int, AVR32_BUILTIN_XCHG);
  1149. + def_builtin ("__builtin_ldxi", int_ftype_ptr_int, AVR32_BUILTIN_LDXI);
  1150. + def_builtin ("__builtin_bswap_16", short_ftype_short,
  1151. + AVR32_BUILTIN_BSWAP16);
  1152. + def_builtin ("__builtin_bswap_32", int_ftype_int, AVR32_BUILTIN_BSWAP32);
  1153. + def_builtin ("__builtin_cop", void_ftype_int_int_int_int_int,
  1154. + AVR32_BUILTIN_COP);
  1155. + def_builtin ("__builtin_mvcr_w", int_ftype_int_int, AVR32_BUILTIN_MVCR_W);
  1156. + def_builtin ("__builtin_mvrc_w", void_ftype_int_int_int,
  1157. + AVR32_BUILTIN_MVRC_W);
  1158. + def_builtin ("__builtin_mvcr_d", longlong_ftype_int_int,
  1159. + AVR32_BUILTIN_MVCR_D);
  1160. + def_builtin ("__builtin_mvrc_d", void_ftype_int_int_longlong,
  1161. + AVR32_BUILTIN_MVRC_D);
  1162. + def_builtin ("__builtin_sats", int_ftype_int_int_int, AVR32_BUILTIN_SATS);
  1163. + def_builtin ("__builtin_satu", int_ftype_int_int_int, AVR32_BUILTIN_SATU);
  1164. + def_builtin ("__builtin_satrnds", int_ftype_int_int_int,
  1165. + AVR32_BUILTIN_SATRNDS);
  1166. + def_builtin ("__builtin_satrndu", int_ftype_int_int_int,
  1167. + AVR32_BUILTIN_SATRNDU);
  1168. + def_builtin ("__builtin_musfr", void_ftype_int, AVR32_BUILTIN_MUSFR);
  1169. + def_builtin ("__builtin_mustr", int_ftype_void, AVR32_BUILTIN_MUSTR);
  1170. + def_builtin ("__builtin_macsathh_w", int_ftype_int_short_short,
  1171. + AVR32_BUILTIN_MACSATHH_W);
  1172. + def_builtin ("__builtin_macwh_d", longlong_ftype_longlong_int_short,
  1173. + AVR32_BUILTIN_MACWH_D);
  1174. + def_builtin ("__builtin_machh_d", longlong_ftype_longlong_short_short,
  1175. + AVR32_BUILTIN_MACHH_D);
  1176. + def_builtin ("__builtin_mems", void_ftype_ptr_int, AVR32_BUILTIN_MEMS);
  1177. + def_builtin ("__builtin_memt", void_ftype_ptr_int, AVR32_BUILTIN_MEMT);
  1178. + def_builtin ("__builtin_memc", void_ftype_ptr_int, AVR32_BUILTIN_MEMC);
  1179. + def_builtin ("__builtin_sleep", void_ftype_int, AVR32_BUILTIN_SLEEP);
  1180. + def_builtin ("__builtin_avr32_delay_cycles", void_ftype_int, AVR32_BUILTIN_DELAY_CYCLES);
  1181. +
  1182. + /* Add all builtins that are more or less simple operations on two
  1183. + operands. */
  1184. + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
  1185. + {
  1186. + /* Use one of the operands; the target can have a different mode for
  1187. + mask-generating compares. */
  1188. +
  1189. + if (d->name == 0)
  1190. + continue;
  1191. +
  1192. + def_mbuiltin (d->mask, d->name, *(d->ftype), d->code);
  1193. + }
  1194. +}
  1195. +
  1196. +
  1197. +/* Subroutine of avr32_expand_builtin to take care of binop insns. */
  1198. +static rtx
  1199. +avr32_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
  1200. +{
  1201. + rtx pat;
  1202. + tree arg0 = CALL_EXPR_ARG (exp,0);
  1203. + tree arg1 = CALL_EXPR_ARG (exp,1);
  1204. + rtx op0 = expand_normal (arg0);
  1205. + rtx op1 = expand_normal (arg1);
  1206. + enum machine_mode tmode = insn_data[icode].operand[0].mode;
  1207. + enum machine_mode mode0 = insn_data[icode].operand[1].mode;
  1208. + enum machine_mode mode1 = insn_data[icode].operand[2].mode;
  1209. +
  1210. + if (!target
  1211. + || GET_MODE (target) != tmode
  1212. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1213. + target = gen_reg_rtx (tmode);
  1214. +
  1215. + /* In case the insn wants input operands in modes different from the
  1216. + result, abort. */
  1217. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1218. + {
  1219. + /* If op0 is already a reg we must cast it to the correct mode. */
  1220. + if (REG_P (op0))
  1221. + op0 = convert_to_mode (mode0, op0, 1);
  1222. + else
  1223. + op0 = copy_to_mode_reg (mode0, op0);
  1224. + }
  1225. + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
  1226. + {
  1227. + /* If op1 is already a reg we must cast it to the correct mode. */
  1228. + if (REG_P (op1))
  1229. + op1 = convert_to_mode (mode1, op1, 1);
  1230. + else
  1231. + op1 = copy_to_mode_reg (mode1, op1);
  1232. + }
  1233. + pat = GEN_FCN (icode) (target, op0, op1);
  1234. + if (!pat)
  1235. + return 0;
  1236. + emit_insn (pat);
  1237. + return target;
  1238. +}
  1239. +
  1240. +
  1241. +/* Expand an expression EXP that calls a built-in function,
  1242. + with result going to TARGET if that's convenient
  1243. + (and in mode MODE if that's convenient).
  1244. + SUBTARGET may be used as the target for computing one of EXP's operands.
  1245. + IGNORE is nonzero if the value is to be ignored. */
  1246. +rtx
  1247. +avr32_expand_builtin (tree exp,
  1248. + rtx target,
  1249. + rtx subtarget ATTRIBUTE_UNUSED,
  1250. + enum machine_mode mode ATTRIBUTE_UNUSED,
  1251. + int ignore ATTRIBUTE_UNUSED)
  1252. +{
  1253. + const struct builtin_description *d;
  1254. + unsigned int i;
  1255. + enum insn_code icode = 0;
  1256. + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
  1257. + tree arg0, arg1, arg2;
  1258. + rtx op0, op1, op2, pat;
  1259. + enum machine_mode tmode, mode0, mode1;
  1260. + enum machine_mode arg0_mode;
  1261. + int fcode = DECL_FUNCTION_CODE (fndecl);
  1262. +
  1263. + switch (fcode)
  1264. + {
  1265. + default:
  1266. + break;
  1267. +
  1268. + case AVR32_BUILTIN_SATS:
  1269. + case AVR32_BUILTIN_SATU:
  1270. + case AVR32_BUILTIN_SATRNDS:
  1271. + case AVR32_BUILTIN_SATRNDU:
  1272. + {
  1273. + const char *fname;
  1274. + switch (fcode)
  1275. + {
  1276. + default:
  1277. + case AVR32_BUILTIN_SATS:
  1278. + icode = CODE_FOR_sats;
  1279. + fname = "sats";
  1280. + break;
  1281. + case AVR32_BUILTIN_SATU:
  1282. + icode = CODE_FOR_satu;
  1283. + fname = "satu";
  1284. + break;
  1285. + case AVR32_BUILTIN_SATRNDS:
  1286. + icode = CODE_FOR_satrnds;
  1287. + fname = "satrnds";
  1288. + break;
  1289. + case AVR32_BUILTIN_SATRNDU:
  1290. + icode = CODE_FOR_satrndu;
  1291. + fname = "satrndu";
  1292. + break;
  1293. + }
  1294. +
  1295. + arg0 = CALL_EXPR_ARG (exp,0);
  1296. + arg1 = CALL_EXPR_ARG (exp,1);
  1297. + arg2 = CALL_EXPR_ARG (exp,2);
  1298. + op0 = expand_normal (arg0);
  1299. + op1 = expand_normal (arg1);
  1300. + op2 = expand_normal (arg2);
  1301. +
  1302. + tmode = insn_data[icode].operand[0].mode;
  1303. +
  1304. +
  1305. + if (target == 0
  1306. + || GET_MODE (target) != tmode
  1307. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1308. + target = gen_reg_rtx (tmode);
  1309. +
  1310. +
  1311. + if (!(*insn_data[icode].operand[0].predicate) (op0, GET_MODE (op0)))
  1312. + {
  1313. + op0 = copy_to_mode_reg (insn_data[icode].operand[0].mode, op0);
  1314. + }
  1315. +
  1316. + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode))
  1317. + {
  1318. + error ("Parameter 2 to __builtin_%s should be a constant number.",
  1319. + fname);
  1320. + return NULL_RTX;
  1321. + }
  1322. +
  1323. + if (!(*insn_data[icode].operand[1].predicate) (op2, SImode))
  1324. + {
  1325. + error ("Parameter 3 to __builtin_%s should be a constant number.",
  1326. + fname);
  1327. + return NULL_RTX;
  1328. + }
  1329. +
  1330. + emit_move_insn (target, op0);
  1331. + pat = GEN_FCN (icode) (target, op1, op2);
  1332. + if (!pat)
  1333. + return 0;
  1334. + emit_insn (pat);
  1335. +
  1336. + return target;
  1337. + }
  1338. + case AVR32_BUILTIN_MUSTR:
  1339. + icode = CODE_FOR_mustr;
  1340. + tmode = insn_data[icode].operand[0].mode;
  1341. +
  1342. + if (target == 0
  1343. + || GET_MODE (target) != tmode
  1344. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1345. + target = gen_reg_rtx (tmode);
  1346. + pat = GEN_FCN (icode) (target);
  1347. + if (!pat)
  1348. + return 0;
  1349. + emit_insn (pat);
  1350. + return target;
  1351. +
  1352. + case AVR32_BUILTIN_MFSR:
  1353. + icode = CODE_FOR_mfsr;
  1354. + arg0 = CALL_EXPR_ARG (exp,0);
  1355. + op0 = expand_normal (arg0);
  1356. + tmode = insn_data[icode].operand[0].mode;
  1357. + mode0 = insn_data[icode].operand[1].mode;
  1358. +
  1359. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1360. + {
  1361. + error ("Parameter 1 to __builtin_mfsr must be a constant number");
  1362. + }
  1363. +
  1364. + if (target == 0
  1365. + || GET_MODE (target) != tmode
  1366. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1367. + target = gen_reg_rtx (tmode);
  1368. + pat = GEN_FCN (icode) (target, op0);
  1369. + if (!pat)
  1370. + return 0;
  1371. + emit_insn (pat);
  1372. + return target;
  1373. + case AVR32_BUILTIN_MTSR:
  1374. + icode = CODE_FOR_mtsr;
  1375. + arg0 = CALL_EXPR_ARG (exp,0);
  1376. + arg1 = CALL_EXPR_ARG (exp,1);
  1377. + op0 = expand_normal (arg0);
  1378. + op1 = expand_normal (arg1);
  1379. + mode0 = insn_data[icode].operand[0].mode;
  1380. + mode1 = insn_data[icode].operand[1].mode;
  1381. +
  1382. + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
  1383. + {
  1384. + error ("Parameter 1 to __builtin_mtsr must be a constant number");
  1385. + return gen_reg_rtx (mode0);
  1386. + }
  1387. + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
  1388. + op1 = copy_to_mode_reg (mode1, op1);
  1389. + pat = GEN_FCN (icode) (op0, op1);
  1390. + if (!pat)
  1391. + return 0;
  1392. + emit_insn (pat);
  1393. + return NULL_RTX;
  1394. + case AVR32_BUILTIN_MFDR:
  1395. + icode = CODE_FOR_mfdr;
  1396. + arg0 = CALL_EXPR_ARG (exp,0);
  1397. + op0 = expand_normal (arg0);
  1398. + tmode = insn_data[icode].operand[0].mode;
  1399. + mode0 = insn_data[icode].operand[1].mode;
  1400. +
  1401. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1402. + {
  1403. + error ("Parameter 1 to __builtin_mfdr must be a constant number");
  1404. + }
  1405. +
  1406. + if (target == 0
  1407. + || GET_MODE (target) != tmode
  1408. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1409. + target = gen_reg_rtx (tmode);
  1410. + pat = GEN_FCN (icode) (target, op0);
  1411. + if (!pat)
  1412. + return 0;
  1413. + emit_insn (pat);
  1414. + return target;
  1415. + case AVR32_BUILTIN_MTDR:
  1416. + icode = CODE_FOR_mtdr;
  1417. + arg0 = CALL_EXPR_ARG (exp,0);
  1418. + arg1 = CALL_EXPR_ARG (exp,1);
  1419. + op0 = expand_normal (arg0);
  1420. + op1 = expand_normal (arg1);
  1421. + mode0 = insn_data[icode].operand[0].mode;
  1422. + mode1 = insn_data[icode].operand[1].mode;
  1423. +
  1424. + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
  1425. + {
  1426. + error ("Parameter 1 to __builtin_mtdr must be a constant number");
  1427. + return gen_reg_rtx (mode0);
  1428. + }
  1429. + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
  1430. + op1 = copy_to_mode_reg (mode1, op1);
  1431. + pat = GEN_FCN (icode) (op0, op1);
  1432. + if (!pat)
  1433. + return 0;
  1434. + emit_insn (pat);
  1435. + return NULL_RTX;
  1436. + case AVR32_BUILTIN_CACHE:
  1437. + icode = CODE_FOR_cache;
  1438. + arg0 = CALL_EXPR_ARG (exp,0);
  1439. + arg1 = CALL_EXPR_ARG (exp,1);
  1440. + op0 = expand_normal (arg0);
  1441. + op1 = expand_normal (arg1);
  1442. + mode0 = insn_data[icode].operand[0].mode;
  1443. + mode1 = insn_data[icode].operand[1].mode;
  1444. +
  1445. + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
  1446. + {
  1447. + error ("Parameter 2 to __builtin_cache must be a constant number");
  1448. + return gen_reg_rtx (mode1);
  1449. + }
  1450. +
  1451. + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
  1452. + op0 = copy_to_mode_reg (mode0, op0);
  1453. +
  1454. + pat = GEN_FCN (icode) (op0, op1);
  1455. + if (!pat)
  1456. + return 0;
  1457. + emit_insn (pat);
  1458. + return NULL_RTX;
  1459. + case AVR32_BUILTIN_SYNC:
  1460. + case AVR32_BUILTIN_MUSFR:
  1461. + case AVR32_BUILTIN_SSRF:
  1462. + case AVR32_BUILTIN_CSRF:
  1463. + {
  1464. + const char *fname;
  1465. + switch (fcode)
  1466. + {
  1467. + default:
  1468. + case AVR32_BUILTIN_SYNC:
  1469. + icode = CODE_FOR_sync;
  1470. + fname = "sync";
  1471. + break;
  1472. + case AVR32_BUILTIN_MUSFR:
  1473. + icode = CODE_FOR_musfr;
  1474. + fname = "musfr";
  1475. + break;
  1476. + case AVR32_BUILTIN_SSRF:
  1477. + icode = CODE_FOR_ssrf;
  1478. + fname = "ssrf";
  1479. + break;
  1480. + case AVR32_BUILTIN_CSRF:
  1481. + icode = CODE_FOR_csrf;
  1482. + fname = "csrf";
  1483. + break;
  1484. + }
  1485. +
  1486. + arg0 = CALL_EXPR_ARG (exp,0);
  1487. + op0 = expand_normal (arg0);
  1488. + mode0 = insn_data[icode].operand[0].mode;
  1489. +
  1490. + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
  1491. + {
  1492. + if (icode == CODE_FOR_musfr)
  1493. + op0 = copy_to_mode_reg (mode0, op0);
  1494. + else
  1495. + {
  1496. + error ("Parameter to __builtin_%s is illegal.", fname);
  1497. + return gen_reg_rtx (mode0);
  1498. + }
  1499. + }
  1500. + pat = GEN_FCN (icode) (op0);
  1501. + if (!pat)
  1502. + return 0;
  1503. + emit_insn (pat);
  1504. + return NULL_RTX;
  1505. + }
  1506. + case AVR32_BUILTIN_TLBR:
  1507. + icode = CODE_FOR_tlbr;
  1508. + pat = GEN_FCN (icode) (NULL_RTX);
  1509. + if (!pat)
  1510. + return 0;
  1511. + emit_insn (pat);
  1512. + return NULL_RTX;
  1513. + case AVR32_BUILTIN_TLBS:
  1514. + icode = CODE_FOR_tlbs;
  1515. + pat = GEN_FCN (icode) (NULL_RTX);
  1516. + if (!pat)
  1517. + return 0;
  1518. + emit_insn (pat);
  1519. + return NULL_RTX;
  1520. + case AVR32_BUILTIN_TLBW:
  1521. + icode = CODE_FOR_tlbw;
  1522. + pat = GEN_FCN (icode) (NULL_RTX);
  1523. + if (!pat)
  1524. + return 0;
  1525. + emit_insn (pat);
  1526. + return NULL_RTX;
  1527. + case AVR32_BUILTIN_BREAKPOINT:
  1528. + icode = CODE_FOR_breakpoint;
  1529. + pat = GEN_FCN (icode) (NULL_RTX);
  1530. + if (!pat)
  1531. + return 0;
  1532. + emit_insn (pat);
  1533. + return NULL_RTX;
  1534. + case AVR32_BUILTIN_XCHG:
  1535. + icode = CODE_FOR_sync_lock_test_and_setsi;
  1536. + arg0 = CALL_EXPR_ARG (exp,0);
  1537. + arg1 = CALL_EXPR_ARG (exp,1);
  1538. + op0 = expand_normal (arg0);
  1539. + op1 = expand_normal (arg1);
  1540. + tmode = insn_data[icode].operand[0].mode;
  1541. + mode0 = insn_data[icode].operand[1].mode;
  1542. + mode1 = insn_data[icode].operand[2].mode;
  1543. +
  1544. + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
  1545. + {
  1546. + op1 = copy_to_mode_reg (mode1, op1);
  1547. + }
  1548. +
  1549. + op0 = force_reg (GET_MODE (op0), op0);
  1550. + op0 = gen_rtx_MEM (GET_MODE (op0), op0);
  1551. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1552. + {
  1553. + error
  1554. + ("Parameter 1 to __builtin_xchg must be a pointer to an integer.");
  1555. + }
  1556. +
  1557. + if (target == 0
  1558. + || GET_MODE (target) != tmode
  1559. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1560. + target = gen_reg_rtx (tmode);
  1561. + pat = GEN_FCN (icode) (target, op0, op1);
  1562. + if (!pat)
  1563. + return 0;
  1564. + emit_insn (pat);
  1565. + return target;
  1566. + case AVR32_BUILTIN_LDXI:
  1567. + icode = CODE_FOR_ldxi;
  1568. + arg0 = CALL_EXPR_ARG (exp,0);
  1569. + arg1 = CALL_EXPR_ARG (exp,1);
  1570. + arg2 = CALL_EXPR_ARG (exp,2);
  1571. + op0 = expand_normal (arg0);
  1572. + op1 = expand_normal (arg1);
  1573. + op2 = expand_normal (arg2);
  1574. + tmode = insn_data[icode].operand[0].mode;
  1575. + mode0 = insn_data[icode].operand[1].mode;
  1576. + mode1 = insn_data[icode].operand[2].mode;
  1577. +
  1578. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1579. + {
  1580. + op0 = copy_to_mode_reg (mode0, op0);
  1581. + }
  1582. +
  1583. + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
  1584. + {
  1585. + op1 = copy_to_mode_reg (mode1, op1);
  1586. + }
  1587. +
  1588. + if (!(*insn_data[icode].operand[3].predicate) (op2, SImode))
  1589. + {
  1590. + error
  1591. + ("Parameter 3 to __builtin_ldxi must be a valid extract shift operand: (0|8|16|24)");
  1592. + return gen_reg_rtx (mode0);
  1593. + }
  1594. +
  1595. + if (target == 0
  1596. + || GET_MODE (target) != tmode
  1597. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1598. + target = gen_reg_rtx (tmode);
  1599. + pat = GEN_FCN (icode) (target, op0, op1, op2);
  1600. + if (!pat)
  1601. + return 0;
  1602. + emit_insn (pat);
  1603. + return target;
  1604. + case AVR32_BUILTIN_BSWAP16:
  1605. + {
  1606. + icode = CODE_FOR_bswap_16;
  1607. + arg0 = CALL_EXPR_ARG (exp,0);
  1608. + arg0_mode = TYPE_MODE (TREE_TYPE (arg0));
  1609. + mode0 = insn_data[icode].operand[1].mode;
  1610. + if (arg0_mode != mode0)
  1611. + arg0 = build1 (NOP_EXPR,
  1612. + (*lang_hooks.types.type_for_mode) (mode0, 0), arg0);
  1613. +
  1614. + op0 = expand_expr (arg0, NULL_RTX, HImode, 0);
  1615. + tmode = insn_data[icode].operand[0].mode;
  1616. +
  1617. +
  1618. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1619. + {
  1620. + if ( CONST_INT_P (op0) )
  1621. + {
  1622. + HOST_WIDE_INT val = ( ((INTVAL (op0)&0x00ff) << 8) |
  1623. + ((INTVAL (op0)&0xff00) >> 8) );
  1624. + /* Sign extend 16-bit value to host wide int */
  1625. + val <<= (HOST_BITS_PER_WIDE_INT - 16);
  1626. + val >>= (HOST_BITS_PER_WIDE_INT - 16);
  1627. + op0 = GEN_INT(val);
  1628. + if (target == 0
  1629. + || GET_MODE (target) != tmode
  1630. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1631. + target = gen_reg_rtx (tmode);
  1632. + emit_move_insn(target, op0);
  1633. + return target;
  1634. + }
  1635. + else
  1636. + op0 = copy_to_mode_reg (mode0, op0);
  1637. + }
  1638. +
  1639. + if (target == 0
  1640. + || GET_MODE (target) != tmode
  1641. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1642. + {
  1643. + target = gen_reg_rtx (tmode);
  1644. + }
  1645. +
  1646. +
  1647. + pat = GEN_FCN (icode) (target, op0);
  1648. + if (!pat)
  1649. + return 0;
  1650. + emit_insn (pat);
  1651. +
  1652. + return target;
  1653. + }
  1654. + case AVR32_BUILTIN_BSWAP32:
  1655. + {
  1656. + icode = CODE_FOR_bswap_32;
  1657. + arg0 = CALL_EXPR_ARG (exp,0);
  1658. + op0 = expand_normal (arg0);
  1659. + tmode = insn_data[icode].operand[0].mode;
  1660. + mode0 = insn_data[icode].operand[1].mode;
  1661. +
  1662. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1663. + {
  1664. + if ( CONST_INT_P (op0) )
  1665. + {
  1666. + HOST_WIDE_INT val = ( ((INTVAL (op0)&0x000000ff) << 24) |
  1667. + ((INTVAL (op0)&0x0000ff00) << 8) |
  1668. + ((INTVAL (op0)&0x00ff0000) >> 8) |
  1669. + ((INTVAL (op0)&0xff000000) >> 24) );
  1670. + /* Sign extend 32-bit value to host wide int */
  1671. + val <<= (HOST_BITS_PER_WIDE_INT - 32);
  1672. + val >>= (HOST_BITS_PER_WIDE_INT - 32);
  1673. + op0 = GEN_INT(val);
  1674. + if (target == 0
  1675. + || GET_MODE (target) != tmode
  1676. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1677. + target = gen_reg_rtx (tmode);
  1678. + emit_move_insn(target, op0);
  1679. + return target;
  1680. + }
  1681. + else
  1682. + op0 = copy_to_mode_reg (mode0, op0);
  1683. + }
  1684. +
  1685. + if (target == 0
  1686. + || GET_MODE (target) != tmode
  1687. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1688. + target = gen_reg_rtx (tmode);
  1689. +
  1690. +
  1691. + pat = GEN_FCN (icode) (target, op0);
  1692. + if (!pat)
  1693. + return 0;
  1694. + emit_insn (pat);
  1695. +
  1696. + return target;
  1697. + }
  1698. + case AVR32_BUILTIN_MVCR_W:
  1699. + case AVR32_BUILTIN_MVCR_D:
  1700. + {
  1701. + arg0 = CALL_EXPR_ARG (exp,0);
  1702. + arg1 = CALL_EXPR_ARG (exp,1);
  1703. + op0 = expand_normal (arg0);
  1704. + op1 = expand_normal (arg1);
  1705. +
  1706. + if (fcode == AVR32_BUILTIN_MVCR_W)
  1707. + icode = CODE_FOR_mvcrsi;
  1708. + else
  1709. + icode = CODE_FOR_mvcrdi;
  1710. +
  1711. + tmode = insn_data[icode].operand[0].mode;
  1712. +
  1713. + if (target == 0
  1714. + || GET_MODE (target) != tmode
  1715. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1716. + target = gen_reg_rtx (tmode);
  1717. +
  1718. + if (!(*insn_data[icode].operand[1].predicate) (op0, SImode))
  1719. + {
  1720. + error
  1721. + ("Parameter 1 to __builtin_cop is not a valid coprocessor number.");
  1722. + error ("Number should be between 0 and 7.");
  1723. + return NULL_RTX;
  1724. + }
  1725. +
  1726. + if (!(*insn_data[icode].operand[2].predicate) (op1, SImode))
  1727. + {
  1728. + error
  1729. + ("Parameter 2 to __builtin_cop is not a valid coprocessor register number.");
  1730. + error ("Number should be between 0 and 15.");
  1731. + return NULL_RTX;
  1732. + }
  1733. +
  1734. + pat = GEN_FCN (icode) (target, op0, op1);
  1735. + if (!pat)
  1736. + return 0;
  1737. + emit_insn (pat);
  1738. +
  1739. + return target;
  1740. + }
  1741. + case AVR32_BUILTIN_MACSATHH_W:
  1742. + case AVR32_BUILTIN_MACWH_D:
  1743. + case AVR32_BUILTIN_MACHH_D:
  1744. + {
  1745. + arg0 = CALL_EXPR_ARG (exp,0);
  1746. + arg1 = CALL_EXPR_ARG (exp,1);
  1747. + arg2 = CALL_EXPR_ARG (exp,2);
  1748. + op0 = expand_normal (arg0);
  1749. + op1 = expand_normal (arg1);
  1750. + op2 = expand_normal (arg2);
  1751. +
  1752. + icode = ((fcode == AVR32_BUILTIN_MACSATHH_W) ? CODE_FOR_macsathh_w :
  1753. + (fcode == AVR32_BUILTIN_MACWH_D) ? CODE_FOR_macwh_d :
  1754. + CODE_FOR_machh_d);
  1755. +
  1756. + tmode = insn_data[icode].operand[0].mode;
  1757. + mode0 = insn_data[icode].operand[1].mode;
  1758. + mode1 = insn_data[icode].operand[2].mode;
  1759. +
  1760. +
  1761. + if (!target
  1762. + || GET_MODE (target) != tmode
  1763. + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
  1764. + target = gen_reg_rtx (tmode);
  1765. +
  1766. + if (!(*insn_data[icode].operand[0].predicate) (op0, tmode))
  1767. + {
  1768. + /* If op0 is already a reg we must cast it to the correct mode. */
  1769. + if (REG_P (op0))
  1770. + op0 = convert_to_mode (tmode, op0, 1);
  1771. + else
  1772. + op0 = copy_to_mode_reg (tmode, op0);
  1773. + }
  1774. +
  1775. + if (!(*insn_data[icode].operand[1].predicate) (op1, mode0))
  1776. + {
  1777. + /* If op1 is already a reg we must cast it to the correct mode. */
  1778. + if (REG_P (op1))
  1779. + op1 = convert_to_mode (mode0, op1, 1);
  1780. + else
  1781. + op1 = copy_to_mode_reg (mode0, op1);
  1782. + }
  1783. +
  1784. + if (!(*insn_data[icode].operand[2].predicate) (op2, mode1))
  1785. + {
  1786. + /* If op1 is already a reg we must cast it to the correct mode. */
  1787. + if (REG_P (op2))
  1788. + op2 = convert_to_mode (mode1, op2, 1);
  1789. + else
  1790. + op2 = copy_to_mode_reg (mode1, op2);
  1791. + }
  1792. +
  1793. + emit_move_insn (target, op0);
  1794. +
  1795. + pat = GEN_FCN (icode) (target, op1, op2);
  1796. + if (!pat)
  1797. + return 0;
  1798. + emit_insn (pat);
  1799. + return target;
  1800. + }
  1801. + case AVR32_BUILTIN_MVRC_W:
  1802. + case AVR32_BUILTIN_MVRC_D:
  1803. + {
  1804. + arg0 = CALL_EXPR_ARG (exp,0);
  1805. + arg1 = CALL_EXPR_ARG (exp,1);
  1806. + arg2 = CALL_EXPR_ARG (exp,2);
  1807. + op0 = expand_normal (arg0);
  1808. + op1 = expand_normal (arg1);
  1809. + op2 = expand_normal (arg2);
  1810. +
  1811. + if (fcode == AVR32_BUILTIN_MVRC_W)
  1812. + icode = CODE_FOR_mvrcsi;
  1813. + else
  1814. + icode = CODE_FOR_mvrcdi;
  1815. +
  1816. + if (!(*insn_data[icode].operand[0].predicate) (op0, SImode))
  1817. + {
  1818. + error ("Parameter 1 is not a valid coprocessor number.");
  1819. + error ("Number should be between 0 and 7.");
  1820. + return NULL_RTX;
  1821. + }
  1822. +
  1823. + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode))
  1824. + {
  1825. + error ("Parameter 2 is not a valid coprocessor register number.");
  1826. + error ("Number should be between 0 and 15.");
  1827. + return NULL_RTX;
  1828. + }
  1829. +
  1830. + if (GET_CODE (op2) == CONST_INT
  1831. + || GET_CODE (op2) == CONST
  1832. + || GET_CODE (op2) == SYMBOL_REF || GET_CODE (op2) == LABEL_REF)
  1833. + {
  1834. + op2 = force_const_mem (insn_data[icode].operand[2].mode, op2);
  1835. + }
  1836. +
  1837. + if (!(*insn_data[icode].operand[2].predicate) (op2, GET_MODE (op2)))
  1838. + op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2);
  1839. +
  1840. +
  1841. + pat = GEN_FCN (icode) (op0, op1, op2);
  1842. + if (!pat)
  1843. + return 0;
  1844. + emit_insn (pat);
  1845. +
  1846. + return NULL_RTX;
  1847. + }
  1848. + case AVR32_BUILTIN_COP:
  1849. + {
  1850. + rtx op3, op4;
  1851. + tree arg3, arg4;
  1852. + icode = CODE_FOR_cop;
  1853. + arg0 = CALL_EXPR_ARG (exp,0);
  1854. + arg1 = CALL_EXPR_ARG (exp,1);
  1855. + arg2 = CALL_EXPR_ARG (exp,2);
  1856. + arg3 = CALL_EXPR_ARG (exp,3);
  1857. + arg4 = CALL_EXPR_ARG (exp,4);
  1858. + op0 = expand_normal (arg0);
  1859. + op1 = expand_normal (arg1);
  1860. + op2 = expand_normal (arg2);
  1861. + op3 = expand_normal (arg3);
  1862. + op4 = expand_normal (arg4);
  1863. +
  1864. + if (!(*insn_data[icode].operand[0].predicate) (op0, SImode))
  1865. + {
  1866. + error
  1867. + ("Parameter 1 to __builtin_cop is not a valid coprocessor number.");
  1868. + error ("Number should be between 0 and 7.");
  1869. + return NULL_RTX;
  1870. + }
  1871. +
  1872. + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode))
  1873. + {
  1874. + error
  1875. + ("Parameter 2 to __builtin_cop is not a valid coprocessor register number.");
  1876. + error ("Number should be between 0 and 15.");
  1877. + return NULL_RTX;
  1878. + }
  1879. +
  1880. + if (!(*insn_data[icode].operand[2].predicate) (op2, SImode))
  1881. + {
  1882. + error
  1883. + ("Parameter 3 to __builtin_cop is not a valid coprocessor register number.");
  1884. + error ("Number should be between 0 and 15.");
  1885. + return NULL_RTX;
  1886. + }
  1887. +
  1888. + if (!(*insn_data[icode].operand[3].predicate) (op3, SImode))
  1889. + {
  1890. + error
  1891. + ("Parameter 4 to __builtin_cop is not a valid coprocessor register number.");
  1892. + error ("Number should be between 0 and 15.");
  1893. + return NULL_RTX;
  1894. + }
  1895. +
  1896. + if (!(*insn_data[icode].operand[4].predicate) (op4, SImode))
  1897. + {
  1898. + error
  1899. + ("Parameter 5 to __builtin_cop is not a valid coprocessor operation.");
  1900. + error ("Number should be between 0 and 127.");
  1901. + return NULL_RTX;
  1902. + }
  1903. +
  1904. + pat = GEN_FCN (icode) (op0, op1, op2, op3, op4);
  1905. + if (!pat)
  1906. + return 0;
  1907. + emit_insn (pat);
  1908. +
  1909. + return target;
  1910. + }
  1911. +
  1912. + case AVR32_BUILTIN_MEMS:
  1913. + case AVR32_BUILTIN_MEMC:
  1914. + case AVR32_BUILTIN_MEMT:
  1915. + {
  1916. + if (!TARGET_RMW)
  1917. + error ("Trying to use __builtin_mem(s/c/t) when target does not support RMW insns.");
  1918. +
  1919. + switch (fcode) {
  1920. + case AVR32_BUILTIN_MEMS:
  1921. + icode = CODE_FOR_iorsi3;
  1922. + break;
  1923. + case AVR32_BUILTIN_MEMC:
  1924. + icode = CODE_FOR_andsi3;
  1925. + break;
  1926. + case AVR32_BUILTIN_MEMT:
  1927. + icode = CODE_FOR_xorsi3;
  1928. + break;
  1929. + }
  1930. + arg0 = CALL_EXPR_ARG (exp,0);
  1931. + arg1 = CALL_EXPR_ARG (exp,1);
  1932. + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
  1933. + if ( GET_CODE (op0) == SYMBOL_REF )
  1934. + // This symbol must be RMW addressable
  1935. + SYMBOL_REF_FLAGS (op0) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT);
  1936. + op0 = gen_rtx_MEM(SImode, op0);
  1937. + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
  1938. + mode0 = insn_data[icode].operand[1].mode;
  1939. +
  1940. +
  1941. + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
  1942. + {
  1943. + error ("Parameter 1 to __builtin_mem(s/c/t) must be a Ks15<<2 address or a rmw addressable symbol.");
  1944. + }
  1945. +
  1946. + if ( !CONST_INT_P (op1)
  1947. + || INTVAL (op1) > 31
  1948. + || INTVAL (op1) < 0 )
  1949. + error ("Parameter 2 to __builtin_mem(s/c/t) must be a constant between 0 and 31.");
  1950. +
  1951. + if ( fcode == AVR32_BUILTIN_MEMC )
  1952. + op1 = GEN_INT((~(1 << INTVAL(op1)))&0xffffffff);
  1953. + else
  1954. + op1 = GEN_INT((1 << INTVAL(op1))&0xffffffff);
  1955. + pat = GEN_FCN (icode) (op0, op0, op1);
  1956. + if (!pat)
  1957. + return 0;
  1958. + emit_insn (pat);
  1959. + return op0;
  1960. + }
  1961. +
  1962. + case AVR32_BUILTIN_SLEEP:
  1963. + {
  1964. + arg0 = CALL_EXPR_ARG (exp, 0);
  1965. + op0 = expand_normal (arg0);
  1966. + int intval = INTVAL(op0);
  1967. +
  1968. + /* Check if the argument if integer and if the value of integer
  1969. + is greater than 0. */
  1970. +
  1971. + if (!CONSTANT_P (op0))
  1972. + error ("Parameter 1 to __builtin_sleep() is not a valid integer.");
  1973. + if (intval < 0 )
  1974. + error ("Parameter 1 to __builtin_sleep() should be an integer greater than 0.");
  1975. +
  1976. + int strncmpval = strncmp (avr32_part_name,"uc3l", 4);
  1977. +
  1978. + /* Check if op0 is less than 7 for uc3l* and less than 6 for other
  1979. + devices. By this check we are avoiding if operand is less than
  1980. + 256. For more devices, add more such checks. */
  1981. +
  1982. + if ( strncmpval == 0 && intval >= 7)
  1983. + error ("Parameter 1 to __builtin_sleep() should be less than or equal to 7.");
  1984. + else if ( strncmp != 0 && intval >= 6)
  1985. + error ("Parameter 1 to __builtin_sleep() should be less than or equal to 6.");
  1986. +
  1987. + emit_insn (gen_sleep(op0));
  1988. + return target;
  1989. +
  1990. + }
  1991. + case AVR32_BUILTIN_DELAY_CYCLES:
  1992. + {
  1993. + arg0 = CALL_EXPR_ARG (exp, 0);
  1994. + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
  1995. +
  1996. + if (TARGET_ARCH_AP)
  1997. + error (" __builtin_avr32_delay_cycles() not supported for \'%s\' architecture.", avr32_arch_name);
  1998. + if (!CONSTANT_P (op0))
  1999. + error ("Parameter 1 to __builtin_avr32_delay_cycles() should be an integer.");
  2000. + emit_insn (gen_delay_cycles (op0));
  2001. + return 0;
  2002. +
  2003. + }
  2004. +
  2005. + }
  2006. +
  2007. + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
  2008. + if (d->code == fcode)
  2009. + return avr32_expand_binop_builtin (d->icode, exp, target);
  2010. +
  2011. +
  2012. + /* @@@ Should really do something sensible here. */
  2013. + return NULL_RTX;
  2014. +}
  2015. +
  2016. +
  2017. +/* Handle an "interrupt" or "isr" attribute;
  2018. + arguments as in struct attribute_spec.handler. */
  2019. +static tree
  2020. +avr32_handle_isr_attribute (tree * node, tree name, tree args,
  2021. + int flags, bool * no_add_attrs)
  2022. +{
  2023. + if (DECL_P (*node))
  2024. + {
  2025. + if (TREE_CODE (*node) != FUNCTION_DECL)
  2026. + {
  2027. + warning (OPT_Wattributes,"`%s' attribute only applies to functions",
  2028. + IDENTIFIER_POINTER (name));
  2029. + *no_add_attrs = true;
  2030. + }
  2031. + /* FIXME: the argument if any is checked for type attributes; should it
  2032. + be checked for decl ones? */
  2033. + }
  2034. + else
  2035. + {
  2036. + if (TREE_CODE (*node) == FUNCTION_TYPE
  2037. + || TREE_CODE (*node) == METHOD_TYPE)
  2038. + {
  2039. + if (avr32_isr_value (args) == AVR32_FT_UNKNOWN)
  2040. + {
  2041. + warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name));
  2042. + *no_add_attrs = true;
  2043. + }
  2044. + }
  2045. + else if (TREE_CODE (*node) == POINTER_TYPE
  2046. + && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
  2047. + || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
  2048. + && avr32_isr_value (args) != AVR32_FT_UNKNOWN)
  2049. + {
  2050. + *node = build_variant_type_copy (*node);
  2051. + TREE_TYPE (*node) = build_type_attribute_variant
  2052. + (TREE_TYPE (*node),
  2053. + tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
  2054. + *no_add_attrs = true;
  2055. + }
  2056. + else
  2057. + {
  2058. + /* Possibly pass this attribute on from the type to a decl. */
  2059. + if (flags & ((int) ATTR_FLAG_DECL_NEXT
  2060. + | (int) ATTR_FLAG_FUNCTION_NEXT
  2061. + | (int) ATTR_FLAG_ARRAY_NEXT))
  2062. + {
  2063. + *no_add_attrs = true;
  2064. + return tree_cons (name, args, NULL_TREE);
  2065. + }
  2066. + else
  2067. + {
  2068. + warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name));
  2069. + }
  2070. + }
  2071. + }
  2072. +
  2073. + return NULL_TREE;
  2074. +}
  2075. +
  2076. +
  2077. +/* Handle an attribute requiring a FUNCTION_DECL;
  2078. + arguments as in struct attribute_spec.handler. */
  2079. +static tree
  2080. +avr32_handle_fndecl_attribute (tree * node, tree name,
  2081. + tree args,
  2082. + int flags ATTRIBUTE_UNUSED,
  2083. + bool * no_add_attrs)
  2084. +{
  2085. + if (TREE_CODE (*node) != FUNCTION_DECL)
  2086. + {
  2087. + warning (OPT_Wattributes,"%qs attribute only applies to functions",
  2088. + IDENTIFIER_POINTER (name));
  2089. + *no_add_attrs = true;
  2090. + return NULL_TREE;
  2091. + }
  2092. +
  2093. + fndecl_attribute_args = args;
  2094. + if (args == NULL_TREE)
  2095. + return NULL_TREE;
  2096. +
  2097. + tree value = TREE_VALUE (args);
  2098. + if (TREE_CODE (value) != INTEGER_CST)
  2099. + {
  2100. + warning (OPT_Wattributes,
  2101. + "argument of %qs attribute is not an integer constant",
  2102. + IDENTIFIER_POINTER (name));
  2103. + *no_add_attrs = true;
  2104. + }
  2105. +
  2106. + return NULL_TREE;
  2107. +}
  2108. +
  2109. +
  2110. +/* Handle an acall attribute;
  2111. + arguments as in struct attribute_spec.handler. */
  2112. +
  2113. +static tree
  2114. +avr32_handle_acall_attribute (tree * node, tree name,
  2115. + tree args ATTRIBUTE_UNUSED,
  2116. + int flags ATTRIBUTE_UNUSED, bool * no_add_attrs)
  2117. +{
  2118. + if (TREE_CODE (*node) == FUNCTION_TYPE || TREE_CODE (*node) == METHOD_TYPE)
  2119. + {
  2120. + warning (OPT_Wattributes,"`%s' attribute not yet supported...",
  2121. + IDENTIFIER_POINTER (name));
  2122. + *no_add_attrs = true;
  2123. + return NULL_TREE;
  2124. + }
  2125. +
  2126. + warning (OPT_Wattributes,"`%s' attribute only applies to functions",
  2127. + IDENTIFIER_POINTER (name));
  2128. + *no_add_attrs = true;
  2129. + return NULL_TREE;
  2130. +}
  2131. +
  2132. +
  2133. +bool
  2134. +avr32_flashvault_call(tree decl)
  2135. +{
  2136. + tree attributes;
  2137. + tree fv_attribute;
  2138. + tree vector_tree;
  2139. + unsigned int vector;
  2140. +
  2141. + if (decl && TREE_CODE (decl) == FUNCTION_DECL)
  2142. + {
  2143. + attributes = DECL_ATTRIBUTES(decl);
  2144. + fv_attribute = lookup_attribute ("flashvault", attributes);
  2145. + if (fv_attribute != NULL_TREE)
  2146. + {
  2147. + /* Get attribute parameter, for the function vector number. */
  2148. + /*
  2149. + There is probably an easier, standard way to retrieve the
  2150. + attribute parameter which needs to be done here.
  2151. + */
  2152. + vector_tree = TREE_VALUE(fv_attribute);
  2153. + if (vector_tree != NULL_TREE)
  2154. + {
  2155. + vector = (unsigned int)TREE_INT_CST_LOW(TREE_VALUE(vector_tree));
  2156. + fprintf (asm_out_file,
  2157. + "\tmov\tr8, lo(%i)\t# Load vector number for sscall.\n",
  2158. + vector);
  2159. + }
  2160. +
  2161. + fprintf (asm_out_file,
  2162. + "\tsscall\t# Secure system call.\n");
  2163. +
  2164. + return true;
  2165. + }
  2166. + }
  2167. +
  2168. + return false;
  2169. +}
  2170. +
  2171. +
  2172. +static bool has_attribute_p (tree decl, const char *name)
  2173. +{
  2174. + if (decl && TREE_CODE (decl) == FUNCTION_DECL)
  2175. + {
  2176. + return (lookup_attribute (name, DECL_ATTRIBUTES(decl)) != NULL_TREE);
  2177. + }
  2178. + return NULL_TREE;
  2179. +}
  2180. +
  2181. +
  2182. +/* Return 0 if the attributes for two types are incompatible, 1 if they
  2183. + are compatible, and 2 if they are nearly compatible (which causes a
  2184. + warning to be generated). */
  2185. +static int
  2186. +avr32_comp_type_attributes (tree type1, tree type2)
  2187. +{
  2188. + bool acall1, acall2, isr1, isr2, naked1, naked2, fv1, fv2, fvimpl1, fvimpl2;
  2189. +
  2190. + /* Check for mismatch of non-default calling convention. */
  2191. + if (TREE_CODE (type1) != FUNCTION_TYPE)
  2192. + return 1;
  2193. +
  2194. + /* Check for mismatched call attributes. */
  2195. + acall1 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type1)) != NULL;
  2196. + acall2 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type2)) != NULL;
  2197. + naked1 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type1)) != NULL;
  2198. + naked2 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type2)) != NULL;
  2199. + fv1 = lookup_attribute ("flashvault", TYPE_ATTRIBUTES (type1)) != NULL;
  2200. + fv2 = lookup_attribute ("flashvault", TYPE_ATTRIBUTES (type2)) != NULL;
  2201. + fvimpl1 = lookup_attribute ("flashvault_impl", TYPE_ATTRIBUTES (type1)) != NULL;
  2202. + fvimpl2 = lookup_attribute ("flashvault_impl", TYPE_ATTRIBUTES (type2)) != NULL;
  2203. + isr1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
  2204. + if (!isr1)
  2205. + isr1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
  2206. +
  2207. + isr2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
  2208. + if (!isr2)
  2209. + isr2 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
  2210. +
  2211. + if ((acall1 && isr2)
  2212. + || (acall2 && isr1)
  2213. + || (naked1 && isr2)
  2214. + || (naked2 && isr1)
  2215. + || (fv1 && isr2)
  2216. + || (fv2 && isr1)
  2217. + || (fvimpl1 && isr2)
  2218. + || (fvimpl2 && isr1)
  2219. + || (fv1 && fvimpl2)
  2220. + || (fv2 && fvimpl1)
  2221. + )
  2222. + return 0;
  2223. +
  2224. + return 1;
  2225. +}
  2226. +
  2227. +
  2228. +/* Computes the type of the current function. */
  2229. +static unsigned long
  2230. +avr32_compute_func_type (void)
  2231. +{
  2232. + unsigned long type = AVR32_FT_UNKNOWN;
  2233. + tree a;
  2234. + tree attr;
  2235. +
  2236. + if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
  2237. + abort ();
  2238. +
  2239. + /* Decide if the current function is volatile. Such functions never
  2240. + return, and many memory cycles can be saved by not storing register
  2241. + values that will never be needed again. This optimization was added to
  2242. + speed up context switching in a kernel application. */
  2243. + if (optimize > 0
  2244. + && TREE_NOTHROW (current_function_decl)
  2245. + && TREE_THIS_VOLATILE (current_function_decl))
  2246. + type |= AVR32_FT_VOLATILE;
  2247. +
  2248. + if (cfun->static_chain_decl != NULL)
  2249. + type |= AVR32_FT_NESTED;
  2250. +
  2251. + attr = DECL_ATTRIBUTES (current_function_decl);
  2252. +
  2253. + a = lookup_attribute ("isr", attr);
  2254. + if (a == NULL_TREE)
  2255. + a = lookup_attribute ("interrupt", attr);
  2256. +
  2257. + if (a == NULL_TREE)
  2258. + type |= AVR32_FT_NORMAL;
  2259. + else
  2260. + type |= avr32_isr_value (TREE_VALUE (a));
  2261. +
  2262. +
  2263. + a = lookup_attribute ("acall", attr);
  2264. + if (a != NULL_TREE)
  2265. + type |= AVR32_FT_ACALL;
  2266. +
  2267. + a = lookup_attribute ("naked", attr);
  2268. + if (a != NULL_TREE)
  2269. + type |= AVR32_FT_NAKED;
  2270. +
  2271. + a = lookup_attribute ("flashvault", attr);
  2272. + if (a != NULL_TREE)
  2273. + type |= AVR32_FT_FLASHVAULT;
  2274. +
  2275. + a = lookup_attribute ("flashvault_impl", attr);
  2276. + if (a != NULL_TREE)
  2277. + type |= AVR32_FT_FLASHVAULT_IMPL;
  2278. +
  2279. + return type;
  2280. +}
  2281. +
  2282. +
  2283. +/* Returns the type of the current function. */
  2284. +static unsigned long
  2285. +avr32_current_func_type (void)
  2286. +{
  2287. + if (AVR32_FUNC_TYPE (cfun->machine->func_type) == AVR32_FT_UNKNOWN)
  2288. + cfun->machine->func_type = avr32_compute_func_type ();
  2289. +
  2290. + return cfun->machine->func_type;
  2291. +}
  2292. +
  2293. +
  2294. +/*
  2295. +This target hook should return true if we should not pass type solely
  2296. +in registers. The file expr.h defines a definition that is usually appropriate,
  2297. +refer to expr.h for additional documentation.
  2298. +*/
  2299. +bool
  2300. +avr32_must_pass_in_stack (enum machine_mode mode ATTRIBUTE_UNUSED, tree type)
  2301. +{
  2302. + if (type && AGGREGATE_TYPE_P (type)
  2303. + /* If the alignment is less than the size then pass in the struct on
  2304. + the stack. */
  2305. + && ((unsigned int) TYPE_ALIGN_UNIT (type) <
  2306. + (unsigned int) int_size_in_bytes (type))
  2307. + /* If we support unaligned word accesses then structs of size 4 and 8
  2308. + can have any alignment and still be passed in registers. */
  2309. + && !(TARGET_UNALIGNED_WORD
  2310. + && (int_size_in_bytes (type) == 4
  2311. + || int_size_in_bytes (type) == 8))
  2312. + /* Double word structs need only a word alignment. */
  2313. + && !(int_size_in_bytes (type) == 8 && TYPE_ALIGN_UNIT (type) >= 4))
  2314. + return true;
  2315. +
  2316. + if (type && AGGREGATE_TYPE_P (type)
  2317. + /* Structs of size 3,5,6,7 are always passed in registers. */
  2318. + && (int_size_in_bytes (type) == 3
  2319. + || int_size_in_bytes (type) == 5
  2320. + || int_size_in_bytes (type) == 6 || int_size_in_bytes (type) == 7))
  2321. + return true;
  2322. +
  2323. +
  2324. + return (type && TREE_ADDRESSABLE (type));
  2325. +}
  2326. +
  2327. +
  2328. +bool
  2329. +avr32_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
  2330. +{
  2331. + return true;
  2332. +}
  2333. +
  2334. +
  2335. +/*
  2336. + This target hook should return true if an argument at the position indicated
  2337. + by cum should be passed by reference. This predicate is queried after target
  2338. + independent reasons for being passed by reference, such as TREE_ADDRESSABLE (type).
  2339. +
  2340. + If the hook returns true, a copy of that argument is made in memory and a
  2341. + pointer to the argument is passed instead of the argument itself. The pointer
  2342. + is passed in whatever way is appropriate for passing a pointer to that type.
  2343. +*/
  2344. +bool
  2345. +avr32_pass_by_reference (CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,
  2346. + enum machine_mode mode ATTRIBUTE_UNUSED,
  2347. + tree type, bool named ATTRIBUTE_UNUSED)
  2348. +{
  2349. + return (type && (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST));
  2350. +}
  2351. +
  2352. +
  2353. +static int
  2354. +avr32_arg_partial_bytes (CUMULATIVE_ARGS * pcum ATTRIBUTE_UNUSED,
  2355. + enum machine_mode mode ATTRIBUTE_UNUSED,
  2356. + tree type ATTRIBUTE_UNUSED,
  2357. + bool named ATTRIBUTE_UNUSED)
  2358. +{
  2359. + return 0;
  2360. +}
  2361. +
  2362. +
  2363. +struct gcc_target targetm = TARGET_INITIALIZER;
  2364. +
  2365. +/*
  2366. + Table used to convert from register number in the assembler instructions and
  2367. + the register numbers used in gcc.
  2368. +*/
  2369. +const int avr32_function_arg_reglist[] = {
  2370. + INTERNAL_REGNUM (12),
  2371. + INTERNAL_REGNUM (11),
  2372. + INTERNAL_REGNUM (10),
  2373. + INTERNAL_REGNUM (9),
  2374. + INTERNAL_REGNUM (8)
  2375. +};
  2376. +
  2377. +
  2378. +rtx avr32_compare_op0 = NULL_RTX;
  2379. +rtx avr32_compare_op1 = NULL_RTX;
  2380. +rtx avr32_compare_operator = NULL_RTX;
  2381. +rtx avr32_acc_cache = NULL_RTX;
  2382. +/* type of branch to use */
  2383. +enum avr32_cmp_type avr32_branch_type;
  2384. +
  2385. +
  2386. +/*
  2387. + Returns nonzero if it is allowed to store a value of mode mode in hard
  2388. + register number regno.
  2389. +*/
  2390. +int
  2391. +avr32_hard_regno_mode_ok (int regnr, enum machine_mode mode)
  2392. +{
  2393. + switch (mode)
  2394. + {
  2395. + case DImode: /* long long */
  2396. + case DFmode: /* double */
  2397. + case SCmode: /* __complex__ float */
  2398. + case CSImode: /* __complex__ int */
  2399. + if (regnr < 4)
  2400. + { /* long long int not supported in r12, sp, lr or pc. */
  2401. + return 0;
  2402. + }
  2403. + else
  2404. + {
  2405. + /* long long int has to be referred in even registers. */
  2406. + if (regnr % 2)
  2407. + return 0;
  2408. + else
  2409. + return 1;
  2410. + }
  2411. + case CDImode: /* __complex__ long long */
  2412. + case DCmode: /* __complex__ double */
  2413. + case TImode: /* 16 bytes */
  2414. + if (regnr < 7)
  2415. + return 0;
  2416. + else if (regnr % 2)
  2417. + return 0;
  2418. + else
  2419. + return 1;
  2420. + default:
  2421. + return 1;
  2422. + }
  2423. +}
  2424. +
  2425. +
  2426. +int
  2427. +avr32_rnd_operands (rtx add, rtx shift)
  2428. +{
  2429. + if (GET_CODE (shift) == CONST_INT &&
  2430. + GET_CODE (add) == CONST_INT && INTVAL (shift) > 0)
  2431. + {
  2432. + if ((1 << (INTVAL (shift) - 1)) == INTVAL (add))
  2433. + return TRUE;
  2434. + }
  2435. +
  2436. + return FALSE;
  2437. +}
  2438. +
  2439. +
  2440. +int
  2441. +avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, const char *str)
  2442. +{
  2443. + switch (c)
  2444. + {
  2445. + case 'K':
  2446. + case 'I':
  2447. + {
  2448. + HOST_WIDE_INT min_value = 0, max_value = 0;
  2449. + char size_str[3];
  2450. + int const_size;
  2451. +
  2452. + size_str[0] = str[2];
  2453. + size_str[1] = str[3];
  2454. + size_str[2] = '\0';
  2455. + const_size = atoi (size_str);
  2456. +
  2457. + if (TOUPPER (str[1]) == 'U')
  2458. + {
  2459. + min_value = 0;
  2460. + max_value = (1 << const_size) - 1;
  2461. + }
  2462. + else if (TOUPPER (str[1]) == 'S')
  2463. + {
  2464. + min_value = -(1 << (const_size - 1));
  2465. + max_value = (1 << (const_size - 1)) - 1;
  2466. + }
  2467. +
  2468. + if (c == 'I')
  2469. + {
  2470. + value = -value;
  2471. + }
  2472. +
  2473. + if (value >= min_value && value <= max_value)
  2474. + {
  2475. + return 1;
  2476. + }
  2477. + break;
  2478. + }
  2479. + case 'M':
  2480. + return avr32_mask_upper_bits_operand (GEN_INT (value), VOIDmode);
  2481. + case 'J':
  2482. + return avr32_hi16_immediate_operand (GEN_INT (value), VOIDmode);
  2483. + case 'O':
  2484. + return one_bit_set_operand (GEN_INT (value), VOIDmode);
  2485. + case 'N':
  2486. + return one_bit_cleared_operand (GEN_INT (value), VOIDmode);
  2487. + case 'L':
  2488. + /* The lower 16-bits are set. */
  2489. + return ((value & 0xffff) == 0xffff) ;
  2490. + }
  2491. +
  2492. + return 0;
  2493. +}
  2494. +
  2495. +
  2496. +/* Compute mask of registers which needs saving upon function entry. */
  2497. +static unsigned long
  2498. +avr32_compute_save_reg_mask (int push)
  2499. +{
  2500. + unsigned long func_type;
  2501. + unsigned int save_reg_mask = 0;
  2502. + unsigned int reg;
  2503. +
  2504. + func_type = avr32_current_func_type ();
  2505. +
  2506. + if (IS_INTERRUPT (func_type))
  2507. + {
  2508. + unsigned int max_reg = 12;
  2509. +
  2510. + /* Get the banking scheme for the interrupt */
  2511. + switch (func_type)
  2512. + {
  2513. + case AVR32_FT_ISR_FULL:
  2514. + max_reg = 0;
  2515. + break;
  2516. + case AVR32_FT_ISR_HALF:
  2517. + max_reg = 7;
  2518. + break;
  2519. + case AVR32_FT_ISR_NONE:
  2520. + max_reg = 12;
  2521. + break;
  2522. + }
  2523. +
  2524. + /* Interrupt functions must not corrupt any registers, even call
  2525. + clobbered ones. If this is a leaf function we can just examine the
  2526. + registers used by the RTL, but otherwise we have to assume that
  2527. + whatever function is called might clobber anything, and so we have
  2528. + to save all the call-clobbered registers as well. */
  2529. +
  2530. + /* Need not push the registers r8-r12 for AVR32A architectures, as this
  2531. + is automatially done in hardware. We also do not have any shadow
  2532. + registers. */
  2533. + if (TARGET_UARCH_AVR32A)
  2534. + {
  2535. + max_reg = 7;
  2536. + func_type = AVR32_FT_ISR_NONE;
  2537. + }
  2538. +
  2539. + /* All registers which are used and are not shadowed must be saved. */
  2540. + for (reg = 0; reg <= max_reg; reg++)
  2541. + if (df_regs_ever_live_p (INTERNAL_REGNUM (reg))
  2542. + || (!current_function_is_leaf
  2543. + && call_used_regs[INTERNAL_REGNUM (reg)]))
  2544. + save_reg_mask |= (1 << reg);
  2545. +
  2546. + /* Check LR */
  2547. + if ((df_regs_ever_live_p (LR_REGNUM)
  2548. + || !current_function_is_leaf || frame_pointer_needed)
  2549. + /* Only non-shadowed register models */
  2550. + && (func_type == AVR32_FT_ISR_NONE))
  2551. + save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM));
  2552. +
  2553. + /* Make sure that the GOT register is pushed. */
  2554. + if (max_reg >= ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)
  2555. + && crtl->uses_pic_offset_table)
  2556. + save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM));
  2557. +
  2558. + }
  2559. + else
  2560. + {
  2561. + int use_pushm = optimize_size;
  2562. +
  2563. + /* In the normal case we only need to save those registers which are
  2564. + call saved and which are used by this function. */
  2565. + for (reg = 0; reg <= 7; reg++)
  2566. + if (df_regs_ever_live_p (INTERNAL_REGNUM (reg))
  2567. + && !call_used_regs[INTERNAL_REGNUM (reg)])
  2568. + save_reg_mask |= (1 << reg);
  2569. +
  2570. + /* Make sure that the GOT register is pushed. */
  2571. + if (crtl->uses_pic_offset_table)
  2572. + save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM));
  2573. +
  2574. +
  2575. + /* If we optimize for size and do not have anonymous arguments: use
  2576. + pushm/popm always. */
  2577. + if (use_pushm)
  2578. + {
  2579. + if ((save_reg_mask & (1 << 0))
  2580. + || (save_reg_mask & (1 << 1))
  2581. + || (save_reg_mask & (1 << 2)) || (save_reg_mask & (1 << 3)))
  2582. + save_reg_mask |= 0xf;
  2583. +
  2584. + if ((save_reg_mask & (1 << 4))
  2585. + || (save_reg_mask & (1 << 5))
  2586. + || (save_reg_mask & (1 << 6)) || (save_reg_mask & (1 << 7)))
  2587. + save_reg_mask |= 0xf0;
  2588. +
  2589. + if ((save_reg_mask & (1 << 8)) || (save_reg_mask & (1 << 9)))
  2590. + save_reg_mask |= 0x300;
  2591. + }
  2592. +
  2593. +
  2594. + /* Check LR */
  2595. + if ((df_regs_ever_live_p (LR_REGNUM)
  2596. + || !current_function_is_leaf
  2597. + || (optimize_size
  2598. + && save_reg_mask
  2599. + && !crtl->calls_eh_return)
  2600. + || frame_pointer_needed)
  2601. + && !IS_FLASHVAULT (func_type))
  2602. + {
  2603. + if (push
  2604. + /* Never pop LR into PC for functions which
  2605. + calls __builtin_eh_return, since we need to
  2606. + fix the SP after the restoring of the registers
  2607. + and before returning. */
  2608. + || crtl->calls_eh_return)
  2609. + {
  2610. + /* Push/Pop LR */
  2611. + save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM));
  2612. + }
  2613. + else
  2614. + {
  2615. + /* Pop PC */
  2616. + save_reg_mask |= (1 << ASM_REGNUM (PC_REGNUM));
  2617. + }
  2618. + }
  2619. + }
  2620. +
  2621. +
  2622. + /* Save registers so the exception handler can modify them. */
  2623. + if (crtl->calls_eh_return)
  2624. + {
  2625. + unsigned int i;
  2626. +
  2627. + for (i = 0;; i++)
  2628. + {
  2629. + reg = EH_RETURN_DATA_REGNO (i);
  2630. + if (reg == INVALID_REGNUM)
  2631. + break;
  2632. + save_reg_mask |= 1 << ASM_REGNUM (reg);
  2633. + }
  2634. + }
  2635. +
  2636. + return save_reg_mask;
  2637. +}
  2638. +
  2639. +
  2640. +/* Compute total size in bytes of all saved registers. */
  2641. +static int
  2642. +avr32_get_reg_mask_size (int reg_mask)
  2643. +{
  2644. + int reg, size;
  2645. + size = 0;
  2646. +
  2647. + for (reg = 0; reg <= 15; reg++)
  2648. + if (reg_mask & (1 << reg))
  2649. + size += 4;
  2650. +
  2651. + return size;
  2652. +}
  2653. +
  2654. +
  2655. +/* Get a register from one of the registers which are saved onto the stack
  2656. + upon function entry. */
  2657. +static int
  2658. +avr32_get_saved_reg (int save_reg_mask)
  2659. +{
  2660. + unsigned int reg;
  2661. +
  2662. + /* Find the first register which is saved in the saved_reg_mask */
  2663. + for (reg = 0; reg <= 15; reg++)
  2664. + if (save_reg_mask & (1 << reg))
  2665. + return reg;
  2666. +
  2667. + return -1;
  2668. +}
  2669. +
  2670. +
  2671. +/* Return 1 if it is possible to return using a single instruction. */
  2672. +int
  2673. +avr32_use_return_insn (int iscond)
  2674. +{
  2675. + unsigned int func_type = avr32_current_func_type ();
  2676. + unsigned long saved_int_regs;
  2677. +
  2678. + /* Never use a return instruction before reload has run. */
  2679. + if (!reload_completed)
  2680. + return 0;
  2681. +
  2682. + /* Must adjust the stack for vararg functions. */
  2683. + if (crtl->args.info.uses_anonymous_args)
  2684. + return 0;
  2685. +
  2686. + /* If there a stack adjstment. */
  2687. + if (get_frame_size ())
  2688. + return 0;
  2689. +
  2690. + saved_int_regs = avr32_compute_save_reg_mask (TRUE);
  2691. +
  2692. + /* Conditional returns can not be performed in one instruction if we need
  2693. + to restore registers from the stack */
  2694. + if (iscond && saved_int_regs)
  2695. + return 0;
  2696. +
  2697. + /* Conditional return can not be used for interrupt handlers. */
  2698. + if (iscond && IS_INTERRUPT (func_type))
  2699. + return 0;
  2700. +
  2701. + /* For interrupt handlers which needs to pop registers */
  2702. + if (saved_int_regs && IS_INTERRUPT (func_type))
  2703. + return 0;
  2704. +
  2705. +
  2706. + /* If there are saved registers but the LR isn't saved, then we need two
  2707. + instructions for the return. */
  2708. + if (saved_int_regs && !(saved_int_regs & (1 << ASM_REGNUM (LR_REGNUM))))
  2709. + return 0;
  2710. +
  2711. +
  2712. + return 1;
  2713. +}
  2714. +
  2715. +
  2716. +/* Generate some function prologue info in the assembly file. */
  2717. +void
  2718. +avr32_target_asm_function_prologue (FILE * f, HOST_WIDE_INT frame_size)
  2719. +{
  2720. + unsigned long func_type = avr32_current_func_type ();
  2721. +
  2722. + if (IS_NAKED (func_type))
  2723. + fprintf (f,
  2724. + "\t# Function is naked: Prologue and epilogue provided by programmer\n");
  2725. +
  2726. + if (IS_FLASHVAULT (func_type))
  2727. + {
  2728. + fprintf(f,
  2729. + "\t.ident \"flashvault\"\n\t# Function is defined with flashvault attribute.\n");
  2730. + }
  2731. +
  2732. + if (IS_FLASHVAULT_IMPL (func_type))
  2733. + {
  2734. + fprintf(f,
  2735. + "\t.ident \"flashvault\"\n\t# Function is defined with flashvault_impl attribute.\n");
  2736. +
  2737. + /* Save information on flashvault function declaration. */
  2738. + tree fv_attribute = lookup_attribute ("flashvault_impl", DECL_ATTRIBUTES(current_function_decl));
  2739. + if (fv_attribute != NULL_TREE)
  2740. + {
  2741. + tree vector_tree = TREE_VALUE(fv_attribute);
  2742. + if (vector_tree != NULL_TREE)
  2743. + {
  2744. + unsigned int vector_num;
  2745. + const char * name;
  2746. +
  2747. + vector_num = (unsigned int) TREE_INT_CST_LOW (TREE_VALUE (vector_tree));
  2748. +
  2749. + name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
  2750. +
  2751. + flashvault_decl_list_add (vector_num, name);
  2752. + }
  2753. + }
  2754. + }
  2755. +
  2756. + if (IS_INTERRUPT (func_type))
  2757. + {
  2758. + switch (func_type)
  2759. + {
  2760. + case AVR32_FT_ISR_FULL:
  2761. + fprintf (f,
  2762. + "\t# Interrupt Function: Fully shadowed register file\n");
  2763. + break;
  2764. + case AVR32_FT_ISR_HALF:
  2765. + fprintf (f,
  2766. + "\t# Interrupt Function: Half shadowed register file\n");
  2767. + break;
  2768. + default:
  2769. + case AVR32_FT_ISR_NONE:
  2770. + fprintf (f, "\t# Interrupt Function: No shadowed register file\n");
  2771. + break;
  2772. + }
  2773. + }
  2774. +
  2775. +
  2776. + fprintf (f, "\t# args = %i, frame = %li, pretend = %i\n",
  2777. + crtl->args.size, frame_size,
  2778. + crtl->args.pretend_args_size);
  2779. +
  2780. + fprintf (f, "\t# frame_needed = %i, leaf_function = %i\n",
  2781. + frame_pointer_needed, current_function_is_leaf);
  2782. +
  2783. + fprintf (f, "\t# uses_anonymous_args = %i\n",
  2784. + crtl->args.info.uses_anonymous_args);
  2785. +
  2786. + if (crtl->calls_eh_return)
  2787. + fprintf (f, "\t# Calls __builtin_eh_return.\n");
  2788. +
  2789. +}
  2790. +
  2791. +
  2792. +/* Generate and emit an insn that we will recognize as a pushm or stm.
  2793. + Unfortunately, since this insn does not reflect very well the actual
  2794. + semantics of the operation, we need to annotate the insn for the benefit
  2795. + of DWARF2 frame unwind information. */
  2796. +
  2797. +int avr32_convert_to_reglist16 (int reglist8_vect);
  2798. +
  2799. +static rtx
  2800. +emit_multi_reg_push (int reglist, int usePUSHM)
  2801. +{
  2802. + rtx insn;
  2803. + rtx dwarf;
  2804. + rtx tmp;
  2805. + rtx reg;
  2806. + int i;
  2807. + int nr_regs;
  2808. + int index = 0;
  2809. +
  2810. + if (usePUSHM)
  2811. + {
  2812. + insn = emit_insn (gen_pushm (gen_rtx_CONST_INT (SImode, reglist)));
  2813. + reglist = avr32_convert_to_reglist16 (reglist);
  2814. + }
  2815. + else
  2816. + {
  2817. + insn = emit_insn (gen_stm (stack_pointer_rtx,
  2818. + gen_rtx_CONST_INT (SImode, reglist),
  2819. + gen_rtx_CONST_INT (SImode, 1)));
  2820. + }
  2821. +
  2822. + nr_regs = avr32_get_reg_mask_size (reglist) / 4;
  2823. + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nr_regs + 1));
  2824. +
  2825. + for (i = 15; i >= 0; i--)
  2826. + {
  2827. + if (reglist & (1 << i))
  2828. + {
  2829. + reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (i));
  2830. + tmp = gen_rtx_SET (VOIDmode,
  2831. + gen_rtx_MEM (SImode,
  2832. + plus_constant (stack_pointer_rtx,
  2833. + 4 * index)), reg);
  2834. + RTX_FRAME_RELATED_P (tmp) = 1;
  2835. + XVECEXP (dwarf, 0, 1 + index++) = tmp;
  2836. + }
  2837. + }
  2838. +
  2839. + tmp = gen_rtx_SET (SImode,
  2840. + stack_pointer_rtx,
  2841. + gen_rtx_PLUS (SImode,
  2842. + stack_pointer_rtx,
  2843. + GEN_INT (-4 * nr_regs)));
  2844. + RTX_FRAME_RELATED_P (tmp) = 1;
  2845. + XVECEXP (dwarf, 0, 0) = tmp;
  2846. + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
  2847. + REG_NOTES (insn));
  2848. + return insn;
  2849. +}
  2850. +
  2851. +rtx
  2852. +avr32_gen_load_multiple (rtx * regs, int count, rtx from,
  2853. + int write_back, int in_struct_p, int scalar_p)
  2854. +{
  2855. +
  2856. + rtx result;
  2857. + int i = 0, j;
  2858. +
  2859. + result =
  2860. + gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + (write_back ? 1 : 0)));
  2861. +
  2862. + if (write_back)
  2863. + {
  2864. + XVECEXP (result, 0, 0)
  2865. + = gen_rtx_SET (GET_MODE (from), from,
  2866. + plus_constant (from, count * 4));
  2867. + i = 1;
  2868. + count++;
  2869. + }
  2870. +
  2871. +
  2872. + for (j = 0; i < count; i++, j++)
  2873. + {
  2874. + rtx unspec;
  2875. + rtx mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4));
  2876. + MEM_IN_STRUCT_P (mem) = in_struct_p;
  2877. + MEM_SCALAR_P (mem) = scalar_p;
  2878. + unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, mem), UNSPEC_LDM);
  2879. + XVECEXP (result, 0, i) = gen_rtx_SET (VOIDmode, regs[j], unspec);
  2880. + }
  2881. +
  2882. + return result;
  2883. +}
  2884. +
  2885. +
  2886. +rtx
  2887. +avr32_gen_store_multiple (rtx * regs, int count, rtx to,
  2888. + int in_struct_p, int scalar_p)
  2889. +{
  2890. + rtx result;
  2891. + int i = 0, j;
  2892. +
  2893. + result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
  2894. +
  2895. + for (j = 0; i < count; i++, j++)
  2896. + {
  2897. + rtx mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4));
  2898. + MEM_IN_STRUCT_P (mem) = in_struct_p;
  2899. + MEM_SCALAR_P (mem) = scalar_p;
  2900. + XVECEXP (result, 0, i)
  2901. + = gen_rtx_SET (VOIDmode, mem,
  2902. + gen_rtx_UNSPEC (VOIDmode,
  2903. + gen_rtvec (1, regs[j]),
  2904. + UNSPEC_STORE_MULTIPLE));
  2905. + }
  2906. +
  2907. + return result;
  2908. +}
  2909. +
  2910. +
  2911. +/* Move a block of memory if it is word aligned or we support unaligned
  2912. + word memory accesses. The size must be maximum 64 bytes. */
  2913. +int
  2914. +avr32_gen_movmemsi (rtx * operands)
  2915. +{
  2916. + HOST_WIDE_INT bytes_to_go;
  2917. + rtx src, dst;
  2918. + rtx st_src, st_dst;
  2919. + int src_offset = 0, dst_offset = 0;
  2920. + int block_size;
  2921. + int dst_in_struct_p, src_in_struct_p;
  2922. + int dst_scalar_p, src_scalar_p;
  2923. + int unaligned;
  2924. +
  2925. + if (GET_CODE (operands[2]) != CONST_INT
  2926. + || GET_CODE (operands[3]) != CONST_INT
  2927. + || INTVAL (operands[2]) > 64
  2928. + || ((INTVAL (operands[3]) & 3) && !TARGET_UNALIGNED_WORD))
  2929. + return 0;
  2930. +
  2931. + unaligned = (INTVAL (operands[3]) & 3) != 0;
  2932. +
  2933. + block_size = 4;
  2934. +
  2935. + st_dst = XEXP (operands[0], 0);
  2936. + st_src = XEXP (operands[1], 0);
  2937. +
  2938. + dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
  2939. + dst_scalar_p = MEM_SCALAR_P (operands[0]);
  2940. + src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
  2941. + src_scalar_p = MEM_SCALAR_P (operands[1]);
  2942. +
  2943. + dst = copy_to_mode_reg (SImode, st_dst);
  2944. + src = copy_to_mode_reg (SImode, st_src);
  2945. +
  2946. + bytes_to_go = INTVAL (operands[2]);
  2947. +
  2948. + while (bytes_to_go)
  2949. + {
  2950. + enum machine_mode move_mode;
  2951. + /* (Seems to be a problem with reloads for the movti pattern so this is
  2952. + disabled until that problem is resolved)
  2953. + UPDATE: Problem seems to be solved now.... */
  2954. + if (bytes_to_go >= GET_MODE_SIZE (TImode) && !unaligned
  2955. + /* Do not emit ldm/stm for UC3 as ld.d/st.d is more optimal. */
  2956. + && !TARGET_ARCH_UC)
  2957. + move_mode = TImode;
  2958. + else if ((bytes_to_go >= GET_MODE_SIZE (DImode)) && !unaligned)
  2959. + move_mode = DImode;
  2960. + else if (bytes_to_go >= GET_MODE_SIZE (SImode))
  2961. + move_mode = SImode;
  2962. + else
  2963. + move_mode = QImode;
  2964. +
  2965. + {
  2966. + rtx src_mem;
  2967. + rtx dst_mem = gen_rtx_MEM (move_mode,
  2968. + gen_rtx_PLUS (SImode, dst,
  2969. + GEN_INT (dst_offset)));
  2970. + dst_offset += GET_MODE_SIZE (move_mode);
  2971. + if ( 0 /* This causes an error in GCC. Think there is
  2972. + something wrong in the gcse pass which causes REQ_EQUIV notes
  2973. + to be wrong so disabling it for now. */
  2974. + && move_mode == TImode
  2975. + && INTVAL (operands[2]) > GET_MODE_SIZE (TImode) )
  2976. + {
  2977. + src_mem = gen_rtx_MEM (move_mode,
  2978. + gen_rtx_POST_INC (SImode, src));
  2979. + }
  2980. + else
  2981. + {
  2982. + src_mem = gen_rtx_MEM (move_mode,
  2983. + gen_rtx_PLUS (SImode, src,
  2984. + GEN_INT (src_offset)));
  2985. + src_offset += GET_MODE_SIZE (move_mode);
  2986. + }
  2987. +
  2988. + bytes_to_go -= GET_MODE_SIZE (move_mode);
  2989. +
  2990. + MEM_IN_STRUCT_P (dst_mem) = dst_in_struct_p;
  2991. + MEM_SCALAR_P (dst_mem) = dst_scalar_p;
  2992. +
  2993. + MEM_IN_STRUCT_P (src_mem) = src_in_struct_p;
  2994. + MEM_SCALAR_P (src_mem) = src_scalar_p;
  2995. + emit_move_insn (dst_mem, src_mem);
  2996. +
  2997. + }
  2998. + }
  2999. +
  3000. + return 1;
  3001. +}
  3002. +
  3003. +
  3004. +/* Expand the prologue instruction. */
  3005. +void
  3006. +avr32_expand_prologue (void)
  3007. +{
  3008. + rtx insn, dwarf;
  3009. + unsigned long saved_reg_mask;
  3010. + int reglist8 = 0;
  3011. +
  3012. + /* Naked functions do not have a prologue. */
  3013. + if (IS_NAKED (avr32_current_func_type ()))
  3014. + return;
  3015. +
  3016. + saved_reg_mask = avr32_compute_save_reg_mask (TRUE);
  3017. +
  3018. + if (saved_reg_mask)
  3019. + {
  3020. + /* Must push used registers. */
  3021. +
  3022. + /* Should we use POPM or LDM? */
  3023. + int usePUSHM = TRUE;
  3024. + reglist8 = 0;
  3025. + if (((saved_reg_mask & (1 << 0)) ||
  3026. + (saved_reg_mask & (1 << 1)) ||
  3027. + (saved_reg_mask & (1 << 2)) || (saved_reg_mask & (1 << 3))))
  3028. + {
  3029. + /* One of R0-R3 should at least be pushed. */
  3030. + if (((saved_reg_mask & (1 << 0)) &&
  3031. + (saved_reg_mask & (1 << 1)) &&
  3032. + (saved_reg_mask & (1 << 2)) && (saved_reg_mask & (1 << 3))))
  3033. + {
  3034. + /* All should be pushed. */
  3035. + reglist8 |= 0x01;
  3036. + }
  3037. + else
  3038. + {
  3039. + usePUSHM = FALSE;
  3040. + }
  3041. + }
  3042. +
  3043. + if (((saved_reg_mask & (1 << 4)) ||
  3044. + (saved_reg_mask & (1 << 5)) ||
  3045. + (saved_reg_mask & (1 << 6)) || (saved_reg_mask & (1 << 7))))
  3046. + {
  3047. + /* One of R4-R7 should at least be pushed */
  3048. + if (((saved_reg_mask & (1 << 4)) &&
  3049. + (saved_reg_mask & (1 << 5)) &&
  3050. + (saved_reg_mask & (1 << 6)) && (saved_reg_mask & (1 << 7))))
  3051. + {
  3052. + if (usePUSHM)
  3053. + /* All should be pushed */
  3054. + reglist8 |= 0x02;
  3055. + }
  3056. + else
  3057. + {
  3058. + usePUSHM = FALSE;
  3059. + }
  3060. + }
  3061. +
  3062. + if (((saved_reg_mask & (1 << 8)) || (saved_reg_mask & (1 << 9))))
  3063. + {
  3064. + /* One of R8-R9 should at least be pushed. */
  3065. + if (((saved_reg_mask & (1 << 8)) && (saved_reg_mask & (1 << 9))))
  3066. + {
  3067. + if (usePUSHM)
  3068. + /* All should be pushed. */
  3069. + reglist8 |= 0x04;
  3070. + }
  3071. + else
  3072. + {
  3073. + usePUSHM = FALSE;
  3074. + }
  3075. + }
  3076. +
  3077. + if (saved_reg_mask & (1 << 10))
  3078. + reglist8 |= 0x08;
  3079. +
  3080. + if (saved_reg_mask & (1 << 11))
  3081. + reglist8 |= 0x10;
  3082. +
  3083. + if (saved_reg_mask & (1 << 12))
  3084. + reglist8 |= 0x20;
  3085. +
  3086. + if ((saved_reg_mask & (1 << ASM_REGNUM (LR_REGNUM)))
  3087. + && !IS_FLASHVAULT (avr32_current_func_type ()))
  3088. + {
  3089. + /* Push LR */
  3090. + reglist8 |= 0x40;
  3091. + }
  3092. +
  3093. + if (usePUSHM)
  3094. + {
  3095. + insn = emit_multi_reg_push (reglist8, TRUE);
  3096. + }
  3097. + else
  3098. + {
  3099. + insn = emit_multi_reg_push (saved_reg_mask, FALSE);
  3100. + }
  3101. + RTX_FRAME_RELATED_P (insn) = 1;
  3102. +
  3103. + /* Prevent this instruction from being scheduled after any other
  3104. + instructions. */
  3105. + emit_insn (gen_blockage ());
  3106. + }
  3107. +
  3108. + /* Set frame pointer */
  3109. + if (frame_pointer_needed)
  3110. + {
  3111. + insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
  3112. + RTX_FRAME_RELATED_P (insn) = 1;
  3113. + }
  3114. +
  3115. + if (get_frame_size () > 0)
  3116. + {
  3117. + if (avr32_const_ok_for_constraint_p (get_frame_size (), 'K', "Ks21"))
  3118. + {
  3119. + insn = emit_insn (gen_rtx_SET (SImode,
  3120. + stack_pointer_rtx,
  3121. + gen_rtx_PLUS (SImode,
  3122. + stack_pointer_rtx,
  3123. + gen_rtx_CONST_INT
  3124. + (SImode,
  3125. + -get_frame_size
  3126. + ()))));
  3127. + RTX_FRAME_RELATED_P (insn) = 1;
  3128. + }
  3129. + else
  3130. + {
  3131. + /* Immediate is larger than k21 We must either check if we can use
  3132. + one of the pushed reegisters as temporary storage or we must
  3133. + make us a temp register by pushing a register to the stack. */
  3134. + rtx temp_reg, const_pool_entry, insn;
  3135. + if (saved_reg_mask)
  3136. + {
  3137. + temp_reg =
  3138. + gen_rtx_REG (SImode,
  3139. + INTERNAL_REGNUM (avr32_get_saved_reg
  3140. + (saved_reg_mask)));
  3141. + }
  3142. + else
  3143. + {
  3144. + temp_reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (7));
  3145. + emit_move_insn (gen_rtx_MEM
  3146. + (SImode,
  3147. + gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)),
  3148. + temp_reg);
  3149. + }
  3150. +
  3151. + const_pool_entry =
  3152. + force_const_mem (SImode,
  3153. + gen_rtx_CONST_INT (SImode, get_frame_size ()));
  3154. + emit_move_insn (temp_reg, const_pool_entry);
  3155. +
  3156. + insn = emit_insn (gen_rtx_SET (SImode,
  3157. + stack_pointer_rtx,
  3158. + gen_rtx_MINUS (SImode,
  3159. + stack_pointer_rtx,
  3160. + temp_reg)));
  3161. +
  3162. + dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
  3163. + gen_rtx_PLUS (SImode, stack_pointer_rtx,
  3164. + GEN_INT (-get_frame_size ())));
  3165. + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
  3166. + dwarf, REG_NOTES (insn));
  3167. + RTX_FRAME_RELATED_P (insn) = 1;
  3168. +
  3169. + if (!saved_reg_mask)
  3170. + {
  3171. + insn =
  3172. + emit_move_insn (temp_reg,
  3173. + gen_rtx_MEM (SImode,
  3174. + gen_rtx_POST_INC (SImode,
  3175. + gen_rtx_REG
  3176. + (SImode,
  3177. + 13))));
  3178. + }
  3179. +
  3180. + /* Mark the temp register as dead */
  3181. + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, temp_reg,
  3182. + REG_NOTES (insn));
  3183. +
  3184. +
  3185. + }
  3186. +
  3187. + /* Prevent the the stack adjustment to be scheduled after any
  3188. + instructions using the frame pointer. */
  3189. + emit_insn (gen_blockage ());
  3190. + }
  3191. +
  3192. + /* Load GOT */
  3193. + if (flag_pic)
  3194. + {
  3195. + avr32_load_pic_register ();
  3196. +
  3197. + /* gcc does not know that load or call instructions might use the pic
  3198. + register so it might schedule these instructions before the loading
  3199. + of the pic register. To avoid this emit a barrier for now. TODO!
  3200. + Find out a better way to let gcc know which instructions might use
  3201. + the pic register. */
  3202. + emit_insn (gen_blockage ());
  3203. + }
  3204. + return;
  3205. +}
  3206. +
  3207. +
  3208. +void
  3209. +avr32_set_return_address (rtx source, rtx scratch)
  3210. +{
  3211. + rtx addr;
  3212. + unsigned long saved_regs;
  3213. +
  3214. + saved_regs = avr32_compute_save_reg_mask (TRUE);
  3215. +
  3216. + if (!(saved_regs & (1 << ASM_REGNUM (LR_REGNUM))))
  3217. + emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
  3218. + else
  3219. + {
  3220. + if (frame_pointer_needed)
  3221. + addr = gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM);
  3222. + else
  3223. + if (avr32_const_ok_for_constraint_p (get_frame_size (), 'K', "Ks16"))
  3224. + {
  3225. + addr = plus_constant (stack_pointer_rtx, get_frame_size ());
  3226. + }
  3227. + else
  3228. + {
  3229. + emit_insn (gen_movsi (scratch, GEN_INT (get_frame_size ())));
  3230. + addr = scratch;
  3231. + }
  3232. + emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
  3233. + }
  3234. +}
  3235. +
  3236. +
  3237. +/* Return the length of INSN. LENGTH is the initial length computed by
  3238. + attributes in the machine-description file. */
  3239. +int
  3240. +avr32_adjust_insn_length (rtx insn ATTRIBUTE_UNUSED,
  3241. + int length ATTRIBUTE_UNUSED)
  3242. +{
  3243. + return length;
  3244. +}
  3245. +
  3246. +
  3247. +void
  3248. +avr32_output_return_instruction (int single_ret_inst ATTRIBUTE_UNUSED,
  3249. + int iscond ATTRIBUTE_UNUSED,
  3250. + rtx cond ATTRIBUTE_UNUSED, rtx r12_imm)
  3251. +{
  3252. +
  3253. + unsigned long saved_reg_mask;
  3254. + int insert_ret = TRUE;
  3255. + int reglist8 = 0;
  3256. + int stack_adjustment = get_frame_size ();
  3257. + unsigned int func_type = avr32_current_func_type ();
  3258. + FILE *f = asm_out_file;
  3259. +
  3260. + /* Naked functions does not have an epilogue */
  3261. + if (IS_NAKED (func_type))
  3262. + return;
  3263. +
  3264. + saved_reg_mask = avr32_compute_save_reg_mask (FALSE);
  3265. +
  3266. + /* Reset frame pointer */
  3267. + if (stack_adjustment > 0)
  3268. + {
  3269. + if (avr32_const_ok_for_constraint_p (stack_adjustment, 'I', "Is21"))
  3270. + {
  3271. + fprintf (f, "\tsub\tsp, %i # Reset Frame Pointer\n",
  3272. + -stack_adjustment);
  3273. + }
  3274. + else
  3275. + {
  3276. + /* TODO! Is it safe to use r8 as scratch?? */
  3277. + fprintf (f, "\tmov\tr8, lo(%i) # Reset Frame Pointer\n",
  3278. + -stack_adjustment);
  3279. + fprintf (f, "\torh\tr8, hi(%i) # Reset Frame Pointer\n",
  3280. + -stack_adjustment);
  3281. + fprintf (f, "\tadd\tsp, r8 # Reset Frame Pointer\n");
  3282. + }
  3283. + }
  3284. +
  3285. + if (saved_reg_mask)
  3286. + {
  3287. + /* Must pop used registers */
  3288. +
  3289. + /* Should we use POPM or LDM? */
  3290. + int usePOPM = TRUE;
  3291. + if (((saved_reg_mask & (1 << 0)) ||
  3292. + (saved_reg_mask & (1 << 1)) ||
  3293. + (saved_reg_mask & (1 << 2)) || (saved_reg_mask & (1 << 3))))
  3294. + {
  3295. + /* One of R0-R3 should at least be popped */
  3296. + if (((saved_reg_mask & (1 << 0)) &&
  3297. + (saved_reg_mask & (1 << 1)) &&
  3298. + (saved_reg_mask & (1 << 2)) && (saved_reg_mask & (1 << 3))))
  3299. + {
  3300. + /* All should be popped */
  3301. + reglist8 |= 0x01;
  3302. + }
  3303. + else
  3304. + {
  3305. + usePOPM = FALSE;
  3306. + }
  3307. + }
  3308. +
  3309. + if (((saved_reg_mask & (1 << 4)) ||
  3310. + (saved_reg_mask & (1 << 5)) ||
  3311. + (saved_reg_mask & (1 << 6)) || (saved_reg_mask & (1 << 7))))
  3312. + {
  3313. + /* One of R0-R3 should at least be popped */
  3314. + if (((saved_reg_mask & (1 << 4)) &&
  3315. + (saved_reg_mask & (1 << 5)) &&
  3316. + (saved_reg_mask & (1 << 6)) && (saved_reg_mask & (1 << 7))))
  3317. + {
  3318. + if (usePOPM)
  3319. + /* All should be popped */
  3320. + reglist8 |= 0x02;
  3321. + }
  3322. + else
  3323. + {
  3324. + usePOPM = FALSE;
  3325. + }
  3326. + }
  3327. +
  3328. + if (((saved_reg_mask & (1 << 8)) || (saved_reg_mask & (1 << 9))))
  3329. + {
  3330. + /* One of R8-R9 should at least be pushed */
  3331. + if (((saved_reg_mask & (1 << 8)) && (saved_reg_mask & (1 << 9))))
  3332. + {
  3333. + if (usePOPM)
  3334. + /* All should be pushed */
  3335. + reglist8 |= 0x04;
  3336. + }
  3337. + else
  3338. + {
  3339. + usePOPM = FALSE;
  3340. + }
  3341. + }
  3342. +
  3343. + if (saved_reg_mask & (1 << 10))
  3344. + reglist8 |= 0x08;
  3345. +
  3346. + if (saved_reg_mask & (1 << 11))
  3347. + reglist8 |= 0x10;
  3348. +
  3349. + if (saved_reg_mask & (1 << 12))
  3350. + reglist8 |= 0x20;
  3351. +
  3352. + if (saved_reg_mask & (1 << ASM_REGNUM (LR_REGNUM)))
  3353. + /* Pop LR */
  3354. + reglist8 |= 0x40;
  3355. +
  3356. + if ((saved_reg_mask & (1 << ASM_REGNUM (PC_REGNUM)))
  3357. + && !IS_FLASHVAULT_IMPL (func_type))
  3358. + /* Pop LR into PC. */
  3359. + reglist8 |= 0x80;
  3360. +
  3361. + if (usePOPM)
  3362. + {
  3363. + char reglist[64]; /* 64 bytes should be enough... */
  3364. + avr32_make_reglist8 (reglist8, (char *) reglist);
  3365. +
  3366. + if (reglist8 & 0x80)
  3367. + /* This instruction is also a return */
  3368. + insert_ret = FALSE;
  3369. +
  3370. + if (r12_imm && !insert_ret)
  3371. + fprintf (f, "\tpopm\t%s, r12=%li\n", reglist, INTVAL (r12_imm));
  3372. + else
  3373. + fprintf (f, "\tpopm\t%s\n", reglist);
  3374. +
  3375. + }
  3376. + else
  3377. + {
  3378. + char reglist[64]; /* 64 bytes should be enough... */
  3379. + avr32_make_reglist16 (saved_reg_mask, (char *) reglist);
  3380. + if (saved_reg_mask & (1 << ASM_REGNUM (PC_REGNUM)))
  3381. + /* This instruction is also a return */
  3382. + insert_ret = FALSE;
  3383. +
  3384. + if (r12_imm && !insert_ret)
  3385. + fprintf (f, "\tldm\tsp++, %s, r12=%li\n", reglist,
  3386. + INTVAL (r12_imm));
  3387. + else
  3388. + fprintf (f, "\tldm\tsp++, %s\n", reglist);
  3389. +
  3390. + }
  3391. +
  3392. + }
  3393. +
  3394. + /* Stack adjustment for exception handler. */
  3395. + if (crtl->calls_eh_return)
  3396. + fprintf (f, "\tadd\tsp, r%d\n", ASM_REGNUM (EH_RETURN_STACKADJ_REGNO));
  3397. +
  3398. +
  3399. + if (IS_INTERRUPT (func_type))
  3400. + {
  3401. + fprintf (f, "\trete\n");
  3402. + }
  3403. + else if (IS_FLASHVAULT (func_type))
  3404. + {
  3405. + /* Normal return from Secure System call, increment SS_RAR before
  3406. + returning. Use R8 as scratch. */
  3407. + fprintf (f,
  3408. + "\t# Normal return from sscall.\n"
  3409. + "\t# Increment SS_RAR before returning.\n"
  3410. + "\t# Use R8 as scratch.\n"
  3411. + "\tmfsr\tr8, 440\n"
  3412. + "\tsub\tr8, -2\n"
  3413. + "\tmtsr\t440, r8\n"
  3414. + "\tretss\n");
  3415. + }
  3416. + else if (insert_ret)
  3417. + {
  3418. + if (r12_imm)
  3419. + fprintf (f, "\tretal\t%li\n", INTVAL (r12_imm));
  3420. + else
  3421. + fprintf (f, "\tretal\tr12\n");
  3422. + }
  3423. +}
  3424. +
  3425. +void
  3426. +avr32_make_reglist16 (int reglist16_vect, char *reglist16_string)
  3427. +{
  3428. + int i;
  3429. + bool first_reg = true;
  3430. + /* Make sure reglist16_string is empty. */
  3431. + reglist16_string[0] = '\0';
  3432. +
  3433. + for (i = 0; i < 16; ++i)
  3434. + {
  3435. + if (reglist16_vect & (1 << i))
  3436. + {
  3437. + first_reg == true ? first_reg = false : strcat(reglist16_string,", ");
  3438. + strcat (reglist16_string, reg_names[INTERNAL_REGNUM (i)]);
  3439. + }
  3440. + }
  3441. +}
  3442. +
  3443. +int
  3444. +avr32_convert_to_reglist16 (int reglist8_vect)
  3445. +{
  3446. + int reglist16_vect = 0;
  3447. + if (reglist8_vect & 0x1)
  3448. + reglist16_vect |= 0xF;
  3449. + if (reglist8_vect & 0x2)
  3450. + reglist16_vect |= 0xF0;
  3451. + if (reglist8_vect & 0x4)
  3452. + reglist16_vect |= 0x300;
  3453. + if (reglist8_vect & 0x8)
  3454. + reglist16_vect |= 0x400;
  3455. + if (reglist8_vect & 0x10)
  3456. + reglist16_vect |= 0x800;
  3457. + if (reglist8_vect & 0x20)
  3458. + reglist16_vect |= 0x1000;
  3459. + if (reglist8_vect & 0x40)
  3460. + reglist16_vect |= 0x4000;
  3461. + if (reglist8_vect & 0x80)
  3462. + reglist16_vect |= 0x8000;
  3463. +
  3464. + return reglist16_vect;
  3465. +}
  3466. +
  3467. +void
  3468. +avr32_make_reglist8 (int reglist8_vect, char *reglist8_string)
  3469. +{
  3470. + /* Make sure reglist8_string is empty. */
  3471. + reglist8_string[0] = '\0';
  3472. +
  3473. + if (reglist8_vect & 0x1)
  3474. + strcpy (reglist8_string, "r0-r3");
  3475. + if (reglist8_vect & 0x2)
  3476. + strlen (reglist8_string) ? strcat (reglist8_string, ", r4-r7") :
  3477. + strcpy (reglist8_string, "r4-r7");
  3478. + if (reglist8_vect & 0x4)
  3479. + strlen (reglist8_string) ? strcat (reglist8_string, ", r8-r9") :
  3480. + strcpy (reglist8_string, "r8-r9");
  3481. + if (reglist8_vect & 0x8)
  3482. + strlen (reglist8_string) ? strcat (reglist8_string, ", r10") :
  3483. + strcpy (reglist8_string, "r10");
  3484. + if (reglist8_vect & 0x10)
  3485. + strlen (reglist8_string) ? strcat (reglist8_string, ", r11") :
  3486. + strcpy (reglist8_string, "r11");
  3487. + if (reglist8_vect & 0x20)
  3488. + strlen (reglist8_string) ? strcat (reglist8_string, ", r12") :
  3489. + strcpy (reglist8_string, "r12");
  3490. + if (reglist8_vect & 0x40)
  3491. + strlen (reglist8_string) ? strcat (reglist8_string, ", lr") :
  3492. + strcpy (reglist8_string, "lr");
  3493. + if (reglist8_vect & 0x80)
  3494. + strlen (reglist8_string) ? strcat (reglist8_string, ", pc") :
  3495. + strcpy (reglist8_string, "pc");
  3496. +}
  3497. +
  3498. +
  3499. +int
  3500. +avr32_eh_return_data_regno (int n)
  3501. +{
  3502. + if (n >= 0 && n <= 3)
  3503. + return 8 + n;
  3504. + else
  3505. + return INVALID_REGNUM;
  3506. +}
  3507. +
  3508. +
  3509. +/* Compute the distance from register FROM to register TO.
  3510. + These can be the arg pointer, the frame pointer or
  3511. + the stack pointer.
  3512. + Typical stack layout looks like this:
  3513. +
  3514. + old stack pointer -> | |
  3515. + ----
  3516. + | | \
  3517. + | | saved arguments for
  3518. + | | vararg functions
  3519. + arg_pointer -> | | /
  3520. + --
  3521. + | | \
  3522. + | | call saved
  3523. + | | registers
  3524. + | | /
  3525. + frame ptr -> --
  3526. + | | \
  3527. + | | local
  3528. + | | variables
  3529. + stack ptr --> | | /
  3530. + --
  3531. + | | \
  3532. + | | outgoing
  3533. + | | arguments
  3534. + | | /
  3535. + --
  3536. +
  3537. + For a given funciton some or all of these stack compomnents
  3538. + may not be needed, giving rise to the possibility of
  3539. + eliminating some of the registers.
  3540. +
  3541. + The values returned by this function must reflect the behaviour
  3542. + of avr32_expand_prologue() and avr32_compute_save_reg_mask().
  3543. +
  3544. + The sign of the number returned reflects the direction of stack
  3545. + growth, so the values are positive for all eliminations except
  3546. + from the soft frame pointer to the hard frame pointer. */
  3547. +int
  3548. +avr32_initial_elimination_offset (int from, int to)
  3549. +{
  3550. + int i;
  3551. + int call_saved_regs = 0;
  3552. + unsigned long saved_reg_mask;
  3553. + unsigned int local_vars = get_frame_size ();
  3554. +
  3555. + saved_reg_mask = avr32_compute_save_reg_mask (TRUE);
  3556. +
  3557. + for (i = 0; i < 16; ++i)
  3558. + {
  3559. + if (saved_reg_mask & (1 << i))
  3560. + call_saved_regs += 4;
  3561. + }
  3562. +
  3563. + switch (from)
  3564. + {
  3565. + case ARG_POINTER_REGNUM:
  3566. + switch (to)
  3567. + {
  3568. + case STACK_POINTER_REGNUM:
  3569. + return call_saved_regs + local_vars;
  3570. + case FRAME_POINTER_REGNUM:
  3571. + return call_saved_regs;
  3572. + default:
  3573. + abort ();
  3574. + }
  3575. + case FRAME_POINTER_REGNUM:
  3576. + switch (to)
  3577. + {
  3578. + case STACK_POINTER_REGNUM:
  3579. + return local_vars;
  3580. + default:
  3581. + abort ();
  3582. + }
  3583. + default:
  3584. + abort ();
  3585. + }
  3586. +}
  3587. +
  3588. +
  3589. +/*
  3590. + Returns a rtx used when passing the next argument to a function.
  3591. + avr32_init_cumulative_args() and avr32_function_arg_advance() sets which
  3592. + register to use.
  3593. +*/
  3594. +rtx
  3595. +avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode,
  3596. + tree type, int named)
  3597. +{
  3598. + int index = -1;
  3599. + //unsigned long func_type = avr32_current_func_type ();
  3600. + //int last_reg_index = (IS_FLASHVAULT(func_type) || IS_FLASHVAULT_IMPL(func_type) || cum->flashvault_func ? LAST_CUM_REG_INDEX - 1 : LAST_CUM_REG_INDEX);
  3601. + int last_reg_index = (cum->flashvault_func ? LAST_CUM_REG_INDEX - 1 : LAST_CUM_REG_INDEX);
  3602. +
  3603. + HOST_WIDE_INT arg_size, arg_rsize;
  3604. + if (type)
  3605. + {
  3606. + arg_size = int_size_in_bytes (type);
  3607. + }
  3608. + else
  3609. + {
  3610. + arg_size = GET_MODE_SIZE (mode);
  3611. + }
  3612. + arg_rsize = PUSH_ROUNDING (arg_size);
  3613. +
  3614. + /*
  3615. + The last time this macro is called, it is called with mode == VOIDmode,
  3616. + and its result is passed to the call or call_value pattern as operands 2
  3617. + and 3 respectively. */
  3618. + if (mode == VOIDmode)
  3619. + {
  3620. + return gen_rtx_CONST_INT (SImode, 22); /* ToDo: fixme. */
  3621. + }
  3622. +
  3623. + if ((*targetm.calls.must_pass_in_stack) (mode, type) || !named)
  3624. + {
  3625. + return NULL_RTX;
  3626. + }
  3627. +
  3628. + if (arg_rsize == 8)
  3629. + {
  3630. + /* use r11:r10 or r9:r8. */
  3631. + if (!(GET_USED_INDEX (cum, 1) || GET_USED_INDEX (cum, 2)))
  3632. + index = 1;
  3633. + else if ((last_reg_index == 4) &&
  3634. + !(GET_USED_INDEX (cum, 3) || GET_USED_INDEX (cum, 4)))
  3635. + index = 3;
  3636. + else
  3637. + index = -1;
  3638. + }
  3639. + else if (arg_rsize == 4)
  3640. + { /* Use first available register */
  3641. + index = 0;
  3642. + while (index <= last_reg_index && GET_USED_INDEX (cum, index))
  3643. + index++;
  3644. + if (index > last_reg_index)
  3645. + index = -1;
  3646. + }
  3647. +
  3648. + SET_REG_INDEX (cum, index);
  3649. +
  3650. + if (GET_REG_INDEX (cum) >= 0)
  3651. + return gen_rtx_REG (mode, avr32_function_arg_reglist[GET_REG_INDEX (cum)]);
  3652. +
  3653. + return NULL_RTX;
  3654. +}
  3655. +
  3656. +
  3657. +/* Set the register used for passing the first argument to a function. */
  3658. +void
  3659. +avr32_init_cumulative_args (CUMULATIVE_ARGS * cum,
  3660. + tree fntype ATTRIBUTE_UNUSED,
  3661. + rtx libname ATTRIBUTE_UNUSED,
  3662. + tree fndecl)
  3663. +{
  3664. + /* Set all registers as unused. */
  3665. + SET_INDEXES_UNUSED (cum);
  3666. +
  3667. + /* Reset uses_anonymous_args */
  3668. + cum->uses_anonymous_args = 0;
  3669. +
  3670. + /* Reset size of stack pushed arguments */
  3671. + cum->stack_pushed_args_size = 0;
  3672. +
  3673. + cum->flashvault_func = (fndecl && (has_attribute_p (fndecl,"flashvault") || has_attribute_p (fndecl,"flashvault_impl")));
  3674. +}
  3675. +
  3676. +
  3677. +/*
  3678. + Set register used for passing the next argument to a function. Only the
  3679. + Scratch Registers are used.
  3680. +
  3681. + number name
  3682. + 15 r15 PC
  3683. + 14 r14 LR
  3684. + 13 r13 _SP_________
  3685. + FIRST_CUM_REG 12 r12 _||_
  3686. + 10 r11 ||
  3687. + 11 r10 _||_ Scratch Registers
  3688. + 8 r9 ||
  3689. + LAST_SCRATCH_REG 9 r8 _\/_________
  3690. + 6 r7 /\
  3691. + 7 r6 ||
  3692. + 4 r5 ||
  3693. + 5 r4 ||
  3694. + 2 r3 ||
  3695. + 3 r2 ||
  3696. + 0 r1 ||
  3697. + 1 r0 _||_________
  3698. +
  3699. +*/
  3700. +void
  3701. +avr32_function_arg_advance (CUMULATIVE_ARGS * cum, enum machine_mode mode,
  3702. + tree type, int named ATTRIBUTE_UNUSED)
  3703. +{
  3704. + HOST_WIDE_INT arg_size, arg_rsize;
  3705. +
  3706. + if (type)
  3707. + {
  3708. + arg_size = int_size_in_bytes (type);
  3709. + }
  3710. + else
  3711. + {
  3712. + arg_size = GET_MODE_SIZE (mode);
  3713. + }
  3714. + arg_rsize = PUSH_ROUNDING (arg_size);
  3715. +
  3716. + /* If the argument had to be passed in stack, no register is used. */
  3717. + if ((*targetm.calls.must_pass_in_stack) (mode, type))
  3718. + {
  3719. + cum->stack_pushed_args_size += PUSH_ROUNDING (int_size_in_bytes (type));
  3720. + return;
  3721. + }
  3722. +
  3723. + /* Mark the used registers as "used". */
  3724. + if (GET_REG_INDEX (cum) >= 0)
  3725. + {
  3726. + SET_USED_INDEX (cum, GET_REG_INDEX (cum));
  3727. + if (arg_rsize == 8)
  3728. + {
  3729. + SET_USED_INDEX (cum, (GET_REG_INDEX (cum) + 1));
  3730. + }
  3731. + }
  3732. + else
  3733. + {
  3734. + /* Had to use stack */
  3735. + cum->stack_pushed_args_size += arg_rsize;
  3736. + }
  3737. +}
  3738. +
  3739. +
  3740. +/*
  3741. + Defines witch direction to go to find the next register to use if the
  3742. + argument is larger then one register or for arguments shorter than an
  3743. + int which is not promoted, such as the last part of structures with
  3744. + size not a multiple of 4. */
  3745. +enum direction
  3746. +avr32_function_arg_padding (enum machine_mode mode ATTRIBUTE_UNUSED,
  3747. + tree type)
  3748. +{
  3749. + /* Pad upward for all aggregates except byte and halfword sized aggregates
  3750. + which can be passed in registers. */
  3751. + if (type
  3752. + && AGGREGATE_TYPE_P (type)
  3753. + && (int_size_in_bytes (type) != 1)
  3754. + && !((int_size_in_bytes (type) == 2)
  3755. + && TYPE_ALIGN_UNIT (type) >= 2)
  3756. + && (int_size_in_bytes (type) & 0x3))
  3757. + {
  3758. + return upward;
  3759. + }
  3760. +
  3761. + return downward;
  3762. +}
  3763. +
  3764. +
  3765. +/* Return a rtx used for the return value from a function call. */
  3766. +rtx
  3767. +avr32_function_value (tree type, tree func, bool outgoing ATTRIBUTE_UNUSED)
  3768. +{
  3769. + if (avr32_return_in_memory (type, func))
  3770. + return NULL_RTX;
  3771. +
  3772. + if (int_size_in_bytes (type) <= 4)
  3773. + {
  3774. + enum machine_mode mode = TYPE_MODE (type);
  3775. + int unsignedp = 0;
  3776. + PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
  3777. + return gen_rtx_REG (mode, RET_REGISTER);
  3778. + }
  3779. + else if (int_size_in_bytes (type) <= 8)
  3780. + return gen_rtx_REG (TYPE_MODE (type), INTERNAL_REGNUM (11));
  3781. +
  3782. + return NULL_RTX;
  3783. +}
  3784. +
  3785. +
  3786. +/* Return a rtx used for the return value from a library function call. */
  3787. +rtx
  3788. +avr32_libcall_value (enum machine_mode mode)
  3789. +{
  3790. +
  3791. + if (GET_MODE_SIZE (mode) <= 4)
  3792. + return gen_rtx_REG (mode, RET_REGISTER);
  3793. + else if (GET_MODE_SIZE (mode) <= 8)
  3794. + return gen_rtx_REG (mode, INTERNAL_REGNUM (11));
  3795. + else
  3796. + return NULL_RTX;
  3797. +}
  3798. +
  3799. +
  3800. +/* Return TRUE if X references a SYMBOL_REF. */
  3801. +int
  3802. +symbol_mentioned_p (rtx x)
  3803. +{
  3804. + const char *fmt;
  3805. + int i;
  3806. +
  3807. + if (GET_CODE (x) == SYMBOL_REF)
  3808. + return 1;
  3809. +
  3810. + fmt = GET_RTX_FORMAT (GET_CODE (x));
  3811. +
  3812. + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
  3813. + {
  3814. + if (fmt[i] == 'E')
  3815. + {
  3816. + int j;
  3817. +
  3818. + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
  3819. + if (symbol_mentioned_p (XVECEXP (x, i, j)))
  3820. + return 1;
  3821. + }
  3822. + else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
  3823. + return 1;
  3824. + }
  3825. +
  3826. + return 0;
  3827. +}
  3828. +
  3829. +
  3830. +/* Return TRUE if X references a LABEL_REF. */
  3831. +int
  3832. +label_mentioned_p (rtx x)
  3833. +{
  3834. + const char *fmt;
  3835. + int i;
  3836. +
  3837. + if (GET_CODE (x) == LABEL_REF)
  3838. + return 1;
  3839. +
  3840. + fmt = GET_RTX_FORMAT (GET_CODE (x));
  3841. + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
  3842. + {
  3843. + if (fmt[i] == 'E')
  3844. + {
  3845. + int j;
  3846. +
  3847. + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
  3848. + if (label_mentioned_p (XVECEXP (x, i, j)))
  3849. + return 1;
  3850. + }
  3851. + else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
  3852. + return 1;
  3853. + }
  3854. +
  3855. + return 0;
  3856. +}
  3857. +
  3858. +
  3859. +/* Return TRUE if X contains a MEM expression. */
  3860. +int
  3861. +mem_mentioned_p (rtx x)
  3862. +{
  3863. + const char *fmt;
  3864. + int i;
  3865. +
  3866. + if (MEM_P (x))
  3867. + return 1;
  3868. +
  3869. + fmt = GET_RTX_FORMAT (GET_CODE (x));
  3870. + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
  3871. + {
  3872. + if (fmt[i] == 'E')
  3873. + {
  3874. + int j;
  3875. +
  3876. + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
  3877. + if (mem_mentioned_p (XVECEXP (x, i, j)))
  3878. + return 1;
  3879. + }
  3880. + else if (fmt[i] == 'e' && mem_mentioned_p (XEXP (x, i)))
  3881. + return 1;
  3882. + }
  3883. +
  3884. + return 0;
  3885. +}
  3886. +
  3887. +
  3888. +int
  3889. +avr32_legitimate_pic_operand_p (rtx x)
  3890. +{
  3891. +
  3892. + /* We can't have const, this must be broken down to a symbol. */
  3893. + if (GET_CODE (x) == CONST)
  3894. + return FALSE;
  3895. +
  3896. + /* Can't access symbols or labels via the constant pool either */
  3897. + if ((GET_CODE (x) == SYMBOL_REF
  3898. + && CONSTANT_POOL_ADDRESS_P (x)
  3899. + && (symbol_mentioned_p (get_pool_constant (x))
  3900. + || label_mentioned_p (get_pool_constant (x)))))
  3901. + return FALSE;
  3902. +
  3903. + return TRUE;
  3904. +}
  3905. +
  3906. +
  3907. +rtx
  3908. +legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
  3909. + rtx reg)
  3910. +{
  3911. +
  3912. + if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
  3913. + {
  3914. + int subregs = 0;
  3915. +
  3916. + if (reg == 0)
  3917. + {
  3918. + if (!can_create_pseudo_p ())
  3919. + abort ();
  3920. + else
  3921. + reg = gen_reg_rtx (Pmode);
  3922. +
  3923. + subregs = 1;
  3924. + }
  3925. +
  3926. + emit_move_insn (reg, orig);
  3927. +
  3928. + /* Only set current function as using pic offset table if flag_pic is
  3929. + set. This is because this function is also used if
  3930. + TARGET_HAS_ASM_ADDR_PSEUDOS is set. */
  3931. + if (flag_pic)
  3932. + crtl->uses_pic_offset_table = 1;
  3933. +
  3934. + /* Put a REG_EQUAL note on this insn, so that it can be optimized by
  3935. + loop. */
  3936. + return reg;
  3937. + }
  3938. + else if (GET_CODE (orig) == CONST)
  3939. + {
  3940. + rtx base, offset;
  3941. +
  3942. + if (flag_pic
  3943. + && GET_CODE (XEXP (orig, 0)) == PLUS
  3944. + && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
  3945. + return orig;
  3946. +
  3947. + if (reg == 0)
  3948. + {
  3949. + if (!can_create_pseudo_p ())
  3950. + abort ();
  3951. + else
  3952. + reg = gen_reg_rtx (Pmode);
  3953. + }
  3954. +
  3955. + if (GET_CODE (XEXP (orig, 0)) == PLUS)
  3956. + {
  3957. + base =
  3958. + legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
  3959. + offset =
  3960. + legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
  3961. + base == reg ? 0 : reg);
  3962. + }
  3963. + else
  3964. + abort ();
  3965. +
  3966. + if (GET_CODE (offset) == CONST_INT)
  3967. + {
  3968. + /* The base register doesn't really matter, we only want to test
  3969. + the index for the appropriate mode. */
  3970. + if (!avr32_const_ok_for_constraint_p (INTVAL (offset), 'I', "Is21"))
  3971. + {
  3972. + if (can_create_pseudo_p ())
  3973. + offset = force_reg (Pmode, offset);
  3974. + else
  3975. + abort ();
  3976. + }
  3977. +
  3978. + if (GET_CODE (offset) == CONST_INT)
  3979. + return plus_constant (base, INTVAL (offset));
  3980. + }
  3981. +
  3982. + return gen_rtx_PLUS (Pmode, base, offset);
  3983. + }
  3984. +
  3985. + return orig;
  3986. +}
  3987. +
  3988. +
  3989. +/* Generate code to load the PIC register. */
  3990. +void
  3991. +avr32_load_pic_register (void)
  3992. +{
  3993. + rtx l1, pic_tmp;
  3994. + rtx global_offset_table;
  3995. +
  3996. + if ((crtl->uses_pic_offset_table == 0) || TARGET_NO_INIT_GOT)
  3997. + return;
  3998. +
  3999. + if (!flag_pic)
  4000. + abort ();
  4001. +
  4002. + l1 = gen_label_rtx ();
  4003. +
  4004. + global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
  4005. + pic_tmp =
  4006. + gen_rtx_CONST (Pmode,
  4007. + gen_rtx_MINUS (SImode, gen_rtx_LABEL_REF (Pmode, l1),
  4008. + global_offset_table));
  4009. + emit_insn (gen_pic_load_addr
  4010. + (pic_offset_table_rtx, force_const_mem (SImode, pic_tmp)));
  4011. + emit_insn (gen_pic_compute_got_from_pc (pic_offset_table_rtx, l1));
  4012. +
  4013. + /* Need to emit this whether or not we obey regdecls, since setjmp/longjmp
  4014. + can cause life info to screw up. */
  4015. + emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
  4016. +}
  4017. +
  4018. +
  4019. +/* This hook should return true if values of type type are returned at the most
  4020. + significant end of a register (in other words, if they are padded at the
  4021. + least significant end). You can assume that type is returned in a register;
  4022. + the caller is required to check this. Note that the register provided by
  4023. + FUNCTION_VALUE must be able to hold the complete return value. For example,
  4024. + if a 1-, 2- or 3-byte structure is returned at the most significant end of a
  4025. + 4-byte register, FUNCTION_VALUE should provide an SImode rtx. */
  4026. +bool
  4027. +avr32_return_in_msb (tree type ATTRIBUTE_UNUSED)
  4028. +{
  4029. + /* if ( AGGREGATE_TYPE_P (type) ) if ((int_size_in_bytes(type) == 1) ||
  4030. + ((int_size_in_bytes(type) == 2) && TYPE_ALIGN_UNIT(type) >= 2)) return
  4031. + false; else return true; */
  4032. +
  4033. + return false;
  4034. +}
  4035. +
  4036. +
  4037. +/*
  4038. + Returns one if a certain function value is going to be returned in memory
  4039. + and zero if it is going to be returned in a register.
  4040. +
  4041. + BLKmode and all other modes that is larger than 64 bits are returned in
  4042. + memory.
  4043. +*/
  4044. +bool
  4045. +avr32_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
  4046. +{
  4047. + if (TYPE_MODE (type) == VOIDmode)
  4048. + return false;
  4049. +
  4050. + if (int_size_in_bytes (type) > (2 * UNITS_PER_WORD)
  4051. + || int_size_in_bytes (type) == -1)
  4052. + {
  4053. + return true;
  4054. + }
  4055. +
  4056. + /* If we have an aggregate then use the same mechanism as when checking if
  4057. + it should be passed on the stack. */
  4058. + if (type
  4059. + && AGGREGATE_TYPE_P (type)
  4060. + && (*targetm.calls.must_pass_in_stack) (TYPE_MODE (type), type))
  4061. + return true;
  4062. +
  4063. + return false;
  4064. +}
  4065. +
  4066. +
  4067. +/* Output the constant part of the trampoline.
  4068. + lddpc r0, pc[0x8:e] ; load static chain register
  4069. + lddpc pc, pc[0x8:e] ; jump to subrutine
  4070. + .long 0 ; Address to static chain,
  4071. + ; filled in by avr32_initialize_trampoline()
  4072. + .long 0 ; Address to subrutine,
  4073. + ; filled in by avr32_initialize_trampoline()
  4074. +*/
  4075. +void
  4076. +avr32_trampoline_template (FILE * file)
  4077. +{
  4078. + fprintf (file, "\tlddpc r0, pc[8]\n");
  4079. + fprintf (file, "\tlddpc pc, pc[8]\n");
  4080. + /* make room for the address of the static chain. */
  4081. + fprintf (file, "\t.long\t0\n");
  4082. + /* make room for the address to the subrutine. */
  4083. + fprintf (file, "\t.long\t0\n");
  4084. +}
  4085. +
  4086. +
  4087. +/* Initialize the variable parts of a trampoline. */
  4088. +void
  4089. +avr32_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
  4090. +{
  4091. + /* Store the address to the static chain. */
  4092. + emit_move_insn (gen_rtx_MEM
  4093. + (SImode, plus_constant (addr, TRAMPOLINE_SIZE - 4)),
  4094. + static_chain);
  4095. +
  4096. + /* Store the address to the function. */
  4097. + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, TRAMPOLINE_SIZE)),
  4098. + fnaddr);
  4099. +
  4100. + emit_insn (gen_cache (gen_rtx_REG (SImode, 13),
  4101. + gen_rtx_CONST_INT (SImode,
  4102. + AVR32_CACHE_INVALIDATE_ICACHE)));
  4103. +}
  4104. +
  4105. +
  4106. +/* Return nonzero if X is valid as an addressing register. */
  4107. +int
  4108. +avr32_address_register_rtx_p (rtx x, int strict_p)
  4109. +{
  4110. + int regno;
  4111. +
  4112. + if (!register_operand(x, GET_MODE(x)))
  4113. + return 0;
  4114. +
  4115. + /* If strict we require the register to be a hard register. */
  4116. + if (strict_p
  4117. + && !REG_P(x))
  4118. + return 0;
  4119. +
  4120. + regno = REGNO (x);
  4121. +
  4122. + if (strict_p)
  4123. + return REGNO_OK_FOR_BASE_P (regno);
  4124. +
  4125. + return (regno <= LAST_REGNUM || regno >= FIRST_PSEUDO_REGISTER);
  4126. +}
  4127. +
  4128. +
  4129. +/* Return nonzero if INDEX is valid for an address index operand. */
  4130. +int
  4131. +avr32_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
  4132. +{
  4133. + enum rtx_code code = GET_CODE (index);
  4134. +
  4135. + if (GET_MODE_SIZE (mode) > 8)
  4136. + return 0;
  4137. +
  4138. + /* Standard coprocessor addressing modes. */
  4139. + if (code == CONST_INT)
  4140. + {
  4141. + return CONST_OK_FOR_CONSTRAINT_P (INTVAL (index), 'K', "Ks16");
  4142. + }
  4143. +
  4144. + if (avr32_address_register_rtx_p (index, strict_p))
  4145. + return 1;
  4146. +
  4147. + if (code == MULT)
  4148. + {
  4149. + rtx xiop0 = XEXP (index, 0);
  4150. + rtx xiop1 = XEXP (index, 1);
  4151. + return ((avr32_address_register_rtx_p (xiop0, strict_p)
  4152. + && power_of_two_operand (xiop1, SImode)
  4153. + && (INTVAL (xiop1) <= 8))
  4154. + || (avr32_address_register_rtx_p (xiop1, strict_p)
  4155. + && power_of_two_operand (xiop0, SImode)
  4156. + && (INTVAL (xiop0) <= 8)));
  4157. + }
  4158. + else if (code == ASHIFT)
  4159. + {
  4160. + rtx op = XEXP (index, 1);
  4161. +
  4162. + return (avr32_address_register_rtx_p (XEXP (index, 0), strict_p)
  4163. + && GET_CODE (op) == CONST_INT
  4164. + && INTVAL (op) > 0 && INTVAL (op) <= 3);
  4165. + }
  4166. +
  4167. + return 0;
  4168. +}
  4169. +
  4170. +
  4171. +/*
  4172. + Used in the GO_IF_LEGITIMATE_ADDRESS macro. Returns a nonzero value if
  4173. + the RTX x is a legitimate memory address.
  4174. +
  4175. + Returns NO_REGS if the address is not legatime, GENERAL_REGS or ALL_REGS
  4176. + if it is.
  4177. +*/
  4178. +
  4179. +
  4180. +/* Forward declaration */
  4181. +int is_minipool_label (rtx label);
  4182. +
  4183. +int
  4184. +avr32_legitimate_address (enum machine_mode mode, rtx x, int strict)
  4185. +{
  4186. +
  4187. + switch (GET_CODE (x))
  4188. + {
  4189. + case REG:
  4190. + return avr32_address_register_rtx_p (x, strict);
  4191. + case CONST_INT:
  4192. + return ((mode==SImode) && TARGET_RMW_ADDRESSABLE_DATA
  4193. + && CONST_OK_FOR_CONSTRAINT_P(INTVAL(x), 'K', "Ks17"));
  4194. + case CONST:
  4195. + {
  4196. + rtx label = avr32_find_symbol (x);
  4197. + if (label
  4198. + &&
  4199. + (/*
  4200. + If we enable (const (plus (symbol_ref ...))) type constant
  4201. + pool entries we must add support for it in the predicates and
  4202. + in the minipool generation in avr32_reorg().
  4203. + (CONSTANT_POOL_ADDRESS_P (label)
  4204. + && !(flag_pic
  4205. + && (symbol_mentioned_p (get_pool_constant (label))
  4206. + || label_mentioned_p (get_pool_constant (label)))))
  4207. + ||*/
  4208. + ((GET_CODE (label) == LABEL_REF)
  4209. + && GET_CODE (XEXP (label, 0)) == CODE_LABEL
  4210. + && is_minipool_label (XEXP (label, 0)))
  4211. + /*|| ((GET_CODE (label) == SYMBOL_REF)
  4212. + && mode == SImode
  4213. + && SYMBOL_REF_RMW_ADDR(label))*/))
  4214. + {
  4215. + return TRUE;
  4216. + }
  4217. + }
  4218. + break;
  4219. + case LABEL_REF:
  4220. + if (GET_CODE (XEXP (x, 0)) == CODE_LABEL
  4221. + && is_minipool_label (XEXP (x, 0)))
  4222. + {
  4223. + return TRUE;
  4224. + }
  4225. + break;
  4226. + case SYMBOL_REF:
  4227. + {
  4228. + if (CONSTANT_POOL_ADDRESS_P (x)
  4229. + && !(flag_pic
  4230. + && (symbol_mentioned_p (get_pool_constant (x))
  4231. + || label_mentioned_p (get_pool_constant (x)))))
  4232. + return TRUE;
  4233. + else if (SYMBOL_REF_RCALL_FUNCTION_P (x)
  4234. + || (mode == SImode
  4235. + && SYMBOL_REF_RMW_ADDR (x)))
  4236. + return TRUE;
  4237. + break;
  4238. + }
  4239. + case PRE_DEC: /* (pre_dec (...)) */
  4240. + case POST_INC: /* (post_inc (...)) */
  4241. + return avr32_address_register_rtx_p (XEXP (x, 0), strict);
  4242. + case PLUS: /* (plus (...) (...)) */
  4243. + {
  4244. + rtx xop0 = XEXP (x, 0);
  4245. + rtx xop1 = XEXP (x, 1);
  4246. +
  4247. + return ((avr32_address_register_rtx_p (xop0, strict)
  4248. + && avr32_legitimate_index_p (mode, xop1, strict))
  4249. + || (avr32_address_register_rtx_p (xop1, strict)
  4250. + && avr32_legitimate_index_p (mode, xop0, strict)));
  4251. + }
  4252. + default:
  4253. + break;
  4254. + }
  4255. +
  4256. + return FALSE;
  4257. +}
  4258. +
  4259. +
  4260. +int
  4261. +avr32_const_ok_for_move (HOST_WIDE_INT c)
  4262. +{
  4263. + if ( TARGET_V2_INSNS )
  4264. + return ( avr32_const_ok_for_constraint_p (c, 'K', "Ks21")
  4265. + /* movh instruction */
  4266. + || avr32_hi16_immediate_operand (GEN_INT(c), VOIDmode) );
  4267. + else
  4268. + return avr32_const_ok_for_constraint_p (c, 'K', "Ks21");
  4269. +}
  4270. +
  4271. +
  4272. +int
  4273. +avr32_const_double_immediate (rtx value)
  4274. +{
  4275. + HOST_WIDE_INT hi, lo;
  4276. +
  4277. + if (GET_CODE (value) != CONST_DOUBLE)
  4278. + return FALSE;
  4279. +
  4280. + if (SCALAR_FLOAT_MODE_P (GET_MODE (value)))
  4281. + {
  4282. + HOST_WIDE_INT target_float[2];
  4283. + hi = lo = 0;
  4284. + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (value),
  4285. + GET_MODE (value));
  4286. + lo = target_float[0];
  4287. + hi = target_float[1];
  4288. + }
  4289. + else
  4290. + {
  4291. + hi = CONST_DOUBLE_HIGH (value);
  4292. + lo = CONST_DOUBLE_LOW (value);
  4293. + }
  4294. +
  4295. + if (avr32_const_ok_for_constraint_p (lo, 'K', "Ks21")
  4296. + && (GET_MODE (value) == SFmode
  4297. + || avr32_const_ok_for_constraint_p (hi, 'K', "Ks21")))
  4298. + {
  4299. + return TRUE;
  4300. + }
  4301. +
  4302. + return FALSE;
  4303. +}
  4304. +
  4305. +
  4306. +int
  4307. +avr32_legitimate_constant_p (rtx x)
  4308. +{
  4309. + switch (GET_CODE (x))
  4310. + {
  4311. + case CONST_INT:
  4312. + /* Check if we should put large immediate into constant pool
  4313. + or load them directly with mov/orh.*/
  4314. + if (!avr32_imm_in_const_pool)
  4315. + return 1;
  4316. +
  4317. + return avr32_const_ok_for_move (INTVAL (x));
  4318. + case CONST_DOUBLE:
  4319. + /* Check if we should put large immediate into constant pool
  4320. + or load them directly with mov/orh.*/
  4321. + if (!avr32_imm_in_const_pool)
  4322. + return 1;
  4323. +
  4324. + if (GET_MODE (x) == SFmode
  4325. + || GET_MODE (x) == DFmode || GET_MODE (x) == DImode)
  4326. + return avr32_const_double_immediate (x);
  4327. + else
  4328. + return 0;
  4329. + case LABEL_REF:
  4330. + case SYMBOL_REF:
  4331. + return avr32_find_symbol (x) && (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS);
  4332. + case CONST:
  4333. + case HIGH:
  4334. + case CONST_VECTOR:
  4335. + return 0;
  4336. + default:
  4337. + printf ("%s():\n", __FUNCTION__);
  4338. + debug_rtx (x);
  4339. + return 1;
  4340. + }
  4341. +}
  4342. +
  4343. +
  4344. +/* Strip any special encoding from labels */
  4345. +const char *
  4346. +avr32_strip_name_encoding (const char *name)
  4347. +{
  4348. + const char *stripped = name;
  4349. +
  4350. + while (1)
  4351. + {
  4352. + switch (stripped[0])
  4353. + {
  4354. + case '#':
  4355. + stripped = strchr (name + 1, '#') + 1;
  4356. + break;
  4357. + case '*':
  4358. + stripped = &stripped[1];
  4359. + break;
  4360. + default:
  4361. + return stripped;
  4362. + }
  4363. + }
  4364. +}
  4365. +
  4366. +
  4367. +
  4368. +/* Do anything needed before RTL is emitted for each function. */
  4369. +static struct machine_function *
  4370. +avr32_init_machine_status (void)
  4371. +{
  4372. + struct machine_function *machine;
  4373. + machine =
  4374. + (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
  4375. +
  4376. +#if AVR32_FT_UNKNOWN != 0
  4377. + machine->func_type = AVR32_FT_UNKNOWN;
  4378. +#endif
  4379. +
  4380. + machine->minipool_label_head = 0;
  4381. + machine->minipool_label_tail = 0;
  4382. + machine->ifcvt_after_reload = 0;
  4383. + return machine;
  4384. +}
  4385. +
  4386. +
  4387. +void
  4388. +avr32_init_expanders (void)
  4389. +{
  4390. + /* Arrange to initialize and mark the machine per-function status. */
  4391. + init_machine_status = avr32_init_machine_status;
  4392. +}
  4393. +
  4394. +
  4395. +/* Return an RTX indicating where the return address to the
  4396. + calling function can be found. */
  4397. +rtx
  4398. +avr32_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
  4399. +{
  4400. + if (count != 0)
  4401. + return NULL_RTX;
  4402. +
  4403. + return get_hard_reg_initial_val (Pmode, LR_REGNUM);
  4404. +}
  4405. +
  4406. +
  4407. +void
  4408. +avr32_encode_section_info (tree decl, rtx rtl, int first)
  4409. +{
  4410. + default_encode_section_info(decl, rtl, first);
  4411. +
  4412. + if ( TREE_CODE (decl) == VAR_DECL
  4413. + && (GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
  4414. + && (lookup_attribute ("rmw_addressable", DECL_ATTRIBUTES (decl))
  4415. + || TARGET_RMW_ADDRESSABLE_DATA) ){
  4416. + if ( !TARGET_RMW || flag_pic )
  4417. + return;
  4418. + // {
  4419. + // warning ("Using RMW addressable data with an arch that does not support RMW instructions.");
  4420. + // return;
  4421. + // }
  4422. + //
  4423. + //if ( flag_pic )
  4424. + // {
  4425. + // warning ("Using RMW addressable data with together with -fpic switch. Can not use RMW instruction when compiling with -fpic.");
  4426. + // return;
  4427. + // }
  4428. + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT);
  4429. + }
  4430. +}
  4431. +
  4432. +
  4433. +void
  4434. +avr32_asm_output_label (FILE * stream, const char *name)
  4435. +{
  4436. + name = avr32_strip_name_encoding (name);
  4437. +
  4438. + /* Print the label. */
  4439. + assemble_name (stream, name);
  4440. + fprintf (stream, ":\n");
  4441. +}
  4442. +
  4443. +
  4444. +void
  4445. +avr32_asm_weaken_label (FILE * stream, const char *name)
  4446. +{
  4447. + fprintf (stream, "\t.weak ");
  4448. + assemble_name (stream, name);
  4449. + fprintf (stream, "\n");
  4450. +}
  4451. +
  4452. +
  4453. +/*
  4454. + Checks if a labelref is equal to a reserved word in the assembler. If it is,
  4455. + insert a '_' before the label name.
  4456. +*/
  4457. +void
  4458. +avr32_asm_output_labelref (FILE * stream, const char *name)
  4459. +{
  4460. + int verbatim = FALSE;
  4461. + const char *stripped = name;
  4462. + int strip_finished = FALSE;
  4463. +
  4464. + while (!strip_finished)
  4465. + {
  4466. + switch (stripped[0])
  4467. + {
  4468. + case '#':
  4469. + stripped = strchr (name + 1, '#') + 1;
  4470. + break;
  4471. + case '*':
  4472. + stripped = &stripped[1];
  4473. + verbatim = TRUE;
  4474. + break;
  4475. + default:
  4476. + strip_finished = TRUE;
  4477. + break;
  4478. + }
  4479. + }
  4480. +
  4481. + if (verbatim)
  4482. + fputs (stripped, stream);
  4483. + else
  4484. + asm_fprintf (stream, "%U%s", stripped);
  4485. +}
  4486. +
  4487. +
  4488. +/*
  4489. + Check if the comparison in compare_exp is redundant
  4490. + for the condition given in next_cond given that the
  4491. + needed flags are already set by an earlier instruction.
  4492. + Uses cc_prev_status to check this.
  4493. +
  4494. + Returns NULL_RTX if the compare is not redundant
  4495. + or the new condition to use in the conditional
  4496. + instruction if the compare is redundant.
  4497. +*/
  4498. +static rtx
  4499. +is_compare_redundant (rtx compare_exp, rtx next_cond)
  4500. +{
  4501. + int z_flag_valid = FALSE;
  4502. + int n_flag_valid = FALSE;
  4503. + rtx new_cond;
  4504. +
  4505. + if (GET_CODE (compare_exp) != COMPARE
  4506. + && GET_CODE (compare_exp) != AND)
  4507. + return NULL_RTX;
  4508. +
  4509. +
  4510. + if (rtx_equal_p (cc_prev_status.mdep.value, compare_exp))
  4511. + {
  4512. + /* cc0 already contains the correct comparison -> delete cmp insn */
  4513. + return next_cond;
  4514. + }
  4515. +
  4516. + if (GET_MODE (compare_exp) != SImode)
  4517. + return NULL_RTX;
  4518. +
  4519. + switch (cc_prev_status.mdep.flags)
  4520. + {
  4521. + case CC_SET_VNCZ:
  4522. + case CC_SET_NCZ:
  4523. + n_flag_valid = TRUE;
  4524. + case CC_SET_CZ:
  4525. + case CC_SET_Z:
  4526. + z_flag_valid = TRUE;
  4527. + }
  4528. +
  4529. + if (cc_prev_status.mdep.value
  4530. + && GET_CODE (compare_exp) == COMPARE
  4531. + && REG_P (XEXP (compare_exp, 0))
  4532. + && REGNO (XEXP (compare_exp, 0)) == REGNO (cc_prev_status.mdep.value)
  4533. + && GET_CODE (XEXP (compare_exp, 1)) == CONST_INT
  4534. + && next_cond != NULL_RTX)
  4535. + {
  4536. + if (INTVAL (XEXP (compare_exp, 1)) == 0
  4537. + && z_flag_valid
  4538. + && (GET_CODE (next_cond) == EQ || GET_CODE (next_cond) == NE))
  4539. + /* We can skip comparison Z flag is already reflecting ops[0] */
  4540. + return next_cond;
  4541. + else if (n_flag_valid
  4542. + && ((INTVAL (XEXP (compare_exp, 1)) == 0
  4543. + && (GET_CODE (next_cond) == GE
  4544. + || GET_CODE (next_cond) == LT))
  4545. + || (INTVAL (XEXP (compare_exp, 1)) == -1
  4546. + && (GET_CODE (next_cond) == GT
  4547. + || GET_CODE (next_cond) == LE))))
  4548. + {
  4549. + /* We can skip comparison N flag is already reflecting ops[0],
  4550. + which means that we can use the mi/pl conditions to check if
  4551. + ops[0] is GE or LT 0. */
  4552. + if ((GET_CODE (next_cond) == GE) || (GET_CODE (next_cond) == GT))
  4553. + new_cond =
  4554. + gen_rtx_UNSPEC (GET_MODE (next_cond), gen_rtvec (2, cc0_rtx, const0_rtx),
  4555. + UNSPEC_COND_PL);
  4556. + else
  4557. + new_cond =
  4558. + gen_rtx_UNSPEC (GET_MODE (next_cond), gen_rtvec (2, cc0_rtx, const0_rtx),
  4559. + UNSPEC_COND_MI);
  4560. + return new_cond;
  4561. + }
  4562. + }
  4563. + return NULL_RTX;
  4564. +}
  4565. +
  4566. +
  4567. +/* Updates cc_status. */
  4568. +void
  4569. +avr32_notice_update_cc (rtx exp, rtx insn)
  4570. +{
  4571. + enum attr_cc attr_cc = get_attr_cc (insn);
  4572. +
  4573. + if ( attr_cc == CC_SET_Z_IF_NOT_V2 )
  4574. + {
  4575. + if (TARGET_V2_INSNS)
  4576. + attr_cc = CC_NONE;
  4577. + else
  4578. + attr_cc = CC_SET_Z;
  4579. + }
  4580. +
  4581. + switch (attr_cc)
  4582. + {
  4583. + case CC_CALL_SET:
  4584. + CC_STATUS_INIT;
  4585. + /* Check if the function call returns a value in r12 */
  4586. + if (REG_P (recog_data.operand[0])
  4587. + && REGNO (recog_data.operand[0]) == RETVAL_REGNUM)
  4588. + {
  4589. + cc_status.flags = 0;
  4590. + cc_status.mdep.value =
  4591. + gen_rtx_COMPARE (SImode, recog_data.operand[0], const0_rtx);
  4592. + cc_status.mdep.flags = CC_SET_VNCZ;
  4593. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4594. +
  4595. + }
  4596. + break;
  4597. + case CC_COMPARE:
  4598. + {
  4599. + /* Check that compare will not be optimized away if so nothing should
  4600. + be done */
  4601. + rtx compare_exp = SET_SRC (exp);
  4602. + /* Check if we have a tst expression. If so convert it to a
  4603. + compare with 0. */
  4604. + if ( REG_P (SET_SRC (exp)) )
  4605. + compare_exp = gen_rtx_COMPARE (GET_MODE (SET_SRC (exp)),
  4606. + SET_SRC (exp),
  4607. + const0_rtx);
  4608. +
  4609. + if (!next_insn_emits_cmp (insn)
  4610. + && (is_compare_redundant (compare_exp, get_next_insn_cond (insn)) == NULL_RTX))
  4611. + {
  4612. +
  4613. + /* Reset the nonstandard flag */
  4614. + CC_STATUS_INIT;
  4615. + cc_status.flags = 0;
  4616. + cc_status.mdep.value = compare_exp;
  4617. + cc_status.mdep.flags = CC_SET_VNCZ;
  4618. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4619. + }
  4620. + }
  4621. + break;
  4622. + case CC_CMP_COND_INSN:
  4623. + {
  4624. + /* Conditional insn that emit the compare itself. */
  4625. + rtx cmp;
  4626. + rtx cmp_op0, cmp_op1;
  4627. + rtx cond;
  4628. + rtx dest;
  4629. + rtx next_insn = next_nonnote_insn (insn);
  4630. +
  4631. + if ( GET_CODE (exp) == COND_EXEC )
  4632. + {
  4633. + cmp_op0 = XEXP (COND_EXEC_TEST (exp), 0);
  4634. + cmp_op1 = XEXP (COND_EXEC_TEST (exp), 1);
  4635. + cond = COND_EXEC_TEST (exp);
  4636. + dest = SET_DEST (COND_EXEC_CODE (exp));
  4637. + }
  4638. + else
  4639. + {
  4640. + /* If then else conditional. compare operands are in operands
  4641. + 4 and 5. */
  4642. + cmp_op0 = recog_data.operand[4];
  4643. + cmp_op1 = recog_data.operand[5];
  4644. + cond = recog_data.operand[1];
  4645. + dest = SET_DEST (exp);
  4646. + }
  4647. +
  4648. + if ( GET_CODE (cmp_op0) == AND )
  4649. + cmp = cmp_op0;
  4650. + else
  4651. + cmp = gen_rtx_COMPARE (GET_MODE (cmp_op0),
  4652. + cmp_op0,
  4653. + cmp_op1);
  4654. +
  4655. + /* Check if the conditional insns updates a register present
  4656. + in the comparison, if so then we must reset the cc_status. */
  4657. + if (REG_P (dest)
  4658. + && (reg_mentioned_p (dest, cmp_op0)
  4659. + || reg_mentioned_p (dest, cmp_op1))
  4660. + && GET_CODE (exp) != COND_EXEC )
  4661. + {
  4662. + CC_STATUS_INIT;
  4663. + }
  4664. + else if (is_compare_redundant (cmp, cond) == NULL_RTX)
  4665. + {
  4666. + /* Reset the nonstandard flag */
  4667. + CC_STATUS_INIT;
  4668. + if ( GET_CODE (cmp_op0) == AND )
  4669. + {
  4670. + cc_status.flags = CC_INVERTED;
  4671. + cc_status.mdep.flags = CC_SET_Z;
  4672. + }
  4673. + else
  4674. + {
  4675. + cc_status.flags = 0;
  4676. + cc_status.mdep.flags = CC_SET_VNCZ;
  4677. + }
  4678. + cc_status.mdep.value = cmp;
  4679. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4680. + }
  4681. +
  4682. +
  4683. + /* Check if we have a COND_EXEC insn which updates one
  4684. + of the registers in the compare status. */
  4685. + if (REG_P (dest)
  4686. + && (reg_mentioned_p (dest, cmp_op0)
  4687. + || reg_mentioned_p (dest, cmp_op1))
  4688. + && GET_CODE (exp) == COND_EXEC )
  4689. + cc_status.mdep.cond_exec_cmp_clobbered = 1;
  4690. +
  4691. + if ( cc_status.mdep.cond_exec_cmp_clobbered
  4692. + && GET_CODE (exp) == COND_EXEC
  4693. + && next_insn != NULL
  4694. + && INSN_P (next_insn)
  4695. + && !(GET_CODE (PATTERN (next_insn)) == COND_EXEC
  4696. + && rtx_equal_p (XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 0), cmp_op0)
  4697. + && rtx_equal_p (XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 1), cmp_op1)
  4698. + && (GET_CODE (COND_EXEC_TEST (PATTERN (next_insn))) == GET_CODE (cond)
  4699. + || GET_CODE (COND_EXEC_TEST (PATTERN (next_insn))) == reverse_condition (GET_CODE (cond)))) )
  4700. + {
  4701. + /* We have a sequence of conditional insns where the compare status has been clobbered
  4702. + since the compare no longer reflects the content of the values to compare. */
  4703. + CC_STATUS_INIT;
  4704. + cc_status.mdep.cond_exec_cmp_clobbered = 1;
  4705. + }
  4706. +
  4707. + }
  4708. + break;
  4709. + case CC_BLD:
  4710. + /* Bit load is kind of like an inverted testsi, because the Z flag is
  4711. + inverted */
  4712. + CC_STATUS_INIT;
  4713. + cc_status.flags = CC_INVERTED;
  4714. + cc_status.mdep.value = SET_SRC (exp);
  4715. + cc_status.mdep.flags = CC_SET_Z;
  4716. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4717. + break;
  4718. + case CC_NONE:
  4719. + /* Insn does not affect CC at all. Check if the instruction updates
  4720. + some of the register currently reflected in cc0 */
  4721. +
  4722. + if ((GET_CODE (exp) == SET)
  4723. + && (cc_status.value1 || cc_status.value2 || cc_status.mdep.value)
  4724. + && (reg_mentioned_p (SET_DEST (exp), cc_status.value1)
  4725. + || reg_mentioned_p (SET_DEST (exp), cc_status.value2)
  4726. + || reg_mentioned_p (SET_DEST (exp), cc_status.mdep.value)))
  4727. + {
  4728. + CC_STATUS_INIT;
  4729. + }
  4730. +
  4731. + /* If this is a parallel we must step through each of the parallel
  4732. + expressions */
  4733. + if (GET_CODE (exp) == PARALLEL)
  4734. + {
  4735. + int i;
  4736. + for (i = 0; i < XVECLEN (exp, 0); ++i)
  4737. + {
  4738. + rtx vec_exp = XVECEXP (exp, 0, i);
  4739. + if ((GET_CODE (vec_exp) == SET)
  4740. + && (cc_status.value1 || cc_status.value2
  4741. + || cc_status.mdep.value)
  4742. + && (reg_mentioned_p (SET_DEST (vec_exp), cc_status.value1)
  4743. + || reg_mentioned_p (SET_DEST (vec_exp),
  4744. + cc_status.value2)
  4745. + || reg_mentioned_p (SET_DEST (vec_exp),
  4746. + cc_status.mdep.value)))
  4747. + {
  4748. + CC_STATUS_INIT;
  4749. + }
  4750. + }
  4751. + }
  4752. +
  4753. + /* Check if we have memory opartions with post_inc or pre_dec on the
  4754. + register currently reflected in cc0 */
  4755. + if (GET_CODE (exp) == SET
  4756. + && GET_CODE (SET_SRC (exp)) == MEM
  4757. + && (GET_CODE (XEXP (SET_SRC (exp), 0)) == POST_INC
  4758. + || GET_CODE (XEXP (SET_SRC (exp), 0)) == PRE_DEC)
  4759. + &&
  4760. + (reg_mentioned_p
  4761. + (XEXP (XEXP (SET_SRC (exp), 0), 0), cc_status.value1)
  4762. + || reg_mentioned_p (XEXP (XEXP (SET_SRC (exp), 0), 0),
  4763. + cc_status.value2)
  4764. + || reg_mentioned_p (XEXP (XEXP (SET_SRC (exp), 0), 0),
  4765. + cc_status.mdep.value)))
  4766. + CC_STATUS_INIT;
  4767. +
  4768. + if (GET_CODE (exp) == SET
  4769. + && GET_CODE (SET_DEST (exp)) == MEM
  4770. + && (GET_CODE (XEXP (SET_DEST (exp), 0)) == POST_INC
  4771. + || GET_CODE (XEXP (SET_DEST (exp), 0)) == PRE_DEC)
  4772. + &&
  4773. + (reg_mentioned_p
  4774. + (XEXP (XEXP (SET_DEST (exp), 0), 0), cc_status.value1)
  4775. + || reg_mentioned_p (XEXP (XEXP (SET_DEST (exp), 0), 0),
  4776. + cc_status.value2)
  4777. + || reg_mentioned_p (XEXP (XEXP (SET_DEST (exp), 0), 0),
  4778. + cc_status.mdep.value)))
  4779. + CC_STATUS_INIT;
  4780. + break;
  4781. +
  4782. + case CC_SET_VNCZ:
  4783. + CC_STATUS_INIT;
  4784. + cc_status.mdep.value = recog_data.operand[0];
  4785. + cc_status.mdep.flags = CC_SET_VNCZ;
  4786. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4787. + break;
  4788. +
  4789. + case CC_SET_NCZ:
  4790. + CC_STATUS_INIT;
  4791. + cc_status.mdep.value = recog_data.operand[0];
  4792. + cc_status.mdep.flags = CC_SET_NCZ;
  4793. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4794. + break;
  4795. +
  4796. + case CC_SET_CZ:
  4797. + CC_STATUS_INIT;
  4798. + cc_status.mdep.value = recog_data.operand[0];
  4799. + cc_status.mdep.flags = CC_SET_CZ;
  4800. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4801. + break;
  4802. +
  4803. + case CC_SET_Z:
  4804. + CC_STATUS_INIT;
  4805. + cc_status.mdep.value = recog_data.operand[0];
  4806. + cc_status.mdep.flags = CC_SET_Z;
  4807. + cc_status.mdep.cond_exec_cmp_clobbered = 0;
  4808. + break;
  4809. +
  4810. + case CC_CLOBBER:
  4811. + CC_STATUS_INIT;
  4812. + break;
  4813. +
  4814. + default:
  4815. + CC_STATUS_INIT;
  4816. + }
  4817. +}
  4818. +
  4819. +
  4820. +/*
  4821. + Outputs to stdio stream stream the assembler syntax for an instruction
  4822. + operand x. x is an RTL expression.
  4823. +*/
  4824. +void
  4825. +avr32_print_operand (FILE * stream, rtx x, int code)
  4826. +{
  4827. + int error = 0;
  4828. +
  4829. + if ( code == '?' )
  4830. + {
  4831. + /* Predicable instruction, print condition code */
  4832. +
  4833. + /* If the insn should not be conditional then do nothing. */
  4834. + if ( current_insn_predicate == NULL_RTX )
  4835. + return;
  4836. +
  4837. + /* Set x to the predicate to force printing
  4838. + the condition later on. */
  4839. + x = current_insn_predicate;
  4840. +
  4841. + /* Reverse condition if useing bld insn. */
  4842. + if ( GET_CODE (XEXP(current_insn_predicate,0)) == AND )
  4843. + x = reversed_condition (current_insn_predicate);
  4844. + }
  4845. + else if ( code == '!' )
  4846. + {
  4847. + /* Output compare for conditional insn if needed. */
  4848. + rtx new_cond;
  4849. + gcc_assert ( current_insn_predicate != NULL_RTX );
  4850. + new_cond = avr32_output_cmp(current_insn_predicate,
  4851. + GET_MODE(XEXP(current_insn_predicate,0)),
  4852. + XEXP(current_insn_predicate,0),
  4853. + XEXP(current_insn_predicate,1));
  4854. +
  4855. + /* Check if the new condition is a special avr32 condition
  4856. + specified using UNSPECs. If so we must handle it differently. */
  4857. + if ( GET_CODE (new_cond) == UNSPEC )
  4858. + {
  4859. + current_insn_predicate =
  4860. + gen_rtx_UNSPEC (CCmode,
  4861. + gen_rtvec (2,
  4862. + XEXP(current_insn_predicate,0),
  4863. + XEXP(current_insn_predicate,1)),
  4864. + XINT (new_cond, 1));
  4865. + }
  4866. + else
  4867. + {
  4868. + PUT_CODE(current_insn_predicate, GET_CODE(new_cond));
  4869. + }
  4870. + return;
  4871. + }
  4872. +
  4873. + switch (GET_CODE (x))
  4874. + {
  4875. + case UNSPEC:
  4876. + switch (XINT (x, 1))
  4877. + {
  4878. + case UNSPEC_COND_PL:
  4879. + if (code == 'i')
  4880. + fputs ("mi", stream);
  4881. + else
  4882. + fputs ("pl", stream);
  4883. + break;
  4884. + case UNSPEC_COND_MI:
  4885. + if (code == 'i')
  4886. + fputs ("pl", stream);
  4887. + else
  4888. + fputs ("mi", stream);
  4889. + break;
  4890. + default:
  4891. + error = 1;
  4892. + }
  4893. + break;
  4894. + case EQ:
  4895. + if (code == 'i')
  4896. + fputs ("ne", stream);
  4897. + else
  4898. + fputs ("eq", stream);
  4899. + break;
  4900. + case NE:
  4901. + if (code == 'i')
  4902. + fputs ("eq", stream);
  4903. + else
  4904. + fputs ("ne", stream);
  4905. + break;
  4906. + case GT:
  4907. + if (code == 'i')
  4908. + fputs ("le", stream);
  4909. + else
  4910. + fputs ("gt", stream);
  4911. + break;
  4912. + case GTU:
  4913. + if (code == 'i')
  4914. + fputs ("ls", stream);
  4915. + else
  4916. + fputs ("hi", stream);
  4917. + break;
  4918. + case LT:
  4919. + if (code == 'i')
  4920. + fputs ("ge", stream);
  4921. + else
  4922. + fputs ("lt", stream);
  4923. + break;
  4924. + case LTU:
  4925. + if (code == 'i')
  4926. + fputs ("hs", stream);
  4927. + else
  4928. + fputs ("lo", stream);
  4929. + break;
  4930. + case GE:
  4931. + if (code == 'i')
  4932. + fputs ("lt", stream);
  4933. + else
  4934. + fputs ("ge", stream);
  4935. + break;
  4936. + case GEU:
  4937. + if (code == 'i')
  4938. + fputs ("lo", stream);
  4939. + else
  4940. + fputs ("hs", stream);
  4941. + break;
  4942. + case LE:
  4943. + if (code == 'i')
  4944. + fputs ("gt", stream);
  4945. + else
  4946. + fputs ("le", stream);
  4947. + break;
  4948. + case LEU:
  4949. + if (code == 'i')
  4950. + fputs ("hi", stream);
  4951. + else
  4952. + fputs ("ls", stream);
  4953. + break;
  4954. + case CONST_INT:
  4955. + {
  4956. + HOST_WIDE_INT value = INTVAL (x);
  4957. +
  4958. + switch (code)
  4959. + {
  4960. + case 'm':
  4961. + if ( HOST_BITS_PER_WIDE_INT > BITS_PER_WORD )
  4962. + {
  4963. + /* A const_int can be used to represent DImode constants. */
  4964. + value >>= BITS_PER_WORD;
  4965. + }
  4966. + /* We might get a const_int immediate for setting a DI register,
  4967. + we then must then return the correct sign extended DI. The most
  4968. + significant word is just a sign extension. */
  4969. + else if (value < 0)
  4970. + value = -1;
  4971. + else
  4972. + value = 0;
  4973. + break;
  4974. + case 'i':
  4975. + value++;
  4976. + break;
  4977. + case 'p':
  4978. + {
  4979. + /* Set to bit position of first bit set in immediate */
  4980. + int i, bitpos = 32;
  4981. + for (i = 0; i < 32; i++)
  4982. + if (value & (1 << i))
  4983. + {
  4984. + bitpos = i;
  4985. + break;
  4986. + }
  4987. + value = bitpos;
  4988. + }
  4989. + break;
  4990. + case 'z':
  4991. + {
  4992. + /* Set to bit position of first bit cleared in immediate */
  4993. + int i, bitpos = 32;
  4994. + for (i = 0; i < 32; i++)
  4995. + if (!(value & (1 << i)))
  4996. + {
  4997. + bitpos = i;
  4998. + break;
  4999. + }
  5000. + value = bitpos;
  5001. + }
  5002. + break;
  5003. + case 'r':
  5004. + {
  5005. + /* Reglist 8 */
  5006. + char op[50];
  5007. + op[0] = '\0';
  5008. +
  5009. + if (value & 0x01)
  5010. + strcpy (op, "r0-r3");
  5011. + if (value & 0x02)
  5012. + strlen (op) ? strcat (op, ", r4-r7") : strcpy (op,"r4-r7");
  5013. + if (value & 0x04)
  5014. + strlen (op) ? strcat (op, ", r8-r9") : strcpy (op,"r8-r9");
  5015. + if (value & 0x08)
  5016. + strlen (op) ? strcat (op, ", r10") : strcpy (op,"r10");
  5017. + if (value & 0x10)
  5018. + strlen (op) ? strcat (op, ", r11") : strcpy (op,"r11");
  5019. + if (value & 0x20)
  5020. + strlen (op) ? strcat (op, ", r12") : strcpy (op,"r12");
  5021. + if (value & 0x40)
  5022. + strlen (op) ? strcat (op, ", lr") : strcpy (op, "lr");
  5023. + if (value & 0x80)
  5024. + strlen (op) ? strcat (op, ", pc") : strcpy (op, "pc");
  5025. +
  5026. + fputs (op, stream);
  5027. + return;
  5028. + }
  5029. + case 's':
  5030. + {
  5031. + /* Reglist 16 */
  5032. + char reglist16_string[100];
  5033. + int i;
  5034. + bool first_reg = true;
  5035. + reglist16_string[0] = '\0';
  5036. +
  5037. + for (i = 0; i < 16; ++i)
  5038. + {
  5039. + if (value & (1 << i))
  5040. + {
  5041. + first_reg == true ? first_reg = false : strcat(reglist16_string,", ");
  5042. + strcat(reglist16_string,reg_names[INTERNAL_REGNUM(i)]);
  5043. + }
  5044. + }
  5045. + fputs (reglist16_string, stream);
  5046. + return;
  5047. + }
  5048. + case 'h':
  5049. + /* Print halfword part of word */
  5050. + fputs (value ? "b" : "t", stream);
  5051. + return;
  5052. + }
  5053. +
  5054. + /* Print Value */
  5055. + fprintf (stream, "%d", value);
  5056. + break;
  5057. + }
  5058. + case CONST_DOUBLE:
  5059. + {
  5060. + HOST_WIDE_INT hi, lo;
  5061. + if (SCALAR_FLOAT_MODE_P (GET_MODE (x)))
  5062. + {
  5063. + HOST_WIDE_INT target_float[2];
  5064. + hi = lo = 0;
  5065. + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (x),
  5066. + GET_MODE (x));
  5067. + /* For doubles the most significant part starts at index 0. */
  5068. + if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
  5069. + {
  5070. + hi = target_float[0];
  5071. + lo = target_float[1];
  5072. + }
  5073. + else
  5074. + {
  5075. + lo = target_float[0];
  5076. + }
  5077. + }
  5078. + else
  5079. + {
  5080. + hi = CONST_DOUBLE_HIGH (x);
  5081. + lo = CONST_DOUBLE_LOW (x);
  5082. + }
  5083. +
  5084. + if (code == 'm')
  5085. + fprintf (stream, "%ld", hi);
  5086. + else
  5087. + fprintf (stream, "%ld", lo);
  5088. +
  5089. + break;
  5090. + }
  5091. + case CONST:
  5092. + output_addr_const (stream, XEXP (XEXP (x, 0), 0));
  5093. + fprintf (stream, "+%ld", INTVAL (XEXP (XEXP (x, 0), 1)));
  5094. + break;
  5095. + case REG:
  5096. + /* Swap register name if the register is DImode or DFmode. */
  5097. + if (GET_MODE (x) == DImode || GET_MODE (x) == DFmode)
  5098. + {
  5099. + /* Double register must have an even numbered address */
  5100. + gcc_assert (!(REGNO (x) % 2));
  5101. + if (code == 'm')
  5102. + fputs (reg_names[true_regnum (x)], stream);
  5103. + else
  5104. + fputs (reg_names[true_regnum (x) + 1], stream);
  5105. + }
  5106. + else if (GET_MODE (x) == TImode)
  5107. + {
  5108. + switch (code)
  5109. + {
  5110. + case 'T':
  5111. + fputs (reg_names[true_regnum (x)], stream);
  5112. + break;
  5113. + case 'U':
  5114. + fputs (reg_names[true_regnum (x) + 1], stream);
  5115. + break;
  5116. + case 'L':
  5117. + fputs (reg_names[true_regnum (x) + 2], stream);
  5118. + break;
  5119. + case 'B':
  5120. + fputs (reg_names[true_regnum (x) + 3], stream);
  5121. + break;
  5122. + default:
  5123. + fprintf (stream, "%s, %s, %s, %s",
  5124. + reg_names[true_regnum (x) + 3],
  5125. + reg_names[true_regnum (x) + 2],
  5126. + reg_names[true_regnum (x) + 1],
  5127. + reg_names[true_regnum (x)]);
  5128. + break;
  5129. + }
  5130. + }
  5131. + else
  5132. + {
  5133. + fputs (reg_names[true_regnum (x)], stream);
  5134. + }
  5135. + break;
  5136. + case CODE_LABEL:
  5137. + case LABEL_REF:
  5138. + case SYMBOL_REF:
  5139. + output_addr_const (stream, x);
  5140. + break;
  5141. + case MEM:
  5142. + switch (GET_CODE (XEXP (x, 0)))
  5143. + {
  5144. + case LABEL_REF:
  5145. + case SYMBOL_REF:
  5146. + output_addr_const (stream, XEXP (x, 0));
  5147. + break;
  5148. + case MEM:
  5149. + switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
  5150. + {
  5151. + case SYMBOL_REF:
  5152. + output_addr_const (stream, XEXP (XEXP (x, 0), 0));
  5153. + break;
  5154. + default:
  5155. + error = 1;
  5156. + break;
  5157. + }
  5158. + break;
  5159. + case REG:
  5160. + avr32_print_operand (stream, XEXP (x, 0), 0);
  5161. + if (code != 'p')
  5162. + fputs ("[0]", stream);
  5163. + break;
  5164. + case PRE_DEC:
  5165. + fputs ("--", stream);
  5166. + avr32_print_operand (stream, XEXP (XEXP (x, 0), 0), 0);
  5167. + break;
  5168. + case POST_INC:
  5169. + avr32_print_operand (stream, XEXP (XEXP (x, 0), 0), 0);
  5170. + fputs ("++", stream);
  5171. + break;
  5172. + case PLUS:
  5173. + {
  5174. + rtx op0 = XEXP (XEXP (x, 0), 0);
  5175. + rtx op1 = XEXP (XEXP (x, 0), 1);
  5176. + rtx base = NULL_RTX, offset = NULL_RTX;
  5177. +
  5178. + if (avr32_address_register_rtx_p (op0, 1))
  5179. + {
  5180. + base = op0;
  5181. + offset = op1;
  5182. + }
  5183. + else if (avr32_address_register_rtx_p (op1, 1))
  5184. + {
  5185. + /* Operands are switched. */
  5186. + base = op1;
  5187. + offset = op0;
  5188. + }
  5189. +
  5190. + gcc_assert (base && offset
  5191. + && avr32_address_register_rtx_p (base, 1)
  5192. + && avr32_legitimate_index_p (GET_MODE (x), offset,
  5193. + 1));
  5194. +
  5195. + avr32_print_operand (stream, base, 0);
  5196. + fputs ("[", stream);
  5197. + avr32_print_operand (stream, offset, 0);
  5198. + fputs ("]", stream);
  5199. + break;
  5200. + }
  5201. + case CONST:
  5202. + output_addr_const (stream, XEXP (XEXP (XEXP (x, 0), 0), 0));
  5203. + fprintf (stream, " + %ld",
  5204. + INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)));
  5205. + break;
  5206. + case CONST_INT:
  5207. + avr32_print_operand (stream, XEXP (x, 0), 0);
  5208. + break;
  5209. + default:
  5210. + error = 1;
  5211. + }
  5212. + break;
  5213. + case MULT:
  5214. + {
  5215. + int value = INTVAL (XEXP (x, 1));
  5216. +
  5217. + /* Convert immediate in multiplication into a shift immediate */
  5218. + switch (value)
  5219. + {
  5220. + case 2:
  5221. + value = 1;
  5222. + break;
  5223. + case 4:
  5224. + value = 2;
  5225. + break;
  5226. + case 8:
  5227. + value = 3;
  5228. + break;
  5229. + default:
  5230. + value = 0;
  5231. + }
  5232. + fprintf (stream, "%s << %i", reg_names[true_regnum (XEXP (x, 0))],
  5233. + value);
  5234. + break;
  5235. + }
  5236. + case ASHIFT:
  5237. + if (GET_CODE (XEXP (x, 1)) == CONST_INT)
  5238. + fprintf (stream, "%s << %i", reg_names[true_regnum (XEXP (x, 0))],
  5239. + (int) INTVAL (XEXP (x, 1)));
  5240. + else if (REG_P (XEXP (x, 1)))
  5241. + fprintf (stream, "%s << %s", reg_names[true_regnum (XEXP (x, 0))],
  5242. + reg_names[true_regnum (XEXP (x, 1))]);
  5243. + else
  5244. + {
  5245. + error = 1;
  5246. + }
  5247. + break;
  5248. + case LSHIFTRT:
  5249. + if (GET_CODE (XEXP (x, 1)) == CONST_INT)
  5250. + fprintf (stream, "%s >> %i", reg_names[true_regnum (XEXP (x, 0))],
  5251. + (int) INTVAL (XEXP (x, 1)));
  5252. + else if (REG_P (XEXP (x, 1)))
  5253. + fprintf (stream, "%s >> %s", reg_names[true_regnum (XEXP (x, 0))],
  5254. + reg_names[true_regnum (XEXP (x, 1))]);
  5255. + else
  5256. + {
  5257. + error = 1;
  5258. + }
  5259. + fprintf (stream, ">>");
  5260. + break;
  5261. + case PARALLEL:
  5262. + {
  5263. + /* Load store multiple */
  5264. + int i;
  5265. + int count = XVECLEN (x, 0);
  5266. + int reglist16 = 0;
  5267. + char reglist16_string[100];
  5268. +
  5269. + for (i = 0; i < count; ++i)
  5270. + {
  5271. + rtx vec_elm = XVECEXP (x, 0, i);
  5272. + if (GET_MODE (vec_elm) != SET)
  5273. + {
  5274. + debug_rtx (vec_elm);
  5275. + internal_error ("Unknown element in parallel expression!");
  5276. + }
  5277. + if (GET_MODE (XEXP (vec_elm, 0)) == REG)
  5278. + {
  5279. + /* Load multiple */
  5280. + reglist16 |= 1 << ASM_REGNUM (REGNO (XEXP (vec_elm, 0)));
  5281. + }
  5282. + else
  5283. + {
  5284. + /* Store multiple */
  5285. + reglist16 |= 1 << ASM_REGNUM (REGNO (XEXP (vec_elm, 1)));
  5286. + }
  5287. + }
  5288. +
  5289. + avr32_make_reglist16 (reglist16, reglist16_string);
  5290. + fputs (reglist16_string, stream);
  5291. +
  5292. + break;
  5293. + }
  5294. +
  5295. + case PLUS:
  5296. + {
  5297. + rtx op0 = XEXP (x, 0);
  5298. + rtx op1 = XEXP (x, 1);
  5299. + rtx base = NULL_RTX, offset = NULL_RTX;
  5300. +
  5301. + if (avr32_address_register_rtx_p (op0, 1))
  5302. + {
  5303. + base = op0;
  5304. + offset = op1;
  5305. + }
  5306. + else if (avr32_address_register_rtx_p (op1, 1))
  5307. + {
  5308. + /* Operands are switched. */
  5309. + base = op1;
  5310. + offset = op0;
  5311. + }
  5312. +
  5313. + gcc_assert (base && offset
  5314. + && avr32_address_register_rtx_p (base, 1)
  5315. + && avr32_legitimate_index_p (GET_MODE (x), offset, 1));
  5316. +
  5317. + avr32_print_operand (stream, base, 0);
  5318. + fputs ("[", stream);
  5319. + avr32_print_operand (stream, offset, 0);
  5320. + fputs ("]", stream);
  5321. + break;
  5322. + }
  5323. +
  5324. + default:
  5325. + error = 1;
  5326. + }
  5327. +
  5328. + if (error)
  5329. + {
  5330. + debug_rtx (x);
  5331. + internal_error ("Illegal expression for avr32_print_operand");
  5332. + }
  5333. +}
  5334. +
  5335. +rtx
  5336. +avr32_get_note_reg_equiv (rtx insn)
  5337. +{
  5338. + rtx note;
  5339. +
  5340. + note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
  5341. +
  5342. + if (note != NULL_RTX)
  5343. + return XEXP (note, 0);
  5344. + else
  5345. + return NULL_RTX;
  5346. +}
  5347. +
  5348. +
  5349. +/*
  5350. + Outputs to stdio stream stream the assembler syntax for an instruction
  5351. + operand that is a memory reference whose address is x. x is an RTL
  5352. + expression.
  5353. +
  5354. + ToDo: fixme.
  5355. +*/
  5356. +void
  5357. +avr32_print_operand_address (FILE * stream, rtx x)
  5358. +{
  5359. + fprintf (stream, "(%d) /* address */", REGNO (x));
  5360. +}
  5361. +
  5362. +
  5363. +/* Return true if _GLOBAL_OFFSET_TABLE_ symbol is mentioned. */
  5364. +bool
  5365. +avr32_got_mentioned_p (rtx addr)
  5366. +{
  5367. + if (GET_CODE (addr) == MEM)
  5368. + addr = XEXP (addr, 0);
  5369. + while (GET_CODE (addr) == CONST)
  5370. + addr = XEXP (addr, 0);
  5371. + if (GET_CODE (addr) == SYMBOL_REF)
  5372. + {
  5373. + return streq (XSTR (addr, 0), "_GLOBAL_OFFSET_TABLE_");
  5374. + }
  5375. + if (GET_CODE (addr) == PLUS || GET_CODE (addr) == MINUS)
  5376. + {
  5377. + bool l1, l2;
  5378. +
  5379. + l1 = avr32_got_mentioned_p (XEXP (addr, 0));
  5380. + l2 = avr32_got_mentioned_p (XEXP (addr, 1));
  5381. + return l1 || l2;
  5382. + }
  5383. + return false;
  5384. +}
  5385. +
  5386. +
  5387. +/* Find the symbol in an address expression. */
  5388. +rtx
  5389. +avr32_find_symbol (rtx addr)
  5390. +{
  5391. + if (GET_CODE (addr) == MEM)
  5392. + addr = XEXP (addr, 0);
  5393. +
  5394. + while (GET_CODE (addr) == CONST)
  5395. + addr = XEXP (addr, 0);
  5396. +
  5397. + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
  5398. + return addr;
  5399. + if (GET_CODE (addr) == PLUS)
  5400. + {
  5401. + rtx l1, l2;
  5402. +
  5403. + l1 = avr32_find_symbol (XEXP (addr, 0));
  5404. + l2 = avr32_find_symbol (XEXP (addr, 1));
  5405. + if (l1 != NULL_RTX && l2 == NULL_RTX)
  5406. + return l1;
  5407. + else if (l1 == NULL_RTX && l2 != NULL_RTX)
  5408. + return l2;
  5409. + }
  5410. +
  5411. + return NULL_RTX;
  5412. +}
  5413. +
  5414. +
  5415. +/* Routines for manipulation of the constant pool. */
  5416. +
  5417. +/* AVR32 instructions cannot load a large constant directly into a
  5418. + register; they have to come from a pc relative load. The constant
  5419. + must therefore be placed in the addressable range of the pc
  5420. + relative load. Depending on the precise pc relative load
  5421. + instruction the range is somewhere between 256 bytes and 4k. This
  5422. + means that we often have to dump a constant inside a function, and
  5423. + generate code to branch around it.
  5424. +
  5425. + It is important to minimize this, since the branches will slow
  5426. + things down and make the code larger.
  5427. +
  5428. + Normally we can hide the table after an existing unconditional
  5429. + branch so that there is no interruption of the flow, but in the
  5430. + worst case the code looks like this:
  5431. +
  5432. + lddpc rn, L1
  5433. + ...
  5434. + rjmp L2
  5435. + align
  5436. + L1: .long value
  5437. + L2:
  5438. + ...
  5439. +
  5440. + lddpc rn, L3
  5441. + ...
  5442. + rjmp L4
  5443. + align
  5444. + L3: .long value
  5445. + L4:
  5446. + ...
  5447. +
  5448. + We fix this by performing a scan after scheduling, which notices
  5449. + which instructions need to have their operands fetched from the
  5450. + constant table and builds the table.
  5451. +
  5452. + The algorithm starts by building a table of all the constants that
  5453. + need fixing up and all the natural barriers in the function (places
  5454. + where a constant table can be dropped without breaking the flow).
  5455. + For each fixup we note how far the pc-relative replacement will be
  5456. + able to reach and the offset of the instruction into the function.
  5457. +
  5458. + Having built the table we then group the fixes together to form
  5459. + tables that are as large as possible (subject to addressing
  5460. + constraints) and emit each table of constants after the last
  5461. + barrier that is within range of all the instructions in the group.
  5462. + If a group does not contain a barrier, then we forcibly create one
  5463. + by inserting a jump instruction into the flow. Once the table has
  5464. + been inserted, the insns are then modified to reference the
  5465. + relevant entry in the pool.
  5466. +
  5467. + Possible enhancements to the algorithm (not implemented) are:
  5468. +
  5469. + 1) For some processors and object formats, there may be benefit in
  5470. + aligning the pools to the start of cache lines; this alignment
  5471. + would need to be taken into account when calculating addressability
  5472. + of a pool. */
  5473. +
  5474. +/* These typedefs are located at the start of this file, so that
  5475. + they can be used in the prototypes there. This comment is to
  5476. + remind readers of that fact so that the following structures
  5477. + can be understood more easily.
  5478. +
  5479. + typedef struct minipool_node Mnode;
  5480. + typedef struct minipool_fixup Mfix; */
  5481. +
  5482. +struct minipool_node
  5483. +{
  5484. + /* Doubly linked chain of entries. */
  5485. + Mnode *next;
  5486. + Mnode *prev;
  5487. + /* The maximum offset into the code that this entry can be placed. While
  5488. + pushing fixes for forward references, all entries are sorted in order of
  5489. + increasing max_address. */
  5490. + HOST_WIDE_INT max_address;
  5491. + /* Similarly for an entry inserted for a backwards ref. */
  5492. + HOST_WIDE_INT min_address;
  5493. + /* The number of fixes referencing this entry. This can become zero if we
  5494. + "unpush" an entry. In this case we ignore the entry when we come to
  5495. + emit the code. */
  5496. + int refcount;
  5497. + /* The offset from the start of the minipool. */
  5498. + HOST_WIDE_INT offset;
  5499. + /* The value in table. */
  5500. + rtx value;
  5501. + /* The mode of value. */
  5502. + enum machine_mode mode;
  5503. + /* The size of the value. */
  5504. + int fix_size;
  5505. +};
  5506. +
  5507. +
  5508. +struct minipool_fixup
  5509. +{
  5510. + Mfix *next;
  5511. + rtx insn;
  5512. + HOST_WIDE_INT address;
  5513. + rtx *loc;
  5514. + enum machine_mode mode;
  5515. + int fix_size;
  5516. + rtx value;
  5517. + Mnode *minipool;
  5518. + HOST_WIDE_INT forwards;
  5519. + HOST_WIDE_INT backwards;
  5520. +};
  5521. +
  5522. +
  5523. +/* Fixes less than a word need padding out to a word boundary. */
  5524. +#define MINIPOOL_FIX_SIZE(mode, value) \
  5525. + (IS_FORCE_MINIPOOL(value) ? 0 : \
  5526. + (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4))
  5527. +
  5528. +#define IS_FORCE_MINIPOOL(x) \
  5529. + (GET_CODE(x) == UNSPEC && \
  5530. + XINT(x, 1) == UNSPEC_FORCE_MINIPOOL)
  5531. +
  5532. +static Mnode *minipool_vector_head;
  5533. +static Mnode *minipool_vector_tail;
  5534. +
  5535. +/* The linked list of all minipool fixes required for this function. */
  5536. +Mfix *minipool_fix_head;
  5537. +Mfix *minipool_fix_tail;
  5538. +/* The fix entry for the current minipool, once it has been placed. */
  5539. +Mfix *minipool_barrier;
  5540. +
  5541. +
  5542. +/* Determines if INSN is the start of a jump table. Returns the end
  5543. + of the TABLE or NULL_RTX. */
  5544. +static rtx
  5545. +is_jump_table (rtx insn)
  5546. +{
  5547. + rtx table;
  5548. +
  5549. + if (GET_CODE (insn) == JUMP_INSN
  5550. + && JUMP_LABEL (insn) != NULL
  5551. + && ((table = next_real_insn (JUMP_LABEL (insn)))
  5552. + == next_real_insn (insn))
  5553. + && table != NULL
  5554. + && GET_CODE (table) == JUMP_INSN
  5555. + && (GET_CODE (PATTERN (table)) == ADDR_VEC
  5556. + || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
  5557. + return table;
  5558. +
  5559. + return NULL_RTX;
  5560. +}
  5561. +
  5562. +
  5563. +static HOST_WIDE_INT
  5564. +get_jump_table_size (rtx insn)
  5565. +{
  5566. + /* ADDR_VECs only take room if read-only data does into the text section. */
  5567. + if (JUMP_TABLES_IN_TEXT_SECTION
  5568. +#if !defined(READONLY_DATA_SECTION_ASM_OP)
  5569. + || 1
  5570. +#endif
  5571. + )
  5572. + {
  5573. + rtx body = PATTERN (insn);
  5574. + int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
  5575. +
  5576. + return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
  5577. + }
  5578. +
  5579. + return 0;
  5580. +}
  5581. +
  5582. +
  5583. +/* Move a minipool fix MP from its current location to before MAX_MP.
  5584. + If MAX_MP is NULL, then MP doesn't need moving, but the addressing
  5585. + constraints may need updating. */
  5586. +static Mnode *
  5587. +move_minipool_fix_forward_ref (Mnode * mp, Mnode * max_mp,
  5588. + HOST_WIDE_INT max_address)
  5589. +{
  5590. + /* This should never be true and the code below assumes these are
  5591. + different. */
  5592. + if (mp == max_mp)
  5593. + abort ();
  5594. +
  5595. + if (max_mp == NULL)
  5596. + {
  5597. + if (max_address < mp->max_address)
  5598. + mp->max_address = max_address;
  5599. + }
  5600. + else
  5601. + {
  5602. + if (max_address > max_mp->max_address - mp->fix_size)
  5603. + mp->max_address = max_mp->max_address - mp->fix_size;
  5604. + else
  5605. + mp->max_address = max_address;
  5606. +
  5607. + /* Unlink MP from its current position. Since max_mp is non-null,
  5608. + mp->prev must be non-null. */
  5609. + mp->prev->next = mp->next;
  5610. + if (mp->next != NULL)
  5611. + mp->next->prev = mp->prev;
  5612. + else
  5613. + minipool_vector_tail = mp->prev;
  5614. +
  5615. + /* Re-insert it before MAX_MP. */
  5616. + mp->next = max_mp;
  5617. + mp->prev = max_mp->prev;
  5618. + max_mp->prev = mp;
  5619. +
  5620. + if (mp->prev != NULL)
  5621. + mp->prev->next = mp;
  5622. + else
  5623. + minipool_vector_head = mp;
  5624. + }
  5625. +
  5626. + /* Save the new entry. */
  5627. + max_mp = mp;
  5628. +
  5629. + /* Scan over the preceding entries and adjust their addresses as required.
  5630. + */
  5631. + while (mp->prev != NULL
  5632. + && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
  5633. + {
  5634. + mp->prev->max_address = mp->max_address - mp->prev->fix_size;
  5635. + mp = mp->prev;
  5636. + }
  5637. +
  5638. + return max_mp;
  5639. +}
  5640. +
  5641. +
  5642. +/* Add a constant to the minipool for a forward reference. Returns the
  5643. + node added or NULL if the constant will not fit in this pool. */
  5644. +static Mnode *
  5645. +add_minipool_forward_ref (Mfix * fix)
  5646. +{
  5647. + /* If set, max_mp is the first pool_entry that has a lower constraint than
  5648. + the one we are trying to add. */
  5649. + Mnode *max_mp = NULL;
  5650. + HOST_WIDE_INT max_address = fix->address + fix->forwards;
  5651. + Mnode *mp;
  5652. +
  5653. + /* If this fix's address is greater than the address of the first entry,
  5654. + then we can't put the fix in this pool. We subtract the size of the
  5655. + current fix to ensure that if the table is fully packed we still have
  5656. + enough room to insert this value by suffling the other fixes forwards. */
  5657. + if (minipool_vector_head &&
  5658. + fix->address >= minipool_vector_head->max_address - fix->fix_size)
  5659. + return NULL;
  5660. +
  5661. + /* Scan the pool to see if a constant with the same value has already been
  5662. + added. While we are doing this, also note the location where we must
  5663. + insert the constant if it doesn't already exist. */
  5664. + for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
  5665. + {
  5666. + if (GET_CODE (fix->value) == GET_CODE (mp->value)
  5667. + && fix->mode == mp->mode
  5668. + && (GET_CODE (fix->value) != CODE_LABEL
  5669. + || (CODE_LABEL_NUMBER (fix->value)
  5670. + == CODE_LABEL_NUMBER (mp->value)))
  5671. + && rtx_equal_p (fix->value, mp->value))
  5672. + {
  5673. + /* More than one fix references this entry. */
  5674. + mp->refcount++;
  5675. + return move_minipool_fix_forward_ref (mp, max_mp, max_address);
  5676. + }
  5677. +
  5678. + /* Note the insertion point if necessary. */
  5679. + if (max_mp == NULL && mp->max_address > max_address)
  5680. + max_mp = mp;
  5681. +
  5682. + }
  5683. +
  5684. + /* The value is not currently in the minipool, so we need to create a new
  5685. + entry for it. If MAX_MP is NULL, the entry will be put on the end of
  5686. + the list since the placement is less constrained than any existing
  5687. + entry. Otherwise, we insert the new fix before MAX_MP and, if
  5688. + necessary, adjust the constraints on the other entries. */
  5689. + mp = xmalloc (sizeof (*mp));
  5690. + mp->fix_size = fix->fix_size;
  5691. + mp->mode = fix->mode;
  5692. + mp->value = fix->value;
  5693. + mp->refcount = 1;
  5694. + /* Not yet required for a backwards ref. */
  5695. + mp->min_address = -65536;
  5696. +
  5697. + if (max_mp == NULL)
  5698. + {
  5699. + mp->max_address = max_address;
  5700. + mp->next = NULL;
  5701. + mp->prev = minipool_vector_tail;
  5702. +
  5703. + if (mp->prev == NULL)
  5704. + {
  5705. + minipool_vector_head = mp;
  5706. + minipool_vector_label = gen_label_rtx ();
  5707. + }
  5708. + else
  5709. + mp->prev->next = mp;
  5710. +
  5711. + minipool_vector_tail = mp;
  5712. + }
  5713. + else
  5714. + {
  5715. + if (max_address > max_mp->max_address - mp->fix_size)
  5716. + mp->max_address = max_mp->max_address - mp->fix_size;
  5717. + else
  5718. + mp->max_address = max_address;
  5719. +
  5720. + mp->next = max_mp;
  5721. + mp->prev = max_mp->prev;
  5722. + max_mp->prev = mp;
  5723. + if (mp->prev != NULL)
  5724. + mp->prev->next = mp;
  5725. + else
  5726. + minipool_vector_head = mp;
  5727. + }
  5728. +
  5729. + /* Save the new entry. */
  5730. + max_mp = mp;
  5731. +
  5732. + /* Scan over the preceding entries and adjust their addresses as required.
  5733. + */
  5734. + while (mp->prev != NULL
  5735. + && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
  5736. + {
  5737. + mp->prev->max_address = mp->max_address - mp->prev->fix_size;
  5738. + mp = mp->prev;
  5739. + }
  5740. +
  5741. + return max_mp;
  5742. +}
  5743. +
  5744. +
  5745. +static Mnode *
  5746. +move_minipool_fix_backward_ref (Mnode * mp, Mnode * min_mp,
  5747. + HOST_WIDE_INT min_address)
  5748. +{
  5749. + HOST_WIDE_INT offset;
  5750. +
  5751. + /* This should never be true, and the code below assumes these are
  5752. + different. */
  5753. + if (mp == min_mp)
  5754. + abort ();
  5755. +
  5756. + if (min_mp == NULL)
  5757. + {
  5758. + if (min_address > mp->min_address)
  5759. + mp->min_address = min_address;
  5760. + }
  5761. + else
  5762. + {
  5763. + /* We will adjust this below if it is too loose. */
  5764. + mp->min_address = min_address;
  5765. +
  5766. + /* Unlink MP from its current position. Since min_mp is non-null,
  5767. + mp->next must be non-null. */
  5768. + mp->next->prev = mp->prev;
  5769. + if (mp->prev != NULL)
  5770. + mp->prev->next = mp->next;
  5771. + else
  5772. + minipool_vector_head = mp->next;
  5773. +
  5774. + /* Reinsert it after MIN_MP. */
  5775. + mp->prev = min_mp;
  5776. + mp->next = min_mp->next;
  5777. + min_mp->next = mp;
  5778. + if (mp->next != NULL)
  5779. + mp->next->prev = mp;
  5780. + else
  5781. + minipool_vector_tail = mp;
  5782. + }
  5783. +
  5784. + min_mp = mp;
  5785. +
  5786. + offset = 0;
  5787. + for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
  5788. + {
  5789. + mp->offset = offset;
  5790. + if (mp->refcount > 0)
  5791. + offset += mp->fix_size;
  5792. +
  5793. + if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
  5794. + mp->next->min_address = mp->min_address + mp->fix_size;
  5795. + }
  5796. +
  5797. + return min_mp;
  5798. +}
  5799. +
  5800. +
  5801. +/* Add a constant to the minipool for a backward reference. Returns the
  5802. + node added or NULL if the constant will not fit in this pool.
  5803. +
  5804. + Note that the code for insertion for a backwards reference can be
  5805. + somewhat confusing because the calculated offsets for each fix do
  5806. + not take into account the size of the pool (which is still under
  5807. + construction. */
  5808. +static Mnode *
  5809. +add_minipool_backward_ref (Mfix * fix)
  5810. +{
  5811. + /* If set, min_mp is the last pool_entry that has a lower constraint than
  5812. + the one we are trying to add. */
  5813. + Mnode *min_mp = NULL;
  5814. + /* This can be negative, since it is only a constraint. */
  5815. + HOST_WIDE_INT min_address = fix->address - fix->backwards;
  5816. + Mnode *mp;
  5817. +
  5818. + /* If we can't reach the current pool from this insn, or if we can't insert
  5819. + this entry at the end of the pool without pushing other fixes out of
  5820. + range, then we don't try. This ensures that we can't fail later on. */
  5821. + if (min_address >= minipool_barrier->address
  5822. + || (minipool_vector_tail->min_address + fix->fix_size
  5823. + >= minipool_barrier->address))
  5824. + return NULL;
  5825. +
  5826. + /* Scan the pool to see if a constant with the same value has already been
  5827. + added. While we are doing this, also note the location where we must
  5828. + insert the constant if it doesn't already exist. */
  5829. + for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
  5830. + {
  5831. + if (GET_CODE (fix->value) == GET_CODE (mp->value)
  5832. + && fix->mode == mp->mode
  5833. + && (GET_CODE (fix->value) != CODE_LABEL
  5834. + || (CODE_LABEL_NUMBER (fix->value)
  5835. + == CODE_LABEL_NUMBER (mp->value)))
  5836. + && rtx_equal_p (fix->value, mp->value)
  5837. + /* Check that there is enough slack to move this entry to the end
  5838. + of the table (this is conservative). */
  5839. + && (mp->max_address
  5840. + > (minipool_barrier->address
  5841. + + minipool_vector_tail->offset
  5842. + + minipool_vector_tail->fix_size)))
  5843. + {
  5844. + mp->refcount++;
  5845. + return move_minipool_fix_backward_ref (mp, min_mp, min_address);
  5846. + }
  5847. +
  5848. + if (min_mp != NULL)
  5849. + mp->min_address += fix->fix_size;
  5850. + else
  5851. + {
  5852. + /* Note the insertion point if necessary. */
  5853. + if (mp->min_address < min_address)
  5854. + {
  5855. + min_mp = mp;
  5856. + }
  5857. + else if (mp->max_address
  5858. + < minipool_barrier->address + mp->offset + fix->fix_size)
  5859. + {
  5860. + /* Inserting before this entry would push the fix beyond its
  5861. + maximum address (which can happen if we have re-located a
  5862. + forwards fix); force the new fix to come after it. */
  5863. + min_mp = mp;
  5864. + min_address = mp->min_address + fix->fix_size;
  5865. + }
  5866. + }
  5867. + }
  5868. +
  5869. + /* We need to create a new entry. */
  5870. + mp = xmalloc (sizeof (*mp));
  5871. + mp->fix_size = fix->fix_size;
  5872. + mp->mode = fix->mode;
  5873. + mp->value = fix->value;
  5874. + mp->refcount = 1;
  5875. + mp->max_address = minipool_barrier->address + 65536;
  5876. +
  5877. + mp->min_address = min_address;
  5878. +
  5879. + if (min_mp == NULL)
  5880. + {
  5881. + mp->prev = NULL;
  5882. + mp->next = minipool_vector_head;
  5883. +
  5884. + if (mp->next == NULL)
  5885. + {
  5886. + minipool_vector_tail = mp;
  5887. + minipool_vector_label = gen_label_rtx ();
  5888. + }
  5889. + else
  5890. + mp->next->prev = mp;
  5891. +
  5892. + minipool_vector_head = mp;
  5893. + }
  5894. + else
  5895. + {
  5896. + mp->next = min_mp->next;
  5897. + mp->prev = min_mp;
  5898. + min_mp->next = mp;
  5899. +
  5900. + if (mp->next != NULL)
  5901. + mp->next->prev = mp;
  5902. + else
  5903. + minipool_vector_tail = mp;
  5904. + }
  5905. +
  5906. + /* Save the new entry. */
  5907. + min_mp = mp;
  5908. +
  5909. + if (mp->prev)
  5910. + mp = mp->prev;
  5911. + else
  5912. + mp->offset = 0;
  5913. +
  5914. + /* Scan over the following entries and adjust their offsets. */
  5915. + while (mp->next != NULL)
  5916. + {
  5917. + if (mp->next->min_address < mp->min_address + mp->fix_size)
  5918. + mp->next->min_address = mp->min_address + mp->fix_size;
  5919. +
  5920. + if (mp->refcount)
  5921. + mp->next->offset = mp->offset + mp->fix_size;
  5922. + else
  5923. + mp->next->offset = mp->offset;
  5924. +
  5925. + mp = mp->next;
  5926. + }
  5927. +
  5928. + return min_mp;
  5929. +}
  5930. +
  5931. +
  5932. +static void
  5933. +assign_minipool_offsets (Mfix * barrier)
  5934. +{
  5935. + HOST_WIDE_INT offset = 0;
  5936. + Mnode *mp;
  5937. +
  5938. + minipool_barrier = barrier;
  5939. +
  5940. + for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
  5941. + {
  5942. + mp->offset = offset;
  5943. +
  5944. + if (mp->refcount > 0)
  5945. + offset += mp->fix_size;
  5946. + }
  5947. +}
  5948. +
  5949. +
  5950. +/* Print a symbolic form of X to the debug file, F. */
  5951. +static void
  5952. +avr32_print_value (FILE * f, rtx x)
  5953. +{
  5954. + switch (GET_CODE (x))
  5955. + {
  5956. + case CONST_INT:
  5957. + fprintf (f, "0x%x", (int) INTVAL (x));
  5958. + return;
  5959. +
  5960. + case CONST_DOUBLE:
  5961. + fprintf (f, "<0x%lx,0x%lx>", (long) XWINT (x, 2), (long) XWINT (x, 3));
  5962. + return;
  5963. +
  5964. + case CONST_VECTOR:
  5965. + {
  5966. + int i;
  5967. +
  5968. + fprintf (f, "<");
  5969. + for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
  5970. + {
  5971. + fprintf (f, "0x%x", (int) INTVAL (CONST_VECTOR_ELT (x, i)));
  5972. + if (i < (CONST_VECTOR_NUNITS (x) - 1))
  5973. + fputc (',', f);
  5974. + }
  5975. + fprintf (f, ">");
  5976. + }
  5977. + return;
  5978. +
  5979. + case CONST_STRING:
  5980. + fprintf (f, "\"%s\"", XSTR (x, 0));
  5981. + return;
  5982. +
  5983. + case SYMBOL_REF:
  5984. + fprintf (f, "`%s'", XSTR (x, 0));
  5985. + return;
  5986. +
  5987. + case LABEL_REF:
  5988. + fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
  5989. + return;
  5990. +
  5991. + case CONST:
  5992. + avr32_print_value (f, XEXP (x, 0));
  5993. + return;
  5994. +
  5995. + case PLUS:
  5996. + avr32_print_value (f, XEXP (x, 0));
  5997. + fprintf (f, "+");
  5998. + avr32_print_value (f, XEXP (x, 1));
  5999. + return;
  6000. +
  6001. + case PC:
  6002. + fprintf (f, "pc");
  6003. + return;
  6004. +
  6005. + default:
  6006. + fprintf (f, "????");
  6007. + return;
  6008. + }
  6009. +}
  6010. +
  6011. +
  6012. +int
  6013. +is_minipool_label (rtx label)
  6014. +{
  6015. + minipool_labels *cur_mp_label = cfun->machine->minipool_label_head;
  6016. +
  6017. + if (GET_CODE (label) != CODE_LABEL)
  6018. + return FALSE;
  6019. +
  6020. + while (cur_mp_label)
  6021. + {
  6022. + if (CODE_LABEL_NUMBER (label)
  6023. + == CODE_LABEL_NUMBER (cur_mp_label->label))
  6024. + return TRUE;
  6025. + cur_mp_label = cur_mp_label->next;
  6026. + }
  6027. + return FALSE;
  6028. +}
  6029. +
  6030. +
  6031. +static void
  6032. +new_minipool_label (rtx label)
  6033. +{
  6034. + if (!cfun->machine->minipool_label_head)
  6035. + {
  6036. + cfun->machine->minipool_label_head =
  6037. + ggc_alloc (sizeof (minipool_labels));
  6038. + cfun->machine->minipool_label_tail = cfun->machine->minipool_label_head;
  6039. + cfun->machine->minipool_label_head->label = label;
  6040. + cfun->machine->minipool_label_head->next = 0;
  6041. + cfun->machine->minipool_label_head->prev = 0;
  6042. + }
  6043. + else
  6044. + {
  6045. + cfun->machine->minipool_label_tail->next =
  6046. + ggc_alloc (sizeof (minipool_labels));
  6047. + cfun->machine->minipool_label_tail->next->label = label;
  6048. + cfun->machine->minipool_label_tail->next->next = 0;
  6049. + cfun->machine->minipool_label_tail->next->prev =
  6050. + cfun->machine->minipool_label_tail;
  6051. + cfun->machine->minipool_label_tail =
  6052. + cfun->machine->minipool_label_tail->next;
  6053. + }
  6054. +}
  6055. +
  6056. +
  6057. +/* Output the literal table */
  6058. +static void
  6059. +dump_minipool (rtx scan)
  6060. +{
  6061. + Mnode *mp;
  6062. + Mnode *nmp;
  6063. +
  6064. + if (dump_file)
  6065. + fprintf (dump_file,
  6066. + ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
  6067. + INSN_UID (scan), (unsigned long) minipool_barrier->address, 4);
  6068. +
  6069. + scan = emit_insn_after (gen_consttable_start (), scan);
  6070. + scan = emit_insn_after (gen_align_4 (), scan);
  6071. + scan = emit_label_after (minipool_vector_label, scan);
  6072. + new_minipool_label (minipool_vector_label);
  6073. +
  6074. + for (mp = minipool_vector_head; mp != NULL; mp = nmp)
  6075. + {
  6076. + if (mp->refcount > 0)
  6077. + {
  6078. + if (dump_file)
  6079. + {
  6080. + fprintf (dump_file,
  6081. + ";; Offset %u, min %ld, max %ld ",
  6082. + (unsigned) mp->offset, (unsigned long) mp->min_address,
  6083. + (unsigned long) mp->max_address);
  6084. + avr32_print_value (dump_file, mp->value);
  6085. + fputc ('\n', dump_file);
  6086. + }
  6087. +
  6088. + switch (mp->fix_size)
  6089. + {
  6090. +#ifdef HAVE_consttable_4
  6091. + case 4:
  6092. + scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
  6093. + break;
  6094. +
  6095. +#endif
  6096. +#ifdef HAVE_consttable_8
  6097. + case 8:
  6098. + scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
  6099. + break;
  6100. +
  6101. +#endif
  6102. +#ifdef HAVE_consttable_16
  6103. + case 16:
  6104. + scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
  6105. + break;
  6106. +
  6107. +#endif
  6108. + case 0:
  6109. + /* This can happen for force-minipool entries which just are
  6110. + there to force the minipool to be generate. */
  6111. + break;
  6112. + default:
  6113. + abort ();
  6114. + break;
  6115. + }
  6116. + }
  6117. +
  6118. + nmp = mp->next;
  6119. + free (mp);
  6120. + }
  6121. +
  6122. + minipool_vector_head = minipool_vector_tail = NULL;
  6123. + scan = emit_insn_after (gen_consttable_end (), scan);
  6124. + scan = emit_barrier_after (scan);
  6125. +}
  6126. +
  6127. +
  6128. +/* Return the cost of forcibly inserting a barrier after INSN. */
  6129. +static int
  6130. +avr32_barrier_cost (rtx insn)
  6131. +{
  6132. + /* Basing the location of the pool on the loop depth is preferable, but at
  6133. + the moment, the basic block information seems to be corrupt by this
  6134. + stage of the compilation. */
  6135. + int base_cost = 50;
  6136. + rtx next = next_nonnote_insn (insn);
  6137. +
  6138. + if (next != NULL && GET_CODE (next) == CODE_LABEL)
  6139. + base_cost -= 20;
  6140. +
  6141. + switch (GET_CODE (insn))
  6142. + {
  6143. + case CODE_LABEL:
  6144. + /* It will always be better to place the table before the label, rather
  6145. + than after it. */
  6146. + return 50;
  6147. +
  6148. + case INSN:
  6149. + case CALL_INSN:
  6150. + return base_cost;
  6151. +
  6152. + case JUMP_INSN:
  6153. + return base_cost - 10;
  6154. +
  6155. + default:
  6156. + return base_cost + 10;
  6157. + }
  6158. +}
  6159. +
  6160. +
  6161. +/* Find the best place in the insn stream in the range
  6162. + (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
  6163. + Create the barrier by inserting a jump and add a new fix entry for
  6164. + it. */
  6165. +static Mfix *
  6166. +create_fix_barrier (Mfix * fix, HOST_WIDE_INT max_address)
  6167. +{
  6168. + HOST_WIDE_INT count = 0;
  6169. + rtx barrier;
  6170. + rtx from = fix->insn;
  6171. + rtx selected = from;
  6172. + int selected_cost;
  6173. + HOST_WIDE_INT selected_address;
  6174. + Mfix *new_fix;
  6175. + HOST_WIDE_INT max_count = max_address - fix->address;
  6176. + rtx label = gen_label_rtx ();
  6177. +
  6178. + selected_cost = avr32_barrier_cost (from);
  6179. + selected_address = fix->address;
  6180. +
  6181. + while (from && count < max_count)
  6182. + {
  6183. + rtx tmp;
  6184. + int new_cost;
  6185. +
  6186. + /* This code shouldn't have been called if there was a natural barrier
  6187. + within range. */
  6188. + if (GET_CODE (from) == BARRIER)
  6189. + abort ();
  6190. +
  6191. + /* Count the length of this insn. */
  6192. + count += get_attr_length (from);
  6193. +
  6194. + /* If there is a jump table, add its length. */
  6195. + tmp = is_jump_table (from);
  6196. + if (tmp != NULL)
  6197. + {
  6198. + count += get_jump_table_size (tmp);
  6199. +
  6200. + /* Jump tables aren't in a basic block, so base the cost on the
  6201. + dispatch insn. If we select this location, we will still put
  6202. + the pool after the table. */
  6203. + new_cost = avr32_barrier_cost (from);
  6204. +
  6205. + if (count < max_count && new_cost <= selected_cost)
  6206. + {
  6207. + selected = tmp;
  6208. + selected_cost = new_cost;
  6209. + selected_address = fix->address + count;
  6210. + }
  6211. +
  6212. + /* Continue after the dispatch table. */
  6213. + from = NEXT_INSN (tmp);
  6214. + continue;
  6215. + }
  6216. +
  6217. + new_cost = avr32_barrier_cost (from);
  6218. +
  6219. + if (count < max_count && new_cost <= selected_cost)
  6220. + {
  6221. + selected = from;
  6222. + selected_cost = new_cost;
  6223. + selected_address = fix->address + count;
  6224. + }
  6225. +
  6226. + from = NEXT_INSN (from);
  6227. + }
  6228. +
  6229. + /* Create a new JUMP_INSN that branches around a barrier. */
  6230. + from = emit_jump_insn_after (gen_jump (label), selected);
  6231. + JUMP_LABEL (from) = label;
  6232. + barrier = emit_barrier_after (from);
  6233. + emit_label_after (label, barrier);
  6234. +
  6235. + /* Create a minipool barrier entry for the new barrier. */
  6236. + new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*new_fix));
  6237. + new_fix->insn = barrier;
  6238. + new_fix->address = selected_address;
  6239. + new_fix->next = fix->next;
  6240. + fix->next = new_fix;
  6241. +
  6242. + return new_fix;
  6243. +}
  6244. +
  6245. +
  6246. +/* Record that there is a natural barrier in the insn stream at
  6247. + ADDRESS. */
  6248. +static void
  6249. +push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
  6250. +{
  6251. + Mfix *fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*fix));
  6252. +
  6253. + fix->insn = insn;
  6254. + fix->address = address;
  6255. +
  6256. + fix->next = NULL;
  6257. + if (minipool_fix_head != NULL)
  6258. + minipool_fix_tail->next = fix;
  6259. + else
  6260. + minipool_fix_head = fix;
  6261. +
  6262. + minipool_fix_tail = fix;
  6263. +}
  6264. +
  6265. +
  6266. +/* Record INSN, which will need fixing up to load a value from the
  6267. + minipool. ADDRESS is the offset of the insn since the start of the
  6268. + function; LOC is a pointer to the part of the insn which requires
  6269. + fixing; VALUE is the constant that must be loaded, which is of type
  6270. + MODE. */
  6271. +static void
  6272. +push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx * loc,
  6273. + enum machine_mode mode, rtx value)
  6274. +{
  6275. + Mfix *fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*fix));
  6276. + rtx body = PATTERN (insn);
  6277. +
  6278. + fix->insn = insn;
  6279. + fix->address = address;
  6280. + fix->loc = loc;
  6281. + fix->mode = mode;
  6282. + fix->fix_size = MINIPOOL_FIX_SIZE (mode, value);
  6283. + fix->value = value;
  6284. +
  6285. + if (GET_CODE (body) == PARALLEL)
  6286. + {
  6287. + /* Mcall : Ks16 << 2 */
  6288. + fix->forwards = ((1 << 15) - 1) << 2;
  6289. + fix->backwards = (1 << 15) << 2;
  6290. + }
  6291. + else if (GET_CODE (body) == SET
  6292. + && GET_MODE_SIZE (GET_MODE (SET_DEST (body))) == 4)
  6293. + {
  6294. + if (optimize_size)
  6295. + {
  6296. + /* Lddpc : Ku7 << 2 */
  6297. + fix->forwards = ((1 << 7) - 1) << 2;
  6298. + fix->backwards = 0;
  6299. + }
  6300. + else
  6301. + {
  6302. + /* Ld.w : Ks16 */
  6303. + fix->forwards = ((1 << 15) - 4);
  6304. + fix->backwards = (1 << 15);
  6305. + }
  6306. + }
  6307. + else if (GET_CODE (body) == SET
  6308. + && GET_MODE_SIZE (GET_MODE (SET_DEST (body))) == 8)
  6309. + {
  6310. + /* Ld.d : Ks16 */
  6311. + fix->forwards = ((1 << 15) - 4);
  6312. + fix->backwards = (1 << 15);
  6313. + }
  6314. + else if (GET_CODE (body) == UNSPEC_VOLATILE
  6315. + && XINT (body, 1) == VUNSPEC_MVRC)
  6316. + {
  6317. + /* Coprocessor load */
  6318. + /* Ldc : Ku8 << 2 */
  6319. + fix->forwards = ((1 << 8) - 1) << 2;
  6320. + fix->backwards = 0;
  6321. + }
  6322. + else
  6323. + {
  6324. + /* Assume worst case which is lddpc insn. */
  6325. + fix->forwards = ((1 << 7) - 1) << 2;
  6326. + fix->backwards = 0;
  6327. + }
  6328. +
  6329. + fix->minipool = NULL;
  6330. +
  6331. + /* If an insn doesn't have a range defined for it, then it isn't expecting
  6332. + to be reworked by this code. Better to abort now than to generate duff
  6333. + assembly code. */
  6334. + if (fix->forwards == 0 && fix->backwards == 0)
  6335. + abort ();
  6336. +
  6337. + if (dump_file)
  6338. + {
  6339. + fprintf (dump_file,
  6340. + ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
  6341. + GET_MODE_NAME (mode),
  6342. + INSN_UID (insn), (unsigned long) address,
  6343. + -1 * (long) fix->backwards, (long) fix->forwards);
  6344. + avr32_print_value (dump_file, fix->value);
  6345. + fprintf (dump_file, "\n");
  6346. + }
  6347. +
  6348. + /* Add it to the chain of fixes. */
  6349. + fix->next = NULL;
  6350. +
  6351. + if (minipool_fix_head != NULL)
  6352. + minipool_fix_tail->next = fix;
  6353. + else
  6354. + minipool_fix_head = fix;
  6355. +
  6356. + minipool_fix_tail = fix;
  6357. +}
  6358. +
  6359. +
  6360. +/* Scan INSN and note any of its operands that need fixing.
  6361. + If DO_PUSHES is false we do not actually push any of the fixups
  6362. + needed. The function returns TRUE is any fixups were needed/pushed.
  6363. + This is used by avr32_memory_load_p() which needs to know about loads
  6364. + of constants that will be converted into minipool loads. */
  6365. +static bool
  6366. +note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
  6367. +{
  6368. + bool result = false;
  6369. + int opno;
  6370. +
  6371. + extract_insn (insn);
  6372. +
  6373. + if (!constrain_operands (1))
  6374. + fatal_insn_not_found (insn);
  6375. +
  6376. + if (recog_data.n_alternatives == 0)
  6377. + return false;
  6378. +
  6379. + /* Fill in recog_op_alt with information about the constraints of this
  6380. + insn. */
  6381. + preprocess_constraints ();
  6382. +
  6383. + for (opno = 0; opno < recog_data.n_operands; opno++)
  6384. + {
  6385. + rtx op;
  6386. +
  6387. + /* Things we need to fix can only occur in inputs. */
  6388. + if (recog_data.operand_type[opno] != OP_IN)
  6389. + continue;
  6390. +
  6391. + op = recog_data.operand[opno];
  6392. +
  6393. + if (avr32_const_pool_ref_operand (op, GET_MODE (op)))
  6394. + {
  6395. + if (do_pushes)
  6396. + {
  6397. + rtx cop = avoid_constant_pool_reference (op);
  6398. +
  6399. + /* Casting the address of something to a mode narrower than a
  6400. + word can cause avoid_constant_pool_reference() to return the
  6401. + pool reference itself. That's no good to us here. Lets
  6402. + just hope that we can use the constant pool value directly.
  6403. + */
  6404. + if (op == cop)
  6405. + cop = get_pool_constant (XEXP (op, 0));
  6406. +
  6407. + push_minipool_fix (insn, address,
  6408. + recog_data.operand_loc[opno],
  6409. + recog_data.operand_mode[opno], cop);
  6410. + }
  6411. +
  6412. + result = true;
  6413. + }
  6414. + else if (TARGET_HAS_ASM_ADDR_PSEUDOS
  6415. + && avr32_address_operand (op, GET_MODE (op)))
  6416. + {
  6417. + /* Handle pseudo instructions using a direct address. These pseudo
  6418. + instructions might need entries in the constant pool and we must
  6419. + therefor create a constant pool for them, in case the
  6420. + assembler/linker needs to insert entries. */
  6421. + if (do_pushes)
  6422. + {
  6423. + /* Push a dummy constant pool entry so that the .cpool
  6424. + directive should be inserted on the appropriate place in the
  6425. + code even if there are no real constant pool entries. This
  6426. + is used by the assembler and linker to know where to put
  6427. + generated constant pool entries. */
  6428. + push_minipool_fix (insn, address,
  6429. + recog_data.operand_loc[opno],
  6430. + recog_data.operand_mode[opno],
  6431. + gen_rtx_UNSPEC (VOIDmode,
  6432. + gen_rtvec (1, const0_rtx),
  6433. + UNSPEC_FORCE_MINIPOOL));
  6434. + result = true;
  6435. + }
  6436. + }
  6437. + }
  6438. + return result;
  6439. +}
  6440. +
  6441. +
  6442. +static int
  6443. +avr32_insn_is_cast (rtx insn)
  6444. +{
  6445. +
  6446. + if (NONJUMP_INSN_P (insn)
  6447. + && GET_CODE (PATTERN (insn)) == SET
  6448. + && (GET_CODE (SET_SRC (PATTERN (insn))) == ZERO_EXTEND
  6449. + || GET_CODE (SET_SRC (PATTERN (insn))) == SIGN_EXTEND)
  6450. + && REG_P (XEXP (SET_SRC (PATTERN (insn)), 0))
  6451. + && REG_P (SET_DEST (PATTERN (insn))))
  6452. + return true;
  6453. + return false;
  6454. +}
  6455. +
  6456. +
  6457. +/* Replace all occurances of reg FROM with reg TO in X. */
  6458. +rtx
  6459. +avr32_replace_reg (rtx x, rtx from, rtx to)
  6460. +{
  6461. + int i, j;
  6462. + const char *fmt;
  6463. +
  6464. + gcc_assert ( REG_P (from) && REG_P (to) );
  6465. +
  6466. + /* Allow this function to make replacements in EXPR_LISTs. */
  6467. + if (x == 0)
  6468. + return 0;
  6469. +
  6470. + if (rtx_equal_p (x, from))
  6471. + return to;
  6472. +
  6473. + if (GET_CODE (x) == SUBREG)
  6474. + {
  6475. + rtx new = avr32_replace_reg (SUBREG_REG (x), from, to);
  6476. +
  6477. + if (GET_CODE (new) == CONST_INT)
  6478. + {
  6479. + x = simplify_subreg (GET_MODE (x), new,
  6480. + GET_MODE (SUBREG_REG (x)),
  6481. + SUBREG_BYTE (x));
  6482. + gcc_assert (x);
  6483. + }
  6484. + else
  6485. + SUBREG_REG (x) = new;
  6486. +
  6487. + return x;
  6488. + }
  6489. + else if (GET_CODE (x) == ZERO_EXTEND)
  6490. + {
  6491. + rtx new = avr32_replace_reg (XEXP (x, 0), from, to);
  6492. +
  6493. + if (GET_CODE (new) == CONST_INT)
  6494. + {
  6495. + x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
  6496. + new, GET_MODE (XEXP (x, 0)));
  6497. + gcc_assert (x);
  6498. + }
  6499. + else
  6500. + XEXP (x, 0) = new;
  6501. +
  6502. + return x;
  6503. + }
  6504. +
  6505. + fmt = GET_RTX_FORMAT (GET_CODE (x));
  6506. + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
  6507. + {
  6508. + if (fmt[i] == 'e')
  6509. + XEXP (x, i) = avr32_replace_reg (XEXP (x, i), from, to);
  6510. + else if (fmt[i] == 'E')
  6511. + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
  6512. + XVECEXP (x, i, j) = avr32_replace_reg (XVECEXP (x, i, j), from, to);
  6513. + }
  6514. +
  6515. + return x;
  6516. +}
  6517. +
  6518. +
  6519. +/* FIXME: The level of nesting in this function is way too deep. It needs to be
  6520. + torn apart. */
  6521. +static void
  6522. +avr32_reorg_optimization (void)
  6523. +{
  6524. + rtx first = get_first_nonnote_insn ();
  6525. + rtx insn;
  6526. +
  6527. + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
  6528. + {
  6529. +
  6530. + /* Scan through all insns looking for cast operations. */
  6531. + if (dump_file)
  6532. + {
  6533. + fprintf (dump_file, ";; Deleting redundant cast operations:\n");
  6534. + }
  6535. + for (insn = first; insn; insn = NEXT_INSN (insn))
  6536. + {
  6537. + rtx reg, src_reg, scan;
  6538. + enum machine_mode mode;
  6539. + int unused_cast;
  6540. + rtx label_ref;
  6541. +
  6542. + if (avr32_insn_is_cast (insn)
  6543. + && (GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == QImode
  6544. + || GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == HImode))
  6545. + {
  6546. + mode = GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0));
  6547. + reg = SET_DEST (PATTERN (insn));
  6548. + src_reg = XEXP (SET_SRC (PATTERN (insn)), 0);
  6549. + }
  6550. + else
  6551. + {
  6552. + continue;
  6553. + }
  6554. +
  6555. + unused_cast = false;
  6556. + label_ref = NULL_RTX;
  6557. + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan))
  6558. + {
  6559. + /* Check if we have reached the destination of a simple
  6560. + conditional jump which we have already scanned past. If so,
  6561. + we can safely continue scanning. */
  6562. + if (LABEL_P (scan) && label_ref != NULL_RTX)
  6563. + {
  6564. + if (CODE_LABEL_NUMBER (scan) ==
  6565. + CODE_LABEL_NUMBER (XEXP (label_ref, 0)))
  6566. + label_ref = NULL_RTX;
  6567. + else
  6568. + break;
  6569. + }
  6570. +
  6571. + if (!INSN_P (scan))
  6572. + continue;
  6573. +
  6574. + /* For conditional jumps we can manage to keep on scanning if
  6575. + we meet the destination label later on before any new jump
  6576. + insns occure. */
  6577. + if (GET_CODE (scan) == JUMP_INSN)
  6578. + {
  6579. + if (any_condjump_p (scan) && label_ref == NULL_RTX)
  6580. + label_ref = condjump_label (scan);
  6581. + else
  6582. + break;
  6583. + }
  6584. +
  6585. + /* Check if we have a call and the register is used as an argument. */
  6586. + if (CALL_P (scan)
  6587. + && find_reg_fusage (scan, USE, reg) )
  6588. + break;
  6589. +
  6590. + if (!reg_mentioned_p (reg, PATTERN (scan)))
  6591. + continue;
  6592. +
  6593. + /* Check if casted register is used in this insn */
  6594. + if ((regno_use_in (REGNO (reg), PATTERN (scan)) != NULL_RTX)
  6595. + && (GET_MODE (regno_use_in (REGNO (reg), PATTERN (scan))) ==
  6596. + GET_MODE (reg)))
  6597. + {
  6598. + /* If not used in the source to the set or in a memory
  6599. + expression in the destiantion then the register is used
  6600. + as a destination and is really dead. */
  6601. + if (single_set (scan)
  6602. + && GET_CODE (PATTERN (scan)) == SET
  6603. + && REG_P (SET_DEST (PATTERN (scan)))
  6604. + && !regno_use_in (REGNO (reg), SET_SRC (PATTERN (scan)))
  6605. + && label_ref == NULL_RTX)
  6606. + {
  6607. + unused_cast = true;
  6608. + }
  6609. + break;
  6610. + }
  6611. +
  6612. + /* Check if register is dead or set in this insn */
  6613. + if (dead_or_set_p (scan, reg))
  6614. + {
  6615. + unused_cast = true;
  6616. + break;
  6617. + }
  6618. + }
  6619. +
  6620. + /* Check if we have unresolved conditional jumps */
  6621. + if (label_ref != NULL_RTX)
  6622. + continue;
  6623. +
  6624. + if (unused_cast)
  6625. + {
  6626. + if (REGNO (reg) == REGNO (XEXP (SET_SRC (PATTERN (insn)), 0)))
  6627. + {
  6628. + /* One operand cast, safe to delete */
  6629. + if (dump_file)
  6630. + {
  6631. + fprintf (dump_file,
  6632. + ";; INSN %i removed, casted register %i value not used.\n",
  6633. + INSN_UID (insn), REGNO (reg));
  6634. + }
  6635. + SET_INSN_DELETED (insn);
  6636. + /* Force the instruction to be recognized again */
  6637. + INSN_CODE (insn) = -1;
  6638. + }
  6639. + else
  6640. + {
  6641. + /* Two operand cast, which really could be substituted with
  6642. + a move, if the source register is dead after the cast
  6643. + insn and then the insn which sets the source register
  6644. + could instead directly set the destination register for
  6645. + the cast. As long as there are no insns in between which
  6646. + uses the register. */
  6647. + rtx link = NULL_RTX;
  6648. + rtx set;
  6649. + rtx src_reg = XEXP (SET_SRC (PATTERN (insn)), 0);
  6650. + unused_cast = false;
  6651. +
  6652. + if (!find_reg_note (insn, REG_DEAD, src_reg))
  6653. + continue;
  6654. +
  6655. + /* Search for the insn which sets the source register */
  6656. + for (scan = PREV_INSN (insn);
  6657. + scan && GET_CODE (scan) != CODE_LABEL;
  6658. + scan = PREV_INSN (scan))
  6659. + {
  6660. + if (! INSN_P (scan))
  6661. + continue;
  6662. +
  6663. + set = single_set (scan);
  6664. + // Fix for bug #11763 : the following if condition
  6665. + // has been modified and else part is included to
  6666. + // set the link to NULL_RTX.
  6667. + // if (set && rtx_equal_p (src_reg, SET_DEST (set)))
  6668. + if (set && (REGNO(src_reg) == REGNO(SET_DEST(set))))
  6669. + {
  6670. + if (rtx_equal_p (src_reg, SET_DEST (set)))
  6671. + {
  6672. + link = scan;
  6673. + break;
  6674. + }
  6675. + else
  6676. + {
  6677. + link = NULL_RTX;
  6678. + break;
  6679. + }
  6680. + }
  6681. + }
  6682. +
  6683. +
  6684. + /* Found no link or link is a call insn where we can not
  6685. + change the destination register */
  6686. + if (link == NULL_RTX || CALL_P (link))
  6687. + continue;
  6688. +
  6689. + /* Scan through all insn between link and insn */
  6690. + for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
  6691. + {
  6692. + /* Don't try to trace forward past a CODE_LABEL if we
  6693. + haven't seen INSN yet. Ordinarily, we will only
  6694. + find the setting insn in LOG_LINKS if it is in the
  6695. + same basic block. However, cross-jumping can insert
  6696. + code labels in between the load and the call, and
  6697. + can result in situations where a single call insn
  6698. + may have two targets depending on where we came
  6699. + from. */
  6700. +
  6701. + if (GET_CODE (scan) == CODE_LABEL)
  6702. + break;
  6703. +
  6704. + if (!INSN_P (scan))
  6705. + continue;
  6706. +
  6707. + /* Don't try to trace forward past a JUMP. To optimize
  6708. + safely, we would have to check that all the
  6709. + instructions at the jump destination did not use REG.
  6710. + */
  6711. +
  6712. + if (GET_CODE (scan) == JUMP_INSN)
  6713. + {
  6714. + break;
  6715. + }
  6716. +
  6717. + if (!reg_mentioned_p (src_reg, PATTERN (scan)))
  6718. + continue;
  6719. +
  6720. + /* We have reached the cast insn */
  6721. + if (scan == insn)
  6722. + {
  6723. + /* We can remove cast and replace the destination
  6724. + register of the link insn with the destination
  6725. + of the cast */
  6726. + if (dump_file)
  6727. + {
  6728. + fprintf (dump_file,
  6729. + ";; INSN %i removed, casted value unused. "
  6730. + "Destination of removed cast operation: register %i, folded into INSN %i.\n",
  6731. + INSN_UID (insn), REGNO (reg),
  6732. + INSN_UID (link));
  6733. + }
  6734. + /* Update link insn */
  6735. + SET_DEST (PATTERN (link)) =
  6736. + gen_rtx_REG (mode, REGNO (reg));
  6737. + /* Force the instruction to be recognized again */
  6738. + INSN_CODE (link) = -1;
  6739. +
  6740. + /* Delete insn */
  6741. + SET_INSN_DELETED (insn);
  6742. + /* Force the instruction to be recognized again */
  6743. + INSN_CODE (insn) = -1;
  6744. + break;
  6745. + }
  6746. + }
  6747. + }
  6748. + }
  6749. + }
  6750. + }
  6751. +
  6752. + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
  6753. + {
  6754. +
  6755. + /* Scan through all insns looking for shifted add operations */
  6756. + if (dump_file)
  6757. + {
  6758. + fprintf (dump_file,
  6759. + ";; Deleting redundant shifted add operations:\n");
  6760. + }
  6761. + for (insn = first; insn; insn = NEXT_INSN (insn))
  6762. + {
  6763. + rtx reg, mem_expr, scan, op0, op1;
  6764. + int add_only_used_as_pointer;
  6765. +
  6766. + if (INSN_P (insn)
  6767. + && GET_CODE (PATTERN (insn)) == SET
  6768. + && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
  6769. + && (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == MULT
  6770. + || GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == ASHIFT)
  6771. + && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1)) ==
  6772. + CONST_INT && REG_P (SET_DEST (PATTERN (insn)))
  6773. + && REG_P (XEXP (SET_SRC (PATTERN (insn)), 1))
  6774. + && REG_P (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0)))
  6775. + {
  6776. + reg = SET_DEST (PATTERN (insn));
  6777. + mem_expr = SET_SRC (PATTERN (insn));
  6778. + op0 = XEXP (XEXP (mem_expr, 0), 0);
  6779. + op1 = XEXP (mem_expr, 1);
  6780. + }
  6781. + else
  6782. + {
  6783. + continue;
  6784. + }
  6785. +
  6786. + /* Scan forward the check if the result of the shifted add
  6787. + operation is only used as an address in memory operations and
  6788. + that the operands to the shifted add are not clobbered. */
  6789. + add_only_used_as_pointer = false;
  6790. + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan))
  6791. + {
  6792. + if (!INSN_P (scan))
  6793. + continue;
  6794. +
  6795. + /* Don't try to trace forward past a JUMP or CALL. To optimize
  6796. + safely, we would have to check that all the instructions at
  6797. + the jump destination did not use REG. */
  6798. +
  6799. + if (GET_CODE (scan) == JUMP_INSN)
  6800. + {
  6801. + break;
  6802. + }
  6803. +
  6804. + /* If used in a call insn then we cannot optimize it away */
  6805. + if (CALL_P (scan) && find_regno_fusage (scan, USE, REGNO (reg)))
  6806. + break;
  6807. +
  6808. + /* If any of the operands of the shifted add are clobbered we
  6809. + cannot optimize the shifted adda away */
  6810. + if ((reg_set_p (op0, scan) && (REGNO (op0) != REGNO (reg)))
  6811. + || (reg_set_p (op1, scan) && (REGNO (op1) != REGNO (reg))))
  6812. + break;
  6813. +
  6814. + if (!reg_mentioned_p (reg, PATTERN (scan)))
  6815. + continue;
  6816. +
  6817. + /* If used any other place than as a pointer or as the
  6818. + destination register we failed */
  6819. + if (!(single_set (scan)
  6820. + && GET_CODE (PATTERN (scan)) == SET
  6821. + && ((MEM_P (SET_DEST (PATTERN (scan)))
  6822. + && REG_P (XEXP (SET_DEST (PATTERN (scan)), 0))
  6823. + && REGNO (XEXP (SET_DEST (PATTERN (scan)), 0)) == REGNO (reg))
  6824. + || (MEM_P (SET_SRC (PATTERN (scan)))
  6825. + && REG_P (XEXP (SET_SRC (PATTERN (scan)), 0))
  6826. + && REGNO (XEXP
  6827. + (SET_SRC (PATTERN (scan)), 0)) == REGNO (reg))))
  6828. + && !(GET_CODE (PATTERN (scan)) == SET
  6829. + && REG_P (SET_DEST (PATTERN (scan)))
  6830. + && !regno_use_in (REGNO (reg),
  6831. + SET_SRC (PATTERN (scan)))))
  6832. + break;
  6833. +
  6834. + /* We cannot replace the pointer in TImode insns
  6835. + as these has a differene addressing mode than the other
  6836. + memory insns. */
  6837. + if ( GET_MODE (SET_DEST (PATTERN (scan))) == TImode )
  6838. + break;
  6839. +
  6840. + /* Check if register is dead or set in this insn */
  6841. + if (dead_or_set_p (scan, reg))
  6842. + {
  6843. + add_only_used_as_pointer = true;
  6844. + break;
  6845. + }
  6846. + }
  6847. +
  6848. + if (add_only_used_as_pointer)
  6849. + {
  6850. + /* Lets delete the add insn and replace all memory references
  6851. + which uses the pointer with the full expression. */
  6852. + if (dump_file)
  6853. + {
  6854. + fprintf (dump_file,
  6855. + ";; Deleting INSN %i since address expression can be folded into all "
  6856. + "memory references using this expression\n",
  6857. + INSN_UID (insn));
  6858. + }
  6859. + SET_INSN_DELETED (insn);
  6860. + /* Force the instruction to be recognized again */
  6861. + INSN_CODE (insn) = -1;
  6862. +
  6863. + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan))
  6864. + {
  6865. + if (!INSN_P (scan))
  6866. + continue;
  6867. +
  6868. + if (!reg_mentioned_p (reg, PATTERN (scan)))
  6869. + continue;
  6870. +
  6871. + /* If used any other place than as a pointer or as the
  6872. + destination register we failed */
  6873. + if ((single_set (scan)
  6874. + && GET_CODE (PATTERN (scan)) == SET
  6875. + && ((MEM_P (SET_DEST (PATTERN (scan)))
  6876. + && REG_P (XEXP (SET_DEST (PATTERN (scan)), 0))
  6877. + && REGNO (XEXP (SET_DEST (PATTERN (scan)), 0)) ==
  6878. + REGNO (reg)) || (MEM_P (SET_SRC (PATTERN (scan)))
  6879. + &&
  6880. + REG_P (XEXP
  6881. + (SET_SRC (PATTERN (scan)),
  6882. + 0))
  6883. + &&
  6884. + REGNO (XEXP
  6885. + (SET_SRC (PATTERN (scan)),
  6886. + 0)) == REGNO (reg)))))
  6887. + {
  6888. + if (dump_file)
  6889. + {
  6890. + fprintf (dump_file,
  6891. + ";; Register %i replaced by indexed address in INSN %i\n",
  6892. + REGNO (reg), INSN_UID (scan));
  6893. + }
  6894. + if (MEM_P (SET_DEST (PATTERN (scan))))
  6895. + XEXP (SET_DEST (PATTERN (scan)), 0) = mem_expr;
  6896. + else
  6897. + XEXP (SET_SRC (PATTERN (scan)), 0) = mem_expr;
  6898. + }
  6899. +
  6900. + /* Check if register is dead or set in this insn */
  6901. + if (dead_or_set_p (scan, reg))
  6902. + {
  6903. + break;
  6904. + }
  6905. +
  6906. + }
  6907. + }
  6908. + }
  6909. + }
  6910. +
  6911. +
  6912. + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
  6913. + {
  6914. +
  6915. + /* Scan through all insns looking for conditional register to
  6916. + register move operations */
  6917. + if (dump_file)
  6918. + {
  6919. + fprintf (dump_file,
  6920. + ";; Folding redundant conditional move operations:\n");
  6921. + }
  6922. + for (insn = first; insn; insn = next_nonnote_insn (insn))
  6923. + {
  6924. + rtx src_reg, dst_reg, scan, test;
  6925. +
  6926. + if (INSN_P (insn)
  6927. + && GET_CODE (PATTERN (insn)) == COND_EXEC
  6928. + && GET_CODE (COND_EXEC_CODE (PATTERN (insn))) == SET
  6929. + && REG_P (SET_SRC (COND_EXEC_CODE (PATTERN (insn))))
  6930. + && REG_P (SET_DEST (COND_EXEC_CODE (PATTERN (insn))))
  6931. + && find_reg_note (insn, REG_DEAD, SET_SRC (COND_EXEC_CODE (PATTERN (insn)))))
  6932. + {
  6933. + src_reg = SET_SRC (COND_EXEC_CODE (PATTERN (insn)));
  6934. + dst_reg = SET_DEST (COND_EXEC_CODE (PATTERN (insn)));
  6935. + test = COND_EXEC_TEST (PATTERN (insn));
  6936. + }
  6937. + else
  6938. + {
  6939. + continue;
  6940. + }
  6941. +
  6942. + /* Scan backward through the rest of insns in this if-then or if-else
  6943. + block and check if we can fold the move into another of the conditional
  6944. + insns in the same block. */
  6945. + scan = prev_nonnote_insn (insn);
  6946. + while (INSN_P (scan)
  6947. + && GET_CODE (PATTERN (scan)) == COND_EXEC
  6948. + && rtx_equal_p (COND_EXEC_TEST (PATTERN (scan)), test))
  6949. + {
  6950. + rtx pattern = COND_EXEC_CODE (PATTERN (scan));
  6951. + if ( GET_CODE (pattern) == PARALLEL )
  6952. + pattern = XVECEXP (pattern, 0, 0);
  6953. +
  6954. + if ( reg_set_p (src_reg, pattern) )
  6955. + {
  6956. + /* Fold in the destination register for the cond. move
  6957. + into this insn. */
  6958. + SET_DEST (pattern) = dst_reg;
  6959. + if (dump_file)
  6960. + {
  6961. + fprintf (dump_file,
  6962. + ";; Deleting INSN %i since this operation can be folded into INSN %i\n",
  6963. + INSN_UID (insn), INSN_UID (scan));
  6964. + }
  6965. +
  6966. + /* Scan and check if any of the insns in between uses the src_reg. We
  6967. + must then replace it with the dst_reg. */
  6968. + while ( (scan = next_nonnote_insn (scan)) != insn ){
  6969. + avr32_replace_reg (scan, src_reg, dst_reg);
  6970. + }
  6971. + /* Delete the insn. */
  6972. + SET_INSN_DELETED (insn);
  6973. +
  6974. + /* Force the instruction to be recognized again */
  6975. + INSN_CODE (insn) = -1;
  6976. + break;
  6977. + }
  6978. +
  6979. + /* If the destination register is used but not set in this insn
  6980. + we cannot fold. */
  6981. + if ( reg_mentioned_p (dst_reg, pattern) )
  6982. + break;
  6983. +
  6984. + scan = prev_nonnote_insn (scan);
  6985. + }
  6986. + }
  6987. + }
  6988. +
  6989. +}
  6990. +
  6991. +
  6992. +/* Exported to toplev.c.
  6993. +
  6994. + Do a final pass over the function, just before delayed branch
  6995. + scheduling. */
  6996. +static void
  6997. +avr32_reorg (void)
  6998. +{
  6999. + rtx insn;
  7000. + HOST_WIDE_INT address = 0;
  7001. + Mfix *fix;
  7002. +
  7003. + minipool_fix_head = minipool_fix_tail = NULL;
  7004. +
  7005. + /* The first insn must always be a note, or the code below won't scan it
  7006. + properly. */
  7007. + insn = get_insns ();
  7008. + if (GET_CODE (insn) != NOTE)
  7009. + abort ();
  7010. +
  7011. + /* Scan all the insns and record the operands that will need fixing. */
  7012. + for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
  7013. + {
  7014. + if (GET_CODE (insn) == BARRIER)
  7015. + push_minipool_barrier (insn, address);
  7016. + else if (INSN_P (insn))
  7017. + {
  7018. + rtx table;
  7019. +
  7020. + note_invalid_constants (insn, address, true);
  7021. + address += get_attr_length (insn);
  7022. +
  7023. + /* If the insn is a vector jump, add the size of the table and skip
  7024. + the table. */
  7025. + if ((table = is_jump_table (insn)) != NULL)
  7026. + {
  7027. + address += get_jump_table_size (table);
  7028. + insn = table;
  7029. + }
  7030. + }
  7031. + }
  7032. +
  7033. + fix = minipool_fix_head;
  7034. +
  7035. + /* Now scan the fixups and perform the required changes. */
  7036. + while (fix)
  7037. + {
  7038. + Mfix *ftmp;
  7039. + Mfix *fdel;
  7040. + Mfix *last_added_fix;
  7041. + Mfix *last_barrier = NULL;
  7042. + Mfix *this_fix;
  7043. +
  7044. + /* Skip any further barriers before the next fix. */
  7045. + while (fix && GET_CODE (fix->insn) == BARRIER)
  7046. + fix = fix->next;
  7047. +
  7048. + /* No more fixes. */
  7049. + if (fix == NULL)
  7050. + break;
  7051. +
  7052. + last_added_fix = NULL;
  7053. +
  7054. + for (ftmp = fix; ftmp; ftmp = ftmp->next)
  7055. + {
  7056. + if (GET_CODE (ftmp->insn) == BARRIER)
  7057. + {
  7058. + if (ftmp->address >= minipool_vector_head->max_address)
  7059. + break;
  7060. +
  7061. + last_barrier = ftmp;
  7062. + }
  7063. + else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
  7064. + break;
  7065. +
  7066. + last_added_fix = ftmp; /* Keep track of the last fix added.
  7067. + */
  7068. + }
  7069. +
  7070. + /* If we found a barrier, drop back to that; any fixes that we could
  7071. + have reached but come after the barrier will now go in the next
  7072. + mini-pool. */
  7073. + if (last_barrier != NULL)
  7074. + {
  7075. + /* Reduce the refcount for those fixes that won't go into this pool
  7076. + after all. */
  7077. + for (fdel = last_barrier->next;
  7078. + fdel && fdel != ftmp; fdel = fdel->next)
  7079. + {
  7080. + fdel->minipool->refcount--;
  7081. + fdel->minipool = NULL;
  7082. + }
  7083. +
  7084. + ftmp = last_barrier;
  7085. + }
  7086. + else
  7087. + {
  7088. + /* ftmp is first fix that we can't fit into this pool and there no
  7089. + natural barriers that we could use. Insert a new barrier in the
  7090. + code somewhere between the previous fix and this one, and
  7091. + arrange to jump around it. */
  7092. + HOST_WIDE_INT max_address;
  7093. +
  7094. + /* The last item on the list of fixes must be a barrier, so we can
  7095. + never run off the end of the list of fixes without last_barrier
  7096. + being set. */
  7097. + if (ftmp == NULL)
  7098. + abort ();
  7099. +
  7100. + max_address = minipool_vector_head->max_address;
  7101. + /* Check that there isn't another fix that is in range that we
  7102. + couldn't fit into this pool because the pool was already too
  7103. + large: we need to put the pool before such an instruction. */
  7104. + if (ftmp->address < max_address)
  7105. + max_address = ftmp->address;
  7106. +
  7107. + last_barrier = create_fix_barrier (last_added_fix, max_address);
  7108. + }
  7109. +
  7110. + assign_minipool_offsets (last_barrier);
  7111. +
  7112. + while (ftmp)
  7113. + {
  7114. + if (GET_CODE (ftmp->insn) != BARRIER
  7115. + && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
  7116. + == NULL))
  7117. + break;
  7118. +
  7119. + ftmp = ftmp->next;
  7120. + }
  7121. +
  7122. + /* Scan over the fixes we have identified for this pool, fixing them up
  7123. + and adding the constants to the pool itself. */
  7124. + for (this_fix = fix; this_fix && ftmp != this_fix;
  7125. + this_fix = this_fix->next)
  7126. + if (GET_CODE (this_fix->insn) != BARRIER
  7127. + /* Do nothing for entries present just to force the insertion of
  7128. + a minipool. */
  7129. + && !IS_FORCE_MINIPOOL (this_fix->value))
  7130. + {
  7131. + rtx addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
  7132. + minipool_vector_label),
  7133. + this_fix->minipool->offset);
  7134. + *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
  7135. + }
  7136. +
  7137. + dump_minipool (last_barrier->insn);
  7138. + fix = ftmp;
  7139. + }
  7140. +
  7141. + /* Free the minipool memory. */
  7142. + obstack_free (&minipool_obstack, minipool_startobj);
  7143. +
  7144. + avr32_reorg_optimization ();
  7145. +}
  7146. +
  7147. +
  7148. +/* Hook for doing some final scanning of instructions. Does nothing yet...*/
  7149. +void
  7150. +avr32_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED,
  7151. + rtx * opvec ATTRIBUTE_UNUSED,
  7152. + int noperands ATTRIBUTE_UNUSED)
  7153. +{
  7154. + return;
  7155. +}
  7156. +
  7157. +
  7158. +/* Function for changing the condition on the next instruction,
  7159. + should be used when emmiting compare instructions and
  7160. + the condition of the next instruction needs to change.
  7161. +*/
  7162. +int
  7163. +set_next_insn_cond (rtx cur_insn, rtx new_cond)
  7164. +{
  7165. + rtx next_insn = next_nonnote_insn (cur_insn);
  7166. + if ((next_insn != NULL_RTX)
  7167. + && (INSN_P (next_insn)))
  7168. + {
  7169. + if ((GET_CODE (PATTERN (next_insn)) == SET)
  7170. + && (GET_CODE (SET_SRC (PATTERN (next_insn))) == IF_THEN_ELSE))
  7171. + {
  7172. + /* Branch instructions */
  7173. + XEXP (SET_SRC (PATTERN (next_insn)), 0) = new_cond;
  7174. + /* Force the instruction to be recognized again */
  7175. + INSN_CODE (next_insn) = -1;
  7176. + return TRUE;
  7177. + }
  7178. + else if ((GET_CODE (PATTERN (next_insn)) == SET)
  7179. + && avr32_comparison_operator (SET_SRC (PATTERN (next_insn)),
  7180. + GET_MODE (SET_SRC (PATTERN (next_insn)))))
  7181. + {
  7182. + /* scc with no compare */
  7183. + SET_SRC (PATTERN (next_insn)) = new_cond;
  7184. + /* Force the instruction to be recognized again */
  7185. + INSN_CODE (next_insn) = -1;
  7186. + return TRUE;
  7187. + }
  7188. + else if (GET_CODE (PATTERN (next_insn)) == COND_EXEC)
  7189. + {
  7190. + if ( GET_CODE (new_cond) == UNSPEC )
  7191. + {
  7192. + COND_EXEC_TEST (PATTERN (next_insn)) =
  7193. + gen_rtx_UNSPEC (CCmode,
  7194. + gen_rtvec (2,
  7195. + XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 0),
  7196. + XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 1)),
  7197. + XINT (new_cond, 1));
  7198. + }
  7199. + else
  7200. + {
  7201. + PUT_CODE(COND_EXEC_TEST (PATTERN (next_insn)), GET_CODE(new_cond));
  7202. + }
  7203. + }
  7204. + }
  7205. +
  7206. + return FALSE;
  7207. +}
  7208. +
  7209. +
  7210. +/* Function for obtaining the condition for the next instruction after cur_insn.
  7211. +*/
  7212. +rtx
  7213. +get_next_insn_cond (rtx cur_insn)
  7214. +{
  7215. + rtx next_insn = next_nonnote_insn (cur_insn);
  7216. + rtx cond = NULL_RTX;
  7217. + if (next_insn != NULL_RTX
  7218. + && INSN_P (next_insn))
  7219. + {
  7220. + if ((GET_CODE (PATTERN (next_insn)) == SET)
  7221. + && (GET_CODE (SET_SRC (PATTERN (next_insn))) == IF_THEN_ELSE))
  7222. + {
  7223. + /* Branch and cond if then else instructions */
  7224. + cond = XEXP (SET_SRC (PATTERN (next_insn)), 0);
  7225. + }
  7226. + else if ((GET_CODE (PATTERN (next_insn)) == SET)
  7227. + && avr32_comparison_operator (SET_SRC (PATTERN (next_insn)),
  7228. + GET_MODE (SET_SRC (PATTERN (next_insn)))))
  7229. + {
  7230. + /* scc with no compare */
  7231. + cond = SET_SRC (PATTERN (next_insn));
  7232. + }
  7233. + else if (GET_CODE (PATTERN (next_insn)) == COND_EXEC)
  7234. + {
  7235. + cond = COND_EXEC_TEST (PATTERN (next_insn));
  7236. + }
  7237. + }
  7238. + return cond;
  7239. +}
  7240. +
  7241. +
  7242. +/* Check if the next insn is a conditional insn that will emit a compare
  7243. + for itself.
  7244. +*/
  7245. +rtx
  7246. +next_insn_emits_cmp (rtx cur_insn)
  7247. +{
  7248. + rtx next_insn = next_nonnote_insn (cur_insn);
  7249. + rtx cond = NULL_RTX;
  7250. + if (next_insn != NULL_RTX
  7251. + && INSN_P (next_insn))
  7252. + {
  7253. + if ( ((GET_CODE (PATTERN (next_insn)) == SET)
  7254. + && (GET_CODE (SET_SRC (PATTERN (next_insn))) == IF_THEN_ELSE)
  7255. + && (XEXP (XEXP (SET_SRC (PATTERN (next_insn)), 0),0) != cc0_rtx))
  7256. + || GET_CODE (PATTERN (next_insn)) == COND_EXEC )
  7257. + return TRUE;
  7258. + }
  7259. + return FALSE;
  7260. +}
  7261. +
  7262. +
  7263. +rtx
  7264. +avr32_output_cmp (rtx cond, enum machine_mode mode, rtx op0, rtx op1)
  7265. +{
  7266. +
  7267. + rtx new_cond = NULL_RTX;
  7268. + rtx ops[2];
  7269. + rtx compare_pattern;
  7270. + ops[0] = op0;
  7271. + ops[1] = op1;
  7272. +
  7273. + if ( GET_CODE (op0) == AND )
  7274. + compare_pattern = op0;
  7275. + else
  7276. + compare_pattern = gen_rtx_COMPARE (mode, op0, op1);
  7277. +
  7278. + new_cond = is_compare_redundant (compare_pattern, cond);
  7279. +
  7280. + if (new_cond != NULL_RTX)
  7281. + return new_cond;
  7282. +
  7283. + /* Check if we are inserting a bit-load instead of a compare. */
  7284. + if ( GET_CODE (op0) == AND )
  7285. + {
  7286. + ops[0] = XEXP (op0, 0);
  7287. + ops[1] = XEXP (op0, 1);
  7288. + output_asm_insn ("bld\t%0, %p1", ops);
  7289. + return cond;
  7290. + }
  7291. +
  7292. + /* Insert compare */
  7293. + switch (mode)
  7294. + {
  7295. + case QImode:
  7296. + output_asm_insn ("cp.b\t%0, %1", ops);
  7297. + break;
  7298. + case HImode:
  7299. + output_asm_insn ("cp.h\t%0, %1", ops);
  7300. + break;
  7301. + case SImode:
  7302. + output_asm_insn ("cp.w\t%0, %1", ops);
  7303. + break;
  7304. + case DImode:
  7305. + if (GET_CODE (op1) != REG)
  7306. + output_asm_insn ("cp.w\t%0, %1\ncpc\t%m0", ops);
  7307. + else
  7308. + output_asm_insn ("cp.w\t%0, %1\ncpc\t%m0, %m1", ops);
  7309. + break;
  7310. + default:
  7311. + internal_error ("Unknown comparison mode");
  7312. + break;
  7313. + }
  7314. +
  7315. + return cond;
  7316. +}
  7317. +
  7318. +
  7319. +int
  7320. +avr32_load_multiple_operation (rtx op,
  7321. + enum machine_mode mode ATTRIBUTE_UNUSED)
  7322. +{
  7323. + int count = XVECLEN (op, 0);
  7324. + unsigned int dest_regno;
  7325. + rtx src_addr;
  7326. + rtx elt;
  7327. + int i = 1, base = 0;
  7328. +
  7329. + if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
  7330. + return 0;
  7331. +
  7332. + /* Check to see if this might be a write-back. */
  7333. + if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
  7334. + {
  7335. + i++;
  7336. + base = 1;
  7337. +
  7338. + /* Now check it more carefully. */
  7339. + if (GET_CODE (SET_DEST (elt)) != REG
  7340. + || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
  7341. + || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
  7342. + || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
  7343. + return 0;
  7344. + }
  7345. +
  7346. + /* Perform a quick check so we don't blow up below. */
  7347. + if (count <= 1
  7348. + || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
  7349. + || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
  7350. + || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != UNSPEC)
  7351. + return 0;
  7352. +
  7353. + dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
  7354. + src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
  7355. +
  7356. + for (; i < count; i++)
  7357. + {
  7358. + elt = XVECEXP (op, 0, i);
  7359. +
  7360. + if (GET_CODE (elt) != SET
  7361. + || GET_CODE (SET_DEST (elt)) != REG
  7362. + || GET_MODE (SET_DEST (elt)) != SImode
  7363. + || GET_CODE (SET_SRC (elt)) != UNSPEC)
  7364. + return 0;
  7365. + }
  7366. +
  7367. + return 1;
  7368. +}
  7369. +
  7370. +
  7371. +int
  7372. +avr32_store_multiple_operation (rtx op,
  7373. + enum machine_mode mode ATTRIBUTE_UNUSED)
  7374. +{
  7375. + int count = XVECLEN (op, 0);
  7376. + int src_regno;
  7377. + rtx dest_addr;
  7378. + rtx elt;
  7379. + int i = 1;
  7380. +
  7381. + if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
  7382. + return 0;
  7383. +
  7384. + /* Perform a quick check so we don't blow up below. */
  7385. + if (count <= i
  7386. + || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
  7387. + || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
  7388. + || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != UNSPEC)
  7389. + return 0;
  7390. +
  7391. + src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
  7392. + dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
  7393. +
  7394. + for (; i < count; i++)
  7395. + {
  7396. + elt = XVECEXP (op, 0, i);
  7397. +
  7398. + if (GET_CODE (elt) != SET
  7399. + || GET_CODE (SET_DEST (elt)) != MEM
  7400. + || GET_MODE (SET_DEST (elt)) != SImode
  7401. + || GET_CODE (SET_SRC (elt)) != UNSPEC)
  7402. + return 0;
  7403. + }
  7404. +
  7405. + return 1;
  7406. +}
  7407. +
  7408. +
  7409. +int
  7410. +avr32_valid_macmac_bypass (rtx insn_out, rtx insn_in)
  7411. +{
  7412. + /* Check if they use the same accumulator */
  7413. + if (rtx_equal_p
  7414. + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in))))
  7415. + {
  7416. + return TRUE;
  7417. + }
  7418. +
  7419. + return FALSE;
  7420. +}
  7421. +
  7422. +
  7423. +int
  7424. +avr32_valid_mulmac_bypass (rtx insn_out, rtx insn_in)
  7425. +{
  7426. + /*
  7427. + Check if the mul instruction produces the accumulator for the mac
  7428. + instruction. */
  7429. + if (rtx_equal_p
  7430. + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in))))
  7431. + {
  7432. + return TRUE;
  7433. + }
  7434. + return FALSE;
  7435. +}
  7436. +
  7437. +
  7438. +int
  7439. +avr32_store_bypass (rtx insn_out, rtx insn_in)
  7440. +{
  7441. + /* Only valid bypass if the output result is used as an src in the store
  7442. + instruction, NOT if used as a pointer or base. */
  7443. + if (rtx_equal_p
  7444. + (SET_DEST (PATTERN (insn_out)), SET_SRC (PATTERN (insn_in))))
  7445. + {
  7446. + return TRUE;
  7447. + }
  7448. +
  7449. + return FALSE;
  7450. +}
  7451. +
  7452. +
  7453. +int
  7454. +avr32_mul_waw_bypass (rtx insn_out, rtx insn_in)
  7455. +{
  7456. + /* Check if the register holding the result from the mul instruction is
  7457. + used as a result register in the input instruction. */
  7458. + if (rtx_equal_p
  7459. + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in))))
  7460. + {
  7461. + return TRUE;
  7462. + }
  7463. +
  7464. + return FALSE;
  7465. +}
  7466. +
  7467. +
  7468. +int
  7469. +avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in)
  7470. +{
  7471. + /* Check if the first loaded word in insn_out is used in insn_in. */
  7472. + rtx dst_reg;
  7473. + rtx second_loaded_reg;
  7474. +
  7475. + /* If this is a double alu operation then the bypass is not valid */
  7476. + if ((get_attr_type (insn_in) == TYPE_ALU
  7477. + || get_attr_type (insn_in) == TYPE_ALU2)
  7478. + && (GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (insn_out)))) > 4))
  7479. + return FALSE;
  7480. +
  7481. + /* Get the destination register in the load */
  7482. + if (!REG_P (SET_DEST (PATTERN (insn_out))))
  7483. + return FALSE;
  7484. +
  7485. + dst_reg = SET_DEST (PATTERN (insn_out));
  7486. + second_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 1);
  7487. +
  7488. + if (!reg_mentioned_p (second_loaded_reg, PATTERN (insn_in)))
  7489. + return TRUE;
  7490. +
  7491. + return FALSE;
  7492. +}
  7493. +
  7494. +
  7495. +int
  7496. +avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in)
  7497. +{
  7498. + /*
  7499. + Check if the two first loaded word in insn_out are used in insn_in. */
  7500. + rtx dst_reg;
  7501. + rtx third_loaded_reg, fourth_loaded_reg;
  7502. +
  7503. + /* Get the destination register in the load */
  7504. + if (!REG_P (SET_DEST (PATTERN (insn_out))))
  7505. + return FALSE;
  7506. +
  7507. + dst_reg = SET_DEST (PATTERN (insn_out));
  7508. + third_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 2);
  7509. + fourth_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 3);
  7510. +
  7511. + if (!reg_mentioned_p (third_loaded_reg, PATTERN (insn_in))
  7512. + && !reg_mentioned_p (fourth_loaded_reg, PATTERN (insn_in)))
  7513. + {
  7514. + return TRUE;
  7515. + }
  7516. +
  7517. + return FALSE;
  7518. +}
  7519. +
  7520. +
  7521. +rtx
  7522. +avr32_ifcvt_modify_test (ce_if_block_t *ce_info, rtx test )
  7523. +{
  7524. + rtx branch_insn;
  7525. + rtx cmp_test;
  7526. + rtx compare_op0;
  7527. + rtx compare_op1;
  7528. +
  7529. +
  7530. + if ( !ce_info
  7531. + || test == NULL_RTX
  7532. + || !reg_mentioned_p (cc0_rtx, test))
  7533. + return test;
  7534. +
  7535. + branch_insn = BB_END (ce_info->test_bb);
  7536. + cmp_test = PATTERN(prev_nonnote_insn (branch_insn));
  7537. +
  7538. + if (GET_CODE(cmp_test) != SET
  7539. + || !CC0_P(XEXP(cmp_test, 0)) )
  7540. + return cmp_test;
  7541. +
  7542. + if ( GET_CODE(SET_SRC(cmp_test)) == COMPARE ){
  7543. + compare_op0 = XEXP(SET_SRC(cmp_test), 0);
  7544. + compare_op1 = XEXP(SET_SRC(cmp_test), 1);
  7545. + } else {
  7546. + compare_op0 = SET_SRC(cmp_test);
  7547. + compare_op1 = const0_rtx;
  7548. + }
  7549. +
  7550. + return gen_rtx_fmt_ee (GET_CODE(test), GET_MODE (compare_op0),
  7551. + compare_op0, compare_op1);
  7552. +}
  7553. +
  7554. +
  7555. +rtx
  7556. +avr32_ifcvt_modify_insn (ce_if_block_t *ce_info, rtx pattern, rtx insn,
  7557. + int *num_true_changes)
  7558. +{
  7559. + rtx test = COND_EXEC_TEST(pattern);
  7560. + rtx op = COND_EXEC_CODE(pattern);
  7561. + rtx cmp_insn;
  7562. + rtx cond_exec_insn;
  7563. + int inputs_set_outside_ifblock = 1;
  7564. + basic_block current_bb = BLOCK_FOR_INSN (insn);
  7565. + rtx bb_insn ;
  7566. + enum machine_mode mode = GET_MODE (XEXP (op, 0));
  7567. +
  7568. + if (CC0_P(XEXP(test, 0)))
  7569. + test = avr32_ifcvt_modify_test (ce_info,
  7570. + test );
  7571. +
  7572. + /* We do not support multiple tests. */
  7573. + if ( ce_info
  7574. + && ce_info->num_multiple_test_blocks > 0 )
  7575. + return NULL_RTX;
  7576. +
  7577. + pattern = gen_rtx_COND_EXEC (VOIDmode, test, op);
  7578. +
  7579. + if ( !reload_completed )
  7580. + {
  7581. + rtx start;
  7582. + int num_insns;
  7583. + int max_insns = MAX_CONDITIONAL_EXECUTE;
  7584. +
  7585. + if ( !ce_info )
  7586. + return op;
  7587. +
  7588. + /* Check if the insn is not suitable for conditional
  7589. + execution. */
  7590. + start_sequence ();
  7591. + cond_exec_insn = emit_insn (pattern);
  7592. + if ( recog_memoized (cond_exec_insn) < 0
  7593. + && can_create_pseudo_p () )
  7594. + {
  7595. + /* Insn is not suitable for conditional execution, try
  7596. + to fix it up by using an extra scratch register or
  7597. + by pulling the operation outside the if-then-else
  7598. + and then emiting a conditional move inside the if-then-else. */
  7599. + end_sequence ();
  7600. + if ( GET_CODE (op) != SET
  7601. + || !REG_P (SET_DEST (op))
  7602. + || GET_CODE (SET_SRC (op)) == IF_THEN_ELSE
  7603. + || GET_MODE_SIZE (mode) > UNITS_PER_WORD )
  7604. + return NULL_RTX;
  7605. +
  7606. + /* Check if any of the input operands to the insn is set inside the
  7607. + current block. */
  7608. + if ( current_bb->index == ce_info->then_bb->index )
  7609. + start = PREV_INSN (BB_HEAD (ce_info->then_bb));
  7610. + else
  7611. + start = PREV_INSN (BB_HEAD (ce_info->else_bb));
  7612. +
  7613. +
  7614. + for ( bb_insn = next_nonnote_insn (start); bb_insn != insn; bb_insn = next_nonnote_insn (bb_insn) )
  7615. + {
  7616. + rtx set = single_set (bb_insn);
  7617. +
  7618. + if ( set && reg_mentioned_p (SET_DEST (set), SET_SRC (op)))
  7619. + {
  7620. + inputs_set_outside_ifblock = 0;
  7621. + break;
  7622. + }
  7623. + }
  7624. +
  7625. + cmp_insn = prev_nonnote_insn (BB_END (ce_info->test_bb));
  7626. +
  7627. +
  7628. + /* Check if we can insert more insns. */
  7629. + num_insns = ( ce_info->num_then_insns +
  7630. + ce_info->num_else_insns +
  7631. + ce_info->num_cond_clobber_insns +
  7632. + ce_info->num_extra_move_insns );
  7633. +
  7634. + if ( ce_info->num_else_insns != 0 )
  7635. + max_insns *=2;
  7636. +
  7637. + if ( num_insns >= max_insns )
  7638. + return NULL_RTX;
  7639. +
  7640. + /* Check if we have an instruction which might be converted to
  7641. + conditional form if we give it a scratch register to clobber. */
  7642. + {
  7643. + rtx clobber_insn;
  7644. + rtx scratch_reg = gen_reg_rtx (mode);
  7645. + rtx new_pattern = copy_rtx (pattern);
  7646. + rtx set_src = SET_SRC (COND_EXEC_CODE (new_pattern));
  7647. +
  7648. + rtx clobber = gen_rtx_CLOBBER (mode, scratch_reg);
  7649. + rtx vec[2] = { COND_EXEC_CODE (new_pattern), clobber };
  7650. + COND_EXEC_CODE (new_pattern) = gen_rtx_PARALLEL (mode, gen_rtvec_v (2, vec));
  7651. +
  7652. + start_sequence ();
  7653. + clobber_insn = emit_insn (new_pattern);
  7654. +
  7655. + if ( recog_memoized (clobber_insn) >= 0
  7656. + && ( ( GET_RTX_LENGTH (GET_CODE (set_src)) == 2
  7657. + && CONST_INT_P (XEXP (set_src, 1))
  7658. + && avr32_const_ok_for_constraint_p (INTVAL (XEXP (set_src, 1)), 'K', "Ks08") )
  7659. + || !ce_info->else_bb
  7660. + || current_bb->index == ce_info->else_bb->index ))
  7661. + {
  7662. + end_sequence ();
  7663. + /* Force the insn to be recognized again. */
  7664. + INSN_CODE (insn) = -1;
  7665. +
  7666. + /* If this is the first change in this IF-block then
  7667. + signal that we have made a change. */
  7668. + if ( ce_info->num_cond_clobber_insns == 0
  7669. + && ce_info->num_extra_move_insns == 0 )
  7670. + *num_true_changes += 1;
  7671. +
  7672. + ce_info->num_cond_clobber_insns++;
  7673. +
  7674. + if (dump_file)
  7675. + fprintf (dump_file,
  7676. + "\nReplacing INSN %d with an insn using a scratch register for later ifcvt passes...\n",
  7677. + INSN_UID (insn));
  7678. +
  7679. + return COND_EXEC_CODE (new_pattern);
  7680. + }
  7681. + end_sequence ();
  7682. + }
  7683. +
  7684. + if ( inputs_set_outside_ifblock )
  7685. + {
  7686. + /* Check if the insn before the cmp is an and which used
  7687. + together with the cmp can be optimized into a bld. If
  7688. + so then we should try to put the insn before the and
  7689. + so that we can catch the bld peephole. */
  7690. + rtx set;
  7691. + rtx insn_before_cmp_insn = prev_nonnote_insn (cmp_insn);
  7692. + if (insn_before_cmp_insn
  7693. + && (set = single_set (insn_before_cmp_insn))
  7694. + && GET_CODE (SET_SRC (set)) == AND
  7695. + && one_bit_set_operand (XEXP (SET_SRC (set), 1), SImode)
  7696. + /* Also make sure that the insn does not set any
  7697. + of the input operands to the insn we are pulling out. */
  7698. + && !reg_mentioned_p (SET_DEST (set), SET_SRC (op)) )
  7699. + cmp_insn = prev_nonnote_insn (cmp_insn);
  7700. +
  7701. + /* We can try to put the operation outside the if-then-else
  7702. + blocks and insert a move. */
  7703. + if ( !insn_invalid_p (insn)
  7704. + /* Do not allow conditional insns to be moved outside the
  7705. + if-then-else. */
  7706. + && !reg_mentioned_p (cc0_rtx, insn)
  7707. + /* We cannot move memory loads outside of the if-then-else
  7708. + since the memory access should not be perfomed if the
  7709. + condition is not met. */
  7710. + && !mem_mentioned_p (SET_SRC (op)) )
  7711. + {
  7712. + rtx scratch_reg = gen_reg_rtx (mode);
  7713. + rtx op_pattern = copy_rtx (op);
  7714. + rtx new_insn, seq;
  7715. + rtx link, prev_link;
  7716. + op = copy_rtx (op);
  7717. + /* Emit the operation to a temp reg before the compare,
  7718. + and emit a move inside the if-then-else, hoping that the
  7719. + whole if-then-else can be converted to conditional
  7720. + execution. */
  7721. + SET_DEST (op_pattern) = scratch_reg;
  7722. + start_sequence ();
  7723. + new_insn = emit_insn (op_pattern);
  7724. + seq = get_insns();
  7725. + end_sequence ();
  7726. +
  7727. + /* Check again that the insn is valid. For some insns the insn might
  7728. + become invalid if the destination register is changed. Ie. for mulacc
  7729. + operations. */
  7730. + if ( insn_invalid_p (new_insn) )
  7731. + return NULL_RTX;
  7732. +
  7733. + emit_insn_before_setloc (seq, cmp_insn, INSN_LOCATOR (insn));
  7734. +
  7735. + if (dump_file)
  7736. + fprintf (dump_file,
  7737. + "\nMoving INSN %d out of IF-block by adding INSN %d...\n",
  7738. + INSN_UID (insn), INSN_UID (new_insn));
  7739. +
  7740. + ce_info->extra_move_insns[ce_info->num_extra_move_insns] = insn;
  7741. + ce_info->moved_insns[ce_info->num_extra_move_insns] = new_insn;
  7742. + XEXP (op, 1) = scratch_reg;
  7743. + /* Force the insn to be recognized again. */
  7744. + INSN_CODE (insn) = -1;
  7745. +
  7746. + /* Move REG_DEAD notes to the moved insn. */
  7747. + prev_link = NULL_RTX;
  7748. + for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
  7749. + {
  7750. + if (REG_NOTE_KIND (link) == REG_DEAD)
  7751. + {
  7752. + /* Add the REG_DEAD note to the new insn. */
  7753. + rtx dead_reg = XEXP (link, 0);
  7754. + REG_NOTES (new_insn) = gen_rtx_EXPR_LIST (REG_DEAD, dead_reg, REG_NOTES (new_insn));
  7755. + /* Remove the REG_DEAD note from the insn we convert to a move. */
  7756. + if ( prev_link )
  7757. + XEXP (prev_link, 1) = XEXP (link, 1);
  7758. + else
  7759. + REG_NOTES (insn) = XEXP (link, 1);
  7760. + }
  7761. + else
  7762. + {
  7763. + prev_link = link;
  7764. + }
  7765. + }
  7766. + /* Add a REG_DEAD note to signal that the scratch register is dead. */
  7767. + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, scratch_reg, REG_NOTES (insn));
  7768. +
  7769. + /* If this is the first change in this IF-block then
  7770. + signal that we have made a change. */
  7771. + if ( ce_info->num_cond_clobber_insns == 0
  7772. + && ce_info->num_extra_move_insns == 0 )
  7773. + *num_true_changes += 1;
  7774. +
  7775. + ce_info->num_extra_move_insns++;
  7776. + return op;
  7777. + }
  7778. + }
  7779. +
  7780. + /* We failed to fixup the insns, so this if-then-else can not be made
  7781. + conditional. Just return NULL_RTX so that the if-then-else conversion
  7782. + for this if-then-else will be cancelled. */
  7783. + return NULL_RTX;
  7784. + }
  7785. + end_sequence ();
  7786. + return op;
  7787. + }
  7788. +
  7789. + /* Signal that we have started if conversion after reload, which means
  7790. + that it should be safe to split all the predicable clobber insns which
  7791. + did not become cond_exec back into a simpler form if possible. */
  7792. + cfun->machine->ifcvt_after_reload = 1;
  7793. +
  7794. + return pattern;
  7795. +}
  7796. +
  7797. +
  7798. +void
  7799. +avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info, int *num_true_changes)
  7800. +{
  7801. + int n;
  7802. +
  7803. + if ( ce_info->num_extra_move_insns > 0
  7804. + && ce_info->num_cond_clobber_insns == 0)
  7805. + /* Signal that we did not do any changes after all. */
  7806. + *num_true_changes -= 1;
  7807. +
  7808. + /* Remove any inserted move insns. */
  7809. + for ( n = 0; n < ce_info->num_extra_move_insns; n++ )
  7810. + {
  7811. + rtx link, prev_link;
  7812. +
  7813. + /* Remove REG_DEAD note since we are not needing the scratch register anyway. */
  7814. + prev_link = NULL_RTX;
  7815. + for (link = REG_NOTES (ce_info->extra_move_insns[n]); link; link = XEXP (link, 1))
  7816. + {
  7817. + if (REG_NOTE_KIND (link) == REG_DEAD)
  7818. + {
  7819. + if ( prev_link )
  7820. + XEXP (prev_link, 1) = XEXP (link, 1);
  7821. + else
  7822. + REG_NOTES (ce_info->extra_move_insns[n]) = XEXP (link, 1);
  7823. + }
  7824. + else
  7825. + {
  7826. + prev_link = link;
  7827. + }
  7828. + }
  7829. +
  7830. + /* Revert all reg_notes for the moved insn. */
  7831. + for (link = REG_NOTES (ce_info->moved_insns[n]); link; link = XEXP (link, 1))
  7832. + {
  7833. + REG_NOTES (ce_info->extra_move_insns[n]) = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link),
  7834. + XEXP (link, 0),
  7835. + REG_NOTES (ce_info->extra_move_insns[n]));
  7836. + }
  7837. +
  7838. + /* Remove the moved insn. */
  7839. + remove_insn ( ce_info->moved_insns[n] );
  7840. + }
  7841. +}
  7842. +
  7843. +
  7844. +/* Function returning TRUE if INSN with OPERANDS is a splittable
  7845. + conditional immediate clobber insn. We assume that the insn is
  7846. + already a conditional immediate clobber insns and do not check
  7847. + for that. */
  7848. +int
  7849. +avr32_cond_imm_clobber_splittable (rtx insn, rtx operands[])
  7850. +{
  7851. + if ( REGNO (operands[0]) == REGNO (operands[1]) )
  7852. + {
  7853. + if ( (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == PLUS
  7854. + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'I', "Is21"))
  7855. + || (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == MINUS
  7856. + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks21")))
  7857. + return FALSE;
  7858. + }
  7859. + else if ( (logical_binary_operator (SET_SRC (XVECEXP (PATTERN (insn),0,0)), VOIDmode)
  7860. + || (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == PLUS
  7861. + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'I', "Is16"))
  7862. + || (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == MINUS
  7863. + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks16"))) )
  7864. + return FALSE;
  7865. +
  7866. + return TRUE;
  7867. +}
  7868. +
  7869. +
  7870. +/* Function for getting an integer value from a const_int or const_double
  7871. + expression regardless of the HOST_WIDE_INT size. Each target cpu word
  7872. + will be put into the val array where the LSW will be stored at the lowest
  7873. + address and so forth. Assumes that const_expr is either a const_int or
  7874. + const_double. Only valid for modes which have sizes that are a multiple
  7875. + of the word size.
  7876. +*/
  7877. +void
  7878. +avr32_get_intval (enum machine_mode mode, rtx const_expr, HOST_WIDE_INT *val)
  7879. +{
  7880. + int words_in_mode = GET_MODE_SIZE (mode)/UNITS_PER_WORD;
  7881. + const int words_in_const_int = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD;
  7882. +
  7883. + if ( GET_CODE(const_expr) == CONST_DOUBLE ){
  7884. + HOST_WIDE_INT hi = CONST_DOUBLE_HIGH(const_expr);
  7885. + HOST_WIDE_INT lo = CONST_DOUBLE_LOW(const_expr);
  7886. + /* Evaluate hi and lo values of const_double. */
  7887. + avr32_get_intval (mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0),
  7888. + GEN_INT (lo),
  7889. + &val[0]);
  7890. + avr32_get_intval (mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0),
  7891. + GEN_INT (hi),
  7892. + &val[words_in_const_int]);
  7893. + } else if ( GET_CODE(const_expr) == CONST_INT ){
  7894. + HOST_WIDE_INT value = INTVAL(const_expr);
  7895. + int word;
  7896. + for ( word = 0; (word < words_in_mode) && (word < words_in_const_int); word++ ){
  7897. + /* Shift word up to the MSW and shift down again to extract the
  7898. + word and sign-extend. */
  7899. + int lshift = (words_in_const_int - word - 1) * BITS_PER_WORD;
  7900. + int rshift = (words_in_const_int-1) * BITS_PER_WORD;
  7901. + val[word] = (value << lshift) >> rshift;
  7902. + }
  7903. +
  7904. + for ( ; word < words_in_mode; word++ ){
  7905. + /* Just put the sign bits in the remaining words. */
  7906. + val[word] = value < 0 ? -1 : 0;
  7907. + }
  7908. + }
  7909. +}
  7910. +
  7911. +
  7912. +void
  7913. +avr32_split_const_expr (enum machine_mode mode, enum machine_mode new_mode,
  7914. + rtx expr, rtx *split_expr)
  7915. +{
  7916. + int i, word;
  7917. + int words_in_intval = GET_MODE_SIZE (mode)/UNITS_PER_WORD;
  7918. + int words_in_split_values = GET_MODE_SIZE (new_mode)/UNITS_PER_WORD;
  7919. + const int words_in_const_int = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD;
  7920. + HOST_WIDE_INT *val = alloca (words_in_intval * UNITS_PER_WORD);
  7921. +
  7922. + avr32_get_intval (mode, expr, val);
  7923. +
  7924. + for ( i=0; i < (words_in_intval/words_in_split_values); i++ )
  7925. + {
  7926. + HOST_WIDE_INT value_lo = 0, value_hi = 0;
  7927. + for ( word = 0; word < words_in_split_values; word++ )
  7928. + {
  7929. + if ( word >= words_in_const_int )
  7930. + value_hi |= ((val[i * words_in_split_values + word] &
  7931. + (((HOST_WIDE_INT)1 << BITS_PER_WORD)-1))
  7932. + << (BITS_PER_WORD * (word - words_in_const_int)));
  7933. + else
  7934. + value_lo |= ((val[i * words_in_split_values + word] &
  7935. + (((HOST_WIDE_INT)1 << BITS_PER_WORD)-1))
  7936. + << (BITS_PER_WORD * word));
  7937. + }
  7938. + split_expr[i] = immed_double_const(value_lo, value_hi, new_mode);
  7939. + }
  7940. +}
  7941. +
  7942. +
  7943. +/* Set up library functions to comply to AVR32 ABI */
  7944. +static void
  7945. +avr32_init_libfuncs (void)
  7946. +{
  7947. + /* Convert gcc run-time function names to AVR32 ABI names */
  7948. +
  7949. + /* Double-precision floating-point arithmetic. */
  7950. + set_optab_libfunc (neg_optab, DFmode, NULL);
  7951. +
  7952. + /* Double-precision comparisons. */
  7953. + set_optab_libfunc (eq_optab, DFmode, "__avr32_f64_cmp_eq");
  7954. + set_optab_libfunc (ne_optab, DFmode, NULL);
  7955. + set_optab_libfunc (lt_optab, DFmode, "__avr32_f64_cmp_lt");
  7956. + set_optab_libfunc (le_optab, DFmode, NULL);
  7957. + set_optab_libfunc (ge_optab, DFmode, "__avr32_f64_cmp_ge");
  7958. + set_optab_libfunc (gt_optab, DFmode, NULL);
  7959. +
  7960. + /* Single-precision floating-point arithmetic. */
  7961. + set_optab_libfunc (smul_optab, SFmode, "__avr32_f32_mul");
  7962. + set_optab_libfunc (neg_optab, SFmode, NULL);
  7963. +
  7964. + /* Single-precision comparisons. */
  7965. + set_optab_libfunc (eq_optab, SFmode, "__avr32_f32_cmp_eq");
  7966. + set_optab_libfunc (ne_optab, SFmode, NULL);
  7967. + set_optab_libfunc (lt_optab, SFmode, "__avr32_f32_cmp_lt");
  7968. + set_optab_libfunc (le_optab, SFmode, NULL);
  7969. + set_optab_libfunc (ge_optab, SFmode, "__avr32_f32_cmp_ge");
  7970. + set_optab_libfunc (gt_optab, SFmode, NULL);
  7971. +
  7972. + /* Floating-point to integer conversions. */
  7973. + set_conv_libfunc (sfix_optab, SImode, DFmode, "__avr32_f64_to_s32");
  7974. + set_conv_libfunc (ufix_optab, SImode, DFmode, "__avr32_f64_to_u32");
  7975. + set_conv_libfunc (sfix_optab, DImode, DFmode, "__avr32_f64_to_s64");
  7976. + set_conv_libfunc (ufix_optab, DImode, DFmode, "__avr32_f64_to_u64");
  7977. + set_conv_libfunc (sfix_optab, SImode, SFmode, "__avr32_f32_to_s32");
  7978. + set_conv_libfunc (ufix_optab, SImode, SFmode, "__avr32_f32_to_u32");
  7979. + set_conv_libfunc (sfix_optab, DImode, SFmode, "__avr32_f32_to_s64");
  7980. + set_conv_libfunc (ufix_optab, DImode, SFmode, "__avr32_f32_to_u64");
  7981. +
  7982. + /* Conversions between floating types. */
  7983. + set_conv_libfunc (trunc_optab, SFmode, DFmode, "__avr32_f64_to_f32");
  7984. + set_conv_libfunc (sext_optab, DFmode, SFmode, "__avr32_f32_to_f64");
  7985. +
  7986. + /* Integer to floating-point conversions. Table 8. */
  7987. + set_conv_libfunc (sfloat_optab, DFmode, SImode, "__avr32_s32_to_f64");
  7988. + set_conv_libfunc (sfloat_optab, DFmode, DImode, "__avr32_s64_to_f64");
  7989. + set_conv_libfunc (sfloat_optab, SFmode, SImode, "__avr32_s32_to_f32");
  7990. + set_conv_libfunc (sfloat_optab, SFmode, DImode, "__avr32_s64_to_f32");
  7991. + set_conv_libfunc (ufloat_optab, DFmode, SImode, "__avr32_u32_to_f64");
  7992. + set_conv_libfunc (ufloat_optab, SFmode, SImode, "__avr32_u32_to_f32");
  7993. + /* TODO: Add these to gcc library functions */
  7994. + //set_conv_libfunc (ufloat_optab, DFmode, DImode, NULL);
  7995. + //set_conv_libfunc (ufloat_optab, SFmode, DImode, NULL);
  7996. +
  7997. + /* Long long. Table 9. */
  7998. + set_optab_libfunc (smul_optab, DImode, "__avr32_mul64");
  7999. + set_optab_libfunc (sdiv_optab, DImode, "__avr32_sdiv64");
  8000. + set_optab_libfunc (udiv_optab, DImode, "__avr32_udiv64");
  8001. + set_optab_libfunc (smod_optab, DImode, "__avr32_smod64");
  8002. + set_optab_libfunc (umod_optab, DImode, "__avr32_umod64");
  8003. + set_optab_libfunc (ashl_optab, DImode, "__avr32_lsl64");
  8004. + set_optab_libfunc (lshr_optab, DImode, "__avr32_lsr64");
  8005. + set_optab_libfunc (ashr_optab, DImode, "__avr32_asr64");
  8006. +
  8007. + /* Floating point library functions which have fast versions. */
  8008. + if ( TARGET_FAST_FLOAT )
  8009. + {
  8010. + set_optab_libfunc (sdiv_optab, DFmode, "__avr32_f64_div_fast");
  8011. + set_optab_libfunc (smul_optab, DFmode, "__avr32_f64_mul_fast");
  8012. + set_optab_libfunc (add_optab, DFmode, "__avr32_f64_add_fast");
  8013. + set_optab_libfunc (sub_optab, DFmode, "__avr32_f64_sub_fast");
  8014. + set_optab_libfunc (add_optab, SFmode, "__avr32_f32_add_fast");
  8015. + set_optab_libfunc (sub_optab, SFmode, "__avr32_f32_sub_fast");
  8016. + set_optab_libfunc (sdiv_optab, SFmode, "__avr32_f32_div_fast");
  8017. + }
  8018. + else
  8019. + {
  8020. + set_optab_libfunc (sdiv_optab, DFmode, "__avr32_f64_div");
  8021. + set_optab_libfunc (smul_optab, DFmode, "__avr32_f64_mul");
  8022. + set_optab_libfunc (add_optab, DFmode, "__avr32_f64_add");
  8023. + set_optab_libfunc (sub_optab, DFmode, "__avr32_f64_sub");
  8024. + set_optab_libfunc (add_optab, SFmode, "__avr32_f32_add");
  8025. + set_optab_libfunc (sub_optab, SFmode, "__avr32_f32_sub");
  8026. + set_optab_libfunc (sdiv_optab, SFmode, "__avr32_f32_div");
  8027. + }
  8028. +}
  8029. +
  8030. +
  8031. +/* Record a flashvault declaration. */
  8032. +static void
  8033. +flashvault_decl_list_add (unsigned int vector_num, const char *name)
  8034. +{
  8035. + struct flashvault_decl_list *p;
  8036. +
  8037. + p = (struct flashvault_decl_list *)
  8038. + xmalloc (sizeof (struct flashvault_decl_list));
  8039. + p->next = flashvault_decl_list_head;
  8040. + p->name = name;
  8041. + p->vector_num = vector_num;
  8042. + flashvault_decl_list_head = p;
  8043. +}
  8044. +
  8045. +
  8046. +static void
  8047. +avr32_file_end (void)
  8048. +{
  8049. + struct flashvault_decl_list *p;
  8050. + unsigned int num_entries = 0;
  8051. +
  8052. + /* Check if a list of flashvault declarations exists. */
  8053. + if (flashvault_decl_list_head != NULL)
  8054. + {
  8055. + /* Calculate the number of entries in the table. */
  8056. + for (p = flashvault_decl_list_head; p != NULL; p = p->next)
  8057. + {
  8058. + num_entries++;
  8059. + }
  8060. +
  8061. + /* Generate the beginning of the flashvault data table. */
  8062. + fputs ("\t.global __fv_table\n"
  8063. + "\t.data\n"
  8064. + "\t.align 2\n"
  8065. + "\t.set .LFVTABLE, . + 0\n"
  8066. + "\t.type __fv_table, @object\n", asm_out_file);
  8067. + /* Each table entry is 8 bytes. */
  8068. + fprintf (asm_out_file, "\t.size __fv_table, %u\n", (num_entries * 8));
  8069. +
  8070. + fputs("__fv_table:\n", asm_out_file);
  8071. +
  8072. + for (p = flashvault_decl_list_head; p != NULL; p = p->next)
  8073. + {
  8074. + /* Output table entry. */
  8075. + fprintf (asm_out_file,
  8076. + "\t.align 2\n"
  8077. + "\t.int %u\n", p->vector_num);
  8078. + fprintf (asm_out_file,
  8079. + "\t.align 2\n"
  8080. + "\t.int %s\n", p->name);
  8081. + }
  8082. + }
  8083. +}
  8084. --- /dev/null
  8085. +++ b/gcc/config/avr32/avr32-elf.h
  8086. @@ -0,0 +1,91 @@
  8087. +/*
  8088. + Elf specific definitions.
  8089. + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  8090. +
  8091. + This file is part of GCC.
  8092. +
  8093. + This program is free software; you can redistribute it and/or modify
  8094. + it under the terms of the GNU General Public License as published by
  8095. + the Free Software Foundation; either version 2 of the License, or
  8096. + (at your option) any later version.
  8097. +
  8098. + This program is distributed in the hope that it will be useful,
  8099. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  8100. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  8101. + GNU General Public License for more details.
  8102. +
  8103. + You should have received a copy of the GNU General Public License
  8104. + along with this program; if not, write to the Free Software
  8105. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  8106. +
  8107. +
  8108. +/*****************************************************************************
  8109. + * Controlling the Compiler Driver, 'gcc'
  8110. + *****************************************************************************/
  8111. +
  8112. +/* Run-time Target Specification. */
  8113. +#undef TARGET_VERSION
  8114. +#define TARGET_VERSION fputs (" (AVR32 GNU with ELF)", stderr);
  8115. +
  8116. +/*
  8117. +Another C string constant used much like LINK_SPEC. The
  8118. +difference between the two is that STARTFILE_SPEC is used at
  8119. +the very beginning of the command given to the linker.
  8120. +
  8121. +If this macro is not defined, a default is provided that loads the
  8122. +standard C startup file from the usual place. See gcc.c.
  8123. +*/
  8124. +#if 0
  8125. +#undef STARTFILE_SPEC
  8126. +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
  8127. +#endif
  8128. +#undef STARTFILE_SPEC
  8129. +#define STARTFILE_SPEC "%{mflashvault: crtfv.o%s} %{!mflashvault: crt0.o%s} \
  8130. + crti.o%s crtbegin.o%s"
  8131. +
  8132. +#undef LINK_SPEC
  8133. +#define LINK_SPEC "%{muse-oscall:--defsym __do_not_use_oscall_coproc__=0} %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}} %{mpart=uc3a3revd:-mavr32elf_uc3a3256s;:%{mpart=*:-mavr32elf_%*}} %{mcpu=*:-mavr32elf_%*}"
  8134. +
  8135. +
  8136. +/*
  8137. +Another C string constant used much like LINK_SPEC. The
  8138. +difference between the two is that ENDFILE_SPEC is used at
  8139. +the very end of the command given to the linker.
  8140. +
  8141. +Do not define this macro if it does not need to do anything.
  8142. +*/
  8143. +#undef ENDFILE_SPEC
  8144. +#define ENDFILE_SPEC "crtend%O%s crtn%O%s"
  8145. +
  8146. +
  8147. +/* Target CPU builtins. */
  8148. +#define TARGET_CPU_CPP_BUILTINS() \
  8149. + do \
  8150. + { \
  8151. + builtin_define ("__avr32__"); \
  8152. + builtin_define ("__AVR32__"); \
  8153. + builtin_define ("__AVR32_ELF__"); \
  8154. + builtin_define (avr32_part->macro); \
  8155. + builtin_define (avr32_arch->macro); \
  8156. + if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \
  8157. + builtin_define ("__AVR32_AVR32A__"); \
  8158. + else \
  8159. + builtin_define ("__AVR32_AVR32B__"); \
  8160. + if (TARGET_UNALIGNED_WORD) \
  8161. + builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \
  8162. + if (TARGET_SIMD) \
  8163. + builtin_define ("__AVR32_HAS_SIMD__"); \
  8164. + if (TARGET_DSP) \
  8165. + builtin_define ("__AVR32_HAS_DSP__"); \
  8166. + if (TARGET_RMW) \
  8167. + builtin_define ("__AVR32_HAS_RMW__"); \
  8168. + if (TARGET_BRANCH_PRED) \
  8169. + builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \
  8170. + if (TARGET_FAST_FLOAT) \
  8171. + builtin_define ("__AVR32_FAST_FLOAT__"); \
  8172. + if (TARGET_FLASHVAULT) \
  8173. + builtin_define ("__AVR32_FLASHVAULT__"); \
  8174. + if (TARGET_NO_MUL_INSNS) \
  8175. + builtin_define ("__AVR32_NO_MUL__"); \
  8176. + } \
  8177. + while (0)
  8178. --- /dev/null
  8179. +++ b/gcc/config/avr32/avr32.h
  8180. @@ -0,0 +1,3316 @@
  8181. +/*
  8182. + Definitions of target machine for AVR32.
  8183. + Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation.
  8184. +
  8185. + This file is part of GCC.
  8186. +
  8187. + This program is free software; you can redistribute it and/or modify
  8188. + it under the terms of the GNU General Public License as published by
  8189. + the Free Software Foundation; either version 2 of the License, or
  8190. + (at your option) any later version.
  8191. +
  8192. + This program is distributed in the hope that it will be useful,
  8193. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  8194. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  8195. + GNU General Public License for more details.
  8196. +
  8197. + You should have received a copy of the GNU General Public License
  8198. + along with this program; if not, write to the Free Software
  8199. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  8200. +
  8201. +#ifndef GCC_AVR32_H
  8202. +#define GCC_AVR32_H
  8203. +
  8204. +
  8205. +#ifndef OBJECT_FORMAT_ELF
  8206. +#error avr32.h included before elfos.h
  8207. +#endif
  8208. +
  8209. +#ifndef LOCAL_LABEL_PREFIX
  8210. +#define LOCAL_LABEL_PREFIX "."
  8211. +#endif
  8212. +
  8213. +#ifndef SUBTARGET_CPP_SPEC
  8214. +#define SUBTARGET_CPP_SPEC "-D__ELF__"
  8215. +#endif
  8216. +
  8217. +
  8218. +extern struct rtx_def *avr32_compare_op0;
  8219. +extern struct rtx_def *avr32_compare_op1;
  8220. +
  8221. +/* comparison type */
  8222. +enum avr32_cmp_type {
  8223. + CMP_QI, /* 1 byte ->char */
  8224. + CMP_HI, /* 2 byte->half word */
  8225. + CMP_SI, /* four byte->word*/
  8226. + CMP_DI, /* eight byte->double word */
  8227. + CMP_SF, /* single precision floats */
  8228. + CMP_MAX /* max comparison type */
  8229. +};
  8230. +
  8231. +extern enum avr32_cmp_type avr32_branch_type; /* type of branch to use */
  8232. +
  8233. +
  8234. +extern struct rtx_def *avr32_acc_cache;
  8235. +
  8236. +/* cache instruction op5 codes */
  8237. +#define AVR32_CACHE_INVALIDATE_ICACHE 1
  8238. +
  8239. +/*
  8240. +These bits describe the different types of function supported by the AVR32
  8241. +backend. They are exclusive, e.g. a function cannot be both a normal function
  8242. +and an interworked function. Knowing the type of a function is important for
  8243. +determining its prologue and epilogue sequences. Note value 7 is currently
  8244. +unassigned. Also note that the interrupt function types all have bit 2 set,
  8245. +so that they can be tested for easily. Note that 0 is deliberately chosen for
  8246. +AVR32_FT_UNKNOWN so that when the machine_function structure is initialized
  8247. +(to zero) func_type will default to unknown. This will force the first use of
  8248. +avr32_current_func_type to call avr32_compute_func_type.
  8249. +*/
  8250. +#define AVR32_FT_UNKNOWN 0 /* Type has not yet been determined. */
  8251. +#define AVR32_FT_NORMAL 1 /* Normal function. */
  8252. +#define AVR32_FT_ACALL 2 /* An acall function. */
  8253. +#define AVR32_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
  8254. +#define AVR32_FT_ISR_FULL 4 /* A fully shadowed interrupt mode. */
  8255. +#define AVR32_FT_ISR_HALF 5 /* A half shadowed interrupt mode. */
  8256. +#define AVR32_FT_ISR_NONE 6 /* No shadow registers. */
  8257. +
  8258. +#define AVR32_FT_TYPE_MASK ((1 << 3) - 1)
  8259. +
  8260. +/* In addition functions can have several type modifiers, outlined by these bit masks: */
  8261. +#define AVR32_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
  8262. +#define AVR32_FT_NAKED (1 << 3) /* No prologue or epilogue. */
  8263. +#define AVR32_FT_VOLATILE (1 << 4) /* Does not return. */
  8264. +#define AVR32_FT_NESTED (1 << 5) /* Embedded inside another func. */
  8265. +#define AVR32_FT_FLASHVAULT (1 << 6) /* Flashvault function call. */
  8266. +#define AVR32_FT_FLASHVAULT_IMPL (1 << 7) /* Function definition in FlashVault. */
  8267. +
  8268. +
  8269. +/* Some macros to test these flags. */
  8270. +#define AVR32_FUNC_TYPE(t) (t & AVR32_FT_TYPE_MASK)
  8271. +#define IS_INTERRUPT(t) (t & AVR32_FT_INTERRUPT)
  8272. +#define IS_NAKED(t) (t & AVR32_FT_NAKED)
  8273. +#define IS_VOLATILE(t) (t & AVR32_FT_VOLATILE)
  8274. +#define IS_NESTED(t) (t & AVR32_FT_NESTED)
  8275. +#define IS_FLASHVAULT(t) (t & AVR32_FT_FLASHVAULT)
  8276. +#define IS_FLASHVAULT_IMPL(t) (t & AVR32_FT_FLASHVAULT_IMPL)
  8277. +
  8278. +#define SYMBOL_FLAG_RMW_ADDR_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
  8279. +#define SYMBOL_REF_RMW_ADDR(RTX) \
  8280. + ((SYMBOL_REF_FLAGS (RTX) & (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT)) != 0)
  8281. +
  8282. +
  8283. +typedef struct minipool_labels
  8284. +GTY ((chain_next ("%h.next"), chain_prev ("%h.prev")))
  8285. +{
  8286. + rtx label;
  8287. + struct minipool_labels *prev;
  8288. + struct minipool_labels *next;
  8289. +} minipool_labels;
  8290. +
  8291. +/* A C structure for machine-specific, per-function data.
  8292. + This is added to the cfun structure. */
  8293. +
  8294. +typedef struct machine_function
  8295. +GTY (())
  8296. +{
  8297. + /* Records the type of the current function. */
  8298. + unsigned long func_type;
  8299. + /* List of minipool labels, use for checking if code label is valid in a
  8300. + memory expression */
  8301. + minipool_labels *minipool_label_head;
  8302. + minipool_labels *minipool_label_tail;
  8303. + int ifcvt_after_reload;
  8304. +} machine_function;
  8305. +
  8306. +/* Initialize data used by insn expanders. This is called from insn_emit,
  8307. + once for every function before code is generated. */
  8308. +#define INIT_EXPANDERS avr32_init_expanders ()
  8309. +
  8310. +/******************************************************************************
  8311. + * SPECS
  8312. + *****************************************************************************/
  8313. +
  8314. +#ifndef ASM_SPEC
  8315. +#define ASM_SPEC "%{fpic:--pic} %{mrelax|O*:%{mno-relax|O0|O1: ;:--linkrelax}} %{march=ucr2nomul:-march=ucr2;:%{march=*:-march=%*}} %{mpart=uc3a3revd:-mpart=uc3a3256s;:%{mpart=*:-mpart=%*}}"
  8316. +#endif
  8317. +
  8318. +#ifndef MULTILIB_DEFAULTS
  8319. +#define MULTILIB_DEFAULTS { "march=ap", "" }
  8320. +#endif
  8321. +
  8322. +/******************************************************************************
  8323. + * Run-time Target Specification
  8324. + *****************************************************************************/
  8325. +#ifndef TARGET_VERSION
  8326. +#define TARGET_VERSION fprintf(stderr, " (AVR32, GNU assembler syntax)");
  8327. +#endif
  8328. +
  8329. +
  8330. +/* Part types. Keep this in sync with the order of avr32_part_types in avr32.c*/
  8331. +enum part_type
  8332. +{
  8333. + PART_TYPE_AVR32_NONE,
  8334. + PART_TYPE_AVR32_AP7000,
  8335. + PART_TYPE_AVR32_AP7001,
  8336. + PART_TYPE_AVR32_AP7002,
  8337. + PART_TYPE_AVR32_AP7200,
  8338. + PART_TYPE_AVR32_UC3A0128,
  8339. + PART_TYPE_AVR32_UC3A0256,
  8340. + PART_TYPE_AVR32_UC3A0512,
  8341. + PART_TYPE_AVR32_UC3A0512ES,
  8342. + PART_TYPE_AVR32_UC3A1128,
  8343. + PART_TYPE_AVR32_UC3A1256,
  8344. + PART_TYPE_AVR32_UC3A1512,
  8345. + PART_TYPE_AVR32_UC3A1512ES,
  8346. + PART_TYPE_AVR32_UC3A3REVD,
  8347. + PART_TYPE_AVR32_UC3A364,
  8348. + PART_TYPE_AVR32_UC3A364S,
  8349. + PART_TYPE_AVR32_UC3A3128,
  8350. + PART_TYPE_AVR32_UC3A3128S,
  8351. + PART_TYPE_AVR32_UC3A3256,
  8352. + PART_TYPE_AVR32_UC3A3256S,
  8353. + PART_TYPE_AVR32_UC3A464,
  8354. + PART_TYPE_AVR32_UC3A464S,
  8355. + PART_TYPE_AVR32_UC3A4128,
  8356. + PART_TYPE_AVR32_UC3A4128S,
  8357. + PART_TYPE_AVR32_UC3A4256,
  8358. + PART_TYPE_AVR32_UC3A4256S,
  8359. + PART_TYPE_AVR32_UC3B064,
  8360. + PART_TYPE_AVR32_UC3B0128,
  8361. + PART_TYPE_AVR32_UC3B0256,
  8362. + PART_TYPE_AVR32_UC3B0256ES,
  8363. + PART_TYPE_AVR32_UC3B0512,
  8364. + PART_TYPE_AVR32_UC3B0512REVC,
  8365. + PART_TYPE_AVR32_UC3B164,
  8366. + PART_TYPE_AVR32_UC3B1128,
  8367. + PART_TYPE_AVR32_UC3B1256,
  8368. + PART_TYPE_AVR32_UC3B1256ES,
  8369. + PART_TYPE_AVR32_UC3B1512,
  8370. + PART_TYPE_AVR32_UC3B1512REVC,
  8371. + PART_TYPE_AVR32_UC64D3,
  8372. + PART_TYPE_AVR32_UC128D3,
  8373. + PART_TYPE_AVR32_UC64D4,
  8374. + PART_TYPE_AVR32_UC128D4,
  8375. + PART_TYPE_AVR32_UC3C0512CREVC,
  8376. + PART_TYPE_AVR32_UC3C1512CREVC,
  8377. + PART_TYPE_AVR32_UC3C2512CREVC,
  8378. + PART_TYPE_AVR32_UC3L0256,
  8379. + PART_TYPE_AVR32_UC3L0128,
  8380. + PART_TYPE_AVR32_UC3L064,
  8381. + PART_TYPE_AVR32_UC3L032,
  8382. + PART_TYPE_AVR32_UC3L016,
  8383. + PART_TYPE_AVR32_UC3L064REVB,
  8384. + PART_TYPE_AVR32_UC64L3U,
  8385. + PART_TYPE_AVR32_UC128L3U,
  8386. + PART_TYPE_AVR32_UC256L3U,
  8387. + PART_TYPE_AVR32_UC64L4U,
  8388. + PART_TYPE_AVR32_UC128L4U,
  8389. + PART_TYPE_AVR32_UC256L4U,
  8390. + PART_TYPE_AVR32_UC3C064C,
  8391. + PART_TYPE_AVR32_UC3C0128C,
  8392. + PART_TYPE_AVR32_UC3C0256C,
  8393. + PART_TYPE_AVR32_UC3C0512C,
  8394. + PART_TYPE_AVR32_UC3C164C,
  8395. + PART_TYPE_AVR32_UC3C1128C,
  8396. + PART_TYPE_AVR32_UC3C1256C,
  8397. + PART_TYPE_AVR32_UC3C1512C,
  8398. + PART_TYPE_AVR32_UC3C264C,
  8399. + PART_TYPE_AVR32_UC3C2128C,
  8400. + PART_TYPE_AVR32_UC3C2256C,
  8401. + PART_TYPE_AVR32_UC3C2512C,
  8402. + PART_TYPE_AVR32_MXT768E
  8403. +};
  8404. +
  8405. +/* Microarchitectures. */
  8406. +enum microarchitecture_type
  8407. +{
  8408. + UARCH_TYPE_AVR32A,
  8409. + UARCH_TYPE_AVR32B,
  8410. + UARCH_TYPE_NONE
  8411. +};
  8412. +
  8413. +/* Architectures types which specifies the pipeline.
  8414. + Keep this in sync with avr32_arch_types in avr32.c
  8415. + and the pipeline attribute in avr32.md */
  8416. +enum architecture_type
  8417. +{
  8418. + ARCH_TYPE_AVR32_AP,
  8419. + ARCH_TYPE_AVR32_UCR1,
  8420. + ARCH_TYPE_AVR32_UCR2,
  8421. + ARCH_TYPE_AVR32_UCR2NOMUL,
  8422. + ARCH_TYPE_AVR32_UCR3,
  8423. + ARCH_TYPE_AVR32_UCR3FP,
  8424. + ARCH_TYPE_AVR32_NONE
  8425. +};
  8426. +
  8427. +/* Flag specifying if the cpu has support for DSP instructions.*/
  8428. +#define FLAG_AVR32_HAS_DSP (1 << 0)
  8429. +/* Flag specifying if the cpu has support for Read-Modify-Write
  8430. + instructions.*/
  8431. +#define FLAG_AVR32_HAS_RMW (1 << 1)
  8432. +/* Flag specifying if the cpu has support for SIMD instructions. */
  8433. +#define FLAG_AVR32_HAS_SIMD (1 << 2)
  8434. +/* Flag specifying if the cpu has support for unaligned memory word access. */
  8435. +#define FLAG_AVR32_HAS_UNALIGNED_WORD (1 << 3)
  8436. +/* Flag specifying if the cpu has support for branch prediction. */
  8437. +#define FLAG_AVR32_HAS_BRANCH_PRED (1 << 4)
  8438. +/* Flag specifying if the cpu has support for a return stack. */
  8439. +#define FLAG_AVR32_HAS_RETURN_STACK (1 << 5)
  8440. +/* Flag specifying if the cpu has caches. */
  8441. +#define FLAG_AVR32_HAS_CACHES (1 << 6)
  8442. +/* Flag specifying if the cpu has support for v2 insns. */
  8443. +#define FLAG_AVR32_HAS_V2_INSNS (1 << 7)
  8444. +/* Flag specifying that the cpu has buggy mul insns. */
  8445. +#define FLAG_AVR32_HAS_NO_MUL_INSNS (1 << 8)
  8446. +/* Flag specifying that the device has FPU instructions according
  8447. + to AVR32002 specifications*/
  8448. +#define FLAG_AVR32_HAS_FPU (1 << 9)
  8449. +
  8450. +/* Structure for holding information about different avr32 CPUs/parts */
  8451. +struct part_type_s
  8452. +{
  8453. + const char *const name;
  8454. + enum part_type part_type;
  8455. + enum architecture_type arch_type;
  8456. + /* Must lie outside user's namespace. NULL == no macro. */
  8457. + const char *const macro;
  8458. +};
  8459. +
  8460. +/* Structure for holding information about different avr32 pipeline
  8461. + architectures. */
  8462. +struct arch_type_s
  8463. +{
  8464. + const char *const name;
  8465. + enum architecture_type arch_type;
  8466. + enum microarchitecture_type uarch_type;
  8467. + const unsigned long feature_flags;
  8468. + /* Must lie outside user's namespace. NULL == no macro. */
  8469. + const char *const macro;
  8470. +};
  8471. +
  8472. +extern const struct part_type_s *avr32_part;
  8473. +extern const struct arch_type_s *avr32_arch;
  8474. +
  8475. +#define TARGET_SIMD (avr32_arch->feature_flags & FLAG_AVR32_HAS_SIMD)
  8476. +#define TARGET_DSP (avr32_arch->feature_flags & FLAG_AVR32_HAS_DSP)
  8477. +#define TARGET_RMW (avr32_arch->feature_flags & FLAG_AVR32_HAS_RMW)
  8478. +#define TARGET_UNALIGNED_WORD (avr32_arch->feature_flags & FLAG_AVR32_HAS_UNALIGNED_WORD)
  8479. +#define TARGET_BRANCH_PRED (avr32_arch->feature_flags & FLAG_AVR32_HAS_BRANCH_PRED)
  8480. +#define TARGET_RETURN_STACK (avr32_arch->feature_flags & FLAG_AVR32_HAS_RETURN_STACK)
  8481. +#define TARGET_V2_INSNS (avr32_arch->feature_flags & FLAG_AVR32_HAS_V2_INSNS)
  8482. +#define TARGET_CACHES (avr32_arch->feature_flags & FLAG_AVR32_HAS_CACHES)
  8483. +#define TARGET_NO_MUL_INSNS (avr32_arch->feature_flags & FLAG_AVR32_HAS_NO_MUL_INSNS)
  8484. +#define TARGET_ARCH_AP (avr32_arch->arch_type == ARCH_TYPE_AVR32_AP)
  8485. +#define TARGET_ARCH_UCR1 (avr32_arch->arch_type == ARCH_TYPE_AVR32_UCR1)
  8486. +#define TARGET_ARCH_UCR2 (avr32_arch->arch_type == ARCH_TYPE_AVR32_UCR2)
  8487. +#define TARGET_ARCH_UC (TARGET_ARCH_UCR1 || TARGET_ARCH_UCR2)
  8488. +#define TARGET_UARCH_AVR32A (avr32_arch->uarch_type == UARCH_TYPE_AVR32A)
  8489. +#define TARGET_UARCH_AVR32B (avr32_arch->uarch_type == UARCH_TYPE_AVR32B)
  8490. +#define TARGET_ARCH_FPU (avr32_arch->feature_flags & FLAG_AVR32_HAS_FPU)
  8491. +
  8492. +#define CAN_DEBUG_WITHOUT_FP
  8493. +
  8494. +
  8495. +
  8496. +
  8497. +/******************************************************************************
  8498. + * Storage Layout
  8499. + *****************************************************************************/
  8500. +
  8501. +/*
  8502. +Define this macro to have the value 1 if the most significant bit in a
  8503. +byte has the lowest number; otherwise define it to have the value zero.
  8504. +This means that bit-field instructions count from the most significant
  8505. +bit. If the machine has no bit-field instructions, then this must still
  8506. +be defined, but it doesn't matter which value it is defined to. This
  8507. +macro need not be a constant.
  8508. +
  8509. +This macro does not affect the way structure fields are packed into
  8510. +bytes or words; that is controlled by BYTES_BIG_ENDIAN.
  8511. +*/
  8512. +#define BITS_BIG_ENDIAN 0
  8513. +
  8514. +/*
  8515. +Define this macro to have the value 1 if the most significant byte in a
  8516. +word has the lowest number. This macro need not be a constant.
  8517. +*/
  8518. +/*
  8519. + Data is stored in an big-endian way.
  8520. +*/
  8521. +#define BYTES_BIG_ENDIAN 1
  8522. +
  8523. +/*
  8524. +Define this macro to have the value 1 if, in a multiword object, the
  8525. +most significant word has the lowest number. This applies to both
  8526. +memory locations and registers; GCC fundamentally assumes that the
  8527. +order of words in memory is the same as the order in registers. This
  8528. +macro need not be a constant.
  8529. +*/
  8530. +/*
  8531. + Data is stored in an bin-endian way.
  8532. +*/
  8533. +#define WORDS_BIG_ENDIAN 1
  8534. +
  8535. +/*
  8536. +Define this macro if WORDS_BIG_ENDIAN is not constant. This must be a
  8537. +constant value with the same meaning as WORDS_BIG_ENDIAN, which will be
  8538. +used only when compiling libgcc2.c. Typically the value will be set
  8539. +based on preprocessor defines.
  8540. +*/
  8541. +#define LIBGCC2_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN
  8542. +
  8543. +/*
  8544. +Define this macro to have the value 1 if DFmode, XFmode or
  8545. +TFmode floating point numbers are stored in memory with the word
  8546. +containing the sign bit at the lowest address; otherwise define it to
  8547. +have the value 0. This macro need not be a constant.
  8548. +
  8549. +You need not define this macro if the ordering is the same as for
  8550. +multi-word integers.
  8551. +*/
  8552. +/* #define FLOAT_WORDS_BIG_ENDIAN 1 */
  8553. +
  8554. +/*
  8555. +Define this macro to be the number of bits in an addressable storage
  8556. +unit (byte); normally 8.
  8557. +*/
  8558. +#define BITS_PER_UNIT 8
  8559. +
  8560. +/*
  8561. +Number of bits in a word; normally 32.
  8562. +*/
  8563. +#define BITS_PER_WORD 32
  8564. +
  8565. +/*
  8566. +Maximum number of bits in a word. If this is undefined, the default is
  8567. +BITS_PER_WORD. Otherwise, it is the constant value that is the
  8568. +largest value that BITS_PER_WORD can have at run-time.
  8569. +*/
  8570. +/* MAX_BITS_PER_WORD not defined*/
  8571. +
  8572. +/*
  8573. +Number of storage units in a word; normally 4.
  8574. +*/
  8575. +#define UNITS_PER_WORD 4
  8576. +
  8577. +/*
  8578. +Minimum number of units in a word. If this is undefined, the default is
  8579. +UNITS_PER_WORD. Otherwise, it is the constant value that is the
  8580. +smallest value that UNITS_PER_WORD can have at run-time.
  8581. +*/
  8582. +/* MIN_UNITS_PER_WORD not defined */
  8583. +
  8584. +/*
  8585. +Width of a pointer, in bits. You must specify a value no wider than the
  8586. +width of Pmode. If it is not equal to the width of Pmode,
  8587. +you must define POINTERS_EXTEND_UNSIGNED.
  8588. +*/
  8589. +#define POINTER_SIZE 32
  8590. +
  8591. +/*
  8592. +A C expression whose value is greater than zero if pointers that need to be
  8593. +extended from being POINTER_SIZE bits wide to Pmode are to
  8594. +be zero-extended and zero if they are to be sign-extended. If the value
  8595. +is less then zero then there must be an "ptr_extend" instruction that
  8596. +extends a pointer from POINTER_SIZE to Pmode.
  8597. +
  8598. +You need not define this macro if the POINTER_SIZE is equal
  8599. +to the width of Pmode.
  8600. +*/
  8601. +/* #define POINTERS_EXTEND_UNSIGNED */
  8602. +
  8603. +/*
  8604. +A Macro to update M and UNSIGNEDP when an object whose type
  8605. +is TYPE and which has the specified mode and signedness is to be
  8606. +stored in a register. This macro is only called when TYPE is a
  8607. +scalar type.
  8608. +
  8609. +On most RISC machines, which only have operations that operate on a full
  8610. +register, define this macro to set M to word_mode if
  8611. +M is an integer mode narrower than BITS_PER_WORD. In most
  8612. +cases, only integer modes should be widened because wider-precision
  8613. +floating-point operations are usually more expensive than their narrower
  8614. +counterparts.
  8615. +
  8616. +For most machines, the macro definition does not change UNSIGNEDP.
  8617. +However, some machines, have instructions that preferentially handle
  8618. +either signed or unsigned quantities of certain modes. For example, on
  8619. +the DEC Alpha, 32-bit loads from memory and 32-bit add instructions
  8620. +sign-extend the result to 64 bits. On such machines, set
  8621. +UNSIGNEDP according to which kind of extension is more efficient.
  8622. +
  8623. +Do not define this macro if it would never modify M.
  8624. +*/
  8625. +#define PROMOTE_MODE(M, UNSIGNEDP, TYPE) \
  8626. + { \
  8627. + if (!AGGREGATE_TYPE_P (TYPE) \
  8628. + && GET_MODE_CLASS (mode) == MODE_INT \
  8629. + && GET_MODE_SIZE (mode) < 4) \
  8630. + { \
  8631. + if (M == QImode) \
  8632. + (UNSIGNEDP) = 1; \
  8633. + else if (M == HImode) \
  8634. + (UNSIGNEDP) = 0; \
  8635. + (M) = SImode; \
  8636. + } \
  8637. + }
  8638. +
  8639. +#define PROMOTE_FUNCTION_MODE(M, UNSIGNEDP, TYPE) \
  8640. + PROMOTE_MODE(M, UNSIGNEDP, TYPE)
  8641. +
  8642. +/* Define if operations between registers always perform the operation
  8643. + on the full register even if a narrower mode is specified. */
  8644. +#define WORD_REGISTER_OPERATIONS
  8645. +
  8646. +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
  8647. + will either zero-extend or sign-extend. The value of this macro should
  8648. + be the code that says which one of the two operations is implicitly
  8649. + done, UNKNOWN if not known. */
  8650. +#define LOAD_EXTEND_OP(MODE) \
  8651. + (((MODE) == QImode) ? ZERO_EXTEND \
  8652. + : ((MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)
  8653. +
  8654. +
  8655. +/*
  8656. +Normal alignment required for function parameters on the stack, in
  8657. +bits. All stack parameters receive at least this much alignment
  8658. +regardless of data type. On most machines, this is the same as the
  8659. +size of an integer.
  8660. +*/
  8661. +#define PARM_BOUNDARY 32
  8662. +
  8663. +/*
  8664. +Define this macro to the minimum alignment enforced by hardware for the
  8665. +stack pointer on this machine. The definition is a C expression for the
  8666. +desired alignment (measured in bits). This value is used as a default
  8667. +if PREFERRED_STACK_BOUNDARY is not defined. On most machines,
  8668. +this should be the same as PARM_BOUNDARY.
  8669. +*/
  8670. +#define STACK_BOUNDARY 32
  8671. +
  8672. +/*
  8673. +Define this macro if you wish to preserve a certain alignment for the
  8674. +stack pointer, greater than what the hardware enforces. The definition
  8675. +is a C expression for the desired alignment (measured in bits). This
  8676. +macro must evaluate to a value equal to or larger than
  8677. +STACK_BOUNDARY.
  8678. +*/
  8679. +#define PREFERRED_STACK_BOUNDARY (TARGET_FORCE_DOUBLE_ALIGN ? 64 : 32 )
  8680. +
  8681. +/*
  8682. +Alignment required for a function entry point, in bits.
  8683. +*/
  8684. +#define FUNCTION_BOUNDARY 16
  8685. +
  8686. +/*
  8687. +Biggest alignment that any data type can require on this machine, in bits.
  8688. +*/
  8689. +#define BIGGEST_ALIGNMENT (TARGET_FORCE_DOUBLE_ALIGN ? 64 : 32 )
  8690. +
  8691. +/*
  8692. +If defined, the smallest alignment, in bits, that can be given to an
  8693. +object that can be referenced in one operation, without disturbing any
  8694. +nearby object. Normally, this is BITS_PER_UNIT, but may be larger
  8695. +on machines that don't have byte or half-word store operations.
  8696. +*/
  8697. +#define MINIMUM_ATOMIC_ALIGNMENT BITS_PER_UNIT
  8698. +
  8699. +
  8700. +/*
  8701. +An integer expression for the size in bits of the largest integer machine mode that
  8702. +should actually be used. All integer machine modes of this size or smaller can be
  8703. +used for structures and unions with the appropriate sizes. If this macro is undefined,
  8704. +GET_MODE_BITSIZE (DImode) is assumed.*/
  8705. +#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
  8706. +
  8707. +
  8708. +/*
  8709. +If defined, a C expression to compute the alignment given to a constant
  8710. +that is being placed in memory. CONSTANT is the constant and
  8711. +BASIC_ALIGN is the alignment that the object would ordinarily
  8712. +have. The value of this macro is used instead of that alignment to
  8713. +align the object.
  8714. +
  8715. +If this macro is not defined, then BASIC_ALIGN is used.
  8716. +
  8717. +The typical use of this macro is to increase alignment for string
  8718. +constants to be word aligned so that strcpy calls that copy
  8719. +constants can be done inline.
  8720. +*/
  8721. +#define CONSTANT_ALIGNMENT(CONSTANT, BASIC_ALIGN) \
  8722. + ((TREE_CODE(CONSTANT) == STRING_CST) ? BITS_PER_WORD : BASIC_ALIGN)
  8723. +
  8724. +/* Try to align string to a word. */
  8725. +#define DATA_ALIGNMENT(TYPE, ALIGN) \
  8726. + ({(TREE_CODE (TYPE) == ARRAY_TYPE \
  8727. + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
  8728. + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN));})
  8729. +
  8730. +/* Try to align local store strings to a word. */
  8731. +#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
  8732. + ({(TREE_CODE (TYPE) == ARRAY_TYPE \
  8733. + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
  8734. + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN));})
  8735. +
  8736. +/*
  8737. +Define this macro to be the value 1 if instructions will fail to work
  8738. +if given data not on the nominal alignment. If instructions will merely
  8739. +go slower in that case, define this macro as 0.
  8740. +*/
  8741. +#define STRICT_ALIGNMENT 1
  8742. +
  8743. +/*
  8744. +Define this if you wish to imitate the way many other C compilers handle
  8745. +alignment of bit-fields and the structures that contain them.
  8746. +
  8747. +The behavior is that the type written for a bit-field (int,
  8748. +short, or other integer type) imposes an alignment for the
  8749. +entire structure, as if the structure really did contain an ordinary
  8750. +field of that type. In addition, the bit-field is placed within the
  8751. +structure so that it would fit within such a field, not crossing a
  8752. +boundary for it.
  8753. +
  8754. +Thus, on most machines, a bit-field whose type is written as int
  8755. +would not cross a four-byte boundary, and would force four-byte
  8756. +alignment for the whole structure. (The alignment used may not be four
  8757. +bytes; it is controlled by the other alignment parameters.)
  8758. +
  8759. +If the macro is defined, its definition should be a C expression;
  8760. +a nonzero value for the expression enables this behavior.
  8761. +
  8762. +Note that if this macro is not defined, or its value is zero, some
  8763. +bit-fields may cross more than one alignment boundary. The compiler can
  8764. +support such references if there are insv, extv, and
  8765. +extzv insns that can directly reference memory.
  8766. +
  8767. +The other known way of making bit-fields work is to define
  8768. +STRUCTURE_SIZE_BOUNDARY as large as BIGGEST_ALIGNMENT.
  8769. +Then every structure can be accessed with fullwords.
  8770. +
  8771. +Unless the machine has bit-field instructions or you define
  8772. +STRUCTURE_SIZE_BOUNDARY that way, you must define
  8773. +PCC_BITFIELD_TYPE_MATTERS to have a nonzero value.
  8774. +
  8775. +If your aim is to make GCC use the same conventions for laying out
  8776. +bit-fields as are used by another compiler, here is how to investigate
  8777. +what the other compiler does. Compile and run this program:
  8778. +
  8779. +struct foo1
  8780. +{
  8781. + char x;
  8782. + char :0;
  8783. + char y;
  8784. +};
  8785. +
  8786. +struct foo2
  8787. +{
  8788. + char x;
  8789. + int :0;
  8790. + char y;
  8791. +};
  8792. +
  8793. +main ()
  8794. +{
  8795. + printf ("Size of foo1 is %d\n",
  8796. + sizeof (struct foo1));
  8797. + printf ("Size of foo2 is %d\n",
  8798. + sizeof (struct foo2));
  8799. + exit (0);
  8800. +}
  8801. +
  8802. +If this prints 2 and 5, then the compiler's behavior is what you would
  8803. +get from PCC_BITFIELD_TYPE_MATTERS.
  8804. +*/
  8805. +#define PCC_BITFIELD_TYPE_MATTERS 1
  8806. +
  8807. +
  8808. +/******************************************************************************
  8809. + * Layout of Source Language Data Types
  8810. + *****************************************************************************/
  8811. +
  8812. +/*
  8813. +A C expression for the size in bits of the type int on the
  8814. +target machine. If you don't define this, the default is one word.
  8815. +*/
  8816. +#define INT_TYPE_SIZE 32
  8817. +
  8818. +/*
  8819. +A C expression for the size in bits of the type short on the
  8820. +target machine. If you don't define this, the default is half a word. (If
  8821. +this would be less than one storage unit, it is rounded up to one unit.)
  8822. +*/
  8823. +#define SHORT_TYPE_SIZE 16
  8824. +
  8825. +/*
  8826. +A C expression for the size in bits of the type long on the
  8827. +target machine. If you don't define this, the default is one word.
  8828. +*/
  8829. +#define LONG_TYPE_SIZE 32
  8830. +
  8831. +
  8832. +/*
  8833. +A C expression for the size in bits of the type long long on the
  8834. +target machine. If you don't define this, the default is two
  8835. +words. If you want to support GNU Ada on your machine, the value of this
  8836. +macro must be at least 64.
  8837. +*/
  8838. +#define LONG_LONG_TYPE_SIZE 64
  8839. +
  8840. +/*
  8841. +A C expression for the size in bits of the type char on the
  8842. +target machine. If you don't define this, the default is
  8843. +BITS_PER_UNIT.
  8844. +*/
  8845. +#define CHAR_TYPE_SIZE 8
  8846. +
  8847. +
  8848. +/*
  8849. +A C expression for the size in bits of the C++ type bool and
  8850. +C99 type _Bool on the target machine. If you don't define
  8851. +this, and you probably shouldn't, the default is CHAR_TYPE_SIZE.
  8852. +*/
  8853. +#define BOOL_TYPE_SIZE 8
  8854. +
  8855. +
  8856. +/*
  8857. +An expression whose value is 1 or 0, according to whether the type
  8858. +char should be signed or unsigned by default. The user can
  8859. +always override this default with the options -fsigned-char
  8860. +and -funsigned-char.
  8861. +*/
  8862. +/* We are using unsigned char */
  8863. +#define DEFAULT_SIGNED_CHAR 0
  8864. +
  8865. +
  8866. +/*
  8867. +A C expression for a string describing the name of the data type to use
  8868. +for size values. The typedef name size_t is defined using the
  8869. +contents of the string.
  8870. +
  8871. +The string can contain more than one keyword. If so, separate them with
  8872. +spaces, and write first any length keyword, then unsigned if
  8873. +appropriate, and finally int. The string must exactly match one
  8874. +of the data type names defined in the function
  8875. +init_decl_processing in the file c-decl.c. You may not
  8876. +omit int or change the order - that would cause the compiler to
  8877. +crash on startup.
  8878. +
  8879. +If you don't define this macro, the default is "long unsigned int".
  8880. +*/
  8881. +#define SIZE_TYPE "long unsigned int"
  8882. +
  8883. +/*
  8884. +A C expression for a string describing the name of the data type to use
  8885. +for the result of subtracting two pointers. The typedef name
  8886. +ptrdiff_t is defined using the contents of the string. See
  8887. +SIZE_TYPE above for more information.
  8888. +
  8889. +If you don't define this macro, the default is "long int".
  8890. +*/
  8891. +#define PTRDIFF_TYPE "long int"
  8892. +
  8893. +
  8894. +/*
  8895. +A C expression for the size in bits of the data type for wide
  8896. +characters. This is used in cpp, which cannot make use of
  8897. +WCHAR_TYPE.
  8898. +*/
  8899. +#define WCHAR_TYPE_SIZE 32
  8900. +
  8901. +
  8902. +/*
  8903. +A C expression for a string describing the name of the data type to
  8904. +use for wide characters passed to printf and returned from
  8905. +getwc. The typedef name wint_t is defined using the
  8906. +contents of the string. See SIZE_TYPE above for more
  8907. +information.
  8908. +
  8909. +If you don't define this macro, the default is "unsigned int".
  8910. +*/
  8911. +#define WINT_TYPE "unsigned int"
  8912. +
  8913. +/*
  8914. +A C expression for a string describing the name of the data type that
  8915. +can represent any value of any standard or extended signed integer type.
  8916. +The typedef name intmax_t is defined using the contents of the
  8917. +string. See SIZE_TYPE above for more information.
  8918. +
  8919. +If you don't define this macro, the default is the first of
  8920. +"int", "long int", or "long long int" that has as
  8921. +much precision as long long int.
  8922. +*/
  8923. +#define INTMAX_TYPE "long long int"
  8924. +
  8925. +/*
  8926. +A C expression for a string describing the name of the data type that
  8927. +can represent any value of any standard or extended unsigned integer
  8928. +type. The typedef name uintmax_t is defined using the contents
  8929. +of the string. See SIZE_TYPE above for more information.
  8930. +
  8931. +If you don't define this macro, the default is the first of
  8932. +"unsigned int", "long unsigned int", or "long long unsigned int"
  8933. +that has as much precision as long long unsigned int.
  8934. +*/
  8935. +#define UINTMAX_TYPE "long long unsigned int"
  8936. +
  8937. +
  8938. +/******************************************************************************
  8939. + * Register Usage
  8940. + *****************************************************************************/
  8941. +
  8942. +/* Convert from gcc internal register number to register number
  8943. + used in assembly code */
  8944. +#define ASM_REGNUM(reg) (LAST_REGNUM - (reg))
  8945. +
  8946. +/* Convert between register number used in assembly to gcc
  8947. + internal register number */
  8948. +#define INTERNAL_REGNUM(reg) (LAST_REGNUM - (reg))
  8949. +
  8950. +/** Basic Characteristics of Registers **/
  8951. +
  8952. +/*
  8953. +Number of hardware registers known to the compiler. They receive
  8954. +numbers 0 through FIRST_PSEUDO_REGISTER-1; thus, the first
  8955. +pseudo register's number really is assigned the number
  8956. +FIRST_PSEUDO_REGISTER.
  8957. +*/
  8958. +#define FIRST_PSEUDO_REGISTER (LAST_REGNUM + 1)
  8959. +
  8960. +#define FIRST_REGNUM 0
  8961. +#define LAST_REGNUM 15
  8962. +
  8963. +/*
  8964. +An initializer that says which registers are used for fixed purposes
  8965. +all throughout the compiled code and are therefore not available for
  8966. +general allocation. These would include the stack pointer, the frame
  8967. +pointer (except on machines where that can be used as a general
  8968. +register when no frame pointer is needed), the program counter on
  8969. +machines where that is considered one of the addressable registers,
  8970. +and any other numbered register with a standard use.
  8971. +
  8972. +This information is expressed as a sequence of numbers, separated by
  8973. +commas and surrounded by braces. The nth number is 1 if
  8974. +register n is fixed, 0 otherwise.
  8975. +
  8976. +The table initialized from this macro, and the table initialized by
  8977. +the following one, may be overridden at run time either automatically,
  8978. +by the actions of the macro CONDITIONAL_REGISTER_USAGE, or by
  8979. +the user with the command options -ffixed-[reg],
  8980. +-fcall-used-[reg] and -fcall-saved-[reg].
  8981. +*/
  8982. +
  8983. +/* The internal gcc register numbers are reversed
  8984. + compared to the real register numbers since
  8985. + gcc expects data types stored over multiple
  8986. + registers in the register file to be big endian
  8987. + if the memory layout is big endian. But this
  8988. + is not the case for avr32 so we fake a big
  8989. + endian register file. */
  8990. +
  8991. +#define FIXED_REGISTERS { \
  8992. + 1, /* Program Counter */ \
  8993. + 0, /* Link Register */ \
  8994. + 1, /* Stack Pointer */ \
  8995. + 0, /* r12 */ \
  8996. + 0, /* r11 */ \
  8997. + 0, /* r10 */ \
  8998. + 0, /* r9 */ \
  8999. + 0, /* r8 */ \
  9000. + 0, /* r7 */ \
  9001. + 0, /* r6 */ \
  9002. + 0, /* r5 */ \
  9003. + 0, /* r4 */ \
  9004. + 0, /* r3 */ \
  9005. + 0, /* r2 */ \
  9006. + 0, /* r1 */ \
  9007. + 0, /* r0 */ \
  9008. +}
  9009. +
  9010. +/*
  9011. +Like FIXED_REGISTERS but has 1 for each register that is
  9012. +clobbered (in general) by function calls as well as for fixed
  9013. +registers. This macro therefore identifies the registers that are not
  9014. +available for general allocation of values that must live across
  9015. +function calls.
  9016. +
  9017. +If a register has 0 in CALL_USED_REGISTERS, the compiler
  9018. +automatically saves it on function entry and restores it on function
  9019. +exit, if the register is used within the function.
  9020. +*/
  9021. +#define CALL_USED_REGISTERS { \
  9022. + 1, /* Program Counter */ \
  9023. + 0, /* Link Register */ \
  9024. + 1, /* Stack Pointer */ \
  9025. + 1, /* r12 */ \
  9026. + 1, /* r11 */ \
  9027. + 1, /* r10 */ \
  9028. + 1, /* r9 */ \
  9029. + 1, /* r8 */ \
  9030. + 0, /* r7 */ \
  9031. + 0, /* r6 */ \
  9032. + 0, /* r5 */ \
  9033. + 0, /* r4 */ \
  9034. + 0, /* r3 */ \
  9035. + 0, /* r2 */ \
  9036. + 0, /* r1 */ \
  9037. + 0, /* r0 */ \
  9038. +}
  9039. +
  9040. +/* Interrupt functions can only use registers that have already been
  9041. + saved by the prologue, even if they would normally be
  9042. + call-clobbered. */
  9043. +#define HARD_REGNO_RENAME_OK(SRC, DST) \
  9044. + (! IS_INTERRUPT (cfun->machine->func_type) || \
  9045. + df_regs_ever_live_p (DST))
  9046. +
  9047. +
  9048. +/*
  9049. +Zero or more C statements that may conditionally modify five variables
  9050. +fixed_regs, call_used_regs, global_regs,
  9051. +reg_names, and reg_class_contents, to take into account
  9052. +any dependence of these register sets on target flags. The first three
  9053. +of these are of type char [] (interpreted as Boolean vectors).
  9054. +global_regs is a const char *[], and
  9055. +reg_class_contents is a HARD_REG_SET. Before the macro is
  9056. +called, fixed_regs, call_used_regs,
  9057. +reg_class_contents, and reg_names have been initialized
  9058. +from FIXED_REGISTERS, CALL_USED_REGISTERS,
  9059. +REG_CLASS_CONTENTS, and REGISTER_NAMES, respectively.
  9060. +global_regs has been cleared, and any -ffixed-[reg],
  9061. +-fcall-used-[reg] and -fcall-saved-[reg]
  9062. +command options have been applied.
  9063. +
  9064. +You need not define this macro if it has no work to do.
  9065. +
  9066. +If the usage of an entire class of registers depends on the target
  9067. +flags, you may indicate this to GCC by using this macro to modify
  9068. +fixed_regs and call_used_regs to 1 for each of the
  9069. +registers in the classes which should not be used by GCC. Also define
  9070. +the macro REG_CLASS_FROM_LETTER to return NO_REGS if it
  9071. +is called with a letter for a class that shouldn't be used.
  9072. +
  9073. + (However, if this class is not included in GENERAL_REGS and all
  9074. +of the insn patterns whose constraints permit this class are
  9075. +controlled by target switches, then GCC will automatically avoid using
  9076. +these registers when the target switches are opposed to them.)
  9077. +*/
  9078. +#define CONDITIONAL_REGISTER_USAGE \
  9079. + do \
  9080. + { \
  9081. + if (flag_pic) \
  9082. + { \
  9083. + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
  9084. + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
  9085. + } \
  9086. + } \
  9087. + while (0)
  9088. +
  9089. +
  9090. +/*
  9091. +If the program counter has a register number, define this as that
  9092. +register number. Otherwise, do not define it.
  9093. +*/
  9094. +
  9095. +#define LAST_AVR32_REGNUM 16
  9096. +
  9097. +
  9098. +/** Order of Allocation of Registers **/
  9099. +
  9100. +/*
  9101. +If defined, an initializer for a vector of integers, containing the
  9102. +numbers of hard registers in the order in which GCC should prefer
  9103. +to use them (from most preferred to least).
  9104. +
  9105. +If this macro is not defined, registers are used lowest numbered first
  9106. +(all else being equal).
  9107. +
  9108. +One use of this macro is on machines where the highest numbered
  9109. +registers must always be saved and the save-multiple-registers
  9110. +instruction supports only sequences of consecutive registers. On such
  9111. +machines, define REG_ALLOC_ORDER to be an initializer that lists
  9112. +the highest numbered allocable register first.
  9113. +*/
  9114. +#define REG_ALLOC_ORDER \
  9115. +{ \
  9116. + INTERNAL_REGNUM(8), \
  9117. + INTERNAL_REGNUM(9), \
  9118. + INTERNAL_REGNUM(10), \
  9119. + INTERNAL_REGNUM(11), \
  9120. + INTERNAL_REGNUM(12), \
  9121. + LR_REGNUM, \
  9122. + INTERNAL_REGNUM(7), \
  9123. + INTERNAL_REGNUM(6), \
  9124. + INTERNAL_REGNUM(5), \
  9125. + INTERNAL_REGNUM(4), \
  9126. + INTERNAL_REGNUM(3), \
  9127. + INTERNAL_REGNUM(2), \
  9128. + INTERNAL_REGNUM(1), \
  9129. + INTERNAL_REGNUM(0), \
  9130. + SP_REGNUM, \
  9131. + PC_REGNUM \
  9132. +}
  9133. +
  9134. +
  9135. +/** How Values Fit in Registers **/
  9136. +
  9137. +/*
  9138. +A C expression for the number of consecutive hard registers, starting
  9139. +at register number REGNO, required to hold a value of mode
  9140. +MODE.
  9141. +
  9142. +On a machine where all registers are exactly one word, a suitable
  9143. +definition of this macro is
  9144. +
  9145. +#define HARD_REGNO_NREGS(REGNO, MODE) \
  9146. + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
  9147. + / UNITS_PER_WORD)
  9148. +*/
  9149. +#define HARD_REGNO_NREGS(REGNO, MODE) \
  9150. + ((unsigned int)((GET_MODE_SIZE(MODE) + UNITS_PER_WORD -1 ) / UNITS_PER_WORD))
  9151. +
  9152. +/*
  9153. +A C expression that is nonzero if it is permissible to store a value
  9154. +of mode MODE in hard register number REGNO (or in several
  9155. +registers starting with that one). For a machine where all registers
  9156. +are equivalent, a suitable definition is
  9157. +
  9158. + #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
  9159. +
  9160. +You need not include code to check for the numbers of fixed registers,
  9161. +because the allocation mechanism considers them to be always occupied.
  9162. +
  9163. +On some machines, double-precision values must be kept in even/odd
  9164. +register pairs. You can implement that by defining this macro to reject
  9165. +odd register numbers for such modes.
  9166. +
  9167. +The minimum requirement for a mode to be OK in a register is that the
  9168. +mov[mode] instruction pattern support moves between the
  9169. +register and other hard register in the same class and that moving a
  9170. +value into the register and back out not alter it.
  9171. +
  9172. +Since the same instruction used to move word_mode will work for
  9173. +all narrower integer modes, it is not necessary on any machine for
  9174. +HARD_REGNO_MODE_OK to distinguish between these modes, provided
  9175. +you define patterns movhi, etc., to take advantage of this. This
  9176. +is useful because of the interaction between HARD_REGNO_MODE_OK
  9177. +and MODES_TIEABLE_P; it is very desirable for all integer modes
  9178. +to be tieable.
  9179. +
  9180. +Many machines have special registers for floating point arithmetic.
  9181. +Often people assume that floating point machine modes are allowed only
  9182. +in floating point registers. This is not true. Any registers that
  9183. +can hold integers can safely hold a floating point machine
  9184. +mode, whether or not floating arithmetic can be done on it in those
  9185. +registers. Integer move instructions can be used to move the values.
  9186. +
  9187. +On some machines, though, the converse is true: fixed-point machine
  9188. +modes may not go in floating registers. This is true if the floating
  9189. +registers normalize any value stored in them, because storing a
  9190. +non-floating value there would garble it. In this case,
  9191. +HARD_REGNO_MODE_OK should reject fixed-point machine modes in
  9192. +floating registers. But if the floating registers do not automatically
  9193. +normalize, if you can store any bit pattern in one and retrieve it
  9194. +unchanged without a trap, then any machine mode may go in a floating
  9195. +register, so you can define this macro to say so.
  9196. +
  9197. +The primary significance of special floating registers is rather that
  9198. +they are the registers acceptable in floating point arithmetic
  9199. +instructions. However, this is of no concern to
  9200. +HARD_REGNO_MODE_OK. You handle it by writing the proper
  9201. +constraints for those instructions.
  9202. +
  9203. +On some machines, the floating registers are especially slow to access,
  9204. +so that it is better to store a value in a stack frame than in such a
  9205. +register if floating point arithmetic is not being done. As long as the
  9206. +floating registers are not in class GENERAL_REGS, they will not
  9207. +be used unless some pattern's constraint asks for one.
  9208. +*/
  9209. +#define HARD_REGNO_MODE_OK(REGNO, MODE) avr32_hard_regno_mode_ok(REGNO, MODE)
  9210. +
  9211. +/*
  9212. +A C expression that is nonzero if a value of mode
  9213. +MODE1 is accessible in mode MODE2 without copying.
  9214. +
  9215. +If HARD_REGNO_MODE_OK(R, MODE1) and
  9216. +HARD_REGNO_MODE_OK(R, MODE2) are always the same for
  9217. +any R, then MODES_TIEABLE_P(MODE1, MODE2)
  9218. +should be nonzero. If they differ for any R, you should define
  9219. +this macro to return zero unless some other mechanism ensures the
  9220. +accessibility of the value in a narrower mode.
  9221. +
  9222. +You should define this macro to return nonzero in as many cases as
  9223. +possible since doing so will allow GCC to perform better register
  9224. +allocation.
  9225. +*/
  9226. +#define MODES_TIEABLE_P(MODE1, MODE2) \
  9227. + (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
  9228. +
  9229. +
  9230. +
  9231. +/******************************************************************************
  9232. + * Register Classes
  9233. + *****************************************************************************/
  9234. +
  9235. +/*
  9236. +An enumeral type that must be defined with all the register class names
  9237. +as enumeral values. NO_REGS must be first. ALL_REGS
  9238. +must be the last register class, followed by one more enumeral value,
  9239. +LIM_REG_CLASSES, which is not a register class but rather
  9240. +tells how many classes there are.
  9241. +
  9242. +Each register class has a number, which is the value of casting
  9243. +the class name to type int. The number serves as an index
  9244. +in many of the tables described below.
  9245. +*/
  9246. +enum reg_class
  9247. +{
  9248. + NO_REGS,
  9249. + GENERAL_REGS,
  9250. + ALL_REGS,
  9251. + LIM_REG_CLASSES
  9252. +};
  9253. +
  9254. +/*
  9255. +The number of distinct register classes, defined as follows:
  9256. + #define N_REG_CLASSES (int) LIM_REG_CLASSES
  9257. +*/
  9258. +#define N_REG_CLASSES (int)LIM_REG_CLASSES
  9259. +
  9260. +/*
  9261. +An initializer containing the names of the register classes as C string
  9262. +constants. These names are used in writing some of the debugging dumps.
  9263. +*/
  9264. +#define REG_CLASS_NAMES \
  9265. +{ \
  9266. + "NO_REGS", \
  9267. + "GENERAL_REGS", \
  9268. + "ALL_REGS" \
  9269. +}
  9270. +
  9271. +/*
  9272. +An initializer containing the contents of the register classes, as integers
  9273. +which are bit masks. The nth integer specifies the contents of class
  9274. +n. The way the integer mask is interpreted is that
  9275. +register r is in the class if mask & (1 << r) is 1.
  9276. +
  9277. +When the machine has more than 32 registers, an integer does not suffice.
  9278. +Then the integers are replaced by sub-initializers, braced groupings containing
  9279. +several integers. Each sub-initializer must be suitable as an initializer
  9280. +for the type HARD_REG_SET which is defined in hard-reg-set.h.
  9281. +In this situation, the first integer in each sub-initializer corresponds to
  9282. +registers 0 through 31, the second integer to registers 32 through 63, and
  9283. +so on.
  9284. +*/
  9285. +#define REG_CLASS_CONTENTS { \
  9286. + {0x00000000}, /* NO_REGS */ \
  9287. + {0x0000FFFF}, /* GENERAL_REGS */ \
  9288. + {0x7FFFFFFF}, /* ALL_REGS */ \
  9289. +}
  9290. +
  9291. +
  9292. +/*
  9293. +A C expression whose value is a register class containing hard register
  9294. +REGNO. In general there is more than one such class; choose a class
  9295. +which is minimal, meaning that no smaller class also contains the
  9296. +register.
  9297. +*/
  9298. +#define REGNO_REG_CLASS(REGNO) (GENERAL_REGS)
  9299. +
  9300. +/*
  9301. +A macro whose definition is the name of the class to which a valid
  9302. +base register must belong. A base register is one used in an address
  9303. +which is the register value plus a displacement.
  9304. +*/
  9305. +#define BASE_REG_CLASS GENERAL_REGS
  9306. +
  9307. +/*
  9308. +This is a variation of the BASE_REG_CLASS macro which allows
  9309. +the selection of a base register in a mode depenedent manner. If
  9310. +mode is VOIDmode then it should return the same value as
  9311. +BASE_REG_CLASS.
  9312. +*/
  9313. +#define MODE_BASE_REG_CLASS(MODE) BASE_REG_CLASS
  9314. +
  9315. +/*
  9316. +A macro whose definition is the name of the class to which a valid
  9317. +index register must belong. An index register is one used in an
  9318. +address where its value is either multiplied by a scale factor or
  9319. +added to another register (as well as added to a displacement).
  9320. +*/
  9321. +#define INDEX_REG_CLASS BASE_REG_CLASS
  9322. +
  9323. +/*
  9324. +A C expression which defines the machine-dependent operand constraint
  9325. +letters for register classes. If CHAR is such a letter, the
  9326. +value should be the register class corresponding to it. Otherwise,
  9327. +the value should be NO_REGS. The register letter r,
  9328. +corresponding to class GENERAL_REGS, will not be passed
  9329. +to this macro; you do not need to handle it.
  9330. +*/
  9331. +#define REG_CLASS_FROM_LETTER(CHAR) NO_REGS
  9332. +
  9333. +/* These assume that REGNO is a hard or pseudo reg number.
  9334. + They give nonzero only if REGNO is a hard reg of the suitable class
  9335. + or a pseudo reg currently allocated to a suitable hard reg.
  9336. + Since they use reg_renumber, they are safe only once reg_renumber
  9337. + has been allocated, which happens in local-alloc.c. */
  9338. +#define TEST_REGNO(R, TEST, VALUE) \
  9339. + ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
  9340. +
  9341. +/*
  9342. +A C expression which is nonzero if register number num is suitable for use as a base
  9343. +register in operand addresses. It may be either a suitable hard register or a pseudo
  9344. +register that has been allocated such a hard register.
  9345. +*/
  9346. +#define REGNO_OK_FOR_BASE_P(NUM) TEST_REGNO(NUM, <=, LAST_REGNUM)
  9347. +
  9348. +/* The following macro defines cover classes for Integrated Register
  9349. + Allocator. Cover classes is a set of non-intersected register
  9350. + classes covering all hard registers used for register allocation
  9351. + purpose. Any move between two registers of a cover class should be
  9352. + cheaper than load or store of the registers. The macro value is
  9353. + array of register classes with LIM_REG_CLASSES used as the end
  9354. + marker. */
  9355. +
  9356. +#define IRA_COVER_CLASSES \
  9357. +{ \
  9358. + GENERAL_REGS, LIM_REG_CLASSES \
  9359. +}
  9360. +
  9361. +/*
  9362. +A C expression which is nonzero if register number NUM is
  9363. +suitable for use as an index register in operand addresses. It may be
  9364. +either a suitable hard register or a pseudo register that has been
  9365. +allocated such a hard register.
  9366. +
  9367. +The difference between an index register and a base register is that
  9368. +the index register may be scaled. If an address involves the sum of
  9369. +two registers, neither one of them scaled, then either one may be
  9370. +labeled the ``base'' and the other the ``index''; but whichever
  9371. +labeling is used must fit the machine's constraints of which registers
  9372. +may serve in each capacity. The compiler will try both labelings,
  9373. +looking for one that is valid, and will reload one or both registers
  9374. +only if neither labeling works.
  9375. +*/
  9376. +#define REGNO_OK_FOR_INDEX_P(NUM) TEST_REGNO(NUM, <=, LAST_REGNUM)
  9377. +
  9378. +/*
  9379. +A C expression that places additional restrictions on the register class
  9380. +to use when it is necessary to copy value X into a register in class
  9381. +CLASS. The value is a register class; perhaps CLASS, or perhaps
  9382. +another, smaller class. On many machines, the following definition is
  9383. +safe: #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
  9384. +
  9385. +Sometimes returning a more restrictive class makes better code. For
  9386. +example, on the 68000, when X is an integer constant that is in range
  9387. +for a 'moveq' instruction, the value of this macro is always
  9388. +DATA_REGS as long as CLASS includes the data registers.
  9389. +Requiring a data register guarantees that a 'moveq' will be used.
  9390. +
  9391. +If X is a const_double, by returning NO_REGS
  9392. +you can force X into a memory constant. This is useful on
  9393. +certain machines where immediate floating values cannot be loaded into
  9394. +certain kinds of registers.
  9395. +*/
  9396. +#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
  9397. +
  9398. +
  9399. +
  9400. +/*
  9401. +A C expression for the maximum number of consecutive registers
  9402. +of class CLASS needed to hold a value of mode MODE.
  9403. +
  9404. +This is closely related to the macro HARD_REGNO_NREGS. In fact,
  9405. +the value of the macro CLASS_MAX_NREGS(CLASS, MODE)
  9406. +should be the maximum value of HARD_REGNO_NREGS(REGNO, MODE)
  9407. +for all REGNO values in the class CLASS.
  9408. +
  9409. +This macro helps control the handling of multiple-word values
  9410. +in the reload pass.
  9411. +*/
  9412. +#define CLASS_MAX_NREGS(CLASS, MODE) /* ToDo:fixme */ \
  9413. + (unsigned int)((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
  9414. +
  9415. +
  9416. +/*
  9417. + Using CONST_OK_FOR_CONSTRAINT_P instead of CONS_OK_FOR_LETTER_P
  9418. + in order to support constraints with more than one letter.
  9419. + Only two letters are then used for constant constraints,
  9420. + the letter 'K' and the letter 'I'. The constraint starting with
  9421. + these letters must consist of four characters. The character following
  9422. + 'K' or 'I' must be either 'u' (unsigned) or 's' (signed) to specify
  9423. + if the constant is zero or sign extended. The last two characters specify
  9424. + the length in bits of the constant. The base constraint letter 'I' means
  9425. + that this is an negated constant, meaning that actually -VAL should be
  9426. + checked to lie withing the valid range instead of VAL which is used when
  9427. + 'K' is the base constraint letter.
  9428. +
  9429. +*/
  9430. +
  9431. +#define CONSTRAINT_LEN(C, STR) \
  9432. + ( ((C) == 'K' || (C) == 'I') ? 4 : \
  9433. + ((C) == 'R') ? 5 : \
  9434. + ((C) == 'P') ? -1 : \
  9435. + DEFAULT_CONSTRAINT_LEN((C), (STR)) )
  9436. +
  9437. +#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
  9438. + avr32_const_ok_for_constraint_p(VALUE, C, STR)
  9439. +
  9440. +/*
  9441. +A C expression that defines the machine-dependent operand constraint
  9442. +letters that specify particular ranges of const_double values ('G' or 'H').
  9443. +
  9444. +If C is one of those letters, the expression should check that
  9445. +VALUE, an RTX of code const_double, is in the appropriate
  9446. +range and return 1 if so, 0 otherwise. If C is not one of those
  9447. +letters, the value should be 0 regardless of VALUE.
  9448. +
  9449. +const_double is used for all floating-point constants and for
  9450. +DImode fixed-point constants. A given letter can accept either
  9451. +or both kinds of values. It can use GET_MODE to distinguish
  9452. +between these kinds.
  9453. +*/
  9454. +#define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
  9455. + ((C) == 'G' ? avr32_const_double_immediate(OP) : 0)
  9456. +
  9457. +/*
  9458. +A C expression that defines the optional machine-dependent constraint
  9459. +letters that can be used to segregate specific types of operands, usually
  9460. +memory references, for the target machine. Any letter that is not
  9461. +elsewhere defined and not matched by REG_CLASS_FROM_LETTER
  9462. +may be used. Normally this macro will not be defined.
  9463. +
  9464. +If it is required for a particular target machine, it should return 1
  9465. +if VALUE corresponds to the operand type represented by the
  9466. +constraint letter C. If C is not defined as an extra
  9467. +constraint, the value returned should be 0 regardless of VALUE.
  9468. +
  9469. +For example, on the ROMP, load instructions cannot have their output
  9470. +in r0 if the memory reference contains a symbolic address. Constraint
  9471. +letter 'Q' is defined as representing a memory address that does
  9472. +not contain a symbolic address. An alternative is specified with
  9473. +a 'Q' constraint on the input and 'r' on the output. The next
  9474. +alternative specifies 'm' on the input and a register class that
  9475. +does not include r0 on the output.
  9476. +*/
  9477. +#define EXTRA_CONSTRAINT_STR(OP, C, STR) \
  9478. + ((C) == 'W' ? avr32_address_operand(OP, GET_MODE(OP)) : \
  9479. + (C) == 'R' ? (avr32_indirect_register_operand(OP, GET_MODE(OP)) || \
  9480. + (avr32_imm_disp_memory_operand(OP, GET_MODE(OP)) \
  9481. + && avr32_const_ok_for_constraint_p( \
  9482. + INTVAL(XEXP(XEXP(OP, 0), 1)), \
  9483. + (STR)[1], &(STR)[1]))) : \
  9484. + (C) == 'S' ? avr32_indexed_memory_operand(OP, GET_MODE(OP)) : \
  9485. + (C) == 'T' ? avr32_const_pool_ref_operand(OP, GET_MODE(OP)) : \
  9486. + (C) == 'U' ? SYMBOL_REF_RCALL_FUNCTION_P(OP) : \
  9487. + (C) == 'Z' ? avr32_cop_memory_operand(OP, GET_MODE(OP)) : \
  9488. + (C) == 'Q' ? avr32_non_rmw_memory_operand(OP, GET_MODE(OP)) : \
  9489. + (C) == 'Y' ? avr32_rmw_memory_operand(OP, GET_MODE(OP)) : \
  9490. + 0)
  9491. +
  9492. +
  9493. +#define EXTRA_MEMORY_CONSTRAINT(C, STR) ( ((C) == 'R') || \
  9494. + ((C) == 'Q') || \
  9495. + ((C) == 'S') || \
  9496. + ((C) == 'Y') || \
  9497. + ((C) == 'Z') )
  9498. +
  9499. +
  9500. +/* Returns nonzero if op is a function SYMBOL_REF which
  9501. + can be called using an rcall instruction */
  9502. +#define SYMBOL_REF_RCALL_FUNCTION_P(op) \
  9503. + ( GET_CODE(op) == SYMBOL_REF \
  9504. + && SYMBOL_REF_FUNCTION_P(op) \
  9505. + && SYMBOL_REF_LOCAL_P(op) \
  9506. + && !SYMBOL_REF_EXTERNAL_P(op) \
  9507. + && !TARGET_HAS_ASM_ADDR_PSEUDOS )
  9508. +
  9509. +/******************************************************************************
  9510. + * Stack Layout and Calling Conventions
  9511. + *****************************************************************************/
  9512. +
  9513. +/** Basic Stack Layout **/
  9514. +
  9515. +/*
  9516. +Define this macro if pushing a word onto the stack moves the stack
  9517. +pointer to a smaller address.
  9518. +
  9519. +When we say, ``define this macro if ...,'' it means that the
  9520. +compiler checks this macro only with #ifdef so the precise
  9521. +definition used does not matter.
  9522. +*/
  9523. +/* pushm decrece SP: *(--SP) <-- Rx */
  9524. +#define STACK_GROWS_DOWNWARD
  9525. +
  9526. +/*
  9527. +This macro defines the operation used when something is pushed
  9528. +on the stack. In RTL, a push operation will be
  9529. +(set (mem (STACK_PUSH_CODE (reg sp))) ...)
  9530. +
  9531. +The choices are PRE_DEC, POST_DEC, PRE_INC,
  9532. +and POST_INC. Which of these is correct depends on
  9533. +the stack direction and on whether the stack pointer points
  9534. +to the last item on the stack or whether it points to the
  9535. +space for the next item on the stack.
  9536. +
  9537. +The default is PRE_DEC when STACK_GROWS_DOWNWARD is
  9538. +defined, which is almost always right, and PRE_INC otherwise,
  9539. +which is often wrong.
  9540. +*/
  9541. +/* pushm: *(--SP) <-- Rx */
  9542. +#define STACK_PUSH_CODE PRE_DEC
  9543. +
  9544. +/* Define this to nonzero if the nominal address of the stack frame
  9545. + is at the high-address end of the local variables;
  9546. + that is, each additional local variable allocated
  9547. + goes at a more negative offset in the frame. */
  9548. +#define FRAME_GROWS_DOWNWARD 1
  9549. +
  9550. +
  9551. +/*
  9552. +Offset from the frame pointer to the first local variable slot to be allocated.
  9553. +
  9554. +If FRAME_GROWS_DOWNWARD, find the next slot's offset by
  9555. +subtracting the first slot's length from STARTING_FRAME_OFFSET.
  9556. +Otherwise, it is found by adding the length of the first slot to the
  9557. +value STARTING_FRAME_OFFSET.
  9558. + (i'm not sure if the above is still correct.. had to change it to get
  9559. + rid of an overfull. --mew 2feb93 )
  9560. +*/
  9561. +#define STARTING_FRAME_OFFSET 0
  9562. +
  9563. +/*
  9564. +Offset from the stack pointer register to the first location at which
  9565. +outgoing arguments are placed. If not specified, the default value of
  9566. +zero is used. This is the proper value for most machines.
  9567. +
  9568. +If ARGS_GROW_DOWNWARD, this is the offset to the location above
  9569. +the first location at which outgoing arguments are placed.
  9570. +*/
  9571. +#define STACK_POINTER_OFFSET 0
  9572. +
  9573. +/*
  9574. +Offset from the argument pointer register to the first argument's
  9575. +address. On some machines it may depend on the data type of the
  9576. +function.
  9577. +
  9578. +If ARGS_GROW_DOWNWARD, this is the offset to the location above
  9579. +the first argument's address.
  9580. +*/
  9581. +#define FIRST_PARM_OFFSET(FUNDECL) 0
  9582. +
  9583. +
  9584. +/*
  9585. +A C expression whose value is RTL representing the address in a stack
  9586. +frame where the pointer to the caller's frame is stored. Assume that
  9587. +FRAMEADDR is an RTL expression for the address of the stack frame
  9588. +itself.
  9589. +
  9590. +If you don't define this macro, the default is to return the value
  9591. +of FRAMEADDR - that is, the stack frame address is also the
  9592. +address of the stack word that points to the previous frame.
  9593. +*/
  9594. +#define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) plus_constant ((FRAMEADDR), 4)
  9595. +
  9596. +
  9597. +/*
  9598. +A C expression whose value is RTL representing the value of the return
  9599. +address for the frame COUNT steps up from the current frame, after
  9600. +the prologue. FRAMEADDR is the frame pointer of the COUNT
  9601. +frame, or the frame pointer of the COUNT - 1 frame if
  9602. +RETURN_ADDR_IN_PREVIOUS_FRAME is defined.
  9603. +
  9604. +The value of the expression must always be the correct address when
  9605. +COUNT is zero, but may be NULL_RTX if there is not way to
  9606. +determine the return address of other frames.
  9607. +*/
  9608. +#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) avr32_return_addr(COUNT, FRAMEADDR)
  9609. +
  9610. +
  9611. +/*
  9612. +A C expression whose value is RTL representing the location of the
  9613. +incoming return address at the beginning of any function, before the
  9614. +prologue. This RTL is either a REG, indicating that the return
  9615. +value is saved in 'REG', or a MEM representing a location in
  9616. +the stack.
  9617. +
  9618. +You only need to define this macro if you want to support call frame
  9619. +debugging information like that provided by DWARF 2.
  9620. +
  9621. +If this RTL is a REG, you should also define
  9622. +DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).
  9623. +*/
  9624. +#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
  9625. +
  9626. +/*
  9627. +A C expression whose value is an integer giving the offset, in bytes,
  9628. +from the value of the stack pointer register to the top of the stack
  9629. +frame at the beginning of any function, before the prologue. The top of
  9630. +the frame is defined to be the value of the stack pointer in the
  9631. +previous frame, just before the call instruction.
  9632. +
  9633. +You only need to define this macro if you want to support call frame
  9634. +debugging information like that provided by DWARF 2.
  9635. +*/
  9636. +#define INCOMING_FRAME_SP_OFFSET 0
  9637. +
  9638. +
  9639. +/** Exception Handling Support **/
  9640. +
  9641. +/* Use setjump/longjump for exception handling. */
  9642. +#define DWARF2_UNWIND_INFO 0
  9643. +#define MUST_USE_SJLJ_EXCEPTIONS 1
  9644. +
  9645. +/*
  9646. +A C expression whose value is the Nth register number used for
  9647. +data by exception handlers, or INVALID_REGNUM if fewer than
  9648. +N registers are usable.
  9649. +
  9650. +The exception handling library routines communicate with the exception
  9651. +handlers via a set of agreed upon registers. Ideally these registers
  9652. +should be call-clobbered; it is possible to use call-saved registers,
  9653. +but may negatively impact code size. The target must support at least
  9654. +2 data registers, but should define 4 if there are enough free registers.
  9655. +
  9656. +You must define this macro if you want to support call frame exception
  9657. +handling like that provided by DWARF 2.
  9658. +*/
  9659. +/*
  9660. + Use r9-r11
  9661. +*/
  9662. +#define EH_RETURN_DATA_REGNO(N) \
  9663. + ((N<3) ? INTERNAL_REGNUM(N+9) : INVALID_REGNUM)
  9664. +
  9665. +/*
  9666. +A C expression whose value is RTL representing a location in which
  9667. +to store a stack adjustment to be applied before function return.
  9668. +This is used to unwind the stack to an exception handler's call frame.
  9669. +It will be assigned zero on code paths that return normally.
  9670. +
  9671. +Typically this is a call-clobbered hard register that is otherwise
  9672. +untouched by the epilogue, but could also be a stack slot.
  9673. +
  9674. +You must define this macro if you want to support call frame exception
  9675. +handling like that provided by DWARF 2.
  9676. +*/
  9677. +/*
  9678. + Use r8
  9679. +*/
  9680. +#define EH_RETURN_STACKADJ_REGNO INTERNAL_REGNUM(8)
  9681. +#define EH_RETURN_STACKADJ_RTX gen_rtx_REG(SImode, EH_RETURN_STACKADJ_REGNO)
  9682. +
  9683. +/*
  9684. +A C expression whose value is RTL representing a location in which
  9685. +to store the address of an exception handler to which we should
  9686. +return. It will not be assigned on code paths that return normally.
  9687. +
  9688. +Typically this is the location in the call frame at which the normal
  9689. +return address is stored. For targets that return by popping an
  9690. +address off the stack, this might be a memory address just below
  9691. +the target call frame rather than inside the current call
  9692. +frame. EH_RETURN_STACKADJ_RTX will have already been assigned,
  9693. +so it may be used to calculate the location of the target call frame.
  9694. +
  9695. +Some targets have more complex requirements than storing to an
  9696. +address calculable during initial code generation. In that case
  9697. +the eh_return instruction pattern should be used instead.
  9698. +
  9699. +If you want to support call frame exception handling, you must
  9700. +define either this macro or the eh_return instruction pattern.
  9701. +*/
  9702. +/*
  9703. + We define the eh_return instruction pattern, so this isn't needed.
  9704. +*/
  9705. +/* #define EH_RETURN_HANDLER_RTX gen_rtx_REG(Pmode, RET_REGISTER) */
  9706. +
  9707. +/*
  9708. + This macro chooses the encoding of pointers embedded in the
  9709. + exception handling sections. If at all possible, this should be
  9710. + defined such that the exception handling section will not require
  9711. + dynamic relocations, and so may be read-only.
  9712. +
  9713. + code is 0 for data, 1 for code labels, 2 for function
  9714. + pointers. global is true if the symbol may be affected by dynamic
  9715. + relocations. The macro should return a combination of the DW_EH_PE_*
  9716. + defines as found in dwarf2.h.
  9717. +
  9718. + If this macro is not defined, pointers will not be encoded but
  9719. + represented directly.
  9720. +*/
  9721. +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
  9722. + ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
  9723. + | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
  9724. + | DW_EH_PE_sdata4)
  9725. +
  9726. +/* ToDo: The rest of this subsection */
  9727. +
  9728. +/** Specifying How Stack Checking is Done **/
  9729. +/* ToDo: All in this subsection */
  9730. +
  9731. +/** Registers That Address the Stack Frame **/
  9732. +
  9733. +/*
  9734. +The register number of the stack pointer register, which must also be a
  9735. +fixed register according to FIXED_REGISTERS. On most machines,
  9736. +the hardware determines which register this is.
  9737. +*/
  9738. +/* Using r13 as stack pointer. */
  9739. +#define STACK_POINTER_REGNUM INTERNAL_REGNUM(13)
  9740. +
  9741. +/*
  9742. +The register number of the frame pointer register, which is used to
  9743. +access automatic variables in the stack frame. On some machines, the
  9744. +hardware determines which register this is. On other machines, you can
  9745. +choose any register you wish for this purpose.
  9746. +*/
  9747. +/* Use r7 */
  9748. +#define FRAME_POINTER_REGNUM INTERNAL_REGNUM(7)
  9749. +
  9750. +/*
  9751. +The register number of the arg pointer register, which is used to access
  9752. +the function's argument list. On some machines, this is the same as the
  9753. +frame pointer register. On some machines, the hardware determines which
  9754. +register this is. On other machines, you can choose any register you
  9755. +wish for this purpose. If this is not the same register as the frame
  9756. +pointer register, then you must mark it as a fixed register according to
  9757. +FIXED_REGISTERS, or arrange to be able to eliminate it (see Section
  9758. +10.10.5 [Elimination], page 224).
  9759. +*/
  9760. +/* Using r5 */
  9761. +#define ARG_POINTER_REGNUM INTERNAL_REGNUM(4)
  9762. +
  9763. +
  9764. +/*
  9765. +Register numbers used for passing a function's static chain pointer. If
  9766. +register windows are used, the register number as seen by the called
  9767. +function is STATIC_CHAIN_INCOMING_REGNUM, while the register
  9768. +number as seen by the calling function is STATIC_CHAIN_REGNUM. If
  9769. +these registers are the same, STATIC_CHAIN_INCOMING_REGNUM need
  9770. +not be defined.
  9771. +
  9772. +The static chain register need not be a fixed register.
  9773. +
  9774. +If the static chain is passed in memory, these macros should not be
  9775. +defined; instead, the next two macros should be defined.
  9776. +*/
  9777. +/* Using r0 */
  9778. +#define STATIC_CHAIN_REGNUM INTERNAL_REGNUM(0)
  9779. +
  9780. +/** Eliminating Frame Pointer and Arg Pointer **/
  9781. +
  9782. +/*
  9783. +A C expression which is nonzero if a function must have and use a frame
  9784. +pointer. This expression is evaluated in the reload pass. If its value is
  9785. +nonzero the function will have a frame pointer.
  9786. +
  9787. +The expression can in principle examine the current function and decide
  9788. +according to the facts, but on most machines the constant 0 or the
  9789. +constant 1 suffices. Use 0 when the machine allows code to be generated
  9790. +with no frame pointer, and doing so saves some time or space. Use 1
  9791. +when there is no possible advantage to avoiding a frame pointer.
  9792. +
  9793. +In certain cases, the compiler does not know how to produce valid code
  9794. +without a frame pointer. The compiler recognizes those cases and
  9795. +automatically gives the function a frame pointer regardless of what
  9796. +FRAME_POINTER_REQUIRED says. You don't need to worry about
  9797. +them.
  9798. +
  9799. +In a function that does not require a frame pointer, the frame pointer
  9800. +register can be allocated for ordinary usage, unless you mark it as a
  9801. +fixed register. See FIXED_REGISTERS for more information.
  9802. +*/
  9803. +/* We need the frame pointer when compiling for profiling */
  9804. +#define FRAME_POINTER_REQUIRED (crtl->profile)
  9805. +
  9806. +/*
  9807. +A C statement to store in the variable DEPTH_VAR the difference
  9808. +between the frame pointer and the stack pointer values immediately after
  9809. +the function prologue. The value would be computed from information
  9810. +such as the result of get_frame_size () and the tables of
  9811. +registers regs_ever_live and call_used_regs.
  9812. +
  9813. +If ELIMINABLE_REGS is defined, this macro will be not be used and
  9814. +need not be defined. Otherwise, it must be defined even if
  9815. +FRAME_POINTER_REQUIRED is defined to always be true; in that
  9816. +case, you may set DEPTH_VAR to anything.
  9817. +*/
  9818. +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) ((DEPTH_VAR) = get_frame_size())
  9819. +
  9820. +/*
  9821. +If defined, this macro specifies a table of register pairs used to
  9822. +eliminate unneeded registers that point into the stack frame. If it is not
  9823. +defined, the only elimination attempted by the compiler is to replace
  9824. +references to the frame pointer with references to the stack pointer.
  9825. +
  9826. +The definition of this macro is a list of structure initializations, each
  9827. +of which specifies an original and replacement register.
  9828. +
  9829. +On some machines, the position of the argument pointer is not known until
  9830. +the compilation is completed. In such a case, a separate hard register
  9831. +must be used for the argument pointer. This register can be eliminated by
  9832. +replacing it with either the frame pointer or the argument pointer,
  9833. +depending on whether or not the frame pointer has been eliminated.
  9834. +
  9835. +In this case, you might specify:
  9836. + #define ELIMINABLE_REGS \
  9837. + {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
  9838. + {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
  9839. + {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
  9840. +
  9841. +Note that the elimination of the argument pointer with the stack pointer is
  9842. +specified first since that is the preferred elimination.
  9843. +*/
  9844. +#define ELIMINABLE_REGS \
  9845. +{ \
  9846. + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
  9847. + { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
  9848. + { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM } \
  9849. +}
  9850. +
  9851. +/*
  9852. +A C expression that returns nonzero if the compiler is allowed to try
  9853. +to replace register number FROM with register number
  9854. +TO. This macro need only be defined if ELIMINABLE_REGS
  9855. +is defined, and will usually be the constant 1, since most of the cases
  9856. +preventing register elimination are things that the compiler already
  9857. +knows about.
  9858. +*/
  9859. +#define CAN_ELIMINATE(FROM, TO) 1
  9860. +
  9861. +/*
  9862. +This macro is similar to INITIAL_FRAME_POINTER_OFFSET. It
  9863. +specifies the initial difference between the specified pair of
  9864. +registers. This macro must be defined if ELIMINABLE_REGS is
  9865. +defined.
  9866. +*/
  9867. +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
  9868. + ((OFFSET) = avr32_initial_elimination_offset(FROM, TO))
  9869. +
  9870. +/** Passing Function Arguments on the Stack **/
  9871. +
  9872. +
  9873. +/*
  9874. +A C expression. If nonzero, push insns will be used to pass
  9875. +outgoing arguments.
  9876. +If the target machine does not have a push instruction, set it to zero.
  9877. +That directs GCC to use an alternate strategy: to
  9878. +allocate the entire argument block and then store the arguments into
  9879. +it. When PUSH_ARGS is nonzero, PUSH_ROUNDING must be defined too.
  9880. +*/
  9881. +#define PUSH_ARGS 1
  9882. +
  9883. +/*
  9884. +A C expression that is the number of bytes actually pushed onto the
  9885. +stack when an instruction attempts to push NPUSHED bytes.
  9886. +
  9887. +On some machines, the definition
  9888. +
  9889. + #define PUSH_ROUNDING(BYTES) (BYTES)
  9890. +
  9891. +will suffice. But on other machines, instructions that appear
  9892. +to push one byte actually push two bytes in an attempt to maintain
  9893. +alignment. Then the definition should be
  9894. +
  9895. + #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
  9896. +*/
  9897. +/* Push 4 bytes at the time. */
  9898. +#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
  9899. +
  9900. +/*
  9901. +A C expression. If nonzero, the maximum amount of space required for
  9902. +outgoing arguments will be computed and placed into the variable
  9903. +current_function_outgoing_args_size. No space will be pushed
  9904. +onto the stack for each call; instead, the function prologue should
  9905. +increase the stack frame size by this amount.
  9906. +
  9907. +Setting both PUSH_ARGS and ACCUMULATE_OUTGOING_ARGS is not proper.
  9908. +*/
  9909. +#define ACCUMULATE_OUTGOING_ARGS 0
  9910. +
  9911. +/*
  9912. +A C expression that should indicate the number of bytes of its own
  9913. +arguments that a function pops on returning, or 0 if the
  9914. +function pops no arguments and the caller must therefore pop them all
  9915. +after the function returns.
  9916. +
  9917. +FUNDECL is a C variable whose value is a tree node that describes
  9918. +the function in question. Normally it is a node of type
  9919. +FUNCTION_DECL that describes the declaration of the function.
  9920. +From this you can obtain the DECL_ATTRIBUTES of the function.
  9921. +
  9922. +FUNTYPE is a C variable whose value is a tree node that
  9923. +describes the function in question. Normally it is a node of type
  9924. +FUNCTION_TYPE that describes the data type of the function.
  9925. +From this it is possible to obtain the data types of the value and
  9926. +arguments (if known).
  9927. +
  9928. +When a call to a library function is being considered, FUNDECL
  9929. +will contain an identifier node for the library function. Thus, if
  9930. +you need to distinguish among various library functions, you can do so
  9931. +by their names. Note that ``library function'' in this context means
  9932. +a function used to perform arithmetic, whose name is known specially
  9933. +in the compiler and was not mentioned in the C code being compiled.
  9934. +
  9935. +STACK_SIZE is the number of bytes of arguments passed on the
  9936. +stack. If a variable number of bytes is passed, it is zero, and
  9937. +argument popping will always be the responsibility of the calling function.
  9938. +
  9939. +On the VAX, all functions always pop their arguments, so the definition
  9940. +of this macro is STACK_SIZE. On the 68000, using the standard
  9941. +calling convention, no functions pop their arguments, so the value of
  9942. +the macro is always 0 in this case. But an alternative calling
  9943. +convention is available in which functions that take a fixed number of
  9944. +arguments pop them but other functions (such as printf) pop
  9945. +nothing (the caller pops all). When this convention is in use,
  9946. +FUNTYPE is examined to determine whether a function takes a fixed
  9947. +number of arguments.
  9948. +*/
  9949. +#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
  9950. +
  9951. +
  9952. +/*Return true if this function can we use a single return instruction*/
  9953. +#define USE_RETURN_INSN(ISCOND) avr32_use_return_insn(ISCOND)
  9954. +
  9955. +/*
  9956. +A C expression that should indicate the number of bytes a call sequence
  9957. +pops off the stack. It is added to the value of RETURN_POPS_ARGS
  9958. +when compiling a function call.
  9959. +
  9960. +CUM is the variable in which all arguments to the called function
  9961. +have been accumulated.
  9962. +
  9963. +On certain architectures, such as the SH5, a call trampoline is used
  9964. +that pops certain registers off the stack, depending on the arguments
  9965. +that have been passed to the function. Since this is a property of the
  9966. +call site, not of the called function, RETURN_POPS_ARGS is not
  9967. +appropriate.
  9968. +*/
  9969. +#define CALL_POPS_ARGS(CUM) 0
  9970. +
  9971. +/* Passing Arguments in Registers */
  9972. +
  9973. +/*
  9974. +A C expression that controls whether a function argument is passed
  9975. +in a register, and which register.
  9976. +
  9977. +The arguments are CUM, which summarizes all the previous
  9978. +arguments; MODE, the machine mode of the argument; TYPE,
  9979. +the data type of the argument as a tree node or 0 if that is not known
  9980. +(which happens for C support library functions); and NAMED,
  9981. +which is 1 for an ordinary argument and 0 for nameless arguments that
  9982. +correspond to '...' in the called function's prototype.
  9983. +TYPE can be an incomplete type if a syntax error has previously
  9984. +occurred.
  9985. +
  9986. +The value of the expression is usually either a reg RTX for the
  9987. +hard register in which to pass the argument, or zero to pass the
  9988. +argument on the stack.
  9989. +
  9990. +For machines like the VAX and 68000, where normally all arguments are
  9991. +pushed, zero suffices as a definition.
  9992. +
  9993. +The value of the expression can also be a parallel RTX. This is
  9994. +used when an argument is passed in multiple locations. The mode of the
  9995. +of the parallel should be the mode of the entire argument. The
  9996. +parallel holds any number of expr_list pairs; each one
  9997. +describes where part of the argument is passed. In each
  9998. +expr_list the first operand must be a reg RTX for the hard
  9999. +register in which to pass this part of the argument, and the mode of the
  10000. +register RTX indicates how large this part of the argument is. The
  10001. +second operand of the expr_list is a const_int which gives
  10002. +the offset in bytes into the entire argument of where this part starts.
  10003. +As a special exception the first expr_list in the parallel
  10004. +RTX may have a first operand of zero. This indicates that the entire
  10005. +argument is also stored on the stack.
  10006. +
  10007. +The last time this macro is called, it is called with MODE == VOIDmode,
  10008. +and its result is passed to the call or call_value
  10009. +pattern as operands 2 and 3 respectively.
  10010. +
  10011. +The usual way to make the ISO library 'stdarg.h' work on a machine
  10012. +where some arguments are usually passed in registers, is to cause
  10013. +nameless arguments to be passed on the stack instead. This is done
  10014. +by making FUNCTION_ARG return 0 whenever NAMED is 0.
  10015. +
  10016. +You may use the macro MUST_PASS_IN_STACK (MODE, TYPE)
  10017. +in the definition of this macro to determine if this argument is of a
  10018. +type that must be passed in the stack. If REG_PARM_STACK_SPACE
  10019. +is not defined and FUNCTION_ARG returns nonzero for such an
  10020. +argument, the compiler will abort. If REG_PARM_STACK_SPACE is
  10021. +defined, the argument will be computed in the stack and then loaded into
  10022. +a register. */
  10023. +
  10024. +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
  10025. + avr32_function_arg(&(CUM), MODE, TYPE, NAMED)
  10026. +
  10027. +/*
  10028. +A C type for declaring a variable that is used as the first argument of
  10029. +FUNCTION_ARG and other related values. For some target machines,
  10030. +the type int suffices and can hold the number of bytes of
  10031. +argument so far.
  10032. +
  10033. +There is no need to record in CUMULATIVE_ARGS anything about the
  10034. +arguments that have been passed on the stack. The compiler has other
  10035. +variables to keep track of that. For target machines on which all
  10036. +arguments are passed on the stack, there is no need to store anything in
  10037. +CUMULATIVE_ARGS; however, the data structure must exist and
  10038. +should not be empty, so use int.
  10039. +*/
  10040. +typedef struct avr32_args
  10041. +{
  10042. + /* Index representing the argument register the current function argument
  10043. + will occupy */
  10044. + int index;
  10045. + /* A mask with bits representing the argument registers: if a bit is set
  10046. + then this register is used for an argument */
  10047. + int used_index;
  10048. + /* TRUE if this function has anonymous arguments */
  10049. + int uses_anonymous_args;
  10050. + /* The size in bytes of the named arguments pushed on the stack */
  10051. + int stack_pushed_args_size;
  10052. + /* Set to true if this function needs a Return Value Pointer */
  10053. + int use_rvp;
  10054. + /* Set to true if function is a flashvault function. */
  10055. + int flashvault_func;
  10056. +
  10057. +} CUMULATIVE_ARGS;
  10058. +
  10059. +
  10060. +#define FIRST_CUM_REG_INDEX 0
  10061. +#define LAST_CUM_REG_INDEX 4
  10062. +#define GET_REG_INDEX(CUM) ((CUM)->index)
  10063. +#define SET_REG_INDEX(CUM, INDEX) ((CUM)->index = (INDEX));
  10064. +#define GET_USED_INDEX(CUM, INDEX) ((CUM)->used_index & (1 << (INDEX)))
  10065. +#define SET_USED_INDEX(CUM, INDEX) \
  10066. + do \
  10067. + { \
  10068. + if (INDEX >= 0) \
  10069. + (CUM)->used_index |= (1 << (INDEX)); \
  10070. + } \
  10071. + while (0)
  10072. +#define SET_INDEXES_UNUSED(CUM) ((CUM)->used_index = 0)
  10073. +
  10074. +/*
  10075. + A C statement (sans semicolon) for initializing the variable cum for the
  10076. + state at the beginning of the argument list. The variable has type
  10077. + CUMULATIVE_ARGS. The value of FNTYPE is the tree node for the data type of
  10078. + the function which will receive the args, or 0 if the args are to a compiler
  10079. + support library function. For direct calls that are not libcalls, FNDECL
  10080. + contain the declaration node of the function. FNDECL is also set when
  10081. + INIT_CUMULATIVE_ARGS is used to find arguments for the function being
  10082. + compiled. N_NAMED_ARGS is set to the number of named arguments, including a
  10083. + structure return address if it is passed as a parameter, when making a call.
  10084. + When processing incoming arguments, N_NAMED_ARGS is set to -1.
  10085. +
  10086. + When processing a call to a compiler support library function, LIBNAME
  10087. + identifies which one. It is a symbol_ref rtx which contains the name of the
  10088. + function, as a string. LIBNAME is 0 when an ordinary C function call is
  10089. + being processed. Thus, each time this macro is called, either LIBNAME or
  10090. + FNTYPE is nonzero, but never both of them at once.
  10091. +*/
  10092. +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
  10093. + avr32_init_cumulative_args(&(CUM), FNTYPE, LIBNAME, FNDECL)
  10094. +
  10095. +/*
  10096. +A C statement (sans semicolon) to update the summarizer variable
  10097. +CUM to advance past an argument in the argument list. The
  10098. +values MODE, TYPE and NAMED describe that argument.
  10099. +Once this is done, the variable CUM is suitable for analyzing
  10100. +the following argument with FUNCTION_ARG, etc.
  10101. +
  10102. +This macro need not do anything if the argument in question was passed
  10103. +on the stack. The compiler knows how to track the amount of stack space
  10104. +used for arguments without any special help.
  10105. +*/
  10106. +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
  10107. + avr32_function_arg_advance(&(CUM), MODE, TYPE, NAMED)
  10108. +
  10109. +/*
  10110. +If defined, a C expression which determines whether, and in which direction,
  10111. +to pad out an argument with extra space. The value should be of type
  10112. +enum direction: either 'upward' to pad above the argument,
  10113. +'downward' to pad below, or 'none' to inhibit padding.
  10114. +
  10115. +The amount of padding is always just enough to reach the next
  10116. +multiple of FUNCTION_ARG_BOUNDARY; this macro does not control
  10117. +it.
  10118. +
  10119. +This macro has a default definition which is right for most systems.
  10120. +For little-endian machines, the default is to pad upward. For
  10121. +big-endian machines, the default is to pad downward for an argument of
  10122. +constant size shorter than an int, and upward otherwise.
  10123. +*/
  10124. +#define FUNCTION_ARG_PADDING(MODE, TYPE) \
  10125. + avr32_function_arg_padding(MODE, TYPE)
  10126. +
  10127. +/*
  10128. + Specify padding for the last element of a block move between registers
  10129. + and memory. First is nonzero if this is the only element. Defining
  10130. + this macro allows better control of register function parameters on
  10131. + big-endian machines, without using PARALLEL rtl. In particular,
  10132. + MUST_PASS_IN_STACK need not test padding and mode of types in registers,
  10133. + as there is no longer a "wrong" part of a register; For example, a three
  10134. + byte aggregate may be passed in the high part of a register if so required.
  10135. +*/
  10136. +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
  10137. + avr32_function_arg_padding(MODE, TYPE)
  10138. +
  10139. +/*
  10140. +If defined, a C expression which determines whether the default
  10141. +implementation of va_arg will attempt to pad down before reading the
  10142. +next argument, if that argument is smaller than its aligned space as
  10143. +controlled by PARM_BOUNDARY. If this macro is not defined, all such
  10144. +arguments are padded down if BYTES_BIG_ENDIAN is true.
  10145. +*/
  10146. +#define PAD_VARARGS_DOWN \
  10147. + (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
  10148. +
  10149. +/*
  10150. +A C expression that is nonzero if REGNO is the number of a hard
  10151. +register in which function arguments are sometimes passed. This does
  10152. +not include implicit arguments such as the static chain and
  10153. +the structure-value address. On many machines, no registers can be
  10154. +used for this purpose since all function arguments are pushed on the
  10155. +stack.
  10156. +*/
  10157. +/*
  10158. + Use r8 - r12 for function arguments.
  10159. +*/
  10160. +#define FUNCTION_ARG_REGNO_P(REGNO) \
  10161. + (REGNO >= 3 && REGNO <= 7)
  10162. +
  10163. +/* Number of registers used for passing function arguments */
  10164. +#define NUM_ARG_REGS 5
  10165. +
  10166. +/*
  10167. +If defined, the order in which arguments are loaded into their
  10168. +respective argument registers is reversed so that the last
  10169. +argument is loaded first. This macro only affects arguments
  10170. +passed in registers.
  10171. +*/
  10172. +/* #define LOAD_ARGS_REVERSED */
  10173. +
  10174. +/** How Scalar Function Values Are Returned **/
  10175. +
  10176. +/* AVR32 is using r12 as return register. */
  10177. +#define RET_REGISTER (15 - 12)
  10178. +
  10179. +/*
  10180. +A C expression to create an RTX representing the place where a library
  10181. +function returns a value of mode MODE. If the precise function
  10182. +being called is known, FUNC is a tree node
  10183. +(FUNCTION_DECL) for it; otherwise, func is a null
  10184. +pointer. This makes it possible to use a different value-returning
  10185. +convention for specific functions when all their calls are
  10186. +known.
  10187. +
  10188. +Note that "library function" in this context means a compiler
  10189. +support routine, used to perform arithmetic, whose name is known
  10190. +specially by the compiler and was not mentioned in the C code being
  10191. +compiled.
  10192. +
  10193. +The definition of LIBRARY_VALUE need not be concerned aggregate
  10194. +data types, because none of the library functions returns such types.
  10195. +*/
  10196. +#define LIBCALL_VALUE(MODE) avr32_libcall_value(MODE)
  10197. +
  10198. +/*
  10199. +A C expression that is nonzero if REGNO is the number of a hard
  10200. +register in which the values of called function may come back.
  10201. +
  10202. +A register whose use for returning values is limited to serving as the
  10203. +second of a pair (for a value of type double, say) need not be
  10204. +recognized by this macro. So for most machines, this definition
  10205. +suffices:
  10206. + #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
  10207. +
  10208. +If the machine has register windows, so that the caller and the called
  10209. +function use different registers for the return value, this macro
  10210. +should recognize only the caller's register numbers.
  10211. +*/
  10212. +/*
  10213. + When returning a value of mode DImode, r11:r10 is used, else r12 is used.
  10214. +*/
  10215. +#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RET_REGISTER \
  10216. + || (REGNO) == INTERNAL_REGNUM(11))
  10217. +
  10218. +
  10219. +/** How Large Values Are Returned **/
  10220. +
  10221. +
  10222. +/*
  10223. +Define this macro to be 1 if all structure and union return values must be
  10224. +in memory. Since this results in slower code, this should be defined
  10225. +only if needed for compatibility with other compilers or with an ABI.
  10226. +If you define this macro to be 0, then the conventions used for structure
  10227. +and union return values are decided by the RETURN_IN_MEMORY macro.
  10228. +
  10229. +If not defined, this defaults to the value 1.
  10230. +*/
  10231. +#define DEFAULT_PCC_STRUCT_RETURN 0
  10232. +
  10233. +
  10234. +
  10235. +
  10236. +/** Generating Code for Profiling **/
  10237. +
  10238. +/*
  10239. +A C statement or compound statement to output to FILE some
  10240. +assembler code to call the profiling subroutine mcount.
  10241. +
  10242. +The details of how mcount expects to be called are determined by
  10243. +your operating system environment, not by GCC. To figure them out,
  10244. +compile a small program for profiling using the system's installed C
  10245. +compiler and look at the assembler code that results.
  10246. +
  10247. +Older implementations of mcount expect the address of a counter
  10248. +variable to be loaded into some register. The name of this variable is
  10249. +'LP' followed by the number LABELNO, so you would generate
  10250. +the name using 'LP%d' in a fprintf.
  10251. +*/
  10252. +/* ToDo: fixme */
  10253. +#ifndef FUNCTION_PROFILER
  10254. +#define FUNCTION_PROFILER(FILE, LABELNO) \
  10255. + fprintf((FILE), "/* profiler %d */", (LABELNO))
  10256. +#endif
  10257. +
  10258. +
  10259. +/*****************************************************************************
  10260. + * Trampolines for Nested Functions *
  10261. + *****************************************************************************/
  10262. +
  10263. +/*
  10264. +A C statement to output, on the stream FILE, assembler code for a
  10265. +block of data that contains the constant parts of a trampoline. This
  10266. +code should not include a label - the label is taken care of
  10267. +automatically.
  10268. +
  10269. +If you do not define this macro, it means no template is needed
  10270. +for the target. Do not define this macro on systems where the block move
  10271. +code to copy the trampoline into place would be larger than the code
  10272. +to generate it on the spot.
  10273. +*/
  10274. +/* ToDo: correct? */
  10275. +#define TRAMPOLINE_TEMPLATE(FILE) avr32_trampoline_template(FILE);
  10276. +
  10277. +
  10278. +/*
  10279. +A C expression for the size in bytes of the trampoline, as an integer.
  10280. +*/
  10281. +/* ToDo: fixme */
  10282. +#define TRAMPOLINE_SIZE 0x0C
  10283. +
  10284. +/*
  10285. +Alignment required for trampolines, in bits.
  10286. +
  10287. +If you don't define this macro, the value of BIGGEST_ALIGNMENT
  10288. +is used for aligning trampolines.
  10289. +*/
  10290. +#define TRAMPOLINE_ALIGNMENT 16
  10291. +
  10292. +/*
  10293. +A C statement to initialize the variable parts of a trampoline.
  10294. +ADDR is an RTX for the address of the trampoline; FNADDR is
  10295. +an RTX for the address of the nested function; STATIC_CHAIN is an
  10296. +RTX for the static chain value that should be passed to the function
  10297. +when it is called.
  10298. +*/
  10299. +#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
  10300. + avr32_initialize_trampoline(ADDR, FNADDR, STATIC_CHAIN)
  10301. +
  10302. +
  10303. +/******************************************************************************
  10304. + * Implicit Calls to Library Routines
  10305. + *****************************************************************************/
  10306. +
  10307. +/* Tail calling. */
  10308. +
  10309. +/* A C expression that evaluates to true if it is ok to perform a sibling
  10310. + call to DECL. */
  10311. +#define FUNCTION_OK_FOR_SIBCALL(DECL) 0
  10312. +
  10313. +#define OVERRIDE_OPTIONS avr32_override_options ()
  10314. +
  10315. +#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) avr32_optimization_options (LEVEL, SIZE)
  10316. +
  10317. +/******************************************************************************
  10318. + * Addressing Modes
  10319. + *****************************************************************************/
  10320. +
  10321. +/*
  10322. +A C expression that is nonzero if the machine supports pre-increment,
  10323. +pre-decrement, post-increment, or post-decrement addressing respectively.
  10324. +*/
  10325. +/*
  10326. + AVR32 supports Rp++ and --Rp
  10327. +*/
  10328. +#define HAVE_PRE_INCREMENT 0
  10329. +#define HAVE_PRE_DECREMENT 1
  10330. +#define HAVE_POST_INCREMENT 1
  10331. +#define HAVE_POST_DECREMENT 0
  10332. +
  10333. +/*
  10334. +A C expression that is nonzero if the machine supports pre- or
  10335. +post-address side-effect generation involving constants other than
  10336. +the size of the memory operand.
  10337. +*/
  10338. +#define HAVE_PRE_MODIFY_DISP 0
  10339. +#define HAVE_POST_MODIFY_DISP 0
  10340. +
  10341. +/*
  10342. +A C expression that is nonzero if the machine supports pre- or
  10343. +post-address side-effect generation involving a register displacement.
  10344. +*/
  10345. +#define HAVE_PRE_MODIFY_REG 0
  10346. +#define HAVE_POST_MODIFY_REG 0
  10347. +
  10348. +/*
  10349. +A C expression that is 1 if the RTX X is a constant which
  10350. +is a valid address. On most machines, this can be defined as
  10351. +CONSTANT_P (X), but a few machines are more restrictive
  10352. +in which constant addresses are supported.
  10353. +
  10354. +CONSTANT_P accepts integer-values expressions whose values are
  10355. +not explicitly known, such as symbol_ref, label_ref, and
  10356. +high expressions and const arithmetic expressions, in
  10357. +addition to const_int and const_double expressions.
  10358. +*/
  10359. +#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
  10360. +
  10361. +/*
  10362. +A number, the maximum number of registers that can appear in a valid
  10363. +memory address. Note that it is up to you to specify a value equal to
  10364. +the maximum number that GO_IF_LEGITIMATE_ADDRESS would ever
  10365. +accept.
  10366. +*/
  10367. +#define MAX_REGS_PER_ADDRESS 2
  10368. +
  10369. +/*
  10370. +A C compound statement with a conditional goto LABEL;
  10371. +executed if X (an RTX) is a legitimate memory address on the
  10372. +target machine for a memory operand of mode MODE.
  10373. +
  10374. +It usually pays to define several simpler macros to serve as
  10375. +subroutines for this one. Otherwise it may be too complicated to
  10376. +understand.
  10377. +
  10378. +This macro must exist in two variants: a strict variant and a
  10379. +non-strict one. The strict variant is used in the reload pass. It
  10380. +must be defined so that any pseudo-register that has not been
  10381. +allocated a hard register is considered a memory reference. In
  10382. +contexts where some kind of register is required, a pseudo-register
  10383. +with no hard register must be rejected.
  10384. +
  10385. +The non-strict variant is used in other passes. It must be defined to
  10386. +accept all pseudo-registers in every context where some kind of
  10387. +register is required.
  10388. +
  10389. +Compiler source files that want to use the strict variant of this
  10390. +macro define the macro REG_OK_STRICT. You should use an
  10391. +#ifdef REG_OK_STRICT conditional to define the strict variant
  10392. +in that case and the non-strict variant otherwise.
  10393. +
  10394. +Subroutines to check for acceptable registers for various purposes (one
  10395. +for base registers, one for index registers, and so on) are typically
  10396. +among the subroutines used to define GO_IF_LEGITIMATE_ADDRESS.
  10397. +Then only these subroutine macros need have two variants; the higher
  10398. +levels of macros may be the same whether strict or not.
  10399. +
  10400. +Normally, constant addresses which are the sum of a symbol_ref
  10401. +and an integer are stored inside a const RTX to mark them as
  10402. +constant. Therefore, there is no need to recognize such sums
  10403. +specifically as legitimate addresses. Normally you would simply
  10404. +recognize any const as legitimate.
  10405. +
  10406. +Usually PRINT_OPERAND_ADDRESS is not prepared to handle constant
  10407. +sums that are not marked with const. It assumes that a naked
  10408. +plus indicates indexing. If so, then you must reject such
  10409. +naked constant sums as illegitimate addresses, so that none of them will
  10410. +be given to PRINT_OPERAND_ADDRESS.
  10411. +
  10412. +On some machines, whether a symbolic address is legitimate depends on
  10413. +the section that the address refers to. On these machines, define the
  10414. +macro ENCODE_SECTION_INFO to store the information into the
  10415. +symbol_ref, and then check for it here. When you see a
  10416. +const, you will have to look inside it to find the
  10417. +symbol_ref in order to determine the section.
  10418. +
  10419. +The best way to modify the name string is by adding text to the
  10420. +beginning, with suitable punctuation to prevent any ambiguity. Allocate
  10421. +the new name in saveable_obstack. You will have to modify
  10422. +ASM_OUTPUT_LABELREF to remove and decode the added text and
  10423. +output the name accordingly, and define STRIP_NAME_ENCODING to
  10424. +access the original name string.
  10425. +
  10426. +You can check the information stored here into the symbol_ref in
  10427. +the definitions of the macros GO_IF_LEGITIMATE_ADDRESS and
  10428. +PRINT_OPERAND_ADDRESS.
  10429. +*/
  10430. +#ifdef REG_OK_STRICT
  10431. +# define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
  10432. + do \
  10433. + { \
  10434. + if (avr32_legitimate_address(MODE, X, 1)) \
  10435. + goto LABEL; \
  10436. + } \
  10437. + while (0)
  10438. +#else
  10439. +# define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
  10440. + do \
  10441. + { \
  10442. + if (avr32_legitimate_address(MODE, X, 0)) \
  10443. + goto LABEL; \
  10444. + } \
  10445. + while (0)
  10446. +#endif
  10447. +
  10448. +
  10449. +
  10450. +/*
  10451. +A C compound statement that attempts to replace X with a valid
  10452. +memory address for an operand of mode MODE. win will be a
  10453. +C statement label elsewhere in the code; the macro definition may use
  10454. +
  10455. + GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
  10456. +
  10457. +to avoid further processing if the address has become legitimate.
  10458. +
  10459. +X will always be the result of a call to break_out_memory_refs,
  10460. +and OLDX will be the operand that was given to that function to produce
  10461. +X.
  10462. +
  10463. +The code generated by this macro should not alter the substructure of
  10464. +X. If it transforms X into a more legitimate form, it
  10465. +should assign X (which will always be a C variable) a new value.
  10466. +
  10467. +It is not necessary for this macro to come up with a legitimate
  10468. +address. The compiler has standard ways of doing so in all cases. In
  10469. +fact, it is safe for this macro to do nothing. But often a
  10470. +machine-dependent strategy can generate better code.
  10471. +*/
  10472. +#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
  10473. + do \
  10474. + { \
  10475. + if (GET_CODE(X) == PLUS \
  10476. + && GET_CODE(XEXP(X, 0)) == REG \
  10477. + && GET_CODE(XEXP(X, 1)) == CONST_INT \
  10478. + && !CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(X, 1)), \
  10479. + 'K', "Ks16")) \
  10480. + { \
  10481. + rtx index = force_reg(SImode, XEXP(X, 1)); \
  10482. + X = gen_rtx_PLUS( SImode, XEXP(X, 0), index); \
  10483. + } \
  10484. + GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN); \
  10485. + } \
  10486. + while(0)
  10487. +
  10488. +
  10489. +/*
  10490. +A C statement or compound statement with a conditional
  10491. +goto LABEL; executed if memory address X (an RTX) can have
  10492. +different meanings depending on the machine mode of the memory
  10493. +reference it is used for or if the address is valid for some modes
  10494. +but not others.
  10495. +
  10496. +Autoincrement and autodecrement addresses typically have mode-dependent
  10497. +effects because the amount of the increment or decrement is the size
  10498. +of the operand being addressed. Some machines have other mode-dependent
  10499. +addresses. Many RISC machines have no mode-dependent addresses.
  10500. +
  10501. +You may assume that ADDR is a valid address for the machine.
  10502. +*/
  10503. +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
  10504. + do \
  10505. + { \
  10506. + if (GET_CODE (ADDR) == POST_INC \
  10507. + || GET_CODE (ADDR) == PRE_DEC) \
  10508. + goto LABEL; \
  10509. + } \
  10510. + while (0)
  10511. +
  10512. +/*
  10513. +A C expression that is nonzero if X is a legitimate constant for
  10514. +an immediate operand on the target machine. You can assume that
  10515. +X satisfies CONSTANT_P, so you need not check this. In fact,
  10516. +'1' is a suitable definition for this macro on machines where
  10517. +anything CONSTANT_P is valid.
  10518. +*/
  10519. +#define LEGITIMATE_CONSTANT_P(X) avr32_legitimate_constant_p(X)
  10520. +
  10521. +
  10522. +/******************************************************************************
  10523. + * Condition Code Status
  10524. + *****************************************************************************/
  10525. +
  10526. +/*
  10527. +C code for a data type which is used for declaring the mdep
  10528. +component of cc_status. It defaults to int.
  10529. +
  10530. +This macro is not used on machines that do not use cc0.
  10531. +*/
  10532. +
  10533. +typedef struct
  10534. +{
  10535. + int flags;
  10536. + rtx value;
  10537. + int cond_exec_cmp_clobbered;
  10538. +} avr32_status_reg;
  10539. +
  10540. +
  10541. +#define CC_STATUS_MDEP avr32_status_reg
  10542. +
  10543. +/*
  10544. +A C expression to initialize the mdep field to "empty".
  10545. +The default definition does nothing, since most machines don't use
  10546. +the field anyway. If you want to use the field, you should probably
  10547. +define this macro to initialize it.
  10548. +
  10549. +This macro is not used on machines that do not use cc0.
  10550. +*/
  10551. +
  10552. +#define CC_STATUS_MDEP_INIT \
  10553. + (cc_status.mdep.flags = CC_NONE , cc_status.mdep.cond_exec_cmp_clobbered = 0, cc_status.mdep.value = 0)
  10554. +
  10555. +/*
  10556. +A C compound statement to set the components of cc_status
  10557. +appropriately for an insn INSN whose body is EXP. It is
  10558. +this macro's responsibility to recognize insns that set the condition
  10559. +code as a byproduct of other activity as well as those that explicitly
  10560. +set (cc0).
  10561. +
  10562. +This macro is not used on machines that do not use cc0.
  10563. +
  10564. +If there are insns that do not set the condition code but do alter
  10565. +other machine registers, this macro must check to see whether they
  10566. +invalidate the expressions that the condition code is recorded as
  10567. +reflecting. For example, on the 68000, insns that store in address
  10568. +registers do not set the condition code, which means that usually
  10569. +NOTICE_UPDATE_CC can leave cc_status unaltered for such
  10570. +insns. But suppose that the previous insn set the condition code
  10571. +based on location 'a4@@(102)' and the current insn stores a new
  10572. +value in 'a4'. Although the condition code is not changed by
  10573. +this, it will no longer be true that it reflects the contents of
  10574. +'a4@@(102)'. Therefore, NOTICE_UPDATE_CC must alter
  10575. +cc_status in this case to say that nothing is known about the
  10576. +condition code value.
  10577. +
  10578. +The definition of NOTICE_UPDATE_CC must be prepared to deal
  10579. +with the results of peephole optimization: insns whose patterns are
  10580. +parallel RTXs containing various reg, mem or
  10581. +constants which are just the operands. The RTL structure of these
  10582. +insns is not sufficient to indicate what the insns actually do. What
  10583. +NOTICE_UPDATE_CC should do when it sees one is just to run
  10584. +CC_STATUS_INIT.
  10585. +
  10586. +A possible definition of NOTICE_UPDATE_CC is to call a function
  10587. +that looks at an attribute (see Insn Attributes) named, for example,
  10588. +'cc'. This avoids having detailed information about patterns in
  10589. +two places, the 'md' file and in NOTICE_UPDATE_CC.
  10590. +*/
  10591. +
  10592. +#define NOTICE_UPDATE_CC(EXP, INSN) avr32_notice_update_cc(EXP, INSN)
  10593. +
  10594. +
  10595. +
  10596. +
  10597. +/******************************************************************************
  10598. + * Describing Relative Costs of Operations
  10599. + *****************************************************************************/
  10600. +
  10601. +
  10602. +
  10603. +/*
  10604. +A C expression for the cost of moving data of mode MODE from a
  10605. +register in class FROM to one in class TO. The classes are
  10606. +expressed using the enumeration values such as GENERAL_REGS. A
  10607. +value of 2 is the default; other values are interpreted relative to
  10608. +that.
  10609. +
  10610. +It is not required that the cost always equal 2 when FROM is the
  10611. +same as TO; on some machines it is expensive to move between
  10612. +registers if they are not general registers.
  10613. +
  10614. +If reload sees an insn consisting of a single set between two
  10615. +hard registers, and if REGISTER_MOVE_COST applied to their
  10616. +classes returns a value of 2, reload does not check to ensure that the
  10617. +constraints of the insn are met. Setting a cost of other than 2 will
  10618. +allow reload to verify that the constraints are met. You should do this
  10619. +if the movm pattern's constraints do not allow such copying.
  10620. +*/
  10621. +#define REGISTER_MOVE_COST(MODE, FROM, TO) \
  10622. + ((GET_MODE_SIZE(MODE) <= 4) ? 2: \
  10623. + (GET_MODE_SIZE(MODE) <= 8) ? 3: \
  10624. + 4)
  10625. +
  10626. +/*
  10627. +A C expression for the cost of moving data of mode MODE between a
  10628. +register of class CLASS and memory; IN is zero if the value
  10629. +is to be written to memory, nonzero if it is to be read in. This cost
  10630. +is relative to those in REGISTER_MOVE_COST. If moving between
  10631. +registers and memory is more expensive than between two registers, you
  10632. +should define this macro to express the relative cost.
  10633. +
  10634. +If you do not define this macro, GCC uses a default cost of 4 plus
  10635. +the cost of copying via a secondary reload register, if one is
  10636. +needed. If your machine requires a secondary reload register to copy
  10637. +between memory and a register of CLASS but the reload mechanism is
  10638. +more complex than copying via an intermediate, define this macro to
  10639. +reflect the actual cost of the move.
  10640. +
  10641. +GCC defines the function memory_move_secondary_cost if
  10642. +secondary reloads are needed. It computes the costs due to copying via
  10643. +a secondary register. If your machine copies from memory using a
  10644. +secondary register in the conventional way but the default base value of
  10645. +4 is not correct for your machine, define this macro to add some other
  10646. +value to the result of that function. The arguments to that function
  10647. +are the same as to this macro.
  10648. +*/
  10649. +/*
  10650. + Memory moves are costly
  10651. +*/
  10652. +#define MEMORY_MOVE_COST(MODE, CLASS, IN) \
  10653. + (((IN) ? ((GET_MODE_SIZE(MODE) < 4) ? 4 : \
  10654. + (GET_MODE_SIZE(MODE) > 8) ? 6 : \
  10655. + 3) \
  10656. + : ((GET_MODE_SIZE(MODE) > 8) ? 6 : 3)))
  10657. +
  10658. +/*
  10659. +A C expression for the cost of a branch instruction. A value of 1 is
  10660. +the default; other values are interpreted relative to that.
  10661. +*/
  10662. + /* Try to use conditionals as much as possible */
  10663. +#define BRANCH_COST(speed_p, predictable_p) (TARGET_BRANCH_PRED ? 3 : 4)
  10664. +
  10665. +/*A C expression for the maximum number of instructions to execute via conditional
  10666. + execution instructions instead of a branch. A value of BRANCH_COST+1 is the default
  10667. + if the machine does not use cc0, and 1 if it does use cc0.*/
  10668. +#define MAX_CONDITIONAL_EXECUTE 4
  10669. +
  10670. +/*
  10671. +Define this macro as a C expression which is nonzero if accessing less
  10672. +than a word of memory (i.e.: a char or a short) is no
  10673. +faster than accessing a word of memory, i.e., if such access
  10674. +require more than one instruction or if there is no difference in cost
  10675. +between byte and (aligned) word loads.
  10676. +
  10677. +When this macro is not defined, the compiler will access a field by
  10678. +finding the smallest containing object; when it is defined, a fullword
  10679. +load will be used if alignment permits. Unless bytes accesses are
  10680. +faster than word accesses, using word accesses is preferable since it
  10681. +may eliminate subsequent memory access if subsequent accesses occur to
  10682. +other fields in the same word of the structure, but to different bytes.
  10683. +*/
  10684. +#define SLOW_BYTE_ACCESS 1
  10685. +
  10686. +
  10687. +/*
  10688. +Define this macro if it is as good or better to call a constant
  10689. +function address than to call an address kept in a register.
  10690. +*/
  10691. +#define NO_FUNCTION_CSE
  10692. +
  10693. +
  10694. +/******************************************************************************
  10695. + * Adjusting the Instruction Scheduler
  10696. + *****************************************************************************/
  10697. +
  10698. +/*****************************************************************************
  10699. + * Dividing the Output into Sections (Texts, Data, ...) *
  10700. + *****************************************************************************/
  10701. +
  10702. +/*
  10703. +A C expression whose value is a string, including spacing, containing the
  10704. +assembler operation that should precede instructions and read-only data.
  10705. +Normally "\t.text" is right.
  10706. +*/
  10707. +#define TEXT_SECTION_ASM_OP "\t.text"
  10708. +/*
  10709. +A C statement that switches to the default section containing instructions.
  10710. +Normally this is not needed, as simply defining TEXT_SECTION_ASM_OP
  10711. +is enough. The MIPS port uses this to sort all functions after all data
  10712. +declarations.
  10713. +*/
  10714. +/* #define TEXT_SECTION */
  10715. +
  10716. +/*
  10717. +A C expression whose value is a string, including spacing, containing the
  10718. +assembler operation to identify the following data as writable initialized
  10719. +data. Normally "\t.data" is right.
  10720. +*/
  10721. +#define DATA_SECTION_ASM_OP "\t.data"
  10722. +
  10723. +/*
  10724. +If defined, a C expression whose value is a string, including spacing,
  10725. +containing the assembler operation to identify the following data as
  10726. +shared data. If not defined, DATA_SECTION_ASM_OP will be used.
  10727. +*/
  10728. +
  10729. +/*
  10730. +A C expression whose value is a string, including spacing, containing
  10731. +the assembler operation to identify the following data as read-only
  10732. +initialized data.
  10733. +*/
  10734. +#undef READONLY_DATA_SECTION_ASM_OP
  10735. +#define READONLY_DATA_SECTION_ASM_OP \
  10736. + ((TARGET_USE_RODATA_SECTION) ? \
  10737. + "\t.section\t.rodata" : \
  10738. + TEXT_SECTION_ASM_OP )
  10739. +
  10740. +
  10741. +/*
  10742. +If defined, a C expression whose value is a string, including spacing,
  10743. +containing the assembler operation to identify the following data as
  10744. +uninitialized global data. If not defined, and neither
  10745. +ASM_OUTPUT_BSS nor ASM_OUTPUT_ALIGNED_BSS are defined,
  10746. +uninitialized global data will be output in the data section if
  10747. +-fno-common is passed, otherwise ASM_OUTPUT_COMMON will be
  10748. +used.
  10749. +*/
  10750. +#define BSS_SECTION_ASM_OP "\t.section\t.bss"
  10751. +
  10752. +/*
  10753. +If defined, a C expression whose value is a string, including spacing,
  10754. +containing the assembler operation to identify the following data as
  10755. +uninitialized global shared data. If not defined, and
  10756. +BSS_SECTION_ASM_OP is, the latter will be used.
  10757. +*/
  10758. +/*#define SHARED_BSS_SECTION_ASM_OP "\trseg\tshared_bbs_section:data:noroot(0)\n"*/
  10759. +/*
  10760. +If defined, a C expression whose value is a string, including spacing,
  10761. +containing the assembler operation to identify the following data as
  10762. +initialization code. If not defined, GCC will assume such a section does
  10763. +not exist.
  10764. +*/
  10765. +#undef INIT_SECTION_ASM_OP
  10766. +#define INIT_SECTION_ASM_OP "\t.section\t.init"
  10767. +
  10768. +/*
  10769. +If defined, a C expression whose value is a string, including spacing,
  10770. +containing the assembler operation to identify the following data as
  10771. +finalization code. If not defined, GCC will assume such a section does
  10772. +not exist.
  10773. +*/
  10774. +#undef FINI_SECTION_ASM_OP
  10775. +#define FINI_SECTION_ASM_OP "\t.section\t.fini"
  10776. +
  10777. +/*
  10778. +If defined, an ASM statement that switches to a different section
  10779. +via SECTION_OP, calls FUNCTION, and switches back to
  10780. +the text section. This is used in crtstuff.c if
  10781. +INIT_SECTION_ASM_OP or FINI_SECTION_ASM_OP to calls
  10782. +to initialization and finalization functions from the init and fini
  10783. +sections. By default, this macro uses a simple function call. Some
  10784. +ports need hand-crafted assembly code to avoid dependencies on
  10785. +registers initialized in the function prologue or to ensure that
  10786. +constant pools don't end up too far way in the text section.
  10787. +*/
  10788. +#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
  10789. + asm ( SECTION_OP "\n" \
  10790. + "mcall r6[" USER_LABEL_PREFIX #FUNC "@got]\n" \
  10791. + TEXT_SECTION_ASM_OP);
  10792. +
  10793. +
  10794. +/*
  10795. +Define this macro to be an expression with a nonzero value if jump
  10796. +tables (for tablejump insns) should be output in the text
  10797. +section, along with the assembler instructions. Otherwise, the
  10798. +readonly data section is used.
  10799. +
  10800. +This macro is irrelevant if there is no separate readonly data section.
  10801. +*/
  10802. +/* Put jump tables in text section if we have caches. Otherwise assume that
  10803. + loading data from code memory is slow. */
  10804. +#define JUMP_TABLES_IN_TEXT_SECTION \
  10805. + (TARGET_CACHES ? 1 : 0)
  10806. +
  10807. +
  10808. +/******************************************************************************
  10809. + * Position Independent Code (PIC)
  10810. + *****************************************************************************/
  10811. +
  10812. +#ifndef AVR32_ALWAYS_PIC
  10813. +#define AVR32_ALWAYS_PIC 0
  10814. +#endif
  10815. +
  10816. +/* GOT is set to r6 */
  10817. +#define PIC_OFFSET_TABLE_REGNUM INTERNAL_REGNUM(6)
  10818. +
  10819. +/*
  10820. +A C expression that is nonzero if X is a legitimate immediate
  10821. +operand on the target machine when generating position independent code.
  10822. +You can assume that X satisfies CONSTANT_P, so you need not
  10823. +check this. You can also assume flag_pic is true, so you need not
  10824. +check it either. You need not define this macro if all constants
  10825. +(including SYMBOL_REF) can be immediate operands when generating
  10826. +position independent code.
  10827. +*/
  10828. +/* We can't directly access anything that contains a symbol,
  10829. + nor can we indirect via the constant pool. */
  10830. +#define LEGITIMATE_PIC_OPERAND_P(X) avr32_legitimate_pic_operand_p(X)
  10831. +
  10832. +
  10833. +/* We need to know when we are making a constant pool; this determines
  10834. + whether data needs to be in the GOT or can be referenced via a GOT
  10835. + offset. */
  10836. +extern int making_const_table;
  10837. +
  10838. +/******************************************************************************
  10839. + * Defining the Output Assembler Language
  10840. + *****************************************************************************/
  10841. +
  10842. +
  10843. +/*
  10844. +A C string constant describing how to begin a comment in the target
  10845. +assembler language. The compiler assumes that the comment will end at
  10846. +the end of the line.
  10847. +*/
  10848. +#define ASM_COMMENT_START "# "
  10849. +
  10850. +/*
  10851. +A C string constant for text to be output before each asm
  10852. +statement or group of consecutive ones. Normally this is
  10853. +"#APP", which is a comment that has no effect on most
  10854. +assemblers but tells the GNU assembler that it must check the lines
  10855. +that follow for all valid assembler constructs.
  10856. +*/
  10857. +#undef ASM_APP_ON
  10858. +#define ASM_APP_ON "#APP\n"
  10859. +
  10860. +/*
  10861. +A C string constant for text to be output after each asm
  10862. +statement or group of consecutive ones. Normally this is
  10863. +"#NO_APP", which tells the GNU assembler to resume making the
  10864. +time-saving assumptions that are valid for ordinary compiler output.
  10865. +*/
  10866. +#undef ASM_APP_OFF
  10867. +#define ASM_APP_OFF "#NO_APP\n"
  10868. +
  10869. +
  10870. +
  10871. +#define FILE_ASM_OP "\t.file\n"
  10872. +#define IDENT_ASM_OP "\t.ident\t"
  10873. +#define SET_ASM_OP "\t.set\t"
  10874. +
  10875. +
  10876. +/*
  10877. + * Output assembly directives to switch to section name. The section
  10878. + * should have attributes as specified by flags, which is a bit mask
  10879. + * of the SECTION_* flags defined in 'output.h'. If align is nonzero,
  10880. + * it contains an alignment in bytes to be used for the section,
  10881. + * otherwise some target default should be used. Only targets that
  10882. + * must specify an alignment within the section directive need pay
  10883. + * attention to align -- we will still use ASM_OUTPUT_ALIGN.
  10884. + *
  10885. + * NOTE: This one must not be moved to avr32.c
  10886. + */
  10887. +#undef TARGET_ASM_NAMED_SECTION
  10888. +#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
  10889. +
  10890. +
  10891. +/*
  10892. +You may define this macro as a C expression. You should define the
  10893. +expression to have a nonzero value if GCC should output the constant
  10894. +pool for a function before the code for the function, or a zero value if
  10895. +GCC should output the constant pool after the function. If you do
  10896. +not define this macro, the usual case, GCC will output the constant
  10897. +pool before the function.
  10898. +*/
  10899. +#define CONSTANT_POOL_BEFORE_FUNCTION 0
  10900. +
  10901. +
  10902. +/*
  10903. +Define this macro as a C expression which is nonzero if the constant
  10904. +EXP, of type tree, should be output after the code for a
  10905. +function. The compiler will normally output all constants before the
  10906. +function; you need not define this macro if this is OK.
  10907. +*/
  10908. +#define CONSTANT_AFTER_FUNCTION_P(EXP) 1
  10909. +
  10910. +
  10911. +/*
  10912. +Define this macro as a C expression which is nonzero if C is
  10913. +as a logical line separator by the assembler. STR points to the
  10914. +position in the string where C was found; this can be used if a
  10915. +line separator uses multiple characters.
  10916. +
  10917. +If you do not define this macro, the default is that only
  10918. +the character ';' is treated as a logical line separator.
  10919. +*/
  10920. +#define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) (((C) == '\n') || ((C) == ';'))
  10921. +
  10922. +
  10923. +/** Output of Uninitialized Variables **/
  10924. +
  10925. +/*
  10926. +A C statement (sans semicolon) to output to the stdio stream
  10927. +STREAM the assembler definition of a common-label named
  10928. +NAME whose size is SIZE bytes. The variable ROUNDED
  10929. +is the size rounded up to whatever alignment the caller wants.
  10930. +
  10931. +Use the expression assemble_name(STREAM, NAME) to
  10932. +output the name itself; before and after that, output the additional
  10933. +assembler syntax for defining the name, and a newline.
  10934. +
  10935. +This macro controls how the assembler definitions of uninitialized
  10936. +common global variables are output.
  10937. +*/
  10938. +/*
  10939. +#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
  10940. + avr32_asm_output_common(STREAM, NAME, SIZE, ROUNDED)
  10941. +*/
  10942. +
  10943. +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
  10944. + do \
  10945. + { \
  10946. + fputs ("\t.comm ", (FILE)); \
  10947. + assemble_name ((FILE), (NAME)); \
  10948. + fprintf ((FILE), ",%d\n", (SIZE)); \
  10949. + } \
  10950. + while (0)
  10951. +
  10952. +/*
  10953. + * Like ASM_OUTPUT_BSS except takes the required alignment as a
  10954. + * separate, explicit argument. If you define this macro, it is used
  10955. + * in place of ASM_OUTPUT_BSS, and gives you more flexibility in
  10956. + * handling the required alignment of the variable. The alignment is
  10957. + * specified as the number of bits.
  10958. + *
  10959. + * Try to use function asm_output_aligned_bss defined in file varasm.c
  10960. + * when defining this macro.
  10961. + */
  10962. +#define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
  10963. + asm_output_aligned_bss (STREAM, DECL, NAME, SIZE, ALIGNMENT)
  10964. +
  10965. +/*
  10966. +A C statement (sans semicolon) to output to the stdio stream
  10967. +STREAM the assembler definition of a local-common-label named
  10968. +NAME whose size is SIZE bytes. The variable ROUNDED
  10969. +is the size rounded up to whatever alignment the caller wants.
  10970. +
  10971. +Use the expression assemble_name(STREAM, NAME) to
  10972. +output the name itself; before and after that, output the additional
  10973. +assembler syntax for defining the name, and a newline.
  10974. +
  10975. +This macro controls how the assembler definitions of uninitialized
  10976. +static variables are output.
  10977. +*/
  10978. +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
  10979. + do \
  10980. + { \
  10981. + fputs ("\t.lcomm ", (FILE)); \
  10982. + assemble_name ((FILE), (NAME)); \
  10983. + fprintf ((FILE), ",%d, %d\n", (SIZE), 2); \
  10984. + } \
  10985. + while (0)
  10986. +
  10987. +
  10988. +/*
  10989. +A C statement (sans semicolon) to output to the stdio stream
  10990. +STREAM the assembler definition of a label named NAME.
  10991. +Use the expression assemble_name(STREAM, NAME) to
  10992. +output the name itself; before and after that, output the additional
  10993. +assembler syntax for defining the name, and a newline.
  10994. +*/
  10995. +#define ASM_OUTPUT_LABEL(STREAM, NAME) avr32_asm_output_label(STREAM, NAME)
  10996. +
  10997. +/* A C string containing the appropriate assembler directive to
  10998. + * specify the size of a symbol, without any arguments. On systems
  10999. + * that use ELF, the default (in 'config/elfos.h') is '"\t.size\t"';
  11000. + * on other systems, the default is not to define this macro.
  11001. + *
  11002. + * Define this macro only if it is correct to use the default
  11003. + * definitions of ASM_ OUTPUT_SIZE_DIRECTIVE and
  11004. + * ASM_OUTPUT_MEASURED_SIZE for your system. If you need your own
  11005. + * custom definitions of those macros, or if you do not need explicit
  11006. + * symbol sizes at all, do not define this macro.
  11007. + */
  11008. +#define SIZE_ASM_OP "\t.size\t"
  11009. +
  11010. +
  11011. +/*
  11012. +A C statement (sans semicolon) to output to the stdio stream
  11013. +STREAM some commands that will make the label NAME global;
  11014. +that is, available for reference from other files. Use the expression
  11015. +assemble_name(STREAM, NAME) to output the name
  11016. +itself; before and after that, output the additional assembler syntax
  11017. +for making that name global, and a newline.
  11018. +*/
  11019. +#define GLOBAL_ASM_OP "\t.global\t"
  11020. +
  11021. +
  11022. +
  11023. +/*
  11024. +A C expression which evaluates to true if the target supports weak symbols.
  11025. +
  11026. +If you don't define this macro, defaults.h provides a default
  11027. +definition. If either ASM_WEAKEN_LABEL or ASM_WEAKEN_DECL
  11028. +is defined, the default definition is '1'; otherwise, it is
  11029. +'0'. Define this macro if you want to control weak symbol support
  11030. +with a compiler flag such as -melf.
  11031. +*/
  11032. +#define SUPPORTS_WEAK 1
  11033. +
  11034. +/*
  11035. +A C statement (sans semicolon) to output to the stdio stream
  11036. +STREAM a reference in assembler syntax to a label named
  11037. +NAME. This should add '_' to the front of the name, if that
  11038. +is customary on your operating system, as it is in most Berkeley Unix
  11039. +systems. This macro is used in assemble_name.
  11040. +*/
  11041. +#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
  11042. + avr32_asm_output_labelref(STREAM, NAME)
  11043. +
  11044. +
  11045. +
  11046. +/*
  11047. +A C expression to assign to OUTVAR (which is a variable of type
  11048. +char *) a newly allocated string made from the string
  11049. +NAME and the number NUMBER, with some suitable punctuation
  11050. +added. Use alloca to get space for the string.
  11051. +
  11052. +The string will be used as an argument to ASM_OUTPUT_LABELREF to
  11053. +produce an assembler label for an internal static variable whose name is
  11054. +NAME. Therefore, the string must be such as to result in valid
  11055. +assembler code. The argument NUMBER is different each time this
  11056. +macro is executed; it prevents conflicts between similarly-named
  11057. +internal static variables in different scopes.
  11058. +
  11059. +Ideally this string should not be a valid C identifier, to prevent any
  11060. +conflict with the user's own symbols. Most assemblers allow periods
  11061. +or percent signs in assembler symbols; putting at least one of these
  11062. +between the name and the number will suffice.
  11063. +*/
  11064. +#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
  11065. + do \
  11066. + { \
  11067. + (OUTVAR) = (char *) alloca (strlen ((NAME)) + 10); \
  11068. + sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)); \
  11069. + } \
  11070. + while (0)
  11071. +
  11072. +
  11073. +/** Macros Controlling Initialization Routines **/
  11074. +
  11075. +
  11076. +/*
  11077. +If defined, main will not call __main as described above.
  11078. +This macro should be defined for systems that control start-up code
  11079. +on a symbol-by-symbol basis, such as OSF/1, and should not
  11080. +be defined explicitly for systems that support INIT_SECTION_ASM_OP.
  11081. +*/
  11082. +/*
  11083. + __main is not defined when debugging.
  11084. +*/
  11085. +#define HAS_INIT_SECTION
  11086. +
  11087. +
  11088. +/** Output of Assembler Instructions **/
  11089. +
  11090. +/*
  11091. +A C initializer containing the assembler's names for the machine
  11092. +registers, each one as a C string constant. This is what translates
  11093. +register numbers in the compiler into assembler language.
  11094. +*/
  11095. +
  11096. +#define REGISTER_NAMES \
  11097. +{ \
  11098. + "pc", "lr", \
  11099. + "sp", "r12", \
  11100. + "r11", "r10", \
  11101. + "r9", "r8", \
  11102. + "r7", "r6", \
  11103. + "r5", "r4", \
  11104. + "r3", "r2", \
  11105. + "r1", "r0", \
  11106. +}
  11107. +
  11108. +/*
  11109. +A C compound statement to output to stdio stream STREAM the
  11110. +assembler syntax for an instruction operand X. X is an
  11111. +RTL expression.
  11112. +
  11113. +CODE is a value that can be used to specify one of several ways
  11114. +of printing the operand. It is used when identical operands must be
  11115. +printed differently depending on the context. CODE comes from
  11116. +the '%' specification that was used to request printing of the
  11117. +operand. If the specification was just '%digit' then
  11118. +CODE is 0; if the specification was '%ltr digit'
  11119. +then CODE is the ASCII code for ltr.
  11120. +
  11121. +If X is a register, this macro should print the register's name.
  11122. +The names can be found in an array reg_names whose type is
  11123. +char *[]. reg_names is initialized from REGISTER_NAMES.
  11124. +
  11125. +When the machine description has a specification '%punct'
  11126. +(a '%' followed by a punctuation character), this macro is called
  11127. +with a null pointer for X and the punctuation character for
  11128. +CODE.
  11129. +*/
  11130. +#define PRINT_OPERAND(STREAM, X, CODE) avr32_print_operand(STREAM, X, CODE)
  11131. +
  11132. +/* A C statement to be executed just prior to the output of
  11133. + assembler code for INSN, to modify the extracted operands so
  11134. + they will be output differently.
  11135. +
  11136. + Here the argument OPVEC is the vector containing the operands
  11137. + extracted from INSN, and NOPERANDS is the number of elements of
  11138. + the vector which contain meaningful data for this insn.
  11139. + The contents of this vector are what will be used to convert the insn
  11140. + template into assembler code, so you can change the assembler output
  11141. + by changing the contents of the vector. */
  11142. +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
  11143. + avr32_final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
  11144. +
  11145. +/*
  11146. +A C expression which evaluates to true if CODE is a valid
  11147. +punctuation character for use in the PRINT_OPERAND macro. If
  11148. +PRINT_OPERAND_PUNCT_VALID_P is not defined, it means that no
  11149. +punctuation characters (except for the standard one, '%') are used
  11150. +in this way.
  11151. +*/
  11152. +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
  11153. + (((CODE) == '?') \
  11154. + || ((CODE) == '!'))
  11155. +
  11156. +/*
  11157. +A C compound statement to output to stdio stream STREAM the
  11158. +assembler syntax for an instruction operand that is a memory reference
  11159. +whose address is X. X is an RTL expression.
  11160. +
  11161. +On some machines, the syntax for a symbolic address depends on the
  11162. +section that the address refers to. On these machines, define the macro
  11163. +ENCODE_SECTION_INFO to store the information into the
  11164. +symbol_ref, and then check for it here. (see Assembler Format.)
  11165. +*/
  11166. +#define PRINT_OPERAND_ADDRESS(STREAM, X) avr32_print_operand_address(STREAM, X)
  11167. +
  11168. +
  11169. +/** Output of Dispatch Tables **/
  11170. +
  11171. +/*
  11172. + * A C statement to output to the stdio stream stream an assembler
  11173. + * pseudo-instruction to generate a difference between two
  11174. + * labels. value and rel are the numbers of two internal labels. The
  11175. + * definitions of these labels are output using
  11176. + * (*targetm.asm_out.internal_label), and they must be printed in the
  11177. + * same way here. For example,
  11178. + *
  11179. + * fprintf (stream, "\t.word L%d-L%d\n",
  11180. + * value, rel)
  11181. + *
  11182. + * You must provide this macro on machines where the addresses in a
  11183. + * dispatch table are relative to the table's own address. If defined,
  11184. + * GCC will also use this macro on all machines when producing
  11185. + * PIC. body is the body of the ADDR_DIFF_VEC; it is provided so that
  11186. + * the mode and flags can be read.
  11187. + */
  11188. +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
  11189. + fprintf(STREAM, "\tbral\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
  11190. +
  11191. +/*
  11192. +This macro should be provided on machines where the addresses
  11193. +in a dispatch table are absolute.
  11194. +
  11195. +The definition should be a C statement to output to the stdio stream
  11196. +STREAM an assembler pseudo-instruction to generate a reference to
  11197. +a label. VALUE is the number of an internal label whose
  11198. +definition is output using ASM_OUTPUT_INTERNAL_LABEL.
  11199. +For example,
  11200. +
  11201. +fprintf(STREAM, "\t.word L%d\n", VALUE)
  11202. +*/
  11203. +
  11204. +#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
  11205. + fprintf(STREAM, "\t.long %sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
  11206. +
  11207. +/** Assembler Commands for Exception Regions */
  11208. +
  11209. +/* ToDo: All of this subsection */
  11210. +
  11211. +/** Assembler Commands for Alignment */
  11212. +
  11213. +
  11214. +/*
  11215. +A C statement to output to the stdio stream STREAM an assembler
  11216. +command to advance the location counter to a multiple of 2 to the
  11217. +POWER bytes. POWER will be a C expression of type int.
  11218. +*/
  11219. +#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
  11220. + do \
  11221. + { \
  11222. + if ((POWER) != 0) \
  11223. + fprintf(STREAM, "\t.align\t%d\n", POWER); \
  11224. + } \
  11225. + while (0)
  11226. +
  11227. +/*
  11228. +Like ASM_OUTPUT_ALIGN, except that the \nop" instruction is used for padding, if
  11229. +necessary.
  11230. +*/
  11231. +#define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \
  11232. + fprintf(STREAM, "\t.balignw\t%d, 0xd703\n", (1 << POWER))
  11233. +
  11234. +
  11235. +
  11236. +/******************************************************************************
  11237. + * Controlling Debugging Information Format
  11238. + *****************************************************************************/
  11239. +
  11240. +/* How to renumber registers for dbx and gdb. */
  11241. +#define DBX_REGISTER_NUMBER(REGNO) ASM_REGNUM (REGNO)
  11242. +
  11243. +/* The DWARF 2 CFA column which tracks the return address. */
  11244. +#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM(LR_REGNUM)
  11245. +
  11246. +/*
  11247. +Define this macro if GCC should produce dwarf version 2 format
  11248. +debugging output in response to the -g option.
  11249. +
  11250. +To support optional call frame debugging information, you must also
  11251. +define INCOMING_RETURN_ADDR_RTX and either set
  11252. +RTX_FRAME_RELATED_P on the prologue insns if you use RTL for the
  11253. +prologue, or call dwarf2out_def_cfa and dwarf2out_reg_save
  11254. +as appropriate from TARGET_ASM_FUNCTION_PROLOGUE if you don't.
  11255. +*/
  11256. +#define DWARF2_DEBUGGING_INFO 1
  11257. +
  11258. +
  11259. +#define DWARF2_ASM_LINE_DEBUG_INFO 1
  11260. +#define DWARF2_FRAME_INFO 1
  11261. +
  11262. +
  11263. +/******************************************************************************
  11264. + * Miscellaneous Parameters
  11265. + *****************************************************************************/
  11266. +
  11267. +/* ToDo: a lot */
  11268. +
  11269. +/*
  11270. +An alias for a machine mode name. This is the machine mode that
  11271. +elements of a jump-table should have.
  11272. +*/
  11273. +#define CASE_VECTOR_MODE SImode
  11274. +
  11275. +/*
  11276. +Define this macro to be a C expression to indicate when jump-tables
  11277. +should contain relative addresses. If jump-tables never contain
  11278. +relative addresses, then you need not define this macro.
  11279. +*/
  11280. +#define CASE_VECTOR_PC_RELATIVE 0
  11281. +
  11282. +/* Increase the threshold for using table jumps on the UC arch. */
  11283. +#define CASE_VALUES_THRESHOLD (TARGET_BRANCH_PRED ? 4 : 7)
  11284. +
  11285. +/*
  11286. +The maximum number of bytes that a single instruction can move quickly
  11287. +between memory and registers or between two memory locations.
  11288. +*/
  11289. +#define MOVE_MAX (2*UNITS_PER_WORD)
  11290. +
  11291. +
  11292. +/* A C expression that is nonzero if on this machine the number of bits actually used
  11293. + for the count of a shift operation is equal to the number of bits needed to represent
  11294. + the size of the object being shifted. When this macro is nonzero, the compiler will
  11295. + assume that it is safe to omit a sign-extend, zero-extend, and certain bitwise 'and'
  11296. + instructions that truncates the count of a shift operation. On machines that have
  11297. + instructions that act on bit-fields at variable positions, which may include 'bit test'
  11298. + 378 GNU Compiler Collection (GCC) Internals
  11299. + instructions, a nonzero SHIFT_COUNT_TRUNCATED also enables deletion of truncations
  11300. + of the values that serve as arguments to bit-field instructions.
  11301. + If both types of instructions truncate the count (for shifts) and position (for bit-field
  11302. + operations), or if no variable-position bit-field instructions exist, you should define
  11303. + this macro.
  11304. + However, on some machines, such as the 80386 and the 680x0, truncation only applies
  11305. + to shift operations and not the (real or pretended) bit-field operations. Define SHIFT_
  11306. + COUNT_TRUNCATED to be zero on such machines. Instead, add patterns to the 'md' file
  11307. + that include the implied truncation of the shift instructions.
  11308. + You need not de ne this macro if it would always have the value of zero. */
  11309. +#define SHIFT_COUNT_TRUNCATED 1
  11310. +
  11311. +/*
  11312. +A C expression which is nonzero if on this machine it is safe to
  11313. +convert an integer of INPREC bits to one of OUTPREC
  11314. +bits (where OUTPREC is smaller than INPREC) by merely
  11315. +operating on it as if it had only OUTPREC bits.
  11316. +
  11317. +On many machines, this expression can be 1.
  11318. +
  11319. +When TRULY_NOOP_TRUNCATION returns 1 for a pair of sizes for
  11320. +modes for which MODES_TIEABLE_P is 0, suboptimal code can result.
  11321. +If this is the case, making TRULY_NOOP_TRUNCATION return 0 in
  11322. +such cases may improve things.
  11323. +*/
  11324. +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
  11325. +
  11326. +/*
  11327. +An alias for the machine mode for pointers. On most machines, define
  11328. +this to be the integer mode corresponding to the width of a hardware
  11329. +pointer; SImode on 32-bit machine or DImode on 64-bit machines.
  11330. +On some machines you must define this to be one of the partial integer
  11331. +modes, such as PSImode.
  11332. +
  11333. +The width of Pmode must be at least as large as the value of
  11334. +POINTER_SIZE. If it is not equal, you must define the macro
  11335. +POINTERS_EXTEND_UNSIGNED to specify how pointers are extended
  11336. +to Pmode.
  11337. +*/
  11338. +#define Pmode SImode
  11339. +
  11340. +/*
  11341. +An alias for the machine mode used for memory references to functions
  11342. +being called, in call RTL expressions. On most machines this
  11343. +should be QImode.
  11344. +*/
  11345. +#define FUNCTION_MODE SImode
  11346. +
  11347. +
  11348. +#define REG_S_P(x) \
  11349. + (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (XEXP (x, 0))))
  11350. +
  11351. +
  11352. +/* If defined, modifies the length assigned to instruction INSN as a
  11353. + function of the context in which it is used. LENGTH is an lvalue
  11354. + that contains the initially computed length of the insn and should
  11355. + be updated with the correct length of the insn. */
  11356. +#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  11357. + ((LENGTH) = avr32_adjust_insn_length ((INSN), (LENGTH)))
  11358. +
  11359. +
  11360. +#define CLZ_DEFINED_VALUE_AT_ZERO(mode, value) \
  11361. + (value = 32, (mode == SImode))
  11362. +
  11363. +#define CTZ_DEFINED_VALUE_AT_ZERO(mode, value) \
  11364. + (value = 32, (mode == SImode))
  11365. +
  11366. +#define UNITS_PER_SIMD_WORD(mode) UNITS_PER_WORD
  11367. +
  11368. +#define STORE_FLAG_VALUE 1
  11369. +
  11370. +
  11371. +/* IF-conversion macros. */
  11372. +#define IFCVT_MODIFY_INSN( CE_INFO, PATTERN, INSN ) \
  11373. + { \
  11374. + (PATTERN) = avr32_ifcvt_modify_insn (CE_INFO, PATTERN, INSN, &num_true_changes); \
  11375. + }
  11376. +
  11377. +#define IFCVT_EXTRA_FIELDS \
  11378. + int num_cond_clobber_insns; \
  11379. + int num_extra_move_insns; \
  11380. + rtx extra_move_insns[MAX_CONDITIONAL_EXECUTE]; \
  11381. + rtx moved_insns[MAX_CONDITIONAL_EXECUTE];
  11382. +
  11383. +#define IFCVT_INIT_EXTRA_FIELDS( CE_INFO ) \
  11384. + { \
  11385. + (CE_INFO)->num_cond_clobber_insns = 0; \
  11386. + (CE_INFO)->num_extra_move_insns = 0; \
  11387. + }
  11388. +
  11389. +
  11390. +#define IFCVT_MODIFY_CANCEL( CE_INFO ) avr32_ifcvt_modify_cancel (CE_INFO, &num_true_changes)
  11391. +
  11392. +#define IFCVT_ALLOW_MODIFY_TEST_IN_INSN 1
  11393. +#define IFCVT_COND_EXEC_BEFORE_RELOAD (TARGET_COND_EXEC_BEFORE_RELOAD)
  11394. +
  11395. +enum avr32_builtins
  11396. +{
  11397. + AVR32_BUILTIN_MTSR,
  11398. + AVR32_BUILTIN_MFSR,
  11399. + AVR32_BUILTIN_MTDR,
  11400. + AVR32_BUILTIN_MFDR,
  11401. + AVR32_BUILTIN_CACHE,
  11402. + AVR32_BUILTIN_SYNC,
  11403. + AVR32_BUILTIN_SSRF,
  11404. + AVR32_BUILTIN_CSRF,
  11405. + AVR32_BUILTIN_TLBR,
  11406. + AVR32_BUILTIN_TLBS,
  11407. + AVR32_BUILTIN_TLBW,
  11408. + AVR32_BUILTIN_BREAKPOINT,
  11409. + AVR32_BUILTIN_XCHG,
  11410. + AVR32_BUILTIN_LDXI,
  11411. + AVR32_BUILTIN_BSWAP16,
  11412. + AVR32_BUILTIN_BSWAP32,
  11413. + AVR32_BUILTIN_COP,
  11414. + AVR32_BUILTIN_MVCR_W,
  11415. + AVR32_BUILTIN_MVRC_W,
  11416. + AVR32_BUILTIN_MVCR_D,
  11417. + AVR32_BUILTIN_MVRC_D,
  11418. + AVR32_BUILTIN_MULSATHH_H,
  11419. + AVR32_BUILTIN_MULSATHH_W,
  11420. + AVR32_BUILTIN_MULSATRNDHH_H,
  11421. + AVR32_BUILTIN_MULSATRNDWH_W,
  11422. + AVR32_BUILTIN_MULSATWH_W,
  11423. + AVR32_BUILTIN_MACSATHH_W,
  11424. + AVR32_BUILTIN_SATADD_H,
  11425. + AVR32_BUILTIN_SATSUB_H,
  11426. + AVR32_BUILTIN_SATADD_W,
  11427. + AVR32_BUILTIN_SATSUB_W,
  11428. + AVR32_BUILTIN_MULWH_D,
  11429. + AVR32_BUILTIN_MULNWH_D,
  11430. + AVR32_BUILTIN_MACWH_D,
  11431. + AVR32_BUILTIN_MACHH_D,
  11432. + AVR32_BUILTIN_MUSFR,
  11433. + AVR32_BUILTIN_MUSTR,
  11434. + AVR32_BUILTIN_SATS,
  11435. + AVR32_BUILTIN_SATU,
  11436. + AVR32_BUILTIN_SATRNDS,
  11437. + AVR32_BUILTIN_SATRNDU,
  11438. + AVR32_BUILTIN_MEMS,
  11439. + AVR32_BUILTIN_MEMC,
  11440. + AVR32_BUILTIN_MEMT,
  11441. + AVR32_BUILTIN_SLEEP,
  11442. + AVR32_BUILTIN_DELAY_CYCLES
  11443. +};
  11444. +
  11445. +
  11446. +#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) \
  11447. + ((MODE == SFmode) || (MODE == DFmode))
  11448. +
  11449. +#define RENAME_LIBRARY_SET ".set"
  11450. +
  11451. +/* Make ABI_NAME an alias for __GCC_NAME. */
  11452. +#define RENAME_LIBRARY(GCC_NAME, ABI_NAME) \
  11453. + __asm__ (".globl\t__avr32_" #ABI_NAME "\n" \
  11454. + ".set\t__avr32_" #ABI_NAME \
  11455. + ", __" #GCC_NAME "\n");
  11456. +
  11457. +/* Give libgcc functions avr32 ABI name. */
  11458. +#ifdef L_muldi3
  11459. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, mul64)
  11460. +#endif
  11461. +#ifdef L_divdi3
  11462. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divdi3, sdiv64)
  11463. +#endif
  11464. +#ifdef L_udivdi3
  11465. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (udivdi3, udiv64)
  11466. +#endif
  11467. +#ifdef L_moddi3
  11468. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (moddi3, smod64)
  11469. +#endif
  11470. +#ifdef L_umoddi3
  11471. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (umoddi3, umod64)
  11472. +#endif
  11473. +#ifdef L_ashldi3
  11474. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashldi3, lsl64)
  11475. +#endif
  11476. +#ifdef L_lshrdi3
  11477. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (lshrdi3, lsr64)
  11478. +#endif
  11479. +#ifdef L_ashrdi3
  11480. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashrdi3, asr64)
  11481. +#endif
  11482. +
  11483. +#ifdef L_fixsfdi
  11484. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f32_to_s64)
  11485. +#endif
  11486. +#ifdef L_fixunssfdi
  11487. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f32_to_u64)
  11488. +#endif
  11489. +#ifdef L_floatdidf
  11490. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdidf, s64_to_f64)
  11491. +#endif
  11492. +#ifdef L_floatdisf
  11493. +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdisf, s64_to_f32)
  11494. +#endif
  11495. +
  11496. +#endif
  11497. --- /dev/null
  11498. +++ b/gcc/config/avr32/avr32.md
  11499. @@ -0,0 +1,5198 @@
  11500. +;; AVR32 machine description file.
  11501. +;; Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  11502. +;;
  11503. +;; This file is part of GCC.
  11504. +;;
  11505. +;; This program is free software; you can redistribute it and/or modify
  11506. +;; it under the terms of the GNU General Public License as published by
  11507. +;; the Free Software Foundation; either version 2 of the License, or
  11508. +;; (at your option) any later version.
  11509. +;;
  11510. +;; This program is distributed in the hope that it will be useful,
  11511. +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  11512. +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11513. +;; GNU General Public License for more details.
  11514. +;;
  11515. +;; You should have received a copy of the GNU General Public License
  11516. +;; along with this program; if not, write to the Free Software
  11517. +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  11518. +
  11519. +;; -*- Mode: Scheme -*-
  11520. +
  11521. +(define_attr "type" "alu,alu2,alu_sat,mulhh,mulwh,mulww_w,mulww_d,div,machh_w,macww_w,macww_d,branch,call,load,load_rm,store,load2,load4,store2,store4,fmul,fcmps,fcmpd,fcast,fmv,fmvcpu,fldd,fstd,flds,fsts,fstm"
  11522. + (const_string "alu"))
  11523. +
  11524. +
  11525. +(define_attr "cc" "none,set_vncz,set_ncz,set_cz,set_z,set_z_if_not_v2,bld,compare,cmp_cond_insn,clobber,call_set,fpcompare,from_fpcc"
  11526. + (const_string "none"))
  11527. +
  11528. +
  11529. +; NB! Keep this in sync with enum architecture_type in avr32.h
  11530. +(define_attr "pipeline" "ap,ucr1,ucr2,ucr2nomul,ucr3,ucr3fp"
  11531. + (const (symbol_ref "avr32_arch->arch_type")))
  11532. +
  11533. +; Insn length in bytes
  11534. +(define_attr "length" ""
  11535. + (const_int 4))
  11536. +
  11537. +; Signal if an insn is predicable and hence can be conditionally executed.
  11538. +(define_attr "predicable" "no,yes" (const_string "no"))
  11539. +
  11540. +;; Uses of UNSPEC in this file:
  11541. +(define_constants
  11542. + [(UNSPEC_PUSHM 0)
  11543. + (UNSPEC_POPM 1)
  11544. + (UNSPEC_UDIVMODSI4_INTERNAL 2)
  11545. + (UNSPEC_DIVMODSI4_INTERNAL 3)
  11546. + (UNSPEC_STM 4)
  11547. + (UNSPEC_LDM 5)
  11548. + (UNSPEC_MOVSICC 6)
  11549. + (UNSPEC_ADDSICC 7)
  11550. + (UNSPEC_COND_MI 8)
  11551. + (UNSPEC_COND_PL 9)
  11552. + (UNSPEC_PIC_SYM 10)
  11553. + (UNSPEC_PIC_BASE 11)
  11554. + (UNSPEC_STORE_MULTIPLE 12)
  11555. + (UNSPEC_STMFP 13)
  11556. + (UNSPEC_FRCPA 14)
  11557. + (UNSPEC_REG_TO_CC 15)
  11558. + (UNSPEC_FORCE_MINIPOOL 16)
  11559. + (UNSPEC_SATS 17)
  11560. + (UNSPEC_SATU 18)
  11561. + (UNSPEC_SATRNDS 19)
  11562. + (UNSPEC_SATRNDU 20)
  11563. + ])
  11564. +
  11565. +(define_constants
  11566. + [(VUNSPEC_EPILOGUE 0)
  11567. + (VUNSPEC_CACHE 1)
  11568. + (VUNSPEC_MTSR 2)
  11569. + (VUNSPEC_MFSR 3)
  11570. + (VUNSPEC_BLOCKAGE 4)
  11571. + (VUNSPEC_SYNC 5)
  11572. + (VUNSPEC_TLBR 6)
  11573. + (VUNSPEC_TLBW 7)
  11574. + (VUNSPEC_TLBS 8)
  11575. + (VUNSPEC_BREAKPOINT 9)
  11576. + (VUNSPEC_MTDR 10)
  11577. + (VUNSPEC_MFDR 11)
  11578. + (VUNSPEC_MVCR 12)
  11579. + (VUNSPEC_MVRC 13)
  11580. + (VUNSPEC_COP 14)
  11581. + (VUNSPEC_ALIGN 15)
  11582. + (VUNSPEC_POOL_START 16)
  11583. + (VUNSPEC_POOL_END 17)
  11584. + (VUNSPEC_POOL_4 18)
  11585. + (VUNSPEC_POOL_8 19)
  11586. + (VUNSPEC_POOL_16 20)
  11587. + (VUNSPEC_MUSFR 21)
  11588. + (VUNSPEC_MUSTR 22)
  11589. + (VUNSPEC_SYNC_CMPXCHG 23)
  11590. + (VUNSPEC_SYNC_SET_LOCK_AND_LOAD 24)
  11591. + (VUNSPEC_SYNC_STORE_IF_LOCK 25)
  11592. + (VUNSPEC_EH_RETURN 26)
  11593. + (VUNSPEC_FRS 27)
  11594. + (VUNSPEC_CSRF 28)
  11595. + (VUNSPEC_SSRF 29)
  11596. + (VUNSPEC_SLEEP 30)
  11597. + (VUNSPEC_DELAY_CYCLES 31)
  11598. + (VUNSPEC_DELAY_CYCLES_1 32)
  11599. + (VUNSPEC_DELAY_CYCLES_2 33)
  11600. + (VUNSPEC_NOP 34)
  11601. + (VUNSPEC_NOP3 35)
  11602. + ])
  11603. +
  11604. +(define_constants
  11605. + [
  11606. + ;; R7 = 15-7 = 8
  11607. + (FP_REGNUM 8)
  11608. + ;; Return Register = R12 = 15 - 12 = 3
  11609. + (RETVAL_REGNUM 3)
  11610. + ;; SP = R13 = 15 - 13 = 2
  11611. + (SP_REGNUM 2)
  11612. + ;; LR = R14 = 15 - 14 = 1
  11613. + (LR_REGNUM 1)
  11614. + ;; PC = R15 = 15 - 15 = 0
  11615. + (PC_REGNUM 0)
  11616. + ;; FPSR = GENERAL_REGS + 1 = 17
  11617. + (FPCC_REGNUM 17)
  11618. + ])
  11619. +
  11620. +
  11621. +
  11622. +
  11623. +;;******************************************************************************
  11624. +;; Macros
  11625. +;;******************************************************************************
  11626. +
  11627. +;; Integer Modes for basic alu insns
  11628. +(define_mode_iterator INTM [SI HI QI])
  11629. +(define_mode_attr alu_cc_attr [(SI "set_vncz") (HI "clobber") (QI "clobber")])
  11630. +
  11631. +;; Move word modes
  11632. +(define_mode_iterator MOVM [SI V2HI V4QI])
  11633. +
  11634. +;; For mov/addcc insns
  11635. +(define_mode_iterator ADDCC [SI HI QI])
  11636. +(define_mode_iterator MOVCC [SF SI HI QI])
  11637. +(define_mode_iterator CMP [DI SI HI QI])
  11638. +(define_mode_attr store_postfix [(SF ".w") (SI ".w") (HI ".h") (QI ".b")])
  11639. +(define_mode_attr load_postfix [(SF ".w") (SI ".w") (HI ".sh") (QI ".ub")])
  11640. +(define_mode_attr load_postfix_s [(SI ".w") (HI ".sh") (QI ".sb")])
  11641. +(define_mode_attr load_postfix_u [(SI ".w") (HI ".uh") (QI ".ub")])
  11642. +(define_mode_attr pred_mem_constraint [(SF "RKu11") (SI "RKu11") (HI "RKu10") (QI "RKu09")])
  11643. +(define_mode_attr cmp_constraint [(DI "rKu20") (SI "rKs21") (HI "r") (QI "r")])
  11644. +(define_mode_attr cmp_predicate [(DI "register_immediate_operand")
  11645. + (SI "register_const_int_operand")
  11646. + (HI "register_operand")
  11647. + (QI "register_operand")])
  11648. +(define_mode_attr cmp_length [(DI "6")
  11649. + (SI "4")
  11650. + (HI "4")
  11651. + (QI "4")])
  11652. +
  11653. +;; For all conditional insns
  11654. +(define_code_iterator any_cond_b [ge lt geu ltu])
  11655. +(define_code_iterator any_cond [gt ge lt le gtu geu ltu leu])
  11656. +(define_code_iterator any_cond4 [gt le gtu leu])
  11657. +(define_code_attr cond [(eq "eq") (ne "ne") (gt "gt") (ge "ge") (lt "lt") (le "le")
  11658. + (gtu "hi") (geu "hs") (ltu "lo") (leu "ls")])
  11659. +(define_code_attr invcond [(eq "ne") (ne "eq") (gt "le") (ge "lt") (lt "ge") (le "gt")
  11660. + (gtu "ls") (geu "lo") (ltu "hs") (leu "hi")])
  11661. +
  11662. +;; For logical operations
  11663. +(define_code_iterator logical [and ior xor])
  11664. +(define_code_attr logical_insn [(and "and") (ior "or") (xor "eor")])
  11665. +
  11666. +;; Predicable operations with three register operands
  11667. +(define_code_iterator predicable_op3 [and ior xor plus minus])
  11668. +(define_code_attr predicable_insn3 [(and "and") (ior "or") (xor "eor") (plus "add") (minus "sub")])
  11669. +(define_code_attr predicable_commutative3 [(and "%") (ior "%") (xor "%") (plus "%") (minus "")])
  11670. +
  11671. +;; Load the predicates
  11672. +(include "predicates.md")
  11673. +
  11674. +
  11675. +;;******************************************************************************
  11676. +;; Automaton pipeline description for avr32
  11677. +;;******************************************************************************
  11678. +
  11679. +(define_automaton "avr32_ap")
  11680. +
  11681. +
  11682. +(define_cpu_unit "is" "avr32_ap")
  11683. +(define_cpu_unit "a1,m1,da" "avr32_ap")
  11684. +(define_cpu_unit "a2,m2,d" "avr32_ap")
  11685. +
  11686. +;;Alu instructions
  11687. +(define_insn_reservation "alu_op" 1
  11688. + (and (eq_attr "pipeline" "ap")
  11689. + (eq_attr "type" "alu"))
  11690. + "is,a1,a2")
  11691. +
  11692. +(define_insn_reservation "alu2_op" 2
  11693. + (and (eq_attr "pipeline" "ap")
  11694. + (eq_attr "type" "alu2"))
  11695. + "is,is+a1,a1+a2,a2")
  11696. +
  11697. +(define_insn_reservation "alu_sat_op" 2
  11698. + (and (eq_attr "pipeline" "ap")
  11699. + (eq_attr "type" "alu_sat"))
  11700. + "is,a1,a2")
  11701. +
  11702. +
  11703. +;;Mul instructions
  11704. +(define_insn_reservation "mulhh_op" 2
  11705. + (and (eq_attr "pipeline" "ap")
  11706. + (eq_attr "type" "mulhh,mulwh"))
  11707. + "is,m1,m2")
  11708. +
  11709. +(define_insn_reservation "mulww_w_op" 3
  11710. + (and (eq_attr "pipeline" "ap")
  11711. + (eq_attr "type" "mulww_w"))
  11712. + "is,m1,m1+m2,m2")
  11713. +
  11714. +(define_insn_reservation "mulww_d_op" 5
  11715. + (and (eq_attr "pipeline" "ap")
  11716. + (eq_attr "type" "mulww_d"))
  11717. + "is,m1,m1+m2,m1+m2,m2,m2")
  11718. +
  11719. +(define_insn_reservation "div_op" 33
  11720. + (and (eq_attr "pipeline" "ap")
  11721. + (eq_attr "type" "div"))
  11722. + "is,m1,m1*31 + m2*31,m2")
  11723. +
  11724. +(define_insn_reservation "machh_w_op" 3
  11725. + (and (eq_attr "pipeline" "ap")
  11726. + (eq_attr "type" "machh_w"))
  11727. + "is*2,m1,m2")
  11728. +
  11729. +
  11730. +(define_insn_reservation "macww_w_op" 4
  11731. + (and (eq_attr "pipeline" "ap")
  11732. + (eq_attr "type" "macww_w"))
  11733. + "is*2,m1,m1,m2")
  11734. +
  11735. +
  11736. +(define_insn_reservation "macww_d_op" 6
  11737. + (and (eq_attr "pipeline" "ap")
  11738. + (eq_attr "type" "macww_d"))
  11739. + "is*2,m1,m1+m2,m1+m2,m2")
  11740. +
  11741. +;;Bypasses for Mac instructions, because of accumulator cache.
  11742. +;;Set latency as low as possible in order to let the compiler let
  11743. +;;mul -> mac and mac -> mac combinations which use the same
  11744. +;;accumulator cache be placed close together to avoid any
  11745. +;;instructions which can ruin the accumulator cache come inbetween.
  11746. +(define_bypass 4 "machh_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
  11747. +(define_bypass 5 "macww_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
  11748. +(define_bypass 7 "macww_d_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
  11749. +
  11750. +(define_bypass 3 "mulhh_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
  11751. +(define_bypass 4 "mulww_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
  11752. +(define_bypass 6 "mulww_d_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
  11753. +
  11754. +
  11755. +;;Bypasses for all mul/mac instructions followed by an instruction
  11756. +;;which reads the output AND writes the result to the same register.
  11757. +;;This will generate an Write After Write hazard which gives an
  11758. +;;extra cycle before the result is ready.
  11759. +(define_bypass 0 "machh_w_op" "machh_w_op" "avr32_valid_macmac_bypass")
  11760. +(define_bypass 0 "macww_w_op" "macww_w_op" "avr32_valid_macmac_bypass")
  11761. +(define_bypass 0 "macww_d_op" "macww_d_op" "avr32_valid_macmac_bypass")
  11762. +
  11763. +(define_bypass 0 "mulhh_op" "machh_w_op" "avr32_valid_mulmac_bypass")
  11764. +(define_bypass 0 "mulww_w_op" "macww_w_op" "avr32_valid_mulmac_bypass")
  11765. +(define_bypass 0 "mulww_d_op" "macww_d_op" "avr32_valid_mulmac_bypass")
  11766. +
  11767. +;;Branch and call instructions
  11768. +;;We assume that all branches and rcalls are predicted correctly :-)
  11769. +;;while calls use a lot of cycles.
  11770. +(define_insn_reservation "branch_op" 0
  11771. + (and (eq_attr "pipeline" "ap")
  11772. + (eq_attr "type" "branch"))
  11773. + "nothing")
  11774. +
  11775. +(define_insn_reservation "call_op" 10
  11776. + (and (eq_attr "pipeline" "ap")
  11777. + (eq_attr "type" "call"))
  11778. + "nothing")
  11779. +
  11780. +
  11781. +;;Load store instructions
  11782. +(define_insn_reservation "load_op" 2
  11783. + (and (eq_attr "pipeline" "ap")
  11784. + (eq_attr "type" "load"))
  11785. + "is,da,d")
  11786. +
  11787. +(define_insn_reservation "load_rm_op" 3
  11788. + (and (eq_attr "pipeline" "ap")
  11789. + (eq_attr "type" "load_rm"))
  11790. + "is,da,d")
  11791. +
  11792. +
  11793. +(define_insn_reservation "store_op" 0
  11794. + (and (eq_attr "pipeline" "ap")
  11795. + (eq_attr "type" "store"))
  11796. + "is,da,d")
  11797. +
  11798. +
  11799. +(define_insn_reservation "load_double_op" 3
  11800. + (and (eq_attr "pipeline" "ap")
  11801. + (eq_attr "type" "load2"))
  11802. + "is,da,da+d,d")
  11803. +
  11804. +(define_insn_reservation "load_quad_op" 4
  11805. + (and (eq_attr "pipeline" "ap")
  11806. + (eq_attr "type" "load4"))
  11807. + "is,da,da+d,da+d,d")
  11808. +
  11809. +(define_insn_reservation "store_double_op" 0
  11810. + (and (eq_attr "pipeline" "ap")
  11811. + (eq_attr "type" "store2"))
  11812. + "is,da,da+d,d")
  11813. +
  11814. +
  11815. +(define_insn_reservation "store_quad_op" 0
  11816. + (and (eq_attr "pipeline" "ap")
  11817. + (eq_attr "type" "store4"))
  11818. + "is,da,da+d,da+d,d")
  11819. +
  11820. +;;For store the operand to write to memory is read in d and
  11821. +;;the real latency between any instruction and a store is therefore
  11822. +;;one less than for the instructions which reads the operands in the first
  11823. +;;excecution stage
  11824. +(define_bypass 2 "load_double_op" "store_double_op" "avr32_store_bypass")
  11825. +(define_bypass 3 "load_quad_op" "store_quad_op" "avr32_store_bypass")
  11826. +(define_bypass 1 "load_op" "store_op" "avr32_store_bypass")
  11827. +(define_bypass 2 "load_rm_op" "store_op" "avr32_store_bypass")
  11828. +(define_bypass 1 "alu_sat_op" "store_op" "avr32_store_bypass")
  11829. +(define_bypass 1 "alu2_op" "store_op" "avr32_store_bypass")
  11830. +(define_bypass 1 "mulhh_op" "store_op" "avr32_store_bypass")
  11831. +(define_bypass 2 "mulww_w_op" "store_op" "avr32_store_bypass")
  11832. +(define_bypass 4 "mulww_d_op" "store_op" "avr32_store_bypass" )
  11833. +(define_bypass 2 "machh_w_op" "store_op" "avr32_store_bypass")
  11834. +(define_bypass 3 "macww_w_op" "store_op" "avr32_store_bypass")
  11835. +(define_bypass 5 "macww_d_op" "store_op" "avr32_store_bypass")
  11836. +
  11837. +
  11838. +; Bypass for load double operation. If only the first loaded word is needed
  11839. +; then the latency is 2
  11840. +(define_bypass 2 "load_double_op"
  11841. + "load_op,load_rm_op,alu_sat_op, alu2_op, alu_op, mulhh_op, mulww_w_op,
  11842. + mulww_d_op, machh_w_op, macww_w_op, macww_d_op"
  11843. + "avr32_valid_load_double_bypass")
  11844. +
  11845. +; Bypass for load quad operation. If only the first or second loaded word is needed
  11846. +; we set the latency to 2
  11847. +(define_bypass 2 "load_quad_op"
  11848. + "load_op,load_rm_op,alu_sat_op, alu2_op, alu_op, mulhh_op, mulww_w_op,
  11849. + mulww_d_op, machh_w_op, macww_w_op, macww_d_op"
  11850. + "avr32_valid_load_quad_bypass")
  11851. +
  11852. +
  11853. +;;******************************************************************************
  11854. +;; End of Automaton pipeline description for avr32
  11855. +;;******************************************************************************
  11856. +
  11857. +(define_cond_exec
  11858. + [(match_operator 0 "avr32_comparison_operator"
  11859. + [(match_operand:CMP 1 "register_operand" "r")
  11860. + (match_operand:CMP 2 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")])]
  11861. + "TARGET_V2_INSNS"
  11862. + "%!"
  11863. +)
  11864. +
  11865. +(define_cond_exec
  11866. + [(match_operator 0 "avr32_comparison_operator"
  11867. + [(and:SI (match_operand:SI 1 "register_operand" "r")
  11868. + (match_operand:SI 2 "one_bit_set_operand" "i"))
  11869. + (const_int 0)])]
  11870. + "TARGET_V2_INSNS"
  11871. + "%!"
  11872. + )
  11873. +
  11874. +;;=============================================================================
  11875. +;; move
  11876. +;;-----------------------------------------------------------------------------
  11877. +
  11878. +
  11879. +;;== char - 8 bits ============================================================
  11880. +(define_expand "movqi"
  11881. + [(set (match_operand:QI 0 "nonimmediate_operand" "")
  11882. + (match_operand:QI 1 "general_operand" ""))]
  11883. + ""
  11884. + {
  11885. + if ( can_create_pseudo_p () ){
  11886. + if (GET_CODE (operands[1]) == MEM && optimize){
  11887. + rtx reg = gen_reg_rtx (SImode);
  11888. +
  11889. + emit_insn (gen_zero_extendqisi2 (reg, operands[1]));
  11890. + operands[1] = gen_lowpart (QImode, reg);
  11891. + }
  11892. +
  11893. + /* One of the ops has to be in a register. */
  11894. + if (GET_CODE (operands[0]) == MEM)
  11895. + operands[1] = force_reg (QImode, operands[1]);
  11896. + }
  11897. +
  11898. + })
  11899. +
  11900. +(define_insn "*movqi_internal"
  11901. + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r")
  11902. + (match_operand:QI 1 "general_operand" "rKs08,m,r,i"))]
  11903. + "register_operand (operands[0], QImode)
  11904. + || register_operand (operands[1], QImode)"
  11905. + "@
  11906. + mov\t%0, %1
  11907. + ld.ub\t%0, %1
  11908. + st.b\t%0, %1
  11909. + mov\t%0, %1"
  11910. + [(set_attr "length" "2,4,4,4")
  11911. + (set_attr "type" "alu,load_rm,store,alu")])
  11912. +
  11913. +
  11914. +
  11915. +;;== short - 16 bits ==========================================================
  11916. +(define_expand "movhi"
  11917. + [(set (match_operand:HI 0 "nonimmediate_operand" "")
  11918. + (match_operand:HI 1 "general_operand" ""))]
  11919. + ""
  11920. + {
  11921. + if ( can_create_pseudo_p () ){
  11922. + if (GET_CODE (operands[1]) == MEM && optimize){
  11923. + rtx reg = gen_reg_rtx (SImode);
  11924. +
  11925. + emit_insn (gen_extendhisi2 (reg, operands[1]));
  11926. + operands[1] = gen_lowpart (HImode, reg);
  11927. + }
  11928. +
  11929. + /* One of the ops has to be in a register. */
  11930. + if (GET_CODE (operands[0]) == MEM)
  11931. + operands[1] = force_reg (HImode, operands[1]);
  11932. + }
  11933. +
  11934. + })
  11935. +
  11936. +
  11937. +(define_insn "*movhi_internal"
  11938. + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
  11939. + (match_operand:HI 1 "general_operand" "rKs08,m,r,i"))]
  11940. + "register_operand (operands[0], HImode)
  11941. + || register_operand (operands[1], HImode)"
  11942. + "@
  11943. + mov\t%0, %1
  11944. + ld.sh\t%0, %1
  11945. + st.h\t%0, %1
  11946. + mov\t%0, %1"
  11947. + [(set_attr "length" "2,4,4,4")
  11948. + (set_attr "type" "alu,load_rm,store,alu")])
  11949. +
  11950. +
  11951. +;;== int - 32 bits ============================================================
  11952. +
  11953. +(define_expand "movmisalignsi"
  11954. + [(set (match_operand:SI 0 "nonimmediate_operand" "")
  11955. + (match_operand:SI 1 "nonimmediate_operand" ""))]
  11956. + "TARGET_UNALIGNED_WORD"
  11957. + {
  11958. + }
  11959. +)
  11960. +
  11961. +(define_expand "mov<mode>"
  11962. + [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "")
  11963. + (match_operand:MOVM 1 "avr32_non_rmw_general_operand" ""))]
  11964. + ""
  11965. + {
  11966. +
  11967. + /* One of the ops has to be in a register. */
  11968. + if (GET_CODE (operands[0]) == MEM)
  11969. + operands[1] = force_reg (<MODE>mode, operands[1]);
  11970. +
  11971. + /* Check for out of range immediate constants as these may
  11972. + occur during reloading, since it seems like reload does
  11973. + not check if the immediate is legitimate. Don't know if
  11974. + this is a bug? */
  11975. + if ( reload_in_progress
  11976. + && avr32_imm_in_const_pool
  11977. + && GET_CODE(operands[1]) == CONST_INT
  11978. + && !avr32_const_ok_for_constraint_p(INTVAL(operands[1]), 'K', "Ks21") ){
  11979. + operands[1] = force_const_mem(SImode, operands[1]);
  11980. + }
  11981. + /* Check for RMW memory operands. They are not allowed for mov operations
  11982. + only the atomic memc/s/t operations */
  11983. + if ( !reload_in_progress
  11984. + && avr32_rmw_memory_operand (operands[0], <MODE>mode) ){
  11985. + operands[0] = copy_rtx (operands[0]);
  11986. + XEXP(operands[0], 0) = force_reg (<MODE>mode, XEXP(operands[0], 0));
  11987. + }
  11988. +
  11989. + if ( !reload_in_progress
  11990. + && avr32_rmw_memory_operand (operands[1], <MODE>mode) ){
  11991. + operands[1] = copy_rtx (operands[1]);
  11992. + XEXP(operands[1], 0) = force_reg (<MODE>mode, XEXP(operands[1], 0));
  11993. + }
  11994. + if ( (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS)
  11995. + && !avr32_legitimate_pic_operand_p(operands[1]) )
  11996. + operands[1] = legitimize_pic_address (operands[1], <MODE>mode,
  11997. + (can_create_pseudo_p () ? 0: operands[0]));
  11998. + else if ( flag_pic && avr32_address_operand(operands[1], GET_MODE(operands[1])) )
  11999. + /* If we have an address operand then this function uses the pic register. */
  12000. + crtl->uses_pic_offset_table = 1;
  12001. + })
  12002. +
  12003. +
  12004. +(define_insn "mov<mode>_internal"
  12005. + [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "=r, r, r,r,r,Q,r")
  12006. + (match_operand:MOVM 1 "avr32_non_rmw_general_operand" "rKs08,Ks21,J,n,Q,r,W"))]
  12007. + "(register_operand (operands[0], <MODE>mode)
  12008. + || register_operand (operands[1], <MODE>mode))
  12009. + && !avr32_rmw_memory_operand (operands[0], <MODE>mode)
  12010. + && !avr32_rmw_memory_operand (operands[1], <MODE>mode)"
  12011. + {
  12012. + switch (which_alternative) {
  12013. + case 0:
  12014. + case 1: return "mov\t%0, %1";
  12015. + case 2:
  12016. + if ( TARGET_V2_INSNS )
  12017. + return "movh\t%0, hi(%1)";
  12018. + /* Fallthrough */
  12019. + case 3: return "mov\t%0, lo(%1)\;orh\t%0,hi(%1)";
  12020. + case 4:
  12021. + if ( (REG_P(XEXP(operands[1], 0))
  12022. + && REGNO(XEXP(operands[1], 0)) == SP_REGNUM)
  12023. + || (GET_CODE(XEXP(operands[1], 0)) == PLUS
  12024. + && REGNO(XEXP(XEXP(operands[1], 0), 0)) == SP_REGNUM
  12025. + && GET_CODE(XEXP(XEXP(operands[1], 0), 1)) == CONST_INT
  12026. + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) % 4 == 0
  12027. + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) <= 0x1FC) )
  12028. + return "lddsp\t%0, %1";
  12029. + else if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])) )
  12030. + return "lddpc\t%0, %1";
  12031. + else
  12032. + return "ld.w\t%0, %1";
  12033. + case 5:
  12034. + if ( (REG_P(XEXP(operands[0], 0))
  12035. + && REGNO(XEXP(operands[0], 0)) == SP_REGNUM)
  12036. + || (GET_CODE(XEXP(operands[0], 0)) == PLUS
  12037. + && REGNO(XEXP(XEXP(operands[0], 0), 0)) == SP_REGNUM
  12038. + && GET_CODE(XEXP(XEXP(operands[0], 0), 1)) == CONST_INT
  12039. + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) % 4 == 0
  12040. + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) <= 0x1FC) )
  12041. + return "stdsp\t%0, %1";
  12042. + else
  12043. + return "st.w\t%0, %1";
  12044. + case 6:
  12045. + if ( TARGET_HAS_ASM_ADDR_PSEUDOS )
  12046. + return "lda.w\t%0, %1";
  12047. + else
  12048. + return "ld.w\t%0, r6[%1@got]";
  12049. + default:
  12050. + abort();
  12051. + }
  12052. + }
  12053. +
  12054. + [(set_attr "length" "2,4,4,8,4,4,8")
  12055. + (set_attr "type" "alu,alu,alu,alu2,load,store,load")
  12056. + (set_attr "cc" "none,none,set_z_if_not_v2,set_z,none,none,clobber")])
  12057. +
  12058. +
  12059. +(define_expand "reload_out_rmw_memory_operand"
  12060. + [(set (match_operand:SI 2 "register_operand" "=r")
  12061. + (match_operand:SI 0 "address_operand" ""))
  12062. + (set (mem:SI (match_dup 2))
  12063. + (match_operand:SI 1 "register_operand" ""))]
  12064. + ""
  12065. + {
  12066. + operands[0] = XEXP(operands[0], 0);
  12067. + }
  12068. +)
  12069. +
  12070. +(define_expand "reload_in_rmw_memory_operand"
  12071. + [(set (match_operand:SI 2 "register_operand" "=r")
  12072. + (match_operand:SI 1 "address_operand" ""))
  12073. + (set (match_operand:SI 0 "register_operand" "")
  12074. + (mem:SI (match_dup 2)))]
  12075. + ""
  12076. + {
  12077. + operands[1] = XEXP(operands[1], 0);
  12078. + }
  12079. +)
  12080. +
  12081. +
  12082. +;; These instructions are for loading constants which cannot be loaded
  12083. +;; directly from the constant pool because the offset is too large
  12084. +;; high and lo_sum are used even tough for our case it should be
  12085. +;; low and high sum :-)
  12086. +(define_insn "mov_symbol_lo"
  12087. + [(set (match_operand:SI 0 "register_operand" "=r")
  12088. + (high:SI (match_operand:SI 1 "immediate_operand" "i" )))]
  12089. + ""
  12090. + "mov\t%0, lo(%1)"
  12091. + [(set_attr "type" "alu")
  12092. + (set_attr "length" "4")]
  12093. +)
  12094. +
  12095. +(define_insn "add_symbol_hi"
  12096. + [(set (match_operand:SI 0 "register_operand" "=r")
  12097. + (lo_sum:SI (match_dup 0)
  12098. + (match_operand:SI 1 "immediate_operand" "i" )))]
  12099. + ""
  12100. + "orh\t%0, hi(%1)"
  12101. + [(set_attr "type" "alu")
  12102. + (set_attr "length" "4")]
  12103. +)
  12104. +
  12105. +
  12106. +
  12107. +;; When generating pic, we need to load the symbol offset into a register.
  12108. +;; So that the optimizer does not confuse this with a normal symbol load
  12109. +;; we use an unspec. The offset will be loaded from a constant pool entry,
  12110. +;; since that is the only type of relocation we can use.
  12111. +(define_insn "pic_load_addr"
  12112. + [(set (match_operand:SI 0 "register_operand" "=r")
  12113. + (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC_SYM))]
  12114. + "flag_pic && CONSTANT_POOL_ADDRESS_P(XEXP(operands[1], 0))"
  12115. + "lddpc\t%0, %1"
  12116. + [(set_attr "type" "load")
  12117. + (set_attr "length" "4")]
  12118. +)
  12119. +
  12120. +(define_insn "pic_compute_got_from_pc"
  12121. + [(set (match_operand:SI 0 "register_operand" "+r")
  12122. + (unspec:SI [(minus:SI (pc)
  12123. + (match_dup 0))] UNSPEC_PIC_BASE))
  12124. + (use (label_ref (match_operand 1 "" "")))]
  12125. + "flag_pic"
  12126. + {
  12127. + (*targetm.asm_out.internal_label) (asm_out_file, "L",
  12128. + CODE_LABEL_NUMBER (operands[1]));
  12129. + return \"rsub\t%0, pc\";
  12130. + }
  12131. + [(set_attr "cc" "clobber")
  12132. + (set_attr "length" "2")]
  12133. +)
  12134. +
  12135. +;;== long long int - 64 bits ==================================================
  12136. +
  12137. +(define_expand "movdi"
  12138. + [(set (match_operand:DI 0 "nonimmediate_operand" "")
  12139. + (match_operand:DI 1 "general_operand" ""))]
  12140. + ""
  12141. + {
  12142. +
  12143. + /* One of the ops has to be in a register. */
  12144. + if (GET_CODE (operands[0]) != REG)
  12145. + operands[1] = force_reg (DImode, operands[1]);
  12146. +
  12147. + })
  12148. +
  12149. +
  12150. +(define_insn_and_split "*movdi_internal"
  12151. + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r, r, r,r,r,m")
  12152. + (match_operand:DI 1 "general_operand" "r, Ks08,Ks21,G,n,m,r"))]
  12153. + "register_operand (operands[0], DImode)
  12154. + || register_operand (operands[1], DImode)"
  12155. + {
  12156. + switch (which_alternative ){
  12157. + case 0:
  12158. + case 1:
  12159. + case 2:
  12160. + case 3:
  12161. + case 4:
  12162. + return "#";
  12163. + case 5:
  12164. + if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])))
  12165. + return "ld.d\t%0, pc[%1 - .]";
  12166. + else
  12167. + return "ld.d\t%0, %1";
  12168. + case 6:
  12169. + return "st.d\t%0, %1";
  12170. + default:
  12171. + abort();
  12172. + }
  12173. + }
  12174. +;; Lets split all reg->reg or imm->reg transfers into two SImode transfers
  12175. + "reload_completed &&
  12176. + (REG_P (operands[0]) &&
  12177. + (REG_P (operands[1])
  12178. + || GET_CODE (operands[1]) == CONST_INT
  12179. + || GET_CODE (operands[1]) == CONST_DOUBLE))"
  12180. + [(set (match_dup 0) (match_dup 1))
  12181. + (set (match_dup 2) (match_dup 3))]
  12182. + {
  12183. + operands[2] = gen_highpart (SImode, operands[0]);
  12184. + operands[0] = gen_lowpart (SImode, operands[0]);
  12185. + if ( REG_P(operands[1]) ){
  12186. + operands[3] = gen_highpart(SImode, operands[1]);
  12187. + operands[1] = gen_lowpart(SImode, operands[1]);
  12188. + } else if ( GET_CODE(operands[1]) == CONST_DOUBLE
  12189. + || GET_CODE(operands[1]) == CONST_INT ){
  12190. + rtx split_const[2];
  12191. + avr32_split_const_expr (DImode, SImode, operands[1], split_const);
  12192. + operands[3] = split_const[1];
  12193. + operands[1] = split_const[0];
  12194. + } else {
  12195. + internal_error("Illegal operand[1] for movdi split!");
  12196. + }
  12197. + }
  12198. +
  12199. + [(set_attr "length" "*,*,*,*,*,4,4")
  12200. + (set_attr "type" "*,*,*,*,*,load2,store2")
  12201. + (set_attr "cc" "*,*,*,*,*,none,none")])
  12202. +
  12203. +
  12204. +;;== 128 bits ==================================================
  12205. +(define_expand "movti"
  12206. + [(set (match_operand:TI 0 "nonimmediate_operand" "")
  12207. + (match_operand:TI 1 "nonimmediate_operand" ""))]
  12208. + "TARGET_ARCH_AP"
  12209. + {
  12210. +
  12211. + /* One of the ops has to be in a register. */
  12212. + if (GET_CODE (operands[0]) != REG)
  12213. + operands[1] = force_reg (TImode, operands[1]);
  12214. +
  12215. + /* We must fix any pre_dec for loads and post_inc stores */
  12216. + if ( GET_CODE (operands[0]) == MEM
  12217. + && GET_CODE (XEXP(operands[0],0)) == POST_INC ){
  12218. + emit_move_insn(gen_rtx_MEM(TImode, XEXP(XEXP(operands[0],0),0)), operands[1]);
  12219. + emit_insn(gen_addsi3(XEXP(XEXP(operands[0],0),0), XEXP(XEXP(operands[0],0),0), GEN_INT(GET_MODE_SIZE(TImode))));
  12220. + DONE;
  12221. + }
  12222. +
  12223. + if ( GET_CODE (operands[1]) == MEM
  12224. + && GET_CODE (XEXP(operands[1],0)) == PRE_DEC ){
  12225. + emit_insn(gen_addsi3(XEXP(XEXP(operands[1],0),0), XEXP(XEXP(operands[1],0),0), GEN_INT(-GET_MODE_SIZE(TImode))));
  12226. + emit_move_insn(operands[0], gen_rtx_MEM(TImode, XEXP(XEXP(operands[1],0),0)));
  12227. + DONE;
  12228. + }
  12229. + })
  12230. +
  12231. +
  12232. +(define_insn_and_split "*movti_internal"
  12233. + [(set (match_operand:TI 0 "avr32_movti_dst_operand" "=r,&r, r, <RKu00,r,r")
  12234. + (match_operand:TI 1 "avr32_movti_src_operand" " r,RKu00>,RKu00,r, n,T"))]
  12235. + "(register_operand (operands[0], TImode)
  12236. + || register_operand (operands[1], TImode))"
  12237. + {
  12238. + switch (which_alternative ){
  12239. + case 0:
  12240. + case 2:
  12241. + case 4:
  12242. + return "#";
  12243. + case 1:
  12244. + return "ldm\t%p1, %0";
  12245. + case 3:
  12246. + return "stm\t%p0, %1";
  12247. + case 5:
  12248. + return "ld.d\t%U0, pc[%1 - .]\;ld.d\t%B0, pc[%1 - . + 8]";
  12249. + }
  12250. + }
  12251. +
  12252. + "reload_completed &&
  12253. + (REG_P (operands[0]) &&
  12254. + (REG_P (operands[1])
  12255. + /* If this is a load from the constant pool we split it into
  12256. + two double loads. */
  12257. + || (GET_CODE (operands[1]) == MEM
  12258. + && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
  12259. + && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
  12260. + /* If this is a load where the pointer register is a part
  12261. + of the register list, we must split it into two double
  12262. + loads in order for it to be exception safe. */
  12263. + || (GET_CODE (operands[1]) == MEM
  12264. + && register_operand (XEXP (operands[1], 0), SImode)
  12265. + && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
  12266. + || GET_CODE (operands[1]) == CONST_INT
  12267. + || GET_CODE (operands[1]) == CONST_DOUBLE))"
  12268. + [(set (match_dup 0) (match_dup 1))
  12269. + (set (match_dup 2) (match_dup 3))]
  12270. + {
  12271. + operands[2] = simplify_gen_subreg ( DImode, operands[0],
  12272. + TImode, 0 );
  12273. + operands[0] = simplify_gen_subreg ( DImode, operands[0],
  12274. + TImode, 8 );
  12275. + if ( REG_P(operands[1]) ){
  12276. + operands[3] = simplify_gen_subreg ( DImode, operands[1],
  12277. + TImode, 0 );
  12278. + operands[1] = simplify_gen_subreg ( DImode, operands[1],
  12279. + TImode, 8 );
  12280. + } else if ( GET_CODE(operands[1]) == CONST_DOUBLE
  12281. + || GET_CODE(operands[1]) == CONST_INT ){
  12282. + rtx split_const[2];
  12283. + avr32_split_const_expr (TImode, DImode, operands[1], split_const);
  12284. + operands[3] = split_const[1];
  12285. + operands[1] = split_const[0];
  12286. + } else if (avr32_const_pool_ref_operand (operands[1], GET_MODE(operands[1]))){
  12287. + rtx split_const[2];
  12288. + rtx cop = avoid_constant_pool_reference (operands[1]);
  12289. + if (operands[1] == cop)
  12290. + cop = get_pool_constant (XEXP (operands[1], 0));
  12291. + avr32_split_const_expr (TImode, DImode, cop, split_const);
  12292. + operands[3] = force_const_mem (DImode, split_const[1]);
  12293. + operands[1] = force_const_mem (DImode, split_const[0]);
  12294. + } else {
  12295. + rtx ptr_reg = XEXP (operands[1], 0);
  12296. + operands[1] = gen_rtx_MEM (DImode,
  12297. + gen_rtx_PLUS ( SImode,
  12298. + ptr_reg,
  12299. + GEN_INT (8) ));
  12300. + operands[3] = gen_rtx_MEM (DImode,
  12301. + ptr_reg);
  12302. +
  12303. + /* Check if the first load will clobber the pointer.
  12304. + If so, we must switch the order of the operations. */
  12305. + if ( reg_overlap_mentioned_p (operands[0], ptr_reg) )
  12306. + {
  12307. + /* We need to switch the order of the operations
  12308. + so that the pointer register does not get clobbered
  12309. + after the first double word load. */
  12310. + rtx tmp;
  12311. + tmp = operands[0];
  12312. + operands[0] = operands[2];
  12313. + operands[2] = tmp;
  12314. + tmp = operands[1];
  12315. + operands[1] = operands[3];
  12316. + operands[3] = tmp;
  12317. + }
  12318. +
  12319. +
  12320. + }
  12321. + }
  12322. + [(set_attr "length" "*,*,4,4,*,8")
  12323. + (set_attr "type" "*,*,load4,store4,*,load4")])
  12324. +
  12325. +
  12326. +;;== float - 32 bits ==========================================================
  12327. +(define_expand "movsf"
  12328. + [(set (match_operand:SF 0 "nonimmediate_operand" "")
  12329. + (match_operand:SF 1 "general_operand" ""))]
  12330. + ""
  12331. + {
  12332. +
  12333. +
  12334. + /* One of the ops has to be in a register. */
  12335. + if (GET_CODE (operands[0]) != REG)
  12336. + operands[1] = force_reg (SFmode, operands[1]);
  12337. +
  12338. + })
  12339. +
  12340. +(define_insn "*movsf_internal"
  12341. + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m")
  12342. + (match_operand:SF 1 "general_operand" "r, G,F,m,r"))]
  12343. + "(register_operand (operands[0], SFmode)
  12344. + || register_operand (operands[1], SFmode))"
  12345. + {
  12346. + switch (which_alternative) {
  12347. + case 0:
  12348. + case 1: return "mov\t%0, %1";
  12349. + case 2:
  12350. + {
  12351. + HOST_WIDE_INT target_float[2];
  12352. + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode);
  12353. + if ( TARGET_V2_INSNS
  12354. + && avr32_hi16_immediate_operand (GEN_INT (target_float[0]), VOIDmode) )
  12355. + return "movh\t%0, hi(%1)";
  12356. + else
  12357. + return "mov\t%0, lo(%1)\;orh\t%0, hi(%1)";
  12358. + }
  12359. + case 3:
  12360. + if ( (REG_P(XEXP(operands[1], 0))
  12361. + && REGNO(XEXP(operands[1], 0)) == SP_REGNUM)
  12362. + || (GET_CODE(XEXP(operands[1], 0)) == PLUS
  12363. + && REGNO(XEXP(XEXP(operands[1], 0), 0)) == SP_REGNUM
  12364. + && GET_CODE(XEXP(XEXP(operands[1], 0), 1)) == CONST_INT
  12365. + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) % 4 == 0
  12366. + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) <= 0x1FC) )
  12367. + return "lddsp\t%0, %1";
  12368. + else if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])) )
  12369. + return "lddpc\t%0, %1";
  12370. + else
  12371. + return "ld.w\t%0, %1";
  12372. + case 4:
  12373. + if ( (REG_P(XEXP(operands[0], 0))
  12374. + && REGNO(XEXP(operands[0], 0)) == SP_REGNUM)
  12375. + || (GET_CODE(XEXP(operands[0], 0)) == PLUS
  12376. + && REGNO(XEXP(XEXP(operands[0], 0), 0)) == SP_REGNUM
  12377. + && GET_CODE(XEXP(XEXP(operands[0], 0), 1)) == CONST_INT
  12378. + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) % 4 == 0
  12379. + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) <= 0x1FC) )
  12380. + return "stdsp\t%0, %1";
  12381. + else
  12382. + return "st.w\t%0, %1";
  12383. + default:
  12384. + abort();
  12385. + }
  12386. + }
  12387. +
  12388. + [(set_attr "length" "2,4,8,4,4")
  12389. + (set_attr "type" "alu,alu,alu2,load,store")
  12390. + (set_attr "cc" "none,none,clobber,none,none")])
  12391. +
  12392. +
  12393. +
  12394. +;;== double - 64 bits =========================================================
  12395. +(define_expand "movdf"
  12396. + [(set (match_operand:DF 0 "nonimmediate_operand" "")
  12397. + (match_operand:DF 1 "general_operand" ""))]
  12398. + ""
  12399. + {
  12400. + /* One of the ops has to be in a register. */
  12401. + if (GET_CODE (operands[0]) != REG){
  12402. + operands[1] = force_reg (DFmode, operands[1]);
  12403. + }
  12404. + })
  12405. +
  12406. +
  12407. +(define_insn_and_split "*movdf_internal"
  12408. + [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,r,r,m")
  12409. + (match_operand:DF 1 "general_operand" " r,G,F,m,r"))]
  12410. + "(register_operand (operands[0], DFmode)
  12411. + || register_operand (operands[1], DFmode))"
  12412. + {
  12413. + switch (which_alternative ){
  12414. + case 0:
  12415. + case 1:
  12416. + case 2:
  12417. + return "#";
  12418. + case 3:
  12419. + if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])))
  12420. + return "ld.d\t%0, pc[%1 - .]";
  12421. + else
  12422. + return "ld.d\t%0, %1";
  12423. + case 4:
  12424. + return "st.d\t%0, %1";
  12425. + default:
  12426. + abort();
  12427. + }
  12428. + }
  12429. + "reload_completed
  12430. + && (REG_P (operands[0])
  12431. + && (REG_P (operands[1])
  12432. + || GET_CODE (operands[1]) == CONST_DOUBLE))"
  12433. + [(set (match_dup 0) (match_dup 1))
  12434. + (set (match_dup 2) (match_dup 3))]
  12435. + "
  12436. + {
  12437. + operands[2] = gen_highpart (SImode, operands[0]);
  12438. + operands[0] = gen_lowpart (SImode, operands[0]);
  12439. + operands[3] = gen_highpart(SImode, operands[1]);
  12440. + operands[1] = gen_lowpart(SImode, operands[1]);
  12441. + }
  12442. + "
  12443. +
  12444. + [(set_attr "length" "*,*,*,4,4")
  12445. + (set_attr "type" "*,*,*,load2,store2")
  12446. + (set_attr "cc" "*,*,*,none,none")])
  12447. +
  12448. +
  12449. +;;=============================================================================
  12450. +;; Conditional Moves
  12451. +;;=============================================================================
  12452. +(define_insn "ld<mode>_predicable"
  12453. + [(set (match_operand:MOVCC 0 "register_operand" "=r")
  12454. + (match_operand:MOVCC 1 "avr32_non_rmw_memory_operand" "<MOVCC:pred_mem_constraint>"))]
  12455. + "TARGET_V2_INSNS"
  12456. + "ld<MOVCC:load_postfix>%?\t%0, %1"
  12457. + [(set_attr "length" "4")
  12458. + (set_attr "cc" "cmp_cond_insn")
  12459. + (set_attr "type" "load")
  12460. + (set_attr "predicable" "yes")]
  12461. +)
  12462. +
  12463. +
  12464. +(define_insn "st<mode>_predicable"
  12465. + [(set (match_operand:MOVCC 0 "avr32_non_rmw_memory_operand" "=<MOVCC:pred_mem_constraint>")
  12466. + (match_operand:MOVCC 1 "register_operand" "r"))]
  12467. + "TARGET_V2_INSNS"
  12468. + "st<MOVCC:store_postfix>%?\t%0, %1"
  12469. + [(set_attr "length" "4")
  12470. + (set_attr "cc" "cmp_cond_insn")
  12471. + (set_attr "type" "store")
  12472. + (set_attr "predicable" "yes")]
  12473. +)
  12474. +
  12475. +(define_insn "mov<mode>_predicable"
  12476. + [(set (match_operand:MOVCC 0 "register_operand" "=r")
  12477. + (match_operand:MOVCC 1 "avr32_cond_register_immediate_operand" "rKs08"))]
  12478. + ""
  12479. + "mov%?\t%0, %1"
  12480. + [(set_attr "length" "4")
  12481. + (set_attr "cc" "cmp_cond_insn")
  12482. + (set_attr "type" "alu")
  12483. + (set_attr "predicable" "yes")]
  12484. +)
  12485. +
  12486. +
  12487. +;;=============================================================================
  12488. +;; Move chunks of memory
  12489. +;;=============================================================================
  12490. +
  12491. +(define_expand "movmemsi"
  12492. + [(match_operand:BLK 0 "general_operand" "")
  12493. + (match_operand:BLK 1 "general_operand" "")
  12494. + (match_operand:SI 2 "const_int_operand" "")
  12495. + (match_operand:SI 3 "const_int_operand" "")]
  12496. + ""
  12497. + "
  12498. + if (avr32_gen_movmemsi (operands))
  12499. + DONE;
  12500. + FAIL;
  12501. + "
  12502. + )
  12503. +
  12504. +
  12505. +
  12506. +
  12507. +;;=============================================================================
  12508. +;; Bit field instructions
  12509. +;;-----------------------------------------------------------------------------
  12510. +;; Instructions to insert or extract bit-fields
  12511. +;;=============================================================================
  12512. +
  12513. +(define_insn "insv"
  12514. + [ (set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
  12515. + (match_operand:SI 1 "immediate_operand" "Ku05")
  12516. + (match_operand:SI 2 "immediate_operand" "Ku05"))
  12517. + (match_operand 3 "register_operand" "r"))]
  12518. + ""
  12519. + "bfins\t%0, %3, %2, %1"
  12520. + [(set_attr "type" "alu")
  12521. + (set_attr "length" "4")
  12522. + (set_attr "cc" "set_ncz")])
  12523. +
  12524. +
  12525. +
  12526. +(define_expand "extv"
  12527. + [ (set (match_operand:SI 0 "register_operand" "")
  12528. + (sign_extract:SI (match_operand:SI 1 "register_operand" "")
  12529. + (match_operand:SI 2 "immediate_operand" "")
  12530. + (match_operand:SI 3 "immediate_operand" "")))]
  12531. + ""
  12532. + {
  12533. + if ( INTVAL(operands[2]) >= 32 )
  12534. + FAIL;
  12535. + }
  12536. +)
  12537. +
  12538. +(define_expand "extzv"
  12539. + [ (set (match_operand:SI 0 "register_operand" "")
  12540. + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
  12541. + (match_operand:SI 2 "immediate_operand" "")
  12542. + (match_operand:SI 3 "immediate_operand" "")))]
  12543. + ""
  12544. + {
  12545. + if ( INTVAL(operands[2]) >= 32 )
  12546. + FAIL;
  12547. + }
  12548. +)
  12549. +
  12550. +(define_insn "extv_internal"
  12551. + [ (set (match_operand:SI 0 "register_operand" "=r")
  12552. + (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
  12553. + (match_operand:SI 2 "immediate_operand" "Ku05")
  12554. + (match_operand:SI 3 "immediate_operand" "Ku05")))]
  12555. + "INTVAL(operands[2]) < 32"
  12556. + "bfexts\t%0, %1, %3, %2"
  12557. + [(set_attr "type" "alu")
  12558. + (set_attr "length" "4")
  12559. + (set_attr "cc" "set_ncz")])
  12560. +
  12561. +
  12562. +(define_insn "extzv_internal"
  12563. + [ (set (match_operand:SI 0 "register_operand" "=r")
  12564. + (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
  12565. + (match_operand:SI 2 "immediate_operand" "Ku05")
  12566. + (match_operand:SI 3 "immediate_operand" "Ku05")))]
  12567. + "INTVAL(operands[2]) < 32"
  12568. + "bfextu\t%0, %1, %3, %2"
  12569. + [(set_attr "type" "alu")
  12570. + (set_attr "length" "4")
  12571. + (set_attr "cc" "set_ncz")])
  12572. +
  12573. +
  12574. +
  12575. +;;=============================================================================
  12576. +;; Some peepholes for avoiding unnecessary cast instructions
  12577. +;; followed by bfins.
  12578. +;;-----------------------------------------------------------------------------
  12579. +
  12580. +(define_peephole2
  12581. + [(set (match_operand:SI 0 "register_operand" "")
  12582. + (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
  12583. + (set (zero_extract:SI (match_operand 2 "register_operand" "")
  12584. + (match_operand:SI 3 "immediate_operand" "")
  12585. + (match_operand:SI 4 "immediate_operand" ""))
  12586. + (match_dup 0))]
  12587. + "((peep2_reg_dead_p(2, operands[0]) &&
  12588. + (INTVAL(operands[3]) <= 8)))"
  12589. + [(set (zero_extract:SI (match_dup 2)
  12590. + (match_dup 3)
  12591. + (match_dup 4))
  12592. + (match_dup 1))]
  12593. + )
  12594. +
  12595. +(define_peephole2
  12596. + [(set (match_operand:SI 0 "register_operand" "")
  12597. + (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
  12598. + (set (zero_extract:SI (match_operand 2 "register_operand" "")
  12599. + (match_operand:SI 3 "immediate_operand" "")
  12600. + (match_operand:SI 4 "immediate_operand" ""))
  12601. + (match_dup 0))]
  12602. + "((peep2_reg_dead_p(2, operands[0]) &&
  12603. + (INTVAL(operands[3]) <= 16)))"
  12604. + [(set (zero_extract:SI (match_dup 2)
  12605. + (match_dup 3)
  12606. + (match_dup 4))
  12607. + (match_dup 1))]
  12608. + )
  12609. +
  12610. +;;=============================================================================
  12611. +;; push bytes
  12612. +;;-----------------------------------------------------------------------------
  12613. +;; Implements the push instruction
  12614. +;;=============================================================================
  12615. +(define_insn "pushm"
  12616. + [(set (mem:BLK (pre_dec:BLK (reg:SI SP_REGNUM)))
  12617. + (unspec:BLK [(match_operand 0 "const_int_operand" "")]
  12618. + UNSPEC_PUSHM))]
  12619. + ""
  12620. + {
  12621. + if (INTVAL(operands[0])) {
  12622. + return "pushm\t%r0";
  12623. + } else {
  12624. + return "";
  12625. + }
  12626. + }
  12627. + [(set_attr "type" "store")
  12628. + (set_attr "length" "2")
  12629. + (set_attr "cc" "none")])
  12630. +
  12631. +(define_insn "stm"
  12632. + [(unspec [(match_operand 0 "register_operand" "r")
  12633. + (match_operand 1 "const_int_operand" "")
  12634. + (match_operand 2 "const_int_operand" "")]
  12635. + UNSPEC_STM)]
  12636. + ""
  12637. + {
  12638. + if (INTVAL(operands[1])) {
  12639. + if (INTVAL(operands[2]) != 0)
  12640. + return "stm\t--%0, %s1";
  12641. + else
  12642. + return "stm\t%0, %s1";
  12643. + } else {
  12644. + return "";
  12645. + }
  12646. + }
  12647. + [(set_attr "type" "store")
  12648. + (set_attr "length" "4")
  12649. + (set_attr "cc" "none")])
  12650. +
  12651. +
  12652. +
  12653. +(define_insn "popm"
  12654. + [(unspec [(match_operand 0 "const_int_operand" "")]
  12655. + UNSPEC_POPM)]
  12656. + ""
  12657. + {
  12658. + if (INTVAL(operands[0])) {
  12659. + return "popm %r0";
  12660. + } else {
  12661. + return "";
  12662. + }
  12663. + }
  12664. + [(set_attr "type" "load")
  12665. + (set_attr "length" "2")])
  12666. +
  12667. +
  12668. +
  12669. +;;=============================================================================
  12670. +;; add
  12671. +;;-----------------------------------------------------------------------------
  12672. +;; Adds reg1 with reg2 and puts the result in reg0.
  12673. +;;=============================================================================
  12674. +(define_insn "add<mode>3"
  12675. + [(set (match_operand:INTM 0 "register_operand" "=r,r,r,r,r")
  12676. + (plus:INTM (match_operand:INTM 1 "register_operand" "%0,r,0,r,0")
  12677. + (match_operand:INTM 2 "avr32_add_operand" "r,r,Is08,Is16,Is21")))]
  12678. + ""
  12679. + "@
  12680. + add %0, %2
  12681. + add %0, %1, %2
  12682. + sub %0, %n2
  12683. + sub %0, %1, %n2
  12684. + sub %0, %n2"
  12685. +
  12686. + [(set_attr "length" "2,4,2,4,4")
  12687. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12688. +
  12689. +(define_insn "add<mode>3_lsl"
  12690. + [(set (match_operand:INTM 0 "register_operand" "=r")
  12691. + (plus:INTM (ashift:INTM (match_operand:INTM 1 "register_operand" "r")
  12692. + (match_operand:INTM 3 "avr32_add_shift_immediate_operand" "Ku02"))
  12693. + (match_operand:INTM 2 "register_operand" "r")))]
  12694. + ""
  12695. + "add %0, %2, %1 << %3"
  12696. + [(set_attr "length" "4")
  12697. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12698. +
  12699. +(define_insn "add<mode>3_lsl2"
  12700. + [(set (match_operand:INTM 0 "register_operand" "=r")
  12701. + (plus:INTM (match_operand:INTM 1 "register_operand" "r")
  12702. + (ashift:INTM (match_operand:INTM 2 "register_operand" "r")
  12703. + (match_operand:INTM 3 "avr32_add_shift_immediate_operand" "Ku02"))))]
  12704. + ""
  12705. + "add %0, %1, %2 << %3"
  12706. + [(set_attr "length" "4")
  12707. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12708. +
  12709. +
  12710. +(define_insn "add<mode>3_mul"
  12711. + [(set (match_operand:INTM 0 "register_operand" "=r")
  12712. + (plus:INTM (mult:INTM (match_operand:INTM 1 "register_operand" "r")
  12713. + (match_operand:INTM 3 "immediate_operand" "Ku04" ))
  12714. + (match_operand:INTM 2 "register_operand" "r")))]
  12715. + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) ||
  12716. + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)"
  12717. + "add %0, %2, %1 << %p3"
  12718. + [(set_attr "length" "4")
  12719. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12720. +
  12721. +(define_insn "add<mode>3_mul2"
  12722. + [(set (match_operand:INTM 0 "register_operand" "=r")
  12723. + (plus:INTM (match_operand:INTM 1 "register_operand" "r")
  12724. + (mult:INTM (match_operand:INTM 2 "register_operand" "r")
  12725. + (match_operand:INTM 3 "immediate_operand" "Ku04" ))))]
  12726. + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) ||
  12727. + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)"
  12728. + "add %0, %1, %2 << %p3"
  12729. + [(set_attr "length" "4")
  12730. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12731. +
  12732. +
  12733. +(define_peephole2
  12734. + [(set (match_operand:SI 0 "register_operand" "")
  12735. + (ashift:SI (match_operand:SI 1 "register_operand" "")
  12736. + (match_operand:SI 2 "immediate_operand" "")))
  12737. + (set (match_operand:SI 3 "register_operand" "")
  12738. + (plus:SI (match_dup 0)
  12739. + (match_operand:SI 4 "register_operand" "")))]
  12740. + "(peep2_reg_dead_p(2, operands[0]) &&
  12741. + (INTVAL(operands[2]) < 4 && INTVAL(operands[2]) > 0))"
  12742. + [(set (match_dup 3)
  12743. + (plus:SI (ashift:SI (match_dup 1)
  12744. + (match_dup 2))
  12745. + (match_dup 4)))]
  12746. + )
  12747. +
  12748. +(define_peephole2
  12749. + [(set (match_operand:SI 0 "register_operand" "")
  12750. + (ashift:SI (match_operand:SI 1 "register_operand" "")
  12751. + (match_operand:SI 2 "immediate_operand" "")))
  12752. + (set (match_operand:SI 3 "register_operand" "")
  12753. + (plus:SI (match_operand:SI 4 "register_operand" "")
  12754. + (match_dup 0)))]
  12755. + "(peep2_reg_dead_p(2, operands[0]) &&
  12756. + (INTVAL(operands[2]) < 4 && INTVAL(operands[2]) > 0))"
  12757. + [(set (match_dup 3)
  12758. + (plus:SI (ashift:SI (match_dup 1)
  12759. + (match_dup 2))
  12760. + (match_dup 4)))]
  12761. + )
  12762. +
  12763. +(define_insn "adddi3"
  12764. + [(set (match_operand:DI 0 "register_operand" "=r,r")
  12765. + (plus:DI (match_operand:DI 1 "register_operand" "%0,r")
  12766. + (match_operand:DI 2 "register_operand" "r,r")))]
  12767. + ""
  12768. + "@
  12769. + add %0, %2\;adc %m0, %m0, %m2
  12770. + add %0, %1, %2\;adc %m0, %m1, %m2"
  12771. + [(set_attr "length" "6,8")
  12772. + (set_attr "type" "alu2")
  12773. + (set_attr "cc" "set_vncz")])
  12774. +
  12775. +
  12776. +(define_insn "add<mode>_imm_predicable"
  12777. + [(set (match_operand:INTM 0 "register_operand" "+r")
  12778. + (plus:INTM (match_dup 0)
  12779. + (match_operand:INTM 1 "avr32_cond_immediate_operand" "%Is08")))]
  12780. + ""
  12781. + "sub%?\t%0, -%1"
  12782. + [(set_attr "length" "4")
  12783. + (set_attr "cc" "cmp_cond_insn")
  12784. + (set_attr "predicable" "yes")]
  12785. +)
  12786. +
  12787. +;;=============================================================================
  12788. +;; subtract
  12789. +;;-----------------------------------------------------------------------------
  12790. +;; Subtract reg2 or immediate value from reg0 and puts the result in reg0.
  12791. +;;=============================================================================
  12792. +
  12793. +(define_insn "sub<mode>3"
  12794. + [(set (match_operand:INTM 0 "general_operand" "=r,r,r,r,r,r,r")
  12795. + (minus:INTM (match_operand:INTM 1 "register_const_int_operand" "0,r,0,r,0,r,Ks08")
  12796. + (match_operand:INTM 2 "register_const_int_operand" "r,r,Ks08,Ks16,Ks21,0,r")))]
  12797. + ""
  12798. + "@
  12799. + sub %0, %2
  12800. + sub %0, %1, %2
  12801. + sub %0, %2
  12802. + sub %0, %1, %2
  12803. + sub %0, %2
  12804. + rsub %0, %1
  12805. + rsub %0, %2, %1"
  12806. + [(set_attr "length" "2,4,2,4,4,2,4")
  12807. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12808. +
  12809. +(define_insn "*sub<mode>3_mul"
  12810. + [(set (match_operand:INTM 0 "register_operand" "=r")
  12811. + (minus:INTM (match_operand:INTM 1 "register_operand" "r")
  12812. + (mult:INTM (match_operand:INTM 2 "register_operand" "r")
  12813. + (match_operand:SI 3 "immediate_operand" "Ku04" ))))]
  12814. + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) ||
  12815. + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)"
  12816. + "sub %0, %1, %2 << %p3"
  12817. + [(set_attr "length" "4")
  12818. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12819. +
  12820. +(define_insn "*sub<mode>3_lsl"
  12821. + [(set (match_operand:INTM 0 "register_operand" "=r")
  12822. + (minus:INTM (match_operand:INTM 1 "register_operand" "r")
  12823. + (ashift:INTM (match_operand:INTM 2 "register_operand" "r")
  12824. + (match_operand:SI 3 "avr32_add_shift_immediate_operand" "Ku02"))))]
  12825. + ""
  12826. + "sub %0, %1, %2 << %3"
  12827. + [(set_attr "length" "4")
  12828. + (set_attr "cc" "<INTM:alu_cc_attr>")])
  12829. +
  12830. +
  12831. +(define_insn "subdi3"
  12832. + [(set (match_operand:DI 0 "register_operand" "=r,r")
  12833. + (minus:DI (match_operand:DI 1 "register_operand" "%0,r")
  12834. + (match_operand:DI 2 "register_operand" "r,r")))]
  12835. + ""
  12836. + "@
  12837. + sub %0, %2\;sbc %m0, %m0, %m2
  12838. + sub %0, %1, %2\;sbc %m0, %m1, %m2"
  12839. + [(set_attr "length" "6,8")
  12840. + (set_attr "type" "alu2")
  12841. + (set_attr "cc" "set_vncz")])
  12842. +
  12843. +
  12844. +(define_insn "sub<mode>_imm_predicable"
  12845. + [(set (match_operand:INTM 0 "register_operand" "+r")
  12846. + (minus:INTM (match_dup 0)
  12847. + (match_operand:INTM 1 "avr32_cond_immediate_operand" "Ks08")))]
  12848. + ""
  12849. + "sub%?\t%0, %1"
  12850. + [(set_attr "length" "4")
  12851. + (set_attr "cc" "cmp_cond_insn")
  12852. + (set_attr "predicable" "yes")])
  12853. +
  12854. +(define_insn "rsub<mode>_imm_predicable"
  12855. + [(set (match_operand:INTM 0 "register_operand" "+r")
  12856. + (minus:INTM (match_operand:INTM 1 "avr32_cond_immediate_operand" "Ks08")
  12857. + (match_dup 0)))]
  12858. + ""
  12859. + "rsub%?\t%0, %1"
  12860. + [(set_attr "length" "4")
  12861. + (set_attr "cc" "cmp_cond_insn")
  12862. + (set_attr "predicable" "yes")])
  12863. +
  12864. +;;=============================================================================
  12865. +;; multiply
  12866. +;;-----------------------------------------------------------------------------
  12867. +;; Multiply op1 and op2 and put the value in op0.
  12868. +;;=============================================================================
  12869. +
  12870. +
  12871. +(define_insn "mulqi3"
  12872. + [(set (match_operand:QI 0 "register_operand" "=r,r,r")
  12873. + (mult:QI (match_operand:QI 1 "register_operand" "%0,r,r")
  12874. + (match_operand:QI 2 "avr32_mul_operand" "r,r,Ks08")))]
  12875. + "!TARGET_NO_MUL_INSNS"
  12876. + {
  12877. + switch (which_alternative){
  12878. + case 0:
  12879. + return "mul %0, %2";
  12880. + case 1:
  12881. + return "mul %0, %1, %2";
  12882. + case 2:
  12883. + return "mul %0, %1, %2";
  12884. + default:
  12885. + gcc_unreachable();
  12886. + }
  12887. + }
  12888. + [(set_attr "type" "mulww_w,mulww_w,mulwh")
  12889. + (set_attr "length" "2,4,4")
  12890. + (set_attr "cc" "none")])
  12891. +
  12892. +(define_insn "mulsi3"
  12893. + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
  12894. + (mult:SI (match_operand:SI 1 "register_operand" "%0,r,r")
  12895. + (match_operand:SI 2 "avr32_mul_operand" "r,r,Ks08")))]
  12896. + "!TARGET_NO_MUL_INSNS"
  12897. + {
  12898. + switch (which_alternative){
  12899. + case 0:
  12900. + return "mul %0, %2";
  12901. + case 1:
  12902. + return "mul %0, %1, %2";
  12903. + case 2:
  12904. + return "mul %0, %1, %2";
  12905. + default:
  12906. + gcc_unreachable();
  12907. + }
  12908. + }
  12909. + [(set_attr "type" "mulww_w,mulww_w,mulwh")
  12910. + (set_attr "length" "2,4,4")
  12911. + (set_attr "cc" "none")])
  12912. +
  12913. +
  12914. +(define_insn "mulhisi3"
  12915. + [(set (match_operand:SI 0 "register_operand" "=r")
  12916. + (mult:SI
  12917. + (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
  12918. + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
  12919. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  12920. + "mulhh.w %0, %1:b, %2:b"
  12921. + [(set_attr "type" "mulhh")
  12922. + (set_attr "length" "4")
  12923. + (set_attr "cc" "none")])
  12924. +
  12925. +(define_peephole2
  12926. + [(match_scratch:DI 6 "r")
  12927. + (set (match_operand:SI 0 "register_operand" "")
  12928. + (mult:SI
  12929. + (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
  12930. + (sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
  12931. + (set (match_operand:SI 3 "register_operand" "")
  12932. + (ashiftrt:SI (match_dup 0)
  12933. + (const_int 16)))]
  12934. + "!TARGET_NO_MUL_INSNS && TARGET_DSP
  12935. + && (peep2_reg_dead_p(1, operands[0]) || (REGNO(operands[0]) == REGNO(operands[3])))"
  12936. + [(set (match_dup 4) (sign_extend:SI (match_dup 1)))
  12937. + (set (match_dup 6)
  12938. + (ashift:DI (mult:DI (sign_extend:DI (match_dup 4))
  12939. + (sign_extend:DI (match_dup 2)))
  12940. + (const_int 16)))
  12941. + (set (match_dup 3) (match_dup 5))]
  12942. +
  12943. + "{
  12944. + operands[4] = gen_rtx_REG(SImode, REGNO(operands[1]));
  12945. + operands[5] = gen_highpart (SImode, operands[4]);
  12946. + }"
  12947. + )
  12948. +
  12949. +(define_insn "mulnhisi3"
  12950. + [(set (match_operand:SI 0 "register_operand" "=r")
  12951. + (mult:SI
  12952. + (sign_extend:SI (neg:HI (match_operand:HI 1 "register_operand" "r")))
  12953. + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
  12954. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  12955. + "mulnhh.w %0, %1:b, %2:b"
  12956. + [(set_attr "type" "mulhh")
  12957. + (set_attr "length" "4")
  12958. + (set_attr "cc" "none")])
  12959. +
  12960. +(define_insn "machisi3"
  12961. + [(set (match_operand:SI 0 "register_operand" "+r")
  12962. + (plus:SI (mult:SI
  12963. + (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
  12964. + (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))
  12965. + (match_dup 0)))]
  12966. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  12967. + "machh.w %0, %1:b, %2:b"
  12968. + [(set_attr "type" "machh_w")
  12969. + (set_attr "length" "4")
  12970. + (set_attr "cc" "none")])
  12971. +
  12972. +
  12973. +
  12974. +(define_insn "mulsidi3"
  12975. + [(set (match_operand:DI 0 "register_operand" "=r")
  12976. + (mult:DI
  12977. + (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
  12978. + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
  12979. + "!TARGET_NO_MUL_INSNS"
  12980. + "muls.d %0, %1, %2"
  12981. + [(set_attr "type" "mulww_d")
  12982. + (set_attr "length" "4")
  12983. + (set_attr "cc" "none")])
  12984. +
  12985. +(define_insn "umulsidi3"
  12986. + [(set (match_operand:DI 0 "register_operand" "=r")
  12987. + (mult:DI
  12988. + (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
  12989. + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
  12990. + "!TARGET_NO_MUL_INSNS"
  12991. + "mulu.d %0, %1, %2"
  12992. + [(set_attr "type" "mulww_d")
  12993. + (set_attr "length" "4")
  12994. + (set_attr "cc" "none")])
  12995. +
  12996. +(define_insn "*mulaccsi3"
  12997. + [(set (match_operand:SI 0 "register_operand" "+r")
  12998. + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r")
  12999. + (match_operand:SI 2 "register_operand" "r"))
  13000. + (match_dup 0)))]
  13001. + "!TARGET_NO_MUL_INSNS"
  13002. + "mac %0, %1, %2"
  13003. + [(set_attr "type" "macww_w")
  13004. + (set_attr "length" "4")
  13005. + (set_attr "cc" "none")])
  13006. +
  13007. +(define_insn "*mulaccsidi3"
  13008. + [(set (match_operand:DI 0 "register_operand" "+r")
  13009. + (plus:DI (mult:DI
  13010. + (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
  13011. + (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
  13012. + (match_dup 0)))]
  13013. + "!TARGET_NO_MUL_INSNS"
  13014. + "macs.d %0, %1, %2"
  13015. + [(set_attr "type" "macww_d")
  13016. + (set_attr "length" "4")
  13017. + (set_attr "cc" "none")])
  13018. +
  13019. +(define_insn "*umulaccsidi3"
  13020. + [(set (match_operand:DI 0 "register_operand" "+r")
  13021. + (plus:DI (mult:DI
  13022. + (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
  13023. + (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
  13024. + (match_dup 0)))]
  13025. + "!TARGET_NO_MUL_INSNS"
  13026. + "macu.d %0, %1, %2"
  13027. + [(set_attr "type" "macww_d")
  13028. + (set_attr "length" "4")
  13029. + (set_attr "cc" "none")])
  13030. +
  13031. +
  13032. +
  13033. +;; Try to avoid Write-After-Write hazards for mul operations
  13034. +;; if it can be done
  13035. +(define_peephole2
  13036. + [(set (match_operand:SI 0 "register_operand" "")
  13037. + (mult:SI
  13038. + (sign_extend:SI (match_operand 1 "general_operand" ""))
  13039. + (sign_extend:SI (match_operand 2 "general_operand" ""))))
  13040. + (set (match_dup 0)
  13041. + (match_operator:SI 3 "alu_operator" [(match_dup 0)
  13042. + (match_operand 4 "general_operand" "")]))]
  13043. + "peep2_reg_dead_p(1, operands[2])"
  13044. + [(set (match_dup 5)
  13045. + (mult:SI
  13046. + (sign_extend:SI (match_dup 1))
  13047. + (sign_extend:SI (match_dup 2))))
  13048. + (set (match_dup 0)
  13049. + (match_op_dup 3 [(match_dup 5)
  13050. + (match_dup 4)]))]
  13051. + "{operands[5] = gen_rtx_REG(SImode, REGNO(operands[2]));}"
  13052. + )
  13053. +
  13054. +
  13055. +
  13056. +;;=============================================================================
  13057. +;; DSP instructions
  13058. +;;=============================================================================
  13059. +(define_insn "mulsathh_h"
  13060. + [(set (match_operand:HI 0 "register_operand" "=r")
  13061. + (ss_truncate:HI (ashiftrt:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
  13062. + (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))
  13063. + (const_int 15))))]
  13064. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13065. + "mulsathh.h\t%0, %1:b, %2:b"
  13066. + [(set_attr "length" "4")
  13067. + (set_attr "cc" "none")
  13068. + (set_attr "type" "mulhh")])
  13069. +
  13070. +(define_insn "mulsatrndhh_h"
  13071. + [(set (match_operand:HI 0 "register_operand" "=r")
  13072. + (ss_truncate:HI (ashiftrt:SI
  13073. + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
  13074. + (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))
  13075. + (const_int 1073741824))
  13076. + (const_int 15))))]
  13077. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13078. + "mulsatrndhh.h\t%0, %1:b, %2:b"
  13079. + [(set_attr "length" "4")
  13080. + (set_attr "cc" "none")
  13081. + (set_attr "type" "mulhh")])
  13082. +
  13083. +(define_insn "mulsathh_w"
  13084. + [(set (match_operand:SI 0 "register_operand" "=r")
  13085. + (ss_truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r"))
  13086. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
  13087. + (const_int 1))))]
  13088. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13089. + "mulsathh.w\t%0, %1:b, %2:b"
  13090. + [(set_attr "length" "4")
  13091. + (set_attr "cc" "none")
  13092. + (set_attr "type" "mulhh")])
  13093. +
  13094. +(define_insn "mulsatwh_w"
  13095. + [(set (match_operand:SI 0 "register_operand" "=r")
  13096. + (ss_truncate:SI (ashiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  13097. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
  13098. + (const_int 15))))]
  13099. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13100. + "mulsatwh.w\t%0, %1, %2:b"
  13101. + [(set_attr "length" "4")
  13102. + (set_attr "cc" "none")
  13103. + (set_attr "type" "mulwh")])
  13104. +
  13105. +(define_insn "mulsatrndwh_w"
  13106. + [(set (match_operand:SI 0 "register_operand" "=r")
  13107. + (ss_truncate:SI (ashiftrt:DI (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  13108. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
  13109. + (const_int 1073741824))
  13110. + (const_int 15))))]
  13111. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13112. + "mulsatrndwh.w\t%0, %1, %2:b"
  13113. + [(set_attr "length" "4")
  13114. + (set_attr "cc" "none")
  13115. + (set_attr "type" "mulwh")])
  13116. +
  13117. +(define_insn "macsathh_w"
  13118. + [(set (match_operand:SI 0 "register_operand" "+r")
  13119. + (plus:SI (match_dup 0)
  13120. + (ss_truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r"))
  13121. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
  13122. + (const_int 1)))))]
  13123. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13124. + "macsathh.w\t%0, %1:b, %2:b"
  13125. + [(set_attr "length" "4")
  13126. + (set_attr "cc" "none")
  13127. + (set_attr "type" "mulhh")])
  13128. +
  13129. +
  13130. +(define_insn "mulwh_d"
  13131. + [(set (match_operand:DI 0 "register_operand" "=r")
  13132. + (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
  13133. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
  13134. + (const_int 16)))]
  13135. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13136. + "mulwh.d\t%0, %1, %2:b"
  13137. + [(set_attr "length" "4")
  13138. + (set_attr "cc" "none")
  13139. + (set_attr "type" "mulwh")])
  13140. +
  13141. +
  13142. +(define_insn "mulnwh_d"
  13143. + [(set (match_operand:DI 0 "register_operand" "=r")
  13144. + (ashift:DI (mult:DI (not:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))
  13145. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
  13146. + (const_int 16)))]
  13147. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13148. + "mulnwh.d\t%0, %1, %2:b"
  13149. + [(set_attr "length" "4")
  13150. + (set_attr "cc" "none")
  13151. + (set_attr "type" "mulwh")])
  13152. +
  13153. +(define_insn "macwh_d"
  13154. + [(set (match_operand:DI 0 "register_operand" "+r")
  13155. + (plus:DI (match_dup 0)
  13156. + (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
  13157. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
  13158. + (const_int 16))))]
  13159. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13160. + "macwh.d\t%0, %1, %2:b"
  13161. + [(set_attr "length" "4")
  13162. + (set_attr "cc" "none")
  13163. + (set_attr "type" "mulwh")])
  13164. +
  13165. +(define_insn "machh_d"
  13166. + [(set (match_operand:DI 0 "register_operand" "+r")
  13167. + (plus:DI (match_dup 0)
  13168. + (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r"))
  13169. + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))))]
  13170. + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
  13171. + "machh.d\t%0, %1:b, %2:b"
  13172. + [(set_attr "length" "4")
  13173. + (set_attr "cc" "none")
  13174. + (set_attr "type" "mulwh")])
  13175. +
  13176. +(define_insn "satadd_w"
  13177. + [(set (match_operand:SI 0 "register_operand" "=r")
  13178. + (ss_plus:SI (match_operand:SI 1 "register_operand" "r")
  13179. + (match_operand:SI 2 "register_operand" "r")))]
  13180. + "TARGET_DSP"
  13181. + "satadd.w\t%0, %1, %2"
  13182. + [(set_attr "length" "4")
  13183. + (set_attr "cc" "none")
  13184. + (set_attr "type" "alu_sat")])
  13185. +
  13186. +(define_insn "satsub_w"
  13187. + [(set (match_operand:SI 0 "register_operand" "=r")
  13188. + (ss_minus:SI (match_operand:SI 1 "register_operand" "r")
  13189. + (match_operand:SI 2 "register_operand" "r")))]
  13190. + "TARGET_DSP"
  13191. + "satsub.w\t%0, %1, %2"
  13192. + [(set_attr "length" "4")
  13193. + (set_attr "cc" "none")
  13194. + (set_attr "type" "alu_sat")])
  13195. +
  13196. +(define_insn "satadd_h"
  13197. + [(set (match_operand:HI 0 "register_operand" "=r")
  13198. + (ss_plus:HI (match_operand:HI 1 "register_operand" "r")
  13199. + (match_operand:HI 2 "register_operand" "r")))]
  13200. + "TARGET_DSP"
  13201. + "satadd.h\t%0, %1, %2"
  13202. + [(set_attr "length" "4")
  13203. + (set_attr "cc" "none")
  13204. + (set_attr "type" "alu_sat")])
  13205. +
  13206. +(define_insn "satsub_h"
  13207. + [(set (match_operand:HI 0 "register_operand" "=r")
  13208. + (ss_minus:HI (match_operand:HI 1 "register_operand" "r")
  13209. + (match_operand:HI 2 "register_operand" "r")))]
  13210. + "TARGET_DSP"
  13211. + "satsub.h\t%0, %1, %2"
  13212. + [(set_attr "length" "4")
  13213. + (set_attr "cc" "none")
  13214. + (set_attr "type" "alu_sat")])
  13215. +
  13216. +
  13217. +;;=============================================================================
  13218. +;; smin
  13219. +;;-----------------------------------------------------------------------------
  13220. +;; Set reg0 to the smallest value of reg1 and reg2. It is used for signed
  13221. +;; values in the registers.
  13222. +;;=============================================================================
  13223. +(define_insn "sminsi3"
  13224. + [(set (match_operand:SI 0 "register_operand" "=r")
  13225. + (smin:SI (match_operand:SI 1 "register_operand" "r")
  13226. + (match_operand:SI 2 "register_operand" "r")))]
  13227. + ""
  13228. + "min %0, %1, %2"
  13229. + [(set_attr "length" "4")
  13230. + (set_attr "cc" "none")])
  13231. +
  13232. +;;=============================================================================
  13233. +;; smax
  13234. +;;-----------------------------------------------------------------------------
  13235. +;; Set reg0 to the largest value of reg1 and reg2. It is used for signed
  13236. +;; values in the registers.
  13237. +;;=============================================================================
  13238. +(define_insn "smaxsi3"
  13239. + [(set (match_operand:SI 0 "register_operand" "=r")
  13240. + (smax:SI (match_operand:SI 1 "register_operand" "r")
  13241. + (match_operand:SI 2 "register_operand" "r")))]
  13242. + ""
  13243. + "max %0, %1, %2"
  13244. + [(set_attr "length" "4")
  13245. + (set_attr "cc" "none")])
  13246. +
  13247. +
  13248. +
  13249. +;;=============================================================================
  13250. +;; Logical operations
  13251. +;;-----------------------------------------------------------------------------
  13252. +
  13253. +
  13254. +;; Split up simple DImode logical operations. Simply perform the logical
  13255. +;; operation on the upper and lower halves of the registers.
  13256. +(define_split
  13257. + [(set (match_operand:DI 0 "register_operand" "")
  13258. + (match_operator:DI 6 "logical_binary_operator"
  13259. + [(match_operand:DI 1 "register_operand" "")
  13260. + (match_operand:DI 2 "register_operand" "")]))]
  13261. + "reload_completed"
  13262. + [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
  13263. + (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
  13264. + "
  13265. + {
  13266. + operands[3] = gen_highpart (SImode, operands[0]);
  13267. + operands[0] = gen_lowpart (SImode, operands[0]);
  13268. + operands[4] = gen_highpart (SImode, operands[1]);
  13269. + operands[1] = gen_lowpart (SImode, operands[1]);
  13270. + operands[5] = gen_highpart (SImode, operands[2]);
  13271. + operands[2] = gen_lowpart (SImode, operands[2]);
  13272. + }"
  13273. +)
  13274. +
  13275. +;;=============================================================================
  13276. +;; Logical operations with shifted operand
  13277. +;;=============================================================================
  13278. +(define_insn "<code>si_lshift"
  13279. + [(set (match_operand:SI 0 "register_operand" "=r")
  13280. + (logical:SI (match_operator:SI 4 "logical_shift_operator"
  13281. + [(match_operand:SI 2 "register_operand" "r")
  13282. + (match_operand:SI 3 "immediate_operand" "Ku05")])
  13283. + (match_operand:SI 1 "register_operand" "r")))]
  13284. + ""
  13285. + {
  13286. + if ( GET_CODE(operands[4]) == ASHIFT )
  13287. + return "<logical_insn>\t%0, %1, %2 << %3";
  13288. + else
  13289. + return "<logical_insn>\t%0, %1, %2 >> %3";
  13290. + }
  13291. +
  13292. + [(set_attr "cc" "set_z")]
  13293. +)
  13294. +
  13295. +
  13296. +;;************************************************
  13297. +;; Peepholes for detecting logical operantions
  13298. +;; with shifted operands
  13299. +;;************************************************
  13300. +
  13301. +(define_peephole
  13302. + [(set (match_operand:SI 3 "register_operand" "")
  13303. + (match_operator:SI 5 "logical_shift_operator"
  13304. + [(match_operand:SI 1 "register_operand" "")
  13305. + (match_operand:SI 2 "immediate_operand" "")]))
  13306. + (set (match_operand:SI 0 "register_operand" "")
  13307. + (logical:SI (match_operand:SI 4 "register_operand" "")
  13308. + (match_dup 3)))]
  13309. + "(dead_or_set_p(insn, operands[3])) || (REGNO(operands[3]) == REGNO(operands[0]))"
  13310. + {
  13311. + if ( GET_CODE(operands[5]) == ASHIFT )
  13312. + return "<logical_insn>\t%0, %4, %1 << %2";
  13313. + else
  13314. + return "<logical_insn>\t%0, %4, %1 >> %2";
  13315. + }
  13316. + [(set_attr "cc" "set_z")]
  13317. + )
  13318. +
  13319. +(define_peephole
  13320. + [(set (match_operand:SI 3 "register_operand" "")
  13321. + (match_operator:SI 5 "logical_shift_operator"
  13322. + [(match_operand:SI 1 "register_operand" "")
  13323. + (match_operand:SI 2 "immediate_operand" "")]))
  13324. + (set (match_operand:SI 0 "register_operand" "")
  13325. + (logical:SI (match_dup 3)
  13326. + (match_operand:SI 4 "register_operand" "")))]
  13327. + "(dead_or_set_p(insn, operands[3])) || (REGNO(operands[3]) == REGNO(operands[0]))"
  13328. + {
  13329. + if ( GET_CODE(operands[5]) == ASHIFT )
  13330. + return "<logical_insn>\t%0, %4, %1 << %2";
  13331. + else
  13332. + return "<logical_insn>\t%0, %4, %1 >> %2";
  13333. + }
  13334. + [(set_attr "cc" "set_z")]
  13335. + )
  13336. +
  13337. +
  13338. +(define_peephole2
  13339. + [(set (match_operand:SI 0 "register_operand" "")
  13340. + (match_operator:SI 5 "logical_shift_operator"
  13341. + [(match_operand:SI 1 "register_operand" "")
  13342. + (match_operand:SI 2 "immediate_operand" "")]))
  13343. + (set (match_operand:SI 3 "register_operand" "")
  13344. + (logical:SI (match_operand:SI 4 "register_operand" "")
  13345. + (match_dup 0)))]
  13346. + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[3]) == REGNO(operands[0]))"
  13347. +
  13348. + [(set (match_dup 3)
  13349. + (logical:SI (match_op_dup:SI 5 [(match_dup 1) (match_dup 2)])
  13350. + (match_dup 4)))]
  13351. +
  13352. + ""
  13353. +)
  13354. +
  13355. +(define_peephole2
  13356. + [(set (match_operand:SI 0 "register_operand" "")
  13357. + (match_operator:SI 5 "logical_shift_operator"
  13358. + [(match_operand:SI 1 "register_operand" "")
  13359. + (match_operand:SI 2 "immediate_operand" "")]))
  13360. + (set (match_operand:SI 3 "register_operand" "")
  13361. + (logical:SI (match_dup 0)
  13362. + (match_operand:SI 4 "register_operand" "")))]
  13363. + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[3]) == REGNO(operands[0]))"
  13364. +
  13365. + [(set (match_dup 3)
  13366. + (logical:SI (match_op_dup:SI 5 [(match_dup 1) (match_dup 2)])
  13367. + (match_dup 4)))]
  13368. +
  13369. + ""
  13370. +)
  13371. +
  13372. +
  13373. +;;=============================================================================
  13374. +;; and
  13375. +;;-----------------------------------------------------------------------------
  13376. +;; Store the result after a bitwise logical-and between reg0 and reg2 in reg0.
  13377. +;;=============================================================================
  13378. +
  13379. +(define_insn "andnsi"
  13380. + [(set (match_operand:SI 0 "register_operand" "+r")
  13381. + (and:SI (match_dup 0)
  13382. + (not:SI (match_operand:SI 1 "register_operand" "r"))))]
  13383. + ""
  13384. + "andn %0, %1"
  13385. + [(set_attr "cc" "set_z")
  13386. + (set_attr "length" "2")]
  13387. +)
  13388. +
  13389. +
  13390. +(define_insn "andsi3"
  13391. + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r,r, r, r,r,r,r,r")
  13392. + (and:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,r,0,0, 0, 0,0,0,0,r" )
  13393. + (match_operand:SI 2 "nonmemory_operand" " N,M,N,Ku16,Ks17,J,L,r,i,r")))]
  13394. + ""
  13395. + "@
  13396. + memc\t%0, %z2
  13397. + bfextu\t%0, %1, 0, %z2
  13398. + cbr\t%0, %z2
  13399. + andl\t%0, %2, COH
  13400. + andl\t%0, lo(%2)
  13401. + andh\t%0, hi(%2), COH
  13402. + andh\t%0, hi(%2)
  13403. + and\t%0, %2
  13404. + andh\t%0, hi(%2)\;andl\t%0, lo(%2)
  13405. + and\t%0, %1, %2"
  13406. +
  13407. + [(set_attr "length" "4,4,2,4,4,4,4,2,8,4")
  13408. + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z")])
  13409. +
  13410. +
  13411. +
  13412. +(define_insn "anddi3"
  13413. + [(set (match_operand:DI 0 "register_operand" "=&r,&r")
  13414. + (and:DI (match_operand:DI 1 "register_operand" "%0,r")
  13415. + (match_operand:DI 2 "register_operand" "r,r")))]
  13416. + ""
  13417. + "#"
  13418. + [(set_attr "length" "8")
  13419. + (set_attr "cc" "clobber")]
  13420. +)
  13421. +
  13422. +;;=============================================================================
  13423. +;; or
  13424. +;;-----------------------------------------------------------------------------
  13425. +;; Store the result after a bitwise inclusive-or between reg0 and reg2 in reg0.
  13426. +;;=============================================================================
  13427. +
  13428. +(define_insn "iorsi3"
  13429. + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r, r,r,r,r")
  13430. + (ior:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0,0, 0,0,0,r" )
  13431. + (match_operand:SI 2 "nonmemory_operand" " O,O,Ku16,J,r,i,r")))]
  13432. + ""
  13433. + "@
  13434. + mems\t%0, %p2
  13435. + sbr\t%0, %p2
  13436. + orl\t%0, %2
  13437. + orh\t%0, hi(%2)
  13438. + or\t%0, %2
  13439. + orh\t%0, hi(%2)\;orl\t%0, lo(%2)
  13440. + or\t%0, %1, %2"
  13441. +
  13442. + [(set_attr "length" "4,2,4,4,2,8,4")
  13443. + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z")])
  13444. +
  13445. +
  13446. +(define_insn "iordi3"
  13447. + [(set (match_operand:DI 0 "register_operand" "=&r,&r")
  13448. + (ior:DI (match_operand:DI 1 "register_operand" "%0,r")
  13449. + (match_operand:DI 2 "register_operand" "r,r")))]
  13450. + ""
  13451. + "#"
  13452. + [(set_attr "length" "8")
  13453. + (set_attr "cc" "clobber")]
  13454. +)
  13455. +
  13456. +;;=============================================================================
  13457. +;; xor bytes
  13458. +;;-----------------------------------------------------------------------------
  13459. +;; Store the result after a bitwise exclusive-or between reg0 and reg2 in reg0.
  13460. +;;=============================================================================
  13461. +
  13462. +(define_insn "xorsi3"
  13463. + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r, r,r,r,r")
  13464. + (xor:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0, 0,0,0,r" )
  13465. + (match_operand:SI 2 "nonmemory_operand" " O,Ku16,J,r,i,r")))]
  13466. + ""
  13467. + "@
  13468. + memt\t%0, %p2
  13469. + eorl\t%0, %2
  13470. + eorh\t%0, hi(%2)
  13471. + eor\t%0, %2
  13472. + eorh\t%0, hi(%2)\;eorl\t%0, lo(%2)
  13473. + eor\t%0, %1, %2"
  13474. +
  13475. + [(set_attr "length" "4,4,4,2,8,4")
  13476. + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z")])
  13477. +
  13478. +(define_insn "xordi3"
  13479. + [(set (match_operand:DI 0 "register_operand" "=&r,&r")
  13480. + (xor:DI (match_operand:DI 1 "register_operand" "%0,r")
  13481. + (match_operand:DI 2 "register_operand" "r,r")))]
  13482. + ""
  13483. + "#"
  13484. + [(set_attr "length" "8")
  13485. + (set_attr "cc" "clobber")]
  13486. +)
  13487. +
  13488. +;;=============================================================================
  13489. +;; Three operand predicable insns
  13490. +;;=============================================================================
  13491. +
  13492. +(define_insn "<predicable_insn3><mode>_predicable"
  13493. + [(set (match_operand:INTM 0 "register_operand" "=r")
  13494. + (predicable_op3:INTM (match_operand:INTM 1 "register_operand" "<predicable_commutative3>r")
  13495. + (match_operand:INTM 2 "register_operand" "r")))]
  13496. + "TARGET_V2_INSNS"
  13497. + "<predicable_insn3>%?\t%0, %1, %2"
  13498. + [(set_attr "length" "4")
  13499. + (set_attr "cc" "cmp_cond_insn")
  13500. + (set_attr "predicable" "yes")]
  13501. +)
  13502. +
  13503. +(define_insn_and_split "<predicable_insn3><mode>_imm_clobber_predicable"
  13504. + [(parallel
  13505. + [(set (match_operand:INTM 0 "register_operand" "=r")
  13506. + (predicable_op3:INTM (match_operand:INTM 1 "register_operand" "<predicable_commutative3>r")
  13507. + (match_operand:INTM 2 "avr32_mov_immediate_operand" "JKs21")))
  13508. + (clobber (match_operand:INTM 3 "register_operand" "=&r"))])]
  13509. + "TARGET_V2_INSNS"
  13510. + {
  13511. + if ( current_insn_predicate != NULL_RTX )
  13512. + {
  13513. + if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks08") )
  13514. + return "%! mov%?\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
  13515. + else if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks21") )
  13516. + return "%! mov\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
  13517. + else
  13518. + return "%! movh\t%3, hi(%2)\;<predicable_insn3>%?\t%0, %1, %3";
  13519. + }
  13520. + else
  13521. + {
  13522. + if ( !avr32_cond_imm_clobber_splittable (insn, operands) )
  13523. + {
  13524. + if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks08") )
  13525. + return "mov%?\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
  13526. + else if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks21") )
  13527. + return "mov\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
  13528. + else
  13529. + return "movh\t%3, hi(%2)\;<predicable_insn3>%?\t%0, %1, %3";
  13530. + }
  13531. + return "#";
  13532. + }
  13533. +
  13534. + }
  13535. + ;; If we find out that we could not actually do if-conversion on the block
  13536. + ;; containing this insn we convert it back to normal immediate format
  13537. + ;; to avoid outputing a redundant move insn
  13538. + ;; Do not split until after we have checked if we can make the insn
  13539. + ;; conditional.
  13540. + "(GET_CODE (PATTERN (insn)) != COND_EXEC
  13541. + && cfun->machine->ifcvt_after_reload
  13542. + && avr32_cond_imm_clobber_splittable (insn, operands))"
  13543. + [(set (match_dup 0)
  13544. + (predicable_op3:INTM (match_dup 1)
  13545. + (match_dup 2)))]
  13546. + ""
  13547. + [(set_attr "length" "8")
  13548. + (set_attr "cc" "cmp_cond_insn")
  13549. + (set_attr "predicable" "yes")]
  13550. + )
  13551. +
  13552. +
  13553. +;;=============================================================================
  13554. +;; Zero extend predicable insns
  13555. +;;=============================================================================
  13556. +(define_insn_and_split "zero_extendhisi_clobber_predicable"
  13557. + [(parallel
  13558. + [(set (match_operand:SI 0 "register_operand" "=r")
  13559. + (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
  13560. + (clobber (match_operand:SI 2 "register_operand" "=&r"))])]
  13561. + "TARGET_V2_INSNS"
  13562. + {
  13563. + if ( current_insn_predicate != NULL_RTX )
  13564. + {
  13565. + return "%! mov\t%2, 0xffff\;and%?\t%0, %1, %2";
  13566. + }
  13567. + else
  13568. + {
  13569. + return "#";
  13570. + }
  13571. +
  13572. + }
  13573. + ;; If we find out that we could not actually do if-conversion on the block
  13574. + ;; containing this insn we convert it back to normal immediate format
  13575. + ;; to avoid outputing a redundant move insn
  13576. + ;; Do not split until after we have checked if we can make the insn
  13577. + ;; conditional.
  13578. + "(GET_CODE (PATTERN (insn)) != COND_EXEC
  13579. + && cfun->machine->ifcvt_after_reload)"
  13580. + [(set (match_dup 0)
  13581. + (zero_extend:SI (match_dup 1)))]
  13582. + ""
  13583. + [(set_attr "length" "8")
  13584. + (set_attr "cc" "cmp_cond_insn")
  13585. + (set_attr "predicable" "yes")]
  13586. + )
  13587. +
  13588. +(define_insn_and_split "zero_extendqisi_clobber_predicable"
  13589. + [(parallel
  13590. + [(set (match_operand:SI 0 "register_operand" "=r")
  13591. + (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
  13592. + (clobber (match_operand:SI 2 "register_operand" "=&r"))])]
  13593. + "TARGET_V2_INSNS"
  13594. + {
  13595. + if ( current_insn_predicate != NULL_RTX )
  13596. + {
  13597. + return "%! mov\t%2, 0xff\;and%?\t%0, %1, %2";
  13598. + }
  13599. + else
  13600. + {
  13601. + return "#";
  13602. + }
  13603. +
  13604. + }
  13605. + ;; If we find out that we could not actually do if-conversion on the block
  13606. + ;; containing this insn we convert it back to normal immediate format
  13607. + ;; to avoid outputing a redundant move insn
  13608. + ;; Do not split until after we have checked if we can make the insn
  13609. + ;; conditional.
  13610. + "(GET_CODE (PATTERN (insn)) != COND_EXEC
  13611. + && cfun->machine->ifcvt_after_reload)"
  13612. + [(set (match_dup 0)
  13613. + (zero_extend:SI (match_dup 1)))]
  13614. + ""
  13615. + [(set_attr "length" "8")
  13616. + (set_attr "cc" "cmp_cond_insn")
  13617. + (set_attr "predicable" "yes")]
  13618. + )
  13619. +
  13620. +(define_insn_and_split "zero_extendqihi_clobber_predicable"
  13621. + [(parallel
  13622. + [(set (match_operand:HI 0 "register_operand" "=r")
  13623. + (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))
  13624. + (clobber (match_operand:SI 2 "register_operand" "=&r"))])]
  13625. + "TARGET_V2_INSNS"
  13626. + {
  13627. + if ( current_insn_predicate != NULL_RTX )
  13628. + {
  13629. + return "%! mov\t%2, 0xff\;and%?\t%0, %1, %2";
  13630. + }
  13631. + else
  13632. + {
  13633. + return "#";
  13634. + }
  13635. +
  13636. + }
  13637. + ;; If we find out that we could not actually do if-conversion on the block
  13638. + ;; containing this insn we convert it back to normal immediate format
  13639. + ;; to avoid outputing a redundant move insn
  13640. + ;; Do not split until after we have checked if we can make the insn
  13641. + ;; conditional.
  13642. + "(GET_CODE (PATTERN (insn)) != COND_EXEC
  13643. + && cfun->machine->ifcvt_after_reload)"
  13644. + [(set (match_dup 0)
  13645. + (zero_extend:HI (match_dup 1)))]
  13646. + ""
  13647. + [(set_attr "length" "8")
  13648. + (set_attr "cc" "cmp_cond_insn")
  13649. + (set_attr "predicable" "yes")]
  13650. + )
  13651. +;;=============================================================================
  13652. +;; divmod
  13653. +;;-----------------------------------------------------------------------------
  13654. +;; Signed division that produces both a quotient and a remainder.
  13655. +;;=============================================================================
  13656. +
  13657. +(define_expand "divmodsi4"
  13658. + [(parallel [
  13659. + (parallel [
  13660. + (set (match_operand:SI 0 "register_operand" "=r")
  13661. + (div:SI (match_operand:SI 1 "register_operand" "r")
  13662. + (match_operand:SI 2 "register_operand" "r")))
  13663. + (set (match_operand:SI 3 "register_operand" "=r")
  13664. + (mod:SI (match_dup 1)
  13665. + (match_dup 2)))])
  13666. + (use (match_dup 4))])]
  13667. + ""
  13668. + {
  13669. + if (can_create_pseudo_p ()) {
  13670. + operands[4] = gen_reg_rtx (DImode);
  13671. + emit_insn(gen_divmodsi4_internal(operands[4],operands[1],operands[2]));
  13672. + emit_move_insn(operands[0], gen_rtx_SUBREG( SImode, operands[4], 4));
  13673. + emit_move_insn(operands[3], gen_rtx_SUBREG( SImode, operands[4], 0));
  13674. + DONE;
  13675. + } else {
  13676. + FAIL;
  13677. + }
  13678. + })
  13679. +
  13680. +
  13681. +(define_insn "divmodsi4_internal"
  13682. + [(set (match_operand:DI 0 "register_operand" "=r")
  13683. + (unspec:DI [(match_operand:SI 1 "register_operand" "r")
  13684. + (match_operand:SI 2 "register_operand" "r")]
  13685. + UNSPEC_DIVMODSI4_INTERNAL))]
  13686. + ""
  13687. + "divs %0, %1, %2"
  13688. + [(set_attr "type" "div")
  13689. + (set_attr "cc" "none")])
  13690. +
  13691. +
  13692. +;;=============================================================================
  13693. +;; udivmod
  13694. +;;-----------------------------------------------------------------------------
  13695. +;; Unsigned division that produces both a quotient and a remainder.
  13696. +;;=============================================================================
  13697. +(define_expand "udivmodsi4"
  13698. + [(parallel [
  13699. + (parallel [
  13700. + (set (match_operand:SI 0 "register_operand" "=r")
  13701. + (udiv:SI (match_operand:SI 1 "register_operand" "r")
  13702. + (match_operand:SI 2 "register_operand" "r")))
  13703. + (set (match_operand:SI 3 "register_operand" "=r")
  13704. + (umod:SI (match_dup 1)
  13705. + (match_dup 2)))])
  13706. + (use (match_dup 4))])]
  13707. + ""
  13708. + {
  13709. + if (can_create_pseudo_p ()) {
  13710. + operands[4] = gen_reg_rtx (DImode);
  13711. +
  13712. + emit_insn(gen_udivmodsi4_internal(operands[4],operands[1],operands[2]));
  13713. + emit_move_insn(operands[0], gen_rtx_SUBREG( SImode, operands[4], 4));
  13714. + emit_move_insn(operands[3], gen_rtx_SUBREG( SImode, operands[4], 0));
  13715. +
  13716. + DONE;
  13717. + } else {
  13718. + FAIL;
  13719. + }
  13720. + })
  13721. +
  13722. +(define_insn "udivmodsi4_internal"
  13723. + [(set (match_operand:DI 0 "register_operand" "=r")
  13724. + (unspec:DI [(match_operand:SI 1 "register_operand" "r")
  13725. + (match_operand:SI 2 "register_operand" "r")]
  13726. + UNSPEC_UDIVMODSI4_INTERNAL))]
  13727. + ""
  13728. + "divu %0, %1, %2"
  13729. + [(set_attr "type" "div")
  13730. + (set_attr "cc" "none")])
  13731. +
  13732. +
  13733. +;;=============================================================================
  13734. +;; Arithmetic-shift left
  13735. +;;-----------------------------------------------------------------------------
  13736. +;; Arithmetic-shift reg0 left by reg2 or immediate value.
  13737. +;;=============================================================================
  13738. +
  13739. +(define_insn "ashlsi3"
  13740. + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
  13741. + (ashift:SI (match_operand:SI 1 "register_operand" "r,0,r")
  13742. + (match_operand:SI 2 "register_const_int_operand" "r,Ku05,Ku05")))]
  13743. + ""
  13744. + "@
  13745. + lsl %0, %1, %2
  13746. + lsl %0, %2
  13747. + lsl %0, %1, %2"
  13748. + [(set_attr "length" "4,2,4")
  13749. + (set_attr "cc" "set_ncz")])
  13750. +
  13751. +;;=============================================================================
  13752. +;; Arithmetic-shift right
  13753. +;;-----------------------------------------------------------------------------
  13754. +;; Arithmetic-shift reg0 right by an immediate value.
  13755. +;;=============================================================================
  13756. +
  13757. +(define_insn "ashrsi3"
  13758. + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
  13759. + (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,0,r")
  13760. + (match_operand:SI 2 "register_const_int_operand" "r,Ku05,Ku05")))]
  13761. + ""
  13762. + "@
  13763. + asr %0, %1, %2
  13764. + asr %0, %2
  13765. + asr %0, %1, %2"
  13766. + [(set_attr "length" "4,2,4")
  13767. + (set_attr "cc" "set_ncz")])
  13768. +
  13769. +;;=============================================================================
  13770. +;; Logical shift right
  13771. +;;-----------------------------------------------------------------------------
  13772. +;; Logical shift reg0 right by an immediate value.
  13773. +;;=============================================================================
  13774. +
  13775. +(define_insn "lshrsi3"
  13776. + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
  13777. + (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0,r")
  13778. + (match_operand:SI 2 "register_const_int_operand" "r,Ku05,Ku05")))]
  13779. + ""
  13780. + "@
  13781. + lsr %0, %1, %2
  13782. + lsr %0, %2
  13783. + lsr %0, %1, %2"
  13784. + [(set_attr "length" "4,2,4")
  13785. + (set_attr "cc" "set_ncz")])
  13786. +
  13787. +
  13788. +;;=============================================================================
  13789. +;; neg
  13790. +;;-----------------------------------------------------------------------------
  13791. +;; Negate operand 1 and store the result in operand 0.
  13792. +;;=============================================================================
  13793. +(define_insn "negsi2"
  13794. + [(set (match_operand:SI 0 "register_operand" "=r,r")
  13795. + (neg:SI (match_operand:SI 1 "register_operand" "0,r")))]
  13796. + ""
  13797. + "@
  13798. + neg\t%0
  13799. + rsub\t%0, %1, 0"
  13800. + [(set_attr "length" "2,4")
  13801. + (set_attr "cc" "set_vncz")])
  13802. +
  13803. +(define_insn "negsi2_predicable"
  13804. + [(set (match_operand:SI 0 "register_operand" "+r")
  13805. + (neg:SI (match_dup 0)))]
  13806. + "TARGET_V2_INSNS"
  13807. + "rsub%?\t%0, 0"
  13808. + [(set_attr "length" "4")
  13809. + (set_attr "cc" "cmp_cond_insn")
  13810. + (set_attr "predicable" "yes")])
  13811. +
  13812. +;;=============================================================================
  13813. +;; abs
  13814. +;;-----------------------------------------------------------------------------
  13815. +;; Store the absolute value of operand 1 into operand 0.
  13816. +;;=============================================================================
  13817. +(define_insn "abssi2"
  13818. + [(set (match_operand:SI 0 "register_operand" "=r")
  13819. + (abs:SI (match_operand:SI 1 "register_operand" "0")))]
  13820. + ""
  13821. + "abs\t%0"
  13822. + [(set_attr "length" "2")
  13823. + (set_attr "cc" "set_z")])
  13824. +
  13825. +
  13826. +;;=============================================================================
  13827. +;; one_cmpl
  13828. +;;-----------------------------------------------------------------------------
  13829. +;; Store the bitwise-complement of operand 1 into operand 0.
  13830. +;;=============================================================================
  13831. +
  13832. +(define_insn "one_cmplsi2"
  13833. + [(set (match_operand:SI 0 "register_operand" "=r,r")
  13834. + (not:SI (match_operand:SI 1 "register_operand" "0,r")))]
  13835. + ""
  13836. + "@
  13837. + com\t%0
  13838. + rsub\t%0, %1, -1"
  13839. + [(set_attr "length" "2,4")
  13840. + (set_attr "cc" "set_z")])
  13841. +
  13842. +
  13843. +(define_insn "one_cmplsi2_predicable"
  13844. + [(set (match_operand:SI 0 "register_operand" "+r")
  13845. + (not:SI (match_dup 0)))]
  13846. + "TARGET_V2_INSNS"
  13847. + "rsub%?\t%0, -1"
  13848. + [(set_attr "length" "4")
  13849. + (set_attr "cc" "cmp_cond_insn")
  13850. + (set_attr "predicable" "yes")])
  13851. +
  13852. +
  13853. +;;=============================================================================
  13854. +;; Bit load
  13855. +;;-----------------------------------------------------------------------------
  13856. +;; Load a bit into Z and C flags
  13857. +;;=============================================================================
  13858. +(define_insn "bldsi"
  13859. + [(set (cc0)
  13860. + (and:SI (match_operand:SI 0 "register_operand" "r")
  13861. + (match_operand:SI 1 "one_bit_set_operand" "i")))]
  13862. + ""
  13863. + "bld\t%0, %p1"
  13864. + [(set_attr "length" "4")
  13865. + (set_attr "cc" "bld")]
  13866. + )
  13867. +
  13868. +
  13869. +;;=============================================================================
  13870. +;; Compare
  13871. +;;-----------------------------------------------------------------------------
  13872. +;; Compare reg0 with reg1 or an immediate value.
  13873. +;;=============================================================================
  13874. +
  13875. +(define_expand "cmp<mode>"
  13876. + [(set (cc0)
  13877. + (compare:CMP
  13878. + (match_operand:CMP 0 "register_operand" "")
  13879. + (match_operand:CMP 1 "<CMP:cmp_predicate>" "")))]
  13880. + ""
  13881. + "{
  13882. + avr32_compare_op0 = operands[0];
  13883. + avr32_compare_op1 = operands[1];
  13884. + }"
  13885. +)
  13886. +
  13887. +(define_insn "cmp<mode>_internal"
  13888. + [(set (cc0)
  13889. + (compare:CMP
  13890. + (match_operand:CMP 0 "register_operand" "r")
  13891. + (match_operand:CMP 1 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")))]
  13892. + ""
  13893. + {
  13894. +switch(GET_MODE(operands[0]))
  13895. + {
  13896. + case QImode:
  13897. + avr32_branch_type = CMP_QI;
  13898. + break;
  13899. + case HImode:
  13900. + avr32_branch_type = CMP_HI;
  13901. + break;
  13902. + case SImode:
  13903. + avr32_branch_type = CMP_SI;
  13904. + break;
  13905. + case DImode:
  13906. + avr32_branch_type = CMP_DI;
  13907. + break;
  13908. + default:
  13909. + abort();
  13910. + }
  13911. + /* Check if the next insn already will output a compare. */
  13912. + if (!next_insn_emits_cmp (insn))
  13913. + set_next_insn_cond(insn,
  13914. + avr32_output_cmp(get_next_insn_cond(insn), GET_MODE (operands[0]), operands[0], operands[1]));
  13915. + return "";
  13916. + }
  13917. + [(set_attr "length" "4")
  13918. + (set_attr "cc" "compare")])
  13919. +
  13920. +(define_expand "cmpsf"
  13921. + [(set (cc0)
  13922. + (compare:SF
  13923. + (match_operand:SF 0 "general_operand" "")
  13924. + (match_operand:SF 1 "general_operand" "")))]
  13925. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  13926. + "{
  13927. + if ( !REG_P(operands[0]) )
  13928. + operands[0] = force_reg(SFmode, operands[0]);
  13929. +
  13930. + if ( !REG_P(operands[1]) )
  13931. + operands[1] = force_reg(SFmode, operands[1]);
  13932. +
  13933. + avr32_compare_op0 = operands[0];
  13934. + avr32_compare_op1 = operands[1];
  13935. + emit_insn(gen_cmpsf_internal_uc3fp(operands[0], operands[1]));
  13936. + DONE;
  13937. + }"
  13938. +)
  13939. +
  13940. +;;;=============================================================================
  13941. +;; Test if zero
  13942. +;;-----------------------------------------------------------------------------
  13943. +;; Compare reg against zero and set the condition codes.
  13944. +;;=============================================================================
  13945. +
  13946. +
  13947. +(define_expand "tstsi"
  13948. + [(set (cc0)
  13949. + (match_operand:SI 0 "register_operand" ""))]
  13950. + ""
  13951. + {
  13952. + avr32_compare_op0 = operands[0];
  13953. + avr32_compare_op1 = const0_rtx;
  13954. + }
  13955. +)
  13956. +
  13957. +(define_insn "tstsi_internal"
  13958. + [(set (cc0)
  13959. + (match_operand:SI 0 "register_operand" "r"))]
  13960. + ""
  13961. + {
  13962. + /* Check if the next insn already will output a compare. */
  13963. + if (!next_insn_emits_cmp (insn))
  13964. + set_next_insn_cond(insn,
  13965. + avr32_output_cmp(get_next_insn_cond(insn), SImode, operands[0], const0_rtx));
  13966. +
  13967. + return "";
  13968. + }
  13969. + [(set_attr "length" "2")
  13970. + (set_attr "cc" "compare")])
  13971. +
  13972. +
  13973. +(define_expand "tstdi"
  13974. + [(set (cc0)
  13975. + (match_operand:DI 0 "register_operand" ""))]
  13976. + ""
  13977. + {
  13978. + avr32_compare_op0 = operands[0];
  13979. + avr32_compare_op1 = const0_rtx;
  13980. + }
  13981. +)
  13982. +
  13983. +(define_insn "tstdi_internal"
  13984. + [(set (cc0)
  13985. + (match_operand:DI 0 "register_operand" "r"))]
  13986. + ""
  13987. + {
  13988. + /* Check if the next insn already will output a compare. */
  13989. + if (!next_insn_emits_cmp (insn))
  13990. + set_next_insn_cond(insn,
  13991. + avr32_output_cmp(get_next_insn_cond(insn), DImode, operands[0], const0_rtx));
  13992. + return "";
  13993. + }
  13994. + [(set_attr "length" "4")
  13995. + (set_attr "type" "alu2")
  13996. + (set_attr "cc" "compare")])
  13997. +
  13998. +
  13999. +
  14000. +;;=============================================================================
  14001. +;; Convert operands
  14002. +;;-----------------------------------------------------------------------------
  14003. +;;
  14004. +;;=============================================================================
  14005. +(define_insn "truncdisi2"
  14006. + [(set (match_operand:SI 0 "general_operand" "")
  14007. + (truncate:SI (match_operand:DI 1 "general_operand" "")))]
  14008. + ""
  14009. + "truncdisi2")
  14010. +
  14011. +;;=============================================================================
  14012. +;; Extend
  14013. +;;-----------------------------------------------------------------------------
  14014. +;;
  14015. +;;=============================================================================
  14016. +
  14017. +
  14018. +(define_insn "extendhisi2"
  14019. + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
  14020. + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
  14021. + ""
  14022. + {
  14023. + switch ( which_alternative ){
  14024. + case 0:
  14025. + return "casts.h\t%0";
  14026. + case 1:
  14027. + return "bfexts\t%0, %1, 0, 16";
  14028. + case 2:
  14029. + case 3:
  14030. + return "ld.sh\t%0, %1";
  14031. + default:
  14032. + abort();
  14033. + }
  14034. + }
  14035. + [(set_attr "length" "2,4,2,4")
  14036. + (set_attr "cc" "set_ncz,set_ncz,none,none")
  14037. + (set_attr "type" "alu,alu,load_rm,load_rm")])
  14038. +
  14039. +(define_insn "extendqisi2"
  14040. + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
  14041. + (sign_extend:SI (match_operand:QI 1 "extendqi_operand" "0,r,RKu00,m")))]
  14042. + ""
  14043. + {
  14044. + switch ( which_alternative ){
  14045. + case 0:
  14046. + return "casts.b\t%0";
  14047. + case 1:
  14048. + return "bfexts\t%0, %1, 0, 8";
  14049. + case 2:
  14050. + case 3:
  14051. + return "ld.sb\t%0, %1";
  14052. + default:
  14053. + abort();
  14054. + }
  14055. + }
  14056. + [(set_attr "length" "2,4,2,4")
  14057. + (set_attr "cc" "set_ncz,set_ncz,none,none")
  14058. + (set_attr "type" "alu,alu,load_rm,load_rm")])
  14059. +
  14060. +(define_insn "extendqihi2"
  14061. + [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
  14062. + (sign_extend:HI (match_operand:QI 1 "extendqi_operand" "0,r,RKu00,m")))]
  14063. + ""
  14064. + {
  14065. + switch ( which_alternative ){
  14066. + case 0:
  14067. + return "casts.b\t%0";
  14068. + case 1:
  14069. + return "bfexts\t%0, %1, 0, 8";
  14070. + case 2:
  14071. + case 3:
  14072. + return "ld.sb\t%0, %1";
  14073. + default:
  14074. + abort();
  14075. + }
  14076. + }
  14077. + [(set_attr "length" "2,4,2,4")
  14078. + (set_attr "cc" "set_ncz,set_ncz,none,none")
  14079. + (set_attr "type" "alu,alu,load_rm,load_rm")])
  14080. +
  14081. +
  14082. +;;=============================================================================
  14083. +;; Zero-extend
  14084. +;;-----------------------------------------------------------------------------
  14085. +;;
  14086. +;;=============================================================================
  14087. +
  14088. +(define_insn "zero_extendhisi2"
  14089. + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
  14090. + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
  14091. + ""
  14092. + {
  14093. + switch ( which_alternative ){
  14094. + case 0:
  14095. + return "castu.h\t%0";
  14096. + case 1:
  14097. + return "bfextu\t%0, %1, 0, 16";
  14098. + case 2:
  14099. + case 3:
  14100. + return "ld.uh\t%0, %1";
  14101. + default:
  14102. + abort();
  14103. + }
  14104. + }
  14105. +
  14106. + [(set_attr "length" "2,4,2,4")
  14107. + (set_attr "cc" "set_ncz,set_ncz,none,none")
  14108. + (set_attr "type" "alu,alu,load_rm,load_rm")])
  14109. +
  14110. +(define_insn "zero_extendqisi2"
  14111. + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
  14112. + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
  14113. + ""
  14114. + {
  14115. + switch ( which_alternative ){
  14116. + case 0:
  14117. + return "castu.b\t%0";
  14118. + case 1:
  14119. + return "bfextu\t%0, %1, 0, 8";
  14120. + case 2:
  14121. + case 3:
  14122. + return "ld.ub\t%0, %1";
  14123. + default:
  14124. + abort();
  14125. + }
  14126. + }
  14127. + [(set_attr "length" "2,4,2,4")
  14128. + (set_attr "cc" "set_ncz, set_ncz, none, none")
  14129. + (set_attr "type" "alu, alu, load_rm, load_rm")])
  14130. +
  14131. +(define_insn "zero_extendqihi2"
  14132. + [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
  14133. + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
  14134. + ""
  14135. + {
  14136. + switch ( which_alternative ){
  14137. + case 0:
  14138. + return "castu.b\t%0";
  14139. + case 1:
  14140. + return "bfextu\t%0, %1, 0, 8";
  14141. + case 2:
  14142. + case 3:
  14143. + return "ld.ub\t%0, %1";
  14144. + default:
  14145. + abort();
  14146. + }
  14147. + }
  14148. + [(set_attr "length" "2,4,2,4")
  14149. + (set_attr "cc" "set_ncz, set_ncz, none, none")
  14150. + (set_attr "type" "alu, alu, load_rm, load_rm")])
  14151. +
  14152. +
  14153. +;;=============================================================================
  14154. +;; Conditional load and extend insns
  14155. +;;=============================================================================
  14156. +(define_insn "ldsi<mode>_predicable_se"
  14157. + [(set (match_operand:SI 0 "register_operand" "=r")
  14158. + (sign_extend:SI
  14159. + (match_operand:INTM 1 "memory_operand" "<INTM:pred_mem_constraint>")))]
  14160. + "TARGET_V2_INSNS"
  14161. + "ld<INTM:load_postfix_s>%?\t%0, %1"
  14162. + [(set_attr "length" "4")
  14163. + (set_attr "cc" "cmp_cond_insn")
  14164. + (set_attr "type" "load")
  14165. + (set_attr "predicable" "yes")]
  14166. +)
  14167. +
  14168. +(define_insn "ldsi<mode>_predicable_ze"
  14169. + [(set (match_operand:SI 0 "register_operand" "=r")
  14170. + (zero_extend:SI
  14171. + (match_operand:INTM 1 "memory_operand" "<INTM:pred_mem_constraint>")))]
  14172. + "TARGET_V2_INSNS"
  14173. + "ld<INTM:load_postfix_u>%?\t%0, %1"
  14174. + [(set_attr "length" "4")
  14175. + (set_attr "cc" "cmp_cond_insn")
  14176. + (set_attr "type" "load")
  14177. + (set_attr "predicable" "yes")]
  14178. +)
  14179. +
  14180. +(define_insn "ldhi_predicable_ze"
  14181. + [(set (match_operand:HI 0 "register_operand" "=r")
  14182. + (zero_extend:HI
  14183. + (match_operand:QI 1 "memory_operand" "RKs10")))]
  14184. + "TARGET_V2_INSNS"
  14185. + "ld.ub%?\t%0, %1"
  14186. + [(set_attr "length" "4")
  14187. + (set_attr "cc" "cmp_cond_insn")
  14188. + (set_attr "type" "load")
  14189. + (set_attr "predicable" "yes")]
  14190. +)
  14191. +
  14192. +(define_insn "ldhi_predicable_se"
  14193. + [(set (match_operand:HI 0 "register_operand" "=r")
  14194. + (sign_extend:HI
  14195. + (match_operand:QI 1 "memory_operand" "RKs10")))]
  14196. + "TARGET_V2_INSNS"
  14197. + "ld.sb%?\t%0, %1"
  14198. + [(set_attr "length" "4")
  14199. + (set_attr "cc" "cmp_cond_insn")
  14200. + (set_attr "type" "load")
  14201. + (set_attr "predicable" "yes")]
  14202. +)
  14203. +
  14204. +;;=============================================================================
  14205. +;; Conditional set register
  14206. +;; sr{cond4} rd
  14207. +;;-----------------------------------------------------------------------------
  14208. +
  14209. +;;Because of the same issue as with conditional moves and adds we must
  14210. +;;not separate the compare instrcution from the scc instruction as
  14211. +;;they might be sheduled "badly".
  14212. +
  14213. +(define_expand "s<code>"
  14214. + [(set (match_operand:SI 0 "register_operand" "=r")
  14215. + (any_cond:SI (cc0)
  14216. + (const_int 0)))]
  14217. +""
  14218. +{
  14219. + if(TARGET_HARD_FLOAT && TARGET_ARCH_FPU)
  14220. + FAIL;
  14221. +})
  14222. +
  14223. +(define_insn "*s<code>"
  14224. + [(set (match_operand:SI 0 "register_operand" "=r")
  14225. + (any_cond:SI (cc0)
  14226. + (const_int 0)))]
  14227. + ""
  14228. +{
  14229. + return "sr<cond>\t%0";
  14230. +}
  14231. +[(set_attr "length" "2")
  14232. +(set_attr "cc" "none")])
  14233. +
  14234. +(define_insn "seq"
  14235. +[(set (match_operand:SI 0 "register_operand" "=r")
  14236. +(eq:SI (cc0)
  14237. + (const_int 0)))]
  14238. + ""
  14239. +"sreq\t%0"
  14240. +[(set_attr "length" "2")
  14241. +(set_attr "cc" "none")])
  14242. +
  14243. +(define_insn "sne"
  14244. +[(set (match_operand:SI 0 "register_operand" "=r")
  14245. +(ne:SI (cc0)
  14246. + (const_int 0)))]
  14247. + ""
  14248. +"srne\t%0"
  14249. + [(set_attr "length" "2")
  14250. + (set_attr "cc" "none")])
  14251. +
  14252. +(define_insn "smi"
  14253. + [(set (match_operand:SI 0 "register_operand" "=r")
  14254. + (unspec:SI [(cc0)
  14255. + (const_int 0)] UNSPEC_COND_MI))]
  14256. + ""
  14257. + "srmi\t%0"
  14258. + [(set_attr "length" "2")
  14259. + (set_attr "cc" "none")])
  14260. +
  14261. +(define_insn "spl"
  14262. + [(set (match_operand:SI 0 "register_operand" "=r")
  14263. + (unspec:SI [(cc0)
  14264. + (const_int 0)] UNSPEC_COND_PL))]
  14265. + ""
  14266. + "srpl\t%0"
  14267. + [(set_attr "length" "2")
  14268. + (set_attr "cc" "none")])
  14269. +
  14270. +
  14271. +;;=============================================================================
  14272. +;; Conditional branch
  14273. +;;-----------------------------------------------------------------------------
  14274. +;; Branch to label if the specified condition codes are set.
  14275. +;;=============================================================================
  14276. +; branch if negative
  14277. +(define_insn "bmi"
  14278. + [(set (pc)
  14279. + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_MI)
  14280. + (label_ref (match_operand 0 "" ""))
  14281. + (pc)))]
  14282. + ""
  14283. + "brmi %0"
  14284. + [(set_attr "type" "branch")
  14285. + (set (attr "length")
  14286. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14287. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14288. + (const_int 2)] ; use compact branch
  14289. + (const_int 4))) ; use extended branch
  14290. + (set_attr "cc" "none")])
  14291. +
  14292. +(define_insn "*bmi-reverse"
  14293. + [(set (pc)
  14294. + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_MI)
  14295. + (pc)
  14296. + (label_ref (match_operand 0 "" ""))))]
  14297. + ""
  14298. + "brpl %0"
  14299. + [(set_attr "type" "branch")
  14300. + (set (attr "length")
  14301. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14302. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14303. + (const_int 2)] ; use compact branch
  14304. + (const_int 4))) ; use extended branch
  14305. + (set_attr "cc" "none")])
  14306. +
  14307. +; branch if positive
  14308. +(define_insn "bpl"
  14309. + [(set (pc)
  14310. + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_PL)
  14311. + (label_ref (match_operand 0 "" ""))
  14312. + (pc)))]
  14313. + ""
  14314. + "brpl %0"
  14315. + [(set_attr "type" "branch")
  14316. + (set (attr "length")
  14317. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14318. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14319. + (const_int 2)] ; use compact branch
  14320. + (const_int 4))) ; use extended branch
  14321. + (set_attr "cc" "none")])
  14322. +
  14323. +(define_insn "*bpl-reverse"
  14324. + [(set (pc)
  14325. + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_PL)
  14326. + (pc)
  14327. + (label_ref (match_operand 0 "" ""))))]
  14328. + ""
  14329. + "brmi %0"
  14330. + [(set_attr "type" "branch")
  14331. + (set (attr "length")
  14332. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14333. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14334. + (const_int 2)] ; use compact branch
  14335. + (const_int 4))) ; use extended branch
  14336. + (set_attr "cc" "none")])
  14337. +
  14338. +; branch if equal
  14339. +(define_insn "b<code>"
  14340. + [(set (pc)
  14341. + (if_then_else (any_cond_b:CC (cc0)
  14342. + (const_int 0))
  14343. + (label_ref (match_operand 0 "" ""))
  14344. + (pc)))]
  14345. + ""
  14346. + {
  14347. + if (TARGET_HARD_FLOAT && TARGET_ARCH_FPU && (avr32_branch_type == CMP_SF))
  14348. + return get_attr_length(insn) == 6 ? "brvs .+6\;br<cond> %0" : "brvs .+8\;br<cond> %0";
  14349. + else
  14350. + return "br<cond> %0";
  14351. + }
  14352. + [(set_attr "type" "branch")
  14353. + (set (attr "length")
  14354. + (if_then_else (eq (const_int 1)(symbol_ref "TARGET_HARD_FLOAT && TARGET_ARCH_FPU"))
  14355. + (if_then_else
  14356. + (and (le (minus (match_dup 0) (pc)) (const_int 254))
  14357. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14358. + (const_int 6)
  14359. + (const_int 8))
  14360. + (if_then_else
  14361. + (and (le (minus (match_dup 0) (pc)) (const_int 254))
  14362. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14363. + (const_int 2)
  14364. + (const_int 4))))
  14365. + (set_attr "cc" "none")])
  14366. +
  14367. +(define_insn "beq"
  14368. + [(set (pc)
  14369. + (if_then_else (eq:CC (cc0)
  14370. + (const_int 0))
  14371. + (label_ref (match_operand 0 "" ""))
  14372. + (pc)))]
  14373. + ""
  14374. + "breq %0";
  14375. + [(set_attr "type" "branch")
  14376. + (set (attr "length")
  14377. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14378. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14379. + (const_int 2)] ; use compact branch
  14380. + (const_int 4))) ; use extended branch
  14381. + (set_attr "cc" "none")])
  14382. +
  14383. +(define_insn "bne"
  14384. + [(set (pc)
  14385. + (if_then_else (ne:CC (cc0)
  14386. + (const_int 0))
  14387. + (label_ref (match_operand 0 "" ""))
  14388. + (pc)))]
  14389. + ""
  14390. + "brne %0";
  14391. + [(set_attr "type" "branch")
  14392. + (set (attr "length")
  14393. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14394. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14395. + (const_int 2)] ; use compact branch
  14396. + (const_int 4))) ; use extended branch
  14397. + (set_attr "cc" "none")])
  14398. +
  14399. +(define_insn "b<code>"
  14400. + [(set (pc)
  14401. + (if_then_else (any_cond4:CC (cc0)
  14402. + (const_int 0))
  14403. + (label_ref (match_operand 0 "" ""))
  14404. + (pc)))]
  14405. + ""
  14406. + {
  14407. + if(TARGET_HARD_FLOAT && TARGET_ARCH_FPU && (avr32_branch_type == CMP_SF))
  14408. + return "brvs .+8\;br<cond> %l0";
  14409. + else
  14410. + return "br<cond> %l0";
  14411. + }
  14412. + [(set_attr "type" "branch")
  14413. + (set (attr "length")
  14414. + (cond [(eq (const_int 1)(symbol_ref "TARGET_HARD_FLOAT && TARGET_ARCH_FPU"))
  14415. + (const_int 8)]
  14416. + (const_int 4)))
  14417. + (set_attr "cc" "none")])
  14418. +
  14419. +(define_insn "*b<code>-reverse"
  14420. + [(set (pc)
  14421. + (if_then_else (any_cond_b:CC (cc0)
  14422. + (const_int 0))
  14423. + (pc)
  14424. + (label_ref (match_operand 0 "" ""))))]
  14425. + ""
  14426. + {
  14427. + if (TARGET_HARD_FLOAT && TARGET_ARCH_FPU && (avr32_branch_type == CMP_SF))
  14428. + return "brvs %0\;br<invcond> %0";
  14429. + else
  14430. + return "br<invcond> %0";
  14431. + }
  14432. + [(set_attr "type" "branch")
  14433. + (set (attr "length")
  14434. + (if_then_else (eq (const_int 1)(symbol_ref "TARGET_HARD_FLOAT && TARGET_ARCH_FPU"))
  14435. + (if_then_else
  14436. + (and (le (minus (match_dup 0) (pc)) (const_int 254))
  14437. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14438. + (const_int 6)
  14439. + (const_int 8))
  14440. + (if_then_else
  14441. + (and (le (minus (match_dup 0) (pc)) (const_int 254))
  14442. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14443. + (const_int 2)
  14444. + (const_int 4))))
  14445. + (set_attr "cc" "none")])
  14446. +
  14447. +(define_insn "*beq-reverse"
  14448. + [(set (pc)
  14449. + (if_then_else (eq:CC (cc0)
  14450. + (const_int 0))
  14451. + (pc)
  14452. + (label_ref (match_operand 0 "" ""))))]
  14453. + ""
  14454. + "brne %0";
  14455. + [(set_attr "type" "branch")
  14456. + (set (attr "length")
  14457. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14458. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14459. + (const_int 2)] ; use compact branch
  14460. + (const_int 4))) ; use extended branch
  14461. + (set_attr "cc" "none")])
  14462. +
  14463. +(define_insn "*bne-reverse"
  14464. + [(set (pc)
  14465. + (if_then_else (ne:CC (cc0)
  14466. + (const_int 0))
  14467. + (pc)
  14468. + (label_ref (match_operand 0 "" ""))))]
  14469. + ""
  14470. + "breq %0";
  14471. + [(set_attr "type" "branch")
  14472. + (set (attr "length")
  14473. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
  14474. + (le (minus (pc) (match_dup 0)) (const_int 256)))
  14475. + (const_int 2)] ; use compact branch
  14476. + (const_int 4))) ; use extended branch
  14477. + (set_attr "cc" "none")])
  14478. +
  14479. +(define_insn "*b<code>-reverse"
  14480. + [(set (pc)
  14481. + (if_then_else (any_cond4:CC (cc0)
  14482. + (const_int 0))
  14483. + (pc)
  14484. + (label_ref (match_operand 0 "" ""))))]
  14485. + ""
  14486. + {
  14487. + if (TARGET_HARD_FLOAT && TARGET_ARCH_FPU && (avr32_branch_type == CMP_SF))
  14488. + return "brvs %l0\;br<invcond> %l0";
  14489. + else
  14490. + return "br<invcond> %0";
  14491. + }
  14492. + [(set_attr "type" "branch")
  14493. + (set (attr "length")
  14494. + (cond [(eq (const_int 1)(symbol_ref "TARGET_HARD_FLOAT && TARGET_ARCH_FPU"))
  14495. + (const_int 8)]
  14496. + (const_int 4)))
  14497. + (set_attr "cc" "none")])
  14498. +
  14499. +;=============================================================================
  14500. +; Conditional Add/Subtract
  14501. +;-----------------------------------------------------------------------------
  14502. +; sub{cond4} Rd, imm
  14503. +;=============================================================================
  14504. +
  14505. +
  14506. +(define_expand "add<mode>cc"
  14507. + [(set (match_operand:ADDCC 0 "register_operand" "")
  14508. + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator"
  14509. + [(match_dup 4)
  14510. + (match_dup 5)])
  14511. + (match_operand:ADDCC 2 "register_operand" "")
  14512. + (plus:ADDCC
  14513. + (match_dup 2)
  14514. + (match_operand:ADDCC 3 "" ""))))]
  14515. + ""
  14516. + {
  14517. + if ( !(GET_CODE (operands[3]) == CONST_INT
  14518. + || (TARGET_V2_INSNS && REG_P(operands[3]))) ){
  14519. + FAIL;
  14520. + }
  14521. +
  14522. + /* Delete compare instruction as it is merged into this instruction */
  14523. + remove_insn (get_last_insn_anywhere ());
  14524. +
  14525. + operands[4] = avr32_compare_op0;
  14526. + operands[5] = avr32_compare_op1;
  14527. +
  14528. + if ( TARGET_V2_INSNS
  14529. + && REG_P(operands[3])
  14530. + && REGNO(operands[0]) != REGNO(operands[2]) ){
  14531. + emit_move_insn (operands[0], operands[2]);
  14532. + operands[2] = operands[0];
  14533. + }
  14534. + }
  14535. + )
  14536. +
  14537. +(define_insn "add<ADDCC:mode>cc_cmp<CMP:mode>_reg"
  14538. + [(set (match_operand:ADDCC 0 "register_operand" "=r")
  14539. + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator"
  14540. + [(match_operand:CMP 4 "register_operand" "r")
  14541. + (match_operand:CMP 5 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")])
  14542. + (match_dup 0)
  14543. + (plus:ADDCC
  14544. + (match_operand:ADDCC 2 "register_operand" "r")
  14545. + (match_operand:ADDCC 3 "register_operand" "r"))))]
  14546. + "TARGET_V2_INSNS"
  14547. + {
  14548. + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
  14549. + return "add%i1\t%0, %2, %3";
  14550. + }
  14551. + [(set_attr "length" "8")
  14552. + (set_attr "cc" "cmp_cond_insn")])
  14553. +
  14554. +(define_insn "add<ADDCC:mode>cc_cmp<CMP:mode>"
  14555. + [(set (match_operand:ADDCC 0 "register_operand" "=r")
  14556. + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator"
  14557. + [(match_operand:CMP 4 "register_operand" "r")
  14558. + (match_operand:CMP 5 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")])
  14559. + (match_operand:ADDCC 2 "register_operand" "0")
  14560. + (plus:ADDCC
  14561. + (match_dup 2)
  14562. + (match_operand:ADDCC 3 "avr32_cond_immediate_operand" "Is08"))))]
  14563. + ""
  14564. + {
  14565. + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
  14566. + return "sub%i1\t%0, -%3";
  14567. + }
  14568. + [(set_attr "length" "8")
  14569. + (set_attr "cc" "cmp_cond_insn")])
  14570. +
  14571. +;=============================================================================
  14572. +; Conditional Move
  14573. +;-----------------------------------------------------------------------------
  14574. +; mov{cond4} Rd, (Rs/imm)
  14575. +;=============================================================================
  14576. +(define_expand "mov<mode>cc"
  14577. + [(set (match_operand:MOVCC 0 "register_operand" "")
  14578. + (if_then_else:MOVCC (match_operator 1 "avr32_comparison_operator"
  14579. + [(match_dup 4)
  14580. + (match_dup 5)])
  14581. + (match_operand:MOVCC 2 "avr32_cond_register_immediate_operand" "")
  14582. + (match_operand:MOVCC 3 "avr32_cond_register_immediate_operand" "")))]
  14583. + ""
  14584. + {
  14585. + /* Delete compare instruction as it is merged into this instruction */
  14586. + remove_insn (get_last_insn_anywhere ());
  14587. +
  14588. + operands[4] = avr32_compare_op0;
  14589. + operands[5] = avr32_compare_op1;
  14590. + }
  14591. + )
  14592. +
  14593. +
  14594. +(define_insn "mov<MOVCC:mode>cc_cmp<CMP:mode>"
  14595. + [(set (match_operand:MOVCC 0 "register_operand" "=r,r,r")
  14596. + (if_then_else:MOVCC (match_operator 1 "avr32_comparison_operator"
  14597. + [(match_operand:CMP 4 "register_operand" "r,r,r")
  14598. + (match_operand:CMP 5 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>,<CMP:cmp_constraint>,<CMP:cmp_constraint>")])
  14599. + (match_operand:MOVCC 2 "avr32_cond_register_immediate_operand" "0, rKs08,rKs08")
  14600. + (match_operand:MOVCC 3 "avr32_cond_register_immediate_operand" "rKs08,0,rKs08")))]
  14601. + ""
  14602. + {
  14603. + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
  14604. +
  14605. + switch( which_alternative ){
  14606. + case 0:
  14607. + return "mov%i1 %0, %3";
  14608. + case 1:
  14609. + return "mov%1 %0, %2";
  14610. + case 2:
  14611. + return "mov%1 %0, %2\;mov%i1 %0, %3";
  14612. + default:
  14613. + abort();
  14614. + }
  14615. +
  14616. + }
  14617. + [(set_attr "length" "8,8,12")
  14618. + (set_attr "cc" "cmp_cond_insn")])
  14619. +
  14620. +
  14621. +
  14622. +
  14623. +;;=============================================================================
  14624. +;; jump
  14625. +;;-----------------------------------------------------------------------------
  14626. +;; Jump inside a function; an unconditional branch to a label.
  14627. +;;=============================================================================
  14628. +(define_insn "jump"
  14629. + [(set (pc)
  14630. + (label_ref (match_operand 0 "" "")))]
  14631. + ""
  14632. + {
  14633. + if (get_attr_length(insn) > 4)
  14634. + return "Can't jump this far";
  14635. + return (get_attr_length(insn) == 2 ?
  14636. + "rjmp %0" : "bral %0");
  14637. + }
  14638. + [(set_attr "type" "branch")
  14639. + (set (attr "length")
  14640. + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 1022))
  14641. + (le (minus (pc) (match_dup 0)) (const_int 1024)))
  14642. + (const_int 2) ; use rjmp
  14643. + (le (match_dup 0) (const_int 1048575))
  14644. + (const_int 4)] ; use bral
  14645. + (const_int 8))) ; do something else
  14646. + (set_attr "cc" "none")])
  14647. +
  14648. +;;=============================================================================
  14649. +;; call
  14650. +;;-----------------------------------------------------------------------------
  14651. +;; Subroutine call instruction returning no value.
  14652. +;;=============================================================================
  14653. +(define_insn "call_internal"
  14654. + [(parallel [(call (mem:SI (match_operand:SI 0 "avr32_call_operand" "r,U,T,W"))
  14655. + (match_operand 1 "" ""))
  14656. + (clobber (reg:SI LR_REGNUM))])]
  14657. + ""
  14658. + {
  14659. +
  14660. + /* Check for a flashvault call. */
  14661. + if (avr32_flashvault_call (SYMBOL_REF_DECL (operands[0])))
  14662. + {
  14663. + /* Assembly is already emitted. */
  14664. + return "";
  14665. + }
  14666. +
  14667. + switch (which_alternative) {
  14668. + case 0:
  14669. + return "icall\t%0";
  14670. + case 1:
  14671. + return "rcall\t%0";
  14672. + case 2:
  14673. + return "mcall\t%0";
  14674. + case 3:
  14675. + if (TARGET_HAS_ASM_ADDR_PSEUDOS)
  14676. + return "call\t%0";
  14677. + else
  14678. + return "mcall\tr6[%0@got]";
  14679. + default:
  14680. + abort();
  14681. + }
  14682. + }
  14683. + [(set_attr "type" "call")
  14684. + (set_attr "length" "2,4,4,10")
  14685. + (set_attr "cc" "clobber")])
  14686. +
  14687. +
  14688. +(define_expand "call"
  14689. + [(parallel [(call (match_operand:SI 0 "" "")
  14690. + (match_operand 1 "" ""))
  14691. + (clobber (reg:SI LR_REGNUM))])]
  14692. + ""
  14693. + {
  14694. + rtx call_address;
  14695. + if ( GET_CODE(operands[0]) != MEM )
  14696. + FAIL;
  14697. +
  14698. + call_address = XEXP(operands[0], 0);
  14699. +
  14700. + /* If assembler supports call pseudo insn and the call address is a symbol then nothing special needs to be done. */
  14701. + if (TARGET_HAS_ASM_ADDR_PSEUDOS && (GET_CODE(call_address) == SYMBOL_REF) )
  14702. + {
  14703. + /* We must however mark the function as using the GOT if flag_pic is set, since the call insn might turn into a mcall using the GOT ptr register. */
  14704. + if (flag_pic)
  14705. + {
  14706. + crtl->uses_pic_offset_table = 1;
  14707. + emit_call_insn(gen_call_internal(call_address, operands[1]));
  14708. + DONE;
  14709. + }
  14710. + }
  14711. + else
  14712. + {
  14713. + if (flag_pic && GET_CODE(call_address) == SYMBOL_REF )
  14714. + {
  14715. + crtl->uses_pic_offset_table = 1;
  14716. + emit_call_insn(gen_call_internal(call_address, operands[1]));
  14717. + DONE;
  14718. + }
  14719. +
  14720. + if (!SYMBOL_REF_RCALL_FUNCTION_P(operands[0]) )
  14721. + {
  14722. + if (optimize_size && GET_CODE(call_address) == SYMBOL_REF )
  14723. + {
  14724. + call_address = force_const_mem(SImode, call_address);
  14725. + }
  14726. + else
  14727. + {
  14728. + call_address = force_reg(SImode, call_address);
  14729. + }
  14730. + }
  14731. + }
  14732. + emit_call_insn(gen_call_internal(call_address, operands[1]));
  14733. + DONE;
  14734. +
  14735. + }
  14736. +)
  14737. +
  14738. +;;=============================================================================
  14739. +;; call_value
  14740. +;;-----------------------------------------------------------------------------
  14741. +;; Subroutine call instruction returning a value.
  14742. +;;=============================================================================
  14743. +(define_expand "call_value"
  14744. + [(parallel [(set (match_operand:SI 0 "" "")
  14745. + (call (match_operand:SI 1 "" "")
  14746. + (match_operand 2 "" "")))
  14747. + (clobber (reg:SI LR_REGNUM))])]
  14748. + ""
  14749. + {
  14750. + rtx call_address;
  14751. + if ( GET_CODE(operands[1]) != MEM )
  14752. + FAIL;
  14753. +
  14754. + call_address = XEXP(operands[1], 0);
  14755. +
  14756. + /* Check for a flashvault call.
  14757. + if (GET_CODE (call_address) == SYMBOL_REF
  14758. + && avr32_flashvault_call (SYMBOL_REF_DECL (call_address)))
  14759. + DONE;
  14760. +
  14761. + */
  14762. +
  14763. + /* If assembler supports call pseudo insn and the call
  14764. + address is a symbol then nothing special needs to be done. */
  14765. + if ( TARGET_HAS_ASM_ADDR_PSEUDOS
  14766. + && (GET_CODE(call_address) == SYMBOL_REF) ){
  14767. + /* We must however mark the function as using the GOT if
  14768. + flag_pic is set, since the call insn might turn into
  14769. + a mcall using the GOT ptr register. */
  14770. + if ( flag_pic ) {
  14771. + crtl->uses_pic_offset_table = 1;
  14772. + emit_call_insn(gen_call_value_internal(operands[0], call_address, operands[2]));
  14773. + DONE;
  14774. + }
  14775. + } else {
  14776. + if ( flag_pic &&
  14777. + GET_CODE(call_address) == SYMBOL_REF ){
  14778. + crtl->uses_pic_offset_table = 1;
  14779. + emit_call_insn(gen_call_value_internal(operands[0], call_address, operands[2]));
  14780. + DONE;
  14781. + }
  14782. +
  14783. + if ( !SYMBOL_REF_RCALL_FUNCTION_P(operands[1]) ){
  14784. + if ( optimize_size &&
  14785. + GET_CODE(call_address) == SYMBOL_REF){
  14786. + call_address = force_const_mem(SImode, call_address);
  14787. + } else {
  14788. + call_address = force_reg(SImode, call_address);
  14789. + }
  14790. + }
  14791. + }
  14792. + emit_call_insn(gen_call_value_internal(operands[0], call_address,
  14793. + operands[2]));
  14794. + DONE;
  14795. +
  14796. + })
  14797. +
  14798. +(define_insn "call_value_internal"
  14799. + [(parallel [(set (match_operand 0 "register_operand" "=r,r,r,r")
  14800. + (call (mem:SI (match_operand:SI 1 "avr32_call_operand" "r,U,T,W"))
  14801. + (match_operand 2 "" "")))
  14802. + (clobber (reg:SI LR_REGNUM))])]
  14803. + ;; Operand 2 not used on the AVR32.
  14804. + ""
  14805. + {
  14806. + /* Check for a flashvault call. */
  14807. + if (avr32_flashvault_call (SYMBOL_REF_DECL (operands[1])))
  14808. + {
  14809. + /* Assembly is already emitted. */
  14810. + return "";
  14811. + }
  14812. +
  14813. +
  14814. + switch (which_alternative) {
  14815. + case 0:
  14816. + return "icall\t%1";
  14817. + case 1:
  14818. + return "rcall\t%1";
  14819. + case 2:
  14820. + return "mcall\t%1";
  14821. + case 3:
  14822. + if ( TARGET_HAS_ASM_ADDR_PSEUDOS )
  14823. + return "call\t%1";
  14824. + else
  14825. + return "mcall\tr6[%1@got]";
  14826. + default:
  14827. + abort();
  14828. + }
  14829. + }
  14830. + [(set_attr "type" "call")
  14831. + (set_attr "length" "2,4,4,10")
  14832. + (set_attr "cc" "call_set")])
  14833. +
  14834. +
  14835. +;;=============================================================================
  14836. +;; untyped_call
  14837. +;;-----------------------------------------------------------------------------
  14838. +;; Subrutine call instruction returning a value of any type.
  14839. +;; The code is copied from m68k.md (except gen_blockage is removed)
  14840. +;; Fixme!
  14841. +;;=============================================================================
  14842. +(define_expand "untyped_call"
  14843. + [(parallel [(call (match_operand 0 "avr32_call_operand" "")
  14844. + (const_int 0))
  14845. + (match_operand 1 "" "")
  14846. + (match_operand 2 "" "")])]
  14847. + ""
  14848. + {
  14849. + int i;
  14850. +
  14851. + emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
  14852. +
  14853. + for (i = 0; i < XVECLEN (operands[2], 0); i++) {
  14854. + rtx set = XVECEXP (operands[2], 0, i);
  14855. + emit_move_insn (SET_DEST (set), SET_SRC (set));
  14856. + }
  14857. +
  14858. + /* The optimizer does not know that the call sets the function value
  14859. + registers we stored in the result block. We avoid problems by
  14860. + claiming that all hard registers are used and clobbered at this
  14861. + point. */
  14862. + emit_insn (gen_blockage ());
  14863. +
  14864. + DONE;
  14865. + })
  14866. +
  14867. +
  14868. +;;=============================================================================
  14869. +;; return
  14870. +;;=============================================================================
  14871. +
  14872. +(define_insn "return"
  14873. + [(return)]
  14874. + "USE_RETURN_INSN (FALSE)"
  14875. + {
  14876. + avr32_output_return_instruction(TRUE, FALSE, NULL, NULL);
  14877. + return "";
  14878. + }
  14879. + [(set_attr "length" "4")
  14880. + (set_attr "type" "call")]
  14881. + )
  14882. +
  14883. +
  14884. +(define_insn "return_cond"
  14885. + [(set (pc)
  14886. + (if_then_else (match_operand 0 "avr32_comparison_operand" "")
  14887. + (return)
  14888. + (pc)))]
  14889. + "USE_RETURN_INSN (TRUE)"
  14890. + "ret%0\tr12";
  14891. + [(set_attr "type" "call")])
  14892. +
  14893. +(define_insn "return_cond_predicable"
  14894. + [(return)]
  14895. + "USE_RETURN_INSN (TRUE)"
  14896. + "ret%?\tr12";
  14897. + [(set_attr "type" "call")
  14898. + (set_attr "predicable" "yes")])
  14899. +
  14900. +
  14901. +(define_insn "return_imm"
  14902. + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
  14903. + (use (reg RETVAL_REGNUM))
  14904. + (return)])]
  14905. + "USE_RETURN_INSN (FALSE) &&
  14906. + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
  14907. + {
  14908. + avr32_output_return_instruction(TRUE, FALSE, NULL, operands[0]);
  14909. + return "";
  14910. + }
  14911. + [(set_attr "length" "4")
  14912. + (set_attr "type" "call")]
  14913. + )
  14914. +
  14915. +(define_insn "return_imm_cond"
  14916. + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
  14917. + (use (reg RETVAL_REGNUM))
  14918. + (set (pc)
  14919. + (if_then_else (match_operand 1 "avr32_comparison_operand" "")
  14920. + (return)
  14921. + (pc)))])]
  14922. + "USE_RETURN_INSN (TRUE) &&
  14923. + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
  14924. + "ret%1\t%0";
  14925. + [(set_attr "type" "call")]
  14926. + )
  14927. +
  14928. +(define_insn "return_imm_predicable"
  14929. + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
  14930. + (use (reg RETVAL_REGNUM))
  14931. + (return)])]
  14932. + "USE_RETURN_INSN (TRUE) &&
  14933. + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
  14934. + "ret%?\t%0";
  14935. + [(set_attr "type" "call")
  14936. + (set_attr "predicable" "yes")])
  14937. +
  14938. +(define_insn "return_<mode>reg"
  14939. + [(set (reg RETVAL_REGNUM) (match_operand:MOVM 0 "register_operand" "r"))
  14940. + (use (reg RETVAL_REGNUM))
  14941. + (return)]
  14942. + "USE_RETURN_INSN (TRUE)"
  14943. + "ret%?\t%0";
  14944. + [(set_attr "type" "call")
  14945. + (set_attr "predicable" "yes")])
  14946. +
  14947. +(define_insn "return_<mode>reg_cond"
  14948. + [(set (reg RETVAL_REGNUM) (match_operand:MOVM 0 "register_operand" "r"))
  14949. + (use (reg RETVAL_REGNUM))
  14950. + (set (pc)
  14951. + (if_then_else (match_operator 1 "avr32_comparison_operator"
  14952. + [(cc0) (const_int 0)])
  14953. + (return)
  14954. + (pc)))]
  14955. + "USE_RETURN_INSN (TRUE)"
  14956. + "ret%1\t%0";
  14957. + [(set_attr "type" "call")])
  14958. +
  14959. +;;=============================================================================
  14960. +;; nonlocal_goto_receiver
  14961. +;;-----------------------------------------------------------------------------
  14962. +;; For targets with a return stack we must make sure to flush the return stack
  14963. +;; since it will be corrupt after a nonlocal goto.
  14964. +;;=============================================================================
  14965. +(define_expand "nonlocal_goto_receiver"
  14966. + [(const_int 0)]
  14967. + "TARGET_RETURN_STACK"
  14968. + "
  14969. + {
  14970. + emit_insn ( gen_frs() );
  14971. + DONE;
  14972. + }
  14973. + "
  14974. + )
  14975. +
  14976. +
  14977. +;;=============================================================================
  14978. +;; builtin_setjmp_receiver
  14979. +;;-----------------------------------------------------------------------------
  14980. +;; For pic code we need to reload the pic register.
  14981. +;; For targets with a return stack we must make sure to flush the return stack
  14982. +;; since it will probably be corrupted.
  14983. +;;=============================================================================
  14984. +(define_expand "builtin_setjmp_receiver"
  14985. + [(label_ref (match_operand 0 "" ""))]
  14986. + "flag_pic"
  14987. + "
  14988. + {
  14989. + if ( TARGET_RETURN_STACK )
  14990. + emit_insn ( gen_frs() );
  14991. +
  14992. + avr32_load_pic_register ();
  14993. + DONE;
  14994. + }
  14995. + "
  14996. +)
  14997. +
  14998. +
  14999. +;;=============================================================================
  15000. +;; indirect_jump
  15001. +;;-----------------------------------------------------------------------------
  15002. +;; Jump to an address in reg or memory.
  15003. +;;=============================================================================
  15004. +(define_expand "indirect_jump"
  15005. + [(set (pc)
  15006. + (match_operand:SI 0 "general_operand" ""))]
  15007. + ""
  15008. + {
  15009. + /* One of the ops has to be in a register. */
  15010. + if ( (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS )
  15011. + && !avr32_legitimate_pic_operand_p(operands[0]) )
  15012. + operands[0] = legitimize_pic_address (operands[0], SImode, 0);
  15013. + else if ( flag_pic && avr32_address_operand(operands[0], GET_MODE(operands[0])) )
  15014. + /* If we have an address operand then this function uses the pic register. */
  15015. + crtl->uses_pic_offset_table = 1;
  15016. + })
  15017. +
  15018. +
  15019. +(define_insn "indirect_jump_internal"
  15020. + [(set (pc)
  15021. + (match_operand:SI 0 "avr32_non_rmw_general_operand" "r,m,W"))]
  15022. + ""
  15023. + {
  15024. + switch( which_alternative ){
  15025. + case 0:
  15026. + return "mov\tpc, %0";
  15027. + case 1:
  15028. + if ( avr32_const_pool_ref_operand(operands[0], GET_MODE(operands[0])) )
  15029. + return "lddpc\tpc, %0";
  15030. + else
  15031. + return "ld.w\tpc, %0";
  15032. + case 2:
  15033. + if ( flag_pic )
  15034. + return "ld.w\tpc, r6[%0@got]";
  15035. + else
  15036. + return "lda.w\tpc, %0";
  15037. + default:
  15038. + abort();
  15039. + }
  15040. + }
  15041. + [(set_attr "length" "2,4,8")
  15042. + (set_attr "type" "call,call,call")
  15043. + (set_attr "cc" "none,none,clobber")])
  15044. +
  15045. +
  15046. +
  15047. +;;=============================================================================
  15048. +;; casesi and tablejump
  15049. +;;=============================================================================
  15050. +(define_insn "tablejump_add"
  15051. + [(set (pc)
  15052. + (plus:SI (match_operand:SI 0 "register_operand" "r")
  15053. + (mult:SI (match_operand:SI 1 "register_operand" "r")
  15054. + (match_operand:SI 2 "immediate_operand" "Ku04" ))))
  15055. + (use (label_ref (match_operand 3 "" "")))]
  15056. + "flag_pic &&
  15057. + ((INTVAL(operands[2]) == 0) || (INTVAL(operands[2]) == 2) ||
  15058. + (INTVAL(operands[2]) == 4) || (INTVAL(operands[2]) == 8))"
  15059. + "add\tpc, %0, %1 << %p2"
  15060. + [(set_attr "length" "4")
  15061. + (set_attr "cc" "clobber")])
  15062. +
  15063. +(define_insn "tablejump_insn"
  15064. + [(set (pc) (match_operand:SI 0 "memory_operand" "m"))
  15065. + (use (label_ref (match_operand 1 "" "")))]
  15066. + "!flag_pic"
  15067. + "ld.w\tpc, %0"
  15068. + [(set_attr "length" "4")
  15069. + (set_attr "type" "call")
  15070. + (set_attr "cc" "none")])
  15071. +
  15072. +(define_expand "casesi"
  15073. + [(match_operand:SI 0 "register_operand" "") ; index to jump on
  15074. + (match_operand:SI 1 "const_int_operand" "") ; lower bound
  15075. + (match_operand:SI 2 "const_int_operand" "") ; total range
  15076. + (match_operand:SI 3 "" "") ; table label
  15077. + (match_operand:SI 4 "" "")] ; Out of range label
  15078. + ""
  15079. + "
  15080. + {
  15081. + rtx reg;
  15082. + rtx index = operands[0];
  15083. + rtx low_bound = operands[1];
  15084. + rtx range = operands[2];
  15085. + rtx table_label = operands[3];
  15086. + rtx oor_label = operands[4];
  15087. +
  15088. + index = force_reg ( SImode, index );
  15089. + if (low_bound != const0_rtx)
  15090. + {
  15091. + if (!avr32_const_ok_for_constraint_p(INTVAL (low_bound), 'I', \"Is21\")){
  15092. + reg = force_reg(SImode, GEN_INT (INTVAL (low_bound)));
  15093. + emit_insn (gen_subsi3 (reg, index,
  15094. + reg));
  15095. + } else {
  15096. + reg = gen_reg_rtx (SImode);
  15097. + emit_insn (gen_addsi3 (reg, index,
  15098. + GEN_INT (-INTVAL (low_bound))));
  15099. + }
  15100. + index = reg;
  15101. + }
  15102. +
  15103. + if (!avr32_const_ok_for_constraint_p (INTVAL (range), 'K', \"Ks21\"))
  15104. + range = force_reg (SImode, range);
  15105. +
  15106. + emit_cmp_and_jump_insns ( index, range, GTU, NULL_RTX, SImode, 1, oor_label );
  15107. + reg = gen_reg_rtx (SImode);
  15108. + emit_move_insn ( reg, gen_rtx_LABEL_REF (VOIDmode, table_label));
  15109. +
  15110. + if ( flag_pic )
  15111. + emit_jump_insn ( gen_tablejump_add ( reg, index, GEN_INT(4), table_label));
  15112. + else
  15113. + emit_jump_insn (
  15114. + gen_tablejump_insn ( gen_rtx_MEM ( SImode,
  15115. + gen_rtx_PLUS ( SImode,
  15116. + reg,
  15117. + gen_rtx_MULT ( SImode,
  15118. + index,
  15119. + GEN_INT(4)))),
  15120. + table_label));
  15121. + DONE;
  15122. + }"
  15123. +)
  15124. +
  15125. +
  15126. +
  15127. +(define_insn "prefetch"
  15128. + [(prefetch (match_operand:SI 0 "avr32_ks16_address_operand" "p")
  15129. + (match_operand 1 "const_int_operand" "")
  15130. + (match_operand 2 "const_int_operand" ""))]
  15131. + ""
  15132. + {
  15133. + return "pref\t%0";
  15134. + }
  15135. +
  15136. + [(set_attr "length" "4")
  15137. + (set_attr "type" "load")
  15138. + (set_attr "cc" "none")])
  15139. +
  15140. +
  15141. +
  15142. +;;=============================================================================
  15143. +;; prologue
  15144. +;;-----------------------------------------------------------------------------
  15145. +;; This pattern, if defined, emits RTL for entry to a function. The function
  15146. +;; entry i responsible for setting up the stack frame, initializing the frame
  15147. +;; pointer register, saving callee saved registers, etc.
  15148. +;;=============================================================================
  15149. +(define_expand "prologue"
  15150. + [(clobber (const_int 0))]
  15151. + ""
  15152. + "
  15153. + avr32_expand_prologue();
  15154. + DONE;
  15155. + "
  15156. + )
  15157. +
  15158. +;;=============================================================================
  15159. +;; eh_return
  15160. +;;-----------------------------------------------------------------------------
  15161. +;; This pattern, if defined, affects the way __builtin_eh_return, and
  15162. +;; thence the call frame exception handling library routines, are
  15163. +;; built. It is intended to handle non-trivial actions needed along
  15164. +;; the abnormal return path.
  15165. +;;
  15166. +;; The address of the exception handler to which the function should
  15167. +;; return is passed as operand to this pattern. It will normally need
  15168. +;; to copied by the pattern to some special register or memory
  15169. +;; location. If the pattern needs to determine the location of the
  15170. +;; target call frame in order to do so, it may use
  15171. +;; EH_RETURN_STACKADJ_RTX, if defined; it will have already been
  15172. +;; assigned.
  15173. +;;
  15174. +;; If this pattern is not defined, the default action will be to
  15175. +;; simply copy the return address to EH_RETURN_HANDLER_RTX. Either
  15176. +;; that macro or this pattern needs to be defined if call frame
  15177. +;; exception handling is to be used.
  15178. +
  15179. +;; We can't expand this before we know where the link register is stored.
  15180. +(define_insn_and_split "eh_return"
  15181. + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
  15182. + VUNSPEC_EH_RETURN)
  15183. + (clobber (match_scratch:SI 1 "=&r"))]
  15184. + ""
  15185. + "#"
  15186. + "reload_completed"
  15187. + [(const_int 0)]
  15188. + "
  15189. + {
  15190. + avr32_set_return_address (operands[0], operands[1]);
  15191. + DONE;
  15192. + }"
  15193. + )
  15194. +
  15195. +
  15196. +;;=============================================================================
  15197. +;; ffssi2
  15198. +;;-----------------------------------------------------------------------------
  15199. +(define_insn "ffssi2"
  15200. + [ (set (match_operand:SI 0 "register_operand" "=r")
  15201. + (ffs:SI (match_operand:SI 1 "register_operand" "r"))) ]
  15202. + ""
  15203. + "mov %0, %1
  15204. + brev %0
  15205. + clz %0, %0
  15206. + sub %0, -1
  15207. + cp %0, 33
  15208. + moveq %0, 0"
  15209. + [(set_attr "length" "18")
  15210. + (set_attr "cc" "clobber")]
  15211. + )
  15212. +
  15213. +
  15214. +
  15215. +;;=============================================================================
  15216. +;; swap_h
  15217. +;;-----------------------------------------------------------------------------
  15218. +(define_insn "*swap_h"
  15219. + [ (set (match_operand:SI 0 "register_operand" "=r")
  15220. + (ior:SI (ashift:SI (match_dup 0) (const_int 16))
  15221. + (lshiftrt:SI (match_dup 0) (const_int 16))))]
  15222. + ""
  15223. + "swap.h %0"
  15224. + [(set_attr "length" "2")]
  15225. + )
  15226. +
  15227. +(define_insn_and_split "bswap_16"
  15228. + [ (set (match_operand:HI 0 "avr32_bswap_operand" "=r,RKs13,r")
  15229. + (ior:HI (and:HI (lshiftrt:HI (match_operand:HI 1 "avr32_bswap_operand" "r,r,RKs13")
  15230. + (const_int 8))
  15231. + (const_int 255))
  15232. + (ashift:HI (and:HI (match_dup 1)
  15233. + (const_int 255))
  15234. + (const_int 8))))]
  15235. + ""
  15236. + {
  15237. + switch ( which_alternative ){
  15238. + case 0:
  15239. + if ( REGNO(operands[0]) == REGNO(operands[1]))
  15240. + return "swap.bh\t%0";
  15241. + else
  15242. + return "mov\t%0, %1\;swap.bh\t%0";
  15243. + case 1:
  15244. + return "stswp.h\t%0, %1";
  15245. + case 2:
  15246. + return "ldswp.sh\t%0, %1";
  15247. + default:
  15248. + abort();
  15249. + }
  15250. + }
  15251. +
  15252. + "(reload_completed &&
  15253. + REG_P(operands[0]) && REG_P(operands[1])
  15254. + && (REGNO(operands[0]) != REGNO(operands[1])))"
  15255. + [(set (match_dup 0) (match_dup 1))
  15256. + (set (match_dup 0)
  15257. + (ior:HI (and:HI (lshiftrt:HI (match_dup 0)
  15258. + (const_int 8))
  15259. + (const_int 255))
  15260. + (ashift:HI (and:HI (match_dup 0)
  15261. + (const_int 255))
  15262. + (const_int 8))))]
  15263. + ""
  15264. +
  15265. + [(set_attr "length" "4,4,4")
  15266. + (set_attr "type" "alu,store,load_rm")]
  15267. + )
  15268. +
  15269. +(define_insn_and_split "bswap_32"
  15270. + [ (set (match_operand:SI 0 "avr32_bswap_operand" "=r,RKs14,r")
  15271. + (ior:SI (ior:SI (lshiftrt:SI (and:SI (match_operand:SI 1 "avr32_bswap_operand" "r,r,RKs14")
  15272. + (const_int -16777216))
  15273. + (const_int 24))
  15274. + (lshiftrt:SI (and:SI (match_dup 1)
  15275. + (const_int 16711680))
  15276. + (const_int 8)))
  15277. + (ior:SI (ashift:SI (and:SI (match_dup 1)
  15278. + (const_int 65280))
  15279. + (const_int 8))
  15280. + (ashift:SI (and:SI (match_dup 1)
  15281. + (const_int 255))
  15282. + (const_int 24)))))]
  15283. + ""
  15284. + {
  15285. + switch ( which_alternative ){
  15286. + case 0:
  15287. + if ( REGNO(operands[0]) == REGNO(operands[1]))
  15288. + return "swap.b\t%0";
  15289. + else
  15290. + return "#";
  15291. + case 1:
  15292. + return "stswp.w\t%0, %1";
  15293. + case 2:
  15294. + return "ldswp.w\t%0, %1";
  15295. + default:
  15296. + abort();
  15297. + }
  15298. + }
  15299. + "(reload_completed &&
  15300. + REG_P(operands[0]) && REG_P(operands[1])
  15301. + && (REGNO(operands[0]) != REGNO(operands[1])))"
  15302. + [(set (match_dup 0) (match_dup 1))
  15303. + (set (match_dup 0)
  15304. + (ior:SI (ior:SI (lshiftrt:SI (and:SI (match_dup 0)
  15305. + (const_int -16777216))
  15306. + (const_int 24))
  15307. + (lshiftrt:SI (and:SI (match_dup 0)
  15308. + (const_int 16711680))
  15309. + (const_int 8)))
  15310. + (ior:SI (ashift:SI (and:SI (match_dup 0)
  15311. + (const_int 65280))
  15312. + (const_int 8))
  15313. + (ashift:SI (and:SI (match_dup 0)
  15314. + (const_int 255))
  15315. + (const_int 24)))))]
  15316. + ""
  15317. +
  15318. + [(set_attr "length" "4,4,4")
  15319. + (set_attr "type" "alu,store,load_rm")]
  15320. + )
  15321. +
  15322. +
  15323. +;;=============================================================================
  15324. +;; blockage
  15325. +;;-----------------------------------------------------------------------------
  15326. +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
  15327. +;; all of memory. This blocks insns from being moved across this point.
  15328. +
  15329. +(define_insn "blockage"
  15330. + [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
  15331. + ""
  15332. + ""
  15333. + [(set_attr "length" "0")]
  15334. +)
  15335. +
  15336. +;;=============================================================================
  15337. +;; clzsi2
  15338. +;;-----------------------------------------------------------------------------
  15339. +(define_insn "clzsi2"
  15340. + [ (set (match_operand:SI 0 "register_operand" "=r")
  15341. + (clz:SI (match_operand:SI 1 "register_operand" "r"))) ]
  15342. + ""
  15343. + "clz %0, %1"
  15344. + [(set_attr "length" "4")
  15345. + (set_attr "cc" "set_z")]
  15346. + )
  15347. +
  15348. +;;=============================================================================
  15349. +;; ctzsi2
  15350. +;;-----------------------------------------------------------------------------
  15351. +(define_insn "ctzsi2"
  15352. + [ (set (match_operand:SI 0 "register_operand" "=r,r")
  15353. + (ctz:SI (match_operand:SI 1 "register_operand" "0,r"))) ]
  15354. + ""
  15355. + "@
  15356. + brev\t%0\;clz\t%0, %0
  15357. + mov\t%0, %1\;brev\t%0\;clz\t%0, %0"
  15358. + [(set_attr "length" "8")
  15359. + (set_attr "cc" "set_z")]
  15360. + )
  15361. +
  15362. +;;=============================================================================
  15363. +;; cache instructions
  15364. +;;-----------------------------------------------------------------------------
  15365. +(define_insn "cache"
  15366. + [ (unspec_volatile [(match_operand:SI 0 "avr32_ks11_address_operand" "p")
  15367. + (match_operand:SI 1 "immediate_operand" "Ku05")] VUNSPEC_CACHE)]
  15368. + ""
  15369. + "cache %0, %1"
  15370. + [(set_attr "length" "4")]
  15371. + )
  15372. +
  15373. +(define_insn "sync"
  15374. + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku08")] VUNSPEC_SYNC)]
  15375. + ""
  15376. + "sync %0"
  15377. + [(set_attr "length" "4")]
  15378. + )
  15379. +
  15380. +;;=============================================================================
  15381. +;; TLB instructions
  15382. +;;-----------------------------------------------------------------------------
  15383. +(define_insn "tlbr"
  15384. + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBR)]
  15385. + ""
  15386. + "tlbr"
  15387. + [(set_attr "length" "2")]
  15388. + )
  15389. +
  15390. +(define_insn "tlbw"
  15391. + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBW)]
  15392. + ""
  15393. + "tlbw"
  15394. + [(set_attr "length" "2")]
  15395. + )
  15396. +
  15397. +(define_insn "tlbs"
  15398. + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBS)]
  15399. + ""
  15400. + "tlbs"
  15401. + [(set_attr "length" "2")]
  15402. + )
  15403. +
  15404. +;;=============================================================================
  15405. +;; Breakpoint instruction
  15406. +;;-----------------------------------------------------------------------------
  15407. +(define_insn "breakpoint"
  15408. + [ (unspec_volatile [(const_int 0)] VUNSPEC_BREAKPOINT)]
  15409. + ""
  15410. + "breakpoint"
  15411. + [(set_attr "length" "2")]
  15412. + )
  15413. +
  15414. +
  15415. +;;=============================================================================
  15416. +;; mtsr/mfsr instruction
  15417. +;;-----------------------------------------------------------------------------
  15418. +(define_insn "mtsr"
  15419. + [ (unspec_volatile [(match_operand 0 "immediate_operand" "i")
  15420. + (match_operand:SI 1 "register_operand" "r")] VUNSPEC_MTSR)]
  15421. + ""
  15422. + "mtsr\t%0, %1"
  15423. + [(set_attr "length" "4")]
  15424. + )
  15425. +
  15426. +(define_insn "mfsr"
  15427. + [ (set (match_operand:SI 0 "register_operand" "=r")
  15428. + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "i")] VUNSPEC_MFSR)) ]
  15429. + ""
  15430. + "mfsr\t%0, %1"
  15431. + [(set_attr "length" "4")]
  15432. + )
  15433. +
  15434. +;;=============================================================================
  15435. +;; mtdr/mfdr instruction
  15436. +;;-----------------------------------------------------------------------------
  15437. +(define_insn "mtdr"
  15438. + [ (unspec_volatile [(match_operand 0 "immediate_operand" "i")
  15439. + (match_operand:SI 1 "register_operand" "r")] VUNSPEC_MTDR)]
  15440. + ""
  15441. + "mtdr\t%0, %1"
  15442. + [(set_attr "length" "4")]
  15443. + )
  15444. +
  15445. +(define_insn "mfdr"
  15446. + [ (set (match_operand:SI 0 "register_operand" "=r")
  15447. + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "i")] VUNSPEC_MFDR)) ]
  15448. + ""
  15449. + "mfdr\t%0, %1"
  15450. + [(set_attr "length" "4")]
  15451. + )
  15452. +
  15453. +;;=============================================================================
  15454. +;; musfr
  15455. +;;-----------------------------------------------------------------------------
  15456. +(define_insn "musfr"
  15457. + [ (unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_MUSFR)]
  15458. + ""
  15459. + "musfr\t%0"
  15460. + [(set_attr "length" "2")
  15461. + (set_attr "cc" "clobber")]
  15462. + )
  15463. +
  15464. +(define_insn "mustr"
  15465. + [ (set (match_operand:SI 0 "register_operand" "=r")
  15466. + (unspec_volatile:SI [(const_int 0)] VUNSPEC_MUSTR)) ]
  15467. + ""
  15468. + "mustr\t%0"
  15469. + [(set_attr "length" "2")]
  15470. + )
  15471. +
  15472. +(define_insn "ssrf"
  15473. + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku05")] VUNSPEC_SSRF)]
  15474. + ""
  15475. + "ssrf %0"
  15476. + [(set_attr "length" "2")
  15477. + (set_attr "cc" "clobber")]
  15478. + )
  15479. +
  15480. +(define_insn "csrf"
  15481. + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku05")] VUNSPEC_CSRF)]
  15482. + ""
  15483. + "csrf %0"
  15484. + [(set_attr "length" "2")
  15485. + (set_attr "cc" "clobber")]
  15486. + )
  15487. +
  15488. +;;=============================================================================
  15489. +;; Flush Return Stack instruction
  15490. +;;-----------------------------------------------------------------------------
  15491. +(define_insn "frs"
  15492. + [ (unspec_volatile [(const_int 0)] VUNSPEC_FRS)]
  15493. + ""
  15494. + "frs"
  15495. + [(set_attr "length" "2")
  15496. + (set_attr "cc" "none")]
  15497. + )
  15498. +
  15499. +
  15500. +;;=============================================================================
  15501. +;; Saturation Round Scale instruction
  15502. +;;-----------------------------------------------------------------------------
  15503. +(define_insn "sats"
  15504. + [ (set (match_operand:SI 0 "register_operand" "+r")
  15505. + (unspec:SI [(match_dup 0)
  15506. + (match_operand 1 "immediate_operand" "Ku05")
  15507. + (match_operand 2 "immediate_operand" "Ku05")]
  15508. + UNSPEC_SATS)) ]
  15509. + "TARGET_DSP"
  15510. + "sats\t%0 >> %1, %2"
  15511. + [(set_attr "type" "alu_sat")
  15512. + (set_attr "length" "4")]
  15513. + )
  15514. +
  15515. +(define_insn "satu"
  15516. + [ (set (match_operand:SI 0 "register_operand" "+r")
  15517. + (unspec:SI [(match_dup 0)
  15518. + (match_operand 1 "immediate_operand" "Ku05")
  15519. + (match_operand 2 "immediate_operand" "Ku05")]
  15520. + UNSPEC_SATU)) ]
  15521. + "TARGET_DSP"
  15522. + "satu\t%0 >> %1, %2"
  15523. + [(set_attr "type" "alu_sat")
  15524. + (set_attr "length" "4")]
  15525. + )
  15526. +
  15527. +(define_insn "satrnds"
  15528. + [ (set (match_operand:SI 0 "register_operand" "+r")
  15529. + (unspec:SI [(match_dup 0)
  15530. + (match_operand 1 "immediate_operand" "Ku05")
  15531. + (match_operand 2 "immediate_operand" "Ku05")]
  15532. + UNSPEC_SATRNDS)) ]
  15533. + "TARGET_DSP"
  15534. + "satrnds\t%0 >> %1, %2"
  15535. + [(set_attr "type" "alu_sat")
  15536. + (set_attr "length" "4")]
  15537. + )
  15538. +
  15539. +(define_insn "satrndu"
  15540. + [ (set (match_operand:SI 0 "register_operand" "+r")
  15541. + (unspec:SI [(match_dup 0)
  15542. + (match_operand 1 "immediate_operand" "Ku05")
  15543. + (match_operand 2 "immediate_operand" "Ku05")]
  15544. + UNSPEC_SATRNDU)) ]
  15545. + "TARGET_DSP"
  15546. + "sats\t%0 >> %1, %2"
  15547. + [(set_attr "type" "alu_sat")
  15548. + (set_attr "length" "4")]
  15549. + )
  15550. +
  15551. +(define_insn "sleep"
  15552. + [(unspec_volatile [(const_int 0)] VUNSPEC_SLEEP)
  15553. + (match_operand:SI 0 "const_int_operand" "")]
  15554. + ""
  15555. + "sleep %0"
  15556. + [(set_attr "length" "1")
  15557. + (set_attr "cc" "none")
  15558. + ])
  15559. +
  15560. +(define_expand "delay_cycles"
  15561. + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")]
  15562. + VUNSPEC_DELAY_CYCLES)]
  15563. + ""
  15564. + "
  15565. + unsigned int cycles = UINTVAL (operands[0]);
  15566. + if (IN_RANGE(cycles,0x10000 ,0xFFFFFFFF))
  15567. + {
  15568. + unsigned int msb = (cycles & 0xFFFF0000);
  15569. + unsigned int shift = 16;
  15570. + msb = (msb >> shift);
  15571. + unsigned int cycles_used = (msb*0x10000);
  15572. + emit_insn (gen_delay_cycles_2 (gen_int_mode (msb, SImode)));
  15573. + cycles -= cycles_used;
  15574. + }
  15575. + if (IN_RANGE(cycles, 4, 0xFFFF))
  15576. + {
  15577. + unsigned int loop_count = (cycles/ 4);
  15578. + unsigned int cycles_used = (loop_count*4);
  15579. + emit_insn (gen_delay_cycles_1 (gen_int_mode (loop_count, SImode)));
  15580. + cycles -= cycles_used;
  15581. + }
  15582. + while (cycles >= 3)
  15583. + {
  15584. + emit_insn (gen_nop3 ());
  15585. + cycles -= 3;
  15586. + }
  15587. + if (cycles == 1 || cycles == 2)
  15588. + {
  15589. + while (cycles--)
  15590. + emit_insn (gen_nop ());
  15591. + }
  15592. + DONE;
  15593. + ")
  15594. +
  15595. +(define_insn "delay_cycles_1"
  15596. +[(unspec_volatile [(const_int 0)] VUNSPEC_DELAY_CYCLES_1)
  15597. + (match_operand:SI 0 "immediate_operand" "")
  15598. + (clobber (match_scratch:SI 1 "=&r"))]
  15599. + ""
  15600. + "mov\t%1, %0
  15601. + 1: sub\t%1, 1
  15602. + brne\t1b
  15603. + nop"
  15604. +)
  15605. +
  15606. +(define_insn "delay_cycles_2"
  15607. +[(unspec_volatile [(const_int 0)] VUNSPEC_DELAY_CYCLES_2)
  15608. + (match_operand:SI 0 "immediate_operand" "")
  15609. + (clobber (match_scratch:SI 1 "=&r"))
  15610. + (clobber (match_scratch:SI 2 "=&r"))]
  15611. + ""
  15612. + "mov\t%1, %0
  15613. + 1: mov\t%2, 16383
  15614. + 2: sub\t%2, 1
  15615. + brne\t2b
  15616. + nop
  15617. + sub\t%1, 1
  15618. + brne\t1b
  15619. + nop"
  15620. +)
  15621. +
  15622. +;; CPU instructions
  15623. +
  15624. +;;=============================================================================
  15625. +;; nop
  15626. +;;-----------------------------------------------------------------------------
  15627. +;; No-op instruction.
  15628. +;;=============================================================================
  15629. +(define_insn "nop"
  15630. + [(unspec_volatile [(const_int 0)] VUNSPEC_NOP)]
  15631. + ""
  15632. + "nop"
  15633. + [(set_attr "length" "1")
  15634. + (set_attr "type" "alu")
  15635. + (set_attr "cc" "none")])
  15636. +
  15637. +;; NOP3
  15638. +(define_insn "nop3"
  15639. + [(unspec_volatile [(const_int 0)] VUNSPEC_NOP3)]
  15640. + ""
  15641. + "rjmp\t2"
  15642. + [(set_attr "length" "3")
  15643. + (set_attr "type" "alu")
  15644. + (set_attr "cc" "none")])
  15645. +
  15646. +;; Special patterns for dealing with the constant pool
  15647. +
  15648. +(define_insn "align_4"
  15649. + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN)]
  15650. + ""
  15651. + {
  15652. + assemble_align (32);
  15653. + return "";
  15654. + }
  15655. + [(set_attr "length" "2")]
  15656. +)
  15657. +
  15658. +
  15659. +(define_insn "consttable_start"
  15660. + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_START)]
  15661. + ""
  15662. + {
  15663. + return ".cpool";
  15664. + }
  15665. + [(set_attr "length" "0")]
  15666. + )
  15667. +
  15668. +(define_insn "consttable_end"
  15669. + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
  15670. + ""
  15671. + {
  15672. + making_const_table = FALSE;
  15673. + return "";
  15674. + }
  15675. + [(set_attr "length" "0")]
  15676. +)
  15677. +
  15678. +
  15679. +(define_insn "consttable_4"
  15680. + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_4)]
  15681. + ""
  15682. + {
  15683. + making_const_table = TRUE;
  15684. + switch (GET_MODE_CLASS (GET_MODE (operands[0])))
  15685. + {
  15686. + case MODE_FLOAT:
  15687. + {
  15688. + REAL_VALUE_TYPE r;
  15689. + char real_string[1024];
  15690. + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
  15691. + real_to_decimal(real_string, &r, 1024, 0, 1);
  15692. + asm_fprintf (asm_out_file, "\t.float\t%s\n", real_string);
  15693. + break;
  15694. + }
  15695. + default:
  15696. + assemble_integer (operands[0], 4, 0, 1);
  15697. + break;
  15698. + }
  15699. + return "";
  15700. + }
  15701. + [(set_attr "length" "4")]
  15702. +)
  15703. +
  15704. +(define_insn "consttable_8"
  15705. + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_8)]
  15706. + ""
  15707. + {
  15708. + making_const_table = TRUE;
  15709. + switch (GET_MODE_CLASS (GET_MODE (operands[0])))
  15710. + {
  15711. + case MODE_FLOAT:
  15712. + {
  15713. + REAL_VALUE_TYPE r;
  15714. + char real_string[1024];
  15715. + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
  15716. + real_to_decimal(real_string, &r, 1024, 0, 1);
  15717. + asm_fprintf (asm_out_file, "\t.double\t%s\n", real_string);
  15718. + break;
  15719. + }
  15720. + default:
  15721. + assemble_integer(operands[0], 8, 0, 1);
  15722. + break;
  15723. + }
  15724. + return "";
  15725. + }
  15726. + [(set_attr "length" "8")]
  15727. +)
  15728. +
  15729. +(define_insn "consttable_16"
  15730. + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_16)]
  15731. + ""
  15732. + {
  15733. + making_const_table = TRUE;
  15734. + assemble_integer(operands[0], 16, 0, 1);
  15735. + return "";
  15736. + }
  15737. + [(set_attr "length" "16")]
  15738. +)
  15739. +
  15740. +;;=============================================================================
  15741. +;; coprocessor instructions
  15742. +;;-----------------------------------------------------------------------------
  15743. +(define_insn "cop"
  15744. + [ (unspec_volatile [(match_operand 0 "immediate_operand" "Ku03")
  15745. + (match_operand 1 "immediate_operand" "Ku04")
  15746. + (match_operand 2 "immediate_operand" "Ku04")
  15747. + (match_operand 3 "immediate_operand" "Ku04")
  15748. + (match_operand 4 "immediate_operand" "Ku07")] VUNSPEC_COP)]
  15749. + ""
  15750. + "cop\tcp%0, cr%1, cr%2, cr%3, %4"
  15751. + [(set_attr "length" "4")]
  15752. + )
  15753. +
  15754. +(define_insn "mvcrsi"
  15755. + [ (set (match_operand:SI 0 "avr32_cop_move_operand" "=r,<,Z")
  15756. + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "Ku03,Ku03,Ku03")
  15757. + (match_operand 2 "immediate_operand" "Ku04,Ku04,Ku04")]
  15758. + VUNSPEC_MVCR)) ]
  15759. + ""
  15760. + "@
  15761. + mvcr.w\tcp%1, %0, cr%2
  15762. + stcm.w\tcp%1, %0, cr%2
  15763. + stc.w\tcp%1, %0, cr%2"
  15764. + [(set_attr "length" "4")]
  15765. + )
  15766. +
  15767. +(define_insn "mvcrdi"
  15768. + [ (set (match_operand:DI 0 "avr32_cop_move_operand" "=r,<,Z")
  15769. + (unspec_volatile:DI [(match_operand 1 "immediate_operand" "Ku03,Ku03,Ku03")
  15770. + (match_operand 2 "immediate_operand" "Ku04,Ku04,Ku04")]
  15771. + VUNSPEC_MVCR)) ]
  15772. + ""
  15773. + "@
  15774. + mvcr.d\tcp%1, %0, cr%2
  15775. + stcm.d\tcp%1, %0, cr%2-cr%i2
  15776. + stc.d\tcp%1, %0, cr%2"
  15777. + [(set_attr "length" "4")]
  15778. + )
  15779. +
  15780. +(define_insn "mvrcsi"
  15781. + [ (unspec_volatile:SI [(match_operand 0 "immediate_operand" "Ku03,Ku03,Ku03")
  15782. + (match_operand 1 "immediate_operand" "Ku04,Ku04,Ku04")
  15783. + (match_operand:SI 2 "avr32_cop_move_operand" "r,>,Z")]
  15784. + VUNSPEC_MVRC)]
  15785. + ""
  15786. + {
  15787. + switch (which_alternative){
  15788. + case 0:
  15789. + return "mvrc.w\tcp%0, cr%1, %2";
  15790. + case 1:
  15791. + return "ldcm.w\tcp%0, %2, cr%1";
  15792. + case 2:
  15793. + return "ldc.w\tcp%0, cr%1, %2";
  15794. + default:
  15795. + abort();
  15796. + }
  15797. + }
  15798. + [(set_attr "length" "4")]
  15799. + )
  15800. +
  15801. +(define_insn "mvrcdi"
  15802. + [ (unspec_volatile:DI [(match_operand 0 "immediate_operand" "Ku03,Ku03,Ku03")
  15803. + (match_operand 1 "immediate_operand" "Ku04,Ku04,Ku04")
  15804. + (match_operand:DI 2 "avr32_cop_move_operand" "r,>,Z")]
  15805. + VUNSPEC_MVRC)]
  15806. + ""
  15807. + {
  15808. + switch (which_alternative){
  15809. + case 0:
  15810. + return "mvrc.d\tcp%0, cr%1, %2";
  15811. + case 1:
  15812. + return "ldcm.d\tcp%0, %2, cr%1-cr%i1";
  15813. + case 2:
  15814. + return "ldc.d\tcp%0, cr%1, %2";
  15815. + default:
  15816. + abort();
  15817. + }
  15818. + }
  15819. + [(set_attr "length" "4")]
  15820. + )
  15821. +
  15822. +;;=============================================================================
  15823. +;; epilogue
  15824. +;;-----------------------------------------------------------------------------
  15825. +;; This pattern emits RTL for exit from a function. The function exit is
  15826. +;; responsible for deallocating the stack frame, restoring callee saved
  15827. +;; registers and emitting the return instruction.
  15828. +;; ToDo: using TARGET_ASM_FUNCTION_PROLOGUE instead.
  15829. +;;=============================================================================
  15830. +(define_expand "epilogue"
  15831. + [(unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
  15832. + ""
  15833. + "
  15834. + if (USE_RETURN_INSN (FALSE)){
  15835. + emit_jump_insn (gen_return ());
  15836. + DONE;
  15837. + }
  15838. + emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
  15839. + gen_rtvec (1,
  15840. + gen_rtx_RETURN (VOIDmode)),
  15841. + VUNSPEC_EPILOGUE));
  15842. + DONE;
  15843. + "
  15844. + )
  15845. +
  15846. +(define_insn "*epilogue_insns"
  15847. + [(unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
  15848. + ""
  15849. + {
  15850. + avr32_output_return_instruction (FALSE, FALSE, NULL, NULL);
  15851. + return "";
  15852. + }
  15853. + ; Length is absolute worst case
  15854. + [(set_attr "type" "branch")
  15855. + (set_attr "length" "12")]
  15856. + )
  15857. +
  15858. +(define_insn "*epilogue_insns_ret_imm"
  15859. + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
  15860. + (use (reg RETVAL_REGNUM))
  15861. + (unspec_volatile [(return)] VUNSPEC_EPILOGUE)])]
  15862. + "((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
  15863. + {
  15864. + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[0]);
  15865. + return "";
  15866. + }
  15867. + ; Length is absolute worst case
  15868. + [(set_attr "type" "branch")
  15869. + (set_attr "length" "12")]
  15870. + )
  15871. +
  15872. +(define_insn "sibcall_epilogue"
  15873. + [(unspec_volatile [(const_int 0)] VUNSPEC_EPILOGUE)]
  15874. + ""
  15875. + {
  15876. + avr32_output_return_instruction (FALSE, FALSE, NULL, NULL);
  15877. + return "";
  15878. + }
  15879. +;; Length is absolute worst case
  15880. + [(set_attr "type" "branch")
  15881. + (set_attr "length" "12")]
  15882. + )
  15883. +
  15884. +(define_insn "*sibcall_epilogue_insns_ret_imm"
  15885. + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
  15886. + (use (reg RETVAL_REGNUM))
  15887. + (unspec_volatile [(const_int 0)] VUNSPEC_EPILOGUE)])]
  15888. + "((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
  15889. + {
  15890. + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[0]);
  15891. + return "";
  15892. + }
  15893. + ; Length is absolute worst case
  15894. + [(set_attr "type" "branch")
  15895. + (set_attr "length" "12")]
  15896. + )
  15897. +
  15898. +(define_insn "ldxi"
  15899. + [(set (match_operand:SI 0 "register_operand" "=r")
  15900. + (mem:SI (plus:SI
  15901. + (match_operand:SI 1 "register_operand" "r")
  15902. + (mult:SI (zero_extract:SI (match_operand:SI 2 "register_operand" "r")
  15903. + (const_int 8)
  15904. + (match_operand:SI 3 "immediate_operand" "Ku05"))
  15905. + (const_int 4)))))]
  15906. + "(INTVAL(operands[3]) == 24 || INTVAL(operands[3]) == 16 || INTVAL(operands[3]) == 8
  15907. + || INTVAL(operands[3]) == 0)"
  15908. + {
  15909. + switch ( INTVAL(operands[3]) ){
  15910. + case 0:
  15911. + return "ld.w %0, %1[%2:b << 2]";
  15912. + case 8:
  15913. + return "ld.w %0, %1[%2:l << 2]";
  15914. + case 16:
  15915. + return "ld.w %0, %1[%2:u << 2]";
  15916. + case 24:
  15917. + return "ld.w %0, %1[%2:t << 2]";
  15918. + default:
  15919. + internal_error("illegal operand for ldxi");
  15920. + }
  15921. + }
  15922. + [(set_attr "type" "load")
  15923. + (set_attr "length" "4")
  15924. + (set_attr "cc" "none")])
  15925. +
  15926. +
  15927. +
  15928. +
  15929. +
  15930. +
  15931. +;;=============================================================================
  15932. +;; Peephole optimizing
  15933. +;;-----------------------------------------------------------------------------
  15934. +;; Changing
  15935. +;; sub r8, r7, 8
  15936. +;; st.w r8[0x0], r12
  15937. +;; to
  15938. +;; sub r8, r7, 8
  15939. +;; st.w r7[-0x8], r12
  15940. +;;=============================================================================
  15941. +; (set (reg:SI 9 r8)
  15942. +; (plus:SI (reg/f:SI 6 r7)
  15943. +; (const_int ...)))
  15944. +; (set (mem:SI (reg:SI 9 r8))
  15945. +; (reg:SI 12 r12))
  15946. +(define_peephole2
  15947. + [(set (match_operand:SI 0 "register_operand" "")
  15948. + (plus:SI (match_operand:SI 1 "register_operand" "")
  15949. + (match_operand:SI 2 "immediate_operand" "")))
  15950. + (set (mem:SI (match_dup 0))
  15951. + (match_operand:SI 3 "register_operand" ""))]
  15952. + "REGNO(operands[0]) != REGNO(operands[1]) && avr32_const_ok_for_constraint_p(INTVAL(operands[2]), 'K', \"Ks16\")"
  15953. + [(set (match_dup 0)
  15954. + (plus:SI (match_dup 1)
  15955. + (match_dup 2)))
  15956. + (set (mem:SI (plus:SI (match_dup 1)
  15957. + (match_dup 2)))
  15958. + (match_dup 3))]
  15959. + "")
  15960. +
  15961. +;;=============================================================================
  15962. +;; Peephole optimizing
  15963. +;;-----------------------------------------------------------------------------
  15964. +;; Changing
  15965. +;; sub r6, r7, 4
  15966. +;; ld.w r6, r6[0x0]
  15967. +;; to
  15968. +;; sub r6, r7, 4
  15969. +;; ld.w r6, r7[-0x4]
  15970. +;;=============================================================================
  15971. +; (set (reg:SI 7 r6)
  15972. +; (plus:SI (reg/f:SI 6 r7)
  15973. +; (const_int -4 [0xfffffffc])))
  15974. +; (set (reg:SI 7 r6)
  15975. +; (mem:SI (reg:SI 7 r6)))
  15976. +(define_peephole2
  15977. + [(set (match_operand:SI 0 "register_operand" "")
  15978. + (plus:SI (match_operand:SI 1 "register_operand" "")
  15979. + (match_operand:SI 2 "immediate_operand" "")))
  15980. + (set (match_operand:SI 3 "register_operand" "")
  15981. + (mem:SI (match_dup 0)))]
  15982. + "REGNO(operands[0]) != REGNO(operands[1]) && avr32_const_ok_for_constraint_p(INTVAL(operands[2]), 'K', \"Ks16\")"
  15983. + [(set (match_dup 0)
  15984. + (plus:SI (match_dup 1)
  15985. + (match_dup 2)))
  15986. + (set (match_dup 3)
  15987. + (mem:SI (plus:SI (match_dup 1)
  15988. + (match_dup 2))))]
  15989. + "")
  15990. +
  15991. +;;=============================================================================
  15992. +;; Peephole optimizing
  15993. +;;-----------------------------------------------------------------------------
  15994. +;; Changing
  15995. +;; ld.sb r0, r7[-0x6]
  15996. +;; cashs.b r0
  15997. +;; to
  15998. +;; ld.sb r0, r7[-0x6]
  15999. +;;=============================================================================
  16000. +(define_peephole2
  16001. + [(set (match_operand:QI 0 "register_operand" "")
  16002. + (match_operand:QI 1 "load_sb_memory_operand" ""))
  16003. + (set (match_operand:SI 2 "register_operand" "")
  16004. + (sign_extend:SI (match_dup 0)))]
  16005. + "(REGNO(operands[0]) == REGNO(operands[2]) || peep2_reg_dead_p(2, operands[0]))"
  16006. + [(set (match_dup 2)
  16007. + (sign_extend:SI (match_dup 1)))]
  16008. + "")
  16009. +
  16010. +;;=============================================================================
  16011. +;; Peephole optimizing
  16012. +;;-----------------------------------------------------------------------------
  16013. +;; Changing
  16014. +;; ld.ub r0, r7[-0x6]
  16015. +;; cashu.b r0
  16016. +;; to
  16017. +;; ld.ub r0, r7[-0x6]
  16018. +;;=============================================================================
  16019. +(define_peephole2
  16020. + [(set (match_operand:QI 0 "register_operand" "")
  16021. + (match_operand:QI 1 "memory_operand" ""))
  16022. + (set (match_operand:SI 2 "register_operand" "")
  16023. + (zero_extend:SI (match_dup 0)))]
  16024. + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])"
  16025. + [(set (match_dup 2)
  16026. + (zero_extend:SI (match_dup 1)))]
  16027. + "")
  16028. +
  16029. +;;=============================================================================
  16030. +;; Peephole optimizing
  16031. +;;-----------------------------------------------------------------------------
  16032. +;; Changing
  16033. +;; ld.sh r0, r7[-0x6]
  16034. +;; casts.h r0
  16035. +;; to
  16036. +;; ld.sh r0, r7[-0x6]
  16037. +;;=============================================================================
  16038. +(define_peephole2
  16039. + [(set (match_operand:HI 0 "register_operand" "")
  16040. + (match_operand:HI 1 "memory_operand" ""))
  16041. + (set (match_operand:SI 2 "register_operand" "")
  16042. + (sign_extend:SI (match_dup 0)))]
  16043. + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])"
  16044. + [(set (match_dup 2)
  16045. + (sign_extend:SI (match_dup 1)))]
  16046. + "")
  16047. +
  16048. +;;=============================================================================
  16049. +;; Peephole optimizing
  16050. +;;-----------------------------------------------------------------------------
  16051. +;; Changing
  16052. +;; ld.uh r0, r7[-0x6]
  16053. +;; castu.h r0
  16054. +;; to
  16055. +;; ld.uh r0, r7[-0x6]
  16056. +;;=============================================================================
  16057. +(define_peephole2
  16058. + [(set (match_operand:HI 0 "register_operand" "")
  16059. + (match_operand:HI 1 "memory_operand" ""))
  16060. + (set (match_operand:SI 2 "register_operand" "")
  16061. + (zero_extend:SI (match_dup 0)))]
  16062. + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])"
  16063. + [(set (match_dup 2)
  16064. + (zero_extend:SI (match_dup 1)))]
  16065. + "")
  16066. +
  16067. +;;=============================================================================
  16068. +;; Peephole optimizing
  16069. +;;-----------------------------------------------------------------------------
  16070. +;; Changing
  16071. +;; mul rd, rx, ry
  16072. +;; add rd2, rd
  16073. +;; or
  16074. +;; add rd2, rd, rd2
  16075. +;; to
  16076. +;; mac rd2, rx, ry
  16077. +;;=============================================================================
  16078. +(define_peephole2
  16079. + [(set (match_operand:SI 0 "register_operand" "")
  16080. + (mult:SI (match_operand:SI 1 "register_operand" "")
  16081. + (match_operand:SI 2 "register_operand" "")))
  16082. + (set (match_operand:SI 3 "register_operand" "")
  16083. + (plus:SI (match_dup 3)
  16084. + (match_dup 0)))]
  16085. + "peep2_reg_dead_p(2, operands[0])"
  16086. + [(set (match_dup 3)
  16087. + (plus:SI (mult:SI (match_dup 1)
  16088. + (match_dup 2))
  16089. + (match_dup 3)))]
  16090. + "")
  16091. +
  16092. +(define_peephole2
  16093. + [(set (match_operand:SI 0 "register_operand" "")
  16094. + (mult:SI (match_operand:SI 1 "register_operand" "")
  16095. + (match_operand:SI 2 "register_operand" "")))
  16096. + (set (match_operand:SI 3 "register_operand" "")
  16097. + (plus:SI (match_dup 0)
  16098. + (match_dup 3)))]
  16099. + "peep2_reg_dead_p(2, operands[0])"
  16100. + [(set (match_dup 3)
  16101. + (plus:SI (mult:SI (match_dup 1)
  16102. + (match_dup 2))
  16103. + (match_dup 3)))]
  16104. + "")
  16105. +
  16106. +
  16107. +;;=============================================================================
  16108. +;; Peephole optimizing
  16109. +;;-----------------------------------------------------------------------------
  16110. +;; Changing
  16111. +;; bfextu rd, rs, k5, 1 or and(h/l) rd, one_bit_set_mask
  16112. +;; to
  16113. +;; bld rs, k5
  16114. +;;
  16115. +;; If rd is dead after the operation.
  16116. +;;=============================================================================
  16117. +(define_peephole2
  16118. + [ (set (match_operand:SI 0 "register_operand" "")
  16119. + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
  16120. + (const_int 1)
  16121. + (match_operand:SI 2 "immediate_operand" "")))
  16122. + (set (cc0)
  16123. + (match_dup 0))]
  16124. + "peep2_reg_dead_p(2, operands[0])"
  16125. + [(set (cc0)
  16126. + (and:SI (match_dup 1)
  16127. + (match_dup 2)))]
  16128. + "operands[2] = GEN_INT(1 << INTVAL(operands[2]));")
  16129. +
  16130. +(define_peephole2
  16131. + [ (set (match_operand:SI 0 "register_operand" "")
  16132. + (and:SI (match_operand:SI 1 "register_operand" "")
  16133. + (match_operand:SI 2 "one_bit_set_operand" "")))
  16134. + (set (cc0)
  16135. + (match_dup 0))]
  16136. + "peep2_reg_dead_p(2, operands[0])"
  16137. + [(set (cc0)
  16138. + (and:SI (match_dup 1)
  16139. + (match_dup 2)))]
  16140. + "")
  16141. +
  16142. +;;=============================================================================
  16143. +;; Peephole optimizing
  16144. +;;-----------------------------------------------------------------------------
  16145. +;; Load with extracted index: ld.w Rd, Rb[Ri:{t/u/b/l} << 2]
  16146. +;;
  16147. +;;=============================================================================
  16148. +
  16149. +
  16150. +(define_peephole
  16151. + [(set (match_operand:SI 0 "register_operand" "")
  16152. + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
  16153. + (const_int 8)
  16154. + (match_operand:SI 2 "avr32_extract_shift_operand" "")))
  16155. + (set (match_operand:SI 3 "register_operand" "")
  16156. + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
  16157. + (match_operand:SI 4 "register_operand" ""))))]
  16158. +
  16159. + "(dead_or_set_p(insn, operands[0]))"
  16160. + {
  16161. + switch ( INTVAL(operands[2]) ){
  16162. + case 0:
  16163. + return "ld.w %3, %4[%1:b << 2]";
  16164. + case 8:
  16165. + return "ld.w %3, %4[%1:l << 2]";
  16166. + case 16:
  16167. + return "ld.w %3, %4[%1:u << 2]";
  16168. + case 24:
  16169. + return "ld.w %3, %4[%1:t << 2]";
  16170. + default:
  16171. + internal_error("illegal operand for ldxi");
  16172. + }
  16173. + }
  16174. + [(set_attr "type" "load")
  16175. + (set_attr "length" "4")
  16176. + (set_attr "cc" "clobber")]
  16177. + )
  16178. +
  16179. +
  16180. +
  16181. +(define_peephole
  16182. + [(set (match_operand:SI 0 "register_operand" "")
  16183. + (and:SI (match_operand:SI 1 "register_operand" "") (const_int 255)))
  16184. + (set (match_operand:SI 2 "register_operand" "")
  16185. + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
  16186. + (match_operand:SI 3 "register_operand" ""))))]
  16187. +
  16188. + "(dead_or_set_p(insn, operands[0]))"
  16189. +
  16190. + "ld.w %2, %3[%1:b << 2]"
  16191. + [(set_attr "type" "load")
  16192. + (set_attr "length" "4")
  16193. + (set_attr "cc" "clobber")]
  16194. + )
  16195. +
  16196. +
  16197. +(define_peephole2
  16198. + [(set (match_operand:SI 0 "register_operand" "")
  16199. + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
  16200. + (const_int 8)
  16201. + (match_operand:SI 2 "avr32_extract_shift_operand" "")))
  16202. + (set (match_operand:SI 3 "register_operand" "")
  16203. + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
  16204. + (match_operand:SI 4 "register_operand" ""))))]
  16205. +
  16206. + "(peep2_reg_dead_p(2, operands[0]))
  16207. + || (REGNO(operands[0]) == REGNO(operands[3]))"
  16208. + [(set (match_dup 3)
  16209. + (mem:SI (plus:SI
  16210. + (match_dup 4)
  16211. + (mult:SI (zero_extract:SI (match_dup 1)
  16212. + (const_int 8)
  16213. + (match_dup 2))
  16214. + (const_int 4)))))]
  16215. + )
  16216. +
  16217. +(define_peephole2
  16218. + [(set (match_operand:SI 0 "register_operand" "")
  16219. + (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
  16220. + (set (match_operand:SI 2 "register_operand" "")
  16221. + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
  16222. + (match_operand:SI 3 "register_operand" ""))))]
  16223. +
  16224. + "(peep2_reg_dead_p(2, operands[0]))
  16225. + || (REGNO(operands[0]) == REGNO(operands[2]))"
  16226. + [(set (match_dup 2)
  16227. + (mem:SI (plus:SI
  16228. + (match_dup 3)
  16229. + (mult:SI (zero_extract:SI (match_dup 1)
  16230. + (const_int 8)
  16231. + (const_int 0))
  16232. + (const_int 4)))))]
  16233. + "operands[1] = gen_rtx_REG(SImode, REGNO(operands[1]));"
  16234. + )
  16235. +
  16236. +
  16237. +(define_peephole2
  16238. + [(set (match_operand:SI 0 "register_operand" "")
  16239. + (and:SI (match_operand:SI 1 "register_operand" "")
  16240. + (const_int 255)))
  16241. + (set (match_operand:SI 2 "register_operand" "")
  16242. + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
  16243. + (match_operand:SI 3 "register_operand" ""))))]
  16244. +
  16245. + "(peep2_reg_dead_p(2, operands[0]))
  16246. + || (REGNO(operands[0]) == REGNO(operands[2]))"
  16247. + [(set (match_dup 2)
  16248. + (mem:SI (plus:SI
  16249. + (match_dup 3)
  16250. + (mult:SI (zero_extract:SI (match_dup 1)
  16251. + (const_int 8)
  16252. + (const_int 0))
  16253. + (const_int 4)))))]
  16254. + ""
  16255. + )
  16256. +
  16257. +
  16258. +
  16259. +(define_peephole2
  16260. + [(set (match_operand:SI 0 "register_operand" "")
  16261. + (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
  16262. + (const_int 24)))
  16263. + (set (match_operand:SI 2 "register_operand" "")
  16264. + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
  16265. + (match_operand:SI 3 "register_operand" ""))))]
  16266. +
  16267. + "(peep2_reg_dead_p(2, operands[0]))
  16268. + || (REGNO(operands[0]) == REGNO(operands[2]))"
  16269. + [(set (match_dup 2)
  16270. + (mem:SI (plus:SI
  16271. + (match_dup 3)
  16272. + (mult:SI (zero_extract:SI (match_dup 1)
  16273. + (const_int 8)
  16274. + (const_int 24))
  16275. + (const_int 4)))))]
  16276. + ""
  16277. + )
  16278. +
  16279. +
  16280. +;;************************************************
  16281. +;; ANDN
  16282. +;;
  16283. +;;************************************************
  16284. +
  16285. +
  16286. +(define_peephole2
  16287. + [(set (match_operand:SI 0 "register_operand" "")
  16288. + (not:SI (match_operand:SI 1 "register_operand" "")))
  16289. + (set (match_operand:SI 2 "register_operand" "")
  16290. + (and:SI (match_dup 2)
  16291. + (match_dup 0)))]
  16292. + "peep2_reg_dead_p(2, operands[0])"
  16293. +
  16294. + [(set (match_dup 2)
  16295. + (and:SI (match_dup 2)
  16296. + (not:SI (match_dup 1))
  16297. + ))]
  16298. + ""
  16299. +)
  16300. +
  16301. +(define_peephole2
  16302. + [(set (match_operand:SI 0 "register_operand" "")
  16303. + (not:SI (match_operand:SI 1 "register_operand" "")))
  16304. + (set (match_operand:SI 2 "register_operand" "")
  16305. + (and:SI (match_dup 0)
  16306. + (match_dup 2)
  16307. + ))]
  16308. + "peep2_reg_dead_p(2, operands[0])"
  16309. +
  16310. + [(set (match_dup 2)
  16311. + (and:SI (match_dup 2)
  16312. + (not:SI (match_dup 1))
  16313. + ))]
  16314. +
  16315. + ""
  16316. +)
  16317. +
  16318. +
  16319. +;;=================================================================
  16320. +;; Addabs peephole
  16321. +;;=================================================================
  16322. +
  16323. +(define_peephole
  16324. + [(set (match_operand:SI 2 "register_operand" "=r")
  16325. + (abs:SI (match_operand:SI 1 "register_operand" "r")))
  16326. + (set (match_operand:SI 0 "register_operand" "=r")
  16327. + (plus:SI (match_operand:SI 3 "register_operand" "r")
  16328. + (match_dup 2)))]
  16329. + "dead_or_set_p(insn, operands[2])"
  16330. + "addabs %0, %3, %1"
  16331. + [(set_attr "length" "4")
  16332. + (set_attr "cc" "set_z")])
  16333. +
  16334. +(define_peephole
  16335. + [(set (match_operand:SI 2 "register_operand" "=r")
  16336. + (abs:SI (match_operand:SI 1 "register_operand" "r")))
  16337. + (set (match_operand:SI 0 "register_operand" "=r")
  16338. + (plus:SI (match_dup 2)
  16339. + (match_operand:SI 3 "register_operand" "r")))]
  16340. + "dead_or_set_p(insn, operands[2])"
  16341. + "addabs %0, %3, %1"
  16342. + [(set_attr "length" "4")
  16343. + (set_attr "cc" "set_z")])
  16344. +
  16345. +
  16346. +;;=================================================================
  16347. +;; Detect roundings
  16348. +;;=================================================================
  16349. +
  16350. +(define_insn "*round"
  16351. + [(set (match_operand:SI 0 "register_operand" "+r")
  16352. + (ashiftrt:SI (plus:SI (match_dup 0)
  16353. + (match_operand:SI 1 "immediate_operand" "i"))
  16354. + (match_operand:SI 2 "immediate_operand" "i")))]
  16355. + "avr32_rnd_operands(operands[1], operands[2])"
  16356. +
  16357. + "satrnds %0 >> %2, 31"
  16358. +
  16359. + [(set_attr "type" "alu_sat")
  16360. + (set_attr "length" "4")]
  16361. +
  16362. + )
  16363. +
  16364. +
  16365. +(define_peephole2
  16366. + [(set (match_operand:SI 0 "register_operand" "")
  16367. + (plus:SI (match_dup 0)
  16368. + (match_operand:SI 1 "immediate_operand" "")))
  16369. + (set (match_dup 0)
  16370. + (ashiftrt:SI (match_dup 0)
  16371. + (match_operand:SI 2 "immediate_operand" "")))]
  16372. + "avr32_rnd_operands(operands[1], operands[2])"
  16373. +
  16374. + [(set (match_dup 0)
  16375. + (ashiftrt:SI (plus:SI (match_dup 0)
  16376. + (match_dup 1))
  16377. + (match_dup 2)))]
  16378. + )
  16379. +
  16380. +(define_peephole
  16381. + [(set (match_operand:SI 0 "register_operand" "r")
  16382. + (plus:SI (match_dup 0)
  16383. + (match_operand:SI 1 "immediate_operand" "i")))
  16384. + (set (match_dup 0)
  16385. + (ashiftrt:SI (match_dup 0)
  16386. + (match_operand:SI 2 "immediate_operand" "i")))]
  16387. + "avr32_rnd_operands(operands[1], operands[2])"
  16388. +
  16389. + "satrnds %0 >> %2, 31"
  16390. +
  16391. + [(set_attr "type" "alu_sat")
  16392. + (set_attr "length" "4")
  16393. + (set_attr "cc" "clobber")]
  16394. +
  16395. + )
  16396. +
  16397. +
  16398. +;;=================================================================
  16399. +;; mcall
  16400. +;;=================================================================
  16401. +(define_peephole
  16402. + [(set (match_operand:SI 0 "register_operand" "")
  16403. + (match_operand 1 "avr32_const_pool_ref_operand" ""))
  16404. + (parallel [(call (mem:SI (match_dup 0))
  16405. + (match_operand 2 "" ""))
  16406. + (clobber (reg:SI LR_REGNUM))])]
  16407. + "dead_or_set_p(insn, operands[0])"
  16408. + "mcall %1"
  16409. + [(set_attr "type" "call")
  16410. + (set_attr "length" "4")
  16411. + (set_attr "cc" "clobber")]
  16412. +)
  16413. +
  16414. +(define_peephole
  16415. + [(set (match_operand:SI 2 "register_operand" "")
  16416. + (match_operand 1 "avr32_const_pool_ref_operand" ""))
  16417. + (parallel [(set (match_operand 0 "register_operand" "")
  16418. + (call (mem:SI (match_dup 2))
  16419. + (match_operand 3 "" "")))
  16420. + (clobber (reg:SI LR_REGNUM))])]
  16421. + "dead_or_set_p(insn, operands[2])"
  16422. + "mcall %1"
  16423. + [(set_attr "type" "call")
  16424. + (set_attr "length" "4")
  16425. + (set_attr "cc" "call_set")]
  16426. +)
  16427. +
  16428. +
  16429. +(define_peephole2
  16430. + [(set (match_operand:SI 0 "register_operand" "")
  16431. + (match_operand 1 "avr32_const_pool_ref_operand" ""))
  16432. + (parallel [(call (mem:SI (match_dup 0))
  16433. + (match_operand 2 "" ""))
  16434. + (clobber (reg:SI LR_REGNUM))])]
  16435. + "peep2_reg_dead_p(2, operands[0])"
  16436. + [(parallel [(call (mem:SI (match_dup 1))
  16437. + (match_dup 2))
  16438. + (clobber (reg:SI LR_REGNUM))])]
  16439. + ""
  16440. +)
  16441. +
  16442. +(define_peephole2
  16443. + [(set (match_operand:SI 0 "register_operand" "")
  16444. + (match_operand 1 "avr32_const_pool_ref_operand" ""))
  16445. + (parallel [(set (match_operand 2 "register_operand" "")
  16446. + (call (mem:SI (match_dup 0))
  16447. + (match_operand 3 "" "")))
  16448. + (clobber (reg:SI LR_REGNUM))])]
  16449. + "(peep2_reg_dead_p(2, operands[0]) || (REGNO(operands[2]) == REGNO(operands[0])))"
  16450. + [(parallel [(set (match_dup 2)
  16451. + (call (mem:SI (match_dup 1))
  16452. + (match_dup 3)))
  16453. + (clobber (reg:SI LR_REGNUM))])]
  16454. + ""
  16455. +)
  16456. +
  16457. +;;=================================================================
  16458. +;; Returning a value
  16459. +;;=================================================================
  16460. +
  16461. +
  16462. +(define_peephole
  16463. + [(set (match_operand 0 "register_operand" "")
  16464. + (match_operand 1 "register_operand" ""))
  16465. + (return)]
  16466. + "USE_RETURN_INSN (TRUE) && (REGNO(operands[0]) == RETVAL_REGNUM)
  16467. + && (REGNO(operands[1]) != LR_REGNUM)
  16468. + && (REGNO_REG_CLASS(REGNO(operands[1])) == GENERAL_REGS)"
  16469. + "retal %1"
  16470. + [(set_attr "type" "call")
  16471. + (set_attr "length" "2")]
  16472. + )
  16473. +
  16474. +
  16475. +(define_peephole
  16476. + [(set (match_operand 0 "register_operand" "r")
  16477. + (match_operand 1 "immediate_operand" "i"))
  16478. + (return)]
  16479. + "(USE_RETURN_INSN (FALSE) && (REGNO(operands[0]) == RETVAL_REGNUM) &&
  16480. + ((INTVAL(operands[1]) == -1) || (INTVAL(operands[1]) == 0) || (INTVAL(operands[1]) == 1)))"
  16481. + {
  16482. + avr32_output_return_instruction (TRUE, FALSE, NULL, operands[1]);
  16483. + return "";
  16484. + }
  16485. + [(set_attr "type" "call")
  16486. + (set_attr "length" "4")]
  16487. + )
  16488. +
  16489. +(define_peephole
  16490. + [(set (match_operand 0 "register_operand" "r")
  16491. + (match_operand 1 "immediate_operand" "i"))
  16492. + (unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
  16493. + "(REGNO(operands[0]) == RETVAL_REGNUM) &&
  16494. + ((INTVAL(operands[1]) == -1) || (INTVAL(operands[1]) == 0) || (INTVAL(operands[1]) == 1))"
  16495. + {
  16496. + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[1]);
  16497. + return "";
  16498. + }
  16499. + ; Length is absolute worst case
  16500. + [(set_attr "type" "branch")
  16501. + (set_attr "length" "12")]
  16502. + )
  16503. +
  16504. +(define_peephole
  16505. + [(set (match_operand 0 "register_operand" "=r")
  16506. + (if_then_else (match_operator 1 "avr32_comparison_operator"
  16507. + [(match_operand 4 "register_operand" "r")
  16508. + (match_operand 5 "register_immediate_operand" "rKs21")])
  16509. + (match_operand 2 "avr32_cond_register_immediate_operand" "rKs08")
  16510. + (match_operand 3 "avr32_cond_register_immediate_operand" "rKs08")))
  16511. + (return)]
  16512. + "USE_RETURN_INSN (TRUE) && (REGNO(operands[0]) == RETVAL_REGNUM)"
  16513. + {
  16514. + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
  16515. +
  16516. + if ( GET_CODE(operands[2]) == REG
  16517. + && GET_CODE(operands[3]) == REG
  16518. + && REGNO(operands[2]) != LR_REGNUM
  16519. + && REGNO(operands[3]) != LR_REGNUM ){
  16520. + return "ret%1 %2\;ret%i1 %3";
  16521. + } else if ( GET_CODE(operands[2]) == REG
  16522. + && GET_CODE(operands[3]) == CONST_INT ){
  16523. + if ( INTVAL(operands[3]) == -1
  16524. + || INTVAL(operands[3]) == 0
  16525. + || INTVAL(operands[3]) == 1 ){
  16526. + return "ret%1 %2\;ret%i1 %d3";
  16527. + } else {
  16528. + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12";
  16529. + }
  16530. + } else if ( GET_CODE(operands[2]) == CONST_INT
  16531. + && GET_CODE(operands[3]) == REG ){
  16532. + if ( INTVAL(operands[2]) == -1
  16533. + || INTVAL(operands[2]) == 0
  16534. + || INTVAL(operands[2]) == 1 ){
  16535. + return "ret%1 %d2\;ret%i1 %3";
  16536. + } else {
  16537. + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12";
  16538. + }
  16539. + } else {
  16540. + if ( (INTVAL(operands[2]) == -1
  16541. + || INTVAL(operands[2]) == 0
  16542. + || INTVAL(operands[2]) == 1 )
  16543. + && (INTVAL(operands[3]) == -1
  16544. + || INTVAL(operands[3]) == 0
  16545. + || INTVAL(operands[3]) == 1 )){
  16546. + return "ret%1 %d2\;ret%i1 %d3";
  16547. + } else {
  16548. + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12";
  16549. + }
  16550. + }
  16551. + }
  16552. +
  16553. + [(set_attr "length" "10")
  16554. + (set_attr "cc" "none")
  16555. + (set_attr "type" "call")])
  16556. +
  16557. +
  16558. +
  16559. +;;=================================================================
  16560. +;; mulnhh.w
  16561. +;;=================================================================
  16562. +
  16563. +(define_peephole2
  16564. + [(set (match_operand:HI 0 "register_operand" "")
  16565. + (neg:HI (match_operand:HI 1 "register_operand" "")))
  16566. + (set (match_operand:SI 2 "register_operand" "")
  16567. + (mult:SI
  16568. + (sign_extend:SI (match_dup 0))
  16569. + (sign_extend:SI (match_operand:HI 3 "register_operand" ""))))]
  16570. + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[2]) == REGNO(operands[0]))"
  16571. + [ (set (match_dup 2)
  16572. + (mult:SI
  16573. + (sign_extend:SI (neg:HI (match_dup 1)))
  16574. + (sign_extend:SI (match_dup 3))))]
  16575. + ""
  16576. + )
  16577. +
  16578. +(define_peephole2
  16579. + [(set (match_operand:HI 0 "register_operand" "")
  16580. + (neg:HI (match_operand:HI 1 "register_operand" "")))
  16581. + (set (match_operand:SI 2 "register_operand" "")
  16582. + (mult:SI
  16583. + (sign_extend:SI (match_operand:HI 3 "register_operand" ""))
  16584. + (sign_extend:SI (match_dup 0))))]
  16585. + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[2]) == REGNO(operands[0]))"
  16586. + [ (set (match_dup 2)
  16587. + (mult:SI
  16588. + (sign_extend:SI (neg:HI (match_dup 1)))
  16589. + (sign_extend:SI (match_dup 3))))]
  16590. + ""
  16591. + )
  16592. +
  16593. +
  16594. +
  16595. +;;=================================================================
  16596. +;; Vector set and extract operations
  16597. +;;=================================================================
  16598. +(define_insn "vec_setv2hi_hi"
  16599. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  16600. + (vec_merge:V2HI
  16601. + (match_dup 0)
  16602. + (vec_duplicate:V2HI
  16603. + (match_operand:HI 1 "register_operand" "r"))
  16604. + (const_int 1)))]
  16605. + ""
  16606. + "bfins\t%0, %1, 16, 16"
  16607. + [(set_attr "type" "alu")
  16608. + (set_attr "length" "4")
  16609. + (set_attr "cc" "clobber")])
  16610. +
  16611. +(define_insn "vec_setv2hi_lo"
  16612. + [(set (match_operand:V2HI 0 "register_operand" "+r")
  16613. + (vec_merge:V2HI
  16614. + (match_dup 0)
  16615. + (vec_duplicate:V2HI
  16616. + (match_operand:HI 1 "register_operand" "r"))
  16617. + (const_int 2)))]
  16618. + ""
  16619. + "bfins\t%0, %1, 0, 16"
  16620. + [(set_attr "type" "alu")
  16621. + (set_attr "length" "4")
  16622. + (set_attr "cc" "clobber")])
  16623. +
  16624. +(define_expand "vec_setv2hi"
  16625. + [(set (match_operand:V2HI 0 "register_operand" "")
  16626. + (vec_merge:V2HI
  16627. + (match_dup 0)
  16628. + (vec_duplicate:V2HI
  16629. + (match_operand:HI 1 "register_operand" ""))
  16630. + (match_operand 2 "immediate_operand" "")))]
  16631. + ""
  16632. + { operands[2] = GEN_INT(INTVAL(operands[2]) + 1); }
  16633. + )
  16634. +
  16635. +(define_insn "vec_extractv2hi"
  16636. + [(set (match_operand:HI 0 "register_operand" "=r")
  16637. + (vec_select:HI
  16638. + (match_operand:V2HI 1 "register_operand" "r")
  16639. + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
  16640. + ""
  16641. + {
  16642. + if ( INTVAL(operands[2]) == 0 )
  16643. + return "bfextu\t%0, %1, 16, 16";
  16644. + else
  16645. + return "bfextu\t%0, %1, 0, 16";
  16646. + }
  16647. + [(set_attr "type" "alu")
  16648. + (set_attr "length" "4")
  16649. + (set_attr "cc" "clobber")])
  16650. +
  16651. +(define_insn "vec_extractv4qi"
  16652. + [(set (match_operand:QI 0 "register_operand" "=r")
  16653. + (vec_select:QI
  16654. + (match_operand:V4QI 1 "register_operand" "r")
  16655. + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
  16656. + ""
  16657. + {
  16658. + switch ( INTVAL(operands[2]) ){
  16659. + case 0:
  16660. + return "bfextu\t%0, %1, 24, 8";
  16661. + case 1:
  16662. + return "bfextu\t%0, %1, 16, 8";
  16663. + case 2:
  16664. + return "bfextu\t%0, %1, 8, 8";
  16665. + case 3:
  16666. + return "bfextu\t%0, %1, 0, 8";
  16667. + default:
  16668. + abort();
  16669. + }
  16670. + }
  16671. + [(set_attr "type" "alu")
  16672. + (set_attr "length" "4")
  16673. + (set_attr "cc" "clobber")])
  16674. +
  16675. +
  16676. +(define_insn "concatv2hi"
  16677. + [(set (match_operand:V2HI 0 "register_operand" "=r, r, r")
  16678. + (vec_concat:V2HI
  16679. + (match_operand:HI 1 "register_operand" "r, r, 0")
  16680. + (match_operand:HI 2 "register_operand" "r, 0, r")))]
  16681. + ""
  16682. + "@
  16683. + mov\t%0, %1\;bfins\t%0, %2, 0, 16
  16684. + bfins\t%0, %2, 0, 16
  16685. + bfins\t%0, %1, 16, 16"
  16686. + [(set_attr "length" "6, 4, 4")
  16687. + (set_attr "type" "alu")])
  16688. +
  16689. +
  16690. +;; Load the atomic operation description
  16691. +(include "sync.md")
  16692. +
  16693. +;; Load the SIMD description
  16694. +(include "simd.md")
  16695. +
  16696. +;; Include the FPU for uc3
  16697. +(include "uc3fpu.md")
  16698. --- /dev/null
  16699. +++ b/gcc/config/avr32/avr32-modes.def
  16700. @@ -0,0 +1 @@
  16701. +VECTOR_MODES (INT, 4); /* V4QI V2HI */
  16702. --- /dev/null
  16703. +++ b/gcc/config/avr32/avr32.opt
  16704. @@ -0,0 +1,93 @@
  16705. +; Options for the ATMEL AVR32 port of the compiler.
  16706. +
  16707. +; Copyright 2007 Atmel Corporation.
  16708. +;
  16709. +; This file is part of GCC.
  16710. +;
  16711. +; GCC is free software; you can redistribute it and/or modify it under
  16712. +; the terms of the GNU General Public License as published by the Free
  16713. +; Software Foundation; either version 2, or (at your option) any later
  16714. +; version.
  16715. +;
  16716. +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  16717. +; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16718. +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16719. +; for more details.
  16720. +;
  16721. +; You should have received a copy of the GNU General Public License
  16722. +; along with GCC; see the file COPYING. If not, write to the Free
  16723. +; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  16724. +; 02110-1301, USA.
  16725. +
  16726. +muse-rodata-section
  16727. +Target Report Mask(USE_RODATA_SECTION)
  16728. +Use section .rodata for read-only data instead of .text.
  16729. +
  16730. +mhard-float
  16731. +Target Report Mask(HARD_FLOAT)
  16732. +Use FPU instructions instead of floating point emulation.
  16733. +
  16734. +msoft-float
  16735. +Target Report InverseMask(HARD_FLOAT, SOFT_FLOAT)
  16736. +Use floating point emulation for floating point operations.
  16737. +
  16738. +mforce-double-align
  16739. +Target Report RejectNegative Mask(FORCE_DOUBLE_ALIGN)
  16740. +Force double-word alignment for double-word memory accesses.
  16741. +
  16742. +mno-init-got
  16743. +Target Report RejectNegative Mask(NO_INIT_GOT)
  16744. +Do not initialize GOT register before using it when compiling PIC code.
  16745. +
  16746. +mrelax
  16747. +Target Report Mask(RELAX)
  16748. +Let invoked assembler and linker do relaxing (Enabled by default when optimization level is >1).
  16749. +
  16750. +mmd-reorg-opt
  16751. +Target Report Undocumented Mask(MD_REORG_OPTIMIZATION)
  16752. +Perform machine dependent optimizations in reorg stage.
  16753. +
  16754. +masm-addr-pseudos
  16755. +Target Report Mask(HAS_ASM_ADDR_PSEUDOS)
  16756. +Use assembler pseudo-instructions lda.w and call for handling direct addresses. (Enabled by default)
  16757. +
  16758. +mpart=
  16759. +Target Report RejectNegative Joined Var(avr32_part_name)
  16760. +Specify the AVR32 part name
  16761. +
  16762. +mcpu=
  16763. +Target Report RejectNegative Joined Undocumented Var(avr32_part_name)
  16764. +Specify the AVR32 part name (deprecated)
  16765. +
  16766. +march=
  16767. +Target Report RejectNegative Joined Var(avr32_arch_name)
  16768. +Specify the AVR32 architecture name
  16769. +
  16770. +mfast-float
  16771. +Target Report Mask(FAST_FLOAT)
  16772. +Enable fast floating-point library. Enabled by default if the -funsafe-math-optimizations switch is specified.
  16773. +
  16774. +mimm-in-const-pool
  16775. +Target Report Var(avr32_imm_in_const_pool) Init(-1)
  16776. +Put large immediates in constant pool. This is enabled by default for archs with insn-cache.
  16777. +
  16778. +mno-pic
  16779. +Target Report RejectNegative Mask(NO_PIC)
  16780. +Do not generate position-independent code. (deprecated, use -fno-pic instead)
  16781. +
  16782. +mcond-exec-before-reload
  16783. +Target Report Undocumented Mask(COND_EXEC_BEFORE_RELOAD)
  16784. +Enable experimental conditional execution preparation before the reload stage.
  16785. +
  16786. +mrmw-addressable-data
  16787. +Target Report Mask(RMW_ADDRESSABLE_DATA)
  16788. +Signal that all data is in range for the Atomic Read-Modify-Write memory instructions, and that
  16789. +gcc can safely generate these whenever possible.
  16790. +
  16791. +mflashvault
  16792. +Target Var(TARGET_FLASHVAULT)
  16793. +Generate code for flashvault
  16794. +
  16795. +mlist-devices
  16796. +Target RejectNegative Var(avr32_list_supported_parts)
  16797. +Print the list of parts supported while printing --target-help.
  16798. --- /dev/null
  16799. +++ b/gcc/config/avr32/avr32-protos.h
  16800. @@ -0,0 +1,196 @@
  16801. +/*
  16802. + Prototypes for exported functions defined in avr32.c
  16803. + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  16804. +
  16805. + This file is part of GCC.
  16806. +
  16807. + This program is free software; you can redistribute it and/or modify
  16808. + it under the terms of the GNU General Public License as published by
  16809. + the Free Software Foundation; either version 2 of the License, or
  16810. + (at your option) any later version.
  16811. +
  16812. + This program is distributed in the hope that it will be useful,
  16813. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  16814. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16815. + GNU General Public License for more details.
  16816. +
  16817. + You should have received a copy of the GNU General Public License
  16818. + along with this program; if not, write to the Free Software
  16819. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  16820. +
  16821. +
  16822. +#ifndef AVR32_PROTOS_H
  16823. +#define AVR32_PROTOS_H
  16824. +
  16825. +extern const int swap_reg[];
  16826. +
  16827. +extern int avr32_valid_macmac_bypass (rtx, rtx);
  16828. +extern int avr32_valid_mulmac_bypass (rtx, rtx);
  16829. +
  16830. +extern int avr32_decode_lcomm_symbol_offset (rtx, int *);
  16831. +extern void avr32_encode_lcomm_symbol_offset (tree, char *, int);
  16832. +
  16833. +extern const char *avr32_strip_name_encoding (const char *);
  16834. +
  16835. +extern rtx avr32_get_note_reg_equiv (rtx insn);
  16836. +
  16837. +extern int avr32_use_return_insn (int iscond);
  16838. +
  16839. +extern void avr32_make_reglist16 (int reglist16_vect, char *reglist16_string);
  16840. +
  16841. +extern void avr32_make_reglist8 (int reglist8_vect, char *reglist8_string);
  16842. +extern void avr32_make_fp_reglist_w (int reglist_mask, char *reglist_string);
  16843. +extern void avr32_make_fp_reglist_d (int reglist_mask, char *reglist_string);
  16844. +
  16845. +extern void avr32_output_return_instruction (int single_ret_inst,
  16846. + int iscond, rtx cond,
  16847. + rtx r12_imm);
  16848. +extern void avr32_expand_prologue (void);
  16849. +extern void avr32_set_return_address (rtx source, rtx scratch);
  16850. +
  16851. +extern int avr32_hard_regno_mode_ok (int regno, enum machine_mode mode);
  16852. +extern int avr32_extra_constraint_s (rtx value, const int strict);
  16853. +extern int avr32_eh_return_data_regno (const int n);
  16854. +extern int avr32_initial_elimination_offset (const int from, const int to);
  16855. +extern rtx avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode,
  16856. + tree type, int named);
  16857. +extern void avr32_init_cumulative_args (CUMULATIVE_ARGS * cum, tree fntype,
  16858. + rtx libname, tree fndecl);
  16859. +extern void avr32_function_arg_advance (CUMULATIVE_ARGS * cum,
  16860. + enum machine_mode mode,
  16861. + tree type, int named);
  16862. +#ifdef ARGS_SIZE_RTX
  16863. +/* expr.h defines ARGS_SIZE_RTX and `enum direction'. */
  16864. +extern enum direction avr32_function_arg_padding (enum machine_mode mode,
  16865. + tree type);
  16866. +#endif /* ARGS_SIZE_RTX */
  16867. +extern rtx avr32_function_value (tree valtype, tree func, bool outgoing);
  16868. +extern rtx avr32_libcall_value (enum machine_mode mode);
  16869. +extern int avr32_sched_use_dfa_pipeline_interface (void);
  16870. +extern bool avr32_return_in_memory (tree type, tree fntype);
  16871. +extern void avr32_regs_to_save (char *operand);
  16872. +extern void avr32_target_asm_function_prologue (FILE * file,
  16873. + HOST_WIDE_INT size);
  16874. +extern void avr32_target_asm_function_epilogue (FILE * file,
  16875. + HOST_WIDE_INT size);
  16876. +extern void avr32_trampoline_template (FILE * file);
  16877. +extern void avr32_initialize_trampoline (rtx addr, rtx fnaddr,
  16878. + rtx static_chain);
  16879. +extern int avr32_legitimate_address (enum machine_mode mode, rtx x,
  16880. + int strict);
  16881. +extern int avr32_legitimate_constant_p (rtx x);
  16882. +
  16883. +extern int avr32_legitimate_pic_operand_p (rtx x);
  16884. +
  16885. +extern rtx avr32_find_symbol (rtx x);
  16886. +extern void avr32_select_section (rtx exp, int reloc, int align);
  16887. +extern void avr32_encode_section_info (tree decl, rtx rtl, int first);
  16888. +extern void avr32_asm_file_end (FILE * stream);
  16889. +extern void avr32_asm_output_ascii (FILE * stream, char *ptr, int len);
  16890. +extern void avr32_asm_output_common (FILE * stream, const char *name,
  16891. + int size, int rounded);
  16892. +extern void avr32_asm_output_label (FILE * stream, const char *name);
  16893. +extern void avr32_asm_declare_object_name (FILE * stream, char *name,
  16894. + tree decl);
  16895. +extern void avr32_asm_globalize_label (FILE * stream, const char *name);
  16896. +extern void avr32_asm_weaken_label (FILE * stream, const char *name);
  16897. +extern void avr32_asm_output_external (FILE * stream, tree decl,
  16898. + const char *name);
  16899. +extern void avr32_asm_output_external_libcall (FILE * stream, rtx symref);
  16900. +extern void avr32_asm_output_labelref (FILE * stream, const char *name);
  16901. +extern void avr32_notice_update_cc (rtx exp, rtx insn);
  16902. +extern void avr32_print_operand (FILE * stream, rtx x, int code);
  16903. +extern void avr32_print_operand_address (FILE * stream, rtx x);
  16904. +
  16905. +extern int avr32_symbol (rtx x);
  16906. +
  16907. +extern void avr32_select_rtx_section (enum machine_mode mode, rtx x,
  16908. + unsigned HOST_WIDE_INT align);
  16909. +
  16910. +extern int avr32_load_multiple_operation (rtx op, enum machine_mode mode);
  16911. +extern int avr32_store_multiple_operation (rtx op, enum machine_mode mode);
  16912. +
  16913. +extern int avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c,
  16914. + const char *str);
  16915. +
  16916. +extern bool avr32_cannot_force_const_mem (rtx x);
  16917. +
  16918. +extern void avr32_init_builtins (void);
  16919. +
  16920. +extern rtx avr32_expand_builtin (tree exp, rtx target, rtx subtarget,
  16921. + enum machine_mode mode, int ignore);
  16922. +
  16923. +extern bool avr32_must_pass_in_stack (enum machine_mode mode, tree type);
  16924. +
  16925. +extern bool avr32_strict_argument_naming (CUMULATIVE_ARGS * ca);
  16926. +
  16927. +extern bool avr32_pass_by_reference (CUMULATIVE_ARGS * cum,
  16928. + enum machine_mode mode,
  16929. + tree type, bool named);
  16930. +
  16931. +extern rtx avr32_gen_load_multiple (rtx * regs, int count, rtx from,
  16932. + int write_back, int in_struct_p,
  16933. + int scalar_p);
  16934. +extern rtx avr32_gen_store_multiple (rtx * regs, int count, rtx to,
  16935. + int in_struct_p, int scalar_p);
  16936. +extern int avr32_gen_movmemsi (rtx * operands);
  16937. +
  16938. +extern int avr32_rnd_operands (rtx add, rtx shift);
  16939. +extern int avr32_adjust_insn_length (rtx insn, int length);
  16940. +
  16941. +extern int symbol_mentioned_p (rtx x);
  16942. +extern int label_mentioned_p (rtx x);
  16943. +extern rtx legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg);
  16944. +extern int avr32_address_register_rtx_p (rtx x, int strict_p);
  16945. +extern int avr32_legitimate_index_p (enum machine_mode mode, rtx index,
  16946. + int strict_p);
  16947. +
  16948. +extern int avr32_const_double_immediate (rtx value);
  16949. +extern void avr32_init_expanders (void);
  16950. +extern rtx avr32_return_addr (int count, rtx frame);
  16951. +extern bool avr32_got_mentioned_p (rtx addr);
  16952. +
  16953. +extern void avr32_final_prescan_insn (rtx insn, rtx * opvec, int noperands);
  16954. +
  16955. +extern int avr32_expand_movcc (enum machine_mode mode, rtx operands[]);
  16956. +extern int avr32_expand_addcc (enum machine_mode mode, rtx operands[]);
  16957. +#ifdef RTX_CODE
  16958. +extern int avr32_expand_scc (RTX_CODE cond, rtx * operands);
  16959. +#endif
  16960. +
  16961. +extern int avr32_store_bypass (rtx insn_out, rtx insn_in);
  16962. +extern int avr32_mul_waw_bypass (rtx insn_out, rtx insn_in);
  16963. +extern int avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in);
  16964. +extern int avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in);
  16965. +extern rtx avr32_output_cmp (rtx cond, enum machine_mode mode,
  16966. + rtx op0, rtx op1);
  16967. +
  16968. +rtx get_next_insn_cond (rtx cur_insn);
  16969. +int set_next_insn_cond (rtx cur_insn, rtx cond);
  16970. +rtx next_insn_emits_cmp (rtx cur_insn);
  16971. +void avr32_override_options (void);
  16972. +void avr32_load_pic_register (void);
  16973. +#ifdef GCC_BASIC_BLOCK_H
  16974. +rtx avr32_ifcvt_modify_insn (ce_if_block_t *ce_info, rtx pattern, rtx insn,
  16975. + int *num_true_changes);
  16976. +rtx avr32_ifcvt_modify_test (ce_if_block_t *ce_info, rtx test );
  16977. +void avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info, int *num_true_changes);
  16978. +#endif
  16979. +void avr32_optimization_options (int level, int size);
  16980. +int avr32_const_ok_for_move (HOST_WIDE_INT c);
  16981. +
  16982. +void avr32_split_const_expr (enum machine_mode mode,
  16983. + enum machine_mode new_mode,
  16984. + rtx expr,
  16985. + rtx *split_expr);
  16986. +void avr32_get_intval (enum machine_mode mode,
  16987. + rtx const_expr,
  16988. + HOST_WIDE_INT *val);
  16989. +
  16990. +int avr32_cond_imm_clobber_splittable (rtx insn,
  16991. + rtx operands[]);
  16992. +
  16993. +bool avr32_flashvault_call(tree decl);
  16994. +extern void avr32_emit_swdivsf (rtx, rtx, rtx);
  16995. +
  16996. +#endif /* AVR32_PROTOS_H */
  16997. --- /dev/null
  16998. +++ b/gcc/config/avr32/crti.asm
  16999. @@ -0,0 +1,64 @@
  17000. +/*
  17001. + Init/fini stuff for AVR32.
  17002. + Copyright 2003-2006 Atmel Corporation.
  17003. +
  17004. + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
  17005. +
  17006. + This file is part of GCC.
  17007. +
  17008. + This program is free software; you can redistribute it and/or modify
  17009. + it under the terms of the GNU General Public License as published by
  17010. + the Free Software Foundation; either version 2 of the License, or
  17011. + (at your option) any later version.
  17012. +
  17013. + This program is distributed in the hope that it will be useful,
  17014. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  17015. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17016. + GNU General Public License for more details.
  17017. +
  17018. + You should have received a copy of the GNU General Public License
  17019. + along with this program; if not, write to the Free Software
  17020. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  17021. +
  17022. +
  17023. +/* The code in sections .init and .fini is supposed to be a single
  17024. + regular function. The function in .init is called directly from
  17025. + start in crt1.asm. The function in .fini is atexit()ed in crt1.asm
  17026. + too.
  17027. +
  17028. + crti.asm contributes the prologue of a function to these sections,
  17029. + and crtn.asm comes up the epilogue. STARTFILE_SPEC should list
  17030. + crti.o before any other object files that might add code to .init
  17031. + or .fini sections, and ENDFILE_SPEC should list crtn.o after any
  17032. + such object files. */
  17033. +
  17034. + .file "crti.asm"
  17035. +
  17036. + .section ".init"
  17037. +/* Just load the GOT */
  17038. + .align 2
  17039. + .global _init
  17040. +_init:
  17041. + stm --sp, r6, lr
  17042. + lddpc r6, 1f
  17043. +0:
  17044. + rsub r6, pc
  17045. + rjmp 2f
  17046. + .align 2
  17047. +1: .long 0b - _GLOBAL_OFFSET_TABLE_
  17048. +2:
  17049. +
  17050. + .section ".fini"
  17051. +/* Just load the GOT */
  17052. + .align 2
  17053. + .global _fini
  17054. +_fini:
  17055. + stm --sp, r6, lr
  17056. + lddpc r6, 1f
  17057. +0:
  17058. + rsub r6, pc
  17059. + rjmp 2f
  17060. + .align 2
  17061. +1: .long 0b - _GLOBAL_OFFSET_TABLE_
  17062. +2:
  17063. +
  17064. --- /dev/null
  17065. +++ b/gcc/config/avr32/crtn.asm
  17066. @@ -0,0 +1,44 @@
  17067. +/* Copyright (C) 2001 Free Software Foundation, Inc.
  17068. + Written By Nick Clifton
  17069. +
  17070. + This file is free software; you can redistribute it and/or modify it
  17071. + under the terms of the GNU General Public License as published by the
  17072. + Free Software Foundation; either version 2, or (at your option) any
  17073. + later version.
  17074. +
  17075. + In addition to the permissions in the GNU General Public License, the
  17076. + Free Software Foundation gives you unlimited permission to link the
  17077. + compiled version of this file with other programs, and to distribute
  17078. + those programs without any restriction coming from the use of this
  17079. + file. (The General Public License restrictions do apply in other
  17080. + respects; for example, they cover modification of the file, and
  17081. + distribution when not linked into another program.)
  17082. +
  17083. + This file is distributed in the hope that it will be useful, but
  17084. + WITHOUT ANY WARRANTY; without even the implied warranty of
  17085. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17086. + General Public License for more details.
  17087. +
  17088. + You should have received a copy of the GNU General Public License
  17089. + along with this program; see the file COPYING. If not, write to
  17090. + the Free Software Foundation, 59 Temple Place - Suite 330,
  17091. + Boston, MA 02111-1307, USA.
  17092. +
  17093. + As a special exception, if you link this library with files
  17094. + compiled with GCC to produce an executable, this does not cause
  17095. + the resulting executable to be covered by the GNU General Public License.
  17096. + This exception does not however invalidate any other reasons why
  17097. + the executable file might be covered by the GNU General Public License.
  17098. +*/
  17099. +
  17100. +
  17101. +
  17102. +
  17103. + .file "crtn.asm"
  17104. +
  17105. + .section ".init"
  17106. + ldm sp++, r6, pc
  17107. +
  17108. + .section ".fini"
  17109. + ldm sp++, r6, pc
  17110. +
  17111. --- /dev/null
  17112. +++ b/gcc/config/avr32/lib1funcs.S
  17113. @@ -0,0 +1,2903 @@
  17114. +/* Macro for moving immediate value to register. */
  17115. +.macro mov_imm reg, imm
  17116. +.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm))
  17117. + mov \reg, \imm
  17118. +#if __AVR32_UC__ >= 2
  17119. +.elseif ((\imm & 0xffff) == 0)
  17120. + movh \reg, hi(\imm)
  17121. +
  17122. +#endif
  17123. +.else
  17124. + mov \reg, lo(\imm)
  17125. + orh \reg, hi(\imm)
  17126. +.endif
  17127. +.endm
  17128. +
  17129. +
  17130. +
  17131. +/* Adjust the unpacked double number if it is a subnormal number.
  17132. + The exponent and mantissa pair are stored
  17133. + in [mant_hi,mant_lo] and [exp]. A register with the correct sign bit in
  17134. + the MSB is passed in [sign]. Needs two scratch
  17135. + registers [scratch1] and [scratch2]. An adjusted and packed double float
  17136. + is present in [mant_hi,mant_lo] after macro has executed */
  17137. +.macro adjust_subnormal_df exp, mant_lo, mant_hi, sign, scratch1, scratch2
  17138. + /* We have an exponent which is <=0 indicating a subnormal number
  17139. + As it should be stored as if the exponent was 1 (although the
  17140. + exponent field is all zeros to indicate a subnormal number)
  17141. + we have to shift down the mantissa to its correct position. */
  17142. + neg \exp
  17143. + sub \exp,-1 /* amount to shift down */
  17144. + cp.w \exp,54
  17145. + brlo 50f /* if more than 53 shift steps, the
  17146. + entire mantissa will disappear
  17147. + without any rounding to occur */
  17148. + mov \mant_hi, 0
  17149. + mov \mant_lo, 0
  17150. + rjmp 52f
  17151. +50:
  17152. + sub \exp,-10 /* do the shift to position the
  17153. + mantissa at the same time
  17154. + note! this does not include the
  17155. + final 1 step shift to add the sign */
  17156. +
  17157. + /* when shifting, save all shifted out bits in [scratch2]. we may need to
  17158. + look at them to make correct rounding. */
  17159. +
  17160. + rsub \scratch1,\exp,32 /* get inverted shift count */
  17161. + cp.w \exp,32 /* handle shifts >= 32 separately */
  17162. + brhs 51f
  17163. +
  17164. + /* small (<32) shift amount, both words are part of the shift */
  17165. + lsl \scratch2,\mant_lo,\scratch1 /* save bits to shift out from lsw*/
  17166. + lsl \scratch1,\mant_hi,\scratch1 /* get bits from msw destined for lsw*/
  17167. + lsr \mant_lo,\mant_lo,\exp /* shift down lsw */
  17168. + lsr \mant_hi,\mant_hi,\exp /* shift down msw */
  17169. + or \mant_hi,\scratch1 /* add bits from msw with prepared lsw */
  17170. + rjmp 50f
  17171. +
  17172. + /* large (>=32) shift amount, only lsw will have bits left after shift.
  17173. + note that shift operations will use ((shift count) mod 32) so
  17174. + we do not need to subtract 32 from shift count. */
  17175. +51:
  17176. + lsl \scratch2,\mant_hi,\scratch1 /* save bits to shift out from msw */
  17177. + or \scratch2,\mant_lo /* also save all bits from lsw */
  17178. + mov \mant_lo,\mant_hi /* msw -> lsw (i.e. "shift 32 first") */
  17179. + mov \mant_hi,0 /* clear msw */
  17180. + lsr \mant_lo,\mant_lo,\exp /* make rest of shift inside lsw */
  17181. +
  17182. +50:
  17183. + /* result is almost ready to return, except that least significant bit
  17184. + and the part we already shifted out may cause the result to be
  17185. + rounded */
  17186. + bld \mant_lo,0 /* get bit to be shifted out */
  17187. + brcc 51f /* if bit was 0, no rounding */
  17188. +
  17189. + /* msb of part to remove is 1, so rounding depends on rest of bits */
  17190. + tst \scratch2,\scratch2 /* get shifted out tail */
  17191. + brne 50f /* if rest > 0, do round */
  17192. + bld \mant_lo,1 /* we have to look at lsb in result */
  17193. + brcc 51f /* if lsb is 0, don't round */
  17194. +
  17195. +50:
  17196. + /* subnormal result requires rounding
  17197. + rounding may cause subnormal to become smallest normal number
  17198. + luckily, smallest normal number has exactly the representation
  17199. + we got by rippling a one bit up from mantissa into exponent field. */
  17200. + sub \mant_lo,-1
  17201. + subcc \mant_hi,-1
  17202. +
  17203. +51:
  17204. + /* shift and return packed double with correct sign */
  17205. + rol \sign
  17206. + ror \mant_hi
  17207. + ror \mant_lo
  17208. +52:
  17209. +.endm
  17210. +
  17211. +
  17212. +/* Adjust subnormal single float number with exponent [exp]
  17213. + and mantissa [mant] and round. */
  17214. +.macro adjust_subnormal_sf sf, exp, mant, sign, scratch
  17215. + /* subnormal number */
  17216. + rsub \exp,\exp, 1 /* shift amount */
  17217. + cp.w \exp, 25
  17218. + movhs \mant, 0
  17219. + brhs 90f /* Return zero */
  17220. + rsub \scratch, \exp, 32
  17221. + lsl \scratch, \mant,\scratch/* Check if there are any bits set
  17222. + in the bits discarded in the mantissa */
  17223. + srne \scratch /* If so set the lsb of the shifted mantissa */
  17224. + lsr \mant,\mant,\exp /* Shift the mantissa */
  17225. + or \mant, \scratch /* Round lsb if any bits were shifted out */
  17226. + /* Rounding : For explaination, see round_sf. */
  17227. + mov \scratch, 0x7f /* Set rounding constant */
  17228. + bld \mant, 8
  17229. + subeq \scratch, -1 /* For odd numbers use rounding constant 0x80 */
  17230. + add \mant, \scratch /* Add rounding constant to mantissa */
  17231. + /* We can't overflow because mantissa is at least shifted one position
  17232. + to the right so the implicit bit is zero. We can however get the implicit
  17233. + bit set after rounding which means that we have the lowest normal number
  17234. + but this is ok since this bit has the same position as the LSB of the
  17235. + exponent */
  17236. + lsr \sf, \mant, 7
  17237. + /* Rotate in sign */
  17238. + lsl \sign, 1
  17239. + ror \sf
  17240. +90:
  17241. +.endm
  17242. +
  17243. +
  17244. +/* Round the unpacked df number with exponent [exp] and
  17245. + mantissa [mant_hi, mant_lo]. Uses scratch register
  17246. + [scratch] */
  17247. +.macro round_df exp, mant_lo, mant_hi, scratch
  17248. + mov \scratch, 0x3ff /* Rounding constant */
  17249. + bld \mant_lo,11 /* Check if lsb in the final result is
  17250. + set */
  17251. + subeq \scratch, -1 /* Adjust rounding constant to 0x400
  17252. + if rounding 0.5 upwards */
  17253. + add \mant_lo, \scratch /* Round */
  17254. + acr \mant_hi /* If overflowing we know that
  17255. + we have all zeros in the bits not
  17256. + scaled out so we can leave them
  17257. + but we must increase the exponent with
  17258. + two since we had an implicit bit
  17259. + which is lost + the extra overflow bit */
  17260. + subcs \exp, -2 /* Update exponent */
  17261. +.endm
  17262. +
  17263. +/* Round single float number stored in [mant] and [exp] */
  17264. +.macro round_sf exp, mant, scratch
  17265. + /* Round:
  17266. + For 0.5 we round to nearest even integer
  17267. + for all other cases we round to nearest integer.
  17268. + This means that if the digit left of the "point" (.)
  17269. + is 1 we can add 0x80 to the mantissa since the
  17270. + corner case 0x180 will round up to 0x200. If the
  17271. + digit left of the "point" is 0 we will have to
  17272. + add 0x7f since this will give 0xff and hence a
  17273. + truncation/rounding downwards for the corner
  17274. + case when the 9 lowest bits are 0x080 */
  17275. + mov \scratch, 0x7f /* Set rounding constant */
  17276. + /* Check if the mantissa is even or odd */
  17277. + bld \mant, 8
  17278. + subeq \scratch, -1 /* Rounding constant should be 0x80 */
  17279. + add \mant, \scratch
  17280. + subcs \exp, -2 /* Adjust exponent if we overflowed */
  17281. +.endm
  17282. +
  17283. +
  17284. +
  17285. +/* Pack a single float number stored in [mant] and [exp]
  17286. + into a single float number in [sf] */
  17287. +.macro pack_sf sf, exp, mant
  17288. + bld \mant,31 /* implicit bit to z */
  17289. + subne \exp,1 /* if subnormal (implicit bit 0)
  17290. + adjust exponent to storage format */
  17291. +
  17292. + lsr \sf, \mant, 7
  17293. + bfins \sf, \exp, 24, 8
  17294. +.endm
  17295. +
  17296. +/* Pack exponent [exp] and mantissa [mant_hi, mant_lo]
  17297. + into [df_hi, df_lo]. [df_hi] is shifted
  17298. + one bit up so the sign bit can be shifted into it */
  17299. +
  17300. +.macro pack_df exp, mant_lo, mant_hi, df_lo, df_hi
  17301. + bld \mant_hi,31 /* implicit bit to z */
  17302. + subne \exp,1 /* if subnormal (implicit bit 0)
  17303. + adjust exponent to storage format */
  17304. +
  17305. + lsr \mant_lo,11 /* shift back lsw */
  17306. + or \df_lo,\mant_lo,\mant_hi<<21 /* combine with low bits from msw */
  17307. + lsl \mant_hi,1 /* get rid of implicit bit */
  17308. + lsr \mant_hi,11 /* shift back msw except for one step*/
  17309. + or \df_hi,\mant_hi,\exp<<21 /* combine msw with exponent */
  17310. +.endm
  17311. +
  17312. +/* Normalize single float number stored in [mant] and [exp]
  17313. + using scratch register [scratch] */
  17314. +.macro normalize_sf exp, mant, scratch
  17315. + /* Adjust exponent and mantissa */
  17316. + clz \scratch, \mant
  17317. + sub \exp, \scratch
  17318. + lsl \mant, \mant, \scratch
  17319. +.endm
  17320. +
  17321. +/* Normalize the exponent and mantissa pair stored
  17322. + in [mant_hi,mant_lo] and [exp]. Needs two scratch
  17323. + registers [scratch1] and [scratch2]. */
  17324. +.macro normalize_df exp, mant_lo, mant_hi, scratch1, scratch2
  17325. + clz \scratch1,\mant_hi /* Check if we have zeros in high bits */
  17326. + breq 80f /* No need for scaling if no zeros in high bits */
  17327. + brcs 81f /* Check for all zeros */
  17328. +
  17329. + /* shift amount is smaller than 32, and involves both msw and lsw*/
  17330. + rsub \scratch2,\scratch1,32 /* shift mantissa */
  17331. + lsl \mant_hi,\mant_hi,\scratch1
  17332. + lsr \scratch2,\mant_lo,\scratch2
  17333. + or \mant_hi,\scratch2
  17334. + lsl \mant_lo,\mant_lo,\scratch1
  17335. + sub \exp,\scratch1 /* adjust exponent */
  17336. + rjmp 80f /* Finished */
  17337. +81:
  17338. + /* shift amount is greater than 32 */
  17339. + clz \scratch1,\mant_lo /* shift mantissa */
  17340. + movcs \scratch1, 0
  17341. + subcc \scratch1,-32
  17342. + lsl \mant_hi,\mant_lo,\scratch1
  17343. + mov \mant_lo,0
  17344. + sub \exp,\scratch1 /* adjust exponent */
  17345. +80:
  17346. +.endm
  17347. +
  17348. +
  17349. +/* Fast but approximate multiply of two 64-bit numbers to give a 64 bit result.
  17350. + The multiplication of [al]x[bl] is discarded.
  17351. + Operands in [ah], [al], [bh], [bl].
  17352. + Scratch registers in [sh], [sl].
  17353. + Returns results in registers [rh], [rl].*/
  17354. +.macro mul_approx_df ah, al, bh, bl, rh, rl, sh, sl
  17355. + mulu.d \sl, \ah, \bl
  17356. + macu.d \sl, \al, \bh
  17357. + mulu.d \rl, \ah, \bh
  17358. + add \rl, \sh
  17359. + acr \rh
  17360. +.endm
  17361. +
  17362. +
  17363. +
  17364. +#if defined(L_avr32_f64_mul) || defined(L_avr32_f64_mul_fast)
  17365. + .align 2
  17366. +#if defined(L_avr32_f64_mul)
  17367. + .global __avr32_f64_mul
  17368. + .type __avr32_f64_mul,@function
  17369. +__avr32_f64_mul:
  17370. +#else
  17371. + .global __avr32_f64_mul_fast
  17372. + .type __avr32_f64_mul_fast,@function
  17373. +__avr32_f64_mul_fast:
  17374. +#endif
  17375. + or r12, r10, r11 << 1
  17376. + breq __avr32_f64_mul_op1_zero
  17377. +
  17378. +#if defined(L_avr32_f64_mul)
  17379. + pushm r4-r7, lr
  17380. +#else
  17381. + stm --sp, r5,r6,r7,lr
  17382. +#endif
  17383. +
  17384. +#define AVR32_F64_MUL_OP1_INT_BITS 1
  17385. +#define AVR32_F64_MUL_OP2_INT_BITS 10
  17386. +#define AVR32_F64_MUL_RES_INT_BITS 11
  17387. +
  17388. + /* op1 in {r11,r10}*/
  17389. + /* op2 in {r9,r8}*/
  17390. + eor lr, r11, r9 /* MSB(lr) = Sign(op1) ^ Sign(op2) */
  17391. +
  17392. + /* Unpack op1 to 1.63 format*/
  17393. + /* exp: r7 */
  17394. + /* sf: r11, r10 */
  17395. + bfextu r7, r11, 20, 11 /* Extract exponent */
  17396. +
  17397. + mov r5, 1
  17398. +
  17399. + /* Check if normalization is needed */
  17400. + breq __avr32_f64_mul_op1_subnormal /*If number is subnormal, normalize it */
  17401. +
  17402. + lsl r11, (12-AVR32_F64_MUL_OP1_INT_BITS-1) /* Extract mantissa, leave room for implicit bit */
  17403. + or r11, r11, r10>>(32-(12-AVR32_F64_MUL_OP1_INT_BITS-1))
  17404. + lsl r10, (12-AVR32_F64_MUL_OP1_INT_BITS-1)
  17405. + bfins r11, r5, 32 - (1 + AVR32_F64_MUL_OP1_INT_BITS), 1 + AVR32_F64_MUL_OP1_INT_BITS /* Insert implicit bit */
  17406. +
  17407. +
  17408. +22:
  17409. + /* Unpack op2 to 10.54 format */
  17410. + /* exp: r6 */
  17411. + /* sf: r9, r8 */
  17412. + bfextu r6, r9, 20, 11 /* Extract exponent */
  17413. +
  17414. + /* Check if normalization is needed */
  17415. + breq __avr32_f64_mul_op2_subnormal /*If number is subnormal, normalize it */
  17416. +
  17417. + lsl r8, 1 /* Extract mantissa, leave room for implicit bit */
  17418. + rol r9
  17419. + bfins r9, r5, 32 - (1 + AVR32_F64_MUL_OP2_INT_BITS), 1 + AVR32_F64_MUL_OP2_INT_BITS /* Insert implicit bit */
  17420. +
  17421. +23:
  17422. +
  17423. + /* Check if any operands are NaN or INF */
  17424. + cp r7, 0x7ff
  17425. + breq __avr32_f64_mul_op_nan_or_inf /* Check op1 for NaN or Inf */
  17426. + cp r6, 0x7ff
  17427. + breq __avr32_f64_mul_op_nan_or_inf /* Check op2 for NaN or Inf */
  17428. +
  17429. +
  17430. + /* Calculate new exponent in r12*/
  17431. + add r12, r7, r6
  17432. + sub r12, (1023-1)
  17433. +
  17434. +#if defined(L_avr32_f64_mul)
  17435. + /* Do the multiplication.
  17436. + Place result in [r11, r10, r7, r6]. The result is in 11.117 format. */
  17437. + mulu.d r4, r11, r8
  17438. + macu.d r4, r10, r9
  17439. + mulu.d r6, r10, r8
  17440. + mulu.d r10, r11, r9
  17441. + add r7, r4
  17442. + adc r10, r10, r5
  17443. + acr r11
  17444. +#else
  17445. + /* Do the multiplication using approximate calculation. discard the al x bl
  17446. + calculation.
  17447. + Place result in [r11, r10, r7]. The result is in 11.85 format. */
  17448. +
  17449. + /* Do the multiplication using approximate calculation.
  17450. + Place result in r11, r10. Use r7, r6 as scratch registers */
  17451. + mulu.d r6, r11, r8
  17452. + macu.d r6, r10, r9
  17453. + mulu.d r10, r11, r9
  17454. + add r10, r7
  17455. + acr r11
  17456. +#endif
  17457. + /* Adjust exponent and mantissa */
  17458. + /* [r12]:exp, [r11, r10]:mant [r7, r6]:sticky bits */
  17459. + /* Mantissa may be of the format 00000000000.0xxx or 00000000000.1xxx. */
  17460. + /* In the first case, shift one pos to left.*/
  17461. + bld r11, 32-AVR32_F64_MUL_RES_INT_BITS-1
  17462. + breq 0f
  17463. + lsl r7, 1
  17464. + rol r10
  17465. + rol r11
  17466. + sub r12, 1
  17467. +0:
  17468. + cp r12, 0
  17469. + brle __avr32_f64_mul_res_subnormal /*Result was subnormal.*/
  17470. +
  17471. + /* Check for Inf. */
  17472. + cp.w r12, 0x7ff
  17473. + brge __avr32_f64_mul_res_inf
  17474. +
  17475. + /* Insert exponent. */
  17476. + bfins r11, r12, 20, 11
  17477. +
  17478. + /* Result was not subnormal. Perform rounding. */
  17479. + /* For the fast version we discard the sticky bits and always round
  17480. + the halfwaycase up. */
  17481. +24:
  17482. +#if defined(L_avr32_f64_mul)
  17483. + or r6, r6, r10 << 31 /* Or in parity bit into stickybits */
  17484. + or r7, r7, r6 >> 1 /* Or together sticky and still make the msb
  17485. + of r7 represent the halfway bit. */
  17486. + eorh r7, 0x8000 /* Toggle halfway bit. */
  17487. + /* We should now round up by adding one for the following cases:
  17488. +
  17489. + halfway sticky|parity round-up
  17490. + 0 x no
  17491. + 1 0 no
  17492. + 1 1 yes
  17493. +
  17494. + Since we have inverted the halfway bit we can use the satu instruction
  17495. + by saturating to 1 bit to implement this.
  17496. + */
  17497. + satu r7 >> 0, 1
  17498. +#else
  17499. + lsr r7, 31
  17500. +#endif
  17501. + add r10, r7
  17502. + acr r11
  17503. +
  17504. + /* Insert sign bit*/
  17505. + bld lr, 31
  17506. + bst r11, 31
  17507. +
  17508. + /* Return result in [r11,r10] */
  17509. +#if defined(L_avr32_f64_mul)
  17510. + popm r4-r7, pc
  17511. +#else
  17512. + ldm sp++, r5, r6, r7,pc
  17513. +#endif
  17514. +
  17515. +
  17516. +__avr32_f64_mul_op1_subnormal:
  17517. + andh r11, 0x000f /* Remove sign bit and exponent */
  17518. + clz r12, r10 /* Count leading zeros in lsw */
  17519. + clz r6, r11 /* Count leading zeros in msw */
  17520. + subcs r12, -32 + AVR32_F64_MUL_OP1_INT_BITS
  17521. + movcs r6, r12
  17522. + subcc r6, AVR32_F64_MUL_OP1_INT_BITS
  17523. + cp.w r6, 32
  17524. + brge 0f
  17525. +
  17526. + /* shifting involves both msw and lsw*/
  17527. + rsub r12, r6, 32 /* shift mantissa */
  17528. + lsl r11, r11, r6
  17529. + lsr r12, r10, r12
  17530. + or r11, r12
  17531. + lsl r10, r10, r6
  17532. + sub r6, 12-AVR32_F64_MUL_OP1_INT_BITS
  17533. + sub r7, r6 /* adjust exponent */
  17534. + rjmp 22b /* Finished */
  17535. +0:
  17536. + /* msw is zero so only need to consider lsw */
  17537. + lsl r11, r10, r6
  17538. + breq __avr32_f64_mul_res_zero
  17539. + mov r10, 0
  17540. + sub r6, 12-AVR32_F64_MUL_OP1_INT_BITS
  17541. + sub r7, r6 /* adjust exponent */
  17542. + rjmp 22b
  17543. +
  17544. +
  17545. +__avr32_f64_mul_op2_subnormal:
  17546. + andh r9, 0x000f /* Remove sign bit and exponent */
  17547. + clz r12, r8 /* Count leading zeros in lsw */
  17548. + clz r5, r9 /* Count leading zeros in msw */
  17549. + subcs r12, -32 + AVR32_F64_MUL_OP2_INT_BITS
  17550. + movcs r5, r12
  17551. + subcc r5, AVR32_F64_MUL_OP2_INT_BITS
  17552. + cp.w r5, 32
  17553. + brge 0f
  17554. +
  17555. + /* shifting involves both msw and lsw*/
  17556. + rsub r12, r5, 32 /* shift mantissa */
  17557. + lsl r9, r9, r5
  17558. + lsr r12, r8, r12
  17559. + or r9, r12
  17560. + lsl r8, r8, r5
  17561. + sub r5, 12 - AVR32_F64_MUL_OP2_INT_BITS
  17562. + sub r6, r5 /* adjust exponent */
  17563. + rjmp 23b /* Finished */
  17564. +0:
  17565. + /* msw is zero so only need to consider lsw */
  17566. + lsl r9, r8, r5
  17567. + breq __avr32_f64_mul_res_zero
  17568. + mov r8, 0
  17569. + sub r5, 12 - AVR32_F64_MUL_OP2_INT_BITS
  17570. + sub r6, r5 /* adjust exponent */
  17571. + rjmp 23b
  17572. +
  17573. +
  17574. +__avr32_f64_mul_op_nan_or_inf:
  17575. + /* Same code for OP1 and OP2*/
  17576. + /* Since we are here, at least one of the OPs were NaN or INF*/
  17577. + andh r9, 0x000f /* Remove sign bit and exponent */
  17578. + andh r11, 0x000f /* Remove sign bit and exponent */
  17579. + /* Merge the regs in each operand to check for zero*/
  17580. + or r11, r10 /* op1 */
  17581. + or r9, r8 /* op2 */
  17582. + /* Check if op1 is NaN or INF */
  17583. + cp r7, 0x7ff
  17584. + brne __avr32_f64_mul_op1_not_naninf
  17585. + /* op1 was NaN or INF.*/
  17586. + cp r11, 0
  17587. + brne __avr32_f64_mul_res_nan /* op1 was NaN. Result will be NaN*/
  17588. + /*op1 was INF. check if op2 is NaN or INF*/
  17589. + cp r6, 0x7ff
  17590. + brne __avr32_f64_mul_res_inf /*op1 was INF, op2 was neither NaN nor INF*/
  17591. + /* op1 is INF, op2 is either NaN or INF*/
  17592. + cp r9, 0
  17593. + breq __avr32_f64_mul_res_inf /*op2 was also INF*/
  17594. + rjmp __avr32_f64_mul_res_nan /*op2 was NaN*/
  17595. +
  17596. +__avr32_f64_mul_op1_not_naninf:
  17597. + /* op1 was not NaN nor INF. Then op2 must be NaN or INF*/
  17598. + cp r9, 0
  17599. + breq __avr32_f64_mul_res_inf /*op2 was INF, return INF*/
  17600. + rjmp __avr32_f64_mul_res_nan /*else return NaN*/
  17601. +
  17602. +__avr32_f64_mul_res_subnormal:/* Multiply result was subnormal. */
  17603. +#if defined(L_avr32_f64_mul)
  17604. + /* Check how much we must scale down the mantissa. */
  17605. + neg r12
  17606. + sub r12, -1 /* We do no longer have an implicit bit. */
  17607. + satu r12 >> 0, 6 /* Saturate shift amount to max 63. */
  17608. + cp.w r12, 32
  17609. + brge 0f
  17610. + /* Shift amount <32 */
  17611. + rsub r8, r12, 32
  17612. + or r6, r7
  17613. + lsr r7, r7, r12
  17614. + lsl r9, r10, r8
  17615. + or r7, r9
  17616. + lsr r10, r10, r12
  17617. + lsl r9, r11, r8
  17618. + or r10, r9
  17619. + lsr r11, r11, r12
  17620. + rjmp 24b
  17621. +0:
  17622. + /* Shift amount >=32 */
  17623. + rsub r8, r12, 32
  17624. + moveq r9, 0
  17625. + breq 0f
  17626. + lsl r9, r11, r8
  17627. +0:
  17628. + or r6, r7
  17629. + or r6, r6, r10 << 1
  17630. + lsr r10, r10, r12
  17631. + or r7, r9, r10
  17632. + lsr r10, r11, r12
  17633. + mov r11, 0
  17634. + rjmp 24b
  17635. +#else
  17636. + /* Flush to zero for the fast version. */
  17637. + mov r11, lr /*Get correct sign*/
  17638. + andh r11, 0x8000, COH
  17639. + mov r10, 0
  17640. + ldm sp++, r5, r6, r7,pc
  17641. +#endif
  17642. +
  17643. +__avr32_f64_mul_res_zero:/* Multiply result is zero. */
  17644. + mov r11, lr /*Get correct sign*/
  17645. + andh r11, 0x8000, COH
  17646. + mov r10, 0
  17647. +#if defined(L_avr32_f64_mul)
  17648. + popm r4-r7, pc
  17649. +#else
  17650. + ldm sp++, r5, r6, r7,pc
  17651. +#endif
  17652. +
  17653. +__avr32_f64_mul_res_nan: /* Return NaN. */
  17654. + mov r11, -1
  17655. + mov r10, -1
  17656. +#if defined(L_avr32_f64_mul)
  17657. + popm r4-r7, pc
  17658. +#else
  17659. + ldm sp++, r5, r6, r7,pc
  17660. +#endif
  17661. +
  17662. +__avr32_f64_mul_res_inf: /* Return INF. */
  17663. + mov r11, 0xfff00000
  17664. + bld lr, 31
  17665. + bst r11, 31
  17666. + mov r10, 0
  17667. +#if defined(L_avr32_f64_mul)
  17668. + popm r4-r7, pc
  17669. +#else
  17670. + ldm sp++, r5, r6, r7,pc
  17671. +#endif
  17672. +
  17673. +__avr32_f64_mul_op1_zero:
  17674. + /* Get sign */
  17675. + eor r11, r11, r9
  17676. + andh r11, 0x8000, COH
  17677. + /* Check if op2 is Inf or NaN. */
  17678. + bfextu r12, r9, 20, 11
  17679. + cp.w r12, 0x7ff
  17680. + retne r12 /* Return 0.0 */
  17681. + /* Return NaN */
  17682. + mov r10, -1
  17683. + mov r11, -1
  17684. + ret r12
  17685. +
  17686. +
  17687. +
  17688. +#endif
  17689. +
  17690. +
  17691. +#if defined(L_avr32_f64_addsub) || defined(L_avr32_f64_addsub_fast)
  17692. + .align 2
  17693. +
  17694. +__avr32_f64_sub_from_add:
  17695. + /* Switch sign on op2 */
  17696. + eorh r9, 0x8000
  17697. +
  17698. +#if defined(L_avr32_f64_addsub_fast)
  17699. + .global __avr32_f64_sub_fast
  17700. + .type __avr32_f64_sub_fast,@function
  17701. +__avr32_f64_sub_fast:
  17702. +#else
  17703. + .global __avr32_f64_sub
  17704. + .type __avr32_f64_sub,@function
  17705. +__avr32_f64_sub:
  17706. +#endif
  17707. +
  17708. + /* op1 in {r11,r10}*/
  17709. + /* op2 in {r9,r8}*/
  17710. +
  17711. +#if defined(L_avr32_f64_addsub_fast)
  17712. + /* If op2 is zero just return op1 */
  17713. + or r12, r8, r9 << 1
  17714. + reteq r12
  17715. +#endif
  17716. +
  17717. + /* Check signs */
  17718. + eor r12, r11, r9
  17719. + /* Different signs, use addition. */
  17720. + brmi __avr32_f64_add_from_sub
  17721. +
  17722. + stm --sp, r5, r6, r7, lr
  17723. +
  17724. + /* Get sign of op1 into r12 */
  17725. + mov r12, r11
  17726. + andh r12, 0x8000, COH
  17727. +
  17728. + /* Remove sign from operands */
  17729. + cbr r11, 31
  17730. + cbr r9, 31
  17731. +
  17732. + /* Put the largest number in [r11, r10]
  17733. + and the smallest number in [r9, r8] */
  17734. + cp r10, r8
  17735. + cpc r11, r9
  17736. + brhs 1f /* Skip swap if operands already correctly ordered*/
  17737. + /* Operands were not correctly ordered, swap them*/
  17738. + mov r7, r11
  17739. + mov r11, r9
  17740. + mov r9, r7
  17741. + mov r7, r10
  17742. + mov r10, r8
  17743. + mov r8, r7
  17744. + eorh r12, 0x8000 /* Invert sign in r12*/
  17745. +1:
  17746. + /* Unpack largest operand - opH */
  17747. + /* exp: r7 */
  17748. + /* sf: r11, r10 */
  17749. + lsr r7, r11, 20 /* Extract exponent */
  17750. + lsl r11, 11 /* Extract mantissa, leave room for implicit bit */
  17751. + or r11, r11, r10>>21
  17752. + lsl r10, 11
  17753. + sbr r11, 31 /* Insert implicit bit */
  17754. +
  17755. +
  17756. + /* Unpack smallest operand - opL */
  17757. + /* exp: r6 */
  17758. + /* sf: r9, r8 */
  17759. + lsr r6, r9, 20 /* Extract exponent */
  17760. + breq __avr32_f64_sub_opL_subnormal /* If either zero or subnormal */
  17761. + lsl r9, 11 /* Extract mantissa, leave room for implicit bit */
  17762. + or r9, r9, r8>>21
  17763. + lsl r8, 11
  17764. + sbr r9, 31 /* Insert implicit bit */
  17765. +
  17766. +
  17767. +__avr32_f64_sub_opL_subnormal_done:
  17768. + /* opH is NaN or Inf. */
  17769. + cp.w r7, 0x7ff
  17770. + breq __avr32_f64_sub_opH_nan_or_inf
  17771. +
  17772. + /* Get shift amount to scale mantissa of op2. */
  17773. + rsub r6, r7
  17774. + breq __avr32_f64_sub_shift_done /* No need to shift, exponents are equal*/
  17775. +
  17776. + /* Scale mantissa [r9, r8] with amount [r6].
  17777. + Uses scratch registers [r5] and [lr].
  17778. + In IEEE mode:Must not forget the sticky bits we intend to shift out. */
  17779. +
  17780. + rsub r5,r6,32 /* get (32 - shift count)
  17781. + (if shift count > 32 we get a
  17782. + negative value, but that will
  17783. + work as well in the code below.) */
  17784. +
  17785. + cp.w r6,32 /* handle shifts >= 32 separately */
  17786. + brhs __avr32_f64_sub_longshift
  17787. +
  17788. + /* small (<32) shift amount, both words are part of the shift
  17789. + first remember whether part that is lost contains any 1 bits ... */
  17790. + lsl lr,r8,r5 /* shift away bits that are part of
  17791. + final mantissa. only part that goes
  17792. + to lr are bits that will be lost */
  17793. +
  17794. + /* ... and now to the actual shift */
  17795. + lsl r5,r9,r5 /* get bits from msw destined for lsw*/
  17796. + lsr r8,r8,r6 /* shift down lsw of mantissa */
  17797. + lsr r9,r9,r6 /* shift down msw of mantissa */
  17798. + or r8,r5 /* combine these bits with prepared lsw*/
  17799. +#if defined(L_avr32_f64_addsub)
  17800. + cp.w lr,0 /* if any '1' bit in part we lost ...*/
  17801. + srne lr
  17802. + or r8, lr /* ... we need to set sticky bit*/
  17803. +#endif
  17804. +
  17805. +__avr32_f64_sub_shift_done:
  17806. + /* Now subtract the mantissas. */
  17807. + sub r10, r8
  17808. + sbc r11, r11, r9
  17809. +
  17810. + /* Normalize the exponent and mantissa pair stored in
  17811. + [r11,r10] and exponent in [r7]. Needs two scratch registers [r6] and [lr]. */
  17812. + clz r6,r11 /* Check if we have zeros in high bits */
  17813. + breq __avr32_f64_sub_longnormalize_done /* No need for scaling if no zeros in high bits */
  17814. + brcs __avr32_f64_sub_longnormalize
  17815. +
  17816. +
  17817. + /* shift amount is smaller than 32, and involves both msw and lsw*/
  17818. + rsub lr,r6,32 /* shift mantissa */
  17819. + lsl r11,r11,r6
  17820. + lsr lr,r10,lr
  17821. + or r11,lr
  17822. + lsl r10,r10,r6
  17823. +
  17824. + sub r7,r6 /* adjust exponent */
  17825. + brle __avr32_f64_sub_subnormal_result
  17826. +__avr32_f64_sub_longnormalize_done:
  17827. +
  17828. +#if defined(L_avr32_f64_addsub)
  17829. + /* Insert the bits we will remove from the mantissa r9[31:21] */
  17830. + lsl r9, r10, (32 - 11)
  17831. +#else
  17832. + /* Keep the last bit shifted out. */
  17833. + bfextu r9, r10, 10, 1
  17834. +#endif
  17835. +
  17836. + /* Pack final result*/
  17837. + /* Input: [r7]:exp, [r11, r10]:mant, [r12]:sign in MSB */
  17838. + /* Result in [r11,r10] */
  17839. + /* Insert mantissa */
  17840. + lsr r10, 11
  17841. + or r10, r10, r11<<21
  17842. + lsr r11, 11
  17843. + /* Insert exponent and sign bit*/
  17844. + bfins r11, r7, 20, 11
  17845. + or r11, r12
  17846. +
  17847. + /* Round */
  17848. +__avr32_f64_sub_round:
  17849. +#if defined(L_avr32_f64_addsub)
  17850. + mov_imm r7, 0x80000000
  17851. + bld r10, 0
  17852. + subne r7, -1
  17853. +
  17854. + cp.w r9, r7
  17855. + srhs r9
  17856. +#endif
  17857. + add r10, r9
  17858. + acr r11
  17859. +
  17860. + /* Return result in [r11,r10] */
  17861. + ldm sp++, r5, r6, r7,pc
  17862. +
  17863. +
  17864. +
  17865. +__avr32_f64_sub_opL_subnormal:
  17866. + /* Extract the of mantissa */
  17867. + lsl r9, 11 /* Extract mantissa, leave room for implicit bit */
  17868. + or r9, r9, r8>>21
  17869. + lsl r8, 11
  17870. +
  17871. + /* Set exponent to 1 if we do not have a zero. */
  17872. + or lr, r9, r8
  17873. + movne r6,1
  17874. +
  17875. + /* Check if opH is also subnormal. If so, clear implicit bit in r11*/
  17876. + rsub lr, r7, 0
  17877. + moveq r7,1
  17878. + bst r11, 31
  17879. +
  17880. + /* Check if op1 is zero, if so set exponent to 0. */
  17881. + or lr, r11, r10
  17882. + moveq r7,0
  17883. +
  17884. + rjmp __avr32_f64_sub_opL_subnormal_done
  17885. +
  17886. +__avr32_f64_sub_opH_nan_or_inf:
  17887. + /* Check if opH is NaN, if so return NaN */
  17888. + cbr r11, 31
  17889. + or lr, r11, r10
  17890. + brne __avr32_f64_sub_return_nan
  17891. +
  17892. + /* opH is Inf. */
  17893. + /* Check if opL is Inf. or NaN */
  17894. + cp.w r6, 0x7ff
  17895. + breq __avr32_f64_sub_return_nan
  17896. + /* Return infinity with correct sign. */
  17897. + or r11, r12, r7 << 20
  17898. + ldm sp++, r5, r6, r7, pc/* opL not Inf or NaN, return opH */
  17899. +__avr32_f64_sub_return_nan:
  17900. + mov r10, -1 /* Generate NaN in r11, r10 */
  17901. + mov r11, -1
  17902. + ldm sp++, r5, r6, r7, pc/* opL Inf or NaN, return NaN */
  17903. +
  17904. +
  17905. +__avr32_f64_sub_subnormal_result:
  17906. +#if defined(L_avr32_f64_addsub)
  17907. + /* Check how much we must scale down the mantissa. */
  17908. + neg r7
  17909. + sub r7, -1 /* We do no longer have an implicit bit. */
  17910. + satu r7 >> 0, 6 /* Saturate shift amount to max 63. */
  17911. + cp.w r7, 32
  17912. + brge 0f
  17913. + /* Shift amount <32 */
  17914. + rsub r8, r7, 32
  17915. + lsl r9, r10, r8
  17916. + srne r6
  17917. + lsr r10, r10, r7
  17918. + or r10, r6 /* Sticky bit from the
  17919. + part that was shifted out. */
  17920. + lsl r9, r11, r8
  17921. + or r10, r10, r9
  17922. + lsr r11, r10, r7
  17923. + /* Set exponent */
  17924. + mov r7, 0
  17925. + rjmp __avr32_f64_sub_longnormalize_done
  17926. +0:
  17927. + /* Shift amount >=32 */
  17928. + rsub r8, r7, 64
  17929. + lsl r9, r11, r8
  17930. + or r9, r10
  17931. + srne r6
  17932. + lsr r10, r11, r7
  17933. + or r10, r6 /* Sticky bit from the
  17934. + part that was shifted out. */
  17935. + mov r11, 0
  17936. + /* Set exponent */
  17937. + mov r7, 0
  17938. + rjmp __avr32_f64_sub_longnormalize_done
  17939. +#else
  17940. + /* Just flush subnormals to zero. */
  17941. + mov r10, 0
  17942. + mov r11, 0
  17943. +#endif
  17944. + ldm sp++, r5, r6, r7, pc
  17945. +
  17946. +__avr32_f64_sub_longshift:
  17947. + /* large (>=32) shift amount, only lsw will have bits left after shift.
  17948. + note that shift operations will use ((shift count=r6) mod 32) so
  17949. + we do not need to subtract 32 from shift count. */
  17950. + /* Saturate the shift amount to 63. If the amount
  17951. + is any larger op2 is insignificant. */
  17952. + satu r6 >> 0, 6
  17953. +
  17954. +#if defined(L_avr32_f64_addsub)
  17955. + /* first remember whether part that is lost contains any 1 bits ... */
  17956. + moveq lr, r8 /* If shift amount is 32, no bits from msw are lost. */
  17957. + breq 0f
  17958. + lsl lr,r9,r5 /* save all lost bits from msw */
  17959. + or lr,r8 /* also save lost bits (all) from lsw
  17960. + now lr != 0 if we lose any bits */
  17961. +#endif
  17962. +0:
  17963. + /* ... and now to the actual shift */
  17964. + lsr r8,r9,r6 /* Move msw to lsw and shift. */
  17965. + mov r9,0 /* clear msw */
  17966. +#if defined(L_avr32_f64_addsub)
  17967. + cp.w lr,0 /* if any '1' bit in part we lost ...*/
  17968. + srne lr
  17969. + or r8, lr /* ... we need to set sticky bit*/
  17970. +#endif
  17971. + rjmp __avr32_f64_sub_shift_done
  17972. +
  17973. +__avr32_f64_sub_longnormalize:
  17974. + /* shift amount is greater than 32 */
  17975. + clz r6,r10 /* shift mantissa */
  17976. + /* If the resulting mantissa is zero the result is
  17977. + zero so force exponent to zero. */
  17978. + movcs r7, 0
  17979. + movcs r6, 0
  17980. + movcs r12, 0 /* Also clear sign bit. A zero result from subtraction
  17981. + always is +0.0 */
  17982. + subcc r6,-32
  17983. + lsl r11,r10,r6
  17984. + mov r10,0
  17985. + sub r7,r6 /* adjust exponent */
  17986. + brle __avr32_f64_sub_subnormal_result
  17987. + rjmp __avr32_f64_sub_longnormalize_done
  17988. +
  17989. +
  17990. +
  17991. + .align 2
  17992. +__avr32_f64_add_from_sub:
  17993. + /* Switch sign on op2 */
  17994. + eorh r9, 0x8000
  17995. +
  17996. +#if defined(L_avr32_f64_addsub_fast)
  17997. + .global __avr32_f64_add_fast
  17998. + .type __avr32_f64_add_fast,@function
  17999. +__avr32_f64_add_fast:
  18000. +#else
  18001. + .global __avr32_f64_add
  18002. + .type __avr32_f64_add,@function
  18003. +__avr32_f64_add:
  18004. +#endif
  18005. +
  18006. + /* op1 in {r11,r10}*/
  18007. + /* op2 in {r9,r8}*/
  18008. +
  18009. +#if defined(L_avr32_f64_addsub_fast)
  18010. + /* If op2 is zero just return op1 */
  18011. + or r12, r8, r9 << 1
  18012. + reteq r12
  18013. +#endif
  18014. +
  18015. + /* Check signs */
  18016. + eor r12, r11, r9
  18017. + /* Different signs, use subtraction. */
  18018. + brmi __avr32_f64_sub_from_add
  18019. +
  18020. + stm --sp, r5, r6, r7, lr
  18021. +
  18022. + /* Get sign of op1 into r12 */
  18023. + mov r12, r11
  18024. + andh r12, 0x8000, COH
  18025. +
  18026. + /* Remove sign from operands */
  18027. + cbr r11, 31
  18028. + cbr r9, 31
  18029. +
  18030. + /* Put the number with the largest exponent in [r11, r10]
  18031. + and the number with the smallest exponent in [r9, r8] */
  18032. + cp r11, r9
  18033. + brhs 1f /* Skip swap if operands already correctly ordered */
  18034. + /* Operands were not correctly ordered, swap them */
  18035. + mov r7, r11
  18036. + mov r11, r9
  18037. + mov r9, r7
  18038. + mov r7, r10
  18039. + mov r10, r8
  18040. + mov r8, r7
  18041. +1:
  18042. + mov lr, 0 /* Set sticky bits to zero */
  18043. + /* Unpack largest operand - opH */
  18044. + /* exp: r7 */
  18045. + /* sf: r11, r10 */
  18046. + bfextu R7, R11, 20, 11 /* Extract exponent */
  18047. + bfextu r11, r11, 0, 20 /* Extract mantissa */
  18048. + sbr r11, 20 /* Insert implicit bit */
  18049. +
  18050. + /* Unpack smallest operand - opL */
  18051. + /* exp: r6 */
  18052. + /* sf: r9, r8 */
  18053. + bfextu R6, R9, 20, 11 /* Extract exponent */
  18054. + breq __avr32_f64_add_op2_subnormal
  18055. + bfextu r9, r9, 0, 20 /* Extract mantissa */
  18056. + sbr r9, 20 /* Insert implicit bit */
  18057. +
  18058. +2:
  18059. + /* opH is NaN or Inf. */
  18060. + cp.w r7, 0x7ff
  18061. + breq __avr32_f64_add_opH_nan_or_inf
  18062. +
  18063. + /* Get shift amount to scale mantissa of op2. */
  18064. + rsub r6, r7
  18065. + breq __avr32_f64_add_shift_done /* No need to shift, exponents are equal*/
  18066. +
  18067. + /* Scale mantissa [r9, r8] with amount [r6].
  18068. + Uses scratch registers [r5] and [lr].
  18069. + In IEEE mode:Must not forget the sticky bits we intend to shift out. */
  18070. + rsub r5,r6,32 /* get (32 - shift count)
  18071. + (if shift count > 32 we get a
  18072. + negative value, but that will
  18073. + work as well in the code below.) */
  18074. +
  18075. + cp.w r6,32 /* handle shifts >= 32 separately */
  18076. + brhs __avr32_f64_add_longshift
  18077. +
  18078. + /* small (<32) shift amount, both words are part of the shift
  18079. + first remember whether part that is lost contains any 1 bits ... */
  18080. + lsl lr,r8,r5 /* shift away bits that are part of
  18081. + final mantissa. only part that goes
  18082. + to lr are bits that will be lost */
  18083. +
  18084. + /* ... and now to the actual shift */
  18085. + lsl r5,r9,r5 /* get bits from msw destined for lsw*/
  18086. + lsr r8,r8,r6 /* shift down lsw of mantissa */
  18087. + lsr r9,r9,r6 /* shift down msw of mantissa */
  18088. + or r8,r5 /* combine these bits with prepared lsw*/
  18089. +
  18090. +__avr32_f64_add_shift_done:
  18091. + /* Now add the mantissas. */
  18092. + add r10, r8
  18093. + adc r11, r11, r9
  18094. +
  18095. + /* Check if we overflowed. */
  18096. + bld r11, 21
  18097. + breq __avr32_f64_add_res_of:
  18098. +
  18099. +__avr32_f64_add_res_of_done:
  18100. +
  18101. + /* Pack final result*/
  18102. + /* Input: [r7]:exp, [r11, r10]:mant, [r12]:sign in MSB */
  18103. + /* Result in [r11,r10] */
  18104. + /* Insert exponent and sign bit*/
  18105. + bfins r11, r7, 20, 11
  18106. + or r11, r12
  18107. +
  18108. + /* Round */
  18109. +__avr32_f64_add_round:
  18110. +#if defined(L_avr32_f64_addsub)
  18111. + bfextu r12, r10, 0, 1 /* Extract parity bit.*/
  18112. + or lr, r12 /* or it together with the sticky bits. */
  18113. + eorh lr, 0x8000 /* Toggle round bit. */
  18114. + /* We should now round up by adding one for the following cases:
  18115. +
  18116. + halfway sticky|parity round-up
  18117. + 0 x no
  18118. + 1 0 no
  18119. + 1 1 yes
  18120. +
  18121. + Since we have inverted the halfway bit we can use the satu instruction
  18122. + by saturating to 1 bit to implement this.
  18123. + */
  18124. + satu lr >> 0, 1
  18125. +#else
  18126. + lsr lr, 31
  18127. +#endif
  18128. + add r10, lr
  18129. + acr r11
  18130. +
  18131. + /* Return result in [r11,r10] */
  18132. + ldm sp++, r5, r6, r7,pc
  18133. +
  18134. +
  18135. +__avr32_f64_add_opH_nan_or_inf:
  18136. + /* Check if opH is NaN, if so return NaN */
  18137. + cbr r11, 20
  18138. + or lr, r11, r10
  18139. + brne __avr32_f64_add_return_nan
  18140. +
  18141. + /* opH is Inf. */
  18142. + /* Check if opL is Inf. or NaN */
  18143. + cp.w r6, 0x7ff
  18144. + breq __avr32_f64_add_opL_nan_or_inf
  18145. + ldm sp++, r5, r6, r7, pc/* opL not Inf or NaN, return opH */
  18146. +__avr32_f64_add_opL_nan_or_inf:
  18147. + cbr r9, 20
  18148. + or lr, r9, r8
  18149. + brne __avr32_f64_add_return_nan
  18150. + mov r10, 0 /* Generate Inf in r11, r10 */
  18151. + mov_imm r11, 0x7ff00000
  18152. + or r11, r12 /* Put sign bit back */
  18153. + ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */
  18154. +__avr32_f64_add_return_nan:
  18155. + mov r10, -1 /* Generate NaN in r11, r10 */
  18156. + mov r11, -1
  18157. + ldm sp++, r5, r6, r7, pc/* opL Inf or NaN, return NaN */
  18158. +
  18159. +
  18160. +__avr32_f64_add_longshift:
  18161. + /* large (>=32) shift amount, only lsw will have bits left after shift.
  18162. + note that shift operations will use ((shift count=r6) mod 32) so
  18163. + we do not need to subtract 32 from shift count. */
  18164. + /* Saturate the shift amount to 63. If the amount
  18165. + is any larger op2 is insignificant. */
  18166. + satu r6 >> 0, 6
  18167. + /* If shift amount is 32 there are no bits from the msw that are lost. */
  18168. + moveq lr, r8
  18169. + breq 0f
  18170. + /* first remember whether part that is lost contains any 1 bits ... */
  18171. + lsl lr,r9,r5 /* save all lost bits from msw */
  18172. +#if defined(L_avr32_f64_addsub)
  18173. + cp.w r8, 0
  18174. + srne r8
  18175. + or lr,r8 /* also save lost bits (all) from lsw
  18176. + now lr != 0 if we lose any bits */
  18177. +#endif
  18178. +0:
  18179. + /* ... and now to the actual shift */
  18180. + lsr r8,r9,r6 /* msw -> lsw and make rest of shift inside lsw*/
  18181. + mov r9,0 /* clear msw */
  18182. + rjmp __avr32_f64_add_shift_done
  18183. +
  18184. +__avr32_f64_add_res_of:
  18185. + /* We overflowed. Scale down mantissa by shifting right one position. */
  18186. + or lr, lr, lr << 1 /* Remember stickybits*/
  18187. + lsr r11, 1
  18188. + ror r10
  18189. + ror lr
  18190. + sub r7, -1 /* Increment exponent */
  18191. +
  18192. + /* Clear mantissa to set result to Inf if the exponent is 255. */
  18193. + cp.w r7, 0x7ff
  18194. + moveq r10, 0
  18195. + moveq r11, 0
  18196. + moveq lr, 0
  18197. + rjmp __avr32_f64_add_res_of_done
  18198. +
  18199. +__avr32_f64_add_op2_subnormal:
  18200. + /* Set epxponent to 1 */
  18201. + mov r6, 1
  18202. +
  18203. + /* Check if op2 is also subnormal. */
  18204. + cp.w r7, 0
  18205. + brne 2b
  18206. +
  18207. + cbr r11, 20
  18208. + /* Both operands are subnormal. Just addd the mantissas
  18209. + and the exponent will automatically be set to 1 if
  18210. + we overflow into a normal number. */
  18211. + add r10, r8
  18212. + adc r11, r11, r9
  18213. +
  18214. + /* Add sign bit */
  18215. + or r11, r12
  18216. +
  18217. + /* Return result in [r11,r10] */
  18218. + ldm sp++, r5, r6, r7,pc
  18219. +
  18220. +
  18221. +
  18222. +#endif
  18223. +
  18224. +#ifdef L_avr32_f64_to_u32
  18225. + /* This goes into L_fixdfsi */
  18226. +#endif
  18227. +
  18228. +
  18229. +#ifdef L_avr32_f64_to_s32
  18230. + .global __avr32_f64_to_u32
  18231. + .type __avr32_f64_to_u32,@function
  18232. +__avr32_f64_to_u32:
  18233. + cp.w r11, 0
  18234. + retmi 0 /* Negative returns 0 */
  18235. +
  18236. + /* Fallthrough to df to signed si conversion */
  18237. + .global __avr32_f64_to_s32
  18238. + .type __avr32_f64_to_s32,@function
  18239. +__avr32_f64_to_s32:
  18240. + lsl r12,r11,1
  18241. + lsr r12,21 /* extract exponent*/
  18242. + sub r12,1023 /* convert to unbiased exponent.*/
  18243. + retlo 0 /* too small exponent implies zero. */
  18244. +
  18245. +1:
  18246. + rsub r12,r12,31 /* shift count = 31 - exponent */
  18247. + mov r9,r11 /* save sign for later...*/
  18248. + lsl r11,11 /* remove exponent and sign*/
  18249. + sbr r11,31 /* add implicit bit*/
  18250. + or r11,r11,r10>>21 /* get rest of bits from lsw of double */
  18251. + lsr r11,r11,r12 /* shift down mantissa to final place */
  18252. + lsl r9,1 /* sign -> carry */
  18253. + retcc r11 /* if positive, we are done */
  18254. + neg r11 /* if negative float, negate result */
  18255. + ret r11
  18256. +
  18257. +#endif /* L_fixdfsi*/
  18258. +
  18259. +#ifdef L_avr32_f64_to_u64
  18260. + /* Actual function is in L_fixdfdi */
  18261. +#endif
  18262. +
  18263. +#ifdef L_avr32_f64_to_s64
  18264. + .global __avr32_f64_to_u64
  18265. + .type __avr32_f64_to_u64,@function
  18266. +__avr32_f64_to_u64:
  18267. + cp.w r11,0
  18268. + /* Negative numbers return zero */
  18269. + movmi r10, 0
  18270. + movmi r11, 0
  18271. + retmi r11
  18272. +
  18273. +
  18274. +
  18275. + /* Fallthrough */
  18276. + .global __avr32_f64_to_s64
  18277. + .type __avr32_f64_to_s64,@function
  18278. +__avr32_f64_to_s64:
  18279. + lsl r9,r11,1
  18280. + lsr r9,21 /* get exponent*/
  18281. + sub r9,1023 /* convert to correct range*/
  18282. + /* Return zero if exponent to small */
  18283. + movlo r10, 0
  18284. + movlo r11, 0
  18285. + retlo r11
  18286. +
  18287. + mov r8,r11 /* save sign for later...*/
  18288. +1:
  18289. + lsl r11,11 /* remove exponent */
  18290. + sbr r11,31 /* add implicit bit*/
  18291. + or r11,r11,r10>>21 /* get rest of bits from lsw of double*/
  18292. + lsl r10,11 /* align lsw correctly as well */
  18293. + rsub r9,r9,63 /* shift count = 63 - exponent */
  18294. + breq 1f
  18295. +
  18296. + cp.w r9,32 /* is shift count more than one reg? */
  18297. + brhs 0f
  18298. +
  18299. + mov r12,r11 /* save msw */
  18300. + lsr r10,r10,r9 /* small shift count, shift down lsw */
  18301. + lsr r11,r11,r9 /* small shift count, shift down msw */
  18302. + rsub r9,r9,32 /* get 32-size of shifted out tail */
  18303. + lsl r12,r12,r9 /* align part to move from msw to lsw */
  18304. + or r10,r12 /* combine to get new lsw */
  18305. + rjmp 1f
  18306. +
  18307. +0:
  18308. + lsr r10,r11,r9 /* large shift count,only lsw get bits
  18309. + note that shift count is modulo 32*/
  18310. + mov r11,0 /* msw will be 0 */
  18311. +
  18312. +1:
  18313. + lsl r8,1 /* sign -> carry */
  18314. + retcc r11 /* if positive, we are done */
  18315. +
  18316. + neg r11 /* if negative float, negate result */
  18317. + neg r10
  18318. + scr r11
  18319. + ret r11
  18320. +
  18321. +#endif
  18322. +
  18323. +#ifdef L_avr32_u32_to_f64
  18324. + /* Code located in L_floatsidf */
  18325. +#endif
  18326. +
  18327. +#ifdef L_avr32_s32_to_f64
  18328. + .global __avr32_u32_to_f64
  18329. + .type __avr32_u32_to_f64,@function
  18330. +__avr32_u32_to_f64:
  18331. + sub r11, r12, 0 /* Move to r11 and force Z flag to be updated */
  18332. + mov r12, 0 /* always positive */
  18333. + rjmp 0f /* Jump to common code for floatsidf */
  18334. +
  18335. + .global __avr32_s32_to_f64
  18336. + .type __avr32_s32_to_f64,@function
  18337. +__avr32_s32_to_f64:
  18338. + mov r11, r12 /* Keep original value in r12 for sign */
  18339. + abs r11 /* Absolute value if r12 */
  18340. +0:
  18341. + mov r10,0 /* let remaining bits be zero */
  18342. + reteq r11 /* zero long will return zero float */
  18343. +
  18344. + pushm lr
  18345. + mov r9,31+1023 /* set exponent */
  18346. +
  18347. + normalize_df r9 /*exp*/, r10, r11 /* mantissa */, r8, lr /* scratch */
  18348. +
  18349. + /* Check if a subnormal result was created */
  18350. + cp.w r9, 0
  18351. + brgt 0f
  18352. +
  18353. + adjust_subnormal_df r9 /* exp */, r10, r11 /* Mantissa */, r12 /*sign*/, r8, lr /* scratch */
  18354. + popm pc
  18355. +0:
  18356. +
  18357. + /* Round result */
  18358. + round_df r9 /*exp*/, r10, r11 /* Mantissa */, r8 /*scratch*/
  18359. + cp.w r9,0x7ff
  18360. + brlt 0f
  18361. + /*Return infinity */
  18362. + mov r10, 0
  18363. + mov_imm r11, 0xffe00000
  18364. + rjmp __floatsidf_return_op1
  18365. +
  18366. +0:
  18367. +
  18368. + /* Pack */
  18369. + pack_df r9 /*exp*/, r10, r11 /* mantissa */, r10, r11 /* Output df number*/
  18370. +__floatsidf_return_op1:
  18371. + lsl r12,1 /* shift in sign bit */
  18372. + ror r11
  18373. +
  18374. + popm pc
  18375. +#endif
  18376. +
  18377. +
  18378. +#ifdef L_avr32_f32_cmp_eq
  18379. + .global __avr32_f32_cmp_eq
  18380. + .type __avr32_f32_cmp_eq,@function
  18381. +__avr32_f32_cmp_eq:
  18382. + cp.w r12, r11
  18383. + breq 0f
  18384. + /* If not equal check for +/-0 */
  18385. + /* Or together the two values and shift out the sign bit.
  18386. + If the result is zero, then the two values are both zero. */
  18387. + or r12, r11
  18388. + lsl r12, 1
  18389. + reteq 1
  18390. + ret 0
  18391. +0:
  18392. + /* Numbers were equal. Check for NaN or Inf */
  18393. + mov_imm r11, 0xff000000
  18394. + lsl r12, 1
  18395. + cp.w r12, r11
  18396. + retls 1 /* 0 if NaN, 1 otherwise */
  18397. + ret 0
  18398. +#endif
  18399. +
  18400. +#if defined(L_avr32_f32_cmp_ge) || defined(L_avr32_f32_cmp_lt)
  18401. +#ifdef L_avr32_f32_cmp_ge
  18402. + .global __avr32_f32_cmp_ge
  18403. + .type __avr32_f32_cmp_ge,@function
  18404. +__avr32_f32_cmp_ge:
  18405. +#endif
  18406. +#ifdef L_avr32_f32_cmp_lt
  18407. + .global __avr32_f32_cmp_lt
  18408. + .type __avr32_f32_cmp_lt,@function
  18409. +__avr32_f32_cmp_lt:
  18410. +#endif
  18411. + lsl r10, r12, 1 /* Remove sign bits */
  18412. + lsl r9, r11, 1
  18413. + subfeq r10, 0
  18414. +#ifdef L_avr32_f32_cmp_ge
  18415. + reteq 1 /* Both number are zero. Return true. */
  18416. +#endif
  18417. +#ifdef L_avr32_f32_cmp_lt
  18418. + reteq 0 /* Both number are zero. Return false. */
  18419. +#endif
  18420. + mov_imm r8, 0xff000000
  18421. + cp.w r10, r8
  18422. + rethi 0 /* Op0 is NaN */
  18423. + cp.w r9, r8
  18424. + rethi 0 /* Op1 is Nan */
  18425. +
  18426. + eor r8, r11, r12
  18427. + bld r12, 31
  18428. +#ifdef L_avr32_f32_cmp_ge
  18429. + srcc r8 /* Set result to true if op0 is positive*/
  18430. +#endif
  18431. +#ifdef L_avr32_f32_cmp_lt
  18432. + srcs r8 /* Set result to true if op0 is negative*/
  18433. +#endif
  18434. + retmi r8 /* Return if signs are different */
  18435. + brcs 0f /* Both signs negative? */
  18436. +
  18437. + /* Both signs positive */
  18438. + cp.w r12, r11
  18439. +#ifdef L_avr32_f32_cmp_ge
  18440. + reths 1
  18441. + retlo 0
  18442. +#endif
  18443. +#ifdef L_avr32_f32_cmp_lt
  18444. + reths 0
  18445. + retlo 1
  18446. +#endif
  18447. +0:
  18448. + /* Both signs negative */
  18449. + cp.w r11, r12
  18450. +#ifdef L_avr32_f32_cmp_ge
  18451. + reths 1
  18452. + retlo 0
  18453. +#endif
  18454. +#ifdef L_avr32_f32_cmp_lt
  18455. + reths 0
  18456. + retlo 1
  18457. +#endif
  18458. +#endif
  18459. +
  18460. +
  18461. +#ifdef L_avr32_f64_cmp_eq
  18462. + .global __avr32_f64_cmp_eq
  18463. + .type __avr32_f64_cmp_eq,@function
  18464. +__avr32_f64_cmp_eq:
  18465. + cp.w r10,r8
  18466. + cpc r11,r9
  18467. + breq 0f
  18468. +
  18469. + /* Args were not equal*/
  18470. + /* Both args could be zero with different sign bits */
  18471. + lsl r11,1 /* get rid of sign bits */
  18472. + lsl r9,1
  18473. + or r11,r10 /* Check if all bits are zero */
  18474. + or r11,r9
  18475. + or r11,r8
  18476. + reteq 1 /* If all zeros the arguments are equal
  18477. + so return 1 else return 0 */
  18478. + ret 0
  18479. +0:
  18480. + /* check for NaN */
  18481. + lsl r11,1
  18482. + mov_imm r12, 0xffe00000
  18483. + cp.w r10,0
  18484. + cpc r11,r12 /* check if nan or inf */
  18485. + retls 1 /* If Arg is NaN return 0 else 1*/
  18486. + ret 0 /* Return */
  18487. +
  18488. +#endif
  18489. +
  18490. +
  18491. +#if defined(L_avr32_f64_cmp_ge) || defined(L_avr32_f64_cmp_lt)
  18492. +
  18493. +#ifdef L_avr32_f64_cmp_ge
  18494. + .global __avr32_f64_cmp_ge
  18495. + .type __avr32_f64_cmp_ge,@function
  18496. +__avr32_f64_cmp_ge:
  18497. +#endif
  18498. +#ifdef L_avr32_f64_cmp_lt
  18499. + .global __avr32_f64_cmp_lt
  18500. + .type __avr32_f64_cmp_lt,@function
  18501. +__avr32_f64_cmp_lt:
  18502. +#endif
  18503. +
  18504. + /* compare magnitude of op1 and op2 */
  18505. + st.w --sp, lr
  18506. + st.w --sp, r7
  18507. + lsl r11,1 /* Remove sign bit of op1 */
  18508. + srcs r12 /* Sign op1 to lsb of r12*/
  18509. + lsl r9,1 /* Remove sign bit of op2 */
  18510. + srcs r7
  18511. + rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/
  18512. +
  18513. +
  18514. + /* Check for Nan */
  18515. + mov_imm lr, 0xffe00000
  18516. + cp.w r10,0
  18517. + cpc r11,lr
  18518. + brhi 0f /* We have NaN */
  18519. + cp.w r8,0
  18520. + cpc r9,lr
  18521. + brhi 0f /* We have NaN */
  18522. +
  18523. + cp.w r11, 0
  18524. + subfeq r10, 0
  18525. + breq 3f /* op1 zero */
  18526. + ld.w r7, sp++
  18527. + ld.w lr, sp++
  18528. +
  18529. + cp.w r12,3 /* both operands negative ?*/
  18530. + breq 1f
  18531. +
  18532. + cp.w r12,1 /* both operands positive? */
  18533. + brlo 2f
  18534. +
  18535. + /* Different signs. If sign of op1 is negative the difference
  18536. + between op1 and op2 will always be negative, and if op1 is
  18537. + positive the difference will always be positive */
  18538. +#ifdef L_avr32_f64_cmp_ge
  18539. + reteq 1
  18540. + retne 0
  18541. +#endif
  18542. +#ifdef L_avr32_f64_cmp_lt
  18543. + reteq 0
  18544. + retne 1
  18545. +#endif
  18546. +
  18547. +2:
  18548. + /* Both operands positive. Just compute the difference */
  18549. + cp.w r10,r8
  18550. + cpc r11,r9
  18551. +#ifdef L_avr32_f64_cmp_ge
  18552. + reths 1
  18553. + retlo 0
  18554. +#endif
  18555. +#ifdef L_avr32_f64_cmp_lt
  18556. + reths 0
  18557. + retlo 1
  18558. +#endif
  18559. +
  18560. +1:
  18561. + /* Both operands negative. Compute the difference with operands switched */
  18562. + cp r8,r10
  18563. + cpc r9,r11
  18564. +#ifdef L_avr32_f64_cmp_ge
  18565. + reths 1
  18566. + retlo 0
  18567. +#endif
  18568. +#ifdef L_avr32_f64_cmp_lt
  18569. + reths 0
  18570. + retlo 1
  18571. +#endif
  18572. +
  18573. +0:
  18574. + ld.w r7, sp++
  18575. + popm pc, r12=0
  18576. +#endif
  18577. +
  18578. +3:
  18579. + cp.w r7, 1 /* Check sign bit from r9 */
  18580. +#ifdef L_avr32_f64_cmp_ge
  18581. + sreq r12 /* If op2 is negative then op1 >= op2. */
  18582. +#endif
  18583. +#ifdef L_avr32_f64_cmp_lt
  18584. + srne r12 /* If op2 is positve then op1 <= op2. */
  18585. +#endif
  18586. + cp.w r9, 0
  18587. + subfeq r8, 0
  18588. + ld.w r7, sp++
  18589. + ld.w lr, sp++
  18590. +#ifdef L_avr32_f64_cmp_ge
  18591. + reteq 1 /* Both operands are zero. Return true. */
  18592. +#endif
  18593. +#ifdef L_avr32_f64_cmp_lt
  18594. + reteq 0 /* Both operands are zero. Return false. */
  18595. +#endif
  18596. + ret r12
  18597. +
  18598. +
  18599. +#if defined(L_avr32_f64_div) || defined(L_avr32_f64_div_fast)
  18600. + .align 2
  18601. +
  18602. +#if defined(L_avr32_f64_div_fast)
  18603. + .global __avr32_f64_div_fast
  18604. + .type __avr32_f64_div_fast,@function
  18605. +__avr32_f64_div_fast:
  18606. +#else
  18607. + .global __avr32_f64_div
  18608. + .type __avr32_f64_div,@function
  18609. +__avr32_f64_div:
  18610. +#endif
  18611. + stm --sp, r0, r1, r2, r3, r4, r5, r6, r7,lr
  18612. + /* op1 in {r11,r10}*/
  18613. + /* op2 in {r9,r8}*/
  18614. + eor lr, r11, r9 /* MSB(lr) = Sign(op1) ^ Sign(op2) */
  18615. +
  18616. +
  18617. + /* Unpack op1 to 2.62 format*/
  18618. + /* exp: r7 */
  18619. + /* sf: r11, r10 */
  18620. + lsr r7, r11, 20 /* Extract exponent */
  18621. +
  18622. + lsl r11, 9 /* Extract mantissa, leave room for implicit bit */
  18623. + or r11, r11, r10>>23
  18624. + lsl r10, 9
  18625. + sbr r11, 29 /* Insert implicit bit */
  18626. + andh r11, 0x3fff /*Mask last part of exponent since we use 2.62 format*/
  18627. +
  18628. + cbr r7, 11 /* Clear sign bit */
  18629. + /* Check if normalization is needed */
  18630. + breq 11f /*If number is subnormal, normalize it */
  18631. +22:
  18632. + cp r7, 0x7ff
  18633. + brge 2f /* Check op1 for NaN or Inf */
  18634. +
  18635. + /* Unpack op2 to 2.62 format*/
  18636. + /* exp: r6 */
  18637. + /* sf: r9, r8 */
  18638. + lsr r6, r9, 20 /* Extract exponent */
  18639. +
  18640. + lsl r9, 9 /* Extract mantissa, leave room for implicit bit */
  18641. + or r9, r9, r8>>23
  18642. + lsl r8, 9
  18643. + sbr r9, 29 /* Insert implicit bit */
  18644. + andh r9, 0x3fff /*Mask last part of exponent since we use 2.62 format*/
  18645. +
  18646. + cbr r6, 11 /* Clear sign bit */
  18647. + /* Check if normalization is needed */
  18648. + breq 13f /*If number is subnormal, normalize it */
  18649. +23:
  18650. + cp r6, 0x7ff
  18651. + brge 3f /* Check op2 for NaN or Inf */
  18652. +
  18653. + /* Calculate new exponent */
  18654. + sub r7, r6
  18655. + sub r7,-1023
  18656. +
  18657. + /* Divide */
  18658. + /* Approximating 1/d with the following recurrence: */
  18659. + /* R[j+1] = R[j]*(2-R[j]*d) */
  18660. + /* Using 2.62 format */
  18661. + /* TWO: r12 */
  18662. + /* d = op2 = divisor (2.62 format): r9,r8 */
  18663. + /* Multiply result : r5, r4 */
  18664. + /* Initial guess : r3, r2 */
  18665. + /* New approximations : r3, r2 */
  18666. + /* op1 = Dividend (2.62 format) : r11, r10 */
  18667. +
  18668. + mov_imm r12, 0x80000000
  18669. +
  18670. + /* Load initial guess, using look-up table */
  18671. + /* Initial guess is of format 01.XY, where XY is constructed as follows: */
  18672. + /* Let d be of following format: 00.1xy....., then XY=~xy */
  18673. + /* For d=00.100 = 0,5 -> initial guess=01.11 = 1,75 */
  18674. + /* For d=00.101 = 0,625 -> initial guess=01.11 = 1,5 */
  18675. + /* For d=00.110 = 0,75 -> initial guess=01.11 = 1,25 */
  18676. + /* For d=00.111 = 0,875 -> initial guess=01.11 = 1,0 */
  18677. + /* r2 is also part of the reg pair forming initial guess, but it*/
  18678. + /* is kept uninitialized to save one cycle since it has so low significance*/
  18679. +
  18680. + lsr r3, r12, 1
  18681. + bfextu r4, r9, 27, 2
  18682. + com r4
  18683. + bfins r3, r4, 28, 2
  18684. +
  18685. + /* First approximation */
  18686. + /* Approximating to 32 bits */
  18687. + /* r5 = R[j]*d */
  18688. + mulu.d r4, r3, r9
  18689. + /* r5 = 2-R[j]*d */
  18690. + sub r5, r12, r5<<2
  18691. + /* r3 = R[j]*(2-R[j]*d) */
  18692. + mulu.d r4, r3, r5
  18693. + lsl r3, r5, 2
  18694. +
  18695. + /* Second approximation */
  18696. + /* Approximating to 32 bits */
  18697. + /* r5 = R[j]*d */
  18698. + mulu.d r4, r3, r9
  18699. + /* r5 = 2-R[j]*d */
  18700. + sub r5, r12, r5<<2
  18701. + /* r3 = R[j]*(2-R[j]*d) */
  18702. + mulu.d r4, r3, r5
  18703. + lsl r3, r5, 2
  18704. +
  18705. + /* Third approximation */
  18706. + /* Approximating to 32 bits */
  18707. + /* r5 = R[j]*d */
  18708. + mulu.d r4, r3, r9
  18709. + /* r5 = 2-R[j]*d */
  18710. + sub r5, r12, r5<<2
  18711. + /* r3 = R[j]*(2-R[j]*d) */
  18712. + mulu.d r4, r3, r5
  18713. + lsl r3, r5, 2
  18714. +
  18715. + /* Fourth approximation */
  18716. + /* Approximating to 64 bits */
  18717. + /* r5,r4 = R[j]*d */
  18718. + mul_approx_df r3 /*ah*/, r2 /*al*/, r9 /*bh*/, r8 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
  18719. + lsl r5, 2
  18720. + or r5, r5, r4>>30
  18721. + lsl r4, 2
  18722. + /* r5,r4 = 2-R[j]*d */
  18723. + neg r4
  18724. + sbc r5, r12, r5
  18725. + /* r3,r2 = R[j]*(2-R[j]*d) */
  18726. + mul_approx_df r3 /*ah*/, r2 /*al*/, r5 /*bh*/, r4 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
  18727. + lsl r3, r5, 2
  18728. + or r3, r3, r4>>30
  18729. + lsl r2, r4, 2
  18730. +
  18731. +
  18732. + /* Fifth approximation */
  18733. + /* Approximating to 64 bits */
  18734. + /* r5,r4 = R[j]*d */
  18735. + mul_approx_df r3 /*ah*/, r2 /*al*/, r9 /*bh*/, r8 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
  18736. + lsl r5, 2
  18737. + or r5, r5, r4>>30
  18738. + lsl r4, 2
  18739. + /* r5,r4 = 2-R[j]*d */
  18740. + neg r4
  18741. + sbc r5, r12, r5
  18742. + /* r3,r2 = R[j]*(2-R[j]*d) */
  18743. + mul_approx_df r3 /*ah*/, r2 /*al*/, r5 /*bh*/, r4 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
  18744. + lsl r3, r5, 2
  18745. + or r3, r3, r4>>30
  18746. + lsl r2, r4, 2
  18747. +
  18748. +
  18749. + /* Multiply with dividend to get quotient */
  18750. + mul_approx_df r3 /*ah*/, r2 /*al*/, r11 /*bh*/, r10 /*bl*/, r3 /*rh*/, r2 /*rl*/, r1 /*sh*/, r0 /*sl*/
  18751. +
  18752. +
  18753. + /* To increase speed, this result is not corrected before final rounding.*/
  18754. + /* This may give a difference to IEEE compliant code of 1 ULP.*/
  18755. +
  18756. +
  18757. + /* Adjust exponent and mantissa */
  18758. + /* r7:exp, [r3, r2]:mant, [r5, r4]:scratch*/
  18759. + /* Mantissa may be of the format 0.xxxx or 1.xxxx. */
  18760. + /* In the first case, shift one pos to left.*/
  18761. + bld r3, 31-3
  18762. + breq 0f
  18763. + lsl r2, 1
  18764. + rol r3
  18765. + sub r7, 1
  18766. +#if defined(L_avr32_f64_div)
  18767. + /* We must scale down the dividend to 5.59 format. */
  18768. + lsr r10, 3
  18769. + or r10, r10, r11 << 29
  18770. + lsr r11, 3
  18771. + rjmp 1f
  18772. +#endif
  18773. +0:
  18774. +#if defined(L_avr32_f64_div)
  18775. + /* We must scale down the dividend to 6.58 format. */
  18776. + lsr r10, 4
  18777. + or r10, r10, r11 << 28
  18778. + lsr r11, 4
  18779. +1:
  18780. +#endif
  18781. + cp r7, 0
  18782. + brle __avr32_f64_div_res_subnormal /* Result was subnormal. */
  18783. +
  18784. +
  18785. +#if defined(L_avr32_f64_div)
  18786. + /* In order to round correctly we calculate the remainder:
  18787. + Remainder = dividend[11:r10] - divisor[r9:r8]*quotient[r3:r2]
  18788. + for the case when the quotient is halfway between the round-up
  18789. + value and the round down value. If the remainder then is negative
  18790. + it means that the quotient was to big and that it should not be
  18791. + rounded up, if the remainder is positive the quotient was to small
  18792. + and we need to round up. If the remainder is zero it means that the
  18793. + quotient is exact but since we need to remove the guard bit we should
  18794. + round to even. */
  18795. +
  18796. + /* Truncate and add guard bit. */
  18797. + andl r2, 0xff00
  18798. + orl r2, 0x0080
  18799. +
  18800. +
  18801. + /* Now do the multiplication. The quotient has the format 4.60
  18802. + while the divisor has the format 2.62 which gives a result
  18803. + of 6.58 */
  18804. + mulu.d r0, r3, r8
  18805. + macu.d r0, r2, r9
  18806. + mulu.d r4, r2, r8
  18807. + mulu.d r8, r3, r9
  18808. + add r5, r0
  18809. + adc r8, r8, r1
  18810. + acr r9
  18811. +
  18812. +
  18813. + /* Check if remainder is positive, negative or equal. */
  18814. + bfextu r12, r2, 8, 1 /* Get parity bit into bit 0 of r0 */
  18815. + cp r4, 0
  18816. + cpc r5
  18817. +__avr32_f64_div_round_subnormal:
  18818. + cpc r8, r10
  18819. + cpc r9, r11
  18820. + srlo r6 /* Remainder positive: we need to round up.*/
  18821. + moveq r6, r12 /* Remainder zero: round up if mantissa odd. */
  18822. +#else
  18823. + bfextu r6, r2, 7, 1 /* Get guard bit */
  18824. +#endif
  18825. + /* Final packing, scale down mantissa. */
  18826. + lsr r10, r2, 8
  18827. + or r10, r10, r3<<24
  18828. + lsr r11, r3, 8
  18829. + /* Insert exponent and sign bit*/
  18830. + bfins r11, r7, 20, 11
  18831. + bld lr, 31
  18832. + bst r11, 31
  18833. +
  18834. + /* Final rounding */
  18835. + add r10, r6
  18836. + acr r11
  18837. +
  18838. + /* Return result in [r11,r10] */
  18839. + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
  18840. +
  18841. +
  18842. +2:
  18843. + /* Op1 is NaN or inf */
  18844. + andh r11, 0x000f /* Extract mantissa */
  18845. + or r11, r10
  18846. + brne 16f /* Return NaN if op1 is NaN */
  18847. + /* Op1 is inf check op2 */
  18848. + lsr r6, r9, 20 /* Extract exponent */
  18849. + cbr r6, 11 /* Clear sign bit */
  18850. + cp r6, 0x7ff
  18851. + brne 17f /* Inf/number gives inf, return inf */
  18852. + rjmp 16f /* The rest gives NaN*/
  18853. +
  18854. +3:
  18855. + /* Op1 is a valid number. Op 2 is NaN or inf */
  18856. + andh r9, 0x000f /* Extract mantissa */
  18857. + or r9, r8
  18858. + brne 16f /* Return NaN if op2 is NaN */
  18859. + rjmp 15f /* Op2 was inf, return zero*/
  18860. +
  18861. +11: /* Op1 was denormal. Fix it. */
  18862. + lsl r11, 3
  18863. + or r11, r11, r10 >> 29
  18864. + lsl r10, 3
  18865. + /* Check if op1 is zero. */
  18866. + or r4, r10, r11
  18867. + breq __avr32_f64_div_op1_zero
  18868. + normalize_df r7 /*exp*/, r10, r11 /*Mantissa*/, r4, r5 /*scratch*/
  18869. + lsr r10, 2
  18870. + or r10, r10, r11 << 30
  18871. + lsr r11, 2
  18872. + rjmp 22b
  18873. +
  18874. +
  18875. +13: /* Op2 was denormal. Fix it */
  18876. + lsl r9, 3
  18877. + or r9, r9, r8 >> 29
  18878. + lsl r8, 3
  18879. + /* Check if op2 is zero. */
  18880. + or r4, r9, r8
  18881. + breq 17f /* Divisor is zero -> return Inf */
  18882. + normalize_df r6 /*exp*/, r8, r9 /*Mantissa*/, r4, r5 /*scratch*/
  18883. + lsr r8, 2
  18884. + or r8, r8, r9 << 30
  18885. + lsr r9, 2
  18886. + rjmp 23b
  18887. +
  18888. +
  18889. +__avr32_f64_div_res_subnormal:/* Divide result was subnormal. */
  18890. +#if defined(L_avr32_f64_div)
  18891. + /* Check how much we must scale down the mantissa. */
  18892. + neg r7
  18893. + sub r7, -1 /* We do no longer have an implicit bit. */
  18894. + satu r7 >> 0, 6 /* Saturate shift amount to max 63. */
  18895. + cp.w r7, 32
  18896. + brge 0f
  18897. + /* Shift amount <32 */
  18898. + /* Scale down quotient */
  18899. + rsub r6, r7, 32
  18900. + lsr r2, r2, r7
  18901. + lsl r12, r3, r6
  18902. + or r2, r12
  18903. + lsr r3, r3, r7
  18904. + /* Scale down the dividend to match the scaling of the quotient. */
  18905. + lsl r1, r10, r6
  18906. + lsr r10, r10, r7
  18907. + lsl r12, r11, r6
  18908. + or r10, r12
  18909. + lsr r11, r11, r7
  18910. + mov r0, 0
  18911. + rjmp 1f
  18912. +0:
  18913. + /* Shift amount >=32 */
  18914. + rsub r6, r7, 32
  18915. + moveq r0, 0
  18916. + moveq r12, 0
  18917. + breq 0f
  18918. + lsl r0, r10, r6
  18919. + lsl r12, r11, r6
  18920. +0:
  18921. + lsr r2, r3, r7
  18922. + mov r3, 0
  18923. + /* Scale down the dividend to match the scaling of the quotient. */
  18924. + lsr r1, r10, r7
  18925. + or r1, r12
  18926. + lsr r10, r11, r7
  18927. + mov r11, 0
  18928. +1:
  18929. + /* Start performing the same rounding as done for normal numbers
  18930. + but this time we have scaled the quotient and dividend and hence
  18931. + need a little different comparison. */
  18932. + /* Truncate and add guard bit. */
  18933. + andl r2, 0xff00
  18934. + orl r2, 0x0080
  18935. +
  18936. + /* Now do the multiplication. */
  18937. + mulu.d r6, r3, r8
  18938. + macu.d r6, r2, r9
  18939. + mulu.d r4, r2, r8
  18940. + mulu.d r8, r3, r9
  18941. + add r5, r6
  18942. + adc r8, r8, r7
  18943. + acr r9
  18944. +
  18945. + /* Set exponent to 0 */
  18946. + mov r7, 0
  18947. +
  18948. + /* Check if remainder is positive, negative or equal. */
  18949. + bfextu r12, r2, 8, 1 /* Get parity bit into bit 0 of r0 */
  18950. + cp r4, r0
  18951. + cpc r5, r1
  18952. + /* Now the rest of the rounding is the same as for normals. */
  18953. + rjmp __avr32_f64_div_round_subnormal
  18954. +
  18955. +#endif
  18956. +15:
  18957. + /* Flush to zero for the fast version. */
  18958. + mov r11, lr /*Get correct sign*/
  18959. + andh r11, 0x8000, COH
  18960. + mov r10, 0
  18961. + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
  18962. +
  18963. +16: /* Return NaN. */
  18964. + mov r11, -1
  18965. + mov r10, 0
  18966. + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
  18967. +
  18968. +17:
  18969. + /* Check if op1 is zero. */
  18970. + or r4, r10, r11
  18971. + breq __avr32_f64_div_op1_zero
  18972. + /* Return INF. */
  18973. + mov r11, lr /*Get correct sign*/
  18974. + andh r11, 0x8000, COH
  18975. + orh r11, 0x7ff0
  18976. + mov r10, 0
  18977. + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
  18978. +
  18979. +__avr32_f64_div_op1_zero:
  18980. + or r5, r8, r9 << 1
  18981. + breq 16b /* 0.0/0.0 -> NaN */
  18982. + bfextu r4, r9, 20, 11
  18983. + cp r4, 0x7ff
  18984. + brne 15b /* Return zero */
  18985. + /* Check if divisor is Inf or NaN */
  18986. + or r5, r8, r9 << 12
  18987. + breq 15b /* Divisor is inf -> return zero */
  18988. + rjmp 16b /* Return NaN */
  18989. +
  18990. +
  18991. +
  18992. +
  18993. +#endif
  18994. +
  18995. +#if defined(L_avr32_f32_addsub) || defined(L_avr32_f32_addsub_fast)
  18996. +
  18997. + .align 2
  18998. +__avr32_f32_sub_from_add:
  18999. + /* Switch sign on op2 */
  19000. + eorh r11, 0x8000
  19001. +
  19002. +#if defined(L_avr32_f32_addsub_fast)
  19003. + .global __avr32_f32_sub_fast
  19004. + .type __avr32_f32_sub_fast,@function
  19005. +__avr32_f32_sub_fast:
  19006. +#else
  19007. + .global __avr32_f32_sub
  19008. + .type __avr32_f32_sub,@function
  19009. +__avr32_f32_sub:
  19010. +#endif
  19011. +
  19012. + /* Check signs */
  19013. + eor r8, r11, r12
  19014. + /* Different signs, use subtraction. */
  19015. + brmi __avr32_f32_add_from_sub
  19016. +
  19017. + /* Get sign of op1 */
  19018. + mov r8, r12
  19019. + andh r12, 0x8000, COH
  19020. +
  19021. + /* Remove sign from operands */
  19022. + cbr r11, 31
  19023. +#if defined(L_avr32_f32_addsub_fast)
  19024. + reteq r8 /* If op2 is zero return op1 */
  19025. +#endif
  19026. + cbr r8, 31
  19027. +
  19028. + /* Put the number with the largest exponent in r10
  19029. + and the number with the smallest exponent in r9 */
  19030. + max r10, r8, r11
  19031. + min r9, r8, r11
  19032. + cp r10, r8 /*If largest operand (in R10) is not equal to op1*/
  19033. + subne r12, 1 /* Subtract 1 from sign, which will invert MSB of r12*/
  19034. + andh r12, 0x8000, COH /*Mask all but MSB*/
  19035. +
  19036. + /* Unpack exponent and mantissa of op1 */
  19037. + lsl r8, r10, 8
  19038. + sbr r8, 31 /* Set implicit bit. */
  19039. + lsr r10, 23
  19040. +
  19041. + /* op1 is NaN or Inf. */
  19042. + cp.w r10, 0xff
  19043. + breq __avr32_f32_sub_op1_nan_or_inf
  19044. +
  19045. + /* Unpack exponent and mantissa of op2 */
  19046. + lsl r11, r9, 8
  19047. + sbr r11, 31 /* Set implicit bit. */
  19048. + lsr r9, 23
  19049. +
  19050. +#if defined(L_avr32_f32_addsub)
  19051. + /* Keep sticky bit for correct IEEE rounding */
  19052. + st.w --sp, r12
  19053. +
  19054. + /* op2 is either zero or subnormal. */
  19055. + breq __avr32_f32_sub_op2_subnormal
  19056. +0:
  19057. + /* Get shift amount to scale mantissa of op2. */
  19058. + sub r12, r10, r9
  19059. +
  19060. + breq __avr32_f32_sub_shift_done
  19061. +
  19062. + /* Saturate the shift amount to 31. If the amount
  19063. + is any larger op2 is insignificant. */
  19064. + satu r12 >> 0, 5
  19065. +
  19066. + /* Put the remaining bits into r9.*/
  19067. + rsub r9, r12, 32
  19068. + lsl r9, r11, r9
  19069. +
  19070. + /* If the remaining bits are non-zero then we must subtract one
  19071. + more from opL. */
  19072. + subne r8, 1
  19073. + srne r9 /* LSB of r9 represents sticky bits. */
  19074. +
  19075. + /* Shift mantissa of op2 to same decimal point as the mantissa
  19076. + of op1. */
  19077. + lsr r11, r11, r12
  19078. +
  19079. +
  19080. +__avr32_f32_sub_shift_done:
  19081. + /* Now subtract the mantissas. */
  19082. + sub r8, r11
  19083. +
  19084. + ld.w r12, sp++
  19085. +
  19086. + /* Normalize resulting mantissa. */
  19087. + clz r11, r8
  19088. +
  19089. + retcs 0
  19090. + lsl r8, r8, r11
  19091. + sub r10, r11
  19092. + brle __avr32_f32_sub_subnormal_result
  19093. +
  19094. + /* Insert the bits we will remove from the mantissa into r9[31:24] */
  19095. + or r9, r9, r8 << 24
  19096. +#else
  19097. + /* Ignore sticky bit to simplify and speed up rounding */
  19098. + /* op2 is either zero or subnormal. */
  19099. + breq __avr32_f32_sub_op2_subnormal
  19100. +0:
  19101. + /* Get shift amount to scale mantissa of op2. */
  19102. + rsub r9, r10
  19103. +
  19104. + /* Saturate the shift amount to 31. If the amount
  19105. + is any larger op2 is insignificant. */
  19106. + satu r9 >> 0, 5
  19107. +
  19108. + /* Shift mantissa of op2 to same decimal point as the mantissa
  19109. + of op1. */
  19110. + lsr r11, r11, r9
  19111. +
  19112. + /* Now subtract the mantissas. */
  19113. + sub r8, r11
  19114. +
  19115. + /* Normalize resulting mantissa. */
  19116. + clz r9, r8
  19117. + retcs 0
  19118. + lsl r8, r8, r9
  19119. + sub r10, r9
  19120. + brle __avr32_f32_sub_subnormal_result
  19121. +#endif
  19122. +
  19123. + /* Pack result. */
  19124. + or r12, r12, r8 >> 8
  19125. + bfins r12, r10, 23, 8
  19126. +
  19127. + /* Round */
  19128. +__avr32_f32_sub_round:
  19129. +#if defined(L_avr32_f32_addsub)
  19130. + mov_imm r10, 0x80000000
  19131. + bld r12, 0
  19132. + subne r10, -1
  19133. + cp.w r9, r10
  19134. + subhs r12, -1
  19135. +#else
  19136. + bld r8, 7
  19137. + acr r12
  19138. +#endif
  19139. +
  19140. + ret r12
  19141. +
  19142. +
  19143. +__avr32_f32_sub_op2_subnormal:
  19144. + /* Fix implicit bit and adjust exponent of subnormals. */
  19145. + cbr r11, 31
  19146. + /* Set exponent to 1 if we do not have a zero. */
  19147. + movne r9,1
  19148. +
  19149. + /* Check if op1 is also subnormal. */
  19150. + cp.w r10, 0
  19151. + brne 0b
  19152. +
  19153. + cbr r8, 31
  19154. + /* If op1 is not zero set exponent to 1. */
  19155. + movne r10,1
  19156. +
  19157. + rjmp 0b
  19158. +
  19159. +__avr32_f32_sub_op1_nan_or_inf:
  19160. + /* Check if op1 is NaN, if so return NaN */
  19161. + lsl r11, r8, 1
  19162. + retne -1
  19163. +
  19164. + /* op1 is Inf. */
  19165. + bfins r12, r10, 23, 8 /* Generate Inf in r12 */
  19166. +
  19167. + /* Check if op2 is Inf. or NaN */
  19168. + lsr r11, r9, 23
  19169. + cp.w r11, 0xff
  19170. + retne r12 /* op2 not Inf or NaN, return op1 */
  19171. +
  19172. + ret -1 /* op2 Inf or NaN, return NaN */
  19173. +
  19174. +__avr32_f32_sub_subnormal_result:
  19175. + /* Check if the number is so small that
  19176. + it will be represented with zero. */
  19177. + rsub r10, r10, 9
  19178. + rsub r11, r10, 32
  19179. + retcs 0
  19180. +
  19181. + /* Shift the mantissa into the correct position.*/
  19182. + lsr r10, r8, r10
  19183. + /* Add sign bit. */
  19184. + or r12, r10
  19185. +
  19186. + /* Put the shifted out bits in the most significant part
  19187. + of r8. */
  19188. + lsl r8, r8, r11
  19189. +
  19190. +#if defined(L_avr32_f32_addsub)
  19191. + /* Add all the remainder bits used for rounding into r9 */
  19192. + or r9, r8
  19193. +#else
  19194. + lsr r8, 24
  19195. +#endif
  19196. + rjmp __avr32_f32_sub_round
  19197. +
  19198. +
  19199. + .align 2
  19200. +
  19201. +__avr32_f32_add_from_sub:
  19202. + /* Switch sign on op2 */
  19203. + eorh r11, 0x8000
  19204. +
  19205. +#if defined(L_avr32_f32_addsub_fast)
  19206. + .global __avr32_f32_add_fast
  19207. + .type __avr32_f32_add_fast,@function
  19208. +__avr32_f32_add_fast:
  19209. +#else
  19210. + .global __avr32_f32_add
  19211. + .type __avr32_f32_add,@function
  19212. +__avr32_f32_add:
  19213. +#endif
  19214. +
  19215. + /* Check signs */
  19216. + eor r8, r11, r12
  19217. + /* Different signs, use subtraction. */
  19218. + brmi __avr32_f32_sub_from_add
  19219. +
  19220. + /* Get sign of op1 */
  19221. + mov r8, r12
  19222. + andh r12, 0x8000, COH
  19223. +
  19224. + /* Remove sign from operands */
  19225. + cbr r11, 31
  19226. +#if defined(L_avr32_f32_addsub_fast)
  19227. + reteq r8 /* If op2 is zero return op1 */
  19228. +#endif
  19229. + cbr r8, 31
  19230. +
  19231. + /* Put the number with the largest exponent in r10
  19232. + and the number with the smallest exponent in r9 */
  19233. + max r10, r8, r11
  19234. + min r9, r8, r11
  19235. +
  19236. + /* Unpack exponent and mantissa of op1 */
  19237. + lsl r8, r10, 8
  19238. + sbr r8, 31 /* Set implicit bit. */
  19239. + lsr r10, 23
  19240. +
  19241. + /* op1 is NaN or Inf. */
  19242. + cp.w r10, 0xff
  19243. + breq __avr32_f32_add_op1_nan_or_inf
  19244. +
  19245. + /* Unpack exponent and mantissa of op2 */
  19246. + lsl r11, r9, 8
  19247. + sbr r11, 31 /* Set implicit bit. */
  19248. + lsr r9, 23
  19249. +
  19250. +#if defined(L_avr32_f32_addsub)
  19251. + /* op2 is either zero or subnormal. */
  19252. + breq __avr32_f32_add_op2_subnormal
  19253. +0:
  19254. + /* Keep sticky bit for correct IEEE rounding */
  19255. + st.w --sp, r12
  19256. +
  19257. + /* Get shift amount to scale mantissa of op2. */
  19258. + rsub r9, r10
  19259. +
  19260. + /* Saturate the shift amount to 31. If the amount
  19261. + is any larger op2 is insignificant. */
  19262. + satu r9 >> 0, 5
  19263. +
  19264. + /* Shift mantissa of op2 to same decimal point as the mantissa
  19265. + of op1. */
  19266. + lsr r12, r11, r9
  19267. +
  19268. + /* Put the remainding bits into r11[23:..].*/
  19269. + rsub r9, r9, (32-8)
  19270. + lsl r11, r11, r9
  19271. + /* Insert the bits we will remove from the mantissa into r11[31:24] */
  19272. + bfins r11, r12, 24, 8
  19273. +
  19274. + /* Now add the mantissas. */
  19275. + add r8, r12
  19276. +
  19277. + ld.w r12, sp++
  19278. +#else
  19279. + /* Ignore sticky bit to simplify and speed up rounding */
  19280. + /* op2 is either zero or subnormal. */
  19281. + breq __avr32_f32_add_op2_subnormal
  19282. +0:
  19283. + /* Get shift amount to scale mantissa of op2. */
  19284. + rsub r9, r10
  19285. +
  19286. + /* Saturate the shift amount to 31. If the amount
  19287. + is any larger op2 is insignificant. */
  19288. + satu r9 >> 0, 5
  19289. +
  19290. + /* Shift mantissa of op2 to same decimal point as the mantissa
  19291. + of op1. */
  19292. + lsr r11, r11, r9
  19293. +
  19294. + /* Now add the mantissas. */
  19295. + add r8, r11
  19296. +
  19297. +#endif
  19298. + /* Check if we overflowed. */
  19299. + brcs __avr32_f32_add_res_of
  19300. +1:
  19301. + /* Pack result. */
  19302. + or r12, r12, r8 >> 8
  19303. + bfins r12, r10, 23, 8
  19304. +
  19305. + /* Round */
  19306. +#if defined(L_avr32_f32_addsub)
  19307. + mov_imm r10, 0x80000000
  19308. + bld r12, 0
  19309. + subne r10, -1
  19310. + cp.w r11, r10
  19311. + subhs r12, -1
  19312. +#else
  19313. + bld r8, 7
  19314. + acr r12
  19315. +#endif
  19316. +
  19317. + ret r12
  19318. +
  19319. +__avr32_f32_add_op2_subnormal:
  19320. + /* Fix implicit bit and adjust exponent of subnormals. */
  19321. + cbr r11, 31
  19322. + /* Set exponent to 1 if we do not have a zero. */
  19323. + movne r9,1
  19324. +
  19325. + /* Check if op1 is also subnormal. */
  19326. + cp.w r10, 0
  19327. + brne 0b
  19328. + /* Both operands subnormal, just add the mantissas and
  19329. + pack. If the addition of the subnormal numbers results
  19330. + in a normal number then the exponent will automatically
  19331. + be set to 1 by the addition. */
  19332. + cbr r8, 31
  19333. + add r11, r8
  19334. + or r12, r12, r11 >> 8
  19335. + ret r12
  19336. +
  19337. +__avr32_f32_add_op1_nan_or_inf:
  19338. + /* Check if op1 is NaN, if so return NaN */
  19339. + lsl r11, r8, 1
  19340. + retne -1
  19341. +
  19342. + /* op1 is Inf. */
  19343. + bfins r12, r10, 23, 8 /* Generate Inf in r12 */
  19344. +
  19345. + /* Check if op2 is Inf. or NaN */
  19346. + lsr r11, r9, 23
  19347. + cp.w r11, 0xff
  19348. + retne r12 /* op2 not Inf or NaN, return op1 */
  19349. +
  19350. + lsl r9, 9
  19351. + reteq r12 /* op2 Inf return op1 */
  19352. + ret -1 /* op2 is NaN, return NaN */
  19353. +
  19354. +__avr32_f32_add_res_of:
  19355. + /* We overflowed. Increase exponent and shift mantissa.*/
  19356. + lsr r8, 1
  19357. + sub r10, -1
  19358. +
  19359. + /* Clear mantissa to set result to Inf if the exponent is 255. */
  19360. + cp.w r10, 255
  19361. + moveq r8, 0
  19362. + moveq r11, 0
  19363. + rjmp 1b
  19364. +
  19365. +
  19366. +#endif
  19367. +
  19368. +
  19369. +#if defined(L_avr32_f32_div) || defined(L_avr32_f32_div_fast)
  19370. + .align 2
  19371. +
  19372. +#if defined(L_avr32_f32_div_fast)
  19373. + .global __avr32_f32_div_fast
  19374. + .type __avr32_f32_div_fast,@function
  19375. +__avr32_f32_div_fast:
  19376. +#else
  19377. + .global __avr32_f32_div
  19378. + .type __avr32_f32_div,@function
  19379. +__avr32_f32_div:
  19380. +#endif
  19381. +
  19382. + eor r8, r11, r12 /* MSB(r8) = Sign(op1) ^ Sign(op2) */
  19383. +
  19384. + /* Unpack */
  19385. + lsl r12,1
  19386. + lsl r11,1
  19387. + breq 4f /* Check op2 for zero */
  19388. +
  19389. + tst r12, r12
  19390. + moveq r9, 0
  19391. + breq 12f
  19392. +
  19393. + /* Unpack op1*/
  19394. + /* exp: r9 */
  19395. + /* sf: r12 */
  19396. + lsr r9, r12, 24
  19397. + breq 11f /*If number is subnormal*/
  19398. + cp r9, 0xff
  19399. + brhs 2f /* Check op1 for NaN or Inf */
  19400. + lsl r12, 7
  19401. + sbr r12, 31 /*Implicit bit*/
  19402. +12:
  19403. +
  19404. + /* Unpack op2*/
  19405. + /* exp: r10 */
  19406. + /* sf: r11 */
  19407. + lsr r10, r11, 24
  19408. + breq 13f /*If number is subnormal*/
  19409. + cp r10, 0xff
  19410. + brhs 3f /* Check op2 for NaN or Inf */
  19411. + lsl r11,7
  19412. + sbr r11, 31 /*Implicit bit*/
  19413. +
  19414. + cp.w r9, 0
  19415. + subfeq r12, 0
  19416. + reteq 0 /* op1 is zero and op2 is not zero */
  19417. + /* or NaN so return zero */
  19418. +
  19419. +14:
  19420. +
  19421. + /* For UC3, store with predecrement is faster than stm */
  19422. + st.w --sp, r5
  19423. + st.d --sp, r6
  19424. +
  19425. + /* Calculate new exponent */
  19426. + sub r9, r10
  19427. + sub r9,-127
  19428. +
  19429. + /* Divide */
  19430. + /* Approximating 1/d with the following recurrence: */
  19431. + /* R[j+1] = R[j]*(2-R[j]*d) */
  19432. + /* Using 2.30 format */
  19433. + /* TWO: r10 */
  19434. + /* d: r5 */
  19435. + /* Multiply result : r6, r7 */
  19436. + /* Initial guess : r11 */
  19437. + /* New approximations : r11 */
  19438. + /* Dividend : r12 */
  19439. +
  19440. + /* Load TWO */
  19441. + mov_imm r10, 0x80000000
  19442. +
  19443. + lsr r12, 2 /* Get significand of Op1 in 2.30 format */
  19444. + lsr r5, r11, 2 /* Get significand of Op2 (=d) in 2.30 format */
  19445. +
  19446. + /* Load initial guess, using look-up table */
  19447. + /* Initial guess is of format 01.XY, where XY is constructed as follows: */
  19448. + /* Let d be of following format: 00.1xy....., then XY=~xy */
  19449. + /* For d=00.100 = 0,5 -> initial guess=01.11 = 1,75 */
  19450. + /* For d=00.101 = 0,625 -> initial guess=01.11 = 1,5 */
  19451. + /* For d=00.110 = 0,75 -> initial guess=01.11 = 1,25 */
  19452. + /* For d=00.111 = 0,875 -> initial guess=01.11 = 1,0 */
  19453. +
  19454. + lsr r11, r10, 1
  19455. + bfextu r6, r5, 27, 2
  19456. + com r6
  19457. + bfins r11, r6, 28, 2
  19458. +
  19459. + /* First approximation */
  19460. + /* r7 = R[j]*d */
  19461. + mulu.d r6, r11, r5
  19462. + /* r7 = 2-R[j]*d */
  19463. + sub r7, r10, r7<<2
  19464. + /* r11 = R[j]*(2-R[j]*d) */
  19465. + mulu.d r6, r11, r7
  19466. + lsl r11, r7, 2
  19467. +
  19468. + /* Second approximation */
  19469. + /* r7 = R[j]*d */
  19470. + mulu.d r6, r11, r5
  19471. + /* r7 = 2-R[j]*d */
  19472. + sub r7, r10, r7<<2
  19473. + /* r11 = R[j]*(2-R[j]*d) */
  19474. + mulu.d r6, r11, r7
  19475. + lsl r11, r7, 2
  19476. +
  19477. + /* Third approximation */
  19478. + /* r7 = R[j]*d */
  19479. + mulu.d r6, r11, r5
  19480. + /* r7 = 2-R[j]*d */
  19481. + sub r7, r10, r7<<2
  19482. + /* r11 = R[j]*(2-R[j]*d) */
  19483. + mulu.d r6, r11, r7
  19484. + lsl r11, r7, 2
  19485. +
  19486. + /* Fourth approximation */
  19487. + /* r7 = R[j]*d */
  19488. + mulu.d r6, r11, r5
  19489. + /* r7 = 2-R[j]*d */
  19490. + sub r7, r10, r7<<2
  19491. + /* r11 = R[j]*(2-R[j]*d) */
  19492. + mulu.d r6, r11, r7
  19493. + lsl r11, r7, 2
  19494. +
  19495. +
  19496. + /* Multiply with dividend to get quotient, r7 = sf(op1)/sf(op2) */
  19497. + mulu.d r6, r11, r12
  19498. +
  19499. + /* Shift by 3 to get result in 1.31 format, as required by the exponent. */
  19500. + /* Note that 1.31 format is already used by the exponent in r9, since */
  19501. + /* a bias of 127 was added to the result exponent, even though the implicit */
  19502. + /* bit was inserted. This gives the exponent an additional bias of 1, which */
  19503. + /* supports 1.31 format. */
  19504. + //lsl r10, r7, 3
  19505. +
  19506. + /* Adjust exponent and mantissa in case the result is of format
  19507. + 0000.1xxx to 0001.xxx*/
  19508. +#if defined(L_avr32_f32_div)
  19509. + lsr r12, 4 /* Scale dividend to 6.26 format to match the
  19510. + result of the multiplication of the divisor and
  19511. + quotient to get the remainder. */
  19512. +#endif
  19513. + bld r7, 31-3
  19514. + breq 0f
  19515. + lsl r7, 1
  19516. + sub r9, 1
  19517. +#if defined(L_avr32_f32_div)
  19518. + lsl r12, 1 /* Scale dividend to 5.27 format to match the
  19519. + result of the multiplication of the divisor and
  19520. + quotient to get the remainder. */
  19521. +#endif
  19522. +0:
  19523. + cp r9, 0
  19524. + brle __avr32_f32_div_res_subnormal /* Result was subnormal. */
  19525. +
  19526. +
  19527. +#if defined(L_avr32_f32_div)
  19528. + /* In order to round correctly we calculate the remainder:
  19529. + Remainder = dividend[r12] - divisor[r5]*quotient[r7]
  19530. + for the case when the quotient is halfway between the round-up
  19531. + value and the round down value. If the remainder then is negative
  19532. + it means that the quotient was to big and that it should not be
  19533. + rounded up, if the remainder is positive the quotient was to small
  19534. + and we need to round up. If the remainder is zero it means that the
  19535. + quotient is exact but since we need to remove the guard bit we should
  19536. + round to even. */
  19537. + andl r7, 0xffe0
  19538. + orl r7, 0x0010
  19539. +
  19540. + /* Now do the multiplication. The quotient has the format 4.28
  19541. + while the divisor has the format 2.30 which gives a result
  19542. + of 6.26 */
  19543. + mulu.d r10, r5, r7
  19544. +
  19545. + /* Check if remainder is positive, negative or equal. */
  19546. + bfextu r5, r7, 5, 1 /* Get parity bit into bit 0 of r5 */
  19547. + cp r10, 0
  19548. +__avr32_f32_div_round_subnormal:
  19549. + cpc r11, r12
  19550. + srlo r11 /* Remainder positive: we need to round up.*/
  19551. + moveq r11, r5 /* Remainder zero: round up if mantissa odd. */
  19552. +#else
  19553. + bfextu r11, r7, 4, 1 /* Get guard bit */
  19554. +#endif
  19555. +
  19556. + /* Pack final result*/
  19557. + lsr r12, r7, 5
  19558. + bfins r12, r9, 23, 8
  19559. + /* For UC3, load with postincrement is faster than ldm */
  19560. + ld.d r6, sp++
  19561. + ld.w r5, sp++
  19562. + bld r8, 31
  19563. + bst r12, 31
  19564. + /* Rounding add. */
  19565. + add r12, r11
  19566. + ret r12
  19567. +
  19568. +__divsf_return_op1:
  19569. + lsl r8, 1
  19570. + ror r12
  19571. + ret r12
  19572. +
  19573. +
  19574. +2:
  19575. + /* Op1 is NaN or inf */
  19576. + retne -1 /* Return NaN if op1 is NaN */
  19577. + /* Op1 is inf check op2 */
  19578. + mov_imm r9, 0xff000000
  19579. + cp r11, r9
  19580. + brlo __divsf_return_op1 /* inf/number gives inf */
  19581. + ret -1 /* The rest gives NaN*/
  19582. +3:
  19583. + /* Op2 is NaN or inf */
  19584. + reteq 0 /* Return zero if number/inf*/
  19585. + ret -1 /* Return NaN*/
  19586. +4:
  19587. + /* Op1 is zero ? */
  19588. + tst r12,r12
  19589. + reteq -1 /* 0.0/0.0 is NaN */
  19590. + /* Op1 is Nan? */
  19591. + lsr r9, r12, 24
  19592. + breq 11f /*If number is subnormal*/
  19593. + cp r9, 0xff
  19594. + brhs 2b /* Check op1 for NaN or Inf */
  19595. + /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/
  19596. + mov_imm r12, 0xff000000
  19597. + rjmp __divsf_return_op1
  19598. +
  19599. +11: /* Op1 was denormal. Fix it. */
  19600. + lsl r12,7
  19601. + clz r9,r12
  19602. + lsl r12,r12,r9
  19603. + rsub r9,r9,1
  19604. + rjmp 12b
  19605. +
  19606. +13: /* Op2 was denormal. Fix it. */
  19607. + lsl r11,7
  19608. + clz r10,r11
  19609. + lsl r11,r11,r10
  19610. + rsub r10,r10,1
  19611. + rjmp 14b
  19612. +
  19613. +
  19614. +__avr32_f32_div_res_subnormal: /* Divide result was subnormal */
  19615. +#if defined(L_avr32_f32_div)
  19616. + /* Check how much we must scale down the mantissa. */
  19617. + neg r9
  19618. + sub r9, -1 /* We do no longer have an implicit bit. */
  19619. + satu r9 >> 0, 5 /* Saturate shift amount to max 32. */
  19620. + /* Scale down quotient */
  19621. + rsub r10, r9, 32
  19622. + lsr r7, r7, r9
  19623. + /* Scale down the dividend to match the scaling of the quotient. */
  19624. + lsl r6, r12, r10 /* Make the divident 64-bit and put the lsw in r6 */
  19625. + lsr r12, r12, r9
  19626. +
  19627. + /* Start performing the same rounding as done for normal numbers
  19628. + but this time we have scaled the quotient and dividend and hence
  19629. + need a little different comparison. */
  19630. + andl r7, 0xffe0
  19631. + orl r7, 0x0010
  19632. +
  19633. + /* Now do the multiplication. The quotient has the format 4.28
  19634. + while the divisor has the format 2.30 which gives a result
  19635. + of 6.26 */
  19636. + mulu.d r10, r5, r7
  19637. +
  19638. + /* Set exponent to 0 */
  19639. + mov r9, 0
  19640. +
  19641. + /* Check if remainder is positive, negative or equal. */
  19642. + bfextu r5, r7, 5, 1 /* Get parity bit into bit 0 of r5 */
  19643. + cp r10, r6
  19644. + rjmp __avr32_f32_div_round_subnormal
  19645. +
  19646. +#else
  19647. + ld.d r6, sp++
  19648. + ld.w r5, sp++
  19649. + /*Flush to zero*/
  19650. + ret 0
  19651. +#endif
  19652. +#endif
  19653. +
  19654. +#ifdef L_avr32_f32_mul
  19655. + .global __avr32_f32_mul
  19656. + .type __avr32_f32_mul,@function
  19657. +
  19658. +
  19659. +__avr32_f32_mul:
  19660. + mov r8, r12
  19661. + eor r12, r11 /* MSB(r8) = Sign(op1) ^ Sign(op2) */
  19662. + andh r12, 0x8000, COH
  19663. +
  19664. + /* arrange operands so that that op1 >= op2 */
  19665. + cbr r8, 31
  19666. + breq __avr32_f32_mul_op1_zero
  19667. + cbr r11, 31
  19668. +
  19669. + /* Put the number with the largest exponent in r10
  19670. + and the number with the smallest exponent in r9 */
  19671. + max r10, r8, r11
  19672. + min r9, r8, r11
  19673. +
  19674. + /* Unpack exponent and mantissa of op1 */
  19675. + lsl r8, r10, 8
  19676. + sbr r8, 31 /* Set implicit bit. */
  19677. + lsr r10, 23
  19678. +
  19679. + /* op1 is NaN or Inf. */
  19680. + cp.w r10, 0xff
  19681. + breq __avr32_f32_mul_op1_nan_or_inf
  19682. +
  19683. + /* Unpack exponent and mantissa of op2 */
  19684. + lsl r11, r9, 8
  19685. + sbr r11, 31 /* Set implicit bit. */
  19686. + lsr r9, 23
  19687. +
  19688. + /* op2 is either zero or subnormal. */
  19689. + breq __avr32_f32_mul_op2_subnormal
  19690. +0:
  19691. + /* Calculate new exponent */
  19692. + add r9,r10
  19693. +
  19694. + /* Do the multiplication */
  19695. + mulu.d r10,r8,r11
  19696. +
  19697. + /* We might need to scale up by two if the MSB of the result is
  19698. + zero. */
  19699. + lsl r8, r11, 1
  19700. + movcc r11, r8
  19701. + subcc r9, 1
  19702. +
  19703. + /* Put the shifted out bits of the mantissa into r10 */
  19704. + lsr r10, 8
  19705. + bfins r10, r11, 24, 8
  19706. +
  19707. + sub r9,(127-1) /* remove extra exponent bias */
  19708. + brle __avr32_f32_mul_res_subnormal
  19709. +
  19710. + /* Check for Inf. */
  19711. + cp.w r9, 0xff
  19712. + brge 1f
  19713. +
  19714. + /* Pack result. */
  19715. + or r12, r12, r11 >> 8
  19716. + bfins r12, r9, 23, 8
  19717. +
  19718. + /* Round */
  19719. +__avr32_f32_mul_round:
  19720. + mov_imm r8, 0x80000000
  19721. + bld r12, 0
  19722. + subne r8, -1
  19723. +
  19724. + cp.w r10, r8
  19725. + subhs r12, -1
  19726. +
  19727. + ret r12
  19728. +
  19729. +1:
  19730. + /* Return Inf */
  19731. + orh r12, 0x7f80
  19732. + ret r12
  19733. +
  19734. +__avr32_f32_mul_op2_subnormal:
  19735. + cbr r11, 31
  19736. + clz r9, r11
  19737. + retcs 0 /* op2 is zero. Return 0 */
  19738. + sub r9, 8
  19739. + lsl r11, r11, r9
  19740. + rsub r9, r9, 1
  19741. +
  19742. + /* Check if op2 is subnormal. */
  19743. + tst r10, r10
  19744. + brne 0b
  19745. +
  19746. + /* op2 is subnormal */
  19747. + cbr r8, 31
  19748. + clz r10, r11
  19749. + retcs 0 /* op1 is zero. Return 0 */
  19750. + lsl r8, r8, r10
  19751. + rsub r10, r10, 1
  19752. +
  19753. + rjmp 0b
  19754. +
  19755. +
  19756. +__avr32_f32_mul_op1_nan_or_inf:
  19757. + /* Check if op1 is NaN, if so return NaN */
  19758. + lsl r11, r8, 1
  19759. + retne -1
  19760. +
  19761. + /* op1 is Inf. */
  19762. + tst r9, r9
  19763. + reteq -1 /* Inf * 0 -> NaN */
  19764. +
  19765. + bfins r12, r10, 23, 8 /* Generate Inf in r12 */
  19766. +
  19767. + /* Check if op2 is Inf. or NaN */
  19768. + lsr r11, r9, 23
  19769. + cp.w r11, 0xff
  19770. + retne r12 /* op2 not Inf or NaN, return Info */
  19771. +
  19772. + lsl r9, 9
  19773. + reteq r12 /* op2 Inf return Inf */
  19774. + ret -1 /* op2 is NaN, return NaN */
  19775. +
  19776. +__avr32_f32_mul_res_subnormal:
  19777. + /* Check if the number is so small that
  19778. + it will be represented with zero. */
  19779. + rsub r9, r9, 9
  19780. + rsub r8, r9, 32
  19781. + retcs 0
  19782. +
  19783. + /* Shift the mantissa into the correct position.*/
  19784. + lsr r9, r11, r9
  19785. + /* Add sign bit. */
  19786. + or r12, r9
  19787. + /* Put the shifted out bits in the most significant part
  19788. + of r8. */
  19789. + lsl r11, r11, r8
  19790. +
  19791. + /* Add all the remainder bits used for rounding into r11 */
  19792. + andh r10, 0x00FF
  19793. + or r10, r11
  19794. + rjmp __avr32_f32_mul_round
  19795. +
  19796. +__avr32_f32_mul_op1_zero:
  19797. + bfextu r10, r11, 23, 8
  19798. + cp.w r10, 0xff
  19799. + retne r12
  19800. + reteq -1
  19801. +
  19802. +#endif
  19803. +
  19804. +
  19805. +#ifdef L_avr32_s32_to_f32
  19806. + .global __avr32_s32_to_f32
  19807. + .type __avr32_s32_to_f32,@function
  19808. +__avr32_s32_to_f32:
  19809. + cp r12, 0
  19810. + reteq r12 /* If zero then return zero float */
  19811. + mov r11, r12 /* Keep the sign */
  19812. + abs r12 /* Compute the absolute value */
  19813. + mov r10, 31 + 127 /* Set the correct exponent */
  19814. +
  19815. + /* Normalize */
  19816. + normalize_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
  19817. +
  19818. + /* Check for subnormal result */
  19819. + cp.w r10, 0
  19820. + brle __avr32_s32_to_f32_subnormal
  19821. +
  19822. + round_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
  19823. + pack_sf r12 /*sf*/, r10 /*exp*/, r12 /*mant*/
  19824. + lsl r11, 1
  19825. + ror r12
  19826. + ret r12
  19827. +
  19828. +__avr32_s32_to_f32_subnormal:
  19829. + /* Adjust a subnormal result */
  19830. + adjust_subnormal_sf r12/*sf*/, r10 /*exp*/, r12 /*mant*/, r11/*sign*/, r9 /*scratch*/
  19831. + ret r12
  19832. +
  19833. +#endif
  19834. +
  19835. +#ifdef L_avr32_u32_to_f32
  19836. + .global __avr32_u32_to_f32
  19837. + .type __avr32_u32_to_f32,@function
  19838. +__avr32_u32_to_f32:
  19839. + cp r12, 0
  19840. + reteq r12 /* If zero then return zero float */
  19841. + mov r10, 31 + 127 /* Set the correct exponent */
  19842. +
  19843. + /* Normalize */
  19844. + normalize_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
  19845. +
  19846. + /* Check for subnormal result */
  19847. + cp.w r10, 0
  19848. + brle __avr32_u32_to_f32_subnormal
  19849. +
  19850. + round_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
  19851. + pack_sf r12 /*sf*/, r10 /*exp*/, r12 /*mant*/
  19852. + lsr r12,1 /* Sign bit is 0 for unsigned int */
  19853. + ret r12
  19854. +
  19855. +__avr32_u32_to_f32_subnormal:
  19856. + /* Adjust a subnormal result */
  19857. + mov r8, 0
  19858. + adjust_subnormal_sf r12/*sf*/,r10 /*exp*/, r12 /*mant*/,r8/*sign*/, r9 /*scratch*/
  19859. + ret r12
  19860. +
  19861. +
  19862. +#endif
  19863. +
  19864. +
  19865. +#ifdef L_avr32_f32_to_s32
  19866. + .global __avr32_f32_to_s32
  19867. + .type __avr32_f32_to_s32,@function
  19868. +__avr32_f32_to_s32:
  19869. + bfextu r11, r12, 23, 8
  19870. + sub r11,127 /* Fix bias */
  19871. + retlo 0 /* Negative exponent yields zero integer */
  19872. +
  19873. + /* Shift mantissa into correct position */
  19874. + rsub r11,r11,31 /* Shift amount */
  19875. + lsl r10,r12,8 /* Get mantissa */
  19876. + sbr r10,31 /* Add implicit bit */
  19877. + lsr r10,r10,r11 /* Perform shift */
  19878. + lsl r12,1 /* Check sign */
  19879. + retcc r10 /* if positive, we are done */
  19880. + neg r10 /* if negative float, negate result */
  19881. + ret r10
  19882. +
  19883. +#endif
  19884. +
  19885. +#ifdef L_avr32_f32_to_u32
  19886. + .global __avr32_f32_to_u32
  19887. + .type __avr32_f32_to_u32,@function
  19888. +__avr32_f32_to_u32:
  19889. + cp r12,0
  19890. + retmi 0 /* Negative numbers gives 0 */
  19891. + bfextu r11, r12, 23, 8 /* Extract exponent */
  19892. + sub r11,127 /* Fix bias */
  19893. + retlo 0 /* Negative exponent yields zero integer */
  19894. +
  19895. + /* Shift mantissa into correct position */
  19896. + rsub r11,r11,31 /* Shift amount */
  19897. + lsl r12,8 /* Get mantissa */
  19898. + sbr r12,31 /* Add implicit bit */
  19899. + lsr r12,r12,r11 /* Perform shift */
  19900. + ret r12
  19901. +
  19902. +#endif
  19903. +
  19904. +#ifdef L_avr32_f32_to_f64
  19905. + .global __avr32_f32_to_f64
  19906. + .type __avr32_f32_to_f64,@function
  19907. +
  19908. +__avr32_f32_to_f64:
  19909. + lsl r11,r12,1 /* Remove sign bit, keep original value in r12*/
  19910. + moveq r10, 0
  19911. + reteq r11 /* Return zero if input is zero */
  19912. +
  19913. + bfextu r9,r11,24,8 /* Get exponent */
  19914. + cp.w r9,0xff /* check for NaN or inf */
  19915. + breq 0f
  19916. +
  19917. + lsl r11,7 /* Convert sf mantissa to df format */
  19918. + mov r10,0
  19919. +
  19920. + /* Check if implicit bit should be set */
  19921. + cp.w r9, 0
  19922. + subeq r9,-1 /* Adjust exponent if it was 0 */
  19923. + srne r8
  19924. + or r11, r11, r8 << 31 /* Set implicit bit if needed */
  19925. + sub r9,(127-0x3ff) /* Convert exponent to df format exponent */
  19926. +
  19927. + /*We know that low register of mantissa is 0, and will be unaffected by normalization.*/
  19928. + /*We can therefore use the faster normalize_sf function instead of normalize_df.*/
  19929. + normalize_sf r9 /*exp*/, r11 /*mantissa*/, r8 /*scratch*/
  19930. + pack_df r9 /*exp*/, r10, r11 /*mantissa*/, r10, r11 /*df*/
  19931. +
  19932. +__extendsfdf_return_op1:
  19933. + /* Rotate in sign bit */
  19934. + lsl r12, 1
  19935. + ror r11
  19936. + ret r11
  19937. +
  19938. +0:
  19939. + /* Inf or NaN*/
  19940. + mov_imm r10, 0xffe00000
  19941. + lsl r11,8 /* check mantissa */
  19942. + movne r11, -1 /* Return NaN */
  19943. + moveq r11, r10 /* Return inf */
  19944. + mov r10, 0
  19945. + rjmp __extendsfdf_return_op1
  19946. +#endif
  19947. +
  19948. +
  19949. +#ifdef L_avr32_f64_to_f32
  19950. + .global __avr32_f64_to_f32
  19951. + .type __avr32_f64_to_f32,@function
  19952. +
  19953. +__avr32_f64_to_f32:
  19954. + /* Unpack */
  19955. + lsl r9,r11,1 /* Unpack exponent */
  19956. + lsr r9,21
  19957. +
  19958. + reteq 0 /* If exponent is 0 the number is so small
  19959. + that the conversion to single float gives
  19960. + zero */
  19961. +
  19962. + lsl r8,r11,10 /* Adjust mantissa */
  19963. + or r12,r8,r10>>22
  19964. +
  19965. + lsl r10,10 /* Check if there are any remaining bits
  19966. + in the low part of the mantissa.*/
  19967. + neg r10
  19968. + rol r12 /* If there were remaining bits then set lsb
  19969. + of mantissa to 1 */
  19970. +
  19971. + cp r9,0x7ff
  19972. + breq 2f /* Check for NaN or inf */
  19973. +
  19974. + sub r9,(0x3ff-127) /* Adjust bias of exponent */
  19975. + sbr r12,31 /* set the implicit bit.*/
  19976. +
  19977. + cp.w r9, 0 /* Check for subnormal number */
  19978. + brle 3f
  19979. +
  19980. + round_sf r9 /*exp*/, r12 /*mant*/, r10 /*scratch*/
  19981. + pack_sf r12 /*sf*/, r9 /*exp*/, r12 /*mant*/
  19982. +__truncdfsf_return_op1:
  19983. + /* Rotate in sign bit */
  19984. + lsl r11, 1
  19985. + ror r12
  19986. + ret r12
  19987. +
  19988. +2:
  19989. + /* NaN or inf */
  19990. + cbr r12,31 /* clear implicit bit */
  19991. + retne -1 /* Return NaN if mantissa not zero */
  19992. + mov_imm r12, 0x7f800000
  19993. + ret r12 /* Return inf */
  19994. +
  19995. +3: /* Result is subnormal. Adjust it.*/
  19996. + adjust_subnormal_sf r12/*sf*/,r9 /*exp*/, r12 /*mant*/, r11/*sign*/, r10 /*scratch*/
  19997. + ret r12
  19998. +
  19999. +
  20000. +#endif
  20001. +
  20002. +#if defined(L_mulsi3) && defined(__AVR32_NO_MUL__)
  20003. + .global __mulsi3
  20004. + .type __mulsi3,@function
  20005. +
  20006. +__mulsi3:
  20007. + mov r9, 0
  20008. +0:
  20009. + lsr r11, 1
  20010. + addcs r9, r9, r12
  20011. + breq 1f
  20012. + lsl r12, 1
  20013. + rjmp 0b
  20014. +1:
  20015. + ret r9
  20016. +#endif
  20017. --- /dev/null
  20018. +++ b/gcc/config/avr32/lib2funcs.S
  20019. @@ -0,0 +1,21 @@
  20020. + .align 4
  20021. + .global __nonlocal_goto
  20022. + .type __nonlocal_goto,@function
  20023. +
  20024. +/* __nonlocal_goto: This function handles nonlocal_goto's in gcc.
  20025. +
  20026. + parameter 0 (r12) = New Frame Pointer
  20027. + parameter 1 (r11) = Address to goto
  20028. + parameter 2 (r10) = New Stack Pointer
  20029. +
  20030. + This function invalidates the return stack, since it returns from a
  20031. + function without using a return instruction.
  20032. +*/
  20033. +__nonlocal_goto:
  20034. + mov r7, r12
  20035. + mov sp, r10
  20036. + frs # Flush return stack
  20037. + mov pc, r11
  20038. +
  20039. +
  20040. +
  20041. --- /dev/null
  20042. +++ b/gcc/config/avr32/linux-elf.h
  20043. @@ -0,0 +1,151 @@
  20044. +/*
  20045. + Linux/Elf specific definitions.
  20046. + Copyright 2003-2006 Atmel Corporation.
  20047. +
  20048. + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
  20049. + and H�vard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  20050. +
  20051. + This file is part of GCC.
  20052. +
  20053. + This program is free software; you can redistribute it and/or modify
  20054. + it under the terms of the GNU General Public License as published by
  20055. + the Free Software Foundation; either version 2 of the License, or
  20056. + (at your option) any later version.
  20057. +
  20058. + This program is distributed in the hope that it will be useful,
  20059. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  20060. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20061. + GNU General Public License for more details.
  20062. +
  20063. + You should have received a copy of the GNU General Public License
  20064. + along with this program; if not, write to the Free Software
  20065. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  20066. +
  20067. +
  20068. +
  20069. +/* elfos.h should have already been included. Now just override
  20070. + any conflicting definitions and add any extras. */
  20071. +
  20072. +/* Run-time Target Specification. */
  20073. +#undef TARGET_VERSION
  20074. +#define TARGET_VERSION fputs (" (AVR32 GNU/Linux with ELF)", stderr);
  20075. +
  20076. +/* Do not assume anything about header files. */
  20077. +#define NO_IMPLICIT_EXTERN_C
  20078. +
  20079. +/* The GNU C++ standard library requires that these macros be defined. */
  20080. +#undef CPLUSPLUS_CPP_SPEC
  20081. +#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
  20082. +
  20083. +/* Now we define the strings used to build the spec file. */
  20084. +#undef LIB_SPEC
  20085. +#define LIB_SPEC \
  20086. + "%{pthread:-lpthread} \
  20087. + %{shared:-lc} \
  20088. + %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
  20089. +
  20090. +/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add
  20091. + the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
  20092. + provides part of the support for getting C++ file-scope static
  20093. + object constructed before entering `main'. */
  20094. +
  20095. +#undef STARTFILE_SPEC
  20096. +#define STARTFILE_SPEC \
  20097. + "%{!shared: \
  20098. + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \
  20099. + %{!p:%{profile:gcrt1.o%s} \
  20100. + %{!profile:crt1.o%s}}}} \
  20101. + crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
  20102. +
  20103. +/* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on
  20104. + the GNU/Linux magical crtend.o file (see crtstuff.c) which
  20105. + provides part of the support for getting C++ file-scope static
  20106. + object constructed before entering `main', followed by a normal
  20107. + GNU/Linux "finalizer" file, `crtn.o'. */
  20108. +
  20109. +#undef ENDFILE_SPEC
  20110. +#define ENDFILE_SPEC \
  20111. + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
  20112. +
  20113. +#undef ASM_SPEC
  20114. +#define ASM_SPEC "%{!mno-pic:%{!fno-pic:--pic}} %{mrelax|O*:%{mno-relax|O0|O1: ;:--linkrelax}} %{mcpu=*:-mcpu=%*}"
  20115. +
  20116. +#undef LINK_SPEC
  20117. +#define LINK_SPEC "%{version:-v} \
  20118. + %{static:-Bstatic} \
  20119. + %{shared:-shared} \
  20120. + %{symbolic:-Bsymbolic} \
  20121. + %{rdynamic:-export-dynamic} \
  20122. + %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0} \
  20123. + %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}}"
  20124. +
  20125. +#define TARGET_OS_CPP_BUILTINS() LINUX_TARGET_OS_CPP_BUILTINS()
  20126. +
  20127. +/* This is how we tell the assembler that two symbols have the same value. */
  20128. +#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \
  20129. + do \
  20130. + { \
  20131. + assemble_name (FILE, NAME1); \
  20132. + fputs (" = ", FILE); \
  20133. + assemble_name (FILE, NAME2); \
  20134. + fputc ('\n', FILE); \
  20135. + } \
  20136. + while (0)
  20137. +
  20138. +
  20139. +
  20140. +#undef CC1_SPEC
  20141. +#define CC1_SPEC "%{profile:-p}"
  20142. +
  20143. +/* Target CPU builtins. */
  20144. +#define TARGET_CPU_CPP_BUILTINS() \
  20145. + do \
  20146. + { \
  20147. + builtin_define ("__avr32__"); \
  20148. + builtin_define ("__AVR32__"); \
  20149. + builtin_define ("__AVR32_LINUX__"); \
  20150. + builtin_define (avr32_part->macro); \
  20151. + builtin_define (avr32_arch->macro); \
  20152. + if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \
  20153. + builtin_define ("__AVR32_AVR32A__"); \
  20154. + else \
  20155. + builtin_define ("__AVR32_AVR32B__"); \
  20156. + if (TARGET_UNALIGNED_WORD) \
  20157. + builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \
  20158. + if (TARGET_SIMD) \
  20159. + builtin_define ("__AVR32_HAS_SIMD__"); \
  20160. + if (TARGET_DSP) \
  20161. + builtin_define ("__AVR32_HAS_DSP__"); \
  20162. + if (TARGET_RMW) \
  20163. + builtin_define ("__AVR32_HAS_RMW__"); \
  20164. + if (TARGET_BRANCH_PRED) \
  20165. + builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \
  20166. + if (TARGET_FAST_FLOAT) \
  20167. + builtin_define ("__AVR32_FAST_FLOAT__"); \
  20168. + } \
  20169. + while (0)
  20170. +
  20171. +
  20172. +
  20173. +/* Call the function profiler with a given profile label. */
  20174. +#undef FUNCTION_PROFILER
  20175. +#define FUNCTION_PROFILER(STREAM, LABELNO) \
  20176. + do \
  20177. + { \
  20178. + fprintf (STREAM, "\tmov\tlr, lo(mcount)\n\torh\tlr, hi(mcount)\n"); \
  20179. + fprintf (STREAM, "\ticall lr\n"); \
  20180. + } \
  20181. + while (0)
  20182. +
  20183. +#define NO_PROFILE_COUNTERS 1
  20184. +
  20185. +/* For dynamic libraries to work */
  20186. +/* #define PLT_REG_CALL_CLOBBERED 1 */
  20187. +#define AVR32_ALWAYS_PIC 1
  20188. +
  20189. +/* uclibc does not implement sinf, cosf etc. */
  20190. +#undef TARGET_C99_FUNCTIONS
  20191. +#define TARGET_C99_FUNCTIONS 0
  20192. +
  20193. +#define LINK_GCC_C_SEQUENCE_SPEC \
  20194. + "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
  20195. --- /dev/null
  20196. +++ b/gcc/config/avr32/predicates.md
  20197. @@ -0,0 +1,422 @@
  20198. +;; AVR32 predicates file.
  20199. +;; Copyright 2003-2006 Atmel Corporation.
  20200. +;;
  20201. +;; Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
  20202. +;;
  20203. +;; This file is part of GCC.
  20204. +;;
  20205. +;; This program is free software; you can redistribute it and/or modify
  20206. +;; it under the terms of the GNU General Public License as published by
  20207. +;; the Free Software Foundation; either version 2 of the License, or
  20208. +;; (at your option) any later version.
  20209. +;;
  20210. +;; This program is distributed in the hope that it will be useful,
  20211. +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  20212. +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20213. +;; GNU General Public License for more details.
  20214. +;;
  20215. +;; You should have received a copy of the GNU General Public License
  20216. +;; along with this program; if not, write to the Free Software
  20217. +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20218. +
  20219. +
  20220. +;; True if the operand is a memory reference which contains an
  20221. +;; Address consisting of a single pointer register
  20222. +(define_predicate "avr32_indirect_register_operand"
  20223. + (and (match_code "mem")
  20224. + (match_test "register_operand(XEXP(op, 0), SImode)")))
  20225. +
  20226. +
  20227. +
  20228. +;; Address expression with a base pointer offset with
  20229. +;; a register displacement
  20230. +(define_predicate "avr32_indexed_memory_operand"
  20231. + (and (match_code "mem")
  20232. + (match_test "GET_CODE(XEXP(op, 0)) == PLUS"))
  20233. + {
  20234. +
  20235. + rtx op0 = XEXP(XEXP(op, 0), 0);
  20236. + rtx op1 = XEXP(XEXP(op, 0), 1);
  20237. +
  20238. + return ((avr32_address_register_rtx_p (op0, 0)
  20239. + && avr32_legitimate_index_p (GET_MODE(op), op1, 0))
  20240. + || (avr32_address_register_rtx_p (op1, 0)
  20241. + && avr32_legitimate_index_p (GET_MODE(op), op0, 0)));
  20242. +
  20243. + })
  20244. +
  20245. +;; Operand suitable for the ld.sb instruction
  20246. +(define_predicate "load_sb_memory_operand"
  20247. + (ior (match_operand 0 "avr32_indirect_register_operand")
  20248. + (match_operand 0 "avr32_indexed_memory_operand")))
  20249. +
  20250. +
  20251. +;; Operand suitable as operand to insns sign extending QI values
  20252. +(define_predicate "extendqi_operand"
  20253. + (ior (match_operand 0 "load_sb_memory_operand")
  20254. + (match_operand 0 "register_operand")))
  20255. +
  20256. +(define_predicate "post_inc_memory_operand"
  20257. + (and (match_code "mem")
  20258. + (match_test "(GET_CODE(XEXP(op, 0)) == POST_INC)
  20259. + && REG_P(XEXP(XEXP(op, 0), 0))")))
  20260. +
  20261. +(define_predicate "pre_dec_memory_operand"
  20262. + (and (match_code "mem")
  20263. + (match_test "(GET_CODE(XEXP(op, 0)) == PRE_DEC)
  20264. + && REG_P(XEXP(XEXP(op, 0), 0))")))
  20265. +
  20266. +;; Operand suitable for add instructions
  20267. +(define_predicate "avr32_add_operand"
  20268. + (ior (match_operand 0 "register_operand")
  20269. + (and (match_operand 0 "immediate_operand")
  20270. + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'I', \"Is21\")"))))
  20271. +
  20272. +;; Operand is a power of two immediate
  20273. +(define_predicate "power_of_two_operand"
  20274. + (match_code "const_int")
  20275. +{
  20276. + HOST_WIDE_INT value = INTVAL (op);
  20277. +
  20278. + return value != 0 && (value & (value - 1)) == 0;
  20279. +})
  20280. +
  20281. +;; Operand is a multiple of 8 immediate
  20282. +(define_predicate "multiple_of_8_operand"
  20283. + (match_code "const_int")
  20284. +{
  20285. + HOST_WIDE_INT value = INTVAL (op);
  20286. +
  20287. + return (value & 0x7) == 0 ;
  20288. +})
  20289. +
  20290. +;; Operand is a multiple of 16 immediate
  20291. +(define_predicate "multiple_of_16_operand"
  20292. + (match_code "const_int")
  20293. +{
  20294. + HOST_WIDE_INT value = INTVAL (op);
  20295. +
  20296. + return (value & 0xf) == 0 ;
  20297. +})
  20298. +
  20299. +;; Operand is a mask used for masking away upper bits of a reg
  20300. +(define_predicate "avr32_mask_upper_bits_operand"
  20301. + (match_code "const_int")
  20302. +{
  20303. + HOST_WIDE_INT value = INTVAL (op) + 1;
  20304. +
  20305. + return value != 1 && value != 0 && (value & (value - 1)) == 0;
  20306. +})
  20307. +
  20308. +
  20309. +;; Operand suitable for mul instructions
  20310. +(define_predicate "avr32_mul_operand"
  20311. + (ior (match_operand 0 "register_operand")
  20312. + (and (match_operand 0 "immediate_operand")
  20313. + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")"))))
  20314. +
  20315. +;; True for logical binary operators.
  20316. +(define_predicate "logical_binary_operator"
  20317. + (match_code "ior,xor,and"))
  20318. +
  20319. +;; True for logical shift operators
  20320. +(define_predicate "logical_shift_operator"
  20321. + (match_code "ashift,lshiftrt"))
  20322. +
  20323. +;; True for shift operand for logical and, or and eor insns
  20324. +(define_predicate "avr32_logical_shift_operand"
  20325. + (and (match_code "ashift,lshiftrt")
  20326. + (ior (and (match_test "GET_CODE(XEXP(op, 1)) == CONST_INT")
  20327. + (match_test "register_operand(XEXP(op, 0), GET_MODE(XEXP(op, 0)))"))
  20328. + (and (match_test "GET_CODE(XEXP(op, 0)) == CONST_INT")
  20329. + (match_test "register_operand(XEXP(op, 1), GET_MODE(XEXP(op, 1)))"))))
  20330. + )
  20331. +
  20332. +
  20333. +;; Predicate for second operand to and, ior and xor insn patterns
  20334. +(define_predicate "avr32_logical_insn_operand"
  20335. + (ior (match_operand 0 "register_operand")
  20336. + (match_operand 0 "avr32_logical_shift_operand"))
  20337. +)
  20338. +
  20339. +
  20340. +;; True for avr32 comparison operators
  20341. +(define_predicate "avr32_comparison_operator"
  20342. + (ior (match_code "eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu")
  20343. + (and (match_code "unspec")
  20344. + (match_test "(XINT(op, 1) == UNSPEC_COND_MI)
  20345. + || (XINT(op, 1) == UNSPEC_COND_PL)"))))
  20346. +
  20347. +(define_predicate "avr32_cond3_comparison_operator"
  20348. + (ior (match_code "eq, ne, ge, lt, geu, ltu")
  20349. + (and (match_code "unspec")
  20350. + (match_test "(XINT(op, 1) == UNSPEC_COND_MI)
  20351. + || (XINT(op, 1) == UNSPEC_COND_PL)"))))
  20352. +
  20353. +;; True for avr32 comparison operand
  20354. +(define_predicate "avr32_comparison_operand"
  20355. + (ior (and (match_code "eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu")
  20356. + (match_test "(CC0_P (XEXP(op,0)) && rtx_equal_p (XEXP(op,1), const0_rtx))"))
  20357. + (and (match_code "unspec")
  20358. + (match_test "(XINT(op, 1) == UNSPEC_COND_MI)
  20359. + || (XINT(op, 1) == UNSPEC_COND_PL)"))))
  20360. +
  20361. +;; True if this is a const_int with one bit set
  20362. +(define_predicate "one_bit_set_operand"
  20363. + (match_code "const_int")
  20364. + {
  20365. + int i;
  20366. + int value;
  20367. + int ones = 0;
  20368. +
  20369. + value = INTVAL(op);
  20370. + for ( i = 0 ; i < 32; i++ ){
  20371. + if ( value & ( 1 << i ) ){
  20372. + ones++;
  20373. + }
  20374. + }
  20375. +
  20376. + return ( ones == 1 );
  20377. + })
  20378. +
  20379. +
  20380. +;; True if this is a const_int with one bit cleared
  20381. +(define_predicate "one_bit_cleared_operand"
  20382. + (match_code "const_int")
  20383. + {
  20384. + int i;
  20385. + int value;
  20386. + int zeroes = 0;
  20387. +
  20388. + value = INTVAL(op);
  20389. + for ( i = 0 ; i < 32; i++ ){
  20390. + if ( !(value & ( 1 << i )) ){
  20391. + zeroes++;
  20392. + }
  20393. + }
  20394. +
  20395. + return ( zeroes == 1 );
  20396. + })
  20397. +
  20398. +
  20399. +;; Immediate all the low 16-bits cleared
  20400. +(define_predicate "avr32_hi16_immediate_operand"
  20401. + (match_code "const_int")
  20402. + {
  20403. + /* If the low 16-bits are zero then this
  20404. + is a hi16 immediate. */
  20405. + return ((INTVAL(op) & 0xffff) == 0);
  20406. + }
  20407. +)
  20408. +
  20409. +;; True if this is a register or immediate operand
  20410. +(define_predicate "register_immediate_operand"
  20411. + (ior (match_operand 0 "register_operand")
  20412. + (match_operand 0 "immediate_operand")))
  20413. +
  20414. +;; True if this is a register or const_int operand
  20415. +(define_predicate "register_const_int_operand"
  20416. + (ior (match_operand 0 "register_operand")
  20417. + (and (match_operand 0 "const_int_operand")
  20418. + (match_operand 0 "immediate_operand"))))
  20419. +
  20420. +;; True if this is a register or const_double operand
  20421. +(define_predicate "register_const_double_operand"
  20422. + (ior (match_operand 0 "register_operand")
  20423. + (match_operand 0 "const_double_operand")))
  20424. +
  20425. +;; True if this is an operand containing a label_ref.
  20426. +(define_predicate "avr32_label_ref_operand"
  20427. + (and (match_code "mem")
  20428. + (match_test "avr32_find_symbol(op)
  20429. + && (GET_CODE(avr32_find_symbol(op)) == LABEL_REF)")))
  20430. +
  20431. +;; True if this is a valid symbol pointing to the constant pool.
  20432. +(define_predicate "avr32_const_pool_operand"
  20433. + (and (match_code "symbol_ref")
  20434. + (match_test "CONSTANT_POOL_ADDRESS_P(op)"))
  20435. + {
  20436. + return (flag_pic ? (!(symbol_mentioned_p (get_pool_constant (op))
  20437. + || label_mentioned_p (get_pool_constant (op)))
  20438. + || avr32_got_mentioned_p(get_pool_constant (op)))
  20439. + : true);
  20440. + }
  20441. +)
  20442. +
  20443. +;; True if this is a memory reference to the constant or mini pool.
  20444. +(define_predicate "avr32_const_pool_ref_operand"
  20445. + (ior (match_operand 0 "avr32_label_ref_operand")
  20446. + (and (match_code "mem")
  20447. + (match_test "avr32_const_pool_operand(XEXP(op,0), GET_MODE(XEXP(op,0)))"))))
  20448. +
  20449. +
  20450. +;; Legal source operand for movti insns
  20451. +(define_predicate "avr32_movti_src_operand"
  20452. + (ior (match_operand 0 "avr32_const_pool_ref_operand")
  20453. + (ior (ior (match_operand 0 "register_immediate_operand")
  20454. + (match_operand 0 "avr32_indirect_register_operand"))
  20455. + (match_operand 0 "post_inc_memory_operand"))))
  20456. +
  20457. +;; Legal destination operand for movti insns
  20458. +(define_predicate "avr32_movti_dst_operand"
  20459. + (ior (ior (match_operand 0 "register_operand")
  20460. + (match_operand 0 "avr32_indirect_register_operand"))
  20461. + (match_operand 0 "pre_dec_memory_operand")))
  20462. +
  20463. +
  20464. +;; True if this is a k12 offseted memory operand.
  20465. +(define_predicate "avr32_k12_memory_operand"
  20466. + (and (match_code "mem")
  20467. + (ior (match_test "REG_P(XEXP(op, 0))")
  20468. + (match_test "GET_CODE(XEXP(op, 0)) == PLUS
  20469. + && REG_P(XEXP(XEXP(op, 0), 0))
  20470. + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT)
  20471. + && (CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(XEXP(op, 0), 0)),
  20472. + 'K', (mode == SImode) ? \"Ks14\" : ((mode == HImode) ? \"Ks13\" : \"Ks12\")))"))))
  20473. +
  20474. +;; True if this is a memory operand with an immediate displacement.
  20475. +(define_predicate "avr32_imm_disp_memory_operand"
  20476. + (and (match_code "mem")
  20477. + (match_test "GET_CODE(XEXP(op, 0)) == PLUS
  20478. + && REG_P(XEXP(XEXP(op, 0), 0))
  20479. + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT)")))
  20480. +
  20481. +;; True if this is a bswap operand.
  20482. +(define_predicate "avr32_bswap_operand"
  20483. + (ior (match_operand 0 "avr32_k12_memory_operand")
  20484. + (match_operand 0 "register_operand")))
  20485. +
  20486. +;; True if this is a valid coprocessor insn memory operand.
  20487. +(define_predicate "avr32_cop_memory_operand"
  20488. + (and (match_operand 0 "memory_operand")
  20489. + (not (match_test "GET_CODE(XEXP(op, 0)) == PLUS
  20490. + && REG_P(XEXP(XEXP(op, 0), 0))
  20491. + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT)
  20492. + && !(CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(XEXP(op, 0), 0)), 'K', \"Ku10\"))"))))
  20493. +
  20494. +;; True if this is a valid source/destination operand.
  20495. +;; for moving values to/from a coprocessor
  20496. +(define_predicate "avr32_cop_move_operand"
  20497. + (ior (match_operand 0 "register_operand")
  20498. + (match_operand 0 "avr32_cop_memory_operand")))
  20499. +
  20500. +
  20501. +;; True if this is a valid extract byte offset for use in
  20502. +;; load extracted index insns.
  20503. +(define_predicate "avr32_extract_shift_operand"
  20504. + (and (match_operand 0 "const_int_operand")
  20505. + (match_test "(INTVAL(op) == 0) || (INTVAL(op) == 8)
  20506. + || (INTVAL(op) == 16) || (INTVAL(op) == 24)")))
  20507. +
  20508. +;; True if this is a valid avr32 symbol operand.
  20509. +(define_predicate "avr32_symbol_operand"
  20510. + (and (match_code "label_ref, symbol_ref, const")
  20511. + (match_test "avr32_find_symbol(op)")))
  20512. +
  20513. +;; True if this is a valid operand for the lda.w and call pseudo insns.
  20514. +(define_predicate "avr32_address_operand"
  20515. + (and (and (match_code "label_ref, symbol_ref")
  20516. + (match_test "avr32_find_symbol(op)"))
  20517. + (ior (match_test "TARGET_HAS_ASM_ADDR_PSEUDOS")
  20518. + (match_test "flag_pic")) ))
  20519. +
  20520. +;; An immediate k16 address operand
  20521. +(define_predicate "avr32_ks16_address_operand"
  20522. + (and (match_operand 0 "address_operand")
  20523. + (ior (match_test "REG_P(op)")
  20524. + (match_test "GET_CODE(op) == PLUS
  20525. + && ((GET_CODE(XEXP(op,0)) == CONST_INT)
  20526. + || (GET_CODE(XEXP(op,1)) == CONST_INT))")) ))
  20527. +
  20528. +;; An offset k16 memory operand
  20529. +(define_predicate "avr32_ks16_memory_operand"
  20530. + (and (match_code "mem")
  20531. + (match_test "avr32_ks16_address_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
  20532. +
  20533. +;; An immediate k11 address operand
  20534. +(define_predicate "avr32_ks11_address_operand"
  20535. + (and (match_operand 0 "address_operand")
  20536. + (ior (match_test "REG_P(op)")
  20537. + (match_test "GET_CODE(op) == PLUS
  20538. + && (((GET_CODE(XEXP(op,0)) == CONST_INT)
  20539. + && avr32_const_ok_for_constraint_p(INTVAL(XEXP(op,0)), 'K', \"Ks11\"))
  20540. + || ((GET_CODE(XEXP(op,1)) == CONST_INT)
  20541. + && avr32_const_ok_for_constraint_p(INTVAL(XEXP(op,1)), 'K', \"Ks11\")))")) ))
  20542. +
  20543. +;; True if this is a avr32 call operand
  20544. +(define_predicate "avr32_call_operand"
  20545. + (ior (ior (match_operand 0 "register_operand")
  20546. + (ior (match_operand 0 "avr32_const_pool_ref_operand")
  20547. + (match_operand 0 "avr32_address_operand")))
  20548. + (match_test "SYMBOL_REF_RCALL_FUNCTION_P(op)")))
  20549. +
  20550. +;; Return true for operators performing ALU operations
  20551. +
  20552. +(define_predicate "alu_operator"
  20553. + (match_code "ior, xor, and, plus, minus, ashift, lshiftrt, ashiftrt"))
  20554. +
  20555. +(define_predicate "avr32_add_shift_immediate_operand"
  20556. + (and (match_operand 0 "immediate_operand")
  20557. + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ku02\")")))
  20558. +
  20559. +(define_predicate "avr32_cond_register_immediate_operand"
  20560. + (ior (match_operand 0 "register_operand")
  20561. + (and (match_operand 0 "immediate_operand")
  20562. + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")"))))
  20563. +
  20564. +(define_predicate "avr32_cond_immediate_operand"
  20565. + (and (match_operand 0 "immediate_operand")
  20566. + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'I', \"Is08\")")))
  20567. +
  20568. +
  20569. +(define_predicate "avr32_cond_move_operand"
  20570. + (ior (ior (match_operand 0 "register_operand")
  20571. + (and (match_operand 0 "immediate_operand")
  20572. + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")")))
  20573. + (and (match_test "TARGET_V2_INSNS")
  20574. + (match_operand 0 "memory_operand"))))
  20575. +
  20576. +(define_predicate "avr32_mov_immediate_operand"
  20577. + (and (match_operand 0 "immediate_operand")
  20578. + (match_test "avr32_const_ok_for_move(INTVAL(op))")))
  20579. +
  20580. +
  20581. +(define_predicate "avr32_rmw_address_operand"
  20582. + (ior (and (match_code "symbol_ref")
  20583. + (match_test "({rtx symbol = avr32_find_symbol(op); \
  20584. + symbol && (GET_CODE (symbol) == SYMBOL_REF) && SYMBOL_REF_RMW_ADDR(symbol);})"))
  20585. + (and (match_operand 0 "immediate_operand")
  20586. + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks17\")")))
  20587. + {
  20588. + return TARGET_RMW && !flag_pic;
  20589. + }
  20590. +)
  20591. +
  20592. +(define_predicate "avr32_rmw_memory_operand"
  20593. + (and (match_code "mem")
  20594. + (match_test "!volatile_refs_p(op) && (GET_MODE(op) == SImode) &&
  20595. + avr32_rmw_address_operand(XEXP(op, 0), GET_MODE(XEXP(op, 0)))")))
  20596. +
  20597. +(define_predicate "avr32_rmw_memory_or_register_operand"
  20598. + (ior (match_operand 0 "avr32_rmw_memory_operand")
  20599. + (match_operand 0 "register_operand")))
  20600. +
  20601. +(define_predicate "avr32_non_rmw_memory_operand"
  20602. + (and (not (match_operand 0 "avr32_rmw_memory_operand"))
  20603. + (match_operand 0 "memory_operand")))
  20604. +
  20605. +(define_predicate "avr32_non_rmw_general_operand"
  20606. + (and (not (match_operand 0 "avr32_rmw_memory_operand"))
  20607. + (match_operand 0 "general_operand")))
  20608. +
  20609. +(define_predicate "avr32_non_rmw_nonimmediate_operand"
  20610. + (and (not (match_operand 0 "avr32_rmw_memory_operand"))
  20611. + (match_operand 0 "nonimmediate_operand")))
  20612. +
  20613. +;; Return true if the operand is the 1.0f constant.
  20614. +
  20615. +(define_predicate "const_1f_operand"
  20616. + (match_code "const_int,const_double")
  20617. +{
  20618. + return (op == CONST1_RTX (SFmode));
  20619. +})
  20620. --- /dev/null
  20621. +++ b/gcc/config/avr32/simd.md
  20622. @@ -0,0 +1,145 @@
  20623. +;; AVR32 machine description file for SIMD instructions.
  20624. +;; Copyright 2003-2006 Atmel Corporation.
  20625. +;;
  20626. +;; Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
  20627. +;;
  20628. +;; This file is part of GCC.
  20629. +;;
  20630. +;; This program is free software; you can redistribute it and/or modify
  20631. +;; it under the terms of the GNU General Public License as published by
  20632. +;; the Free Software Foundation; either version 2 of the License, or
  20633. +;; (at your option) any later version.
  20634. +;;
  20635. +;; This program is distributed in the hope that it will be useful,
  20636. +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  20637. +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20638. +;; GNU General Public License for more details.
  20639. +;;
  20640. +;; You should have received a copy of the GNU General Public License
  20641. +;; along with this program; if not, write to the Free Software
  20642. +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20643. +
  20644. +;; -*- Mode: Scheme -*-
  20645. +
  20646. +
  20647. +;; Vector modes
  20648. +(define_mode_iterator VECM [V2HI V4QI])
  20649. +(define_mode_attr size [(V2HI "h") (V4QI "b")])
  20650. +
  20651. +(define_insn "add<mode>3"
  20652. + [(set (match_operand:VECM 0 "register_operand" "=r")
  20653. + (plus:VECM (match_operand:VECM 1 "register_operand" "r")
  20654. + (match_operand:VECM 2 "register_operand" "r")))]
  20655. + "TARGET_SIMD"
  20656. + "padd.<size>\t%0, %1, %2"
  20657. + [(set_attr "length" "4")
  20658. + (set_attr "type" "alu")])
  20659. +
  20660. +
  20661. +(define_insn "sub<mode>3"
  20662. + [(set (match_operand:VECM 0 "register_operand" "=r")
  20663. + (minus:VECM (match_operand:VECM 1 "register_operand" "r")
  20664. + (match_operand:VECM 2 "register_operand" "r")))]
  20665. + "TARGET_SIMD"
  20666. + "psub.<size>\t%0, %1, %2"
  20667. + [(set_attr "length" "4")
  20668. + (set_attr "type" "alu")])
  20669. +
  20670. +
  20671. +(define_insn "abs<mode>2"
  20672. + [(set (match_operand:VECM 0 "register_operand" "=r")
  20673. + (abs:VECM (match_operand:VECM 1 "register_operand" "r")))]
  20674. + "TARGET_SIMD"
  20675. + "pabs.s<size>\t%0, %1"
  20676. + [(set_attr "length" "4")
  20677. + (set_attr "type" "alu")])
  20678. +
  20679. +(define_insn "ashl<mode>3"
  20680. + [(set (match_operand:VECM 0 "register_operand" "=r")
  20681. + (ashift:VECM (match_operand:VECM 1 "register_operand" "r")
  20682. + (match_operand:SI 2 "immediate_operand" "Ku04")))]
  20683. + "TARGET_SIMD"
  20684. + "plsl.<size>\t%0, %1, %2"
  20685. + [(set_attr "length" "4")
  20686. + (set_attr "type" "alu")])
  20687. +
  20688. +(define_insn "ashr<mode>3"
  20689. + [(set (match_operand:VECM 0 "register_operand" "=r")
  20690. + (ashiftrt:VECM (match_operand:VECM 1 "register_operand" "r")
  20691. + (match_operand:SI 2 "immediate_operand" "Ku04")))]
  20692. + "TARGET_SIMD"
  20693. + "pasr.<size>\t%0, %1, %2"
  20694. + [(set_attr "length" "4")
  20695. + (set_attr "type" "alu")])
  20696. +
  20697. +(define_insn "lshr<mode>3"
  20698. + [(set (match_operand:VECM 0 "register_operand" "=r")
  20699. + (lshiftrt:VECM (match_operand:VECM 1 "register_operand" "r")
  20700. + (match_operand:SI 2 "immediate_operand" "Ku04")))]
  20701. + "TARGET_SIMD"
  20702. + "plsr.<size>\t%0, %1, %2"
  20703. + [(set_attr "length" "4")
  20704. + (set_attr "type" "alu")])
  20705. +
  20706. +(define_insn "smaxv2hi3"
  20707. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  20708. + (smax:V2HI (match_operand:V2HI 1 "register_operand" "r")
  20709. + (match_operand:V2HI 2 "register_operand" "r")))]
  20710. +
  20711. + "TARGET_SIMD"
  20712. + "pmax.sh\t%0, %1, %2"
  20713. + [(set_attr "length" "4")
  20714. + (set_attr "type" "alu")])
  20715. +
  20716. +(define_insn "sminv2hi3"
  20717. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  20718. + (smin:V2HI (match_operand:V2HI 1 "register_operand" "r")
  20719. + (match_operand:V2HI 2 "register_operand" "r")))]
  20720. +
  20721. + "TARGET_SIMD"
  20722. + "pmin.sh\t%0, %1, %2"
  20723. + [(set_attr "length" "4")
  20724. + (set_attr "type" "alu")])
  20725. +
  20726. +(define_insn "umaxv4qi3"
  20727. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  20728. + (umax:V4QI (match_operand:V4QI 1 "register_operand" "r")
  20729. + (match_operand:V4QI 2 "register_operand" "r")))]
  20730. +
  20731. + "TARGET_SIMD"
  20732. + "pmax.ub\t%0, %1, %2"
  20733. + [(set_attr "length" "4")
  20734. + (set_attr "type" "alu")])
  20735. +
  20736. +(define_insn "uminv4qi3"
  20737. + [(set (match_operand:V4QI 0 "register_operand" "=r")
  20738. + (umin:V4QI (match_operand:V4QI 1 "register_operand" "r")
  20739. + (match_operand:V4QI 2 "register_operand" "r")))]
  20740. +
  20741. + "TARGET_SIMD"
  20742. + "pmin.ub\t%0, %1, %2"
  20743. + [(set_attr "length" "4")
  20744. + (set_attr "type" "alu")])
  20745. +
  20746. +
  20747. +(define_insn "addsubv2hi"
  20748. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  20749. + (vec_concat:V2HI
  20750. + (plus:HI (match_operand:HI 1 "register_operand" "r")
  20751. + (match_operand:HI 2 "register_operand" "r"))
  20752. + (minus:HI (match_dup 1) (match_dup 2))))]
  20753. + "TARGET_SIMD"
  20754. + "paddsub.h\t%0, %1:b, %2:b"
  20755. + [(set_attr "length" "4")
  20756. + (set_attr "type" "alu")])
  20757. +
  20758. +(define_insn "subaddv2hi"
  20759. + [(set (match_operand:V2HI 0 "register_operand" "=r")
  20760. + (vec_concat:V2HI
  20761. + (minus:HI (match_operand:HI 1 "register_operand" "r")
  20762. + (match_operand:HI 2 "register_operand" "r"))
  20763. + (plus:HI (match_dup 1) (match_dup 2))))]
  20764. + "TARGET_SIMD"
  20765. + "psubadd.h\t%0, %1:b, %2:b"
  20766. + [(set_attr "length" "4")
  20767. + (set_attr "type" "alu")])
  20768. --- /dev/null
  20769. +++ b/gcc/config/avr32/sync.md
  20770. @@ -0,0 +1,244 @@
  20771. +;;=================================================================
  20772. +;; Atomic operations
  20773. +;;=================================================================
  20774. +
  20775. +
  20776. +(define_insn "sync_compare_and_swapsi"
  20777. + [(set (match_operand:SI 0 "register_operand" "=&r,&r")
  20778. + (match_operand:SI 1 "memory_operand" "+RKs16,+RKs16"))
  20779. + (set (match_dup 1)
  20780. + (unspec_volatile:SI
  20781. + [(match_dup 1)
  20782. + (match_operand:SI 2 "register_immediate_operand" "r,Ks21")
  20783. + (match_operand:SI 3 "register_operand" "r,r")]
  20784. + VUNSPEC_SYNC_CMPXCHG)) ]
  20785. + ""
  20786. + "0:
  20787. + ssrf\t5
  20788. + ld.w\t%0,%1
  20789. + cp.w\t%0,%2
  20790. + brne\t0f
  20791. + stcond\t%1, %3
  20792. + brne\t0b
  20793. + 0:
  20794. + "
  20795. + [(set_attr "length" "16,18")
  20796. + (set_attr "cc" "clobber")]
  20797. + )
  20798. +
  20799. +
  20800. +(define_code_iterator atomic_op [plus minus and ior xor])
  20801. +(define_code_attr atomic_asm_insn [(plus "add") (minus "sub") (and "and") (ior "or") (xor "eor")])
  20802. +(define_code_attr atomic_insn [(plus "add") (minus "sub") (and "and") (ior "ior") (xor "xor")])
  20803. +
  20804. +(define_insn "sync_loadsi"
  20805. + ; NB! Put an early clobber on the destination operand to
  20806. + ; avoid gcc using the same register in the source and
  20807. + ; destination. This is done in order to avoid gcc to
  20808. + ; clobber the source operand since these instructions
  20809. + ; are actually inside a "loop".
  20810. + [(set (match_operand:SI 0 "register_operand" "=&r")
  20811. + (unspec_volatile:SI
  20812. + [(match_operand:SI 1 "avr32_ks16_memory_operand" "RKs16")
  20813. + (label_ref (match_operand 2 "" ""))]
  20814. + VUNSPEC_SYNC_SET_LOCK_AND_LOAD) )]
  20815. + ""
  20816. + "%2:
  20817. + ssrf\t5
  20818. + ld.w\t%0,%1"
  20819. + [(set_attr "length" "6")
  20820. + (set_attr "cc" "clobber")]
  20821. + )
  20822. +
  20823. +(define_insn "sync_store_if_lock"
  20824. + [(set (match_operand:SI 0 "avr32_ks16_memory_operand" "=RKs16")
  20825. + (unspec_volatile:SI
  20826. + [(match_operand:SI 1 "register_operand" "r")
  20827. + (label_ref (match_operand 2 "" ""))]
  20828. + VUNSPEC_SYNC_STORE_IF_LOCK) )]
  20829. + ""
  20830. + "stcond\t%0, %1
  20831. + brne\t%2"
  20832. + [(set_attr "length" "6")
  20833. + (set_attr "cc" "clobber")]
  20834. + )
  20835. +
  20836. +
  20837. +(define_expand "sync_<atomic_insn>si"
  20838. + [(set (match_dup 2)
  20839. + (unspec_volatile:SI
  20840. + [(match_operand:SI 0 "avr32_ks16_memory_operand" "")
  20841. + (match_dup 3)]
  20842. + VUNSPEC_SYNC_SET_LOCK_AND_LOAD))
  20843. + (set (match_dup 2)
  20844. + (atomic_op:SI (match_dup 2)
  20845. + (match_operand:SI 1 "register_immediate_operand" "")))
  20846. + (set (match_dup 0)
  20847. + (unspec_volatile:SI
  20848. + [(match_dup 2)
  20849. + (match_dup 3)]
  20850. + VUNSPEC_SYNC_STORE_IF_LOCK) )
  20851. + (use (match_dup 1))
  20852. + (use (match_dup 4))]
  20853. + ""
  20854. + {
  20855. + rtx *mem_expr = &operands[0];
  20856. + rtx ptr_reg;
  20857. + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) )
  20858. + {
  20859. + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0));
  20860. + XEXP (*mem_expr, 0) = ptr_reg;
  20861. + }
  20862. + else
  20863. + {
  20864. + rtx address = XEXP (*mem_expr, 0);
  20865. + if ( REG_P (address) )
  20866. + ptr_reg = address;
  20867. + else if ( REG_P (XEXP (address, 0)) )
  20868. + ptr_reg = XEXP (address, 0);
  20869. + else
  20870. + ptr_reg = XEXP (address, 1);
  20871. + }
  20872. +
  20873. + operands[2] = gen_reg_rtx (SImode);
  20874. + operands[3] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ());
  20875. + operands[4] = ptr_reg;
  20876. +
  20877. + }
  20878. + )
  20879. +
  20880. +
  20881. +
  20882. +(define_expand "sync_old_<atomic_insn>si"
  20883. + [(set (match_operand:SI 0 "register_operand" "")
  20884. + (unspec_volatile:SI
  20885. + [(match_operand:SI 1 "avr32_ks16_memory_operand" "")
  20886. + (match_dup 4)]
  20887. + VUNSPEC_SYNC_SET_LOCK_AND_LOAD))
  20888. + (set (match_dup 3)
  20889. + (atomic_op:SI (match_dup 0)
  20890. + (match_operand:SI 2 "register_immediate_operand" "")))
  20891. + (set (match_dup 1)
  20892. + (unspec_volatile:SI
  20893. + [(match_dup 3)
  20894. + (match_dup 4)]
  20895. + VUNSPEC_SYNC_STORE_IF_LOCK) )
  20896. + (use (match_dup 2))
  20897. + (use (match_dup 5))]
  20898. + ""
  20899. + {
  20900. + rtx *mem_expr = &operands[1];
  20901. + rtx ptr_reg;
  20902. + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) )
  20903. + {
  20904. + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0));
  20905. + XEXP (*mem_expr, 0) = ptr_reg;
  20906. + }
  20907. + else
  20908. + {
  20909. + rtx address = XEXP (*mem_expr, 0);
  20910. + if ( REG_P (address) )
  20911. + ptr_reg = address;
  20912. + else if ( REG_P (XEXP (address, 0)) )
  20913. + ptr_reg = XEXP (address, 0);
  20914. + else
  20915. + ptr_reg = XEXP (address, 1);
  20916. + }
  20917. +
  20918. + operands[3] = gen_reg_rtx (SImode);
  20919. + operands[4] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ());
  20920. + operands[5] = ptr_reg;
  20921. + }
  20922. + )
  20923. +
  20924. +(define_expand "sync_new_<atomic_insn>si"
  20925. + [(set (match_operand:SI 0 "register_operand" "")
  20926. + (unspec_volatile:SI
  20927. + [(match_operand:SI 1 "avr32_ks16_memory_operand" "")
  20928. + (match_dup 3)]
  20929. + VUNSPEC_SYNC_SET_LOCK_AND_LOAD))
  20930. + (set (match_dup 0)
  20931. + (atomic_op:SI (match_dup 0)
  20932. + (match_operand:SI 2 "register_immediate_operand" "")))
  20933. + (set (match_dup 1)
  20934. + (unspec_volatile:SI
  20935. + [(match_dup 0)
  20936. + (match_dup 3)]
  20937. + VUNSPEC_SYNC_STORE_IF_LOCK) )
  20938. + (use (match_dup 2))
  20939. + (use (match_dup 4))]
  20940. + ""
  20941. + {
  20942. + rtx *mem_expr = &operands[1];
  20943. + rtx ptr_reg;
  20944. + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) )
  20945. + {
  20946. + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0));
  20947. + XEXP (*mem_expr, 0) = ptr_reg;
  20948. + }
  20949. + else
  20950. + {
  20951. + rtx address = XEXP (*mem_expr, 0);
  20952. + if ( REG_P (address) )
  20953. + ptr_reg = address;
  20954. + else if ( REG_P (XEXP (address, 0)) )
  20955. + ptr_reg = XEXP (address, 0);
  20956. + else
  20957. + ptr_reg = XEXP (address, 1);
  20958. + }
  20959. +
  20960. + operands[3] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ());
  20961. + operands[4] = ptr_reg;
  20962. + }
  20963. + )
  20964. +
  20965. +
  20966. +;(define_insn "sync_<atomic_insn>si"
  20967. +; [(set (match_operand:SI 0 "memory_operand" "+RKs16")
  20968. +; (unspec_volatile:SI
  20969. +; [(atomic_op:SI (match_dup 0)
  20970. +; (match_operand:SI 1 "register_operand" "r"))]
  20971. +; VUNSPEC_SYNC_CMPXCHG))
  20972. +; (clobber (match_scratch:SI 2 "=&r"))]
  20973. +; ""
  20974. +; "0:
  20975. +; ssrf\t5
  20976. +; ld.w\t%2,%0
  20977. +; <atomic_asm_insn>\t%2,%1
  20978. +; stcond\t%0, %2
  20979. +; brne\t0b
  20980. +; "
  20981. +; [(set_attr "length" "14")
  20982. +; (set_attr "cc" "clobber")]
  20983. +; )
  20984. +;
  20985. +;(define_insn "sync_new_<atomic_insn>si"
  20986. +; [(set (match_operand:SI 1 "memory_operand" "+RKs16")
  20987. +; (unspec_volatile:SI
  20988. +; [(atomic_op:SI (match_dup 1)
  20989. +; (match_operand:SI 2 "register_operand" "r"))]
  20990. +; VUNSPEC_SYNC_CMPXCHG))
  20991. +; (set (match_operand:SI 0 "register_operand" "=&r")
  20992. +; (atomic_op:SI (match_dup 1)
  20993. +; (match_dup 2)))]
  20994. +; ""
  20995. +; "0:
  20996. +; ssrf\t5
  20997. +; ld.w\t%0,%1
  20998. +; <atomic_asm_insn>\t%0,%2
  20999. +; stcond\t%1, %0
  21000. +; brne\t0b
  21001. +; "
  21002. +; [(set_attr "length" "14")
  21003. +; (set_attr "cc" "clobber")]
  21004. +; )
  21005. +
  21006. +(define_insn "sync_lock_test_and_setsi"
  21007. + [ (set (match_operand:SI 0 "register_operand" "=&r")
  21008. + (match_operand:SI 1 "memory_operand" "+RKu00"))
  21009. + (set (match_dup 1)
  21010. + (match_operand:SI 2 "register_operand" "r")) ]
  21011. + ""
  21012. + "xchg\t%0, %p1, %2"
  21013. + [(set_attr "length" "4")]
  21014. + )
  21015. --- /dev/null
  21016. +++ b/gcc/config/avr32/t-avr32
  21017. @@ -0,0 +1,118 @@
  21018. +
  21019. +MD_INCLUDES= $(srcdir)/config/avr32/avr32.md \
  21020. + $(srcdir)/config/avr32/sync.md \
  21021. + $(srcdir)/config/avr32/simd.md \
  21022. + $(srcdir)/config/avr32/predicates.md
  21023. +
  21024. +s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
  21025. + s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
  21026. +
  21027. +# We want fine grained libraries, so use the new code
  21028. +# to build the floating point emulation libraries.
  21029. +FPBIT = fp-bit.c
  21030. +DPBIT = dp-bit.c
  21031. +
  21032. +LIB1ASMSRC = avr32/lib1funcs.S
  21033. +LIB1ASMFUNCS = _avr32_f64_mul _avr32_f64_mul_fast _avr32_f64_addsub _avr32_f64_addsub_fast _avr32_f64_to_u32 \
  21034. + _avr32_f64_to_s32 _avr32_f64_to_u64 _avr32_f64_to_s64 _avr32_u32_to_f64 \
  21035. + _avr32_s32_to_f64 _avr32_f64_cmp_eq _avr32_f64_cmp_ge _avr32_f64_cmp_lt \
  21036. + _avr32_f32_cmp_eq _avr32_f32_cmp_ge _avr32_f32_cmp_lt _avr32_f64_div _avr32_f64_div_fast \
  21037. + _avr32_f32_div _avr32_f32_div_fast _avr32_f32_addsub _avr32_f32_addsub_fast \
  21038. + _avr32_f32_mul _avr32_s32_to_f32 _avr32_u32_to_f32 _avr32_f32_to_s32 \
  21039. + _avr32_f32_to_u32 _avr32_f32_to_f64 _avr32_f64_to_f32 _mulsi3
  21040. +
  21041. +#LIB2FUNCS_EXTRA += $(srcdir)/config/avr32/lib2funcs.S
  21042. +
  21043. +MULTILIB_OPTIONS = march=ap/march=ucr1/march=ucr2/march=ucr2nomul/march=ucr3/march=ucr3fp
  21044. +MULTILIB_DIRNAMES = ap ucr1 ucr2 ucr2nomul ucr3 ucr3fp
  21045. +MULTILIB_EXCEPTIONS =
  21046. +MULTILIB_MATCHES += march?ap=mpart?ap7000
  21047. +MULTILIB_MATCHES += march?ap=mpart?ap7001
  21048. +MULTILIB_MATCHES += march?ap=mpart?ap7002
  21049. +MULTILIB_MATCHES += march?ap=mpart?ap7200
  21050. +MULTILIB_MATCHES += march?ucr1=march?uc
  21051. +MULTILIB_MATCHES += march?ucr1=mpart?uc3a0512es
  21052. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0128
  21053. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0256
  21054. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0512
  21055. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1128
  21056. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1256
  21057. +MULTILIB_MATCHES += march?ucr1=mpart?uc3a1512es
  21058. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1512
  21059. +MULTILIB_MATCHES += march?ucr2nomul=mpart?uc3a3revd
  21060. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364
  21061. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364s
  21062. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128
  21063. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128s
  21064. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256
  21065. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256s
  21066. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a464
  21067. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a464s
  21068. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4128
  21069. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4128s
  21070. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4256
  21071. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4256s
  21072. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b064
  21073. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0128
  21074. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256es
  21075. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256
  21076. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b0512
  21077. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b0512revc
  21078. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b164
  21079. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1128
  21080. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256es
  21081. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256
  21082. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b1512
  21083. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b1512revc
  21084. +MULTILIB_MATCHES += march?ucr3=mpart?uc64d3
  21085. +MULTILIB_MATCHES += march?ucr3=mpart?uc128d3
  21086. +MULTILIB_MATCHES += march?ucr3=mpart?uc64d4
  21087. +MULTILIB_MATCHES += march?ucr3=mpart?uc128d4
  21088. +MULTILIB_MATCHES += march?ucr3=mpart?uc3c0512crevc
  21089. +MULTILIB_MATCHES += march?ucr3=mpart?uc3c1512crevc
  21090. +MULTILIB_MATCHES += march?ucr3=mpart?uc3c2512crevc
  21091. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l0256
  21092. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l0128
  21093. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l064
  21094. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l032
  21095. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l016
  21096. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l064revb
  21097. +MULTILIB_MATCHES += march?ucr3=mpart?uc64l3u
  21098. +MULTILIB_MATCHES += march?ucr3=mpart?uc128l3u
  21099. +MULTILIB_MATCHES += march?ucr3=mpart?uc256l3u
  21100. +MULTILIB_MATCHES += march?ucr3=mpart?uc64l4u
  21101. +MULTILIB_MATCHES += march?ucr3=mpart?uc128l4u
  21102. +MULTILIB_MATCHES += march?ucr3=mpart?uc256l4u
  21103. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c064c
  21104. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c0128c
  21105. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c0256c
  21106. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c0512c
  21107. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c164c
  21108. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c1128c
  21109. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c1256c
  21110. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c1512c
  21111. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c264c
  21112. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c2128c
  21113. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c2256c
  21114. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c2512c
  21115. +MULTILIB_MATCHES += march?ucr3=mpart?mxt768e
  21116. +
  21117. +
  21118. +EXTRA_MULTILIB_PARTS = crtbegin.o crtbeginS.o crtend.o crtendS.o crti.o crtn.o
  21119. +
  21120. +CRTSTUFF_T_CFLAGS = -mrelax
  21121. +CRTSTUFF_T_CFLAGS_S = -mrelax -fPIC
  21122. +TARGET_LIBGCC2_CFLAGS += -mrelax
  21123. +
  21124. +LIBGCC = stmp-multilib
  21125. +INSTALL_LIBGCC = install-multilib
  21126. +
  21127. +fp-bit.c: $(srcdir)/config/fp-bit.c
  21128. + echo '#define FLOAT' > fp-bit.c
  21129. + cat $(srcdir)/config/fp-bit.c >> fp-bit.c
  21130. +
  21131. +dp-bit.c: $(srcdir)/config/fp-bit.c
  21132. + cat $(srcdir)/config/fp-bit.c > dp-bit.c
  21133. +
  21134. +
  21135. +
  21136. --- /dev/null
  21137. +++ b/gcc/config/avr32/t-avr32-linux
  21138. @@ -0,0 +1,118 @@
  21139. +
  21140. +MD_INCLUDES= $(srcdir)/config/avr32/avr32.md \
  21141. + $(srcdir)/config/avr32/sync.md \
  21142. + $(srcdir)/config/avr32/simd.md \
  21143. + $(srcdir)/config/avr32/predicates.md
  21144. +
  21145. +s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
  21146. + s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
  21147. +
  21148. +# We want fine grained libraries, so use the new code
  21149. +# to build the floating point emulation libraries.
  21150. +FPBIT = fp-bit.c
  21151. +DPBIT = dp-bit.c
  21152. +
  21153. +LIB1ASMSRC = avr32/lib1funcs.S
  21154. +LIB1ASMFUNCS = _avr32_f64_mul _avr32_f64_mul_fast _avr32_f64_addsub _avr32_f64_addsub_fast _avr32_f64_to_u32 \
  21155. + _avr32_f64_to_s32 _avr32_f64_to_u64 _avr32_f64_to_s64 _avr32_u32_to_f64 \
  21156. + _avr32_s32_to_f64 _avr32_f64_cmp_eq _avr32_f64_cmp_ge _avr32_f64_cmp_lt \
  21157. + _avr32_f32_cmp_eq _avr32_f32_cmp_ge _avr32_f32_cmp_lt _avr32_f64_div _avr32_f64_div_fast \
  21158. + _avr32_f32_div _avr32_f32_div_fast _avr32_f32_addsub _avr32_f32_addsub_fast \
  21159. + _avr32_f32_mul _avr32_s32_to_f32 _avr32_u32_to_f32 _avr32_f32_to_s32 \
  21160. + _avr32_f32_to_u32 _avr32_f32_to_f64 _avr32_f64_to_f32 _mulsi3
  21161. +
  21162. +#LIB2FUNCS_EXTRA += $(srcdir)/config/avr32/lib2funcs.S
  21163. +
  21164. +MULTILIB_OPTIONS = march=ap/march=ucr1/march=ucr2/march=ucr2nomul/march=ucr3/march=ucr3fp
  21165. +MULTILIB_DIRNAMES = ap ucr1 ucr2 ucr2nomul ucr3 ucr3fp
  21166. +MULTILIB_EXCEPTIONS =
  21167. +MULTILIB_MATCHES += march?ap=mpart?ap7000
  21168. +MULTILIB_MATCHES += march?ap=mpart?ap7001
  21169. +MULTILIB_MATCHES += march?ap=mpart?ap7002
  21170. +MULTILIB_MATCHES += march?ap=mpart?ap7200
  21171. +MULTILIB_MATCHES += march?ucr1=march?uc
  21172. +MULTILIB_MATCHES += march?ucr1=mpart?uc3a0512es
  21173. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0128
  21174. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0256
  21175. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0512
  21176. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1128
  21177. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1256
  21178. +MULTILIB_MATCHES += march?ucr1=mpart?uc3a1512es
  21179. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1512
  21180. +MULTILIB_MATCHES += march?ucr2nomul=mpart?uc3a3revd
  21181. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364
  21182. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364s
  21183. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128
  21184. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128s
  21185. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256
  21186. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256s
  21187. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a464
  21188. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a464s
  21189. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4128
  21190. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4128s
  21191. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4256
  21192. +MULTILIB_MATCHES += march?ucr2=mpart?uc3a4256s
  21193. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b064
  21194. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0128
  21195. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256es
  21196. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256
  21197. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b0512
  21198. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b0512revc
  21199. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b164
  21200. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1128
  21201. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256es
  21202. +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256
  21203. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b1512
  21204. +MULTILIB_MATCHES += march?ucr2=mpart?uc3b1512revc
  21205. +MULTILIB_MATCHES += march?ucr3=mpart?uc64d3
  21206. +MULTILIB_MATCHES += march?ucr3=mpart?uc128d3
  21207. +MULTILIB_MATCHES += march?ucr3=mpart?uc64d4
  21208. +MULTILIB_MATCHES += march?ucr3=mpart?uc128d4
  21209. +MULTILIB_MATCHES += march?ucr3=mpart?uc3c0512crevc
  21210. +MULTILIB_MATCHES += march?ucr3=mpart?uc3c1512crevc
  21211. +MULTILIB_MATCHES += march?ucr3=mpart?uc3c2512crevc
  21212. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l0256
  21213. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l0128
  21214. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l064
  21215. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l032
  21216. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l016
  21217. +MULTILIB_MATCHES += march?ucr3=mpart?uc3l064revb
  21218. +MULTILIB_MATCHES += march?ucr3=mpart?uc64l3u
  21219. +MULTILIB_MATCHES += march?ucr3=mpart?uc128l3u
  21220. +MULTILIB_MATCHES += march?ucr3=mpart?uc256l3u
  21221. +MULTILIB_MATCHES += march?ucr3=mpart?uc64l4u
  21222. +MULTILIB_MATCHES += march?ucr3=mpart?uc128l4u
  21223. +MULTILIB_MATCHES += march?ucr3=mpart?uc256l4u
  21224. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c064c
  21225. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c0128c
  21226. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c0256c
  21227. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c0512c
  21228. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c164c
  21229. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c1128c
  21230. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c1256c
  21231. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c1512c
  21232. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c264c
  21233. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c2128c
  21234. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c2256c
  21235. +MULTILIB_MATCHES += march?ucr3fp=mpart?uc3c2512c
  21236. +MULTILIB_MATCHES += march?ucr3=mpart?mxt768e
  21237. +
  21238. +
  21239. +EXTRA_MULTILIB_PARTS = crtbegin.o crtbeginS.o crtend.o crtendS.o
  21240. +
  21241. +CRTSTUFF_T_CFLAGS = -mrelax
  21242. +CRTSTUFF_T_CFLAGS_S = -mrelax -fPIC
  21243. +TARGET_LIBGCC2_CFLAGS += -mrelax
  21244. +
  21245. +LIBGCC = stmp-multilib
  21246. +INSTALL_LIBGCC = install-multilib
  21247. +
  21248. +fp-bit.c: $(srcdir)/config/fp-bit.c
  21249. + echo '#define FLOAT' > fp-bit.c
  21250. + cat $(srcdir)/config/fp-bit.c >> fp-bit.c
  21251. +
  21252. +dp-bit.c: $(srcdir)/config/fp-bit.c
  21253. + cat $(srcdir)/config/fp-bit.c > dp-bit.c
  21254. +
  21255. +
  21256. +
  21257. --- /dev/null
  21258. +++ b/gcc/config/avr32/t-elf
  21259. @@ -0,0 +1,16 @@
  21260. +
  21261. +# Assemble startup files.
  21262. +$(T)crti.o: $(srcdir)/config/avr32/crti.asm $(GCC_PASSES)
  21263. + $(GCC_FOR_TARGET) $(CRTSTUFF_CFLAGS) $(CRTSTUFF_T_CFLAGS) $(INCLUDES) \
  21264. + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/avr32/crti.asm
  21265. +
  21266. +$(T)crtn.o: $(srcdir)/config/avr32/crtn.asm $(GCC_PASSES)
  21267. + $(GCC_FOR_TARGET) $(CRTSTUFF_CFLAGS) $(CRTSTUFF_T_CFLAGS) $(INCLUDES) \
  21268. + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/avr32/crtn.asm
  21269. +
  21270. +
  21271. +# Build the libraries for both hard and soft floating point
  21272. +EXTRA_MULTILIB_PARTS = crtbegin.o crtbeginS.o crtend.o crtendS.o crti.o crtn.o
  21273. +
  21274. +LIBGCC = stmp-multilib
  21275. +INSTALL_LIBGCC = install-multilib
  21276. --- /dev/null
  21277. +++ b/gcc/config/avr32/uc3fpu.md
  21278. @@ -0,0 +1,199 @@
  21279. +;; AVR32 machine description file for Floating-Point instructions.
  21280. +;; Copyright 2003-2006 Atmel Corporation.
  21281. +;;
  21282. +;;
  21283. +;; This file is part of GCC.
  21284. +;;
  21285. +;; This program is free software; you can redistribute it and/or modify
  21286. +;; it under the terms of the GNU General Public License as published by
  21287. +;; the Free Software Foundation; either version 2 of the License, or
  21288. +;; (at your option) any later version.
  21289. +;;
  21290. +;; This program is distributed in the hope that it will be useful,
  21291. +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  21292. +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21293. +;; GNU General Public License for more details.
  21294. +;;
  21295. +;; You should have received a copy of the GNU General Public License
  21296. +;; along with this program; if not, write to the Free Software
  21297. +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21298. +
  21299. +(define_insn "*movsf_uc3fp"
  21300. + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,m")
  21301. + (match_operand:SF 1 "general_operand" "r,G,m,r"))]
  21302. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21303. + "@
  21304. + mov\t%0, %1
  21305. + mov\t%0, %1
  21306. + ld.w\t%0, %1
  21307. + st.w\t%0, %1"
  21308. + [(set_attr "length" "2,4,4,4")
  21309. + (set_attr "type" "alu,alu,load,store")])
  21310. +
  21311. +(define_insn "mulsf3"
  21312. + [(set (match_operand:SF 0 "register_operand" "=r")
  21313. + (mult:SF (match_operand:SF 1 "register_operand" "r")
  21314. + (match_operand:SF 2 "register_operand" "r")))]
  21315. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21316. + "fmul.s\t%0, %1, %2"
  21317. + [(set_attr "length" "4")
  21318. + (set_attr "type" "fmul")])
  21319. +
  21320. +(define_insn "nmulsf3"
  21321. + [(set (match_operand:SF 0 "register_operand" "=r")
  21322. + (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "%r")
  21323. + (match_operand:SF 2 "register_operand" "r"))))]
  21324. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21325. + "fnmul.s\t%0, %1, %2"
  21326. + [(set_attr "length" "4")
  21327. + (set_attr "type" "fmul")])
  21328. +
  21329. +(define_insn "macsf3"
  21330. + [(set (match_operand:SF 0 "register_operand" "=r")
  21331. + (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
  21332. + (match_operand:SF 2 "register_operand" "r"))
  21333. + (match_operand:SF 3 "register_operand" "r")))]
  21334. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21335. + "fmac.s\t%0, %3, %1, %2"
  21336. + [(set_attr "length" "4")
  21337. + (set_attr "type" "fmul")])
  21338. +
  21339. +;(define_insn "nmacsf3"
  21340. +; [(set (match_operand:SF 0 "register_operand" "=r")
  21341. +; (plus:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
  21342. +; (mult:SF(match_operand:SF 2 "register_operand" "r")
  21343. +; (match_operand:SF 3 "register_operand" "r"))))]
  21344. +; "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21345. +; "fnmac.s\t%0, %1, %2, %3"
  21346. +; [(set_attr "length" "4")
  21347. +; (set_attr "type" "fmul")])
  21348. +
  21349. +(define_insn "nmacsf3"
  21350. + [(set (match_operand:SF 0 "register_operand" "=r")
  21351. + (minus:SF (mult:SF (match_operand:SF 2 "register_operand" "r")
  21352. + (match_operand:SF 3 "register_operand" "r"))
  21353. + (match_operand:SF 1 "register_operand" "r")))]
  21354. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21355. + "fnmac.s\t%0, %1, %2, %3"
  21356. + [(set_attr "length" "4")
  21357. + (set_attr "type" "fmul")])
  21358. +
  21359. +(define_insn "msubacsf3"
  21360. + [(set (match_operand:SF 0 "register_operand" "=r")
  21361. + (minus:SF (match_operand:SF 3 "register_operand" "r")
  21362. + (mult:SF (match_operand:SF 1 "register_operand" "r")
  21363. + (match_operand:SF 2 "register_operand" "r"))))]
  21364. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21365. + "fmsc.s\t%0, %3, %1, %2"
  21366. + [(set_attr "length" "4")
  21367. + (set_attr "type" "fmul")])
  21368. +
  21369. +(define_insn "nmsubacsf3"
  21370. + [(set (match_operand:SF 0 "register_operand" "=r")
  21371. + (minus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
  21372. + (match_operand:SF 2 "register_operand" "r")))
  21373. + (match_operand:SF 3 "register_operand" "r")))]
  21374. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21375. + "fnmsc.s\t%0, %3, %1, %2"
  21376. + [(set_attr "length" "4")
  21377. + (set_attr "type" "fmul")])
  21378. +
  21379. +(define_insn "addsf3"
  21380. + [(set (match_operand:SF 0 "register_operand" "=r")
  21381. + (plus:SF (match_operand:SF 1 "register_operand" "%r")
  21382. + (match_operand:SF 2 "register_operand" "r")))]
  21383. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21384. + "fadd.s\t%0, %1, %2"
  21385. + [(set_attr "length" "4")
  21386. + (set_attr "type" "fmul")])
  21387. +
  21388. +(define_insn "subsf3"
  21389. + [(set (match_operand:SF 0 "register_operand" "=r")
  21390. + (minus:SF (match_operand:SF 1 "register_operand" "r")
  21391. + (match_operand:SF 2 "register_operand" "r")))]
  21392. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21393. + "fsub.s\t%0, %1, %2"
  21394. + [(set_attr "length" "4")
  21395. + (set_attr "type" "fmul")])
  21396. +
  21397. +(define_insn "fixuns_truncsfsi2"
  21398. + [(set (match_operand:SI 0 "register_operand" "=r")
  21399. + (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
  21400. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21401. + "fcastrs.uw\t%0, %1"
  21402. + [(set_attr "length" "4")])
  21403. +
  21404. +(define_insn "fix_truncsfsi2"
  21405. + [(set (match_operand:SI 0 "register_operand" "=r")
  21406. + (fix:SI (match_operand:SF 1 "register_operand" "r")))]
  21407. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21408. + "fcastrs.sw\t%0, %1"
  21409. + [(set_attr "length" "4")])
  21410. +
  21411. +(define_insn "floatunssisf2"
  21412. + [(set (match_operand:SF 0 "register_operand" "=r")
  21413. + (unsigned_float:SF (match_operand:SI 1 "register_operand" "r")))]
  21414. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21415. + "fcastuw.s\t%0, %1"
  21416. + [(set_attr "length" "4")])
  21417. +
  21418. +(define_insn "floatsisf2"
  21419. + [(set (match_operand:SF 0 "register_operand" "=r")
  21420. + (float:SF (match_operand:SI 1 "register_operand" "r")))]
  21421. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21422. + "fcastsw.s\t%0, %1"
  21423. + [(set_attr "length" "4")])
  21424. +
  21425. +(define_insn "cmpsf_internal_uc3fp"
  21426. + [(set (cc0)
  21427. + (compare:CC
  21428. + (match_operand:SF 0 "register_operand" "r")
  21429. + (match_operand:SF 1 "register_operand" "r")))]
  21430. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21431. + {
  21432. + avr32_branch_type = CMP_SF;
  21433. + if (!rtx_equal_p(cc_prev_status.mdep.value, SET_SRC(PATTERN (insn))) )
  21434. + return "fcmp.s\t%0, %1";
  21435. + return "";
  21436. + }
  21437. + [(set_attr "length" "4")
  21438. + (set_attr "cc" "compare")])
  21439. +
  21440. +(define_expand "divsf3"
  21441. + [(set (match_operand:SF 0 "register_operand" "=r")
  21442. + (div:SF (match_operand:SF 1 "register_operand" "r")
  21443. + (match_operand:SF 2 "register_operand" "r")))]
  21444. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
  21445. + "{
  21446. + emit_insn(gen_frcpa_internal(operands[0],operands[2]));
  21447. + emit_insn(gen_mulsf3(operands[0],operands[0],operands[1]));
  21448. + DONE;
  21449. + }"
  21450. +)
  21451. +
  21452. +(define_insn "frcpa_internal"
  21453. + [(set (match_operand:SF 0 "register_operand" "=r")
  21454. + (unspec:SF [(match_operand:SF 1 "register_operand" "r")] UNSPEC_FRCPA))]
  21455. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21456. + "frcpa.s %0,%1"
  21457. + [(set_attr "length" "4")])
  21458. +
  21459. +(define_expand "sqrtsf2"
  21460. + [(set (match_operand:SF 0 "register_operand" "")
  21461. + (sqrt:SF (match_operand:SF 1 "register_operand" "")))]
  21462. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
  21463. + "
  21464. +{
  21465. + rtx scratch = gen_reg_rtx (SFmode);
  21466. + emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
  21467. + emit_insn (gen_divsf3(operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
  21468. + scratch));
  21469. + DONE;
  21470. +}")
  21471. +
  21472. +(define_insn "rsqrtsf2"
  21473. + [(set (match_operand:SF 0 "register_operand" "=r")
  21474. + (div:SF (match_operand:SF 2 "const_1f_operand" "F")
  21475. + (sqrt:SF (match_operand:SF 1 "register_operand" "?r"))))]
  21476. + "TARGET_ARCH_FPU && TARGET_HARD_FLOAT"
  21477. + "frsqrta.s %1, %0")
  21478. --- /dev/null
  21479. +++ b/gcc/config/avr32/uclinux-elf.h
  21480. @@ -0,0 +1,20 @@
  21481. +
  21482. +/* Run-time Target Specification. */
  21483. +#undef TARGET_VERSION
  21484. +#define TARGET_VERSION fputs (" (AVR32 uClinux with ELF)", stderr)
  21485. +
  21486. +/* We don't want a .jcr section on uClinux. As if this makes a difference... */
  21487. +#define TARGET_USE_JCR_SECTION 0
  21488. +
  21489. +/* Here we go. Drop the crtbegin/crtend stuff completely. */
  21490. +#undef STARTFILE_SPEC
  21491. +#define STARTFILE_SPEC \
  21492. + "%{!shared: %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s}" \
  21493. + " %{!p:%{profile:gcrt1.o%s}" \
  21494. + " %{!profile:crt1.o%s}}}} crti.o%s"
  21495. +
  21496. +#undef ENDFILE_SPEC
  21497. +#define ENDFILE_SPEC "crtn.o%s"
  21498. +
  21499. +#undef TARGET_DEFAULT
  21500. +#define TARGET_DEFAULT (AVR32_FLAG_NO_INIT_GOT)
  21501. --- a/gcc/config/host-linux.c
  21502. +++ b/gcc/config/host-linux.c
  21503. @@ -25,6 +25,9 @@
  21504. #include "hosthooks.h"
  21505. #include "hosthooks-def.h"
  21506. +#ifndef SSIZE_MAX
  21507. +#define SSIZE_MAX LONG_MAX
  21508. +#endif
  21509. /* Linux has a feature called exec-shield-randomize that perturbs the
  21510. address of non-fixed mapped segments by a (relatively) small amount.
  21511. --- a/gcc/config.gcc
  21512. +++ b/gcc/config.gcc
  21513. @@ -810,6 +810,24 @@ avr-*-rtems*)
  21514. avr-*-*)
  21515. tm_file="avr/avr.h dbxelf.h"
  21516. ;;
  21517. +avr32*-*-linux*)
  21518. + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h "
  21519. + tmake_file="t-linux avr32/t-avr32-linux"
  21520. + extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
  21521. + extra_modes=avr32/avr32-modes.def
  21522. + gnu_ld=yes
  21523. + ;;
  21524. +avr32*-*-uclinux*)
  21525. + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/uclinux-elf.h avr32/avr32.h"
  21526. + tmake_file="t-linux avr32/t-avr32-linux"
  21527. + extra_modes=avr32/avr32-modes.def
  21528. + gnu_ld=yes
  21529. + ;;
  21530. +avr32-*-*)
  21531. + tm_file="dbxelf.h elfos.h avr32/avr32.h avr32/avr32-elf.h"
  21532. + tmake_file="avr32/t-avr32 avr32/t-elf"
  21533. + extra_modes=avr32/avr32-modes.def
  21534. + ;;
  21535. bfin*-elf*)
  21536. tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h"
  21537. tmake_file=bfin/t-bfin-elf
  21538. @@ -2764,6 +2782,32 @@ case "${target}" in
  21539. fi
  21540. ;;
  21541. + avr32*-*-*)
  21542. + supported_defaults="part arch"
  21543. +
  21544. + case "$with_part" in
  21545. + "" \
  21546. + | "ap7000" | "ap7010" | "ap7020" | "uc3a0256" | "uc3a0512" | "uc3a1128" | "uc3a1256" | "uc3a1512" )
  21547. + # OK
  21548. + ;;
  21549. + *)
  21550. + echo "Unknown part used in --with-part=$with_part" 1>&2
  21551. + exit 1
  21552. + ;;
  21553. + esac
  21554. +
  21555. + case "$with_arch" in
  21556. + "" \
  21557. + | "ap" | "uc")
  21558. + # OK
  21559. + ;;
  21560. + *)
  21561. + echo "Unknown arch used in --with-arch=$with_arch" 1>&2
  21562. + exit 1
  21563. + ;;
  21564. + esac
  21565. + ;;
  21566. +
  21567. fr*-*-*linux*)
  21568. supported_defaults=cpu
  21569. case "$with_cpu" in
  21570. --- a/gcc/configure.ac
  21571. +++ b/gcc/configure.ac
  21572. @@ -2240,10 +2240,9 @@ L2:],
  21573. as_ver=`$gcc_cv_as --version 2>/dev/null | sed 1q`
  21574. if echo "$as_ver" | grep GNU > /dev/null; then
  21575. changequote(,)dnl
  21576. - as_vers=`echo $as_ver | sed -n \
  21577. - -e 's,^.*[ ]\([0-9][0-9]*\.[0-9][0-9]*.*\)$,\1,p'`
  21578. - as_major=`expr "$as_vers" : '\([0-9]*\)'`
  21579. - as_minor=`expr "$as_vers" : '[0-9]*\.\([0-9]*\)'`
  21580. + as_ver=`echo $as_ver | sed -e 's/GNU assembler\( (GNU Binutils)\)\? \([0-9.][0-9.]*\).*/\2/'`
  21581. + as_major=`echo $as_ver | sed 's/\..*//'`
  21582. + as_minor=`echo $as_ver | sed 's/[^.]*\.\([0-9]*\).*/\1/'`
  21583. changequote([,])dnl
  21584. if test $as_major -eq 2 && test $as_minor -lt 11
  21585. then :
  21586. @@ -3308,7 +3307,7 @@ case "$target" in
  21587. i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \
  21588. | x86_64*-*-* | hppa*-*-* | arm*-*-* \
  21589. | xstormy16*-*-* | cris-*-* | crisv32-*-* | xtensa*-*-* | bfin-*-* | score*-*-* \
  21590. - | spu-*-* | fido*-*-* | m32c-*-*)
  21591. + | spu-*-* | fido*-*-* | m32c-*-* | avr32-*-*)
  21592. insn="nop"
  21593. ;;
  21594. ia64*-*-* | s390*-*-*)
  21595. --- a/gcc/doc/extend.texi
  21596. +++ b/gcc/doc/extend.texi
  21597. @@ -2397,7 +2397,7 @@ This attribute is ignored for R8C target
  21598. @item interrupt
  21599. @cindex interrupt handler functions
  21600. -Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k,
  21601. +Use this attribute on the ARM, AVR, AVR32, CRX, M32C, M32R/D, m68k,
  21602. and Xstormy16 ports to indicate that the specified function is an
  21603. interrupt handler. The compiler will generate function entry and exit
  21604. sequences suitable for use in an interrupt handler when this attribute
  21605. @@ -2417,6 +2417,15 @@ void f () __attribute__ ((interrupt ("IR
  21606. Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and UNDEF@.
  21607. +Note, for the AVR32, you can specify which banking scheme is used for
  21608. +the interrupt mode this interrupt handler is used in like this:
  21609. +
  21610. +@smallexample
  21611. +void f () __attribute__ ((interrupt ("FULL")));
  21612. +@end smallexample
  21613. +
  21614. +Permissible values for this parameter are: FULL, HALF, NONE and UNDEF.
  21615. +
  21616. On ARMv7-M the interrupt type is ignored, and the attribute means the function
  21617. may be called with a word aligned stack pointer.
  21618. @@ -4188,6 +4197,23 @@ placed in either the @code{.bss_below100
  21619. @end table
  21620. +@subsection AVR32 Variable Attributes
  21621. +
  21622. +One attribute is currently defined for AVR32 configurations:
  21623. +@code{rmw_addressable}
  21624. +
  21625. +@table @code
  21626. +@item rmw_addressable
  21627. +@cindex @code{rmw_addressable} attribute
  21628. +
  21629. +This attribute can be used to signal that a variable can be accessed
  21630. +with the addressing mode of the AVR32 Atomic Read-Modify-Write memory
  21631. +instructions and hence make it possible for gcc to generate these
  21632. +instructions without using built-in functions or inline assembly statements.
  21633. +Variables used within the AVR32 Atomic Read-Modify-Write built-in
  21634. +functions will automatically get the @code{rmw_addressable} attribute.
  21635. +@end table
  21636. +
  21637. @subsection AVR Variable Attributes
  21638. @table @code
  21639. @@ -7042,6 +7068,7 @@ instructions, but allow the compiler to
  21640. * Alpha Built-in Functions::
  21641. * ARM iWMMXt Built-in Functions::
  21642. * ARM NEON Intrinsics::
  21643. +* AVR32 Built-in Functions::
  21644. * Blackfin Built-in Functions::
  21645. * FR-V Built-in Functions::
  21646. * X86 Built-in Functions::
  21647. @@ -7284,6 +7311,7 @@ long long __builtin_arm_wxor (long long,
  21648. long long __builtin_arm_wzero ()
  21649. @end smallexample
  21650. +
  21651. @node ARM NEON Intrinsics
  21652. @subsection ARM NEON Intrinsics
  21653. @@ -7292,6 +7320,74 @@ when the @option{-mfpu=neon} switch is u
  21654. @include arm-neon-intrinsics.texi
  21655. +@node AVR32 Built-in Functions
  21656. +@subsection AVR32 Built-in Functions
  21657. +
  21658. +Built-in functions for atomic memory (RMW) instructions. Note that these
  21659. +built-ins will fail for targets where the RMW instructions are not
  21660. +implemented. Also note that these instructions only that a Ks15 << 2
  21661. +memory address and will therefor not work with any runtime computed
  21662. +memory addresses. The user is responsible for making sure that any
  21663. +pointers used within these functions points to a valid memory address.
  21664. +
  21665. +@smallexample
  21666. +void __builtin_mems(int */*ptr*/, int /*bit*/)
  21667. +void __builtin_memc(int */*ptr*/, int /*bit*/)
  21668. +void __builtin_memt(int */*ptr*/, int /*bit*/)
  21669. +@end smallexample
  21670. +
  21671. +Built-in functions for DSP instructions. Note that these built-ins will
  21672. +fail for targets where the DSP instructions are not implemented.
  21673. +
  21674. +@smallexample
  21675. +int __builtin_sats (int /*Rd*/,int /*sa*/, int /*bn*/)
  21676. +int __builtin_satu (int /*Rd*/,int /*sa*/, int /*bn*/)
  21677. +int __builtin_satrnds (int /*Rd*/,int /*sa*/, int /*bn*/)
  21678. +int __builtin_satrndu (int /*Rd*/,int /*sa*/, int /*bn*/)
  21679. +short __builtin_mulsathh_h (short, short)
  21680. +int __builtin_mulsathh_w (short, short)
  21681. +short __builtin_mulsatrndhh_h (short, short)
  21682. +int __builtin_mulsatrndwh_w (int, short)
  21683. +int __builtin_mulsatwh_w (int, short)
  21684. +int __builtin_macsathh_w (int, short, short)
  21685. +short __builtin_satadd_h (short, short)
  21686. +short __builtin_satsub_h (short, short)
  21687. +int __builtin_satadd_w (int, int)
  21688. +int __builtin_satsub_w (int, int)
  21689. +long long __builtin_mulwh_d(int, short)
  21690. +long long __builtin_mulnwh_d(int, short)
  21691. +long long __builtin_macwh_d(long long, int, short)
  21692. +long long __builtin_machh_d(long long, short, short)
  21693. +@end smallexample
  21694. +
  21695. +Other built-in functions for instructions that cannot easily be
  21696. +generated by the compiler.
  21697. +
  21698. +@smallexample
  21699. +void __builtin_ssrf(int);
  21700. +void __builtin_csrf(int);
  21701. +void __builtin_musfr(int);
  21702. +int __builtin_mustr(void);
  21703. +int __builtin_mfsr(int /*Status Register Address*/)
  21704. +void __builtin_mtsr(int /*Status Register Address*/, int /*Value*/)
  21705. +int __builtin_mfdr(int /*Debug Register Address*/)
  21706. +void __builtin_mtdr(int /*Debug Register Address*/, int /*Value*/)
  21707. +void __builtin_cache(void * /*Address*/, int /*Cache Operation*/)
  21708. +void __builtin_sync(int /*Sync Operation*/)
  21709. +void __builtin_tlbr(void)
  21710. +void __builtin_tlbs(void)
  21711. +void __builtin_tlbw(void)
  21712. +void __builtin_breakpoint(void)
  21713. +int __builtin_xchg(void * /*Address*/, int /*Value*/ )
  21714. +short __builtin_bswap_16(short)
  21715. +int __builtin_bswap_32(int)
  21716. +void __builtin_cop(int/*cpnr*/, int/*crd*/, int/*crx*/, int/*cry*/, int/*op*/)
  21717. +int __builtin_mvcr_w(int/*cpnr*/, int/*crs*/)
  21718. +void __builtin_mvrc_w(int/*cpnr*/, int/*crd*/, int/*value*/)
  21719. +long long __builtin_mvcr_d(int/*cpnr*/, int/*crs*/)
  21720. +void __builtin_mvrc_d(int/*cpnr*/, int/*crd*/, long long/*value*/)
  21721. +@end smallexample
  21722. +
  21723. @node Blackfin Built-in Functions
  21724. @subsection Blackfin Built-in Functions
  21725. --- a/gcc/doc/invoke.texi
  21726. +++ b/gcc/doc/invoke.texi
  21727. @@ -195,7 +195,7 @@ in the following sections.
  21728. -fvisibility-ms-compat @gol
  21729. -Wabi -Wctor-dtor-privacy @gol
  21730. -Wnon-virtual-dtor -Wreorder @gol
  21731. --Weffc++ -Wstrict-null-sentinel @gol
  21732. +-Weffc++ -Wno-deprecated @gol
  21733. -Wno-non-template-friend -Wold-style-cast @gol
  21734. -Woverloaded-virtual -Wno-pmf-conversions @gol
  21735. -Wsign-promo}
  21736. @@ -641,6 +641,12 @@ Objective-C and Objective-C++ Dialects}.
  21737. -mauto-incdec -minmax -mlong-calls -mshort @gol
  21738. -msoft-reg-count=@var{count}}
  21739. +@emph{AVR32 Options}
  21740. +@gccoptlist{-muse-rodata-section -mhard-float -msoft-float -mrelax @gol
  21741. +-mforce-double-align -mno-init-got -mrelax -mmd-reorg-opt -masm-addr-pseudos @gol
  21742. +-mpart=@var{part} -mcpu=@var{cpu} -march=@var{arch} @gol
  21743. +-mfast-float -mimm-in-const-pool}
  21744. +
  21745. @emph{MCore Options}
  21746. @gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol
  21747. -mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol
  21748. @@ -3256,13 +3262,11 @@ appears in a class without constructors.
  21749. If you want to warn about code which uses the uninitialized value of the
  21750. variable in its own initializer, use the @option{-Winit-self} option.
  21751. -These warnings occur for individual uninitialized or clobbered
  21752. -elements of structure, union or array variables as well as for
  21753. -variables which are uninitialized or clobbered as a whole. They do
  21754. -not occur for variables or elements declared @code{volatile}. Because
  21755. -these warnings depend on optimization, the exact variables or elements
  21756. -for which there are warnings will depend on the precise optimization
  21757. -options and version of GCC used.
  21758. +These warnings occur only for variables that are candidates for
  21759. +register allocation. Therefore, they do not occur for a variable that
  21760. +is declared @code{volatile}, or whose address is taken, or whose size
  21761. +is other than 1, 2, 4 or 8 bytes. Also, they do not occur for
  21762. +structures, unions or arrays, even when they are in registers.
  21763. Note that there may be no warning about a variable that is used only
  21764. to compute a value that itself is never used, because such
  21765. @@ -7461,10 +7465,6 @@ If number of candidates in the set is sm
  21766. we always try to remove unnecessary ivs from the set during its
  21767. optimization when a new iv is added to the set.
  21768. -@item scev-max-expr-size
  21769. -Bound on size of expressions used in the scalar evolutions analyzer.
  21770. -Large expressions slow the analyzer.
  21771. -
  21772. @item omega-max-vars
  21773. The maximum number of variables in an Omega constraint system.
  21774. The default value is 128.
  21775. @@ -8860,6 +8860,7 @@ platform.
  21776. * ARC Options::
  21777. * ARM Options::
  21778. * AVR Options::
  21779. +* AVR32 Options::
  21780. * Blackfin Options::
  21781. * CRIS Options::
  21782. * CRX Options::
  21783. @@ -9348,6 +9349,145 @@ comply to the C standards, but it will p
  21784. size.
  21785. @end table
  21786. +@node AVR32 Options
  21787. +@subsection AVR32 Options
  21788. +@cindex AVR32 Options
  21789. +
  21790. +These options are defined for AVR32 implementations:
  21791. +
  21792. +@table @gcctabopt
  21793. +@item -muse-rodata-section
  21794. +@opindex muse-rodata-section
  21795. +Use section @samp{.rodata} for read-only data instead of @samp{.text}.
  21796. +
  21797. +@item -mhard-float
  21798. +@opindex mhard-float
  21799. +Use floating point coprocessor instructions.
  21800. +
  21801. +@item -msoft-float
  21802. +@opindex msoft-float
  21803. +Use software floating-point library for floating-point operations.
  21804. +
  21805. +@item -mforce-double-align
  21806. +@opindex mforce-double-align
  21807. +Force double-word alignment for double-word memory accesses.
  21808. +
  21809. +@item -masm-addr-pseudos
  21810. +@opindex masm-addr-pseudos
  21811. +Use assembler pseudo-instructions lda.w and call for handling direct
  21812. +addresses. (Enabled by default)
  21813. +
  21814. +@item -mno-init-got
  21815. +@opindex mno-init-got
  21816. +Do not initialize the GOT register before using it when compiling PIC
  21817. +code.
  21818. +
  21819. +@item -mrelax
  21820. +@opindex mrelax
  21821. +Let invoked assembler and linker do relaxing
  21822. +(Enabled by default when optimization level is >1).
  21823. +This means that when the address of symbols are known at link time,
  21824. +the linker can optimize @samp{icall} and @samp{mcall}
  21825. +instructions into a @samp{rcall} instruction if possible.
  21826. +Loading the address of a symbol can also be optimized.
  21827. +
  21828. +@item -mmd-reorg-opt
  21829. +@opindex mmd-reorg-opt
  21830. +Perform machine dependent optimizations in reorg stage.
  21831. +
  21832. +@item -mpart=@var{part}
  21833. +@opindex mpart
  21834. +Generate code for the specified part. Permissible parts are:
  21835. +@samp{ap7000},
  21836. +@samp{ap7001},
  21837. +@samp{ap7002},
  21838. +@samp{ap7200},
  21839. +@samp{uc3a0128},
  21840. +@samp{uc3a0256},
  21841. +@samp{uc3a0512},
  21842. +@samp{uc3a0512es},
  21843. +@samp{uc3a1128},
  21844. +@samp{uc3a1256},
  21845. +@samp{uc3a1512},
  21846. +@samp{uc3a1512es},
  21847. +@samp{uc3a3revd},
  21848. +@samp{uc3a364},
  21849. +@samp{uc3a364s},
  21850. +@samp{uc3a3128},
  21851. +@samp{uc3a3128s},
  21852. +@samp{uc3a3256},
  21853. +@samp{uc3a3256s},
  21854. +@samp{uc3a464},
  21855. +@samp{uc3a464s},
  21856. +@samp{uc3a4128},
  21857. +@samp{uc3a4128s},
  21858. +@samp{uc3a4256},
  21859. +@samp{uc3a4256s},
  21860. +@samp{uc3b064},
  21861. +@samp{uc3b0128},
  21862. +@samp{uc3b0256},
  21863. +@samp{uc3b0256es},
  21864. +@samp{uc3b0512},
  21865. +@samp{uc3b0512revc},
  21866. +@samp{uc3b164},
  21867. +@samp{uc3b1128},
  21868. +@samp{uc3b1256},
  21869. +@samp{uc3b1256es},
  21870. +@samp{uc3b1512},
  21871. +@samp{uc3b1512revc}
  21872. +@samp{uc64d3},
  21873. +@samp{uc128d3},
  21874. +@samp{uc64d4},
  21875. +@samp{uc128d4},
  21876. +@samp{uc3c0512crevc},
  21877. +@samp{uc3c1512crevc},
  21878. +@samp{uc3c2512crevc},
  21879. +@samp{uc3l0256},
  21880. +@samp{uc3l0128},
  21881. +@samp{uc3l064},
  21882. +@samp{uc3l032},
  21883. +@samp{uc3l016},
  21884. +@samp{uc3l064revb},
  21885. +@samp{uc64l3u},
  21886. +@samp{uc128l3u},
  21887. +@samp{uc256l3u},
  21888. +@samp{uc64l4u},
  21889. +@samp{uc128l4u},
  21890. +@samp{uc256l4u},
  21891. +@samp{uc3c064c},
  21892. +@samp{uc3c0128c},
  21893. +@samp{uc3c0256c},
  21894. +@samp{uc3c0512c},
  21895. +@samp{uc3c164c},
  21896. +@samp{uc3c1128c},
  21897. +@samp{uc3c1256c},
  21898. +@samp{uc3c1512c},
  21899. +@samp{uc3c264c},
  21900. +@samp{uc3c2128c},
  21901. +@samp{uc3c2256c},
  21902. +@samp{uc3c2512c},
  21903. +@samp{mxt768e}.
  21904. +
  21905. +@item -mcpu=@var{cpu-type}
  21906. +@opindex mcpu
  21907. +Same as -mpart. Obsolete.
  21908. +
  21909. +@item -march=@var{arch}
  21910. +@opindex march
  21911. +Generate code for the specified architecture. Permissible architectures are:
  21912. +@samp{ap}, @samp{uc} and @samp{ucr2}.
  21913. +
  21914. +@item -mfast-float
  21915. +@opindex mfast-float
  21916. +Enable fast floating-point library that does not conform to IEEE-754 but is still good enough
  21917. +for most applications. The fast floating-point library does not round to the nearest even
  21918. +but away from zero. Enabled by default if the -funsafe-math-optimizations switch is specified.
  21919. +
  21920. +@item -mimm-in-const-pool
  21921. +@opindex mimm-in-const-pool
  21922. +Put large immediates in constant pool. This is enabled by default for archs with insn-cache.
  21923. +@end table
  21924. +
  21925. @node Blackfin Options
  21926. @subsection Blackfin Options
  21927. @cindex Blackfin Options
  21928. @@ -9403,29 +9543,12 @@ When enabled, the compiler will ensure t
  21929. contain speculative loads after jump instructions. If this option is used,
  21930. @code{__WORKAROUND_SPECULATIVE_LOADS} is defined.
  21931. -@item -mno-specld-anomaly
  21932. -@opindex mno-specld-anomaly
  21933. -Don't generate extra code to prevent speculative loads from occurring.
  21934. -
  21935. @item -mcsync-anomaly
  21936. @opindex mcsync-anomaly
  21937. When enabled, the compiler will ensure that the generated code does not
  21938. contain CSYNC or SSYNC instructions too soon after conditional branches.
  21939. If this option is used, @code{__WORKAROUND_SPECULATIVE_SYNCS} is defined.
  21940. -@item -mno-csync-anomaly
  21941. -@opindex mno-csync-anomaly
  21942. -Don't generate extra code to prevent CSYNC or SSYNC instructions from
  21943. -occurring too soon after a conditional branch.
  21944. -
  21945. -@item -mlow-64k
  21946. -@opindex mlow-64k
  21947. -When enabled, the compiler is free to take advantage of the knowledge that
  21948. -the entire program fits into the low 64k of memory.
  21949. -
  21950. -@item -mno-low-64k
  21951. -@opindex mno-low-64k
  21952. -Assume that the program is arbitrarily large. This is the default.
  21953. @item -mstack-check-l1
  21954. @opindex mstack-check-l1
  21955. @@ -9439,11 +9562,6 @@ This allows for execute in place and sha
  21956. without virtual memory management. This option implies @option{-fPIC}.
  21957. With a @samp{bfin-elf} target, this option implies @option{-msim}.
  21958. -@item -mno-id-shared-library
  21959. -@opindex mno-id-shared-library
  21960. -Generate code that doesn't assume ID based shared libraries are being used.
  21961. -This is the default.
  21962. -
  21963. @item -mleaf-id-shared-library
  21964. @opindex mleaf-id-shared-library
  21965. Generate code that supports shared libraries via the library ID method,
  21966. @@ -9485,11 +9603,6 @@ call on this register. This switch is n
  21967. will lie outside of the 24 bit addressing range of the offset based
  21968. version of subroutine call instruction.
  21969. -This feature is not enabled by default. Specifying
  21970. -@option{-mno-long-calls} will restore the default behavior. Note these
  21971. -switches have no effect on how the compiler generates code to handle
  21972. -function calls via function pointers.
  21973. -
  21974. @item -mfast-fp
  21975. @opindex mfast-fp
  21976. Link with the fast floating-point library. This library relaxes some of
  21977. --- a/gcc/doc/md.texi
  21978. +++ b/gcc/doc/md.texi
  21979. @@ -4,6 +4,7 @@
  21980. @c This is part of the GCC manual.
  21981. @c For copying conditions, see the file gcc.texi.
  21982. +
  21983. @ifset INTERNALS
  21984. @node Machine Desc
  21985. @chapter Machine Descriptions
  21986. @@ -1685,6 +1686,58 @@ A memory reference suitable for iWMMXt l
  21987. A memory reference suitable for the ARMv4 ldrsb instruction.
  21988. @end table
  21989. +@item AVR32 family---@file{avr32.h}
  21990. +@table @code
  21991. +@item f
  21992. +Floating-point registers (f0 to f15)
  21993. +
  21994. +@item Ku@var{bits}
  21995. +Unsigned constant representable with @var{bits} number of bits (Must be
  21996. +two digits). I.e: An unsigned 8-bit constant is written as @samp{Ku08}
  21997. +
  21998. +@item Ks@var{bits}
  21999. +Signed constant representable with @var{bits} number of bits (Must be
  22000. +two digits). I.e: A signed 12-bit constant is written as @samp{Ks12}
  22001. +
  22002. +@item Is@var{bits}
  22003. +The negated range of a signed constant representable with @var{bits}
  22004. +number of bits. The same as @samp{Ks@var{bits}} with a negated range.
  22005. +This means that the constant must be in the range @math{-2^{bits-1}-1} to @math{2^{bits-1}}
  22006. +
  22007. +@item G
  22008. +A single/double precision floating-point immediate or 64-bit integer
  22009. +immediate where the least and most significant words both can be
  22010. +loaded with a move instruction. That is the the integer form of the
  22011. +values in the least and most significant words both are in the range
  22012. +@math{-2^{20}} to @math{2^{20}-1}.
  22013. +
  22014. +@item RKs@var{bits}
  22015. +A memory reference where the address consists of a base register
  22016. +plus a signed immediate displacement with range given by @samp{Ks@var{bits}}
  22017. +which has the same format as for the signed immediate integer constraint
  22018. +given above.
  22019. +
  22020. +@item RKu@var{bits}
  22021. +A memory reference where the address consists of a base register
  22022. +plus an unsigned immediate displacement with range given by @samp{Ku@var{bits}}
  22023. +which has the same format as for the unsigned immediate integer constraint
  22024. +given above.
  22025. +
  22026. +@item S
  22027. +A memory reference with an immediate or register offset
  22028. +
  22029. +@item T
  22030. +A memory reference to a constant pool entry
  22031. +
  22032. +@item W
  22033. +A valid operand for use in the @samp{lda.w} instruction macro when
  22034. +relaxing is enabled
  22035. +
  22036. +@item Z
  22037. +A memory reference valid for coprocessor memory instructions
  22038. +
  22039. +@end table
  22040. +
  22041. @item AVR family---@file{config/avr/constraints.md}
  22042. @table @code
  22043. @item l
  22044. --- a/gcc/expmed.c
  22045. +++ b/gcc/expmed.c
  22046. @@ -472,9 +472,9 @@ store_bit_field_1 (rtx str_rtx, unsigned
  22047. ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
  22048. || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
  22049. && byte_offset % GET_MODE_SIZE (fieldmode) == 0)
  22050. - : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
  22051. + : ( (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
  22052. || (offset * BITS_PER_UNIT % bitsize == 0
  22053. - && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))
  22054. + && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0)))))
  22055. {
  22056. if (MEM_P (op0))
  22057. op0 = adjust_address (op0, fieldmode, offset);
  22058. --- a/gcc/expr.c
  22059. +++ b/gcc/expr.c
  22060. @@ -52,6 +52,7 @@ along with GCC; see the file COPYING3.
  22061. #include "tree-flow.h"
  22062. #include "target.h"
  22063. #include "timevar.h"
  22064. +#include "c-common.h"
  22065. #include "df.h"
  22066. #include "diagnostic.h"
  22067. @@ -3647,16 +3648,17 @@ emit_single_push_insn (enum machine_mode
  22068. }
  22069. else
  22070. {
  22071. + emit_move_insn (stack_pointer_rtx,
  22072. + expand_binop (Pmode,
  22073. #ifdef STACK_GROWS_DOWNWARD
  22074. - /* ??? This seems wrong if STACK_PUSH_CODE == POST_DEC. */
  22075. - dest_addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
  22076. - GEN_INT (-(HOST_WIDE_INT) rounded_size));
  22077. + sub_optab,
  22078. #else
  22079. - /* ??? This seems wrong if STACK_PUSH_CODE == POST_INC. */
  22080. - dest_addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
  22081. - GEN_INT (rounded_size));
  22082. + add_optab,
  22083. #endif
  22084. - dest_addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, dest_addr);
  22085. + stack_pointer_rtx,
  22086. + GEN_INT (rounded_size),
  22087. + NULL_RTX, 0, OPTAB_LIB_WIDEN));
  22088. + dest_addr = stack_pointer_rtx;
  22089. }
  22090. dest = gen_rtx_MEM (mode, dest_addr);
  22091. @@ -5775,7 +5777,8 @@ store_field (rtx target, HOST_WIDE_INT b
  22092. is a bit field, we cannot use addressing to access it.
  22093. Use bit-field techniques or SUBREG to store in it. */
  22094. - if (mode == VOIDmode
  22095. + if (
  22096. + mode == VOIDmode
  22097. || (mode != BLKmode && ! direct_store[(int) mode]
  22098. && GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
  22099. && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
  22100. @@ -5932,7 +5935,18 @@ get_inner_reference (tree exp, HOST_WIDE
  22101. {
  22102. tree field = TREE_OPERAND (exp, 1);
  22103. size_tree = DECL_SIZE (field);
  22104. - if (!DECL_BIT_FIELD (field))
  22105. + if (!DECL_BIT_FIELD (field)
  22106. + /* Added for AVR32:
  22107. + Bitfields with a size equal to a target storage
  22108. + type might not cause DECL_BIT_FIELD to return
  22109. + true since it can be optimized into a normal array
  22110. + access operation. But for volatile bitfields we do
  22111. + not allow this when targetm.narrow_volatile_bitfield ()
  22112. + is false. We can use DECL_C_BIT_FIELD to check if this
  22113. + really is a c-bitfield. */
  22114. + && !(TREE_THIS_VOLATILE (exp)
  22115. + && !targetm.narrow_volatile_bitfield ()
  22116. + && DECL_C_BIT_FIELD (field)) )
  22117. mode = DECL_MODE (field);
  22118. else if (DECL_MODE (field) == BLKmode)
  22119. blkmode_bitfield = true;
  22120. @@ -7915,7 +7929,8 @@ expand_expr_real_1 (tree exp, rtx target
  22121. by doing the extract into an object as wide as the field
  22122. (which we know to be the width of a basic mode), then
  22123. storing into memory, and changing the mode to BLKmode. */
  22124. - if (mode1 == VOIDmode
  22125. + if (
  22126. + mode1 == VOIDmode
  22127. || REG_P (op0) || GET_CODE (op0) == SUBREG
  22128. || (mode1 != BLKmode && ! direct_load[(int) mode1]
  22129. && GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
  22130. --- a/gcc/function.c
  22131. +++ b/gcc/function.c
  22132. @@ -2810,7 +2810,11 @@ assign_parm_setup_reg (struct assign_par
  22133. assign_parm_remove_parallels (data);
  22134. /* Copy the value into the register. */
  22135. - if (data->nominal_mode != data->passed_mode
  22136. + if ( (data->nominal_mode != data->passed_mode
  22137. + /* Added for AVR32: If passed_mode is equal
  22138. + to promoted nominal mode why should be convert?
  22139. + The conversion should make no difference. */
  22140. + && data->passed_mode != promoted_nominal_mode)
  22141. || promoted_nominal_mode != data->promoted_mode)
  22142. {
  22143. int save_tree_used;
  22144. --- a/gcc/genemit.c
  22145. +++ b/gcc/genemit.c
  22146. @@ -121,6 +121,24 @@ max_operand_vec (rtx insn, int arg)
  22147. }
  22148. static void
  22149. +gen_vararg_prologue(int operands)
  22150. +{
  22151. + int i;
  22152. +
  22153. + if (operands > 1)
  22154. + {
  22155. + for (i = 1; i < operands; i++)
  22156. + printf(" rtx operand%d ATTRIBUTE_UNUSED;\n", i);
  22157. +
  22158. + printf(" va_list args;\n\n");
  22159. + printf(" va_start(args, operand0);\n");
  22160. + for (i = 1; i < operands; i++)
  22161. + printf(" operand%d = va_arg(args, rtx);\n", i);
  22162. + printf(" va_end(args);\n\n");
  22163. + }
  22164. +}
  22165. +
  22166. +static void
  22167. print_code (RTX_CODE code)
  22168. {
  22169. const char *p1;
  22170. @@ -406,18 +424,16 @@ gen_insn (rtx insn, int lineno)
  22171. fatal ("match_dup operand number has no match_operand");
  22172. /* Output the function name and argument declarations. */
  22173. - printf ("rtx\ngen_%s (", XSTR (insn, 0));
  22174. + printf ("rtx\ngen_%s ", XSTR (insn, 0));
  22175. +
  22176. if (operands)
  22177. - for (i = 0; i < operands; i++)
  22178. - if (i)
  22179. - printf (",\n\trtx operand%d ATTRIBUTE_UNUSED", i);
  22180. + printf("(rtx operand0 ATTRIBUTE_UNUSED, ...)\n");
  22181. else
  22182. - printf ("rtx operand%d ATTRIBUTE_UNUSED", i);
  22183. - else
  22184. - printf ("void");
  22185. - printf (")\n");
  22186. + printf("(void)\n");
  22187. printf ("{\n");
  22188. + gen_vararg_prologue(operands);
  22189. +
  22190. /* Output code to construct and return the rtl for the instruction body. */
  22191. if (XVECLEN (insn, 1) == 1)
  22192. @@ -461,16 +477,12 @@ gen_expand (rtx expand)
  22193. operands = max_operand_vec (expand, 1);
  22194. /* Output the function name and argument declarations. */
  22195. - printf ("rtx\ngen_%s (", XSTR (expand, 0));
  22196. + printf ("rtx\ngen_%s ", XSTR (expand, 0));
  22197. if (operands)
  22198. - for (i = 0; i < operands; i++)
  22199. - if (i)
  22200. - printf (",\n\trtx operand%d", i);
  22201. - else
  22202. - printf ("rtx operand%d", i);
  22203. + printf("(rtx operand0 ATTRIBUTE_UNUSED, ...)\n");
  22204. else
  22205. - printf ("void");
  22206. - printf (")\n");
  22207. + printf("(void)\n");
  22208. +
  22209. printf ("{\n");
  22210. /* If we don't have any C code to write, only one insn is being written,
  22211. @@ -480,6 +492,8 @@ gen_expand (rtx expand)
  22212. && operands > max_dup_opno
  22213. && XVECLEN (expand, 1) == 1)
  22214. {
  22215. + gen_vararg_prologue(operands);
  22216. +
  22217. printf (" return ");
  22218. gen_exp (XVECEXP (expand, 1, 0), DEFINE_EXPAND, NULL);
  22219. printf (";\n}\n\n");
  22220. @@ -493,6 +507,7 @@ gen_expand (rtx expand)
  22221. for (; i <= max_scratch_opno; i++)
  22222. printf (" rtx operand%d ATTRIBUTE_UNUSED;\n", i);
  22223. printf (" rtx _val = 0;\n");
  22224. + gen_vararg_prologue(operands);
  22225. printf (" start_sequence ();\n");
  22226. /* The fourth operand of DEFINE_EXPAND is some code to be executed
  22227. --- a/gcc/genflags.c
  22228. +++ b/gcc/genflags.c
  22229. @@ -127,7 +127,6 @@ static void
  22230. gen_proto (rtx insn)
  22231. {
  22232. int num = num_operands (insn);
  22233. - int i;
  22234. const char *name = XSTR (insn, 0);
  22235. int truth = maybe_eval_c_test (XSTR (insn, 2));
  22236. @@ -158,12 +157,7 @@ gen_proto (rtx insn)
  22237. if (num == 0)
  22238. fputs ("void", stdout);
  22239. else
  22240. - {
  22241. - for (i = 1; i < num; i++)
  22242. - fputs ("rtx, ", stdout);
  22243. -
  22244. - fputs ("rtx", stdout);
  22245. - }
  22246. + fputs("rtx, ...", stdout);
  22247. puts (");");
  22248. @@ -173,12 +167,7 @@ gen_proto (rtx insn)
  22249. {
  22250. printf ("static inline rtx\ngen_%s", name);
  22251. if (num > 0)
  22252. - {
  22253. - putchar ('(');
  22254. - for (i = 0; i < num-1; i++)
  22255. - printf ("rtx ARG_UNUSED (%c), ", 'a' + i);
  22256. - printf ("rtx ARG_UNUSED (%c))\n", 'a' + i);
  22257. - }
  22258. + puts("(rtx ARG_UNUSED(a), ...)");
  22259. else
  22260. puts ("(void)");
  22261. puts ("{\n return 0;\n}");
  22262. --- a/gcc/genoutput.c
  22263. +++ b/gcc/genoutput.c
  22264. @@ -386,7 +386,7 @@ output_insn_data (void)
  22265. }
  22266. if (d->name && d->name[0] != '*')
  22267. - printf (" (insn_gen_fn) gen_%s,\n", d->name);
  22268. + printf (" gen_%s,\n", d->name);
  22269. else
  22270. printf (" 0,\n");
  22271. --- a/gcc/ifcvt.c
  22272. +++ b/gcc/ifcvt.c
  22273. @@ -84,7 +84,7 @@ static int num_possible_if_blocks;
  22274. static int num_updated_if_blocks;
  22275. /* # of changes made. */
  22276. -static int num_true_changes;
  22277. +int num_true_changes;
  22278. /* Whether conditional execution changes were made. */
  22279. static int cond_exec_changed_p;
  22280. @@ -290,6 +290,9 @@ cond_exec_process_insns (ce_if_block_t *
  22281. if (must_be_last)
  22282. return FALSE;
  22283. +#ifdef IFCVT_ALLOW_MODIFY_TEST_IN_INSN
  22284. + if ( !IFCVT_ALLOW_MODIFY_TEST_IN_INSN )
  22285. +#endif
  22286. if (modified_in_p (test, insn))
  22287. {
  22288. if (!mod_ok)
  22289. @@ -570,15 +573,18 @@ cond_exec_process_if_block (ce_if_block_
  22290. IFCVT_MODIFY_FINAL (ce_info);
  22291. #endif
  22292. + /* Merge the blocks! */
  22293. + if ( reload_completed ){
  22294. /* Conversion succeeded. */
  22295. if (dump_file)
  22296. fprintf (dump_file, "%d insn%s converted to conditional execution.\n",
  22297. n_insns, (n_insns == 1) ? " was" : "s were");
  22298. - /* Merge the blocks! */
  22299. merge_if_block (ce_info);
  22300. cond_exec_changed_p = TRUE;
  22301. return TRUE;
  22302. + }
  22303. + return FALSE;
  22304. fail:
  22305. #ifdef IFCVT_MODIFY_CANCEL
  22306. @@ -1087,7 +1093,11 @@ noce_try_addcc (struct noce_if_info *if_
  22307. != UNKNOWN))
  22308. {
  22309. rtx cond = if_info->cond;
  22310. - enum rtx_code code = reversed_comparison_code (cond, if_info->jump);
  22311. + /* This generates wrong code for AVR32. The cond code need not be reversed
  22312. + since the addmodecc patterns add if the condition is NOT met. */
  22313. + /* enum rtx_code code = reversed_comparison_code (cond, if_info->jump);*/
  22314. + enum rtx_code code = GET_CODE(cond);
  22315. +
  22316. /* First try to use addcc pattern. */
  22317. if (general_operand (XEXP (cond, 0), VOIDmode)
  22318. @@ -3039,7 +3049,12 @@ find_if_header (basic_block test_bb, int
  22319. && noce_find_if_block (test_bb, then_edge, else_edge, pass))
  22320. goto success;
  22321. - if (HAVE_conditional_execution && reload_completed
  22322. + if (HAVE_conditional_execution &&
  22323. +#ifdef IFCVT_COND_EXEC_BEFORE_RELOAD
  22324. + (reload_completed || IFCVT_COND_EXEC_BEFORE_RELOAD)
  22325. +#else
  22326. + reload_completed
  22327. +#endif
  22328. && cond_exec_find_if_block (&ce_info))
  22329. goto success;
  22330. @@ -3154,7 +3169,11 @@ cond_exec_find_if_block (struct ce_if_bl
  22331. /* We only ever should get here after reload,
  22332. and only if we have conditional execution. */
  22333. +#ifdef IFCVT_COND_EXEC_BEFORE_RELOAD
  22334. + gcc_assert (HAVE_conditional_execution && (reload_completed||IFCVT_COND_EXEC_BEFORE_RELOAD));
  22335. +#else
  22336. gcc_assert (HAVE_conditional_execution && reload_completed);
  22337. +#endif
  22338. /* Discover if any fall through predecessors of the current test basic block
  22339. were && tests (which jump to the else block) or || tests (which jump to
  22340. @@ -4259,6 +4278,14 @@ gate_handle_if_after_reload (void)
  22341. static unsigned int
  22342. rest_of_handle_if_after_reload (void)
  22343. {
  22344. + /* Hack for the AVR32 experimental ifcvt processing before reload.
  22345. + The AVR32 specific ifcvt code needs to know when ifcvt after reload
  22346. + has begun. */
  22347. +#ifdef IFCVT_COND_EXEC_BEFORE_RELOAD
  22348. + if ( IFCVT_COND_EXEC_BEFORE_RELOAD )
  22349. + cfun->machine->ifcvt_after_reload = 1;
  22350. +#endif
  22351. +
  22352. if_convert ();
  22353. return 0;
  22354. }
  22355. --- a/gcc/longlong.h
  22356. +++ b/gcc/longlong.h
  22357. @@ -250,6 +250,41 @@ UDItype __umulsidi3 (USItype, USItype);
  22358. #define COUNT_LEADING_ZEROS_0 32
  22359. #endif
  22360. +#if defined (__avr32__) && W_TYPE_SIZE == 32
  22361. +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  22362. + __asm__ ("add\t%1, %4, %5\n\tadc\t%0, %2, %3" \
  22363. + : "=r" ((USItype) (sh)), \
  22364. + "=&r" ((USItype) (sl)) \
  22365. + : "r" ((USItype) (ah)), \
  22366. + "r" ((USItype) (bh)), \
  22367. + "r" ((USItype) (al)), \
  22368. + "r" ((USItype) (bl)) __CLOBBER_CC)
  22369. +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  22370. + __asm__ ("sub\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
  22371. + : "=r" ((USItype) (sh)), \
  22372. + "=&r" ((USItype) (sl)) \
  22373. + : "r" ((USItype) (ah)), \
  22374. + "r" ((USItype) (bh)), \
  22375. + "r" ((USItype) (al)), \
  22376. + "r" ((USItype) (bl)) __CLOBBER_CC)
  22377. +
  22378. +#if !defined (__AVR32_NO_MUL__)
  22379. +#define __umulsidi3(a,b) ((UDItype)(a) * (UDItype)(b))
  22380. +
  22381. +#define umul_ppmm(w1, w0, u, v) \
  22382. +{ \
  22383. + DWunion __w; \
  22384. + __w.ll = __umulsidi3 (u, v); \
  22385. + w1 = __w.s.high; \
  22386. + w0 = __w.s.low; \
  22387. +}
  22388. +#endif
  22389. +
  22390. +#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
  22391. +#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
  22392. +#define COUNT_LEADING_ZEROS_0 32
  22393. +#endif
  22394. +
  22395. #if defined (__CRIS__) && __CRIS_arch_version >= 3
  22396. #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
  22397. #if __CRIS_arch_version >= 8
  22398. --- a/gcc/optabs.h
  22399. +++ b/gcc/optabs.h
  22400. @@ -603,7 +603,7 @@ extern enum insn_code reload_out_optab[N
  22401. extern optab code_to_optab[NUM_RTX_CODE + 1];
  22402. -typedef rtx (*rtxfun) (rtx);
  22403. +typedef rtx (*rtxfun) (rtx, ...);
  22404. /* Indexed by the rtx-code for a conditional (e.g. EQ, LT,...)
  22405. gives the gen_function to make a branch to test that condition. */
  22406. --- a/gcc/regrename.c
  22407. +++ b/gcc/regrename.c
  22408. @@ -1582,6 +1582,9 @@ copyprop_hardreg_forward_1 (basic_block
  22409. bool changed = false;
  22410. rtx insn;
  22411. + rtx prev_pred_test;
  22412. + int prev_pred_insn_skipped = 0;
  22413. +
  22414. for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
  22415. {
  22416. int n_ops, i, alt, predicated;
  22417. @@ -1621,6 +1624,58 @@ copyprop_hardreg_forward_1 (basic_block
  22418. recog_data.operand_type[i] = OP_INOUT;
  22419. }
  22420. +
  22421. + /* Added for targets (AVR32) which supports test operands to be modified
  22422. + in cond_exec instruction. For these targets we cannot make a change to
  22423. + the test operands if one of the test operands is an output operand This beacuse
  22424. + changing the test operands might cause the need for inserting a new test
  22425. + insns in the middle of a sequence of cond_exec insns and if the test operands
  22426. + are modified these tests will fail.
  22427. + */
  22428. + if ( IFCVT_ALLOW_MODIFY_TEST_IN_INSN
  22429. + && predicated )
  22430. + {
  22431. + int insn_skipped = 0;
  22432. + rtx test = COND_EXEC_TEST (PATTERN (insn));
  22433. +
  22434. + /* Check if the previous insn was a skipped predicated insn with the same
  22435. + test as this predicated insns. If so we cannot do any modification to
  22436. + this insn either since we cannot emit the test insn because the operands
  22437. + are clobbered. */
  22438. + if ( prev_pred_insn_skipped
  22439. + && (rtx_equal_p (test, prev_pred_test)
  22440. + || rtx_equal_p (test, reversed_condition (prev_pred_test))) )
  22441. + {
  22442. + insn_skipped = 1;
  22443. + }
  22444. + else
  22445. + {
  22446. + /* Check if the output operand is used in the test expression. */
  22447. + for (i = 0; i < n_ops; ++i)
  22448. + if ( recog_data.operand_type[i] == OP_INOUT
  22449. + && reg_mentioned_p (recog_data.operand[i], test) )
  22450. + {
  22451. + insn_skipped = 1;
  22452. + break;
  22453. + }
  22454. +
  22455. + }
  22456. +
  22457. + prev_pred_test = test;
  22458. + prev_pred_insn_skipped = insn_skipped;
  22459. + if ( insn_skipped )
  22460. + {
  22461. + if (insn == BB_END (bb))
  22462. + break;
  22463. + else
  22464. + continue;
  22465. + }
  22466. + }
  22467. + else
  22468. + {
  22469. + prev_pred_insn_skipped = 0;
  22470. + }
  22471. +
  22472. /* For each earlyclobber operand, zap the value data. */
  22473. for (i = 0; i < n_ops; i++)
  22474. if (recog_op_alt[i][alt].earlyclobber)
  22475. --- a/gcc/sched-deps.c
  22476. +++ b/gcc/sched-deps.c
  22477. @@ -1473,7 +1473,14 @@ fixup_sched_groups (rtx insn)
  22478. prev_nonnote = prev_nonnote_insn (insn);
  22479. if (BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (prev_nonnote)
  22480. - && ! sched_insns_conditions_mutex_p (insn, prev_nonnote))
  22481. + /* Modification for AVR32 by RP: Why is this here, this will
  22482. + cause instruction to be without any dependencies which might
  22483. + cause it to be moved anywhere. For the AVR32 we try to keep
  22484. + a group of conditionals together even if they are mutual exclusive.
  22485. + */
  22486. + && (! sched_insns_conditions_mutex_p (insn, prev_nonnote)
  22487. + || GET_CODE (PATTERN (insn)) == COND_EXEC )
  22488. + )
  22489. add_dependence (insn, prev_nonnote, REG_DEP_ANTI);
  22490. }
  22491. @@ -2230,8 +2237,29 @@ sched_analyze_insn (struct deps *deps, r
  22492. if (code == COND_EXEC)
  22493. {
  22494. +#ifdef IFCVT_ALLOW_MODIFY_TEST_IN_INSN
  22495. + if (IFCVT_ALLOW_MODIFY_TEST_IN_INSN)
  22496. + {
  22497. + /* Check if we have a group og conditional instructions with the same test.
  22498. + If so we must make sure that they are not scheduled apart in order to
  22499. + avoid unnecesarry tests and if one of the registers in the test is modified
  22500. + in the instruction this is needed to ensure correct code. */
  22501. + if ( prev_nonnote_insn (insn)
  22502. + && INSN_P (prev_nonnote_insn (insn))
  22503. + && GET_CODE (PATTERN (prev_nonnote_insn (insn))) == COND_EXEC
  22504. + && rtx_equal_p (XEXP(COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn))), 0), XEXP (COND_EXEC_TEST (x), 0))
  22505. + && rtx_equal_p (XEXP(COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn))), 1), XEXP (COND_EXEC_TEST (x), 1))
  22506. + && ( GET_CODE (COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn)))) == GET_CODE (COND_EXEC_TEST (x))
  22507. + || GET_CODE (COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn)))) == reversed_comparison_code (COND_EXEC_TEST (x), insn)))
  22508. + {
  22509. + SCHED_GROUP_P (insn) = 1;
  22510. + //CANT_MOVE (prev_nonnote_insn (insn)) = 1;
  22511. + }
  22512. + }
  22513. +#endif
  22514. sched_analyze_2 (deps, COND_EXEC_TEST (x), insn);
  22515. +
  22516. /* ??? Should be recording conditions so we reduce the number of
  22517. false dependencies. */
  22518. x = COND_EXEC_CODE (x);
  22519. --- a/gcc/testsuite/gcc.dg/sibcall-3.c
  22520. +++ b/gcc/testsuite/gcc.dg/sibcall-3.c
  22521. @@ -5,7 +5,7 @@
  22522. Copyright (C) 2002 Free Software Foundation Inc.
  22523. Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
  22524. -/* { dg-do run { xfail { { arc-*-* avr-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  22525. +/* { dg-do run { xfail { { arc-*-* avr-*-* avr32-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  22526. /* -mlongcall disables sibcall patterns. */
  22527. /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
  22528. /* { dg-options "-O2 -foptimize-sibling-calls" } */
  22529. --- a/gcc/testsuite/gcc.dg/sibcall-4.c
  22530. +++ b/gcc/testsuite/gcc.dg/sibcall-4.c
  22531. @@ -5,7 +5,7 @@
  22532. Copyright (C) 2002 Free Software Foundation Inc.
  22533. Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
  22534. -/* { dg-do run { xfail { { arc-*-* avr-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  22535. +/* { dg-do run { xfail { { arc-*-* avr-*-* avr32-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  22536. /* -mlongcall disables sibcall patterns. */
  22537. /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
  22538. /* { dg-options "-O2 -foptimize-sibling-calls" } */
  22539. --- a/gcc/testsuite/gcc.dg/trampoline-1.c
  22540. +++ b/gcc/testsuite/gcc.dg/trampoline-1.c
  22541. @@ -47,6 +47,8 @@ void foo (void)
  22542. int main (void)
  22543. {
  22544. +#ifndef NO_TRAMPOLINES
  22545. foo ();
  22546. +#endif
  22547. return 0;
  22548. }
  22549. --- a/libgcc/config.host
  22550. +++ b/libgcc/config.host
  22551. @@ -218,6 +218,13 @@ arm*-wince-pe*)
  22552. ;;
  22553. arm-*-pe*)
  22554. ;;
  22555. +avr32-*-linux*)
  22556. + # No need to build crtbeginT.o on uClibc systems. Should probably be
  22557. + # moved to the OS specific section above.
  22558. + extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
  22559. + ;;
  22560. +avr32-*-*)
  22561. + ;;
  22562. avr-*-rtems*)
  22563. ;;
  22564. avr-*-*)
  22565. --- a/libstdc++-v3/config/os/gnu-linux/ctype_base.h
  22566. +++ b/libstdc++-v3/config/os/gnu-linux/ctype_base.h
  22567. @@ -26,6 +26,8 @@
  22568. //
  22569. // ISO C++ 14882: 22.1 Locales
  22570. //
  22571. +#include <features.h>
  22572. +#include <ctype.h>
  22573. /** @file ctype_base.h
  22574. * This is an internal header file, included by other library headers.
  22575. @@ -40,7 +42,11 @@ _GLIBCXX_BEGIN_NAMESPACE(std)
  22576. struct ctype_base
  22577. {
  22578. // Non-standard typedefs.
  22579. +#ifdef __UCLIBC__
  22580. + typedef const __ctype_touplow_t* __to_type;
  22581. +#else
  22582. typedef const int* __to_type;
  22583. +#endif
  22584. // NB: Offsets into ctype<char>::_M_table force a particular size
  22585. // on the mask type. Because of this, we don't use an enum.
  22586. --- a/libstdc++-v3/include/Makefile.in
  22587. +++ b/libstdc++-v3/include/Makefile.in
  22588. @@ -36,6 +36,7 @@ POST_UNINSTALL = :
  22589. build_triplet = @build@
  22590. host_triplet = @host@
  22591. target_triplet = @target@
  22592. +LIBOBJDIR =
  22593. DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
  22594. $(top_srcdir)/fragment.am
  22595. subdir = include
  22596. --- a/libstdc++-v3/libsupc++/Makefile.in
  22597. +++ b/libstdc++-v3/libsupc++/Makefile.in
  22598. @@ -38,6 +38,7 @@ POST_UNINSTALL = :
  22599. build_triplet = @build@
  22600. host_triplet = @host@
  22601. target_triplet = @target@
  22602. +LIBOBJDIR =
  22603. DIST_COMMON = $(glibcxxinstall_HEADERS) $(srcdir)/Makefile.am \
  22604. $(srcdir)/Makefile.in $(top_srcdir)/fragment.am
  22605. subdir = libsupc++
  22606. --- a/libstdc++-v3/Makefile.in
  22607. +++ b/libstdc++-v3/Makefile.in
  22608. @@ -36,6 +36,7 @@ POST_UNINSTALL = :
  22609. build_triplet = @build@
  22610. host_triplet = @host@
  22611. target_triplet = @target@
  22612. +LIBOBJDIR =
  22613. DIST_COMMON = $(top_srcdir)/fragment.am $(srcdir)/../config.guess \
  22614. $(srcdir)/../config.sub README ChangeLog $(srcdir)/Makefile.in \
  22615. $(srcdir)/Makefile.am $(top_srcdir)/configure \
  22616. --- a/libstdc++-v3/po/Makefile.in
  22617. +++ b/libstdc++-v3/po/Makefile.in
  22618. @@ -36,6 +36,7 @@ POST_UNINSTALL = :
  22619. build_triplet = @build@
  22620. host_triplet = @host@
  22621. target_triplet = @target@
  22622. +LIBOBJDIR =
  22623. DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
  22624. $(top_srcdir)/fragment.am
  22625. subdir = po
  22626. --- a/libstdc++-v3/src/Makefile.in
  22627. +++ b/libstdc++-v3/src/Makefile.in
  22628. @@ -37,6 +37,7 @@ POST_UNINSTALL = :
  22629. build_triplet = @build@
  22630. host_triplet = @host@
  22631. target_triplet = @target@
  22632. +LIBOBJDIR =
  22633. DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
  22634. $(top_srcdir)/fragment.am
  22635. subdir = src