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j2.patch 13 KB

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  1. diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.c gcc-6.2.0/gcc/config/sh/sh.c
  2. --- gcc-6.2.0.orig/gcc/config/sh/sh.c 2016-04-22 13:09:22.000000000 +0200
  3. +++ gcc-6.2.0/gcc/config/sh/sh.c 2016-12-10 19:58:58.649784537 +0100
  4. @@ -692,6 +692,7 @@
  5. model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
  6. model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
  7. model_names[sh_atomic_model::soft_imask] = "soft-imask";
  8. + model_names[sh_atomic_model::hard_cas] = "hard-cas";
  9. const char* model_cdef_names[sh_atomic_model::num_models];
  10. model_cdef_names[sh_atomic_model::none] = "NONE";
  11. @@ -699,6 +700,7 @@
  12. model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
  13. model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
  14. model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
  15. + model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
  16. sh_atomic_model ret;
  17. ret.type = sh_atomic_model::none;
  18. @@ -780,6 +782,9 @@
  19. if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
  20. err_ret ("cannot use atomic model %s in user mode", ret.name);
  21. + if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
  22. + err_ret ("atomic model %s is only available J2 targets", ret.name);
  23. +
  24. return ret;
  25. #undef err_ret
  26. @@ -845,6 +850,8 @@
  27. sh_cpu = PROCESSOR_SH2E;
  28. if (TARGET_SH2A)
  29. sh_cpu = PROCESSOR_SH2A;
  30. + if (TARGET_SHJ2)
  31. + sh_cpu = PROCESSOR_SHJ2;
  32. if (TARGET_SH3)
  33. sh_cpu = PROCESSOR_SH3;
  34. if (TARGET_SH3E)
  35. diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.h gcc-6.2.0/gcc/config/sh/sh.h
  36. --- gcc-6.2.0.orig/gcc/config/sh/sh.h 2016-01-04 15:30:50.000000000 +0100
  37. +++ gcc-6.2.0/gcc/config/sh/sh.h 2016-12-10 19:58:58.649784537 +0100
  38. @@ -106,6 +106,7 @@
  39. #define SUPPORT_SH4_SINGLE 1
  40. #define SUPPORT_SH2A 1
  41. #define SUPPORT_SH2A_SINGLE 1
  42. +#define SUPPORT_SHJ2 1
  43. #endif
  44. #define TARGET_DIVIDE_INV \
  45. @@ -157,6 +158,7 @@
  46. #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
  47. #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
  48. #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
  49. +#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
  50. #if SUPPORT_SH1
  51. #define SUPPORT_SH2 1
  52. @@ -164,6 +166,7 @@
  53. #if SUPPORT_SH2
  54. #define SUPPORT_SH3 1
  55. #define SUPPORT_SH2A_NOFPU 1
  56. +#define SUPPORT_SHJ2 1
  57. #endif
  58. #if SUPPORT_SH3
  59. #define SUPPORT_SH4_NOFPU 1
  60. @@ -211,7 +214,7 @@
  61. #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
  62. | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
  63. | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
  64. - | MASK_FPU_SINGLE_ONLY)
  65. + | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
  66. /* This defaults us to big-endian. */
  67. #ifndef TARGET_ENDIAN_DEFAULT
  68. @@ -289,8 +292,8 @@
  69. %{m5-compact*:--isa=SHcompact} \
  70. %{m5-32media*:--isa=SHmedia --abi=32} \
  71. %{m5-64media*:--isa=SHmedia --abi=64} \
  72. -%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
  73. -
  74. +%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \
  75. +%{mj2:-isa=j2}"
  76. #define ASM_SPEC SH_ASM_SPEC
  77. #ifndef SUBTARGET_ASM_ENDIAN_SPEC
  78. @@ -1853,7 +1856,7 @@
  79. /* Nonzero if the target supports dynamic shift instructions
  80. like shad and shld. */
  81. -#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
  82. +#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
  83. /* The cost of using the dynamic shift insns (shad, shld) are the same
  84. if they are available. If they are not available a library function will
  85. @@ -2185,6 +2188,7 @@
  86. PROCESSOR_SH2,
  87. PROCESSOR_SH2E,
  88. PROCESSOR_SH2A,
  89. + PROCESSOR_SHJ2,
  90. PROCESSOR_SH3,
  91. PROCESSOR_SH3E,
  92. PROCESSOR_SH4,
  93. diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.opt gcc-6.2.0/gcc/config/sh/sh.opt
  94. --- gcc-6.2.0.orig/gcc/config/sh/sh.opt 2016-01-04 15:30:50.000000000 +0100
  95. +++ gcc-6.2.0/gcc/config/sh/sh.opt 2016-12-10 19:58:58.649784537 +0100
  96. @@ -71,6 +71,10 @@
  97. Target RejectNegative Condition(SUPPORT_SH2E)
  98. Generate SH2e code.
  99. +mj2
  100. +Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
  101. +Generate J2 code.
  102. +
  103. m3
  104. Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
  105. Generate SH3 code.
  106. diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh-protos.h gcc-6.2.0/gcc/config/sh/sh-protos.h
  107. --- gcc-6.2.0.orig/gcc/config/sh/sh-protos.h 2016-01-04 15:30:50.000000000 +0100
  108. +++ gcc-6.2.0/gcc/config/sh/sh-protos.h 2016-12-10 19:58:58.641785064 +0100
  109. @@ -45,6 +45,7 @@
  110. hard_llcs,
  111. soft_tcb,
  112. soft_imask,
  113. + hard_cas,
  114. num_models
  115. };
  116. @@ -88,6 +89,9 @@
  117. #define TARGET_ATOMIC_SOFT_IMASK \
  118. (selected_atomic_model ().type == sh_atomic_model::soft_imask)
  119. +#define TARGET_ATOMIC_HARD_CAS \
  120. + (selected_atomic_model ().type == sh_atomic_model::hard_cas)
  121. +
  122. #ifdef RTX_CODE
  123. extern rtx sh_fsca_sf2int (void);
  124. extern rtx sh_fsca_int2sf (void);
  125. diff -Nur gcc-6.2.0.orig/gcc/config/sh/sync.md gcc-6.2.0/gcc/config/sh/sync.md
  126. --- gcc-6.2.0.orig/gcc/config/sh/sync.md 2016-01-04 15:30:50.000000000 +0100
  127. +++ gcc-6.2.0/gcc/config/sh/sync.md 2016-12-10 19:58:58.649784537 +0100
  128. @@ -240,6 +240,9 @@
  129. || (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
  130. atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
  131. exp_val, new_val);
  132. + else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
  133. + atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
  134. + exp_val, new_val);
  135. else if (TARGET_ATOMIC_SOFT_GUSA)
  136. atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
  137. exp_val, new_val);
  138. @@ -306,6 +309,57 @@
  139. }
  140. [(set_attr "length" "14")])
  141. +(define_expand "atomic_compare_and_swapsi_cas"
  142. + [(set (match_operand:SI 0 "register_operand" "=r")
  143. + (unspec_volatile:SI
  144. + [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
  145. + (match_operand:SI 2 "register_operand" "r")
  146. + (match_operand:SI 3 "register_operand" "r")]
  147. + UNSPECV_CMPXCHG_1))]
  148. + "TARGET_ATOMIC_HARD_CAS"
  149. +{
  150. + rtx mem = gen_rtx_REG (SImode, 0);
  151. + emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
  152. + emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
  153. + DONE;
  154. +})
  155. +
  156. +(define_insn "shj2_cas"
  157. + [(set (match_operand:SI 0 "register_operand" "=&r")
  158. + (unspec_volatile:SI
  159. + [(match_operand:SI 1 "register_operand" "=r")
  160. + (match_operand:SI 2 "register_operand" "r")
  161. + (match_operand:SI 3 "register_operand" "0")]
  162. + UNSPECV_CMPXCHG_1))
  163. + (set (reg:SI T_REG)
  164. + (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
  165. + "TARGET_ATOMIC_HARD_CAS"
  166. + "cas.l %2,%0,@%1"
  167. + [(set_attr "length" "2")]
  168. +)
  169. +
  170. +(define_expand "atomic_compare_and_swapqi_cas"
  171. + [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
  172. + (unspec_volatile:SI
  173. + [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
  174. + (match_operand:SI 2 "arith_operand" "rI08")
  175. + (match_operand:SI 3 "arith_operand" "rI08")]
  176. + UNSPECV_CMPXCHG_1))]
  177. + "TARGET_ATOMIC_HARD_CAS"
  178. +{FAIL;}
  179. +)
  180. +
  181. +(define_expand "atomic_compare_and_swaphi_cas"
  182. + [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
  183. + (unspec_volatile:SI
  184. + [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
  185. + (match_operand:SI 2 "arith_operand" "rI08")
  186. + (match_operand:SI 3 "arith_operand" "rI08")]
  187. + UNSPECV_CMPXCHG_1))]
  188. + "TARGET_ATOMIC_HARD_CAS"
  189. +{FAIL;}
  190. +)
  191. +
  192. ;; The QIHImode llcs patterns modify the address register of the memory
  193. ;; operand. In order to express that, we have to open code the memory
  194. ;; operand. Initially the insn is expanded like every other atomic insn
  195. diff -Nur gcc-6.2.0.orig/gcc/config/sh/t-sh gcc-6.2.0/gcc/config/sh/t-sh
  196. --- gcc-6.2.0.orig/gcc/config/sh/t-sh 2016-01-04 15:30:50.000000000 +0100
  197. +++ gcc-6.2.0/gcc/config/sh/t-sh 2016-12-10 19:58:58.649784537 +0100
  198. @@ -52,7 +52,7 @@
  199. m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
  200. m4,m4-100,m4-200,m4-300,m4a \
  201. m5-32media,m5-compact,m5-32media \
  202. - m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
  203. + m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \
  204. subst= ; \
  205. for lib in `echo $$abi|tr , ' '` ; do \
  206. if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
  207. @@ -65,9 +65,9 @@
  208. # SH1 and SH2A support big endian only.
  209. ifeq ($(DEFAULT_ENDIAN),ml)
  210. -MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  211. +MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  212. else
  213. -MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  214. +MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  215. endif
  216. MULTILIB_OSDIRNAMES = \
  217. @@ -96,6 +96,7 @@
  218. m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
  219. m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
  220. m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
  221. + mj2=!j2
  222. $(out_object_file): gt-sh.h
  223. gt-sh.h : s-gtype ; @true
  224. diff -Nur gcc-6.2.0.orig/gcc/config.gcc gcc-6.2.0/gcc/config.gcc
  225. --- gcc-6.2.0.orig/gcc/config.gcc 2016-06-08 15:34:25.000000000 +0200
  226. +++ gcc-6.2.0/gcc/config.gcc 2016-12-10 19:58:58.641785064 +0100
  227. @@ -471,7 +471,7 @@
  228. extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
  229. ;;
  230. # Note the 'l'; we need to be able to match e.g. "shle" or "shl".
  231. -sh[123456789lbe]*-*-* | sh-*-*)
  232. +sh[123456789lbej]*-*-* | sh-*-*)
  233. cpu_type=sh
  234. extra_options="${extra_options} fused-madd.opt"
  235. extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
  236. @@ -2613,19 +2613,19 @@
  237. extra_options="${extra_options} s390/tpf.opt"
  238. tmake_file="${tmake_file} s390/t-s390"
  239. ;;
  240. -sh-*-elf* | sh[12346l]*-*-elf* | \
  241. - sh-*-linux* | sh[2346lbe]*-*-linux* | \
  242. +sh-*-elf* | sh[12346lj]*-*-elf* | \
  243. + sh-*-linux* | sh[2346lbej]*-*-linux* | \
  244. sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
  245. sh64-*-netbsd* | sh64l*-*-netbsd*)
  246. tmake_file="${tmake_file} sh/t-sh sh/t-elf"
  247. if test x${with_endian} = x; then
  248. case ${target} in
  249. - sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
  250. + sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
  251. shbe-*-* | sheb-*-*) with_endian=big,little ;;
  252. sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
  253. shl* | sh64l* | sh*-*-linux* | \
  254. sh5l* | sh-superh-elf) with_endian=little,big ;;
  255. - sh[1234]*-*-*) with_endian=big ;;
  256. + sh[j1234]*-*-*) with_endian=big ;;
  257. *) with_endian=big,little ;;
  258. esac
  259. fi
  260. @@ -2715,6 +2715,7 @@
  261. sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
  262. sh2a*) sh_cpu_target=sh2a ;;
  263. sh2e*) sh_cpu_target=sh2e ;;
  264. + shj2*) sh_cpu_target=shj2;;
  265. sh2*) sh_cpu_target=sh2 ;;
  266. *) sh_cpu_target=sh1 ;;
  267. esac
  268. @@ -2739,7 +2740,7 @@
  269. sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
  270. sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
  271. sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
  272. - sh3e | sh3 | sh2e | sh2 | sh1) ;;
  273. + sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
  274. "") sh_cpu_default=${sh_cpu_target} ;;
  275. *) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
  276. esac
  277. @@ -2750,9 +2751,9 @@
  278. sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
  279. sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
  280. sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
  281. - sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
  282. + sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
  283. sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
  284. - *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
  285. + *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
  286. esac
  287. if test x$with_fp = xno; then
  288. sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
  289. @@ -2770,7 +2771,8 @@
  290. m2a | m2a-single | m2a-single-only | m2a-nofpu | \
  291. m5-64media | m5-64media-nofpu | \
  292. m5-32media | m5-32media-nofpu | \
  293. - m5-compact | m5-compact-nofpu)
  294. + m5-compact | m5-compact-nofpu | \
  295. + mj2)
  296. # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
  297. # It is passed to MULTIILIB_OPTIONS verbatim.
  298. TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
  299. @@ -2787,7 +2789,7 @@
  300. done
  301. TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
  302. if test x${enable_incomplete_targets} = xyes ; then
  303. - tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
  304. + tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1"
  305. fi
  306. tm_file="$tm_file ./sysroot-suffix.h"
  307. tmake_file="$tmake_file t-sysroot-suffix"
  308. @@ -4268,6 +4270,8 @@
  309. ;;
  310. m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
  311. ;;
  312. + mj2)
  313. + ;;
  314. *)
  315. echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
  316. echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
  317. @@ -4477,7 +4481,7 @@
  318. tmake_file="rs6000/t-rs6000 ${tmake_file}"
  319. ;;
  320. - sh[123456ble]*-*-* | sh-*-*)
  321. + sh[123456blej]*-*-* | sh-*-*)
  322. c_target_objs="${c_target_objs} sh-c.o"
  323. cxx_target_objs="${cxx_target_objs} sh-c.o"
  324. ;;