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0001-openwrt-ath79.patch 1.2 MB

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  1. diff -Nur linux-4.1.43.orig/arch/mips/Kconfig linux-4.1.43/arch/mips/Kconfig
  2. --- linux-4.1.43.orig/arch/mips/Kconfig 2017-08-06 01:56:14.000000000 +0200
  3. +++ linux-4.1.43/arch/mips/Kconfig 2017-08-06 20:02:15.000000000 +0200
  4. @@ -1071,6 +1071,9 @@
  5. config MIPS_NILE4
  6. bool
  7. +config MYLOADER
  8. + bool
  9. +
  10. config SYNC_R4K
  11. bool
  12. diff -Nur linux-4.1.43.orig/arch/mips/Makefile linux-4.1.43/arch/mips/Makefile
  13. --- linux-4.1.43.orig/arch/mips/Makefile 2017-08-06 01:56:14.000000000 +0200
  14. +++ linux-4.1.43/arch/mips/Makefile 2017-08-06 20:02:15.000000000 +0200
  15. @@ -216,6 +216,7 @@
  16. #
  17. libs-$(CONFIG_FW_ARC) += arch/mips/fw/arc/
  18. libs-$(CONFIG_FW_CFE) += arch/mips/fw/cfe/
  19. +libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
  20. libs-$(CONFIG_FW_SNIPROM) += arch/mips/fw/sni/
  21. libs-y += arch/mips/fw/lib/
  22. diff -Nur linux-4.1.43.orig/arch/mips/ath79/Kconfig linux-4.1.43/arch/mips/ath79/Kconfig
  23. --- linux-4.1.43.orig/arch/mips/ath79/Kconfig 2017-08-06 01:56:14.000000000 +0200
  24. +++ linux-4.1.43/arch/mips/ath79/Kconfig 2017-08-06 20:02:15.000000000 +0200
  25. @@ -2,75 +2,1466 @@
  26. menu "Atheros AR71XX/AR724X/AR913X machine selection"
  27. +config ATH79_MACH_ALFA_AP96
  28. + bool "ALFA Network AP96 board support"
  29. + select SOC_AR71XX
  30. + select ATH79_DEV_ETH
  31. + select ATH79_DEV_GPIO_BUTTONS
  32. + select ATH79_DEV_M25P80
  33. + select ATH79_DEV_USB
  34. +
  35. +config ATH79_MACH_HORNET_UB
  36. + bool "ALFA Network Hornet-UB board support"
  37. + select SOC_AR933X
  38. + select ATH79_DEV_ETH
  39. + select ATH79_DEV_GPIO_BUTTONS
  40. + select ATH79_DEV_LEDS_GPIO
  41. + select ATH79_DEV_M25P80
  42. + select ATH79_DEV_USB
  43. + select ATH79_DEV_WMAC
  44. +
  45. +config ATH79_MACH_ALFA_NX
  46. + bool "ALFA Network N2/N5 board support"
  47. + select SOC_AR724X
  48. + select ATH79_DEV_AP9X_PCI if PCI
  49. + select ATH79_DEV_ETH
  50. + select ATH79_DEV_GPIO_BUTTONS
  51. + select ATH79_DEV_LEDS_GPIO
  52. + select ATH79_DEV_M25P80
  53. +
  54. +config ATH79_MACH_TUBE2H
  55. + bool "ALFA Network Tube2H board support"
  56. + select SOC_AR933X
  57. + select ATH79_DEV_ETH
  58. + select ATH79_DEV_GPIO_BUTTONS
  59. + select ATH79_DEV_LEDS_GPIO
  60. + select ATH79_DEV_M25P80
  61. + select ATH79_DEV_WMAC
  62. +
  63. +config ATH79_MACH_ALL0258N
  64. + bool "Allnet ALL0258N support"
  65. + select SOC_AR724X
  66. + select ATH79_DEV_AP9X_PCI if PCI
  67. + select ATH79_DEV_ETH
  68. + select ATH79_DEV_GPIO_BUTTONS
  69. + select ATH79_DEV_LEDS_GPIO
  70. + select ATH79_DEV_M25P80
  71. +
  72. +config ATH79_MACH_ALL0315N
  73. + bool "Allnet ALL0315N support"
  74. + select SOC_AR724X
  75. + select ATH79_DEV_AP9X_PCI if PCI
  76. + select ATH79_DEV_ETH
  77. + select ATH79_DEV_GPIO_BUTTONS
  78. + select ATH79_DEV_LEDS_GPIO
  79. + select ATH79_DEV_M25P80
  80. +
  81. +config ATH79_MACH_ANTMINER_S1
  82. + bool "Bitmain Antminer S1 support"
  83. + select SOC_AR933X
  84. + select ATH79_DEV_ETH
  85. + select ATH79_DEV_GPIO_BUTTONS
  86. + select ATH79_DEV_LEDS_GPIO
  87. + select ATH79_DEV_M25P80
  88. + select ATH79_DEV_USB
  89. + select ATH79_DEV_WMAC
  90. +
  91. +config ATH79_MACH_ANTMINER_S3
  92. + bool "Bitmain Antminer S3 support"
  93. + select SOC_AR933X
  94. + select ATH79_DEV_ETH
  95. + select ATH79_DEV_GPIO_BUTTONS
  96. + select ATH79_DEV_LEDS_GPIO
  97. + select ATH79_DEV_M25P80
  98. + select ATH79_DEV_USB
  99. + select ATH79_DEV_WMAC
  100. +
  101. +config ATH79_MACH_ARDUINO_YUN
  102. + bool "Arduino Yun"
  103. + select SOC_AR933X
  104. + select ATH79_DEV_ETH
  105. + select ATH79_DEV_GPIO_BUTTONS
  106. + select ATH79_DEV_LEDS_GPIO
  107. + select ATH79_DEV_M25P80
  108. + select ATH79_DEV_USB
  109. + select ATH79_DEV_WMAC
  110. + help
  111. + Say 'Y' here if you want your kernel to support the
  112. + Arduino Yun.
  113. +
  114. +config ATH79_MACH_AP113
  115. + bool "Atheros AP113 board support"
  116. + select SOC_AR724X
  117. + select ATH79_DEV_M25P80
  118. + select ATH79_DEV_PB9X_PCI if PCI
  119. + select ATH79_DEV_GPIO_BUTTONS
  120. + select ATH79_DEV_LEDS_GPIO
  121. + select ATH79_DEV_USB
  122. + select ATH79_DEV_ETH
  123. +
  124. config ATH79_MACH_AP121
  125. bool "Atheros AP121 reference board"
  126. select SOC_AR933X
  127. + select ATH79_DEV_ETH
  128. + select ATH79_DEV_GPIO_BUTTONS
  129. + select ATH79_DEV_LEDS_GPIO
  130. + select ATH79_DEV_M25P80
  131. + select ATH79_DEV_USB
  132. + select ATH79_DEV_WMAC
  133. + help
  134. + Say 'Y' here if you want your kernel to support the
  135. + Atheros AP121 reference board.
  136. +
  137. +config ATH79_MACH_AP132
  138. + bool "Atheros AP132 reference board"
  139. + select SOC_QCA955X
  140. + select ATH79_DEV_GPIO_BUTTONS
  141. + select ATH79_DEV_LEDS_GPIO
  142. + select ATH79_DEV_M25P80
  143. + select ATH79_DEV_USB
  144. + select ATH79_DEV_WMAC
  145. + help
  146. + Say 'Y' here if you want your kernel to support the
  147. + Atheros AP132 reference boards.
  148. +
  149. +config ATH79_MACH_AP136
  150. + bool "Atheros AP136/AP135 reference board"
  151. + select SOC_QCA955X
  152. + select ATH79_DEV_GPIO_BUTTONS
  153. + select ATH79_DEV_LEDS_GPIO
  154. + select ATH79_DEV_NFC
  155. + select ATH79_DEV_M25P80
  156. + select ATH79_DEV_USB
  157. + select ATH79_DEV_WMAC
  158. + help
  159. + Say 'Y' here if you want your kernel to support the
  160. + Atheros AP136 or AP135 reference boards.
  161. +
  162. +config ATH79_MACH_AP143
  163. + bool "Atheros AP143 reference board"
  164. + select SOC_QCA953X
  165. + select ATH79_DEV_GPIO_BUTTONS
  166. + select ATH79_DEV_LEDS_GPIO
  167. + select ATH79_DEV_SPI
  168. + select ATH79_DEV_USB
  169. + select ATH79_DEV_WMAC
  170. + select ATH79_DEV_ETH
  171. + select ATH79_DEV_M25P80
  172. + help
  173. + Say 'Y' here if you want your kernel to support the
  174. + Atheros AP143 reference board.
  175. +
  176. +config ATH79_MACH_AP147
  177. + bool "Atheros AP147 reference board"
  178. + select SOC_QCA953X
  179. + select ATH79_DEV_GPIO_BUTTONS
  180. + select ATH79_DEV_LEDS_GPIO
  181. + select ATH79_DEV_M25P80
  182. + select ATH79_DEV_USB
  183. + select ATH79_DEV_WMAC
  184. + select ATH79_DEV_AP9X_PCI if PCI
  185. + help
  186. + Say 'Y' here if you want your kernel to support the
  187. + QCA AP147 reference boards.
  188. +
  189. +config ATH79_MACH_AP152
  190. + bool "Atheros AP152 reference board"
  191. + select SOC_QCA956X
  192. + select ATH79_DEV_GPIO_BUTTONS
  193. + select ATH79_DEV_LEDS_GPIO
  194. + select ATH79_DEV_M25P80
  195. + select ATH79_DEV_USB
  196. + select ATH79_DEV_WMAC
  197. + select ATH79_DEV_AP9X_PCI if PCI
  198. + help
  199. + Say 'Y' here if you want your kernel to support the
  200. + QCA AP152 reference boards.
  201. +
  202. +
  203. +config ATH79_MACH_AP81
  204. + bool "Atheros AP81 reference board"
  205. + select SOC_AR913X
  206. + select ATH79_DEV_ETH
  207. + select ATH79_DEV_GPIO_BUTTONS
  208. + select ATH79_DEV_LEDS_GPIO
  209. + select ATH79_DEV_M25P80
  210. + select ATH79_DEV_USB
  211. + select ATH79_DEV_WMAC
  212. + help
  213. + Say 'Y' here if you want your kernel to support the
  214. + Atheros AP81 reference board.
  215. +
  216. +config ATH79_MACH_AP83
  217. + bool "Atheros AP83 board support"
  218. + select SOC_AR913X
  219. + select ATH79_DEV_GPIO_BUTTONS
  220. + select ATH79_DEV_LEDS_GPIO
  221. + select ATH79_DEV_USB
  222. + select ATH79_DEV_WMAC
  223. +
  224. +config ATH79_MACH_AP96
  225. + bool "Atheros AP96 board support"
  226. + select SOC_AR71XX
  227. + select ATH79_DEV_AP9X_PCI if PCI
  228. + select ATH79_DEV_ETH
  229. + select ATH79_DEV_GPIO_BUTTONS
  230. + select ATH79_DEV_LEDS_GPIO
  231. + select ATH79_DEV_M25P80
  232. + select ATH79_DEV_USB
  233. +
  234. +config ATH79_MACH_DB120
  235. + bool "Atheros DB120 reference board"
  236. + select SOC_AR934X
  237. + select ATH79_DEV_AP9X_PCI if PCI
  238. + select ATH79_DEV_ETH
  239. + select ATH79_DEV_GPIO_BUTTONS
  240. + select ATH79_DEV_LEDS_GPIO
  241. + select ATH79_DEV_M25P80
  242. + select ATH79_DEV_NFC
  243. + select ATH79_DEV_USB
  244. + select ATH79_DEV_WMAC
  245. + help
  246. + Say 'Y' here if you want your kernel to support the
  247. + Atheros DB120 reference board.
  248. +
  249. +config ATH79_MACH_PB42
  250. + bool "Atheros PB42 board support"
  251. + select SOC_AR71XX
  252. + select ATH79_DEV_ETH
  253. + select ATH79_DEV_GPIO_BUTTONS
  254. + select ATH79_DEV_M25P80
  255. +
  256. +config ATH79_MACH_PB44
  257. + bool "Atheros PB44 reference board"
  258. + select SOC_AR71XX
  259. + select ATH79_DEV_ETH
  260. + select ATH79_DEV_GPIO_BUTTONS
  261. + select ATH79_DEV_LEDS_GPIO
  262. + select ATH79_DEV_SPI
  263. + select ATH79_DEV_USB
  264. + help
  265. + Say 'Y' here if you want your kernel to support the
  266. + Atheros PB44 reference board.
  267. +
  268. +config ATH79_MACH_PB92
  269. + bool "Atheros PB92 board support"
  270. + select SOC_AR724X
  271. + select ATH79_DEV_ETH
  272. + select ATH79_DEV_GPIO_BUTTONS
  273. + select ATH79_DEV_LEDS_GPIO
  274. + select ATH79_DEV_PB9X_PCI if PCI
  275. + select ATH79_DEV_USB
  276. +
  277. +config ATH79_MACH_AW_NR580
  278. + bool "AzureWave AW-NR580 board support"
  279. + select SOC_AR71XX
  280. + select ATH79_DEV_ETH
  281. + select ATH79_DEV_GPIO_BUTTONS
  282. + select ATH79_DEV_LEDS_GPIO
  283. + select ATH79_DEV_M25P80
  284. +
  285. +config ATH79_MACH_F9K1115V2
  286. + bool "Belkin AC1750DB board support"
  287. + select SOC_QCA955X
  288. + select ATH79_DEV_ETH
  289. + select ATH79_DEV_GPIO_BUTTONS
  290. + select ATH79_DEV_LEDS_GPIO
  291. + select ATH79_DEV_M25P80
  292. + select ATH79_DEV_USB
  293. + select ATH79_DEV_WMAC
  294. +
  295. +config ATH79_MACH_EPG5000
  296. + bool "EnGenius EPG5000 board support"
  297. + select SOC_QCA955X
  298. + select ATH79_DEV_ETH
  299. + select ATH79_DEV_GPIO_BUTTONS
  300. + select ATH79_DEV_LEDS_GPIO
  301. + select ATH79_DEV_M25P80
  302. + select ATH79_DEV_USB
  303. + select ATH79_DEV_WMAC
  304. + select ATH79_NVRAM
  305. +
  306. +config ATH79_MACH_ESR1750
  307. + bool "EnGenius ESR1750 board support"
  308. + select SOC_QCA955X
  309. + select ATH79_DEV_ETH
  310. + select ATH79_DEV_GPIO_BUTTONS
  311. + select ATH79_DEV_LEDS_GPIO
  312. + select ATH79_DEV_M25P80
  313. + select ATH79_DEV_USB
  314. + select ATH79_DEV_WMAC
  315. +
  316. +config ATH79_MACH_WHR_HP_G300N
  317. + bool "Buffalo WHR-HP-G300N board support"
  318. + select SOC_AR724X
  319. + select ATH79_DEV_AP9X_PCI if PCI
  320. + select ATH79_DEV_ETH
  321. + select ATH79_DEV_GPIO_BUTTONS
  322. + select ATH79_DEV_LEDS_GPIO
  323. + select ATH79_DEV_M25P80
  324. +
  325. +config ATH79_MACH_WLAE_AG300N
  326. + bool "Buffalo WLAE-AG300N board support"
  327. + select SOC_AR71XX
  328. + select ATH79_DEV_ETH
  329. + select ATH79_DEV_GPIO_BUTTONS
  330. + select ATH79_DEV_LEDS_GPIO
  331. + select ATH79_DEV_M25P80
  332. +
  333. +config ATH79_MACH_WLR8100
  334. + bool "Sitecom WLR-8100 board support"
  335. + select SOC_QCA955X
  336. + select ATH79_DEV_ETH
  337. + select ATH79_DEV_GPIO_BUTTONS
  338. + select ATH79_DEV_LEDS_GPIO
  339. + select ATH79_DEV_M25P80
  340. + select ATH79_DEV_USB
  341. + select ATH79_DEV_WMAC
  342. +
  343. +config ATH79_MACH_WZR_HP_AG300H
  344. + bool "Buffalo WZR-HP-AG300H board support"
  345. + select SOC_AR71XX
  346. + select ATH79_DEV_AP9X_PCI if PCI
  347. + select ATH79_DEV_ETH
  348. + select ATH79_DEV_GPIO_BUTTONS
  349. + select ATH79_DEV_LEDS_GPIO
  350. + select ATH79_DEV_M25P80
  351. + select ATH79_DEV_USB
  352. +
  353. +config ATH79_MACH_WZR_HP_G300NH
  354. + bool "Buffalo WZR-HP-G300NH board support"
  355. + select SOC_AR913X
  356. + select ATH79_DEV_ETH
  357. + select ATH79_DEV_GPIO_BUTTONS
  358. + select ATH79_DEV_LEDS_GPIO
  359. + select ATH79_DEV_USB
  360. + select ATH79_DEV_WMAC
  361. + select RTL8366_SMI
  362. +
  363. +config ATH79_MACH_WZR_HP_G300NH2
  364. + bool "Buffalo WZR-HP-G300NH2 board support"
  365. + select SOC_AR724X
  366. + select ATH79_DEV_AP9X_PCI if PCI
  367. + select ATH79_DEV_ETH
  368. + select ATH79_DEV_GPIO_BUTTONS
  369. + select ATH79_DEV_LEDS_GPIO
  370. + select ATH79_DEV_M25P80
  371. + select ATH79_DEV_USB
  372. +
  373. +config ATH79_MACH_WZR_HP_G450H
  374. + bool "Buffalo WZR-HP-G450H board support"
  375. + select SOC_AR724X
  376. + select ATH79_DEV_ETH
  377. + select ATH79_DEV_AP9X_PCI if PCI
  378. + select ATH79_DEV_GPIO_BUTTONS
  379. + select ATH79_DEV_LEDS_GPIO
  380. + select ATH79_DEV_M25P80
  381. + select ATH79_DEV_USB
  382. +
  383. +config ATH79_MACH_WZR_450HP2
  384. + bool "Buffalo WZR-450HP2 board support"
  385. + select SOC_QCA955X
  386. + select ATH79_DEV_ETH
  387. + select ATH79_DEV_GPIO_BUTTONS
  388. + select ATH79_DEV_LEDS_GPIO
  389. + select ATH79_DEV_M25P80
  390. + select ATH79_DEV_USB
  391. + select ATH79_DEV_WMAC
  392. +
  393. +config ATH79_MACH_WP543
  394. + bool "Compex WP543/WPJ543 board support"
  395. + select SOC_AR71XX
  396. + select ATH79_DEV_ETH
  397. + select ATH79_DEV_GPIO_BUTTONS
  398. + select ATH79_DEV_LEDS_GPIO
  399. + select ATH79_DEV_M25P80
  400. + select ATH79_DEV_USB
  401. + select MYLOADER
  402. +
  403. +config ATH79_MACH_WPE72
  404. + bool "Compex WPE72/WPE72NX board support"
  405. + select SOC_AR724X
  406. + select ATH79_DEV_ETH
  407. + select ATH79_DEV_GPIO_BUTTONS
  408. + select ATH79_DEV_LEDS_GPIO
  409. + select ATH79_DEV_M25P80
  410. + select ATH79_DEV_USB
  411. + select MYLOADER
  412. +
  413. +config ATH79_MACH_WPJ344
  414. + bool "Compex WPJ344 board support"
  415. + select SOC_AS934X
  416. + select ATH79_DEV_ETH
  417. + select ATH79_DEV_GPIO_BUTTONS
  418. + select ATH79_DEV_LEDS_GPIO
  419. + select ATH79_DEV_M25P80
  420. + select ATH79_DEV_USB
  421. + select ATH79_DEV_WMAC
  422. +
  423. +config ATH79_MACH_WPJ531
  424. + bool "Compex WPJ531 board support"
  425. + select SOC_QCA953X
  426. + select ATH79_DEV_ETH
  427. + select ATH79_DEV_GPIO_BUTTONS
  428. + select ATH79_DEV_LEDS_GPIO
  429. + select ATH79_DEV_M25P80
  430. + select ATH79_DEV_USB
  431. + select ATH79_DEV_WMAC
  432. +
  433. +config ATH79_MACH_WPJ558
  434. + bool "Compex WPJ558 board support"
  435. + select SOC_QCA955X
  436. + select ATH79_DEV_ETH
  437. + select ATH79_DEV_GPIO_BUTTONS
  438. + select ATH79_DEV_LEDS_GPIO
  439. + select ATH79_DEV_M25P80
  440. + select ATH79_DEV_USB
  441. + select ATH79_DEV_WMAC
  442. +
  443. +config ATH79_MACH_DGL_5500_A1
  444. + bool "D-Link DGL-5500 A1 support"
  445. + select SOC_QCA955X
  446. + select ATH79_DEV_ETH
  447. + select ATH79_DEV_GPIO_BUTTONS
  448. + select ATH79_DEV_LEDS_GPIO
  449. + select ATH79_DEV_M25P80
  450. + select ATH79_DEV_WMAC
  451. + select ATH79_DEV_USB
  452. +
  453. +config ATH79_MACH_DHP_1565_A1
  454. + bool "D-Link DHP-1565 rev. A1 board support"
  455. + select SOC_AR934X
  456. + select ATH79_DEV_AP9X_PCI if PCI
  457. + select ATH79_DEV_ETH
  458. + select ATH79_DEV_GPIO_BUTTONS
  459. + select ATH79_DEV_LEDS_GPIO
  460. + select ATH79_DEV_M25P80
  461. + select ATH79_DEV_USB
  462. + select ATH79_DEV_WMAC
  463. +
  464. +config ATH79_MACH_DIR_505_A1
  465. + bool "D-Link DIR-505-A1 support"
  466. + select SOC_AR933X
  467. + select ATH79_DEV_ETH
  468. + select ATH79_DEV_GPIO_BUTTONS
  469. + select ATH79_DEV_LEDS_GPIO
  470. + select ATH79_DEV_M25P80
  471. + select ATH79_DEV_WMAC
  472. + select ATH79_NVRAM
  473. +
  474. +config ATH79_MACH_DIR_600_A1
  475. + bool "D-Link DIR-600 A1/DIR-615 E1/DIR-615 E4 support"
  476. + select SOC_AR724X
  477. + select ATH79_DEV_AP9X_PCI if PCI
  478. + select ATH79_DEV_ETH
  479. + select ATH79_DEV_GPIO_BUTTONS
  480. + select ATH79_DEV_LEDS_GPIO
  481. + select ATH79_DEV_M25P80
  482. + select ATH79_NVRAM
  483. +
  484. +config ATH79_MACH_DIR_615_C1
  485. + bool "D-Link DIR-615 rev. C1 support"
  486. + select SOC_AR913X
  487. + select ATH79_DEV_ETH
  488. + select ATH79_DEV_GPIO_BUTTONS
  489. + select ATH79_DEV_LEDS_GPIO
  490. + select ATH79_DEV_M25P80
  491. + select ATH79_DEV_WMAC
  492. + select ATH79_NVRAM
  493. +
  494. +config ATH79_MACH_DIR_615_I1
  495. + bool "D-Link DIR-615 rev. I1 support"
  496. + select SOC_AR934X
  497. + select ATH79_DEV_AP9X_PCI if PCI
  498. + select ATH79_DEV_ETH
  499. + select ATH79_DEV_GPIO_BUTTONS
  500. + select ATH79_DEV_LEDS_GPIO
  501. + select ATH79_DEV_M25P80
  502. + select ATH79_DEV_WMAC
  503. + select ATH79_NVRAM
  504. +
  505. +config ATH79_MACH_DIR_825_B1
  506. + bool "D-Link DIR-825 rev. B1 board support"
  507. + select SOC_AR71XX
  508. + select ATH79_DEV_AP9X_PCI if PCI
  509. + select ATH79_DEV_ETH
  510. + select ATH79_DEV_GPIO_BUTTONS
  511. + select ATH79_DEV_LEDS_GPIO
  512. + select ATH79_DEV_M25P80
  513. + select ATH79_DEV_USB
  514. +
  515. +config ATH79_MACH_DIR_825_C1
  516. + bool "D-Link DIR-825 rev. C1/DIR-835 rev. A1 board support"
  517. + select SOC_AR934X
  518. + select ATH79_DEV_AP9X_PCI if PCI
  519. + select ATH79_DEV_ETH
  520. + select ATH79_DEV_GPIO_BUTTONS
  521. + select ATH79_DEV_LEDS_GPIO
  522. + select ATH79_DEV_M25P80
  523. + select ATH79_DEV_USB
  524. + select ATH79_DEV_WMAC
  525. +
  526. +config ATH79_MACH_DLAN_HOTSPOT
  527. + bool "devolo dLAN Hotspot support"
  528. + select SOC_AR933X
  529. + select ATH79_DEV_ETH
  530. + select ATH79_DEV_GPIO_BUTTONS
  531. + select ATH79_DEV_LEDS_GPIO
  532. + select ATH79_DEV_M25P80
  533. + select ATH79_DEV_WMAC
  534. +
  535. +config ATH79_MACH_DLAN_PRO_500_WP
  536. + bool "devolo dLAN pro 500 Wireless+ support"
  537. + select SOC_AR934X
  538. + select ATH79_DEV_ETH
  539. + select ATH79_DEV_GPIO_BUTTONS
  540. + select ATH79_DEV_LEDS_GPIO
  541. + select ATH79_DEV_SPI
  542. + select ATH79_DEV_M25P80
  543. + select ATH79_DEV_WMAC
  544. + select ATH79_DEV_USB
  545. +
  546. +config ATH79_MACH_DLAN_PRO_1200_AC
  547. + bool "devolo dLAN pro 1200+ WiFi ac support"
  548. + select SOC_AR934X
  549. + select ATH79_DEV_AP9X_PCI if PCI
  550. + select ATH79_DEV_ETH
  551. + select ATH79_DEV_GPIO_BUTTONS
  552. + select ATH79_DEV_LEDS_GPIO
  553. + select ATH79_DEV_SPI
  554. + select ATH79_DEV_M25P80
  555. + select ATH79_DEV_WMAC
  556. + select ATH79_DEV_NFC
  557. + select ATH79_DEV_USB
  558. +
  559. +config ATH79_MACH_DRAGINO2
  560. + bool "DRAGINO V2 support"
  561. + select SOC_AR933X
  562. + select ATH79_DEV_M25P80
  563. + select ATH79_DEV_GPIO_BUTTONS
  564. + select ATH79_DEV_LEDS_GPIO
  565. + select ATH79_DEV_WMAC
  566. + select ATH79_DEV_ETH
  567. + select ATH79_DEV_USB
  568. +
  569. +config ATH79_MACH_ESR900
  570. + bool "EnGenius ESR900 board support"
  571. + select SOC_QCA955X
  572. + select ATH79_DEV_ETH
  573. + select ATH79_DEV_GPIO_BUTTONS
  574. + select ATH79_DEV_LEDS_GPIO
  575. + select ATH79_DEV_M25P80
  576. + select ATH79_DEV_USB
  577. + select ATH79_DEV_WMAC
  578. +
  579. +config ATH79_MACH_EW_DORIN
  580. + bool "embedded wireless Dorin Platform support"
  581. + select SOC_AR933X
  582. + select ATH79_DEV_M25P80
  583. + select ATH79_DEV_GPIO_BUTTONS
  584. + select ATH79_DEV_LEDS_GPIO
  585. + select ATH79_DEV_WMAC
  586. + select ATH79_DEV_ETH
  587. + help
  588. + Say 'Y' here if you want your kernel to support the
  589. + Dorin Platform from www.80211.de .
  590. +
  591. +config ATH79_MACH_EL_M150
  592. + bool "EasyLink EL-M150 support"
  593. + select SOC_AR933X
  594. + select ATH79_DEV_ETH
  595. + select ATH79_DEV_GPIO_BUTTONS
  596. + select ATH79_DEV_LEDS_GPIO
  597. + select ATH79_DEV_M25P80
  598. + select ATH79_DEV_USB
  599. + select ATH79_DEV_WMAC
  600. +
  601. +config ATH79_MACH_EL_MINI
  602. + bool "EasyLink EL-MINI support"
  603. + select SOC_AR933X
  604. + select ATH79_DEV_ETH
  605. + select ATH79_DEV_GPIO_BUTTONS
  606. + select ATH79_DEV_LEDS_GPIO
  607. + select ATH79_DEV_M25P80
  608. + select ATH79_DEV_USB
  609. + select ATH79_DEV_WMAC
  610. +
  611. +config ATH79_MACH_GL_AR150
  612. + bool "GL AR150 support"
  613. + select SOC_AR933X
  614. + select ATH79_DEV_ETH
  615. + select ATH79_DEV_GPIO_BUTTONS
  616. + select ATH79_DEV_LEDS_GPIO
  617. + select ATH79_DEV_M25P80
  618. + select ATH79_DEV_USB
  619. + select ATH79_DEV_WMAC
  620. +
  621. +config ATH79_MACH_GL_AR300
  622. + bool "GL_AR300 support"
  623. + select SOC_AR934X
  624. + select ATH79_DEV_ETH
  625. + select ATH79_DEV_GPIO_BUTTONS
  626. + select ATH79_DEV_LEDS_GPIO
  627. + select ATH79_DEV_M25P80
  628. + select ATH79_DEV_USB
  629. + select ATH79_DEV_WMAC
  630. +
  631. +config ATH79_MACH_GL_DOMINO
  632. + bool "DOMINO support"
  633. + select SOC_AR933X
  634. + select ATH79_DEV_ETH
  635. + select ATH79_DEV_GPIO_BUTTONS
  636. + select ATH79_DEV_LEDS_GPIO
  637. + select ATH79_DEV_M25P80
  638. + select ATH79_DEV_USB
  639. + select ATH79_DEV_WMAC
  640. +
  641. +config ATH79_MACH_GL_INET
  642. + bool "GL-INET support"
  643. + select SOC_AR933X
  644. + select ATH79_DEV_ETH
  645. + select ATH79_DEV_GPIO_BUTTONS
  646. + select ATH79_DEV_LEDS_GPIO
  647. + select ATH79_DEV_M25P80
  648. + select ATH79_DEV_USB
  649. + select ATH79_DEV_WMAC
  650. +
  651. +config ATH79_MACH_EAP300V2
  652. + bool "EnGenius EAP300 v2 support"
  653. + select SOC_AR934X
  654. + select ATH79_DEV_ETH
  655. + select ATH79_DEV_GPIO_BUTTONS
  656. + select ATH79_DEV_LEDS_GPIO
  657. + select ATH79_DEV_M25P80
  658. + select ATH79_DEV_WMAC
  659. +
  660. +config ATH79_MACH_GS_MINIBOX_V1
  661. + bool "Gainstrong MiniBox V1.0 support"
  662. + select SOC_AR933X
  663. + select ARH79_DEV_ETH
  664. + select ARH79_DEV_GPIO_BUTTONS
  665. + select ATH79_DEV_LEDS_GPIO
  666. + select ATH79_DEV_M25P80
  667. + select ATH79_DEV_USB
  668. + select ATH79_DEV_WMAC
  669. +
  670. +config ATH79_MACH_GS_OOLITE
  671. + bool "GS Oolite V1 support"
  672. + select SOC_AR933X
  673. + select ARH79_DEV_ETH
  674. + select ARH79_DEV_GPIO_BUTTONS
  675. + select ATH79_DEV_LEDS_GPIO
  676. + select ATH79_DEV_M25P80
  677. + select ATH79_DEV_USB
  678. + select ATH79_DEV_WMAC
  679. +
  680. +config ATH79_MACH_HIWIFI_HC6361
  681. + bool "HiWiFi HC6361 board support"
  682. + select SOC_AR933X
  683. + select ATH79_DEV_ETH
  684. + select ATH79_DEV_GPIO_BUTTONS
  685. + select ATH79_DEV_LEDS_GPIO
  686. + select ATH79_DEV_M25P80
  687. + select ATH79_DEV_USB
  688. + select ATH79_DEV_WMAC
  689. +
  690. +config ATH79_MACH_JA76PF
  691. + bool "jjPlus JA76PF board support"
  692. + select SOC_AR71XX
  693. + select ATH79_DEV_ETH
  694. + select ATH79_DEV_GPIO_BUTTONS
  695. + select ATH79_DEV_LEDS_GPIO
  696. + select ATH79_DEV_M25P80
  697. + select ATH79_DEV_USB
  698. +
  699. +config ATH79_MACH_JWAP003
  700. + bool "jjPlus JWAP003 board support"
  701. + select SOC_AR71XX
  702. + select ATH79_DEV_ETH
  703. + select ATH79_DEV_GPIO_BUTTONS
  704. + select ATH79_DEV_M25P80
  705. + select ATH79_DEV_USB
  706. +
  707. +config ATH79_MACH_WRT160NL
  708. + bool "Linksys WRT160NL board support"
  709. + select SOC_AR913X
  710. + select ATH79_DEV_ETH
  711. + select ATH79_DEV_GPIO_BUTTONS
  712. + select ATH79_DEV_LEDS_GPIO
  713. + select ATH79_DEV_M25P80
  714. + select ATH79_DEV_USB
  715. + select ATH79_DEV_WMAC
  716. + select ATH79_NVRAM
  717. +
  718. +config ATH79_MACH_WRT400N
  719. + bool "Linksys WRT400N board support"
  720. + select SOC_AR71XX
  721. + select ATH79_DEV_AP9X_PCI if PCI
  722. + select ATH79_DEV_ETH
  723. + select ATH79_DEV_GPIO_BUTTONS
  724. + select ATH79_DEV_LEDS_GPIO
  725. + select ATH79_DEV_M25P80
  726. +
  727. +config ATH79_MACH_R6100
  728. + bool "NETGEAR R6100 board support"
  729. + select SOC_AR934X
  730. + select ATH79_DEV_AP9X_PCI if PCI
  731. + select ATH79_DEV_ETH
  732. + select ATH79_DEV_GPIO_BUTTONS
  733. + select ATH79_DEV_LEDS_GPIO
  734. + select ATH79_DEV_NFC
  735. + select ATH79_DEV_USB
  736. + select ATH79_DEV_WMAC
  737. +
  738. +config ATH79_MACH_MC_MAC1200R
  739. + bool "MERCURY MAC1200R board support"
  740. + select SOC_AR934X
  741. + select ATH79_DEV_AP9X_PCI if PCI
  742. + select ATH79_DEV_ETH
  743. + select ATH79_DEV_GPIO_BUTTONS
  744. + select ATH79_DEV_LEDS_GPIO
  745. + select ATH79_DEV_M25P80
  746. + select ATH79_DEV_WMAC
  747. +
  748. +config ATH79_MACH_RB4XX
  749. + bool "MikroTik RouterBOARD 4xx series support"
  750. + select SOC_AR71XX
  751. + select ATH79_DEV_ETH
  752. + select ATH79_DEV_GPIO_BUTTONS
  753. + select ATH79_DEV_LEDS_GPIO
  754. + select ATH79_DEV_USB
  755. +
  756. +config ATH79_MACH_RB750
  757. + bool "MikroTik RouterBOARD 750 support"
  758. + select SOC_AR724X
  759. + select ATH79_DEV_AP9X_PCI if PCI
  760. + select ATH79_DEV_ETH
  761. + select ATH79_DEV_USB
  762. + select ATH79_ROUTERBOOT
  763. +
  764. +config ATH79_MACH_RB91X
  765. + bool "MikroTik RouterBOARD 91X support"
  766. + select SOC_AR934X
  767. + select ATH79_DEV_ETH
  768. + select ATH79_DEV_SPI
  769. + select ATH79_DEV_WMAC
  770. + select ATH79_DEV_USB
  771. + select ATH79_ROUTERBOOT
  772. +
  773. +config ATH79_MACH_RB922
  774. + bool "MikroTik RouterBOARD 922 support"
  775. + select SOC_QCA955X
  776. + select ATH79_DEV_ETH
  777. + select ATH79_DEV_M25P80
  778. + select ATH79_DEV_NFC
  779. + select ATH79_DEV_USB
  780. + select ATH79_ROUTERBOOT
  781. + select RLE_DECOMPRESS
  782. +
  783. +config ATH79_MACH_RB95X
  784. + bool "MikroTik RouterBOARD 95X support"
  785. + select SOC_AR934X
  786. + select ATH79_DEV_ETH
  787. + select ATH79_DEV_NFC
  788. + select ATH79_DEV_WMAC
  789. + select ATH79_DEV_USB
  790. + select ATH79_ROUTERBOOT
  791. +
  792. +config ATH79_MACH_RB2011
  793. + bool "MikroTik RouterBOARD 2011 support"
  794. + select SOC_AR934X
  795. + select ATH79_DEV_ETH
  796. + select ATH79_DEV_M25P80
  797. + select ATH79_DEV_NFC
  798. + select ATH79_DEV_USB
  799. + select ATH79_DEV_WMAC
  800. + select ATH79_ROUTERBOOT
  801. +
  802. +config ATH79_MACH_RBSXTLITE
  803. + bool "MikroTik RouterBOARD SXT Lite"
  804. + select SOC_AR934X
  805. + select ATH79_DEV_ETH
  806. + select ATH79_DEV_NFC
  807. + select ATH79_DEV_WMAC
  808. + select ATH79_ROUTERBOOT
  809. +
  810. +config ATH79_MACH_SMART_300
  811. + bool "NC-LINK SMART-300 board support"
  812. + select SOC_AR934X
  813. + select ATH79_DEV_ETH
  814. + select ATH79_DEV_GPIO_BUTTONS
  815. + select ATH79_DEV_LEDS_GPIO
  816. + select ATH79_DEV_M25P80
  817. + select ATH79_DEV_WMAC
  818. +
  819. +config ATH79_MACH_WNDAP360
  820. + bool "NETGEAR WNDAP360 board support"
  821. + select SOC_AR71XX
  822. + select ATH79_DEV_AP9X_PCI if PCI
  823. + select ATH79_DEV_ETH
  824. + select ATH79_DEV_GPIO_BUTTONS
  825. + select ATH79_DEV_LEDS_GPIO
  826. + select ATH79_DEV_M25P80
  827. +
  828. +config ATH79_MACH_WNDR3700
  829. + bool "NETGEAR WNDR3700 board support"
  830. + select SOC_AR71XX
  831. + select ATH79_DEV_AP9X_PCI if PCI
  832. + select ATH79_DEV_ETH
  833. + select ATH79_DEV_GPIO_BUTTONS
  834. + select ATH79_DEV_LEDS_GPIO
  835. + select ATH79_DEV_M25P80
  836. + select ATH79_DEV_USB
  837. +
  838. +config ATH79_MACH_WNDR4300
  839. + bool "NETGEAR WNDR3700v4/WNDR4300 board support"
  840. + select SOC_AR934X
  841. + select ATH79_DEV_AP9X_PCI if PCI
  842. + select ATH79_DEV_ETH
  843. + select ATH79_DEV_GPIO_BUTTONS
  844. + select ATH79_DEV_LEDS_GPIO
  845. + select ATH79_DEV_NFC
  846. + select ATH79_DEV_USB
  847. + select ATH79_DEV_WMAC
  848. +
  849. +config ATH79_MACH_WNR2000
  850. + bool "NETGEAR WNR2000 board support"
  851. + select SOC_AR913X
  852. + select ATH79_DEV_ETH
  853. + select ATH79_DEV_GPIO_BUTTONS
  854. + select ATH79_DEV_LEDS_GPIO
  855. + select ATH79_DEV_M25P80
  856. + select ATH79_DEV_WMAC
  857. +
  858. +config ATH79_MACH_WNR2000_V3
  859. + bool "NETGEAR WNR2000 V3/WNR612 v2/WNR1000 v2 board support"
  860. + select SOC_AR724X
  861. + select ATH79_DEV_AP9X_PCI if PCI
  862. + select ATH79_DEV_ETH
  863. + select ATH79_DEV_GPIO_BUTTONS
  864. + select ATH79_DEV_LEDS_GPIO
  865. + select ATH79_DEV_M25P80
  866. +
  867. + config ATH79_MACH_WNR2200
  868. + bool "NETGEAR WNR2200 board support"
  869. + select SOC_AR724X
  870. + select ATH79_DEV_AP9X_PCI if PCI
  871. + select ATH79_DEV_ETH
  872. + select ATH79_DEV_GPIO_BUTTONS
  873. + select ATH79_DEV_LEDS_GPIO
  874. + select ATH79_DEV_M25P80
  875. + select ATH79_DEV_USB
  876. +
  877. +config ATH79_MACH_WNR2000_V4
  878. + bool "NETGEAR WNR2000 V4"
  879. + select SOC_AR934X
  880. + select ATH79_DEV_ETH
  881. + select ATH79_DEV_GPIO_BUTTONS
  882. + select ATH79_DEV_LEDS_GPIO
  883. + select ATH79_DEV_M25P80
  884. + select ATH79_DEV_USB
  885. + select ATH79_DEV_WMAC
  886. +
  887. +config ATH79_MACH_OM2P
  888. + bool "OpenMesh OM2P board support"
  889. + select SOC_AR724X
  890. + select SOC_AR933X
  891. + select ATH79_DEV_AP9X_PCI if PCI
  892. + select ATH79_DEV_ETH
  893. + select ATH79_DEV_GPIO_BUTTONS
  894. + select ATH79_DEV_LEDS_GPIO
  895. + select ATH79_DEV_M25P80
  896. + select ATH79_DEV_WMAC
  897. +
  898. +config ATH79_MACH_OM5P
  899. + bool "OpenMesh OM5P board support"
  900. + select SOC_AR934X
  901. + select ATH79_DEV_AP9X_PCI if PCI
  902. + select ATH79_DEV_ETH
  903. + select ATH79_DEV_GPIO_BUTTONS
  904. + select ATH79_DEV_LEDS_GPIO
  905. + select ATH79_DEV_M25P80
  906. + select ATH79_DEV_WMAC
  907. +
  908. +config ATH79_MACH_ONION_OMEGA
  909. + bool "ONION OMEGA support"
  910. + select SOC_AR933X
  911. + select ATH79_DEV_ETH
  912. + select ATH79_DEV_GPIO_BUTTONS
  913. + select ATH79_DEV_LEDS_GPIO
  914. + select ATH79_DEV_M25P80
  915. + select ATH79_DEV_USB
  916. + select ATH79_DEV_WMAC
  917. +
  918. +config ATH79_MACH_MR12
  919. + bool "Meraki MR12 board support"
  920. + select SOC_AR724X
  921. + select ATH79_DEV_AP9X_PCI if PCI
  922. + select ATH79_DEV_ETH
  923. + select ATH79_DEV_GPIO_BUTTONS
  924. + select ATH79_DEV_LEDS_GPIO
  925. + select ATH79_DEV_M25P80
  926. + select ATH79_DEV_WMAC
  927. +
  928. +config ATH79_MACH_MR16
  929. + bool "Meraki MR16 board support"
  930. + select SOC_AR71XX
  931. + select ATH79_DEV_AP9X_PCI if PCI
  932. + select ATH79_DEV_ETH
  933. + select ATH79_DEV_GPIO_BUTTONS
  934. + select ATH79_DEV_LEDS_GPIO
  935. + select ATH79_DEV_M25P80
  936. + select ATH79_DEV_WMAC
  937. +
  938. +config ATH79_MACH_MR600
  939. + bool "OpenMesh MR600 board support"
  940. + select SOC_AR934X
  941. + select ATH79_DEV_AP9X_PCI if PCI
  942. + select ATH79_DEV_ETH
  943. + select ATH79_DEV_GPIO_BUTTONS
  944. + select ATH79_DEV_LEDS_GPIO
  945. + select ATH79_DEV_M25P80
  946. + select ATH79_DEV_WMAC
  947. +
  948. +config ATH79_MACH_MZK_W04NU
  949. + bool "Planex MZK-W04NU board support"
  950. + select SOC_AR913X
  951. + select ATH79_DEV_ETH
  952. + select ATH79_DEV_GPIO_BUTTONS
  953. + select ATH79_DEV_LEDS_GPIO
  954. + select ATH79_DEV_M25P80
  955. + select ATH79_DEV_USB
  956. + select ATH79_DEV_WMAC
  957. +
  958. +config ATH79_MACH_MZK_W300NH
  959. + bool "Planex MZK-W300NH board support"
  960. + select SOC_AR913X
  961. + select ATH79_DEV_ETH
  962. + select ATH79_DEV_GPIO_BUTTONS
  963. + select ATH79_DEV_LEDS_GPIO
  964. + select ATH79_DEV_M25P80
  965. + select ATH79_DEV_WMAC
  966. +
  967. +config ATH79_MACH_RW2458N
  968. + bool "Redwave RW2458N board support"
  969. + select SOC_AR724X
  970. + select ATH79_DEV_AP9X_PCI if PCI
  971. + select ATH79_DEV_ETH
  972. + select ATH79_DEV_GPIO_BUTTONS
  973. + select ATH79_DEV_LEDS_GPIO
  974. + select ATH79_DEV_M25P80
  975. + select ATH79_DEV_USB
  976. +
  977. +config ATH79_MACH_CAP4200AG
  978. + bool "Senao CAP4200AG support"
  979. + select SOC_AR934X
  980. + select ATH79_DEV_AP9X_PCI if PCI
  981. + select ATH79_DEV_ETH
  982. + select ATH79_DEV_GPIO_BUTTONS
  983. + select ATH79_DEV_LEDS_GPIO
  984. + select ATH79_DEV_M25P80
  985. + select ATH79_DEV_WMAC
  986. +
  987. +config ATH79_MACH_MR1750
  988. + bool "OpenMesh MR1750 board support"
  989. + select SOC_QCA955X
  990. + select ATH79_DEV_AP9X_PCI if PCI
  991. + select ATH79_DEV_ETH
  992. + select ATH79_DEV_GPIO_BUTTONS
  993. + select ATH79_DEV_LEDS_GPIO
  994. + select ATH79_DEV_M25P80
  995. + select ATH79_DEV_WMAC
  996. +
  997. +config ATH79_MACH_MR900
  998. + bool "OpenMesh MR900 board support"
  999. + select SOC_QCA955X
  1000. + select ATH79_DEV_AP9X_PCI if PCI
  1001. + select ATH79_DEV_ETH
  1002. + select ATH79_DEV_GPIO_BUTTONS
  1003. + select ATH79_DEV_LEDS_GPIO
  1004. + select ATH79_DEV_M25P80
  1005. + select ATH79_DEV_WMAC
  1006. +
  1007. +config ATH79_MACH_EAP7660D
  1008. + bool "Senao EAP7660D support"
  1009. + select SOC_AR71XX
  1010. + select ATH79_DEV_ETH
  1011. + select ATH79_DEV_GPIO_BUTTONS
  1012. + select ATH79_DEV_LEDS_GPIO
  1013. + select ATH79_DEV_M25P80
  1014. +
  1015. +config ATH79_MACH_BSB
  1016. + bool "Smart Electronics Black Swift board"
  1017. + select SOC_AR933X
  1018. + select ATH79_DEV_ETH
  1019. + select ATH79_DEV_GPIO_BUTTONS
  1020. + select ATH79_DEV_LEDS_GPIO
  1021. + select ATH79_DEV_M25P80
  1022. + select ATH79_DEV_USB
  1023. + select ATH79_DEV_WMAC
  1024. +
  1025. +config ATH79_MACH_ARCHER_C7
  1026. + bool "TP-LINK Archer C5/C7/TL-WDR4900 v2 board support"
  1027. + select SOC_QCA955X
  1028. + select ATH79_DEV_AP9X_PCI if PCI
  1029. + select ATH79_DEV_ETH
  1030. + select ATH79_DEV_GPIO_BUTTONS
  1031. + select ATH79_DEV_LEDS_GPIO
  1032. + select ATH79_DEV_M25P80
  1033. + select ATH79_DEV_USB
  1034. + select ATH79_DEV_WMAC
  1035. +
  1036. +config ATH79_MACH_CPE510
  1037. + bool "TP-LINK CPE510 support"
  1038. + select SOC_AR934X
  1039. + select ATH79_DEV_ETH
  1040. + select ATH79_DEV_GPIO_BUTTONS
  1041. + select ATH79_DEV_LEDS_GPIO
  1042. + select ATH79_DEV_M25P80
  1043. + select ATH79_DEV_WMAC
  1044. +
  1045. +config ATH79_MACH_TL_MR11U
  1046. + bool "TP-LINK TL-MR11U/TL-MR3040 support"
  1047. + select SOC_AR933X
  1048. + select ATH79_DEV_ETH
  1049. select ATH79_DEV_GPIO_BUTTONS
  1050. select ATH79_DEV_LEDS_GPIO
  1051. - select ATH79_DEV_SPI
  1052. + select ATH79_DEV_M25P80
  1053. select ATH79_DEV_USB
  1054. select ATH79_DEV_WMAC
  1055. - help
  1056. - Say 'Y' here if you want your kernel to support the
  1057. - Atheros AP121 reference board.
  1058. -config ATH79_MACH_AP136
  1059. - bool "Atheros AP136 reference board"
  1060. - select SOC_QCA955X
  1061. +config ATH79_MACH_TL_MR13U
  1062. + bool "TP-LINK TL-MR13U support"
  1063. + select SOC_AR933X
  1064. + select ATH79_DEV_ETH
  1065. select ATH79_DEV_GPIO_BUTTONS
  1066. select ATH79_DEV_LEDS_GPIO
  1067. - select ATH79_DEV_SPI
  1068. + select ATH79_DEV_M25P80
  1069. select ATH79_DEV_USB
  1070. select ATH79_DEV_WMAC
  1071. - help
  1072. - Say 'Y' here if you want your kernel to support the
  1073. - Atheros AP136 reference board.
  1074. -config ATH79_MACH_AP81
  1075. - bool "Atheros AP81 reference board"
  1076. +config ATH79_MACH_TL_MR3020
  1077. + bool "TP-LINK TL-MR3020 support"
  1078. + select SOC_AR933X
  1079. + select ATH79_DEV_ETH
  1080. + select ATH79_DEV_GPIO_BUTTONS
  1081. + select ATH79_DEV_LEDS_GPIO
  1082. + select ATH79_DEV_M25P80
  1083. + select ATH79_DEV_USB
  1084. + select ATH79_DEV_WMAC
  1085. +
  1086. +config ATH79_MACH_TL_MR3X20
  1087. + bool "TP-LINK TL-MR3220/3420 support"
  1088. + select SOC_AR724X
  1089. + select ATH79_DEV_AP9X_PCI if PCI
  1090. + select ATH79_DEV_ETH
  1091. + select ATH79_DEV_GPIO_BUTTONS
  1092. + select ATH79_DEV_LEDS_GPIO
  1093. + select ATH79_DEV_M25P80
  1094. + select ATH79_DEV_USB
  1095. +
  1096. +config ATH79_MACH_TL_WAX50RE
  1097. + bool "TP-LINK TL-WA750/850RE support"
  1098. + select SOC_AR934X
  1099. + select ATH79_DEV_ETH
  1100. + select ATH79_DEV_GPIO_BUTTONS
  1101. + select ATH79_DEV_LEDS_GPIO
  1102. + select ATH79_DEV_M25P80
  1103. + select ATH79_DEV_WMAC
  1104. +
  1105. +config ATH79_MACH_TL_WA701ND_V2
  1106. + bool "TP-LINK TL-WA701ND v2 support"
  1107. + select SOC_AR933X
  1108. + select ATH79_DEV_ETH
  1109. + select ATH79_DEV_GPIO_BUTTONS
  1110. + select ATH79_DEV_LEDS_GPIO
  1111. + select ATH79_DEV_M25P80
  1112. + select ATH79_DEV_USB
  1113. + select ATH79_DEV_WMAC
  1114. +
  1115. +config ATH79_MACH_TL_WA7210N_V2
  1116. + bool "TP-LINK TL-WA7210N v2 support"
  1117. + select SOC_AR724X
  1118. + select ATH79_DEV_AP9X_PCI if PCI
  1119. + select ATH79_DEV_ETH
  1120. + select ATH79_DEV_LEDS_GPIO
  1121. + select ATH79_DEV_GPIO_BUTTONS
  1122. + select ATH79_DEV_M25P80
  1123. + select ATH79_DEV_WMAC
  1124. +
  1125. +config ATH79_MACH_TL_WA830RE_V2
  1126. + bool "TP-LINK TL-WA830RE v2 support"
  1127. + select SOC_AR934X
  1128. + select ATH79_DEV_ETH
  1129. + select ATH79_DEV_GPIO_BUTTONS
  1130. + select ATH79_DEV_LEDS_GPIO
  1131. + select ATH79_DEV_M25P80
  1132. + select ATH79_DEV_USB
  1133. + select ATH79_DEV_WMAC
  1134. +
  1135. +config ATH79_MACH_TL_WA901ND
  1136. + bool "TP-LINK TL-WA901ND/TL-WA7510N support"
  1137. + select SOC_AR724X
  1138. + select ATH79_DEV_AP9X_PCI if PCI
  1139. + select ATH79_DEV_ETH
  1140. + select ATH79_DEV_GPIO_BUTTONS
  1141. + select ATH79_DEV_LEDS_GPIO
  1142. + select ATH79_DEV_M25P80
  1143. +
  1144. +config ATH79_MACH_TL_WA901ND_V2
  1145. + bool "TP-LINK TL-WA901ND v2 support"
  1146. select SOC_AR913X
  1147. + select ATH79_DEV_ETH
  1148. select ATH79_DEV_GPIO_BUTTONS
  1149. select ATH79_DEV_LEDS_GPIO
  1150. - select ATH79_DEV_SPI
  1151. + select ATH79_DEV_M25P80
  1152. + select ATH79_DEV_WMAC
  1153. +
  1154. +config ATH79_MACH_TL_WDR3320_V2
  1155. + bool "TP-LINK TL-WDR3320 v2 board support"
  1156. + select SOC_AR934X
  1157. + select ATH79_DEV_AP9X_PCI if PCI
  1158. + select ATH79_DEV_ETH
  1159. + select ATH79_DEV_GPIO_BUTTONS
  1160. + select ATH79_DEV_LEDS_GPIO
  1161. + select ATH79_DEV_M25P80
  1162. select ATH79_DEV_USB
  1163. select ATH79_DEV_WMAC
  1164. - help
  1165. - Say 'Y' here if you want your kernel to support the
  1166. - Atheros AP81 reference board.
  1167. -config ATH79_MACH_DB120
  1168. - bool "Atheros DB120 reference board"
  1169. +config ATH79_MACH_TL_WDR3500
  1170. + bool "TP-LINK TL-WDR3500 board support"
  1171. select SOC_AR934X
  1172. + select ATH79_DEV_AP9X_PCI if PCI
  1173. + select ATH79_DEV_ETH
  1174. select ATH79_DEV_GPIO_BUTTONS
  1175. select ATH79_DEV_LEDS_GPIO
  1176. - select ATH79_DEV_SPI
  1177. + select ATH79_DEV_M25P80
  1178. select ATH79_DEV_USB
  1179. select ATH79_DEV_WMAC
  1180. - help
  1181. - Say 'Y' here if you want your kernel to support the
  1182. - Atheros DB120 reference board.
  1183. -config ATH79_MACH_PB44
  1184. - bool "Atheros PB44 reference board"
  1185. +config ATH79_MACH_TL_WDR4300
  1186. + bool "TP-LINK TL-WDR3600/4300/4310 board support"
  1187. + select SOC_AR934X
  1188. + select ATH79_DEV_AP9X_PCI if PCI
  1189. + select ATH79_DEV_ETH
  1190. + select ATH79_DEV_GPIO_BUTTONS
  1191. + select ATH79_DEV_LEDS_GPIO
  1192. + select ATH79_DEV_M25P80
  1193. + select ATH79_DEV_USB
  1194. + select ATH79_DEV_WMAC
  1195. +
  1196. +config ATH79_MACH_TL_WDR6500_V2
  1197. + bool "TP-LINK TL-WDR6500 v2 board support"
  1198. + select SOC_QCA956X
  1199. + select ATH79_DEV_AP9X_PCI if PCI
  1200. + select ATH79_DEV_ETH
  1201. + select ATH79_DEV_GPIO_BUTTONS
  1202. + select ATH79_DEV_LEDS_GPIO
  1203. + select ATH79_DEV_M25P80
  1204. + select ATH79_DEV_USB
  1205. + select ATH79_DEV_WMAC
  1206. +
  1207. +config ATH79_MACH_TL_WR703N
  1208. + bool "TP-LINK TL-WR703N/TL-WR710N/TL-MR10U support"
  1209. + select SOC_AR933X
  1210. + select ATH79_DEV_ETH
  1211. + select ATH79_DEV_GPIO_BUTTONS
  1212. + select ATH79_DEV_LEDS_GPIO
  1213. + select ATH79_DEV_M25P80
  1214. + select ATH79_DEV_USB
  1215. + select ATH79_DEV_WMAC
  1216. +
  1217. +config ATH79_MACH_TL_WR720N_V3
  1218. + bool "TP-LINK TL-WR720N v3/v4 support"
  1219. + select SOC_AR933X
  1220. + select ATH79_DEV_ETH
  1221. + select ATH79_DEV_GPIO_BUTTONS
  1222. + select ATH79_DEV_LEDS_GPIO
  1223. + select ATH79_DEV_M25P80
  1224. + select ATH79_DEV_USB
  1225. + select ATH79_DEV_WMAC
  1226. +
  1227. +config ATH79_MACH_TL_WR741ND
  1228. + bool "TP-LINK TL-WR741ND support"
  1229. + select SOC_AR724X
  1230. + select ATH79_DEV_AP9X_PCI if PCI
  1231. + select ATH79_DEV_ETH
  1232. + select ATH79_DEV_GPIO_BUTTONS
  1233. + select ATH79_DEV_LEDS_GPIO
  1234. + select ATH79_DEV_M25P80
  1235. +
  1236. +config ATH79_MACH_TL_WR741ND_V4
  1237. + bool "TP-LINK TL-WR741ND v4/TL-MR3220 v2 support"
  1238. + select SOC_AR933X
  1239. + select ATH79_DEV_ETH
  1240. + select ATH79_DEV_GPIO_BUTTONS
  1241. + select ATH79_DEV_LEDS_GPIO
  1242. + select ATH79_DEV_M25P80
  1243. + select ATH79_DEV_USB
  1244. + select ATH79_DEV_WMAC
  1245. +
  1246. +config ATH79_MACH_TL_WR841N_V1
  1247. + bool "TP-LINK TL-WR841N v1 support"
  1248. select SOC_AR71XX
  1249. + select ATH79_DEV_DSA
  1250. + select ATH79_DEV_ETH
  1251. select ATH79_DEV_GPIO_BUTTONS
  1252. select ATH79_DEV_LEDS_GPIO
  1253. - select ATH79_DEV_SPI
  1254. + select ATH79_DEV_M25P80
  1255. +
  1256. +config ATH79_MACH_TL_WR841N_V8
  1257. + bool "TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 support"
  1258. + select SOC_AR934X
  1259. + select ATH79_DEV_ETH
  1260. + select ATH79_DEV_GPIO_BUTTONS
  1261. + select ATH79_DEV_LEDS_GPIO
  1262. + select ATH79_DEV_M25P80
  1263. + select ATH79_DEV_USB
  1264. + select ATH79_DEV_WMAC
  1265. +
  1266. +config ATH79_MACH_TL_WR841N_V9
  1267. + bool "TP-LINK TL-WR841N/ND v9 support"
  1268. + select SOC_QCA953X
  1269. + select ATH79_DEV_ETH
  1270. + select ATH79_DEV_GPIO_BUTTONS
  1271. + select ATH79_DEV_LEDS_GPIO
  1272. + select ATH79_DEV_M25P80
  1273. + select ATH79_DEV_WMAC
  1274. +
  1275. +config ATH79_MACH_TL_WR941ND
  1276. + bool "TP-LINK TL-WR941ND support"
  1277. + select SOC_AR913X
  1278. + select ATH79_DEV_DSA
  1279. + select ATH79_DEV_ETH
  1280. + select ATH79_DEV_GPIO_BUTTONS
  1281. + select ATH79_DEV_LEDS_GPIO
  1282. + select ATH79_DEV_M25P80
  1283. + select ATH79_DEV_WMAC
  1284. +
  1285. +config ATH79_MACH_TL_WR941ND_V6
  1286. + bool "TP-LINK TL-WR941ND v6 support"
  1287. + select SOC_QCA956X
  1288. + select ATH79_DEV_ETH
  1289. + select ATH79_DEV_GPIO_BUTTONS
  1290. + select ATH79_DEV_LEDS_GPIO
  1291. + select ATH79_DEV_M25P80
  1292. + select ATH79_DEV_WMAC
  1293. +
  1294. +config ATH79_MACH_TL_WR1041N_V2
  1295. + bool "TP-LINK TL-WR1041N v2 support"
  1296. + select SOC_AR934X
  1297. + select ATH79_DEV_AP9X_PCI if PCI
  1298. + select ATH79_DEV_ETH
  1299. + select ATH79_DEV_GPIO_BUTTONS
  1300. + select ATH79_DEV_LEDS_GPIO
  1301. + select ATH79_DEV_M25P80
  1302. + select ATH79_DEV_USB
  1303. + select ATH79_DEV_WMAC
  1304. +
  1305. +config ATH79_MACH_TL_WR1043ND
  1306. + bool "TP-LINK TL-WR1043ND support"
  1307. + select SOC_AR913X
  1308. + select ATH79_DEV_ETH
  1309. + select ATH79_DEV_GPIO_BUTTONS
  1310. + select ATH79_DEV_LEDS_GPIO
  1311. + select ATH79_DEV_M25P80
  1312. + select ATH79_DEV_USB
  1313. + select ATH79_DEV_WMAC
  1314. +
  1315. +config ATH79_MACH_TL_WR1043ND_V2
  1316. + bool "TP-LINK TL-WR1043ND v2 support"
  1317. + select SOC_QCA955X
  1318. + select ATH79_DEV_ETH
  1319. + select ATH79_DEV_GPIO_BUTTONS
  1320. + select ATH79_DEV_LEDS_GPIO
  1321. + select ATH79_DEV_M25P80
  1322. + select ATH79_DEV_USB
  1323. + select ATH79_DEV_WMAC
  1324. +
  1325. +config ATH79_MACH_TL_WR2543N
  1326. + bool "TP-LINK TL-WR2543N/ND support"
  1327. + select SOC_AR724X
  1328. + select ATH79_DEV_AP9X_PCI if PCI
  1329. + select ATH79_DEV_ETH
  1330. + select ATH79_DEV_GPIO_BUTTONS
  1331. + select ATH79_DEV_LEDS_GPIO
  1332. + select ATH79_DEV_M25P80
  1333. + select ATH79_DEV_USB
  1334. +
  1335. +config ATH79_MACH_TEW_632BRP
  1336. + bool "TRENDnet TEW-632BRP support"
  1337. + select SOC_AR913X
  1338. + select ATH79_DEV_ETH
  1339. + select ATH79_DEV_GPIO_BUTTONS
  1340. + select ATH79_DEV_LEDS_GPIO
  1341. + select ATH79_DEV_M25P80
  1342. + select ATH79_DEV_WMAC
  1343. + select ATH79_NVRAM
  1344. +
  1345. +config ATH79_MACH_TEW_673GRU
  1346. + bool "TRENDnet TEW-673GRU support"
  1347. + select SOC_AR71XX
  1348. + select ATH79_DEV_AP9X_PCI if PCI
  1349. + select ATH79_DEV_ETH
  1350. + select ATH79_DEV_GPIO_BUTTONS
  1351. + select ATH79_DEV_LEDS_GPIO
  1352. + select ATH79_DEV_M25P80
  1353. + select ATH79_DEV_USB
  1354. + select ATH79_NVRAM
  1355. +
  1356. +config ATH79_MACH_TEW_712BR
  1357. + bool "TRENDnet TEW-712BR support"
  1358. + select SOC_AR933X
  1359. + select ATH79_DEV_ETH
  1360. + select ATH79_DEV_GPIO_BUTTONS
  1361. + select ATH79_DEV_LEDS_GPIO
  1362. + select ATH79_DEV_M25P80
  1363. + select ATH79_DEV_WMAC
  1364. + select ATH79_NVRAM
  1365. +
  1366. +config ATH79_MACH_TEW_732BR
  1367. + bool "TRENDnet TEW-732BR support"
  1368. + select SOC_AR934X
  1369. + select ATH79_DEV_ETH
  1370. + select ATH79_DEV_GPIO_BUTTONS
  1371. + select ATH79_DEV_LEDS_GPIO
  1372. + select ATH79_DEV_M25P80
  1373. + select ATH79_DEV_WMAC
  1374. +
  1375. +config ATH79_MACH_UBNT
  1376. + bool "Ubiquiti AR71xx based boards support"
  1377. + select SOC_AR71XX
  1378. + select ATH79_DEV_ETH
  1379. + select ATH79_DEV_GPIO_BUTTONS
  1380. + select ATH79_DEV_LEDS_GPIO
  1381. + select ATH79_DEV_M25P80
  1382. select ATH79_DEV_USB
  1383. - help
  1384. - Say 'Y' here if you want your kernel to support the
  1385. - Atheros PB44 reference board.
  1386. config ATH79_MACH_UBNT_XM
  1387. - bool "Ubiquiti Networks XM (rev 1.0) board"
  1388. + bool "Ubiquiti Networks XM/UniFi boards"
  1389. select SOC_AR724X
  1390. + select SOC_AR934X
  1391. + select ATH79_DEV_AP9X_PCI if PCI
  1392. + select ATH79_DEV_ETH
  1393. select ATH79_DEV_GPIO_BUTTONS
  1394. select ATH79_DEV_LEDS_GPIO
  1395. - select ATH79_DEV_SPI
  1396. + select ATH79_DEV_M25P80
  1397. + select ATH79_DEV_USB
  1398. + select ATH79_DEV_WMAC
  1399. help
  1400. Say 'Y' here if you want your kernel to support the
  1401. Ubiquiti Networks XM (rev 1.0) board.
  1402. +config ATH79_MACH_WEIO
  1403. + bool "WeIO board"
  1404. + select SOC_AR933X
  1405. + select ATH79_DEV_GPIO_BUTTONS
  1406. + select ATH79_DEV_LEDS_GPIO
  1407. + select ATH79_DEV_M25P80
  1408. + select ATH79_DEV_USB
  1409. + select ATH79_DEV_WMAC
  1410. +
  1411. +config ATH79_MACH_MYNET_N600
  1412. + bool "WD My Net N600 board support"
  1413. + select SOC_AR934X
  1414. + select ATH79_DEV_ETH
  1415. + select ATH79_DEV_GPIO_BUTTONS
  1416. + select ATH79_DEV_LEDS_GPIO
  1417. + select ATH79_DEV_M25P80
  1418. + select ATH79_DEV_WMAC
  1419. + select ATH79_NVRAM
  1420. +
  1421. +config ATH79_MACH_MYNET_N750
  1422. + bool "WD My Net N750 board support"
  1423. + select SOC_AR934X
  1424. + select ATH79_DEV_ETH
  1425. + select ATH79_DEV_GPIO_BUTTONS
  1426. + select ATH79_DEV_LEDS_GPIO
  1427. + select ATH79_DEV_M25P80
  1428. + select ATH79_DEV_WMAC
  1429. + select ATH79_NVRAM
  1430. +
  1431. +config ATH79_MACH_MYNET_REXT
  1432. + bool "WD My Net Wi-Fi Range Extender board support"
  1433. + select SOC_AR934X
  1434. + select ATH79_DEV_AP9X_PCI if PCI
  1435. + select ATH79_DEV_ETH
  1436. + select ATH79_DEV_GPIO_BUTTONS
  1437. + select ATH79_DEV_LEDS_GPIO
  1438. + select ATH79_DEV_M25P80
  1439. + select ATH79_DEV_WMAC
  1440. + select ATH79_NVRAM
  1441. +
  1442. +config ATH79_MACH_ZCN_1523H
  1443. + bool "Zcomax ZCN-1523H support"
  1444. + select SOC_AR724X
  1445. + select ATH79_DEV_AP9X_PCI if PCI
  1446. + select ATH79_DEV_ETH
  1447. + select ATH79_DEV_GPIO_BUTTONS
  1448. + select ATH79_DEV_LEDS_GPIO
  1449. + select ATH79_DEV_M25P80
  1450. +
  1451. +config ATH79_MACH_NBG460N
  1452. + bool "Zyxel NBG460N/550N/550NH board support"
  1453. + select SOC_AR913X
  1454. + select ATH79_DEV_ETH
  1455. + select ATH79_DEV_GPIO_BUTTONS
  1456. + select ATH79_DEV_LEDS_GPIO
  1457. + select ATH79_DEV_M25P80
  1458. + select ATH79_DEV_WMAC
  1459. +
  1460. +config ATH79_MACH_NBG6716
  1461. + bool "Zyxel NBG6616/NBG6716 board support"
  1462. + select SOC_QCA955X
  1463. + select ATH79_DEV_ETH
  1464. + select ATH79_DEV_GPIO_BUTTONS
  1465. + select ATH79_DEV_LEDS_GPIO
  1466. + select ATH79_DEV_M25P80
  1467. + select ATH79_DEV_NFC
  1468. + select ATH79_DEV_USB
  1469. + select ATH79_DEV_WMAC
  1470. +
  1471. +config ATH79_MACH_CARAMBOLA2
  1472. + bool "8devices Carambola2 board"
  1473. + select SOC_AR933X
  1474. + select ATH79_DEV_ETH
  1475. + select ATH79_DEV_GPIO_BUTTONS
  1476. + select ATH79_DEV_LEDS_GPIO
  1477. + select ATH79_DEV_M25P80
  1478. + select ATH79_DEV_USB
  1479. + select ATH79_DEV_WMAC
  1480. +
  1481. +config ATH79_MACH_CF_E316N_V2
  1482. + bool "COMFAST CF-E316N v2 board"
  1483. + select SOC_AR934X
  1484. + select ATH79_DEV_ETH
  1485. + select ATH79_DEV_GPIO_BUTTONS
  1486. + select ATH79_DEV_LEDS_GPIO
  1487. + select ATH79_DEV_M25P80
  1488. + select ATH79_DEV_USB
  1489. + select ATH79_DEV_WMAC
  1490. +
  1491. +config ATH79_MACH_BHU_BXU2000N2_A
  1492. + bool "BHU BXU2000n-2 rev. A support"
  1493. + select SOC_AR934X
  1494. + select ATH79_DEV_ETH
  1495. + select ATH79_DEV_GPIO_BUTTONS
  1496. + select ATH79_DEV_LEDS_GPIO
  1497. + select ATH79_DEV_M25P80
  1498. + select ATH79_DEV_USB
  1499. + select ATH79_DEV_WMAC
  1500. +
  1501. +config ATH79_MACH_QIHOO_C301
  1502. + bool "Qihoo 360 C301 board support"
  1503. + select SOC_AR934X
  1504. + select ATH79_DEV_ETH
  1505. + select ATH79_DEV_GPIO_BUTTONS
  1506. + select ATH79_DEV_LEDS_GPIO
  1507. + select ATH79_DEV_M25P80
  1508. + select ATH79_DEV_WMAC
  1509. + select ATH79_DEV_USB
  1510. + select ATH79_NVRAM
  1511. +
  1512. endmenu
  1513. config SOC_AR71XX
  1514. @@ -93,12 +1484,39 @@
  1515. select PCI_AR724X if PCI
  1516. def_bool n
  1517. +config SOC_QCA953X
  1518. + select USB_ARCH_HAS_EHCI
  1519. + def_bool n
  1520. +
  1521. config SOC_QCA955X
  1522. select HW_HAS_PCI
  1523. select PCI_AR724X if PCI
  1524. def_bool n
  1525. -config PCI_AR724X
  1526. +config SOC_QCA956X
  1527. + select USB_ARCH_HAS_EHCI
  1528. + select HW_HAS_PCI
  1529. + select PCI_AR724X if PCI
  1530. + def_bool n
  1531. +
  1532. +config ATH79_DEV_M25P80
  1533. + select ATH79_DEV_SPI
  1534. + def_bool n
  1535. +
  1536. +config ATH79_DEV_AP9X_PCI
  1537. + select ATH79_PCI_ATH9K_FIXUP
  1538. + def_bool n
  1539. +
  1540. +config ATH79_DEV_DSA
  1541. + def_bool n
  1542. +
  1543. +config ATH79_DEV_ETH
  1544. + def_bool n
  1545. +
  1546. +config ATH79_DEV_DSA
  1547. + def_bool n
  1548. +
  1549. +config ATH79_DEV_ETH
  1550. def_bool n
  1551. config ATH79_DEV_GPIO_BUTTONS
  1552. @@ -107,6 +1525,10 @@
  1553. config ATH79_DEV_LEDS_GPIO
  1554. def_bool n
  1555. +config ATH79_DEV_NFC
  1556. + depends on (SOC_AR934X || SOC_QCA955X)
  1557. + def_bool n
  1558. +
  1559. config ATH79_DEV_SPI
  1560. def_bool n
  1561. @@ -114,7 +1536,21 @@
  1562. def_bool n
  1563. config ATH79_DEV_WMAC
  1564. - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  1565. + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
  1566. + def_bool n
  1567. +
  1568. +config ATH79_NVRAM
  1569. + def_bool n
  1570. +
  1571. +config ATH79_PCI_ATH9K_FIXUP
  1572. + def_bool n
  1573. +
  1574. +config ATH79_ROUTERBOOT
  1575. + select RLE_DECOMPRESS
  1576. + select LZO_DECOMPRESS
  1577. + def_bool n
  1578. +
  1579. +config PCI_AR724X
  1580. def_bool n
  1581. endif
  1582. diff -Nur linux-4.1.43.orig/arch/mips/ath79/Makefile linux-4.1.43/arch/mips/ath79/Makefile
  1583. --- linux-4.1.43.orig/arch/mips/ath79/Makefile 2017-08-06 01:56:14.000000000 +0200
  1584. +++ linux-4.1.43/arch/mips/ath79/Makefile 2017-08-06 20:02:15.000000000 +0200
  1585. @@ -17,18 +17,169 @@
  1586. # Devices
  1587. #
  1588. obj-y += dev-common.o
  1589. +obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o
  1590. +obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o
  1591. +obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o
  1592. obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
  1593. obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
  1594. +obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o
  1595. +obj-$(CONFIG_ATH79_DEV_NFC) += dev-nfc.o
  1596. obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
  1597. obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
  1598. obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
  1599. #
  1600. +# Miscellaneous objects
  1601. +#
  1602. +obj-$(CONFIG_ATH79_NVRAM) += nvram.o
  1603. +obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o
  1604. +obj-$(CONFIG_ATH79_ROUTERBOOT) += routerboot.o
  1605. +
  1606. +#
  1607. # Machines
  1608. #
  1609. +obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o
  1610. +obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o
  1611. +obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o
  1612. +obj-$(CONFIG_ATH79_MACH_ALL0315N) += mach-all0315n.o
  1613. +obj-$(CONFIG_ATH79_MACH_ANTMINER_S1)+= mach-antminer-s1.o
  1614. +obj-$(CONFIG_ATH79_MACH_ANTMINER_S3)+= mach-antminer-s3.o
  1615. +obj-$(CONFIG_ATH79_MACH_ARDUINO_YUN) += mach-arduino-yun.o
  1616. +obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o
  1617. obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
  1618. +obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o
  1619. obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
  1620. +obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o
  1621. +obj-$(CONFIG_ATH79_MACH_AP147) += mach-ap147.o
  1622. +obj-$(CONFIG_ATH79_MACH_AP152) += mach-ap152.o
  1623. obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
  1624. +obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
  1625. +obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o
  1626. +obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7.o
  1627. +obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o
  1628. +obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A)+= mach-bhu-bxu2000n2-a.o
  1629. +obj-$(CONFIG_ATH79_MACH_BSB) += mach-bsb.o
  1630. +obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o
  1631. +obj-$(CONFIG_ATH79_MACH_CF_E316N_V2) += mach-cf-e316n-v2.o
  1632. +obj-$(CONFIG_ATH79_MACH_CPE510) += mach-cpe510.o
  1633. obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
  1634. +obj-$(CONFIG_ATH79_MACH_DLAN_HOTSPOT) += mach-dlan-hotspot.o
  1635. +obj-$(CONFIG_ATH79_MACH_DLAN_PRO_500_WP) += mach-dlan-pro-500-wp.o
  1636. +obj-$(CONFIG_ATH79_MACH_DLAN_PRO_1200_AC) += mach-dlan-pro-1200-ac.o
  1637. +obj-$(CONFIG_ATH79_MACH_DGL_5500_A1) += mach-dgl-5500-a1.o
  1638. +obj-$(CONFIG_ATH79_MACH_DHP_1565_A1) += mach-dhp-1565-a1.o
  1639. +obj-$(CONFIG_ATH79_MACH_DIR_505_A1) += mach-dir-505-a1.o
  1640. +obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o
  1641. +obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o
  1642. +obj-$(CONFIG_ATH79_MACH_DIR_615_I1) += mach-dir-615-i1.o
  1643. +obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o
  1644. +obj-$(CONFIG_ATH79_MACH_DIR_825_C1) += mach-dir-825-c1.o
  1645. +obj-$(CONFIG_ATH79_MACH_DRAGINO2) += mach-dragino2.o
  1646. +obj-$(CONFIG_ATH79_MACH_ESR900) += mach-esr900.o
  1647. +obj-$(CONFIG_ATH79_MACH_EW_DORIN) += mach-ew-dorin.o
  1648. +obj-$(CONFIG_ATH79_MACH_EAP300V2) += mach-eap300v2.o
  1649. +obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o
  1650. +obj-$(CONFIG_ATH79_MACH_EL_M150) += mach-el-m150.o
  1651. +obj-$(CONFIG_ATH79_MACH_EL_MINI) += mach-el-mini.o
  1652. +obj-$(CONFIG_ATH79_MACH_EPG5000) += mach-epg5000.o
  1653. +obj-$(CONFIG_ATH79_MACH_ESR1750) += mach-esr1750.o
  1654. +obj-$(CONFIG_ATH79_MACH_F9K1115V2) += mach-f9k1115v2.o
  1655. +obj-$(CONFIG_ATH79_MACH_GL_AR150) += mach-gl-ar150.o
  1656. +obj-$(CONFIG_ATH79_MACH_GL_AR300) += mach-gl-ar300.o
  1657. +obj-$(CONFIG_ATH79_MACH_GL_DOMINO) += mach-gl-domino.o
  1658. +obj-$(CONFIG_ATH79_MACH_GL_INET) += mach-gl-inet.o
  1659. +obj-$(CONFIG_ATH79_MACH_GS_MINIBOX_V1) += mach-gs-minibox-v1.o
  1660. +obj-$(CONFIG_ATH79_MACH_GS_OOLITE) += mach-gs-oolite.o
  1661. +obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361) += mach-hiwifi-hc6361.o
  1662. +obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o
  1663. +obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o
  1664. +obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o
  1665. +obj-$(CONFIG_ATH79_MACH_MC_MAC1200R) += mach-mc-mac1200r.o
  1666. +obj-$(CONFIG_ATH79_MACH_MR12) += mach-mr12.o
  1667. +obj-$(CONFIG_ATH79_MACH_MR16) += mach-mr16.o
  1668. +obj-$(CONFIG_ATH79_MACH_MR1750) += mach-mr1750.o
  1669. +obj-$(CONFIG_ATH79_MACH_MR600) += mach-mr600.o
  1670. +obj-$(CONFIG_ATH79_MACH_MR900) += mach-mr900.o
  1671. +obj-$(CONFIG_ATH79_MACH_MYNET_N600) += mach-mynet-n600.o
  1672. +obj-$(CONFIG_ATH79_MACH_MYNET_N750) += mach-mynet-n750.o
  1673. +obj-$(CONFIG_ATH79_MACH_MYNET_REXT) += mach-mynet-rext.o
  1674. +obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o
  1675. +obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o
  1676. +obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o
  1677. +obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
  1678. +obj-$(CONFIG_ATH79_MACH_OM5P) += mach-om5p.o
  1679. +obj-$(CONFIG_ATH79_MACH_ONION_OMEGA) += mach-onion-omega.o
  1680. +obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
  1681. obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
  1682. +obj-$(CONFIG_ATH79_MACH_PB92) += mach-pb92.o
  1683. +obj-$(CONFIG_ATH79_MACH_QIHOO_C301) += mach-qihoo-c301.o
  1684. +obj-$(CONFIG_ATH79_MACH_R6100) += mach-r6100.o
  1685. +obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o
  1686. +obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o
  1687. +obj-$(CONFIG_ATH79_MACH_RB91X) += mach-rb91x.o
  1688. +obj-$(CONFIG_ATH79_MACH_RB922) += mach-rb922.o
  1689. +obj-$(CONFIG_ATH79_MACH_RB95X) += mach-rb95x.o
  1690. +obj-$(CONFIG_ATH79_MACH_RB2011) += mach-rb2011.o
  1691. +obj-$(CONFIG_ATH79_MACH_RBSXTLITE) += mach-rbsxtlite.o
  1692. +obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
  1693. +obj-$(CONFIG_ATH79_MACH_SMART_300) += mach-smart-300.o
  1694. +obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o
  1695. +obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o
  1696. +obj-$(CONFIG_ATH79_MACH_TEW_712BR) += mach-tew-712br.o
  1697. +obj-$(CONFIG_ATH79_MACH_TEW_732BR) += mach-tew-732br.o
  1698. +obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o
  1699. +obj-$(CONFIG_ATH79_MACH_TL_MR13U) += mach-tl-mr13u.o
  1700. +obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o
  1701. +obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
  1702. +obj-$(CONFIG_ATH79_MACH_TL_WAX50RE) += mach-tl-wax50re.o
  1703. +obj-$(CONFIG_ATH79_MACH_TL_WA701ND_V2) += mach-tl-wa701nd-v2.o
  1704. +obj-$(CONFIG_ATH79_MACH_TL_WA7210N_V2) += mach-tl-wa7210n-v2.o
  1705. +obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2) += mach-tl-wa830re-v2.o
  1706. +obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o
  1707. +obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o
  1708. +obj-$(CONFIG_ATH79_MACH_TL_WDR3320_V2) += mach-tl-wdr3320-v2.o
  1709. +obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o
  1710. +obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o
  1711. +obj-$(CONFIG_ATH79_MACH_TL_WDR6500_V2) += mach-tl-wdr6500-v2.o
  1712. +obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o
  1713. +obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o
  1714. +obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
  1715. +obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o
  1716. +obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o
  1717. +obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
  1718. +obj-$(CONFIG_ATH79_MACH_TL_WR941ND_V6) += mach-tl-wr941nd-v6.o
  1719. +obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2) += mach-tl-wr1041n-v2.o
  1720. +obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o
  1721. +obj-$(CONFIG_ATH79_MACH_TL_WR1043ND_V2) += mach-tl-wr1043nd-v2.o
  1722. +obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o
  1723. +obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o
  1724. +obj-$(CONFIG_ATH79_MACH_TL_WR720N_V3) += mach-tl-wr720n-v3.o
  1725. +obj-$(CONFIG_ATH79_MACH_TUBE2H) += mach-tube2h.o
  1726. +obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o
  1727. obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
  1728. +obj-$(CONFIG_ATH79_MACH_WEIO) += mach-weio.o
  1729. +obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
  1730. +obj-$(CONFIG_ATH79_MACH_WLAE_AG300N) += mach-wlae-ag300n.o
  1731. +obj-$(CONFIG_ATH79_MACH_WLR8100) += mach-wlr8100.o
  1732. +obj-$(CONFIG_ATH79_MACH_WNDAP360) += mach-wndap360.o
  1733. +obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o
  1734. +obj-$(CONFIG_ATH79_MACH_WNDR4300) += mach-wndr4300.o
  1735. +obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o
  1736. +obj-$(CONFIG_ATH79_MACH_WNR2000_V3) += mach-wnr2000-v3.o
  1737. +obj-$(CONFIG_ATH79_MACH_WNR2000_V4) += mach-wnr2000-v4.o
  1738. +obj-$(CONFIG_ATH79_MACH_WNR2200) += mach-wnr2200.o
  1739. +obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o
  1740. +obj-$(CONFIG_ATH79_MACH_WPE72) += mach-wpe72.o
  1741. +obj-$(CONFIG_ATH79_MACH_WPJ344) += mach-wpj344.o
  1742. +obj-$(CONFIG_ATH79_MACH_WPJ531) += mach-wpj531.o
  1743. +obj-$(CONFIG_ATH79_MACH_WPJ558) += mach-wpj558.o
  1744. +obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o
  1745. +obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o
  1746. +obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o
  1747. +obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o
  1748. +obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o
  1749. +obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
  1750. +obj-$(CONFIG_ATH79_MACH_WZR_450HP2) += mach-wzr-450hp2.o
  1751. +obj-$(CONFIG_ATH79_MACH_ZCN_1523H) += mach-zcn-1523h.o
  1752. +obj-$(CONFIG_ATH79_MACH_CARAMBOLA2) += mach-carambola2.o
  1753. +obj-$(CONFIG_ATH79_MACH_NBG6716) += mach-nbg6716.o
  1754. diff -Nur linux-4.1.43.orig/arch/mips/ath79/clock.c linux-4.1.43/arch/mips/ath79/clock.c
  1755. --- linux-4.1.43.orig/arch/mips/ath79/clock.c 2017-08-06 01:56:14.000000000 +0200
  1756. +++ linux-4.1.43/arch/mips/ath79/clock.c 2017-08-06 20:02:15.000000000 +0200
  1757. @@ -25,7 +25,7 @@
  1758. #include "common.h"
  1759. #define AR71XX_BASE_FREQ 40000000
  1760. -#define AR724X_BASE_FREQ 5000000
  1761. +#define AR724X_BASE_FREQ 40000000
  1762. #define AR913X_BASE_FREQ 5000000
  1763. struct clk {
  1764. @@ -99,8 +99,8 @@
  1765. div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
  1766. freq = div * ref_rate;
  1767. - div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
  1768. - freq *= div;
  1769. + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
  1770. + freq /= div;
  1771. cpu_rate = freq;
  1772. @@ -350,6 +350,91 @@
  1773. iounmap(dpll_base);
  1774. }
  1775. +static void __init qca953x_clocks_init(void)
  1776. +{
  1777. + unsigned long ref_rate;
  1778. + unsigned long cpu_rate;
  1779. + unsigned long ddr_rate;
  1780. + unsigned long ahb_rate;
  1781. + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  1782. + u32 cpu_pll, ddr_pll;
  1783. + u32 bootstrap;
  1784. +
  1785. + bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  1786. + if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  1787. + ref_rate = 40 * 1000 * 1000;
  1788. + else
  1789. + ref_rate = 25 * 1000 * 1000;
  1790. +
  1791. + pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  1792. + out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  1793. + QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  1794. + ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  1795. + QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  1796. + nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  1797. + QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  1798. + frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  1799. + QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  1800. +
  1801. + cpu_pll = nint * ref_rate / ref_div;
  1802. + cpu_pll += frac * (ref_rate >> 6) / ref_div;
  1803. + cpu_pll /= (1 << out_div);
  1804. +
  1805. + pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  1806. + out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  1807. + QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  1808. + ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  1809. + QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  1810. + nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  1811. + QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  1812. + frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  1813. + QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  1814. +
  1815. + ddr_pll = nint * ref_rate / ref_div;
  1816. + ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
  1817. + ddr_pll /= (1 << out_div);
  1818. +
  1819. + clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  1820. +
  1821. + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  1822. + QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  1823. +
  1824. + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  1825. + cpu_rate = ref_rate;
  1826. + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  1827. + cpu_rate = cpu_pll / (postdiv + 1);
  1828. + else
  1829. + cpu_rate = ddr_pll / (postdiv + 1);
  1830. +
  1831. + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  1832. + QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  1833. +
  1834. + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  1835. + ddr_rate = ref_rate;
  1836. + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
  1837. + ddr_rate = ddr_pll / (postdiv + 1);
  1838. + else
  1839. + ddr_rate = cpu_pll / (postdiv + 1);
  1840. +
  1841. + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  1842. + QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  1843. +
  1844. + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  1845. + ahb_rate = ref_rate;
  1846. + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  1847. + ahb_rate = ddr_pll / (postdiv + 1);
  1848. + else
  1849. + ahb_rate = cpu_pll / (postdiv + 1);
  1850. +
  1851. + ath79_add_sys_clkdev("ref", ref_rate);
  1852. + ath79_add_sys_clkdev("cpu", cpu_rate);
  1853. + ath79_add_sys_clkdev("ddr", ddr_rate);
  1854. + ath79_add_sys_clkdev("ahb", ahb_rate);
  1855. +
  1856. + clk_add_alias("wdt", NULL, "ref", NULL);
  1857. + clk_add_alias("uart", NULL, "ref", NULL);
  1858. +}
  1859. +
  1860. static void __init qca955x_clocks_init(void)
  1861. {
  1862. unsigned long ref_rate;
  1863. @@ -435,6 +520,100 @@
  1864. clk_add_alias("uart", NULL, "ref", NULL);
  1865. }
  1866. +static void __init qca956x_clocks_init(void)
  1867. +{
  1868. + unsigned long ref_rate;
  1869. + unsigned long cpu_rate;
  1870. + unsigned long ddr_rate;
  1871. + unsigned long ahb_rate;
  1872. + u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
  1873. + u32 cpu_pll, ddr_pll;
  1874. + u32 bootstrap;
  1875. +
  1876. + bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  1877. + if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
  1878. + ref_rate = 40 * 1000 * 1000;
  1879. + else
  1880. + ref_rate = 25 * 1000 * 1000;
  1881. +
  1882. + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
  1883. + out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  1884. + QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
  1885. + ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  1886. + QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
  1887. +
  1888. + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
  1889. + nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
  1890. + QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
  1891. + hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
  1892. + QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
  1893. + lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
  1894. + QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
  1895. +
  1896. + cpu_pll = nint * ref_rate / ref_div;
  1897. + cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  1898. + cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
  1899. + cpu_pll /= (1 << out_div);
  1900. +
  1901. + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
  1902. + out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  1903. + QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
  1904. + ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  1905. + QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
  1906. + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
  1907. + nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
  1908. + QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
  1909. + hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
  1910. + QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
  1911. + lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
  1912. + QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
  1913. +
  1914. + ddr_pll = nint * ref_rate / ref_div;
  1915. + ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  1916. + ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
  1917. + ddr_pll /= (1 << out_div);
  1918. +
  1919. + clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
  1920. +
  1921. + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  1922. + QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  1923. +
  1924. + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  1925. + cpu_rate = ref_rate;
  1926. + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
  1927. + cpu_rate = ddr_pll / (postdiv + 1);
  1928. + else
  1929. + cpu_rate = cpu_pll / (postdiv + 1);
  1930. +
  1931. + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  1932. + QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  1933. +
  1934. + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  1935. + ddr_rate = ref_rate;
  1936. + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
  1937. + ddr_rate = cpu_pll / (postdiv + 1);
  1938. + else
  1939. + ddr_rate = ddr_pll / (postdiv + 1);
  1940. +
  1941. + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  1942. + QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  1943. +
  1944. + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  1945. + ahb_rate = ref_rate;
  1946. + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  1947. + ahb_rate = ddr_pll / (postdiv + 1);
  1948. + else
  1949. + ahb_rate = cpu_pll / (postdiv + 1);
  1950. +
  1951. + ath79_add_sys_clkdev("ref", ref_rate);
  1952. + ath79_add_sys_clkdev("cpu", cpu_rate);
  1953. + ath79_add_sys_clkdev("ddr", ddr_rate);
  1954. + ath79_add_sys_clkdev("ahb", ahb_rate);
  1955. +
  1956. + clk_add_alias("wdt", NULL, "ref", NULL);
  1957. + clk_add_alias("uart", NULL, "ref", NULL);
  1958. +}
  1959. +
  1960. void __init ath79_clocks_init(void)
  1961. {
  1962. if (soc_is_ar71xx())
  1963. @@ -447,8 +626,12 @@
  1964. ar933x_clocks_init();
  1965. else if (soc_is_ar934x())
  1966. ar934x_clocks_init();
  1967. + else if (soc_is_qca953x())
  1968. + qca953x_clocks_init();
  1969. else if (soc_is_qca955x())
  1970. qca955x_clocks_init();
  1971. + else if (soc_is_qca956x())
  1972. + qca956x_clocks_init();
  1973. else
  1974. BUG();
  1975. }
  1976. @@ -488,3 +671,15 @@
  1977. return clk->rate;
  1978. }
  1979. EXPORT_SYMBOL(clk_get_rate);
  1980. +
  1981. +int clk_set_rate(struct clk *clk, unsigned long rate)
  1982. +{
  1983. + return 0;
  1984. +}
  1985. +EXPORT_SYMBOL_GPL(clk_set_rate);
  1986. +
  1987. +long clk_round_rate(struct clk *clk, unsigned long rate)
  1988. +{
  1989. + return 0;
  1990. +}
  1991. +EXPORT_SYMBOL_GPL(clk_round_rate);
  1992. diff -Nur linux-4.1.43.orig/arch/mips/ath79/common.c linux-4.1.43/arch/mips/ath79/common.c
  1993. --- linux-4.1.43.orig/arch/mips/ath79/common.c 2017-08-06 01:56:14.000000000 +0200
  1994. +++ linux-4.1.43/arch/mips/ath79/common.c 2017-08-06 20:02:15.000000000 +0200
  1995. @@ -22,6 +22,7 @@
  1996. #include "common.h"
  1997. static DEFINE_SPINLOCK(ath79_device_reset_lock);
  1998. +static DEFINE_MUTEX(ath79_flash_mutex);
  1999. u32 ath79_cpu_freq;
  2000. EXPORT_SYMBOL_GPL(ath79_cpu_freq);
  2001. @@ -72,10 +73,14 @@
  2002. reg = AR933X_RESET_REG_RESET_MODULE;
  2003. else if (soc_is_ar934x())
  2004. reg = AR934X_RESET_REG_RESET_MODULE;
  2005. + else if (soc_is_qca953x())
  2006. + reg = QCA953X_RESET_REG_RESET_MODULE;
  2007. else if (soc_is_qca955x())
  2008. reg = QCA955X_RESET_REG_RESET_MODULE;
  2009. + else if (soc_is_qca956x())
  2010. + reg = QCA956X_RESET_REG_RESET_MODULE;
  2011. else
  2012. - BUG();
  2013. + panic("Reset register not defined for this SOC");
  2014. spin_lock_irqsave(&ath79_device_reset_lock, flags);
  2015. t = ath79_reset_rr(reg);
  2016. @@ -100,10 +105,14 @@
  2017. reg = AR933X_RESET_REG_RESET_MODULE;
  2018. else if (soc_is_ar934x())
  2019. reg = AR934X_RESET_REG_RESET_MODULE;
  2020. + else if (soc_is_qca953x())
  2021. + reg = QCA953X_RESET_REG_RESET_MODULE;
  2022. else if (soc_is_qca955x())
  2023. reg = QCA955X_RESET_REG_RESET_MODULE;
  2024. + else if (soc_is_qca956x())
  2025. + reg = QCA956X_RESET_REG_RESET_MODULE;
  2026. else
  2027. - BUG();
  2028. + panic("Reset register not defined for this SOC");
  2029. spin_lock_irqsave(&ath79_device_reset_lock, flags);
  2030. t = ath79_reset_rr(reg);
  2031. @@ -111,3 +120,42 @@
  2032. spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
  2033. }
  2034. EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
  2035. +
  2036. +u32 ath79_device_reset_get(u32 mask)
  2037. +{
  2038. + unsigned long flags;
  2039. + u32 reg;
  2040. + u32 ret;
  2041. +
  2042. + if (soc_is_ar71xx())
  2043. + reg = AR71XX_RESET_REG_RESET_MODULE;
  2044. + else if (soc_is_ar724x())
  2045. + reg = AR724X_RESET_REG_RESET_MODULE;
  2046. + else if (soc_is_ar913x())
  2047. + reg = AR913X_RESET_REG_RESET_MODULE;
  2048. + else if (soc_is_ar933x())
  2049. + reg = AR933X_RESET_REG_RESET_MODULE;
  2050. + else if (soc_is_ar934x())
  2051. + reg = AR934X_RESET_REG_RESET_MODULE;
  2052. + else
  2053. + BUG();
  2054. +
  2055. + spin_lock_irqsave(&ath79_device_reset_lock, flags);
  2056. + ret = ath79_reset_rr(reg);
  2057. + spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
  2058. + return ret;
  2059. +}
  2060. +EXPORT_SYMBOL_GPL(ath79_device_reset_get);
  2061. +
  2062. +void ath79_flash_acquire(void)
  2063. +{
  2064. + mutex_lock(&ath79_flash_mutex);
  2065. +}
  2066. +EXPORT_SYMBOL_GPL(ath79_flash_acquire);
  2067. +
  2068. +void ath79_flash_release(void)
  2069. +{
  2070. + mutex_unlock(&ath79_flash_mutex);
  2071. +}
  2072. +EXPORT_SYMBOL_GPL(ath79_flash_release);
  2073. +
  2074. diff -Nur linux-4.1.43.orig/arch/mips/ath79/common.h linux-4.1.43/arch/mips/ath79/common.h
  2075. --- linux-4.1.43.orig/arch/mips/ath79/common.h 2017-08-06 01:56:14.000000000 +0200
  2076. +++ linux-4.1.43/arch/mips/ath79/common.h 2017-08-06 20:02:15.000000000 +0200
  2077. @@ -27,6 +27,9 @@
  2078. void ath79_gpio_function_enable(u32 mask);
  2079. void ath79_gpio_function_disable(u32 mask);
  2080. void ath79_gpio_function_setup(u32 set, u32 clear);
  2081. +void ath79_gpio_function2_setup(u32 set, u32 clear);
  2082. +void ath79_gpio_output_select(unsigned gpio, u8 val);
  2083. +int ath79_gpio_direction_select(unsigned gpio, bool oe);
  2084. void ath79_gpio_init(void);
  2085. #endif /* __ATH79_COMMON_H */
  2086. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-ap9x-pci.c linux-4.1.43/arch/mips/ath79/dev-ap9x-pci.c
  2087. --- linux-4.1.43.orig/arch/mips/ath79/dev-ap9x-pci.c 1970-01-01 01:00:00.000000000 +0100
  2088. +++ linux-4.1.43/arch/mips/ath79/dev-ap9x-pci.c 2017-08-06 20:02:15.000000000 +0200
  2089. @@ -0,0 +1,159 @@
  2090. +/*
  2091. + * Atheros AP9X reference board PCI initialization
  2092. + *
  2093. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  2094. + *
  2095. + * This program is free software; you can redistribute it and/or modify it
  2096. + * under the terms of the GNU General Public License version 2 as published
  2097. + * by the Free Software Foundation.
  2098. + */
  2099. +
  2100. +#include <linux/pci.h>
  2101. +#include <linux/ath9k_platform.h>
  2102. +#include <linux/delay.h>
  2103. +
  2104. +#include <asm/mach-ath79/ath79.h>
  2105. +
  2106. +#include "dev-ap9x-pci.h"
  2107. +#include "pci-ath9k-fixup.h"
  2108. +#include "pci.h"
  2109. +
  2110. +static struct ath9k_platform_data ap9x_wmac0_data = {
  2111. + .led_pin = -1,
  2112. +};
  2113. +static struct ath9k_platform_data ap9x_wmac1_data = {
  2114. + .led_pin = -1,
  2115. +};
  2116. +static char ap9x_wmac0_mac[6];
  2117. +static char ap9x_wmac1_mac[6];
  2118. +
  2119. +__init void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin)
  2120. +{
  2121. + switch (wmac) {
  2122. + case 0:
  2123. + ap9x_wmac0_data.led_pin = pin;
  2124. + break;
  2125. + case 1:
  2126. + ap9x_wmac1_data.led_pin = pin;
  2127. + break;
  2128. + }
  2129. +}
  2130. +
  2131. +__init struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac)
  2132. +{
  2133. + switch (wmac) {
  2134. + case 0:
  2135. + return &ap9x_wmac0_data;
  2136. +
  2137. + case 1:
  2138. + return &ap9x_wmac1_data;
  2139. + }
  2140. +
  2141. + return NULL;
  2142. +}
  2143. +
  2144. +__init void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val)
  2145. +{
  2146. + switch (wmac) {
  2147. + case 0:
  2148. + ap9x_wmac0_data.gpio_mask = mask;
  2149. + ap9x_wmac0_data.gpio_val = val;
  2150. + break;
  2151. + case 1:
  2152. + ap9x_wmac1_data.gpio_mask = mask;
  2153. + ap9x_wmac1_data.gpio_val = val;
  2154. + break;
  2155. + }
  2156. +}
  2157. +
  2158. +__init void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds,
  2159. + int num_leds)
  2160. +{
  2161. + switch (wmac) {
  2162. + case 0:
  2163. + ap9x_wmac0_data.leds = leds;
  2164. + ap9x_wmac0_data.num_leds = num_leds;
  2165. + break;
  2166. + case 1:
  2167. + ap9x_wmac1_data.leds = leds;
  2168. + ap9x_wmac1_data.num_leds = num_leds;
  2169. + break;
  2170. + }
  2171. +}
  2172. +
  2173. +static int ap91_pci_plat_dev_init(struct pci_dev *dev)
  2174. +{
  2175. + switch (PCI_SLOT(dev->devfn)) {
  2176. + case 0:
  2177. + dev->dev.platform_data = &ap9x_wmac0_data;
  2178. + break;
  2179. + }
  2180. +
  2181. + return 0;
  2182. +}
  2183. +
  2184. +__init void ap91_pci_init(u8 *cal_data, u8 *mac_addr)
  2185. +{
  2186. + if (cal_data)
  2187. + memcpy(ap9x_wmac0_data.eeprom_data, cal_data,
  2188. + sizeof(ap9x_wmac0_data.eeprom_data));
  2189. +
  2190. + if (mac_addr) {
  2191. + memcpy(ap9x_wmac0_mac, mac_addr, sizeof(ap9x_wmac0_mac));
  2192. + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
  2193. + }
  2194. +
  2195. + ath79_pci_set_plat_dev_init(ap91_pci_plat_dev_init);
  2196. + ath79_register_pci();
  2197. +
  2198. + pci_enable_ath9k_fixup(0, ap9x_wmac0_data.eeprom_data);
  2199. +}
  2200. +
  2201. +__init void ap91_pci_init_simple(void)
  2202. +{
  2203. + ap91_pci_init(NULL, NULL);
  2204. + ap9x_wmac0_data.eeprom_name = "pci_wmac0.eeprom";
  2205. +}
  2206. +
  2207. +static int ap94_pci_plat_dev_init(struct pci_dev *dev)
  2208. +{
  2209. + switch (PCI_SLOT(dev->devfn)) {
  2210. + case 17:
  2211. + dev->dev.platform_data = &ap9x_wmac0_data;
  2212. + break;
  2213. +
  2214. + case 18:
  2215. + dev->dev.platform_data = &ap9x_wmac1_data;
  2216. + break;
  2217. + }
  2218. +
  2219. + return 0;
  2220. +}
  2221. +
  2222. +__init void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
  2223. + u8 *cal_data1, u8 *mac_addr1)
  2224. +{
  2225. + if (cal_data0)
  2226. + memcpy(ap9x_wmac0_data.eeprom_data, cal_data0,
  2227. + sizeof(ap9x_wmac0_data.eeprom_data));
  2228. +
  2229. + if (cal_data1)
  2230. + memcpy(ap9x_wmac1_data.eeprom_data, cal_data1,
  2231. + sizeof(ap9x_wmac1_data.eeprom_data));
  2232. +
  2233. + if (mac_addr0) {
  2234. + memcpy(ap9x_wmac0_mac, mac_addr0, sizeof(ap9x_wmac0_mac));
  2235. + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
  2236. + }
  2237. +
  2238. + if (mac_addr1) {
  2239. + memcpy(ap9x_wmac1_mac, mac_addr1, sizeof(ap9x_wmac1_mac));
  2240. + ap9x_wmac1_data.macaddr = ap9x_wmac1_mac;
  2241. + }
  2242. +
  2243. + ath79_pci_set_plat_dev_init(ap94_pci_plat_dev_init);
  2244. + ath79_register_pci();
  2245. +
  2246. + pci_enable_ath9k_fixup(17, ap9x_wmac0_data.eeprom_data);
  2247. + pci_enable_ath9k_fixup(18, ap9x_wmac1_data.eeprom_data);
  2248. +}
  2249. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-ap9x-pci.h linux-4.1.43/arch/mips/ath79/dev-ap9x-pci.h
  2250. --- linux-4.1.43.orig/arch/mips/ath79/dev-ap9x-pci.h 1970-01-01 01:00:00.000000000 +0100
  2251. +++ linux-4.1.43/arch/mips/ath79/dev-ap9x-pci.h 2017-08-06 20:02:15.000000000 +0200
  2252. @@ -0,0 +1,48 @@
  2253. +/*
  2254. + * Atheros AP9X reference board PCI initialization
  2255. + *
  2256. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  2257. + *
  2258. + * This program is free software; you can redistribute it and/or modify it
  2259. + * under the terms of the GNU General Public License version 2 as published
  2260. + * by the Free Software Foundation.
  2261. + */
  2262. +
  2263. +#ifndef _ATH79_DEV_AP9X_PCI_H
  2264. +#define _ATH79_DEV_AP9X_PCI_H
  2265. +
  2266. +struct gpio_led;
  2267. +struct ath9k_platform_data;
  2268. +
  2269. +#if defined(CONFIG_ATH79_DEV_AP9X_PCI)
  2270. +void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin);
  2271. +void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val);
  2272. +void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds,
  2273. + int num_leds);
  2274. +struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac);
  2275. +
  2276. +void ap91_pci_init(u8 *cal_data, u8 *mac_addr);
  2277. +void ap91_pci_init_simple(void);
  2278. +void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
  2279. + u8 *cal_data1, u8 *mac_addr1);
  2280. +
  2281. +#else
  2282. +static inline void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) {}
  2283. +static inline void ap9x_pci_setup_wmac_gpio(unsigned wmac,
  2284. + u32 mask, u32 val) {}
  2285. +static inline void ap9x_pci_setup_wmac_leds(unsigned wmac,
  2286. + struct gpio_led *leds,
  2287. + int num_leds) {}
  2288. +static inline struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac)
  2289. +{
  2290. + return NULL;
  2291. +}
  2292. +
  2293. +static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) {}
  2294. +static inline void ap91_pci_init_simple(void) {}
  2295. +static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
  2296. + u8 *cal_data1, u8 *mac_addr1) {}
  2297. +#endif
  2298. +
  2299. +#endif /* _ATH79_DEV_AP9X_PCI_H */
  2300. +
  2301. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-common.c linux-4.1.43/arch/mips/ath79/dev-common.c
  2302. --- linux-4.1.43.orig/arch/mips/ath79/dev-common.c 2017-08-06 01:56:14.000000000 +0200
  2303. +++ linux-4.1.43/arch/mips/ath79/dev-common.c 2017-08-06 20:02:15.000000000 +0200
  2304. @@ -80,11 +80,22 @@
  2305. uart_clk_rate = ath79_get_sys_clk_rate("uart");
  2306. + if (soc_is_ar71xx())
  2307. + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
  2308. + else if (soc_is_ar724x())
  2309. + ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
  2310. + else if (soc_is_ar913x())
  2311. + ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
  2312. + else if (soc_is_ar933x())
  2313. + ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
  2314. +
  2315. if (soc_is_ar71xx() ||
  2316. soc_is_ar724x() ||
  2317. soc_is_ar913x() ||
  2318. soc_is_ar934x() ||
  2319. - soc_is_qca955x()) {
  2320. + soc_is_qca953x() ||
  2321. + soc_is_qca955x() ||
  2322. + soc_is_qca956x()) {
  2323. ath79_uart_data[0].uartclk = uart_clk_rate;
  2324. platform_device_register(&ath79_uart_device);
  2325. } else if (soc_is_ar933x()) {
  2326. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-dsa.c linux-4.1.43/arch/mips/ath79/dev-dsa.c
  2327. --- linux-4.1.43.orig/arch/mips/ath79/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100
  2328. +++ linux-4.1.43/arch/mips/ath79/dev-dsa.c 2017-08-06 20:02:15.000000000 +0200
  2329. @@ -0,0 +1,41 @@
  2330. +/*
  2331. + * Atheros AR71xx DSA switch device support
  2332. + *
  2333. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  2334. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  2335. + *
  2336. + * This program is free software; you can redistribute it and/or modify it
  2337. + * under the terms of the GNU General Public License version 2 as published
  2338. + * by the Free Software Foundation.
  2339. + */
  2340. +
  2341. +#include <linux/init.h>
  2342. +#include <linux/version.h>
  2343. +#include <linux/platform_device.h>
  2344. +
  2345. +#include <asm/mach-ath79/ath79.h>
  2346. +
  2347. +#include "dev-dsa.h"
  2348. +
  2349. +static struct platform_device ar71xx_dsa_switch_device = {
  2350. + .name = "dsa",
  2351. + .id = 0,
  2352. +};
  2353. +
  2354. +void __init ath79_register_dsa(struct device *netdev,
  2355. + struct device *miidev,
  2356. + struct dsa_platform_data *d)
  2357. +{
  2358. + int i;
  2359. +
  2360. + d->netdev = netdev;
  2361. + for (i = 0; i < d->nr_chips; i++)
  2362. +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
  2363. + d->chip[i].mii_bus = miidev;
  2364. +#else
  2365. + d->chip[i].host_dev = miidev;
  2366. +#endif
  2367. +
  2368. + ar71xx_dsa_switch_device.dev.platform_data = d;
  2369. + platform_device_register(&ar71xx_dsa_switch_device);
  2370. +}
  2371. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-dsa.h linux-4.1.43/arch/mips/ath79/dev-dsa.h
  2372. --- linux-4.1.43.orig/arch/mips/ath79/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100
  2373. +++ linux-4.1.43/arch/mips/ath79/dev-dsa.h 2017-08-06 20:02:15.000000000 +0200
  2374. @@ -0,0 +1,21 @@
  2375. +/*
  2376. + * Atheros AR71xx DSA switch device support
  2377. + *
  2378. + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  2379. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  2380. + *
  2381. + * This program is free software; you can redistribute it and/or modify it
  2382. + * under the terms of the GNU General Public License version 2 as published
  2383. + * by the Free Software Foundation.
  2384. + */
  2385. +
  2386. +#ifndef _ATH79_DEV_DSA_H
  2387. +#define _ATH79_DEV_DSA_H
  2388. +
  2389. +#include <net/dsa.h>
  2390. +
  2391. +void ath79_register_dsa(struct device *netdev,
  2392. + struct device *miidev,
  2393. + struct dsa_platform_data *d);
  2394. +
  2395. +#endif /* _ATH79_DEV_DSA_H */
  2396. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-eth.c linux-4.1.43/arch/mips/ath79/dev-eth.c
  2397. --- linux-4.1.43.orig/arch/mips/ath79/dev-eth.c 1970-01-01 01:00:00.000000000 +0100
  2398. +++ linux-4.1.43/arch/mips/ath79/dev-eth.c 2017-08-06 20:02:15.000000000 +0200
  2399. @@ -0,0 +1,1254 @@
  2400. +/*
  2401. + * Atheros AR71xx SoC platform devices
  2402. + *
  2403. + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  2404. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  2405. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  2406. + *
  2407. + * Parts of this file are based on Atheros 2.6.15 BSP
  2408. + * Parts of this file are based on Atheros 2.6.31 BSP
  2409. + *
  2410. + * This program is free software; you can redistribute it and/or modify it
  2411. + * under the terms of the GNU General Public License version 2 as published
  2412. + * by the Free Software Foundation.
  2413. + */
  2414. +
  2415. +#include <linux/kernel.h>
  2416. +#include <linux/init.h>
  2417. +#include <linux/delay.h>
  2418. +#include <linux/etherdevice.h>
  2419. +#include <linux/platform_device.h>
  2420. +#include <linux/serial_8250.h>
  2421. +#include <linux/clk.h>
  2422. +#include <linux/sizes.h>
  2423. +
  2424. +#include <asm/mach-ath79/ath79.h>
  2425. +#include <asm/mach-ath79/ar71xx_regs.h>
  2426. +#include <asm/mach-ath79/irq.h>
  2427. +
  2428. +#include "common.h"
  2429. +#include "dev-eth.h"
  2430. +
  2431. +unsigned char ath79_mac_base[ETH_ALEN] __initdata;
  2432. +
  2433. +static struct resource ath79_mdio0_resources[] = {
  2434. + {
  2435. + .name = "mdio_base",
  2436. + .flags = IORESOURCE_MEM,
  2437. + .start = AR71XX_GE0_BASE,
  2438. + .end = AR71XX_GE0_BASE + 0x200 - 1,
  2439. + }
  2440. +};
  2441. +
  2442. +struct ag71xx_mdio_platform_data ath79_mdio0_data;
  2443. +
  2444. +struct platform_device ath79_mdio0_device = {
  2445. + .name = "ag71xx-mdio",
  2446. + .id = 0,
  2447. + .resource = ath79_mdio0_resources,
  2448. + .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
  2449. + .dev = {
  2450. + .platform_data = &ath79_mdio0_data,
  2451. + },
  2452. +};
  2453. +
  2454. +static struct resource ath79_mdio1_resources[] = {
  2455. + {
  2456. + .name = "mdio_base",
  2457. + .flags = IORESOURCE_MEM,
  2458. + .start = AR71XX_GE1_BASE,
  2459. + .end = AR71XX_GE1_BASE + 0x200 - 1,
  2460. + }
  2461. +};
  2462. +
  2463. +struct ag71xx_mdio_platform_data ath79_mdio1_data;
  2464. +
  2465. +struct platform_device ath79_mdio1_device = {
  2466. + .name = "ag71xx-mdio",
  2467. + .id = 1,
  2468. + .resource = ath79_mdio1_resources,
  2469. + .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
  2470. + .dev = {
  2471. + .platform_data = &ath79_mdio1_data,
  2472. + },
  2473. +};
  2474. +
  2475. +static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
  2476. +{
  2477. + void __iomem *base;
  2478. + u32 t;
  2479. +
  2480. + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  2481. +
  2482. + t = __raw_readl(base + cfg_reg);
  2483. + t &= ~(3 << shift);
  2484. + t |= (2 << shift);
  2485. + __raw_writel(t, base + cfg_reg);
  2486. + udelay(100);
  2487. +
  2488. + __raw_writel(pll_val, base + pll_reg);
  2489. +
  2490. + t |= (3 << shift);
  2491. + __raw_writel(t, base + cfg_reg);
  2492. + udelay(100);
  2493. +
  2494. + t &= ~(3 << shift);
  2495. + __raw_writel(t, base + cfg_reg);
  2496. + udelay(100);
  2497. +
  2498. + printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
  2499. + (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
  2500. +
  2501. + iounmap(base);
  2502. +}
  2503. +
  2504. +static void __init ath79_mii_ctrl_set_if(unsigned int reg,
  2505. + unsigned int mii_if)
  2506. +{
  2507. + void __iomem *base;
  2508. + u32 t;
  2509. +
  2510. + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
  2511. +
  2512. + t = __raw_readl(base + reg);
  2513. + t &= ~(AR71XX_MII_CTRL_IF_MASK);
  2514. + t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
  2515. + __raw_writel(t, base + reg);
  2516. +
  2517. + iounmap(base);
  2518. +}
  2519. +
  2520. +static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
  2521. +{
  2522. + void __iomem *base;
  2523. + unsigned int mii_speed;
  2524. + u32 t;
  2525. +
  2526. + switch (speed) {
  2527. + case SPEED_10:
  2528. + mii_speed = AR71XX_MII_CTRL_SPEED_10;
  2529. + break;
  2530. + case SPEED_100:
  2531. + mii_speed = AR71XX_MII_CTRL_SPEED_100;
  2532. + break;
  2533. + case SPEED_1000:
  2534. + mii_speed = AR71XX_MII_CTRL_SPEED_1000;
  2535. + break;
  2536. + default:
  2537. + BUG();
  2538. + }
  2539. +
  2540. + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
  2541. +
  2542. + t = __raw_readl(base + reg);
  2543. + t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
  2544. + t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
  2545. + __raw_writel(t, base + reg);
  2546. +
  2547. + iounmap(base);
  2548. +}
  2549. +
  2550. +static unsigned long ar934x_get_mdio_ref_clock(void)
  2551. +{
  2552. + void __iomem *base;
  2553. + unsigned long ret;
  2554. + u32 t;
  2555. +
  2556. + base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  2557. +
  2558. + ret = 0;
  2559. + t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
  2560. + if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
  2561. + ret = 100 * 1000 * 1000;
  2562. + } else {
  2563. + struct clk *clk;
  2564. +
  2565. + clk = clk_get(NULL, "ref");
  2566. + if (!IS_ERR(clk))
  2567. + ret = clk_get_rate(clk);
  2568. + }
  2569. +
  2570. + iounmap(base);
  2571. +
  2572. + return ret;
  2573. +}
  2574. +
  2575. +void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  2576. +{
  2577. + struct platform_device *mdio_dev;
  2578. + struct ag71xx_mdio_platform_data *mdio_data;
  2579. + unsigned int max_id;
  2580. +
  2581. + if (ath79_soc == ATH79_SOC_AR9341 ||
  2582. + ath79_soc == ATH79_SOC_AR9342 ||
  2583. + ath79_soc == ATH79_SOC_AR9344 ||
  2584. + ath79_soc == ATH79_SOC_QCA9556 ||
  2585. + ath79_soc == ATH79_SOC_QCA9558)
  2586. + max_id = 1;
  2587. + else
  2588. + max_id = 0;
  2589. +
  2590. + if (id > max_id) {
  2591. + printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
  2592. + return;
  2593. + }
  2594. +
  2595. + switch (ath79_soc) {
  2596. + case ATH79_SOC_AR7241:
  2597. + case ATH79_SOC_AR9330:
  2598. + case ATH79_SOC_AR9331:
  2599. + case ATH79_SOC_QCA9533:
  2600. + case ATH79_SOC_QCA9561:
  2601. + case ATH79_SOC_TP9343:
  2602. + mdio_dev = &ath79_mdio1_device;
  2603. + mdio_data = &ath79_mdio1_data;
  2604. + break;
  2605. +
  2606. + case ATH79_SOC_AR9341:
  2607. + case ATH79_SOC_AR9342:
  2608. + case ATH79_SOC_AR9344:
  2609. + case ATH79_SOC_QCA9556:
  2610. + case ATH79_SOC_QCA9558:
  2611. + if (id == 0) {
  2612. + mdio_dev = &ath79_mdio0_device;
  2613. + mdio_data = &ath79_mdio0_data;
  2614. + } else {
  2615. + mdio_dev = &ath79_mdio1_device;
  2616. + mdio_data = &ath79_mdio1_data;
  2617. + }
  2618. + break;
  2619. +
  2620. + case ATH79_SOC_AR7242:
  2621. + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
  2622. + AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
  2623. + AR71XX_ETH0_PLL_SHIFT);
  2624. + /* fall through */
  2625. + default:
  2626. + mdio_dev = &ath79_mdio0_device;
  2627. + mdio_data = &ath79_mdio0_data;
  2628. + break;
  2629. + }
  2630. +
  2631. + mdio_data->phy_mask = phy_mask;
  2632. +
  2633. + switch (ath79_soc) {
  2634. + case ATH79_SOC_AR7240:
  2635. + mdio_data->is_ar7240 = 1;
  2636. + /* fall through */
  2637. + case ATH79_SOC_AR7241:
  2638. + mdio_data->builtin_switch = 1;
  2639. + break;
  2640. +
  2641. + case ATH79_SOC_AR9330:
  2642. + mdio_data->is_ar9330 = 1;
  2643. + /* fall through */
  2644. + case ATH79_SOC_AR9331:
  2645. + mdio_data->builtin_switch = 1;
  2646. + break;
  2647. +
  2648. + case ATH79_SOC_AR9341:
  2649. + case ATH79_SOC_AR9342:
  2650. + case ATH79_SOC_AR9344:
  2651. + if (id == 1) {
  2652. + mdio_data->builtin_switch = 1;
  2653. + mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
  2654. + mdio_data->mdio_clock = 6250000;
  2655. + }
  2656. + mdio_data->is_ar934x = 1;
  2657. + break;
  2658. +
  2659. + case ATH79_SOC_QCA9533:
  2660. + case ATH79_SOC_QCA9561:
  2661. + case ATH79_SOC_TP9343:
  2662. + mdio_data->builtin_switch = 1;
  2663. + break;
  2664. +
  2665. + case ATH79_SOC_QCA9556:
  2666. + case ATH79_SOC_QCA9558:
  2667. + mdio_data->is_ar934x = 1;
  2668. + break;
  2669. +
  2670. + default:
  2671. + break;
  2672. + }
  2673. +
  2674. + platform_device_register(mdio_dev);
  2675. +}
  2676. +
  2677. +struct ath79_eth_pll_data ath79_eth0_pll_data;
  2678. +struct ath79_eth_pll_data ath79_eth1_pll_data;
  2679. +
  2680. +static u32 ath79_get_eth_pll(unsigned int mac, int speed)
  2681. +{
  2682. + struct ath79_eth_pll_data *pll_data;
  2683. + u32 pll_val;
  2684. +
  2685. + switch (mac) {
  2686. + case 0:
  2687. + pll_data = &ath79_eth0_pll_data;
  2688. + break;
  2689. + case 1:
  2690. + pll_data = &ath79_eth1_pll_data;
  2691. + break;
  2692. + default:
  2693. + BUG();
  2694. + }
  2695. +
  2696. + switch (speed) {
  2697. + case SPEED_10:
  2698. + pll_val = pll_data->pll_10;
  2699. + break;
  2700. + case SPEED_100:
  2701. + pll_val = pll_data->pll_100;
  2702. + break;
  2703. + case SPEED_1000:
  2704. + pll_val = pll_data->pll_1000;
  2705. + break;
  2706. + default:
  2707. + BUG();
  2708. + }
  2709. +
  2710. + return pll_val;
  2711. +}
  2712. +
  2713. +static void ath79_set_speed_ge0(int speed)
  2714. +{
  2715. + u32 val = ath79_get_eth_pll(0, speed);
  2716. +
  2717. + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
  2718. + val, AR71XX_ETH0_PLL_SHIFT);
  2719. + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
  2720. +}
  2721. +
  2722. +static void ath79_set_speed_ge1(int speed)
  2723. +{
  2724. + u32 val = ath79_get_eth_pll(1, speed);
  2725. +
  2726. + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
  2727. + val, AR71XX_ETH1_PLL_SHIFT);
  2728. + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
  2729. +}
  2730. +
  2731. +static void ar7242_set_speed_ge0(int speed)
  2732. +{
  2733. + u32 val = ath79_get_eth_pll(0, speed);
  2734. + void __iomem *base;
  2735. +
  2736. + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  2737. + __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
  2738. + iounmap(base);
  2739. +}
  2740. +
  2741. +static void ar91xx_set_speed_ge0(int speed)
  2742. +{
  2743. + u32 val = ath79_get_eth_pll(0, speed);
  2744. +
  2745. + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
  2746. + val, AR913X_ETH0_PLL_SHIFT);
  2747. + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
  2748. +}
  2749. +
  2750. +static void ar91xx_set_speed_ge1(int speed)
  2751. +{
  2752. + u32 val = ath79_get_eth_pll(1, speed);
  2753. +
  2754. + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
  2755. + val, AR913X_ETH1_PLL_SHIFT);
  2756. + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
  2757. +}
  2758. +
  2759. +static void ar934x_set_speed_ge0(int speed)
  2760. +{
  2761. + void __iomem *base;
  2762. + u32 val = ath79_get_eth_pll(0, speed);
  2763. +
  2764. + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  2765. + __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
  2766. + iounmap(base);
  2767. +}
  2768. +
  2769. +static void qca955x_set_speed_xmii(int speed)
  2770. +{
  2771. + void __iomem *base;
  2772. + u32 val = ath79_get_eth_pll(0, speed);
  2773. +
  2774. + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  2775. + __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
  2776. + iounmap(base);
  2777. +}
  2778. +
  2779. +static void qca955x_set_speed_sgmii(int speed)
  2780. +{
  2781. + void __iomem *base;
  2782. + u32 val = ath79_get_eth_pll(1, speed);
  2783. +
  2784. + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  2785. + __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
  2786. + iounmap(base);
  2787. +}
  2788. +
  2789. +static void ath79_set_speed_dummy(int speed)
  2790. +{
  2791. +}
  2792. +
  2793. +static void ath79_ddr_no_flush(void)
  2794. +{
  2795. +}
  2796. +
  2797. +static void ath79_ddr_flush_ge0(void)
  2798. +{
  2799. + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
  2800. +}
  2801. +
  2802. +static void ath79_ddr_flush_ge1(void)
  2803. +{
  2804. + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
  2805. +}
  2806. +
  2807. +static void ar724x_ddr_flush_ge0(void)
  2808. +{
  2809. + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
  2810. +}
  2811. +
  2812. +static void ar724x_ddr_flush_ge1(void)
  2813. +{
  2814. + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
  2815. +}
  2816. +
  2817. +static void ar91xx_ddr_flush_ge0(void)
  2818. +{
  2819. + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
  2820. +}
  2821. +
  2822. +static void ar91xx_ddr_flush_ge1(void)
  2823. +{
  2824. + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
  2825. +}
  2826. +
  2827. +static void ar933x_ddr_flush_ge0(void)
  2828. +{
  2829. + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
  2830. +}
  2831. +
  2832. +static void ar933x_ddr_flush_ge1(void)
  2833. +{
  2834. + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
  2835. +}
  2836. +
  2837. +static struct resource ath79_eth0_resources[] = {
  2838. + {
  2839. + .name = "mac_base",
  2840. + .flags = IORESOURCE_MEM,
  2841. + .start = AR71XX_GE0_BASE,
  2842. + .end = AR71XX_GE0_BASE + 0x200 - 1,
  2843. + }, {
  2844. + .name = "mac_irq",
  2845. + .flags = IORESOURCE_IRQ,
  2846. + .start = ATH79_CPU_IRQ(4),
  2847. + .end = ATH79_CPU_IRQ(4),
  2848. + },
  2849. +};
  2850. +
  2851. +struct ag71xx_platform_data ath79_eth0_data = {
  2852. + .reset_bit = AR71XX_RESET_GE0_MAC,
  2853. +};
  2854. +
  2855. +struct platform_device ath79_eth0_device = {
  2856. + .name = "ag71xx",
  2857. + .id = 0,
  2858. + .resource = ath79_eth0_resources,
  2859. + .num_resources = ARRAY_SIZE(ath79_eth0_resources),
  2860. + .dev = {
  2861. + .platform_data = &ath79_eth0_data,
  2862. + },
  2863. +};
  2864. +
  2865. +static struct resource ath79_eth1_resources[] = {
  2866. + {
  2867. + .name = "mac_base",
  2868. + .flags = IORESOURCE_MEM,
  2869. + .start = AR71XX_GE1_BASE,
  2870. + .end = AR71XX_GE1_BASE + 0x200 - 1,
  2871. + }, {
  2872. + .name = "mac_irq",
  2873. + .flags = IORESOURCE_IRQ,
  2874. + .start = ATH79_CPU_IRQ(5),
  2875. + .end = ATH79_CPU_IRQ(5),
  2876. + },
  2877. +};
  2878. +
  2879. +struct ag71xx_platform_data ath79_eth1_data = {
  2880. + .reset_bit = AR71XX_RESET_GE1_MAC,
  2881. +};
  2882. +
  2883. +struct platform_device ath79_eth1_device = {
  2884. + .name = "ag71xx",
  2885. + .id = 1,
  2886. + .resource = ath79_eth1_resources,
  2887. + .num_resources = ARRAY_SIZE(ath79_eth1_resources),
  2888. + .dev = {
  2889. + .platform_data = &ath79_eth1_data,
  2890. + },
  2891. +};
  2892. +
  2893. +struct ag71xx_switch_platform_data ath79_switch_data;
  2894. +
  2895. +#define AR71XX_PLL_VAL_1000 0x00110000
  2896. +#define AR71XX_PLL_VAL_100 0x00001099
  2897. +#define AR71XX_PLL_VAL_10 0x00991099
  2898. +
  2899. +#define AR724X_PLL_VAL_1000 0x00110000
  2900. +#define AR724X_PLL_VAL_100 0x00001099
  2901. +#define AR724X_PLL_VAL_10 0x00991099
  2902. +
  2903. +#define AR7242_PLL_VAL_1000 0x16000000
  2904. +#define AR7242_PLL_VAL_100 0x00000101
  2905. +#define AR7242_PLL_VAL_10 0x00001616
  2906. +
  2907. +#define AR913X_PLL_VAL_1000 0x1a000000
  2908. +#define AR913X_PLL_VAL_100 0x13000a44
  2909. +#define AR913X_PLL_VAL_10 0x00441099
  2910. +
  2911. +#define AR933X_PLL_VAL_1000 0x00110000
  2912. +#define AR933X_PLL_VAL_100 0x00001099
  2913. +#define AR933X_PLL_VAL_10 0x00991099
  2914. +
  2915. +#define AR934X_PLL_VAL_1000 0x16000000
  2916. +#define AR934X_PLL_VAL_100 0x00000101
  2917. +#define AR934X_PLL_VAL_10 0x00001616
  2918. +
  2919. +static void __init ath79_init_eth_pll_data(unsigned int id)
  2920. +{
  2921. + struct ath79_eth_pll_data *pll_data;
  2922. + u32 pll_10, pll_100, pll_1000;
  2923. +
  2924. + switch (id) {
  2925. + case 0:
  2926. + pll_data = &ath79_eth0_pll_data;
  2927. + break;
  2928. + case 1:
  2929. + pll_data = &ath79_eth1_pll_data;
  2930. + break;
  2931. + default:
  2932. + BUG();
  2933. + }
  2934. +
  2935. + switch (ath79_soc) {
  2936. + case ATH79_SOC_AR7130:
  2937. + case ATH79_SOC_AR7141:
  2938. + case ATH79_SOC_AR7161:
  2939. + pll_10 = AR71XX_PLL_VAL_10;
  2940. + pll_100 = AR71XX_PLL_VAL_100;
  2941. + pll_1000 = AR71XX_PLL_VAL_1000;
  2942. + break;
  2943. +
  2944. + case ATH79_SOC_AR7240:
  2945. + case ATH79_SOC_AR7241:
  2946. + pll_10 = AR724X_PLL_VAL_10;
  2947. + pll_100 = AR724X_PLL_VAL_100;
  2948. + pll_1000 = AR724X_PLL_VAL_1000;
  2949. + break;
  2950. +
  2951. + case ATH79_SOC_AR7242:
  2952. + pll_10 = AR7242_PLL_VAL_10;
  2953. + pll_100 = AR7242_PLL_VAL_100;
  2954. + pll_1000 = AR7242_PLL_VAL_1000;
  2955. + break;
  2956. +
  2957. + case ATH79_SOC_AR9130:
  2958. + case ATH79_SOC_AR9132:
  2959. + pll_10 = AR913X_PLL_VAL_10;
  2960. + pll_100 = AR913X_PLL_VAL_100;
  2961. + pll_1000 = AR913X_PLL_VAL_1000;
  2962. + break;
  2963. +
  2964. + case ATH79_SOC_AR9330:
  2965. + case ATH79_SOC_AR9331:
  2966. + pll_10 = AR933X_PLL_VAL_10;
  2967. + pll_100 = AR933X_PLL_VAL_100;
  2968. + pll_1000 = AR933X_PLL_VAL_1000;
  2969. + break;
  2970. +
  2971. + case ATH79_SOC_AR9341:
  2972. + case ATH79_SOC_AR9342:
  2973. + case ATH79_SOC_AR9344:
  2974. + case ATH79_SOC_QCA9533:
  2975. + case ATH79_SOC_QCA9556:
  2976. + case ATH79_SOC_QCA9558:
  2977. + case ATH79_SOC_QCA9561:
  2978. + case ATH79_SOC_TP9343:
  2979. + pll_10 = AR934X_PLL_VAL_10;
  2980. + pll_100 = AR934X_PLL_VAL_100;
  2981. + pll_1000 = AR934X_PLL_VAL_1000;
  2982. + break;
  2983. +
  2984. + default:
  2985. + BUG();
  2986. + }
  2987. +
  2988. + if (!pll_data->pll_10)
  2989. + pll_data->pll_10 = pll_10;
  2990. +
  2991. + if (!pll_data->pll_100)
  2992. + pll_data->pll_100 = pll_100;
  2993. +
  2994. + if (!pll_data->pll_1000)
  2995. + pll_data->pll_1000 = pll_1000;
  2996. +}
  2997. +
  2998. +static int __init ath79_setup_phy_if_mode(unsigned int id,
  2999. + struct ag71xx_platform_data *pdata)
  3000. +{
  3001. + unsigned int mii_if;
  3002. +
  3003. + switch (id) {
  3004. + case 0:
  3005. + switch (ath79_soc) {
  3006. + case ATH79_SOC_AR7130:
  3007. + case ATH79_SOC_AR7141:
  3008. + case ATH79_SOC_AR7161:
  3009. + case ATH79_SOC_AR9130:
  3010. + case ATH79_SOC_AR9132:
  3011. + switch (pdata->phy_if_mode) {
  3012. + case PHY_INTERFACE_MODE_MII:
  3013. + mii_if = AR71XX_MII0_CTRL_IF_MII;
  3014. + break;
  3015. + case PHY_INTERFACE_MODE_GMII:
  3016. + mii_if = AR71XX_MII0_CTRL_IF_GMII;
  3017. + break;
  3018. + case PHY_INTERFACE_MODE_RGMII:
  3019. + mii_if = AR71XX_MII0_CTRL_IF_RGMII;
  3020. + break;
  3021. + case PHY_INTERFACE_MODE_RMII:
  3022. + mii_if = AR71XX_MII0_CTRL_IF_RMII;
  3023. + break;
  3024. + default:
  3025. + return -EINVAL;
  3026. + }
  3027. + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
  3028. + break;
  3029. +
  3030. + case ATH79_SOC_AR7240:
  3031. + case ATH79_SOC_AR7241:
  3032. + case ATH79_SOC_AR9330:
  3033. + case ATH79_SOC_AR9331:
  3034. + case ATH79_SOC_QCA9533:
  3035. + case ATH79_SOC_TP9343:
  3036. + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
  3037. + break;
  3038. +
  3039. + case ATH79_SOC_AR7242:
  3040. + /* FIXME */
  3041. +
  3042. + case ATH79_SOC_AR9341:
  3043. + case ATH79_SOC_AR9342:
  3044. + case ATH79_SOC_AR9344:
  3045. + switch (pdata->phy_if_mode) {
  3046. + case PHY_INTERFACE_MODE_MII:
  3047. + case PHY_INTERFACE_MODE_GMII:
  3048. + case PHY_INTERFACE_MODE_RGMII:
  3049. + case PHY_INTERFACE_MODE_RMII:
  3050. + break;
  3051. + default:
  3052. + return -EINVAL;
  3053. + }
  3054. + break;
  3055. +
  3056. + case ATH79_SOC_QCA9556:
  3057. + case ATH79_SOC_QCA9558:
  3058. + switch (pdata->phy_if_mode) {
  3059. + case PHY_INTERFACE_MODE_MII:
  3060. + case PHY_INTERFACE_MODE_RGMII:
  3061. + case PHY_INTERFACE_MODE_SGMII:
  3062. + break;
  3063. + default:
  3064. + return -EINVAL;
  3065. + }
  3066. + break;
  3067. +
  3068. + case ATH79_SOC_QCA9561:
  3069. + if (!pdata->phy_if_mode)
  3070. + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
  3071. + break;
  3072. +
  3073. + default:
  3074. + BUG();
  3075. + }
  3076. + break;
  3077. + case 1:
  3078. + switch (ath79_soc) {
  3079. + case ATH79_SOC_AR7130:
  3080. + case ATH79_SOC_AR7141:
  3081. + case ATH79_SOC_AR7161:
  3082. + case ATH79_SOC_AR9130:
  3083. + case ATH79_SOC_AR9132:
  3084. + switch (pdata->phy_if_mode) {
  3085. + case PHY_INTERFACE_MODE_RMII:
  3086. + mii_if = AR71XX_MII1_CTRL_IF_RMII;
  3087. + break;
  3088. + case PHY_INTERFACE_MODE_RGMII:
  3089. + mii_if = AR71XX_MII1_CTRL_IF_RGMII;
  3090. + break;
  3091. + default:
  3092. + return -EINVAL;
  3093. + }
  3094. + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
  3095. + break;
  3096. +
  3097. + case ATH79_SOC_AR7240:
  3098. + case ATH79_SOC_AR7241:
  3099. + case ATH79_SOC_AR9330:
  3100. + case ATH79_SOC_AR9331:
  3101. + case ATH79_SOC_QCA9561:
  3102. + case ATH79_SOC_TP9343:
  3103. + pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
  3104. + break;
  3105. +
  3106. + case ATH79_SOC_AR7242:
  3107. + /* FIXME */
  3108. +
  3109. + case ATH79_SOC_AR9341:
  3110. + case ATH79_SOC_AR9342:
  3111. + case ATH79_SOC_AR9344:
  3112. + case ATH79_SOC_QCA9533:
  3113. + switch (pdata->phy_if_mode) {
  3114. + case PHY_INTERFACE_MODE_MII:
  3115. + case PHY_INTERFACE_MODE_GMII:
  3116. + break;
  3117. + default:
  3118. + return -EINVAL;
  3119. + }
  3120. + break;
  3121. +
  3122. + case ATH79_SOC_QCA9556:
  3123. + case ATH79_SOC_QCA9558:
  3124. + switch (pdata->phy_if_mode) {
  3125. + case PHY_INTERFACE_MODE_MII:
  3126. + case PHY_INTERFACE_MODE_RGMII:
  3127. + case PHY_INTERFACE_MODE_SGMII:
  3128. + break;
  3129. + default:
  3130. + return -EINVAL;
  3131. + }
  3132. + break;
  3133. +
  3134. + default:
  3135. + BUG();
  3136. + }
  3137. + break;
  3138. + }
  3139. +
  3140. + return 0;
  3141. +}
  3142. +
  3143. +void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
  3144. +{
  3145. + void __iomem *base;
  3146. + u32 t;
  3147. +
  3148. + base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
  3149. +
  3150. + t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
  3151. + t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
  3152. + if (mac)
  3153. + t |= AR933X_ETH_CFG_SW_PHY_SWAP;
  3154. + if (mdio)
  3155. + t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
  3156. + __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
  3157. +
  3158. + iounmap(base);
  3159. +}
  3160. +
  3161. +void __init ath79_setup_ar934x_eth_cfg(u32 mask)
  3162. +{
  3163. + void __iomem *base;
  3164. + u32 t;
  3165. +
  3166. + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
  3167. +
  3168. + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  3169. +
  3170. + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
  3171. + AR934X_ETH_CFG_MII_GMAC0 |
  3172. + AR934X_ETH_CFG_GMII_GMAC0 |
  3173. + AR934X_ETH_CFG_SW_ONLY_MODE |
  3174. + AR934X_ETH_CFG_SW_PHY_SWAP);
  3175. +
  3176. + t |= mask;
  3177. +
  3178. + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
  3179. + /* flush write */
  3180. + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  3181. +
  3182. + iounmap(base);
  3183. +}
  3184. +
  3185. +void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
  3186. + unsigned int rxdv)
  3187. +{
  3188. + void __iomem *base;
  3189. + u32 t;
  3190. +
  3191. + rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
  3192. + rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
  3193. +
  3194. + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
  3195. +
  3196. + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  3197. +
  3198. + t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
  3199. + AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
  3200. +
  3201. + t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
  3202. + rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
  3203. +
  3204. + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
  3205. + /* flush write */
  3206. + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  3207. +
  3208. + iounmap(base);
  3209. +}
  3210. +
  3211. +void __init ath79_setup_qca955x_eth_cfg(u32 mask)
  3212. +{
  3213. + void __iomem *base;
  3214. + u32 t;
  3215. +
  3216. + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
  3217. +
  3218. + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
  3219. +
  3220. + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
  3221. +
  3222. + t |= mask;
  3223. +
  3224. + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
  3225. +
  3226. + iounmap(base);
  3227. +}
  3228. +
  3229. +static int ath79_eth_instance __initdata;
  3230. +void __init ath79_register_eth(unsigned int id)
  3231. +{
  3232. + struct platform_device *pdev;
  3233. + struct ag71xx_platform_data *pdata;
  3234. + int err;
  3235. +
  3236. + if (id > 1) {
  3237. + printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
  3238. + return;
  3239. + }
  3240. +
  3241. + ath79_init_eth_pll_data(id);
  3242. +
  3243. + if (id == 0)
  3244. + pdev = &ath79_eth0_device;
  3245. + else
  3246. + pdev = &ath79_eth1_device;
  3247. +
  3248. + pdata = pdev->dev.platform_data;
  3249. +
  3250. + pdata->max_frame_len = 1540;
  3251. + pdata->desc_pktlen_mask = 0xfff;
  3252. +
  3253. + err = ath79_setup_phy_if_mode(id, pdata);
  3254. + if (err) {
  3255. + printk(KERN_ERR
  3256. + "ar71xx: invalid PHY interface mode for GE%u\n", id);
  3257. + return;
  3258. + }
  3259. +
  3260. + switch (ath79_soc) {
  3261. + case ATH79_SOC_AR7130:
  3262. + if (id == 0) {
  3263. + pdata->ddr_flush = ath79_ddr_flush_ge0;
  3264. + pdata->set_speed = ath79_set_speed_ge0;
  3265. + } else {
  3266. + pdata->ddr_flush = ath79_ddr_flush_ge1;
  3267. + pdata->set_speed = ath79_set_speed_ge1;
  3268. + }
  3269. + break;
  3270. +
  3271. + case ATH79_SOC_AR7141:
  3272. + case ATH79_SOC_AR7161:
  3273. + if (id == 0) {
  3274. + pdata->ddr_flush = ath79_ddr_flush_ge0;
  3275. + pdata->set_speed = ath79_set_speed_ge0;
  3276. + } else {
  3277. + pdata->ddr_flush = ath79_ddr_flush_ge1;
  3278. + pdata->set_speed = ath79_set_speed_ge1;
  3279. + }
  3280. + pdata->has_gbit = 1;
  3281. + break;
  3282. +
  3283. + case ATH79_SOC_AR7242:
  3284. + if (id == 0) {
  3285. + pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
  3286. + AR71XX_RESET_GE0_PHY;
  3287. + pdata->ddr_flush = ar724x_ddr_flush_ge0;
  3288. + pdata->set_speed = ar7242_set_speed_ge0;
  3289. + } else {
  3290. + pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
  3291. + AR71XX_RESET_GE1_PHY;
  3292. + pdata->ddr_flush = ar724x_ddr_flush_ge1;
  3293. + pdata->set_speed = ath79_set_speed_dummy;
  3294. + }
  3295. + pdata->has_gbit = 1;
  3296. + pdata->is_ar724x = 1;
  3297. +
  3298. + if (!pdata->fifo_cfg1)
  3299. + pdata->fifo_cfg1 = 0x0010ffff;
  3300. + if (!pdata->fifo_cfg2)
  3301. + pdata->fifo_cfg2 = 0x015500aa;
  3302. + if (!pdata->fifo_cfg3)
  3303. + pdata->fifo_cfg3 = 0x01f00140;
  3304. + break;
  3305. +
  3306. + case ATH79_SOC_AR7241:
  3307. + if (id == 0)
  3308. + pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
  3309. + else
  3310. + pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
  3311. + /* fall through */
  3312. + case ATH79_SOC_AR7240:
  3313. + if (id == 0) {
  3314. + pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
  3315. + pdata->ddr_flush = ar724x_ddr_flush_ge0;
  3316. + pdata->set_speed = ath79_set_speed_dummy;
  3317. +
  3318. + pdata->phy_mask = BIT(4);
  3319. + } else {
  3320. + pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
  3321. + pdata->ddr_flush = ar724x_ddr_flush_ge1;
  3322. + pdata->set_speed = ath79_set_speed_dummy;
  3323. +
  3324. + pdata->speed = SPEED_1000;
  3325. + pdata->duplex = DUPLEX_FULL;
  3326. + pdata->switch_data = &ath79_switch_data;
  3327. +
  3328. + ath79_switch_data.phy_poll_mask |= BIT(4);
  3329. + }
  3330. + pdata->has_gbit = 1;
  3331. + pdata->is_ar724x = 1;
  3332. + if (ath79_soc == ATH79_SOC_AR7240)
  3333. + pdata->is_ar7240 = 1;
  3334. +
  3335. + if (!pdata->fifo_cfg1)
  3336. + pdata->fifo_cfg1 = 0x0010ffff;
  3337. + if (!pdata->fifo_cfg2)
  3338. + pdata->fifo_cfg2 = 0x015500aa;
  3339. + if (!pdata->fifo_cfg3)
  3340. + pdata->fifo_cfg3 = 0x01f00140;
  3341. + break;
  3342. +
  3343. + case ATH79_SOC_AR9130:
  3344. + if (id == 0) {
  3345. + pdata->ddr_flush = ar91xx_ddr_flush_ge0;
  3346. + pdata->set_speed = ar91xx_set_speed_ge0;
  3347. + } else {
  3348. + pdata->ddr_flush = ar91xx_ddr_flush_ge1;
  3349. + pdata->set_speed = ar91xx_set_speed_ge1;
  3350. + }
  3351. + pdata->is_ar91xx = 1;
  3352. + break;
  3353. +
  3354. + case ATH79_SOC_AR9132:
  3355. + if (id == 0) {
  3356. + pdata->ddr_flush = ar91xx_ddr_flush_ge0;
  3357. + pdata->set_speed = ar91xx_set_speed_ge0;
  3358. + } else {
  3359. + pdata->ddr_flush = ar91xx_ddr_flush_ge1;
  3360. + pdata->set_speed = ar91xx_set_speed_ge1;
  3361. + }
  3362. + pdata->is_ar91xx = 1;
  3363. + pdata->has_gbit = 1;
  3364. + break;
  3365. +
  3366. + case ATH79_SOC_AR9330:
  3367. + case ATH79_SOC_AR9331:
  3368. + if (id == 0) {
  3369. + pdata->reset_bit = AR933X_RESET_GE0_MAC |
  3370. + AR933X_RESET_GE0_MDIO;
  3371. + pdata->ddr_flush = ar933x_ddr_flush_ge0;
  3372. + pdata->set_speed = ath79_set_speed_dummy;
  3373. +
  3374. + pdata->phy_mask = BIT(4);
  3375. + } else {
  3376. + pdata->reset_bit = AR933X_RESET_GE1_MAC |
  3377. + AR933X_RESET_GE1_MDIO;
  3378. + pdata->ddr_flush = ar933x_ddr_flush_ge1;
  3379. + pdata->set_speed = ath79_set_speed_dummy;
  3380. +
  3381. + pdata->speed = SPEED_1000;
  3382. + pdata->has_gbit = 1;
  3383. + pdata->duplex = DUPLEX_FULL;
  3384. + pdata->switch_data = &ath79_switch_data;
  3385. +
  3386. + ath79_switch_data.phy_poll_mask |= BIT(4);
  3387. + }
  3388. +
  3389. + pdata->is_ar724x = 1;
  3390. +
  3391. + if (!pdata->fifo_cfg1)
  3392. + pdata->fifo_cfg1 = 0x0010ffff;
  3393. + if (!pdata->fifo_cfg2)
  3394. + pdata->fifo_cfg2 = 0x015500aa;
  3395. + if (!pdata->fifo_cfg3)
  3396. + pdata->fifo_cfg3 = 0x01f00140;
  3397. + break;
  3398. +
  3399. + case ATH79_SOC_AR9341:
  3400. + case ATH79_SOC_AR9342:
  3401. + case ATH79_SOC_AR9344:
  3402. + case ATH79_SOC_QCA9533:
  3403. + if (id == 0) {
  3404. + pdata->reset_bit = AR934X_RESET_GE0_MAC |
  3405. + AR934X_RESET_GE0_MDIO;
  3406. + pdata->set_speed = ar934x_set_speed_ge0;
  3407. + } else {
  3408. + pdata->reset_bit = AR934X_RESET_GE1_MAC |
  3409. + AR934X_RESET_GE1_MDIO;
  3410. + pdata->set_speed = ath79_set_speed_dummy;
  3411. +
  3412. + pdata->switch_data = &ath79_switch_data;
  3413. +
  3414. + /* reset the built-in switch */
  3415. + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
  3416. + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
  3417. + }
  3418. +
  3419. + pdata->ddr_flush = ath79_ddr_no_flush;
  3420. + pdata->has_gbit = 1;
  3421. + pdata->is_ar724x = 1;
  3422. +
  3423. + pdata->max_frame_len = SZ_16K - 1;
  3424. + pdata->desc_pktlen_mask = SZ_16K - 1;
  3425. +
  3426. + if (!pdata->fifo_cfg1)
  3427. + pdata->fifo_cfg1 = 0x0010ffff;
  3428. + if (!pdata->fifo_cfg2)
  3429. + pdata->fifo_cfg2 = 0x015500aa;
  3430. + if (!pdata->fifo_cfg3)
  3431. + pdata->fifo_cfg3 = 0x01f00140;
  3432. + break;
  3433. +
  3434. + case ATH79_SOC_QCA9561:
  3435. + case ATH79_SOC_TP9343:
  3436. + if (id == 0) {
  3437. + pdata->reset_bit = AR933X_RESET_GE0_MAC |
  3438. + AR933X_RESET_GE0_MDIO;
  3439. + pdata->set_speed = ath79_set_speed_dummy;
  3440. +
  3441. + if (!pdata->phy_mask)
  3442. + pdata->phy_mask = BIT(4);
  3443. + } else {
  3444. + pdata->reset_bit = AR933X_RESET_GE1_MAC |
  3445. + AR933X_RESET_GE1_MDIO;
  3446. + pdata->set_speed = ath79_set_speed_dummy;
  3447. +
  3448. + pdata->speed = SPEED_1000;
  3449. + pdata->duplex = DUPLEX_FULL;
  3450. + pdata->switch_data = &ath79_switch_data;
  3451. +
  3452. + ath79_switch_data.phy_poll_mask |= BIT(4);
  3453. + }
  3454. +
  3455. + pdata->ddr_flush = ath79_ddr_no_flush;
  3456. + pdata->has_gbit = 1;
  3457. + pdata->is_ar724x = 1;
  3458. +
  3459. + if (!pdata->fifo_cfg1)
  3460. + pdata->fifo_cfg1 = 0x0010ffff;
  3461. + if (!pdata->fifo_cfg2)
  3462. + pdata->fifo_cfg2 = 0x015500aa;
  3463. + if (!pdata->fifo_cfg3)
  3464. + pdata->fifo_cfg3 = 0x01f00140;
  3465. + break;
  3466. +
  3467. + case ATH79_SOC_QCA9556:
  3468. + case ATH79_SOC_QCA9558:
  3469. + if (id == 0) {
  3470. + pdata->reset_bit = QCA955X_RESET_GE0_MAC |
  3471. + QCA955X_RESET_GE0_MDIO;
  3472. + pdata->set_speed = qca955x_set_speed_xmii;
  3473. + } else {
  3474. + pdata->reset_bit = QCA955X_RESET_GE1_MAC |
  3475. + QCA955X_RESET_GE1_MDIO;
  3476. + pdata->set_speed = qca955x_set_speed_sgmii;
  3477. + }
  3478. +
  3479. + pdata->ddr_flush = ath79_ddr_no_flush;
  3480. + pdata->has_gbit = 1;
  3481. + pdata->is_ar724x = 1;
  3482. +
  3483. + /*
  3484. + * Limit the maximum frame length to 4095 bytes.
  3485. + * Although the documentation says that the hardware
  3486. + * limit is 16383 bytes but that does not work in
  3487. + * practice. It seems that the hardware only updates
  3488. + * the lowest 12 bits of the packet length field
  3489. + * in the RX descriptor.
  3490. + */
  3491. + pdata->max_frame_len = SZ_4K - 1;
  3492. + pdata->desc_pktlen_mask = SZ_16K - 1;
  3493. +
  3494. + if (!pdata->fifo_cfg1)
  3495. + pdata->fifo_cfg1 = 0x0010ffff;
  3496. + if (!pdata->fifo_cfg2)
  3497. + pdata->fifo_cfg2 = 0x015500aa;
  3498. + if (!pdata->fifo_cfg3)
  3499. + pdata->fifo_cfg3 = 0x01f00140;
  3500. + break;
  3501. +
  3502. + default:
  3503. + BUG();
  3504. + }
  3505. +
  3506. + switch (pdata->phy_if_mode) {
  3507. + case PHY_INTERFACE_MODE_GMII:
  3508. + case PHY_INTERFACE_MODE_RGMII:
  3509. + case PHY_INTERFACE_MODE_SGMII:
  3510. + if (!pdata->has_gbit) {
  3511. + printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
  3512. + id);
  3513. + return;
  3514. + }
  3515. + /* fallthrough */
  3516. + default:
  3517. + break;
  3518. + }
  3519. +
  3520. + if (!is_valid_ether_addr(pdata->mac_addr)) {
  3521. + random_ether_addr(pdata->mac_addr);
  3522. + printk(KERN_DEBUG
  3523. + "ar71xx: using random MAC address for eth%d\n",
  3524. + ath79_eth_instance);
  3525. + }
  3526. +
  3527. + if (pdata->mii_bus_dev == NULL) {
  3528. + switch (ath79_soc) {
  3529. + case ATH79_SOC_AR9341:
  3530. + case ATH79_SOC_AR9342:
  3531. + case ATH79_SOC_AR9344:
  3532. + if (id == 0)
  3533. + pdata->mii_bus_dev = &ath79_mdio0_device.dev;
  3534. + else
  3535. + pdata->mii_bus_dev = &ath79_mdio1_device.dev;
  3536. + break;
  3537. +
  3538. + case ATH79_SOC_AR7241:
  3539. + case ATH79_SOC_AR9330:
  3540. + case ATH79_SOC_AR9331:
  3541. + case ATH79_SOC_QCA9533:
  3542. + case ATH79_SOC_QCA9561:
  3543. + case ATH79_SOC_TP9343:
  3544. + pdata->mii_bus_dev = &ath79_mdio1_device.dev;
  3545. + break;
  3546. +
  3547. + case ATH79_SOC_QCA9556:
  3548. + case ATH79_SOC_QCA9558:
  3549. + /* don't assign any MDIO device by default */
  3550. + break;
  3551. +
  3552. + default:
  3553. + pdata->mii_bus_dev = &ath79_mdio0_device.dev;
  3554. + break;
  3555. + }
  3556. + }
  3557. +
  3558. + /* Reset the device */
  3559. + ath79_device_reset_set(pdata->reset_bit);
  3560. + msleep(100);
  3561. +
  3562. + ath79_device_reset_clear(pdata->reset_bit);
  3563. + msleep(100);
  3564. +
  3565. + platform_device_register(pdev);
  3566. + ath79_eth_instance++;
  3567. +}
  3568. +
  3569. +void __init ath79_set_mac_base(unsigned char *mac)
  3570. +{
  3571. + memcpy(ath79_mac_base, mac, ETH_ALEN);
  3572. +}
  3573. +
  3574. +void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
  3575. +{
  3576. + int t;
  3577. +
  3578. + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
  3579. + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
  3580. +
  3581. + if (t != ETH_ALEN)
  3582. + t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
  3583. + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
  3584. +
  3585. + if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
  3586. + memset(mac, 0, ETH_ALEN);
  3587. + printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
  3588. + mac_str);
  3589. + }
  3590. +}
  3591. +
  3592. +static void __init ath79_set_mac_base_ascii(char *str)
  3593. +{
  3594. + u8 mac[ETH_ALEN];
  3595. +
  3596. + ath79_parse_ascii_mac(str, mac);
  3597. + ath79_set_mac_base(mac);
  3598. +}
  3599. +
  3600. +static int __init ath79_ethaddr_setup(char *str)
  3601. +{
  3602. + ath79_set_mac_base_ascii(str);
  3603. + return 1;
  3604. +}
  3605. +__setup("ethaddr=", ath79_ethaddr_setup);
  3606. +
  3607. +static int __init ath79_kmac_setup(char *str)
  3608. +{
  3609. + ath79_set_mac_base_ascii(str);
  3610. + return 1;
  3611. +}
  3612. +__setup("kmac=", ath79_kmac_setup);
  3613. +
  3614. +void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
  3615. + int offset)
  3616. +{
  3617. + int t;
  3618. +
  3619. + if (!dst)
  3620. + return;
  3621. +
  3622. + if (!src || !is_valid_ether_addr(src)) {
  3623. + memset(dst, '\0', ETH_ALEN);
  3624. + return;
  3625. + }
  3626. +
  3627. + t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
  3628. + t += offset;
  3629. +
  3630. + dst[0] = src[0];
  3631. + dst[1] = src[1];
  3632. + dst[2] = src[2];
  3633. + dst[3] = (t >> 16) & 0xff;
  3634. + dst[4] = (t >> 8) & 0xff;
  3635. + dst[5] = t & 0xff;
  3636. +}
  3637. +
  3638. +void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
  3639. +{
  3640. + int i;
  3641. +
  3642. + if (!dst)
  3643. + return;
  3644. +
  3645. + if (!src || !is_valid_ether_addr(src)) {
  3646. + memset(dst, '\0', ETH_ALEN);
  3647. + return;
  3648. + }
  3649. +
  3650. + for (i = 0; i < ETH_ALEN; i++)
  3651. + dst[i] = src[i];
  3652. + dst[0] |= 0x02;
  3653. +}
  3654. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-eth.h linux-4.1.43/arch/mips/ath79/dev-eth.h
  3655. --- linux-4.1.43.orig/arch/mips/ath79/dev-eth.h 1970-01-01 01:00:00.000000000 +0100
  3656. +++ linux-4.1.43/arch/mips/ath79/dev-eth.h 2017-08-06 20:02:15.000000000 +0200
  3657. @@ -0,0 +1,53 @@
  3658. +/*
  3659. + * Atheros AR71xx SoC device definitions
  3660. + *
  3661. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  3662. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  3663. + *
  3664. + * This program is free software; you can redistribute it and/or modify it
  3665. + * under the terms of the GNU General Public License version 2 as published
  3666. + * by the Free Software Foundation.
  3667. + */
  3668. +
  3669. +#ifndef _ATH79_DEV_ETH_H
  3670. +#define _ATH79_DEV_ETH_H
  3671. +
  3672. +#include <asm/mach-ath79/ag71xx_platform.h>
  3673. +
  3674. +struct platform_device;
  3675. +
  3676. +extern unsigned char ath79_mac_base[] __initdata;
  3677. +void ath79_parse_ascii_mac(char *mac_str, u8 *mac);
  3678. +void ath79_init_mac(unsigned char *dst, const unsigned char *src,
  3679. + int offset);
  3680. +void ath79_init_local_mac(unsigned char *dst, const unsigned char *src);
  3681. +
  3682. +struct ath79_eth_pll_data {
  3683. + u32 pll_10;
  3684. + u32 pll_100;
  3685. + u32 pll_1000;
  3686. +};
  3687. +
  3688. +extern struct ath79_eth_pll_data ath79_eth0_pll_data;
  3689. +extern struct ath79_eth_pll_data ath79_eth1_pll_data;
  3690. +
  3691. +extern struct ag71xx_platform_data ath79_eth0_data;
  3692. +extern struct ag71xx_platform_data ath79_eth1_data;
  3693. +extern struct platform_device ath79_eth0_device;
  3694. +extern struct platform_device ath79_eth1_device;
  3695. +void ath79_register_eth(unsigned int id);
  3696. +
  3697. +extern struct ag71xx_switch_platform_data ath79_switch_data;
  3698. +
  3699. +extern struct ag71xx_mdio_platform_data ath79_mdio0_data;
  3700. +extern struct ag71xx_mdio_platform_data ath79_mdio1_data;
  3701. +extern struct platform_device ath79_mdio0_device;
  3702. +extern struct platform_device ath79_mdio1_device;
  3703. +void ath79_register_mdio(unsigned int id, u32 phy_mask);
  3704. +
  3705. +void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
  3706. +void ath79_setup_ar934x_eth_cfg(u32 mask);
  3707. +void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
  3708. +void ath79_setup_qca955x_eth_cfg(u32 mask);
  3709. +
  3710. +#endif /* _ATH79_DEV_ETH_H */
  3711. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-m25p80.c linux-4.1.43/arch/mips/ath79/dev-m25p80.c
  3712. --- linux-4.1.43.orig/arch/mips/ath79/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100
  3713. +++ linux-4.1.43/arch/mips/ath79/dev-m25p80.c 2017-08-06 20:02:15.000000000 +0200
  3714. @@ -0,0 +1,118 @@
  3715. +/*
  3716. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  3717. + *
  3718. + * This program is free software; you can redistribute it and/or modify it
  3719. + * under the terms of the GNU General Public License version 2 as published
  3720. + * by the Free Software Foundation.
  3721. + */
  3722. +
  3723. +#include <linux/init.h>
  3724. +#include <linux/spi/spi.h>
  3725. +#include <linux/spi/flash.h>
  3726. +#include <linux/mtd/mtd.h>
  3727. +#include <linux/mtd/partitions.h>
  3728. +#include <linux/mtd/concat.h>
  3729. +
  3730. +#include "dev-spi.h"
  3731. +#include "dev-m25p80.h"
  3732. +
  3733. +static struct ath79_spi_controller_data ath79_spi0_cdata =
  3734. +{
  3735. + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  3736. + .cs_line = 0,
  3737. +};
  3738. +
  3739. +static struct ath79_spi_controller_data ath79_spi1_cdata =
  3740. +{
  3741. + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  3742. + .cs_line = 1,
  3743. +};
  3744. +
  3745. +static struct spi_board_info ath79_spi_info[] = {
  3746. + {
  3747. + .bus_num = 0,
  3748. + .chip_select = 0,
  3749. + .max_speed_hz = 25000000,
  3750. + .modalias = "m25p80",
  3751. + .controller_data = &ath79_spi0_cdata,
  3752. + },
  3753. + {
  3754. + .bus_num = 0,
  3755. + .chip_select = 1,
  3756. + .max_speed_hz = 25000000,
  3757. + .modalias = "m25p80",
  3758. + .controller_data = &ath79_spi1_cdata,
  3759. + }
  3760. +};
  3761. +
  3762. +static struct ath79_spi_platform_data ath79_spi_data;
  3763. +
  3764. +void __init ath79_register_m25p80(struct flash_platform_data *pdata)
  3765. +{
  3766. + ath79_spi_data.bus_num = 0;
  3767. + ath79_spi_data.num_chipselect = 1;
  3768. + ath79_spi0_cdata.is_flash = true;
  3769. + ath79_spi_info[0].platform_data = pdata;
  3770. + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1);
  3771. +}
  3772. +
  3773. +static struct flash_platform_data *multi_pdata;
  3774. +
  3775. +static struct mtd_info *concat_devs[2] = { NULL, NULL };
  3776. +static struct work_struct mtd_concat_work;
  3777. +
  3778. +static void mtd_concat_add_work(struct work_struct *work)
  3779. +{
  3780. + struct mtd_info *mtd;
  3781. +
  3782. + mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash");
  3783. +
  3784. + mtd_device_register(mtd, multi_pdata->parts, multi_pdata->nr_parts);
  3785. +}
  3786. +
  3787. +static void mtd_concat_add(struct mtd_info *mtd)
  3788. +{
  3789. + static bool registered = false;
  3790. +
  3791. + if (registered)
  3792. + return;
  3793. +
  3794. + if (!strcmp(mtd->name, "spi0.0"))
  3795. + concat_devs[0] = mtd;
  3796. + else if (!strcmp(mtd->name, "spi0.1"))
  3797. + concat_devs[1] = mtd;
  3798. + else
  3799. + return;
  3800. +
  3801. + if (!concat_devs[0] || !concat_devs[1])
  3802. + return;
  3803. +
  3804. + registered = true;
  3805. + INIT_WORK(&mtd_concat_work, mtd_concat_add_work);
  3806. + schedule_work(&mtd_concat_work);
  3807. +}
  3808. +
  3809. +static void mtd_concat_remove(struct mtd_info *mtd)
  3810. +{
  3811. +}
  3812. +
  3813. +static void add_mtd_concat_notifier(void)
  3814. +{
  3815. + static struct mtd_notifier not = {
  3816. + .add = mtd_concat_add,
  3817. + .remove = mtd_concat_remove,
  3818. + };
  3819. +
  3820. + register_mtd_user(&not);
  3821. +}
  3822. +
  3823. +
  3824. +void __init ath79_register_m25p80_multi(struct flash_platform_data *pdata)
  3825. +{
  3826. + multi_pdata = pdata;
  3827. + add_mtd_concat_notifier();
  3828. + ath79_spi_data.bus_num = 0;
  3829. + ath79_spi_data.num_chipselect = 2;
  3830. + ath79_spi0_cdata.is_flash = true;
  3831. + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 2);
  3832. +}
  3833. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-m25p80.h linux-4.1.43/arch/mips/ath79/dev-m25p80.h
  3834. --- linux-4.1.43.orig/arch/mips/ath79/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100
  3835. +++ linux-4.1.43/arch/mips/ath79/dev-m25p80.h 2017-08-06 20:02:15.000000000 +0200
  3836. @@ -0,0 +1,17 @@
  3837. +/*
  3838. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  3839. + *
  3840. + * This program is free software; you can redistribute it and/or modify it
  3841. + * under the terms of the GNU General Public License version 2 as published
  3842. + * by the Free Software Foundation.
  3843. + */
  3844. +
  3845. +#ifndef _ATH79_DEV_M25P80_H
  3846. +#define _ATH79_DEV_M25P80_H
  3847. +
  3848. +#include <linux/spi/flash.h>
  3849. +
  3850. +void ath79_register_m25p80(struct flash_platform_data *pdata) __init;
  3851. +void ath79_register_m25p80_multi(struct flash_platform_data *pdata) __init;
  3852. +
  3853. +#endif /* _ATH79_DEV_M25P80_H */
  3854. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-nfc.c linux-4.1.43/arch/mips/ath79/dev-nfc.c
  3855. --- linux-4.1.43.orig/arch/mips/ath79/dev-nfc.c 1970-01-01 01:00:00.000000000 +0100
  3856. +++ linux-4.1.43/arch/mips/ath79/dev-nfc.c 2017-08-06 20:02:15.000000000 +0200
  3857. @@ -0,0 +1,141 @@
  3858. +/*
  3859. + * Atheros AR934X SoCs built-in NAND flash controller support
  3860. + *
  3861. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  3862. + *
  3863. + * This program is free software; you can redistribute it and/or modify it
  3864. + * under the terms of the GNU General Public License version 2 as published
  3865. + * by the Free Software Foundation.
  3866. + */
  3867. +
  3868. +#include <linux/kernel.h>
  3869. +#include <linux/delay.h>
  3870. +#include <linux/init.h>
  3871. +#include <linux/irq.h>
  3872. +#include <linux/dma-mapping.h>
  3873. +#include <linux/etherdevice.h>
  3874. +#include <linux/platform_device.h>
  3875. +#include <linux/platform/ar934x_nfc.h>
  3876. +
  3877. +#include <asm/mach-ath79/ath79.h>
  3878. +#include <asm/mach-ath79/ar71xx_regs.h>
  3879. +
  3880. +#include "dev-nfc.h"
  3881. +
  3882. +static struct resource ath79_nfc_resources[2];
  3883. +static u64 ar934x_nfc_dmamask = DMA_BIT_MASK(32);
  3884. +static struct ar934x_nfc_platform_data ath79_nfc_data;
  3885. +
  3886. +static struct platform_device ath79_nfc_device = {
  3887. + .name = AR934X_NFC_DRIVER_NAME,
  3888. + .id = -1,
  3889. + .resource = ath79_nfc_resources,
  3890. + .num_resources = ARRAY_SIZE(ath79_nfc_resources),
  3891. + .dev = {
  3892. + .dma_mask = &ar934x_nfc_dmamask,
  3893. + .coherent_dma_mask = DMA_BIT_MASK(32),
  3894. + .platform_data = &ath79_nfc_data,
  3895. + },
  3896. +};
  3897. +
  3898. +static void __init ath79_nfc_init_resource(struct resource res[2],
  3899. + unsigned long base,
  3900. + unsigned long size,
  3901. + int irq)
  3902. +{
  3903. + memset(res, 0, sizeof(struct resource) * 2);
  3904. +
  3905. + res[0].flags = IORESOURCE_MEM;
  3906. + res[0].start = base;
  3907. + res[0].end = base + size - 1;
  3908. +
  3909. + res[1].flags = IORESOURCE_IRQ;
  3910. + res[1].start = irq;
  3911. + res[1].end = irq;
  3912. +}
  3913. +
  3914. +static void ar934x_nfc_hw_reset(bool active)
  3915. +{
  3916. + if (active) {
  3917. + ath79_device_reset_set(AR934X_RESET_NANDF);
  3918. + udelay(100);
  3919. +
  3920. + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH_ANALOG);
  3921. + udelay(250);
  3922. + } else {
  3923. + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH_ANALOG);
  3924. + udelay(250);
  3925. +
  3926. + ath79_device_reset_clear(AR934X_RESET_NANDF);
  3927. + udelay(100);
  3928. + }
  3929. +}
  3930. +
  3931. +static void ar934x_nfc_setup(void)
  3932. +{
  3933. + ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset;
  3934. +
  3935. + ath79_nfc_init_resource(ath79_nfc_resources,
  3936. + AR934X_NFC_BASE, AR934X_NFC_SIZE,
  3937. + ATH79_MISC_IRQ(21));
  3938. +
  3939. + platform_device_register(&ath79_nfc_device);
  3940. +}
  3941. +
  3942. +static void qca955x_nfc_hw_reset(bool active)
  3943. +{
  3944. + if (active) {
  3945. + ath79_device_reset_set(QCA955X_RESET_NANDF);
  3946. + udelay(250);
  3947. + } else {
  3948. + ath79_device_reset_clear(QCA955X_RESET_NANDF);
  3949. + udelay(100);
  3950. + }
  3951. +}
  3952. +
  3953. +static void qca955x_nfc_setup(void)
  3954. +{
  3955. + ath79_nfc_data.hw_reset = qca955x_nfc_hw_reset;
  3956. +
  3957. + ath79_nfc_init_resource(ath79_nfc_resources,
  3958. + QCA955X_NFC_BASE, QCA955X_NFC_SIZE,
  3959. + ATH79_MISC_IRQ(21));
  3960. +
  3961. + platform_device_register(&ath79_nfc_device);
  3962. +}
  3963. +
  3964. +void __init ath79_nfc_set_select_chip(void (*f)(int chip_no))
  3965. +{
  3966. + ath79_nfc_data.select_chip = f;
  3967. +}
  3968. +
  3969. +void __init ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd))
  3970. +{
  3971. + ath79_nfc_data.scan_fixup = f;
  3972. +}
  3973. +
  3974. +void __init ath79_nfc_set_swap_dma(bool enable)
  3975. +{
  3976. + ath79_nfc_data.swap_dma = enable;
  3977. +}
  3978. +
  3979. +void __init ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode)
  3980. +{
  3981. + ath79_nfc_data.ecc_mode = mode;
  3982. +}
  3983. +
  3984. +void __init ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts)
  3985. +{
  3986. + ath79_nfc_data.parts = parts;
  3987. + ath79_nfc_data.nr_parts = nr_parts;
  3988. +}
  3989. +
  3990. +void __init ath79_register_nfc(void)
  3991. +{
  3992. + if (soc_is_ar934x())
  3993. + ar934x_nfc_setup();
  3994. + else if (soc_is_qca955x())
  3995. + qca955x_nfc_setup();
  3996. + else
  3997. + BUG();
  3998. +}
  3999. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-nfc.h linux-4.1.43/arch/mips/ath79/dev-nfc.h
  4000. --- linux-4.1.43.orig/arch/mips/ath79/dev-nfc.h 1970-01-01 01:00:00.000000000 +0100
  4001. +++ linux-4.1.43/arch/mips/ath79/dev-nfc.h 2017-08-06 20:02:15.000000000 +0200
  4002. @@ -0,0 +1,34 @@
  4003. +/*
  4004. + * Atheros AR934X SoCs built-in NAND Flash Controller support
  4005. + *
  4006. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  4007. + *
  4008. + * This program is free software; you can redistribute it and/or modify it
  4009. + * under the terms of the GNU General Public License version 2 as published
  4010. + * by the Free Software Foundation.
  4011. + */
  4012. +
  4013. +#ifndef _ATH79_DEV_NFC_H
  4014. +#define _ATH79_DEV_NFC_H
  4015. +
  4016. +struct mtd_partition;
  4017. +enum ar934x_nfc_ecc_mode;
  4018. +
  4019. +#ifdef CONFIG_ATH79_DEV_NFC
  4020. +void ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts);
  4021. +void ath79_nfc_set_select_chip(void (*f)(int chip_no));
  4022. +void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd));
  4023. +void ath79_nfc_set_swap_dma(bool enable);
  4024. +void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode);
  4025. +void ath79_register_nfc(void);
  4026. +#else
  4027. +static inline void ath79_nfc_set_parts(struct mtd_partition *parts,
  4028. + int nr_parts) {}
  4029. +static inline void ath79_nfc_set_select_chip(void (*f)(int chip_no)) {}
  4030. +static inline void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) {}
  4031. +static inline void ath79_nfc_set_swap_dma(bool enable) {}
  4032. +static inline void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode) {}
  4033. +static inline void ath79_register_nfc(void) {}
  4034. +#endif
  4035. +
  4036. +#endif /* _ATH79_DEV_NFC_H */
  4037. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-usb.c linux-4.1.43/arch/mips/ath79/dev-usb.c
  4038. --- linux-4.1.43.orig/arch/mips/ath79/dev-usb.c 2017-08-06 01:56:14.000000000 +0200
  4039. +++ linux-4.1.43/arch/mips/ath79/dev-usb.c 2017-08-06 20:02:15.000000000 +0200
  4040. @@ -37,6 +37,8 @@
  4041. static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
  4042. .caps_offset = 0x100,
  4043. .has_tt = 1,
  4044. + .qca_force_host_mode = 1,
  4045. + .qca_force_16bit_ptw = 1,
  4046. };
  4047. static void __init ath79_usb_register(const char *name, int id,
  4048. @@ -159,6 +161,9 @@
  4049. ath79_device_reset_clear(AR913X_RESET_USB_PHY);
  4050. mdelay(10);
  4051. + ath79_ehci_pdata_v2.qca_force_host_mode = 0;
  4052. + ath79_ehci_pdata_v2.qca_force_16bit_ptw = 0;
  4053. +
  4054. ath79_usb_register("ehci-platform", -1,
  4055. AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
  4056. ATH79_CPU_IRQ(3),
  4057. @@ -182,14 +187,34 @@
  4058. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  4059. }
  4060. -static void __init ar934x_usb_setup(void)
  4061. +static void enable_tx_tx_idp_violation_fix(unsigned base)
  4062. {
  4063. - u32 bootstrap;
  4064. + void __iomem *phy_reg;
  4065. + u32 t;
  4066. - bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
  4067. - if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
  4068. + phy_reg = ioremap(base, 4);
  4069. + if (!phy_reg)
  4070. return;
  4071. + t = ioread32(phy_reg);
  4072. + t &= ~0xff;
  4073. + t |= 0x58;
  4074. + iowrite32(t, phy_reg);
  4075. +
  4076. + iounmap(phy_reg);
  4077. +}
  4078. +
  4079. +static void ar934x_usb_reset_notifier(struct platform_device *pdev)
  4080. +{
  4081. + if (pdev->id != -1)
  4082. + return;
  4083. +
  4084. + enable_tx_tx_idp_violation_fix(0x18116c94);
  4085. + dev_info(&pdev->dev, "TX-TX IDP fix enabled\n");
  4086. +}
  4087. +
  4088. +static void __init ar934x_usb_setup(void)
  4089. +{
  4090. ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
  4091. udelay(1000);
  4092. @@ -202,14 +227,64 @@
  4093. ath79_device_reset_clear(AR934X_RESET_USB_HOST);
  4094. udelay(1000);
  4095. + if (ath79_soc_rev >= 3)
  4096. + ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier;
  4097. +
  4098. ath79_usb_register("ehci-platform", -1,
  4099. AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
  4100. ATH79_CPU_IRQ(3),
  4101. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  4102. }
  4103. +static void __init qca953x_usb_setup(void)
  4104. +{
  4105. + u32 bootstrap;
  4106. +
  4107. + bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  4108. +
  4109. + ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
  4110. + udelay(1000);
  4111. +
  4112. + ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
  4113. + udelay(1000);
  4114. +
  4115. + ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
  4116. + udelay(1000);
  4117. +
  4118. + ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
  4119. + udelay(1000);
  4120. +
  4121. + ath79_usb_register("ehci-platform", -1,
  4122. + QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
  4123. + ATH79_CPU_IRQ(3),
  4124. + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  4125. +}
  4126. +
  4127. +static void qca955x_usb_reset_notifier(struct platform_device *pdev)
  4128. +{
  4129. + u32 base;
  4130. +
  4131. + switch (pdev->id) {
  4132. + case 0:
  4133. + base = 0x18116c94;
  4134. + break;
  4135. +
  4136. + case 1:
  4137. + base = 0x18116e54;
  4138. + break;
  4139. +
  4140. + default:
  4141. + return;
  4142. + }
  4143. +
  4144. + enable_tx_tx_idp_violation_fix(base);
  4145. + dev_info(&pdev->dev, "TX-TX IDP fix enabled\n");
  4146. +}
  4147. +
  4148. static void __init qca955x_usb_setup(void)
  4149. {
  4150. + ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier;
  4151. +
  4152. ath79_usb_register("ehci-platform", 0,
  4153. QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
  4154. ATH79_IP3_IRQ(0),
  4155. @@ -221,6 +296,19 @@
  4156. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  4157. }
  4158. +static void __init qca956x_usb_setup(void)
  4159. +{
  4160. + ath79_usb_register("ehci-platform", 0,
  4161. + QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
  4162. + ATH79_IP3_IRQ(0),
  4163. + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  4164. +
  4165. + ath79_usb_register("ehci-platform", 1,
  4166. + QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
  4167. + ATH79_IP3_IRQ(1),
  4168. + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  4169. +}
  4170. +
  4171. void __init ath79_register_usb(void)
  4172. {
  4173. if (soc_is_ar71xx())
  4174. @@ -235,8 +323,12 @@
  4175. ar933x_usb_setup();
  4176. else if (soc_is_ar934x())
  4177. ar934x_usb_setup();
  4178. + else if (soc_is_qca953x())
  4179. + qca953x_usb_setup();
  4180. else if (soc_is_qca955x())
  4181. qca955x_usb_setup();
  4182. + else if (soc_is_qca9561())
  4183. + qca956x_usb_setup();
  4184. else
  4185. BUG();
  4186. }
  4187. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-wmac.c linux-4.1.43/arch/mips/ath79/dev-wmac.c
  4188. --- linux-4.1.43.orig/arch/mips/ath79/dev-wmac.c 2017-08-06 01:56:14.000000000 +0200
  4189. +++ linux-4.1.43/arch/mips/ath79/dev-wmac.c 2017-08-06 20:02:15.000000000 +0200
  4190. @@ -15,14 +15,21 @@
  4191. #include <linux/init.h>
  4192. #include <linux/delay.h>
  4193. #include <linux/irq.h>
  4194. +#include <linux/etherdevice.h>
  4195. #include <linux/platform_device.h>
  4196. #include <linux/ath9k_platform.h>
  4197. +#include <linux/gpio.h>
  4198. #include <asm/mach-ath79/ath79.h>
  4199. #include <asm/mach-ath79/ar71xx_regs.h>
  4200. +#include "common.h"
  4201. #include "dev-wmac.h"
  4202. -static struct ath9k_platform_data ath79_wmac_data;
  4203. +static u8 ath79_wmac_mac[ETH_ALEN];
  4204. +
  4205. +static struct ath9k_platform_data ath79_wmac_data = {
  4206. + .led_pin = -1,
  4207. +};
  4208. static struct resource ath79_wmac_resources[] = {
  4209. {
  4210. @@ -44,7 +51,7 @@
  4211. },
  4212. };
  4213. -static void __init ar913x_wmac_setup(void)
  4214. +static int ar913x_wmac_reset(void)
  4215. {
  4216. /* reset the WMAC */
  4217. ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
  4218. @@ -53,22 +60,48 @@
  4219. ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
  4220. mdelay(10);
  4221. + return 0;
  4222. +}
  4223. +
  4224. +static void __init ar913x_wmac_setup(void)
  4225. +{
  4226. + ar913x_wmac_reset();
  4227. +
  4228. ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
  4229. ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
  4230. ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
  4231. ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
  4232. +
  4233. + ath79_wmac_data.external_reset = ar913x_wmac_reset;
  4234. }
  4235. static int ar933x_wmac_reset(void)
  4236. {
  4237. + int retries = 20;
  4238. +
  4239. ath79_device_reset_set(AR933X_RESET_WMAC);
  4240. ath79_device_reset_clear(AR933X_RESET_WMAC);
  4241. - return 0;
  4242. + while (1) {
  4243. + u32 bootstrap;
  4244. +
  4245. + bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  4246. + if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
  4247. + return 0;
  4248. +
  4249. + if (retries-- == 0)
  4250. + break;
  4251. +
  4252. + udelay(10000);
  4253. + retries++;
  4254. + }
  4255. +
  4256. + pr_err("ar933x: WMAC reset timed out");
  4257. + return -ETIMEDOUT;
  4258. }
  4259. -static int ar933x_r1_get_wmac_revision(void)
  4260. +static int ar93xx_get_soc_revision(void)
  4261. {
  4262. return ath79_soc_rev;
  4263. }
  4264. @@ -93,7 +126,7 @@
  4265. ath79_wmac_data.is_clk_25mhz = true;
  4266. if (ath79_soc_rev == 1)
  4267. - ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
  4268. + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
  4269. ath79_wmac_data.external_reset = ar933x_wmac_reset;
  4270. }
  4271. @@ -114,6 +147,28 @@
  4272. ath79_wmac_data.is_clk_25mhz = false;
  4273. else
  4274. ath79_wmac_data.is_clk_25mhz = true;
  4275. +
  4276. + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
  4277. +}
  4278. +
  4279. +static void qca953x_wmac_setup(void)
  4280. +{
  4281. + u32 t;
  4282. +
  4283. + ath79_wmac_device.name = "qca953x_wmac";
  4284. +
  4285. + ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
  4286. + ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
  4287. + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
  4288. + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
  4289. +
  4290. + t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  4291. + if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
  4292. + ath79_wmac_data.is_clk_25mhz = false;
  4293. + else
  4294. + ath79_wmac_data.is_clk_25mhz = true;
  4295. +
  4296. + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
  4297. }
  4298. static void qca955x_wmac_setup(void)
  4299. @@ -134,7 +189,221 @@
  4300. ath79_wmac_data.is_clk_25mhz = true;
  4301. }
  4302. -void __init ath79_register_wmac(u8 *cal_data)
  4303. +static void qca956x_wmac_setup(void)
  4304. +{
  4305. + u32 t;
  4306. +
  4307. + ath79_wmac_device.name = "qca956x_wmac";
  4308. +
  4309. + ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
  4310. + ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
  4311. + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
  4312. + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
  4313. +
  4314. + t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  4315. + if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
  4316. + ath79_wmac_data.is_clk_25mhz = false;
  4317. + else
  4318. + ath79_wmac_data.is_clk_25mhz = true;
  4319. +}
  4320. +
  4321. +static bool __init
  4322. +ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
  4323. +{
  4324. + int timeout = 1000;
  4325. + u32 val;
  4326. +
  4327. + __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
  4328. + while (timeout--) {
  4329. + val = __raw_readl(base + AR9300_OTP_STATUS);
  4330. + if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
  4331. + break;
  4332. +
  4333. + udelay(10);
  4334. + }
  4335. +
  4336. + if (!timeout)
  4337. + return false;
  4338. +
  4339. + *data = __raw_readl(base + AR9300_OTP_READ_DATA);
  4340. + return true;
  4341. +}
  4342. +
  4343. +static bool __init
  4344. +ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
  4345. +{
  4346. + u32 data;
  4347. + int i;
  4348. +
  4349. + for (i = 0; i < len; i++) {
  4350. + int offset = 8 * ((addr - i) % 4);
  4351. +
  4352. + if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
  4353. + return false;
  4354. +
  4355. + dest[i] = (data >> offset) & 0xff;
  4356. + }
  4357. +
  4358. + return true;
  4359. +}
  4360. +
  4361. +static bool __init
  4362. +ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
  4363. + int dest_start, int dest_len)
  4364. +{
  4365. + int dest_bytes = 0;
  4366. + int offset = 0;
  4367. + int end = addr - len;
  4368. + u8 hdr[2];
  4369. +
  4370. + while (addr > end) {
  4371. + if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
  4372. + return false;
  4373. +
  4374. + addr -= 2;
  4375. + offset += hdr[0];
  4376. +
  4377. + if (offset <= dest_start + dest_len &&
  4378. + offset + len >= dest_start) {
  4379. + int data_offset = 0;
  4380. + int dest_offset = 0;
  4381. + int copy_len;
  4382. +
  4383. + if (offset < dest_start)
  4384. + data_offset = dest_start - offset;
  4385. + else
  4386. + dest_offset = offset - dest_start;
  4387. +
  4388. + copy_len = len - data_offset;
  4389. + if (copy_len > dest_len - dest_offset)
  4390. + copy_len = dest_len - dest_offset;
  4391. +
  4392. + ar93xx_wmac_otp_read(base, addr - data_offset,
  4393. + dest + dest_offset,
  4394. + copy_len);
  4395. +
  4396. + dest_bytes += copy_len;
  4397. + }
  4398. + addr -= hdr[1];
  4399. + }
  4400. + return !!dest_bytes;
  4401. +}
  4402. +
  4403. +bool __init ar93xx_wmac_read_mac_address(u8 *dest)
  4404. +{
  4405. + void __iomem *base;
  4406. + bool ret = false;
  4407. + int addr = 0x1ff;
  4408. + unsigned int len;
  4409. + u32 hdr_u32;
  4410. + u8 *hdr = (u8 *) &hdr_u32;
  4411. + u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
  4412. + int mac_start = 2, mac_end = 8;
  4413. +
  4414. + BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
  4415. + base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
  4416. + while (addr > sizeof(hdr)) {
  4417. + if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
  4418. + break;
  4419. +
  4420. + if (hdr_u32 == 0 || hdr_u32 == ~0)
  4421. + break;
  4422. +
  4423. + len = (hdr[1] << 4) | (hdr[2] >> 4);
  4424. + addr -= 4;
  4425. +
  4426. + switch (hdr[0] >> 5) {
  4427. + case 0:
  4428. + if (len < mac_end)
  4429. + break;
  4430. +
  4431. + ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
  4432. + ret = true;
  4433. + break;
  4434. + case 3:
  4435. + ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
  4436. + mac_start, 6);
  4437. + break;
  4438. + default:
  4439. + break;
  4440. + }
  4441. +
  4442. + addr -= len + 2;
  4443. + }
  4444. +
  4445. + iounmap(base);
  4446. + if (ret)
  4447. + memcpy(dest, mac, 6);
  4448. +
  4449. + return ret;
  4450. +}
  4451. +
  4452. +void __init ath79_wmac_disable_2ghz(void)
  4453. +{
  4454. + ath79_wmac_data.disable_2ghz = true;
  4455. +}
  4456. +
  4457. +void __init ath79_wmac_disable_5ghz(void)
  4458. +{
  4459. + ath79_wmac_data.disable_5ghz = true;
  4460. +}
  4461. +
  4462. +void __init ath79_wmac_set_tx_gain_buffalo(void)
  4463. +{
  4464. + ath79_wmac_data.tx_gain_buffalo = true;
  4465. +}
  4466. +
  4467. +static int ath79_request_ext_lna_gpio(unsigned chain, int gpio)
  4468. +{
  4469. + char buf[32];
  4470. + char *label;
  4471. + int err;
  4472. +
  4473. + scnprintf(buf, sizeof(buf), "external LNA%u", chain);
  4474. + label = kstrdup(buf, GFP_KERNEL);
  4475. +
  4476. + err = gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label);
  4477. + if (err) {
  4478. + pr_err("unable to request GPIO%d for external LNA%u\n",
  4479. + gpio, chain);
  4480. + kfree(label);
  4481. + }
  4482. +
  4483. + return err;
  4484. +}
  4485. +
  4486. +static void ar934x_set_ext_lna_gpio(unsigned chain, int gpio)
  4487. +{
  4488. + unsigned int sel;
  4489. + int err;
  4490. +
  4491. + if (WARN_ON(chain > 1))
  4492. + return;
  4493. +
  4494. + err = ath79_request_ext_lna_gpio(chain, gpio);
  4495. + if (err)
  4496. + return;
  4497. +
  4498. + if (chain == 0)
  4499. + sel = AR934X_GPIO_OUT_EXT_LNA0;
  4500. + else
  4501. + sel = AR934X_GPIO_OUT_EXT_LNA1;
  4502. +
  4503. + ath79_gpio_output_select(gpio, sel);
  4504. +}
  4505. +
  4506. +void __init ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio)
  4507. +{
  4508. + if (soc_is_ar934x())
  4509. + ar934x_set_ext_lna_gpio(chain, gpio);
  4510. +}
  4511. +
  4512. +void __init ath79_wmac_set_led_pin(int gpio)
  4513. +{
  4514. + ath79_wmac_data.led_pin = gpio;
  4515. +}
  4516. +
  4517. +void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
  4518. {
  4519. if (soc_is_ar913x())
  4520. ar913x_wmac_setup();
  4521. @@ -142,8 +411,12 @@
  4522. ar933x_wmac_setup();
  4523. else if (soc_is_ar934x())
  4524. ar934x_wmac_setup();
  4525. + else if (soc_is_qca953x())
  4526. + qca953x_wmac_setup();
  4527. else if (soc_is_qca955x())
  4528. qca955x_wmac_setup();
  4529. + else if (soc_is_qca956x())
  4530. + qca956x_wmac_setup();
  4531. else
  4532. BUG();
  4533. @@ -151,5 +424,16 @@
  4534. memcpy(ath79_wmac_data.eeprom_data, cal_data,
  4535. sizeof(ath79_wmac_data.eeprom_data));
  4536. + if (mac_addr) {
  4537. + memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
  4538. + ath79_wmac_data.macaddr = ath79_wmac_mac;
  4539. + }
  4540. +
  4541. platform_device_register(&ath79_wmac_device);
  4542. }
  4543. +
  4544. +void __init ath79_register_wmac_simple(void)
  4545. +{
  4546. + ath79_register_wmac(NULL, NULL);
  4547. + ath79_wmac_data.eeprom_name = "soc_wmac.eeprom";
  4548. +}
  4549. diff -Nur linux-4.1.43.orig/arch/mips/ath79/dev-wmac.h linux-4.1.43/arch/mips/ath79/dev-wmac.h
  4550. --- linux-4.1.43.orig/arch/mips/ath79/dev-wmac.h 2017-08-06 01:56:14.000000000 +0200
  4551. +++ linux-4.1.43/arch/mips/ath79/dev-wmac.h 2017-08-06 20:02:15.000000000 +0200
  4552. @@ -12,6 +12,14 @@
  4553. #ifndef _ATH79_DEV_WMAC_H
  4554. #define _ATH79_DEV_WMAC_H
  4555. -void ath79_register_wmac(u8 *cal_data);
  4556. +void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
  4557. +void ath79_register_wmac_simple(void);
  4558. +void ath79_wmac_disable_2ghz(void);
  4559. +void ath79_wmac_disable_5ghz(void);
  4560. +void ath79_wmac_set_tx_gain_buffalo(void);
  4561. +void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio);
  4562. +void ath79_wmac_set_led_pin(int gpio);
  4563. +
  4564. +bool ar93xx_wmac_read_mac_address(u8 *dest);
  4565. #endif /* _ATH79_DEV_WMAC_H */
  4566. diff -Nur linux-4.1.43.orig/arch/mips/ath79/early_printk.c linux-4.1.43/arch/mips/ath79/early_printk.c
  4567. --- linux-4.1.43.orig/arch/mips/ath79/early_printk.c 2017-08-06 01:56:14.000000000 +0200
  4568. +++ linux-4.1.43/arch/mips/ath79/early_printk.c 2017-08-06 20:02:15.000000000 +0200
  4569. @@ -58,6 +58,46 @@
  4570. /* nothing to do */
  4571. }
  4572. +static void prom_enable_uart(u32 id)
  4573. +{
  4574. + void __iomem *gpio_base;
  4575. + u32 uart_en;
  4576. + u32 t;
  4577. +
  4578. + switch (id) {
  4579. + case REV_ID_MAJOR_AR71XX:
  4580. + uart_en = AR71XX_GPIO_FUNC_UART_EN;
  4581. + break;
  4582. +
  4583. + case REV_ID_MAJOR_AR7240:
  4584. + case REV_ID_MAJOR_AR7241:
  4585. + case REV_ID_MAJOR_AR7242:
  4586. + uart_en = AR724X_GPIO_FUNC_UART_EN;
  4587. + break;
  4588. +
  4589. + case REV_ID_MAJOR_AR913X:
  4590. + uart_en = AR913X_GPIO_FUNC_UART_EN;
  4591. + break;
  4592. +
  4593. + case REV_ID_MAJOR_AR9330:
  4594. + case REV_ID_MAJOR_AR9331:
  4595. + uart_en = AR933X_GPIO_FUNC_UART_EN;
  4596. + break;
  4597. +
  4598. + case REV_ID_MAJOR_AR9341:
  4599. + case REV_ID_MAJOR_AR9342:
  4600. + case REV_ID_MAJOR_AR9344:
  4601. + /* TODO */
  4602. + default:
  4603. + return;
  4604. + }
  4605. +
  4606. + gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
  4607. + t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
  4608. + t |= uart_en;
  4609. + __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
  4610. +}
  4611. +
  4612. static void prom_putchar_init(void)
  4613. {
  4614. void __iomem *base;
  4615. @@ -76,8 +116,12 @@
  4616. case REV_ID_MAJOR_AR9341:
  4617. case REV_ID_MAJOR_AR9342:
  4618. case REV_ID_MAJOR_AR9344:
  4619. + case REV_ID_MAJOR_QCA9533:
  4620. + case REV_ID_MAJOR_QCA9533_V2:
  4621. case REV_ID_MAJOR_QCA9556:
  4622. case REV_ID_MAJOR_QCA9558:
  4623. + case REV_ID_MAJOR_TP9343:
  4624. + case REV_ID_MAJOR_QCA9561:
  4625. _prom_putchar = prom_putchar_ar71xx;
  4626. break;
  4627. @@ -88,8 +132,10 @@
  4628. default:
  4629. _prom_putchar = prom_putchar_dummy;
  4630. - break;
  4631. + return;
  4632. }
  4633. +
  4634. + prom_enable_uart(id);
  4635. }
  4636. void prom_putchar(unsigned char ch)
  4637. diff -Nur linux-4.1.43.orig/arch/mips/ath79/gpio.c linux-4.1.43/arch/mips/ath79/gpio.c
  4638. --- linux-4.1.43.orig/arch/mips/ath79/gpio.c 2017-08-06 01:56:14.000000000 +0200
  4639. +++ linux-4.1.43/arch/mips/ath79/gpio.c 2017-08-06 20:02:15.000000000 +0200
  4640. @@ -20,15 +20,29 @@
  4641. #include <linux/io.h>
  4642. #include <linux/ioport.h>
  4643. #include <linux/gpio.h>
  4644. +#include <linux/irq.h>
  4645. +#include <linux/interrupt.h>
  4646. +
  4647. +#include <linux/of.h>
  4648. #include <asm/mach-ath79/ar71xx_regs.h>
  4649. #include <asm/mach-ath79/ath79.h>
  4650. +#include <asm/mach-ath79/irq.h>
  4651. #include "common.h"
  4652. -static void __iomem *ath79_gpio_base;
  4653. +void __iomem *ath79_gpio_base;
  4654. +EXPORT_SYMBOL_GPL(ath79_gpio_base);
  4655. +
  4656. static unsigned long ath79_gpio_count;
  4657. static DEFINE_SPINLOCK(ath79_gpio_lock);
  4658. +/*
  4659. + * gpio_both_edge is a bitmask of which gpio pins need to have
  4660. + * the detect priority flipped from the interrupt handler to
  4661. + * emulate IRQ_TYPE_EDGE_BOTH.
  4662. + */
  4663. +static unsigned long gpio_both_edge = 0;
  4664. +
  4665. static void __ath79_gpio_set_value(unsigned gpio, int value)
  4666. {
  4667. void __iomem *base = ath79_gpio_base;
  4668. @@ -128,6 +142,30 @@
  4669. return 0;
  4670. }
  4671. +int ath79_gpio_direction_select(unsigned gpio, bool oe)
  4672. +{
  4673. + void __iomem *base = ath79_gpio_base;
  4674. + unsigned long flags;
  4675. + bool ieq_1 = (soc_is_ar934x() ||
  4676. + soc_is_qca953x());
  4677. +
  4678. + if (gpio >= ath79_gpio_count)
  4679. + return -1;
  4680. +
  4681. + spin_lock_irqsave(&ath79_gpio_lock, flags);
  4682. +
  4683. + if ((ieq_1 && oe) || (!ieq_1 && !oe))
  4684. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
  4685. + base + AR71XX_GPIO_REG_OE);
  4686. + else
  4687. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
  4688. + base + AR71XX_GPIO_REG_OE);
  4689. +
  4690. + spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  4691. +
  4692. + return 0;
  4693. +}
  4694. +
  4695. static struct gpio_chip ath79_gpio_chip = {
  4696. .label = "ath79",
  4697. .get = ath79_gpio_get_value,
  4698. @@ -146,7 +184,8 @@
  4699. soc_is_ar913x() ||
  4700. soc_is_ar933x())
  4701. reg = AR71XX_GPIO_REG_FUNC;
  4702. - else if (soc_is_ar934x())
  4703. + else if (soc_is_ar934x() ||
  4704. + soc_is_qca953x() || soc_is_qca956x())
  4705. reg = AR934X_GPIO_REG_FUNC;
  4706. else
  4707. BUG();
  4708. @@ -154,6 +193,36 @@
  4709. return ath79_gpio_base + reg;
  4710. }
  4711. +static void __iomem *ath79_gpio_get_function2_reg(void)
  4712. +{
  4713. + u32 reg = 0;
  4714. +
  4715. + if (soc_is_ar71xx() ||
  4716. + soc_is_ar724x() ||
  4717. + soc_is_ar913x() ||
  4718. + soc_is_ar933x())
  4719. + reg = AR71XX_GPIO_REG_FUNC_2;
  4720. + else
  4721. + BUG();
  4722. +
  4723. + return ath79_gpio_base + reg;
  4724. +}
  4725. +
  4726. +
  4727. +void ath79_gpio_function2_setup(u32 set, u32 clear)
  4728. +{
  4729. + void __iomem *reg = ath79_gpio_get_function2_reg();
  4730. + unsigned long flags;
  4731. +
  4732. + spin_lock_irqsave(&ath79_gpio_lock, flags);
  4733. +
  4734. + __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
  4735. + /* flush write */
  4736. + __raw_readl(reg);
  4737. +
  4738. + spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  4739. +}
  4740. +
  4741. void ath79_gpio_function_setup(u32 set, u32 clear)
  4742. {
  4743. void __iomem *reg = ath79_gpio_get_function_reg();
  4744. @@ -178,6 +247,172 @@
  4745. ath79_gpio_function_setup(0, mask);
  4746. }
  4747. +void __init ath79_gpio_output_select(unsigned gpio, u8 val)
  4748. +{
  4749. + void __iomem *base = ath79_gpio_base;
  4750. + unsigned long flags;
  4751. + unsigned int reg, reg_base;
  4752. + unsigned long gpio_count;
  4753. + u32 t, s;
  4754. +
  4755. + if (soc_is_ar934x()) {
  4756. + gpio_count = AR934X_GPIO_COUNT;
  4757. + reg_base = AR934X_GPIO_REG_OUT_FUNC0;
  4758. + } else if (soc_is_qca953x()) {
  4759. + gpio_count = QCA953X_GPIO_COUNT;
  4760. + reg_base = QCA953X_GPIO_REG_OUT_FUNC0;
  4761. + } else if (soc_is_qca955x()) {
  4762. + gpio_count = QCA955X_GPIO_COUNT;
  4763. + reg_base = QCA955X_GPIO_REG_OUT_FUNC0;
  4764. + } else {
  4765. + BUG();
  4766. + }
  4767. +
  4768. + if (gpio >= gpio_count)
  4769. + return;
  4770. +
  4771. + reg = reg_base + 4 * (gpio / 4);
  4772. + s = 8 * (gpio % 4);
  4773. +
  4774. + spin_lock_irqsave(&ath79_gpio_lock, flags);
  4775. +
  4776. + t = __raw_readl(base + reg);
  4777. + t &= ~(0xff << s);
  4778. + t |= val << s;
  4779. + __raw_writel(t, base + reg);
  4780. +
  4781. + /* flush write */
  4782. + (void) __raw_readl(base + reg);
  4783. +
  4784. + spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  4785. +}
  4786. +
  4787. +static int ath79_gpio_irq_type(struct irq_data *d, unsigned type)
  4788. +{
  4789. + int offset = d->irq - ATH79_GPIO_IRQ_BASE;
  4790. + void __iomem *base = ath79_gpio_base;
  4791. + unsigned long flags;
  4792. + unsigned long int_type;
  4793. + unsigned long int_polarity;
  4794. + unsigned long bit = (1 << offset);
  4795. +
  4796. + spin_lock_irqsave(&ath79_gpio_lock, flags);
  4797. +
  4798. + int_type = __raw_readl(base + AR71XX_GPIO_REG_INT_TYPE);
  4799. + int_polarity = __raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY);
  4800. +
  4801. + gpio_both_edge &= ~bit;
  4802. +
  4803. + switch (type) {
  4804. + case IRQ_TYPE_EDGE_RISING:
  4805. + int_type &= ~bit;
  4806. + int_polarity |= bit;
  4807. + break;
  4808. +
  4809. + case IRQ_TYPE_EDGE_FALLING:
  4810. + int_type &= ~bit;
  4811. + int_polarity &= ~bit;
  4812. + break;
  4813. +
  4814. + case IRQ_TYPE_LEVEL_HIGH:
  4815. + int_type |= bit;
  4816. + int_polarity |= bit;
  4817. + break;
  4818. +
  4819. + case IRQ_TYPE_LEVEL_LOW:
  4820. + int_type |= bit;
  4821. + int_polarity &= ~bit;
  4822. + break;
  4823. +
  4824. + case IRQ_TYPE_EDGE_BOTH:
  4825. + int_type |= bit;
  4826. + /* set polarity based on current value */
  4827. + if (gpio_get_value(offset)) {
  4828. + int_polarity &= ~bit;
  4829. + } else {
  4830. + int_polarity |= bit;
  4831. + }
  4832. + /* flip this gpio in the interrupt handler */
  4833. + gpio_both_edge |= bit;
  4834. + break;
  4835. +
  4836. + default:
  4837. + spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  4838. + return -EINVAL;
  4839. + }
  4840. +
  4841. + __raw_writel(int_type, base + AR71XX_GPIO_REG_INT_TYPE);
  4842. + __raw_writel(int_polarity, base + AR71XX_GPIO_REG_INT_POLARITY);
  4843. +
  4844. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_MODE) | (1 << offset),
  4845. + base + AR71XX_GPIO_REG_INT_MODE);
  4846. +
  4847. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
  4848. + base + AR71XX_GPIO_REG_INT_ENABLE);
  4849. +
  4850. + spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  4851. + return 0;
  4852. +}
  4853. +
  4854. +static void ath79_gpio_irq_enable(struct irq_data *d)
  4855. +{
  4856. + int offset = d->irq - ATH79_GPIO_IRQ_BASE;
  4857. + void __iomem *base = ath79_gpio_base;
  4858. +
  4859. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) | (1 << offset),
  4860. + base + AR71XX_GPIO_REG_INT_ENABLE);
  4861. +}
  4862. +
  4863. +static void ath79_gpio_irq_disable(struct irq_data *d)
  4864. +{
  4865. + int offset = d->irq - ATH79_GPIO_IRQ_BASE;
  4866. + void __iomem *base = ath79_gpio_base;
  4867. +
  4868. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
  4869. + base + AR71XX_GPIO_REG_INT_ENABLE);
  4870. +}
  4871. +
  4872. +static struct irq_chip ath79_gpio_irqchip = {
  4873. + .name = "GPIO",
  4874. + .irq_enable = ath79_gpio_irq_enable,
  4875. + .irq_disable = ath79_gpio_irq_disable,
  4876. + .irq_set_type = ath79_gpio_irq_type,
  4877. +};
  4878. +
  4879. +static irqreturn_t ath79_gpio_irq(int irq, void *dev)
  4880. +{
  4881. + void __iomem *base = ath79_gpio_base;
  4882. + unsigned long stat = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING);
  4883. + int bit_num;
  4884. +
  4885. + for_each_set_bit(bit_num, &stat, sizeof(stat) * BITS_PER_BYTE) {
  4886. + unsigned long bit = BIT(bit_num);
  4887. +
  4888. + if (bit & gpio_both_edge) {
  4889. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY) ^ bit,
  4890. + base + AR71XX_GPIO_REG_INT_POLARITY);
  4891. + }
  4892. +
  4893. + generic_handle_irq(ATH79_GPIO_IRQ(bit_num));
  4894. + }
  4895. +
  4896. + return IRQ_HANDLED;
  4897. +}
  4898. +
  4899. +static int __init ath79_gpio_irq_init(struct gpio_chip *chip)
  4900. +{
  4901. + int irq;
  4902. + int irq_base = ATH79_GPIO_IRQ_BASE;
  4903. +
  4904. + for (irq = irq_base; irq < irq_base + chip->ngpio; irq++) {
  4905. + irq_set_chip_data(irq, chip);
  4906. + irq_set_chip_and_handler(irq, &ath79_gpio_irqchip, handle_simple_irq);
  4907. + irq_set_noprobe(irq);
  4908. + }
  4909. +
  4910. + return 0;
  4911. +}
  4912. +
  4913. void __init ath79_gpio_init(void)
  4914. {
  4915. int err;
  4916. @@ -194,14 +429,19 @@
  4917. ath79_gpio_count = AR933X_GPIO_COUNT;
  4918. else if (soc_is_ar934x())
  4919. ath79_gpio_count = AR934X_GPIO_COUNT;
  4920. + else if (soc_is_qca953x())
  4921. + ath79_gpio_count = QCA953X_GPIO_COUNT;
  4922. else if (soc_is_qca955x())
  4923. ath79_gpio_count = QCA955X_GPIO_COUNT;
  4924. + else if (soc_is_qca956x())
  4925. + ath79_gpio_count = QCA956X_GPIO_COUNT;
  4926. else
  4927. BUG();
  4928. ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
  4929. ath79_gpio_chip.ngpio = ath79_gpio_count;
  4930. - if (soc_is_ar934x() || soc_is_qca955x()) {
  4931. + if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
  4932. + soc_is_qca956x()) {
  4933. ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
  4934. ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
  4935. }
  4936. @@ -209,6 +449,10 @@
  4937. err = gpiochip_add(&ath79_gpio_chip);
  4938. if (err)
  4939. panic("cannot add AR71xx GPIO chip, error=%d", err);
  4940. +
  4941. + ath79_gpio_irq_init(&ath79_gpio_chip);
  4942. +
  4943. + request_irq(ATH79_MISC_IRQ(2), ath79_gpio_irq, 0, "ath79-gpio", NULL);
  4944. }
  4945. int gpio_get_value(unsigned gpio)
  4946. @@ -231,14 +475,22 @@
  4947. int gpio_to_irq(unsigned gpio)
  4948. {
  4949. - /* FIXME */
  4950. - return -EINVAL;
  4951. + if (gpio > ath79_gpio_count) {
  4952. + return -EINVAL;
  4953. + }
  4954. +
  4955. + return ATH79_GPIO_IRQ_BASE + gpio;
  4956. }
  4957. EXPORT_SYMBOL(gpio_to_irq);
  4958. int irq_to_gpio(unsigned irq)
  4959. {
  4960. - /* FIXME */
  4961. - return -EINVAL;
  4962. + unsigned gpio = irq - ATH79_GPIO_IRQ_BASE;
  4963. +
  4964. + if (gpio > ath79_gpio_count) {
  4965. + return -EINVAL;
  4966. + }
  4967. +
  4968. + return gpio;
  4969. }
  4970. EXPORT_SYMBOL(irq_to_gpio);
  4971. diff -Nur linux-4.1.43.orig/arch/mips/ath79/irq.c linux-4.1.43/arch/mips/ath79/irq.c
  4972. --- linux-4.1.43.orig/arch/mips/ath79/irq.c 2017-08-06 01:56:14.000000000 +0200
  4973. +++ linux-4.1.43/arch/mips/ath79/irq.c 2017-08-06 20:02:15.000000000 +0200
  4974. @@ -26,6 +26,8 @@
  4975. static void (*ath79_ip2_handler)(void);
  4976. static void (*ath79_ip3_handler)(void);
  4977. +static struct irq_chip ip2_chip;
  4978. +static struct irq_chip ip3_chip;
  4979. static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
  4980. {
  4981. @@ -106,7 +108,9 @@
  4982. else if (soc_is_ar724x() ||
  4983. soc_is_ar933x() ||
  4984. soc_is_ar934x() ||
  4985. - soc_is_qca955x())
  4986. + soc_is_qca953x() ||
  4987. + soc_is_qca955x() ||
  4988. + soc_is_qca956x())
  4989. ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
  4990. else
  4991. BUG();
  4992. @@ -147,12 +151,43 @@
  4993. for (i = ATH79_IP2_IRQ_BASE;
  4994. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  4995. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  4996. - handle_level_irq);
  4997. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  4998. irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  4999. }
  5000. +static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
  5001. +{
  5002. + u32 status;
  5003. +
  5004. + disable_irq_nosync(irq);
  5005. +
  5006. + status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
  5007. +
  5008. + if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
  5009. + ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
  5010. + generic_handle_irq(ATH79_IP2_IRQ(0));
  5011. + } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
  5012. + ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
  5013. + generic_handle_irq(ATH79_IP2_IRQ(1));
  5014. + } else {
  5015. + spurious_interrupt();
  5016. + }
  5017. +
  5018. + enable_irq(irq);
  5019. +}
  5020. +
  5021. +static void qca953x_irq_init(void)
  5022. +{
  5023. + int i;
  5024. +
  5025. + for (i = ATH79_IP2_IRQ_BASE;
  5026. + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  5027. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  5028. +
  5029. + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
  5030. +}
  5031. +
  5032. static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
  5033. {
  5034. u32 status;
  5035. @@ -222,19 +257,108 @@
  5036. for (i = ATH79_IP2_IRQ_BASE;
  5037. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  5038. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  5039. - handle_level_irq);
  5040. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  5041. irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
  5042. for (i = ATH79_IP3_IRQ_BASE;
  5043. i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
  5044. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  5045. - handle_level_irq);
  5046. + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  5047. irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  5048. }
  5049. +static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
  5050. +{
  5051. + u32 status;
  5052. +
  5053. + disable_irq_nosync(irq);
  5054. +
  5055. + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
  5056. + status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
  5057. +
  5058. + if (status == 0) {
  5059. + spurious_interrupt();
  5060. + goto enable;
  5061. + }
  5062. +
  5063. + if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
  5064. + /* TODO: flush DDR? */
  5065. + generic_handle_irq(ATH79_IP2_IRQ(0));
  5066. + }
  5067. +
  5068. + if (status & QCA956X_EXT_INT_WMAC_ALL) {
  5069. + /* TODO: flsuh DDR? */
  5070. + generic_handle_irq(ATH79_IP2_IRQ(1));
  5071. + }
  5072. +
  5073. +enable:
  5074. + enable_irq(irq);
  5075. +}
  5076. +
  5077. +static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
  5078. +{
  5079. + u32 status;
  5080. +
  5081. + disable_irq_nosync(irq);
  5082. +
  5083. + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
  5084. + status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
  5085. + QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
  5086. +
  5087. + if (status == 0) {
  5088. + spurious_interrupt();
  5089. + goto enable;
  5090. + }
  5091. +
  5092. + if (status & QCA956X_EXT_INT_USB1) {
  5093. + /* TODO: flush DDR? */
  5094. + generic_handle_irq(ATH79_IP3_IRQ(0));
  5095. + }
  5096. +
  5097. + if (status & QCA956X_EXT_INT_USB2) {
  5098. + /* TODO: flush DDR? */
  5099. + generic_handle_irq(ATH79_IP3_IRQ(1));
  5100. + }
  5101. +
  5102. + if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
  5103. + /* TODO: flush DDR? */
  5104. + generic_handle_irq(ATH79_IP3_IRQ(2));
  5105. + }
  5106. +
  5107. +enable:
  5108. + enable_irq(irq);
  5109. +}
  5110. +
  5111. +static void qca956x_enable_timer_cb(void) {
  5112. + u32 misc;
  5113. +
  5114. + misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
  5115. + misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
  5116. + ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
  5117. +}
  5118. +
  5119. +static void qca956x_irq_init(void)
  5120. +{
  5121. + int i;
  5122. +
  5123. + for (i = ATH79_IP2_IRQ_BASE;
  5124. + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  5125. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  5126. +
  5127. + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
  5128. +
  5129. + for (i = ATH79_IP3_IRQ_BASE;
  5130. + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
  5131. + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  5132. +
  5133. + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
  5134. +
  5135. + /* QCA956x timer init workaround has to be applied right before setting
  5136. + * up the clock. Else, there will be no jiffies */
  5137. + late_time_init = &qca956x_enable_timer_cb;
  5138. +}
  5139. +
  5140. asmlinkage void plat_irq_dispatch(void)
  5141. {
  5142. unsigned long pending;
  5143. @@ -335,8 +459,41 @@
  5144. do_IRQ(ATH79_CPU_IRQ(3));
  5145. }
  5146. +static void qca953x_ip3_handler(void)
  5147. +{
  5148. + ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
  5149. + do_IRQ(ATH79_CPU_IRQ(3));
  5150. +}
  5151. +
  5152. +static void ath79_ip2_disable(struct irq_data *data)
  5153. +{
  5154. + disable_irq(ATH79_CPU_IRQ(2));
  5155. +}
  5156. +
  5157. +static void ath79_ip2_enable(struct irq_data *data)
  5158. +{
  5159. + enable_irq(ATH79_CPU_IRQ(2));
  5160. +}
  5161. +
  5162. +static void ath79_ip3_disable(struct irq_data *data)
  5163. +{
  5164. + disable_irq(ATH79_CPU_IRQ(3));
  5165. +}
  5166. +
  5167. +static void ath79_ip3_enable(struct irq_data *data)
  5168. +{
  5169. + enable_irq(ATH79_CPU_IRQ(3));
  5170. +}
  5171. +
  5172. void __init arch_init_irq(void)
  5173. {
  5174. + ip2_chip = dummy_irq_chip;
  5175. + ip3_chip = dummy_irq_chip;
  5176. + ip2_chip.irq_disable = ath79_ip2_disable;
  5177. + ip2_chip.irq_enable = ath79_ip2_enable;
  5178. + ip3_chip.irq_disable = ath79_ip3_disable;
  5179. + ip3_chip.irq_enable = ath79_ip3_enable;
  5180. +
  5181. if (soc_is_ar71xx()) {
  5182. ath79_ip2_handler = ar71xx_ip2_handler;
  5183. ath79_ip3_handler = ar71xx_ip3_handler;
  5184. @@ -352,9 +509,15 @@
  5185. } else if (soc_is_ar934x()) {
  5186. ath79_ip2_handler = ath79_default_ip2_handler;
  5187. ath79_ip3_handler = ar934x_ip3_handler;
  5188. + } else if (soc_is_qca953x()) {
  5189. + ath79_ip2_handler = ath79_default_ip2_handler;
  5190. + ath79_ip3_handler = qca953x_ip3_handler;
  5191. } else if (soc_is_qca955x()) {
  5192. ath79_ip2_handler = ath79_default_ip2_handler;
  5193. ath79_ip3_handler = ath79_default_ip3_handler;
  5194. + } else if (soc_is_qca956x()) {
  5195. + ath79_ip2_handler = ath79_default_ip2_handler;
  5196. + ath79_ip3_handler = ath79_default_ip3_handler;
  5197. } else {
  5198. BUG();
  5199. }
  5200. @@ -364,6 +527,10 @@
  5201. if (soc_is_ar934x())
  5202. ar934x_ip2_irq_init();
  5203. + else if (soc_is_qca953x())
  5204. + qca953x_irq_init();
  5205. else if (soc_is_qca955x())
  5206. qca955x_irq_init();
  5207. + else if (soc_is_qca956x())
  5208. + qca956x_irq_init();
  5209. }
  5210. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-alfa-ap96.c linux-4.1.43/arch/mips/ath79/mach-alfa-ap96.c
  5211. --- linux-4.1.43.orig/arch/mips/ath79/mach-alfa-ap96.c 1970-01-01 01:00:00.000000000 +0100
  5212. +++ linux-4.1.43/arch/mips/ath79/mach-alfa-ap96.c 2017-08-06 20:02:15.000000000 +0200
  5213. @@ -0,0 +1,151 @@
  5214. +/*
  5215. + * ALFA Network AP96 board support
  5216. + *
  5217. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  5218. + *
  5219. + * This program is free software; you can redistribute it and/or modify it
  5220. + * under the terms of the GNU General Public License version 2 as published
  5221. + * by the Free Software Foundation.
  5222. + */
  5223. +
  5224. +#include <linux/init.h>
  5225. +#include <linux/bitops.h>
  5226. +#include <linux/gpio.h>
  5227. +#include <linux/platform_device.h>
  5228. +#include <linux/mmc/host.h>
  5229. +#include <linux/spi/spi.h>
  5230. +#include <linux/spi/mmc_spi.h>
  5231. +
  5232. +#include <asm/mach-ath79/ath79.h>
  5233. +#include <asm/mach-ath79/ar71xx_regs.h>
  5234. +
  5235. +#include "common.h"
  5236. +#include "dev-eth.h"
  5237. +#include "dev-gpio-buttons.h"
  5238. +#include "dev-spi.h"
  5239. +#include "dev-usb.h"
  5240. +#include "machtypes.h"
  5241. +#include "pci.h"
  5242. +
  5243. +#define ALFA_AP96_GPIO_PCIE_RESET 2
  5244. +#define ALFA_AP96_GPIO_SIM_DETECT 3
  5245. +#define ALFA_AP96_GPIO_MICROSD_CD 4
  5246. +#define ALFA_AP96_GPIO_PCIE_W_DISABLE 5
  5247. +
  5248. +#define ALFA_AP96_GPIO_BUTTON_RESET 11
  5249. +
  5250. +#define ALFA_AP96_KEYS_POLL_INTERVAL 20 /* msecs */
  5251. +#define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_AP96_KEYS_POLL_INTERVAL)
  5252. +
  5253. +static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = {
  5254. + {
  5255. + .desc = "Reset button",
  5256. + .type = EV_KEY,
  5257. + .code = KEY_RESTART,
  5258. + .debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL,
  5259. + .gpio = ALFA_AP96_GPIO_BUTTON_RESET,
  5260. + .active_low = 1,
  5261. + }
  5262. +};
  5263. +
  5264. +static struct mmc_spi_platform_data alfa_ap96_mmc_data = {
  5265. + .flags = MMC_SPI_USE_CD_GPIO,
  5266. + .cd_gpio = ALFA_AP96_GPIO_MICROSD_CD,
  5267. + .cd_debounce = 1,
  5268. + .caps = MMC_CAP_NEEDS_POLL,
  5269. + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
  5270. +};
  5271. +
  5272. +static struct ath79_spi_controller_data ap96_spi0_cdata = {
  5273. + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  5274. + .cs_line = 0,
  5275. + .is_flash = true,
  5276. +};
  5277. +
  5278. +static struct ath79_spi_controller_data ap96_spi1_cdata = {
  5279. + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  5280. + .cs_line = 1,
  5281. +};
  5282. +
  5283. +static struct ath79_spi_controller_data ap96_spi2_cdata = {
  5284. + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  5285. + .cs_line = 2,
  5286. +};
  5287. +
  5288. +static struct spi_board_info alfa_ap96_spi_info[] = {
  5289. + {
  5290. + .bus_num = 0,
  5291. + .chip_select = 0,
  5292. + .max_speed_hz = 25000000,
  5293. + .modalias = "m25p80",
  5294. + .controller_data = &ap96_spi0_cdata
  5295. + }, {
  5296. + .bus_num = 0,
  5297. + .chip_select = 1,
  5298. + .max_speed_hz = 25000000,
  5299. + .modalias = "mmc_spi",
  5300. + .platform_data = &alfa_ap96_mmc_data,
  5301. + .controller_data = &ap96_spi1_cdata
  5302. + }, {
  5303. + .bus_num = 0,
  5304. + .chip_select = 2,
  5305. + .max_speed_hz = 6250000,
  5306. + .modalias = "rtc-pcf2123",
  5307. + .controller_data = &ap96_spi2_cdata
  5308. + },
  5309. +};
  5310. +
  5311. +static struct ath79_spi_platform_data alfa_ap96_spi_data = {
  5312. + .bus_num = 0,
  5313. + .num_chipselect = 3,
  5314. +};
  5315. +
  5316. +static void __init alfa_ap96_gpio_setup(void)
  5317. +{
  5318. + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
  5319. + AR71XX_GPIO_FUNC_SPI_CS2_EN);
  5320. +
  5321. + gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD");
  5322. + gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD);
  5323. + gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset");
  5324. + gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1);
  5325. + gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable");
  5326. + gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1);
  5327. +}
  5328. +
  5329. +#define ALFA_AP96_WAN_PHYMASK BIT(4)
  5330. +#define ALFA_AP96_LAN_PHYMASK BIT(5)
  5331. +#define ALFA_AP96_MDIO_PHYMASK (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK)
  5332. +
  5333. +static void __init alfa_ap96_init(void)
  5334. +{
  5335. + alfa_ap96_gpio_setup();
  5336. +
  5337. + ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK);
  5338. +
  5339. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  5340. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  5341. + ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK;
  5342. + ath79_eth1_pll_data.pll_1000 = 0x110000;
  5343. +
  5344. + ath79_register_eth(0);
  5345. +
  5346. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  5347. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  5348. + ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK;
  5349. + ath79_eth1_pll_data.pll_1000 = 0x110000;
  5350. +
  5351. + ath79_register_eth(1);
  5352. +
  5353. + ath79_register_pci();
  5354. + ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info,
  5355. + ARRAY_SIZE(alfa_ap96_spi_info));
  5356. +
  5357. + ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL,
  5358. + ARRAY_SIZE(alfa_ap96_gpio_keys),
  5359. + alfa_ap96_gpio_keys);
  5360. + ath79_register_usb();
  5361. +}
  5362. +
  5363. +MIPS_MACHINE(ATH79_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96",
  5364. + alfa_ap96_init);
  5365. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-alfa-nx.c linux-4.1.43/arch/mips/ath79/mach-alfa-nx.c
  5366. --- linux-4.1.43.orig/arch/mips/ath79/mach-alfa-nx.c 1970-01-01 01:00:00.000000000 +0100
  5367. +++ linux-4.1.43/arch/mips/ath79/mach-alfa-nx.c 2017-08-06 20:02:15.000000000 +0200
  5368. @@ -0,0 +1,113 @@
  5369. +/*
  5370. + * ALFA Network N2/N5 board support
  5371. + *
  5372. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  5373. + *
  5374. + * This program is free software; you can redistribute it and/or modify it
  5375. + * under the terms of the GNU General Public License version 2 as published
  5376. + * by the Free Software Foundation.
  5377. + */
  5378. +
  5379. +#include <asm/mach-ath79/ar71xx_regs.h>
  5380. +#include <asm/mach-ath79/ath79.h>
  5381. +
  5382. +#include "common.h"
  5383. +#include "dev-eth.h"
  5384. +#include "dev-ap9x-pci.h"
  5385. +#include "dev-gpio-buttons.h"
  5386. +#include "dev-leds-gpio.h"
  5387. +#include "dev-m25p80.h"
  5388. +#include "machtypes.h"
  5389. +
  5390. +#define ALFA_NX_GPIO_LED_2 17
  5391. +#define ALFA_NX_GPIO_LED_3 16
  5392. +#define ALFA_NX_GPIO_LED_5 12
  5393. +#define ALFA_NX_GPIO_LED_6 8
  5394. +#define ALFA_NX_GPIO_LED_7 6
  5395. +#define ALFA_NX_GPIO_LED_8 7
  5396. +
  5397. +#define ALFA_NX_GPIO_BTN_RESET 11
  5398. +
  5399. +#define ALFA_NX_KEYS_POLL_INTERVAL 20 /* msecs */
  5400. +#define ALFA_NX_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_NX_KEYS_POLL_INTERVAL)
  5401. +
  5402. +#define ALFA_NX_MAC0_OFFSET 0
  5403. +#define ALFA_NX_MAC1_OFFSET 6
  5404. +#define ALFA_NX_CALDATA_OFFSET 0x1000
  5405. +
  5406. +static struct gpio_keys_button alfa_nx_gpio_keys[] __initdata = {
  5407. + {
  5408. + .desc = "Reset button",
  5409. + .type = EV_KEY,
  5410. + .code = KEY_RESTART,
  5411. + .debounce_interval = ALFA_NX_KEYS_DEBOUNCE_INTERVAL,
  5412. + .gpio = ALFA_NX_GPIO_BTN_RESET,
  5413. + .active_low = 1,
  5414. + }
  5415. +};
  5416. +
  5417. +static struct gpio_led alfa_nx_leds_gpio[] __initdata = {
  5418. + {
  5419. + .name = "alfa:green:led_2",
  5420. + .gpio = ALFA_NX_GPIO_LED_2,
  5421. + .active_low = 1,
  5422. + }, {
  5423. + .name = "alfa:green:led_3",
  5424. + .gpio = ALFA_NX_GPIO_LED_3,
  5425. + .active_low = 1,
  5426. + }, {
  5427. + .name = "alfa:red:led_5",
  5428. + .gpio = ALFA_NX_GPIO_LED_5,
  5429. + .active_low = 1,
  5430. + }, {
  5431. + .name = "alfa:amber:led_6",
  5432. + .gpio = ALFA_NX_GPIO_LED_6,
  5433. + .active_low = 1,
  5434. + }, {
  5435. + .name = "alfa:green:led_7",
  5436. + .gpio = ALFA_NX_GPIO_LED_7,
  5437. + .active_low = 1,
  5438. + }, {
  5439. + .name = "alfa:green:led_8",
  5440. + .gpio = ALFA_NX_GPIO_LED_8,
  5441. + .active_low = 1,
  5442. + }
  5443. +};
  5444. +
  5445. +static void __init alfa_nx_setup(void)
  5446. +{
  5447. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  5448. +
  5449. + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
  5450. + AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  5451. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  5452. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  5453. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  5454. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  5455. +
  5456. + ath79_register_m25p80(NULL);
  5457. +
  5458. + ath79_register_leds_gpio(0, ARRAY_SIZE(alfa_nx_leds_gpio),
  5459. + alfa_nx_leds_gpio);
  5460. +
  5461. + ath79_register_gpio_keys_polled(-1, ALFA_NX_KEYS_POLL_INTERVAL,
  5462. + ARRAY_SIZE(alfa_nx_gpio_keys),
  5463. + alfa_nx_gpio_keys);
  5464. +
  5465. + ath79_register_mdio(0, 0x0);
  5466. +
  5467. + ath79_init_mac(ath79_eth0_data.mac_addr,
  5468. + art + ALFA_NX_MAC0_OFFSET, 0);
  5469. + ath79_init_mac(ath79_eth1_data.mac_addr,
  5470. + art + ALFA_NX_MAC1_OFFSET, 0);
  5471. +
  5472. + /* WAN port */
  5473. + ath79_register_eth(0);
  5474. + /* LAN port */
  5475. + ath79_register_eth(1);
  5476. +
  5477. + ap91_pci_init(art + ALFA_NX_CALDATA_OFFSET, NULL);
  5478. +}
  5479. +
  5480. +MIPS_MACHINE(ATH79_MACH_ALFA_NX, "ALFA-NX", "ALFA Network N2/N5",
  5481. + alfa_nx_setup);
  5482. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-all0258n.c linux-4.1.43/arch/mips/ath79/mach-all0258n.c
  5483. --- linux-4.1.43.orig/arch/mips/ath79/mach-all0258n.c 1970-01-01 01:00:00.000000000 +0100
  5484. +++ linux-4.1.43/arch/mips/ath79/mach-all0258n.c 2017-08-06 20:02:15.000000000 +0200
  5485. @@ -0,0 +1,88 @@
  5486. +/*
  5487. + * Allnet ALL0258N support
  5488. + *
  5489. + * Copyright (C) 2011 Daniel Golle <dgolle@allnet.de>
  5490. + *
  5491. + * This program is free software; you can redistribute it and/or modify it
  5492. + * under the terms of the GNU General Public License version 2 as published
  5493. + * by the Free Software Foundation.
  5494. + */
  5495. +
  5496. +#include <asm/mach-ath79/ath79.h>
  5497. +
  5498. +#include "dev-eth.h"
  5499. +#include "dev-ap9x-pci.h"
  5500. +#include "dev-gpio-buttons.h"
  5501. +#include "dev-leds-gpio.h"
  5502. +#include "dev-m25p80.h"
  5503. +#include "machtypes.h"
  5504. +
  5505. +/* found via /sys/gpio/... try and error */
  5506. +#define ALL0258N_GPIO_BTN_RESET 1
  5507. +#define ALL0258N_GPIO_LED_RSSIHIGH 13
  5508. +#define ALL0258N_GPIO_LED_RSSIMEDIUM 15
  5509. +#define ALL0258N_GPIO_LED_RSSILOW 14
  5510. +
  5511. +/* defaults taken from others machs */
  5512. +#define ALL0258N_KEYS_POLL_INTERVAL 20 /* msecs */
  5513. +#define ALL0258N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0258N_KEYS_POLL_INTERVAL)
  5514. +
  5515. +/* showed up in the original firmware's bootlog */
  5516. +#define ALL0258N_SEC_PHYMASK BIT(3)
  5517. +
  5518. +static struct gpio_led all0258n_leds_gpio[] __initdata = {
  5519. + {
  5520. + .name = "all0258n:green:rssihigh",
  5521. + .gpio = ALL0258N_GPIO_LED_RSSIHIGH,
  5522. + .active_low = 1,
  5523. + }, {
  5524. + .name = "all0258n:yellow:rssimedium",
  5525. + .gpio = ALL0258N_GPIO_LED_RSSIMEDIUM,
  5526. + .active_low = 1,
  5527. + }, {
  5528. + .name = "all0258n:red:rssilow",
  5529. + .gpio = ALL0258N_GPIO_LED_RSSILOW,
  5530. + .active_low = 1,
  5531. + }
  5532. +};
  5533. +
  5534. +static struct gpio_keys_button all0258n_gpio_keys[] __initdata = {
  5535. + {
  5536. + .desc = "reset",
  5537. + .type = EV_KEY,
  5538. + .code = KEY_RESTART,
  5539. + .debounce_interval = ALL0258N_KEYS_DEBOUNCE_INTERVAL,
  5540. + .gpio = ALL0258N_GPIO_BTN_RESET,
  5541. + .active_low = 1,
  5542. + }
  5543. +};
  5544. +
  5545. +static void __init all0258n_setup(void)
  5546. +{
  5547. + u8 *mac = (u8 *) KSEG1ADDR(0x1f7f0000);
  5548. + u8 *ee = (u8 *) KSEG1ADDR(0x1f7f1000);
  5549. +
  5550. + ath79_register_m25p80(NULL);
  5551. +
  5552. + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0258n_leds_gpio),
  5553. + all0258n_leds_gpio);
  5554. +
  5555. + ath79_register_gpio_keys_polled(-1, ALL0258N_KEYS_POLL_INTERVAL,
  5556. + ARRAY_SIZE(all0258n_gpio_keys),
  5557. + all0258n_gpio_keys);
  5558. +
  5559. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  5560. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  5561. +
  5562. + ath79_eth1_data.phy_mask = ALL0258N_SEC_PHYMASK;
  5563. +
  5564. + ath79_register_mdio(0, 0x0);
  5565. +
  5566. + ath79_register_eth(0);
  5567. + ath79_register_eth(1);
  5568. +
  5569. + ap91_pci_init(ee, mac);
  5570. +}
  5571. +
  5572. +MIPS_MACHINE(ATH79_MACH_ALL0258N, "ALL0258N", "Allnet ALL0258N",
  5573. + all0258n_setup);
  5574. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-all0315n.c linux-4.1.43/arch/mips/ath79/mach-all0315n.c
  5575. --- linux-4.1.43.orig/arch/mips/ath79/mach-all0315n.c 1970-01-01 01:00:00.000000000 +0100
  5576. +++ linux-4.1.43/arch/mips/ath79/mach-all0315n.c 2017-08-06 20:02:15.000000000 +0200
  5577. @@ -0,0 +1,85 @@
  5578. +/*
  5579. + * Allnet ALL0315N support
  5580. + *
  5581. + * Copyright (C) 2012 Daniel Golle <dgolle@allnet.de>
  5582. + *
  5583. + *
  5584. + * This program is free software; you can redistribute it and/or modify it
  5585. + * under the terms of the GNU General Public License version 2 as published
  5586. + * by the Free Software Foundation.
  5587. + */
  5588. +
  5589. +#include <asm/mach-ath79/ath79.h>
  5590. +#include <asm/mach-ath79/ar71xx_regs.h>
  5591. +
  5592. +#include "common.h"
  5593. +#include "dev-eth.h"
  5594. +#include "dev-ap9x-pci.h"
  5595. +#include "dev-gpio-buttons.h"
  5596. +#include "dev-m25p80.h"
  5597. +#include "dev-leds-gpio.h"
  5598. +#include "machtypes.h"
  5599. +#include "pci.h"
  5600. +
  5601. +#define ALL0315N_GPIO_BTN_RESET 0
  5602. +#define ALL0315N_GPIO_LED_RSSIHIGH 14
  5603. +#define ALL0315N_GPIO_LED_RSSIMEDIUM 15
  5604. +#define ALL0315N_GPIO_LED_RSSILOW 16
  5605. +
  5606. +#define ALL0315N_KEYS_POLL_INTERVAL 20 /* msecs */
  5607. +#define ALL0315N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0315N_KEYS_POLL_INTERVAL)
  5608. +
  5609. +static struct gpio_led all0315n_leds_gpio[] __initdata = {
  5610. + {
  5611. + .name = "all0315n:green:rssihigh",
  5612. + .gpio = ALL0315N_GPIO_LED_RSSIHIGH,
  5613. + .active_low = 1,
  5614. + }, {
  5615. + .name = "all0315n:yellow:rssimedium",
  5616. + .gpio = ALL0315N_GPIO_LED_RSSIMEDIUM,
  5617. + .active_low = 1,
  5618. + }, {
  5619. + .name = "all0315n:red:rssilow",
  5620. + .gpio = ALL0315N_GPIO_LED_RSSILOW,
  5621. + .active_low = 1,
  5622. + }
  5623. +};
  5624. +
  5625. +static struct gpio_keys_button all0315n_gpio_keys[] __initdata = {
  5626. + {
  5627. + .desc = "reset",
  5628. + .type = EV_KEY,
  5629. + .code = KEY_RESTART,
  5630. + .debounce_interval = ALL0315N_KEYS_DEBOUNCE_INTERVAL,
  5631. + .gpio = ALL0315N_GPIO_BTN_RESET,
  5632. + .active_low = 1,
  5633. + }
  5634. +};
  5635. +
  5636. +static void __init all0315n_setup(void)
  5637. +{
  5638. + u8 *mac = (u8 *) KSEG1ADDR(0x1ffc0000);
  5639. + u8 *ee = (u8 *) KSEG1ADDR(0x1ffc1000);
  5640. +
  5641. + ath79_register_m25p80(NULL);
  5642. +
  5643. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  5644. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  5645. + ath79_eth0_data.phy_mask = BIT(0);
  5646. +
  5647. + ath79_register_mdio(0, 0x0);
  5648. + ath79_register_eth(0);
  5649. +
  5650. + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0315n_leds_gpio),
  5651. + all0315n_leds_gpio);
  5652. +
  5653. + ath79_register_gpio_keys_polled(-1, ALL0315N_KEYS_POLL_INTERVAL,
  5654. + ARRAY_SIZE(all0315n_gpio_keys),
  5655. + all0315n_gpio_keys);
  5656. +
  5657. + ap9x_pci_setup_wmac_led_pin(0, 1);
  5658. + ap91_pci_init(ee, NULL);
  5659. +}
  5660. +
  5661. +MIPS_MACHINE(ATH79_MACH_ALL0315N, "ALL0315N", "Allnet ALL0315N",
  5662. + all0315n_setup);
  5663. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-antminer-s1.c linux-4.1.43/arch/mips/ath79/mach-antminer-s1.c
  5664. --- linux-4.1.43.orig/arch/mips/ath79/mach-antminer-s1.c 1970-01-01 01:00:00.000000000 +0100
  5665. +++ linux-4.1.43/arch/mips/ath79/mach-antminer-s1.c 2017-08-06 20:02:15.000000000 +0200
  5666. @@ -0,0 +1,98 @@
  5667. +/*
  5668. + * Bitmain Antminer S1 board support
  5669. + *
  5670. + * Copyright (C) 2015 L. D. Pinney <ldpinney@gmail.com>
  5671. + *
  5672. + * This program is free software; you can redistribute it and/or modify it
  5673. + * under the terms of the GNU General Public License version 2 as published
  5674. + * by the Free Software Foundation.
  5675. + */
  5676. +
  5677. +#include <linux/gpio.h>
  5678. +
  5679. +#include <asm/mach-ath79/ath79.h>
  5680. +#include <asm/mach-ath79/ar71xx_regs.h>
  5681. +
  5682. +#include "common.h"
  5683. +#include "dev-eth.h"
  5684. +#include "dev-gpio-buttons.h"
  5685. +#include "dev-leds-gpio.h"
  5686. +#include "dev-m25p80.h"
  5687. +#include "dev-wmac.h"
  5688. +#include "machtypes.h"
  5689. +#include "dev-usb.h"
  5690. +
  5691. +#define ANTMINER_S1_GPIO_BTN_RESET 11
  5692. +
  5693. +#define ANTMINER_S1_GPIO_LED_SYSTEM 23
  5694. +#define ANTMINER_S1_GPIO_LED_WLAN 0
  5695. +#define ANTMINER_S1_GPIO_USB_POWER 26
  5696. +
  5697. +#define ANTMINER_S1_KEYSPOLL_INTERVAL 20 /* msecs */
  5698. +#define ANTMINER_S1_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S1_KEYSPOLL_INTERVAL)
  5699. +
  5700. +static const char *ANTMINER_S1_part_probes[] = {
  5701. + "tp-link",
  5702. + NULL,
  5703. +};
  5704. +
  5705. +static struct flash_platform_data ANTMINER_S1_flash_data = {
  5706. + .part_probes = ANTMINER_S1_part_probes,
  5707. +};
  5708. +
  5709. +static struct gpio_led ANTMINER_S1_leds_gpio[] __initdata = {
  5710. + {
  5711. + .name = "antminer-s1:green:system",
  5712. + .gpio = ANTMINER_S1_GPIO_LED_SYSTEM,
  5713. + .active_low = 0,
  5714. + },{
  5715. + .name = "antminer-s1:green:wlan",
  5716. + .gpio = ANTMINER_S1_GPIO_LED_WLAN,
  5717. + .active_low = 0,
  5718. + },
  5719. +};
  5720. +
  5721. +static struct gpio_keys_button ANTMINER_S1_GPIO_keys[] __initdata = {
  5722. + {
  5723. + .desc = "reset",
  5724. + .type = EV_KEY,
  5725. + .code = KEY_RESTART,
  5726. + .debounce_interval = ANTMINER_S1_KEYSDEBOUNCE_INTERVAL,
  5727. + .gpio = ANTMINER_S1_GPIO_BTN_RESET,
  5728. + .active_low = 0,
  5729. + },
  5730. +};
  5731. +
  5732. +static void __init antminer_s1_setup(void)
  5733. +{
  5734. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  5735. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  5736. +
  5737. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  5738. + ath79_setup_ar933x_phy4_switch(false, false);
  5739. +
  5740. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S1_leds_gpio),
  5741. + ANTMINER_S1_leds_gpio);
  5742. +
  5743. + ath79_register_gpio_keys_polled(-1, ANTMINER_S1_KEYSPOLL_INTERVAL,
  5744. + ARRAY_SIZE(ANTMINER_S1_GPIO_keys),
  5745. + ANTMINER_S1_GPIO_keys);
  5746. +
  5747. + gpio_request_one(ANTMINER_S1_GPIO_USB_POWER,
  5748. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  5749. + "USB power");
  5750. + ath79_register_usb();
  5751. +
  5752. + ath79_register_m25p80(&ANTMINER_S1_flash_data);
  5753. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  5754. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  5755. +
  5756. + ath79_register_mdio(0, 0x0);
  5757. + ath79_register_eth(0);
  5758. + ath79_register_eth(1);
  5759. +
  5760. + ath79_register_wmac(ee, mac);
  5761. +}
  5762. +
  5763. +MIPS_MACHINE(ATH79_MACH_ANTMINER_S1, "ANTMINER-S1",
  5764. + "Antminer-S1", antminer_s1_setup);
  5765. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-antminer-s3.c linux-4.1.43/arch/mips/ath79/mach-antminer-s3.c
  5766. --- linux-4.1.43.orig/arch/mips/ath79/mach-antminer-s3.c 1970-01-01 01:00:00.000000000 +0100
  5767. +++ linux-4.1.43/arch/mips/ath79/mach-antminer-s3.c 2017-08-06 20:02:15.000000000 +0200
  5768. @@ -0,0 +1,103 @@
  5769. +/*
  5770. + * Bitmain Antminer S3 board support
  5771. + *
  5772. + * Copyright (C) 2015 L. D. Pinney <ldpinney@gmail.com>
  5773. + *
  5774. + * This program is free software; you can redistribute it and/or modify it
  5775. + * under the terms of the GNU General Public License version 2 as published
  5776. + * by the Free Software Foundation.
  5777. + */
  5778. +
  5779. +#include <linux/gpio.h>
  5780. +
  5781. +#include <asm/mach-ath79/ath79.h>
  5782. +#include <asm/mach-ath79/ar71xx_regs.h>
  5783. +
  5784. +#include "common.h"
  5785. +#include "dev-eth.h"
  5786. +#include "dev-gpio-buttons.h"
  5787. +#include "dev-leds-gpio.h"
  5788. +#include "dev-m25p80.h"
  5789. +#include "dev-wmac.h"
  5790. +#include "machtypes.h"
  5791. +#include "dev-usb.h"
  5792. +
  5793. +#define ANTMINER_S3_GPIO_LED_WLAN 0
  5794. +#define ANTMINER_S3_GPIO_LED_SYSTEM 17
  5795. +#define ANTMINER_S3_GPIO_LED_LAN 22
  5796. +#define ANTMINER_S3_GPIO_USB_POWER 26
  5797. +
  5798. +#define ANTMINER_S3_GPIO_BTN_RESET 11
  5799. +
  5800. +#define ANTMINER_S3_KEYSPOLL_INTERVAL 88 /* msecs */
  5801. +#define ANTMINER_S3_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S3_KEYSPOLL_INTERVAL)
  5802. +
  5803. +static const char *ANTMINER_S3_part_probes[] = {
  5804. + "tp-link",
  5805. + NULL,
  5806. +};
  5807. +
  5808. +static struct flash_platform_data ANTMINER_S3_flash_data = {
  5809. + .part_probes = ANTMINER_S3_part_probes,
  5810. +};
  5811. +
  5812. +static struct gpio_led ANTMINER_S3_leds_gpio[] __initdata = {
  5813. + {
  5814. + .name = "antminer-s3:green:wlan",
  5815. + .gpio = ANTMINER_S3_GPIO_LED_WLAN,
  5816. + .active_low = 0,
  5817. + },{
  5818. + .name = "antminer-s3:green:system",
  5819. + .gpio = ANTMINER_S3_GPIO_LED_SYSTEM,
  5820. + .active_low = 0,
  5821. + },{
  5822. + .name = "antminer-s3:yellow:lan",
  5823. + .gpio = ANTMINER_S3_GPIO_LED_LAN,
  5824. + .active_low = 0,
  5825. + },
  5826. +};
  5827. +
  5828. +static struct gpio_keys_button ANTMINER_S3_GPIO_keys[] __initdata = {
  5829. + {
  5830. + .desc = "reset",
  5831. + .type = EV_KEY,
  5832. + .code = KEY_RESTART,
  5833. + .debounce_interval = ANTMINER_S3_KEYSDEBOUNCE_INTERVAL,
  5834. + .gpio = ANTMINER_S3_GPIO_BTN_RESET,
  5835. + .active_low = 0,
  5836. + },
  5837. +};
  5838. +
  5839. +static void __init antminer_s3_setup(void)
  5840. +{
  5841. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  5842. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  5843. +
  5844. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  5845. + ath79_setup_ar933x_phy4_switch(false, false);
  5846. +
  5847. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S3_leds_gpio),
  5848. + ANTMINER_S3_leds_gpio);
  5849. +
  5850. + ath79_register_gpio_keys_polled(-1, ANTMINER_S3_KEYSPOLL_INTERVAL,
  5851. + ARRAY_SIZE(ANTMINER_S3_GPIO_keys),
  5852. + ANTMINER_S3_GPIO_keys);
  5853. +
  5854. + gpio_request_one(ANTMINER_S3_GPIO_USB_POWER,
  5855. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  5856. + "USB power");
  5857. + ath79_register_usb();
  5858. +
  5859. + ath79_register_m25p80(&ANTMINER_S3_flash_data);
  5860. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  5861. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  5862. +
  5863. + ath79_register_mdio(0, 0x0);
  5864. + ath79_register_eth(0);
  5865. + ath79_register_eth(1);
  5866. +
  5867. + ath79_register_wmac(ee, mac);
  5868. +}
  5869. +
  5870. +MIPS_MACHINE(ATH79_MACH_ANTMINER_S3, "ANTMINER-S3",
  5871. + "Antminer-S3", antminer_s3_setup);
  5872. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap113.c linux-4.1.43/arch/mips/ath79/mach-ap113.c
  5873. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap113.c 1970-01-01 01:00:00.000000000 +0100
  5874. +++ linux-4.1.43/arch/mips/ath79/mach-ap113.c 2017-08-06 20:02:15.000000000 +0200
  5875. @@ -0,0 +1,84 @@
  5876. +/*
  5877. + * Atheros AP113 board support
  5878. + *
  5879. + * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org>
  5880. + *
  5881. + * This program is free software; you can redistribute it and/or modify it
  5882. + * under the terms of the GNU General Public License version 2 as published
  5883. + * by the Free Software Foundation.
  5884. + */
  5885. +
  5886. +#include "dev-eth.h"
  5887. +#include "dev-gpio-buttons.h"
  5888. +#include "dev-leds-gpio.h"
  5889. +#include "dev-m25p80.h"
  5890. +#include "pci.h"
  5891. +#include "dev-usb.h"
  5892. +#include "machtypes.h"
  5893. +
  5894. +#define AP113_GPIO_LED_USB 0
  5895. +#define AP113_GPIO_LED_STATUS 1
  5896. +#define AP113_GPIO_LED_ST 11
  5897. +
  5898. +#define AP113_GPIO_BTN_JUMPSTART 12
  5899. +
  5900. +#define AP113_KEYS_POLL_INTERVAL 20 /* msecs */
  5901. +#define AP113_KEYS_DEBOUNCE_INTERVAL (3 * AP113_KEYS_POLL_INTERVAL)
  5902. +
  5903. +static struct gpio_led ap113_leds_gpio[] __initdata = {
  5904. + {
  5905. + .name = "ap113:green:usb",
  5906. + .gpio = AP113_GPIO_LED_USB,
  5907. + .active_low = 1,
  5908. + },
  5909. + {
  5910. + .name = "ap113:green:status",
  5911. + .gpio = AP113_GPIO_LED_STATUS,
  5912. + .active_low = 1,
  5913. + },
  5914. + {
  5915. + .name = "ap113:green:st",
  5916. + .gpio = AP113_GPIO_LED_ST,
  5917. + .active_low = 1,
  5918. + }
  5919. +};
  5920. +
  5921. +static struct gpio_keys_button ap113_gpio_keys[] __initdata = {
  5922. + {
  5923. + .desc = "jumpstart button",
  5924. + .type = EV_KEY,
  5925. + .code = KEY_WPS_BUTTON,
  5926. + .debounce_interval = AP113_KEYS_DEBOUNCE_INTERVAL,
  5927. + .gpio = AP113_GPIO_BTN_JUMPSTART,
  5928. + .active_low = 1,
  5929. + },
  5930. +};
  5931. +
  5932. +static void __init ap113_setup(void)
  5933. +{
  5934. + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
  5935. +
  5936. + ath79_register_m25p80(NULL);
  5937. +
  5938. + ath79_register_mdio(0, ~BIT(0));
  5939. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  5940. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  5941. + ath79_eth0_data.speed = SPEED_1000;
  5942. + ath79_eth0_data.duplex = DUPLEX_FULL;
  5943. + ath79_eth0_data.phy_mask = BIT(0);
  5944. +
  5945. + ath79_register_eth(0);
  5946. +
  5947. + ath79_register_gpio_keys_polled(-1, AP113_KEYS_POLL_INTERVAL,
  5948. + ARRAY_SIZE(ap113_gpio_keys),
  5949. + ap113_gpio_keys);
  5950. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap113_leds_gpio),
  5951. + ap113_leds_gpio);
  5952. +
  5953. + ath79_register_pci();
  5954. +
  5955. + ath79_register_usb();
  5956. +}
  5957. +
  5958. +MIPS_MACHINE(ATH79_MACH_AP113, "AP113", "Atheros AP113",
  5959. + ap113_setup);
  5960. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap121.c linux-4.1.43/arch/mips/ath79/mach-ap121.c
  5961. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap121.c 2017-08-06 01:56:14.000000000 +0200
  5962. +++ linux-4.1.43/arch/mips/ath79/mach-ap121.c 2017-08-06 20:02:15.000000000 +0200
  5963. @@ -1,19 +1,21 @@
  5964. /*
  5965. * Atheros AP121 board support
  5966. *
  5967. - * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  5968. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  5969. *
  5970. * This program is free software; you can redistribute it and/or modify it
  5971. * under the terms of the GNU General Public License version 2 as published
  5972. * by the Free Software Foundation.
  5973. */
  5974. -#include "machtypes.h"
  5975. +#include "dev-eth.h"
  5976. #include "dev-gpio-buttons.h"
  5977. #include "dev-leds-gpio.h"
  5978. +#include "dev-m25p80.h"
  5979. #include "dev-spi.h"
  5980. #include "dev-usb.h"
  5981. #include "dev-wmac.h"
  5982. +#include "machtypes.h"
  5983. #define AP121_GPIO_LED_WLAN 0
  5984. #define AP121_GPIO_LED_USB 1
  5985. @@ -24,7 +26,14 @@
  5986. #define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
  5987. #define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
  5988. -#define AP121_CAL_DATA_ADDR 0x1fff1000
  5989. +#define AP121_MAC0_OFFSET 0x0000
  5990. +#define AP121_MAC1_OFFSET 0x0006
  5991. +#define AP121_CALDATA_OFFSET 0x1000
  5992. +#define AP121_WMAC_MAC_OFFSET 0x1002
  5993. +
  5994. +#define AP121_MINI_GPIO_LED_WLAN 0
  5995. +#define AP121_MINI_GPIO_BTN_JUMPSTART 12
  5996. +#define AP121_MINI_GPIO_BTN_RESET 11
  5997. static struct gpio_led ap121_leds_gpio[] __initdata = {
  5998. {
  5999. @@ -58,35 +67,78 @@
  6000. }
  6001. };
  6002. -static struct spi_board_info ap121_spi_info[] = {
  6003. +static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
  6004. {
  6005. - .bus_num = 0,
  6006. - .chip_select = 0,
  6007. - .max_speed_hz = 25000000,
  6008. - .modalias = "mx25l1606e",
  6009. - }
  6010. + .name = "ap121:green:wlan",
  6011. + .gpio = AP121_MINI_GPIO_LED_WLAN,
  6012. + .active_low = 0,
  6013. + },
  6014. };
  6015. -static struct ath79_spi_platform_data ap121_spi_data = {
  6016. - .bus_num = 0,
  6017. - .num_chipselect = 1,
  6018. +static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
  6019. + {
  6020. + .desc = "jumpstart button",
  6021. + .type = EV_KEY,
  6022. + .code = KEY_WPS_BUTTON,
  6023. + .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
  6024. + .gpio = AP121_MINI_GPIO_BTN_JUMPSTART,
  6025. + .active_low = 1,
  6026. + },
  6027. + {
  6028. + .desc = "reset button",
  6029. + .type = EV_KEY,
  6030. + .code = KEY_RESTART,
  6031. + .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
  6032. + .gpio = AP121_MINI_GPIO_BTN_RESET,
  6033. + .active_low = 1,
  6034. + }
  6035. };
  6036. +static void __init ap121_common_setup(void)
  6037. +{
  6038. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  6039. +
  6040. + ath79_register_m25p80(NULL);
  6041. + ath79_register_wmac(art + AP121_CALDATA_OFFSET,
  6042. + art + AP121_WMAC_MAC_OFFSET);
  6043. +
  6044. + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
  6045. + ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
  6046. +
  6047. + ath79_register_mdio(0, 0x0);
  6048. +
  6049. + /* LAN ports */
  6050. + ath79_register_eth(1);
  6051. +
  6052. + /* WAN port */
  6053. + ath79_register_eth(0);
  6054. +}
  6055. +
  6056. static void __init ap121_setup(void)
  6057. {
  6058. - u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
  6059. + ap121_common_setup();
  6060. ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
  6061. ap121_leds_gpio);
  6062. ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
  6063. ARRAY_SIZE(ap121_gpio_keys),
  6064. ap121_gpio_keys);
  6065. -
  6066. - ath79_register_spi(&ap121_spi_data, ap121_spi_info,
  6067. - ARRAY_SIZE(ap121_spi_info));
  6068. ath79_register_usb();
  6069. - ath79_register_wmac(cal_data);
  6070. }
  6071. MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
  6072. ap121_setup);
  6073. +
  6074. +static void __init ap121_mini_setup(void)
  6075. +{
  6076. + ap121_common_setup();
  6077. +
  6078. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
  6079. + ap121_mini_leds_gpio);
  6080. + ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
  6081. + ARRAY_SIZE(ap121_mini_gpio_keys),
  6082. + ap121_mini_gpio_keys);
  6083. +}
  6084. +
  6085. +MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
  6086. + ap121_mini_setup);
  6087. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap132.c linux-4.1.43/arch/mips/ath79/mach-ap132.c
  6088. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap132.c 1970-01-01 01:00:00.000000000 +0100
  6089. +++ linux-4.1.43/arch/mips/ath79/mach-ap132.c 2017-08-06 20:02:15.000000000 +0200
  6090. @@ -0,0 +1,189 @@
  6091. +/*
  6092. + * Atheros AP132 reference board support
  6093. + *
  6094. + * Copyright (c) 2012 Qualcomm Atheros
  6095. + * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
  6096. + * Copyright (c) 2013 Embedded Wireless GmbH <info@embeddedwireless.de>
  6097. + *
  6098. + * Permission to use, copy, modify, and/or distribute this software for any
  6099. + * purpose with or without fee is hereby granted, provided that the above
  6100. + * copyright notice and this permission notice appear in all copies.
  6101. + *
  6102. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  6103. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  6104. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  6105. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  6106. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  6107. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  6108. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  6109. + *
  6110. + */
  6111. +
  6112. +#include <linux/platform_device.h>
  6113. +#include <linux/ar8216_platform.h>
  6114. +
  6115. +#include <asm/mach-ath79/ar71xx_regs.h>
  6116. +
  6117. +#include "common.h"
  6118. +#include "dev-ap9x-pci.h"
  6119. +#include "dev-gpio-buttons.h"
  6120. +#include "dev-eth.h"
  6121. +#include "dev-leds-gpio.h"
  6122. +#include "dev-m25p80.h"
  6123. +#include "dev-usb.h"
  6124. +#include "dev-wmac.h"
  6125. +#include "machtypes.h"
  6126. +
  6127. +#define AP132_GPIO_LED_USB 4
  6128. +#define AP132_GPIO_LED_WLAN_5G 12
  6129. +#define AP132_GPIO_LED_WLAN_2G 13
  6130. +#define AP132_GPIO_LED_STATUS_RED 14
  6131. +#define AP132_GPIO_LED_WPS_RED 15
  6132. +
  6133. +#define AP132_GPIO_BTN_WPS 16
  6134. +
  6135. +#define AP132_KEYS_POLL_INTERVAL 20 /* msecs */
  6136. +#define AP132_KEYS_DEBOUNCE_INTERVAL (3 * AP132_KEYS_POLL_INTERVAL)
  6137. +
  6138. +#define AP132_MAC0_OFFSET 0
  6139. +#define AP132_WMAC_CALDATA_OFFSET 0x1000
  6140. +
  6141. +static struct gpio_led ap132_leds_gpio[] __initdata = {
  6142. + {
  6143. + .name = "ap132:red:status",
  6144. + .gpio = AP132_GPIO_LED_STATUS_RED,
  6145. + .active_low = 1,
  6146. + },
  6147. + {
  6148. + .name = "ap132:red:wps",
  6149. + .gpio = AP132_GPIO_LED_WPS_RED,
  6150. + .active_low = 1,
  6151. + },
  6152. + {
  6153. + .name = "ap132:red:wlan-2g",
  6154. + .gpio = AP132_GPIO_LED_WLAN_2G,
  6155. + .active_low = 1,
  6156. + },
  6157. + {
  6158. + .name = "ap132:red:usb",
  6159. + .gpio = AP132_GPIO_LED_USB,
  6160. + .active_low = 1,
  6161. + }
  6162. +};
  6163. +
  6164. +static struct gpio_keys_button ap132_gpio_keys[] __initdata = {
  6165. + {
  6166. + .desc = "WPS button",
  6167. + .type = EV_KEY,
  6168. + .code = KEY_WPS_BUTTON,
  6169. + .debounce_interval = AP132_KEYS_DEBOUNCE_INTERVAL,
  6170. + .gpio = AP132_GPIO_BTN_WPS,
  6171. + .active_low = 1,
  6172. + },
  6173. +};
  6174. +
  6175. +static struct ar8327_pad_cfg ap132_ar8327_pad0_cfg;
  6176. +
  6177. +static struct ar8327_platform_data ap132_ar8327_data = {
  6178. + .pad0_cfg = &ap132_ar8327_pad0_cfg,
  6179. + .port0_cfg = {
  6180. + .force_link = 1,
  6181. + .speed = AR8327_PORT_SPEED_1000,
  6182. + .duplex = 1,
  6183. + .txpause = 1,
  6184. + .rxpause = 1,
  6185. + },
  6186. +};
  6187. +
  6188. +static struct mdio_board_info ap132_mdio1_info[] = {
  6189. + {
  6190. + .bus_id = "ag71xx-mdio.1",
  6191. + .phy_addr = 0,
  6192. + .platform_data = &ap132_ar8327_data,
  6193. + },
  6194. +};
  6195. +
  6196. +static void __init ap132_mdio_setup(void)
  6197. +{
  6198. + void __iomem *base;
  6199. + u32 t;
  6200. +
  6201. +#define GPIO_IN_ENABLE3_ADDRESS 0x0050
  6202. +#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000
  6203. +#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16
  6204. +#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)
  6205. +#define GPIO_OUT_FUNCTION4_ADDRESS 0x003c
  6206. +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000
  6207. +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24
  6208. +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK)
  6209. +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00
  6210. +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8
  6211. +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)
  6212. +
  6213. + base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
  6214. +
  6215. + t = __raw_readl(base + GPIO_IN_ENABLE3_ADDRESS);
  6216. + t &= ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK;
  6217. + t |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19);
  6218. + __raw_writel(t, base + GPIO_IN_ENABLE3_ADDRESS);
  6219. +
  6220. +
  6221. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 19), base + AR71XX_GPIO_REG_OE);
  6222. +
  6223. + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 17), base + AR71XX_GPIO_REG_OE);
  6224. +
  6225. +
  6226. + t = __raw_readl(base + GPIO_OUT_FUNCTION4_ADDRESS);
  6227. + t &= ~(GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK);
  6228. + t |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21);
  6229. + __raw_writel(t, base + GPIO_OUT_FUNCTION4_ADDRESS);
  6230. +
  6231. + iounmap(base);
  6232. +
  6233. +}
  6234. +
  6235. +static void __init ap132_setup(void)
  6236. +{
  6237. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  6238. +
  6239. + ath79_register_m25p80(NULL);
  6240. +
  6241. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio),
  6242. + ap132_leds_gpio);
  6243. + ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL,
  6244. + ARRAY_SIZE(ap132_gpio_keys),
  6245. + ap132_gpio_keys);
  6246. +
  6247. + ath79_register_usb();
  6248. +
  6249. + ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL);
  6250. +
  6251. + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
  6252. + ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
  6253. + ap132_ar8327_pad0_cfg.sgmii_delay_en = true;
  6254. +
  6255. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  6256. +
  6257. + ap132_mdio_setup();
  6258. +
  6259. + ath79_register_mdio(1, 0x0);
  6260. +
  6261. + ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0);
  6262. +
  6263. + mdiobus_register_board_info(ap132_mdio1_info,
  6264. + ARRAY_SIZE(ap132_mdio1_info));
  6265. +
  6266. + /* GMAC1 is connected to the SGMII interface */
  6267. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  6268. + ath79_eth1_data.speed = SPEED_1000;
  6269. + ath79_eth1_data.duplex = DUPLEX_FULL;
  6270. + ath79_eth1_data.phy_mask = BIT(0);
  6271. + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
  6272. +
  6273. + ath79_register_eth(1);
  6274. +}
  6275. +
  6276. +MIPS_MACHINE(ATH79_MACH_AP132, "AP132",
  6277. + "Atheros AP132 reference board",
  6278. + ap132_setup);
  6279. +
  6280. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap136.c linux-4.1.43/arch/mips/ath79/mach-ap136.c
  6281. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap136.c 2017-08-06 01:56:14.000000000 +0200
  6282. +++ linux-4.1.43/arch/mips/ath79/mach-ap136.c 2017-08-06 20:02:15.000000000 +0200
  6283. @@ -18,23 +18,29 @@
  6284. *
  6285. */
  6286. -#include <linux/pci.h>
  6287. -#include <linux/ath9k_platform.h>
  6288. +#include <linux/platform_device.h>
  6289. +#include <linux/ar8216_platform.h>
  6290. -#include "machtypes.h"
  6291. +#include <asm/mach-ath79/ar71xx_regs.h>
  6292. +
  6293. +#include "common.h"
  6294. +#include "pci.h"
  6295. +#include "dev-ap9x-pci.h"
  6296. #include "dev-gpio-buttons.h"
  6297. +#include "dev-eth.h"
  6298. #include "dev-leds-gpio.h"
  6299. -#include "dev-spi.h"
  6300. +#include "dev-m25p80.h"
  6301. +#include "dev-nfc.h"
  6302. #include "dev-usb.h"
  6303. #include "dev-wmac.h"
  6304. -#include "pci.h"
  6305. +#include "machtypes.h"
  6306. -#define AP136_GPIO_LED_STATUS_RED 14
  6307. -#define AP136_GPIO_LED_STATUS_GREEN 19
  6308. #define AP136_GPIO_LED_USB 4
  6309. -#define AP136_GPIO_LED_WLAN_2G 13
  6310. #define AP136_GPIO_LED_WLAN_5G 12
  6311. +#define AP136_GPIO_LED_WLAN_2G 13
  6312. +#define AP136_GPIO_LED_STATUS_RED 14
  6313. #define AP136_GPIO_LED_WPS_RED 15
  6314. +#define AP136_GPIO_LED_STATUS_GREEN 19
  6315. #define AP136_GPIO_LED_WPS_GREEN 20
  6316. #define AP136_GPIO_BTN_WPS 16
  6317. @@ -43,37 +49,39 @@
  6318. #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
  6319. #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
  6320. -#define AP136_WMAC_CALDATA_OFFSET 0x1000
  6321. -#define AP136_PCIE_CALDATA_OFFSET 0x5000
  6322. +#define AP136_MAC0_OFFSET 0
  6323. +#define AP136_MAC1_OFFSET 6
  6324. +#define AP136_WMAC_CALDATA_OFFSET 0x1000
  6325. +#define AP136_PCIE_CALDATA_OFFSET 0x5000
  6326. static struct gpio_led ap136_leds_gpio[] __initdata = {
  6327. {
  6328. - .name = "qca:green:status",
  6329. + .name = "ap136:green:status",
  6330. .gpio = AP136_GPIO_LED_STATUS_GREEN,
  6331. .active_low = 1,
  6332. },
  6333. {
  6334. - .name = "qca:red:status",
  6335. + .name = "ap136:red:status",
  6336. .gpio = AP136_GPIO_LED_STATUS_RED,
  6337. .active_low = 1,
  6338. },
  6339. {
  6340. - .name = "qca:green:wps",
  6341. + .name = "ap136:green:wps",
  6342. .gpio = AP136_GPIO_LED_WPS_GREEN,
  6343. .active_low = 1,
  6344. },
  6345. {
  6346. - .name = "qca:red:wps",
  6347. + .name = "ap136:red:wps",
  6348. .gpio = AP136_GPIO_LED_WPS_RED,
  6349. .active_low = 1,
  6350. },
  6351. {
  6352. - .name = "qca:red:wlan-2g",
  6353. + .name = "ap136:red:wlan-2g",
  6354. .gpio = AP136_GPIO_LED_WLAN_2G,
  6355. .active_low = 1,
  6356. },
  6357. {
  6358. - .name = "qca:red:usb",
  6359. + .name = "ap136:red:usb",
  6360. .gpio = AP136_GPIO_LED_USB,
  6361. .active_low = 1,
  6362. }
  6363. @@ -98,59 +106,151 @@
  6364. },
  6365. };
  6366. -static struct spi_board_info ap136_spi_info[] = {
  6367. - {
  6368. - .bus_num = 0,
  6369. - .chip_select = 0,
  6370. - .max_speed_hz = 25000000,
  6371. - .modalias = "mx25l6405d",
  6372. - }
  6373. +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
  6374. +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
  6375. +
  6376. +static struct ar8327_platform_data ap136_ar8327_data = {
  6377. + .pad0_cfg = &ap136_ar8327_pad0_cfg,
  6378. + .pad6_cfg = &ap136_ar8327_pad6_cfg,
  6379. + .port0_cfg = {
  6380. + .force_link = 1,
  6381. + .speed = AR8327_PORT_SPEED_1000,
  6382. + .duplex = 1,
  6383. + .txpause = 1,
  6384. + .rxpause = 1,
  6385. + },
  6386. + .port6_cfg = {
  6387. + .force_link = 1,
  6388. + .speed = AR8327_PORT_SPEED_1000,
  6389. + .duplex = 1,
  6390. + .txpause = 1,
  6391. + .rxpause = 1,
  6392. + },
  6393. };
  6394. -static struct ath79_spi_platform_data ap136_spi_data = {
  6395. - .bus_num = 0,
  6396. - .num_chipselect = 1,
  6397. +static struct mdio_board_info ap136_mdio0_info[] = {
  6398. + {
  6399. + .bus_id = "ag71xx-mdio.0",
  6400. + .phy_addr = 0,
  6401. + .platform_data = &ap136_ar8327_data,
  6402. + },
  6403. };
  6404. -#ifdef CONFIG_PCI
  6405. -static struct ath9k_platform_data ap136_ath9k_data;
  6406. +static void __init ap136_common_setup(void)
  6407. +{
  6408. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  6409. +
  6410. + ath79_register_m25p80(NULL);
  6411. +
  6412. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
  6413. + ap136_leds_gpio);
  6414. + ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
  6415. + ARRAY_SIZE(ap136_gpio_keys),
  6416. + ap136_gpio_keys);
  6417. +
  6418. + ath79_register_usb();
  6419. + ath79_register_nfc();
  6420. +
  6421. + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
  6422. +
  6423. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  6424. -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
  6425. + ath79_register_mdio(0, 0x0);
  6426. + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
  6427. +
  6428. + mdiobus_register_board_info(ap136_mdio0_info,
  6429. + ARRAY_SIZE(ap136_mdio0_info));
  6430. +
  6431. + /* GMAC0 is connected to the RMGII interface */
  6432. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  6433. + ath79_eth0_data.phy_mask = BIT(0);
  6434. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  6435. +
  6436. + ath79_register_eth(0);
  6437. +
  6438. + /* GMAC1 is connected tot eh SGMII interface */
  6439. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  6440. + ath79_eth1_data.speed = SPEED_1000;
  6441. + ath79_eth1_data.duplex = DUPLEX_FULL;
  6442. +
  6443. + ath79_register_eth(1);
  6444. +}
  6445. +
  6446. +static void __init ap136_010_setup(void)
  6447. {
  6448. - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
  6449. - dev->dev.platform_data = &ap136_ath9k_data;
  6450. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  6451. - return 0;
  6452. + /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
  6453. + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
  6454. + ap136_ar8327_pad0_cfg.txclk_delay_en = true;
  6455. + ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
  6456. + ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
  6457. + ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
  6458. +
  6459. + /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
  6460. + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
  6461. + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
  6462. + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
  6463. +
  6464. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  6465. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  6466. +
  6467. + ap136_common_setup();
  6468. + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
  6469. }
  6470. -static void __init ap136_pci_init(u8 *eeprom)
  6471. +MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
  6472. + "Atheros AP136-010 reference board",
  6473. + ap136_010_setup);
  6474. +
  6475. +static void __init ap136_020_common_setup(void)
  6476. {
  6477. - memcpy(ap136_ath9k_data.eeprom_data, eeprom,
  6478. - sizeof(ap136_ath9k_data.eeprom_data));
  6479. + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
  6480. + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
  6481. + ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
  6482. +
  6483. + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
  6484. + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
  6485. + ap136_ar8327_pad6_cfg.txclk_delay_en = true;
  6486. + ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
  6487. + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
  6488. + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
  6489. - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
  6490. - ath79_register_pci();
  6491. + ath79_eth0_pll_data.pll_1000 = 0x56000000;
  6492. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  6493. +
  6494. + ap136_common_setup();
  6495. }
  6496. -#else
  6497. -static inline void ap136_pci_init(u8 *eeprom) {}
  6498. -#endif /* CONFIG_PCI */
  6499. -static void __init ap136_setup(void)
  6500. +static void __init ap136_020_setup(void)
  6501. {
  6502. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  6503. - ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
  6504. - ap136_leds_gpio);
  6505. - ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
  6506. - ARRAY_SIZE(ap136_gpio_keys),
  6507. - ap136_gpio_keys);
  6508. - ath79_register_spi(&ap136_spi_data, ap136_spi_info,
  6509. - ARRAY_SIZE(ap136_spi_info));
  6510. - ath79_register_usb();
  6511. - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
  6512. - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
  6513. + ap136_020_common_setup();
  6514. + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
  6515. }
  6516. -MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
  6517. - "Atheros AP136-010 reference board",
  6518. - ap136_setup);
  6519. +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
  6520. + "Atheros AP136-020 reference board",
  6521. + ap136_020_setup);
  6522. +
  6523. +/*
  6524. + * AP135-020 is similar to AP136-020, any future AP135 specific init
  6525. + * code can be added here.
  6526. + */
  6527. +static void __init ap135_020_setup(void)
  6528. +{
  6529. + ap136_leds_gpio[0].name = "ap135:green:status";
  6530. + ap136_leds_gpio[1].name = "ap135:red:status";
  6531. + ap136_leds_gpio[2].name = "ap135:green:wps";
  6532. + ap136_leds_gpio[3].name = "ap135:red:wps";
  6533. + ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
  6534. + ap136_leds_gpio[5].name = "ap135:red:usb";
  6535. +
  6536. + ap136_020_common_setup();
  6537. + ath79_register_pci();
  6538. +}
  6539. +
  6540. +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
  6541. + "Atheros AP135-020 reference board",
  6542. + ap135_020_setup);
  6543. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap143.c linux-4.1.43/arch/mips/ath79/mach-ap143.c
  6544. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap143.c 1970-01-01 01:00:00.000000000 +0100
  6545. +++ linux-4.1.43/arch/mips/ath79/mach-ap143.c 2017-08-06 20:02:15.000000000 +0200
  6546. @@ -0,0 +1,142 @@
  6547. +/*
  6548. + * Atheros AP143 reference board support
  6549. + *
  6550. + * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
  6551. + * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
  6552. + *
  6553. + * Permission to use, copy, modify, and/or distribute this software for any
  6554. + * purpose with or without fee is hereby granted, provided that the above
  6555. + * copyright notice and this permission notice appear in all copies.
  6556. + *
  6557. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  6558. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  6559. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  6560. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  6561. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  6562. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  6563. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  6564. + *
  6565. + */
  6566. +
  6567. +#include <linux/platform_device.h>
  6568. +#include <linux/ath9k_platform.h>
  6569. +#include <linux/ar8216_platform.h>
  6570. +
  6571. +#include <asm/mach-ath79/ar71xx_regs.h>
  6572. +
  6573. +#include "common.h"
  6574. +#include "dev-eth.h"
  6575. +#include "dev-gpio-buttons.h"
  6576. +#include "dev-leds-gpio.h"
  6577. +#include "dev-m25p80.h"
  6578. +#include "dev-spi.h"
  6579. +#include "dev-usb.h"
  6580. +#include "dev-wmac.h"
  6581. +#include "machtypes.h"
  6582. +
  6583. +#define AP143_GPIO_LED_WLAN 12
  6584. +#define AP143_GPIO_LED_WPS 13
  6585. +#define AP143_GPIO_LED_STATUS 13
  6586. +
  6587. +#define AP143_GPIO_LED_WAN 4
  6588. +#define AP143_GPIO_LED_LAN1 16
  6589. +#define AP143_GPIO_LED_LAN2 15
  6590. +#define AP143_GPIO_LED_LAN3 14
  6591. +#define AP143_GPIO_LED_LAN4 11
  6592. +
  6593. +#define AP143_GPIO_BTN_WPS 17
  6594. +
  6595. +#define AP143_KEYS_POLL_INTERVAL 20 /* msecs */
  6596. +#define AP143_KEYS_DEBOUNCE_INTERVAL (3 * AP143_KEYS_POLL_INTERVAL)
  6597. +
  6598. +#define AP143_MAC0_OFFSET 0
  6599. +#define AP143_MAC1_OFFSET 6
  6600. +#define AP143_WMAC_CALDATA_OFFSET 0x1000
  6601. +
  6602. +static struct gpio_led ap143_leds_gpio[] __initdata = {
  6603. + {
  6604. + .name = "ap143:green:status",
  6605. + .gpio = AP143_GPIO_LED_STATUS,
  6606. + .active_low = 1,
  6607. + },
  6608. + {
  6609. + .name = "ap143:green:wlan",
  6610. + .gpio = AP143_GPIO_LED_WLAN,
  6611. + .active_low = 1,
  6612. + }
  6613. +};
  6614. +
  6615. +static struct gpio_keys_button ap143_gpio_keys[] __initdata = {
  6616. + {
  6617. + .desc = "WPS button",
  6618. + .type = EV_KEY,
  6619. + .code = KEY_WPS_BUTTON,
  6620. + .debounce_interval = AP143_KEYS_DEBOUNCE_INTERVAL,
  6621. + .gpio = AP143_GPIO_BTN_WPS,
  6622. + .active_low = 1,
  6623. + },
  6624. +};
  6625. +
  6626. +static void __init ap143_gpio_led_setup(void)
  6627. +{
  6628. + ath79_gpio_direction_select(AP143_GPIO_LED_WAN, true);
  6629. + ath79_gpio_direction_select(AP143_GPIO_LED_LAN1, true);
  6630. + ath79_gpio_direction_select(AP143_GPIO_LED_LAN2, true);
  6631. + ath79_gpio_direction_select(AP143_GPIO_LED_LAN3, true);
  6632. + ath79_gpio_direction_select(AP143_GPIO_LED_LAN4, true);
  6633. +
  6634. + ath79_gpio_output_select(AP143_GPIO_LED_WAN,
  6635. + QCA953X_GPIO_OUT_MUX_LED_LINK5);
  6636. + ath79_gpio_output_select(AP143_GPIO_LED_LAN1,
  6637. + QCA953X_GPIO_OUT_MUX_LED_LINK1);
  6638. + ath79_gpio_output_select(AP143_GPIO_LED_LAN2,
  6639. + QCA953X_GPIO_OUT_MUX_LED_LINK2);
  6640. + ath79_gpio_output_select(AP143_GPIO_LED_LAN3,
  6641. + QCA953X_GPIO_OUT_MUX_LED_LINK3);
  6642. + ath79_gpio_output_select(AP143_GPIO_LED_LAN4,
  6643. + QCA953X_GPIO_OUT_MUX_LED_LINK4);
  6644. +
  6645. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap143_leds_gpio),
  6646. + ap143_leds_gpio);
  6647. + ath79_register_gpio_keys_polled(-1, AP143_KEYS_POLL_INTERVAL,
  6648. + ARRAY_SIZE(ap143_gpio_keys),
  6649. + ap143_gpio_keys);
  6650. +}
  6651. +
  6652. +static void __init ap143_setup(void)
  6653. +{
  6654. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  6655. +
  6656. + ath79_register_m25p80(NULL);
  6657. +
  6658. + ap143_gpio_led_setup();
  6659. +
  6660. + ath79_register_usb();
  6661. +
  6662. + ath79_wmac_set_led_pin(AP143_GPIO_LED_WLAN);
  6663. + ath79_register_wmac(art + AP143_WMAC_CALDATA_OFFSET, NULL);
  6664. +
  6665. + ath79_register_mdio(0, 0x0);
  6666. + ath79_register_mdio(1, 0x0);
  6667. +
  6668. + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP143_MAC0_OFFSET, 0);
  6669. + ath79_init_mac(ath79_eth1_data.mac_addr, art + AP143_MAC1_OFFSET, 0);
  6670. +
  6671. + /* WAN port */
  6672. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  6673. + ath79_eth0_data.speed = SPEED_100;
  6674. + ath79_eth0_data.duplex = DUPLEX_FULL;
  6675. + ath79_eth0_data.phy_mask = BIT(4);
  6676. + ath79_register_eth(0);
  6677. +
  6678. + /* LAN ports */
  6679. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  6680. + ath79_eth1_data.speed = SPEED_1000;
  6681. + ath79_eth1_data.duplex = DUPLEX_FULL;
  6682. + ath79_switch_data.phy_poll_mask |= BIT(4);
  6683. + ath79_switch_data.phy4_mii_en = 1;
  6684. + ath79_register_eth(1);
  6685. +}
  6686. +
  6687. +MIPS_MACHINE(ATH79_MACH_AP143, "AP143", "Qualcomm Atheros AP143 reference board",
  6688. + ap143_setup);
  6689. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap147.c linux-4.1.43/arch/mips/ath79/mach-ap147.c
  6690. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap147.c 1970-01-01 01:00:00.000000000 +0100
  6691. +++ linux-4.1.43/arch/mips/ath79/mach-ap147.c 2017-08-06 20:02:15.000000000 +0200
  6692. @@ -0,0 +1,125 @@
  6693. +/*
  6694. + * Atheros AP147 reference board support
  6695. + *
  6696. + * Copyright (C) 2014 Matthias Schiffer <mschiffer@universe-factory.net>
  6697. + * Copyright (C) 2015 Sven Eckelmann <sven@open-mesh.com>
  6698. + *
  6699. + * This program is free software; you can redistribute it and/or modify it
  6700. + * under the terms of the GNU General Public License version 2 as published
  6701. + * by the Free Software Foundation.
  6702. + */
  6703. +
  6704. +#include <linux/platform_device.h>
  6705. +#include <linux/ar8216_platform.h>
  6706. +
  6707. +#include <asm/mach-ath79/ar71xx_regs.h>
  6708. +#include <asm/mach-ath79/ath79.h>
  6709. +
  6710. +#include "common.h"
  6711. +#include "dev-ap9x-pci.h"
  6712. +#include "dev-eth.h"
  6713. +#include "dev-gpio-buttons.h"
  6714. +#include "dev-leds-gpio.h"
  6715. +#include "dev-m25p80.h"
  6716. +#include "dev-usb.h"
  6717. +#include "dev-wmac.h"
  6718. +#include "machtypes.h"
  6719. +#include "pci.h"
  6720. +
  6721. +#define AP147_GPIO_LED_WAN 4
  6722. +#define AP147_GPIO_LED_LAN1 16
  6723. +#define AP147_GPIO_LED_LAN2 15
  6724. +#define AP147_GPIO_LED_LAN3 14
  6725. +#define AP147_GPIO_LED_LAN4 11
  6726. +#define AP147_GPIO_LED_STATUS 13
  6727. +#define AP147_GPIO_LED_WLAN_2G 12
  6728. +
  6729. +#define AP147_GPIO_BTN_WPS 17
  6730. +
  6731. +#define AP147_KEYS_POLL_INTERVAL 20 /* msecs */
  6732. +#define AP147_KEYS_DEBOUNCE_INTERVAL (3 * AP147_KEYS_POLL_INTERVAL)
  6733. +
  6734. +#define AP147_MAC0_OFFSET 0x1000
  6735. +
  6736. +static struct gpio_led ap147_leds_gpio[] __initdata = {
  6737. + {
  6738. + .name = "ap147:green:status",
  6739. + .gpio = AP147_GPIO_LED_STATUS,
  6740. + .active_low = 1,
  6741. + }, {
  6742. + .name = "ap147:green:wlan-2g",
  6743. + .gpio = AP147_GPIO_LED_WLAN_2G,
  6744. + .active_low = 1,
  6745. + }, {
  6746. + .name = "ap147:green:lan1",
  6747. + .gpio = AP147_GPIO_LED_LAN1,
  6748. + .active_low = 1,
  6749. + }, {
  6750. + .name = "ap147:green:lan2",
  6751. + .gpio = AP147_GPIO_LED_LAN2,
  6752. + .active_low = 1,
  6753. + }, {
  6754. + .name = "ap147:green:lan3",
  6755. + .gpio = AP147_GPIO_LED_LAN3,
  6756. + .active_low = 1,
  6757. + }, {
  6758. + .name = "ap147:green:lan4",
  6759. + .gpio = AP147_GPIO_LED_LAN4,
  6760. + .active_low = 1,
  6761. + }, {
  6762. + .name = "ap147:green:wan",
  6763. + .gpio = AP147_GPIO_LED_WAN,
  6764. + .active_low = 1,
  6765. + },
  6766. +};
  6767. +
  6768. +static struct gpio_keys_button ap147_gpio_keys[] __initdata = {
  6769. + {
  6770. + .desc = "wps button",
  6771. + .type = EV_KEY,
  6772. + .code = KEY_WPS_BUTTON,
  6773. + .debounce_interval = AP147_KEYS_DEBOUNCE_INTERVAL,
  6774. + .gpio = AP147_GPIO_BTN_WPS,
  6775. + .active_low = 1,
  6776. + }
  6777. +};
  6778. +
  6779. +static void __init ap147_setup(void)
  6780. +{
  6781. + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
  6782. +
  6783. + ath79_register_m25p80(NULL);
  6784. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap147_leds_gpio),
  6785. + ap147_leds_gpio);
  6786. + ath79_register_gpio_keys_polled(-1, AP147_KEYS_POLL_INTERVAL,
  6787. + ARRAY_SIZE(ap147_gpio_keys),
  6788. + ap147_gpio_keys);
  6789. +
  6790. + ath79_register_usb();
  6791. +
  6792. + ath79_register_pci();
  6793. +
  6794. + ath79_register_wmac(art + AP147_MAC0_OFFSET, NULL);
  6795. +
  6796. + ath79_setup_ar933x_phy4_switch(false, false);
  6797. +
  6798. + ath79_register_mdio(0, 0x0);
  6799. +
  6800. + /* LAN */
  6801. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  6802. + ath79_eth1_data.duplex = DUPLEX_FULL;
  6803. + ath79_switch_data.phy_poll_mask |= BIT(4);
  6804. + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0);
  6805. + ath79_register_eth(1);
  6806. +
  6807. + /* WAN */
  6808. + ath79_switch_data.phy4_mii_en = 1;
  6809. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  6810. + ath79_eth0_data.duplex = DUPLEX_FULL;
  6811. + ath79_eth0_data.speed = SPEED_100;
  6812. + ath79_eth0_data.phy_mask = BIT(4);
  6813. + ath79_init_mac(ath79_eth0_data.mac_addr, art, 1);
  6814. + ath79_register_eth(0);
  6815. +}
  6816. +
  6817. +MIPS_MACHINE(ATH79_MACH_AP147_010, "AP147-010", "Atheros AP147-010 reference board", ap147_setup);
  6818. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap152.c linux-4.1.43/arch/mips/ath79/mach-ap152.c
  6819. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap152.c 1970-01-01 01:00:00.000000000 +0100
  6820. +++ linux-4.1.43/arch/mips/ath79/mach-ap152.c 2017-08-06 20:02:15.000000000 +0200
  6821. @@ -0,0 +1,141 @@
  6822. +
  6823. +/*
  6824. + * Qualcomm Atheros AP152 reference board support
  6825. + *
  6826. + * Copyright (c) 2015 Qualcomm Atheros
  6827. + * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
  6828. + *
  6829. + * Permission to use, copy, modify, and/or distribute this software for any
  6830. + * purpose with or without fee is hereby granted, provided that the above
  6831. + * copyright notice and this permission notice appear in all copies.
  6832. + *
  6833. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  6834. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  6835. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  6836. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  6837. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  6838. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  6839. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  6840. + *
  6841. + */
  6842. +
  6843. +#include <linux/platform_device.h>
  6844. +#include <linux/ath9k_platform.h>
  6845. +#include <linux/ar8216_platform.h>
  6846. +#include <asm/mach-ath79/ar71xx_regs.h>
  6847. +
  6848. +#include "common.h"
  6849. +#include "dev-m25p80.h"
  6850. +#include "machtypes.h"
  6851. +#include "pci.h"
  6852. +#include "dev-eth.h"
  6853. +#include "dev-gpio-buttons.h"
  6854. +#include "dev-leds-gpio.h"
  6855. +#include "dev-spi.h"
  6856. +#include "dev-usb.h"
  6857. +#include "dev-wmac.h"
  6858. +
  6859. +#define AP152_GPIO_LED_USB0 7
  6860. +#define AP152_GPIO_LED_USB1 8
  6861. +
  6862. +#define AP152_GPIO_BTN_RESET 2
  6863. +#define AP152_GPIO_BTN_WPS 1
  6864. +#define AP152_KEYS_POLL_INTERVAL 20 /* msecs */
  6865. +#define AP152_KEYS_DEBOUNCE_INTERVAL (3 * AP152_KEYS_POLL_INTERVAL)
  6866. +
  6867. +#define AP152_MAC0_OFFSET 0
  6868. +#define AP152_WMAC_CALDATA_OFFSET 0x1000
  6869. +
  6870. +static struct gpio_led ap152_leds_gpio[] __initdata = {
  6871. + {
  6872. + .name = "ap152:green:usb0",
  6873. + .gpio = AP152_GPIO_LED_USB0,
  6874. + .active_low = 1,
  6875. + },
  6876. + {
  6877. + .name = "ap152:green:usb1",
  6878. + .gpio = AP152_GPIO_LED_USB1,
  6879. + .active_low = 1,
  6880. + },
  6881. +};
  6882. +
  6883. +static struct gpio_keys_button ap152_gpio_keys[] __initdata = {
  6884. + {
  6885. + .desc = "WPS button",
  6886. + .type = EV_KEY,
  6887. + .code = KEY_WPS_BUTTON,
  6888. + .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
  6889. + .gpio = AP152_GPIO_BTN_WPS,
  6890. + .active_low = 1,
  6891. + },
  6892. + {
  6893. + .desc = "Reset button",
  6894. + .type = EV_KEY,
  6895. + .code = KEY_RESTART,
  6896. + .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
  6897. + .gpio = AP152_GPIO_BTN_RESET,
  6898. + .active_low = 1,
  6899. + },
  6900. +};
  6901. +
  6902. +static struct ar8327_pad_cfg ap152_ar8337_pad0_cfg = {
  6903. + .mode = AR8327_PAD_MAC_SGMII,
  6904. + .sgmii_delay_en = true,
  6905. +};
  6906. +
  6907. +static struct ar8327_platform_data ap152_ar8337_data = {
  6908. + .pad0_cfg = &ap152_ar8337_pad0_cfg,
  6909. + .port0_cfg = {
  6910. + .force_link = 1,
  6911. + .speed = AR8327_PORT_SPEED_1000,
  6912. + .duplex = 1,
  6913. + .txpause = 1,
  6914. + .rxpause = 1,
  6915. + },
  6916. +};
  6917. +
  6918. +static struct mdio_board_info ap152_mdio0_info[] = {
  6919. + {
  6920. + .bus_id = "ag71xx-mdio.0",
  6921. + .phy_addr = 0,
  6922. + .platform_data = &ap152_ar8337_data,
  6923. + },
  6924. +};
  6925. +
  6926. +static void __init ap152_setup(void)
  6927. +{
  6928. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  6929. +
  6930. + ath79_register_m25p80(NULL);
  6931. +
  6932. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap152_leds_gpio),
  6933. + ap152_leds_gpio);
  6934. + ath79_register_gpio_keys_polled(-1, AP152_KEYS_POLL_INTERVAL,
  6935. + ARRAY_SIZE(ap152_gpio_keys),
  6936. + ap152_gpio_keys);
  6937. +
  6938. + ath79_register_usb();
  6939. +
  6940. + platform_device_register(&ath79_mdio0_device);
  6941. +
  6942. + mdiobus_register_board_info(ap152_mdio0_info,
  6943. + ARRAY_SIZE(ap152_mdio0_info));
  6944. +
  6945. + ath79_register_wmac(art + AP152_WMAC_CALDATA_OFFSET, NULL);
  6946. + ath79_register_pci();
  6947. +
  6948. + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP152_MAC0_OFFSET, 0);
  6949. +
  6950. + /* GMAC0 is connected to an AR8337 switch */
  6951. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  6952. + ath79_eth0_data.speed = SPEED_1000;
  6953. + ath79_eth0_data.duplex = DUPLEX_FULL;
  6954. + ath79_eth0_data.phy_mask = BIT(0);
  6955. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  6956. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  6957. +
  6958. + ath79_register_eth(0);
  6959. +}
  6960. +
  6961. +MIPS_MACHINE(ATH79_MACH_AP152, "AP152", "Qualcomm Atheros AP152 reference board",
  6962. + ap152_setup);
  6963. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap81.c linux-4.1.43/arch/mips/ath79/mach-ap81.c
  6964. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap81.c 2017-08-06 01:56:14.000000000 +0200
  6965. +++ linux-4.1.43/arch/mips/ath79/mach-ap81.c 2017-08-06 20:02:15.000000000 +0200
  6966. @@ -9,12 +9,16 @@
  6967. * by the Free Software Foundation.
  6968. */
  6969. -#include "machtypes.h"
  6970. -#include "dev-wmac.h"
  6971. +#include <linux/mtd/mtd.h>
  6972. +#include <linux/mtd/partitions.h>
  6973. +
  6974. +#include "dev-eth.h"
  6975. #include "dev-gpio-buttons.h"
  6976. #include "dev-leds-gpio.h"
  6977. -#include "dev-spi.h"
  6978. +#include "dev-m25p80.h"
  6979. #include "dev-usb.h"
  6980. +#include "dev-wmac.h"
  6981. +#include "machtypes.h"
  6982. #define AP81_GPIO_LED_STATUS 1
  6983. #define AP81_GPIO_LED_AOSS 3
  6984. @@ -67,20 +71,6 @@
  6985. }
  6986. };
  6987. -static struct spi_board_info ap81_spi_info[] = {
  6988. - {
  6989. - .bus_num = 0,
  6990. - .chip_select = 0,
  6991. - .max_speed_hz = 25000000,
  6992. - .modalias = "m25p64",
  6993. - }
  6994. -};
  6995. -
  6996. -static struct ath79_spi_platform_data ap81_spi_data = {
  6997. - .bus_num = 0,
  6998. - .num_chipselect = 1,
  6999. -};
  7000. -
  7001. static void __init ap81_setup(void)
  7002. {
  7003. u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
  7004. @@ -90,10 +80,24 @@
  7005. ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
  7006. ARRAY_SIZE(ap81_gpio_keys),
  7007. ap81_gpio_keys);
  7008. - ath79_register_spi(&ap81_spi_data, ap81_spi_info,
  7009. - ARRAY_SIZE(ap81_spi_info));
  7010. - ath79_register_wmac(cal_data);
  7011. + ath79_register_m25p80(NULL);
  7012. + ath79_register_wmac(cal_data, NULL);
  7013. ath79_register_usb();
  7014. +
  7015. + ath79_register_mdio(0, 0x0);
  7016. +
  7017. + ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0);
  7018. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  7019. + ath79_eth0_data.speed = SPEED_100;
  7020. + ath79_eth0_data.duplex = DUPLEX_FULL;
  7021. + ath79_eth0_data.has_ar8216 = 1;
  7022. +
  7023. + ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1);
  7024. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  7025. + ath79_eth1_data.phy_mask = 0x10;
  7026. +
  7027. + ath79_register_eth(0);
  7028. + ath79_register_eth(1);
  7029. }
  7030. MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
  7031. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap83.c linux-4.1.43/arch/mips/ath79/mach-ap83.c
  7032. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap83.c 1970-01-01 01:00:00.000000000 +0100
  7033. +++ linux-4.1.43/arch/mips/ath79/mach-ap83.c 2017-08-06 20:02:15.000000000 +0200
  7034. @@ -0,0 +1,242 @@
  7035. +/*
  7036. + * Atheros AP83 board support
  7037. + *
  7038. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  7039. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  7040. + *
  7041. + * This program is free software; you can redistribute it and/or modify it
  7042. + * under the terms of the GNU General Public License version 2 as published
  7043. + * by the Free Software Foundation.
  7044. + */
  7045. +
  7046. +#include <linux/delay.h>
  7047. +#include <linux/platform_device.h>
  7048. +#include <linux/mtd/mtd.h>
  7049. +#include <linux/mtd/partitions.h>
  7050. +#include <linux/mtd/physmap.h>
  7051. +#include <linux/spi/spi.h>
  7052. +#include <linux/spi/spi_gpio.h>
  7053. +#include <linux/spi/vsc7385.h>
  7054. +
  7055. +#include <asm/mach-ath79/ar71xx_regs.h>
  7056. +#include <asm/mach-ath79/ath79.h>
  7057. +
  7058. +#include "dev-eth.h"
  7059. +#include "dev-gpio-buttons.h"
  7060. +#include "dev-leds-gpio.h"
  7061. +#include "dev-usb.h"
  7062. +#include "dev-wmac.h"
  7063. +#include "machtypes.h"
  7064. +
  7065. +#define AP83_GPIO_LED_WLAN 6
  7066. +#define AP83_GPIO_LED_POWER 14
  7067. +#define AP83_GPIO_LED_JUMPSTART 15
  7068. +#define AP83_GPIO_BTN_JUMPSTART 12
  7069. +#define AP83_GPIO_BTN_RESET 21
  7070. +
  7071. +#define AP83_050_GPIO_VSC7385_CS 1
  7072. +#define AP83_050_GPIO_VSC7385_MISO 3
  7073. +#define AP83_050_GPIO_VSC7385_MOSI 16
  7074. +#define AP83_050_GPIO_VSC7385_SCK 17
  7075. +
  7076. +#define AP83_KEYS_POLL_INTERVAL 20 /* msecs */
  7077. +#define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL)
  7078. +
  7079. +static struct physmap_flash_data ap83_flash_data = {
  7080. + .width = 2,
  7081. +};
  7082. +
  7083. +static struct resource ap83_flash_resources[] = {
  7084. + [0] = {
  7085. + .start = AR71XX_SPI_BASE,
  7086. + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
  7087. + .flags = IORESOURCE_MEM,
  7088. + },
  7089. +};
  7090. +
  7091. +static struct platform_device ap83_flash_device = {
  7092. + .name = "ar91xx-flash",
  7093. + .id = -1,
  7094. + .resource = ap83_flash_resources,
  7095. + .num_resources = ARRAY_SIZE(ap83_flash_resources),
  7096. + .dev = {
  7097. + .platform_data = &ap83_flash_data,
  7098. + }
  7099. +};
  7100. +
  7101. +static struct gpio_led ap83_leds_gpio[] __initdata = {
  7102. + {
  7103. + .name = "ap83:green:jumpstart",
  7104. + .gpio = AP83_GPIO_LED_JUMPSTART,
  7105. + .active_low = 0,
  7106. + }, {
  7107. + .name = "ap83:green:power",
  7108. + .gpio = AP83_GPIO_LED_POWER,
  7109. + .active_low = 0,
  7110. + }, {
  7111. + .name = "ap83:green:wlan",
  7112. + .gpio = AP83_GPIO_LED_WLAN,
  7113. + .active_low = 0,
  7114. + },
  7115. +};
  7116. +
  7117. +static struct gpio_keys_button ap83_gpio_keys[] __initdata = {
  7118. + {
  7119. + .desc = "soft_reset",
  7120. + .type = EV_KEY,
  7121. + .code = KEY_RESTART,
  7122. + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL,
  7123. + .gpio = AP83_GPIO_BTN_RESET,
  7124. + .active_low = 1,
  7125. + }, {
  7126. + .desc = "jumpstart",
  7127. + .type = EV_KEY,
  7128. + .code = KEY_WPS_BUTTON,
  7129. + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL,
  7130. + .gpio = AP83_GPIO_BTN_JUMPSTART,
  7131. + .active_low = 1,
  7132. + }
  7133. +};
  7134. +
  7135. +static struct resource ap83_040_spi_resources[] = {
  7136. + [0] = {
  7137. + .start = AR71XX_SPI_BASE,
  7138. + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
  7139. + .flags = IORESOURCE_MEM,
  7140. + },
  7141. +};
  7142. +
  7143. +static struct platform_device ap83_040_spi_device = {
  7144. + .name = "ap83-spi",
  7145. + .id = 0,
  7146. + .resource = ap83_040_spi_resources,
  7147. + .num_resources = ARRAY_SIZE(ap83_040_spi_resources),
  7148. +};
  7149. +
  7150. +static struct spi_gpio_platform_data ap83_050_spi_data = {
  7151. + .miso = AP83_050_GPIO_VSC7385_MISO,
  7152. + .mosi = AP83_050_GPIO_VSC7385_MOSI,
  7153. + .sck = AP83_050_GPIO_VSC7385_SCK,
  7154. + .num_chipselect = 1,
  7155. +};
  7156. +
  7157. +static struct platform_device ap83_050_spi_device = {
  7158. + .name = "spi_gpio",
  7159. + .id = 0,
  7160. + .dev = {
  7161. + .platform_data = &ap83_050_spi_data,
  7162. + }
  7163. +};
  7164. +
  7165. +static void ap83_vsc7385_reset(void)
  7166. +{
  7167. + ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
  7168. + udelay(10);
  7169. + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
  7170. + mdelay(50);
  7171. +}
  7172. +
  7173. +static struct vsc7385_platform_data ap83_vsc7385_data = {
  7174. + .reset = ap83_vsc7385_reset,
  7175. + .ucode_name = "vsc7385_ucode_ap83.bin",
  7176. + .mac_cfg = {
  7177. + .tx_ipg = 6,
  7178. + .bit2 = 0,
  7179. + .clk_sel = 3,
  7180. + },
  7181. +};
  7182. +
  7183. +static struct spi_board_info ap83_spi_info[] = {
  7184. + {
  7185. + .bus_num = 0,
  7186. + .chip_select = 0,
  7187. + .max_speed_hz = 25000000,
  7188. + .modalias = "spi-vsc7385",
  7189. + .platform_data = &ap83_vsc7385_data,
  7190. + .controller_data = (void *) AP83_050_GPIO_VSC7385_CS,
  7191. + }
  7192. +};
  7193. +
  7194. +static void __init ap83_generic_setup(void)
  7195. +{
  7196. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  7197. +
  7198. + ath79_register_mdio(0, 0xfffffffe);
  7199. +
  7200. + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
  7201. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  7202. + ath79_eth0_data.phy_mask = 0x1;
  7203. +
  7204. + ath79_register_eth(0);
  7205. +
  7206. + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
  7207. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  7208. + ath79_eth1_data.speed = SPEED_1000;
  7209. + ath79_eth1_data.duplex = DUPLEX_FULL;
  7210. +
  7211. + ath79_eth1_pll_data.pll_1000 = 0x1f000000;
  7212. +
  7213. + ath79_register_eth(1);
  7214. +
  7215. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio),
  7216. + ap83_leds_gpio);
  7217. +
  7218. + ath79_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL,
  7219. + ARRAY_SIZE(ap83_gpio_keys),
  7220. + ap83_gpio_keys);
  7221. +
  7222. + ath79_register_usb();
  7223. +
  7224. + ath79_register_wmac(eeprom, NULL);
  7225. +
  7226. + platform_device_register(&ap83_flash_device);
  7227. +
  7228. + spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info));
  7229. +}
  7230. +
  7231. +static void ap83_040_flash_lock(struct platform_device *pdev)
  7232. +{
  7233. + ath79_flash_acquire();
  7234. +}
  7235. +
  7236. +static void ap83_040_flash_unlock(struct platform_device *pdev)
  7237. +{
  7238. + ath79_flash_release();
  7239. +}
  7240. +
  7241. +static void __init ap83_040_setup(void)
  7242. +{
  7243. + ap83_flash_data.lock = ap83_040_flash_lock;
  7244. + ap83_flash_data.unlock = ap83_040_flash_unlock;
  7245. + ap83_generic_setup();
  7246. + platform_device_register(&ap83_040_spi_device);
  7247. +}
  7248. +
  7249. +static void __init ap83_050_setup(void)
  7250. +{
  7251. + ap83_generic_setup();
  7252. + platform_device_register(&ap83_050_spi_device);
  7253. +}
  7254. +
  7255. +static void __init ap83_setup(void)
  7256. +{
  7257. + u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244);
  7258. + unsigned int board_version;
  7259. +
  7260. + board_version = (unsigned int)(board_id[0] - '0');
  7261. + board_version += ((unsigned int)(board_id[1] - '0')) * 10;
  7262. +
  7263. + switch (board_version) {
  7264. + case 40:
  7265. + ap83_040_setup();
  7266. + break;
  7267. + case 50:
  7268. + ap83_050_setup();
  7269. + break;
  7270. + default:
  7271. + printk(KERN_WARNING "AP83-%03u board is not yet supported\n",
  7272. + board_version);
  7273. + }
  7274. +}
  7275. +
  7276. +MIPS_MACHINE(ATH79_MACH_AP83, "AP83", "Atheros AP83", ap83_setup);
  7277. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ap96.c linux-4.1.43/arch/mips/ath79/mach-ap96.c
  7278. --- linux-4.1.43.orig/arch/mips/ath79/mach-ap96.c 1970-01-01 01:00:00.000000000 +0100
  7279. +++ linux-4.1.43/arch/mips/ath79/mach-ap96.c 2017-08-06 20:02:15.000000000 +0200
  7280. @@ -0,0 +1,142 @@
  7281. +/*
  7282. + * Atheros AP96 board support
  7283. + *
  7284. + * Copyright (C) 2009 Marco Porsch
  7285. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  7286. + * Copyright (C) 2010 Atheros Communications
  7287. + *
  7288. + * This program is free software; you can redistribute it and/or modify it
  7289. + * under the terms of the GNU General Public License version 2 as published
  7290. + * by the Free Software Foundation.
  7291. + */
  7292. +
  7293. +#include <linux/platform_device.h>
  7294. +#include <linux/delay.h>
  7295. +
  7296. +#include <asm/mach-ath79/ath79.h>
  7297. +
  7298. +#include "dev-ap9x-pci.h"
  7299. +#include "dev-eth.h"
  7300. +#include "dev-gpio-buttons.h"
  7301. +#include "dev-leds-gpio.h"
  7302. +#include "dev-m25p80.h"
  7303. +#include "dev-usb.h"
  7304. +#include "machtypes.h"
  7305. +
  7306. +#define AP96_GPIO_LED_12_GREEN 0
  7307. +#define AP96_GPIO_LED_3_GREEN 1
  7308. +#define AP96_GPIO_LED_2_GREEN 2
  7309. +#define AP96_GPIO_LED_WPS_GREEN 4
  7310. +#define AP96_GPIO_LED_5_GREEN 5
  7311. +#define AP96_GPIO_LED_4_ORANGE 6
  7312. +
  7313. +/* Reset button - next to the power connector */
  7314. +#define AP96_GPIO_BTN_RESET 3
  7315. +/* WPS button - next to a led on right */
  7316. +#define AP96_GPIO_BTN_WPS 8
  7317. +
  7318. +#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */
  7319. +#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL)
  7320. +
  7321. +#define AP96_WMAC0_MAC_OFFSET 0x120c
  7322. +#define AP96_WMAC1_MAC_OFFSET 0x520c
  7323. +#define AP96_CALDATA0_OFFSET 0x1000
  7324. +#define AP96_CALDATA1_OFFSET 0x5000
  7325. +
  7326. +/*
  7327. + * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12
  7328. + * below (from left to right on the board). Led 1 seems to be on whenever the
  7329. + * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange;
  7330. + * others are green.
  7331. + *
  7332. + * In addition, there is one led next to a button on the right side for WPS.
  7333. + */
  7334. +static struct gpio_led ap96_leds_gpio[] __initdata = {
  7335. + {
  7336. + .name = "ap96:green:led2",
  7337. + .gpio = AP96_GPIO_LED_2_GREEN,
  7338. + .active_low = 1,
  7339. + }, {
  7340. + .name = "ap96:green:led3",
  7341. + .gpio = AP96_GPIO_LED_3_GREEN,
  7342. + .active_low = 1,
  7343. + }, {
  7344. + .name = "ap96:orange:led4",
  7345. + .gpio = AP96_GPIO_LED_4_ORANGE,
  7346. + .active_low = 1,
  7347. + }, {
  7348. + .name = "ap96:green:led5",
  7349. + .gpio = AP96_GPIO_LED_5_GREEN,
  7350. + .active_low = 1,
  7351. + }, {
  7352. + .name = "ap96:green:led12",
  7353. + .gpio = AP96_GPIO_LED_12_GREEN,
  7354. + .active_low = 1,
  7355. + }, { /* next to a button on right */
  7356. + .name = "ap96:green:wps",
  7357. + .gpio = AP96_GPIO_LED_WPS_GREEN,
  7358. + .active_low = 1,
  7359. + }
  7360. +};
  7361. +
  7362. +static struct gpio_keys_button ap96_gpio_keys[] __initdata = {
  7363. + {
  7364. + .desc = "reset",
  7365. + .type = EV_KEY,
  7366. + .code = KEY_RESTART,
  7367. + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
  7368. + .gpio = AP96_GPIO_BTN_RESET,
  7369. + .active_low = 1,
  7370. + }, {
  7371. + .desc = "wps",
  7372. + .type = EV_KEY,
  7373. + .code = KEY_WPS_BUTTON,
  7374. + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
  7375. + .gpio = AP96_GPIO_BTN_WPS,
  7376. + .active_low = 1,
  7377. + }
  7378. +};
  7379. +
  7380. +#define AP96_WAN_PHYMASK 0x10
  7381. +#define AP96_LAN_PHYMASK 0x0f
  7382. +
  7383. +static void __init ap96_setup(void)
  7384. +{
  7385. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  7386. +
  7387. + ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK));
  7388. +
  7389. + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
  7390. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  7391. + ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK;
  7392. + ath79_eth0_data.speed = SPEED_1000;
  7393. + ath79_eth0_data.duplex = DUPLEX_FULL;
  7394. +
  7395. + ath79_register_eth(0);
  7396. +
  7397. + ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
  7398. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  7399. + ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK;
  7400. +
  7401. + ath79_eth1_pll_data.pll_1000 = 0x1f000000;
  7402. +
  7403. + ath79_register_eth(1);
  7404. +
  7405. + ath79_register_usb();
  7406. +
  7407. + ath79_register_m25p80(NULL);
  7408. +
  7409. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio),
  7410. + ap96_leds_gpio);
  7411. +
  7412. + ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL,
  7413. + ARRAY_SIZE(ap96_gpio_keys),
  7414. + ap96_gpio_keys);
  7415. +
  7416. + ap94_pci_init(art + AP96_CALDATA0_OFFSET,
  7417. + art + AP96_WMAC0_MAC_OFFSET,
  7418. + art + AP96_CALDATA1_OFFSET,
  7419. + art + AP96_WMAC1_MAC_OFFSET);
  7420. +}
  7421. +
  7422. +MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup);
  7423. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-archer-c7.c linux-4.1.43/arch/mips/ath79/mach-archer-c7.c
  7424. --- linux-4.1.43.orig/arch/mips/ath79/mach-archer-c7.c 1970-01-01 01:00:00.000000000 +0100
  7425. +++ linux-4.1.43/arch/mips/ath79/mach-archer-c7.c 2017-08-06 20:02:15.000000000 +0200
  7426. @@ -0,0 +1,266 @@
  7427. +/*
  7428. + * TP-LINK Archer C5/C7/TL-WDR4900 v2 board support
  7429. + *
  7430. + * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
  7431. + * Copyright (c) 2014 施康成 <tenninjas@tenninjas.ca>
  7432. + * Copyright (c) 2014 Imre Kaloz <kaloz@openwrt.org>
  7433. + *
  7434. + * Based on the Qualcomm Atheros AP135/AP136 reference board support code
  7435. + * Copyright (c) 2012 Qualcomm Atheros
  7436. + *
  7437. + * Permission to use, copy, modify, and/or distribute this software for any
  7438. + * purpose with or without fee is hereby granted, provided that the above
  7439. + * copyright notice and this permission notice appear in all copies.
  7440. + *
  7441. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  7442. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  7443. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  7444. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  7445. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  7446. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  7447. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  7448. + *
  7449. + */
  7450. +
  7451. +#include <linux/pci.h>
  7452. +#include <linux/phy.h>
  7453. +#include <linux/gpio.h>
  7454. +#include <linux/platform_device.h>
  7455. +#include <linux/ath9k_platform.h>
  7456. +#include <linux/ar8216_platform.h>
  7457. +
  7458. +#include <asm/mach-ath79/ar71xx_regs.h>
  7459. +
  7460. +#include "common.h"
  7461. +#include "dev-ap9x-pci.h"
  7462. +#include "dev-eth.h"
  7463. +#include "dev-gpio-buttons.h"
  7464. +#include "dev-leds-gpio.h"
  7465. +#include "dev-m25p80.h"
  7466. +#include "dev-spi.h"
  7467. +#include "dev-usb.h"
  7468. +#include "dev-wmac.h"
  7469. +#include "machtypes.h"
  7470. +#include "pci.h"
  7471. +
  7472. +#define ARCHER_C7_GPIO_LED_WLAN2G 12
  7473. +#define ARCHER_C7_GPIO_LED_SYSTEM 14
  7474. +#define ARCHER_C7_GPIO_LED_QSS 15
  7475. +#define ARCHER_C7_GPIO_LED_WLAN5G 17
  7476. +#define ARCHER_C7_GPIO_LED_USB1 18
  7477. +#define ARCHER_C7_GPIO_LED_USB2 19
  7478. +
  7479. +#define ARCHER_C7_GPIO_BTN_RFKILL 13
  7480. +#define ARCHER_C7_GPIO_BTN_RESET 16
  7481. +
  7482. +#define ARCHER_C7_GPIO_USB1_POWER 22
  7483. +#define ARCHER_C7_GPIO_USB2_POWER 21
  7484. +
  7485. +#define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */
  7486. +#define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL)
  7487. +
  7488. +#define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000
  7489. +#define ARCHER_C7_PCIE_CALDATA_OFFSET 0x5000
  7490. +
  7491. +static const char *archer_c7_part_probes[] = {
  7492. + "tp-link",
  7493. + NULL,
  7494. +};
  7495. +
  7496. +static struct flash_platform_data archer_c7_flash_data = {
  7497. + .part_probes = archer_c7_part_probes,
  7498. +};
  7499. +
  7500. +static struct gpio_led archer_c7_leds_gpio[] __initdata = {
  7501. + {
  7502. + .name = "tp-link:blue:qss",
  7503. + .gpio = ARCHER_C7_GPIO_LED_QSS,
  7504. + .active_low = 1,
  7505. + },
  7506. + {
  7507. + .name = "tp-link:blue:system",
  7508. + .gpio = ARCHER_C7_GPIO_LED_SYSTEM,
  7509. + .active_low = 1,
  7510. + },
  7511. + {
  7512. + .name = "tp-link:blue:wlan2g",
  7513. + .gpio = ARCHER_C7_GPIO_LED_WLAN2G,
  7514. + .active_low = 1,
  7515. + },
  7516. + {
  7517. + .name = "tp-link:blue:wlan5g",
  7518. + .gpio = ARCHER_C7_GPIO_LED_WLAN5G,
  7519. + .active_low = 1,
  7520. + },
  7521. + {
  7522. + .name = "tp-link:green:usb1",
  7523. + .gpio = ARCHER_C7_GPIO_LED_USB1,
  7524. + .active_low = 1,
  7525. + },
  7526. + {
  7527. + .name = "tp-link:green:usb2",
  7528. + .gpio = ARCHER_C7_GPIO_LED_USB2,
  7529. + .active_low = 1,
  7530. + },
  7531. +};
  7532. +
  7533. +static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = {
  7534. + {
  7535. + .desc = "Reset button",
  7536. + .type = EV_KEY,
  7537. + .code = KEY_WPS_BUTTON,
  7538. + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
  7539. + .gpio = ARCHER_C7_GPIO_BTN_RESET,
  7540. + .active_low = 1,
  7541. + },
  7542. + {
  7543. + .desc = "RFKILL switch",
  7544. + .type = EV_SW,
  7545. + .code = KEY_RFKILL,
  7546. + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
  7547. + .gpio = ARCHER_C7_GPIO_BTN_RFKILL,
  7548. + },
  7549. +};
  7550. +
  7551. +static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = {
  7552. + AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"),
  7553. + AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"),
  7554. + AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"),
  7555. + AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"),
  7556. + AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"),
  7557. +};
  7558. +
  7559. +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
  7560. +static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = {
  7561. + .mode = AR8327_PAD_MAC_SGMII,
  7562. + .sgmii_delay_en = true,
  7563. +};
  7564. +
  7565. +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
  7566. +static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = {
  7567. + .mode = AR8327_PAD_MAC_RGMII,
  7568. + .txclk_delay_en = true,
  7569. + .rxclk_delay_en = true,
  7570. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  7571. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  7572. +};
  7573. +
  7574. +static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = {
  7575. + .led_ctrl0 = 0xc737c737,
  7576. + .led_ctrl1 = 0x00000000,
  7577. + .led_ctrl2 = 0x00000000,
  7578. + .led_ctrl3 = 0x0030c300,
  7579. + .open_drain = false,
  7580. +};
  7581. +
  7582. +static struct ar8327_platform_data archer_c7_ar8327_data = {
  7583. + .pad0_cfg = &archer_c7_ar8327_pad0_cfg,
  7584. + .pad6_cfg = &archer_c7_ar8327_pad6_cfg,
  7585. + .port0_cfg = {
  7586. + .force_link = 1,
  7587. + .speed = AR8327_PORT_SPEED_1000,
  7588. + .duplex = 1,
  7589. + .txpause = 1,
  7590. + .rxpause = 1,
  7591. + },
  7592. + .port6_cfg = {
  7593. + .force_link = 1,
  7594. + .speed = AR8327_PORT_SPEED_1000,
  7595. + .duplex = 1,
  7596. + .txpause = 1,
  7597. + .rxpause = 1,
  7598. + },
  7599. + .led_cfg = &archer_c7_ar8327_led_cfg,
  7600. + .num_leds = ARRAY_SIZE(archer_c7_leds_ar8327),
  7601. + .leds = archer_c7_leds_ar8327,
  7602. +};
  7603. +
  7604. +static struct mdio_board_info archer_c7_mdio0_info[] = {
  7605. + {
  7606. + .bus_id = "ag71xx-mdio.0",
  7607. + .phy_addr = 0,
  7608. + .platform_data = &archer_c7_ar8327_data,
  7609. + },
  7610. +};
  7611. +
  7612. +static void __init common_setup(bool pcie_slot)
  7613. +{
  7614. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  7615. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  7616. + u8 tmpmac[ETH_ALEN];
  7617. +
  7618. + ath79_register_m25p80(&archer_c7_flash_data);
  7619. + ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
  7620. + archer_c7_leds_gpio);
  7621. + ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
  7622. + ARRAY_SIZE(archer_c7_gpio_keys),
  7623. + archer_c7_gpio_keys);
  7624. +
  7625. + ath79_init_mac(tmpmac, mac, -1);
  7626. + ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
  7627. +
  7628. + if (pcie_slot) {
  7629. + ath79_register_pci();
  7630. + } else {
  7631. + ath79_init_mac(tmpmac, mac, -1);
  7632. + ap9x_pci_setup_wmac_led_pin(0, 0);
  7633. + ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac);
  7634. + }
  7635. +
  7636. + mdiobus_register_board_info(archer_c7_mdio0_info,
  7637. + ARRAY_SIZE(archer_c7_mdio0_info));
  7638. + ath79_register_mdio(0, 0x0);
  7639. +
  7640. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  7641. +
  7642. + /* GMAC0 is connected to the RMGII interface */
  7643. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  7644. + ath79_eth0_data.phy_mask = BIT(0);
  7645. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  7646. + ath79_eth0_pll_data.pll_1000 = 0x56000000;
  7647. +
  7648. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  7649. + ath79_register_eth(0);
  7650. +
  7651. + /* GMAC1 is connected to the SGMII interface */
  7652. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  7653. + ath79_eth1_data.speed = SPEED_1000;
  7654. + ath79_eth1_data.duplex = DUPLEX_FULL;
  7655. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  7656. +
  7657. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  7658. + ath79_register_eth(1);
  7659. +
  7660. + gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
  7661. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  7662. + "USB1 power");
  7663. + gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
  7664. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  7665. + "USB2 power");
  7666. + ath79_register_usb();
  7667. +}
  7668. +
  7669. +static void __init archer_c5_setup(void)
  7670. +{
  7671. + common_setup(true);
  7672. +}
  7673. +
  7674. +MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5",
  7675. + archer_c5_setup);
  7676. +
  7677. +static void __init archer_c7_setup(void)
  7678. +{
  7679. + common_setup(true);
  7680. +}
  7681. +
  7682. +MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7",
  7683. + archer_c7_setup);
  7684. +
  7685. +static void __init tl_wdr4900_v2_setup(void)
  7686. +{
  7687. + common_setup(false);
  7688. +}
  7689. +
  7690. +MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2",
  7691. + tl_wdr4900_v2_setup)
  7692. +
  7693. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-arduino-yun.c linux-4.1.43/arch/mips/ath79/mach-arduino-yun.c
  7694. --- linux-4.1.43.orig/arch/mips/ath79/mach-arduino-yun.c 1970-01-01 01:00:00.000000000 +0100
  7695. +++ linux-4.1.43/arch/mips/ath79/mach-arduino-yun.c 2017-08-06 20:02:15.000000000 +0200
  7696. @@ -0,0 +1,137 @@
  7697. +/*
  7698. + * Arduino Yun support
  7699. + *
  7700. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  7701. + * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
  7702. + *
  7703. + * This program is free software; you can redistribute it and/or modify it
  7704. + * under the terms of the GNU General Public License version 2 as published
  7705. + * by the Free Software Foundation.
  7706. + */
  7707. +
  7708. +#include "dev-eth.h"
  7709. +#include "dev-gpio-buttons.h"
  7710. +#include "dev-leds-gpio.h"
  7711. +#include "dev-m25p80.h"
  7712. +#include "dev-spi.h"
  7713. +#include "dev-usb.h"
  7714. +#include "dev-wmac.h"
  7715. +#include "machtypes.h"
  7716. +#include <asm/mach-ath79/ar71xx_regs.h>
  7717. +#include <asm/mach-ath79/ath79.h>
  7718. +#include "common.h"
  7719. +#include "gpio.h"
  7720. +#include "linux/gpio.h"
  7721. +
  7722. +// Uncomment to have reset on gpio18 instead of gipo7
  7723. +#define DS2_B
  7724. +
  7725. +#define DS_GPIO_LED_WLAN 0
  7726. +#define DS_GPIO_LED_USB 1
  7727. +
  7728. +#define DS_GPIO_OE 21
  7729. +#define DS_GPIO_AVR_RESET 18
  7730. +
  7731. +// Maintained to have the console in the previous version of DS2 working
  7732. +#define DS_GPIO_AVR_RESET_DS2 7
  7733. +
  7734. +#define DS_GPIO_OE2 22
  7735. +#define DS_GPIO_UART_ENA 23
  7736. +#define DS_GPIO_CONF_BTN 20
  7737. +
  7738. +#define DS_KEYS_POLL_INTERVAL 20 /* msecs */
  7739. +#define DS_KEYS_DEBOUNCE_INTERVAL (3 * DS_KEYS_POLL_INTERVAL)
  7740. +
  7741. +#define DS_MAC0_OFFSET 0x0000
  7742. +#define DS_MAC1_OFFSET 0x0006
  7743. +#define DS_CALDATA_OFFSET 0x1000
  7744. +#define DS_WMAC_MAC_OFFSET 0x1002
  7745. +
  7746. +
  7747. +static struct gpio_led ds_leds_gpio[] __initdata = {
  7748. + {
  7749. + .name = "arduino:white:usb",
  7750. + .gpio = DS_GPIO_LED_USB,
  7751. + .active_low = 0,
  7752. + },
  7753. + {
  7754. + .name = "arduino:blue:wlan",
  7755. + .gpio = DS_GPIO_LED_WLAN,
  7756. + .active_low = 0,
  7757. + },
  7758. +};
  7759. +
  7760. +static void __init ds_common_setup(void)
  7761. +{
  7762. + static u8 mac[6];
  7763. +
  7764. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  7765. + ath79_register_m25p80(NULL);
  7766. +
  7767. + if (ar93xx_wmac_read_mac_address(mac)) {
  7768. + ath79_register_wmac(NULL, NULL);
  7769. + } else {
  7770. + ath79_register_wmac(art + DS_CALDATA_OFFSET,
  7771. + art + DS_WMAC_MAC_OFFSET);
  7772. + memcpy(mac, art + DS_WMAC_MAC_OFFSET, sizeof(mac));
  7773. + }
  7774. +
  7775. + mac[3] |= 0x08;
  7776. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  7777. +
  7778. + mac[3] &= 0xF7;
  7779. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  7780. + ath79_register_mdio(0, 0x0);
  7781. +
  7782. + /* LAN ports */
  7783. + ath79_register_eth(1);
  7784. +
  7785. + /* WAN port */
  7786. + ath79_register_eth(0);
  7787. +}
  7788. +
  7789. +static void __init ds_setup(void)
  7790. +{
  7791. + u32 t;
  7792. +
  7793. + ds_common_setup();
  7794. +
  7795. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ds_leds_gpio),
  7796. + ds_leds_gpio);
  7797. + ath79_register_usb();
  7798. +
  7799. + //Disable the Function for some pins to have GPIO functionality active
  7800. + // GPIO6-7-8 and GPIO11
  7801. + ath79_gpio_function_setup(AR933X_GPIO_FUNC_JTAG_DISABLE | AR933X_GPIO_FUNC_I2S_MCK_EN, 0);
  7802. +
  7803. + ath79_gpio_function2_setup(AR933X_GPIO_FUNC2_JUMPSTART_DISABLE, 0);
  7804. +
  7805. + printk("Setting DogStick2 GPIO\n");
  7806. +
  7807. + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  7808. + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
  7809. + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
  7810. +
  7811. + // Put the avr reset to high
  7812. + if (gpio_request_one(DS_GPIO_AVR_RESET_DS2,
  7813. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "OE-1") != 0)
  7814. + printk("Error setting GPIO OE\n");
  7815. + gpio_unexport(DS_GPIO_AVR_RESET_DS2);
  7816. + gpio_free(DS_GPIO_AVR_RESET_DS2);
  7817. +
  7818. + // enable OE of level shifter
  7819. + if (gpio_request_one(DS_GPIO_OE,
  7820. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "OE-1") != 0)
  7821. + printk("Error setting GPIO OE\n");
  7822. +
  7823. + if (gpio_request_one(DS_GPIO_UART_ENA,
  7824. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "UART-ENA") != 0)
  7825. + printk("Error setting GPIO Uart Enable\n");
  7826. +
  7827. + // enable OE of level shifter
  7828. + if (gpio_request_one(DS_GPIO_OE2,
  7829. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "OE-2") != 0)
  7830. + printk("Error setting GPIO OE2\n");
  7831. +}
  7832. +
  7833. +MIPS_MACHINE(ATH79_MACH_ARDUINO_YUN, "Yun", "Arduino Yun", ds_setup);
  7834. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-aw-nr580.c linux-4.1.43/arch/mips/ath79/mach-aw-nr580.c
  7835. --- linux-4.1.43.orig/arch/mips/ath79/mach-aw-nr580.c 1970-01-01 01:00:00.000000000 +0100
  7836. +++ linux-4.1.43/arch/mips/ath79/mach-aw-nr580.c 2017-08-06 20:02:15.000000000 +0200
  7837. @@ -0,0 +1,107 @@
  7838. +/*
  7839. + * AzureWave AW-NR580 board support
  7840. + *
  7841. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  7842. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  7843. + *
  7844. + * This program is free software; you can redistribute it and/or modify it
  7845. + * under the terms of the GNU General Public License version 2 as published
  7846. + * by the Free Software Foundation.
  7847. + */
  7848. +
  7849. +#include <asm/mach-ath79/ath79.h>
  7850. +
  7851. +#include "dev-eth.h"
  7852. +#include "dev-m25p80.h"
  7853. +#include "dev-gpio-buttons.h"
  7854. +#include "dev-leds-gpio.h"
  7855. +#include "machtypes.h"
  7856. +#include "pci.h"
  7857. +
  7858. +#define AW_NR580_GPIO_LED_READY_RED 0
  7859. +#define AW_NR580_GPIO_LED_WLAN 1
  7860. +#define AW_NR580_GPIO_LED_READY_GREEN 2
  7861. +#define AW_NR580_GPIO_LED_WPS_GREEN 4
  7862. +#define AW_NR580_GPIO_LED_WPS_AMBER 5
  7863. +
  7864. +#define AW_NR580_GPIO_BTN_WPS 3
  7865. +#define AW_NR580_GPIO_BTN_RESET 11
  7866. +
  7867. +#define AW_NR580_KEYS_POLL_INTERVAL 20 /* msecs */
  7868. +#define AW_NR580_KEYS_DEBOUNCE_INTERVAL (3 * AW_NR580_KEYS_POLL_INTERVAL)
  7869. +
  7870. +static struct gpio_led aw_nr580_leds_gpio[] __initdata = {
  7871. + {
  7872. + .name = "aw-nr580:red:ready",
  7873. + .gpio = AW_NR580_GPIO_LED_READY_RED,
  7874. + .active_low = 0,
  7875. + }, {
  7876. + .name = "aw-nr580:green:ready",
  7877. + .gpio = AW_NR580_GPIO_LED_READY_GREEN,
  7878. + .active_low = 0,
  7879. + }, {
  7880. + .name = "aw-nr580:green:wps",
  7881. + .gpio = AW_NR580_GPIO_LED_WPS_GREEN,
  7882. + .active_low = 0,
  7883. + }, {
  7884. + .name = "aw-nr580:amber:wps",
  7885. + .gpio = AW_NR580_GPIO_LED_WPS_AMBER,
  7886. + .active_low = 0,
  7887. + }, {
  7888. + .name = "aw-nr580:green:wlan",
  7889. + .gpio = AW_NR580_GPIO_LED_WLAN,
  7890. + .active_low = 0,
  7891. + }
  7892. +};
  7893. +
  7894. +static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = {
  7895. + {
  7896. + .desc = "reset",
  7897. + .type = EV_KEY,
  7898. + .code = KEY_RESTART,
  7899. + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL,
  7900. + .gpio = AW_NR580_GPIO_BTN_RESET,
  7901. + .active_low = 1,
  7902. + }, {
  7903. + .desc = "wps",
  7904. + .type = EV_KEY,
  7905. + .code = KEY_WPS_BUTTON,
  7906. + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL,
  7907. + .gpio = AW_NR580_GPIO_BTN_WPS,
  7908. + .active_low = 1,
  7909. + }
  7910. +};
  7911. +
  7912. +static const char *aw_nr580_part_probes[] = {
  7913. + "RedBoot",
  7914. + NULL,
  7915. +};
  7916. +
  7917. +static struct flash_platform_data aw_nr580_flash_data = {
  7918. + .part_probes = aw_nr580_part_probes,
  7919. +};
  7920. +
  7921. +static void __init aw_nr580_setup(void)
  7922. +{
  7923. + ath79_register_mdio(0, 0x0);
  7924. +
  7925. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  7926. + ath79_eth0_data.speed = SPEED_100;
  7927. + ath79_eth0_data.duplex = DUPLEX_FULL;
  7928. +
  7929. + ath79_register_eth(0);
  7930. +
  7931. + ath79_register_pci();
  7932. +
  7933. + ath79_register_m25p80(&aw_nr580_flash_data);
  7934. +
  7935. + ath79_register_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio),
  7936. + aw_nr580_leds_gpio);
  7937. +
  7938. + ath79_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL,
  7939. + ARRAY_SIZE(aw_nr580_gpio_keys),
  7940. + aw_nr580_gpio_keys);
  7941. +}
  7942. +
  7943. +MIPS_MACHINE(ATH79_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580",
  7944. + aw_nr580_setup);
  7945. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-bhu-bxu2000n2-a.c linux-4.1.43/arch/mips/ath79/mach-bhu-bxu2000n2-a.c
  7946. --- linux-4.1.43.orig/arch/mips/ath79/mach-bhu-bxu2000n2-a.c 1970-01-01 01:00:00.000000000 +0100
  7947. +++ linux-4.1.43/arch/mips/ath79/mach-bhu-bxu2000n2-a.c 2017-08-06 20:02:15.000000000 +0200
  7948. @@ -0,0 +1,120 @@
  7949. +/*
  7950. + * BHU BXU2000n-2 A1 board support
  7951. + *
  7952. + * Copyright (C) 2013 Terry Yang <yangbo@bhunetworks.com>
  7953. + *
  7954. + * This program is free software; you can redistribute it and/or modify it
  7955. + * under the terms of the GNU General Public License version 2 as published
  7956. + * by the Free Software Foundation.
  7957. + */
  7958. +
  7959. +#include <linux/gpio.h>
  7960. +#include <linux/platform_device.h>
  7961. +
  7962. +#include <asm/mach-ath79/ath79.h>
  7963. +#include <asm/mach-ath79/ar71xx_regs.h>
  7964. +
  7965. +#include "common.h"
  7966. +#include "dev-eth.h"
  7967. +#include "dev-gpio-buttons.h"
  7968. +#include "dev-leds-gpio.h"
  7969. +#include "dev-m25p80.h"
  7970. +#include "dev-usb.h"
  7971. +#include "dev-wmac.h"
  7972. +#include "machtypes.h"
  7973. +
  7974. +#define BHU_BXU2000N2_A1_GPIO_LED_WLAN 13
  7975. +#define BHU_BXU2000N2_A1_GPIO_LED_WAN 19
  7976. +#define BHU_BXU2000N2_A1_GPIO_LED_LAN 21
  7977. +#define BHU_BXU2000N2_A1_GPIO_LED_SYSTEM 14
  7978. +
  7979. +#define BHU_BXU2000N2_A1_GPIO_BTN_RESET 17
  7980. +
  7981. +#define BHU_BXU2000N2_KEYS_POLL_INTERVAL 20 /* msecs */
  7982. +#define BHU_BXU2000N2_KEYS_DEBOUNCE_INTERVAL \
  7983. + (3 * BHU_BXU2000N2_KEYS_POLL_INTERVAL)
  7984. +
  7985. +static const char *bhu_bxu2000n2_part_probes[] = {
  7986. + "cmdlinepart",
  7987. + NULL,
  7988. +};
  7989. +
  7990. +static struct flash_platform_data bhu_bxu2000n2_flash_data = {
  7991. + .part_probes = bhu_bxu2000n2_part_probes,
  7992. +};
  7993. +
  7994. +static struct gpio_led bhu_bxu2000n2_a1_leds_gpio[] __initdata = {
  7995. + {
  7996. + .name = "bhu:green:status",
  7997. + .gpio = BHU_BXU2000N2_A1_GPIO_LED_SYSTEM,
  7998. + .active_low = 1,
  7999. + }, {
  8000. + .name = "bhu:green:lan",
  8001. + .gpio = BHU_BXU2000N2_A1_GPIO_LED_LAN,
  8002. + .active_low = 1,
  8003. + }, {
  8004. + .name = "bhu:green:wan",
  8005. + .gpio = BHU_BXU2000N2_A1_GPIO_LED_WAN,
  8006. + .active_low = 1,
  8007. + }, {
  8008. + .name = "bhu:green:wlan",
  8009. + .gpio = BHU_BXU2000N2_A1_GPIO_LED_WLAN,
  8010. + .active_low = 1,
  8011. + },
  8012. +};
  8013. +
  8014. +static struct gpio_keys_button bhu_bxu2000n2_a1_gpio_keys[] __initdata = {
  8015. + {
  8016. + .desc = "Reset button",
  8017. + .type = EV_KEY,
  8018. + .code = KEY_RESTART,
  8019. + .debounce_interval = BHU_BXU2000N2_KEYS_DEBOUNCE_INTERVAL,
  8020. + .gpio = BHU_BXU2000N2_A1_GPIO_BTN_RESET,
  8021. + .active_low = 1,
  8022. + }
  8023. +};
  8024. +
  8025. +static void __init bhu_ap123_setup(void)
  8026. +{
  8027. + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
  8028. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  8029. +
  8030. + ath79_register_m25p80(&bhu_bxu2000n2_flash_data);
  8031. +
  8032. + ath79_register_mdio(1, 0x0);
  8033. +
  8034. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  8035. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  8036. +
  8037. + /* GMAC0 is connected to the PHY4 of the internal switch */
  8038. + ath79_switch_data.phy4_mii_en = 1;
  8039. + ath79_switch_data.phy_poll_mask = BIT(4);
  8040. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  8041. + ath79_eth0_data.phy_mask = BIT(4);
  8042. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  8043. + ath79_register_eth(0);
  8044. +
  8045. + /* GMAC1 is connected to the internal switch. Only use PHY3 */
  8046. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  8047. + ath79_eth1_data.phy_mask = BIT(3);
  8048. + ath79_register_eth(1);
  8049. +
  8050. + ath79_register_wmac(ee, ee+2);
  8051. +}
  8052. +
  8053. +static void __init bhu_bxu2000n2_a1_setup(void)
  8054. +{
  8055. + bhu_ap123_setup();
  8056. +
  8057. + ath79_register_leds_gpio(-1, ARRAY_SIZE(bhu_bxu2000n2_a1_leds_gpio),
  8058. + bhu_bxu2000n2_a1_leds_gpio);
  8059. +
  8060. + ath79_register_gpio_keys_polled(1, BHU_BXU2000N2_KEYS_POLL_INTERVAL,
  8061. + ARRAY_SIZE(bhu_bxu2000n2_a1_gpio_keys),
  8062. + bhu_bxu2000n2_a1_gpio_keys);
  8063. +}
  8064. +
  8065. +MIPS_MACHINE(ATH79_MACH_BHU_BXU2000N2_A1, "BXU2000n-2-A1",
  8066. + "BHU BXU2000n-2 rev. A1",
  8067. + bhu_bxu2000n2_a1_setup);
  8068. +
  8069. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-bsb.c linux-4.1.43/arch/mips/ath79/mach-bsb.c
  8070. --- linux-4.1.43.orig/arch/mips/ath79/mach-bsb.c 1970-01-01 01:00:00.000000000 +0100
  8071. +++ linux-4.1.43/arch/mips/ath79/mach-bsb.c 2017-08-06 20:02:15.000000000 +0200
  8072. @@ -0,0 +1,83 @@
  8073. +/*
  8074. + * Smart Electronics Black Swift board support
  8075. + *
  8076. + * Copyright (C) 2014 Dmitriy Zherebkov dzh@black-swift.com
  8077. + *
  8078. + * This program is free software; you can redistribute it and/or modify it
  8079. + * under the terms of the GNU General Public License version 2 as published
  8080. + * by the Free Software Foundation.
  8081. + */
  8082. +
  8083. +#include <asm/mach-ath79/ath79.h>
  8084. +#include <asm/mach-ath79/ar71xx_regs.h>
  8085. +#include "common.h"
  8086. +#include "dev-eth.h"
  8087. +#include "dev-gpio-buttons.h"
  8088. +#include "dev-leds-gpio.h"
  8089. +#include "dev-m25p80.h"
  8090. +#include "dev-spi.h"
  8091. +#include "dev-usb.h"
  8092. +#include "dev-wmac.h"
  8093. +#include "machtypes.h"
  8094. +
  8095. +#define BSB_GPIO_LED_SYS 27
  8096. +
  8097. +#define BSB_GPIO_BTN_RESET 11
  8098. +
  8099. +#define BSB_KEYS_POLL_INTERVAL 20 /* msecs */
  8100. +#define BSB_KEYS_DEBOUNCE_INTERVAL (3 * BSB_KEYS_POLL_INTERVAL)
  8101. +
  8102. +#define BSB_MAC_OFFSET 0x0000
  8103. +#define BSB_CALDATA_OFFSET 0x1000
  8104. +
  8105. +static struct gpio_led bsb_leds_gpio[] __initdata = {
  8106. + {
  8107. + .name = "bsb:red:sys",
  8108. + .gpio = BSB_GPIO_LED_SYS,
  8109. + .active_low = 1,
  8110. + }
  8111. +};
  8112. +
  8113. +static struct gpio_keys_button bsb_gpio_keys[] __initdata = {
  8114. + {
  8115. + .desc = "reset button",
  8116. + .type = EV_KEY,
  8117. + .code = KEY_RESTART,
  8118. + .debounce_interval = BSB_KEYS_DEBOUNCE_INTERVAL,
  8119. + .gpio = BSB_GPIO_BTN_RESET,
  8120. + .active_low = 1,
  8121. + },
  8122. +};
  8123. +
  8124. +static void __init bsb_setup(void)
  8125. +{
  8126. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  8127. +
  8128. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  8129. + ath79_setup_ar933x_phy4_switch(false,false);
  8130. +
  8131. + ath79_register_leds_gpio(-1, ARRAY_SIZE(bsb_leds_gpio),
  8132. + bsb_leds_gpio);
  8133. + ath79_register_gpio_keys_polled(-1, BSB_KEYS_POLL_INTERVAL,
  8134. + ARRAY_SIZE(bsb_gpio_keys),
  8135. + bsb_gpio_keys);
  8136. +
  8137. + ath79_register_usb();
  8138. +
  8139. + ath79_register_m25p80(NULL);
  8140. +
  8141. + ath79_init_mac(ath79_eth0_data.mac_addr, art + BSB_MAC_OFFSET, 1);
  8142. + ath79_init_mac(ath79_eth1_data.mac_addr, art + BSB_MAC_OFFSET, 2);
  8143. +
  8144. + ath79_register_mdio(0, 0x0);
  8145. +
  8146. + ath79_register_eth(0);
  8147. + ath79_register_eth(1);
  8148. +
  8149. + ath79_register_wmac(art + BSB_CALDATA_OFFSET,
  8150. + art + BSB_MAC_OFFSET);
  8151. +}
  8152. +
  8153. +MIPS_MACHINE(ATH79_MACH_BSB, "BSB", "Smart Electronics Black Swift board",
  8154. + bsb_setup);
  8155. +
  8156. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-cap4200ag.c linux-4.1.43/arch/mips/ath79/mach-cap4200ag.c
  8157. --- linux-4.1.43.orig/arch/mips/ath79/mach-cap4200ag.c 1970-01-01 01:00:00.000000000 +0100
  8158. +++ linux-4.1.43/arch/mips/ath79/mach-cap4200ag.c 2017-08-06 20:02:15.000000000 +0200
  8159. @@ -0,0 +1,131 @@
  8160. +/*
  8161. + * Senao CAP4200AG board support
  8162. + *
  8163. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  8164. + *
  8165. + * This program is free software; you can redistribute it and/or modify it
  8166. + * under the terms of the GNU General Public License version 2 as published
  8167. + * by the Free Software Foundation.
  8168. + */
  8169. +
  8170. +#include <linux/pci.h>
  8171. +#include <linux/phy.h>
  8172. +#include <linux/platform_device.h>
  8173. +#include <linux/ath9k_platform.h>
  8174. +
  8175. +#include <asm/mach-ath79/ar71xx_regs.h>
  8176. +
  8177. +#include "common.h"
  8178. +#include "dev-ap9x-pci.h"
  8179. +#include "dev-eth.h"
  8180. +#include "dev-gpio-buttons.h"
  8181. +#include "dev-leds-gpio.h"
  8182. +#include "dev-m25p80.h"
  8183. +#include "dev-spi.h"
  8184. +#include "dev-usb.h"
  8185. +#include "dev-wmac.h"
  8186. +#include "machtypes.h"
  8187. +
  8188. +#define CAP4200AG_GPIO_LED_PWR_GREEN 12
  8189. +#define CAP4200AG_GPIO_LED_PWR_AMBER 13
  8190. +#define CAP4200AG_GPIO_LED_LAN_GREEN 14
  8191. +#define CAP4200AG_GPIO_LED_LAN_AMBER 15
  8192. +#define CAP4200AG_GPIO_LED_WLAN_GREEN 18
  8193. +#define CAP4200AG_GPIO_LED_WLAN_AMBER 19
  8194. +
  8195. +#define CAP4200AG_GPIO_BTN_RESET 17
  8196. +
  8197. +#define CAP4200AG_KEYS_POLL_INTERVAL 20 /* msecs */
  8198. +#define CAP4200AG_KEYS_DEBOUNCE_INTERVAL (3 * CAP4200AG_KEYS_POLL_INTERVAL)
  8199. +
  8200. +#define CAP4200AG_MAC_OFFSET 0
  8201. +#define CAP4200AG_WMAC_CALDATA_OFFSET 0x1000
  8202. +#define CAP4200AG_PCIE_CALDATA_OFFSET 0x5000
  8203. +
  8204. +static struct gpio_led cap4200ag_leds_gpio[] __initdata = {
  8205. + {
  8206. + .name = "senao:green:pwr",
  8207. + .gpio = CAP4200AG_GPIO_LED_PWR_GREEN,
  8208. + .active_low = 1,
  8209. + },
  8210. + {
  8211. + .name = "senao:amber:pwr",
  8212. + .gpio = CAP4200AG_GPIO_LED_PWR_AMBER,
  8213. + .active_low = 1,
  8214. + },
  8215. + {
  8216. + .name = "senao:green:lan",
  8217. + .gpio = CAP4200AG_GPIO_LED_LAN_GREEN,
  8218. + .active_low = 1,
  8219. + },
  8220. + {
  8221. + .name = "senao:amber:lan",
  8222. + .gpio = CAP4200AG_GPIO_LED_LAN_AMBER,
  8223. + .active_low = 1,
  8224. + },
  8225. + {
  8226. + .name = "senao:green:wlan",
  8227. + .gpio = CAP4200AG_GPIO_LED_WLAN_GREEN,
  8228. + .active_low = 1,
  8229. + },
  8230. + {
  8231. + .name = "senao:amber:wlan",
  8232. + .gpio = CAP4200AG_GPIO_LED_WLAN_AMBER,
  8233. + .active_low = 1,
  8234. + },
  8235. +};
  8236. +
  8237. +static struct gpio_keys_button cap4200ag_gpio_keys[] __initdata = {
  8238. + {
  8239. + .desc = "Reset button",
  8240. + .type = EV_KEY,
  8241. + .code = KEY_RESTART,
  8242. + .debounce_interval = CAP4200AG_KEYS_DEBOUNCE_INTERVAL,
  8243. + .gpio = CAP4200AG_GPIO_BTN_RESET,
  8244. + .active_low = 1,
  8245. + },
  8246. +};
  8247. +
  8248. +static void __init cap4200ag_setup(void)
  8249. +{
  8250. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  8251. + u8 mac[6];
  8252. +
  8253. + ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_GREEN,
  8254. + AR934X_GPIO_OUT_GPIO);
  8255. + ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_AMBER,
  8256. + AR934X_GPIO_OUT_GPIO);
  8257. +
  8258. + ath79_register_m25p80(NULL);
  8259. +
  8260. + ath79_register_leds_gpio(-1, ARRAY_SIZE(cap4200ag_leds_gpio),
  8261. + cap4200ag_leds_gpio);
  8262. + ath79_register_gpio_keys_polled(-1, CAP4200AG_KEYS_POLL_INTERVAL,
  8263. + ARRAY_SIZE(cap4200ag_gpio_keys),
  8264. + cap4200ag_gpio_keys);
  8265. +
  8266. + ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -1);
  8267. + ath79_wmac_disable_2ghz();
  8268. + ath79_register_wmac(art + CAP4200AG_WMAC_CALDATA_OFFSET, mac);
  8269. +
  8270. + ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -2);
  8271. + ap91_pci_init(art + CAP4200AG_PCIE_CALDATA_OFFSET, mac);
  8272. +
  8273. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  8274. + AR934X_ETH_CFG_SW_ONLY_MODE);
  8275. +
  8276. + ath79_register_mdio(0, 0x0);
  8277. +
  8278. + ath79_init_mac(ath79_eth0_data.mac_addr,
  8279. + art + CAP4200AG_MAC_OFFSET, -2);
  8280. +
  8281. + /* GMAC0 is connected to an external PHY */
  8282. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  8283. + ath79_eth0_data.phy_mask = BIT(0);
  8284. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  8285. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  8286. + ath79_register_eth(0);
  8287. +}
  8288. +
  8289. +MIPS_MACHINE(ATH79_MACH_CAP4200AG, "CAP4200AG", "Senao CAP4200AG",
  8290. + cap4200ag_setup);
  8291. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-carambola2.c linux-4.1.43/arch/mips/ath79/mach-carambola2.c
  8292. --- linux-4.1.43.orig/arch/mips/ath79/mach-carambola2.c 1970-01-01 01:00:00.000000000 +0100
  8293. +++ linux-4.1.43/arch/mips/ath79/mach-carambola2.c 2017-08-06 20:02:15.000000000 +0200
  8294. @@ -0,0 +1,105 @@
  8295. +/*
  8296. + * 8devices Carambola2 board support
  8297. + *
  8298. + * Copyright (C) 2013 Darius Augulis <darius@8devices.com>
  8299. + *
  8300. + * This program is free software; you can redistribute it and/or modify it
  8301. + * under the terms of the GNU General Public License version 2 as published
  8302. + * by the Free Software Foundation.
  8303. + */
  8304. +
  8305. +#include <asm/mach-ath79/ath79.h>
  8306. +#include <asm/mach-ath79/ar71xx_regs.h>
  8307. +#include "common.h"
  8308. +#include "dev-eth.h"
  8309. +#include "dev-gpio-buttons.h"
  8310. +#include "dev-leds-gpio.h"
  8311. +#include "dev-m25p80.h"
  8312. +#include "dev-spi.h"
  8313. +#include "dev-usb.h"
  8314. +#include "dev-wmac.h"
  8315. +#include "machtypes.h"
  8316. +
  8317. +#define CARAMBOLA2_GPIO_LED_WLAN 0
  8318. +#define CARAMBOLA2_GPIO_LED_ETH0 14
  8319. +#define CARAMBOLA2_GPIO_LED_ETH1 13
  8320. +
  8321. +#define CARAMBOLA2_GPIO_BTN_JUMPSTART 11
  8322. +
  8323. +#define CARAMBOLA2_KEYS_POLL_INTERVAL 20 /* msecs */
  8324. +#define CARAMBOLA2_KEYS_DEBOUNCE_INTERVAL (3 * CARAMBOLA2_KEYS_POLL_INTERVAL)
  8325. +
  8326. +#define CARAMBOLA2_MAC0_OFFSET 0x0000
  8327. +#define CARAMBOLA2_MAC1_OFFSET 0x0006
  8328. +#define CARAMBOLA2_CALDATA_OFFSET 0x1000
  8329. +#define CARAMBOLA2_WMAC_MAC_OFFSET 0x1002
  8330. +
  8331. +static struct gpio_led carambola2_leds_gpio[] __initdata = {
  8332. + {
  8333. + .name = "carambola2:green:wlan",
  8334. + .gpio = CARAMBOLA2_GPIO_LED_WLAN,
  8335. + .active_low = 1,
  8336. + }, {
  8337. + .name = "carambola2:orange:eth0",
  8338. + .gpio = CARAMBOLA2_GPIO_LED_ETH0,
  8339. + .active_low = 0,
  8340. + }, {
  8341. + .name = "carambola2:orange:eth1",
  8342. + .gpio = CARAMBOLA2_GPIO_LED_ETH1,
  8343. + .active_low = 0,
  8344. + }
  8345. +};
  8346. +
  8347. +static struct gpio_keys_button carambola2_gpio_keys[] __initdata = {
  8348. + {
  8349. + .desc = "jumpstart button",
  8350. + .type = EV_KEY,
  8351. + .code = KEY_WPS_BUTTON,
  8352. + .debounce_interval = CARAMBOLA2_KEYS_DEBOUNCE_INTERVAL,
  8353. + .gpio = CARAMBOLA2_GPIO_BTN_JUMPSTART,
  8354. + .active_low = 1,
  8355. + },
  8356. +};
  8357. +
  8358. +static void __init carambola2_common_setup(void)
  8359. +{
  8360. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  8361. +
  8362. + ath79_register_m25p80(NULL);
  8363. + ath79_register_wmac(art + CARAMBOLA2_CALDATA_OFFSET,
  8364. + art + CARAMBOLA2_WMAC_MAC_OFFSET);
  8365. +
  8366. + ath79_setup_ar933x_phy4_switch(true, true);
  8367. +
  8368. + ath79_init_mac(ath79_eth0_data.mac_addr, art + CARAMBOLA2_MAC0_OFFSET, 0);
  8369. + ath79_init_mac(ath79_eth1_data.mac_addr, art + CARAMBOLA2_MAC1_OFFSET, 0);
  8370. +
  8371. + ath79_register_mdio(0, 0x0);
  8372. +
  8373. + /* LAN ports */
  8374. + ath79_register_eth(1);
  8375. +
  8376. + /* WAN port */
  8377. + ath79_register_eth(0);
  8378. +}
  8379. +
  8380. +static void __init carambola2_setup(void)
  8381. +{
  8382. + carambola2_common_setup();
  8383. +
  8384. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  8385. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  8386. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  8387. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  8388. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  8389. +
  8390. + ath79_register_leds_gpio(-1, ARRAY_SIZE(carambola2_leds_gpio),
  8391. + carambola2_leds_gpio);
  8392. + ath79_register_gpio_keys_polled(-1, CARAMBOLA2_KEYS_POLL_INTERVAL,
  8393. + ARRAY_SIZE(carambola2_gpio_keys),
  8394. + carambola2_gpio_keys);
  8395. + ath79_register_usb();
  8396. +}
  8397. +
  8398. +MIPS_MACHINE(ATH79_MACH_CARAMBOLA2, "CARAMBOLA2", "8devices Carambola2 board",
  8399. + carambola2_setup);
  8400. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-cf-e316n-v2.c linux-4.1.43/arch/mips/ath79/mach-cf-e316n-v2.c
  8401. --- linux-4.1.43.orig/arch/mips/ath79/mach-cf-e316n-v2.c 1970-01-01 01:00:00.000000000 +0100
  8402. +++ linux-4.1.43/arch/mips/ath79/mach-cf-e316n-v2.c 2017-08-06 20:02:15.000000000 +0200
  8403. @@ -0,0 +1,132 @@
  8404. +/*
  8405. + * COMFAST CF-E316N v2
  8406. + * by Shenzhen Four Seas Global Link Network Technology Co., Ltd
  8407. + *
  8408. + * aka CF-E316V2, CF-E316N-V2 and CF-E316Nv2.0 (no FCC ID)
  8409. + *
  8410. + * Copyright (C) 2015 Paul Fertser <fercerpav@gmail.com>
  8411. + *
  8412. + * This program is free software; you can redistribute it and/or modify it
  8413. + * under the terms of the GNU General Public License version 2 as published
  8414. + * by the Free Software Foundation.
  8415. + */
  8416. +
  8417. +#include <linux/gpio.h>
  8418. +#include <linux/platform_device.h>
  8419. +#include <linux/timer.h>
  8420. +
  8421. +#include <asm/mach-ath79/ath79.h>
  8422. +#include <asm/mach-ath79/ar71xx_regs.h>
  8423. +
  8424. +#include "common.h"
  8425. +#include "dev-eth.h"
  8426. +#include "dev-gpio-buttons.h"
  8427. +#include "dev-leds-gpio.h"
  8428. +#include "dev-m25p80.h"
  8429. +#include "dev-wmac.h"
  8430. +#include "dev-usb.h"
  8431. +#include "machtypes.h"
  8432. +
  8433. +static struct gpio_led cf_e316n_v2_leds_gpio[] __initdata = {
  8434. + {
  8435. + .name = "cf-e316n-v2:blue:diag",
  8436. + .gpio = 0,
  8437. + .active_low = 0,
  8438. + }, {
  8439. + .name = "cf-e316n-v2:red:diag",
  8440. + .gpio = 2,
  8441. + .active_low = 0,
  8442. + }, {
  8443. + .name = "cf-e316n-v2:green:diag",
  8444. + .gpio = 3,
  8445. + .active_low = 0,
  8446. + }, {
  8447. + .name = "cf-e316n-v2:blue:wlan",
  8448. + .gpio = 12,
  8449. + .active_low = 1,
  8450. + }, {
  8451. + .name = "cf-e316n-v2:blue:wan",
  8452. + .gpio = 17,
  8453. + .active_low = 1,
  8454. + }, {
  8455. + .name = "cf-e316n-v2:blue:lan",
  8456. + .gpio = 19,
  8457. + .active_low = 1,
  8458. + },
  8459. +};
  8460. +
  8461. +static struct gpio_keys_button cf_e316n_v2_gpio_keys[] __initdata = {
  8462. + {
  8463. + .desc = "Reset button",
  8464. + .type = EV_KEY,
  8465. + .code = KEY_RESTART,
  8466. + .debounce_interval = 60,
  8467. + .gpio = 20,
  8468. + .active_low = 1,
  8469. + },
  8470. +};
  8471. +
  8472. +/* There's a Pericon Technology PT7A7514 connected to GPIO 16 */
  8473. +#define EXT_WATCHDOG_GPIO 16
  8474. +static struct timer_list gpio_wdt_timer;
  8475. +
  8476. +static void gpio_wdt_toggle(unsigned long period)
  8477. +{
  8478. + static int state;
  8479. + state = !state;
  8480. + gpio_set_value(EXT_WATCHDOG_GPIO, state);
  8481. + mod_timer(&gpio_wdt_timer, jiffies + period);
  8482. +}
  8483. +
  8484. +static void __init cf_e316n_v2_setup(void)
  8485. +{
  8486. + u8 *maclan = (u8 *) KSEG1ADDR(0x1f010000);
  8487. + u8 *macwlan = (u8 *) KSEG1ADDR(0x1f011002);
  8488. + u8 *ee = (u8 *) KSEG1ADDR(0x1f011000);
  8489. + u8 tmpmac[ETH_ALEN];
  8490. +
  8491. + gpio_request(EXT_WATCHDOG_GPIO, "PT7A7514 watchdog");
  8492. + gpio_direction_output(EXT_WATCHDOG_GPIO, 0);
  8493. + setup_timer(&gpio_wdt_timer, gpio_wdt_toggle, msecs_to_jiffies(500));
  8494. + gpio_wdt_toggle(msecs_to_jiffies(1));
  8495. +
  8496. + ath79_register_m25p80(NULL);
  8497. +
  8498. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  8499. + ath79_register_mdio(1, 0x0);
  8500. +
  8501. + /* GMAC0 is connected to the PHY0 of the internal switch */
  8502. + ath79_switch_data.phy4_mii_en = 1;
  8503. + ath79_switch_data.phy_poll_mask = BIT(0);
  8504. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  8505. + ath79_eth0_data.phy_mask = BIT(0);
  8506. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  8507. + ath79_init_mac(ath79_eth0_data.mac_addr, maclan, 0);
  8508. + ath79_register_eth(0);
  8509. +
  8510. + /* GMAC1 is connected to the internal switch */
  8511. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  8512. + ath79_init_mac(ath79_eth1_data.mac_addr, maclan, 2);
  8513. + ath79_register_eth(1);
  8514. +
  8515. + /* Enable 2x Skyworks SE2576L WLAN power amplifiers */
  8516. + gpio_request(13, "RF Amp 1");
  8517. + gpio_direction_output(13, 1);
  8518. + gpio_request(14, "RF Amp 2");
  8519. + gpio_direction_output(14, 1);
  8520. + ath79_init_mac(tmpmac, macwlan, 0);
  8521. + ath79_register_wmac(ee, tmpmac);
  8522. +
  8523. + ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e316n_v2_leds_gpio),
  8524. + cf_e316n_v2_leds_gpio);
  8525. +
  8526. + ath79_register_gpio_keys_polled(1, 20,
  8527. + ARRAY_SIZE(cf_e316n_v2_gpio_keys),
  8528. + cf_e316n_v2_gpio_keys);
  8529. +
  8530. + /* J1 is a High-Speed USB port, pin 1 is Vcc */
  8531. + ath79_register_usb();
  8532. +}
  8533. +
  8534. +MIPS_MACHINE(ATH79_MACH_CF_E316N_V2, "CF-E316N-V2", "COMFAST CF-E316N v2",
  8535. + cf_e316n_v2_setup);
  8536. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-cpe510.c linux-4.1.43/arch/mips/ath79/mach-cpe510.c
  8537. --- linux-4.1.43.orig/arch/mips/ath79/mach-cpe510.c 1970-01-01 01:00:00.000000000 +0100
  8538. +++ linux-4.1.43/arch/mips/ath79/mach-cpe510.c 2017-08-06 20:02:15.000000000 +0200
  8539. @@ -0,0 +1,107 @@
  8540. +/*
  8541. + * TP-LINK CPE210/220/510/520 board support
  8542. + *
  8543. + * Copyright (C) 2014 Matthias Schiffer <mschiffer@universe-factory.net>
  8544. + *
  8545. + * This program is free software; you can redistribute it and/or modify it
  8546. + * under the terms of the GNU General Public License version 2 as published
  8547. + * by the Free Software Foundation.
  8548. + */
  8549. +
  8550. +#include <linux/gpio.h>
  8551. +#include <linux/platform_device.h>
  8552. +
  8553. +#include <asm/mach-ath79/ath79.h>
  8554. +#include <asm/mach-ath79/ar71xx_regs.h>
  8555. +
  8556. +#include "common.h"
  8557. +#include "dev-eth.h"
  8558. +#include "dev-gpio-buttons.h"
  8559. +#include "dev-leds-gpio.h"
  8560. +#include "dev-m25p80.h"
  8561. +#include "dev-wmac.h"
  8562. +#include "machtypes.h"
  8563. +
  8564. +
  8565. +#define CPE510_GPIO_LED_LAN0 11
  8566. +#define CPE510_GPIO_LED_LAN1 12
  8567. +#define CPE510_GPIO_LED_L1 13
  8568. +#define CPE510_GPIO_LED_L2 14
  8569. +#define CPE510_GPIO_LED_L3 15
  8570. +#define CPE510_GPIO_LED_L4 16
  8571. +
  8572. +#define CPE510_GPIO_BTN_RESET 4
  8573. +
  8574. +#define CPE510_KEYS_POLL_INTERVAL 20 /* msecs */
  8575. +#define CPE510_KEYS_DEBOUNCE_INTERVAL (3 * CPE510_KEYS_POLL_INTERVAL)
  8576. +
  8577. +
  8578. +static struct gpio_led cpe510_leds_gpio[] __initdata = {
  8579. + {
  8580. + .name = "tp-link:green:lan0",
  8581. + .gpio = CPE510_GPIO_LED_LAN0,
  8582. + .active_low = 1,
  8583. + }, {
  8584. + .name = "tp-link:green:lan1",
  8585. + .gpio = CPE510_GPIO_LED_LAN1,
  8586. + .active_low = 1,
  8587. + }, {
  8588. + .name = "tp-link:green:link1",
  8589. + .gpio = CPE510_GPIO_LED_L1,
  8590. + .active_low = 1,
  8591. + }, {
  8592. + .name = "tp-link:green:link2",
  8593. + .gpio = CPE510_GPIO_LED_L2,
  8594. + .active_low = 1,
  8595. + }, {
  8596. + .name = "tp-link:green:link3",
  8597. + .gpio = CPE510_GPIO_LED_L3,
  8598. + .active_low = 1,
  8599. + }, {
  8600. + .name = "tp-link:green:link4",
  8601. + .gpio = CPE510_GPIO_LED_L4,
  8602. + .active_low = 1,
  8603. + },
  8604. +};
  8605. +
  8606. +static struct gpio_keys_button cpe510_gpio_keys[] __initdata = {
  8607. + {
  8608. + .desc = "Reset button",
  8609. + .type = EV_KEY,
  8610. + .code = KEY_RESTART,
  8611. + .debounce_interval = CPE510_KEYS_DEBOUNCE_INTERVAL,
  8612. + .gpio = CPE510_GPIO_BTN_RESET,
  8613. + .active_low = 1,
  8614. + }
  8615. +};
  8616. +
  8617. +
  8618. +static void __init cpe510_setup(void)
  8619. +{
  8620. + u8 *mac = (u8 *) KSEG1ADDR(0x1f830008);
  8621. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  8622. +
  8623. + /* Disable JTAG, enabling GPIOs 0-3 */
  8624. + /* Configure OBS4 line, for GPIO 4*/
  8625. + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
  8626. + AR934X_GPIO_FUNC_CLK_OBS4_EN);
  8627. +
  8628. + ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe510_leds_gpio),
  8629. + cpe510_leds_gpio);
  8630. +
  8631. + ath79_register_gpio_keys_polled(1, CPE510_KEYS_POLL_INTERVAL,
  8632. + ARRAY_SIZE(cpe510_gpio_keys),
  8633. + cpe510_gpio_keys);
  8634. +
  8635. + ath79_register_m25p80(NULL);
  8636. +
  8637. + ath79_register_mdio(1, 0);
  8638. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  8639. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  8640. + ath79_register_eth(1);
  8641. +
  8642. + ath79_register_wmac(ee, mac);
  8643. +}
  8644. +
  8645. +MIPS_MACHINE(ATH79_MACH_CPE510, "CPE510", "TP-LINK CPE210/220/510/520",
  8646. + cpe510_setup);
  8647. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-db120.c linux-4.1.43/arch/mips/ath79/mach-db120.c
  8648. --- linux-4.1.43.orig/arch/mips/ath79/mach-db120.c 2017-08-06 01:56:14.000000000 +0200
  8649. +++ linux-4.1.43/arch/mips/ath79/mach-db120.c 2017-08-06 20:02:15.000000000 +0200
  8650. @@ -2,7 +2,7 @@
  8651. * Atheros DB120 reference board support
  8652. *
  8653. * Copyright (c) 2011 Qualcomm Atheros
  8654. - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
  8655. + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  8656. *
  8657. * Permission to use, copy, modify, and/or distribute this software for any
  8658. * purpose with or without fee is hereby granted, provided that the above
  8659. @@ -19,16 +19,26 @@
  8660. */
  8661. #include <linux/pci.h>
  8662. +#include <linux/phy.h>
  8663. +#include <linux/platform_device.h>
  8664. #include <linux/ath9k_platform.h>
  8665. +#include <linux/ar8216_platform.h>
  8666. -#include "machtypes.h"
  8667. +#include <asm/mach-ath79/ar71xx_regs.h>
  8668. +
  8669. +#include "common.h"
  8670. +#include "dev-ap9x-pci.h"
  8671. +#include "dev-eth.h"
  8672. #include "dev-gpio-buttons.h"
  8673. #include "dev-leds-gpio.h"
  8674. +#include "dev-m25p80.h"
  8675. +#include "dev-nfc.h"
  8676. #include "dev-spi.h"
  8677. #include "dev-usb.h"
  8678. #include "dev-wmac.h"
  8679. -#include "pci.h"
  8680. +#include "machtypes.h"
  8681. +#define DB120_GPIO_LED_USB 11
  8682. #define DB120_GPIO_LED_WLAN_5G 12
  8683. #define DB120_GPIO_LED_WLAN_2G 13
  8684. #define DB120_GPIO_LED_STATUS 14
  8685. @@ -39,8 +49,10 @@
  8686. #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
  8687. #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
  8688. -#define DB120_WMAC_CALDATA_OFFSET 0x1000
  8689. -#define DB120_PCIE_CALDATA_OFFSET 0x5000
  8690. +#define DB120_MAC0_OFFSET 0
  8691. +#define DB120_MAC1_OFFSET 6
  8692. +#define DB120_WMAC_CALDATA_OFFSET 0x1000
  8693. +#define DB120_PCIE_CALDATA_OFFSET 0x5000
  8694. static struct gpio_led db120_leds_gpio[] __initdata = {
  8695. {
  8696. @@ -63,6 +75,11 @@
  8697. .gpio = DB120_GPIO_LED_WLAN_2G,
  8698. .active_low = 1,
  8699. },
  8700. + {
  8701. + .name = "db120:green:usb",
  8702. + .gpio = DB120_GPIO_LED_USB,
  8703. + .active_low = 1,
  8704. + }
  8705. };
  8706. static struct gpio_keys_button db120_gpio_keys[] __initdata = {
  8707. @@ -76,60 +93,85 @@
  8708. },
  8709. };
  8710. -static struct spi_board_info db120_spi_info[] = {
  8711. - {
  8712. - .bus_num = 0,
  8713. - .chip_select = 0,
  8714. - .max_speed_hz = 25000000,
  8715. - .modalias = "s25sl064a",
  8716. - }
  8717. +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
  8718. + .mode = AR8327_PAD_MAC_RGMII,
  8719. + .txclk_delay_en = true,
  8720. + .rxclk_delay_en = true,
  8721. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  8722. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  8723. };
  8724. -static struct ath79_spi_platform_data db120_spi_data = {
  8725. - .bus_num = 0,
  8726. - .num_chipselect = 1,
  8727. +static struct ar8327_led_cfg db120_ar8327_led_cfg = {
  8728. + .led_ctrl0 = 0x00000000,
  8729. + .led_ctrl1 = 0xc737c737,
  8730. + .led_ctrl2 = 0x00000000,
  8731. + .led_ctrl3 = 0x00c30c00,
  8732. + .open_drain = true,
  8733. };
  8734. -#ifdef CONFIG_PCI
  8735. -static struct ath9k_platform_data db120_ath9k_data;
  8736. -
  8737. -static int db120_pci_plat_dev_init(struct pci_dev *dev)
  8738. -{
  8739. - switch (PCI_SLOT(dev->devfn)) {
  8740. - case 0:
  8741. - dev->dev.platform_data = &db120_ath9k_data;
  8742. - break;
  8743. - }
  8744. -
  8745. - return 0;
  8746. -}
  8747. -
  8748. -static void __init db120_pci_init(u8 *eeprom)
  8749. -{
  8750. - memcpy(db120_ath9k_data.eeprom_data, eeprom,
  8751. - sizeof(db120_ath9k_data.eeprom_data));
  8752. +static struct ar8327_platform_data db120_ar8327_data = {
  8753. + .pad0_cfg = &db120_ar8327_pad0_cfg,
  8754. + .port0_cfg = {
  8755. + .force_link = 1,
  8756. + .speed = AR8327_PORT_SPEED_1000,
  8757. + .duplex = 1,
  8758. + .txpause = 1,
  8759. + .rxpause = 1,
  8760. + },
  8761. + .led_cfg = &db120_ar8327_led_cfg,
  8762. +};
  8763. - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
  8764. - ath79_register_pci();
  8765. -}
  8766. -#else
  8767. -static inline void db120_pci_init(u8 *eeprom) {}
  8768. -#endif /* CONFIG_PCI */
  8769. +static struct mdio_board_info db120_mdio0_info[] = {
  8770. + {
  8771. + .bus_id = "ag71xx-mdio.0",
  8772. + .phy_addr = 0,
  8773. + .platform_data = &db120_ar8327_data,
  8774. + },
  8775. +};
  8776. static void __init db120_setup(void)
  8777. {
  8778. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  8779. + ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
  8780. + ath79_register_m25p80(NULL);
  8781. +
  8782. ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
  8783. db120_leds_gpio);
  8784. ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
  8785. ARRAY_SIZE(db120_gpio_keys),
  8786. db120_gpio_keys);
  8787. - ath79_register_spi(&db120_spi_data, db120_spi_info,
  8788. - ARRAY_SIZE(db120_spi_info));
  8789. ath79_register_usb();
  8790. - ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
  8791. - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
  8792. + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
  8793. + ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
  8794. +
  8795. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  8796. + AR934X_ETH_CFG_SW_ONLY_MODE);
  8797. +
  8798. + ath79_register_mdio(1, 0x0);
  8799. + ath79_register_mdio(0, 0x0);
  8800. +
  8801. + ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
  8802. +
  8803. + mdiobus_register_board_info(db120_mdio0_info,
  8804. + ARRAY_SIZE(db120_mdio0_info));
  8805. +
  8806. + /* GMAC0 is connected to an AR8327 switch */
  8807. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  8808. + ath79_eth0_data.phy_mask = BIT(0);
  8809. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  8810. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  8811. + ath79_register_eth(0);
  8812. +
  8813. + /* GMAC1 is connected to the internal switch */
  8814. + ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
  8815. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  8816. + ath79_eth1_data.speed = SPEED_1000;
  8817. + ath79_eth1_data.duplex = DUPLEX_FULL;
  8818. +
  8819. + ath79_register_eth(1);
  8820. +
  8821. + ath79_register_nfc();
  8822. }
  8823. MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
  8824. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dgl-5500-a1.c linux-4.1.43/arch/mips/ath79/mach-dgl-5500-a1.c
  8825. --- linux-4.1.43.orig/arch/mips/ath79/mach-dgl-5500-a1.c 1970-01-01 01:00:00.000000000 +0100
  8826. +++ linux-4.1.43/arch/mips/ath79/mach-dgl-5500-a1.c 2017-08-06 20:02:15.000000000 +0200
  8827. @@ -0,0 +1,150 @@
  8828. +/*
  8829. + * D-Link DGL-5500 board support
  8830. + *
  8831. + * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
  8832. + * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
  8833. + *
  8834. + * This program is free software; you can redistribute it and/or modify it
  8835. + * under the terms of the GNU General Public License version 2 as published
  8836. + * by the Free Software Foundation.
  8837. + */
  8838. +
  8839. +#include <linux/gpio.h>
  8840. +#include <linux/platform_device.h>
  8841. +#include <linux/ar8216_platform.h>
  8842. +
  8843. +#include <asm/mach-ath79/ar71xx_regs.h>
  8844. +
  8845. +#include "common.h"
  8846. +#include "pci.h"
  8847. +#include "dev-gpio-buttons.h"
  8848. +#include "dev-eth.h"
  8849. +#include "dev-leds-gpio.h"
  8850. +#include "dev-m25p80.h"
  8851. +#include "dev-usb.h"
  8852. +#include "dev-wmac.h"
  8853. +#include "machtypes.h"
  8854. +
  8855. +#define DGL_5500_A1_GPIO_LED_POWER_ORANGE 14
  8856. +#define DGL_5500_A1_GPIO_LED_POWER_GREEN 19
  8857. +#define DGL_5500_A1_GPIO_LED_PLANET_GREEN 22
  8858. +#define DGL_5500_A1_GPIO_LED_PLANET_ORANGE 23
  8859. +
  8860. +#define DGL_5500_A1_GPIO_BTN_WPS 16
  8861. +#define DGL_5500_A1_GPIO_BTN_RESET 17
  8862. +
  8863. +#define DGL_5500_A1_KEYS_POLL_INTERVAL 20 /* msecs */
  8864. +#define DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL \
  8865. + (3 * DGL_5500_A1_KEYS_POLL_INTERVAL)
  8866. +
  8867. +#define DGL_5500_A1_WMAC_CALDATA_OFFSET 0x1000
  8868. +
  8869. +#define DGL_5500_A1_LAN_MAC_OFFSET 0x04
  8870. +#define DGL_5500_A1_WAN_MAC_OFFSET 0x16
  8871. +
  8872. +static struct gpio_led dgl_5500_a1_leds_gpio[] __initdata = {
  8873. + {
  8874. + .name = "d-link:green:power",
  8875. + .gpio = DGL_5500_A1_GPIO_LED_POWER_GREEN,
  8876. + .active_low = 1,
  8877. + },
  8878. + {
  8879. + .name = "d-link:orange:power",
  8880. + .gpio = DGL_5500_A1_GPIO_LED_POWER_ORANGE,
  8881. + .active_low = 1,
  8882. + },
  8883. + {
  8884. + .name = "d-link:green:planet",
  8885. + .gpio = DGL_5500_A1_GPIO_LED_PLANET_GREEN,
  8886. + .active_low = 1,
  8887. + },
  8888. + {
  8889. + .name = "d-link:orange:planet",
  8890. + .gpio = DGL_5500_A1_GPIO_LED_PLANET_ORANGE,
  8891. + .active_low = 1,
  8892. + },
  8893. +};
  8894. +
  8895. +static struct gpio_keys_button dgl_5500_a1_gpio_keys[] __initdata = {
  8896. + {
  8897. + .desc = "Reset button",
  8898. + .type = EV_KEY,
  8899. + .code = KEY_RESTART,
  8900. + .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL,
  8901. + .gpio = DGL_5500_A1_GPIO_BTN_RESET,
  8902. + .active_low = 1,
  8903. + },
  8904. + {
  8905. + .desc = "WPS button",
  8906. + .type = EV_KEY,
  8907. + .code = KEY_WPS_BUTTON,
  8908. + .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL,
  8909. + .gpio = DGL_5500_A1_GPIO_BTN_WPS,
  8910. + .active_low = 1,
  8911. + },
  8912. +};
  8913. +
  8914. +static struct ar8327_pad_cfg dgl_5500_a1_ar8327_pad0_cfg = {
  8915. + /* Use the SGMII interface for the GMAC0 of the AR8327 switch */
  8916. + .mode = AR8327_PAD_MAC_SGMII,
  8917. + .sgmii_delay_en = true,
  8918. +};
  8919. +
  8920. +static struct ar8327_platform_data dgl_5500_a1_ar8327_data = {
  8921. + .pad0_cfg = &dgl_5500_a1_ar8327_pad0_cfg,
  8922. + .port0_cfg = {
  8923. + .force_link = 1,
  8924. + .speed = AR8327_PORT_SPEED_1000,
  8925. + .duplex = 1,
  8926. + .txpause = 1,
  8927. + .rxpause = 1,
  8928. + },
  8929. +};
  8930. +
  8931. +static struct mdio_board_info dgl_5500_a1_mdio0_info[] = {
  8932. + {
  8933. + .bus_id = "ag71xx-mdio.0",
  8934. + .phy_addr = 0,
  8935. + .platform_data = &dgl_5500_a1_ar8327_data,
  8936. + },
  8937. +};
  8938. +
  8939. +static void __init dgl_5500_a1_setup(void)
  8940. +{
  8941. + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
  8942. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  8943. + u8 lan_mac[ETH_ALEN];
  8944. +
  8945. + ath79_parse_ascii_mac(mac + DGL_5500_A1_LAN_MAC_OFFSET, lan_mac);
  8946. +
  8947. + ath79_register_m25p80(NULL);
  8948. +
  8949. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dgl_5500_a1_leds_gpio),
  8950. + dgl_5500_a1_leds_gpio);
  8951. + ath79_register_gpio_keys_polled(-1, DGL_5500_A1_KEYS_POLL_INTERVAL,
  8952. + ARRAY_SIZE(dgl_5500_a1_gpio_keys),
  8953. + dgl_5500_a1_gpio_keys);
  8954. +
  8955. + ath79_register_wmac(art + DGL_5500_A1_WMAC_CALDATA_OFFSET, lan_mac);
  8956. +
  8957. + ath79_register_mdio(0, 0x0);
  8958. + mdiobus_register_board_info(dgl_5500_a1_mdio0_info,
  8959. + ARRAY_SIZE(dgl_5500_a1_mdio0_info));
  8960. +
  8961. + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
  8962. +
  8963. + /* GMAC1 is connected to an AR8327N switch via the SMGII interface */
  8964. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  8965. + ath79_eth1_data.phy_mask = BIT(0);
  8966. + ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev;
  8967. +
  8968. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  8969. +
  8970. + ath79_register_eth(1);
  8971. +
  8972. + ath79_register_usb();
  8973. + ath79_register_pci();
  8974. +}
  8975. +
  8976. +MIPS_MACHINE(ATH79_MACH_DGL_5500_A1, "DGL-5500-A1", "D-Link DGL-5500 rev. A1",
  8977. + dgl_5500_a1_setup);
  8978. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dhp-1565-a1.c linux-4.1.43/arch/mips/ath79/mach-dhp-1565-a1.c
  8979. --- linux-4.1.43.orig/arch/mips/ath79/mach-dhp-1565-a1.c 1970-01-01 01:00:00.000000000 +0100
  8980. +++ linux-4.1.43/arch/mips/ath79/mach-dhp-1565-a1.c 2017-08-06 20:02:15.000000000 +0200
  8981. @@ -0,0 +1,170 @@
  8982. +/*
  8983. + * D-Link DHP-1565 rev. A1 board support
  8984. + *
  8985. + * Copyright (C) 2014 Jacek Kikiewicz
  8986. + *
  8987. + * This program is free software; you can redistribute it and/or modify it
  8988. + * under the terms of the GNU General Public License version 2 as published
  8989. + * by the Free Software Foundation.
  8990. + */
  8991. +
  8992. +#include <linux/pci.h>
  8993. +#include <linux/phy.h>
  8994. +#include <linux/gpio.h>
  8995. +#include <linux/platform_device.h>
  8996. +#include <linux/ath9k_platform.h>
  8997. +#include <linux/ar8216_platform.h>
  8998. +
  8999. +#include <asm/mach-ath79/ar71xx_regs.h>
  9000. +
  9001. +#include "common.h"
  9002. +#include "dev-ap9x-pci.h"
  9003. +#include "dev-eth.h"
  9004. +#include "dev-gpio-buttons.h"
  9005. +#include "dev-leds-gpio.h"
  9006. +#include "dev-m25p80.h"
  9007. +#include "dev-spi.h"
  9008. +#include "dev-usb.h"
  9009. +#include "dev-wmac.h"
  9010. +#include "machtypes.h"
  9011. +
  9012. +#define DHP1565A1_GPIO_LED_BLUE_USB 11
  9013. +#define DHP1565A1_GPIO_LED_AMBER_POWER 14
  9014. +#define DHP1565A1_GPIO_LED_BLUE_POWER 22
  9015. +#define DHP1565A1_GPIO_LED_BLUE_WPS 15
  9016. +#define DHP1565A1_GPIO_LED_AMBER_PLANET 19
  9017. +#define DHP1565A1_GPIO_LED_BLUE_PLANET 18
  9018. +#define DHP1565A1_GPIO_LED_WLAN_2G 13
  9019. +
  9020. +#define DHP1565A1_GPIO_WAN_LED_ENABLE 20
  9021. +
  9022. +#define DHP1565A1_GPIO_BTN_RESET 17
  9023. +#define DHP1565A1_GPIO_BTN_WPS 16
  9024. +
  9025. +#define DHP1565A1_KEYS_POLL_INTERVAL 20 /* msecs */
  9026. +#define DHP1565A1_KEYS_DEBOUNCE_INTERVAL (3 * DHP1565A1_KEYS_POLL_INTERVAL)
  9027. +
  9028. +#define DHP1565A1_MAC0_OFFSET 0xFFA0
  9029. +#define DHP1565A1_MAC1_OFFSET 0xFFB4
  9030. +#define DHP1565A1_WMAC0_OFFSET 0x5
  9031. +#define DHP1565A1_WMAC_CALDATA_OFFSET 0x1000
  9032. +#define DHP1565A1_PCIE_CALDATA_OFFSET 0x5000
  9033. +
  9034. +static struct gpio_led dhp1565a1_leds_gpio[] __initdata = {
  9035. + {
  9036. + .name = "d-link:amber:power",
  9037. + .gpio = DHP1565A1_GPIO_LED_AMBER_POWER,
  9038. + .active_low = 1,
  9039. + },
  9040. + {
  9041. + .name = "d-link:green:power",
  9042. + .gpio = DHP1565A1_GPIO_LED_BLUE_POWER,
  9043. + .active_low = 1,
  9044. + },
  9045. + {
  9046. + .name = "d-link:amber:planet",
  9047. + .gpio = DHP1565A1_GPIO_LED_AMBER_PLANET,
  9048. + .active_low = 1,
  9049. + },
  9050. + {
  9051. + .name = "d-link:green:planet",
  9052. + .gpio = DHP1565A1_GPIO_LED_BLUE_PLANET,
  9053. + .active_low = 1,
  9054. + },
  9055. +};
  9056. +
  9057. +static struct gpio_keys_button dhp1565a1_gpio_keys[] __initdata = {
  9058. + {
  9059. + .desc = "Soft reset",
  9060. + .type = EV_KEY,
  9061. + .code = KEY_RESTART,
  9062. + .debounce_interval = DHP1565A1_KEYS_DEBOUNCE_INTERVAL,
  9063. + .gpio = DHP1565A1_GPIO_BTN_RESET,
  9064. + .active_low = 1,
  9065. + },
  9066. + {
  9067. + .desc = "WPS button",
  9068. + .type = EV_KEY,
  9069. + .code = KEY_WPS_BUTTON,
  9070. + .debounce_interval = DHP1565A1_KEYS_DEBOUNCE_INTERVAL,
  9071. + .gpio = DHP1565A1_GPIO_BTN_WPS,
  9072. + .active_low = 1,
  9073. + },
  9074. +};
  9075. +
  9076. +static struct ar8327_pad_cfg dhp1565a1_ar8327_pad0_cfg = {
  9077. + .mode = AR8327_PAD_MAC_RGMII,
  9078. + .txclk_delay_en = true,
  9079. + .rxclk_delay_en = true,
  9080. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  9081. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  9082. +};
  9083. +
  9084. +static struct ar8327_platform_data dhp1565a1_ar8327_data = {
  9085. + .pad0_cfg = &dhp1565a1_ar8327_pad0_cfg,
  9086. + .port0_cfg = {
  9087. + .force_link = 1,
  9088. + .speed = AR8327_PORT_SPEED_1000,
  9089. + .duplex = 1,
  9090. + .txpause = 1,
  9091. + .rxpause = 1,
  9092. + },
  9093. +};
  9094. +
  9095. +static struct mdio_board_info dhp1565a1_mdio0_info[] = {
  9096. + {
  9097. + .bus_id = "ag71xx-mdio.0",
  9098. + .phy_addr = 0,
  9099. + .platform_data = &dhp1565a1_ar8327_data,
  9100. + },
  9101. +};
  9102. +
  9103. +static void __init dhp1565a1_generic_setup(void)
  9104. +{
  9105. + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
  9106. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  9107. + u8 mac0[ETH_ALEN], mac1[ETH_ALEN];
  9108. + u8 wmac0[ETH_ALEN];
  9109. +
  9110. + ath79_parse_ascii_mac(mac + DHP1565A1_MAC0_OFFSET, mac0);
  9111. + ath79_parse_ascii_mac(mac + DHP1565A1_MAC1_OFFSET, mac1);
  9112. +
  9113. + ath79_register_m25p80(NULL);
  9114. +
  9115. + ath79_register_gpio_keys_polled(-1, DHP1565A1_KEYS_POLL_INTERVAL,
  9116. + ARRAY_SIZE(dhp1565a1_gpio_keys),
  9117. + dhp1565a1_gpio_keys);
  9118. +
  9119. + ath79_init_mac(wmac0, mac0, 0);
  9120. + ath79_register_wmac(art + DHP1565A1_WMAC_CALDATA_OFFSET, wmac0);
  9121. +
  9122. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  9123. +
  9124. + mdiobus_register_board_info(dhp1565a1_mdio0_info,
  9125. + ARRAY_SIZE(dhp1565a1_mdio0_info));
  9126. +
  9127. + ath79_register_mdio(0, 0x0);
  9128. +
  9129. + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 1);
  9130. +
  9131. + /* GMAC0 is connected to an AR8327N switch */
  9132. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  9133. + ath79_eth0_data.phy_mask = BIT(0);
  9134. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  9135. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  9136. + ath79_register_eth(0);
  9137. +
  9138. + ath79_register_usb();
  9139. +}
  9140. +
  9141. +static void __init dhp1565a1_setup(void)
  9142. +{
  9143. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dhp1565a1_leds_gpio),
  9144. + dhp1565a1_leds_gpio);
  9145. +
  9146. + dhp1565a1_generic_setup();
  9147. +}
  9148. +
  9149. +MIPS_MACHINE(ATH79_MACH_DHP_1565_A1, "DHP-1565-A1",
  9150. + "D-Link DHP-1565 rev. A1",
  9151. + dhp1565a1_setup);
  9152. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dir-505-a1.c linux-4.1.43/arch/mips/ath79/mach-dir-505-a1.c
  9153. --- linux-4.1.43.orig/arch/mips/ath79/mach-dir-505-a1.c 1970-01-01 01:00:00.000000000 +0100
  9154. +++ linux-4.1.43/arch/mips/ath79/mach-dir-505-a1.c 2017-08-06 20:02:15.000000000 +0200
  9155. @@ -0,0 +1,116 @@
  9156. +/*
  9157. + * DLink DIR-505 A1 board support
  9158. + *
  9159. + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  9160. + *
  9161. + * This program is free software; you can redistribute it and/or modify it
  9162. + * under the terms of the GNU General Public License version 2 as published
  9163. + * by the Free Software Foundation.
  9164. + */
  9165. +
  9166. +#include <linux/gpio.h>
  9167. +
  9168. +#include <asm/mach-ath79/ath79.h>
  9169. +#include <asm/mach-ath79/ar71xx_regs.h>
  9170. +
  9171. +#include "common.h"
  9172. +#include "dev-eth.h"
  9173. +#include "dev-gpio-buttons.h"
  9174. +#include "dev-leds-gpio.h"
  9175. +#include "dev-m25p80.h"
  9176. +#include "dev-wmac.h"
  9177. +#include "dev-usb.h"
  9178. +#include "machtypes.h"
  9179. +
  9180. +#define DIR_505A1_GPIO_BTN_WPS 11 /* verify */
  9181. +#define DIR_505A1_GPIO_BTN_RESET 12 /* verify */
  9182. +
  9183. +#define DIR_505A1_GPIO_LED_RED 26 /* unused, fyi */
  9184. +#define DIR_505A1_GPIO_LED_GREEN 27
  9185. +
  9186. +#define DIR_505A1_GPIO_WAN_LED_ENABLE 1
  9187. +
  9188. +#define DIR_505A1_KEYS_POLL_INTERVAL 20 /* msecs */
  9189. +#define DIR_505A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_505A1_KEYS_POLL_INTERVAL)
  9190. +
  9191. +#define DIR_505A1_ART_ADDRESS 0x1f010000
  9192. +#define DIR_505A1_CALDATA_OFFSET 0x1000
  9193. +
  9194. +#define DIR_505A1_MAC_PART_ADDRESS 0x1f020000
  9195. +#define DIR_505A1_LAN_MAC_OFFSET 0x04
  9196. +#define DIR_505A1_WAN_MAC_OFFSET 0x16
  9197. +
  9198. +static struct gpio_led dir_505_a1_leds_gpio[] __initdata = {
  9199. + {
  9200. + .name = "d-link:green:power",
  9201. + .gpio = DIR_505A1_GPIO_LED_GREEN,
  9202. + .active_low = 1,
  9203. + }, {
  9204. + .name = "d-link:red:status",
  9205. + .gpio = DIR_505A1_GPIO_LED_RED,
  9206. + .active_low = 1,
  9207. + },
  9208. +};
  9209. +
  9210. +static struct gpio_keys_button dir_505_a1_gpio_keys[] __initdata = {
  9211. + {
  9212. + .desc = "Reset button",
  9213. + .type = EV_KEY,
  9214. + .code = KEY_RESTART,
  9215. + .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL,
  9216. + .gpio = DIR_505A1_GPIO_BTN_RESET,
  9217. + .active_low = 0,
  9218. + }, {
  9219. + .desc = "WPS button",
  9220. + .type = EV_KEY,
  9221. + .code = KEY_WPS_BUTTON,
  9222. + .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL,
  9223. + .gpio = DIR_505A1_GPIO_BTN_WPS,
  9224. + .active_low = 1,
  9225. + }
  9226. +};
  9227. +
  9228. +static void __init dir_505_a1_setup(void)
  9229. +{
  9230. + u8 *art = (u8 *) KSEG1ADDR(DIR_505A1_ART_ADDRESS);
  9231. + u8 *mac = (u8 *) KSEG1ADDR(DIR_505A1_MAC_PART_ADDRESS);
  9232. + u8 lan_mac[ETH_ALEN];
  9233. + u8 wan_mac[ETH_ALEN];
  9234. +
  9235. + ath79_setup_ar933x_phy4_switch(false, false);
  9236. +
  9237. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  9238. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  9239. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  9240. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  9241. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  9242. +
  9243. + gpio_request_one(DIR_505A1_GPIO_WAN_LED_ENABLE,
  9244. + GPIOF_OUT_INIT_LOW, "WAN LED enable");
  9245. +
  9246. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_505_a1_leds_gpio),
  9247. + dir_505_a1_leds_gpio);
  9248. +
  9249. + ath79_register_gpio_keys_polled(1, DIR_505A1_KEYS_POLL_INTERVAL,
  9250. + ARRAY_SIZE(dir_505_a1_gpio_keys),
  9251. + dir_505_a1_gpio_keys);
  9252. +
  9253. + ath79_register_m25p80(NULL);
  9254. +
  9255. + ath79_register_usb();
  9256. +
  9257. + ath79_parse_ascii_mac(mac + DIR_505A1_LAN_MAC_OFFSET, lan_mac);
  9258. + ath79_parse_ascii_mac(mac + DIR_505A1_WAN_MAC_OFFSET, wan_mac);
  9259. +
  9260. + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
  9261. + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
  9262. +
  9263. + ath79_register_mdio(0, 0x0);
  9264. + ath79_register_eth(1);
  9265. + ath79_register_eth(0);
  9266. +
  9267. + ath79_register_wmac(art + DIR_505A1_CALDATA_OFFSET, lan_mac);
  9268. +}
  9269. +
  9270. +MIPS_MACHINE(ATH79_MACH_DIR_505_A1, "DIR-505-A1",
  9271. + "D-Link DIR-505 rev. A1", dir_505_a1_setup);
  9272. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dir-600-a1.c linux-4.1.43/arch/mips/ath79/mach-dir-600-a1.c
  9273. --- linux-4.1.43.orig/arch/mips/ath79/mach-dir-600-a1.c 1970-01-01 01:00:00.000000000 +0100
  9274. +++ linux-4.1.43/arch/mips/ath79/mach-dir-600-a1.c 2017-08-06 20:02:15.000000000 +0200
  9275. @@ -0,0 +1,159 @@
  9276. +/*
  9277. + * D-Link DIR-600 rev. A1 board support
  9278. + *
  9279. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  9280. + * Copyright (C) 2012 Vadim Girlin <vadimgirlin@gmail.com>
  9281. + *
  9282. + * This program is free software; you can redistribute it and/or modify it
  9283. + * under the terms of the GNU General Public License version 2 as published
  9284. + * by the Free Software Foundation.
  9285. + */
  9286. +
  9287. +#include <asm/mach-ath79/ath79.h>
  9288. +#include <asm/mach-ath79/ar71xx_regs.h>
  9289. +
  9290. +#include "common.h"
  9291. +#include "dev-ap9x-pci.h"
  9292. +#include "dev-eth.h"
  9293. +#include "dev-gpio-buttons.h"
  9294. +#include "dev-leds-gpio.h"
  9295. +#include "dev-m25p80.h"
  9296. +#include "machtypes.h"
  9297. +#include "nvram.h"
  9298. +
  9299. +#define DIR_600_A1_GPIO_LED_WPS 0
  9300. +#define DIR_600_A1_GPIO_LED_POWER_AMBER 1
  9301. +#define DIR_600_A1_GPIO_LED_POWER_GREEN 6
  9302. +#define DIR_600_A1_GPIO_LED_LAN1 13
  9303. +#define DIR_600_A1_GPIO_LED_LAN2 14
  9304. +#define DIR_600_A1_GPIO_LED_LAN3 15
  9305. +#define DIR_600_A1_GPIO_LED_LAN4 16
  9306. +#define DIR_600_A1_GPIO_LED_WAN_AMBER 7
  9307. +#define DIR_600_A1_GPIO_LED_WAN_GREEN 17
  9308. +
  9309. +#define DIR_600_A1_GPIO_BTN_RESET 8
  9310. +#define DIR_600_A1_GPIO_BTN_WPS 12
  9311. +
  9312. +#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */
  9313. +#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL)
  9314. +
  9315. +#define DIR_600_A1_NVRAM_ADDR 0x1f030000
  9316. +#define DIR_600_A1_NVRAM_SIZE 0x10000
  9317. +
  9318. +static struct gpio_led dir_600_a1_leds_gpio[] __initdata = {
  9319. + {
  9320. + .name = "d-link:green:power",
  9321. + .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN,
  9322. + }, {
  9323. + .name = "d-link:amber:power",
  9324. + .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER,
  9325. + }, {
  9326. + .name = "d-link:amber:wan",
  9327. + .gpio = DIR_600_A1_GPIO_LED_WAN_AMBER,
  9328. + }, {
  9329. + .name = "d-link:green:wan",
  9330. + .gpio = DIR_600_A1_GPIO_LED_WAN_GREEN,
  9331. + .active_low = 1,
  9332. + }, {
  9333. + .name = "d-link:green:lan1",
  9334. + .gpio = DIR_600_A1_GPIO_LED_LAN1,
  9335. + .active_low = 1,
  9336. + }, {
  9337. + .name = "d-link:green:lan2",
  9338. + .gpio = DIR_600_A1_GPIO_LED_LAN2,
  9339. + .active_low = 1,
  9340. + }, {
  9341. + .name = "d-link:green:lan3",
  9342. + .gpio = DIR_600_A1_GPIO_LED_LAN3,
  9343. + .active_low = 1,
  9344. + }, {
  9345. + .name = "d-link:green:lan4",
  9346. + .gpio = DIR_600_A1_GPIO_LED_LAN4,
  9347. + .active_low = 1,
  9348. + }, {
  9349. + .name = "d-link:blue:wps",
  9350. + .gpio = DIR_600_A1_GPIO_LED_WPS,
  9351. + .active_low = 1,
  9352. + }
  9353. +};
  9354. +
  9355. +static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = {
  9356. + {
  9357. + .desc = "reset",
  9358. + .type = EV_KEY,
  9359. + .code = KEY_RESTART,
  9360. + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
  9361. + .gpio = DIR_600_A1_GPIO_BTN_RESET,
  9362. + .active_low = 1,
  9363. + }, {
  9364. + .desc = "wps",
  9365. + .type = EV_KEY,
  9366. + .code = KEY_WPS_BUTTON,
  9367. + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
  9368. + .gpio = DIR_600_A1_GPIO_BTN_WPS,
  9369. + .active_low = 1,
  9370. + }
  9371. +};
  9372. +
  9373. +static void __init dir_600_a1_setup(void)
  9374. +{
  9375. + const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR);
  9376. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  9377. + u8 mac_buff[6];
  9378. + u8 *mac = NULL;
  9379. +
  9380. + if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE,
  9381. + "lan_mac=", mac_buff) == 0) {
  9382. + ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0);
  9383. + ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1);
  9384. + mac = mac_buff;
  9385. + }
  9386. +
  9387. + ath79_register_m25p80(NULL);
  9388. +
  9389. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  9390. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  9391. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  9392. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  9393. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  9394. +
  9395. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio),
  9396. + dir_600_a1_leds_gpio);
  9397. +
  9398. + ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL,
  9399. + ARRAY_SIZE(dir_600_a1_gpio_keys),
  9400. + dir_600_a1_gpio_keys);
  9401. +
  9402. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  9403. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  9404. +
  9405. + ath79_register_mdio(0, 0x0);
  9406. +
  9407. + /* LAN ports */
  9408. + ath79_register_eth(1);
  9409. +
  9410. + /* WAN port */
  9411. + ath79_register_eth(0);
  9412. +
  9413. + ap91_pci_init(ee, mac);
  9414. +}
  9415. +
  9416. +MIPS_MACHINE(ATH79_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1",
  9417. + dir_600_a1_setup);
  9418. +
  9419. +static void __init dir_615_e1_setup(void)
  9420. +{
  9421. + dir_600_a1_setup();
  9422. +}
  9423. +
  9424. +MIPS_MACHINE(ATH79_MACH_DIR_615_E1, "DIR-615-E1", "D-Link DIR-615 rev. E1",
  9425. + dir_615_e1_setup);
  9426. +
  9427. +static void __init dir_615_e4_setup(void)
  9428. +{
  9429. + dir_600_a1_setup();
  9430. + ap9x_pci_setup_wmac_led_pin(0, 1);
  9431. +}
  9432. +
  9433. +MIPS_MACHINE(ATH79_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4",
  9434. + dir_615_e4_setup);
  9435. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dir-615-c1.c linux-4.1.43/arch/mips/ath79/mach-dir-615-c1.c
  9436. --- linux-4.1.43.orig/arch/mips/ath79/mach-dir-615-c1.c 1970-01-01 01:00:00.000000000 +0100
  9437. +++ linux-4.1.43/arch/mips/ath79/mach-dir-615-c1.c 2017-08-06 20:02:15.000000000 +0200
  9438. @@ -0,0 +1,135 @@
  9439. +/*
  9440. + * D-Link DIR-615 rev C1 board support
  9441. + *
  9442. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  9443. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  9444. + *
  9445. + * This program is free software; you can redistribute it and/or modify it
  9446. + * under the terms of the GNU General Public License version 2 as published
  9447. + * by the Free Software Foundation.
  9448. + */
  9449. +
  9450. +#include <asm/mach-ath79/ath79.h>
  9451. +
  9452. +#include "dev-eth.h"
  9453. +#include "dev-gpio-buttons.h"
  9454. +#include "dev-leds-gpio.h"
  9455. +#include "dev-m25p80.h"
  9456. +#include "dev-wmac.h"
  9457. +#include "machtypes.h"
  9458. +#include "nvram.h"
  9459. +
  9460. +#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */
  9461. +#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */
  9462. +#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */
  9463. +#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */
  9464. +#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */
  9465. +#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */
  9466. +#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */
  9467. +
  9468. +/* buttons may need refinement */
  9469. +
  9470. +#define DIR_615C1_GPIO_BTN_WPS 12
  9471. +#define DIR_615C1_GPIO_BTN_RESET 21
  9472. +
  9473. +#define DIR_615C1_KEYS_POLL_INTERVAL 20 /* msecs */
  9474. +#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL)
  9475. +
  9476. +#define DIR_615C1_CONFIG_ADDR 0x1f020000
  9477. +#define DIR_615C1_CONFIG_SIZE 0x10000
  9478. +
  9479. +#define DIR_615C1_WLAN_MAC_ADDR 0x1f3fffb4
  9480. +
  9481. +static struct gpio_led dir_615c1_leds_gpio[] __initdata = {
  9482. + {
  9483. + .name = "d-link:orange:status",
  9484. + .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS,
  9485. + .active_low = 1,
  9486. + }, {
  9487. + .name = "d-link:blue:wps",
  9488. + .gpio = DIR_615C1_GPIO_LED_BLUE_WPS,
  9489. + .active_low = 1,
  9490. + }, {
  9491. + .name = "d-link:green:wan",
  9492. + .gpio = DIR_615C1_GPIO_LED_GREEN_WAN,
  9493. + .active_low = 1,
  9494. + }, {
  9495. + .name = "d-link:green:wancpu",
  9496. + .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU,
  9497. + .active_low = 1,
  9498. + }, {
  9499. + .name = "d-link:green:wlan",
  9500. + .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN,
  9501. + .active_low = 1,
  9502. + }, {
  9503. + .name = "d-link:green:status",
  9504. + .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS,
  9505. + .active_low = 1,
  9506. + }, {
  9507. + .name = "d-link:orange:wan",
  9508. + .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN,
  9509. + .active_low = 1,
  9510. + }
  9511. +
  9512. +};
  9513. +
  9514. +static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = {
  9515. + {
  9516. + .desc = "reset",
  9517. + .type = EV_KEY,
  9518. + .code = KEY_RESTART,
  9519. + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL,
  9520. + .gpio = DIR_615C1_GPIO_BTN_RESET,
  9521. + }, {
  9522. + .desc = "wps",
  9523. + .type = EV_KEY,
  9524. + .code = KEY_WPS_BUTTON,
  9525. + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL,
  9526. + .gpio = DIR_615C1_GPIO_BTN_WPS,
  9527. + }
  9528. +};
  9529. +
  9530. +#define DIR_615C1_LAN_PHYMASK BIT(0)
  9531. +#define DIR_615C1_WAN_PHYMASK BIT(4)
  9532. +#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \
  9533. + DIR_615C1_WAN_PHYMASK))
  9534. +
  9535. +static void __init dir_615c1_setup(void)
  9536. +{
  9537. + const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR);
  9538. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  9539. + u8 mac[ETH_ALEN], wlan_mac[ETH_ALEN];
  9540. +
  9541. + if (ath79_nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE,
  9542. + "lan_mac=", mac) == 0) {
  9543. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  9544. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  9545. + }
  9546. +
  9547. + ath79_parse_ascii_mac((char *) KSEG1ADDR(DIR_615C1_WLAN_MAC_ADDR), wlan_mac);
  9548. +
  9549. + ath79_register_mdio(0, DIR_615C1_MDIO_MASK);
  9550. +
  9551. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  9552. + ath79_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK;
  9553. +
  9554. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  9555. + ath79_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK;
  9556. +
  9557. + ath79_register_eth(0);
  9558. + ath79_register_eth(1);
  9559. +
  9560. + ath79_register_m25p80(NULL);
  9561. +
  9562. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio),
  9563. + dir_615c1_leds_gpio);
  9564. +
  9565. + ath79_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL,
  9566. + ARRAY_SIZE(dir_615c1_gpio_keys),
  9567. + dir_615c1_gpio_keys);
  9568. +
  9569. + ath79_register_wmac(eeprom, wlan_mac);
  9570. +}
  9571. +
  9572. +MIPS_MACHINE(ATH79_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1",
  9573. + dir_615c1_setup);
  9574. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dir-615-i1.c linux-4.1.43/arch/mips/ath79/mach-dir-615-i1.c
  9575. --- linux-4.1.43.orig/arch/mips/ath79/mach-dir-615-i1.c 1970-01-01 01:00:00.000000000 +0100
  9576. +++ linux-4.1.43/arch/mips/ath79/mach-dir-615-i1.c 2017-08-06 20:02:15.000000000 +0200
  9577. @@ -0,0 +1,133 @@
  9578. +/*
  9579. + * D-Link DIR-615 rev. I1 board support
  9580. + * Copyright (C) 2013-2015 Jaehoon You <teslamint@gmail.com>
  9581. + *
  9582. + * based on the DIR-600 rev. A1 board support code
  9583. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  9584. + * Copyright (C) 2012 Vadim Girlin <vadimgirlin@gmail.com>
  9585. + *
  9586. + * based on the TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 board support code
  9587. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  9588. + *
  9589. + * This program is free software; you can redistribute it and/or modify it
  9590. + * under the terms of the GNU General Public License version 2 as published
  9591. + * by the Free Software Foundation.
  9592. + */
  9593. +
  9594. +#include <linux/platform_device.h>
  9595. +
  9596. +#include <asm/mach-ath79/ath79.h>
  9597. +#include <asm/mach-ath79/ar71xx_regs.h>
  9598. +
  9599. +#include "common.h"
  9600. +#include "dev-eth.h"
  9601. +#include "dev-gpio-buttons.h"
  9602. +#include "dev-leds-gpio.h"
  9603. +#include "dev-m25p80.h"
  9604. +#include "dev-wmac.h"
  9605. +#include "machtypes.h"
  9606. +
  9607. +#define DIR_615_I1_GPIO_LED_WPS 15
  9608. +#define DIR_615_I1_GPIO_LED_POWER_AMBER 14
  9609. +#define DIR_615_I1_GPIO_LED_POWER_GREEN 4
  9610. +#define DIR_615_I1_GPIO_LED_WAN_AMBER 22
  9611. +#define DIR_615_I1_GPIO_LED_WAN_GREEN 12
  9612. +#define DIR_615_I1_GPIO_LED_WLAN_GREEN 13
  9613. +
  9614. +#define DIR_615_I1_GPIO_BTN_WPS 16
  9615. +#define DIR_615_I1_GPIO_BTN_RESET 17
  9616. +
  9617. +#define DIR_615_I1_KEYS_POLL_INTERVAL 20 /* msecs */
  9618. +#define DIR_615_I1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_I1_KEYS_POLL_INTERVAL)
  9619. +
  9620. +#define DIR_615_I1_LAN_PHYMASK BIT(0)
  9621. +#define DIR_615_I1_WAN_PHYMASK BIT(4)
  9622. +#define DIR_615_I1_WLAN_MAC_ADDR 0x1fffffb4
  9623. +
  9624. +static struct gpio_led dir_615_i1_leds_gpio[] __initdata = {
  9625. + {
  9626. + .name = "d-link:green:power",
  9627. + .gpio = DIR_615_I1_GPIO_LED_POWER_GREEN,
  9628. + }, {
  9629. + .name = "d-link:amber:power",
  9630. + .gpio = DIR_615_I1_GPIO_LED_POWER_AMBER,
  9631. + }, {
  9632. + .name = "d-link:amber:wan",
  9633. + .gpio = DIR_615_I1_GPIO_LED_WAN_AMBER,
  9634. + }, {
  9635. + .name = "d-link:green:wan",
  9636. + .gpio = DIR_615_I1_GPIO_LED_WAN_GREEN,
  9637. + .active_low = 1,
  9638. + }, {
  9639. + .name = "d-link:green:wlan",
  9640. + .gpio = DIR_615_I1_GPIO_LED_WLAN_GREEN,
  9641. + .active_low = 1,
  9642. + }, {
  9643. + .name = "d-link:blue:wps",
  9644. + .gpio = DIR_615_I1_GPIO_LED_WPS,
  9645. + .active_low = 1,
  9646. + }
  9647. +};
  9648. +
  9649. +static struct gpio_keys_button dir_615_i1_gpio_keys[] __initdata = {
  9650. + {
  9651. + .desc = "reset",
  9652. + .type = EV_KEY,
  9653. + .code = KEY_RESTART,
  9654. + .debounce_interval = DIR_615_I1_KEYS_DEBOUNCE_INTERVAL,
  9655. + .gpio = DIR_615_I1_GPIO_BTN_RESET,
  9656. + .active_low = 1,
  9657. + }, {
  9658. + .desc = "wps",
  9659. + .type = EV_KEY,
  9660. + .code = KEY_WPS_BUTTON,
  9661. + .debounce_interval = DIR_615_I1_KEYS_DEBOUNCE_INTERVAL,
  9662. + .gpio = DIR_615_I1_GPIO_BTN_WPS,
  9663. + .active_low = 1,
  9664. + }
  9665. +};
  9666. +
  9667. +static void __init dir_615_i1_setup(void)
  9668. +{
  9669. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  9670. + u8 mac[ETH_ALEN];
  9671. +
  9672. + ath79_register_mdio(0, 0x0);
  9673. + ath79_register_mdio(1, ~(DIR_615_I1_WAN_PHYMASK));
  9674. +
  9675. + ath79_parse_ascii_mac((char *) KSEG1ADDR(DIR_615_I1_WLAN_MAC_ADDR), mac);
  9676. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  9677. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  9678. +
  9679. + /* GMAC0 is connected to the PHY0 of the internal switch */
  9680. + ath79_switch_data.phy4_mii_en = 1;
  9681. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  9682. + ath79_eth0_data.phy_mask = DIR_615_I1_WAN_PHYMASK;
  9683. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  9684. +
  9685. + /* GMAC1 is connected to the internal switch */
  9686. + ath79_eth1_data.phy_mask = DIR_615_I1_LAN_PHYMASK;
  9687. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  9688. +
  9689. + ath79_register_eth(0);
  9690. + ath79_register_eth(1);
  9691. +
  9692. + ath79_register_m25p80(NULL);
  9693. +
  9694. + /* Disable JTAG, enabling GPIOs 0-3 */
  9695. + /* Configure OBS4 line, for GPIO 4*/
  9696. + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
  9697. + AR934X_GPIO_FUNC_CLK_OBS4_EN);
  9698. +
  9699. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615_i1_leds_gpio),
  9700. + dir_615_i1_leds_gpio);
  9701. +
  9702. + ath79_register_gpio_keys_polled(-1, DIR_615_I1_KEYS_POLL_INTERVAL,
  9703. + ARRAY_SIZE(dir_615_i1_gpio_keys),
  9704. + dir_615_i1_gpio_keys);
  9705. +
  9706. + ath79_register_wmac(eeprom, mac);
  9707. +}
  9708. +
  9709. +MIPS_MACHINE(ATH79_MACH_DIR_615_I1, "DIR-615-I1", "D-Link DIR-615 rev. I1",
  9710. + dir_615_i1_setup);
  9711. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dir-825-b1.c linux-4.1.43/arch/mips/ath79/mach-dir-825-b1.c
  9712. --- linux-4.1.43.orig/arch/mips/ath79/mach-dir-825-b1.c 1970-01-01 01:00:00.000000000 +0100
  9713. +++ linux-4.1.43/arch/mips/ath79/mach-dir-825-b1.c 2017-08-06 20:02:15.000000000 +0200
  9714. @@ -0,0 +1,191 @@
  9715. +/*
  9716. + * D-Link DIR-825 rev. B1 board support
  9717. + *
  9718. + * Copyright (C) 2009-2011 Lukas Kuna, Evkanet, s.r.o.
  9719. + *
  9720. + * based on mach-wndr3700.c
  9721. + *
  9722. + * This program is free software; you can redistribute it and/or modify it
  9723. + * under the terms of the GNU General Public License version 2 as published
  9724. + * by the Free Software Foundation.
  9725. + */
  9726. +
  9727. +#include <linux/platform_device.h>
  9728. +#include <linux/delay.h>
  9729. +#include <linux/rtl8366.h>
  9730. +
  9731. +#include <asm/mach-ath79/ath79.h>
  9732. +
  9733. +#include "dev-eth.h"
  9734. +#include "dev-ap9x-pci.h"
  9735. +#include "dev-gpio-buttons.h"
  9736. +#include "dev-leds-gpio.h"
  9737. +#include "dev-m25p80.h"
  9738. +#include "dev-usb.h"
  9739. +#include "machtypes.h"
  9740. +
  9741. +#define DIR825B1_GPIO_LED_BLUE_USB 0
  9742. +#define DIR825B1_GPIO_LED_ORANGE_POWER 1
  9743. +#define DIR825B1_GPIO_LED_BLUE_POWER 2
  9744. +#define DIR825B1_GPIO_LED_BLUE_WPS 4
  9745. +#define DIR825B1_GPIO_LED_ORANGE_PLANET 6
  9746. +#define DIR825B1_GPIO_LED_BLUE_PLANET 11
  9747. +
  9748. +#define DIR825B1_GPIO_BTN_RESET 3
  9749. +#define DIR825B1_GPIO_BTN_WPS 8
  9750. +
  9751. +#define DIR825B1_GPIO_RTL8366_SDA 5
  9752. +#define DIR825B1_GPIO_RTL8366_SCK 7
  9753. +
  9754. +#define DIR825B1_KEYS_POLL_INTERVAL 20 /* msecs */
  9755. +#define DIR825B1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825B1_KEYS_POLL_INTERVAL)
  9756. +
  9757. +#define DIR825B1_CAL0_OFFSET 0x1000
  9758. +#define DIR825B1_CAL1_OFFSET 0x5000
  9759. +#define DIR825B1_MAC0_OFFSET 0xffa0
  9760. +#define DIR825B1_MAC1_OFFSET 0xffb4
  9761. +
  9762. +#define DIR825B1_CAL_LOCATION_0 0x1f660000
  9763. +#define DIR825B1_CAL_LOCATION_1 0x1f7f0000
  9764. +
  9765. +static struct gpio_led dir825b1_leds_gpio[] __initdata = {
  9766. + {
  9767. + .name = "d-link:blue:usb",
  9768. + .gpio = DIR825B1_GPIO_LED_BLUE_USB,
  9769. + .active_low = 1,
  9770. + }, {
  9771. + .name = "d-link:orange:power",
  9772. + .gpio = DIR825B1_GPIO_LED_ORANGE_POWER,
  9773. + .active_low = 1,
  9774. + }, {
  9775. + .name = "d-link:blue:power",
  9776. + .gpio = DIR825B1_GPIO_LED_BLUE_POWER,
  9777. + .active_low = 1,
  9778. + }, {
  9779. + .name = "d-link:blue:wps",
  9780. + .gpio = DIR825B1_GPIO_LED_BLUE_WPS,
  9781. + .active_low = 1,
  9782. + }, {
  9783. + .name = "d-link:orange:planet",
  9784. + .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET,
  9785. + .active_low = 1,
  9786. + }, {
  9787. + .name = "d-link:blue:planet",
  9788. + .gpio = DIR825B1_GPIO_LED_BLUE_PLANET,
  9789. + .active_low = 1,
  9790. + }
  9791. +};
  9792. +
  9793. +static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = {
  9794. + {
  9795. + .desc = "reset",
  9796. + .type = EV_KEY,
  9797. + .code = KEY_RESTART,
  9798. + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL,
  9799. + .gpio = DIR825B1_GPIO_BTN_RESET,
  9800. + .active_low = 1,
  9801. + }, {
  9802. + .desc = "wps",
  9803. + .type = EV_KEY,
  9804. + .code = KEY_WPS_BUTTON,
  9805. + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL,
  9806. + .gpio = DIR825B1_GPIO_BTN_WPS,
  9807. + .active_low = 1,
  9808. + }
  9809. +};
  9810. +
  9811. +static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = {
  9812. + { .reg = 0x06, .val = 0x0108 },
  9813. +};
  9814. +
  9815. +static struct rtl8366_platform_data dir825b1_rtl8366s_data = {
  9816. + .gpio_sda = DIR825B1_GPIO_RTL8366_SDA,
  9817. + .gpio_sck = DIR825B1_GPIO_RTL8366_SCK,
  9818. + .num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals),
  9819. + .initvals = dir825b1_rtl8366s_initvals,
  9820. +};
  9821. +
  9822. +static struct platform_device dir825b1_rtl8366s_device = {
  9823. + .name = RTL8366S_DRIVER_NAME,
  9824. + .id = -1,
  9825. + .dev = {
  9826. + .platform_data = &dir825b1_rtl8366s_data,
  9827. + }
  9828. +};
  9829. +
  9830. +static bool __init dir825b1_is_caldata_valid(u8 *p)
  9831. +{
  9832. + u16 *magic0, *magic1;
  9833. +
  9834. + magic0 = (u16 *)(p + DIR825B1_CAL0_OFFSET);
  9835. + magic1 = (u16 *)(p + DIR825B1_CAL1_OFFSET);
  9836. +
  9837. + return (*magic0 == 0xa55a && *magic1 == 0xa55a);
  9838. +}
  9839. +
  9840. +static void __init dir825b1_wlan_init(void)
  9841. +{
  9842. + u8 *caldata;
  9843. + u8 mac0[ETH_ALEN], mac1[ETH_ALEN];
  9844. + u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN];
  9845. +
  9846. + caldata = (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0);
  9847. + if (!dir825b1_is_caldata_valid(caldata)) {
  9848. + caldata = (u8 *)KSEG1ADDR(DIR825B1_CAL_LOCATION_1);
  9849. + if (!dir825b1_is_caldata_valid(caldata)) {
  9850. + pr_err("no calibration data found\n");
  9851. + return;
  9852. + }
  9853. + }
  9854. +
  9855. + ath79_parse_ascii_mac(caldata + DIR825B1_MAC0_OFFSET, mac0);
  9856. + ath79_parse_ascii_mac(caldata + DIR825B1_MAC1_OFFSET, mac1);
  9857. +
  9858. + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
  9859. + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 0);
  9860. + ath79_init_mac(wmac0, mac0, 0);
  9861. + ath79_init_mac(wmac1, mac1, 1);
  9862. +
  9863. + ap9x_pci_setup_wmac_led_pin(0, 5);
  9864. + ap9x_pci_setup_wmac_led_pin(1, 5);
  9865. +
  9866. + ap94_pci_init(caldata + DIR825B1_CAL0_OFFSET, wmac0,
  9867. + caldata + DIR825B1_CAL1_OFFSET, wmac1);
  9868. +}
  9869. +
  9870. +static void __init dir825b1_setup(void)
  9871. +{
  9872. + dir825b1_wlan_init();
  9873. +
  9874. + ath79_register_mdio(0, 0x0);
  9875. +
  9876. + ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
  9877. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  9878. + ath79_eth0_data.speed = SPEED_1000;
  9879. + ath79_eth0_data.duplex = DUPLEX_FULL;
  9880. + ath79_eth0_pll_data.pll_1000 = 0x11110000;
  9881. +
  9882. + ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
  9883. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  9884. + ath79_eth1_data.phy_mask = 0x10;
  9885. + ath79_eth1_pll_data.pll_1000 = 0x11110000;
  9886. +
  9887. + ath79_register_eth(0);
  9888. + ath79_register_eth(1);
  9889. +
  9890. + ath79_register_m25p80(NULL);
  9891. +
  9892. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
  9893. + dir825b1_leds_gpio);
  9894. +
  9895. + ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL,
  9896. + ARRAY_SIZE(dir825b1_gpio_keys),
  9897. + dir825b1_gpio_keys);
  9898. +
  9899. + ath79_register_usb();
  9900. +
  9901. + platform_device_register(&dir825b1_rtl8366s_device);
  9902. +}
  9903. +
  9904. +MIPS_MACHINE(ATH79_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1",
  9905. + dir825b1_setup);
  9906. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dir-825-c1.c linux-4.1.43/arch/mips/ath79/mach-dir-825-c1.c
  9907. --- linux-4.1.43.orig/arch/mips/ath79/mach-dir-825-c1.c 1970-01-01 01:00:00.000000000 +0100
  9908. +++ linux-4.1.43/arch/mips/ath79/mach-dir-825-c1.c 2017-08-06 20:02:15.000000000 +0200
  9909. @@ -0,0 +1,241 @@
  9910. +/*
  9911. + * D-Link DIR-825 rev. C1 board support
  9912. + *
  9913. + * Copyright (C) 2013 Alexander Stadler
  9914. + *
  9915. + * This program is free software; you can redistribute it and/or modify it
  9916. + * under the terms of the GNU General Public License version 2 as published
  9917. + * by the Free Software Foundation.
  9918. + */
  9919. +
  9920. +#include <linux/pci.h>
  9921. +#include <linux/phy.h>
  9922. +#include <linux/gpio.h>
  9923. +#include <linux/platform_device.h>
  9924. +#include <linux/ath9k_platform.h>
  9925. +#include <linux/ar8216_platform.h>
  9926. +
  9927. +#include <asm/mach-ath79/ar71xx_regs.h>
  9928. +
  9929. +#include "common.h"
  9930. +#include "dev-ap9x-pci.h"
  9931. +#include "dev-eth.h"
  9932. +#include "dev-gpio-buttons.h"
  9933. +#include "dev-leds-gpio.h"
  9934. +#include "dev-m25p80.h"
  9935. +#include "dev-spi.h"
  9936. +#include "dev-usb.h"
  9937. +#include "dev-wmac.h"
  9938. +#include "machtypes.h"
  9939. +
  9940. +#define DIR825C1_GPIO_LED_BLUE_USB 11
  9941. +#define DIR825C1_GPIO_LED_AMBER_POWER 14
  9942. +#define DIR825C1_GPIO_LED_BLUE_POWER 22
  9943. +#define DIR825C1_GPIO_LED_BLUE_WPS 15
  9944. +#define DIR825C1_GPIO_LED_AMBER_PLANET 19
  9945. +#define DIR825C1_GPIO_LED_BLUE_PLANET 18
  9946. +#define DIR825C1_GPIO_LED_WLAN_2G 13
  9947. +
  9948. +#define DIR825C1_GPIO_WAN_LED_ENABLE 20
  9949. +
  9950. +#define DIR825C1_GPIO_BTN_RESET 17
  9951. +#define DIR825C1_GPIO_BTN_WPS 16
  9952. +
  9953. +#define DIR825C1_KEYS_POLL_INTERVAL 20 /* msecs */
  9954. +#define DIR825C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825C1_KEYS_POLL_INTERVAL)
  9955. +
  9956. +#define DIR825C1_MAC0_OFFSET 0x4
  9957. +#define DIR825C1_MAC1_OFFSET 0x18
  9958. +#define DIR825C1_WMAC_CALDATA_OFFSET 0x1000
  9959. +#define DIR825C1_PCIE_CALDATA_OFFSET 0x5000
  9960. +
  9961. +static struct gpio_led dir825c1_leds_gpio[] __initdata = {
  9962. + {
  9963. + .name = "d-link:blue:usb",
  9964. + .gpio = DIR825C1_GPIO_LED_BLUE_USB,
  9965. + .active_low = 1,
  9966. + },
  9967. + {
  9968. + .name = "d-link:amber:power",
  9969. + .gpio = DIR825C1_GPIO_LED_AMBER_POWER,
  9970. + .active_low = 1,
  9971. + },
  9972. + {
  9973. + .name = "d-link:blue:power",
  9974. + .gpio = DIR825C1_GPIO_LED_BLUE_POWER,
  9975. + .active_low = 1,
  9976. + },
  9977. + {
  9978. + .name = "d-link:blue:wps",
  9979. + .gpio = DIR825C1_GPIO_LED_BLUE_WPS,
  9980. + .active_low = 1,
  9981. + },
  9982. + {
  9983. + .name = "d-link:amber:planet",
  9984. + .gpio = DIR825C1_GPIO_LED_AMBER_PLANET,
  9985. + .active_low = 1,
  9986. + },
  9987. + {
  9988. + .name = "d-link:blue:wlan2g",
  9989. + .gpio = DIR825C1_GPIO_LED_WLAN_2G,
  9990. + .active_low = 1,
  9991. + },
  9992. +};
  9993. +
  9994. +static struct gpio_led dir835a1_leds_gpio[] __initdata = {
  9995. + {
  9996. + .name = "d-link:amber:power",
  9997. + .gpio = DIR825C1_GPIO_LED_AMBER_POWER,
  9998. + .active_low = 1,
  9999. + },
  10000. + {
  10001. + .name = "d-link:green:power",
  10002. + .gpio = DIR825C1_GPIO_LED_BLUE_POWER,
  10003. + .active_low = 1,
  10004. + },
  10005. + {
  10006. + .name = "d-link:blue:wps",
  10007. + .gpio = DIR825C1_GPIO_LED_BLUE_WPS,
  10008. + .active_low = 1,
  10009. + },
  10010. + {
  10011. + .name = "d-link:amber:planet",
  10012. + .gpio = DIR825C1_GPIO_LED_AMBER_PLANET,
  10013. + .active_low = 1,
  10014. + },
  10015. + {
  10016. + .name = "d-link:green:planet",
  10017. + .gpio = DIR825C1_GPIO_LED_BLUE_PLANET,
  10018. + .active_low = 1,
  10019. + },
  10020. +};
  10021. +
  10022. +static struct gpio_keys_button dir825c1_gpio_keys[] __initdata = {
  10023. + {
  10024. + .desc = "Soft reset",
  10025. + .type = EV_KEY,
  10026. + .code = KEY_RESTART,
  10027. + .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
  10028. + .gpio = DIR825C1_GPIO_BTN_RESET,
  10029. + .active_low = 1,
  10030. + },
  10031. + {
  10032. + .desc = "WPS button",
  10033. + .type = EV_KEY,
  10034. + .code = KEY_WPS_BUTTON,
  10035. + .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
  10036. + .gpio = DIR825C1_GPIO_BTN_WPS,
  10037. + .active_low = 1,
  10038. + },
  10039. +};
  10040. +
  10041. +static struct ar8327_pad_cfg dir825c1_ar8327_pad0_cfg = {
  10042. + .mode = AR8327_PAD_MAC_RGMII,
  10043. + .txclk_delay_en = true,
  10044. + .rxclk_delay_en = true,
  10045. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  10046. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  10047. +};
  10048. +
  10049. +static struct ar8327_led_cfg dir825c1_ar8327_led_cfg = {
  10050. + .led_ctrl0 = 0x00000000,
  10051. + .led_ctrl1 = 0xc737c737,
  10052. + .led_ctrl2 = 0x00000000,
  10053. + .led_ctrl3 = 0x00c30c00,
  10054. + .open_drain = true,
  10055. +};
  10056. +
  10057. +static struct ar8327_platform_data dir825c1_ar8327_data = {
  10058. + .pad0_cfg = &dir825c1_ar8327_pad0_cfg,
  10059. + .port0_cfg = {
  10060. + .force_link = 1,
  10061. + .speed = AR8327_PORT_SPEED_1000,
  10062. + .duplex = 1,
  10063. + .txpause = 1,
  10064. + .rxpause = 1,
  10065. + },
  10066. + .led_cfg = &dir825c1_ar8327_led_cfg,
  10067. +};
  10068. +
  10069. +static struct mdio_board_info dir825c1_mdio0_info[] = {
  10070. + {
  10071. + .bus_id = "ag71xx-mdio.0",
  10072. + .phy_addr = 0,
  10073. + .platform_data = &dir825c1_ar8327_data,
  10074. + },
  10075. +};
  10076. +
  10077. +static void __init dir825c1_generic_setup(void)
  10078. +{
  10079. + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
  10080. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  10081. + u8 mac0[ETH_ALEN], mac1[ETH_ALEN];
  10082. + u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN];
  10083. +
  10084. + ath79_parse_ascii_mac(mac + DIR825C1_MAC0_OFFSET, mac0);
  10085. + ath79_parse_ascii_mac(mac + DIR825C1_MAC1_OFFSET, mac1);
  10086. +
  10087. + ath79_register_m25p80(NULL);
  10088. +
  10089. + ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
  10090. + ARRAY_SIZE(dir825c1_gpio_keys),
  10091. + dir825c1_gpio_keys);
  10092. +
  10093. + ath79_init_mac(wmac0, mac0, 0);
  10094. + ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, wmac0);
  10095. +
  10096. + ath79_init_mac(wmac1, mac1, 1);
  10097. + ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, wmac1);
  10098. +
  10099. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  10100. +
  10101. + mdiobus_register_board_info(dir825c1_mdio0_info,
  10102. + ARRAY_SIZE(dir825c1_mdio0_info));
  10103. +
  10104. + ath79_register_mdio(0, 0x0);
  10105. +
  10106. + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
  10107. +
  10108. + /* GMAC0 is connected to an AR8327N switch */
  10109. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  10110. + ath79_eth0_data.phy_mask = BIT(0);
  10111. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  10112. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  10113. + ath79_register_eth(0);
  10114. +
  10115. + ath79_register_usb();
  10116. +}
  10117. +
  10118. +static void __init dir825c1_setup(void)
  10119. +{
  10120. + ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB,
  10121. + AR934X_GPIO_OUT_GPIO);
  10122. +
  10123. + gpio_request_one(DIR825C1_GPIO_WAN_LED_ENABLE,
  10124. + GPIOF_OUT_INIT_LOW, "WAN LED enable");
  10125. +
  10126. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
  10127. + dir825c1_leds_gpio);
  10128. +
  10129. + ap9x_pci_setup_wmac_led_pin(0, 0);
  10130. +
  10131. + dir825c1_generic_setup();
  10132. +}
  10133. +
  10134. +static void __init dir835a1_setup(void)
  10135. +{
  10136. + dir825c1_ar8327_data.led_cfg = NULL;
  10137. +
  10138. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir835a1_leds_gpio),
  10139. + dir835a1_leds_gpio);
  10140. +
  10141. + dir825c1_generic_setup();
  10142. +}
  10143. +
  10144. +MIPS_MACHINE(ATH79_MACH_DIR_825_C1, "DIR-825-C1",
  10145. + "D-Link DIR-825 rev. C1",
  10146. + dir825c1_setup);
  10147. +
  10148. +MIPS_MACHINE(ATH79_MACH_DIR_835_A1, "DIR-835-A1",
  10149. + "D-Link DIR-835 rev. A1",
  10150. + dir835a1_setup);
  10151. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dlan-hotspot.c linux-4.1.43/arch/mips/ath79/mach-dlan-hotspot.c
  10152. --- linux-4.1.43.orig/arch/mips/ath79/mach-dlan-hotspot.c 1970-01-01 01:00:00.000000000 +0100
  10153. +++ linux-4.1.43/arch/mips/ath79/mach-dlan-hotspot.c 2017-08-06 20:02:15.000000000 +0200
  10154. @@ -0,0 +1,117 @@
  10155. +/*
  10156. + * devolo dLAN Hotspot board support
  10157. + *
  10158. + * Copyright (C) 2015 Torsten Schnuis <torsten.schnuis@gik.de>
  10159. + * Copyright (C) 2015 devolo AG
  10160. + *
  10161. + * This program is free software; you can redistribute it and/or modify it
  10162. + * under the terms of the GNU General Public License version 2 as published
  10163. + * by the Free Software Foundation.
  10164. + */
  10165. +
  10166. +#include <linux/gpio.h>
  10167. +
  10168. +#include <asm/mach-ath79/ath79.h>
  10169. +
  10170. +#include "dev-eth.h"
  10171. +#include "dev-gpio-buttons.h"
  10172. +#include "dev-leds-gpio.h"
  10173. +#include "dev-m25p80.h"
  10174. +#include "dev-usb.h"
  10175. +#include "dev-wmac.h"
  10176. +#include "machtypes.h"
  10177. +
  10178. +#define DLAN_HOTSPOT_GPIO_LED_WIFI 0
  10179. +
  10180. +#define DLAN_HOTSPOT_GPIO_BTN_RESET 11
  10181. +#define DLAN_HOTSPOT_GPIO_BTN_PLC_PAIRING 12
  10182. +#define DLAN_HOTSPOT_GPIO_BTN_WIFI 21
  10183. +
  10184. +#define DLAN_HOTSPOT_GPIO_PLC_POWER 22
  10185. +#define DLAN_HOTSPOT_GPIO_PLC_RESET 20
  10186. +#define DLAN_HOTSPOT_GPIO_PLC_DISABLE_LEDS 18
  10187. +
  10188. +#define DLAN_HOTSPOT_KEYS_POLL_INTERVAL 20 /* msecs */
  10189. +#define DLAN_HOTSPOT_KEYS_DEBOUNCE_INTERVAL (3 * DLAN_HOTSPOT_KEYS_POLL_INTERVAL)
  10190. +
  10191. +#define DLAN_HOTSPOT_ART_ADDRESS 0x1fff0000
  10192. +#define DLAN_HOTSPOT_CALDATA_OFFSET 0x00001000
  10193. +#define DLAN_HOTSPOT_MAC_ADDRESS_OFFSET 0x00001002
  10194. +
  10195. +static struct gpio_led dlan_hotspot_leds_gpio[] __initdata = {
  10196. + {
  10197. + .name = "devolo:green:wifi",
  10198. + .gpio = DLAN_HOTSPOT_GPIO_LED_WIFI,
  10199. + .active_low = 0,
  10200. + }
  10201. +};
  10202. +
  10203. +static struct gpio_keys_button dlan_hotspot_gpio_keys[] __initdata = {
  10204. + {
  10205. + .desc = "Reset button",
  10206. + .type = EV_KEY,
  10207. + .code = KEY_RESTART,
  10208. + .debounce_interval = DLAN_HOTSPOT_KEYS_DEBOUNCE_INTERVAL,
  10209. + .gpio = DLAN_HOTSPOT_GPIO_BTN_RESET,
  10210. + .active_low = 0,
  10211. + },
  10212. + {
  10213. + .desc = "Pairing button",
  10214. + .type = EV_KEY,
  10215. + .code = BTN_0,
  10216. + .debounce_interval = DLAN_HOTSPOT_KEYS_DEBOUNCE_INTERVAL,
  10217. + .gpio = DLAN_HOTSPOT_GPIO_BTN_PLC_PAIRING,
  10218. + .active_low = 0,
  10219. + },
  10220. + {
  10221. + .desc = "WLAN button",
  10222. + .type = EV_KEY,
  10223. + .code = KEY_WPS_BUTTON,
  10224. + .debounce_interval = DLAN_HOTSPOT_KEYS_DEBOUNCE_INTERVAL,
  10225. + .gpio = DLAN_HOTSPOT_GPIO_BTN_WIFI,
  10226. + .active_low = 0,
  10227. + }
  10228. +};
  10229. +
  10230. +static void __init dlan_hotspot_setup(void)
  10231. +{
  10232. + u8 *art = (u8 *) KSEG1ADDR(DLAN_HOTSPOT_ART_ADDRESS);
  10233. + u8 *cal = art + DLAN_HOTSPOT_CALDATA_OFFSET;
  10234. + u8 *wifi_mac = art + DLAN_HOTSPOT_MAC_ADDRESS_OFFSET;
  10235. +
  10236. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  10237. + ath79_setup_ar933x_phy4_switch(false, false);
  10238. +
  10239. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_hotspot_leds_gpio),
  10240. + dlan_hotspot_leds_gpio);
  10241. +
  10242. + ath79_register_gpio_keys_polled(-1, DLAN_HOTSPOT_KEYS_POLL_INTERVAL,
  10243. + ARRAY_SIZE(dlan_hotspot_gpio_keys),
  10244. + dlan_hotspot_gpio_keys);
  10245. +
  10246. + gpio_request_one(DLAN_HOTSPOT_GPIO_PLC_POWER,
  10247. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  10248. + "PLC power");
  10249. + gpio_request_one(DLAN_HOTSPOT_GPIO_PLC_RESET,
  10250. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
  10251. + "PLC reset");
  10252. + gpio_request_one(DLAN_HOTSPOT_GPIO_PLC_DISABLE_LEDS,
  10253. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
  10254. + "PLC LEDs");
  10255. +
  10256. + ath79_register_usb();
  10257. +
  10258. + ath79_register_m25p80(NULL);
  10259. +
  10260. + ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 1);
  10261. + ath79_init_mac(ath79_eth1_data.mac_addr, wifi_mac, 2);
  10262. +
  10263. + ath79_register_mdio(0, 0x0);
  10264. + ath79_register_eth(0);
  10265. + ath79_register_eth(1);
  10266. +
  10267. + ath79_register_wmac(cal, wifi_mac);
  10268. +}
  10269. +
  10270. +MIPS_MACHINE(ATH79_MACH_DLAN_HOTSPOT, "dLAN-Hotspot",
  10271. + "dLAN Hotspot", dlan_hotspot_setup);
  10272. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dlan-pro-1200-ac.c linux-4.1.43/arch/mips/ath79/mach-dlan-pro-1200-ac.c
  10273. --- linux-4.1.43.orig/arch/mips/ath79/mach-dlan-pro-1200-ac.c 1970-01-01 01:00:00.000000000 +0100
  10274. +++ linux-4.1.43/arch/mips/ath79/mach-dlan-pro-1200-ac.c 2017-08-06 20:02:15.000000000 +0200
  10275. @@ -0,0 +1,189 @@
  10276. +/*
  10277. + * devolo dLAN pro 500 Wireless+ support
  10278. + *
  10279. + * Copyright (c) 2013-2015 devolo AG
  10280. + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  10281. + *
  10282. + * Permission to use, copy, modify, and/or distribute this software for any
  10283. + * purpose with or without fee is hereby granted, provided that the above
  10284. + * copyright notice and this permission notice appear in all copies.
  10285. + *
  10286. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10287. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10288. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10289. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  10290. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  10291. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  10292. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  10293. + *
  10294. + */
  10295. +
  10296. +#include <linux/pci.h>
  10297. +#include <linux/phy.h>
  10298. +#include <linux/platform_device.h>
  10299. +#include <linux/ath9k_platform.h>
  10300. +#include <linux/ar8216_platform.h>
  10301. +#include <linux/gpio.h>
  10302. +
  10303. +#include <asm/mach-ath79/ar71xx_regs.h>
  10304. +
  10305. +#include "common.h"
  10306. +#include "dev-ap9x-pci.h"
  10307. +#include "dev-eth.h"
  10308. +#include "dev-gpio-buttons.h"
  10309. +#include "dev-leds-gpio.h"
  10310. +#include "dev-m25p80.h"
  10311. +#include "dev-nfc.h"
  10312. +#include "dev-spi.h"
  10313. +#include "dev-wmac.h"
  10314. +#include "machtypes.h"
  10315. +
  10316. +#define DLAN_PRO_1200_AC_GPIO_DLAN_POWER_ENABLE 13
  10317. +#define DLAN_PRO_1200_AC_GPIO_WLAN_POWER_ENABLE 21
  10318. +#define DLAN_PRO_1200_AC_GPIO_LED_WLAN 12
  10319. +#define DLAN_PRO_1200_AC_GPIO_LED_DLAN 14
  10320. +#define DLAN_PRO_1200_AC_GPIO_LED_DLAN_ERR 15
  10321. +
  10322. +#define DLAN_PRO_1200_AC_GPIO_BTN_WLAN 20
  10323. +#define DLAN_PRO_1200_AC_GPIO_BTN_DLAN 22
  10324. +#define DLAN_PRO_1200_AC_GPIO_BTN_RESET 4
  10325. +#define DLAN_PRO_1200_AC_GPIO_DLAN_IND 17
  10326. +#define DLAN_PRO_1200_AC_GPIO_DLAN_ERR_IND 16
  10327. +
  10328. +#define DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL 20 /* msecs */
  10329. +#define DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL (3 * DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL)
  10330. +
  10331. +#define DLAN_PRO_1200_AC_ART_ADDRESS 0x1fff0000
  10332. +#define DLAN_PRO_1200_AC_CALDATA_OFFSET 0x1000
  10333. +#define DLAN_PRO_1200_AC_WIFIMAC_OFFSET 0x1002
  10334. +#define DLAN_PRO_1200_AC_PCIE_CALDATA_OFFSET 0x5000
  10335. +
  10336. +static struct gpio_led dlan_pro_1200_ac_leds_gpio[] __initdata = {
  10337. + {
  10338. + .name = "devolo:status:wlan",
  10339. + .gpio = DLAN_PRO_1200_AC_GPIO_LED_WLAN,
  10340. + .active_low = 1,
  10341. + },
  10342. + {
  10343. + .name = "devolo:status:dlan",
  10344. + .gpio = DLAN_PRO_1200_AC_GPIO_LED_DLAN,
  10345. + .active_low = 1,
  10346. + },
  10347. + {
  10348. + .name = "devolo:error:dlan",
  10349. + .gpio = DLAN_PRO_1200_AC_GPIO_LED_DLAN_ERR,
  10350. + .active_low = 0,
  10351. + }
  10352. +};
  10353. +
  10354. +static struct gpio_keys_button dlan_pro_1200_ac_gpio_keys[] __initdata = {
  10355. + {
  10356. + .desc = "dLAN button",
  10357. + .type = EV_KEY,
  10358. + .code = BTN_0,
  10359. + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL,
  10360. + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_DLAN,
  10361. + .active_low = 1,
  10362. + },
  10363. + {
  10364. + .desc = "WLAN button",
  10365. + .type = EV_KEY,
  10366. + .code = KEY_WPS_BUTTON,
  10367. + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL,
  10368. + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_WLAN,
  10369. + .active_low = 0,
  10370. + },
  10371. + {
  10372. + .desc = "Reset button",
  10373. + .type = EV_KEY,
  10374. + .code = KEY_RESTART,
  10375. + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL,
  10376. + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_RESET,
  10377. + .active_low = 1,
  10378. + }
  10379. +};
  10380. +
  10381. +static struct ar8327_pad_cfg dlan_pro_1200_ac_ar8327_pad0_cfg = {
  10382. + .mode = AR8327_PAD_MAC_RGMII,
  10383. + .txclk_delay_en = true,
  10384. + .rxclk_delay_en = false,
  10385. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  10386. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
  10387. +};
  10388. +
  10389. +static struct ar8327_pad_cfg dlan_pro_1200_ac_ar8327_pad5_cfg = {
  10390. + .mode = 0,
  10391. + .txclk_delay_en = 0,
  10392. + .rxclk_delay_en = 0,
  10393. + .txclk_delay_sel = 0,
  10394. + .rxclk_delay_sel = 0,
  10395. +};
  10396. +
  10397. +static struct ar8327_platform_data dlan_pro_1200_ac_ar8327_data = {
  10398. + .pad0_cfg = &dlan_pro_1200_ac_ar8327_pad0_cfg,
  10399. + .pad5_cfg = &dlan_pro_1200_ac_ar8327_pad5_cfg,
  10400. + .port0_cfg = {
  10401. + .force_link = 1,
  10402. + .speed = AR8327_PORT_SPEED_1000,
  10403. + .duplex = 1,
  10404. + .txpause = 1,
  10405. + .rxpause = 1,
  10406. + },
  10407. +};
  10408. +
  10409. +static struct mdio_board_info dlan_pro_1200_ac_mdio0_info[] = {
  10410. + {
  10411. + .bus_id = "ag71xx-mdio.0",
  10412. + .phy_addr = 0,
  10413. + .platform_data = &dlan_pro_1200_ac_ar8327_data,
  10414. + },
  10415. +};
  10416. +
  10417. +static void __init dlan_pro_1200_ac_setup(void)
  10418. +{
  10419. + u8 *art = (u8 *) KSEG1ADDR(DLAN_PRO_1200_AC_ART_ADDRESS);
  10420. + u8 *cal = art + DLAN_PRO_1200_AC_CALDATA_OFFSET;
  10421. + u8 *wifi_mac = art + DLAN_PRO_1200_AC_WIFIMAC_OFFSET;
  10422. +
  10423. + ath79_register_m25p80(NULL);
  10424. +
  10425. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_pro_1200_ac_leds_gpio),
  10426. + dlan_pro_1200_ac_leds_gpio);
  10427. +
  10428. + ath79_register_gpio_keys_polled(-1, DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL,
  10429. + ARRAY_SIZE(dlan_pro_1200_ac_gpio_keys),
  10430. + dlan_pro_1200_ac_gpio_keys);
  10431. +
  10432. + /* dLAN power must be enabled from user-space as soon as the boot-from-host daemon is running */
  10433. + gpio_request_one(DLAN_PRO_1200_AC_GPIO_DLAN_POWER_ENABLE,
  10434. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
  10435. + "dLAN power");
  10436. +
  10437. + /* WLAN power is turned on initially to allow the PCI bus scan to succeed */
  10438. + gpio_request_one(DLAN_PRO_1200_AC_GPIO_WLAN_POWER_ENABLE,
  10439. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  10440. + "WLAN power");
  10441. +
  10442. + ath79_register_wmac(cal, wifi_mac);
  10443. + ap91_pci_init(art + DLAN_PRO_1200_AC_PCIE_CALDATA_OFFSET, NULL);
  10444. +
  10445. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
  10446. +
  10447. + ath79_register_mdio(1, 0x0);
  10448. + ath79_register_mdio(0, 0x0);
  10449. +
  10450. + ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 2);
  10451. +
  10452. + mdiobus_register_board_info(dlan_pro_1200_ac_mdio0_info,
  10453. + ARRAY_SIZE(dlan_pro_1200_ac_mdio0_info));
  10454. +
  10455. + /* GMAC0 is connected to an AR8337 */
  10456. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  10457. + ath79_eth0_data.phy_mask = BIT(0);
  10458. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  10459. + ath79_eth0_pll_data.pll_1000 = 0x02000000;
  10460. + ath79_register_eth(0);
  10461. +}
  10462. +
  10463. +MIPS_MACHINE(ATH79_MACH_DLAN_PRO_1200_AC, "dLAN-pro-1200-ac", "devolo dLAN pro 1200+ WiFi ac",
  10464. + dlan_pro_1200_ac_setup);
  10465. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dlan-pro-500-wp.c linux-4.1.43/arch/mips/ath79/mach-dlan-pro-500-wp.c
  10466. --- linux-4.1.43.orig/arch/mips/ath79/mach-dlan-pro-500-wp.c 1970-01-01 01:00:00.000000000 +0100
  10467. +++ linux-4.1.43/arch/mips/ath79/mach-dlan-pro-500-wp.c 2017-08-06 20:02:15.000000000 +0200
  10468. @@ -0,0 +1,203 @@
  10469. +/*
  10470. + * devolo dLAN pro 500 Wireless+ support
  10471. + *
  10472. + * Copyright (c) 2013-2015 devolo AG
  10473. + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  10474. + *
  10475. + * Permission to use, copy, modify, and/or distribute this software for any
  10476. + * purpose with or without fee is hereby granted, provided that the above
  10477. + * copyright notice and this permission notice appear in all copies.
  10478. + *
  10479. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10480. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10481. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10482. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  10483. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  10484. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  10485. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  10486. + *
  10487. + */
  10488. +
  10489. +#include <linux/pci.h>
  10490. +#include <linux/phy.h>
  10491. +#include <linux/platform_device.h>
  10492. +#include <linux/ath9k_platform.h>
  10493. +#include <linux/ar8216_platform.h>
  10494. +#include <linux/gpio.h>
  10495. +
  10496. +#include <asm/mach-ath79/ar71xx_regs.h>
  10497. +
  10498. +#include "common.h"
  10499. +#include "dev-ap9x-pci.h"
  10500. +#include "dev-eth.h"
  10501. +#include "dev-gpio-buttons.h"
  10502. +#include "dev-leds-gpio.h"
  10503. +#include "dev-m25p80.h"
  10504. +#include "dev-spi.h"
  10505. +#include "dev-wmac.h"
  10506. +#include "machtypes.h"
  10507. +
  10508. +#define DLAN_PRO_500_WP_GPIO_DLAN_POWER_ENABLE 13
  10509. +#define DLAN_PRO_500_WP_GPIO_DLAN_LED_ENABLE 17
  10510. +#define DLAN_PRO_500_WP_GPIO_LED_WLAN_5G 11
  10511. +#define DLAN_PRO_500_WP_GPIO_LED_WLAN_2G 12
  10512. +#define DLAN_PRO_500_WP_GPIO_LED_STATUS 16
  10513. +#define DLAN_PRO_500_WP_GPIO_LED_ETH 14
  10514. +
  10515. +#define DLAN_PRO_500_WP_GPIO_BTN_WPS 20
  10516. +#define DLAN_PRO_500_WP_GPIO_BTN_WLAN 22
  10517. +#define DLAN_PRO_500_WP_GPIO_BTN_DLAN 21
  10518. +#define DLAN_PRO_500_WP_GPIO_BTN_RESET 4
  10519. +
  10520. +#define DLAN_PRO_500_WP_KEYS_POLL_INTERVAL 20 /* msecs */
  10521. +#define DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL (3 * DLAN_PRO_500_WP_KEYS_POLL_INTERVAL)
  10522. +
  10523. +#define DLAN_PRO_500_WP_ART_ADDRESS 0x1fff0000
  10524. +#define DLAN_PRO_500_WP_CALDATA_OFFSET 0x1000
  10525. +#define DLAN_PRO_500_WP_MAC_ADDRESS_OFFSET 0x1002
  10526. +#define DLAN_PRO_500_WP_PCIE_CALDATA_OFFSET 0x5000
  10527. +
  10528. +static struct gpio_led dlan_pro_500_wp_leds_gpio[] __initdata = {
  10529. + {
  10530. + .name = "devolo:green:status",
  10531. + .gpio = DLAN_PRO_500_WP_GPIO_LED_STATUS,
  10532. + .active_low = 1,
  10533. + },
  10534. + {
  10535. + .name = "devolo:green:eth",
  10536. + .gpio = DLAN_PRO_500_WP_GPIO_LED_ETH,
  10537. + .active_low = 1,
  10538. + },
  10539. + {
  10540. + .name = "devolo:blue:wlan-5g",
  10541. + .gpio = DLAN_PRO_500_WP_GPIO_LED_WLAN_5G,
  10542. + .active_low = 1,
  10543. + },
  10544. + {
  10545. + .name = "devolo:green:wlan-2g",
  10546. + .gpio = DLAN_PRO_500_WP_GPIO_LED_WLAN_2G,
  10547. + .active_low = 1,
  10548. + }
  10549. +};
  10550. +
  10551. +static struct gpio_keys_button dlan_pro_500_wp_gpio_keys[] __initdata = {
  10552. + {
  10553. + .desc = "dLAN button",
  10554. + .type = EV_KEY,
  10555. + .code = BTN_0,
  10556. + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL,
  10557. + .gpio = DLAN_PRO_500_WP_GPIO_BTN_DLAN,
  10558. + .active_low = 0,
  10559. + },
  10560. + {
  10561. + .desc = "WPS button",
  10562. + .type = EV_KEY,
  10563. + .code = KEY_WPS_BUTTON,
  10564. + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL,
  10565. + .gpio = DLAN_PRO_500_WP_GPIO_BTN_WPS,
  10566. + .active_low = 0,
  10567. + },
  10568. + {
  10569. + .desc = "WLAN button",
  10570. + .type = EV_KEY,
  10571. + .code = BTN_2,
  10572. + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL,
  10573. + .gpio = DLAN_PRO_500_WP_GPIO_BTN_WLAN,
  10574. + .active_low = 1,
  10575. + },
  10576. + {
  10577. + .desc = "Reset button",
  10578. + .type = EV_KEY,
  10579. + .code = KEY_RESTART,
  10580. + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL,
  10581. + .gpio = DLAN_PRO_500_WP_GPIO_BTN_RESET,
  10582. + .active_low = 1,
  10583. + }
  10584. +};
  10585. +
  10586. +static struct ar8327_pad_cfg dlan_pro_500_wp_ar8327_pad0_cfg = {
  10587. + .mode = AR8327_PAD_PHY_RGMII,
  10588. + .txclk_delay_en = false,
  10589. + .rxclk_delay_en = false,
  10590. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL0,
  10591. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
  10592. +};
  10593. +
  10594. +static struct ar8327_led_cfg dlan_pro_500_wp_ar8327_led_cfg = {
  10595. + .led_ctrl0 = 0x00000000,
  10596. + .led_ctrl1 = 0xc737c737,
  10597. + .led_ctrl2 = 0x00000000,
  10598. + .led_ctrl3 = 0x00c30c00,
  10599. + .open_drain = true,
  10600. +};
  10601. +
  10602. +static struct ar8327_platform_data dlan_pro_500_wp_ar8327_data = {
  10603. + .pad0_cfg = &dlan_pro_500_wp_ar8327_pad0_cfg,
  10604. + .port0_cfg = {
  10605. + .force_link = 1,
  10606. + .speed = AR8327_PORT_SPEED_1000,
  10607. + .duplex = 1,
  10608. + .txpause = 0,
  10609. + .rxpause = 0,
  10610. + },
  10611. + .led_cfg = &dlan_pro_500_wp_ar8327_led_cfg,
  10612. +};
  10613. +
  10614. +static struct mdio_board_info dlan_pro_500_wp_mdio0_info[] = {
  10615. + {
  10616. + .bus_id = "ag71xx-mdio.0",
  10617. + .phy_addr = 0,
  10618. + .platform_data = &dlan_pro_500_wp_ar8327_data,
  10619. + },
  10620. +};
  10621. +
  10622. +static void __init dlan_pro_500_wp_setup(void)
  10623. +{
  10624. + u8 *art = (u8 *) KSEG1ADDR(DLAN_PRO_500_WP_ART_ADDRESS);
  10625. + u8 *cal = art + DLAN_PRO_500_WP_CALDATA_OFFSET;
  10626. + u8 *wifi_mac = art + DLAN_PRO_500_WP_MAC_ADDRESS_OFFSET;
  10627. +
  10628. + ath79_register_m25p80(NULL);
  10629. +
  10630. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_pro_500_wp_leds_gpio),
  10631. + dlan_pro_500_wp_leds_gpio);
  10632. +
  10633. + ath79_register_gpio_keys_polled(-1, DLAN_PRO_500_WP_KEYS_POLL_INTERVAL,
  10634. + ARRAY_SIZE(dlan_pro_500_wp_gpio_keys),
  10635. + dlan_pro_500_wp_gpio_keys);
  10636. +
  10637. + gpio_request_one(DLAN_PRO_500_WP_GPIO_DLAN_POWER_ENABLE,
  10638. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
  10639. + "PLC power");
  10640. + gpio_request_one(DLAN_PRO_500_WP_GPIO_DLAN_LED_ENABLE,
  10641. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
  10642. + "PLC LEDs");
  10643. +
  10644. + ath79_register_wmac(cal, wifi_mac);
  10645. +
  10646. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  10647. +
  10648. + ath79_register_mdio(1, 0x0);
  10649. + ath79_register_mdio(0, 0x0);
  10650. +
  10651. + mdiobus_register_board_info(dlan_pro_500_wp_mdio0_info,
  10652. + ARRAY_SIZE(dlan_pro_500_wp_mdio0_info));
  10653. +
  10654. + /* GMAC0 is connected to a AR7400 PLC in PHY mode */
  10655. + ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 2);
  10656. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  10657. + ath79_eth0_pll_data.pll_1000 = 0x0e000000;
  10658. + ath79_eth0_data.speed = SPEED_1000;
  10659. + ath79_eth0_data.duplex = DUPLEX_FULL;
  10660. + ath79_register_eth(0);
  10661. +
  10662. + /* GMAC1 is connected to the internal switch */
  10663. + ath79_init_mac(ath79_eth1_data.mac_addr, wifi_mac, 1);
  10664. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  10665. + ath79_eth1_data.speed = SPEED_1000;
  10666. + ath79_eth1_data.duplex = DUPLEX_FULL;
  10667. + ath79_register_eth(1);
  10668. +}
  10669. +
  10670. +MIPS_MACHINE(ATH79_MACH_DLAN_PRO_500_WP, "dLAN-pro-500-wp", "devolo dLAN pro 500 Wireless+",
  10671. + dlan_pro_500_wp_setup);
  10672. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-dragino2.c linux-4.1.43/arch/mips/ath79/mach-dragino2.c
  10673. --- linux-4.1.43.orig/arch/mips/ath79/mach-dragino2.c 1970-01-01 01:00:00.000000000 +0100
  10674. +++ linux-4.1.43/arch/mips/ath79/mach-dragino2.c 2017-08-06 20:02:15.000000000 +0200
  10675. @@ -0,0 +1,136 @@
  10676. +/*
  10677. + * DRAGINO V2 board support, based on Atheros AP121 board support
  10678. + *
  10679. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  10680. + * Copyright (C) 2012 Elektra Wagenrad <elektra@villagetelco.org>
  10681. + * Copyright (C) 2014 Vittorio Gambaletta <openwrt@vittgam.net>
  10682. + *
  10683. + * This program is free software; you can redistribute it and/or modify it
  10684. + * under the terms of the GNU General Public License version 2 as published
  10685. + * by the Free Software Foundation.
  10686. + */
  10687. +
  10688. +#include <linux/gpio.h>
  10689. +#include <asm/mach-ath79/ath79.h>
  10690. +#include <asm/mach-ath79/ar71xx_regs.h>
  10691. +#include "common.h"
  10692. +#include "dev-eth.h"
  10693. +#include "dev-gpio-buttons.h"
  10694. +#include "dev-leds-gpio.h"
  10695. +#include "dev-m25p80.h"
  10696. +#include "dev-spi.h"
  10697. +#include "dev-usb.h"
  10698. +#include "dev-wmac.h"
  10699. +#include "machtypes.h"
  10700. +
  10701. +#define DRAGINO2_GPIO_LED_WLAN 0
  10702. +#define DRAGINO2_GPIO_LED_LAN 13
  10703. +#define DRAGINO2_GPIO_LED_WAN 17
  10704. +
  10705. +/*
  10706. + * The following GPIO is named "SYS" on newer revisions of the the board.
  10707. + * It was previously used to indicate USB activity, even though it was
  10708. + * named "Router".
  10709. + */
  10710. +
  10711. +#define DRAGINO2_GPIO_LED_SYS 28
  10712. +#define DRAGINO2_GPIO_BTN_JUMPSTART 11
  10713. +#define DRAGINO2_GPIO_BTN_RESET 12
  10714. +
  10715. +#define DRAGINO2_KEYS_POLL_INTERVAL 20 /* msecs */
  10716. +#define DRAGINO2_KEYS_DEBOUNCE_INTERVAL (3 * DRAGINO2_KEYS_POLL_INTERVAL)
  10717. +
  10718. +#define DRAGINO2_MAC0_OFFSET 0x0000
  10719. +#define DRAGINO2_MAC1_OFFSET 0x0006
  10720. +#define DRAGINO2_CALDATA_OFFSET 0x1000
  10721. +#define DRAGINO2_WMAC_MAC_OFFSET 0x1002
  10722. +
  10723. +static struct gpio_led dragino2_leds_gpio[] __initdata = {
  10724. + {
  10725. + .name = "dragino2:red:wlan",
  10726. + .gpio = DRAGINO2_GPIO_LED_WLAN,
  10727. + .active_low = 0,
  10728. + },
  10729. + {
  10730. + .name = "dragino2:red:wan",
  10731. + .gpio = DRAGINO2_GPIO_LED_WAN,
  10732. + .active_low = 1,
  10733. + },
  10734. + {
  10735. + .name = "dragino2:red:lan",
  10736. + .gpio = DRAGINO2_GPIO_LED_LAN,
  10737. + .active_low = 1,
  10738. + },
  10739. + {
  10740. + .name = "dragino2:red:system",
  10741. + .gpio = DRAGINO2_GPIO_LED_SYS,
  10742. + .active_low = 0,
  10743. + },
  10744. +};
  10745. +
  10746. +static struct gpio_keys_button dragino2_gpio_keys[] __initdata = {
  10747. + {
  10748. + .desc = "jumpstart button",
  10749. + .type = EV_KEY,
  10750. + .code = KEY_WPS_BUTTON,
  10751. + .debounce_interval = DRAGINO2_KEYS_DEBOUNCE_INTERVAL,
  10752. + .gpio = DRAGINO2_GPIO_BTN_JUMPSTART,
  10753. + .active_low = 1,
  10754. + },
  10755. + {
  10756. + .desc = "reset button",
  10757. + .type = EV_KEY,
  10758. + .code = KEY_RESTART,
  10759. + .debounce_interval = DRAGINO2_KEYS_DEBOUNCE_INTERVAL,
  10760. + .gpio = DRAGINO2_GPIO_BTN_RESET,
  10761. + .active_low = 1,
  10762. + }
  10763. +};
  10764. +
  10765. +static void __init dragino2_common_setup(void)
  10766. +{
  10767. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  10768. +
  10769. + ath79_register_m25p80(NULL);
  10770. + ath79_register_wmac(art + DRAGINO2_CALDATA_OFFSET,
  10771. + art + DRAGINO2_WMAC_MAC_OFFSET);
  10772. +
  10773. + ath79_init_mac(ath79_eth0_data.mac_addr, art + DRAGINO2_MAC0_OFFSET, 0);
  10774. + ath79_init_mac(ath79_eth1_data.mac_addr, art + DRAGINO2_MAC1_OFFSET, 0);
  10775. +
  10776. + ath79_register_mdio(0, 0x0);
  10777. +
  10778. + /* Enable GPIO13, GPIO14, GPIO15, GPIO16 and GPIO17 */
  10779. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  10780. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  10781. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  10782. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  10783. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  10784. +
  10785. + /* LAN port */
  10786. + ath79_register_eth(1);
  10787. +
  10788. + /* WAN port */
  10789. + ath79_register_eth(0);
  10790. +
  10791. + /* Enable GPIO26 and GPIO27 */
  10792. + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP,
  10793. + ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) |
  10794. + AR933X_BOOTSTRAP_MDIO_GPIO_EN);
  10795. +}
  10796. +
  10797. +static void __init dragino2_setup(void)
  10798. +{
  10799. + dragino2_common_setup();
  10800. +
  10801. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dragino2_leds_gpio),
  10802. + dragino2_leds_gpio);
  10803. + ath79_register_gpio_keys_polled(-1, DRAGINO2_KEYS_POLL_INTERVAL,
  10804. + ARRAY_SIZE(dragino2_gpio_keys),
  10805. + dragino2_gpio_keys);
  10806. + ath79_register_usb();
  10807. +}
  10808. +
  10809. +MIPS_MACHINE(ATH79_MACH_DRAGINO2, "DRAGINO2", "Dragino Dragino v2",
  10810. + dragino2_setup);
  10811. +
  10812. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-eap300v2.c linux-4.1.43/arch/mips/ath79/mach-eap300v2.c
  10813. --- linux-4.1.43.orig/arch/mips/ath79/mach-eap300v2.c 1970-01-01 01:00:00.000000000 +0100
  10814. +++ linux-4.1.43/arch/mips/ath79/mach-eap300v2.c 2017-08-06 20:02:15.000000000 +0200
  10815. @@ -0,0 +1,101 @@
  10816. +/*
  10817. + * EnGenius EAP300 v2 board support
  10818. + *
  10819. + * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
  10820. + *
  10821. + * This program is free software; you can redistribute it and/or modify it
  10822. + * under the terms of the GNU General Public License version 2 as published
  10823. + * by the Free Software Foundation.
  10824. + */
  10825. +
  10826. +#include <linux/gpio.h>
  10827. +#include <linux/mtd/mtd.h>
  10828. +#include <linux/mtd/partitions.h>
  10829. +#include <linux/platform_device.h>
  10830. +
  10831. +#include <asm/mach-ath79/ar71xx_regs.h>
  10832. +#include <asm/mach-ath79/ath79.h>
  10833. +
  10834. +#include "common.h"
  10835. +#include "dev-eth.h"
  10836. +#include "dev-gpio-buttons.h"
  10837. +#include "dev-leds-gpio.h"
  10838. +#include "dev-m25p80.h"
  10839. +#include "dev-wmac.h"
  10840. +#include "machtypes.h"
  10841. +
  10842. +#define EAP300V2_GPIO_LED_POWER 0
  10843. +#define EAP300V2_GPIO_LED_LAN 16
  10844. +#define EAP300V2_GPIO_LED_WLAN 17
  10845. +
  10846. +#define EAP300V2_GPIO_BTN_RESET 1
  10847. +
  10848. +#define EAP300V2_KEYS_POLL_INTERVAL 20 /* msecs */
  10849. +#define EAP300V2_KEYS_DEBOUNCE_INTERVAL (3 * EAP300V2_KEYS_POLL_INTERVAL)
  10850. +
  10851. +static struct gpio_led eap300v2_leds_gpio[] __initdata = {
  10852. + {
  10853. + .name = "engenius:blue:power",
  10854. + .gpio = EAP300V2_GPIO_LED_POWER,
  10855. + .active_low = 1,
  10856. + }, {
  10857. + .name = "engenius:blue:lan",
  10858. + .gpio = EAP300V2_GPIO_LED_LAN,
  10859. + .active_low = 1,
  10860. + }, {
  10861. + .name = "engenius:blue:wlan",
  10862. + .gpio = EAP300V2_GPIO_LED_WLAN,
  10863. + .active_low = 1,
  10864. + }
  10865. +};
  10866. +
  10867. +static struct gpio_keys_button eap300v2_gpio_keys[] __initdata = {
  10868. + {
  10869. + .desc = "reset",
  10870. + .type = EV_KEY,
  10871. + .code = KEY_RESTART,
  10872. + .debounce_interval = EAP300V2_KEYS_DEBOUNCE_INTERVAL,
  10873. + .gpio = EAP300V2_GPIO_BTN_RESET,
  10874. + .active_low = 1,
  10875. + }
  10876. +};
  10877. +
  10878. +#define EAP300V2_ART_MAC_OFFSET 2
  10879. +
  10880. +#define EAP300V2_LAN_PHYMASK BIT(0)
  10881. +
  10882. +static void __init eap300v2_setup(void)
  10883. +{
  10884. + u8 *art = (u8 *)KSEG1ADDR(0x1fff1000);
  10885. +
  10886. + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
  10887. +
  10888. + ath79_gpio_output_select(EAP300V2_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
  10889. + ath79_gpio_output_select(EAP300V2_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
  10890. + ath79_gpio_output_select(EAP300V2_GPIO_LED_WLAN, AR934X_GPIO_OUT_GPIO);
  10891. +
  10892. + ath79_register_leds_gpio(-1, ARRAY_SIZE(eap300v2_leds_gpio),
  10893. + eap300v2_leds_gpio);
  10894. + ath79_register_gpio_keys_polled(-1, EAP300V2_KEYS_POLL_INTERVAL,
  10895. + ARRAY_SIZE(eap300v2_gpio_keys),
  10896. + eap300v2_gpio_keys);
  10897. +
  10898. + ath79_register_m25p80(NULL);
  10899. + ath79_register_wmac(art, NULL);
  10900. + ath79_register_mdio(1, 0x0);
  10901. +
  10902. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  10903. +
  10904. + ath79_init_mac(ath79_eth0_data.mac_addr,
  10905. + art + EAP300V2_ART_MAC_OFFSET, 0);
  10906. +
  10907. + ath79_switch_data.phy4_mii_en = 1;
  10908. + ath79_switch_data.phy_poll_mask = EAP300V2_LAN_PHYMASK;
  10909. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  10910. + ath79_eth0_data.phy_mask = EAP300V2_LAN_PHYMASK;
  10911. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  10912. + ath79_register_eth(0);
  10913. +}
  10914. +
  10915. +MIPS_MACHINE(ATH79_MACH_EAP300V2, "EAP300V2", "EnGenius EAP300 v2",
  10916. + eap300v2_setup);
  10917. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-eap7660d.c linux-4.1.43/arch/mips/ath79/mach-eap7660d.c
  10918. --- linux-4.1.43.orig/arch/mips/ath79/mach-eap7660d.c 1970-01-01 01:00:00.000000000 +0100
  10919. +++ linux-4.1.43/arch/mips/ath79/mach-eap7660d.c 2017-08-06 20:02:15.000000000 +0200
  10920. @@ -0,0 +1,181 @@
  10921. +/*
  10922. + * Senao EAP7660D board support
  10923. + *
  10924. + * Copyright (C) 2010 Daniel Golle <daniel.golle@gmail.com>
  10925. + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
  10926. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10927. + *
  10928. + * This program is free software; you can redistribute it and/or modify it
  10929. + * under the terms of the GNU General Public License version 2 as published
  10930. + * by the Free Software Foundation.
  10931. + */
  10932. +
  10933. +#include <linux/pci.h>
  10934. +#include <linux/ath5k_platform.h>
  10935. +#include <linux/delay.h>
  10936. +
  10937. +#include <asm/mach-ath79/ath79.h>
  10938. +
  10939. +#include "dev-eth.h"
  10940. +#include "dev-gpio-buttons.h"
  10941. +#include "dev-leds-gpio.h"
  10942. +#include "dev-m25p80.h"
  10943. +#include "machtypes.h"
  10944. +#include "pci.h"
  10945. +
  10946. +#define EAP7660D_KEYS_POLL_INTERVAL 20 /* msecs */
  10947. +#define EAP7660D_KEYS_DEBOUNCE_INTERVAL (3 * EAP7660D_KEYS_POLL_INTERVAL)
  10948. +
  10949. +#define EAP7660D_GPIO_DS4 7
  10950. +#define EAP7660D_GPIO_DS5 2
  10951. +#define EAP7660D_GPIO_DS7 0
  10952. +#define EAP7660D_GPIO_DS8 4
  10953. +#define EAP7660D_GPIO_SW1 3
  10954. +#define EAP7660D_GPIO_SW3 8
  10955. +#define EAP7660D_PHYMASK BIT(20)
  10956. +#define EAP7660D_BOARDCONFIG 0x1F7F0000
  10957. +#define EAP7660D_GBIC_MAC_OFFSET 0x1000
  10958. +#define EAP7660D_WMAC0_MAC_OFFSET 0x1010
  10959. +#define EAP7660D_WMAC1_MAC_OFFSET 0x1016
  10960. +#define EAP7660D_WMAC0_CALDATA_OFFSET 0x2000
  10961. +#define EAP7660D_WMAC1_CALDATA_OFFSET 0x3000
  10962. +
  10963. +#ifdef CONFIG_PCI
  10964. +static struct ath5k_platform_data eap7660d_wmac0_data;
  10965. +static struct ath5k_platform_data eap7660d_wmac1_data;
  10966. +static char eap7660d_wmac0_mac[6];
  10967. +static char eap7660d_wmac1_mac[6];
  10968. +static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS];
  10969. +static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS];
  10970. +
  10971. +static int eap7660d_pci_plat_dev_init(struct pci_dev *dev)
  10972. +{
  10973. + switch (PCI_SLOT(dev->devfn)) {
  10974. + case 17:
  10975. + dev->dev.platform_data = &eap7660d_wmac0_data;
  10976. + break;
  10977. +
  10978. + case 18:
  10979. + dev->dev.platform_data = &eap7660d_wmac1_data;
  10980. + break;
  10981. + }
  10982. +
  10983. + return 0;
  10984. +}
  10985. +
  10986. +void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0,
  10987. + u8 *cal_data1, u8 *mac_addr1)
  10988. +{
  10989. + if (cal_data0 && *cal_data0 == 0xa55a) {
  10990. + memcpy(eap7660d_wmac0_eeprom, cal_data0,
  10991. + ATH5K_PLAT_EEP_MAX_WORDS);
  10992. + eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom;
  10993. + }
  10994. +
  10995. + if (cal_data1 && *cal_data1 == 0xa55a) {
  10996. + memcpy(eap7660d_wmac1_eeprom, cal_data1,
  10997. + ATH5K_PLAT_EEP_MAX_WORDS);
  10998. + eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom;
  10999. + }
  11000. +
  11001. + if (mac_addr0) {
  11002. + memcpy(eap7660d_wmac0_mac, mac_addr0,
  11003. + sizeof(eap7660d_wmac0_mac));
  11004. + eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac;
  11005. + }
  11006. +
  11007. + if (mac_addr1) {
  11008. + memcpy(eap7660d_wmac1_mac, mac_addr1,
  11009. + sizeof(eap7660d_wmac1_mac));
  11010. + eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac;
  11011. + }
  11012. +
  11013. + ath79_pci_set_plat_dev_init(eap7660d_pci_plat_dev_init);
  11014. + ath79_register_pci();
  11015. +}
  11016. +#else
  11017. +static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0,
  11018. + u8 *cal_data1, u8 *mac_addr1)
  11019. +{
  11020. +}
  11021. +#endif /* CONFIG_PCI */
  11022. +
  11023. +static struct gpio_led eap7660d_leds_gpio[] __initdata = {
  11024. + {
  11025. + .name = "eap7660d:green:ds8",
  11026. + .gpio = EAP7660D_GPIO_DS8,
  11027. + .active_low = 0,
  11028. + },
  11029. + {
  11030. + .name = "eap7660d:green:ds5",
  11031. + .gpio = EAP7660D_GPIO_DS5,
  11032. + .active_low = 0,
  11033. + },
  11034. + {
  11035. + .name = "eap7660d:green:ds7",
  11036. + .gpio = EAP7660D_GPIO_DS7,
  11037. + .active_low = 0,
  11038. + },
  11039. + {
  11040. + .name = "eap7660d:green:ds4",
  11041. + .gpio = EAP7660D_GPIO_DS4,
  11042. + .active_low = 0,
  11043. + }
  11044. +};
  11045. +
  11046. +static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = {
  11047. + {
  11048. + .desc = "reset",
  11049. + .type = EV_KEY,
  11050. + .code = KEY_RESTART,
  11051. + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL,
  11052. + .gpio = EAP7660D_GPIO_SW1,
  11053. + .active_low = 1,
  11054. + },
  11055. + {
  11056. + .desc = "wps",
  11057. + .type = EV_KEY,
  11058. + .code = KEY_WPS_BUTTON,
  11059. + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL,
  11060. + .gpio = EAP7660D_GPIO_SW3,
  11061. + .active_low = 1,
  11062. + }
  11063. +};
  11064. +
  11065. +static const char *eap7660d_part_probes[] = {
  11066. + "RedBoot",
  11067. + NULL,
  11068. +};
  11069. +
  11070. +static struct flash_platform_data eap7660d_flash_data = {
  11071. + .part_probes = eap7660d_part_probes,
  11072. +};
  11073. +
  11074. +static void __init eap7660d_setup(void)
  11075. +{
  11076. + u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG);
  11077. +
  11078. + ath79_register_mdio(0, ~EAP7660D_PHYMASK);
  11079. +
  11080. + ath79_init_mac(ath79_eth0_data.mac_addr,
  11081. + boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0);
  11082. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  11083. + ath79_eth0_data.phy_mask = EAP7660D_PHYMASK;
  11084. + ath79_register_eth(0);
  11085. + ath79_register_m25p80(&eap7660d_flash_data);
  11086. + ath79_register_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio),
  11087. + eap7660d_leds_gpio);
  11088. + ath79_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL,
  11089. + ARRAY_SIZE(eap7660d_gpio_keys),
  11090. + eap7660d_gpio_keys);
  11091. + eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET,
  11092. + boardconfig + EAP7660D_WMAC0_MAC_OFFSET,
  11093. + boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET,
  11094. + boardconfig + EAP7660D_WMAC1_MAC_OFFSET);
  11095. +};
  11096. +
  11097. +MIPS_MACHINE(ATH79_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D",
  11098. + eap7660d_setup);
  11099. +
  11100. +MIPS_MACHINE(ATH79_MACH_ALL0305, "ALL0305", "Allnet ALL0305",
  11101. + eap7660d_setup);
  11102. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-el-m150.c linux-4.1.43/arch/mips/ath79/mach-el-m150.c
  11103. --- linux-4.1.43.orig/arch/mips/ath79/mach-el-m150.c 1970-01-01 01:00:00.000000000 +0100
  11104. +++ linux-4.1.43/arch/mips/ath79/mach-el-m150.c 2017-08-06 20:02:15.000000000 +0200
  11105. @@ -0,0 +1,112 @@
  11106. +/*
  11107. + * Easy-Link EL-M150 board support
  11108. + *
  11109. + * Copyright (C) 2012 huangfc <huangfangcheng@163.com>
  11110. + * Copyright (C) 2012 HYS <550663898@qq.com>
  11111. + *
  11112. + * This program is free software; you can redistribute it and/or modify it
  11113. + * under the terms of the GNU General Public License version 2 as published
  11114. + * by the Free Software Foundation.
  11115. + */
  11116. +
  11117. +#include <linux/gpio.h>
  11118. +
  11119. +#include <asm/mach-ath79/ath79.h>
  11120. +#include <asm/mach-ath79/ar71xx_regs.h>
  11121. +
  11122. +#include "common.h"
  11123. +#include "dev-eth.h"
  11124. +#include "dev-gpio-buttons.h"
  11125. +#include "dev-leds-gpio.h"
  11126. +#include "dev-m25p80.h"
  11127. +#include "dev-wmac.h"
  11128. +#include "machtypes.h"
  11129. +#include "dev-usb.h"
  11130. +
  11131. +#define EL_M150_GPIO_BTN6 6
  11132. +#define EL_M150_GPIO_BTN7 7
  11133. +#define EL_M150_GPIO_BTN_RESET 11
  11134. +
  11135. +#define EL_M150_GPIO_LED_SYSTEM 27
  11136. +#define EL_M150_GPIO_USB_POWER 8
  11137. +
  11138. +#define EL_M150_KEYS_POLL_INTERVAL 20 /* msecs */
  11139. +#define EL_M150_KEYS_DEBOUNCE_INTERVAL (3 * EL_M150_KEYS_POLL_INTERVAL)
  11140. +
  11141. +static const char *EL_M150_part_probes[] = {
  11142. + "tp-link",
  11143. + NULL,
  11144. +};
  11145. +
  11146. +static struct flash_platform_data EL_M150_flash_data = {
  11147. + .part_probes = EL_M150_part_probes,
  11148. +};
  11149. +
  11150. +static struct gpio_led EL_M150_leds_gpio[] __initdata = {
  11151. + {
  11152. + .name = "easylink:green:system",
  11153. + .gpio = EL_M150_GPIO_LED_SYSTEM,
  11154. + .active_low = 1,
  11155. + },
  11156. +};
  11157. +
  11158. +static struct gpio_keys_button EL_M150_gpio_keys[] __initdata = {
  11159. + {
  11160. + .desc = "reset",
  11161. + .type = EV_KEY,
  11162. + .code = KEY_RESTART,
  11163. + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL,
  11164. + .gpio = EL_M150_GPIO_BTN_RESET,
  11165. + .active_low = 0,
  11166. + },
  11167. + {
  11168. + .desc = "BTN_6",
  11169. + .type = EV_KEY,
  11170. + .code = BTN_6,
  11171. + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL,
  11172. + .gpio = EL_M150_GPIO_BTN6,
  11173. + .active_low = 1,
  11174. + },
  11175. + {
  11176. + .desc = "BTN_7",
  11177. + .type = EV_KEY,
  11178. + .code = BTN_7,
  11179. + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL,
  11180. + .gpio = EL_M150_GPIO_BTN7,
  11181. + .active_low = 1,
  11182. + },
  11183. +};
  11184. +
  11185. +static void __init el_m150_setup(void)
  11186. +{
  11187. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  11188. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  11189. +
  11190. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  11191. + ath79_setup_ar933x_phy4_switch(false, false);
  11192. +
  11193. + ath79_register_leds_gpio(-1, ARRAY_SIZE(EL_M150_leds_gpio),
  11194. + EL_M150_leds_gpio);
  11195. +
  11196. + ath79_register_gpio_keys_polled(-1, EL_M150_KEYS_POLL_INTERVAL,
  11197. + ARRAY_SIZE(EL_M150_gpio_keys),
  11198. + EL_M150_gpio_keys);
  11199. +
  11200. + gpio_request_one(EL_M150_GPIO_USB_POWER,
  11201. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  11202. + "USB power");
  11203. + ath79_register_usb();
  11204. +
  11205. + ath79_register_m25p80(&EL_M150_flash_data);
  11206. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  11207. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  11208. +
  11209. + ath79_register_mdio(0, 0x0);
  11210. + ath79_register_eth(0);
  11211. + ath79_register_eth(1);
  11212. +
  11213. + ath79_register_wmac(ee, mac);
  11214. +}
  11215. +
  11216. +MIPS_MACHINE(ATH79_MACH_EL_M150, "EL-M150",
  11217. + "EasyLink EL-M150", el_m150_setup);
  11218. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-el-mini.c linux-4.1.43/arch/mips/ath79/mach-el-mini.c
  11219. --- linux-4.1.43.orig/arch/mips/ath79/mach-el-mini.c 1970-01-01 01:00:00.000000000 +0100
  11220. +++ linux-4.1.43/arch/mips/ath79/mach-el-mini.c 2017-08-06 20:02:15.000000000 +0200
  11221. @@ -0,0 +1,86 @@
  11222. +/*
  11223. + * Easy-Link EL-MINI board support
  11224. + *
  11225. + * Copyright (C) 2012 huangfc <huangfangcheng@163.com>
  11226. + * Copyright (C) 2011 hys <550663898@qq.com>
  11227. + *
  11228. + * This program is free software; you can redistribute it and/or modify it
  11229. + * under the terms of the GNU General Public License version 2 as published
  11230. + * by the Free Software Foundation.
  11231. + */
  11232. +
  11233. +#include <linux/gpio.h>
  11234. +
  11235. +#include <asm/mach-ath79/ath79.h>
  11236. +
  11237. +#include "dev-eth.h"
  11238. +#include "dev-gpio-buttons.h"
  11239. +#include "dev-leds-gpio.h"
  11240. +#include "dev-m25p80.h"
  11241. +#include "dev-usb.h"
  11242. +#include "dev-wmac.h"
  11243. +#include "machtypes.h"
  11244. +
  11245. +#define MINI_GPIO_LED_SYSTEM 27
  11246. +#define MINI_GPIO_BTN_RESET 11
  11247. +
  11248. +#define MINI_GPIO_USB_POWER 8
  11249. +
  11250. +#define MINI_KEYS_POLL_INTERVAL 20 /* msecs */
  11251. +#define MINI_KEYS_DEBOUNCE_INTERVAL (3 * MINI_KEYS_POLL_INTERVAL)
  11252. +
  11253. +static const char *mini_part_probes[] = {
  11254. + "tp-link",
  11255. + NULL,
  11256. +};
  11257. +
  11258. +static struct flash_platform_data mini_flash_data = {
  11259. + .part_probes = mini_part_probes,
  11260. +};
  11261. +
  11262. +static struct gpio_led mini_leds_gpio[] __initdata = {
  11263. + {
  11264. + .name = "easylink:green:system",
  11265. + .gpio = MINI_GPIO_LED_SYSTEM,
  11266. + .active_low = 1,
  11267. + },
  11268. +};
  11269. +
  11270. +static struct gpio_keys_button mini_gpio_keys[] __initdata = {
  11271. + {
  11272. + .desc = "reset",
  11273. + .type = EV_KEY,
  11274. + .code = KEY_RESTART,
  11275. + .debounce_interval = MINI_KEYS_DEBOUNCE_INTERVAL,
  11276. + .gpio = MINI_GPIO_BTN_RESET,
  11277. + .active_low = 0,
  11278. + }
  11279. +};
  11280. +
  11281. +static void __init el_mini_setup(void)
  11282. +{
  11283. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  11284. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  11285. +
  11286. + ath79_register_m25p80(&mini_flash_data);
  11287. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mini_leds_gpio),
  11288. + mini_leds_gpio);
  11289. + ath79_register_gpio_keys_polled(-1, MINI_KEYS_POLL_INTERVAL,
  11290. + ARRAY_SIZE(mini_gpio_keys),
  11291. + mini_gpio_keys);
  11292. +
  11293. + gpio_request_one(MINI_GPIO_USB_POWER,
  11294. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  11295. + "USB power");
  11296. + ath79_register_usb();
  11297. +
  11298. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
  11299. +
  11300. + ath79_register_mdio(0, 0x0);
  11301. + ath79_register_eth(0);
  11302. +
  11303. + ath79_register_wmac(ee, mac);
  11304. +}
  11305. +
  11306. +MIPS_MACHINE(ATH79_MACH_EL_MINI, "EL-MINI", "EasyLink EL-MINI",
  11307. + el_mini_setup);
  11308. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-epg5000.c linux-4.1.43/arch/mips/ath79/mach-epg5000.c
  11309. --- linux-4.1.43.orig/arch/mips/ath79/mach-epg5000.c 1970-01-01 01:00:00.000000000 +0100
  11310. +++ linux-4.1.43/arch/mips/ath79/mach-epg5000.c 2017-08-06 20:02:15.000000000 +0200
  11311. @@ -0,0 +1,178 @@
  11312. +/*
  11313. + * EnGenius EPG5000 board support
  11314. + *
  11315. + * Copyright (c) 2014 Jon Suphammer <jon@suphammer.net>
  11316. + * Copyright (c) 2015 Christian Beier <cb@shoutrlabs.com>
  11317. + *
  11318. + * This program is free software; you can redistribute it and/or modify it
  11319. + * under the terms of the GNU General Public License version 2 as published
  11320. + * by the Free Software Foundation.
  11321. + */
  11322. +
  11323. +#include <linux/platform_device.h>
  11324. +#include <linux/ar8216_platform.h>
  11325. +
  11326. +#include <asm/mach-ath79/ar71xx_regs.h>
  11327. +
  11328. +#include "common.h"
  11329. +#include "pci.h"
  11330. +#include "dev-ap9x-pci.h"
  11331. +#include "dev-gpio-buttons.h"
  11332. +#include "dev-eth.h"
  11333. +#include "dev-leds-gpio.h"
  11334. +#include "dev-m25p80.h"
  11335. +#include "dev-usb.h"
  11336. +#include "dev-wmac.h"
  11337. +#include "machtypes.h"
  11338. +#include "nvram.h"
  11339. +
  11340. +#define EPG5000_GPIO_LED_WLAN_5G 23
  11341. +#define EPG5000_GPIO_LED_WLAN_2G 13
  11342. +#define EPG5000_GPIO_LED_POWER_AMBER 2
  11343. +#define EPG5000_GPIO_LED_WPS_AMBER 22
  11344. +#define EPG5000_GPIO_LED_WPS_BLUE 19
  11345. +
  11346. +#define EPG5000_GPIO_BTN_WPS 16
  11347. +#define EPG5000_GPIO_BTN_RESET 17
  11348. +
  11349. +#define EPG5000_KEYS_POLL_INTERVAL 20 /* msecs */
  11350. +#define EPG5000_KEYS_DEBOUNCE_INTERVAL (3 * EPG5000_KEYS_POLL_INTERVAL)
  11351. +
  11352. +#define EPG5000_CALDATA_ADDR 0x1fff0000
  11353. +#define EPG5000_WMAC_CALDATA_OFFSET 0x1000
  11354. +#define EPG5000_PCIE_CALDATA_OFFSET 0x5000
  11355. +
  11356. +#define EPG5000_NVRAM_ADDR 0x1f030000
  11357. +#define EPG5000_NVRAM_SIZE 0x10000
  11358. +
  11359. +static struct gpio_led epg5000_leds_gpio[] __initdata = {
  11360. + {
  11361. + .name = "epg5000:amber:power",
  11362. + .gpio = EPG5000_GPIO_LED_POWER_AMBER,
  11363. + .active_low = 1,
  11364. + },
  11365. + {
  11366. + .name = "epg5000:blue:wps",
  11367. + .gpio = EPG5000_GPIO_LED_WPS_BLUE,
  11368. + .active_low = 1,
  11369. + },
  11370. + {
  11371. + .name = "epg5000:amber:wps",
  11372. + .gpio = EPG5000_GPIO_LED_WPS_AMBER,
  11373. + .active_low = 1,
  11374. + },
  11375. + {
  11376. + .name = "epg5000:blue:wlan-2g",
  11377. + .gpio = EPG5000_GPIO_LED_WLAN_2G,
  11378. + .active_low = 1,
  11379. + },
  11380. + {
  11381. + .name = "epg5000:blue:wlan-5g",
  11382. + .gpio = EPG5000_GPIO_LED_WLAN_5G,
  11383. + .active_low = 1,
  11384. + }
  11385. +};
  11386. +
  11387. +static struct gpio_keys_button epg5000_gpio_keys[] __initdata = {
  11388. + {
  11389. + .desc = "WPS button",
  11390. + .type = EV_KEY,
  11391. + .code = KEY_WPS_BUTTON,
  11392. + .debounce_interval = EPG5000_KEYS_DEBOUNCE_INTERVAL,
  11393. + .gpio = EPG5000_GPIO_BTN_WPS,
  11394. + .active_low = 1,
  11395. + },
  11396. + {
  11397. + .desc = "Reset button",
  11398. + .type = EV_KEY,
  11399. + .code = KEY_RESTART,
  11400. + .debounce_interval = EPG5000_KEYS_DEBOUNCE_INTERVAL,
  11401. + .gpio = EPG5000_GPIO_BTN_RESET,
  11402. + .active_low = 1,
  11403. + },
  11404. +};
  11405. +
  11406. +static struct ar8327_pad_cfg epg5000_ar8327_pad0_cfg = {
  11407. + .mode = AR8327_PAD_MAC_RGMII,
  11408. + .txclk_delay_en = true,
  11409. + .rxclk_delay_en = true,
  11410. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  11411. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  11412. + .mac06_exchange_en = true,
  11413. +};
  11414. +
  11415. +static struct ar8327_platform_data epg5000_ar8327_data = {
  11416. + .pad0_cfg = &epg5000_ar8327_pad0_cfg,
  11417. + .port0_cfg = {
  11418. + .force_link = 1,
  11419. + .speed = AR8327_PORT_SPEED_1000,
  11420. + .duplex = 1,
  11421. + .txpause = 1,
  11422. + .rxpause = 1,
  11423. + },
  11424. +};
  11425. +
  11426. +static struct mdio_board_info epg5000_mdio0_info[] = {
  11427. + {
  11428. + .bus_id = "ag71xx-mdio.0",
  11429. + .phy_addr = 0,
  11430. + .platform_data = &epg5000_ar8327_data,
  11431. + },
  11432. +};
  11433. +
  11434. +static int epg5000_get_mac(const char *name, char *mac)
  11435. +{
  11436. + u8 *nvram = (u8 *) KSEG1ADDR(EPG5000_NVRAM_ADDR);
  11437. + int err;
  11438. +
  11439. + err = ath79_nvram_parse_mac_addr(nvram, EPG5000_NVRAM_SIZE,
  11440. + name, mac);
  11441. + if (err) {
  11442. + pr_err("no MAC address found for %s\n", name);
  11443. + return false;
  11444. + }
  11445. +
  11446. + return true;
  11447. +}
  11448. +
  11449. +static void __init epg5000_setup(void)
  11450. +{
  11451. + u8 *caldata = (u8 *) KSEG1ADDR(EPG5000_CALDATA_ADDR);
  11452. + u8 mac1[ETH_ALEN];
  11453. +
  11454. + ath79_register_m25p80(NULL);
  11455. +
  11456. + ath79_register_leds_gpio(-1, ARRAY_SIZE(epg5000_leds_gpio),
  11457. + epg5000_leds_gpio);
  11458. + ath79_register_gpio_keys_polled(-1, EPG5000_KEYS_POLL_INTERVAL,
  11459. + ARRAY_SIZE(epg5000_gpio_keys),
  11460. + epg5000_gpio_keys);
  11461. +
  11462. + ath79_register_usb();
  11463. +
  11464. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  11465. +
  11466. + ath79_register_mdio(0, 0x0);
  11467. +
  11468. + mdiobus_register_board_info(epg5000_mdio0_info,
  11469. + ARRAY_SIZE(epg5000_mdio0_info));
  11470. +
  11471. + /* GMAC0 is connected to an QCA8327N switch */
  11472. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  11473. + ath79_eth0_data.phy_mask = BIT(0);
  11474. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  11475. +
  11476. + if (epg5000_get_mac("ethaddr=", mac1))
  11477. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  11478. +
  11479. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  11480. + ath79_register_eth(0);
  11481. +
  11482. + ath79_register_wmac(caldata + EPG5000_WMAC_CALDATA_OFFSET, mac1);
  11483. +
  11484. + ath79_register_pci();
  11485. +}
  11486. +
  11487. +MIPS_MACHINE(ATH79_MACH_EPG5000, "EPG5000",
  11488. + "EnGenius EPG5000",
  11489. + epg5000_setup);
  11490. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-esr1750.c linux-4.1.43/arch/mips/ath79/mach-esr1750.c
  11491. --- linux-4.1.43.orig/arch/mips/ath79/mach-esr1750.c 1970-01-01 01:00:00.000000000 +0100
  11492. +++ linux-4.1.43/arch/mips/ath79/mach-esr1750.c 2017-08-06 20:02:15.000000000 +0200
  11493. @@ -0,0 +1,177 @@
  11494. +/*
  11495. + * EnGenius ESR1750 board support
  11496. + *
  11497. + * Copyright (c) 2014 Jon Suphammer <jon@suphammer.net>
  11498. + *
  11499. + * This program is free software; you can redistribute it and/or modify it
  11500. + * under the terms of the GNU General Public License version 2 as published
  11501. + * by the Free Software Foundation.
  11502. + */
  11503. +
  11504. +#include <linux/platform_device.h>
  11505. +#include <linux/ar8216_platform.h>
  11506. +
  11507. +#include <asm/mach-ath79/ar71xx_regs.h>
  11508. +
  11509. +#include "common.h"
  11510. +#include "pci.h"
  11511. +#include "dev-ap9x-pci.h"
  11512. +#include "dev-gpio-buttons.h"
  11513. +#include "dev-eth.h"
  11514. +#include "dev-leds-gpio.h"
  11515. +#include "dev-m25p80.h"
  11516. +#include "dev-usb.h"
  11517. +#include "dev-wmac.h"
  11518. +#include "machtypes.h"
  11519. +#include "nvram.h"
  11520. +
  11521. +#define ESR1750_GPIO_LED_WLAN_5G 23
  11522. +#define ESR1750_GPIO_LED_WLAN_2G 13
  11523. +#define ESR1750_GPIO_LED_POWER_AMBER 2
  11524. +#define ESR1750_GPIO_LED_WPS_AMBER 22
  11525. +#define ESR1750_GPIO_LED_WPS_BLUE 19
  11526. +
  11527. +#define ESR1750_GPIO_BTN_WPS 16
  11528. +#define ESR1750_GPIO_BTN_RESET 17
  11529. +
  11530. +#define ESR1750_KEYS_POLL_INTERVAL 20 /* msecs */
  11531. +#define ESR1750_KEYS_DEBOUNCE_INTERVAL (3 * ESR1750_KEYS_POLL_INTERVAL)
  11532. +
  11533. +#define ESR1750_CALDATA_ADDR 0x1fff0000
  11534. +#define ESR1750_WMAC_CALDATA_OFFSET 0x1000
  11535. +#define ESR1750_PCIE_CALDATA_OFFSET 0x5000
  11536. +
  11537. +#define ESR1750_NVRAM_ADDR 0x1f030000
  11538. +#define ESR1750_NVRAM_SIZE 0x10000
  11539. +
  11540. +static struct gpio_led esr1750_leds_gpio[] __initdata = {
  11541. + {
  11542. + .name = "esr1750:amber:power",
  11543. + .gpio = ESR1750_GPIO_LED_POWER_AMBER,
  11544. + .active_low = 1,
  11545. + },
  11546. + {
  11547. + .name = "esr1750:blue:wps",
  11548. + .gpio = ESR1750_GPIO_LED_WPS_BLUE,
  11549. + .active_low = 1,
  11550. + },
  11551. + {
  11552. + .name = "esr1750:amber:wps",
  11553. + .gpio = ESR1750_GPIO_LED_WPS_AMBER,
  11554. + .active_low = 1,
  11555. + },
  11556. + {
  11557. + .name = "esr1750:blue:wlan-2g",
  11558. + .gpio = ESR1750_GPIO_LED_WLAN_2G,
  11559. + .active_low = 1,
  11560. + },
  11561. + {
  11562. + .name = "esr1750:blue:wlan-5g",
  11563. + .gpio = ESR1750_GPIO_LED_WLAN_5G,
  11564. + .active_low = 1,
  11565. + }
  11566. +};
  11567. +
  11568. +static struct gpio_keys_button esr1750_gpio_keys[] __initdata = {
  11569. + {
  11570. + .desc = "WPS button",
  11571. + .type = EV_KEY,
  11572. + .code = KEY_WPS_BUTTON,
  11573. + .debounce_interval = ESR1750_KEYS_DEBOUNCE_INTERVAL,
  11574. + .gpio = ESR1750_GPIO_BTN_WPS,
  11575. + .active_low = 1,
  11576. + },
  11577. + {
  11578. + .desc = "Reset button",
  11579. + .type = EV_KEY,
  11580. + .code = KEY_RESTART,
  11581. + .debounce_interval = ESR1750_KEYS_DEBOUNCE_INTERVAL,
  11582. + .gpio = ESR1750_GPIO_BTN_RESET,
  11583. + .active_low = 1,
  11584. + },
  11585. +};
  11586. +
  11587. +static struct ar8327_pad_cfg esr1750_ar8327_pad0_cfg = {
  11588. + .mode = AR8327_PAD_MAC_RGMII,
  11589. + .txclk_delay_en = true,
  11590. + .rxclk_delay_en = true,
  11591. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  11592. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  11593. + .mac06_exchange_en = true,
  11594. +};
  11595. +
  11596. +static struct ar8327_platform_data esr1750_ar8327_data = {
  11597. + .pad0_cfg = &esr1750_ar8327_pad0_cfg,
  11598. + .port0_cfg = {
  11599. + .force_link = 1,
  11600. + .speed = AR8327_PORT_SPEED_1000,
  11601. + .duplex = 1,
  11602. + .txpause = 1,
  11603. + .rxpause = 1,
  11604. + },
  11605. +};
  11606. +
  11607. +static struct mdio_board_info esr1750_mdio0_info[] = {
  11608. + {
  11609. + .bus_id = "ag71xx-mdio.0",
  11610. + .phy_addr = 0,
  11611. + .platform_data = &esr1750_ar8327_data,
  11612. + },
  11613. +};
  11614. +
  11615. +static int esr1750_get_mac(const char *name, char *mac)
  11616. +{
  11617. + u8 *nvram = (u8 *) KSEG1ADDR(ESR1750_NVRAM_ADDR);
  11618. + int err;
  11619. +
  11620. + err = ath79_nvram_parse_mac_addr(nvram, ESR1750_NVRAM_SIZE,
  11621. + name, mac);
  11622. + if (err) {
  11623. + pr_err("no MAC address found for %s\n", name);
  11624. + return false;
  11625. + }
  11626. +
  11627. + return true;
  11628. +}
  11629. +
  11630. +static void __init esr1750_setup(void)
  11631. +{
  11632. + u8 *caldata = (u8 *) KSEG1ADDR(ESR1750_CALDATA_ADDR);
  11633. + u8 mac1[ETH_ALEN];
  11634. +
  11635. + ath79_register_m25p80(NULL);
  11636. +
  11637. + ath79_register_leds_gpio(-1, ARRAY_SIZE(esr1750_leds_gpio),
  11638. + esr1750_leds_gpio);
  11639. + ath79_register_gpio_keys_polled(-1, ESR1750_KEYS_POLL_INTERVAL,
  11640. + ARRAY_SIZE(esr1750_gpio_keys),
  11641. + esr1750_gpio_keys);
  11642. +
  11643. + ath79_register_usb();
  11644. +
  11645. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  11646. +
  11647. + ath79_register_mdio(0, 0x0);
  11648. +
  11649. + mdiobus_register_board_info(esr1750_mdio0_info,
  11650. + ARRAY_SIZE(esr1750_mdio0_info));
  11651. +
  11652. + /* GMAC0 is connected to an QCA8327N switch */
  11653. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  11654. + ath79_eth0_data.phy_mask = BIT(0);
  11655. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  11656. +
  11657. + if (esr1750_get_mac("ethaddr=", mac1))
  11658. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  11659. +
  11660. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  11661. + ath79_register_eth(0);
  11662. +
  11663. + ath79_register_wmac(caldata + ESR1750_WMAC_CALDATA_OFFSET, mac1);
  11664. +
  11665. + ath79_register_pci();
  11666. +}
  11667. +
  11668. +MIPS_MACHINE(ATH79_MACH_ESR1750, "ESR1750",
  11669. + "EnGenius ESR1750",
  11670. + esr1750_setup);
  11671. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-esr900.c linux-4.1.43/arch/mips/ath79/mach-esr900.c
  11672. --- linux-4.1.43.orig/arch/mips/ath79/mach-esr900.c 1970-01-01 01:00:00.000000000 +0100
  11673. +++ linux-4.1.43/arch/mips/ath79/mach-esr900.c 2017-08-06 20:02:15.000000000 +0200
  11674. @@ -0,0 +1,200 @@
  11675. +/*
  11676. + * EnGenius ESR900 board support
  11677. + *
  11678. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  11679. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  11680. + *
  11681. + * This program is free software; you can redistribute it and/or modify it
  11682. + * under the terms of the GNU General Public License version 2 as published
  11683. + * by the Free Software Foundation.
  11684. + */
  11685. +
  11686. +#define pr_fmt(fmt) "esr900: " fmt
  11687. +
  11688. +#include <linux/platform_device.h>
  11689. +#include <linux/ar8216_platform.h>
  11690. +
  11691. +#include <asm/mach-ath79/ar71xx_regs.h>
  11692. +
  11693. +#include "common.h"
  11694. +#include "pci.h"
  11695. +#include "dev-ap9x-pci.h"
  11696. +#include "dev-gpio-buttons.h"
  11697. +#include "dev-eth.h"
  11698. +#include "dev-leds-gpio.h"
  11699. +#include "dev-m25p80.h"
  11700. +#include "dev-usb.h"
  11701. +#include "dev-wmac.h"
  11702. +#include "machtypes.h"
  11703. +#include "nvram.h"
  11704. +
  11705. +#define ESR900_GPIO_LED_POWER 2
  11706. +#define ESR900_GPIO_LED_WLAN_2G 13
  11707. +#define ESR900_GPIO_LED_WPS_BLUE 19
  11708. +#define ESR900_GPIO_LED_WPS_AMBER 22
  11709. +#define ESR900_GPIO_LED_WLAN_5G 23
  11710. +
  11711. +#define ESR900_GPIO_BTN_WPS 16
  11712. +#define ESR900_GPIO_BTN_RESET 17
  11713. +
  11714. +#define ESR900_KEYS_POLL_INTERVAL 20 /* msecs */
  11715. +#define ESR900_KEYS_DEBOUNCE_INTERVAL (3 * ESR900_KEYS_POLL_INTERVAL)
  11716. +
  11717. +#define ESR900_CALDATA_ADDR 0x1fff0000
  11718. +#define ESR900_WMAC_CALDATA_OFFSET 0x1000
  11719. +#define ESR900_PCIE_CALDATA_OFFSET 0x5000
  11720. +
  11721. +#define ESR900_CONFIG_ADDR 0x1f030000
  11722. +#define ESR900_CONFIG_SIZE 0x10000
  11723. +
  11724. +#define ESR900_LAN_PHYMASK BIT(0)
  11725. +#define ESR900_WAN_PHYMASK BIT(5)
  11726. +#define ESR900_MDIO_MASK (~(ESR900_LAN_PHYMASK | ESR900_WAN_PHYMASK))
  11727. +
  11728. +static struct gpio_led esr900_leds_gpio[] __initdata = {
  11729. + {
  11730. + .name = "engenius:amber:power",
  11731. + .gpio = ESR900_GPIO_LED_POWER,
  11732. + .active_low = 1,
  11733. + },
  11734. + {
  11735. + .name = "engenius:blue:wlan-2g",
  11736. + .gpio = ESR900_GPIO_LED_WLAN_2G,
  11737. + .active_low = 1,
  11738. + },
  11739. + {
  11740. + .name = "engenius:blue:wps",
  11741. + .gpio = ESR900_GPIO_LED_WPS_BLUE,
  11742. + .active_low = 1,
  11743. + },
  11744. + {
  11745. + .name = "engenius:amber:wps",
  11746. + .gpio = ESR900_GPIO_LED_WPS_AMBER,
  11747. + .active_low = 1,
  11748. + },
  11749. + {
  11750. + .name = "engenius:blue:wlan-5g",
  11751. + .gpio = ESR900_GPIO_LED_WLAN_5G,
  11752. + .active_low = 1,
  11753. + }
  11754. +};
  11755. +
  11756. +static struct gpio_keys_button esr900_gpio_keys[] __initdata = {
  11757. + {
  11758. + .desc = "WPS button",
  11759. + .type = EV_KEY,
  11760. + .code = KEY_WPS_BUTTON,
  11761. + .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL,
  11762. + .gpio = ESR900_GPIO_BTN_WPS,
  11763. + .active_low = 1,
  11764. + },
  11765. + {
  11766. + .desc = "Reset button",
  11767. + .type = EV_KEY,
  11768. + .code = KEY_RESTART,
  11769. + .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL,
  11770. + .gpio = ESR900_GPIO_BTN_RESET,
  11771. + .active_low = 1,
  11772. + },
  11773. +};
  11774. +
  11775. +static struct ar8327_pad_cfg esr900_ar8327_pad0_cfg = {
  11776. + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
  11777. + .mode = AR8327_PAD_MAC_RGMII,
  11778. + .txclk_delay_en = true,
  11779. + .rxclk_delay_en = true,
  11780. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  11781. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  11782. +};
  11783. +
  11784. +static struct ar8327_pad_cfg esr900_ar8327_pad6_cfg = {
  11785. + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
  11786. + .mode = AR8327_PAD_MAC_SGMII,
  11787. + .rxclk_delay_en = true,
  11788. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
  11789. +};
  11790. +
  11791. +static struct ar8327_platform_data esr900_ar8327_data = {
  11792. + .pad0_cfg = &esr900_ar8327_pad0_cfg,
  11793. + .pad6_cfg = &esr900_ar8327_pad6_cfg,
  11794. + .port0_cfg = {
  11795. + .force_link = 1,
  11796. + .speed = AR8327_PORT_SPEED_1000,
  11797. + .duplex = 1,
  11798. + .txpause = 1,
  11799. + .rxpause = 1,
  11800. + },
  11801. + .port6_cfg = {
  11802. + .force_link = 1,
  11803. + .speed = AR8327_PORT_SPEED_1000,
  11804. + .duplex = 1,
  11805. + .txpause = 1,
  11806. + .rxpause = 1,
  11807. + },
  11808. +};
  11809. +
  11810. +static struct mdio_board_info esr900_mdio0_info[] = {
  11811. + {
  11812. + .bus_id = "ag71xx-mdio.0",
  11813. + .phy_addr = 0,
  11814. + .platform_data = &esr900_ar8327_data,
  11815. + },
  11816. +};
  11817. +
  11818. +static void __init esr900_setup(void)
  11819. +{
  11820. + const char *config = (char *) KSEG1ADDR(ESR900_CONFIG_ADDR);
  11821. + u8 *art = (u8 *) KSEG1ADDR(ESR900_CALDATA_ADDR);
  11822. + u8 lan_mac[ETH_ALEN];
  11823. + u8 wlan0_mac[ETH_ALEN];
  11824. + u8 wlan1_mac[ETH_ALEN];
  11825. +
  11826. + if (ath79_nvram_parse_mac_addr(config, ESR900_CONFIG_SIZE,
  11827. + "ethaddr=", lan_mac) == 0) {
  11828. + ath79_init_local_mac(ath79_eth0_data.mac_addr, lan_mac);
  11829. + ath79_init_mac(wlan0_mac, lan_mac, 0);
  11830. + ath79_init_mac(wlan1_mac, lan_mac, 1);
  11831. + } else {
  11832. + pr_err("could not find ethaddr in u-boot environment\n");
  11833. + }
  11834. +
  11835. + ath79_register_m25p80(NULL);
  11836. +
  11837. + ath79_register_leds_gpio(-1, ARRAY_SIZE(esr900_leds_gpio),
  11838. + esr900_leds_gpio);
  11839. + ath79_register_gpio_keys_polled(-1, ESR900_KEYS_POLL_INTERVAL,
  11840. + ARRAY_SIZE(esr900_gpio_keys),
  11841. + esr900_gpio_keys);
  11842. +
  11843. + ath79_register_usb();
  11844. +
  11845. + ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac);
  11846. +
  11847. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  11848. +
  11849. + ath79_register_mdio(0, 0x0);
  11850. +
  11851. + mdiobus_register_board_info(esr900_mdio0_info,
  11852. + ARRAY_SIZE(esr900_mdio0_info));
  11853. +
  11854. + /* GMAC0 is connected to the RMGII interface */
  11855. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  11856. + ath79_eth0_data.phy_mask = ESR900_LAN_PHYMASK;
  11857. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  11858. +
  11859. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  11860. + ath79_register_eth(0);
  11861. +
  11862. + /* GMAC1 is connected to the SGMII interface */
  11863. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  11864. + ath79_eth1_data.speed = SPEED_1000;
  11865. + ath79_eth1_data.duplex = DUPLEX_FULL;
  11866. +
  11867. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  11868. + ath79_register_eth(1);
  11869. +
  11870. + ap91_pci_init(art + ESR900_PCIE_CALDATA_OFFSET, wlan1_mac);
  11871. +}
  11872. +
  11873. +MIPS_MACHINE(ATH79_MACH_ESR900, "ESR900", "EnGenius ESR900", esr900_setup);
  11874. +
  11875. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ew-dorin.c linux-4.1.43/arch/mips/ath79/mach-ew-dorin.c
  11876. --- linux-4.1.43.orig/arch/mips/ath79/mach-ew-dorin.c 1970-01-01 01:00:00.000000000 +0100
  11877. +++ linux-4.1.43/arch/mips/ath79/mach-ew-dorin.c 2017-08-06 20:02:15.000000000 +0200
  11878. @@ -0,0 +1,150 @@
  11879. +/*
  11880. + * EW Dorin board support
  11881. + * (based on Atheros Ref. Design AP121)
  11882. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  11883. + * Copyright (C) 2012-2015 Embedded Wireless GmbH www.80211.de
  11884. + *
  11885. + * This program is free software; you can redistribute it and/or modify it
  11886. + * under the terms of the GNU General Public License version 2 as published
  11887. + * by the Free Software Foundation.
  11888. + */
  11889. +
  11890. +#include <asm/mach-ath79/ath79.h>
  11891. +#include <asm/mach-ath79/ar71xx_regs.h>
  11892. +
  11893. +#include "dev-eth.h"
  11894. +#include "dev-gpio-buttons.h"
  11895. +#include "dev-leds-gpio.h"
  11896. +#include "dev-m25p80.h"
  11897. +#include "dev-spi.h"
  11898. +#include "dev-usb.h"
  11899. +#include "dev-wmac.h"
  11900. +#include "machtypes.h"
  11901. +
  11902. +#define DORIN_KEYS_POLL_INTERVAL 20 /* msecs */
  11903. +#define DORIN_KEYS_DEBOUNCE_INTERVAL (3 * DORIN_KEYS_POLL_INTERVAL)
  11904. +
  11905. +#define DORIN_CALDATA_OFFSET 0x1000
  11906. +#define DORIN_WMAC_MAC_OFFSET 0x1002
  11907. +
  11908. +#define DORIN_GPIO_LED_21 21
  11909. +#define DORIN_GPIO_LED_22 22
  11910. +#define DORIN_GPIO_LED_STATUS 23
  11911. +
  11912. +#define DORIN_GPIO_BTN_JUMPSTART 11
  11913. +#define DORIN_GPIO_BTN_RESET 6
  11914. +
  11915. +static struct gpio_led dorin_leds_gpio[] __initdata = {
  11916. + {
  11917. + .name = "dorin:green:led21",
  11918. + .gpio = DORIN_GPIO_LED_21,
  11919. + .active_low = 1,
  11920. + },
  11921. + {
  11922. + .name = "dorin:green:led22",
  11923. + .gpio = DORIN_GPIO_LED_22,
  11924. + .active_low = 1,
  11925. + },
  11926. + {
  11927. + .name = "dorin:green:status",
  11928. + .gpio = DORIN_GPIO_LED_STATUS,
  11929. + .active_low = 1,
  11930. + },
  11931. +};
  11932. +
  11933. +static struct gpio_keys_button dorin_gpio_keys[] __initdata = {
  11934. + {
  11935. + .desc = "jumpstart button",
  11936. + .type = EV_KEY,
  11937. + .code = KEY_WPS_BUTTON,
  11938. + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL,
  11939. + .gpio = DORIN_GPIO_BTN_JUMPSTART,
  11940. + .active_low = 1,
  11941. + },
  11942. + {
  11943. + .desc = "reset button",
  11944. + .type = EV_KEY,
  11945. + .code = KEY_RESTART,
  11946. + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL,
  11947. + .gpio = DORIN_GPIO_BTN_RESET,
  11948. + .active_low = 0,
  11949. + }
  11950. +};
  11951. +
  11952. +static void __init ew_dorin_setup(void)
  11953. +{
  11954. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  11955. + static u8 mac[6];
  11956. +
  11957. + ath79_register_m25p80(NULL);
  11958. +
  11959. + ath79_register_usb();
  11960. +
  11961. + if (ar93xx_wmac_read_mac_address(mac)) {
  11962. + ath79_register_wmac(NULL, NULL);
  11963. + } else {
  11964. + ath79_register_wmac(art + DORIN_CALDATA_OFFSET,
  11965. + art + DORIN_WMAC_MAC_OFFSET);
  11966. + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac));
  11967. + }
  11968. +
  11969. + mac[3] |= 0x40;
  11970. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  11971. +
  11972. + ath79_register_mdio(0, 0x0);
  11973. +
  11974. + /* LAN ports */
  11975. + ath79_register_eth(1);
  11976. +
  11977. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio),
  11978. + dorin_leds_gpio);
  11979. + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL,
  11980. + ARRAY_SIZE(dorin_gpio_keys),
  11981. + dorin_gpio_keys);
  11982. +}
  11983. +
  11984. +MIPS_MACHINE(ATH79_MACH_EW_DORIN, "EW-DORIN", "EmbWir-Dorin",
  11985. + ew_dorin_setup);
  11986. +
  11987. +
  11988. +static void __init ew_dorin_router_setup(void)
  11989. +{
  11990. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  11991. + static u8 mac[6];
  11992. +
  11993. + ath79_register_m25p80(NULL);
  11994. +
  11995. + ath79_register_usb();
  11996. +
  11997. + if (ar93xx_wmac_read_mac_address(mac)) {
  11998. + ath79_register_wmac(NULL, NULL);
  11999. + } else {
  12000. + ath79_register_wmac(art + DORIN_CALDATA_OFFSET,
  12001. + art + DORIN_WMAC_MAC_OFFSET);
  12002. + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac));
  12003. + }
  12004. +
  12005. + mac[3] |= 0x40;
  12006. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  12007. +
  12008. + mac[3] &= 0x3F;
  12009. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  12010. + ath79_setup_ar933x_phy4_switch(true, true);
  12011. +
  12012. + ath79_register_mdio(0, 0x0);
  12013. +
  12014. + /* LAN ports */
  12015. + ath79_register_eth(1);
  12016. +
  12017. + /* WAN port */
  12018. + ath79_register_eth(0);
  12019. +
  12020. + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio),
  12021. + dorin_leds_gpio);
  12022. + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL,
  12023. + ARRAY_SIZE(dorin_gpio_keys),
  12024. + dorin_gpio_keys);
  12025. +}
  12026. +
  12027. +MIPS_MACHINE(ATH79_MACH_EW_DORIN_ROUTER, "EW-DORIN-ROUTER",
  12028. + "EmbWir-Dorin-Router", ew_dorin_router_setup);
  12029. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-f9k1115v2.c linux-4.1.43/arch/mips/ath79/mach-f9k1115v2.c
  12030. --- linux-4.1.43.orig/arch/mips/ath79/mach-f9k1115v2.c 1970-01-01 01:00:00.000000000 +0100
  12031. +++ linux-4.1.43/arch/mips/ath79/mach-f9k1115v2.c 2017-08-06 20:02:15.000000000 +0200
  12032. @@ -0,0 +1,190 @@
  12033. +/*
  12034. + * Belkin AC1750DB (F9K1115V2) board support
  12035. + *
  12036. + * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
  12037. + * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
  12038. + *
  12039. + * This program is free software; you can redistribute it and/or modify it
  12040. + * under the terms of the GNU General Public License version 2 as published
  12041. + * by the Free Software Foundation.
  12042. + */
  12043. +
  12044. +#include <linux/gpio.h>
  12045. +#include <linux/platform_device.h>
  12046. +#include <linux/ar8216_platform.h>
  12047. +
  12048. +#include <asm/mach-ath79/ar71xx_regs.h>
  12049. +
  12050. +#include "common.h"
  12051. +#include "pci.h"
  12052. +#include "dev-gpio-buttons.h"
  12053. +#include "dev-eth.h"
  12054. +#include "dev-leds-gpio.h"
  12055. +#include "dev-m25p80.h"
  12056. +#include "dev-usb.h"
  12057. +#include "dev-wmac.h"
  12058. +#include "machtypes.h"
  12059. +
  12060. +#define F9K1115V2_GPIO_LED_USB2 4
  12061. +#define F9K1115V2_GPIO_LED_WPS_AMBER 14
  12062. +#define F9K1115V2_GPIO_LED_STATUS_AMBER 15
  12063. +#define F9K1115V2_GPIO_LED_WPS_BLUE 19
  12064. +#define F9K1115V2_GPIO_LED_STATUS_BLUE 20
  12065. +
  12066. +#define F9K1115V2_GPIO_BTN_WPS 16
  12067. +#define F9K1115V2_GPIO_BTN_RESET 17
  12068. +
  12069. +#define F9K1115V2_GPIO_USB2_POWER 21
  12070. +
  12071. +#define F9K1115V2_KEYS_POLL_INTERVAL 20 /* msecs */
  12072. +#define F9K1115V2_KEYS_DEBOUNCE_INTERVAL (3 * F9K1115V2_KEYS_POLL_INTERVAL)
  12073. +
  12074. +#define F9K1115V2_WAN_MAC_OFFSET 0
  12075. +#define F9K1115V2_LAN_MAC_OFFSET 6
  12076. +#define F9K1115V2_WMAC_CALDATA_OFFSET 0x1000
  12077. +#define F9K1115V2_PCIE_CALDATA_OFFSET 0x5000
  12078. +
  12079. +static struct gpio_led f9k1115v2_leds_gpio[] __initdata = {
  12080. + {
  12081. + .name = "belkin:amber:status",
  12082. + .gpio = F9K1115V2_GPIO_LED_STATUS_AMBER,
  12083. + .active_low = 1,
  12084. + },
  12085. + {
  12086. + .name = "belkin:blue:status",
  12087. + .gpio = F9K1115V2_GPIO_LED_STATUS_BLUE,
  12088. + .active_low = 1,
  12089. + },
  12090. + {
  12091. + .name = "belkin:blue:wps",
  12092. + .gpio = F9K1115V2_GPIO_LED_WPS_BLUE,
  12093. + .active_low = 1,
  12094. + },
  12095. + {
  12096. + .name = "belkin:amber:wps",
  12097. + .gpio = F9K1115V2_GPIO_LED_WPS_AMBER,
  12098. + .active_low = 1,
  12099. + },
  12100. + {
  12101. + .name = "belkin:green:usb2",
  12102. + .gpio = F9K1115V2_GPIO_LED_USB2,
  12103. + .active_low = 1,
  12104. + },
  12105. +};
  12106. +
  12107. +static struct gpio_keys_button f9k1115v2_gpio_keys[] __initdata = {
  12108. + {
  12109. + .desc = "Reset button",
  12110. + .type = EV_KEY,
  12111. + .code = KEY_RESTART,
  12112. + .debounce_interval = F9K1115V2_KEYS_DEBOUNCE_INTERVAL,
  12113. + .gpio = F9K1115V2_GPIO_BTN_RESET,
  12114. + .active_low = 1,
  12115. + },
  12116. + {
  12117. + .desc = "WPS button",
  12118. + .type = EV_KEY,
  12119. + .code = KEY_WPS_BUTTON,
  12120. + .debounce_interval = F9K1115V2_KEYS_DEBOUNCE_INTERVAL,
  12121. + .gpio = F9K1115V2_GPIO_BTN_WPS,
  12122. + .active_low = 1,
  12123. + },
  12124. +};
  12125. +
  12126. +static struct ar8327_pad_cfg f9k1115v2_ar8327_pad0_cfg = {
  12127. + /* Use the RGMII interface for the GMAC0 of the AR8337 switch */
  12128. + .mode = AR8327_PAD_MAC_RGMII,
  12129. + .txclk_delay_en = true,
  12130. + .rxclk_delay_en = true,
  12131. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  12132. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  12133. + .mac06_exchange_en = true,
  12134. +};
  12135. +
  12136. +static struct ar8327_pad_cfg f9k1115v2_ar8327_pad6_cfg = {
  12137. + /* Use the SGMII interface for the GMAC6 of the AR8337 switch */
  12138. + .mode = AR8327_PAD_MAC_SGMII,
  12139. + .rxclk_delay_en = true,
  12140. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
  12141. +};
  12142. +
  12143. +static struct ar8327_platform_data f9k1115v2_ar8327_data = {
  12144. + .pad0_cfg = &f9k1115v2_ar8327_pad0_cfg,
  12145. + .pad6_cfg = &f9k1115v2_ar8327_pad6_cfg,
  12146. + .port0_cfg = {
  12147. + .force_link = 1,
  12148. + .speed = AR8327_PORT_SPEED_1000,
  12149. + .duplex = 1,
  12150. + .txpause = 1,
  12151. + .rxpause = 1,
  12152. + },
  12153. + .port6_cfg = {
  12154. + .force_link = 1,
  12155. + .speed = AR8327_PORT_SPEED_1000,
  12156. + .duplex = 1,
  12157. + .txpause = 1,
  12158. + .rxpause = 1,
  12159. + },
  12160. +};
  12161. +
  12162. +static struct mdio_board_info f9k1115v2_mdio0_info[] = {
  12163. + {
  12164. + .bus_id = "ag71xx-mdio.0",
  12165. + .phy_addr = 0,
  12166. + .platform_data = &f9k1115v2_ar8327_data,
  12167. + },
  12168. +};
  12169. +
  12170. +static void __init f9k1115v2_setup(void)
  12171. +{
  12172. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  12173. +
  12174. + ath79_register_m25p80(NULL);
  12175. +
  12176. + ath79_register_leds_gpio(-1, ARRAY_SIZE(f9k1115v2_leds_gpio),
  12177. + f9k1115v2_leds_gpio);
  12178. + ath79_register_gpio_keys_polled(-1, F9K1115V2_KEYS_POLL_INTERVAL,
  12179. + ARRAY_SIZE(f9k1115v2_gpio_keys),
  12180. + f9k1115v2_gpio_keys);
  12181. +
  12182. + ath79_register_wmac(art + F9K1115V2_WMAC_CALDATA_OFFSET, NULL);
  12183. +
  12184. + ath79_register_mdio(0, 0x0);
  12185. + mdiobus_register_board_info(f9k1115v2_mdio0_info,
  12186. + ARRAY_SIZE(f9k1115v2_mdio0_info));
  12187. +
  12188. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  12189. +
  12190. + ath79_init_mac(ath79_eth0_data.mac_addr,
  12191. + art + F9K1115V2_WAN_MAC_OFFSET, 0);
  12192. +
  12193. + ath79_init_mac(ath79_eth1_data.mac_addr,
  12194. + art + F9K1115V2_LAN_MAC_OFFSET, 0);
  12195. +
  12196. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  12197. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  12198. +
  12199. + /* GMAC0 is connected to the RMGII interface */
  12200. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  12201. + ath79_eth0_data.phy_mask = BIT(0);
  12202. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  12203. +
  12204. + ath79_register_eth(0);
  12205. +
  12206. + /* GMAC1 is connected to the SGMII interface */
  12207. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  12208. + ath79_eth1_data.speed = SPEED_1000;
  12209. + ath79_eth1_data.duplex = DUPLEX_FULL;
  12210. +
  12211. + ath79_register_eth(1);
  12212. +
  12213. + ath79_register_pci();
  12214. +
  12215. + ath79_register_usb();
  12216. + gpio_request_one(F9K1115V2_GPIO_USB2_POWER,
  12217. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  12218. + "USB2 power");
  12219. +}
  12220. +
  12221. +MIPS_MACHINE(ATH79_MACH_F9K1115V2, "F9K1115V2", "Belkin AC1750DB",
  12222. + f9k1115v2_setup);
  12223. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-gl-ar150.c linux-4.1.43/arch/mips/ath79/mach-gl-ar150.c
  12224. --- linux-4.1.43.orig/arch/mips/ath79/mach-gl-ar150.c 1970-01-01 01:00:00.000000000 +0100
  12225. +++ linux-4.1.43/arch/mips/ath79/mach-gl-ar150.c 2017-08-06 20:02:15.000000000 +0200
  12226. @@ -0,0 +1,125 @@
  12227. +/*
  12228. + * GL_ar150 board support
  12229. + *
  12230. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  12231. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  12232. + * Copyright (C) 2013 alzhao <alzhao@gmail.com>
  12233. + * Copyright (C) 2014 Michel Stempin <michel.stempin@wanadoo.fr>
  12234. + *
  12235. + * This program is free software; you can redistribute it and/or modify it
  12236. + * under the terms of the GNU General Public License version 2 as published
  12237. + * by the Free Software Foundation.
  12238. +*/
  12239. +
  12240. +#include <linux/gpio.h>
  12241. +
  12242. +#include <asm/mach-ath79/ath79.h>
  12243. +
  12244. +#include "dev-eth.h"
  12245. +#include "dev-gpio-buttons.h"
  12246. +#include "dev-leds-gpio.h"
  12247. +#include "dev-m25p80.h"
  12248. +#include "dev-usb.h"
  12249. +#include "dev-wmac.h"
  12250. +#include "machtypes.h"
  12251. +
  12252. +#define GL_AR150_GPIO_LED_WLAN 0
  12253. +#define GL_AR150_GPIO_LED_LAN 13
  12254. +#define GL_AR150_GPIO_LED_WAN 15
  12255. +
  12256. +#define GL_AR150_GPIO_BIN_USB 6
  12257. +#define GL_AR150_GPIO_BTN_MANUAL 7
  12258. +#define GL_AR150_GPIO_BTN_AUTO 8
  12259. +#define GL_AR150_GPIO_BTN_RESET 11
  12260. +
  12261. +#define GL_AR150_KEYS_POLL_INTERVAL 20 /* msecs */
  12262. +#define GL_AR150_KEYS_DEBOUNCE_INTERVAL (3 * GL_AR150_KEYS_POLL_INTERVAL)
  12263. +
  12264. +#define GL_AR150_MAC0_OFFSET 0x0000
  12265. +#define GL_AR150_MAC1_OFFSET 0x0000
  12266. +#define GL_AR150_CALDATA_OFFSET 0x1000
  12267. +#define GL_AR150_WMAC_MAC_OFFSET 0x0000
  12268. +
  12269. +static struct gpio_led gl_ar150_leds_gpio[] __initdata = {
  12270. + {
  12271. + .name = "gl_ar150:wlan",
  12272. + .gpio = GL_AR150_GPIO_LED_WLAN,
  12273. + .active_low = 0,
  12274. + },
  12275. + {
  12276. + .name = "gl_ar150:lan",
  12277. + .gpio = GL_AR150_GPIO_LED_LAN,
  12278. + .active_low = 0,
  12279. + },
  12280. + {
  12281. + .name = "gl_ar150:wan",
  12282. + .gpio = GL_AR150_GPIO_LED_WAN,
  12283. + .active_low = 0,
  12284. + .default_state = 1,
  12285. + },
  12286. +};
  12287. +
  12288. +static struct gpio_keys_button gl_ar150_gpio_keys[] __initdata = {
  12289. + {
  12290. + .desc = "BTN_7",
  12291. + .type = EV_KEY,
  12292. + .code = BTN_7,
  12293. + .debounce_interval = GL_AR150_KEYS_DEBOUNCE_INTERVAL,
  12294. + .gpio = GL_AR150_GPIO_BTN_MANUAL,
  12295. + .active_low = 0,
  12296. + },
  12297. + {
  12298. + .desc = "BTN_8",
  12299. + .type = EV_KEY,
  12300. + .code = BTN_8,
  12301. + .debounce_interval = GL_AR150_KEYS_DEBOUNCE_INTERVAL,
  12302. + .gpio = GL_AR150_GPIO_BTN_AUTO,
  12303. + .active_low = 0,
  12304. + },
  12305. + {
  12306. + .desc = "reset",
  12307. + .type = EV_KEY,
  12308. + .code = KEY_RESTART,
  12309. + .debounce_interval = GL_AR150_KEYS_DEBOUNCE_INTERVAL,
  12310. + .gpio = GL_AR150_GPIO_BTN_RESET,
  12311. + .active_low = 0,
  12312. + },
  12313. +};
  12314. +
  12315. +static void __init gl_ar150_setup(void)
  12316. +{
  12317. +
  12318. + /* ART base address */
  12319. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  12320. +
  12321. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  12322. + ath79_setup_ar933x_phy4_switch(false, false);
  12323. +
  12324. + /* register flash. */
  12325. + ath79_register_m25p80(NULL);
  12326. +
  12327. + /* register gpio LEDs and keys */
  12328. + ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_ar150_leds_gpio),
  12329. + gl_ar150_leds_gpio);
  12330. + ath79_register_gpio_keys_polled(-1, GL_AR150_KEYS_POLL_INTERVAL,
  12331. + ARRAY_SIZE(gl_ar150_gpio_keys),
  12332. + gl_ar150_gpio_keys);
  12333. +
  12334. + /* enable usb */
  12335. + gpio_request_one(GL_AR150_GPIO_BIN_USB,
  12336. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  12337. + "USB power");
  12338. + ath79_register_usb();
  12339. +
  12340. + /* register eth0 as WAN, eth1 as LAN */
  12341. + ath79_init_mac(ath79_eth0_data.mac_addr, art+GL_AR150_MAC0_OFFSET, 0);
  12342. + ath79_init_mac(ath79_eth1_data.mac_addr, art+GL_AR150_MAC1_OFFSET, 0);
  12343. + ath79_register_mdio(0, 0x0);
  12344. + ath79_register_eth(0);
  12345. + ath79_register_eth(1);
  12346. +
  12347. + /* register wireless mac with cal data */
  12348. + ath79_register_wmac(art + GL_AR150_CALDATA_OFFSET, art + GL_AR150_WMAC_MAC_OFFSET);
  12349. +}
  12350. +
  12351. +MIPS_MACHINE(ATH79_MACH_GL_AR150, "GL-AR150", "GL AR150",gl_ar150_setup);
  12352. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-gl-ar300.c linux-4.1.43/arch/mips/ath79/mach-gl-ar300.c
  12353. --- linux-4.1.43.orig/arch/mips/ath79/mach-gl-ar300.c 1970-01-01 01:00:00.000000000 +0100
  12354. +++ linux-4.1.43/arch/mips/ath79/mach-gl-ar300.c 2017-08-06 20:02:15.000000000 +0200
  12355. @@ -0,0 +1,103 @@
  12356. +/*
  12357. + * Domino board support
  12358. + *
  12359. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  12360. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  12361. + * Copyright (C) 2013 alzhao <alzhao@gmail.com>
  12362. + * Copyright (C) 2014 Michel Stempin <michel.stempin@wanadoo.fr>
  12363. + *
  12364. + * This program is free software; you can redistribute it and/or modify it
  12365. + * under the terms of the GNU General Public License version 2 as published
  12366. + * by the Free Software Foundation.
  12367. +*/
  12368. +
  12369. +#include <linux/gpio.h>
  12370. +#include <linux/platform_device.h>
  12371. +#include <linux/ath9k_platform.h>
  12372. +#include <asm/mach-ath79/ar71xx_regs.h>
  12373. +#include <asm/mach-ath79/ath79.h>
  12374. +
  12375. +#include "common.h"
  12376. +#include "dev-eth.h"
  12377. +#include "dev-gpio-buttons.h"
  12378. +#include "dev-leds-gpio.h"
  12379. +#include "dev-m25p80.h"
  12380. +#include "dev-usb.h"
  12381. +#include "dev-wmac.h"
  12382. +#include "machtypes.h"
  12383. +
  12384. +#define GL_AR300_GPIO_LED_WLAN 13
  12385. +#define GL_AR300_GPIO_LED_WAN 14
  12386. +#define GL_AR300_GPIO_BTN_RESET 16
  12387. +
  12388. +
  12389. +#define GL_AR300_KEYS_POLL_INTERVAL 20 /* msecs */
  12390. +#define GL_AR300_KEYS_DEBOUNCE_INTERVAL (3 * GL_AR300_KEYS_POLL_INTERVAL)
  12391. +
  12392. +#define GL_AR300_MAC0_OFFSET 0x0000
  12393. +#define GL_AR300_MAC1_OFFSET 0x0000
  12394. +#define GL_AR300_CALDATA_OFFSET 0x1000
  12395. +#define GL_AR300_WMAC_MAC_OFFSET 0x0000
  12396. +
  12397. +static struct gpio_led gl_ar300_leds_gpio[] __initdata = {
  12398. + {
  12399. + .name = "gl_ar300:wlan",
  12400. + .gpio = GL_AR300_GPIO_LED_WLAN,
  12401. + .active_low = 1,
  12402. + },
  12403. + {
  12404. + .name = "gl_ar300:wan",
  12405. + .gpio = GL_AR300_GPIO_LED_WAN,
  12406. + .active_low = 1,
  12407. + },
  12408. +};
  12409. +
  12410. +static struct gpio_keys_button gl_ar300_gpio_keys[] __initdata = {
  12411. + {
  12412. + .desc = "reset",
  12413. + .type = EV_KEY,
  12414. + .code = KEY_RESTART,
  12415. + .debounce_interval = GL_AR300_KEYS_DEBOUNCE_INTERVAL,
  12416. + .gpio = GL_AR300_GPIO_BTN_RESET,
  12417. + .active_low = 1,
  12418. + },
  12419. +};
  12420. +
  12421. +static void __init gl_ar300_setup(void)
  12422. +{
  12423. +
  12424. + /* ART base address */
  12425. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  12426. +
  12427. + /* register flash. */
  12428. + ath79_register_m25p80(NULL);
  12429. +
  12430. + /* register gpio LEDs and keys */
  12431. + ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_ar300_leds_gpio),
  12432. + gl_ar300_leds_gpio);
  12433. + ath79_register_gpio_keys_polled(-1, GL_AR300_KEYS_POLL_INTERVAL,
  12434. + ARRAY_SIZE(gl_ar300_gpio_keys),
  12435. + gl_ar300_gpio_keys);
  12436. +
  12437. + /* enable usb */
  12438. + ath79_register_usb();
  12439. + ath79_register_mdio(1, 0x0);
  12440. +
  12441. + /* register eth0 as WAN, eth1 as LAN */
  12442. + ath79_init_mac(ath79_eth0_data.mac_addr, art+GL_AR300_MAC0_OFFSET, 0);
  12443. + ath79_switch_data.phy4_mii_en = 1;
  12444. + ath79_switch_data.phy_poll_mask = BIT(4);
  12445. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  12446. + ath79_eth0_data.phy_mask = BIT(4);
  12447. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  12448. + ath79_register_eth(0);
  12449. +
  12450. + ath79_init_mac(ath79_eth1_data.mac_addr, art+GL_AR300_MAC1_OFFSET, 0);
  12451. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  12452. + ath79_register_eth(1);
  12453. +
  12454. + /* register wireless mac with cal data */
  12455. + ath79_register_wmac(art + GL_AR300_CALDATA_OFFSET, art + GL_AR300_WMAC_MAC_OFFSET);
  12456. +}
  12457. +
  12458. +MIPS_MACHINE(ATH79_MACH_GL_AR300, "GL-AR300", "GL AR300",gl_ar300_setup);
  12459. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-gl-domino.c linux-4.1.43/arch/mips/ath79/mach-gl-domino.c
  12460. --- linux-4.1.43.orig/arch/mips/ath79/mach-gl-domino.c 1970-01-01 01:00:00.000000000 +0100
  12461. +++ linux-4.1.43/arch/mips/ath79/mach-gl-domino.c 2017-08-06 20:02:15.000000000 +0200
  12462. @@ -0,0 +1,136 @@
  12463. +/*
  12464. + * Domino board support
  12465. + *
  12466. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  12467. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  12468. + * Copyright (C) 2013 alzhao <alzhao@gmail.com>
  12469. + * Copyright (C) 2014 Michel Stempin <michel.stempin@wanadoo.fr>
  12470. + *
  12471. + * This program is free software; you can redistribute it and/or modify it
  12472. + * under the terms of the GNU General Public License version 2 as published
  12473. + * by the Free Software Foundation.
  12474. +*/
  12475. +
  12476. +#include <linux/gpio.h>
  12477. +
  12478. +#include <asm/mach-ath79/ath79.h>
  12479. +
  12480. +#include "dev-eth.h"
  12481. +#include "dev-gpio-buttons.h"
  12482. +#include "dev-leds-gpio.h"
  12483. +#include "dev-m25p80.h"
  12484. +#include "dev-usb.h"
  12485. +#include "dev-wmac.h"
  12486. +#include "machtypes.h"
  12487. +
  12488. +#define DOMINO_GPIO_LED_WLAN 0
  12489. +#define DOMINO_GPIO_LED_WAN 17
  12490. +#define DOMINO_GPIO_LED_USB 1
  12491. +#define DOMINO_GPIO_LED_LAN1 13
  12492. +#define DOMINO_GPIO_LED_LAN2 14
  12493. +#define DOMINO_GPIO_LED_LAN3 15
  12494. +#define DOMINO_GPIO_LED_LAN4 16
  12495. +#define DOMINO_GPIO_LED_SYS 27
  12496. +#define DOMINO_GPIO_LED_WPS 26
  12497. +#define DOMINO_GPIO_USB_POWER 6
  12498. +
  12499. +#define DOMINO_GPIO_BTN_RESET 11
  12500. +#define DOMINO_GPIO_BTN_WPS 20
  12501. +
  12502. +#define DOMINO_KEYS_POLL_INTERVAL 20 /* msecs */
  12503. +#define DOMINO_KEYS_DEBOUNCE_INTERVAL (3 * DOMINO_KEYS_POLL_INTERVAL)
  12504. +
  12505. +#define DOMINO_MAC0_OFFSET 0x0000
  12506. +#define DOMINO_MAC1_OFFSET 0x0000
  12507. +#define DOMINO_CALDATA_OFFSET 0x1000
  12508. +#define DOMINO_WMAC_MAC_OFFSET 0x0000
  12509. +
  12510. +static struct gpio_led domino_leds_gpio[] __initdata = {
  12511. + {
  12512. + .name = "domino:blue:wlan",
  12513. + .gpio = DOMINO_GPIO_LED_WLAN,
  12514. + .active_low = 0,
  12515. + },
  12516. + {
  12517. + .name = "domino:red:wan",
  12518. + .gpio = DOMINO_GPIO_LED_WAN,
  12519. + .active_low = 1,
  12520. + },
  12521. + {
  12522. + .name = "domino:white:usb",
  12523. + .gpio = DOMINO_GPIO_LED_USB,
  12524. + .active_low = 0,
  12525. + },
  12526. + {
  12527. + .name = "domino:green:lan1",
  12528. + .gpio = DOMINO_GPIO_LED_LAN1,
  12529. + .active_low = 0,
  12530. + },
  12531. + {
  12532. + .name = "domino:yellow:wps",
  12533. + .gpio = DOMINO_GPIO_LED_WPS,
  12534. + .active_low = 1,
  12535. + },
  12536. + {
  12537. + .name = "domino:orange:sys",
  12538. + .gpio = DOMINO_GPIO_LED_SYS,
  12539. + .active_low = 1,
  12540. + },
  12541. +};
  12542. +
  12543. +static struct gpio_keys_button domino_gpio_keys[] __initdata = {
  12544. + {
  12545. + .desc = "reset",
  12546. + .type = EV_KEY,
  12547. + .code = KEY_RESTART,
  12548. + .debounce_interval = DOMINO_KEYS_DEBOUNCE_INTERVAL,
  12549. + .gpio = DOMINO_GPIO_BTN_RESET,
  12550. + .active_low = 0,
  12551. + },
  12552. + {
  12553. + .desc = "wps",
  12554. + .type = EV_KEY,
  12555. + .code = KEY_WPS_BUTTON,
  12556. + .debounce_interval = DOMINO_KEYS_DEBOUNCE_INTERVAL,
  12557. + .gpio = DOMINO_GPIO_BTN_WPS,
  12558. + .active_low = 0,
  12559. + }
  12560. +};
  12561. +
  12562. +static void __init domino_setup(void)
  12563. +{
  12564. +
  12565. + /* ART base address */
  12566. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  12567. +
  12568. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  12569. + ath79_setup_ar933x_phy4_switch(false, false);
  12570. +
  12571. + /* register flash. */
  12572. + ath79_register_m25p80(NULL);
  12573. +
  12574. + /* register gpio LEDs and keys */
  12575. + ath79_register_leds_gpio(-1, ARRAY_SIZE(domino_leds_gpio),
  12576. + domino_leds_gpio);
  12577. + ath79_register_gpio_keys_polled(-1, DOMINO_KEYS_POLL_INTERVAL,
  12578. + ARRAY_SIZE(domino_gpio_keys),
  12579. + domino_gpio_keys);
  12580. +
  12581. + gpio_request_one(DOMINO_GPIO_USB_POWER,
  12582. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  12583. + "USB power");
  12584. + /* enable usb */
  12585. + ath79_register_usb();
  12586. +
  12587. + /* register eth0 as WAN, eth1 as LAN */
  12588. + ath79_init_mac(ath79_eth0_data.mac_addr, art+DOMINO_MAC0_OFFSET, 0);
  12589. + ath79_init_mac(ath79_eth1_data.mac_addr, art+DOMINO_MAC1_OFFSET, 0);
  12590. + ath79_register_mdio(0, 0x0);
  12591. + ath79_register_eth(0);
  12592. + ath79_register_eth(1);
  12593. +
  12594. + /* register wireless mac with cal data */
  12595. + ath79_register_wmac(art + DOMINO_CALDATA_OFFSET, art + DOMINO_WMAC_MAC_OFFSET);
  12596. +}
  12597. +
  12598. +MIPS_MACHINE(ATH79_MACH_GL_DOMINO, "DOMINO", "Domino Pi", domino_setup);
  12599. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-gl-inet.c linux-4.1.43/arch/mips/ath79/mach-gl-inet.c
  12600. --- linux-4.1.43.orig/arch/mips/ath79/mach-gl-inet.c 1970-01-01 01:00:00.000000000 +0100
  12601. +++ linux-4.1.43/arch/mips/ath79/mach-gl-inet.c 2017-08-06 20:02:15.000000000 +0200
  12602. @@ -0,0 +1,104 @@
  12603. +/*
  12604. + * GL-CONNECT iNet board support
  12605. + *
  12606. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  12607. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  12608. + * Copyright (C) 2013 alzhao <alzhao@gmail.com>
  12609. + * Copyright (C) 2014 Michel Stempin <michel.stempin@wanadoo.fr>
  12610. + *
  12611. + * This program is free software; you can redistribute it and/or modify it
  12612. + * under the terms of the GNU General Public License version 2 as published
  12613. + * by the Free Software Foundation.
  12614. + */
  12615. +
  12616. +#include <linux/gpio.h>
  12617. +
  12618. +#include <asm/mach-ath79/ath79.h>
  12619. +
  12620. +#include "dev-eth.h"
  12621. +#include "dev-gpio-buttons.h"
  12622. +#include "dev-leds-gpio.h"
  12623. +#include "dev-m25p80.h"
  12624. +#include "dev-usb.h"
  12625. +#include "dev-wmac.h"
  12626. +#include "machtypes.h"
  12627. +
  12628. +#define GL_INET_GPIO_LED_WLAN 0
  12629. +#define GL_INET_GPIO_LED_LAN 13
  12630. +#define GL_INET_GPIO_BTN_RESET 11
  12631. +
  12632. +#define GL_INET_KEYS_POLL_INTERVAL 20 /* msecs */
  12633. +#define GL_INET_KEYS_DEBOUNCE_INTERVAL (3 * GL_INET_KEYS_POLL_INTERVAL)
  12634. +
  12635. +static const char * gl_inet_part_probes[] = {
  12636. + "tp-link", /* dont change, this will use tplink parser */
  12637. + NULL ,
  12638. +};
  12639. +
  12640. +static struct flash_platform_data gl_inet_flash_data = {
  12641. + .part_probes = gl_inet_part_probes,
  12642. +};
  12643. +
  12644. +static struct gpio_led gl_inet_leds_gpio[] __initdata = {
  12645. + {
  12646. + .name = "gl-connect:red:wlan",
  12647. + .gpio = GL_INET_GPIO_LED_WLAN,
  12648. + .active_low = 0,
  12649. + },
  12650. + {
  12651. + .name = "gl-connect:green:lan",
  12652. + .gpio = GL_INET_GPIO_LED_LAN,
  12653. + .active_low = 0,
  12654. + .default_state = 1,
  12655. + },
  12656. +};
  12657. +
  12658. +static struct gpio_keys_button gl_inet_gpio_keys[] __initdata = {
  12659. + {
  12660. + .desc = "reset",
  12661. + .type = EV_KEY,
  12662. + .code = KEY_RESTART,
  12663. + .debounce_interval = GL_INET_KEYS_DEBOUNCE_INTERVAL,
  12664. + .gpio = GL_INET_GPIO_BTN_RESET,
  12665. + .active_low = 0,
  12666. + }
  12667. +};
  12668. +
  12669. +static void __init gl_inet_setup(void)
  12670. +{
  12671. + /* get the mac address which is stored in the 1st 64k uboot MTD */
  12672. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  12673. +
  12674. + /* get the art address, which is the last 64K. By using
  12675. + 0x1fff1000, it doesn't matter it is 4M, 8M or 16M flash */
  12676. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  12677. +
  12678. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  12679. + ath79_setup_ar933x_phy4_switch(false, false);
  12680. +
  12681. + /* register flash. MTD will use tp-link parser to parser MTD */
  12682. + ath79_register_m25p80(&gl_inet_flash_data);
  12683. +
  12684. + /* register gpio LEDs and keys */
  12685. + ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_inet_leds_gpio),
  12686. + gl_inet_leds_gpio);
  12687. + ath79_register_gpio_keys_polled(-1, GL_INET_KEYS_POLL_INTERVAL,
  12688. + ARRAY_SIZE(gl_inet_gpio_keys),
  12689. + gl_inet_gpio_keys);
  12690. +
  12691. + /* enable usb */
  12692. + ath79_register_usb();
  12693. +
  12694. + /* register eth0 as WAN, eth1 as LAN */
  12695. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  12696. + ath79_register_mdio(0, 0x0);
  12697. + ath79_register_eth(0);
  12698. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  12699. + ath79_register_eth(1);
  12700. +
  12701. + /* register wireless mac with cal data */
  12702. + ath79_register_wmac(ee, mac);
  12703. +}
  12704. +
  12705. +MIPS_MACHINE(ATH79_MACH_GL_INET, "GL-INET", "GL-CONNECT INET v1",
  12706. + gl_inet_setup);
  12707. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-gs-minibox-v1.c linux-4.1.43/arch/mips/ath79/mach-gs-minibox-v1.c
  12708. --- linux-4.1.43.orig/arch/mips/ath79/mach-gs-minibox-v1.c 1970-01-01 01:00:00.000000000 +0100
  12709. +++ linux-4.1.43/arch/mips/ath79/mach-gs-minibox-v1.c 2017-08-06 20:02:15.000000000 +0200
  12710. @@ -0,0 +1,85 @@
  12711. +/*
  12712. + * Gainstrong MiniBox V1.0 board support
  12713. + *
  12714. + *
  12715. + * This program is free software; you can redistribute it and/or modify it
  12716. + * under the terms of the GNU General Public License version 2 as published
  12717. + * by the Free Software Foundation.
  12718. + */
  12719. +
  12720. +#include <linux/gpio.h>
  12721. +
  12722. +#include <asm/mach-ath79/ath79.h>
  12723. +#include <asm/mach-ath79/ar71xx_regs.h>
  12724. +
  12725. +#include "common.h"
  12726. +#include "dev-eth.h"
  12727. +#include "dev-gpio-buttons.h"
  12728. +#include "dev-leds-gpio.h"
  12729. +#include "dev-m25p80.h"
  12730. +#include "dev-usb.h"
  12731. +#include "dev-wmac.h"
  12732. +#include "machtypes.h"
  12733. +
  12734. +#define GS_MINIBOX_V1_GPIO_BTN_RESET 11
  12735. +
  12736. +#define GS_MINIBOX_V1_GPIO_LED_SYSTEM 1
  12737. +
  12738. +#define GS_MINIBOX_V1_KEYS_POLL_INTERVAL 20 /* msecs */
  12739. +#define GS_MINIBOX_V1_KEYS_DEBOUNCE_INTERVAL (3 * GS_MINIBOX_V1_KEYS_POLL_INTERVAL)
  12740. +
  12741. +static const char *gs_minibox_v1_part_probes[] = {
  12742. + "tp-link",
  12743. + NULL,
  12744. +};
  12745. +
  12746. +static struct flash_platform_data gs_minibox_v1_flash_data = {
  12747. + .part_probes = gs_minibox_v1_part_probes,
  12748. +};
  12749. +
  12750. +static struct gpio_led gs_minibox_v1_leds_gpio[] __initdata = {
  12751. + {
  12752. + .name = "minibox-v1:green:system",
  12753. + .gpio = GS_MINIBOX_V1_GPIO_LED_SYSTEM,
  12754. + .active_low = 1,
  12755. + },
  12756. +};
  12757. +
  12758. +static struct gpio_keys_button gs_minibox_v1_gpio_keys[] __initdata = {
  12759. + {
  12760. + .desc = "reset",
  12761. + .type = EV_KEY,
  12762. + .code = KEY_RESTART,
  12763. + .debounce_interval = GS_MINIBOX_V1_KEYS_DEBOUNCE_INTERVAL,
  12764. + .gpio = GS_MINIBOX_V1_GPIO_BTN_RESET,
  12765. + .active_low = 0,
  12766. + },
  12767. +};
  12768. +
  12769. +static void __init gs_minibox_v1_setup(void)
  12770. +{
  12771. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  12772. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  12773. +
  12774. + ath79_register_leds_gpio(-1, ARRAY_SIZE(gs_minibox_v1_leds_gpio),
  12775. + gs_minibox_v1_leds_gpio);
  12776. +
  12777. + ath79_register_gpio_keys_polled(-1, GS_MINIBOX_V1_KEYS_POLL_INTERVAL,
  12778. + ARRAY_SIZE(gs_minibox_v1_gpio_keys),
  12779. + gs_minibox_v1_gpio_keys);
  12780. +
  12781. + ath79_register_usb();
  12782. +
  12783. + ath79_register_m25p80(&gs_minibox_v1_flash_data);
  12784. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  12785. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  12786. +
  12787. + ath79_register_mdio(0, 0x0);
  12788. + ath79_register_eth(1);
  12789. + ath79_register_eth(0);
  12790. +
  12791. + ath79_register_wmac(ee, mac);
  12792. +}
  12793. +
  12794. +MIPS_MACHINE(ATH79_MACH_GS_MINIBOX_V1, "MINIBOX-V1",
  12795. + "MiniBox V1.0", gs_minibox_v1_setup);
  12796. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-gs-oolite.c linux-4.1.43/arch/mips/ath79/mach-gs-oolite.c
  12797. --- linux-4.1.43.orig/arch/mips/ath79/mach-gs-oolite.c 1970-01-01 01:00:00.000000000 +0100
  12798. +++ linux-4.1.43/arch/mips/ath79/mach-gs-oolite.c 2017-08-06 20:02:15.000000000 +0200
  12799. @@ -0,0 +1,103 @@
  12800. +/*
  12801. + * Oolite board support
  12802. + *
  12803. + *
  12804. + * This program is free software; you can redistribute it and/or modify it
  12805. + * under the terms of the GNU General Public License version 2 as published
  12806. + * by the Free Software Foundation.
  12807. + */
  12808. +
  12809. +#include <linux/gpio.h>
  12810. +
  12811. +#include <asm/mach-ath79/ath79.h>
  12812. +#include <asm/mach-ath79/ar71xx_regs.h>
  12813. +
  12814. +#include "common.h"
  12815. +#include "dev-eth.h"
  12816. +#include "dev-gpio-buttons.h"
  12817. +#include "dev-leds-gpio.h"
  12818. +#include "dev-m25p80.h"
  12819. +#include "dev-wmac.h"
  12820. +#include "machtypes.h"
  12821. +#include "dev-usb.h"
  12822. +
  12823. +#define GS_OOLITE_GPIO_BTN6 6
  12824. +#define GS_OOLITE_GPIO_BTN7 7
  12825. +#define GS_OOLITE_GPIO_BTN_RESET 11
  12826. +
  12827. +#define GS_OOLITE_GPIO_LED_SYSTEM 27
  12828. +
  12829. +#define GS_OOLITE_KEYS_POLL_INTERVAL 20 /* msecs */
  12830. +#define GS_OOLITE_KEYS_DEBOUNCE_INTERVAL (3 * GS_OOLITE_KEYS_POLL_INTERVAL)
  12831. +
  12832. +static const char *gs_oolite_part_probes[] = {
  12833. + "tp-link",
  12834. + NULL,
  12835. +};
  12836. +
  12837. +static struct flash_platform_data gs_oolite_flash_data = {
  12838. + .part_probes = gs_oolite_part_probes,
  12839. +};
  12840. +
  12841. +static struct gpio_led gs_oolite_leds_gpio[] __initdata = {
  12842. + {
  12843. + .name = "oolite:red:system",
  12844. + .gpio = GS_OOLITE_GPIO_LED_SYSTEM,
  12845. + .active_low = 1,
  12846. + },
  12847. +};
  12848. +
  12849. +static struct gpio_keys_button gs_oolite_gpio_keys[] __initdata = {
  12850. + {
  12851. + .desc = "reset",
  12852. + .type = EV_KEY,
  12853. + .code = KEY_RESTART,
  12854. + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL,
  12855. + .gpio = GS_OOLITE_GPIO_BTN_RESET,
  12856. + .active_low = 0,
  12857. + },
  12858. + {
  12859. + .desc = "BTN_6",
  12860. + .type = EV_KEY,
  12861. + .code = BTN_6,
  12862. + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL,
  12863. + .gpio = GS_OOLITE_GPIO_BTN6,
  12864. + .active_low = 0,
  12865. + },
  12866. + {
  12867. + .desc = "BTN_7",
  12868. + .type = EV_KEY,
  12869. + .code = BTN_7,
  12870. + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL,
  12871. + .gpio = GS_OOLITE_GPIO_BTN7,
  12872. + .active_low = 0,
  12873. + },
  12874. +};
  12875. +
  12876. +static void __init gs_oolite_setup(void)
  12877. +{
  12878. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  12879. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  12880. +
  12881. + ath79_register_leds_gpio(-1, ARRAY_SIZE(gs_oolite_leds_gpio),
  12882. + gs_oolite_leds_gpio);
  12883. +
  12884. + ath79_register_gpio_keys_polled(-1, GS_OOLITE_KEYS_POLL_INTERVAL,
  12885. + ARRAY_SIZE(gs_oolite_gpio_keys),
  12886. + gs_oolite_gpio_keys);
  12887. +
  12888. + ath79_register_usb();
  12889. +
  12890. + ath79_register_m25p80(&gs_oolite_flash_data);
  12891. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  12892. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  12893. +
  12894. + ath79_register_mdio(0, 0x0);
  12895. + ath79_register_eth(1);
  12896. + ath79_register_eth(0);
  12897. +
  12898. + ath79_register_wmac(ee, mac);
  12899. +}
  12900. +
  12901. +MIPS_MACHINE(ATH79_MACH_GS_OOLITE, "GS-OOLITE",
  12902. + "Oolite V1.0", gs_oolite_setup);
  12903. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-hiwifi-hc6361.c linux-4.1.43/arch/mips/ath79/mach-hiwifi-hc6361.c
  12904. --- linux-4.1.43.orig/arch/mips/ath79/mach-hiwifi-hc6361.c 1970-01-01 01:00:00.000000000 +0100
  12905. +++ linux-4.1.43/arch/mips/ath79/mach-hiwifi-hc6361.c 2017-08-06 20:02:15.000000000 +0200
  12906. @@ -0,0 +1,115 @@
  12907. +/*
  12908. + * HiWiFi HC6361 board support
  12909. + *
  12910. + * Copyright (C) 2012-2013 eric
  12911. + * Copyright (C) 2014 Yousong Zhou <yszhou4tech@gmail.com>
  12912. + *
  12913. + * This program is free software; you can redistribute it and/or modify it
  12914. + * under the terms of the GNU General Public License version 2 as published
  12915. + * by the Free Software Foundation.
  12916. + */
  12917. +
  12918. +#include <linux/gpio.h>
  12919. +#include <linux/proc_fs.h>
  12920. +
  12921. +#include <asm/mach-ath79/ath79.h>
  12922. +#include <asm/mach-ath79/ar71xx_regs.h>
  12923. +
  12924. +#include "common.h"
  12925. +#include "dev-eth.h"
  12926. +#include "dev-gpio-buttons.h"
  12927. +#include "dev-leds-gpio.h"
  12928. +#include "dev-m25p80.h"
  12929. +#include "dev-usb.h"
  12930. +#include "dev-wmac.h"
  12931. +#include "machtypes.h"
  12932. +
  12933. +#define HIWIFI_HC6361_GPIO_LED_WLAN_2P4 0 /* 2.4G WLAN LED */
  12934. +#define HIWIFI_HC6361_GPIO_LED_SYSTEM 1 /* System LED */
  12935. +#define HIWIFI_HC6361_GPIO_LED_INTERNET 27 /* Internet LED */
  12936. +
  12937. +#define HIWIFI_HC6361_GPIO_USBPOWER 20 /* USB power control */
  12938. +#define HIWIFI_HC6361_GPIO_BTN_RST 11 /* Reset button */
  12939. +
  12940. +#define HIWIFI_HC6361_KEYS_POLL_INTERVAL 20 /* msecs */
  12941. +#define HIWIFI_HC6361_KEYS_DEBOUNCE_INTERVAL \
  12942. + (3 * HIWIFI_HC6361_KEYS_POLL_INTERVAL)
  12943. +
  12944. +static struct gpio_led hiwifi_leds_gpio[] __initdata = {
  12945. + {
  12946. + .name = "hiwifi:blue:wlan-2p4",
  12947. + .gpio = HIWIFI_HC6361_GPIO_LED_WLAN_2P4,
  12948. + .active_low = 1,
  12949. + }, {
  12950. + .name = "hiwifi:blue:system",
  12951. + .gpio = HIWIFI_HC6361_GPIO_LED_SYSTEM,
  12952. + .active_low = 1,
  12953. + }, {
  12954. + .name = "hiwifi:blue:internet",
  12955. + .gpio = HIWIFI_HC6361_GPIO_LED_INTERNET,
  12956. + .active_low = 1,
  12957. + }
  12958. +};
  12959. +
  12960. +static struct gpio_keys_button hiwifi_gpio_keys[] __initdata = {
  12961. + {
  12962. + .desc = "reset",
  12963. + .type = EV_KEY,
  12964. + .code = KEY_RESTART,
  12965. + .debounce_interval = HIWIFI_HC6361_KEYS_DEBOUNCE_INTERVAL,
  12966. + .gpio = HIWIFI_HC6361_GPIO_BTN_RST,
  12967. + .active_low = 1,
  12968. + }
  12969. +};
  12970. +
  12971. +static void __init get_mac_from_bdinfo(u8 *mac, void *bdinfo)
  12972. +{
  12973. + if (sscanf(bdinfo, "fac_mac = %2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx",
  12974. + &mac[0], &mac[1], &mac[2], &mac[3],
  12975. + &mac[4], &mac[5]) == 6) {
  12976. + return;
  12977. + }
  12978. +
  12979. + printk(KERN_WARNING "Parsing MAC address failed.\n");
  12980. + memcpy(mac, "\x00\xba\xbe\x00\x00\x00", 6);
  12981. +}
  12982. +
  12983. +static void __init hiwifi_hc6361_setup(void)
  12984. +{
  12985. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  12986. + u8 mac[6];
  12987. +
  12988. + ath79_setup_ar933x_phy4_switch(false, false);
  12989. +
  12990. + ath79_register_m25p80(NULL);
  12991. + ath79_gpio_function_enable(
  12992. + AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  12993. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  12994. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  12995. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  12996. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  12997. +
  12998. + ath79_register_leds_gpio(-1, ARRAY_SIZE(hiwifi_leds_gpio),
  12999. + hiwifi_leds_gpio);
  13000. + ath79_register_gpio_keys_polled(-1, HIWIFI_HC6361_KEYS_POLL_INTERVAL,
  13001. + ARRAY_SIZE(hiwifi_gpio_keys),
  13002. + hiwifi_gpio_keys);
  13003. + gpio_request_one(HIWIFI_HC6361_GPIO_USBPOWER,
  13004. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  13005. + "USB power");
  13006. + ath79_register_usb();
  13007. +
  13008. + get_mac_from_bdinfo(mac, (void *) KSEG1ADDR(0x1f010180));
  13009. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  13010. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  13011. +
  13012. + ath79_register_mdio(0, 0x0);
  13013. +
  13014. + ath79_register_eth(1);
  13015. + ath79_register_eth(0);
  13016. +
  13017. + ath79_register_wmac(ee, mac);
  13018. +}
  13019. +
  13020. +MIPS_MACHINE(ATH79_MACH_HIWIFI_HC6361, "HiWiFi-HC6361",
  13021. + "HiWiFi HC6361", hiwifi_hc6361_setup);
  13022. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-hornet-ub.c linux-4.1.43/arch/mips/ath79/mach-hornet-ub.c
  13023. --- linux-4.1.43.orig/arch/mips/ath79/mach-hornet-ub.c 1970-01-01 01:00:00.000000000 +0100
  13024. +++ linux-4.1.43/arch/mips/ath79/mach-hornet-ub.c 2017-08-06 20:02:15.000000000 +0200
  13025. @@ -0,0 +1,142 @@
  13026. +/*
  13027. + * ALFA NETWORK Hornet-UB board support
  13028. + *
  13029. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  13030. + *
  13031. + * This program is free software; you can redistribute it and/or modify it
  13032. + * under the terms of the GNU General Public License version 2 as published
  13033. + * by the Free Software Foundation.
  13034. + */
  13035. +
  13036. +#include <linux/gpio.h>
  13037. +
  13038. +#include <asm/mach-ath79/ath79.h>
  13039. +#include <asm/mach-ath79/ar71xx_regs.h>
  13040. +
  13041. +#include "common.h"
  13042. +#include "dev-eth.h"
  13043. +#include "dev-gpio-buttons.h"
  13044. +#include "dev-leds-gpio.h"
  13045. +#include "dev-m25p80.h"
  13046. +#include "dev-usb.h"
  13047. +#include "dev-wmac.h"
  13048. +#include "machtypes.h"
  13049. +
  13050. +#define HORNET_UB_GPIO_LED_WLAN 0
  13051. +#define HORNET_UB_GPIO_LED_USB 1
  13052. +#define HORNET_UB_GPIO_LED_LAN 13
  13053. +#define HORNET_UB_GPIO_LED_WAN 17
  13054. +#define HORNET_UB_GPIO_LED_WPS 27
  13055. +#define HORNET_UB_GPIO_EXT_LNA 28
  13056. +
  13057. +#define HORNET_UB_GPIO_BTN_RESET 12
  13058. +#define HORNET_UB_GPIO_BTN_WPS 11
  13059. +
  13060. +#define HORNET_UB_GPIO_USB_POWER 26
  13061. +
  13062. +#define HORNET_UB_KEYS_POLL_INTERVAL 20 /* msecs */
  13063. +#define HORNET_UB_KEYS_DEBOUNCE_INTERVAL (3 * HORNET_UB_KEYS_POLL_INTERVAL)
  13064. +
  13065. +#define HORNET_UB_MAC0_OFFSET 0x0000
  13066. +#define HORNET_UB_MAC1_OFFSET 0x0006
  13067. +#define HORNET_UB_CALDATA_OFFSET 0x1000
  13068. +
  13069. +static struct gpio_led hornet_ub_leds_gpio[] __initdata = {
  13070. + {
  13071. + .name = "alfa:blue:lan",
  13072. + .gpio = HORNET_UB_GPIO_LED_LAN,
  13073. + .active_low = 0,
  13074. + },
  13075. + {
  13076. + .name = "alfa:blue:usb",
  13077. + .gpio = HORNET_UB_GPIO_LED_USB,
  13078. + .active_low = 0,
  13079. + },
  13080. + {
  13081. + .name = "alfa:blue:wan",
  13082. + .gpio = HORNET_UB_GPIO_LED_WAN,
  13083. + .active_low = 1,
  13084. + },
  13085. + {
  13086. + .name = "alfa:blue:wlan",
  13087. + .gpio = HORNET_UB_GPIO_LED_WLAN,
  13088. + .active_low = 0,
  13089. + },
  13090. + {
  13091. + .name = "alfa:blue:wps",
  13092. + .gpio = HORNET_UB_GPIO_LED_WPS,
  13093. + .active_low = 1,
  13094. + },
  13095. +};
  13096. +
  13097. +static struct gpio_keys_button hornet_ub_gpio_keys[] __initdata = {
  13098. + {
  13099. + .desc = "WPS button",
  13100. + .type = EV_KEY,
  13101. + .code = KEY_WPS_BUTTON,
  13102. + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL,
  13103. + .gpio = HORNET_UB_GPIO_BTN_WPS,
  13104. + .active_low = 0,
  13105. + },
  13106. + {
  13107. + .desc = "Reset button",
  13108. + .type = EV_KEY,
  13109. + .code = KEY_RESTART,
  13110. + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL,
  13111. + .gpio = HORNET_UB_GPIO_BTN_RESET,
  13112. + .active_low = 1,
  13113. + }
  13114. +};
  13115. +
  13116. +static void __init hornet_ub_gpio_setup(void)
  13117. +{
  13118. + u32 t;
  13119. +
  13120. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  13121. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  13122. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  13123. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  13124. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  13125. +
  13126. + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  13127. + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
  13128. + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
  13129. +
  13130. + gpio_request_one(HORNET_UB_GPIO_USB_POWER,
  13131. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  13132. + "USB power");
  13133. + gpio_request_one(HORNET_UB_GPIO_EXT_LNA,
  13134. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  13135. + "external LNA0");
  13136. +
  13137. +}
  13138. +
  13139. +static void __init hornet_ub_setup(void)
  13140. +{
  13141. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  13142. +
  13143. + hornet_ub_gpio_setup();
  13144. +
  13145. + ath79_register_m25p80(NULL);
  13146. + ath79_register_leds_gpio(-1, ARRAY_SIZE(hornet_ub_leds_gpio),
  13147. + hornet_ub_leds_gpio);
  13148. + ath79_register_gpio_keys_polled(-1, HORNET_UB_KEYS_POLL_INTERVAL,
  13149. + ARRAY_SIZE(hornet_ub_gpio_keys),
  13150. + hornet_ub_gpio_keys);
  13151. +
  13152. + ath79_init_mac(ath79_eth1_data.mac_addr,
  13153. + art + HORNET_UB_MAC0_OFFSET, 0);
  13154. + ath79_init_mac(ath79_eth0_data.mac_addr,
  13155. + art + HORNET_UB_MAC1_OFFSET, 0);
  13156. +
  13157. + ath79_register_mdio(0, 0x0);
  13158. +
  13159. + ath79_register_eth(1);
  13160. + ath79_register_eth(0);
  13161. +
  13162. + ath79_register_wmac(art + HORNET_UB_CALDATA_OFFSET, NULL);
  13163. + ath79_register_usb();
  13164. +}
  13165. +
  13166. +MIPS_MACHINE(ATH79_MACH_HORNET_UB, "HORNET-UB", "ALFA NETWORK Hornet-UB",
  13167. + hornet_ub_setup);
  13168. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ja76pf.c linux-4.1.43/arch/mips/ath79/mach-ja76pf.c
  13169. --- linux-4.1.43.orig/arch/mips/ath79/mach-ja76pf.c 1970-01-01 01:00:00.000000000 +0100
  13170. +++ linux-4.1.43/arch/mips/ath79/mach-ja76pf.c 2017-08-06 20:02:15.000000000 +0200
  13171. @@ -0,0 +1,190 @@
  13172. +/*
  13173. + * jjPlus JA76PF board support
  13174. + */
  13175. +
  13176. +#include <linux/i2c.h>
  13177. +#include <linux/i2c-gpio.h>
  13178. +#include <linux/platform_device.h>
  13179. +
  13180. +#include <asm/mach-ath79/ath79.h>
  13181. +
  13182. +#include "dev-eth.h"
  13183. +#include "dev-gpio-buttons.h"
  13184. +#include "dev-leds-gpio.h"
  13185. +#include "dev-m25p80.h"
  13186. +#include "dev-usb.h"
  13187. +#include "machtypes.h"
  13188. +#include "pci.h"
  13189. +
  13190. +#define JA76PF_KEYS_POLL_INTERVAL 20 /* msecs */
  13191. +#define JA76PF_KEYS_DEBOUNCE_INTERVAL (3 * JA76PF_KEYS_POLL_INTERVAL)
  13192. +
  13193. +#define JA76PF_GPIO_I2C_SCL 0
  13194. +#define JA76PF_GPIO_I2C_SDA 1
  13195. +#define JA76PF_GPIO_LED_1 5
  13196. +#define JA76PF_GPIO_LED_2 4
  13197. +#define JA76PF_GPIO_LED_3 3
  13198. +#define JA76PF_GPIO_BTN_RESET 11
  13199. +
  13200. +static struct gpio_led ja76pf_leds_gpio[] __initdata = {
  13201. + {
  13202. + .name = "jjplus:green:led1",
  13203. + .gpio = JA76PF_GPIO_LED_1,
  13204. + .active_low = 1,
  13205. + }, {
  13206. + .name = "jjplus:green:led2",
  13207. + .gpio = JA76PF_GPIO_LED_2,
  13208. + .active_low = 1,
  13209. + }, {
  13210. + .name = "jjplus:green:led3",
  13211. + .gpio = JA76PF_GPIO_LED_3,
  13212. + .active_low = 1,
  13213. + }
  13214. +};
  13215. +
  13216. +static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = {
  13217. + {
  13218. + .desc = "reset",
  13219. + .type = EV_KEY,
  13220. + .code = KEY_RESTART,
  13221. + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL,
  13222. + .gpio = JA76PF_GPIO_BTN_RESET,
  13223. + .active_low = 1,
  13224. + }
  13225. +};
  13226. +
  13227. +static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = {
  13228. + .sda_pin = JA76PF_GPIO_I2C_SDA,
  13229. + .scl_pin = JA76PF_GPIO_I2C_SCL,
  13230. +};
  13231. +
  13232. +static struct platform_device ja76pf_i2c_gpio_device = {
  13233. + .name = "i2c-gpio",
  13234. + .id = 0,
  13235. + .dev = {
  13236. + .platform_data = &ja76pf_i2c_gpio_data,
  13237. + }
  13238. +};
  13239. +
  13240. +static const char *ja76pf_part_probes[] = {
  13241. + "RedBoot",
  13242. + NULL,
  13243. +};
  13244. +
  13245. +static struct flash_platform_data ja76pf_flash_data = {
  13246. + .part_probes = ja76pf_part_probes,
  13247. +};
  13248. +
  13249. +#define JA76PF_WAN_PHYMASK (1 << 4)
  13250. +#define JA76PF_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3))
  13251. +#define JA76PF_MDIO_PHYMASK (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK)
  13252. +
  13253. +static void __init ja76pf_init(void)
  13254. +{
  13255. + ath79_register_m25p80(&ja76pf_flash_data);
  13256. +
  13257. + ath79_register_mdio(0, ~JA76PF_MDIO_PHYMASK);
  13258. +
  13259. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  13260. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  13261. + ath79_eth0_data.phy_mask = JA76PF_LAN_PHYMASK;
  13262. +
  13263. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  13264. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  13265. + ath79_eth1_data.phy_mask = JA76PF_WAN_PHYMASK;
  13266. + ath79_eth1_data.speed = SPEED_1000;
  13267. + ath79_eth1_data.duplex = DUPLEX_FULL;
  13268. +
  13269. + ath79_register_eth(0);
  13270. + ath79_register_eth(1);
  13271. +
  13272. + platform_device_register(&ja76pf_i2c_gpio_device);
  13273. +
  13274. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio),
  13275. + ja76pf_leds_gpio);
  13276. +
  13277. + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
  13278. + ARRAY_SIZE(ja76pf_gpio_keys),
  13279. + ja76pf_gpio_keys);
  13280. +
  13281. + ath79_register_usb();
  13282. + ath79_register_pci();
  13283. +}
  13284. +
  13285. +MIPS_MACHINE(ATH79_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init);
  13286. +
  13287. +#define JA76PF2_GPIO_LED_D2 5
  13288. +#define JA76PF2_GPIO_LED_D3 4
  13289. +#define JA76PF2_GPIO_LED_D4 3
  13290. +#define JA76PF2_GPIO_BTN_RESET 7
  13291. +#define JA76PF2_GPIO_BTN_WPS 8
  13292. +
  13293. +static struct gpio_led ja76pf2_leds_gpio[] __initdata = {
  13294. + {
  13295. + .name = "jjplus:green:led1",
  13296. + .gpio = JA76PF2_GPIO_LED_D2,
  13297. + .active_low = 1,
  13298. + }, {
  13299. + .name = "jjplus:green:led2",
  13300. + .gpio = JA76PF2_GPIO_LED_D3,
  13301. + .active_low = 0,
  13302. + }, {
  13303. + .name = "jjplus:green:led3",
  13304. + .gpio = JA76PF2_GPIO_LED_D4,
  13305. + .active_low = 0,
  13306. + }
  13307. +};
  13308. +
  13309. +static struct gpio_keys_button ja76pf2_gpio_keys[] __initdata = {
  13310. + {
  13311. + .desc = "reset",
  13312. + .type = EV_KEY,
  13313. + .code = KEY_RESTART,
  13314. + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL,
  13315. + .gpio = JA76PF2_GPIO_BTN_RESET,
  13316. + .active_low = 1,
  13317. + },
  13318. + {
  13319. + .desc = "wps",
  13320. + .type = EV_KEY,
  13321. + .code = KEY_WPS_BUTTON,
  13322. + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL,
  13323. + .gpio = JA76PF2_GPIO_BTN_WPS,
  13324. + .active_low = 1,
  13325. + },
  13326. +};
  13327. +
  13328. +#define JA76PF2_LAN_PHYMASK BIT(0)
  13329. +#define JA76PF2_WAN_PHYMASK BIT(4)
  13330. +#define JA76PF2_MDIO_PHYMASK (JA76PF2_LAN_PHYMASK | JA76PF2_WAN_PHYMASK)
  13331. +
  13332. +static void __init ja76pf2_init(void)
  13333. +{
  13334. + ath79_register_m25p80(&ja76pf_flash_data);
  13335. +
  13336. + ath79_register_mdio(0, ~JA76PF2_MDIO_PHYMASK);
  13337. +
  13338. + /* MAC0 is connected to the CPU port of the AR8316 switch */
  13339. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  13340. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  13341. + ath79_eth0_data.phy_mask = BIT(0);
  13342. +
  13343. + /* MAC1 is connected to the PHY4 of the AR8316 switch */
  13344. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  13345. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  13346. + ath79_eth1_data.phy_mask = BIT(4);
  13347. +
  13348. + ath79_register_eth(0);
  13349. + ath79_register_eth(1);
  13350. +
  13351. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf2_leds_gpio),
  13352. + ja76pf2_leds_gpio);
  13353. +
  13354. + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
  13355. + ARRAY_SIZE(ja76pf2_gpio_keys),
  13356. + ja76pf2_gpio_keys);
  13357. +
  13358. + ath79_register_pci();
  13359. +}
  13360. +
  13361. +MIPS_MACHINE(ATH79_MACH_JA76PF2, "JA76PF2", "jjPlus JA76PF2", ja76pf2_init);
  13362. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-jwap003.c linux-4.1.43/arch/mips/ath79/mach-jwap003.c
  13363. --- linux-4.1.43.orig/arch/mips/ath79/mach-jwap003.c 1970-01-01 01:00:00.000000000 +0100
  13364. +++ linux-4.1.43/arch/mips/ath79/mach-jwap003.c 2017-08-06 20:02:15.000000000 +0200
  13365. @@ -0,0 +1,95 @@
  13366. +/*
  13367. + * jjPlus JWAP003 board support
  13368. + *
  13369. + */
  13370. +
  13371. +#include <linux/i2c.h>
  13372. +#include <linux/i2c-gpio.h>
  13373. +#include <linux/platform_device.h>
  13374. +
  13375. +#include <asm/mach-ath79/ath79.h>
  13376. +
  13377. +#include "dev-eth.h"
  13378. +#include "dev-m25p80.h"
  13379. +#include "dev-gpio-buttons.h"
  13380. +#include "dev-usb.h"
  13381. +#include "machtypes.h"
  13382. +#include "pci.h"
  13383. +
  13384. +#define JWAP003_KEYS_POLL_INTERVAL 20 /* msecs */
  13385. +#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL)
  13386. +
  13387. +#define JWAP003_GPIO_WPS 11
  13388. +#define JWAP003_GPIO_I2C_SCL 0
  13389. +#define JWAP003_GPIO_I2C_SDA 1
  13390. +
  13391. +static struct gpio_keys_button jwap003_gpio_keys[] __initdata = {
  13392. + {
  13393. + .desc = "wps",
  13394. + .type = EV_KEY,
  13395. + .code = KEY_WPS_BUTTON,
  13396. + .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL,
  13397. + .gpio = JWAP003_GPIO_WPS,
  13398. + .active_low = 1,
  13399. + }
  13400. +};
  13401. +
  13402. +static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = {
  13403. + .sda_pin = JWAP003_GPIO_I2C_SDA,
  13404. + .scl_pin = JWAP003_GPIO_I2C_SCL,
  13405. +};
  13406. +
  13407. +static struct platform_device jwap003_i2c_gpio_device = {
  13408. + .name = "i2c-gpio",
  13409. + .id = 0,
  13410. + .dev = {
  13411. + .platform_data = &jwap003_i2c_gpio_data,
  13412. + }
  13413. +};
  13414. +
  13415. +static const char *jwap003_part_probes[] = {
  13416. + "RedBoot",
  13417. + NULL,
  13418. +};
  13419. +
  13420. +static struct flash_platform_data jwap003_flash_data = {
  13421. + .part_probes = jwap003_part_probes,
  13422. +};
  13423. +
  13424. +#define JWAP003_WAN_PHYMASK BIT(0)
  13425. +#define JWAP003_LAN_PHYMASK BIT(4)
  13426. +
  13427. +static void __init jwap003_init(void)
  13428. +{
  13429. + ath79_register_m25p80(&jwap003_flash_data);
  13430. +
  13431. + ath79_register_mdio(0, 0x0);
  13432. +
  13433. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  13434. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  13435. + ath79_eth0_data.phy_mask = JWAP003_WAN_PHYMASK;
  13436. + ath79_eth0_data.speed = SPEED_100;
  13437. + ath79_eth0_data.duplex = DUPLEX_FULL;
  13438. + ath79_eth0_data.has_ar8216 = 1;
  13439. +
  13440. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  13441. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  13442. + ath79_eth1_data.phy_mask = JWAP003_LAN_PHYMASK;
  13443. + ath79_eth1_data.speed = SPEED_100;
  13444. + ath79_eth1_data.duplex = DUPLEX_FULL;
  13445. +
  13446. + ath79_register_eth(0);
  13447. + ath79_register_eth(1);
  13448. +
  13449. + platform_device_register(&jwap003_i2c_gpio_device);
  13450. +
  13451. + ath79_register_usb();
  13452. +
  13453. + ath79_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL,
  13454. + ARRAY_SIZE(jwap003_gpio_keys),
  13455. + jwap003_gpio_keys);
  13456. +
  13457. + ath79_register_pci();
  13458. +}
  13459. +
  13460. +MIPS_MACHINE(ATH79_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init);
  13461. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mc-mac1200r.c linux-4.1.43/arch/mips/ath79/mach-mc-mac1200r.c
  13462. --- linux-4.1.43.orig/arch/mips/ath79/mach-mc-mac1200r.c 1970-01-01 01:00:00.000000000 +0100
  13463. +++ linux-4.1.43/arch/mips/ath79/mach-mc-mac1200r.c 2017-08-06 20:02:15.000000000 +0200
  13464. @@ -0,0 +1,155 @@
  13465. +/*
  13466. + * MERCURY MAC1200R board support
  13467. + *
  13468. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  13469. + * Copyright (C) 2013 Gui Iribarren <gui@altermundi.net>
  13470. + *
  13471. + * This program is free software; you can redistribute it and/or modify it
  13472. + * under the terms of the GNU General Public License version 2 as published
  13473. + * by the Free Software Foundation.
  13474. + */
  13475. +
  13476. +#include <linux/pci.h>
  13477. +#include <linux/phy.h>
  13478. +#include <linux/gpio.h>
  13479. +#include <linux/platform_device.h>
  13480. +#include <linux/ath9k_platform.h>
  13481. +#include <linux/ar8216_platform.h>
  13482. +
  13483. +#include <asm/mach-ath79/ar71xx_regs.h>
  13484. +
  13485. +#include "common.h"
  13486. +#include "dev-ap9x-pci.h"
  13487. +#include "dev-eth.h"
  13488. +#include "dev-gpio-buttons.h"
  13489. +#include "dev-leds-gpio.h"
  13490. +#include "dev-m25p80.h"
  13491. +#include "dev-spi.h"
  13492. +#include "dev-wmac.h"
  13493. +#include "machtypes.h"
  13494. +
  13495. +#define MAC1200R_GPIO_LED_WLAN2G 13
  13496. +#define MAC1200R_GPIO_LED_WLAN5G 17
  13497. +#define MAC1200R_GPIO_LED_SYSTEM 14
  13498. +#define MAC1200R_GPIO_LED_WPS 11
  13499. +#define MAC1200R_GPIO_LED_WAN 12
  13500. +#define MAC1200R_GPIO_LED_LAN1 15
  13501. +#define MAC1200R_GPIO_LED_LAN2 21
  13502. +#define MAC1200R_GPIO_LED_LAN3 22
  13503. +#define MAC1200R_GPIO_LED_LAN4 20
  13504. +
  13505. +#define MAC1200R_GPIO_BTN_WPS 16
  13506. +
  13507. +#define MAC1200R_KEYS_POLL_INTERVAL 20 /* msecs */
  13508. +#define MAC1200R_KEYS_DEBOUNCE_INTERVAL (3 * MAC1200R_KEYS_POLL_INTERVAL)
  13509. +
  13510. +#define MAC1200R_MAC0_OFFSET 0
  13511. +#define MAC1200R_MAC1_OFFSET 6
  13512. +#define MAC1200R_WMAC_CALDATA_OFFSET 0x1000
  13513. +#define MAC1200R_PCIE_CALDATA_OFFSET 0x5000
  13514. +
  13515. +static const char *mac1200r_part_probes[] = {
  13516. + "tp-link",
  13517. + NULL,
  13518. +};
  13519. +
  13520. +static struct flash_platform_data mac1200r_flash_data = {
  13521. + .part_probes = mac1200r_part_probes,
  13522. +};
  13523. +
  13524. +static struct gpio_led mac1200r_leds_gpio[] __initdata = {
  13525. + {
  13526. + .name = "mercury:green:wps",
  13527. + .gpio = MAC1200R_GPIO_LED_WPS,
  13528. + .active_low = 1,
  13529. + },
  13530. + {
  13531. + .name = "mercury:green:system",
  13532. + .gpio = MAC1200R_GPIO_LED_SYSTEM,
  13533. + .active_low = 1,
  13534. + },
  13535. + {
  13536. + .name = "mercury:green:wlan2g",
  13537. + .gpio = MAC1200R_GPIO_LED_WLAN2G,
  13538. + .active_low = 1,
  13539. + },
  13540. + {
  13541. + .name = "mercury:green:wlan5g",
  13542. + .gpio = MAC1200R_GPIO_LED_WLAN5G,
  13543. + .active_low = 1,
  13544. + },
  13545. +};
  13546. +
  13547. +static struct gpio_keys_button mac1200r_gpio_keys[] __initdata = {
  13548. + {
  13549. + .desc = "Reset button",
  13550. + .type = EV_KEY,
  13551. + .code = KEY_RESTART,
  13552. + .debounce_interval = MAC1200R_KEYS_DEBOUNCE_INTERVAL,
  13553. + .gpio = MAC1200R_GPIO_BTN_WPS,
  13554. + .active_low = 1,
  13555. + },
  13556. +};
  13557. +
  13558. +
  13559. +static void __init mac1200r_setup(void)
  13560. +{
  13561. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  13562. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  13563. + u8 tmpmac[ETH_ALEN];
  13564. +
  13565. + ath79_register_m25p80(&mac1200r_flash_data);
  13566. +
  13567. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mac1200r_leds_gpio),
  13568. + mac1200r_leds_gpio);
  13569. +
  13570. + ath79_register_gpio_keys_polled(-1, MAC1200R_KEYS_POLL_INTERVAL,
  13571. + ARRAY_SIZE(mac1200r_gpio_keys),
  13572. + mac1200r_gpio_keys);
  13573. +
  13574. + ath79_init_mac(tmpmac, mac, 0);
  13575. + ath79_wmac_disable_5ghz();
  13576. + ath79_register_wmac(art + MAC1200R_WMAC_CALDATA_OFFSET, tmpmac);
  13577. +
  13578. + ath79_init_mac(tmpmac, mac, 1);
  13579. + ap91_pci_init(art + MAC1200R_PCIE_CALDATA_OFFSET, tmpmac);
  13580. +
  13581. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  13582. +
  13583. + ath79_register_mdio(1, 0x0);
  13584. +
  13585. + /* LAN */
  13586. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  13587. +
  13588. + /* GMAC1 is connected to the internal switch */
  13589. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  13590. +
  13591. + ath79_register_eth(1);
  13592. +
  13593. + /* WAN */
  13594. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2);
  13595. +
  13596. + /* GMAC0 is connected to the PHY4 of the internal switch */
  13597. + ath79_switch_data.phy4_mii_en = 1;
  13598. + ath79_switch_data.phy_poll_mask = BIT(4);
  13599. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  13600. + ath79_eth0_data.phy_mask = BIT(4);
  13601. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  13602. +
  13603. + ath79_register_eth(0);
  13604. +
  13605. + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN1,
  13606. + AR934X_GPIO_OUT_LED_LINK3);
  13607. + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN2,
  13608. + AR934X_GPIO_OUT_LED_LINK2);
  13609. + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN3,
  13610. + AR934X_GPIO_OUT_LED_LINK1);
  13611. + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN4,
  13612. + AR934X_GPIO_OUT_LED_LINK0);
  13613. + ath79_gpio_output_select(MAC1200R_GPIO_LED_WAN,
  13614. + AR934X_GPIO_OUT_LED_LINK4);
  13615. +}
  13616. +
  13617. +MIPS_MACHINE(ATH79_MACH_MC_MAC1200R, "MC-MAC1200R",
  13618. + "MERCURY MAC1200R",
  13619. + mac1200r_setup);
  13620. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mr12.c linux-4.1.43/arch/mips/ath79/mach-mr12.c
  13621. --- linux-4.1.43.orig/arch/mips/ath79/mach-mr12.c 1970-01-01 01:00:00.000000000 +0100
  13622. +++ linux-4.1.43/arch/mips/ath79/mach-mr12.c 2017-08-06 20:02:15.000000000 +0200
  13623. @@ -0,0 +1,115 @@
  13624. +/*
  13625. + * Cisco Meraki MR12 board support
  13626. + *
  13627. + * Copyright (C) 2014-2015 Chris Blake <chrisrblake93@gmail.com>
  13628. + *
  13629. + * Based on Atheros AP96 board support configuration
  13630. + *
  13631. + * Copyright (C) 2009 Marco Porsch
  13632. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  13633. + * Copyright (C) 2010 Atheros Communications
  13634. + *
  13635. + * This program is free software; you can redistribute it and/or modify it
  13636. + * under the terms of the GNU General Public License version 2 as published
  13637. + * by the Free Software Foundation.
  13638. + */
  13639. +
  13640. +#include <linux/platform_device.h>
  13641. +#include <linux/delay.h>
  13642. +
  13643. +#include <asm/mach-ath79/ath79.h>
  13644. +
  13645. +#include "dev-ap9x-pci.h"
  13646. +#include "dev-eth.h"
  13647. +#include "dev-gpio-buttons.h"
  13648. +#include "dev-leds-gpio.h"
  13649. +#include "dev-m25p80.h"
  13650. +#include "machtypes.h"
  13651. +
  13652. +#define MR12_GPIO_LED_W4_GREEN 14
  13653. +#define MR12_GPIO_LED_W3_GREEN 13
  13654. +#define MR12_GPIO_LED_W2_GREEN 12
  13655. +#define MR12_GPIO_LED_W1_GREEN 11
  13656. +
  13657. +#define MR12_GPIO_LED_WAN 15
  13658. +
  13659. +#define MR12_GPIO_LED_POWER_ORANGE 16
  13660. +#define MR12_GPIO_LED_POWER_GREEN 17
  13661. +
  13662. +#define MR12_GPIO_BTN_RESET 8
  13663. +#define MR12_KEYS_POLL_INTERVAL 20 /* msecs */
  13664. +#define MR12_KEYS_DEBOUNCE_INTERVAL (3 * MR12_KEYS_POLL_INTERVAL)
  13665. +
  13666. +#define MR12_WAN_PHYMASK BIT(4)
  13667. +
  13668. +#define MR12_WMAC0_MAC_OFFSET 0x120c
  13669. +#define MR12_CALDATA0_OFFSET 0x1000
  13670. +
  13671. +static struct gpio_led MR12_leds_gpio[] __initdata = {
  13672. + {
  13673. + .name = "mr12:green:wan",
  13674. + .gpio = MR12_GPIO_LED_WAN,
  13675. + .active_low = 1,
  13676. + }, {
  13677. + .name = "mr12:orange:power",
  13678. + .gpio = MR12_GPIO_LED_POWER_ORANGE,
  13679. + .active_low = 1,
  13680. + }, {
  13681. + .name = "mr12:green:power",
  13682. + .gpio = MR12_GPIO_LED_POWER_GREEN,
  13683. + .active_low = 1,
  13684. + }, {
  13685. + .name = "mr12:green:wifi4",
  13686. + .gpio = MR12_GPIO_LED_W4_GREEN,
  13687. + .active_low = 1,
  13688. + }, {
  13689. + .name = "mr12:green:wifi3",
  13690. + .gpio = MR12_GPIO_LED_W3_GREEN,
  13691. + .active_low = 1,
  13692. + }, {
  13693. + .name = "mr12:green:wifi2",
  13694. + .gpio = MR12_GPIO_LED_W2_GREEN,
  13695. + .active_low = 1,
  13696. + }, {
  13697. + .name = "mr12:green:wifi1",
  13698. + .gpio = MR12_GPIO_LED_W1_GREEN,
  13699. + .active_low = 1,
  13700. + }
  13701. +};
  13702. +
  13703. +static struct gpio_keys_button MR12_gpio_keys[] __initdata = {
  13704. + {
  13705. + .desc = "reset",
  13706. + .type = EV_KEY,
  13707. + .code = KEY_RESTART,
  13708. + .debounce_interval = MR12_KEYS_DEBOUNCE_INTERVAL,
  13709. + .gpio = MR12_GPIO_BTN_RESET,
  13710. + .active_low = 1,
  13711. + }
  13712. +};
  13713. +
  13714. +static void __init MR12_setup(void)
  13715. +{
  13716. + u8 *mac = (u8 *) KSEG1ADDR(0xbfff0000);
  13717. +
  13718. + ath79_register_mdio(0,0x0);
  13719. +
  13720. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  13721. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  13722. + ath79_eth0_data.phy_mask = MR12_WAN_PHYMASK;
  13723. + ath79_register_eth(0);
  13724. +
  13725. + ath79_register_m25p80(NULL);
  13726. +
  13727. + ath79_register_leds_gpio(-1, ARRAY_SIZE(MR12_leds_gpio),
  13728. + MR12_leds_gpio);
  13729. + ath79_register_gpio_keys_polled(-1, MR12_KEYS_POLL_INTERVAL,
  13730. + ARRAY_SIZE(MR12_gpio_keys),
  13731. + MR12_gpio_keys);
  13732. +
  13733. + ap91_pci_init(mac + MR12_CALDATA0_OFFSET,
  13734. + mac + MR12_WMAC0_MAC_OFFSET);
  13735. +
  13736. +}
  13737. +
  13738. +MIPS_MACHINE(ATH79_MACH_MR12, "MR12", "Meraki MR12", MR12_setup);
  13739. \ No newline at end of file
  13740. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mr16.c linux-4.1.43/arch/mips/ath79/mach-mr16.c
  13741. --- linux-4.1.43.orig/arch/mips/ath79/mach-mr16.c 1970-01-01 01:00:00.000000000 +0100
  13742. +++ linux-4.1.43/arch/mips/ath79/mach-mr16.c 2017-08-06 20:02:15.000000000 +0200
  13743. @@ -0,0 +1,118 @@
  13744. +/*
  13745. + * Cisco Meraki MR16 board support
  13746. + *
  13747. + * Copyright (C) 2015 Chris Blake <chrisrblake93@gmail.com>
  13748. + *
  13749. + * Based on Atheros AP96 board support configuration
  13750. + *
  13751. + * Copyright (C) 2009 Marco Porsch
  13752. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  13753. + * Copyright (C) 2010 Atheros Communications
  13754. + *
  13755. + * This program is free software; you can redistribute it and/or modify it
  13756. + * under the terms of the GNU General Public License version 2 as published
  13757. + * by the Free Software Foundation.
  13758. + */
  13759. +
  13760. +#include <linux/platform_device.h>
  13761. +#include <linux/delay.h>
  13762. +
  13763. +#include <asm/mach-ath79/ath79.h>
  13764. +
  13765. +#include "dev-ap9x-pci.h"
  13766. +#include "dev-eth.h"
  13767. +#include "dev-gpio-buttons.h"
  13768. +#include "dev-leds-gpio.h"
  13769. +#include "dev-m25p80.h"
  13770. +#include "machtypes.h"
  13771. +
  13772. +#define MR16_GPIO_LED_W4_GREEN 3
  13773. +#define MR16_GPIO_LED_W3_GREEN 2
  13774. +#define MR16_GPIO_LED_W2_GREEN 1
  13775. +#define MR16_GPIO_LED_W1_GREEN 0
  13776. +
  13777. +#define MR16_GPIO_LED_WAN 4
  13778. +
  13779. +#define MR16_GPIO_LED_POWER_ORANGE 5
  13780. +#define MR16_GPIO_LED_POWER_GREEN 6
  13781. +
  13782. +#define MR16_GPIO_BTN_RESET 7
  13783. +#define MR16_KEYS_POLL_INTERVAL 20 /* msecs */
  13784. +#define MR16_KEYS_DEBOUNCE_INTERVAL (3 * MR16_KEYS_POLL_INTERVAL)
  13785. +
  13786. +#define MR16_WAN_PHYMASK BIT(0)
  13787. +
  13788. +#define MR16_WMAC0_MAC_OFFSET 0x120c
  13789. +#define MR16_WMAC1_MAC_OFFSET 0x520c
  13790. +#define MR16_CALDATA0_OFFSET 0x1000
  13791. +#define MR16_CALDATA1_OFFSET 0x5000
  13792. +
  13793. +static struct gpio_led MR16_leds_gpio[] __initdata = {
  13794. + {
  13795. + .name = "mr16:green:wan",
  13796. + .gpio = MR16_GPIO_LED_WAN,
  13797. + .active_low = 1,
  13798. + }, {
  13799. + .name = "mr16:orange:power",
  13800. + .gpio = MR16_GPIO_LED_POWER_ORANGE,
  13801. + .active_low = 1,
  13802. + }, {
  13803. + .name = "mr16:green:power",
  13804. + .gpio = MR16_GPIO_LED_POWER_GREEN,
  13805. + .active_low = 1,
  13806. + }, {
  13807. + .name = "mr16:green:wifi4",
  13808. + .gpio = MR16_GPIO_LED_W4_GREEN,
  13809. + .active_low = 1,
  13810. + }, {
  13811. + .name = "mr16:green:wifi3",
  13812. + .gpio = MR16_GPIO_LED_W3_GREEN,
  13813. + .active_low = 1,
  13814. + }, {
  13815. + .name = "mr16:green:wifi2",
  13816. + .gpio = MR16_GPIO_LED_W2_GREEN,
  13817. + .active_low = 1,
  13818. + }, {
  13819. + .name = "mr16:green:wifi1",
  13820. + .gpio = MR16_GPIO_LED_W1_GREEN,
  13821. + .active_low = 1,
  13822. + }
  13823. +};
  13824. +
  13825. +static struct gpio_keys_button MR16_gpio_keys[] __initdata = {
  13826. + {
  13827. + .desc = "reset",
  13828. + .type = EV_KEY,
  13829. + .code = KEY_RESTART,
  13830. + .debounce_interval = MR16_KEYS_DEBOUNCE_INTERVAL,
  13831. + .gpio = MR16_GPIO_BTN_RESET,
  13832. + .active_low = 1,
  13833. + }
  13834. +};
  13835. +
  13836. +static void __init MR16_setup(void)
  13837. +{
  13838. + u8 *mac = (u8 *) KSEG1ADDR(0xbfff0000);
  13839. +
  13840. + ath79_register_mdio(0,0x0);
  13841. +
  13842. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  13843. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  13844. + ath79_eth0_data.phy_mask = MR16_WAN_PHYMASK;
  13845. + ath79_register_eth(0);
  13846. +
  13847. + ath79_register_m25p80(NULL);
  13848. +
  13849. + ath79_register_leds_gpio(-1, ARRAY_SIZE(MR16_leds_gpio),
  13850. + MR16_leds_gpio);
  13851. + ath79_register_gpio_keys_polled(-1, MR16_KEYS_POLL_INTERVAL,
  13852. + ARRAY_SIZE(MR16_gpio_keys),
  13853. + MR16_gpio_keys);
  13854. +
  13855. + ap94_pci_init(mac + MR16_CALDATA0_OFFSET,
  13856. + mac + MR16_WMAC0_MAC_OFFSET,
  13857. + mac + MR16_CALDATA1_OFFSET,
  13858. + mac + MR16_WMAC1_MAC_OFFSET);
  13859. +}
  13860. +
  13861. +MIPS_MACHINE(ATH79_MACH_MR16, "MR16", "Meraki MR16", MR16_setup);
  13862. \ No newline at end of file
  13863. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mr1750.c linux-4.1.43/arch/mips/ath79/mach-mr1750.c
  13864. --- linux-4.1.43.orig/arch/mips/ath79/mach-mr1750.c 1970-01-01 01:00:00.000000000 +0100
  13865. +++ linux-4.1.43/arch/mips/ath79/mach-mr1750.c 2017-08-06 20:02:15.000000000 +0200
  13866. @@ -0,0 +1,129 @@
  13867. +/*
  13868. + * MR1750 board support
  13869. + *
  13870. + * Copyright (c) 2012 Qualcomm Atheros
  13871. + * Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com>
  13872. + *
  13873. + * Permission to use, copy, modify, and/or distribute this software for any
  13874. + * purpose with or without fee is hereby granted, provided that the above
  13875. + * copyright notice and this permission notice appear in all copies.
  13876. + *
  13877. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13878. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13879. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13880. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13881. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13882. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  13883. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  13884. + *
  13885. + */
  13886. +
  13887. +#include <linux/platform_device.h>
  13888. +#include <linux/ar8216_platform.h>
  13889. +
  13890. +#include <asm/mach-ath79/ar71xx_regs.h>
  13891. +
  13892. +#include "common.h"
  13893. +#include "dev-ap9x-pci.h"
  13894. +#include "dev-gpio-buttons.h"
  13895. +#include "dev-eth.h"
  13896. +#include "dev-leds-gpio.h"
  13897. +#include "dev-m25p80.h"
  13898. +#include "dev-wmac.h"
  13899. +#include "machtypes.h"
  13900. +#include "pci.h"
  13901. +
  13902. +#define MR1750_GPIO_LED_LAN 12
  13903. +#define MR1750_GPIO_LED_WLAN_2G 13
  13904. +#define MR1750_GPIO_LED_STATUS_GREEN 19
  13905. +#define MR1750_GPIO_LED_STATUS_RED 21
  13906. +#define MR1750_GPIO_LED_POWER 22
  13907. +#define MR1750_GPIO_LED_WLAN_5G 23
  13908. +
  13909. +#define MR1750_GPIO_BTN_RESET 17
  13910. +
  13911. +#define MR1750_KEYS_POLL_INTERVAL 20 /* msecs */
  13912. +#define MR1750_KEYS_DEBOUNCE_INTERVAL (3 * MR1750_KEYS_POLL_INTERVAL)
  13913. +
  13914. +#define MR1750_MAC0_OFFSET 0
  13915. +#define MR1750_WMAC_CALDATA_OFFSET 0x1000
  13916. +
  13917. +static struct gpio_led mr1750_leds_gpio[] __initdata = {
  13918. + {
  13919. + .name = "mr1750:blue:power",
  13920. + .gpio = MR1750_GPIO_LED_POWER,
  13921. + .active_low = 1,
  13922. + },
  13923. + {
  13924. + .name = "mr1750:blue:wan",
  13925. + .gpio = MR1750_GPIO_LED_LAN,
  13926. + .active_low = 1,
  13927. + },
  13928. + {
  13929. + .name = "mr1750:blue:wlan24",
  13930. + .gpio = MR1750_GPIO_LED_WLAN_2G,
  13931. + .active_low = 1,
  13932. + },
  13933. + {
  13934. + .name = "mr1750:blue:wlan58",
  13935. + .gpio = MR1750_GPIO_LED_WLAN_5G,
  13936. + .active_low = 1,
  13937. + },
  13938. + {
  13939. + .name = "mr1750:green:status",
  13940. + .gpio = MR1750_GPIO_LED_STATUS_GREEN,
  13941. + .active_low = 1,
  13942. + },
  13943. + {
  13944. + .name = "mr1750:red:status",
  13945. + .gpio = MR1750_GPIO_LED_STATUS_RED,
  13946. + .active_low = 1,
  13947. + },
  13948. +};
  13949. +
  13950. +static struct gpio_keys_button mr1750_gpio_keys[] __initdata = {
  13951. + {
  13952. + .desc = "Reset button",
  13953. + .type = EV_KEY,
  13954. + .code = KEY_RESTART,
  13955. + .debounce_interval = MR1750_KEYS_DEBOUNCE_INTERVAL,
  13956. + .gpio = MR1750_GPIO_BTN_RESET,
  13957. + .active_low = 1,
  13958. + },
  13959. +};
  13960. +
  13961. +static void __init mr1750_setup(void)
  13962. +{
  13963. + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
  13964. + u8 mac[6];
  13965. +
  13966. + ath79_eth0_pll_data.pll_1000 = 0xbe000101;
  13967. + ath79_eth0_pll_data.pll_100 = 0x80000101;
  13968. + ath79_eth0_pll_data.pll_10 = 0x80001313;
  13969. +
  13970. + ath79_register_m25p80(NULL);
  13971. +
  13972. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mr1750_leds_gpio),
  13973. + mr1750_leds_gpio);
  13974. + ath79_register_gpio_keys_polled(-1, MR1750_KEYS_POLL_INTERVAL,
  13975. + ARRAY_SIZE(mr1750_gpio_keys),
  13976. + mr1750_gpio_keys);
  13977. +
  13978. + ath79_init_mac(mac, art + MR1750_MAC0_OFFSET, 1);
  13979. + ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
  13980. + ath79_register_pci();
  13981. +
  13982. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  13983. + ath79_register_mdio(0, 0x0);
  13984. +
  13985. + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
  13986. +
  13987. + /* GMAC0 is connected to the RMGII interface */
  13988. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  13989. + ath79_eth0_data.phy_mask = BIT(5);
  13990. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  13991. +
  13992. + ath79_register_eth(0);
  13993. +}
  13994. +
  13995. +MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup);
  13996. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mr600.c linux-4.1.43/arch/mips/ath79/mach-mr600.c
  13997. --- linux-4.1.43.orig/arch/mips/ath79/mach-mr600.c 1970-01-01 01:00:00.000000000 +0100
  13998. +++ linux-4.1.43/arch/mips/ath79/mach-mr600.c 2017-08-06 20:02:15.000000000 +0200
  13999. @@ -0,0 +1,177 @@
  14000. +/*
  14001. + * OpenMesh OM2P board support
  14002. + *
  14003. + * Copyright (C) 2012 Marek Lindner <marek@open-mesh.com>
  14004. + *
  14005. + * Permission to use, copy, modify, and/or distribute this software for any
  14006. + * purpose with or without fee is hereby granted, provided that the above
  14007. + * copyright notice and this permission notice appear in all copies.
  14008. + *
  14009. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14010. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14011. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14012. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14013. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14014. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14015. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14016. + *
  14017. + */
  14018. +
  14019. +#include <linux/pci.h>
  14020. +#include <linux/phy.h>
  14021. +#include <linux/platform_device.h>
  14022. +#include <linux/ath9k_platform.h>
  14023. +
  14024. +#include <asm/mach-ath79/ar71xx_regs.h>
  14025. +
  14026. +#include "common.h"
  14027. +#include "dev-ap9x-pci.h"
  14028. +#include "dev-eth.h"
  14029. +#include "dev-gpio-buttons.h"
  14030. +#include "dev-leds-gpio.h"
  14031. +#include "dev-m25p80.h"
  14032. +#include "dev-spi.h"
  14033. +#include "dev-wmac.h"
  14034. +#include "machtypes.h"
  14035. +
  14036. +#define MR600_GPIO_LED_WLAN58 12
  14037. +#define MR600_GPIO_LED_WPS 13
  14038. +#define MR600_GPIO_LED_POWER 14
  14039. +
  14040. +#define MR600V2_GPIO_LED_WLAN58_RED 12
  14041. +#define MR600V2_GPIO_LED_WPS 13
  14042. +#define MR600V2_GPIO_LED_POWER 14
  14043. +#define MR600V2_GPIO_LED_WLAN24_GREEN 18
  14044. +#define MR600V2_GPIO_LED_WLAN24_YELLOW 19
  14045. +#define MR600V2_GPIO_LED_WLAN24_RED 20
  14046. +#define MR600V2_GPIO_LED_WLAN58_GREEN 21
  14047. +#define MR600V2_GPIO_LED_WLAN58_YELLOW 22
  14048. +
  14049. +#define MR600_GPIO_BTN_RESET 17
  14050. +
  14051. +#define MR600_KEYS_POLL_INTERVAL 20 /* msecs */
  14052. +#define MR600_KEYS_DEBOUNCE_INTERVAL (3 * MR600_KEYS_POLL_INTERVAL)
  14053. +
  14054. +#define MR600_MAC_OFFSET 0
  14055. +#define MR600_WMAC_CALDATA_OFFSET 0x1000
  14056. +#define MR600_PCIE_CALDATA_OFFSET 0x5000
  14057. +
  14058. +static struct gpio_led mr600_leds_gpio[] __initdata = {
  14059. + {
  14060. + .name = "mr600:orange:power",
  14061. + .gpio = MR600_GPIO_LED_POWER,
  14062. + .active_low = 1,
  14063. + },
  14064. + {
  14065. + .name = "mr600:blue:wps",
  14066. + .gpio = MR600_GPIO_LED_WPS,
  14067. + .active_low = 1,
  14068. + },
  14069. + {
  14070. + .name = "mr600:green:wlan58",
  14071. + .gpio = MR600_GPIO_LED_WLAN58,
  14072. + .active_low = 1,
  14073. + },
  14074. +};
  14075. +
  14076. +static struct gpio_led mr600v2_leds_gpio[] __initdata = {
  14077. + {
  14078. + .name = "mr600:blue:power",
  14079. + .gpio = MR600V2_GPIO_LED_POWER,
  14080. + .active_low = 1,
  14081. + },
  14082. + {
  14083. + .name = "mr600:blue:wps",
  14084. + .gpio = MR600V2_GPIO_LED_WPS,
  14085. + .active_low = 1,
  14086. + },
  14087. + {
  14088. + .name = "mr600:red:wlan24",
  14089. + .gpio = MR600V2_GPIO_LED_WLAN24_RED,
  14090. + .active_low = 1,
  14091. + },
  14092. + {
  14093. + .name = "mr600:yellow:wlan24",
  14094. + .gpio = MR600V2_GPIO_LED_WLAN24_YELLOW,
  14095. + .active_low = 1,
  14096. + },
  14097. + {
  14098. + .name = "mr600:green:wlan24",
  14099. + .gpio = MR600V2_GPIO_LED_WLAN24_GREEN,
  14100. + .active_low = 1,
  14101. + },
  14102. + {
  14103. + .name = "mr600:red:wlan58",
  14104. + .gpio = MR600V2_GPIO_LED_WLAN58_RED,
  14105. + .active_low = 1,
  14106. + },
  14107. + {
  14108. + .name = "mr600:yellow:wlan58",
  14109. + .gpio = MR600V2_GPIO_LED_WLAN58_YELLOW,
  14110. + .active_low = 1,
  14111. + },
  14112. + {
  14113. + .name = "mr600:green:wlan58",
  14114. + .gpio = MR600V2_GPIO_LED_WLAN58_GREEN,
  14115. + .active_low = 1,
  14116. + },
  14117. +};
  14118. +
  14119. +static struct gpio_keys_button mr600_gpio_keys[] __initdata = {
  14120. + {
  14121. + .desc = "Reset button",
  14122. + .type = EV_KEY,
  14123. + .code = KEY_RESTART,
  14124. + .debounce_interval = MR600_KEYS_DEBOUNCE_INTERVAL,
  14125. + .gpio = MR600_GPIO_BTN_RESET,
  14126. + .active_low = 1,
  14127. + },
  14128. +};
  14129. +
  14130. +static void __init mr600_base_setup(unsigned num_leds, struct gpio_led *leds)
  14131. +{
  14132. + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
  14133. + u8 mac[6];
  14134. +
  14135. + ath79_register_m25p80(NULL);
  14136. +
  14137. + ath79_register_leds_gpio(-1, num_leds, leds);
  14138. + ath79_register_gpio_keys_polled(-1, MR600_KEYS_POLL_INTERVAL,
  14139. + ARRAY_SIZE(mr600_gpio_keys),
  14140. + mr600_gpio_keys);
  14141. +
  14142. + ath79_init_mac(mac, art + MR600_MAC_OFFSET, 1);
  14143. + ath79_register_wmac(art + MR600_WMAC_CALDATA_OFFSET, mac);
  14144. +
  14145. + ath79_init_mac(mac, art + MR600_MAC_OFFSET, 8);
  14146. + ap91_pci_init(art + MR600_PCIE_CALDATA_OFFSET, mac);
  14147. +
  14148. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  14149. + AR934X_ETH_CFG_SW_ONLY_MODE);
  14150. +
  14151. + ath79_register_mdio(0, 0x0);
  14152. +
  14153. + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR600_MAC_OFFSET, 0);
  14154. +
  14155. + /* GMAC0 is connected to an external PHY */
  14156. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  14157. + ath79_eth0_data.phy_mask = BIT(0);
  14158. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  14159. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  14160. + ath79_register_eth(0);
  14161. +}
  14162. +
  14163. +static void __init mr600_setup(void)
  14164. +{
  14165. + mr600_base_setup(ARRAY_SIZE(mr600_leds_gpio), mr600_leds_gpio);
  14166. + ap9x_pci_setup_wmac_led_pin(0, 0);
  14167. +}
  14168. +
  14169. +MIPS_MACHINE(ATH79_MACH_MR600, "MR600", "OpenMesh MR600", mr600_setup);
  14170. +
  14171. +static void __init mr600v2_setup(void)
  14172. +{
  14173. + mr600_base_setup(ARRAY_SIZE(mr600v2_leds_gpio), mr600v2_leds_gpio);
  14174. +}
  14175. +
  14176. +MIPS_MACHINE(ATH79_MACH_MR600V2, "MR600v2", "OpenMesh MR600v2", mr600v2_setup);
  14177. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mr900.c linux-4.1.43/arch/mips/ath79/mach-mr900.c
  14178. --- linux-4.1.43.orig/arch/mips/ath79/mach-mr900.c 1970-01-01 01:00:00.000000000 +0100
  14179. +++ linux-4.1.43/arch/mips/ath79/mach-mr900.c 2017-08-06 20:02:15.000000000 +0200
  14180. @@ -0,0 +1,140 @@
  14181. +/*
  14182. + * MR900 board support
  14183. + *
  14184. + * Copyright (c) 2012 Qualcomm Atheros
  14185. + * Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com>
  14186. + *
  14187. + * Permission to use, copy, modify, and/or distribute this software for any
  14188. + * purpose with or without fee is hereby granted, provided that the above
  14189. + * copyright notice and this permission notice appear in all copies.
  14190. + *
  14191. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14192. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14193. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14194. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14195. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14196. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14197. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14198. + *
  14199. + */
  14200. +
  14201. +#include <linux/platform_device.h>
  14202. +#include <linux/ar8216_platform.h>
  14203. +#include <linux/ath9k_platform.h>
  14204. +
  14205. +#include <asm/mach-ath79/ar71xx_regs.h>
  14206. +
  14207. +#include "common.h"
  14208. +#include "dev-ap9x-pci.h"
  14209. +#include "dev-gpio-buttons.h"
  14210. +#include "dev-eth.h"
  14211. +#include "dev-leds-gpio.h"
  14212. +#include "dev-m25p80.h"
  14213. +#include "dev-wmac.h"
  14214. +#include "machtypes.h"
  14215. +#include "pci.h"
  14216. +
  14217. +#define MR900_GPIO_LED_LAN 12
  14218. +#define MR900_GPIO_LED_WLAN_2G 13
  14219. +#define MR900_GPIO_LED_STATUS_GREEN 19
  14220. +#define MR900_GPIO_LED_STATUS_RED 21
  14221. +#define MR900_GPIO_LED_POWER 22
  14222. +#define MR900_GPIO_LED_WLAN_5G 23
  14223. +
  14224. +#define MR900_GPIO_BTN_RESET 17
  14225. +
  14226. +#define MR900_KEYS_POLL_INTERVAL 20 /* msecs */
  14227. +#define MR900_KEYS_DEBOUNCE_INTERVAL (3 * MR900_KEYS_POLL_INTERVAL)
  14228. +
  14229. +#define MR900_MAC0_OFFSET 0
  14230. +#define MR900_WMAC_CALDATA_OFFSET 0x1000
  14231. +#define MR900_PCIE_CALDATA_OFFSET 0x5000
  14232. +
  14233. +static struct gpio_led mr900_leds_gpio[] __initdata = {
  14234. + {
  14235. + .name = "mr900:blue:power",
  14236. + .gpio = MR900_GPIO_LED_POWER,
  14237. + .active_low = 1,
  14238. + },
  14239. + {
  14240. + .name = "mr900:blue:wan",
  14241. + .gpio = MR900_GPIO_LED_LAN,
  14242. + .active_low = 1,
  14243. + },
  14244. + {
  14245. + .name = "mr900:blue:wlan24",
  14246. + .gpio = MR900_GPIO_LED_WLAN_2G,
  14247. + .active_low = 1,
  14248. + },
  14249. + {
  14250. + .name = "mr900:blue:wlan58",
  14251. + .gpio = MR900_GPIO_LED_WLAN_5G,
  14252. + .active_low = 1,
  14253. + },
  14254. + {
  14255. + .name = "mr900:green:status",
  14256. + .gpio = MR900_GPIO_LED_STATUS_GREEN,
  14257. + .active_low = 1,
  14258. + },
  14259. + {
  14260. + .name = "mr900:red:status",
  14261. + .gpio = MR900_GPIO_LED_STATUS_RED,
  14262. + .active_low = 1,
  14263. + },
  14264. +};
  14265. +
  14266. +static struct gpio_keys_button mr900_gpio_keys[] __initdata = {
  14267. + {
  14268. + .desc = "Reset button",
  14269. + .type = EV_KEY,
  14270. + .code = KEY_RESTART,
  14271. + .debounce_interval = MR900_KEYS_DEBOUNCE_INTERVAL,
  14272. + .gpio = MR900_GPIO_BTN_RESET,
  14273. + .active_low = 1,
  14274. + },
  14275. +};
  14276. +
  14277. +static void __init mr900_setup(void)
  14278. +{
  14279. + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
  14280. + u8 mac[6], pcie_mac[6];
  14281. + struct ath9k_platform_data *pdata;
  14282. +
  14283. + ath79_eth0_pll_data.pll_1000 = 0xbe000101;
  14284. + ath79_eth0_pll_data.pll_100 = 0x80000101;
  14285. + ath79_eth0_pll_data.pll_10 = 0x80001313;
  14286. +
  14287. + ath79_register_m25p80(NULL);
  14288. +
  14289. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mr900_leds_gpio),
  14290. + mr900_leds_gpio);
  14291. + ath79_register_gpio_keys_polled(-1, MR900_KEYS_POLL_INTERVAL,
  14292. + ARRAY_SIZE(mr900_gpio_keys),
  14293. + mr900_gpio_keys);
  14294. +
  14295. + ath79_init_mac(mac, art + MR900_MAC0_OFFSET, 1);
  14296. + ath79_register_wmac(art + MR900_WMAC_CALDATA_OFFSET, mac);
  14297. + ath79_init_mac(pcie_mac, art + MR900_MAC0_OFFSET, 16);
  14298. + ap91_pci_init(art + MR900_PCIE_CALDATA_OFFSET, pcie_mac);
  14299. + pdata = ap9x_pci_get_wmac_data(0);
  14300. + if (!pdata) {
  14301. + pr_err("mr900: unable to get address of wlan data\n");
  14302. + return;
  14303. + }
  14304. + pdata->use_eeprom = true;
  14305. +
  14306. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  14307. + ath79_register_mdio(0, 0x0);
  14308. +
  14309. + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
  14310. +
  14311. + /* GMAC0 is connected to the RMGII interface */
  14312. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  14313. + ath79_eth0_data.phy_mask = BIT(5);
  14314. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  14315. +
  14316. + ath79_register_eth(0);
  14317. +}
  14318. +
  14319. +MIPS_MACHINE(ATH79_MACH_MR900, "MR900", "OpenMesh MR900", mr900_setup);
  14320. +MIPS_MACHINE(ATH79_MACH_MR900v2, "MR900v2", "OpenMesh MR900v2", mr900_setup);
  14321. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mynet-n600.c linux-4.1.43/arch/mips/ath79/mach-mynet-n600.c
  14322. --- linux-4.1.43.orig/arch/mips/ath79/mach-mynet-n600.c 1970-01-01 01:00:00.000000000 +0100
  14323. +++ linux-4.1.43/arch/mips/ath79/mach-mynet-n600.c 2017-08-06 20:02:15.000000000 +0200
  14324. @@ -0,0 +1,202 @@
  14325. +/*
  14326. + * WD My Net N600 board support
  14327. + *
  14328. + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  14329. + *
  14330. + * This program is free software; you can redistribute it and/or modify it
  14331. + * under the terms of the GNU General Public License version 2 as published
  14332. + * by the Free Software Foundation.
  14333. + */
  14334. +
  14335. +#include <linux/pci.h>
  14336. +#include <linux/phy.h>
  14337. +#include <linux/gpio.h>
  14338. +#include <linux/platform_device.h>
  14339. +#include <linux/ath9k_platform.h>
  14340. +#include <linux/ar8216_platform.h>
  14341. +
  14342. +#include <asm/mach-ath79/ar71xx_regs.h>
  14343. +
  14344. +#include "common.h"
  14345. +#include "dev-ap9x-pci.h"
  14346. +#include "dev-eth.h"
  14347. +#include "dev-gpio-buttons.h"
  14348. +#include "dev-leds-gpio.h"
  14349. +#include "dev-m25p80.h"
  14350. +#include "dev-spi.h"
  14351. +#include "dev-usb.h"
  14352. +#include "dev-wmac.h"
  14353. +#include "machtypes.h"
  14354. +#include "nvram.h"
  14355. +
  14356. +#define MYNET_N600_GPIO_LED_WIFI 0
  14357. +#define MYNET_N600_GPIO_LED_POWER 11
  14358. +#define MYNET_N600_GPIO_LED_INTERNET 12
  14359. +#define MYNET_N600_GPIO_LED_WPS 13
  14360. +
  14361. +#define MYNET_N600_GPIO_LED_LAN1 4
  14362. +#define MYNET_N600_GPIO_LED_LAN2 3
  14363. +#define MYNET_N600_GPIO_LED_LAN3 2
  14364. +#define MYNET_N600_GPIO_LED_LAN4 1
  14365. +
  14366. +#define MYNET_N600_GPIO_BTN_RESET 16
  14367. +#define MYNET_N600_GPIO_BTN_WPS 17
  14368. +
  14369. +#define MYNET_N600_GPIO_EXTERNAL_LNA0 14
  14370. +#define MYNET_N600_GPIO_EXTERNAL_LNA1 15
  14371. +
  14372. +#define MYNET_N600_KEYS_POLL_INTERVAL 20 /* msecs */
  14373. +#define MYNET_N600_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_N600_KEYS_POLL_INTERVAL)
  14374. +
  14375. +#define MYNET_N600_MAC0_OFFSET 0
  14376. +#define MYNET_N600_MAC1_OFFSET 6
  14377. +#define MYNET_N600_WMAC_CALDATA_OFFSET 0x1000
  14378. +#define MYNET_N600_PCIE_CALDATA_OFFSET 0x5000
  14379. +
  14380. +#define MYNET_N600_NVRAM_ADDR 0x1f058010
  14381. +#define MYNET_N600_NVRAM_SIZE 0x7ff0
  14382. +
  14383. +static struct gpio_led mynet_n600_leds_gpio[] __initdata = {
  14384. + {
  14385. + .name = "wd:blue:power",
  14386. + .gpio = MYNET_N600_GPIO_LED_POWER,
  14387. + .active_low = 0,
  14388. + },
  14389. + {
  14390. + .name = "wd:blue:wps",
  14391. + .gpio = MYNET_N600_GPIO_LED_WPS,
  14392. + .active_low = 0,
  14393. + },
  14394. + {
  14395. + .name = "wd:blue:wireless",
  14396. + .gpio = MYNET_N600_GPIO_LED_WIFI,
  14397. + .active_low = 0,
  14398. + },
  14399. + {
  14400. + .name = "wd:blue:internet",
  14401. + .gpio = MYNET_N600_GPIO_LED_INTERNET,
  14402. + .active_low = 0,
  14403. + },
  14404. + {
  14405. + .name = "wd:green:lan1",
  14406. + .gpio = MYNET_N600_GPIO_LED_LAN1,
  14407. + .active_low = 1,
  14408. + },
  14409. + {
  14410. + .name = "wd:green:lan2",
  14411. + .gpio = MYNET_N600_GPIO_LED_LAN2,
  14412. + .active_low = 1,
  14413. + },
  14414. + {
  14415. + .name = "wd:green:lan3",
  14416. + .gpio = MYNET_N600_GPIO_LED_LAN3,
  14417. + .active_low = 1,
  14418. + },
  14419. + {
  14420. + .name = "wd:green:lan4",
  14421. + .gpio = MYNET_N600_GPIO_LED_LAN4,
  14422. + .active_low = 1,
  14423. + },
  14424. +};
  14425. +
  14426. +static struct gpio_keys_button mynet_n600_gpio_keys[] __initdata = {
  14427. + {
  14428. + .desc = "Reset button",
  14429. + .type = EV_KEY,
  14430. + .code = KEY_RESTART,
  14431. + .debounce_interval = MYNET_N600_KEYS_DEBOUNCE_INTERVAL,
  14432. + .gpio = MYNET_N600_GPIO_BTN_RESET,
  14433. + .active_low = 1,
  14434. + },
  14435. + {
  14436. + .desc = "WPS button",
  14437. + .type = EV_KEY,
  14438. + .code = KEY_WPS_BUTTON,
  14439. + .debounce_interval = MYNET_N600_KEYS_DEBOUNCE_INTERVAL,
  14440. + .gpio = MYNET_N600_GPIO_BTN_WPS,
  14441. + .active_low = 1,
  14442. + },
  14443. +};
  14444. +
  14445. +static void mynet_n600_get_mac(const char *name, char *mac)
  14446. +{
  14447. + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N600_NVRAM_ADDR);
  14448. + int err;
  14449. +
  14450. + err = ath79_nvram_parse_mac_addr(nvram, MYNET_N600_NVRAM_SIZE,
  14451. + name, mac);
  14452. + if (err)
  14453. + pr_err("no MAC address found for %s\n", name);
  14454. +}
  14455. +
  14456. +#define MYNET_N600_WAN_PHY_MASK BIT(0)
  14457. +
  14458. +static void __init mynet_n600_setup(void)
  14459. +{
  14460. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  14461. + u8 tmpmac[ETH_ALEN];
  14462. +
  14463. + ath79_register_m25p80(NULL);
  14464. +
  14465. + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN1,
  14466. + AR934X_GPIO_OUT_GPIO);
  14467. + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN2,
  14468. + AR934X_GPIO_OUT_GPIO);
  14469. + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN3,
  14470. + AR934X_GPIO_OUT_GPIO);
  14471. + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN4,
  14472. + AR934X_GPIO_OUT_GPIO);
  14473. + ath79_gpio_output_select(MYNET_N600_GPIO_LED_INTERNET,
  14474. + AR934X_GPIO_OUT_GPIO);
  14475. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n600_leds_gpio),
  14476. + mynet_n600_leds_gpio);
  14477. +
  14478. + ath79_register_gpio_keys_polled(-1, MYNET_N600_KEYS_POLL_INTERVAL,
  14479. + ARRAY_SIZE(mynet_n600_gpio_keys),
  14480. + mynet_n600_gpio_keys);
  14481. +
  14482. + /*
  14483. + * Control signal for external LNAs 0 and 1
  14484. + * Taken from GPL bootloader source:
  14485. + * board/ar7240/db12x/alpha_gpio.c
  14486. + */
  14487. + ath79_wmac_set_ext_lna_gpio(0, MYNET_N600_GPIO_EXTERNAL_LNA0);
  14488. + ath79_wmac_set_ext_lna_gpio(1, MYNET_N600_GPIO_EXTERNAL_LNA1);
  14489. +
  14490. + mynet_n600_get_mac("wlan24mac=", tmpmac);
  14491. + ath79_register_wmac(art + MYNET_N600_WMAC_CALDATA_OFFSET, tmpmac);
  14492. +
  14493. + mynet_n600_get_mac("wlan5mac=", tmpmac);
  14494. + ap91_pci_init(art + MYNET_N600_PCIE_CALDATA_OFFSET, tmpmac);
  14495. +
  14496. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
  14497. + AR934X_ETH_CFG_SW_PHY_SWAP);
  14498. +
  14499. + ath79_register_mdio(1, 0x0);
  14500. +
  14501. + /* LAN */
  14502. + mynet_n600_get_mac("lanmac=", ath79_eth1_data.mac_addr);
  14503. +
  14504. + /* GMAC1 is connected to the internal switch */
  14505. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  14506. +
  14507. + ath79_register_eth(1);
  14508. +
  14509. + /* WAN */
  14510. + mynet_n600_get_mac("wanmac=", ath79_eth0_data.mac_addr);
  14511. +
  14512. + /* GMAC0 is connected to the PHY4 of the internal switch */
  14513. + ath79_switch_data.phy4_mii_en = 1;
  14514. + ath79_switch_data.phy_poll_mask = MYNET_N600_WAN_PHY_MASK;
  14515. +
  14516. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  14517. + ath79_eth0_data.phy_mask = MYNET_N600_WAN_PHY_MASK;
  14518. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  14519. +
  14520. + ath79_register_eth(0);
  14521. +
  14522. + ath79_register_usb();
  14523. +}
  14524. +
  14525. +MIPS_MACHINE(ATH79_MACH_MYNET_N600, "MYNET-N600", "WD My Net N600",
  14526. + mynet_n600_setup);
  14527. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mynet-n750.c linux-4.1.43/arch/mips/ath79/mach-mynet-n750.c
  14528. --- linux-4.1.43.orig/arch/mips/ath79/mach-mynet-n750.c 1970-01-01 01:00:00.000000000 +0100
  14529. +++ linux-4.1.43/arch/mips/ath79/mach-mynet-n750.c 2017-08-06 20:02:15.000000000 +0200
  14530. @@ -0,0 +1,226 @@
  14531. +/*
  14532. + * WD My Net N750 board support
  14533. + *
  14534. + * Copyright (C) 2013 Felix Kaechele <felix@fetzig.org>
  14535. + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  14536. + *
  14537. + * This program is free software; you can redistribute it and/or modify it
  14538. + * under the terms of the GNU General Public License version 2 as published
  14539. + * by the Free Software Foundation.
  14540. + */
  14541. +
  14542. +#include <linux/pci.h>
  14543. +#include <linux/phy.h>
  14544. +#include <linux/gpio.h>
  14545. +#include <linux/delay.h>
  14546. +#include <linux/platform_device.h>
  14547. +#include <linux/ath9k_platform.h>
  14548. +#include <linux/ar8216_platform.h>
  14549. +
  14550. +#include <asm/mach-ath79/ar71xx_regs.h>
  14551. +
  14552. +#include "common.h"
  14553. +#include "dev-ap9x-pci.h"
  14554. +#include "dev-eth.h"
  14555. +#include "dev-gpio-buttons.h"
  14556. +#include "dev-leds-gpio.h"
  14557. +#include "dev-m25p80.h"
  14558. +#include "dev-spi.h"
  14559. +#include "dev-usb.h"
  14560. +#include "dev-wmac.h"
  14561. +#include "machtypes.h"
  14562. +#include "nvram.h"
  14563. +
  14564. +
  14565. +/*
  14566. + * Taken from GPL bootloader source:
  14567. + * board/ar7240/db12x/alpha_gpio.c
  14568. + */
  14569. +#define MYNET_N750_GPIO_LED_WIFI 11
  14570. +#define MYNET_N750_GPIO_LED_INTERNET 12
  14571. +#define MYNET_N750_GPIO_LED_WPS 13
  14572. +#define MYNET_N750_GPIO_LED_POWER 14
  14573. +
  14574. +#define MYNET_N750_GPIO_BTN_RESET 17
  14575. +#define MYNET_N750_GPIO_BTN_WPS 19
  14576. +
  14577. +#define MYNET_N750_GPIO_EXTERNAL_LNA0 15
  14578. +#define MYNET_N750_GPIO_EXTERNAL_LNA1 18
  14579. +
  14580. +#define MYNET_N750_KEYS_POLL_INTERVAL 20 /* msecs */
  14581. +#define MYNET_N750_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_N750_KEYS_POLL_INTERVAL)
  14582. +
  14583. +#define MYNET_N750_WMAC_CALDATA_OFFSET 0x1000
  14584. +#define MYNET_N750_PCIE_CALDATA_OFFSET 0x5000
  14585. +
  14586. +#define MYNET_N750_NVRAM_ADDR 0x1f058010
  14587. +#define MYNET_N750_NVRAM_SIZE 0x7ff0
  14588. +
  14589. +static struct gpio_led mynet_n750_leds_gpio[] __initdata = {
  14590. + {
  14591. + .name = "wd:blue:power",
  14592. + .gpio = MYNET_N750_GPIO_LED_POWER,
  14593. + .active_low = 0,
  14594. + },
  14595. + {
  14596. + .name = "wd:blue:wps",
  14597. + .gpio = MYNET_N750_GPIO_LED_WPS,
  14598. + .active_low = 0,
  14599. + },
  14600. + {
  14601. + .name = "wd:blue:wireless",
  14602. + .gpio = MYNET_N750_GPIO_LED_WIFI,
  14603. + .active_low = 0,
  14604. + },
  14605. + {
  14606. + .name = "wd:blue:internet",
  14607. + .gpio = MYNET_N750_GPIO_LED_INTERNET,
  14608. + .active_low = 0,
  14609. + },
  14610. +};
  14611. +
  14612. +static struct gpio_keys_button mynet_n750_gpio_keys[] __initdata = {
  14613. + {
  14614. + .desc = "Reset button",
  14615. + .type = EV_KEY,
  14616. + .code = KEY_RESTART,
  14617. + .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL,
  14618. + .gpio = MYNET_N750_GPIO_BTN_RESET,
  14619. + .active_low = 1,
  14620. + },
  14621. + {
  14622. + .desc = "WPS button",
  14623. + .type = EV_KEY,
  14624. + .code = KEY_WPS_BUTTON,
  14625. + .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL,
  14626. + .gpio = MYNET_N750_GPIO_BTN_WPS,
  14627. + .active_low = 1,
  14628. + },
  14629. +};
  14630. +
  14631. +static const struct ar8327_led_info mynet_n750_leds_ar8327[] __initconst = {
  14632. + AR8327_LED_INFO(PHY0_0, HW, "wd:green:lan1"),
  14633. + AR8327_LED_INFO(PHY1_0, HW, "wd:green:lan2"),
  14634. + AR8327_LED_INFO(PHY2_0, HW, "wd:green:lan3"),
  14635. + AR8327_LED_INFO(PHY3_0, HW, "wd:green:lan4"),
  14636. + AR8327_LED_INFO(PHY4_0, HW, "wd:green:wan"),
  14637. + AR8327_LED_INFO(PHY0_1, HW, "wd:yellow:lan1"),
  14638. + AR8327_LED_INFO(PHY1_1, HW, "wd:yellow:lan2"),
  14639. + AR8327_LED_INFO(PHY2_1, HW, "wd:yellow:lan3"),
  14640. + AR8327_LED_INFO(PHY3_1, HW, "wd:yellow:lan4"),
  14641. + AR8327_LED_INFO(PHY4_1, HW, "wd:yellow:wan"),
  14642. +};
  14643. +
  14644. +static struct ar8327_pad_cfg mynet_n750_ar8327_pad0_cfg = {
  14645. + .mode = AR8327_PAD_MAC_RGMII,
  14646. + .txclk_delay_en = true,
  14647. + .rxclk_delay_en = true,
  14648. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  14649. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  14650. +};
  14651. +
  14652. +static struct ar8327_led_cfg mynet_n750_ar8327_led_cfg = {
  14653. + .led_ctrl0 = 0xcc35cc35,
  14654. + .led_ctrl1 = 0xca35ca35,
  14655. + .led_ctrl2 = 0xc935c935,
  14656. + .led_ctrl3 = 0x03ffff00,
  14657. + .open_drain = false,
  14658. +};
  14659. +
  14660. +static struct ar8327_platform_data mynet_n750_ar8327_data = {
  14661. + .pad0_cfg = &mynet_n750_ar8327_pad0_cfg,
  14662. + .port0_cfg = {
  14663. + .force_link = 1,
  14664. + .speed = AR8327_PORT_SPEED_1000,
  14665. + .duplex = 1,
  14666. + .txpause = 1,
  14667. + .rxpause = 1,
  14668. + },
  14669. + .led_cfg = &mynet_n750_ar8327_led_cfg,
  14670. + .num_leds = ARRAY_SIZE(mynet_n750_leds_ar8327),
  14671. + .leds = mynet_n750_leds_ar8327,
  14672. +};
  14673. +
  14674. +static struct mdio_board_info mynet_n750_mdio0_info[] = {
  14675. + {
  14676. + .bus_id = "ag71xx-mdio.0",
  14677. + .phy_addr = 0,
  14678. + .platform_data = &mynet_n750_ar8327_data,
  14679. + },
  14680. +};
  14681. +
  14682. +static void mynet_n750_get_mac(const char *name, char *mac)
  14683. +{
  14684. + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N750_NVRAM_ADDR);
  14685. + int err;
  14686. +
  14687. + err = ath79_nvram_parse_mac_addr(nvram, MYNET_N750_NVRAM_SIZE,
  14688. + name, mac);
  14689. + if (err)
  14690. + pr_err("no MAC address found for %s\n", name);
  14691. +}
  14692. +
  14693. +/*
  14694. + * The bootloader on this board powers down all PHYs on the switch
  14695. + * before booting the kernel. We bring all PHYs back up so that they are
  14696. + * discoverable by the mdio bus scan and the switch is detected
  14697. + * correctly.
  14698. + */
  14699. +static void mynet_n750_mdio_fixup(struct mii_bus *bus)
  14700. +{
  14701. + int i;
  14702. +
  14703. + for (i = 0; i < 5; i++)
  14704. + bus->write(bus, i, MII_BMCR,
  14705. + (BMCR_RESET | BMCR_ANENABLE | BMCR_SPEED1000));
  14706. +
  14707. + mdelay(1000);
  14708. +}
  14709. +
  14710. +static void __init mynet_n750_setup(void)
  14711. +{
  14712. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  14713. + u8 tmpmac[ETH_ALEN];
  14714. +
  14715. + ath79_register_m25p80(NULL);
  14716. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio),
  14717. + mynet_n750_leds_gpio);
  14718. + ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL,
  14719. + ARRAY_SIZE(mynet_n750_gpio_keys),
  14720. + mynet_n750_gpio_keys);
  14721. + /*
  14722. + * Control signal for external LNAs 0 and 1
  14723. + * Taken from GPL bootloader source:
  14724. + * board/ar7240/db12x/alpha_gpio.c
  14725. + */
  14726. + ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0);
  14727. + ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1);
  14728. +
  14729. + mynet_n750_get_mac("wlan24mac=", tmpmac);
  14730. + ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac);
  14731. +
  14732. + mynet_n750_get_mac("wlan5mac=", tmpmac);
  14733. + ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac);
  14734. +
  14735. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  14736. +
  14737. + mdiobus_register_board_info(mynet_n750_mdio0_info,
  14738. + ARRAY_SIZE(mynet_n750_mdio0_info));
  14739. +
  14740. + ath79_mdio0_data.reset = mynet_n750_mdio_fixup;
  14741. + ath79_register_mdio(0, 0x0);
  14742. +
  14743. + mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr);
  14744. +
  14745. + /* GMAC0 is connected to an AR8327N switch */
  14746. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  14747. + ath79_eth0_data.phy_mask = BIT(0);
  14748. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  14749. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  14750. + ath79_register_eth(0);
  14751. +
  14752. + ath79_register_usb();
  14753. +}
  14754. +
  14755. +MIPS_MACHINE(ATH79_MACH_MYNET_N750, "MYNET-N750", "WD My Net N750",
  14756. + mynet_n750_setup);
  14757. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mynet-rext.c linux-4.1.43/arch/mips/ath79/mach-mynet-rext.c
  14758. --- linux-4.1.43.orig/arch/mips/ath79/mach-mynet-rext.c 1970-01-01 01:00:00.000000000 +0100
  14759. +++ linux-4.1.43/arch/mips/ath79/mach-mynet-rext.c 2017-08-06 20:02:15.000000000 +0200
  14760. @@ -0,0 +1,208 @@
  14761. +/*
  14762. + * WD My Net WI-FI Range Extender (Codename:Starfish db12x) board support
  14763. + *
  14764. + * Copyright (C) 2013 Christian Lamparter <chunkeey@googlemail.com>
  14765. + *
  14766. + * This program is free software; you can redistribute it and/or modify it
  14767. + * under the terms of the GNU General Public License version 2 as published
  14768. + * by the Free Software Foundation.
  14769. + */
  14770. +
  14771. +#include <linux/pci.h>
  14772. +#include <linux/phy.h>
  14773. +#include <linux/gpio.h>
  14774. +#include <linux/platform_device.h>
  14775. +#include <linux/ath9k_platform.h>
  14776. +#include <linux/ar8216_platform.h>
  14777. +#include <linux/platform_data/phy-at803x.h>
  14778. +
  14779. +#include <asm/mach-ath79/ar71xx_regs.h>
  14780. +
  14781. +#include "common.h"
  14782. +#include "dev-ap9x-pci.h"
  14783. +#include "dev-eth.h"
  14784. +#include "dev-gpio-buttons.h"
  14785. +#include "dev-leds-gpio.h"
  14786. +#include "dev-m25p80.h"
  14787. +#include "dev-spi.h"
  14788. +#include "dev-usb.h"
  14789. +#include "dev-wmac.h"
  14790. +#include "machtypes.h"
  14791. +#include "nvram.h"
  14792. +
  14793. +#define MYNET_REXT_GPIO_LED_POWER 11
  14794. +#define MYNET_REXT_GPIO_LED_ETHERNET 12
  14795. +#define MYNET_REXT_GPIO_LED_WIFI 19
  14796. +
  14797. +#define MYNET_REXT_GPIO_LED_RF_QTY1 20
  14798. +#define MYNET_REXT_GPIO_LED_RF_QTY2 21
  14799. +#define MYNET_REXT_GPIO_LED_RF_QTY3 22
  14800. +
  14801. +#define MYNET_REXT_GPIO_BTN_RESET 13
  14802. +#define MYNET_REXT_GPIO_BTN_WPS 15
  14803. +#define MYNET_REXT_GPIO_SW_RF 14
  14804. +
  14805. +#define MYNET_REXT_GPIO_PHY_SWRST 16 /* disables Ethernet PHY */
  14806. +#define MYNET_REXT_GPIO_PHY_INT 17
  14807. +#define MYNET_REXT_GPIO_18 18
  14808. +
  14809. +#define MYNET_REXT_KEYS_POLL_INTERVAL 20 /* msecs */
  14810. +#define MYNET_REXT_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_REXT_KEYS_POLL_INTERVAL)
  14811. +
  14812. +#define MYNET_REXT_WMAC_CALDATA_OFFSET 0x1000
  14813. +
  14814. +#define MYNET_REXT_NVRAM_ADDR 0x1f7e0010
  14815. +#define MYNET_REXT_NVRAM_SIZE 0xfff0
  14816. +
  14817. +#define MYNET_REXT_ART_ADDR 0x1f7f0000
  14818. +
  14819. +static const char *mynet_rext_part_probes[] = {
  14820. + "cybertan",
  14821. + NULL,
  14822. +};
  14823. +
  14824. +static struct flash_platform_data mynet_rext_flash_data = {
  14825. + .type = "s25fl064k",
  14826. + .part_probes = mynet_rext_part_probes,
  14827. +};
  14828. +
  14829. +static struct gpio_led mynet_rext_leds_gpio[] __initdata = {
  14830. + {
  14831. + .name = "wd:blue:power",
  14832. + .gpio = MYNET_REXT_GPIO_LED_POWER,
  14833. + .active_low = 0,
  14834. + },
  14835. + {
  14836. + .name = "wd:blue:wireless",
  14837. + .gpio = MYNET_REXT_GPIO_LED_WIFI,
  14838. + .active_low = 1,
  14839. + },
  14840. + {
  14841. + .name = "wd:blue:ethernet",
  14842. + .gpio = MYNET_REXT_GPIO_LED_ETHERNET,
  14843. + .active_low = 1,
  14844. + },
  14845. + {
  14846. + .name = "wd:blue:quality1",
  14847. + .gpio = MYNET_REXT_GPIO_LED_RF_QTY1,
  14848. + .active_low = 1,
  14849. + },
  14850. + {
  14851. + .name = "wd:blue:quality2",
  14852. + .gpio = MYNET_REXT_GPIO_LED_RF_QTY2,
  14853. + .active_low = 1,
  14854. + },
  14855. + {
  14856. + .name = "wd:blue:quality3",
  14857. + .gpio = MYNET_REXT_GPIO_LED_RF_QTY3,
  14858. + .active_low = 1,
  14859. + },
  14860. +};
  14861. +
  14862. +static struct gpio_keys_button mynet_rext_gpio_keys[] __initdata = {
  14863. + {
  14864. + .desc = "Reset button",
  14865. + .type = EV_KEY,
  14866. + .code = KEY_RESTART,
  14867. + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL,
  14868. + .gpio = MYNET_REXT_GPIO_BTN_RESET,
  14869. + .active_low = 1,
  14870. + },
  14871. + {
  14872. + .desc = "WPS button",
  14873. + .type = EV_KEY,
  14874. + .code = KEY_WPS_BUTTON,
  14875. + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL,
  14876. + .gpio = MYNET_REXT_GPIO_BTN_WPS,
  14877. + .active_low = 1,
  14878. + },
  14879. + {
  14880. + .desc = "RF Band switch",
  14881. + .type = EV_SW,
  14882. + .code = BTN_1,
  14883. + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL,
  14884. + .gpio = MYNET_REXT_GPIO_SW_RF,
  14885. + },
  14886. +};
  14887. +
  14888. +static struct at803x_platform_data mynet_rext_at803x_data = {
  14889. + .disable_smarteee = 0,
  14890. + .enable_rgmii_rx_delay = 1,
  14891. + .enable_rgmii_tx_delay = 0,
  14892. + .fixup_rgmii_tx_delay = 1,
  14893. +};
  14894. +
  14895. +static struct mdio_board_info mynet_rext_mdio0_info[] = {
  14896. + {
  14897. + .bus_id = "ag71xx-mdio.0",
  14898. + .phy_addr = 4,
  14899. + .platform_data = &mynet_rext_at803x_data,
  14900. + },
  14901. +};
  14902. +
  14903. +static void mynet_rext_get_mac(const char *name, char *mac)
  14904. +{
  14905. + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_REXT_NVRAM_ADDR);
  14906. + int err;
  14907. +
  14908. + err = ath79_nvram_parse_mac_addr(nvram, MYNET_REXT_NVRAM_SIZE,
  14909. + name, mac);
  14910. + if (err)
  14911. + pr_err("no MAC address found for %s\n", name);
  14912. +}
  14913. +
  14914. +static void __init mynet_rext_setup(void)
  14915. +{
  14916. + u8 *art = (u8 *) KSEG1ADDR(MYNET_REXT_ART_ADDR);
  14917. + u8 tmpmac[ETH_ALEN];
  14918. +
  14919. + ath79_register_m25p80(&mynet_rext_flash_data);
  14920. +
  14921. + /* GPIO configuration from drivers/char/GPIO8.c */
  14922. +
  14923. + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_POWER,
  14924. + AR934X_GPIO_OUT_GPIO);
  14925. + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_WIFI,
  14926. + AR934X_GPIO_OUT_GPIO);
  14927. + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY1,
  14928. + AR934X_GPIO_OUT_GPIO);
  14929. + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY2,
  14930. + AR934X_GPIO_OUT_GPIO);
  14931. + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY3,
  14932. + AR934X_GPIO_OUT_GPIO);
  14933. + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_ETHERNET,
  14934. + AR934X_GPIO_OUT_GPIO);
  14935. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_rext_leds_gpio),
  14936. + mynet_rext_leds_gpio);
  14937. +
  14938. + ath79_register_gpio_keys_polled(-1, MYNET_REXT_KEYS_POLL_INTERVAL,
  14939. + ARRAY_SIZE(mynet_rext_gpio_keys),
  14940. + mynet_rext_gpio_keys);
  14941. +
  14942. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  14943. + AR934X_ETH_CFG_RXD_DELAY |
  14944. + AR934X_ETH_CFG_RDV_DELAY);
  14945. +
  14946. + ath79_register_mdio(0, 0x0);
  14947. +
  14948. + mdiobus_register_board_info(mynet_rext_mdio0_info,
  14949. + ARRAY_SIZE(mynet_rext_mdio0_info));
  14950. +
  14951. + /* LAN */
  14952. + mynet_rext_get_mac("et0macaddr=", ath79_eth0_data.mac_addr);
  14953. +
  14954. + /* GMAC0 is connected to an external PHY on Port 4 */
  14955. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  14956. + ath79_eth0_data.phy_mask = BIT(4);
  14957. + ath79_eth0_pll_data.pll_10 = 0x00001313; /* athrs_mac.c */
  14958. + ath79_eth0_pll_data.pll_1000 = 0x0e000000; /* athrs_mac.c */
  14959. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  14960. + ath79_register_eth(0);
  14961. +
  14962. + /* WLAN */
  14963. + mynet_rext_get_mac("wl0_hwaddr=", tmpmac);
  14964. + ap91_pci_init(art + MYNET_REXT_WMAC_CALDATA_OFFSET, tmpmac);
  14965. +}
  14966. +
  14967. +MIPS_MACHINE(ATH79_MACH_MYNET_REXT, "MYNET-REXT",
  14968. + "WD My Net Wi-Fi Range Extender", mynet_rext_setup);
  14969. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mzk-w04nu.c linux-4.1.43/arch/mips/ath79/mach-mzk-w04nu.c
  14970. --- linux-4.1.43.orig/arch/mips/ath79/mach-mzk-w04nu.c 1970-01-01 01:00:00.000000000 +0100
  14971. +++ linux-4.1.43/arch/mips/ath79/mach-mzk-w04nu.c 2017-08-06 20:02:15.000000000 +0200
  14972. @@ -0,0 +1,124 @@
  14973. +/*
  14974. + * Planex MZK-W04NU board support
  14975. + *
  14976. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  14977. + *
  14978. + * This program is free software; you can redistribute it and/or modify it
  14979. + * under the terms of the GNU General Public License version 2 as published
  14980. + * by the Free Software Foundation.
  14981. + */
  14982. +
  14983. +#include <asm/mach-ath79/ath79.h>
  14984. +
  14985. +#include "dev-eth.h"
  14986. +#include "dev-gpio-buttons.h"
  14987. +#include "dev-leds-gpio.h"
  14988. +#include "dev-m25p80.h"
  14989. +#include "dev-usb.h"
  14990. +#include "dev-wmac.h"
  14991. +#include "machtypes.h"
  14992. +
  14993. +#define MZK_W04NU_GPIO_LED_USB 0
  14994. +#define MZK_W04NU_GPIO_LED_STATUS 1
  14995. +#define MZK_W04NU_GPIO_LED_WPS 3
  14996. +#define MZK_W04NU_GPIO_LED_WLAN 6
  14997. +#define MZK_W04NU_GPIO_LED_AP 15
  14998. +#define MZK_W04NU_GPIO_LED_ROUTER 16
  14999. +
  15000. +#define MZK_W04NU_GPIO_BTN_APROUTER 5
  15001. +#define MZK_W04NU_GPIO_BTN_WPS 12
  15002. +#define MZK_W04NU_GPIO_BTN_RESET 21
  15003. +
  15004. +#define MZK_W04NU_KEYS_POLL_INTERVAL 20 /* msecs */
  15005. +#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL)
  15006. +
  15007. +static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = {
  15008. + {
  15009. + .name = "planex:green:status",
  15010. + .gpio = MZK_W04NU_GPIO_LED_STATUS,
  15011. + .active_low = 1,
  15012. + }, {
  15013. + .name = "planex:blue:wps",
  15014. + .gpio = MZK_W04NU_GPIO_LED_WPS,
  15015. + .active_low = 1,
  15016. + }, {
  15017. + .name = "planex:green:wlan",
  15018. + .gpio = MZK_W04NU_GPIO_LED_WLAN,
  15019. + .active_low = 1,
  15020. + }, {
  15021. + .name = "planex:green:usb",
  15022. + .gpio = MZK_W04NU_GPIO_LED_USB,
  15023. + .active_low = 1,
  15024. + }, {
  15025. + .name = "planex:green:ap",
  15026. + .gpio = MZK_W04NU_GPIO_LED_AP,
  15027. + .active_low = 1,
  15028. + }, {
  15029. + .name = "planex:green:router",
  15030. + .gpio = MZK_W04NU_GPIO_LED_ROUTER,
  15031. + .active_low = 1,
  15032. + }
  15033. +};
  15034. +
  15035. +static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = {
  15036. + {
  15037. + .desc = "reset",
  15038. + .type = EV_KEY,
  15039. + .code = KEY_RESTART,
  15040. + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
  15041. + .gpio = MZK_W04NU_GPIO_BTN_RESET,
  15042. + .active_low = 1,
  15043. + }, {
  15044. + .desc = "wps",
  15045. + .type = EV_KEY,
  15046. + .code = KEY_WPS_BUTTON,
  15047. + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
  15048. + .gpio = MZK_W04NU_GPIO_BTN_WPS,
  15049. + .active_low = 1,
  15050. + }, {
  15051. + .desc = "aprouter",
  15052. + .type = EV_KEY,
  15053. + .code = BTN_2,
  15054. + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
  15055. + .gpio = MZK_W04NU_GPIO_BTN_APROUTER,
  15056. + .active_low = 0,
  15057. + }
  15058. +};
  15059. +
  15060. +#define MZK_W04NU_WAN_PHYMASK BIT(4)
  15061. +#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK)
  15062. +
  15063. +static void __init mzk_w04nu_setup(void)
  15064. +{
  15065. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  15066. +
  15067. + ath79_register_mdio(0, MZK_W04NU_MDIO_MASK);
  15068. +
  15069. + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
  15070. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  15071. + ath79_eth0_data.speed = SPEED_100;
  15072. + ath79_eth0_data.duplex = DUPLEX_FULL;
  15073. + ath79_eth0_data.has_ar8216 = 1;
  15074. +
  15075. + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
  15076. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  15077. + ath79_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK;
  15078. +
  15079. + ath79_register_eth(0);
  15080. + ath79_register_eth(1);
  15081. +
  15082. + ath79_register_m25p80(NULL);
  15083. +
  15084. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio),
  15085. + mzk_w04nu_leds_gpio);
  15086. +
  15087. + ath79_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL,
  15088. + ARRAY_SIZE(mzk_w04nu_gpio_keys),
  15089. + mzk_w04nu_gpio_keys);
  15090. + ath79_register_usb();
  15091. +
  15092. + ath79_register_wmac(eeprom, NULL);
  15093. +}
  15094. +
  15095. +MIPS_MACHINE(ATH79_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU",
  15096. + mzk_w04nu_setup);
  15097. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-mzk-w300nh.c linux-4.1.43/arch/mips/ath79/mach-mzk-w300nh.c
  15098. --- linux-4.1.43.orig/arch/mips/ath79/mach-mzk-w300nh.c 1970-01-01 01:00:00.000000000 +0100
  15099. +++ linux-4.1.43/arch/mips/ath79/mach-mzk-w300nh.c 2017-08-06 20:02:15.000000000 +0200
  15100. @@ -0,0 +1,115 @@
  15101. +/*
  15102. + * Planex MZK-W300NH board support
  15103. + *
  15104. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  15105. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  15106. + *
  15107. + * This program is free software; you can redistribute it and/or modify it
  15108. + * under the terms of the GNU General Public License version 2 as published
  15109. + * by the Free Software Foundation.
  15110. + */
  15111. +
  15112. +#include <asm/mach-ath79/ath79.h>
  15113. +
  15114. +#include "dev-eth.h"
  15115. +#include "dev-gpio-buttons.h"
  15116. +#include "dev-leds-gpio.h"
  15117. +#include "dev-m25p80.h"
  15118. +#include "dev-wmac.h"
  15119. +#include "machtypes.h"
  15120. +
  15121. +#define MZK_W300NH_GPIO_LED_STATUS 1
  15122. +#define MZK_W300NH_GPIO_LED_WPS 3
  15123. +#define MZK_W300NH_GPIO_LED_WLAN 6
  15124. +#define MZK_W300NH_GPIO_LED_AP_GREEN 15
  15125. +#define MZK_W300NH_GPIO_LED_AP_AMBER 16
  15126. +
  15127. +#define MZK_W300NH_GPIO_BTN_APROUTER 5
  15128. +#define MZK_W300NH_GPIO_BTN_WPS 12
  15129. +#define MZK_W300NH_GPIO_BTN_RESET 21
  15130. +
  15131. +#define MZK_W300NH_KEYS_POLL_INTERVAL 20 /* msecs */
  15132. +#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL)
  15133. +
  15134. +static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = {
  15135. + {
  15136. + .name = "planex:green:status",
  15137. + .gpio = MZK_W300NH_GPIO_LED_STATUS,
  15138. + .active_low = 1,
  15139. + }, {
  15140. + .name = "planex:blue:wps",
  15141. + .gpio = MZK_W300NH_GPIO_LED_WPS,
  15142. + .active_low = 1,
  15143. + }, {
  15144. + .name = "planex:green:wlan",
  15145. + .gpio = MZK_W300NH_GPIO_LED_WLAN,
  15146. + .active_low = 1,
  15147. + }, {
  15148. + .name = "planex:green:aprouter",
  15149. + .gpio = MZK_W300NH_GPIO_LED_AP_GREEN,
  15150. + }, {
  15151. + .name = "planex:amber:aprouter",
  15152. + .gpio = MZK_W300NH_GPIO_LED_AP_AMBER,
  15153. + }
  15154. +};
  15155. +
  15156. +static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = {
  15157. + {
  15158. + .desc = "reset",
  15159. + .type = EV_KEY,
  15160. + .code = KEY_RESTART,
  15161. + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
  15162. + .gpio = MZK_W300NH_GPIO_BTN_RESET,
  15163. + .active_low = 1,
  15164. + }, {
  15165. + .desc = "wps",
  15166. + .type = EV_KEY,
  15167. + .code = KEY_WPS_BUTTON,
  15168. + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
  15169. + .gpio = MZK_W300NH_GPIO_BTN_WPS,
  15170. + .active_low = 1,
  15171. + }, {
  15172. + .desc = "aprouter",
  15173. + .type = EV_KEY,
  15174. + .code = BTN_2,
  15175. + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
  15176. + .gpio = MZK_W300NH_GPIO_BTN_APROUTER,
  15177. + .active_low = 0,
  15178. + }
  15179. +};
  15180. +
  15181. +#define MZK_W300NH_WAN_PHYMASK BIT(4)
  15182. +#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK)
  15183. +
  15184. +static void __init mzk_w300nh_setup(void)
  15185. +{
  15186. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  15187. +
  15188. + ath79_register_mdio(0, MZK_W300NH_MDIO_MASK);
  15189. +
  15190. + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
  15191. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  15192. + ath79_eth0_data.speed = SPEED_100;
  15193. + ath79_eth0_data.duplex = DUPLEX_FULL;
  15194. + ath79_eth0_data.has_ar8216 = 1;
  15195. +
  15196. + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
  15197. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  15198. + ath79_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK;
  15199. +
  15200. + ath79_register_eth(0);
  15201. + ath79_register_eth(1);
  15202. +
  15203. + ath79_register_m25p80(NULL);
  15204. +
  15205. + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio),
  15206. + mzk_w300nh_leds_gpio);
  15207. +
  15208. + ath79_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL,
  15209. + ARRAY_SIZE(mzk_w300nh_gpio_keys),
  15210. + mzk_w300nh_gpio_keys);
  15211. + ath79_register_wmac(eeprom, NULL);
  15212. +}
  15213. +
  15214. +MIPS_MACHINE(ATH79_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH",
  15215. + mzk_w300nh_setup);
  15216. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-nbg460n.c linux-4.1.43/arch/mips/ath79/mach-nbg460n.c
  15217. --- linux-4.1.43.orig/arch/mips/ath79/mach-nbg460n.c 1970-01-01 01:00:00.000000000 +0100
  15218. +++ linux-4.1.43/arch/mips/ath79/mach-nbg460n.c 2017-08-06 20:02:15.000000000 +0200
  15219. @@ -0,0 +1,220 @@
  15220. +/*
  15221. + * Zyxel NBG 460N/550N/550NH board support
  15222. + *
  15223. + * Copyright (C) 2010 Michael Kurz <michi.kurz@googlemail.com>
  15224. + *
  15225. + * based on mach-tl-wr1043nd.c
  15226. + *
  15227. + * This program is free software; you can redistribute it and/or modify it
  15228. + * under the terms of the GNU General Public License version 2 as published
  15229. + * by the Free Software Foundation.
  15230. + */
  15231. +
  15232. +#include <linux/delay.h>
  15233. +#include <linux/i2c.h>
  15234. +#include <linux/i2c-algo-bit.h>
  15235. +#include <linux/i2c-gpio.h>
  15236. +#include <linux/mtd/mtd.h>
  15237. +#include <linux/mtd/partitions.h>
  15238. +#include <linux/platform_device.h>
  15239. +#include <linux/rtl8366.h>
  15240. +
  15241. +#include <asm/mach-ath79/ath79.h>
  15242. +
  15243. +#include "dev-eth.h"
  15244. +#include "dev-gpio-buttons.h"
  15245. +#include "dev-leds-gpio.h"
  15246. +#include "dev-m25p80.h"
  15247. +#include "dev-wmac.h"
  15248. +#include "machtypes.h"
  15249. +
  15250. +/* LEDs */
  15251. +#define NBG460N_GPIO_LED_WPS 3
  15252. +#define NBG460N_GPIO_LED_WAN 6
  15253. +#define NBG460N_GPIO_LED_POWER 14
  15254. +#define NBG460N_GPIO_LED_WLAN 15
  15255. +
  15256. +/* Buttons */
  15257. +#define NBG460N_GPIO_BTN_WPS 12
  15258. +#define NBG460N_GPIO_BTN_RESET 21
  15259. +
  15260. +#define NBG460N_KEYS_POLL_INTERVAL 20 /* msecs */
  15261. +#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL)
  15262. +
  15263. +/* RTC chip PCF8563 I2C interface */
  15264. +#define NBG460N_GPIO_PCF8563_SDA 8
  15265. +#define NBG460N_GPIO_PCF8563_SCK 7
  15266. +
  15267. +/* Switch configuration I2C interface */
  15268. +#define NBG460N_GPIO_RTL8366_SDA 16
  15269. +#define NBG460N_GPIO_RTL8366_SCK 18
  15270. +
  15271. +static struct mtd_partition nbg460n_partitions[] = {
  15272. + {
  15273. + .name = "Bootbase",
  15274. + .offset = 0,
  15275. + .size = 0x010000,
  15276. + .mask_flags = MTD_WRITEABLE,
  15277. + }, {
  15278. + .name = "U-Boot Config",
  15279. + .offset = 0x010000,
  15280. + .size = 0x030000,
  15281. + }, {
  15282. + .name = "U-Boot",
  15283. + .offset = 0x040000,
  15284. + .size = 0x030000,
  15285. + }, {
  15286. + .name = "linux",
  15287. + .offset = 0x070000,
  15288. + .size = 0x0e0000,
  15289. + }, {
  15290. + .name = "rootfs",
  15291. + .offset = 0x150000,
  15292. + .size = 0x2a0000,
  15293. + }, {
  15294. + .name = "CalibData",
  15295. + .offset = 0x3f0000,
  15296. + .size = 0x010000,
  15297. + .mask_flags = MTD_WRITEABLE,
  15298. + }, {
  15299. + .name = "firmware",
  15300. + .offset = 0x070000,
  15301. + .size = 0x380000,
  15302. + }
  15303. +};
  15304. +
  15305. +static struct flash_platform_data nbg460n_flash_data = {
  15306. + .parts = nbg460n_partitions,
  15307. + .nr_parts = ARRAY_SIZE(nbg460n_partitions),
  15308. +};
  15309. +
  15310. +static struct gpio_led nbg460n_leds_gpio[] __initdata = {
  15311. + {
  15312. + .name = "nbg460n:green:power",
  15313. + .gpio = NBG460N_GPIO_LED_POWER,
  15314. + .active_low = 0,
  15315. + .default_trigger = "default-on",
  15316. + }, {
  15317. + .name = "nbg460n:green:wps",
  15318. + .gpio = NBG460N_GPIO_LED_WPS,
  15319. + .active_low = 0,
  15320. + }, {
  15321. + .name = "nbg460n:green:wlan",
  15322. + .gpio = NBG460N_GPIO_LED_WLAN,
  15323. + .active_low = 0,
  15324. + }, {
  15325. + /* Not really for controlling the LED,
  15326. + when set low the LED blinks uncontrollable */
  15327. + .name = "nbg460n:green:wan",
  15328. + .gpio = NBG460N_GPIO_LED_WAN,
  15329. + .active_low = 0,
  15330. + }
  15331. +};
  15332. +
  15333. +static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = {
  15334. + {
  15335. + .desc = "reset",
  15336. + .type = EV_KEY,
  15337. + .code = KEY_RESTART,
  15338. + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL,
  15339. + .gpio = NBG460N_GPIO_BTN_RESET,
  15340. + .active_low = 1,
  15341. + }, {
  15342. + .desc = "wps",
  15343. + .type = EV_KEY,
  15344. + .code = KEY_WPS_BUTTON,
  15345. + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL,
  15346. + .gpio = NBG460N_GPIO_BTN_WPS,
  15347. + .active_low = 1,
  15348. + }
  15349. +};
  15350. +
  15351. +static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = {
  15352. + .sda_pin = NBG460N_GPIO_PCF8563_SDA,
  15353. + .scl_pin = NBG460N_GPIO_PCF8563_SCK,
  15354. + .udelay = 10,
  15355. +};
  15356. +
  15357. +static struct platform_device nbg460n_i2c_device = {
  15358. + .name = "i2c-gpio",
  15359. + .id = -1,
  15360. + .num_resources = 0,
  15361. + .resource = NULL,
  15362. + .dev = {
  15363. + .platform_data = &nbg460n_i2c_device_platdata,
  15364. + },
  15365. +};
  15366. +
  15367. +static struct i2c_board_info nbg460n_i2c_devs[] __initdata = {
  15368. + {
  15369. + I2C_BOARD_INFO("pcf8563", 0x51),
  15370. + },
  15371. +};
  15372. +
  15373. +static void nbg460n_i2c_init(void)
  15374. +{
  15375. + /* The gpio interface */
  15376. + platform_device_register(&nbg460n_i2c_device);
  15377. + /* I2C devices */
  15378. + i2c_register_board_info(0, nbg460n_i2c_devs,
  15379. + ARRAY_SIZE(nbg460n_i2c_devs));
  15380. +}
  15381. +
  15382. +
  15383. +static struct rtl8366_platform_data nbg460n_rtl8366s_data = {
  15384. + .gpio_sda = NBG460N_GPIO_RTL8366_SDA,
  15385. + .gpio_sck = NBG460N_GPIO_RTL8366_SCK,
  15386. +};
  15387. +
  15388. +static struct platform_device nbg460n_rtl8366s_device = {
  15389. + .name = RTL8366S_DRIVER_NAME,
  15390. + .id = -1,
  15391. + .dev = {
  15392. + .platform_data = &nbg460n_rtl8366s_data,
  15393. + }
  15394. +};
  15395. +
  15396. +static void __init nbg460n_setup(void)
  15397. +{
  15398. + /* end of bootloader sector contains mac address */
  15399. + u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8);
  15400. + /* last sector contains wlan calib data */
  15401. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  15402. +
  15403. + /* LAN Port */
  15404. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  15405. + ath79_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev;
  15406. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  15407. + ath79_eth0_data.speed = SPEED_1000;
  15408. + ath79_eth0_data.duplex = DUPLEX_FULL;
  15409. +
  15410. + /* WAN Port */
  15411. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  15412. + ath79_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev;
  15413. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  15414. + ath79_eth1_data.phy_mask = 0x10;
  15415. +
  15416. + ath79_register_eth(0);
  15417. + ath79_register_eth(1);
  15418. +
  15419. + /* register the switch phy */
  15420. + platform_device_register(&nbg460n_rtl8366s_device);
  15421. +
  15422. + /* register flash */
  15423. + ath79_register_m25p80(&nbg460n_flash_data);
  15424. +
  15425. + ath79_register_wmac(eeprom, mac);
  15426. +
  15427. + /* register RTC chip */
  15428. + nbg460n_i2c_init();
  15429. +
  15430. + ath79_register_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio),
  15431. + nbg460n_leds_gpio);
  15432. +
  15433. + ath79_register_gpio_keys_polled(-1, NBG460N_KEYS_POLL_INTERVAL,
  15434. + ARRAY_SIZE(nbg460n_gpio_keys),
  15435. + nbg460n_gpio_keys);
  15436. +}
  15437. +
  15438. +MIPS_MACHINE(ATH79_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH",
  15439. + nbg460n_setup);
  15440. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-nbg6716.c linux-4.1.43/arch/mips/ath79/mach-nbg6716.c
  15441. --- linux-4.1.43.orig/arch/mips/ath79/mach-nbg6716.c 1970-01-01 01:00:00.000000000 +0100
  15442. +++ linux-4.1.43/arch/mips/ath79/mach-nbg6716.c 2017-08-06 20:02:15.000000000 +0200
  15443. @@ -0,0 +1,381 @@
  15444. +/*
  15445. + * ZyXEL NBG6716/NBG6616 board support
  15446. + *
  15447. + * Based on the Qualcomm Atheros AP135/AP136 reference board support code
  15448. + * Copyright (c) 2012 Qualcomm Atheros
  15449. + * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
  15450. + * Copyright (c) 2013 Andre Valentin <avalentin@marcant.net>
  15451. + *
  15452. + * Permission to use, copy, modify, and/or distribute this software for any
  15453. + * purpose with or without fee is hereby granted, provided that the above
  15454. + * copyright notice and this permission notice appear in all copies.
  15455. + *
  15456. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  15457. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15458. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15459. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15460. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15461. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15462. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15463. + *
  15464. + */
  15465. +
  15466. +#include <linux/platform_device.h>
  15467. +#include <linux/ar8216_platform.h>
  15468. +#include <linux/gpio.h>
  15469. +#include <linux/mtd/mtd.h>
  15470. +#include <linux/mtd/nand.h>
  15471. +#include <linux/platform/ar934x_nfc.h>
  15472. +
  15473. +#include <asm/mach-ath79/ar71xx_regs.h>
  15474. +
  15475. +#include "common.h"
  15476. +#include "pci.h"
  15477. +#include "dev-ap9x-pci.h"
  15478. +#include "dev-gpio-buttons.h"
  15479. +#include "dev-eth.h"
  15480. +#include "dev-leds-gpio.h"
  15481. +#include "dev-nfc.h"
  15482. +#include "dev-m25p80.h"
  15483. +#include "dev-usb.h"
  15484. +#include "dev-wmac.h"
  15485. +#include "machtypes.h"
  15486. +#include "nvram.h"
  15487. +
  15488. +#define NBG6716_GPIO_LED_INTERNET 18
  15489. +#define NBG6716_GPIO_LED_POWER 15
  15490. +#define NBG6716_GPIO_LED_USB1 4
  15491. +#define NBG6716_GPIO_LED_USB2 13
  15492. +#define NBG6716_GPIO_LED_WIFI2G 19
  15493. +#define NBG6716_GPIO_LED_WIFI5G 17
  15494. +#define NBG6716_GPIO_LED_WPS 21
  15495. +
  15496. +#define NBG6716_GPIO_BTN_RESET 23
  15497. +#define NBG6716_GPIO_BTN_RFKILL 1
  15498. +#define NBG6716_GPIO_BTN_USB1 0
  15499. +#define NBG6716_GPIO_BTN_USB2 14
  15500. +#define NBG6716_GPIO_BTN_WPS 22
  15501. +
  15502. +#define NBG6716_GPIO_USB_POWER 16
  15503. +
  15504. +#define NBG6716_KEYS_POLL_INTERVAL 20 /* msecs */
  15505. +#define NBG6716_KEYS_DEBOUNCE_INTERVAL (3 * NBG6716_KEYS_POLL_INTERVAL)
  15506. +
  15507. +#define NBG6716_MAC0_OFFSET 0
  15508. +#define NBG6716_MAC1_OFFSET 6
  15509. +#define NBG6716_WMAC_CALDATA_OFFSET 0x1000
  15510. +#define NBG6716_PCIE_CALDATA_OFFSET 0x5000
  15511. +
  15512. +/* NBG6616 has a different GPIO usage as it does not have USB Buttons */
  15513. +#define NBG6616_GPIO_LED_USB0 14
  15514. +#define NBG6616_GPIO_LED_USB1 21
  15515. +#define NBG6616_GPIO_LED_WPS 0
  15516. +
  15517. +static struct gpio_led nbg6716_leds_gpio[] __initdata = {
  15518. + {
  15519. + .name = "nbg6716:white:internet",
  15520. + .gpio = NBG6716_GPIO_LED_INTERNET,
  15521. + .active_low = 1,
  15522. + },
  15523. + {
  15524. + .name = "nbg6716:white:power",
  15525. + .gpio = NBG6716_GPIO_LED_POWER,
  15526. + .active_low = 1,
  15527. + },
  15528. + {
  15529. + .name = "nbg6716:white:usb1",
  15530. + .gpio = NBG6716_GPIO_LED_USB1,
  15531. + .active_low = 1,
  15532. + },
  15533. + {
  15534. + .name = "nbg6716:white:usb2",
  15535. + .gpio = NBG6716_GPIO_LED_USB2,
  15536. + .active_low = 1,
  15537. + },
  15538. + {
  15539. + .name = "nbg6716:white:wifi2g",
  15540. + .gpio = NBG6716_GPIO_LED_WIFI2G,
  15541. + .active_low = 1,
  15542. + },
  15543. + {
  15544. + .name = "nbg6716:white:wifi5g",
  15545. + .gpio = NBG6716_GPIO_LED_WIFI5G,
  15546. + .active_low = 1,
  15547. + },
  15548. + {
  15549. + .name = "nbg6716:white:wps",
  15550. + .gpio = NBG6716_GPIO_LED_WPS,
  15551. + .active_low = 1,
  15552. + }
  15553. +};
  15554. +
  15555. +static struct gpio_keys_button nbg6716_gpio_keys[] __initdata = {
  15556. + {
  15557. + .desc = "RESET button",
  15558. + .type = EV_KEY,
  15559. + .code = KEY_RESTART,
  15560. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15561. + .gpio = NBG6716_GPIO_BTN_RESET,
  15562. + .active_low = 1,
  15563. + },
  15564. + {
  15565. + .desc = "RFKILL button",
  15566. + .type = EV_SW,
  15567. + .code = KEY_RFKILL,
  15568. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15569. + .gpio = NBG6716_GPIO_BTN_RFKILL,
  15570. + .active_low = 0,
  15571. + },
  15572. + {
  15573. + .desc = "USB1 eject button",
  15574. + .type = EV_KEY,
  15575. + .code = BTN_1,
  15576. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15577. + .gpio = NBG6716_GPIO_BTN_USB1,
  15578. + .active_low = 1,
  15579. + },
  15580. + {
  15581. + .desc = "USB2 eject button",
  15582. + .type = EV_KEY,
  15583. + .code = BTN_2,
  15584. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15585. + .gpio = NBG6716_GPIO_BTN_USB2,
  15586. + .active_low = 1,
  15587. + },
  15588. + {
  15589. + .desc = "WPS button",
  15590. + .type = EV_KEY,
  15591. + .code = KEY_WPS_BUTTON,
  15592. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15593. + .gpio = NBG6716_GPIO_BTN_WPS,
  15594. + .active_low = 1,
  15595. + },
  15596. +};
  15597. +
  15598. +
  15599. +
  15600. +static struct gpio_led nbg6616_leds_gpio[] __initdata = {
  15601. + {
  15602. + .name = "nbg6616:green:power",
  15603. + .gpio = NBG6716_GPIO_LED_POWER,
  15604. + .active_low = 1,
  15605. + },
  15606. + {
  15607. + .name = "nbg6616:green:usb2",
  15608. + .gpio = NBG6616_GPIO_LED_USB0,
  15609. + .active_low = 1,
  15610. + },
  15611. + {
  15612. + .name = "nbg6616:green:usb1",
  15613. + .gpio = NBG6616_GPIO_LED_USB1,
  15614. + .active_low = 1,
  15615. + },
  15616. + {
  15617. + .name = "nbg6616:green:wifi2g",
  15618. + .gpio = NBG6716_GPIO_LED_WIFI2G,
  15619. + .active_low = 1,
  15620. + },
  15621. + {
  15622. + .name = "nbg6616:green:wifi5g",
  15623. + .gpio = NBG6716_GPIO_LED_WIFI5G,
  15624. + .active_low = 1,
  15625. + },
  15626. + {
  15627. + .name = "nbg6616:green:wps",
  15628. + .gpio = NBG6616_GPIO_LED_WPS,
  15629. + .active_low = 1,
  15630. + }
  15631. +};
  15632. +
  15633. +static struct gpio_keys_button nbg6616_gpio_keys[] __initdata = {
  15634. + {
  15635. + .desc = "RESET button",
  15636. + .type = EV_KEY,
  15637. + .code = KEY_RESTART,
  15638. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15639. + .gpio = NBG6716_GPIO_BTN_RESET,
  15640. + .active_low = 1,
  15641. + },
  15642. + {
  15643. + .desc = "RFKILL button",
  15644. + .type = EV_KEY,
  15645. + .code = KEY_RFKILL,
  15646. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15647. + .gpio = NBG6716_GPIO_BTN_RFKILL,
  15648. + .active_low = 1,
  15649. + },
  15650. + {
  15651. + .desc = "WPS button",
  15652. + .type = EV_KEY,
  15653. + .code = KEY_WPS_BUTTON,
  15654. + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL,
  15655. + .gpio = NBG6716_GPIO_BTN_WPS,
  15656. + .active_low = 1,
  15657. + },
  15658. +};
  15659. +
  15660. +
  15661. +static struct ar8327_pad_cfg nbg6716_ar8327_pad0_cfg;
  15662. +static struct ar8327_pad_cfg nbg6716_ar8327_pad6_cfg;
  15663. +static struct ar8327_led_cfg nbg6716_ar8327_led_cfg;
  15664. +
  15665. +static struct ar8327_platform_data nbg6716_ar8327_data = {
  15666. + .pad0_cfg = &nbg6716_ar8327_pad0_cfg,
  15667. + .pad6_cfg = &nbg6716_ar8327_pad6_cfg,
  15668. + .port0_cfg = {
  15669. + .force_link = 1,
  15670. + .speed = AR8327_PORT_SPEED_1000,
  15671. + .duplex = 1,
  15672. + .txpause = 1,
  15673. + .rxpause = 1,
  15674. + },
  15675. + .port6_cfg = {
  15676. + .force_link = 1,
  15677. + .speed = AR8327_PORT_SPEED_1000,
  15678. + .duplex = 1,
  15679. + .txpause = 1,
  15680. + .rxpause = 1,
  15681. + },
  15682. + .led_cfg = &nbg6716_ar8327_led_cfg
  15683. +};
  15684. +
  15685. +static struct mdio_board_info nbg6716_mdio0_info[] = {
  15686. + {
  15687. + .bus_id = "ag71xx-mdio.0",
  15688. + .phy_addr = 0,
  15689. + .platform_data = &nbg6716_ar8327_data,
  15690. + },
  15691. +};
  15692. +
  15693. +static void nbg6716_get_mac(void* nvram_addr, const char *name, char *mac)
  15694. +{
  15695. + u8 *nvram = (u8 *) KSEG1ADDR(nvram_addr);
  15696. + int err;
  15697. +
  15698. + err = ath79_nvram_parse_mac_addr(nvram, 0x10000,
  15699. + name, mac);
  15700. + if (err)
  15701. + pr_err("no MAC address found for %s\n", name);
  15702. +}
  15703. +
  15704. +static void __init nbg6716_common_setup(u32 leds_num, struct gpio_led* leds,
  15705. + u32 keys_num,
  15706. + struct gpio_keys_button* keys,
  15707. + void* art_addr, void* nvram)
  15708. +{
  15709. + u8 *art = (u8 *) KSEG1ADDR(art_addr);
  15710. + u8 tmpmac[ETH_ALEN];
  15711. +
  15712. + ath79_register_m25p80(NULL);
  15713. +
  15714. + ath79_register_leds_gpio(-1, leds_num, leds);
  15715. + ath79_register_gpio_keys_polled(-1, NBG6716_KEYS_POLL_INTERVAL,
  15716. + keys_num, keys);
  15717. +
  15718. + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
  15719. + ath79_register_nfc();
  15720. +
  15721. + gpio_request_one(NBG6716_GPIO_USB_POWER,
  15722. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  15723. + "USB power");
  15724. +
  15725. + ath79_register_usb();
  15726. +
  15727. + nbg6716_get_mac(nvram, "ethaddr=", tmpmac);
  15728. +
  15729. + ath79_register_pci();
  15730. +
  15731. + ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac);
  15732. +
  15733. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  15734. +
  15735. + ath79_register_mdio(0, 0x0);
  15736. +
  15737. + ath79_init_mac(ath79_eth0_data.mac_addr, tmpmac, 2);
  15738. + ath79_init_mac(ath79_eth1_data.mac_addr, tmpmac, 3);
  15739. +
  15740. + mdiobus_register_board_info(nbg6716_mdio0_info,
  15741. + ARRAY_SIZE(nbg6716_mdio0_info));
  15742. +
  15743. + /* GMAC0 is connected to the RMGII interface */
  15744. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  15745. + ath79_eth0_data.phy_mask = BIT(0);
  15746. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  15747. +
  15748. + ath79_register_eth(0);
  15749. +
  15750. + /* GMAC1 is connected to the SGMII interface */
  15751. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  15752. + ath79_eth1_data.speed = SPEED_1000;
  15753. + ath79_eth1_data.duplex = DUPLEX_FULL;
  15754. +
  15755. + ath79_register_eth(1);
  15756. +}
  15757. +
  15758. +static void __init nbg6716_010_setup(void)
  15759. +{
  15760. + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
  15761. + nbg6716_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
  15762. + nbg6716_ar8327_pad0_cfg.txclk_delay_en = true;
  15763. + nbg6716_ar8327_pad0_cfg.rxclk_delay_en = true;
  15764. + nbg6716_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
  15765. + nbg6716_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
  15766. + nbg6716_ar8327_pad0_cfg.mac06_exchange_en = true;
  15767. +
  15768. + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
  15769. + nbg6716_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
  15770. + nbg6716_ar8327_pad6_cfg.rxclk_delay_en = true;
  15771. + nbg6716_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
  15772. +
  15773. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  15774. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  15775. +
  15776. + nbg6716_ar8327_led_cfg.open_drain = 0;
  15777. + nbg6716_ar8327_led_cfg.led_ctrl0 = 0xffb7ffb7;
  15778. + nbg6716_ar8327_led_cfg.led_ctrl1 = 0xffb7ffb7;
  15779. + nbg6716_ar8327_led_cfg.led_ctrl2 = 0xffb7ffb7;
  15780. + nbg6716_ar8327_led_cfg.led_ctrl3 = 0x03ffff00;
  15781. +
  15782. + nbg6716_common_setup(ARRAY_SIZE(nbg6716_leds_gpio), nbg6716_leds_gpio,
  15783. + ARRAY_SIZE(nbg6716_gpio_keys), nbg6716_gpio_keys,
  15784. + (void*) 0x1f050000, (void*) 0x1f040000);
  15785. +}
  15786. +
  15787. +static void __init nbg6616_010_setup(void)
  15788. +{
  15789. + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
  15790. + nbg6716_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
  15791. + nbg6716_ar8327_pad0_cfg.txclk_delay_en = true;
  15792. + nbg6716_ar8327_pad0_cfg.rxclk_delay_en = true;
  15793. + nbg6716_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
  15794. + nbg6716_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
  15795. +
  15796. + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
  15797. + nbg6716_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
  15798. + nbg6716_ar8327_pad6_cfg.rxclk_delay_en = true;
  15799. + nbg6716_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
  15800. +
  15801. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  15802. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  15803. +
  15804. + nbg6716_ar8327_led_cfg.open_drain = 0;
  15805. + nbg6716_ar8327_led_cfg.led_ctrl0 = 0xffb7ffb7;
  15806. + nbg6716_ar8327_led_cfg.led_ctrl1 = 0xffb7ffb7;
  15807. + nbg6716_ar8327_led_cfg.led_ctrl2 = 0xffb7ffb7;
  15808. + nbg6716_ar8327_led_cfg.led_ctrl3 = 0x03ffff00;
  15809. +
  15810. +
  15811. + nbg6716_common_setup(ARRAY_SIZE(nbg6616_leds_gpio), nbg6616_leds_gpio,
  15812. + ARRAY_SIZE(nbg6616_gpio_keys), nbg6616_gpio_keys,
  15813. + (void*) 0x1f040000, (void*) 0x1f030000);
  15814. +}
  15815. +
  15816. +
  15817. +MIPS_MACHINE(ATH79_MACH_NBG6716, "NBG6716",
  15818. + "Zyxel NBG6716",
  15819. + nbg6716_010_setup);
  15820. +
  15821. +MIPS_MACHINE(ATH79_MACH_NBG6616, "NBG6616",
  15822. + "Zyxel NBG6616",
  15823. + nbg6616_010_setup);
  15824. +
  15825. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-om2p.c linux-4.1.43/arch/mips/ath79/mach-om2p.c
  15826. --- linux-4.1.43.orig/arch/mips/ath79/mach-om2p.c 1970-01-01 01:00:00.000000000 +0100
  15827. +++ linux-4.1.43/arch/mips/ath79/mach-om2p.c 2017-08-06 20:02:15.000000000 +0200
  15828. @@ -0,0 +1,225 @@
  15829. +/*
  15830. + * OpenMesh OM2P support
  15831. + *
  15832. + * Copyright (C) 2011 Marek Lindner <marek@open-mesh.com>
  15833. + *
  15834. + * This program is free software; you can redistribute it and/or modify it
  15835. + * under the terms of the GNU General Public License version 2 as published
  15836. + * by the Free Software Foundation.
  15837. + */
  15838. +
  15839. +#include <linux/gpio.h>
  15840. +#include <linux/mtd/mtd.h>
  15841. +#include <linux/mtd/partitions.h>
  15842. +#include <linux/platform_device.h>
  15843. +
  15844. +#include <asm/mach-ath79/ar71xx_regs.h>
  15845. +#include <asm/mach-ath79/ath79.h>
  15846. +
  15847. +#include "common.h"
  15848. +#include "dev-ap9x-pci.h"
  15849. +#include "dev-eth.h"
  15850. +#include "dev-gpio-buttons.h"
  15851. +#include "dev-leds-gpio.h"
  15852. +#include "dev-m25p80.h"
  15853. +#include "dev-wmac.h"
  15854. +#include "machtypes.h"
  15855. +
  15856. +#define OM2P_GPIO_LED_POWER 0
  15857. +#define OM2P_GPIO_LED_GREEN 13
  15858. +#define OM2P_GPIO_LED_RED 14
  15859. +#define OM2P_GPIO_LED_YELLOW 15
  15860. +#define OM2P_GPIO_LED_LAN 16
  15861. +#define OM2P_GPIO_LED_WAN 17
  15862. +#define OM2P_GPIO_BTN_RESET 1
  15863. +
  15864. +#define OM2P_KEYS_POLL_INTERVAL 20 /* msecs */
  15865. +#define OM2P_KEYS_DEBOUNCE_INTERVAL (3 * OM2P_KEYS_POLL_INTERVAL)
  15866. +
  15867. +#define OM2P_WAN_PHYMASK BIT(4)
  15868. +
  15869. +#define OM2P_LC_GPIO_LED_POWER 1
  15870. +#define OM2P_LC_GPIO_LED_GREEN 15
  15871. +#define OM2P_LC_GPIO_LED_RED 16
  15872. +#define OM2P_LC_GPIO_LED_YELLOW 0
  15873. +#define OM2P_LC_GPIO_LED_LAN 13
  15874. +#define OM2P_LC_GPIO_LED_WAN 17
  15875. +#define OM2P_LC_GPIO_BTN_RESET 12
  15876. +
  15877. +static struct flash_platform_data om2p_flash_data = {
  15878. + .type = "s25sl12800",
  15879. + .name = "ar7240-nor0",
  15880. +};
  15881. +
  15882. +static struct gpio_led om2p_leds_gpio[] __initdata = {
  15883. + {
  15884. + .name = "om2p:blue:power",
  15885. + .gpio = OM2P_GPIO_LED_POWER,
  15886. + .active_low = 1,
  15887. + }, {
  15888. + .name = "om2p:red:wifi",
  15889. + .gpio = OM2P_GPIO_LED_RED,
  15890. + .active_low = 1,
  15891. + }, {
  15892. + .name = "om2p:yellow:wifi",
  15893. + .gpio = OM2P_GPIO_LED_YELLOW,
  15894. + .active_low = 1,
  15895. + }, {
  15896. + .name = "om2p:green:wifi",
  15897. + .gpio = OM2P_GPIO_LED_GREEN,
  15898. + .active_low = 1,
  15899. + }, {
  15900. + .name = "om2p:blue:lan",
  15901. + .gpio = OM2P_GPIO_LED_LAN,
  15902. + .active_low = 1,
  15903. + }, {
  15904. + .name = "om2p:blue:wan",
  15905. + .gpio = OM2P_GPIO_LED_WAN,
  15906. + .active_low = 1,
  15907. + }
  15908. +};
  15909. +
  15910. +static struct gpio_keys_button om2p_gpio_keys[] __initdata = {
  15911. + {
  15912. + .desc = "reset",
  15913. + .type = EV_KEY,
  15914. + .code = KEY_RESTART,
  15915. + .debounce_interval = OM2P_KEYS_DEBOUNCE_INTERVAL,
  15916. + .gpio = OM2P_GPIO_BTN_RESET,
  15917. + .active_low = 1,
  15918. + }
  15919. +};
  15920. +
  15921. +static void __init om2p_setup(void)
  15922. +{
  15923. + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
  15924. + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
  15925. + u8 *ee = (u8 *)KSEG1ADDR(0x1ffc1000);
  15926. +
  15927. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  15928. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  15929. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  15930. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  15931. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  15932. +
  15933. + ath79_register_m25p80(&om2p_flash_data);
  15934. +
  15935. + ath79_register_mdio(0, ~OM2P_WAN_PHYMASK);
  15936. +
  15937. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  15938. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
  15939. +
  15940. + ath79_register_eth(0);
  15941. + ath79_register_eth(1);
  15942. +
  15943. + ap91_pci_init(ee, NULL);
  15944. +
  15945. + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
  15946. + om2p_leds_gpio);
  15947. +
  15948. + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
  15949. + ARRAY_SIZE(om2p_gpio_keys),
  15950. + om2p_gpio_keys);
  15951. +}
  15952. +
  15953. +MIPS_MACHINE(ATH79_MACH_OM2P, "OM2P", "OpenMesh OM2P", om2p_setup);
  15954. +
  15955. +
  15956. +static struct flash_platform_data om2p_lc_flash_data = {
  15957. + .type = "s25sl12800",
  15958. +};
  15959. +
  15960. +static void __init om2p_lc_setup(void)
  15961. +{
  15962. + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
  15963. + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
  15964. + u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
  15965. + u32 t;
  15966. +
  15967. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  15968. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  15969. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  15970. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  15971. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  15972. +
  15973. + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  15974. + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
  15975. + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
  15976. +
  15977. + ath79_register_m25p80(&om2p_lc_flash_data);
  15978. +
  15979. + om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER;
  15980. + om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED;
  15981. + om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW;
  15982. + om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN;
  15983. + om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN;
  15984. + om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN;
  15985. + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
  15986. + om2p_leds_gpio);
  15987. +
  15988. + om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET;
  15989. + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
  15990. + ARRAY_SIZE(om2p_gpio_keys),
  15991. + om2p_gpio_keys);
  15992. +
  15993. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  15994. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
  15995. +
  15996. + ath79_register_mdio(0, 0x0);
  15997. +
  15998. + ath79_register_eth(0);
  15999. + ath79_register_eth(1);
  16000. +
  16001. + ath79_register_wmac(art, NULL);
  16002. +}
  16003. +
  16004. +MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup);
  16005. +MIPS_MACHINE(ATH79_MACH_OM2Pv2, "OM2Pv2", "OpenMesh OM2Pv2", om2p_lc_setup);
  16006. +
  16007. +static void __init om2p_hs_setup(void)
  16008. +{
  16009. + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
  16010. + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
  16011. + u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
  16012. +
  16013. + /* make lan / wan leds software controllable */
  16014. + ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
  16015. + ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
  16016. +
  16017. + /* enable reset button */
  16018. + ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
  16019. + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
  16020. +
  16021. + om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
  16022. + om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
  16023. +
  16024. + ath79_register_m25p80(&om2p_lc_flash_data);
  16025. + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
  16026. + om2p_leds_gpio);
  16027. + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
  16028. + ARRAY_SIZE(om2p_gpio_keys),
  16029. + om2p_gpio_keys);
  16030. +
  16031. + ath79_register_wmac(art, NULL);
  16032. +
  16033. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  16034. + ath79_register_mdio(1, 0x0);
  16035. +
  16036. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  16037. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
  16038. +
  16039. + /* GMAC0 is connected to the PHY0 of the internal switch */
  16040. + ath79_switch_data.phy4_mii_en = 1;
  16041. + ath79_switch_data.phy_poll_mask = BIT(0);
  16042. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  16043. + ath79_eth0_data.phy_mask = BIT(0);
  16044. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  16045. + ath79_register_eth(0);
  16046. +
  16047. + /* GMAC1 is connected to the internal switch */
  16048. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  16049. + ath79_register_eth(1);
  16050. +}
  16051. +
  16052. +MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup);
  16053. +MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup);
  16054. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-om5p.c linux-4.1.43/arch/mips/ath79/mach-om5p.c
  16055. --- linux-4.1.43.orig/arch/mips/ath79/mach-om5p.c 1970-01-01 01:00:00.000000000 +0100
  16056. +++ linux-4.1.43/arch/mips/ath79/mach-om5p.c 2017-08-06 20:02:15.000000000 +0200
  16057. @@ -0,0 +1,218 @@
  16058. +/*
  16059. + * OpenMesh OM5P support
  16060. + *
  16061. + * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
  16062. + * Copyright (C) 2014 Sven Eckelmann <sven@open-mesh.com>
  16063. + *
  16064. + * This program is free software; you can redistribute it and/or modify it
  16065. + * under the terms of the GNU General Public License version 2 as published
  16066. + * by the Free Software Foundation.
  16067. + */
  16068. +
  16069. +#include <linux/gpio.h>
  16070. +#include <linux/mtd/mtd.h>
  16071. +#include <linux/mtd/partitions.h>
  16072. +#include <linux/platform_device.h>
  16073. +#include <linux/i2c.h>
  16074. +#include <linux/i2c-algo-bit.h>
  16075. +#include <linux/i2c-gpio.h>
  16076. +#include <linux/platform_data/phy-at803x.h>
  16077. +
  16078. +#include <asm/mach-ath79/ar71xx_regs.h>
  16079. +#include <asm/mach-ath79/ath79.h>
  16080. +
  16081. +#include "common.h"
  16082. +#include "dev-ap9x-pci.h"
  16083. +#include "dev-eth.h"
  16084. +#include "dev-gpio-buttons.h"
  16085. +#include "dev-leds-gpio.h"
  16086. +#include "dev-m25p80.h"
  16087. +#include "dev-wmac.h"
  16088. +#include "machtypes.h"
  16089. +
  16090. +#define OM5P_GPIO_LED_POWER 13
  16091. +#define OM5P_GPIO_LED_GREEN 16
  16092. +#define OM5P_GPIO_LED_RED 19
  16093. +#define OM5P_GPIO_LED_YELLOW 17
  16094. +#define OM5P_GPIO_LED_LAN 14
  16095. +#define OM5P_GPIO_LED_WAN 15
  16096. +#define OM5P_GPIO_BTN_RESET 4
  16097. +#define OM5P_GPIO_I2C_SCL 20
  16098. +#define OM5P_GPIO_I2C_SDA 21
  16099. +
  16100. +#define OM5P_KEYS_POLL_INTERVAL 20 /* msecs */
  16101. +#define OM5P_KEYS_DEBOUNCE_INTERVAL (3 * OM5P_KEYS_POLL_INTERVAL)
  16102. +
  16103. +#define OM5P_WMAC_CALDATA_OFFSET 0x1000
  16104. +#define OM5P_PCI_CALDATA_OFFSET 0x5000
  16105. +
  16106. +static struct gpio_led om5p_leds_gpio[] __initdata = {
  16107. + {
  16108. + .name = "om5p:blue:power",
  16109. + .gpio = OM5P_GPIO_LED_POWER,
  16110. + .active_low = 1,
  16111. + }, {
  16112. + .name = "om5p:red:wifi",
  16113. + .gpio = OM5P_GPIO_LED_RED,
  16114. + .active_low = 1,
  16115. + }, {
  16116. + .name = "om5p:yellow:wifi",
  16117. + .gpio = OM5P_GPIO_LED_YELLOW,
  16118. + .active_low = 1,
  16119. + }, {
  16120. + .name = "om5p:green:wifi",
  16121. + .gpio = OM5P_GPIO_LED_GREEN,
  16122. + .active_low = 1,
  16123. + }, {
  16124. + .name = "om5p:blue:lan",
  16125. + .gpio = OM5P_GPIO_LED_LAN,
  16126. + .active_low = 1,
  16127. + }, {
  16128. + .name = "om5p:blue:wan",
  16129. + .gpio = OM5P_GPIO_LED_WAN,
  16130. + .active_low = 1,
  16131. + }
  16132. +};
  16133. +
  16134. +static struct gpio_keys_button om5p_gpio_keys[] __initdata = {
  16135. + {
  16136. + .desc = "reset",
  16137. + .type = EV_KEY,
  16138. + .code = KEY_RESTART,
  16139. + .debounce_interval = OM5P_KEYS_DEBOUNCE_INTERVAL,
  16140. + .gpio = OM5P_GPIO_BTN_RESET,
  16141. + .active_low = 1,
  16142. + }
  16143. +};
  16144. +
  16145. +static struct flash_platform_data om5p_flash_data = {
  16146. + .type = "mx25l12805d",
  16147. +};
  16148. +
  16149. +static void __init om5p_setup(void)
  16150. +{
  16151. + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
  16152. + u8 mac[6];
  16153. +
  16154. + /* make lan / wan leds software controllable */
  16155. + ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
  16156. + ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
  16157. +
  16158. + ath79_register_m25p80(&om5p_flash_data);
  16159. + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
  16160. + om5p_leds_gpio);
  16161. + ath79_register_gpio_keys_polled(-1, OM5P_KEYS_POLL_INTERVAL,
  16162. + ARRAY_SIZE(om5p_gpio_keys),
  16163. + om5p_gpio_keys);
  16164. +
  16165. + ath79_init_mac(mac, art, 2);
  16166. + ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
  16167. +
  16168. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  16169. + ath79_register_mdio(1, 0x0);
  16170. +
  16171. + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
  16172. + ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
  16173. +
  16174. + /* GMAC0 is connected to the PHY0 of the internal switch */
  16175. + ath79_switch_data.phy4_mii_en = 1;
  16176. + ath79_switch_data.phy_poll_mask = BIT(0);
  16177. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  16178. + ath79_eth0_data.phy_mask = BIT(0);
  16179. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  16180. + ath79_register_eth(0);
  16181. +
  16182. + /* GMAC1 is connected to the internal switch */
  16183. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  16184. + ath79_register_eth(1);
  16185. +}
  16186. +
  16187. +MIPS_MACHINE(ATH79_MACH_OM5P, "OM5P", "OpenMesh OM5P", om5p_setup);
  16188. +
  16189. +static struct i2c_gpio_platform_data om5pan_i2c_device_platdata = {
  16190. + .sda_pin = OM5P_GPIO_I2C_SDA,
  16191. + .scl_pin = OM5P_GPIO_I2C_SCL,
  16192. + .udelay = 10,
  16193. + .sda_is_open_drain = 1,
  16194. + .scl_is_open_drain = 1,
  16195. +};
  16196. +
  16197. +static struct platform_device om5pan_i2c_device = {
  16198. + .name = "i2c-gpio",
  16199. + .id = 0,
  16200. + .dev = {
  16201. + .platform_data = &om5pan_i2c_device_platdata,
  16202. + },
  16203. +};
  16204. +
  16205. +static struct i2c_board_info om5pan_i2c_devs[] __initdata = {
  16206. + {
  16207. + I2C_BOARD_INFO("tmp423", 0x4c),
  16208. + },
  16209. +};
  16210. +
  16211. +static struct at803x_platform_data om5p_an_at803x_data = {
  16212. + .disable_smarteee = 1,
  16213. + .enable_rgmii_rx_delay = 1,
  16214. + .enable_rgmii_tx_delay = 1,
  16215. +};
  16216. +
  16217. +static struct mdio_board_info om5p_an_mdio0_info[] = {
  16218. + {
  16219. + .bus_id = "ag71xx-mdio.0",
  16220. + .phy_addr = 7,
  16221. + .platform_data = &om5p_an_at803x_data,
  16222. + },
  16223. +};
  16224. +
  16225. +static void __init om5p_an_setup(void)
  16226. +{
  16227. + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
  16228. + u8 mac[6];
  16229. +
  16230. + /* temperature sensor */
  16231. + platform_device_register(&om5pan_i2c_device);
  16232. + i2c_register_board_info(0, om5pan_i2c_devs,
  16233. + ARRAY_SIZE(om5pan_i2c_devs));
  16234. +
  16235. + /* make lan / wan leds software controllable */
  16236. + ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
  16237. + ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
  16238. +
  16239. + ath79_register_m25p80(&om5p_flash_data);
  16240. + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
  16241. + om5p_leds_gpio);
  16242. +
  16243. + ath79_init_mac(mac, art, 0x02);
  16244. + ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
  16245. +
  16246. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  16247. + ath79_setup_ar934x_eth_rx_delay(2, 2);
  16248. + ath79_register_mdio(0, 0x0);
  16249. + ath79_register_mdio(1, 0x0);
  16250. +
  16251. + mdiobus_register_board_info(om5p_an_mdio0_info,
  16252. + ARRAY_SIZE(om5p_an_mdio0_info));
  16253. +
  16254. + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
  16255. + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
  16256. +
  16257. + /* GMAC0 is connected to the PHY7 */
  16258. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  16259. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  16260. + ath79_eth0_data.phy_mask = BIT(7);
  16261. + ath79_eth0_pll_data.pll_1000 = 0x02000000;
  16262. + ath79_eth0_pll_data.pll_100 = 0x00000101;
  16263. + ath79_eth0_pll_data.pll_10 = 0x00001313;
  16264. + ath79_register_eth(0);
  16265. +
  16266. + /* GMAC1 is connected to the internal switch */
  16267. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  16268. + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
  16269. + ath79_register_eth(1);
  16270. +
  16271. + ath79_init_mac(mac, art, 0x10);
  16272. + ap91_pci_init(art + OM5P_PCI_CALDATA_OFFSET, mac);
  16273. +}
  16274. +
  16275. +MIPS_MACHINE(ATH79_MACH_OM5P_AN, "OM5P-AN", "OpenMesh OM5P AN", om5p_an_setup);
  16276. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-onion-omega.c linux-4.1.43/arch/mips/ath79/mach-onion-omega.c
  16277. --- linux-4.1.43.orig/arch/mips/ath79/mach-onion-omega.c 1970-01-01 01:00:00.000000000 +0100
  16278. +++ linux-4.1.43/arch/mips/ath79/mach-onion-omega.c 2017-08-06 20:02:15.000000000 +0200
  16279. @@ -0,0 +1,84 @@
  16280. +/*
  16281. + * Onion Omega board support
  16282. + *
  16283. + * Copyright (C) 2015 Boken Lin <bl@onion.io>
  16284. + *
  16285. + * This program is free software; you can redistribute it and/or modify it
  16286. + * under the terms of the GNU General Public License version 2 as published
  16287. + * by the Free Software Foundation.
  16288. + */
  16289. +
  16290. +#include <linux/gpio.h>
  16291. +
  16292. +#include <asm/mach-ath79/ath79.h>
  16293. +
  16294. +#include "dev-eth.h"
  16295. +#include "dev-gpio-buttons.h"
  16296. +#include "dev-leds-gpio.h"
  16297. +#include "dev-m25p80.h"
  16298. +#include "dev-usb.h"
  16299. +#include "dev-wmac.h"
  16300. +#include "machtypes.h"
  16301. +
  16302. +#define OMEGA_GPIO_LED_SYSTEM 27
  16303. +#define OMEGA_GPIO_BTN_RESET 11
  16304. +
  16305. +#define OMEGA_GPIO_USB_POWER 8
  16306. +
  16307. +#define OMEGA_KEYS_POLL_INTERVAL 20 /* msecs */
  16308. +#define OMEGA_KEYS_DEBOUNCE_INTERVAL (3 * OMEGA_KEYS_POLL_INTERVAL)
  16309. +
  16310. +static const char *omega_part_probes[] = {
  16311. + "tp-link",
  16312. + NULL,
  16313. +};
  16314. +
  16315. +static struct flash_platform_data omega_flash_data = {
  16316. + .part_probes = omega_part_probes,
  16317. +};
  16318. +
  16319. +static struct gpio_led omega_leds_gpio[] __initdata = {
  16320. + {
  16321. + .name = "onion:amber:system",
  16322. + .gpio = OMEGA_GPIO_LED_SYSTEM,
  16323. + .active_low = 1,
  16324. + },
  16325. +};
  16326. +
  16327. +static struct gpio_keys_button omega_gpio_keys[] __initdata = {
  16328. + {
  16329. + .desc = "reset",
  16330. + .type = EV_KEY,
  16331. + .code = KEY_RESTART,
  16332. + .debounce_interval = OMEGA_KEYS_DEBOUNCE_INTERVAL,
  16333. + .gpio = OMEGA_GPIO_BTN_RESET,
  16334. + .active_low = 0,
  16335. + }
  16336. +};
  16337. +
  16338. +static void __init onion_omega_setup(void)
  16339. +{
  16340. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  16341. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  16342. +
  16343. + ath79_register_m25p80(&omega_flash_data);
  16344. + ath79_register_leds_gpio(-1, ARRAY_SIZE(omega_leds_gpio),
  16345. + omega_leds_gpio);
  16346. + ath79_register_gpio_keys_polled(-1, OMEGA_KEYS_POLL_INTERVAL,
  16347. + ARRAY_SIZE(omega_gpio_keys),
  16348. + omega_gpio_keys);
  16349. +
  16350. + gpio_request_one(OMEGA_GPIO_USB_POWER,
  16351. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  16352. + "USB power");
  16353. + ath79_register_usb();
  16354. +
  16355. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
  16356. +
  16357. + ath79_register_mdio(0, 0x0);
  16358. + ath79_register_eth(0);
  16359. +
  16360. + ath79_register_wmac(ee, mac);
  16361. +}
  16362. +
  16363. +MIPS_MACHINE(ATH79_MACH_ONION_OMEGA, "ONION-OMEGA", "Onion Omega", onion_omega_setup);
  16364. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-pb42.c linux-4.1.43/arch/mips/ath79/mach-pb42.c
  16365. --- linux-4.1.43.orig/arch/mips/ath79/mach-pb42.c 1970-01-01 01:00:00.000000000 +0100
  16366. +++ linux-4.1.43/arch/mips/ath79/mach-pb42.c 2017-08-06 20:02:15.000000000 +0200
  16367. @@ -0,0 +1,83 @@
  16368. +/*
  16369. + * Atheros PB42 board support
  16370. + *
  16371. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  16372. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  16373. + *
  16374. + * This program is free software; you can redistribute it and/or modify it
  16375. + * under the terms of the GNU General Public License version 2 as published
  16376. + * by the Free Software Foundation.
  16377. + */
  16378. +
  16379. +#include <asm/mach-ath79/ath79.h>
  16380. +
  16381. +#include "dev-eth.h"
  16382. +#include "dev-gpio-buttons.h"
  16383. +#include "dev-m25p80.h"
  16384. +#include "dev-usb.h"
  16385. +#include "machtypes.h"
  16386. +#include "pci.h"
  16387. +
  16388. +#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */
  16389. +#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL)
  16390. +
  16391. +#define PB42_GPIO_BTN_SW4 8
  16392. +#define PB42_GPIO_BTN_SW5 3
  16393. +
  16394. +static struct gpio_keys_button pb42_gpio_keys[] __initdata = {
  16395. + {
  16396. + .desc = "sw4",
  16397. + .type = EV_KEY,
  16398. + .code = BTN_0,
  16399. + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
  16400. + .gpio = PB42_GPIO_BTN_SW4,
  16401. + .active_low = 1,
  16402. + }, {
  16403. + .desc = "sw5",
  16404. + .type = EV_KEY,
  16405. + .code = BTN_1,
  16406. + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
  16407. + .gpio = PB42_GPIO_BTN_SW5,
  16408. + .active_low = 1,
  16409. + }
  16410. +};
  16411. +
  16412. +static const char *pb42_part_probes[] = {
  16413. + "RedBoot",
  16414. + NULL,
  16415. +};
  16416. +
  16417. +static struct flash_platform_data pb42_flash_data = {
  16418. + .part_probes = pb42_part_probes,
  16419. +};
  16420. +
  16421. +#define PB42_WAN_PHYMASK BIT(20)
  16422. +#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19))
  16423. +#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
  16424. +
  16425. +static void __init pb42_init(void)
  16426. +{
  16427. + ath79_register_m25p80(&pb42_flash_data);
  16428. +
  16429. + ath79_register_mdio(0, ~PB42_MDIO_PHYMASK);
  16430. +
  16431. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  16432. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  16433. + ath79_eth0_data.phy_mask = PB42_WAN_PHYMASK;
  16434. +
  16435. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  16436. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  16437. + ath79_eth1_data.speed = SPEED_100;
  16438. + ath79_eth1_data.duplex = DUPLEX_FULL;
  16439. +
  16440. + ath79_register_eth(0);
  16441. + ath79_register_eth(1);
  16442. +
  16443. + ath79_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL,
  16444. + ARRAY_SIZE(pb42_gpio_keys),
  16445. + pb42_gpio_keys);
  16446. +
  16447. + ath79_register_pci();
  16448. +}
  16449. +
  16450. +MIPS_MACHINE(ATH79_MACH_PB42, "PB42", "Atheros PB42", pb42_init);
  16451. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-pb44.c linux-4.1.43/arch/mips/ath79/mach-pb44.c
  16452. --- linux-4.1.43.orig/arch/mips/ath79/mach-pb44.c 2017-08-06 01:56:14.000000000 +0200
  16453. +++ linux-4.1.43/arch/mips/ath79/mach-pb44.c 2017-08-06 20:02:15.000000000 +0200
  16454. @@ -8,23 +8,48 @@
  16455. * by the Free Software Foundation.
  16456. */
  16457. +#include <linux/delay.h>
  16458. #include <linux/init.h>
  16459. #include <linux/platform_device.h>
  16460. #include <linux/i2c.h>
  16461. #include <linux/i2c-gpio.h>
  16462. #include <linux/i2c/pcf857x.h>
  16463. +#include <linux/i2c/pcf857x.h>
  16464. +#include <linux/spi/flash.h>
  16465. +#include <linux/spi/vsc7385.h>
  16466. -#include "machtypes.h"
  16467. +#include <asm/mach-ath79/ar71xx_regs.h>
  16468. +#include <asm/mach-ath79/ath79.h>
  16469. +
  16470. +#include "dev-eth.h"
  16471. #include "dev-gpio-buttons.h"
  16472. #include "dev-leds-gpio.h"
  16473. #include "dev-spi.h"
  16474. #include "dev-usb.h"
  16475. +#include "machtypes.h"
  16476. #include "pci.h"
  16477. #define PB44_GPIO_I2C_SCL 0
  16478. #define PB44_GPIO_I2C_SDA 1
  16479. +#define PB44_PCF8757_VSC7395_CS 0
  16480. +#define PB44_PCF8757_STEREO_CS 1
  16481. +#define PB44_PCF8757_SLIC_CS0 2
  16482. +#define PB44_PCF8757_SLIC_TEST 3
  16483. +#define PB44_PCF8757_SLIC_INT0 4
  16484. +#define PB44_PCF8757_SLIC_INT1 5
  16485. +#define PB44_PCF8757_SW_RESET 6
  16486. +#define PB44_PCF8757_SW_JUMP 8
  16487. +#define PB44_PCF8757_LED_JUMP1 9
  16488. +#define PB44_PCF8757_LED_JUMP2 10
  16489. +#define PB44_PCF8757_TP24 11
  16490. +#define PB44_PCF8757_TP25 12
  16491. +#define PB44_PCF8757_TP26 13
  16492. +#define PB44_PCF8757_TP27 14
  16493. +#define PB44_PCF8757_TP28 15
  16494. +
  16495. #define PB44_GPIO_EXP_BASE 16
  16496. +#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
  16497. #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
  16498. #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
  16499. #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
  16500. @@ -87,20 +112,71 @@
  16501. }
  16502. };
  16503. +static struct ath79_spi_controller_data pb44_spi0_data = {
  16504. + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  16505. + .cs_line = 0,
  16506. +};
  16507. +
  16508. +static struct ath79_spi_controller_data pb44_spi1_data = {
  16509. + .cs_type = ATH79_SPI_CS_TYPE_GPIO,
  16510. + .cs_line = PB44_GPIO_VSC7395_CS,
  16511. +};
  16512. +
  16513. +static void pb44_vsc7395_reset(void)
  16514. +{
  16515. + ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
  16516. + udelay(10);
  16517. + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
  16518. + mdelay(50);
  16519. +}
  16520. +
  16521. +static struct vsc7385_platform_data pb44_vsc7395_data = {
  16522. + .reset = pb44_vsc7395_reset,
  16523. + .ucode_name = "vsc7395_ucode_pb44.bin",
  16524. + .mac_cfg = {
  16525. + .tx_ipg = 6,
  16526. + .bit2 = 1,
  16527. + .clk_sel = 0,
  16528. + },
  16529. +};
  16530. +
  16531. +static const char *pb44_part_probes[] = {
  16532. + "RedBoot",
  16533. + NULL,
  16534. +};
  16535. +
  16536. +static struct flash_platform_data pb44_flash_data = {
  16537. + .part_probes = pb44_part_probes,
  16538. +};
  16539. +
  16540. static struct spi_board_info pb44_spi_info[] = {
  16541. {
  16542. .bus_num = 0,
  16543. .chip_select = 0,
  16544. .max_speed_hz = 25000000,
  16545. .modalias = "m25p64",
  16546. + .platform_data = &pb44_flash_data,
  16547. + .controller_data = &pb44_spi0_data,
  16548. },
  16549. + {
  16550. + .bus_num = 0,
  16551. + .chip_select = 1,
  16552. + .max_speed_hz = 25000000,
  16553. + .modalias = "spi-vsc7385",
  16554. + .platform_data = &pb44_vsc7395_data,
  16555. + .controller_data = &pb44_spi1_data,
  16556. + }
  16557. };
  16558. static struct ath79_spi_platform_data pb44_spi_data = {
  16559. .bus_num = 0,
  16560. - .num_chipselect = 1,
  16561. + .num_chipselect = 2,
  16562. };
  16563. +#define PB44_WAN_PHYMASK BIT(0)
  16564. +#define PB44_LAN_PHYMASK 0
  16565. +#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
  16566. +
  16567. static void __init pb44_init(void)
  16568. {
  16569. i2c_register_board_info(0, pb44_i2c_board_info,
  16570. @@ -116,6 +192,22 @@
  16571. ARRAY_SIZE(pb44_spi_info));
  16572. ath79_register_usb();
  16573. ath79_register_pci();
  16574. +
  16575. + ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
  16576. +
  16577. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  16578. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  16579. + ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
  16580. +
  16581. + ath79_register_eth(0);
  16582. +
  16583. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  16584. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  16585. + ath79_eth1_data.speed = SPEED_1000;
  16586. + ath79_eth1_data.duplex = DUPLEX_FULL;
  16587. + ath79_eth1_pll_data.pll_1000 = 0x110000;
  16588. +
  16589. + ath79_register_eth(1);
  16590. }
  16591. MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
  16592. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-pb92.c linux-4.1.43/arch/mips/ath79/mach-pb92.c
  16593. --- linux-4.1.43.orig/arch/mips/ath79/mach-pb92.c 1970-01-01 01:00:00.000000000 +0100
  16594. +++ linux-4.1.43/arch/mips/ath79/mach-pb92.c 2017-08-06 20:02:15.000000000 +0200
  16595. @@ -0,0 +1,70 @@
  16596. +/*
  16597. + * Atheros PB92 board support
  16598. + *
  16599. + * Copyright (C) 2010 Felix Fietkau <nbd@openwrt.org>
  16600. + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  16601. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  16602. + *
  16603. + * This program is free software; you can redistribute it and/or modify it
  16604. + * under the terms of the GNU General Public License version 2 as published
  16605. + * by the Free Software Foundation.
  16606. + */
  16607. +
  16608. +#include <asm/mach-ath79/ath79.h>
  16609. +
  16610. +#include "dev-eth.h"
  16611. +#include "dev-gpio-buttons.h"
  16612. +#include "dev-m25p80.h"
  16613. +#include "dev-usb.h"
  16614. +#include "machtypes.h"
  16615. +#include "pci.h"
  16616. +
  16617. +#define PB92_KEYS_POLL_INTERVAL 20 /* msecs */
  16618. +#define PB92_KEYS_DEBOUNCE_INTERVAL (3 * PB92_KEYS_POLL_INTERVAL)
  16619. +
  16620. +#define PB92_GPIO_BTN_SW4 8
  16621. +#define PB92_GPIO_BTN_SW5 3
  16622. +
  16623. +static struct gpio_keys_button pb92_gpio_keys[] __initdata = {
  16624. + {
  16625. + .desc = "sw4",
  16626. + .type = EV_KEY,
  16627. + .code = BTN_0,
  16628. + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL,
  16629. + .gpio = PB92_GPIO_BTN_SW4,
  16630. + .active_low = 1,
  16631. + }, {
  16632. + .desc = "sw5",
  16633. + .type = EV_KEY,
  16634. + .code = BTN_1,
  16635. + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL,
  16636. + .gpio = PB92_GPIO_BTN_SW5,
  16637. + .active_low = 1,
  16638. + }
  16639. +};
  16640. +
  16641. +static void __init pb92_init(void)
  16642. +{
  16643. + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
  16644. +
  16645. + ath79_register_m25p80(NULL);
  16646. +
  16647. + ath79_register_mdio(0, ~BIT(0));
  16648. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  16649. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  16650. + ath79_eth0_data.speed = SPEED_1000;
  16651. + ath79_eth0_data.duplex = DUPLEX_FULL;
  16652. + ath79_eth0_data.phy_mask = BIT(0);
  16653. +
  16654. + ath79_register_eth(0);
  16655. +
  16656. + ath79_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL,
  16657. + ARRAY_SIZE(pb92_gpio_keys),
  16658. + pb92_gpio_keys);
  16659. +
  16660. + ath79_register_usb();
  16661. +
  16662. + ath79_register_pci();
  16663. +}
  16664. +
  16665. +MIPS_MACHINE(ATH79_MACH_PB92, "PB92", "Atheros PB92", pb92_init);
  16666. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-qihoo-c301.c linux-4.1.43/arch/mips/ath79/mach-qihoo-c301.c
  16667. --- linux-4.1.43.orig/arch/mips/ath79/mach-qihoo-c301.c 1970-01-01 01:00:00.000000000 +0100
  16668. +++ linux-4.1.43/arch/mips/ath79/mach-qihoo-c301.c 2017-08-06 20:02:15.000000000 +0200
  16669. @@ -0,0 +1,166 @@
  16670. +/*
  16671. + * Qihoo 360 C301 board support
  16672. + *
  16673. + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  16674. + * Copyright (C) 2014 Weijie Gao <hackpascal@gmail.com>
  16675. + *
  16676. + * This program is free software; you can redistribute it and/or modify it
  16677. + * under the terms of the GNU General Public License version 2 as published
  16678. + * by the Free Software Foundation.
  16679. + */
  16680. +
  16681. +#include <linux/pci.h>
  16682. +#include <linux/phy.h>
  16683. +#include <linux/gpio.h>
  16684. +#include <linux/platform_device.h>
  16685. +#include <linux/ath9k_platform.h>
  16686. +
  16687. +#include <asm/mach-ath79/ar71xx_regs.h>
  16688. +
  16689. +#include "common.h"
  16690. +#include "pci.h"
  16691. +#include "dev-eth.h"
  16692. +#include "dev-gpio-buttons.h"
  16693. +#include "dev-leds-gpio.h"
  16694. +#include "dev-m25p80.h"
  16695. +#include "dev-spi.h"
  16696. +#include "dev-usb.h"
  16697. +#include "dev-wmac.h"
  16698. +#include "machtypes.h"
  16699. +#include "nvram.h"
  16700. +
  16701. +#define QIHOO_C301_GPIO_LED_STATUS_GREEN 0
  16702. +#define QIHOO_C301_GPIO_LED_STATUS_RED 11
  16703. +
  16704. +#define QIHOO_C301_GPIO_LED_WAN 1
  16705. +#define QIHOO_C301_GPIO_LED_LAN1 2
  16706. +#define QIHOO_C301_GPIO_LED_LAN2 3
  16707. +#define QIHOO_C301_GPIO_ETH_LEN_EN 18
  16708. +
  16709. +#define QIHOO_C301_GPIO_BTN_RESET 16
  16710. +
  16711. +#define QIHOO_C301_GPIO_USB_POWER 19
  16712. +
  16713. +#define QIHOO_C301_GPIO_SPI_CS1 12
  16714. +
  16715. +#define QIHOO_C301_GPIO_EXTERNAL_LNA0 14
  16716. +#define QIHOO_C301_GPIO_EXTERNAL_LNA1 15
  16717. +
  16718. +#define QIHOO_C301_KEYS_POLL_INTERVAL 20 /* msecs */
  16719. +#define QIHOO_C301_KEYS_DEBOUNCE_INTERVAL \
  16720. + (3 * QIHOO_C301_KEYS_POLL_INTERVAL)
  16721. +
  16722. +#define QIHOO_C301_WMAC_CALDATA_OFFSET 0x1000
  16723. +
  16724. +#define QIHOO_C301_NVRAM_ADDR 0x1f058010
  16725. +#define QIHOO_C301_NVRAM_SIZE 0x7ff0
  16726. +
  16727. +static struct gpio_led qihoo_c301_leds_gpio[] __initdata = {
  16728. + {
  16729. + .name = "qihoo:green:status",
  16730. + .gpio = QIHOO_C301_GPIO_LED_STATUS_GREEN,
  16731. + .active_low = 1,
  16732. + },
  16733. + {
  16734. + .name = "qihoo:red:status",
  16735. + .gpio = QIHOO_C301_GPIO_LED_STATUS_RED,
  16736. + .active_low = 1,
  16737. + },
  16738. +};
  16739. +
  16740. +static struct gpio_keys_button qihoo_c301_gpio_keys[] __initdata = {
  16741. + {
  16742. + .desc = "reset",
  16743. + .type = EV_KEY,
  16744. + .code = KEY_RESTART,
  16745. + .debounce_interval = QIHOO_C301_KEYS_DEBOUNCE_INTERVAL,
  16746. + .gpio = QIHOO_C301_GPIO_BTN_RESET,
  16747. + .active_low = 1,
  16748. + },
  16749. +};
  16750. +
  16751. +static struct flash_platform_data flash __initdata = {NULL, NULL, 0};
  16752. +
  16753. +static void qihoo_c301_get_mac(const char *name, char *mac)
  16754. +{
  16755. + u8 *nvram = (u8 *) KSEG1ADDR(QIHOO_C301_NVRAM_ADDR);
  16756. + int err;
  16757. +
  16758. + err = ath79_nvram_parse_mac_addr(nvram, QIHOO_C301_NVRAM_SIZE,
  16759. + name, mac);
  16760. + if (err)
  16761. + pr_err("no MAC address found for %s\n", name);
  16762. +}
  16763. +
  16764. +static void __init qihoo_c301_setup(void)
  16765. +{
  16766. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  16767. + u8 tmpmac[ETH_ALEN];
  16768. +
  16769. + ath79_register_m25p80_multi(&flash);
  16770. +
  16771. + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
  16772. +
  16773. + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_WAN,
  16774. + AR934X_GPIO_OUT_LED_LINK4);
  16775. + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN1,
  16776. + AR934X_GPIO_OUT_LED_LINK1);
  16777. + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN2,
  16778. + AR934X_GPIO_OUT_LED_LINK2);
  16779. +
  16780. + ath79_gpio_output_select(QIHOO_C301_GPIO_SPI_CS1,
  16781. + AR934X_GPIO_OUT_SPI_CS1);
  16782. +
  16783. + gpio_request_one(QIHOO_C301_GPIO_ETH_LEN_EN,
  16784. + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
  16785. + "Ethernet LED enable");
  16786. +
  16787. + ath79_register_leds_gpio(-1, ARRAY_SIZE(qihoo_c301_leds_gpio),
  16788. + qihoo_c301_leds_gpio);
  16789. +
  16790. + ath79_register_gpio_keys_polled(-1, QIHOO_C301_KEYS_POLL_INTERVAL,
  16791. + ARRAY_SIZE(qihoo_c301_gpio_keys),
  16792. + qihoo_c301_gpio_keys);
  16793. +
  16794. + ath79_wmac_set_ext_lna_gpio(0, QIHOO_C301_GPIO_EXTERNAL_LNA0);
  16795. + ath79_wmac_set_ext_lna_gpio(1, QIHOO_C301_GPIO_EXTERNAL_LNA1);
  16796. +
  16797. + qihoo_c301_get_mac("wlan24mac=", tmpmac);
  16798. + ath79_register_wmac(art + QIHOO_C301_WMAC_CALDATA_OFFSET, tmpmac);
  16799. +
  16800. + ath79_register_pci();
  16801. +
  16802. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
  16803. + AR934X_ETH_CFG_SW_PHY_SWAP);
  16804. +
  16805. + ath79_register_mdio(1, 0x0);
  16806. +
  16807. + /* LAN */
  16808. + qihoo_c301_get_mac("lanmac=", ath79_eth1_data.mac_addr);
  16809. +
  16810. + /* GMAC1 is connected to the internal switch */
  16811. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  16812. +
  16813. + ath79_register_eth(1);
  16814. +
  16815. + /* WAN */
  16816. + qihoo_c301_get_mac("wanmac=", ath79_eth0_data.mac_addr);
  16817. +
  16818. + /* GMAC0 is connected to the PHY4 of the internal switch */
  16819. + ath79_switch_data.phy4_mii_en = 1;
  16820. + ath79_switch_data.phy_poll_mask = BIT(0);
  16821. +
  16822. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  16823. + ath79_eth0_data.phy_mask = BIT(0);
  16824. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  16825. +
  16826. + ath79_register_eth(0);
  16827. +
  16828. + gpio_request_one(QIHOO_C301_GPIO_USB_POWER,
  16829. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  16830. + "USB power");
  16831. + ath79_register_usb();
  16832. +}
  16833. +
  16834. +MIPS_MACHINE(ATH79_MACH_QIHOO_C301, "QIHOO-C301", "Qihoo 360 C301",
  16835. + qihoo_c301_setup);
  16836. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-r6100.c linux-4.1.43/arch/mips/ath79/mach-r6100.c
  16837. --- linux-4.1.43.orig/arch/mips/ath79/mach-r6100.c 1970-01-01 01:00:00.000000000 +0100
  16838. +++ linux-4.1.43/arch/mips/ath79/mach-r6100.c 2017-08-06 20:02:15.000000000 +0200
  16839. @@ -0,0 +1,146 @@
  16840. +/*
  16841. + * NETGEAR R6100 board support
  16842. + *
  16843. + * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
  16844. + * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
  16845. + *
  16846. + * This program is free software; you can redistribute it and/or modify it
  16847. + * under the terms of the GNU General Public License version 2 as published
  16848. + * by the Free Software Foundation.
  16849. + */
  16850. +
  16851. +#include <linux/pci.h>
  16852. +#include <linux/phy.h>
  16853. +#include <linux/gpio.h>
  16854. +#include <linux/platform_device.h>
  16855. +#include <linux/ath9k_platform.h>
  16856. +#include <linux/platform/ar934x_nfc.h>
  16857. +
  16858. +#include <asm/mach-ath79/ar71xx_regs.h>
  16859. +
  16860. +#include "common.h"
  16861. +#include "dev-ap9x-pci.h"
  16862. +#include "dev-eth.h"
  16863. +#include "dev-gpio-buttons.h"
  16864. +#include "dev-leds-gpio.h"
  16865. +#include "dev-nfc.h"
  16866. +#include "dev-usb.h"
  16867. +#include "dev-wmac.h"
  16868. +#include "machtypes.h"
  16869. +
  16870. +#define R6100_GPIO_LED_WLAN 0
  16871. +#define R6100_GPIO_LED_USB 11
  16872. +#define R6100_GPIO_LED_WAN_GREEN 13
  16873. +#define R6100_GPIO_LED_POWER_AMBER 14
  16874. +#define R6100_GPIO_LED_WAN_AMBER 15
  16875. +#define R6100_GPIO_LED_POWER_GREEN 17
  16876. +
  16877. +#define R6100_GPIO_BTN_WIRELESS 1
  16878. +#define R6100_GPIO_BTN_WPS 3
  16879. +#define R6100_GPIO_BTN_RESET 12
  16880. +
  16881. +#define R6100_GPIO_USB_POWER 16
  16882. +
  16883. +#define R6100_KEYS_POLL_INTERVAL 20 /* msecs */
  16884. +#define R6100_KEYS_DEBOUNCE_INTERVAL (3 * R6100_KEYS_POLL_INTERVAL)
  16885. +
  16886. +static struct gpio_led r6100_leds_gpio[] __initdata = {
  16887. + {
  16888. + .name = "netgear:green:power",
  16889. + .gpio = R6100_GPIO_LED_POWER_GREEN,
  16890. + .active_low = 1,
  16891. + },
  16892. + {
  16893. + .name = "netgear:amber:power",
  16894. + .gpio = R6100_GPIO_LED_POWER_AMBER,
  16895. + .active_low = 1,
  16896. + },
  16897. + {
  16898. + .name = "netgear:green:wan",
  16899. + .gpio = R6100_GPIO_LED_WAN_GREEN,
  16900. + .active_low = 1,
  16901. + },
  16902. + {
  16903. + .name = "netgear:amber:wan",
  16904. + .gpio = R6100_GPIO_LED_WAN_AMBER,
  16905. + .active_low = 1,
  16906. + },
  16907. + {
  16908. + .name = "netgear:blue:usb",
  16909. + .gpio = R6100_GPIO_LED_USB,
  16910. + .active_low = 1,
  16911. + },
  16912. + {
  16913. + .name = "netgear:blue:wlan",
  16914. + .gpio = R6100_GPIO_LED_WLAN,
  16915. + .active_low = 1,
  16916. + },
  16917. +};
  16918. +
  16919. +static struct gpio_keys_button r6100_gpio_keys[] __initdata = {
  16920. + {
  16921. + .desc = "Reset button",
  16922. + .type = EV_KEY,
  16923. + .code = KEY_RESTART,
  16924. + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL,
  16925. + .gpio = R6100_GPIO_BTN_RESET,
  16926. + .active_low = 0,
  16927. + },
  16928. + {
  16929. + .desc = "WPS button",
  16930. + .type = EV_KEY,
  16931. + .code = KEY_WPS_BUTTON,
  16932. + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL,
  16933. + .gpio = R6100_GPIO_BTN_WPS,
  16934. + .active_low = 0,
  16935. + },
  16936. + {
  16937. + .desc = "RFKILL switch",
  16938. + .type = EV_SW,
  16939. + .code = KEY_RFKILL,
  16940. + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL,
  16941. + .gpio = R6100_GPIO_BTN_WIRELESS,
  16942. + .active_low = 0,
  16943. + },
  16944. +};
  16945. +
  16946. +static void __init r6100_setup(void)
  16947. +{
  16948. + ath79_register_leds_gpio(-1, ARRAY_SIZE(r6100_leds_gpio),
  16949. + r6100_leds_gpio);
  16950. + ath79_register_gpio_keys_polled(-1, R6100_KEYS_POLL_INTERVAL,
  16951. + ARRAY_SIZE(r6100_gpio_keys),
  16952. + r6100_gpio_keys);
  16953. +
  16954. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  16955. +
  16956. + ath79_register_mdio(1, 0x0);
  16957. +
  16958. + /* GMAC0 is connected to the PHY0 of the internal switch */
  16959. + ath79_switch_data.phy4_mii_en = 1;
  16960. + ath79_switch_data.phy_poll_mask = BIT(0);
  16961. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  16962. + ath79_eth0_data.phy_mask = BIT(0);
  16963. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  16964. + ath79_register_eth(0);
  16965. +
  16966. + /* GMAC1 is connected to the internal switch */
  16967. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  16968. + ath79_register_eth(1);
  16969. +
  16970. + gpio_request_one(R6100_GPIO_USB_POWER,
  16971. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  16972. + "USB power");
  16973. +
  16974. + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
  16975. + ath79_register_nfc();
  16976. +
  16977. + ath79_register_usb();
  16978. +
  16979. + ath79_register_wmac_simple();
  16980. +
  16981. + ap91_pci_init_simple();
  16982. +}
  16983. +
  16984. +MIPS_MACHINE(ATH79_MACH_R6100, "R6100", "NETGEAR R6100",
  16985. + r6100_setup);
  16986. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rb2011.c linux-4.1.43/arch/mips/ath79/mach-rb2011.c
  16987. --- linux-4.1.43.orig/arch/mips/ath79/mach-rb2011.c 1970-01-01 01:00:00.000000000 +0100
  16988. +++ linux-4.1.43/arch/mips/ath79/mach-rb2011.c 2017-08-06 20:02:15.000000000 +0200
  16989. @@ -0,0 +1,338 @@
  16990. +/*
  16991. + * MikroTik RouterBOARD 2011 support
  16992. + *
  16993. + * Copyright (C) 2012 Stijn Tintel <stijn@linux-ipv6.be>
  16994. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  16995. + *
  16996. + * This program is free software; you can redistribute it and/or modify it
  16997. + * under the terms of the GNU General Public License version 2 as published
  16998. + * by the Free Software Foundation.
  16999. + */
  17000. +
  17001. +#define pr_fmt(fmt) "rb2011: " fmt
  17002. +
  17003. +#include <linux/phy.h>
  17004. +#include <linux/delay.h>
  17005. +#include <linux/platform_device.h>
  17006. +#include <linux/ath9k_platform.h>
  17007. +#include <linux/ar8216_platform.h>
  17008. +#include <linux/mtd/mtd.h>
  17009. +#include <linux/mtd/nand.h>
  17010. +#include <linux/mtd/partitions.h>
  17011. +#include <linux/spi/spi.h>
  17012. +#include <linux/spi/flash.h>
  17013. +#include <linux/routerboot.h>
  17014. +#include <linux/gpio.h>
  17015. +
  17016. +#include <asm/prom.h>
  17017. +#include <asm/mach-ath79/ath79.h>
  17018. +#include <asm/mach-ath79/ar71xx_regs.h>
  17019. +
  17020. +#include "common.h"
  17021. +#include "dev-eth.h"
  17022. +#include "dev-m25p80.h"
  17023. +#include "dev-nfc.h"
  17024. +#include "dev-usb.h"
  17025. +#include "dev-wmac.h"
  17026. +#include "machtypes.h"
  17027. +#include "routerboot.h"
  17028. +
  17029. +#define RB2011_GPIO_NAND_NCE 14
  17030. +#define RB2011_GPIO_SFP_LOS 21
  17031. +
  17032. +#define RB_ROUTERBOOT_OFFSET 0x0000
  17033. +#define RB_ROUTERBOOT_MIN_SIZE 0xb000
  17034. +#define RB_HARD_CFG_SIZE 0x1000
  17035. +#define RB_BIOS_OFFSET 0xd000
  17036. +#define RB_BIOS_SIZE 0x1000
  17037. +#define RB_SOFT_CFG_OFFSET 0xf000
  17038. +#define RB_SOFT_CFG_SIZE 0x1000
  17039. +
  17040. +#define RB_ART_SIZE 0x10000
  17041. +
  17042. +#define RB2011_FLAG_SFP BIT(0)
  17043. +#define RB2011_FLAG_USB BIT(1)
  17044. +#define RB2011_FLAG_WLAN BIT(2)
  17045. +
  17046. +static struct mtd_partition rb2011_spi_partitions[] = {
  17047. + {
  17048. + .name = "routerboot",
  17049. + .offset = RB_ROUTERBOOT_OFFSET,
  17050. + .mask_flags = MTD_WRITEABLE,
  17051. + }, {
  17052. + .name = "hard_config",
  17053. + .size = RB_HARD_CFG_SIZE,
  17054. + .mask_flags = MTD_WRITEABLE,
  17055. + }, {
  17056. + .name = "bios",
  17057. + .offset = RB_BIOS_OFFSET,
  17058. + .size = RB_BIOS_SIZE,
  17059. + .mask_flags = MTD_WRITEABLE,
  17060. + }, {
  17061. + .name = "soft_config",
  17062. + .size = RB_SOFT_CFG_SIZE,
  17063. + }
  17064. +};
  17065. +
  17066. +static void __init rb2011_init_partitions(const struct rb_info *info)
  17067. +{
  17068. + rb2011_spi_partitions[0].size = info->hard_cfg_offs;
  17069. + rb2011_spi_partitions[1].offset = info->hard_cfg_offs;
  17070. + rb2011_spi_partitions[3].offset = info->soft_cfg_offs;
  17071. +}
  17072. +
  17073. +static struct mtd_partition rb2011_nand_partitions[] = {
  17074. + {
  17075. + .name = "booter",
  17076. + .offset = 0,
  17077. + .size = (256 * 1024),
  17078. + .mask_flags = MTD_WRITEABLE,
  17079. + },
  17080. + {
  17081. + .name = "kernel",
  17082. + .offset = (256 * 1024),
  17083. + .size = (4 * 1024 * 1024) - (256 * 1024),
  17084. + },
  17085. + {
  17086. + .name = "rootfs",
  17087. + .offset = MTDPART_OFS_NXTBLK,
  17088. + .size = MTDPART_SIZ_FULL,
  17089. + },
  17090. +};
  17091. +
  17092. +static struct flash_platform_data rb2011_spi_flash_data = {
  17093. + .parts = rb2011_spi_partitions,
  17094. + .nr_parts = ARRAY_SIZE(rb2011_spi_partitions),
  17095. +};
  17096. +
  17097. +static struct ar8327_pad_cfg rb2011_ar8327_pad0_cfg = {
  17098. + .mode = AR8327_PAD_MAC_RGMII,
  17099. + .txclk_delay_en = true,
  17100. + .rxclk_delay_en = true,
  17101. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL3,
  17102. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
  17103. +};
  17104. +
  17105. +static struct ar8327_pad_cfg rb2011_ar8327_pad6_cfg;
  17106. +static struct ar8327_sgmii_cfg rb2011_ar8327_sgmii_cfg;
  17107. +
  17108. +static struct ar8327_led_cfg rb2011_ar8327_led_cfg = {
  17109. + .led_ctrl0 = 0xc731c731,
  17110. + .led_ctrl1 = 0x00000000,
  17111. + .led_ctrl2 = 0x00000000,
  17112. + .led_ctrl3 = 0x0030c300,
  17113. + .open_drain = false,
  17114. +};
  17115. +
  17116. +static const struct ar8327_led_info rb2011_ar8327_leds[] __initconst = {
  17117. + AR8327_LED_INFO(PHY0_0, HW, "rb:green:eth1"),
  17118. + AR8327_LED_INFO(PHY1_0, HW, "rb:green:eth2"),
  17119. + AR8327_LED_INFO(PHY2_0, HW, "rb:green:eth3"),
  17120. + AR8327_LED_INFO(PHY3_0, HW, "rb:green:eth4"),
  17121. + AR8327_LED_INFO(PHY4_0, HW, "rb:green:eth5"),
  17122. + AR8327_LED_INFO(PHY0_1, SW, "rb:green:eth6"),
  17123. + AR8327_LED_INFO(PHY1_1, SW, "rb:green:eth7"),
  17124. + AR8327_LED_INFO(PHY2_1, SW, "rb:green:eth8"),
  17125. + AR8327_LED_INFO(PHY3_1, SW, "rb:green:eth9"),
  17126. + AR8327_LED_INFO(PHY4_1, SW, "rb:green:eth10"),
  17127. + AR8327_LED_INFO(PHY4_2, SW, "rb:green:usr"),
  17128. +};
  17129. +
  17130. +static struct ar8327_platform_data rb2011_ar8327_data = {
  17131. + .pad0_cfg = &rb2011_ar8327_pad0_cfg,
  17132. + .port0_cfg = {
  17133. + .force_link = 1,
  17134. + .speed = AR8327_PORT_SPEED_1000,
  17135. + .duplex = 1,
  17136. + .txpause = 1,
  17137. + .rxpause = 1,
  17138. + },
  17139. + .led_cfg = &rb2011_ar8327_led_cfg,
  17140. + .num_leds = ARRAY_SIZE(rb2011_ar8327_leds),
  17141. + .leds = rb2011_ar8327_leds,
  17142. +};
  17143. +
  17144. +static struct mdio_board_info rb2011_mdio0_info[] = {
  17145. + {
  17146. + .bus_id = "ag71xx-mdio.0",
  17147. + .phy_addr = 0,
  17148. + .platform_data = &rb2011_ar8327_data,
  17149. + },
  17150. +};
  17151. +
  17152. +static void __init rb2011_wlan_init(void)
  17153. +{
  17154. + char *art_buf;
  17155. + u8 wlan_mac[ETH_ALEN];
  17156. +
  17157. + art_buf = rb_get_wlan_data();
  17158. + if (art_buf == NULL)
  17159. + return;
  17160. +
  17161. + ath79_init_mac(wlan_mac, ath79_mac_base, 11);
  17162. + ath79_register_wmac(art_buf + 0x1000, wlan_mac);
  17163. +
  17164. + kfree(art_buf);
  17165. +}
  17166. +
  17167. +static void rb2011_nand_select_chip(int chip_no)
  17168. +{
  17169. + switch (chip_no) {
  17170. + case 0:
  17171. + gpio_set_value(RB2011_GPIO_NAND_NCE, 0);
  17172. + break;
  17173. + default:
  17174. + gpio_set_value(RB2011_GPIO_NAND_NCE, 1);
  17175. + break;
  17176. + }
  17177. + ndelay(500);
  17178. +}
  17179. +
  17180. +static struct nand_ecclayout rb2011_nand_ecclayout = {
  17181. + .eccbytes = 6,
  17182. + .eccpos = { 8, 9, 10, 13, 14, 15 },
  17183. + .oobavail = 9,
  17184. + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  17185. +};
  17186. +
  17187. +static int rb2011_nand_scan_fixup(struct mtd_info *mtd)
  17188. +{
  17189. + struct nand_chip *chip = mtd->priv;
  17190. +
  17191. + if (mtd->writesize == 512) {
  17192. + /*
  17193. + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
  17194. + * will not be able to find the kernel that we load.
  17195. + */
  17196. + chip->ecc.layout = &rb2011_nand_ecclayout;
  17197. + }
  17198. +
  17199. + return 0;
  17200. +}
  17201. +
  17202. +static void __init rb2011_nand_init(void)
  17203. +{
  17204. + gpio_request_one(RB2011_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE");
  17205. +
  17206. + ath79_nfc_set_scan_fixup(rb2011_nand_scan_fixup);
  17207. + ath79_nfc_set_parts(rb2011_nand_partitions,
  17208. + ARRAY_SIZE(rb2011_nand_partitions));
  17209. + ath79_nfc_set_select_chip(rb2011_nand_select_chip);
  17210. + ath79_nfc_set_swap_dma(true);
  17211. + ath79_register_nfc();
  17212. +}
  17213. +
  17214. +static int rb2011_get_port_link(unsigned port)
  17215. +{
  17216. + if (port != 6)
  17217. + return -EINVAL;
  17218. +
  17219. + /* The Loss of signal line is active low */
  17220. + return !gpio_get_value(RB2011_GPIO_SFP_LOS);
  17221. +}
  17222. +
  17223. +static void __init rb2011_sfp_init(void)
  17224. +{
  17225. + gpio_request_one(RB2011_GPIO_SFP_LOS, GPIOF_IN, "SFP LOS");
  17226. +
  17227. + rb2011_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
  17228. +
  17229. + rb2011_ar8327_data.pad6_cfg = &rb2011_ar8327_pad6_cfg;
  17230. +
  17231. + rb2011_ar8327_sgmii_cfg.sgmii_ctrl = 0xc70167d0;
  17232. + rb2011_ar8327_sgmii_cfg.serdes_aen = true;
  17233. +
  17234. + rb2011_ar8327_data.sgmii_cfg = &rb2011_ar8327_sgmii_cfg;
  17235. +
  17236. + rb2011_ar8327_data.port6_cfg.force_link = 1;
  17237. + rb2011_ar8327_data.port6_cfg.speed = AR8327_PORT_SPEED_1000;
  17238. + rb2011_ar8327_data.port6_cfg.duplex = 1;
  17239. +
  17240. + rb2011_ar8327_data.get_port_link = rb2011_get_port_link;
  17241. +}
  17242. +
  17243. +static int __init rb2011_setup(u32 flags)
  17244. +{
  17245. + const struct rb_info *info;
  17246. + char buf[64];
  17247. +
  17248. + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000);
  17249. + if (!info)
  17250. + return -ENODEV;
  17251. +
  17252. + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s",
  17253. + (info->board_name) ? info->board_name : "");
  17254. + mips_set_machine_name(buf);
  17255. +
  17256. + rb2011_init_partitions(info);
  17257. +
  17258. + ath79_register_m25p80(&rb2011_spi_flash_data);
  17259. + rb2011_nand_init();
  17260. +
  17261. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  17262. + AR934X_ETH_CFG_SW_ONLY_MODE);
  17263. +
  17264. + ath79_register_mdio(1, 0x0);
  17265. + ath79_register_mdio(0, 0x0);
  17266. +
  17267. + mdiobus_register_board_info(rb2011_mdio0_info,
  17268. + ARRAY_SIZE(rb2011_mdio0_info));
  17269. +
  17270. + /* GMAC0 is connected to an ar8327 switch */
  17271. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  17272. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  17273. + ath79_eth0_data.phy_mask = BIT(0);
  17274. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  17275. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  17276. +
  17277. + ath79_register_eth(0);
  17278. +
  17279. + /* GMAC1 is connected to the internal switch */
  17280. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5);
  17281. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  17282. + ath79_eth1_data.speed = SPEED_1000;
  17283. + ath79_eth1_data.duplex = DUPLEX_FULL;
  17284. +
  17285. + ath79_register_eth(1);
  17286. +
  17287. + if (flags & RB2011_FLAG_SFP)
  17288. + rb2011_sfp_init();
  17289. +
  17290. + if (flags & RB2011_FLAG_WLAN)
  17291. + rb2011_wlan_init();
  17292. +
  17293. + if (flags & RB2011_FLAG_USB)
  17294. + ath79_register_usb();
  17295. +
  17296. + return 0;
  17297. +}
  17298. +
  17299. +static void __init rb2011l_setup(void)
  17300. +{
  17301. + rb2011_setup(0);
  17302. +}
  17303. +
  17304. +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011L, "2011L", rb2011l_setup);
  17305. +
  17306. +static void __init rb2011us_setup(void)
  17307. +{
  17308. + rb2011_setup(RB2011_FLAG_SFP | RB2011_FLAG_USB);
  17309. +}
  17310. +
  17311. +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011US, "2011US", rb2011us_setup);
  17312. +
  17313. +static void __init rb2011r5_setup(void)
  17314. +{
  17315. + rb2011_setup(RB2011_FLAG_SFP | RB2011_FLAG_USB | RB2011_FLAG_WLAN);
  17316. +}
  17317. +
  17318. +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011R5, "2011r5", rb2011r5_setup);
  17319. +
  17320. +static void __init rb2011g_setup(void)
  17321. +{
  17322. + rb2011_setup(RB2011_FLAG_SFP |
  17323. + RB2011_FLAG_USB |
  17324. + RB2011_FLAG_WLAN);
  17325. +}
  17326. +
  17327. +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011G, "2011G", rb2011g_setup);
  17328. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rb4xx.c linux-4.1.43/arch/mips/ath79/mach-rb4xx.c
  17329. --- linux-4.1.43.orig/arch/mips/ath79/mach-rb4xx.c 1970-01-01 01:00:00.000000000 +0100
  17330. +++ linux-4.1.43/arch/mips/ath79/mach-rb4xx.c 2017-08-06 20:02:15.000000000 +0200
  17331. @@ -0,0 +1,465 @@
  17332. +/*
  17333. + * MikroTik RouterBOARD 4xx series support
  17334. + *
  17335. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  17336. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  17337. + *
  17338. + * This program is free software; you can redistribute it and/or modify it
  17339. + * under the terms of the GNU General Public License version 2 as published
  17340. + * by the Free Software Foundation.
  17341. + */
  17342. +
  17343. +#include <linux/platform_device.h>
  17344. +#include <linux/irq.h>
  17345. +#include <linux/mdio-gpio.h>
  17346. +#include <linux/mmc/host.h>
  17347. +#include <linux/spi/spi.h>
  17348. +#include <linux/spi/flash.h>
  17349. +#include <linux/spi/mmc_spi.h>
  17350. +#include <linux/mtd/mtd.h>
  17351. +#include <linux/mtd/partitions.h>
  17352. +
  17353. +#include <asm/mach-ath79/ar71xx_regs.h>
  17354. +#include <asm/mach-ath79/ath79.h>
  17355. +#include <asm/mach-ath79/rb4xx_cpld.h>
  17356. +
  17357. +#include "common.h"
  17358. +#include "dev-eth.h"
  17359. +#include "dev-gpio-buttons.h"
  17360. +#include "dev-leds-gpio.h"
  17361. +#include "dev-usb.h"
  17362. +#include "machtypes.h"
  17363. +#include "pci.h"
  17364. +
  17365. +#define RB4XX_GPIO_USER_LED 4
  17366. +#define RB4XX_GPIO_RESET_SWITCH 7
  17367. +
  17368. +#define RB4XX_GPIO_CPLD_BASE 32
  17369. +#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
  17370. +#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
  17371. +#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
  17372. +#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
  17373. +#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
  17374. +
  17375. +#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */
  17376. +#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL)
  17377. +
  17378. +static struct gpio_led rb4xx_leds_gpio[] __initdata = {
  17379. + {
  17380. + .name = "rb4xx:yellow:user",
  17381. + .gpio = RB4XX_GPIO_USER_LED,
  17382. + .active_low = 0,
  17383. + }, {
  17384. + .name = "rb4xx:green:led1",
  17385. + .gpio = RB4XX_GPIO_CPLD_LED1,
  17386. + .active_low = 1,
  17387. + }, {
  17388. + .name = "rb4xx:green:led2",
  17389. + .gpio = RB4XX_GPIO_CPLD_LED2,
  17390. + .active_low = 1,
  17391. + }, {
  17392. + .name = "rb4xx:green:led3",
  17393. + .gpio = RB4XX_GPIO_CPLD_LED3,
  17394. + .active_low = 1,
  17395. + }, {
  17396. + .name = "rb4xx:green:led4",
  17397. + .gpio = RB4XX_GPIO_CPLD_LED4,
  17398. + .active_low = 1,
  17399. + }, {
  17400. + .name = "rb4xx:green:led5",
  17401. + .gpio = RB4XX_GPIO_CPLD_LED5,
  17402. + .active_low = 0,
  17403. + },
  17404. +};
  17405. +
  17406. +static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
  17407. + {
  17408. + .desc = "reset_switch",
  17409. + .type = EV_KEY,
  17410. + .code = KEY_RESTART,
  17411. + .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
  17412. + .gpio = RB4XX_GPIO_RESET_SWITCH,
  17413. + .active_low = 1,
  17414. + }
  17415. +};
  17416. +
  17417. +static struct platform_device rb4xx_nand_device = {
  17418. + .name = "rb4xx-nand",
  17419. + .id = -1,
  17420. +};
  17421. +
  17422. +static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
  17423. + {
  17424. + .slot = 17,
  17425. + .pin = 1,
  17426. + .irq = ATH79_PCI_IRQ(2),
  17427. + }, {
  17428. + .slot = 18,
  17429. + .pin = 1,
  17430. + .irq = ATH79_PCI_IRQ(0),
  17431. + }, {
  17432. + .slot = 18,
  17433. + .pin = 2,
  17434. + .irq = ATH79_PCI_IRQ(1),
  17435. + }, {
  17436. + .slot = 19,
  17437. + .pin = 1,
  17438. + .irq = ATH79_PCI_IRQ(1),
  17439. + }, {
  17440. + .slot = 19,
  17441. + .pin = 2,
  17442. + .irq = ATH79_PCI_IRQ(2),
  17443. + }, {
  17444. + .slot = 20,
  17445. + .pin = 1,
  17446. + .irq = ATH79_PCI_IRQ(2),
  17447. + }, {
  17448. + .slot = 20,
  17449. + .pin = 2,
  17450. + .irq = ATH79_PCI_IRQ(0),
  17451. + }, {
  17452. + .slot = 21,
  17453. + .pin = 1,
  17454. + .irq = ATH79_PCI_IRQ(0),
  17455. + }, {
  17456. + .slot = 22,
  17457. + .pin = 1,
  17458. + .irq = ATH79_PCI_IRQ(1),
  17459. + }, {
  17460. + .slot = 22,
  17461. + .pin = 2,
  17462. + .irq = ATH79_PCI_IRQ(2),
  17463. + }, {
  17464. + .slot = 23,
  17465. + .pin = 1,
  17466. + .irq = ATH79_PCI_IRQ(2),
  17467. + }, {
  17468. + .slot = 23,
  17469. + .pin = 2,
  17470. + .irq = ATH79_PCI_IRQ(0),
  17471. + }
  17472. +};
  17473. +
  17474. +static struct mtd_partition rb4xx_partitions[] = {
  17475. + {
  17476. + .name = "routerboot",
  17477. + .offset = 0,
  17478. + .size = 0x0b000,
  17479. + .mask_flags = MTD_WRITEABLE,
  17480. + }, {
  17481. + .name = "hard_config",
  17482. + .offset = 0x0b000,
  17483. + .size = 0x01000,
  17484. + .mask_flags = MTD_WRITEABLE,
  17485. + }, {
  17486. + .name = "bios",
  17487. + .offset = 0x0d000,
  17488. + .size = 0x02000,
  17489. + .mask_flags = MTD_WRITEABLE,
  17490. + }, {
  17491. + .name = "soft_config",
  17492. + .offset = 0x0f000,
  17493. + .size = 0x01000,
  17494. + }
  17495. +};
  17496. +
  17497. +static struct flash_platform_data rb4xx_flash_data = {
  17498. + .type = "pm25lv512",
  17499. + .parts = rb4xx_partitions,
  17500. + .nr_parts = ARRAY_SIZE(rb4xx_partitions),
  17501. +};
  17502. +
  17503. +static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
  17504. + .gpio_base = RB4XX_GPIO_CPLD_BASE,
  17505. +};
  17506. +
  17507. +static struct mmc_spi_platform_data rb4xx_mmc_data = {
  17508. + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
  17509. +};
  17510. +
  17511. +static struct spi_board_info rb4xx_spi_info[] = {
  17512. + {
  17513. + .bus_num = 0,
  17514. + .chip_select = 0,
  17515. + .max_speed_hz = 25000000,
  17516. + .modalias = "m25p80",
  17517. + .platform_data = &rb4xx_flash_data,
  17518. + }, {
  17519. + .bus_num = 0,
  17520. + .chip_select = 1,
  17521. + .max_speed_hz = 25000000,
  17522. + .modalias = "spi-rb4xx-cpld",
  17523. + .platform_data = &rb4xx_cpld_data,
  17524. + }
  17525. +};
  17526. +
  17527. +static struct spi_board_info rb4xx_microsd_info[] = {
  17528. + {
  17529. + .bus_num = 0,
  17530. + .chip_select = 2,
  17531. + .max_speed_hz = 25000000,
  17532. + .modalias = "mmc_spi",
  17533. + .platform_data = &rb4xx_mmc_data,
  17534. + }
  17535. +};
  17536. +
  17537. +
  17538. +static struct resource rb4xx_spi_resources[] = {
  17539. + {
  17540. + .start = AR71XX_SPI_BASE,
  17541. + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
  17542. + .flags = IORESOURCE_MEM,
  17543. + },
  17544. +};
  17545. +
  17546. +static struct platform_device rb4xx_spi_device = {
  17547. + .name = "rb4xx-spi",
  17548. + .id = -1,
  17549. + .resource = rb4xx_spi_resources,
  17550. + .num_resources = ARRAY_SIZE(rb4xx_spi_resources),
  17551. +};
  17552. +
  17553. +static void __init rb4xx_generic_setup(void)
  17554. +{
  17555. + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
  17556. + AR71XX_GPIO_FUNC_SPI_CS2_EN);
  17557. +
  17558. + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
  17559. + rb4xx_leds_gpio);
  17560. +
  17561. + ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
  17562. + ARRAY_SIZE(rb4xx_gpio_keys),
  17563. + rb4xx_gpio_keys);
  17564. +
  17565. + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
  17566. + platform_device_register(&rb4xx_spi_device);
  17567. + platform_device_register(&rb4xx_nand_device);
  17568. +}
  17569. +
  17570. +static void __init rb411_setup(void)
  17571. +{
  17572. + rb4xx_generic_setup();
  17573. + spi_register_board_info(rb4xx_microsd_info,
  17574. + ARRAY_SIZE(rb4xx_microsd_info));
  17575. +
  17576. + ath79_register_mdio(0, 0xfffffffc);
  17577. +
  17578. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  17579. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  17580. + ath79_eth0_data.phy_mask = 0x00000003;
  17581. +
  17582. + ath79_register_eth(0);
  17583. +
  17584. + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
  17585. + ath79_register_pci();
  17586. +}
  17587. +
  17588. +MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
  17589. + rb411_setup);
  17590. +
  17591. +static void __init rb411u_setup(void)
  17592. +{
  17593. + rb411_setup();
  17594. + ath79_register_usb();
  17595. +}
  17596. +
  17597. +MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
  17598. + rb411u_setup);
  17599. +
  17600. +#define RB433_LAN_PHYMASK BIT(0)
  17601. +#define RB433_WAN_PHYMASK BIT(4)
  17602. +#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
  17603. +
  17604. +static void __init rb433_setup(void)
  17605. +{
  17606. + rb4xx_generic_setup();
  17607. + spi_register_board_info(rb4xx_microsd_info,
  17608. + ARRAY_SIZE(rb4xx_microsd_info));
  17609. +
  17610. + ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
  17611. +
  17612. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
  17613. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  17614. + ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
  17615. +
  17616. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
  17617. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  17618. + ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
  17619. +
  17620. + ath79_register_eth(1);
  17621. + ath79_register_eth(0);
  17622. +
  17623. + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
  17624. + ath79_register_pci();
  17625. +}
  17626. +
  17627. +MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
  17628. + rb433_setup);
  17629. +
  17630. +static void __init rb433u_setup(void)
  17631. +{
  17632. + rb433_setup();
  17633. + ath79_register_usb();
  17634. +}
  17635. +
  17636. +MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
  17637. + rb433u_setup);
  17638. +
  17639. +static void __init rb435g_setup(void)
  17640. +{
  17641. + rb4xx_generic_setup();
  17642. +
  17643. + spi_register_board_info(rb4xx_microsd_info,
  17644. + ARRAY_SIZE(rb4xx_microsd_info));
  17645. +
  17646. + ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
  17647. +
  17648. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
  17649. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  17650. + ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
  17651. +
  17652. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
  17653. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  17654. + ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
  17655. +
  17656. + ath79_register_eth(1);
  17657. + ath79_register_eth(0);
  17658. +
  17659. + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
  17660. + ath79_register_pci();
  17661. +
  17662. + ath79_register_usb();
  17663. +}
  17664. +
  17665. +MIPS_MACHINE(ATH79_MACH_RB_435G, "435G", "MikroTik RouterBOARD 435G",
  17666. + rb435g_setup);
  17667. +
  17668. +#define RB450_LAN_PHYMASK BIT(0)
  17669. +#define RB450_WAN_PHYMASK BIT(4)
  17670. +#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
  17671. +
  17672. +static void __init rb450_generic_setup(int gige)
  17673. +{
  17674. + rb4xx_generic_setup();
  17675. + ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
  17676. +
  17677. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
  17678. + ath79_eth0_data.phy_if_mode = (gige) ?
  17679. + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
  17680. + ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
  17681. +
  17682. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
  17683. + ath79_eth1_data.phy_if_mode = (gige) ?
  17684. + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
  17685. + ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
  17686. +
  17687. + ath79_register_eth(1);
  17688. + ath79_register_eth(0);
  17689. +}
  17690. +
  17691. +static void __init rb450_setup(void)
  17692. +{
  17693. + rb450_generic_setup(0);
  17694. +}
  17695. +
  17696. +MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
  17697. + rb450_setup);
  17698. +
  17699. +static void __init rb450g_setup(void)
  17700. +{
  17701. + rb450_generic_setup(1);
  17702. + spi_register_board_info(rb4xx_microsd_info,
  17703. + ARRAY_SIZE(rb4xx_microsd_info));
  17704. +}
  17705. +
  17706. +MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
  17707. + rb450g_setup);
  17708. +
  17709. +static void __init rb493_setup(void)
  17710. +{
  17711. + rb4xx_generic_setup();
  17712. +
  17713. + ath79_register_mdio(0, 0x3fffff00);
  17714. +
  17715. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  17716. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  17717. + ath79_eth0_data.speed = SPEED_100;
  17718. + ath79_eth0_data.duplex = DUPLEX_FULL;
  17719. +
  17720. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  17721. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  17722. + ath79_eth1_data.phy_mask = 0x00000001;
  17723. +
  17724. + ath79_register_eth(0);
  17725. + ath79_register_eth(1);
  17726. +
  17727. + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
  17728. + ath79_register_pci();
  17729. +}
  17730. +
  17731. +MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
  17732. + rb493_setup);
  17733. +
  17734. +#define RB493G_GPIO_MDIO_MDC 7
  17735. +#define RB493G_GPIO_MDIO_DATA 8
  17736. +
  17737. +#define RB493G_MDIO_PHYMASK BIT(0)
  17738. +
  17739. +static struct mdio_gpio_platform_data rb493g_mdio_data = {
  17740. + .mdc = RB493G_GPIO_MDIO_MDC,
  17741. + .mdio = RB493G_GPIO_MDIO_DATA,
  17742. +
  17743. + .phy_mask = ~RB493G_MDIO_PHYMASK,
  17744. +};
  17745. +
  17746. +static struct platform_device rb493g_mdio_device = {
  17747. + .name = "mdio-gpio",
  17748. + .id = -1,
  17749. + .dev = {
  17750. + .platform_data = &rb493g_mdio_data,
  17751. + },
  17752. +};
  17753. +
  17754. +static void __init rb493g_setup(void)
  17755. +{
  17756. + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
  17757. + AR71XX_GPIO_FUNC_SPI_CS2_EN);
  17758. +
  17759. + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
  17760. + rb4xx_leds_gpio);
  17761. +
  17762. + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
  17763. + spi_register_board_info(rb4xx_microsd_info,
  17764. + ARRAY_SIZE(rb4xx_microsd_info));
  17765. +
  17766. + platform_device_register(&rb4xx_spi_device);
  17767. + platform_device_register(&rb4xx_nand_device);
  17768. +
  17769. + ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
  17770. +
  17771. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  17772. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  17773. + ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
  17774. + ath79_eth0_data.speed = SPEED_1000;
  17775. + ath79_eth0_data.duplex = DUPLEX_FULL;
  17776. +
  17777. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  17778. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  17779. + ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
  17780. + ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
  17781. + ath79_eth1_data.speed = SPEED_1000;
  17782. + ath79_eth1_data.duplex = DUPLEX_FULL;
  17783. +
  17784. + platform_device_register(&rb493g_mdio_device);
  17785. +
  17786. + ath79_register_eth(1);
  17787. + ath79_register_eth(0);
  17788. +
  17789. + ath79_register_usb();
  17790. +
  17791. + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
  17792. + ath79_register_pci();
  17793. +}
  17794. +
  17795. +MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",
  17796. + rb493g_setup);
  17797. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rb750.c linux-4.1.43/arch/mips/ath79/mach-rb750.c
  17798. --- linux-4.1.43.orig/arch/mips/ath79/mach-rb750.c 1970-01-01 01:00:00.000000000 +0100
  17799. +++ linux-4.1.43/arch/mips/ath79/mach-rb750.c 2017-08-06 20:02:15.000000000 +0200
  17800. @@ -0,0 +1,346 @@
  17801. +/*
  17802. + * MikroTik RouterBOARD 750/750GL support
  17803. + *
  17804. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  17805. + *
  17806. + * This program is free software; you can redistribute it and/or modify it
  17807. + * under the terms of the GNU General Public License version 2 as published
  17808. + * by the Free Software Foundation.
  17809. + */
  17810. +
  17811. +#include <linux/export.h>
  17812. +#include <linux/pci.h>
  17813. +#include <linux/ath9k_platform.h>
  17814. +#include <linux/platform_device.h>
  17815. +#include <linux/phy.h>
  17816. +#include <linux/ar8216_platform.h>
  17817. +#include <linux/rle.h>
  17818. +#include <linux/routerboot.h>
  17819. +
  17820. +#include <asm/mach-ath79/ar71xx_regs.h>
  17821. +#include <asm/mach-ath79/ath79.h>
  17822. +#include <asm/mach-ath79/irq.h>
  17823. +#include <asm/mach-ath79/mach-rb750.h>
  17824. +
  17825. +#include "common.h"
  17826. +#include "dev-ap9x-pci.h"
  17827. +#include "dev-usb.h"
  17828. +#include "dev-eth.h"
  17829. +#include "machtypes.h"
  17830. +#include "routerboot.h"
  17831. +
  17832. +static struct rb750_led_data rb750_leds[] = {
  17833. + {
  17834. + .name = "rb750:green:act",
  17835. + .mask = RB750_LED_ACT,
  17836. + .active_low = 1,
  17837. + }, {
  17838. + .name = "rb750:green:port1",
  17839. + .mask = RB750_LED_PORT5,
  17840. + .active_low = 1,
  17841. + }, {
  17842. + .name = "rb750:green:port2",
  17843. + .mask = RB750_LED_PORT4,
  17844. + .active_low = 1,
  17845. + }, {
  17846. + .name = "rb750:green:port3",
  17847. + .mask = RB750_LED_PORT3,
  17848. + .active_low = 1,
  17849. + }, {
  17850. + .name = "rb750:green:port4",
  17851. + .mask = RB750_LED_PORT2,
  17852. + .active_low = 1,
  17853. + }, {
  17854. + .name = "rb750:green:port5",
  17855. + .mask = RB750_LED_PORT1,
  17856. + .active_low = 1,
  17857. + }
  17858. +};
  17859. +
  17860. +static struct rb750_led_data rb750gr3_leds[] = {
  17861. + {
  17862. + .name = "rb750:green:act",
  17863. + .mask = RB7XX_LED_ACT,
  17864. + .active_low = 1,
  17865. + },
  17866. +};
  17867. +
  17868. +static struct rb750_led_platform_data rb750_leds_data;
  17869. +static struct platform_device rb750_leds_device = {
  17870. + .name = "leds-rb750",
  17871. + .dev = {
  17872. + .platform_data = &rb750_leds_data,
  17873. + }
  17874. +};
  17875. +
  17876. +static struct rb7xx_nand_platform_data rb750_nand_data;
  17877. +static struct platform_device rb750_nand_device = {
  17878. + .name = "rb750-nand",
  17879. + .id = -1,
  17880. + .dev = {
  17881. + .platform_data = &rb750_nand_data,
  17882. + }
  17883. +};
  17884. +
  17885. +static void rb750_latch_change(u32 mask_clr, u32 mask_set)
  17886. +{
  17887. + static DEFINE_SPINLOCK(lock);
  17888. + static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE;
  17889. + static u32 latch_oe;
  17890. + static u32 latch_clr;
  17891. + unsigned long flags;
  17892. + u32 t;
  17893. +
  17894. + spin_lock_irqsave(&lock, flags);
  17895. +
  17896. + if ((mask_clr & BIT(31)) != 0 &&
  17897. + (latch_set & RB750_LVC573_LE) == 0) {
  17898. + goto unlock;
  17899. + }
  17900. +
  17901. + latch_set = (latch_set | mask_set) & ~mask_clr;
  17902. + latch_clr = (latch_clr | mask_clr) & ~mask_set;
  17903. +
  17904. + if (latch_oe == 0)
  17905. + latch_oe = __raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_OE);
  17906. +
  17907. + if (likely(latch_set & RB750_LVC573_LE)) {
  17908. + void __iomem *base = ath79_gpio_base;
  17909. +
  17910. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  17911. + t |= mask_clr | latch_oe | mask_set;
  17912. +
  17913. + __raw_writel(t, base + AR71XX_GPIO_REG_OE);
  17914. + __raw_writel(latch_clr, base + AR71XX_GPIO_REG_CLEAR);
  17915. + __raw_writel(latch_set, base + AR71XX_GPIO_REG_SET);
  17916. + } else if (mask_clr & RB750_LVC573_LE) {
  17917. + void __iomem *base = ath79_gpio_base;
  17918. +
  17919. + latch_oe = __raw_readl(base + AR71XX_GPIO_REG_OE);
  17920. + __raw_writel(RB750_LVC573_LE, base + AR71XX_GPIO_REG_CLEAR);
  17921. + /* flush write */
  17922. + __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
  17923. + }
  17924. +
  17925. +unlock:
  17926. + spin_unlock_irqrestore(&lock, flags);
  17927. +}
  17928. +
  17929. +static void rb750_nand_enable_pins(void)
  17930. +{
  17931. + rb750_latch_change(RB750_LVC573_LE, 0);
  17932. + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
  17933. + AR724X_GPIO_FUNC_SPI_EN);
  17934. +}
  17935. +
  17936. +static void rb750_nand_disable_pins(void)
  17937. +{
  17938. + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN,
  17939. + AR724X_GPIO_FUNC_JTAG_DISABLE);
  17940. + rb750_latch_change(0, RB750_LVC573_LE);
  17941. +}
  17942. +
  17943. +static void __init rb750_setup(void)
  17944. +{
  17945. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  17946. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  17947. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  17948. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  17949. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  17950. +
  17951. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  17952. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  17953. +
  17954. + ath79_register_mdio(0, 0x0);
  17955. +
  17956. + /* LAN ports */
  17957. + ath79_register_eth(1);
  17958. +
  17959. + /* WAN port */
  17960. + ath79_register_eth(0);
  17961. +
  17962. + rb750_leds_data.num_leds = ARRAY_SIZE(rb750_leds);
  17963. + rb750_leds_data.leds = rb750_leds;
  17964. + rb750_leds_data.latch_change = rb750_latch_change;
  17965. + platform_device_register(&rb750_leds_device);
  17966. +
  17967. + rb750_nand_data.nce_line = RB750_NAND_NCE;
  17968. + rb750_nand_data.enable_pins = rb750_nand_enable_pins;
  17969. + rb750_nand_data.disable_pins = rb750_nand_disable_pins;
  17970. + rb750_nand_data.latch_change = rb750_latch_change;
  17971. + platform_device_register(&rb750_nand_device);
  17972. +}
  17973. +
  17974. +MIPS_MACHINE(ATH79_MACH_RB_750, "750i", "MikroTik RouterBOARD 750",
  17975. + rb750_setup);
  17976. +
  17977. +static struct ar8327_pad_cfg rb750gr3_ar8327_pad0_cfg = {
  17978. + .mode = AR8327_PAD_MAC_RGMII,
  17979. + .txclk_delay_en = true,
  17980. + .rxclk_delay_en = true,
  17981. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  17982. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  17983. +};
  17984. +
  17985. +static struct ar8327_platform_data rb750gr3_ar8327_data = {
  17986. + .pad0_cfg = &rb750gr3_ar8327_pad0_cfg,
  17987. + .port0_cfg = {
  17988. + .force_link = 1,
  17989. + .speed = AR8327_PORT_SPEED_1000,
  17990. + .duplex = 1,
  17991. + .txpause = 1,
  17992. + .rxpause = 1,
  17993. + }
  17994. +};
  17995. +
  17996. +static struct mdio_board_info rb750g3_mdio_info[] = {
  17997. + {
  17998. + .bus_id = "ag71xx-mdio.0",
  17999. + .phy_addr = 0,
  18000. + .platform_data = &rb750gr3_ar8327_data,
  18001. + },
  18002. +};
  18003. +
  18004. +static void rb750gr3_nand_enable_pins(void)
  18005. +{
  18006. + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
  18007. + AR724X_GPIO_FUNC_SPI_EN |
  18008. + AR724X_GPIO_FUNC_SPI_CS_EN2);
  18009. +}
  18010. +
  18011. +static void rb750gr3_nand_disable_pins(void)
  18012. +{
  18013. + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN |
  18014. + AR724X_GPIO_FUNC_SPI_CS_EN2,
  18015. + AR724X_GPIO_FUNC_JTAG_DISABLE);
  18016. +}
  18017. +
  18018. +static void rb750gr3_latch_change(u32 mask_clr, u32 mask_set)
  18019. +{
  18020. + static DEFINE_SPINLOCK(lock);
  18021. + static u32 latch_set = RB7XX_LED_ACT;
  18022. + static u32 latch_clr;
  18023. + void __iomem *base = ath79_gpio_base;
  18024. + unsigned long flags;
  18025. + u32 t;
  18026. +
  18027. + spin_lock_irqsave(&lock, flags);
  18028. +
  18029. + latch_set = (latch_set | mask_set) & ~mask_clr;
  18030. + latch_clr = (latch_clr | mask_clr) & ~mask_set;
  18031. +
  18032. + mask_set = latch_set & (RB7XX_USB_POWERON | RB7XX_MONITOR);
  18033. + mask_clr = latch_clr & (RB7XX_USB_POWERON | RB7XX_MONITOR);
  18034. +
  18035. + if ((latch_set ^ RB7XX_LED_ACT) & RB7XX_LED_ACT) {
  18036. + /* enable output mode */
  18037. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  18038. + t |= RB7XX_LED_ACT;
  18039. + __raw_writel(t, base + AR71XX_GPIO_REG_OE);
  18040. +
  18041. + mask_clr |= RB7XX_LED_ACT;
  18042. + } else {
  18043. + /* disable output mode */
  18044. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  18045. + t &= ~RB7XX_LED_ACT;
  18046. + __raw_writel(t, base + AR71XX_GPIO_REG_OE);
  18047. + }
  18048. +
  18049. + __raw_writel(mask_set, base + AR71XX_GPIO_REG_SET);
  18050. + __raw_writel(mask_clr, base + AR71XX_GPIO_REG_CLEAR);
  18051. +
  18052. + spin_unlock_irqrestore(&lock, flags);
  18053. +}
  18054. +
  18055. +static void __init rb750gr3_setup(void)
  18056. +{
  18057. + ath79_register_mdio(0, 0x0);
  18058. + mdiobus_register_board_info(rb750g3_mdio_info,
  18059. + ARRAY_SIZE(rb750g3_mdio_info));
  18060. +
  18061. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  18062. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  18063. + ath79_eth0_data.phy_mask = BIT(0);
  18064. + ath79_eth0_pll_data.pll_1000 = 0x62000000;
  18065. +
  18066. + ath79_register_eth(0);
  18067. +
  18068. + rb750_leds_data.num_leds = ARRAY_SIZE(rb750gr3_leds);
  18069. + rb750_leds_data.leds = rb750gr3_leds;
  18070. + rb750_leds_data.latch_change = rb750gr3_latch_change;
  18071. + platform_device_register(&rb750_leds_device);
  18072. +
  18073. + rb750_nand_data.nce_line = RB7XX_NAND_NCE;
  18074. + rb750_nand_data.enable_pins = rb750gr3_nand_enable_pins;
  18075. + rb750_nand_data.disable_pins = rb750gr3_nand_disable_pins;
  18076. + rb750_nand_data.latch_change = rb750gr3_latch_change;
  18077. + platform_device_register(&rb750_nand_device);
  18078. +}
  18079. +
  18080. +MIPS_MACHINE(ATH79_MACH_RB_750G_R3, "750Gr3", "MikroTik RouterBOARD 750GL",
  18081. + rb750gr3_setup);
  18082. +
  18083. +#define RB751_HARDCONFIG 0x1f00b000
  18084. +#define RB751_HARDCONFIG_SIZE 0x1000
  18085. +
  18086. +static void __init rb751_wlan_setup(void)
  18087. +{
  18088. + u8 *hardconfig = (u8 *) KSEG1ADDR(RB751_HARDCONFIG);
  18089. + struct ath9k_platform_data *wmac_data;
  18090. + u16 tag_len;
  18091. + u8 *tag;
  18092. + u16 mac_len;
  18093. + u8 *mac;
  18094. + int err;
  18095. +
  18096. + wmac_data = ap9x_pci_get_wmac_data(0);
  18097. + if (!wmac_data) {
  18098. + pr_err("rb75x: unable to get address of wlan data\n");
  18099. + return;
  18100. + }
  18101. +
  18102. + ap9x_pci_setup_wmac_led_pin(0, 9);
  18103. +
  18104. + err = routerboot_find_tag(hardconfig, RB751_HARDCONFIG_SIZE,
  18105. + RB_ID_WLAN_DATA, &tag, &tag_len);
  18106. + if (err) {
  18107. + pr_err("rb75x: no calibration data found\n");
  18108. + return;
  18109. + }
  18110. +
  18111. + err = rle_decode(tag, tag_len, (unsigned char *) wmac_data->eeprom_data,
  18112. + sizeof(wmac_data->eeprom_data), NULL, NULL);
  18113. + if (err) {
  18114. + pr_err("rb75x: unable to decode wlan eeprom data\n");
  18115. + return;
  18116. + }
  18117. +
  18118. + err = routerboot_find_tag(hardconfig, RB751_HARDCONFIG_SIZE,
  18119. + RB_ID_MAC_ADDRESS_PACK, &mac, &mac_len);
  18120. + if (err) {
  18121. + pr_err("rb75x: no mac address found\n");
  18122. + return;
  18123. + }
  18124. +
  18125. + ap91_pci_init(NULL, mac);
  18126. +}
  18127. +
  18128. +static void __init rb751_setup(void)
  18129. +{
  18130. + rb750_setup();
  18131. + ath79_register_usb();
  18132. + rb751_wlan_setup();
  18133. +}
  18134. +
  18135. +MIPS_MACHINE(ATH79_MACH_RB_751, "751", "MikroTik RouterBOARD 751",
  18136. + rb751_setup);
  18137. +
  18138. +static void __init rb751g_setup(void)
  18139. +{
  18140. + rb750gr3_setup();
  18141. + ath79_register_usb();
  18142. + rb751_wlan_setup();
  18143. +}
  18144. +
  18145. +MIPS_MACHINE(ATH79_MACH_RB_751G, "751g", "MikroTik RouterBOARD 751G",
  18146. + rb751g_setup);
  18147. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rb91x.c linux-4.1.43/arch/mips/ath79/mach-rb91x.c
  18148. --- linux-4.1.43.orig/arch/mips/ath79/mach-rb91x.c 1970-01-01 01:00:00.000000000 +0100
  18149. +++ linux-4.1.43/arch/mips/ath79/mach-rb91x.c 2017-08-06 20:02:15.000000000 +0200
  18150. @@ -0,0 +1,349 @@
  18151. +/*
  18152. + * MikroTik RouterBOARD 91X support
  18153. + *
  18154. + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  18155. + *
  18156. + * This program is free software; you can redistribute it and/or modify it
  18157. + * under the terms of the GNU General Public License version 2 as published
  18158. + * by the Free Software Foundation.
  18159. + */
  18160. +
  18161. +#define pr_fmt(fmt) "rb91x: " fmt
  18162. +
  18163. +#include <linux/phy.h>
  18164. +#include <linux/delay.h>
  18165. +#include <linux/platform_device.h>
  18166. +#include <linux/ath9k_platform.h>
  18167. +#include <linux/mtd/mtd.h>
  18168. +#include <linux/mtd/nand.h>
  18169. +#include <linux/mtd/partitions.h>
  18170. +#include <linux/spi/spi.h>
  18171. +#include <linux/spi/74x164.h>
  18172. +#include <linux/spi/flash.h>
  18173. +#include <linux/routerboot.h>
  18174. +#include <linux/gpio.h>
  18175. +#include <linux/platform_data/gpio-latch.h>
  18176. +#include <linux/platform_data/rb91x_nand.h>
  18177. +#include <linux/platform_data/phy-at803x.h>
  18178. +
  18179. +#include <asm/prom.h>
  18180. +#include <asm/mach-ath79/ath79.h>
  18181. +#include <asm/mach-ath79/ath79_spi_platform.h>
  18182. +#include <asm/mach-ath79/ar71xx_regs.h>
  18183. +
  18184. +#include "common.h"
  18185. +#include "dev-eth.h"
  18186. +#include "dev-leds-gpio.h"
  18187. +#include "dev-nfc.h"
  18188. +#include "dev-usb.h"
  18189. +#include "dev-spi.h"
  18190. +#include "dev-wmac.h"
  18191. +#include "machtypes.h"
  18192. +#include "pci.h"
  18193. +#include "routerboot.h"
  18194. +
  18195. +#define RB_ROUTERBOOT_OFFSET 0x0000
  18196. +#define RB_ROUTERBOOT_MIN_SIZE 0xb000
  18197. +#define RB_HARD_CFG_SIZE 0x1000
  18198. +#define RB_BIOS_OFFSET 0xd000
  18199. +#define RB_BIOS_SIZE 0x1000
  18200. +#define RB_SOFT_CFG_OFFSET 0xf000
  18201. +#define RB_SOFT_CFG_SIZE 0x1000
  18202. +
  18203. +#define RB91X_FLAG_USB BIT(0)
  18204. +#define RB91X_FLAG_PCIE BIT(1)
  18205. +
  18206. +#define RB91X_LATCH_GPIO_BASE AR934X_GPIO_COUNT
  18207. +#define RB91X_LATCH_GPIO(_x) (RB91X_LATCH_GPIO_BASE + (_x))
  18208. +
  18209. +#define RB91X_SSR_GPIO_BASE (RB91X_LATCH_GPIO_BASE + AR934X_GPIO_COUNT)
  18210. +#define RB91X_SSR_GPIO(_x) (RB91X_SSR_GPIO_BASE + (_x))
  18211. +
  18212. +#define RB91X_SSR_BIT_LED1 0
  18213. +#define RB91X_SSR_BIT_LED2 1
  18214. +#define RB91X_SSR_BIT_LED3 2
  18215. +#define RB91X_SSR_BIT_LED4 3
  18216. +#define RB91X_SSR_BIT_LED5 4
  18217. +#define RB91X_SSR_BIT_5 5
  18218. +#define RB91X_SSR_BIT_USB_POWER 6
  18219. +#define RB91X_SSR_BIT_PCIE_POWER 7
  18220. +
  18221. +#define RB91X_GPIO_SSR_STROBE RB91X_LATCH_GPIO(0)
  18222. +#define RB91X_GPIO_LED_POWER RB91X_LATCH_GPIO(1)
  18223. +#define RB91X_GPIO_LED_USER RB91X_LATCH_GPIO(2)
  18224. +#define RB91X_GPIO_NAND_READ RB91X_LATCH_GPIO(3)
  18225. +#define RB91X_GPIO_NAND_RDY RB91X_LATCH_GPIO(4)
  18226. +#define RB91X_GPIO_NLE RB91X_LATCH_GPIO(11)
  18227. +#define RB91X_GPIO_NAND_NRW RB91X_LATCH_GPIO(12)
  18228. +#define RB91X_GPIO_NAND_NCE RB91X_LATCH_GPIO(13)
  18229. +#define RB91X_GPIO_NAND_CLE RB91X_LATCH_GPIO(14)
  18230. +#define RB91X_GPIO_NAND_ALE RB91X_LATCH_GPIO(15)
  18231. +
  18232. +#define RB91X_GPIO_LED_1 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED1)
  18233. +#define RB91X_GPIO_LED_2 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED2)
  18234. +#define RB91X_GPIO_LED_3 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED3)
  18235. +#define RB91X_GPIO_LED_4 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED4)
  18236. +#define RB91X_GPIO_LED_5 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED5)
  18237. +#define RB91X_GPIO_USB_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_USB_POWER)
  18238. +#define RB91X_GPIO_PCIE_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_PCIE_POWER)
  18239. +
  18240. +struct rb_board_info {
  18241. + const char *name;
  18242. + u32 flags;
  18243. +};
  18244. +
  18245. +static struct mtd_partition rb711gr100_spi_partitions[] = {
  18246. + {
  18247. + .name = "routerboot",
  18248. + .offset = RB_ROUTERBOOT_OFFSET,
  18249. + .mask_flags = MTD_WRITEABLE,
  18250. + }, {
  18251. + .name = "hard_config",
  18252. + .size = RB_HARD_CFG_SIZE,
  18253. + .mask_flags = MTD_WRITEABLE,
  18254. + }, {
  18255. + .name = "bios",
  18256. + .offset = RB_BIOS_OFFSET,
  18257. + .size = RB_BIOS_SIZE,
  18258. + .mask_flags = MTD_WRITEABLE,
  18259. + }, {
  18260. + .name = "soft_config",
  18261. + .size = RB_SOFT_CFG_SIZE,
  18262. + }
  18263. +};
  18264. +
  18265. +static struct flash_platform_data rb711gr100_spi_flash_data = {
  18266. + .parts = rb711gr100_spi_partitions,
  18267. + .nr_parts = ARRAY_SIZE(rb711gr100_spi_partitions),
  18268. +};
  18269. +
  18270. +static int rb711gr100_gpio_latch_gpios[AR934X_GPIO_COUNT] __initdata = {
  18271. + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
  18272. + 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22
  18273. +};
  18274. +
  18275. +static struct gpio_latch_platform_data rb711gr100_gpio_latch_data __initdata = {
  18276. + .base = RB91X_LATCH_GPIO_BASE,
  18277. + .num_gpios = ARRAY_SIZE(rb711gr100_gpio_latch_gpios),
  18278. + .gpios = rb711gr100_gpio_latch_gpios,
  18279. + .le_gpio_index = 11,
  18280. + .le_active_low = true,
  18281. +};
  18282. +
  18283. +static struct rb91x_nand_platform_data rb711gr100_nand_data __initdata = {
  18284. + .gpio_nce = RB91X_GPIO_NAND_NCE,
  18285. + .gpio_ale = RB91X_GPIO_NAND_ALE,
  18286. + .gpio_cle = RB91X_GPIO_NAND_CLE,
  18287. + .gpio_rdy = RB91X_GPIO_NAND_RDY,
  18288. + .gpio_read = RB91X_GPIO_NAND_READ,
  18289. + .gpio_nrw = RB91X_GPIO_NAND_NRW,
  18290. + .gpio_nle = RB91X_GPIO_NLE,
  18291. +};
  18292. +
  18293. +static u8 rb711gr100_ssr_initdata[] __initdata = {
  18294. + BIT(RB91X_SSR_BIT_PCIE_POWER) |
  18295. + BIT(RB91X_SSR_BIT_USB_POWER) |
  18296. + BIT(RB91X_SSR_BIT_5)
  18297. +};
  18298. +
  18299. +static struct gen_74x164_chip_platform_data rb711gr100_ssr_data = {
  18300. + .base = RB91X_SSR_GPIO_BASE,
  18301. + .num_registers = ARRAY_SIZE(rb711gr100_ssr_initdata),
  18302. + .init_data = rb711gr100_ssr_initdata,
  18303. +};
  18304. +
  18305. +static struct ath79_spi_controller_data rb711gr100_spi0_cdata = {
  18306. + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  18307. + .cs_line = 0,
  18308. + .is_flash = true,
  18309. +};
  18310. +
  18311. +static struct ath79_spi_controller_data rb711gr100_spi1_cdata = {
  18312. + .cs_type = ATH79_SPI_CS_TYPE_GPIO,
  18313. + .cs_line = RB91X_GPIO_SSR_STROBE,
  18314. +};
  18315. +
  18316. +static struct spi_board_info rb711gr100_spi_info[] = {
  18317. + {
  18318. + .bus_num = 0,
  18319. + .chip_select = 0,
  18320. + .max_speed_hz = 25000000,
  18321. + .modalias = "m25p80",
  18322. + .platform_data = &rb711gr100_spi_flash_data,
  18323. + .controller_data = &rb711gr100_spi0_cdata
  18324. + }, {
  18325. + .bus_num = 0,
  18326. + .chip_select = 1,
  18327. + .max_speed_hz = 10000000,
  18328. + .modalias = "74x164",
  18329. + .platform_data = &rb711gr100_ssr_data,
  18330. + .controller_data = &rb711gr100_spi1_cdata
  18331. + }
  18332. +};
  18333. +
  18334. +static struct ath79_spi_platform_data rb711gr100_spi_data __initdata = {
  18335. + .bus_num = 0,
  18336. + .num_chipselect = 2,
  18337. +};
  18338. +
  18339. +static struct gpio_led rb711gr100_leds[] __initdata = {
  18340. + {
  18341. + .name = "rb:green:led1",
  18342. + .gpio = RB91X_GPIO_LED_1,
  18343. + .active_low = 0,
  18344. + },
  18345. + {
  18346. + .name = "rb:green:led2",
  18347. + .gpio = RB91X_GPIO_LED_2,
  18348. + .active_low = 0,
  18349. + },
  18350. + {
  18351. + .name = "rb:green:led3",
  18352. + .gpio = RB91X_GPIO_LED_3,
  18353. + .active_low = 0,
  18354. + },
  18355. + {
  18356. + .name = "rb:green:led4",
  18357. + .gpio = RB91X_GPIO_LED_4,
  18358. + .active_low = 0,
  18359. + },
  18360. + {
  18361. + .name = "rb:green:led5",
  18362. + .gpio = RB91X_GPIO_LED_5,
  18363. + .active_low = 0,
  18364. + },
  18365. + {
  18366. + .name = "rb:green:user",
  18367. + .gpio = RB91X_GPIO_LED_USER,
  18368. + .active_low = 0,
  18369. + },
  18370. + {
  18371. + .name = "rb:green:power",
  18372. + .gpio = RB91X_GPIO_LED_POWER,
  18373. + .active_low = 0,
  18374. + },
  18375. +};
  18376. +
  18377. +static struct at803x_platform_data rb91x_at803x_data = {
  18378. + .disable_smarteee = 1,
  18379. + .enable_rgmii_rx_delay = 1,
  18380. + .enable_rgmii_tx_delay = 1,
  18381. +};
  18382. +
  18383. +static struct mdio_board_info rb91x_mdio0_info[] = {
  18384. + {
  18385. + .bus_id = "ag71xx-mdio.0",
  18386. + .phy_addr = 0,
  18387. + .platform_data = &rb91x_at803x_data,
  18388. + },
  18389. +};
  18390. +
  18391. +static void __init rb711gr100_init_partitions(const struct rb_info *info)
  18392. +{
  18393. + rb711gr100_spi_partitions[0].size = info->hard_cfg_offs;
  18394. + rb711gr100_spi_partitions[1].offset = info->hard_cfg_offs;
  18395. +
  18396. + rb711gr100_spi_partitions[3].offset = info->soft_cfg_offs;
  18397. +}
  18398. +
  18399. +void __init rb711gr100_wlan_init(void)
  18400. +{
  18401. + char *caldata;
  18402. + u8 wlan_mac[ETH_ALEN];
  18403. +
  18404. + caldata = rb_get_wlan_data();
  18405. + if (caldata == NULL)
  18406. + return;
  18407. +
  18408. + ath79_init_mac(wlan_mac, ath79_mac_base, 1);
  18409. + ath79_register_wmac(caldata + 0x1000, wlan_mac);
  18410. +
  18411. + kfree(caldata);
  18412. +}
  18413. +
  18414. +#define RB_BOARD_INFO(_name, _flags) \
  18415. + { \
  18416. + .name = (_name), \
  18417. + .flags = (_flags), \
  18418. + }
  18419. +
  18420. +static const struct rb_board_info rb711gr100_boards[] __initconst = {
  18421. + RB_BOARD_INFO("911G-2HPnD", 0),
  18422. + RB_BOARD_INFO("911G-5HPnD", 0),
  18423. + RB_BOARD_INFO("912UAG-2HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE),
  18424. + RB_BOARD_INFO("912UAG-5HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE),
  18425. +};
  18426. +
  18427. +static u32 rb711gr100_get_flags(const struct rb_info *info)
  18428. +{
  18429. + int i;
  18430. +
  18431. + for (i = 0; i < ARRAY_SIZE(rb711gr100_boards); i++) {
  18432. + const struct rb_board_info *bi;
  18433. +
  18434. + bi = &rb711gr100_boards[i];
  18435. + if (strcmp(info->board_name, bi->name) == 0)
  18436. + return bi->flags;
  18437. + }
  18438. +
  18439. + return 0;
  18440. +}
  18441. +
  18442. +static void __init rb711gr100_setup(void)
  18443. +{
  18444. + const struct rb_info *info;
  18445. + char buf[64];
  18446. + u32 flags;
  18447. +
  18448. + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000);
  18449. + if (!info)
  18450. + return;
  18451. +
  18452. + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s",
  18453. + (info->board_name) ? info->board_name : "");
  18454. + mips_set_machine_name(buf);
  18455. +
  18456. + rb711gr100_init_partitions(info);
  18457. + ath79_register_spi(&rb711gr100_spi_data, rb711gr100_spi_info,
  18458. + ARRAY_SIZE(rb711gr100_spi_info));
  18459. +
  18460. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  18461. + AR934X_ETH_CFG_RXD_DELAY |
  18462. + AR934X_ETH_CFG_SW_ONLY_MODE);
  18463. +
  18464. + ath79_register_mdio(0, 0x0);
  18465. +
  18466. + mdiobus_register_board_info(rb91x_mdio0_info,
  18467. + ARRAY_SIZE(rb91x_mdio0_info));
  18468. +
  18469. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  18470. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  18471. + ath79_eth0_data.phy_mask = BIT(0);
  18472. + ath79_eth0_pll_data.pll_1000 = 0x02000000;
  18473. +
  18474. + ath79_register_eth(0);
  18475. +
  18476. + rb711gr100_wlan_init();
  18477. +
  18478. + platform_device_register_data(NULL, "rb91x-nand", -1,
  18479. + &rb711gr100_nand_data,
  18480. + sizeof(rb711gr100_nand_data));
  18481. +
  18482. + platform_device_register_data(NULL, "gpio-latch", -1,
  18483. + &rb711gr100_gpio_latch_data,
  18484. + sizeof(rb711gr100_gpio_latch_data));
  18485. +
  18486. + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb711gr100_leds),
  18487. + rb711gr100_leds);
  18488. +
  18489. + flags = rb711gr100_get_flags(info);
  18490. +
  18491. + if (flags & RB91X_FLAG_USB)
  18492. + ath79_register_usb();
  18493. +
  18494. + if (flags & RB91X_FLAG_PCIE)
  18495. + ath79_register_pci();
  18496. +
  18497. +}
  18498. +
  18499. +MIPS_MACHINE_NONAME(ATH79_MACH_RB_711GR100, "711Gr100", rb711gr100_setup);
  18500. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rb922.c linux-4.1.43/arch/mips/ath79/mach-rb922.c
  18501. --- linux-4.1.43.orig/arch/mips/ath79/mach-rb922.c 1970-01-01 01:00:00.000000000 +0100
  18502. +++ linux-4.1.43/arch/mips/ath79/mach-rb922.c 2017-08-06 20:02:15.000000000 +0200
  18503. @@ -0,0 +1,236 @@
  18504. +/*
  18505. + * MikroTik RouterBOARD 91X support
  18506. + *
  18507. + * Copyright (C) 2015 Gabor Juhos <juhosg@openwrt.org>
  18508. + *
  18509. + * This program is free software; you can redistribute it and/or modify it
  18510. + * under the terms of the GNU General Public License version 2 as published
  18511. + * by the Free Software Foundation.
  18512. + */
  18513. +
  18514. +#include <linux/phy.h>
  18515. +#include <linux/delay.h>
  18516. +#include <linux/platform_device.h>
  18517. +#include <linux/ath9k_platform.h>
  18518. +#include <linux/mtd/mtd.h>
  18519. +#include <linux/mtd/nand.h>
  18520. +#include <linux/mtd/partitions.h>
  18521. +#include <linux/spi/spi.h>
  18522. +#include <linux/spi/flash.h>
  18523. +#include <linux/routerboot.h>
  18524. +#include <linux/gpio.h>
  18525. +#include <linux/platform_data/phy-at803x.h>
  18526. +
  18527. +#include <asm/prom.h>
  18528. +#include <asm/mach-ath79/ath79.h>
  18529. +#include <asm/mach-ath79/ar71xx_regs.h>
  18530. +
  18531. +#include "common.h"
  18532. +#include "dev-gpio-buttons.h"
  18533. +#include "dev-eth.h"
  18534. +#include "dev-leds-gpio.h"
  18535. +#include "dev-m25p80.h"
  18536. +#include "dev-nfc.h"
  18537. +#include "dev-usb.h"
  18538. +#include "dev-spi.h"
  18539. +#include "machtypes.h"
  18540. +#include "pci.h"
  18541. +#include "routerboot.h"
  18542. +
  18543. +#define RB922_GPIO_LED_USR 12
  18544. +#define RB922_GPIO_USB_POWER 13
  18545. +#define RB922_GPIO_FAN_CTRL 14
  18546. +#define RB922_GPIO_BTN_RESET 20
  18547. +#define RB922_GPIO_NAND_NCE 23
  18548. +
  18549. +#define RB922_PHY_ADDR 4
  18550. +
  18551. +#define RB922_KEYS_POLL_INTERVAL 20 /* msecs */
  18552. +#define RB922_KEYS_DEBOUNCE_INTERVAL (3 * RB922_KEYS_POLL_INTERVAL)
  18553. +
  18554. +#define RB_ROUTERBOOT_OFFSET 0x0000
  18555. +#define RB_ROUTERBOOT_MIN_SIZE 0xb000
  18556. +#define RB_HARD_CFG_SIZE 0x1000
  18557. +#define RB_BIOS_OFFSET 0xd000
  18558. +#define RB_BIOS_SIZE 0x1000
  18559. +#define RB_SOFT_CFG_OFFSET 0xf000
  18560. +#define RB_SOFT_CFG_SIZE 0x1000
  18561. +
  18562. +static struct mtd_partition rb922gs_spi_partitions[] = {
  18563. + {
  18564. + .name = "routerboot",
  18565. + .offset = RB_ROUTERBOOT_OFFSET,
  18566. + .mask_flags = MTD_WRITEABLE,
  18567. + }, {
  18568. + .name = "hard_config",
  18569. + .size = RB_HARD_CFG_SIZE,
  18570. + .mask_flags = MTD_WRITEABLE,
  18571. + }, {
  18572. + .name = "bios",
  18573. + .offset = RB_BIOS_OFFSET,
  18574. + .size = RB_BIOS_SIZE,
  18575. + .mask_flags = MTD_WRITEABLE,
  18576. + }, {
  18577. + .name = "soft_config",
  18578. + .size = RB_SOFT_CFG_SIZE,
  18579. + }
  18580. +};
  18581. +
  18582. +static struct flash_platform_data rb922gs_spi_flash_data = {
  18583. + .parts = rb922gs_spi_partitions,
  18584. + .nr_parts = ARRAY_SIZE(rb922gs_spi_partitions),
  18585. +};
  18586. +
  18587. +static struct gpio_led rb922gs_leds[] __initdata = {
  18588. + {
  18589. + .name = "rb:green:user",
  18590. + .gpio = RB922_GPIO_LED_USR,
  18591. + .active_low = 1,
  18592. + },
  18593. +};
  18594. +
  18595. +static struct gpio_keys_button rb922gs_gpio_keys[] __initdata = {
  18596. + {
  18597. + .desc = "Reset button",
  18598. + .type = EV_KEY,
  18599. + .code = KEY_RESTART,
  18600. + .debounce_interval = RB922_KEYS_DEBOUNCE_INTERVAL,
  18601. + .gpio = RB922_GPIO_BTN_RESET,
  18602. + .active_low = 1,
  18603. + },
  18604. +};
  18605. +
  18606. +static struct at803x_platform_data rb922gs_at803x_data = {
  18607. + .disable_smarteee = 1,
  18608. +};
  18609. +
  18610. +static struct mdio_board_info rb922gs_mdio0_info[] = {
  18611. + {
  18612. + .bus_id = "ag71xx-mdio.0",
  18613. + .phy_addr = RB922_PHY_ADDR,
  18614. + .platform_data = &rb922gs_at803x_data,
  18615. + },
  18616. +};
  18617. +
  18618. +static void __init rb922gs_init_partitions(const struct rb_info *info)
  18619. +{
  18620. + rb922gs_spi_partitions[0].size = info->hard_cfg_offs;
  18621. + rb922gs_spi_partitions[1].offset = info->hard_cfg_offs;
  18622. + rb922gs_spi_partitions[3].offset = info->soft_cfg_offs;
  18623. +}
  18624. +
  18625. +static void rb922gs_nand_select_chip(int chip_no)
  18626. +{
  18627. + switch (chip_no) {
  18628. + case 0:
  18629. + gpio_set_value(RB922_GPIO_NAND_NCE, 0);
  18630. + break;
  18631. + default:
  18632. + gpio_set_value(RB922_GPIO_NAND_NCE, 1);
  18633. + break;
  18634. + }
  18635. + ndelay(500);
  18636. +}
  18637. +
  18638. +static struct nand_ecclayout rb922gs_nand_ecclayout = {
  18639. + .eccbytes = 6,
  18640. + .eccpos = { 8, 9, 10, 13, 14, 15 },
  18641. + .oobavail = 9,
  18642. + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  18643. +};
  18644. +
  18645. +static int rb922gs_nand_scan_fixup(struct mtd_info *mtd)
  18646. +{
  18647. + struct nand_chip *chip = mtd->priv;
  18648. +
  18649. + if (mtd->writesize == 512) {
  18650. + /*
  18651. + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
  18652. + * will not be able to find the kernel that we load.
  18653. + */
  18654. + chip->ecc.layout = &rb922gs_nand_ecclayout;
  18655. + }
  18656. +
  18657. + return 0;
  18658. +}
  18659. +
  18660. +static struct mtd_partition rb922gs_nand_partitions[] = {
  18661. + {
  18662. + .name = "booter",
  18663. + .offset = 0,
  18664. + .size = (256 * 1024),
  18665. + .mask_flags = MTD_WRITEABLE,
  18666. + },
  18667. + {
  18668. + .name = "kernel",
  18669. + .offset = (256 * 1024),
  18670. + .size = (4 * 1024 * 1024) - (256 * 1024),
  18671. + },
  18672. + {
  18673. + .name = "rootfs",
  18674. + .offset = MTDPART_OFS_NXTBLK,
  18675. + .size = MTDPART_SIZ_FULL,
  18676. + },
  18677. +};
  18678. +
  18679. +static void __init rb922gs_nand_init(void)
  18680. +{
  18681. + gpio_request_one(RB922_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE");
  18682. +
  18683. + ath79_nfc_set_scan_fixup(rb922gs_nand_scan_fixup);
  18684. + ath79_nfc_set_parts(rb922gs_nand_partitions,
  18685. + ARRAY_SIZE(rb922gs_nand_partitions));
  18686. + ath79_nfc_set_select_chip(rb922gs_nand_select_chip);
  18687. + ath79_nfc_set_swap_dma(true);
  18688. + ath79_register_nfc();
  18689. +}
  18690. +
  18691. +static void __init rb922gs_setup(void)
  18692. +{
  18693. + const struct rb_info *info;
  18694. + char buf[64];
  18695. +
  18696. + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000);
  18697. + if (!info)
  18698. + return;
  18699. +
  18700. + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s",
  18701. + (info->board_name) ? info->board_name : "");
  18702. + mips_set_machine_name(buf);
  18703. +
  18704. + rb922gs_init_partitions(info);
  18705. + ath79_register_m25p80(&rb922gs_spi_flash_data);
  18706. +
  18707. + rb922gs_nand_init();
  18708. +
  18709. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  18710. +
  18711. + ath79_register_mdio(0, 0x0);
  18712. +
  18713. + mdiobus_register_board_info(rb922gs_mdio0_info,
  18714. + ARRAY_SIZE(rb922gs_mdio0_info));
  18715. +
  18716. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  18717. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  18718. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  18719. + ath79_eth0_data.phy_mask = BIT(RB922_PHY_ADDR);
  18720. + ath79_eth0_pll_data.pll_10 = 0x81001313;
  18721. + ath79_eth0_pll_data.pll_100 = 0x81000101;
  18722. + ath79_eth0_pll_data.pll_1000 = 0x8f000000;
  18723. +
  18724. + ath79_register_eth(0);
  18725. +
  18726. + ath79_register_pci();
  18727. + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb922gs_leds), rb922gs_leds);
  18728. + ath79_register_gpio_keys_polled(-1, RB922_KEYS_POLL_INTERVAL,
  18729. + ARRAY_SIZE(rb922gs_gpio_keys),
  18730. + rb922gs_gpio_keys);
  18731. +
  18732. + /* NOTE:
  18733. + * This only supports the RB911G-5HPacD board for now. For other boards
  18734. + * more devices must be registered based on the hardware options which
  18735. + * can be found in the hardware configuration of RouterBOOT.
  18736. + */
  18737. +}
  18738. +
  18739. +MIPS_MACHINE_NONAME(ATH79_MACH_RB_922GS, "922gs", rb922gs_setup);
  18740. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rb95x.c linux-4.1.43/arch/mips/ath79/mach-rb95x.c
  18741. --- linux-4.1.43.orig/arch/mips/ath79/mach-rb95x.c 1970-01-01 01:00:00.000000000 +0100
  18742. +++ linux-4.1.43/arch/mips/ath79/mach-rb95x.c 2017-08-06 20:02:15.000000000 +0200
  18743. @@ -0,0 +1,258 @@
  18744. +/*
  18745. + * MikroTik RouterBOARD 95X support
  18746. + *
  18747. + * Copyright (C) 2012 Stijn Tintel <stijn@linux-ipv6.be>
  18748. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  18749. + * Copyright (C) 2013 Kamil Trzcinski <ayufan@ayufan.eu>
  18750. + *
  18751. + * This program is free software; you can redistribute it and/or modify it
  18752. + * under the terms of the GNU General Public License version 2 as published
  18753. + * by the Free Software Foundation.
  18754. + */
  18755. +
  18756. +#define pr_fmt(fmt) "rb95x: " fmt
  18757. +
  18758. +#include <linux/phy.h>
  18759. +#include <linux/delay.h>
  18760. +#include <linux/platform_device.h>
  18761. +#include <linux/ath9k_platform.h>
  18762. +#include <linux/ar8216_platform.h>
  18763. +#include <linux/mtd/mtd.h>
  18764. +#include <linux/mtd/nand.h>
  18765. +#include <linux/mtd/partitions.h>
  18766. +#include <linux/spi/spi.h>
  18767. +#include <linux/spi/flash.h>
  18768. +#include <linux/routerboot.h>
  18769. +#include <linux/gpio.h>
  18770. +
  18771. +#include <asm/mach-ath79/ath79.h>
  18772. +#include <asm/mach-ath79/ar71xx_regs.h>
  18773. +
  18774. +#include "common.h"
  18775. +#include "dev-eth.h"
  18776. +#include "dev-m25p80.h"
  18777. +#include "dev-nfc.h"
  18778. +#include "dev-usb.h"
  18779. +#include "dev-wmac.h"
  18780. +#include "machtypes.h"
  18781. +#include "routerboot.h"
  18782. +#include "dev-leds-gpio.h"
  18783. +
  18784. +#define RB95X_GPIO_NAND_NCE 14
  18785. +
  18786. +static struct mtd_partition rb95x_nand_partitions[] = {
  18787. + {
  18788. + .name = "booter",
  18789. + .offset = 0,
  18790. + .size = (256 * 1024),
  18791. + .mask_flags = MTD_WRITEABLE,
  18792. + },
  18793. + {
  18794. + .name = "kernel",
  18795. + .offset = (256 * 1024),
  18796. + .size = (4 * 1024 * 1024) - (256 * 1024),
  18797. + },
  18798. + {
  18799. + .name = "rootfs",
  18800. + .offset = MTDPART_OFS_NXTBLK,
  18801. + .size = MTDPART_SIZ_FULL,
  18802. + },
  18803. +};
  18804. +
  18805. +static struct gpio_led rb951ui_leds_gpio[] __initdata = {
  18806. + {
  18807. + .name = "rb:green:wlan",
  18808. + .gpio = 11,
  18809. + .active_low = 1,
  18810. + }, {
  18811. + .name = "rb:green:act",
  18812. + .gpio = 3,
  18813. + .active_low = 1,
  18814. + }, {
  18815. + .name = "rb:green:port1",
  18816. + .gpio = 13,
  18817. + .active_low = 1,
  18818. + }, {
  18819. + .name = "rb:green:port2",
  18820. + .gpio = 12,
  18821. + .active_low = 1,
  18822. + }, {
  18823. + .name = "rb:green:port3",
  18824. + .gpio = 4,
  18825. + .active_low = 1,
  18826. + }, {
  18827. + .name = "rb:green:port4",
  18828. + .gpio = 21,
  18829. + .active_low = 1,
  18830. + }, {
  18831. + .name = "rb:green:port5",
  18832. + .gpio = 16,
  18833. + .active_low = 1,
  18834. + }
  18835. +};
  18836. +
  18837. +static struct ar8327_pad_cfg rb95x_ar8327_pad0_cfg = {
  18838. + .mode = AR8327_PAD_MAC_RGMII,
  18839. + .txclk_delay_en = true,
  18840. + .rxclk_delay_en = true,
  18841. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  18842. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  18843. +};
  18844. +
  18845. +static struct ar8327_platform_data rb95x_ar8327_data = {
  18846. + .pad0_cfg = &rb95x_ar8327_pad0_cfg,
  18847. + .port0_cfg = {
  18848. + .force_link = 1,
  18849. + .speed = AR8327_PORT_SPEED_1000,
  18850. + .duplex = 1,
  18851. + .txpause = 1,
  18852. + .rxpause = 1,
  18853. + }
  18854. +};
  18855. +
  18856. +static struct mdio_board_info rb95x_mdio0_info[] = {
  18857. + {
  18858. + .bus_id = "ag71xx-mdio.0",
  18859. + .phy_addr = 0,
  18860. + .platform_data = &rb95x_ar8327_data,
  18861. + },
  18862. +};
  18863. +
  18864. +void __init rb95x_wlan_init(void)
  18865. +{
  18866. + char *art_buf;
  18867. + u8 wlan_mac[ETH_ALEN];
  18868. +
  18869. + art_buf = rb_get_wlan_data();
  18870. + if (art_buf == NULL)
  18871. + return;
  18872. +
  18873. + ath79_init_mac(wlan_mac, ath79_mac_base, 11);
  18874. + ath79_register_wmac(art_buf + 0x1000, wlan_mac);
  18875. +
  18876. + kfree(art_buf);
  18877. +}
  18878. +
  18879. +static void rb95x_nand_select_chip(int chip_no)
  18880. +{
  18881. + switch (chip_no) {
  18882. + case 0:
  18883. + gpio_set_value(RB95X_GPIO_NAND_NCE, 0);
  18884. + break;
  18885. + default:
  18886. + gpio_set_value(RB95X_GPIO_NAND_NCE, 1);
  18887. + break;
  18888. + }
  18889. + ndelay(500);
  18890. +}
  18891. +
  18892. +static struct nand_ecclayout rb95x_nand_ecclayout = {
  18893. + .eccbytes = 6,
  18894. + .eccpos = { 8, 9, 10, 13, 14, 15 },
  18895. + .oobavail = 9,
  18896. + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  18897. +};
  18898. +
  18899. +static int rb95x_nand_scan_fixup(struct mtd_info *mtd)
  18900. +{
  18901. + struct nand_chip *chip = mtd->priv;
  18902. +
  18903. + if (mtd->writesize == 512) {
  18904. + /*
  18905. + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
  18906. + * will not be able to find the kernel that we load.
  18907. + */
  18908. + chip->ecc.layout = &rb95x_nand_ecclayout;
  18909. + }
  18910. +
  18911. + return 0;
  18912. +}
  18913. +
  18914. +void __init rb95x_nand_init(void)
  18915. +{
  18916. + gpio_request_one(RB95X_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE");
  18917. +
  18918. + ath79_nfc_set_scan_fixup(rb95x_nand_scan_fixup);
  18919. + ath79_nfc_set_parts(rb95x_nand_partitions,
  18920. + ARRAY_SIZE(rb95x_nand_partitions));
  18921. + ath79_nfc_set_select_chip(rb95x_nand_select_chip);
  18922. + ath79_nfc_set_swap_dma(true);
  18923. + ath79_register_nfc();
  18924. +}
  18925. +
  18926. +static int __init rb95x_setup(void)
  18927. +{
  18928. + const struct rb_info *info;
  18929. +
  18930. + info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x10000);
  18931. + if (!info)
  18932. + return -EINVAL;
  18933. +
  18934. + rb95x_nand_init();
  18935. +
  18936. + return 0;
  18937. +}
  18938. +
  18939. +static void __init rb951g_setup(void)
  18940. +{
  18941. + if (rb95x_setup())
  18942. + return;
  18943. +
  18944. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  18945. + AR934X_ETH_CFG_SW_ONLY_MODE);
  18946. +
  18947. + ath79_register_mdio(0, 0x0);
  18948. +
  18949. + mdiobus_register_board_info(rb95x_mdio0_info,
  18950. + ARRAY_SIZE(rb95x_mdio0_info));
  18951. +
  18952. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  18953. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  18954. + ath79_eth0_data.phy_mask = BIT(0);
  18955. +
  18956. + ath79_register_eth(0);
  18957. +
  18958. + rb95x_wlan_init();
  18959. + ath79_register_usb();
  18960. +}
  18961. +
  18962. +MIPS_MACHINE(ATH79_MACH_RB_951G, "951G", "MikroTik RouterBOARD 951G-2HnD",
  18963. + rb951g_setup);
  18964. +
  18965. +static void __init rb951ui_setup(void)
  18966. +{
  18967. + if (rb95x_setup())
  18968. + return;
  18969. +
  18970. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  18971. +
  18972. + ath79_register_mdio(1, 0x0);
  18973. +
  18974. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  18975. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  18976. +
  18977. + ath79_switch_data.phy4_mii_en = 1;
  18978. + ath79_switch_data.phy_poll_mask = BIT(4);
  18979. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  18980. + ath79_eth0_data.phy_mask = BIT(4);
  18981. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  18982. + ath79_register_eth(0);
  18983. +
  18984. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  18985. + ath79_register_eth(1);
  18986. +
  18987. + gpio_request_one(20, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  18988. + "USB power");
  18989. +
  18990. + gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  18991. + "POE power");
  18992. +
  18993. + rb95x_wlan_init();
  18994. + ath79_register_usb();
  18995. +
  18996. + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb951ui_leds_gpio),
  18997. + rb951ui_leds_gpio);
  18998. +}
  18999. +
  19000. +MIPS_MACHINE(ATH79_MACH_RB_951U, "951HnD", "MikroTik RouterBOARD 951Ui-2HnD",
  19001. + rb951ui_setup);
  19002. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rbsxtlite.c linux-4.1.43/arch/mips/ath79/mach-rbsxtlite.c
  19003. --- linux-4.1.43.orig/arch/mips/ath79/mach-rbsxtlite.c 1970-01-01 01:00:00.000000000 +0100
  19004. +++ linux-4.1.43/arch/mips/ath79/mach-rbsxtlite.c 2017-08-06 20:02:15.000000000 +0200
  19005. @@ -0,0 +1,238 @@
  19006. +/*
  19007. + * MikroTik RouterBOARD SXT Lite support
  19008. + *
  19009. + * Copyright (C) 2012 Stijn Tintel <stijn@linux-ipv6.be>
  19010. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  19011. + * Copyright (C) 2013 Vyacheslav Adamanov <adamanov@gmail.com>
  19012. + *
  19013. + * This program is free software; you can redistribute it and/or modify it
  19014. + * under the terms of the GNU General Public License version 2 as published
  19015. + * by the Free Software Foundation.
  19016. + */
  19017. +
  19018. +#define pr_fmt(fmt) "sxtlite: " fmt
  19019. +
  19020. +#include <linux/phy.h>
  19021. +#include <linux/delay.h>
  19022. +#include <linux/platform_device.h>
  19023. +#include <linux/ath9k_platform.h>
  19024. +#include <linux/mtd/mtd.h>
  19025. +#include <linux/mtd/nand.h>
  19026. +#include <linux/mtd/partitions.h>
  19027. +#include <linux/spi/spi.h>
  19028. +#include <linux/spi/flash.h>
  19029. +#include <linux/rle.h>
  19030. +#include <linux/routerboot.h>
  19031. +#include <linux/gpio.h>
  19032. +
  19033. +#include <asm/mach-ath79/ath79.h>
  19034. +#include <asm/mach-ath79/ar71xx_regs.h>
  19035. +#include "common.h"
  19036. +#include "dev-ap9x-pci.h"
  19037. +#include "dev-gpio-buttons.h"
  19038. +#include "dev-leds-gpio.h"
  19039. +#include "dev-eth.h"
  19040. +#include "dev-m25p80.h"
  19041. +#include "dev-nfc.h"
  19042. +#include "dev-wmac.h"
  19043. +#include "dev-usb.h"
  19044. +#include "machtypes.h"
  19045. +#include "routerboot.h"
  19046. +#include <linux/ar8216_platform.h>
  19047. +
  19048. +#define SXTLITE_GPIO_NAND_NCE 14
  19049. +#define SXTLITE_GPIO_LED_USER 3
  19050. +#define SXTLITE_GPIO_LED_1 13
  19051. +#define SXTLITE_GPIO_LED_2 12
  19052. +#define SXTLITE_GPIO_LED_3 4
  19053. +#define SXTLITE_GPIO_LED_4 21
  19054. +#define SXTLITE_GPIO_LED_5 18
  19055. +#define SXTLITE_GPIO_LED_POWER 11
  19056. +
  19057. +#define SXTLITE_GPIO_BUZZER 19
  19058. +
  19059. +#define SXTLITE_GPIO_BTN_RESET 15
  19060. +
  19061. +#define SXTLITE_KEYS_POLL_INTERVAL 20
  19062. +#define SXTLITE_KEYS_DEBOUNCE_INTERVAL (3 * SXTLITE_KEYS_POLL_INTERVAL)
  19063. +
  19064. +static struct mtd_partition rbsxtlite_nand_partitions[] = {
  19065. + {
  19066. + .name = "booter",
  19067. + .offset = 0,
  19068. + .size = (256 * 1024),
  19069. + .mask_flags = MTD_WRITEABLE,
  19070. + },
  19071. + {
  19072. + .name = "kernel",
  19073. + .offset = (256 * 1024),
  19074. + .size = (4 * 1024 * 1024) - (256 * 1024),
  19075. + },
  19076. + {
  19077. + .name = "rootfs",
  19078. + .offset = MTDPART_OFS_NXTBLK,
  19079. + .size = MTDPART_SIZ_FULL,
  19080. + },
  19081. +};
  19082. +
  19083. +static struct gpio_led rbsxtlite_leds_gpio[] __initdata = {
  19084. + {
  19085. + .name = "rb:green:user",
  19086. + .gpio = SXTLITE_GPIO_LED_USER,
  19087. + .active_low = 1,
  19088. + },
  19089. + {
  19090. + .name = "rb:green:led1",
  19091. + .gpio = SXTLITE_GPIO_LED_1,
  19092. + .active_low = 1,
  19093. + },
  19094. + {
  19095. + .name = "rb:green:led2",
  19096. + .gpio = SXTLITE_GPIO_LED_2,
  19097. + .active_low = 1,
  19098. + },
  19099. + {
  19100. + .name = "rb:green:led3",
  19101. + .gpio = SXTLITE_GPIO_LED_3,
  19102. + .active_low = 1,
  19103. + },
  19104. + {
  19105. + .name = "rb:green:led4",
  19106. + .gpio = SXTLITE_GPIO_LED_4,
  19107. + .active_low = 1,
  19108. + },
  19109. + {
  19110. + .name = "rb:green:led5",
  19111. + .gpio = SXTLITE_GPIO_LED_5,
  19112. + .active_low = 1,
  19113. + },
  19114. + {
  19115. + .name = "rb:green:power",
  19116. + .gpio = SXTLITE_GPIO_LED_POWER,
  19117. + },
  19118. +};
  19119. +
  19120. +static struct gpio_keys_button rbsxtlite_gpio_keys[] __initdata = {
  19121. + {
  19122. + .desc = "Reset button",
  19123. + .type = EV_KEY,
  19124. + .code = KEY_RESTART,
  19125. + .debounce_interval = SXTLITE_KEYS_DEBOUNCE_INTERVAL,
  19126. + .gpio = SXTLITE_GPIO_BTN_RESET,
  19127. + .active_low = 0,
  19128. + },
  19129. +};
  19130. +
  19131. +static int __init rbsxtlite_rbinfo_init(void)
  19132. +{
  19133. + const struct rb_info *info;
  19134. +
  19135. + info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x10000);
  19136. + if (!info)
  19137. + return -EINVAL;
  19138. + return 0;
  19139. +
  19140. +}
  19141. +
  19142. +void __init rbsxtlite_wlan_init(void)
  19143. +{
  19144. + char *art_buf;
  19145. + u8 wlan_mac[ETH_ALEN];
  19146. +
  19147. + art_buf = rb_get_wlan_data();
  19148. + if (art_buf == NULL)
  19149. + return;
  19150. +
  19151. + ath79_init_mac(wlan_mac, ath79_mac_base, 1);
  19152. + ath79_register_wmac(art_buf + 0x1000, wlan_mac);
  19153. +
  19154. + kfree(art_buf);
  19155. +}
  19156. +
  19157. +static void rbsxtlite_nand_select_chip(int chip_no)
  19158. +{
  19159. + switch (chip_no) {
  19160. + case 0:
  19161. + gpio_set_value(SXTLITE_GPIO_NAND_NCE, 0);
  19162. + break;
  19163. + default:
  19164. + gpio_set_value(SXTLITE_GPIO_NAND_NCE, 1);
  19165. + break;
  19166. + }
  19167. + ndelay(500);
  19168. +}
  19169. +
  19170. +static struct nand_ecclayout rbsxtlite_nand_ecclayout = {
  19171. + .eccbytes = 6,
  19172. + .eccpos = { 8, 9, 10, 13, 14, 15 },
  19173. + .oobavail = 9,
  19174. + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  19175. +};
  19176. +
  19177. +static int rbsxtlite_nand_scan_fixup(struct mtd_info *mtd)
  19178. +{
  19179. + struct nand_chip *chip = mtd->priv;
  19180. +
  19181. + if (mtd->writesize == 512) {
  19182. + /*
  19183. + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
  19184. + * will not be able to find the kernel that we load.
  19185. + */
  19186. + chip->ecc.layout = &rbsxtlite_nand_ecclayout;
  19187. + }
  19188. +
  19189. + return 0;
  19190. +}
  19191. +
  19192. +void __init rbsxtlite_gpio_init(void)
  19193. +{
  19194. + gpio_request_one(SXTLITE_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE");
  19195. +}
  19196. +
  19197. +void __init rbsxtlite_nand_init(void)
  19198. +{
  19199. + ath79_nfc_set_scan_fixup(rbsxtlite_nand_scan_fixup);
  19200. + ath79_nfc_set_parts(rbsxtlite_nand_partitions,
  19201. + ARRAY_SIZE(rbsxtlite_nand_partitions));
  19202. + ath79_nfc_set_select_chip(rbsxtlite_nand_select_chip);
  19203. + ath79_nfc_set_swap_dma(true);
  19204. + ath79_register_nfc();
  19205. +}
  19206. +
  19207. +
  19208. +static void __init rbsxtlite_setup(void)
  19209. +{
  19210. + if(rbsxtlite_rbinfo_init())
  19211. + return;
  19212. + rbsxtlite_nand_init();
  19213. + rbsxtlite_wlan_init();
  19214. +
  19215. + ath79_register_leds_gpio(-1, ARRAY_SIZE(rbsxtlite_leds_gpio),
  19216. + rbsxtlite_leds_gpio);
  19217. + ath79_register_gpio_keys_polled(-1, SXTLITE_KEYS_POLL_INTERVAL,
  19218. + ARRAY_SIZE(rbsxtlite_gpio_keys),
  19219. + rbsxtlite_gpio_keys);
  19220. +
  19221. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  19222. +
  19223. + ath79_register_mdio(1, 0x0);
  19224. +
  19225. + /* GMAC0 is left unused */
  19226. +
  19227. + /* GMAC1 is connected to MAC0 on the internal switch */
  19228. + /* The ethernet port connects to PHY P0, which connects to MAC1
  19229. + on the internal switch */
  19230. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
  19231. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  19232. + ath79_register_eth(1);
  19233. +
  19234. +
  19235. +}
  19236. +
  19237. +
  19238. +MIPS_MACHINE(ATH79_MACH_RB_SXTLITE2ND, "sxt2n", "Mikrotik RouterBOARD SXT Lite2",
  19239. + rbsxtlite_setup);
  19240. +
  19241. +MIPS_MACHINE(ATH79_MACH_RB_SXTLITE5ND, "sxt5n", "Mikrotik RouterBOARD SXT Lite5",
  19242. + rbsxtlite_setup);
  19243. +
  19244. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-rw2458n.c linux-4.1.43/arch/mips/ath79/mach-rw2458n.c
  19245. --- linux-4.1.43.orig/arch/mips/ath79/mach-rw2458n.c 1970-01-01 01:00:00.000000000 +0100
  19246. +++ linux-4.1.43/arch/mips/ath79/mach-rw2458n.c 2017-08-06 20:02:15.000000000 +0200
  19247. @@ -0,0 +1,91 @@
  19248. +/*
  19249. + * Redwave RW2458N support
  19250. + *
  19251. + * Copyright (C) 2011-2013 Cezary Jackiewicz <cezary@eko.one.pl>
  19252. + *
  19253. + * This program is free software; you can redistribute it and/or modify it
  19254. + * under the terms of the GNU General Public License version 2 as published
  19255. + * by the Free Software Foundation.
  19256. + */
  19257. +
  19258. +#include <asm/mach-ath79/ath79.h>
  19259. +
  19260. +#include "dev-eth.h"
  19261. +#include "dev-ap9x-pci.h"
  19262. +#include "dev-gpio-buttons.h"
  19263. +#include "dev-leds-gpio.h"
  19264. +#include "dev-m25p80.h"
  19265. +#include "dev-usb.h"
  19266. +#include "machtypes.h"
  19267. +#include "pci.h"
  19268. +
  19269. +#define RW2458N_GPIO_LED_D3 1
  19270. +#define RW2458N_GPIO_LED_D4 0
  19271. +#define RW2458N_GPIO_LED_D5 11
  19272. +#define RW2458N_GPIO_LED_D6 7
  19273. +#define RW2458N_GPIO_BTN_RESET 12
  19274. +
  19275. +#define RW2458N_KEYS_POLL_INTERVAL 20 /* msecs */
  19276. +#define RW2458N_KEYS_DEBOUNCE_INTERVAL (3 * RW2458N_KEYS_POLL_INTERVAL)
  19277. +
  19278. +static struct gpio_keys_button rw2458n_gpio_keys[] __initdata = {
  19279. + {
  19280. + .desc = "reset",
  19281. + .type = EV_KEY,
  19282. + .code = KEY_RESTART,
  19283. + .debounce_interval = RW2458N_KEYS_DEBOUNCE_INTERVAL,
  19284. + .gpio = RW2458N_GPIO_BTN_RESET,
  19285. + .active_low = 1,
  19286. + }
  19287. +};
  19288. +
  19289. +#define RW2458N_WAN_PHYMASK BIT(4)
  19290. +
  19291. +static struct gpio_led rw2458n_leds_gpio[] __initdata = {
  19292. + {
  19293. + .name = "rw2458n:green:d3",
  19294. + .gpio = RW2458N_GPIO_LED_D3,
  19295. + .active_low = 1,
  19296. + }, {
  19297. + .name = "rw2458n:green:d4",
  19298. + .gpio = RW2458N_GPIO_LED_D4,
  19299. + .active_low = 1,
  19300. + }, {
  19301. + .name = "rw2458n:green:d5",
  19302. + .gpio = RW2458N_GPIO_LED_D5,
  19303. + .active_low = 1,
  19304. + }, {
  19305. + .name = "rw2458n:green:d6",
  19306. + .gpio = RW2458N_GPIO_LED_D6,
  19307. + .active_low = 1,
  19308. + }
  19309. +};
  19310. +
  19311. +static void __init rw2458n_setup(void)
  19312. +{
  19313. + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
  19314. + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
  19315. +
  19316. + ath79_register_m25p80(NULL);
  19317. +
  19318. + ath79_register_mdio(0, ~RW2458N_WAN_PHYMASK);
  19319. +
  19320. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  19321. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
  19322. +
  19323. + ath79_register_eth(0);
  19324. + ath79_register_eth(1);
  19325. +
  19326. + ath79_register_leds_gpio(-1, ARRAY_SIZE(rw2458n_leds_gpio),
  19327. + rw2458n_leds_gpio);
  19328. +
  19329. + ath79_register_gpio_keys_polled(-1, RW2458N_KEYS_POLL_INTERVAL,
  19330. + ARRAY_SIZE(rw2458n_gpio_keys),
  19331. + rw2458n_gpio_keys);
  19332. + ath79_register_usb();
  19333. +
  19334. + ath79_register_pci();
  19335. +}
  19336. +
  19337. +MIPS_MACHINE(ATH79_MACH_RW2458N, "RW2458N", "Redwave RW2458N",
  19338. + rw2458n_setup);
  19339. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-smart-300.c linux-4.1.43/arch/mips/ath79/mach-smart-300.c
  19340. --- linux-4.1.43.orig/arch/mips/ath79/mach-smart-300.c 1970-01-01 01:00:00.000000000 +0100
  19341. +++ linux-4.1.43/arch/mips/ath79/mach-smart-300.c 2017-08-06 20:02:15.000000000 +0200
  19342. @@ -0,0 +1,135 @@
  19343. +/*
  19344. + * NC-LINK SMART-300 board support
  19345. + *
  19346. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  19347. + * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
  19348. + *
  19349. + * This program is free software; you can redistribute it and/or modify it
  19350. + * under the terms of the GNU General Public License version 2 as published
  19351. + * by the Free Software Foundation.
  19352. + */
  19353. +
  19354. +#include <linux/platform_device.h>
  19355. +#include <linux/gpio.h>
  19356. +#include <asm/mach-ath79/ath79.h>
  19357. +#include <asm/mach-ath79/ar71xx_regs.h>
  19358. +#include <asm/mach-ath79/ag71xx_platform.h>
  19359. +
  19360. +#include "common.h"
  19361. +#include "dev-eth.h"
  19362. +#include "dev-gpio-buttons.h"
  19363. +#include "dev-leds-gpio.h"
  19364. +#include "dev-m25p80.h"
  19365. +#include "dev-wmac.h"
  19366. +#include "machtypes.h"
  19367. +
  19368. +#define SMART_300_GPIO_LED_WLAN 13
  19369. +#define SMART_300_GPIO_LED_WAN 18
  19370. +#define SMART_300_GPIO_LED_LAN4 19
  19371. +#define SMART_300_GPIO_LED_LAN3 12
  19372. +#define SMART_300_GPIO_LED_LAN2 21
  19373. +#define SMART_300_GPIO_LED_LAN1 20
  19374. +#define SMART_300_GPIO_LED_SYSTEM 15
  19375. +#define SMART_300_GPIO_LED_POWER 14
  19376. +
  19377. +#define SMART_300_GPIO_BTN_RESET 17
  19378. +#define SMART_300_GPIO_SW_RFKILL 16
  19379. +
  19380. +#define SMART_300_KEYS_POLL_INTERVAL 20 /* msecs */
  19381. +#define SMART_300_KEYS_DEBOUNCE_INTERVAL (3 * SMART_300_KEYS_POLL_INTERVAL)
  19382. +
  19383. +#define SMART_300_GPIO_MASK 0x007fffff
  19384. +
  19385. +static const char *smart_300_part_probes[] = {
  19386. + "tp-link",
  19387. + NULL,
  19388. +};
  19389. +
  19390. +static struct flash_platform_data smart_300_flash_data = {
  19391. + .part_probes = smart_300_part_probes,
  19392. +};
  19393. +
  19394. +static struct gpio_led smart_300_leds_gpio[] __initdata = {
  19395. + {
  19396. + .name = "nc-link:green:lan1",
  19397. + .gpio = SMART_300_GPIO_LED_LAN1,
  19398. + .active_low = 1,
  19399. + }, {
  19400. + .name = "nc-link:green:lan2",
  19401. + .gpio = SMART_300_GPIO_LED_LAN2,
  19402. + .active_low = 1,
  19403. + }, {
  19404. + .name = "nc-link:green:lan3",
  19405. + .gpio = SMART_300_GPIO_LED_LAN3,
  19406. + .active_low = 1,
  19407. + }, {
  19408. + .name = "nc-link:green:lan4",
  19409. + .gpio = SMART_300_GPIO_LED_LAN4,
  19410. + .active_low = 1,
  19411. + }, {
  19412. + .name = "nc-link:green:system",
  19413. + .gpio = SMART_300_GPIO_LED_SYSTEM,
  19414. + .active_low = 1,
  19415. + }, {
  19416. + .name = "nc-link:green:wan",
  19417. + .gpio = SMART_300_GPIO_LED_WAN,
  19418. + .active_low = 1,
  19419. + }, {
  19420. + .name = "nc-link:green:wlan",
  19421. + .gpio = SMART_300_GPIO_LED_WLAN,
  19422. + .active_low = 1,
  19423. + },
  19424. +};
  19425. +
  19426. +static struct gpio_keys_button smart_300_gpio_keys[] __initdata = {
  19427. + {
  19428. + .desc = "reset",
  19429. + .type = EV_KEY,
  19430. + .code = KEY_RESTART,
  19431. + .debounce_interval = SMART_300_KEYS_DEBOUNCE_INTERVAL,
  19432. + .gpio = SMART_300_GPIO_BTN_RESET,
  19433. + .active_low = 1,
  19434. + }
  19435. +};
  19436. +
  19437. +static void __init smart_300_setup(void)
  19438. +{
  19439. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  19440. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  19441. +
  19442. + ath79_register_leds_gpio(-1, ARRAY_SIZE(smart_300_leds_gpio),
  19443. + smart_300_leds_gpio);
  19444. +
  19445. + ath79_register_gpio_keys_polled(1, SMART_300_KEYS_POLL_INTERVAL,
  19446. + ARRAY_SIZE(smart_300_gpio_keys),
  19447. + smart_300_gpio_keys);
  19448. +
  19449. + ath79_register_m25p80(&smart_300_flash_data);
  19450. +
  19451. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  19452. +
  19453. + ath79_register_mdio(1, 0x0);
  19454. +
  19455. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
  19456. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  19457. +
  19458. + /* GMAC0 is connected to the PHY0 of the internal switch */
  19459. + ath79_switch_data.phy4_mii_en = 1;
  19460. + ath79_switch_data.phy_poll_mask = BIT(4);
  19461. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  19462. + ath79_eth0_data.phy_mask = BIT(4);
  19463. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  19464. + ath79_register_eth(0);
  19465. +
  19466. + /* GMAC1 is connected to the internal switch */
  19467. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  19468. + ath79_register_eth(1);
  19469. +
  19470. + ath79_register_wmac(ee, mac);
  19471. +
  19472. + gpio_request(SMART_300_GPIO_LED_POWER, "power");
  19473. + gpio_direction_output(SMART_300_GPIO_LED_POWER, GPIOF_OUT_INIT_LOW);
  19474. +}
  19475. +
  19476. +MIPS_MACHINE(ATH79_MACH_SMART_300, "SMART-300", "NC-LINK SMART-300",
  19477. + smart_300_setup);
  19478. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tew-632brp.c linux-4.1.43/arch/mips/ath79/mach-tew-632brp.c
  19479. --- linux-4.1.43.orig/arch/mips/ath79/mach-tew-632brp.c 1970-01-01 01:00:00.000000000 +0100
  19480. +++ linux-4.1.43/arch/mips/ath79/mach-tew-632brp.c 2017-08-06 20:02:15.000000000 +0200
  19481. @@ -0,0 +1,111 @@
  19482. +/*
  19483. + * TrendNET TEW-632BRP board support
  19484. + *
  19485. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  19486. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  19487. + *
  19488. + * This program is free software; you can redistribute it and/or modify it
  19489. + * under the terms of the GNU General Public License version 2 as published
  19490. + * by the Free Software Foundation.
  19491. + */
  19492. +
  19493. +#include <asm/mach-ath79/ath79.h>
  19494. +
  19495. +#include "dev-eth.h"
  19496. +#include "dev-gpio-buttons.h"
  19497. +#include "dev-leds-gpio.h"
  19498. +#include "dev-m25p80.h"
  19499. +#include "dev-wmac.h"
  19500. +#include "machtypes.h"
  19501. +#include "nvram.h"
  19502. +
  19503. +#define TEW_632BRP_GPIO_LED_STATUS 1
  19504. +#define TEW_632BRP_GPIO_LED_WPS 3
  19505. +#define TEW_632BRP_GPIO_LED_WLAN 6
  19506. +#define TEW_632BRP_GPIO_BTN_WPS 12
  19507. +#define TEW_632BRP_GPIO_BTN_RESET 21
  19508. +
  19509. +#define TEW_632BRP_KEYS_POLL_INTERVAL 20 /* msecs */
  19510. +#define TEW_632BRP_KEYS_DEBOUNCE_INTERVAL (3 * TEW_632BRP_KEYS_POLL_INTERVAL)
  19511. +
  19512. +#define TEW_632BRP_CONFIG_ADDR 0x1f020000
  19513. +#define TEW_632BRP_CONFIG_SIZE 0x10000
  19514. +
  19515. +static struct gpio_led tew_632brp_leds_gpio[] __initdata = {
  19516. + {
  19517. + .name = "tew-632brp:green:status",
  19518. + .gpio = TEW_632BRP_GPIO_LED_STATUS,
  19519. + .active_low = 1,
  19520. + }, {
  19521. + .name = "tew-632brp:blue:wps",
  19522. + .gpio = TEW_632BRP_GPIO_LED_WPS,
  19523. + .active_low = 1,
  19524. + }, {
  19525. + .name = "tew-632brp:green:wlan",
  19526. + .gpio = TEW_632BRP_GPIO_LED_WLAN,
  19527. + .active_low = 1,
  19528. + }
  19529. +};
  19530. +
  19531. +static struct gpio_keys_button tew_632brp_gpio_keys[] __initdata = {
  19532. + {
  19533. + .desc = "reset",
  19534. + .type = EV_KEY,
  19535. + .code = KEY_RESTART,
  19536. + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL,
  19537. + .gpio = TEW_632BRP_GPIO_BTN_RESET,
  19538. + .active_low = 1,
  19539. + }, {
  19540. + .desc = "wps",
  19541. + .type = EV_KEY,
  19542. + .code = KEY_WPS_BUTTON,
  19543. + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL,
  19544. + .gpio = TEW_632BRP_GPIO_BTN_WPS,
  19545. + .active_low = 1,
  19546. + }
  19547. +};
  19548. +
  19549. +#define TEW_632BRP_LAN_PHYMASK BIT(0)
  19550. +#define TEW_632BRP_WAN_PHYMASK BIT(4)
  19551. +#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \
  19552. + TEW_632BRP_WAN_PHYMASK))
  19553. +
  19554. +static void __init tew_632brp_setup(void)
  19555. +{
  19556. + const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR);
  19557. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  19558. + u8 mac[6];
  19559. + u8 *wlan_mac = NULL;
  19560. +
  19561. + if (ath79_nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE,
  19562. + "lan_mac=", mac) == 0) {
  19563. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  19564. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  19565. + wlan_mac = mac;
  19566. + }
  19567. +
  19568. + ath79_register_mdio(0, TEW_632BRP_MDIO_MASK);
  19569. +
  19570. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  19571. + ath79_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK;
  19572. +
  19573. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  19574. + ath79_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK;
  19575. +
  19576. + ath79_register_eth(0);
  19577. + ath79_register_eth(1);
  19578. +
  19579. + ath79_register_m25p80(NULL);
  19580. +
  19581. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio),
  19582. + tew_632brp_leds_gpio);
  19583. +
  19584. + ath79_register_gpio_keys_polled(-1, TEW_632BRP_KEYS_POLL_INTERVAL,
  19585. + ARRAY_SIZE(tew_632brp_gpio_keys),
  19586. + tew_632brp_gpio_keys);
  19587. +
  19588. + ath79_register_wmac(eeprom, wlan_mac);
  19589. +}
  19590. +
  19591. +MIPS_MACHINE(ATH79_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP",
  19592. + tew_632brp_setup);
  19593. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tew-673gru.c linux-4.1.43/arch/mips/ath79/mach-tew-673gru.c
  19594. --- linux-4.1.43.orig/arch/mips/ath79/mach-tew-673gru.c 1970-01-01 01:00:00.000000000 +0100
  19595. +++ linux-4.1.43/arch/mips/ath79/mach-tew-673gru.c 2017-08-06 20:02:15.000000000 +0200
  19596. @@ -0,0 +1,198 @@
  19597. +/*
  19598. + * TRENDnet TEW-673GRU board support
  19599. + *
  19600. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  19601. + *
  19602. + * This program is free software; you can redistribute it and/or modify it
  19603. + * under the terms of the GNU General Public License version 2 as published
  19604. + * by the Free Software Foundation.
  19605. + */
  19606. +
  19607. +#include <linux/platform_device.h>
  19608. +#include <linux/delay.h>
  19609. +#include <linux/rtl8366.h>
  19610. +#include <linux/spi/spi.h>
  19611. +#include <linux/spi/spi_gpio.h>
  19612. +
  19613. +#include <asm/mach-ath79/ath79.h>
  19614. +
  19615. +#include "dev-ap9x-pci.h"
  19616. +#include "dev-eth.h"
  19617. +#include "dev-gpio-buttons.h"
  19618. +#include "dev-leds-gpio.h"
  19619. +#include "dev-m25p80.h"
  19620. +#include "dev-usb.h"
  19621. +#include "machtypes.h"
  19622. +
  19623. +#define TEW673GRU_GPIO_LCD_SCK 0
  19624. +#define TEW673GRU_GPIO_LCD_MOSI 1
  19625. +#define TEW673GRU_GPIO_LCD_MISO 2
  19626. +#define TEW673GRU_GPIO_LCD_CS 6
  19627. +
  19628. +#define TEW673GRU_GPIO_LED_WPS 9
  19629. +
  19630. +#define TEW673GRU_GPIO_BTN_RESET 3
  19631. +#define TEW673GRU_GPIO_BTN_WPS 8
  19632. +
  19633. +#define TEW673GRU_GPIO_RTL8366_SDA 5
  19634. +#define TEW673GRU_GPIO_RTL8366_SCK 7
  19635. +
  19636. +#define TEW673GRU_KEYS_POLL_INTERVAL 20 /* msecs */
  19637. +#define TEW673GRU_KEYS_DEBOUNCE_INTERVAL (3 * TEW673GRU_KEYS_POLL_INTERVAL)
  19638. +
  19639. +#define TEW673GRU_CAL0_OFFSET 0x1000
  19640. +#define TEW673GRU_CAL1_OFFSET 0x5000
  19641. +#define TEW673GRU_MAC0_OFFSET 0xffa0
  19642. +#define TEW673GRU_MAC1_OFFSET 0xffb4
  19643. +
  19644. +#define TEW673GRU_CAL_LOCATION_0 0x1f660000
  19645. +#define TEW673GRU_CAL_LOCATION_1 0x1f7f0000
  19646. +
  19647. +static struct gpio_led tew673gru_leds_gpio[] __initdata = {
  19648. + {
  19649. + .name = "trendnet:blue:wps",
  19650. + .gpio = TEW673GRU_GPIO_LED_WPS,
  19651. + .active_low = 1,
  19652. + }
  19653. +};
  19654. +
  19655. +static struct gpio_keys_button tew673gru_gpio_keys[] __initdata = {
  19656. + {
  19657. + .desc = "reset",
  19658. + .type = EV_KEY,
  19659. + .code = KEY_RESTART,
  19660. + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL,
  19661. + .gpio = TEW673GRU_GPIO_BTN_RESET,
  19662. + .active_low = 1,
  19663. + }, {
  19664. + .desc = "wps",
  19665. + .type = EV_KEY,
  19666. + .code = KEY_WPS_BUTTON,
  19667. + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL,
  19668. + .gpio = TEW673GRU_GPIO_BTN_WPS,
  19669. + .active_low = 1,
  19670. + }
  19671. +};
  19672. +
  19673. +static struct rtl8366_initval tew673gru_rtl8366s_initvals[] = {
  19674. + { .reg = 0x06, .val = 0x0108 },
  19675. +};
  19676. +
  19677. +static struct rtl8366_platform_data tew673gru_rtl8366s_data = {
  19678. + .gpio_sda = TEW673GRU_GPIO_RTL8366_SDA,
  19679. + .gpio_sck = TEW673GRU_GPIO_RTL8366_SCK,
  19680. + .num_initvals = ARRAY_SIZE(tew673gru_rtl8366s_initvals),
  19681. + .initvals = tew673gru_rtl8366s_initvals,
  19682. +};
  19683. +
  19684. +static struct platform_device tew673gru_rtl8366s_device = {
  19685. + .name = RTL8366S_DRIVER_NAME,
  19686. + .id = -1,
  19687. + .dev = {
  19688. + .platform_data = &tew673gru_rtl8366s_data,
  19689. + }
  19690. +};
  19691. +
  19692. +static struct spi_board_info tew673gru_spi_info[] = {
  19693. + {
  19694. + .bus_num = 1,
  19695. + .chip_select = 0,
  19696. + .max_speed_hz = 400000,
  19697. + .modalias = "spidev",
  19698. + .mode = SPI_MODE_2,
  19699. + .controller_data = (void *) TEW673GRU_GPIO_LCD_CS,
  19700. + },
  19701. +};
  19702. +
  19703. +static struct spi_gpio_platform_data tew673gru_spi_data = {
  19704. + .sck = TEW673GRU_GPIO_LCD_SCK,
  19705. + .miso = TEW673GRU_GPIO_LCD_MISO,
  19706. + .mosi = TEW673GRU_GPIO_LCD_MOSI,
  19707. + .num_chipselect = 1,
  19708. +};
  19709. +
  19710. +static struct platform_device tew673gru_spi_device = {
  19711. + .name = "spi_gpio",
  19712. + .id = 1,
  19713. + .dev = {
  19714. + .platform_data = &tew673gru_spi_data,
  19715. + },
  19716. +};
  19717. +
  19718. +static bool __init tew673gru_is_caldata_valid(u8 *p)
  19719. +{
  19720. + u16 *magic0, *magic1;
  19721. +
  19722. + magic0 = (u16 *)(p + TEW673GRU_CAL0_OFFSET);
  19723. + magic1 = (u16 *)(p + TEW673GRU_CAL1_OFFSET);
  19724. +
  19725. + return (*magic0 == 0xa55a && *magic1 == 0xa55a);
  19726. +}
  19727. +
  19728. +static void __init tew673gru_wlan_init(void)
  19729. +{
  19730. + u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
  19731. + u8 *caldata;
  19732. +
  19733. + caldata = (u8 *) KSEG1ADDR(TEW673GRU_CAL_LOCATION_0);
  19734. + if (!tew673gru_is_caldata_valid(caldata)) {
  19735. + caldata = (u8 *)KSEG1ADDR(TEW673GRU_CAL_LOCATION_1);
  19736. + if (!tew673gru_is_caldata_valid(caldata)) {
  19737. + pr_err("no calibration data found\n");
  19738. + return;
  19739. + }
  19740. + }
  19741. +
  19742. + ath79_parse_ascii_mac(caldata + TEW673GRU_MAC0_OFFSET, mac1);
  19743. + ath79_parse_ascii_mac(caldata + TEW673GRU_MAC1_OFFSET, mac2);
  19744. +
  19745. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2);
  19746. + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3);
  19747. +
  19748. + ap9x_pci_setup_wmac_led_pin(0, 5);
  19749. + ap9x_pci_setup_wmac_led_pin(1, 5);
  19750. +
  19751. + ap94_pci_init(caldata + TEW673GRU_CAL0_OFFSET, mac1,
  19752. + caldata + TEW673GRU_CAL1_OFFSET, mac2);
  19753. +}
  19754. +
  19755. +static void __init tew673gru_setup(void)
  19756. +{
  19757. + tew673gru_wlan_init();
  19758. +
  19759. + ath79_register_mdio(0, 0x0);
  19760. +
  19761. + ath79_eth0_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev;
  19762. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  19763. + ath79_eth0_data.speed = SPEED_1000;
  19764. + ath79_eth0_data.duplex = DUPLEX_FULL;
  19765. + ath79_eth0_pll_data.pll_1000 = 0x11110000;
  19766. +
  19767. + ath79_eth1_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev;
  19768. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  19769. + ath79_eth1_data.phy_mask = 0x10;
  19770. + ath79_eth1_pll_data.pll_1000 = 0x11110000;
  19771. +
  19772. + ath79_register_eth(0);
  19773. + ath79_register_eth(1);
  19774. +
  19775. + ath79_register_m25p80(NULL);
  19776. +
  19777. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew673gru_leds_gpio),
  19778. + tew673gru_leds_gpio);
  19779. +
  19780. + ath79_register_gpio_keys_polled(-1, TEW673GRU_KEYS_POLL_INTERVAL,
  19781. + ARRAY_SIZE(tew673gru_gpio_keys),
  19782. + tew673gru_gpio_keys);
  19783. +
  19784. + ath79_register_usb();
  19785. +
  19786. + platform_device_register(&tew673gru_rtl8366s_device);
  19787. +
  19788. + spi_register_board_info(tew673gru_spi_info,
  19789. + ARRAY_SIZE(tew673gru_spi_info));
  19790. + platform_device_register(&tew673gru_spi_device);
  19791. +}
  19792. +
  19793. +MIPS_MACHINE(ATH79_MACH_TEW_673GRU, "TEW-673GRU", "TRENDnet TEW-673GRU",
  19794. + tew673gru_setup);
  19795. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tew-712br.c linux-4.1.43/arch/mips/ath79/mach-tew-712br.c
  19796. --- linux-4.1.43.orig/arch/mips/ath79/mach-tew-712br.c 1970-01-01 01:00:00.000000000 +0100
  19797. +++ linux-4.1.43/arch/mips/ath79/mach-tew-712br.c 2017-08-06 20:02:15.000000000 +0200
  19798. @@ -0,0 +1,153 @@
  19799. +/*
  19800. + * TRENDnet TEW-712BR board support
  19801. + *
  19802. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  19803. + *
  19804. + * This program is free software; you can redistribute it and/or modify it
  19805. + * under the terms of the GNU General Public License version 2 as published
  19806. + * by the Free Software Foundation.
  19807. + */
  19808. +
  19809. +#include <linux/gpio.h>
  19810. +
  19811. +#include <asm/mach-ath79/ath79.h>
  19812. +#include <asm/mach-ath79/ar71xx_regs.h>
  19813. +
  19814. +#include "common.h"
  19815. +#include "dev-eth.h"
  19816. +#include "dev-gpio-buttons.h"
  19817. +#include "dev-leds-gpio.h"
  19818. +#include "dev-m25p80.h"
  19819. +#include "dev-wmac.h"
  19820. +#include "machtypes.h"
  19821. +
  19822. +#define TEW_712BR_GPIO_BTN_WPS 11
  19823. +#define TEW_712BR_GPIO_BTN_RESET 12
  19824. +
  19825. +#define TEW_712BR_GPIO_LED_LAN1 13
  19826. +#define TEW_712BR_GPIO_LED_LAN2 14
  19827. +#define TEW_712BR_GPIO_LED_LAN3 15
  19828. +#define TEW_712BR_GPIO_LED_LAN4 16
  19829. +#define TEW_712BR_GPIO_LED_POWER_GREEN 20
  19830. +#define TEW_712BR_GPIO_LED_POWER_ORANGE 27
  19831. +#define TEW_712BR_GPIO_LED_WAN_GREEN 17
  19832. +#define TEW_712BR_GPIO_LED_WAN_ORANGE 23
  19833. +#define TEW_712BR_GPIO_LED_WLAN 0
  19834. +#define TEW_712BR_GPIO_LED_WPS 26
  19835. +
  19836. +#define TEW_712BR_GPIO_WAN_LED_ENABLE 1
  19837. +
  19838. +#define TEW_712BR_KEYS_POLL_INTERVAL 20 /* msecs */
  19839. +#define TEW_712BR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_712BR_KEYS_POLL_INTERVAL)
  19840. +
  19841. +#define TEW_712BR_ART_ADDRESS 0x1f010000
  19842. +#define TEW_712BR_CALDATA_OFFSET 0x1000
  19843. +
  19844. +#define TEW_712BR_MAC_PART_ADDRESS 0x1f020000
  19845. +#define TEW_712BR_LAN_MAC_OFFSET 0x04
  19846. +#define TEW_712BR_WAN_MAC_OFFSET 0x16
  19847. +
  19848. +static struct gpio_led tew_712br_leds_gpio[] __initdata = {
  19849. + {
  19850. + .name = "trendnet:green:lan1",
  19851. + .gpio = TEW_712BR_GPIO_LED_LAN1,
  19852. + .active_low = 0,
  19853. + }, {
  19854. + .name = "trendnet:green:lan2",
  19855. + .gpio = TEW_712BR_GPIO_LED_LAN2,
  19856. + .active_low = 0,
  19857. + }, {
  19858. + .name = "trendnet:green:lan3",
  19859. + .gpio = TEW_712BR_GPIO_LED_LAN3,
  19860. + .active_low = 0,
  19861. + }, {
  19862. + .name = "trendnet:green:lan4",
  19863. + .gpio = TEW_712BR_GPIO_LED_LAN4,
  19864. + .active_low = 0,
  19865. + }, {
  19866. + .name = "trendnet:blue:wps",
  19867. + .gpio = TEW_712BR_GPIO_LED_WPS,
  19868. + .active_low = 1,
  19869. + }, {
  19870. + .name = "trendnet:green:power",
  19871. + .gpio = TEW_712BR_GPIO_LED_POWER_GREEN,
  19872. + .active_low = 0,
  19873. + }, {
  19874. + .name = "trendnet:orange:power",
  19875. + .gpio = TEW_712BR_GPIO_LED_POWER_ORANGE,
  19876. + .active_low = 0,
  19877. + }, {
  19878. + .name = "trendnet:green:wan",
  19879. + .gpio = TEW_712BR_GPIO_LED_WAN_GREEN,
  19880. + .active_low = 1,
  19881. + }, {
  19882. + .name = "trendnet:orange:wan",
  19883. + .gpio = TEW_712BR_GPIO_LED_WAN_ORANGE,
  19884. + .active_low = 0,
  19885. + }, {
  19886. + .name = "trendnet:green:wlan",
  19887. + .gpio = TEW_712BR_GPIO_LED_WLAN,
  19888. + .active_low = 0,
  19889. + },
  19890. +};
  19891. +
  19892. +static struct gpio_keys_button tew_712br_gpio_keys[] __initdata = {
  19893. + {
  19894. + .desc = "Reset button",
  19895. + .type = EV_KEY,
  19896. + .code = KEY_RESTART,
  19897. + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL,
  19898. + .gpio = TEW_712BR_GPIO_BTN_RESET,
  19899. + .active_low = 1,
  19900. + }, {
  19901. + .desc = "WPS button",
  19902. + .type = EV_KEY,
  19903. + .code = KEY_WPS_BUTTON,
  19904. + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL,
  19905. + .gpio = TEW_712BR_GPIO_BTN_WPS,
  19906. + .active_low = 1,
  19907. + }
  19908. +};
  19909. +
  19910. +static void __init tew_712br_setup(void)
  19911. +{
  19912. + u8 *art = (u8 *) KSEG1ADDR(TEW_712BR_ART_ADDRESS);
  19913. + u8 *mac = (u8 *) KSEG1ADDR(TEW_712BR_MAC_PART_ADDRESS);
  19914. + u8 lan_mac[ETH_ALEN];
  19915. + u8 wan_mac[ETH_ALEN];
  19916. +
  19917. + ath79_setup_ar933x_phy4_switch(false, false);
  19918. +
  19919. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  19920. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  19921. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  19922. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  19923. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  19924. +
  19925. + gpio_request_one(TEW_712BR_GPIO_WAN_LED_ENABLE,
  19926. + GPIOF_OUT_INIT_LOW, "WAN LED enable");
  19927. +
  19928. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_712br_leds_gpio),
  19929. + tew_712br_leds_gpio);
  19930. +
  19931. + ath79_register_gpio_keys_polled(1, TEW_712BR_KEYS_POLL_INTERVAL,
  19932. + ARRAY_SIZE(tew_712br_gpio_keys),
  19933. + tew_712br_gpio_keys);
  19934. +
  19935. + ath79_register_m25p80(NULL);
  19936. +
  19937. + ath79_parse_ascii_mac(mac + TEW_712BR_LAN_MAC_OFFSET, lan_mac);
  19938. + ath79_parse_ascii_mac(mac + TEW_712BR_WAN_MAC_OFFSET, wan_mac);
  19939. +
  19940. + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
  19941. + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
  19942. +
  19943. + ath79_register_mdio(0, 0x0);
  19944. + ath79_register_eth(1);
  19945. + ath79_register_eth(0);
  19946. +
  19947. + ath79_register_wmac(art + TEW_712BR_CALDATA_OFFSET, wan_mac);
  19948. +}
  19949. +
  19950. +MIPS_MACHINE(ATH79_MACH_TEW_712BR, "TEW-712BR",
  19951. + "TRENDnet TEW-712BR", tew_712br_setup);
  19952. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tew-732br.c linux-4.1.43/arch/mips/ath79/mach-tew-732br.c
  19953. --- linux-4.1.43.orig/arch/mips/ath79/mach-tew-732br.c 1970-01-01 01:00:00.000000000 +0100
  19954. +++ linux-4.1.43/arch/mips/ath79/mach-tew-732br.c 2017-08-06 20:02:15.000000000 +0200
  19955. @@ -0,0 +1,127 @@
  19956. +/*
  19957. + * TRENDnet TEW-732BR board support
  19958. + *
  19959. + * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  19960. + *
  19961. + * This program is free software; you can redistribute it and/or modify it
  19962. + * under the terms of the GNU General Public License version 2 as published
  19963. + * by the Free Software Foundation.
  19964. + */
  19965. +
  19966. +#include <linux/gpio.h>
  19967. +#include <linux/platform_device.h>
  19968. +
  19969. +#include <asm/mach-ath79/ath79.h>
  19970. +#include <asm/mach-ath79/ar71xx_regs.h>
  19971. +
  19972. +#include "common.h"
  19973. +#include "dev-eth.h"
  19974. +#include "dev-gpio-buttons.h"
  19975. +#include "dev-leds-gpio.h"
  19976. +#include "dev-m25p80.h"
  19977. +#include "dev-wmac.h"
  19978. +#include "machtypes.h"
  19979. +
  19980. +#define TEW_732BR_GPIO_BTN_WPS 16
  19981. +#define TEW_732BR_GPIO_BTN_RESET 17
  19982. +
  19983. +#define TEW_732BR_GPIO_LED_POWER_GREEN 4
  19984. +#define TEW_732BR_GPIO_LED_POWER_AMBER 14
  19985. +#define TEW_732BR_GPIO_LED_PLANET_GREEN 12
  19986. +#define TEW_732BR_GPIO_LED_PLANET_AMBER 22
  19987. +
  19988. +#define TEW_732BR_KEYS_POLL_INTERVAL 20 /* msecs */
  19989. +#define TEW_732BR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_732BR_KEYS_POLL_INTERVAL)
  19990. +
  19991. +#define TEW_732BR_ART_ADDRESS 0x1fff0000
  19992. +#define TEW_732BR_CALDATA_OFFSET 0x1000
  19993. +#define TEW_732BR_LAN_MAC_OFFSET 0xffa0
  19994. +#define TEW_732BR_WAN_MAC_OFFSET 0xffb4
  19995. +
  19996. +static struct gpio_led tew_732br_leds_gpio[] __initdata = {
  19997. + {
  19998. + .name = "trendnet:green:power",
  19999. + .gpio = TEW_732BR_GPIO_LED_POWER_GREEN,
  20000. + .active_low = 0,
  20001. + },
  20002. + {
  20003. + .name = "trendnet:amber:power",
  20004. + .gpio = TEW_732BR_GPIO_LED_POWER_AMBER,
  20005. + .active_low = 0,
  20006. + },
  20007. + {
  20008. + .name = "trendnet:green:wan",
  20009. + .gpio = TEW_732BR_GPIO_LED_PLANET_GREEN,
  20010. + .active_low = 1,
  20011. + },
  20012. + {
  20013. + .name = "trendnet:amber:wan",
  20014. + .gpio = TEW_732BR_GPIO_LED_PLANET_AMBER,
  20015. + .active_low = 0,
  20016. + },
  20017. +};
  20018. +
  20019. +static struct gpio_keys_button tew_732br_gpio_keys[] __initdata = {
  20020. + {
  20021. + .desc = "Reset button",
  20022. + .type = EV_KEY,
  20023. + .code = KEY_RESTART,
  20024. + .debounce_interval = TEW_732BR_KEYS_DEBOUNCE_INTERVAL,
  20025. + .gpio = TEW_732BR_GPIO_BTN_RESET,
  20026. + .active_low = 1,
  20027. + },
  20028. + {
  20029. + .desc = "WPS button",
  20030. + .type = EV_KEY,
  20031. + .code = KEY_WPS_BUTTON,
  20032. + .debounce_interval = TEW_732BR_KEYS_DEBOUNCE_INTERVAL,
  20033. + .gpio = TEW_732BR_GPIO_BTN_WPS,
  20034. + .active_low = 1,
  20035. + },
  20036. +};
  20037. +
  20038. +static void __init tew_732br_setup(void)
  20039. +{
  20040. + u8 *art = (u8 *) KSEG1ADDR(TEW_732BR_ART_ADDRESS);
  20041. + u8 lan_mac[ETH_ALEN];
  20042. + u8 wan_mac[ETH_ALEN];
  20043. +
  20044. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_732br_leds_gpio),
  20045. + tew_732br_leds_gpio);
  20046. +
  20047. + ath79_register_gpio_keys_polled(1, TEW_732BR_KEYS_POLL_INTERVAL,
  20048. + ARRAY_SIZE(tew_732br_gpio_keys),
  20049. + tew_732br_gpio_keys);
  20050. +
  20051. + ath79_register_m25p80(NULL);
  20052. +
  20053. + ath79_parse_ascii_mac(art + TEW_732BR_LAN_MAC_OFFSET, lan_mac);
  20054. + ath79_parse_ascii_mac(art + TEW_732BR_WAN_MAC_OFFSET, wan_mac);
  20055. +
  20056. + ath79_register_wmac(art + TEW_732BR_CALDATA_OFFSET, lan_mac);
  20057. +
  20058. + ath79_register_mdio(1, 0x0);
  20059. +
  20060. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  20061. +
  20062. + /* LAN: GMAC1 is connected to the internal switch */
  20063. + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
  20064. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  20065. +
  20066. + ath79_register_eth(1);
  20067. +
  20068. + /* WAN: GMAC0 is connected to the PHY4 of the internal switch */
  20069. + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
  20070. +
  20071. + ath79_switch_data.phy4_mii_en = 1;
  20072. + ath79_switch_data.phy_poll_mask = BIT(4);
  20073. +
  20074. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  20075. + ath79_eth0_data.phy_mask = BIT(4);
  20076. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  20077. +
  20078. + ath79_register_eth(0);
  20079. +}
  20080. +
  20081. +MIPS_MACHINE(ATH79_MACH_TEW_732BR, "TEW-732BR", "TRENDnet TEW-732BR",
  20082. + tew_732br_setup);
  20083. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr11u.c linux-4.1.43/arch/mips/ath79/mach-tl-mr11u.c
  20084. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr11u.c 1970-01-01 01:00:00.000000000 +0100
  20085. +++ linux-4.1.43/arch/mips/ath79/mach-tl-mr11u.c 2017-08-06 20:02:15.000000000 +0200
  20086. @@ -0,0 +1,183 @@
  20087. +/*
  20088. + * TP-LINK TL-MR11U/TL-MR3040 board support
  20089. + *
  20090. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  20091. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  20092. + *
  20093. + * This program is free software; you can redistribute it and/or modify it
  20094. + * under the terms of the GNU General Public License version 2 as published
  20095. + * by the Free Software Foundation.
  20096. + */
  20097. +
  20098. +#include <linux/gpio.h>
  20099. +
  20100. +#include <asm/mach-ath79/ath79.h>
  20101. +#include <asm/mach-ath79/ar71xx_regs.h>
  20102. +
  20103. +#include "common.h"
  20104. +#include "dev-eth.h"
  20105. +#include "dev-gpio-buttons.h"
  20106. +#include "dev-leds-gpio.h"
  20107. +#include "dev-m25p80.h"
  20108. +#include "dev-usb.h"
  20109. +#include "dev-wmac.h"
  20110. +#include "machtypes.h"
  20111. +
  20112. +#define TL_MR11U_GPIO_LED_3G 27
  20113. +#define TL_MR11U_GPIO_LED_WLAN 26
  20114. +#define TL_MR11U_GPIO_LED_LAN 17
  20115. +
  20116. +#define TL_MR11U_GPIO_BTN_WPS 20
  20117. +#define TL_MR11U_GPIO_BTN_RESET 11
  20118. +
  20119. +#define TL_MR11U_GPIO_USB_POWER 8
  20120. +#define TL_MR3040_GPIO_USB_POWER 18
  20121. +
  20122. +#define TL_MR3040_V2_GPIO_BTN_SW1 19
  20123. +#define TL_MR3040_V2_GPIO_BTN_SW2 20
  20124. +
  20125. +#define TL_MR11U_KEYS_POLL_INTERVAL 20 /* msecs */
  20126. +#define TL_MR11U_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR11U_KEYS_POLL_INTERVAL)
  20127. +
  20128. +static const char *tl_mr11u_part_probes[] = {
  20129. + "tp-link",
  20130. + NULL,
  20131. +};
  20132. +
  20133. +static struct flash_platform_data tl_mr11u_flash_data = {
  20134. + .part_probes = tl_mr11u_part_probes,
  20135. +};
  20136. +
  20137. +static struct gpio_led tl_mr11u_leds_gpio[] __initdata = {
  20138. + {
  20139. + .name = "tp-link:green:3g",
  20140. + .gpio = TL_MR11U_GPIO_LED_3G,
  20141. + .active_low = 1,
  20142. + },
  20143. + {
  20144. + .name = "tp-link:green:wlan",
  20145. + .gpio = TL_MR11U_GPIO_LED_WLAN,
  20146. + .active_low = 1,
  20147. + },
  20148. + {
  20149. + .name = "tp-link:green:lan",
  20150. + .gpio = TL_MR11U_GPIO_LED_LAN,
  20151. + .active_low = 1,
  20152. + }
  20153. +};
  20154. +
  20155. +static struct gpio_keys_button tl_mr11u_gpio_keys[] __initdata = {
  20156. + {
  20157. + .desc = "reset",
  20158. + .type = EV_KEY,
  20159. + .code = KEY_RESTART,
  20160. + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL,
  20161. + .gpio = TL_MR11U_GPIO_BTN_RESET,
  20162. + .active_low = 0,
  20163. + },
  20164. + {
  20165. + .desc = "wps",
  20166. + .type = EV_KEY,
  20167. + .code = KEY_WPS_BUTTON,
  20168. + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL,
  20169. + .gpio = TL_MR11U_GPIO_BTN_WPS,
  20170. + .active_low = 0,
  20171. + },
  20172. +};
  20173. +
  20174. +static struct gpio_keys_button tl_mr3040_v2_gpio_keys[] __initdata = {
  20175. + {
  20176. + .desc = "reset",
  20177. + .type = EV_KEY,
  20178. + .code = KEY_RESTART,
  20179. + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL,
  20180. + .gpio = TL_MR11U_GPIO_BTN_RESET,
  20181. + .active_low = 0,
  20182. + },
  20183. + {
  20184. + .desc = "sw1",
  20185. + .type = EV_SW,
  20186. + .code = BTN_0,
  20187. + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL,
  20188. + .gpio = TL_MR3040_V2_GPIO_BTN_SW1,
  20189. + .active_low = 0,
  20190. + },
  20191. + {
  20192. + .desc = "sw2",
  20193. + .type = EV_SW,
  20194. + .code = BTN_1,
  20195. + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL,
  20196. + .gpio = TL_MR3040_V2_GPIO_BTN_SW2,
  20197. + .active_low = 0,
  20198. + }
  20199. +};
  20200. +
  20201. +static void __init common_setup(void)
  20202. +{
  20203. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  20204. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  20205. +
  20206. + /* Disable hardware control LAN1 and LAN2 LEDs, enabling GPIO14 and GPIO15 */
  20207. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  20208. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN);
  20209. +
  20210. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  20211. + ath79_setup_ar933x_phy4_switch(false, false);
  20212. +
  20213. + ath79_register_m25p80(&tl_mr11u_flash_data);
  20214. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr11u_leds_gpio),
  20215. + tl_mr11u_leds_gpio);
  20216. +
  20217. + ath79_register_usb();
  20218. +
  20219. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  20220. +
  20221. + ath79_register_mdio(0, 0x0);
  20222. + ath79_register_eth(0);
  20223. +
  20224. + ath79_register_wmac(ee, mac);
  20225. +}
  20226. +
  20227. +static void __init tl_mr11u_setup(void)
  20228. +{
  20229. + common_setup();
  20230. +
  20231. + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL,
  20232. + ARRAY_SIZE(tl_mr11u_gpio_keys),
  20233. + tl_mr11u_gpio_keys);
  20234. + gpio_request_one(TL_MR11U_GPIO_USB_POWER,
  20235. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  20236. + "USB power");
  20237. +}
  20238. +
  20239. +MIPS_MACHINE(ATH79_MACH_TL_MR11U, "TL-MR11U", "TP-LINK TL-MR11U",
  20240. + tl_mr11u_setup);
  20241. +
  20242. +static void __init tl_mr3040_setup(void)
  20243. +{
  20244. + common_setup();
  20245. +
  20246. + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL,
  20247. + 1, tl_mr11u_gpio_keys);
  20248. + gpio_request_one(TL_MR3040_GPIO_USB_POWER,
  20249. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  20250. + "USB power");
  20251. +}
  20252. +
  20253. +MIPS_MACHINE(ATH79_MACH_TL_MR3040, "TL-MR3040", "TP-LINK TL-MR3040",
  20254. + tl_mr3040_setup);
  20255. +
  20256. +static void __init tl_mr3040_v2_setup(void)
  20257. +{
  20258. + common_setup();
  20259. +
  20260. + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL,
  20261. + ARRAY_SIZE(tl_mr3040_v2_gpio_keys),
  20262. + tl_mr3040_v2_gpio_keys);
  20263. + gpio_request_one(TL_MR3040_GPIO_USB_POWER,
  20264. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  20265. + "USB power");
  20266. +}
  20267. +
  20268. +MIPS_MACHINE(ATH79_MACH_TL_MR3040_V2, "TL-MR3040-v2", "TP-LINK TL-MR3040 v2",
  20269. + tl_mr3040_v2_setup);
  20270. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr13u.c linux-4.1.43/arch/mips/ath79/mach-tl-mr13u.c
  20271. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr13u.c 1970-01-01 01:00:00.000000000 +0100
  20272. +++ linux-4.1.43/arch/mips/ath79/mach-tl-mr13u.c 2017-08-06 20:02:15.000000000 +0200
  20273. @@ -0,0 +1,107 @@
  20274. +/*
  20275. + * TP-LINK TL-MR13U board support
  20276. + *
  20277. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  20278. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  20279. + *
  20280. + * This program is free software; you can redistribute it and/or modify it
  20281. + * under the terms of the GNU General Public License version 2 as published
  20282. + * by the Free Software Foundation.
  20283. + */
  20284. +
  20285. +#include <linux/gpio.h>
  20286. +
  20287. +#include <asm/mach-ath79/ath79.h>
  20288. +
  20289. +#include "dev-eth.h"
  20290. +#include "dev-gpio-buttons.h"
  20291. +#include "dev-leds-gpio.h"
  20292. +#include "dev-m25p80.h"
  20293. +#include "dev-usb.h"
  20294. +#include "dev-wmac.h"
  20295. +#include "machtypes.h"
  20296. +
  20297. +#define TL_MR13U_GPIO_LED_SYSTEM 27
  20298. +
  20299. +#define TL_MR13U_GPIO_BTN_RESET 11
  20300. +#define TL_MR13U_GPIO_BTN_SW1 6
  20301. +#define TL_MR13U_GPIO_BTN_SW2 7
  20302. +
  20303. +#define TL_MR13U_GPIO_USB_POWER 18
  20304. +
  20305. +#define TL_MR13U_KEYS_POLL_INTERVAL 20 /* msecs */
  20306. +#define TL_MR13U_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR13U_KEYS_POLL_INTERVAL)
  20307. +
  20308. +static const char *tl_mr13u_part_probes[] = {
  20309. + "tp-link",
  20310. + NULL,
  20311. +};
  20312. +
  20313. +static struct flash_platform_data tl_mr13u_flash_data = {
  20314. + .part_probes = tl_mr13u_part_probes,
  20315. +};
  20316. +
  20317. +static struct gpio_led tl_mr13u_leds_gpio[] __initdata = {
  20318. + {
  20319. + .name = "tp-link:blue:system",
  20320. + .gpio = TL_MR13U_GPIO_LED_SYSTEM,
  20321. + .active_low = 0,
  20322. + },
  20323. +};
  20324. +
  20325. +static struct gpio_keys_button tl_mr13u_gpio_keys[] __initdata = {
  20326. + {
  20327. + .desc = "reset",
  20328. + .type = EV_KEY,
  20329. + .code = KEY_RESTART,
  20330. + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL,
  20331. + .gpio = TL_MR13U_GPIO_BTN_RESET,
  20332. + .active_low = 0,
  20333. + },
  20334. + {
  20335. + .desc = "sw1",
  20336. + .type = EV_KEY,
  20337. + .code = BTN_0,
  20338. + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL,
  20339. + .gpio = TL_MR13U_GPIO_BTN_SW1,
  20340. + .active_low = 0,
  20341. + },
  20342. + {
  20343. + .desc = "sw2",
  20344. + .type = EV_KEY,
  20345. + .code = BTN_1,
  20346. + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL,
  20347. + .gpio = TL_MR13U_GPIO_BTN_SW2,
  20348. + .active_low = 0,
  20349. + },
  20350. +};
  20351. +
  20352. +static void __init tl_mr13u_setup(void)
  20353. +{
  20354. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  20355. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  20356. +
  20357. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  20358. + ath79_setup_ar933x_phy4_switch(false, false);
  20359. +
  20360. + ath79_register_m25p80(&tl_mr13u_flash_data);
  20361. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr13u_leds_gpio),
  20362. + tl_mr13u_leds_gpio);
  20363. + ath79_register_gpio_keys_polled(-1, TL_MR13U_KEYS_POLL_INTERVAL,
  20364. + ARRAY_SIZE(tl_mr13u_gpio_keys),
  20365. + tl_mr13u_gpio_keys);
  20366. +
  20367. + gpio_request_one(TL_MR13U_GPIO_USB_POWER,
  20368. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  20369. + "USB power");
  20370. + ath79_register_usb();
  20371. +
  20372. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  20373. +
  20374. + ath79_register_mdio(0, 0x0);
  20375. + ath79_register_eth(0);
  20376. + ath79_register_wmac(ee, mac);
  20377. +}
  20378. +
  20379. +MIPS_MACHINE(ATH79_MACH_TL_MR13U, "TL-MR13U", "TP-LINK TL-MR13U v1",
  20380. + tl_mr13u_setup);
  20381. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr3020.c linux-4.1.43/arch/mips/ath79/mach-tl-mr3020.c
  20382. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr3020.c 1970-01-01 01:00:00.000000000 +0100
  20383. +++ linux-4.1.43/arch/mips/ath79/mach-tl-mr3020.c 2017-08-06 20:02:15.000000000 +0200
  20384. @@ -0,0 +1,126 @@
  20385. +/*
  20386. + * TP-LINK TL-MR3020 board support
  20387. + *
  20388. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  20389. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  20390. + *
  20391. + * This program is free software; you can redistribute it and/or modify it
  20392. + * under the terms of the GNU General Public License version 2 as published
  20393. + * by the Free Software Foundation.
  20394. + */
  20395. +
  20396. +#include <linux/gpio.h>
  20397. +
  20398. +#include <asm/mach-ath79/ath79.h>
  20399. +#include <asm/mach-ath79/ar71xx_regs.h>
  20400. +
  20401. +#include "dev-eth.h"
  20402. +#include "dev-gpio-buttons.h"
  20403. +#include "dev-leds-gpio.h"
  20404. +#include "dev-m25p80.h"
  20405. +#include "dev-usb.h"
  20406. +#include "dev-wmac.h"
  20407. +#include "machtypes.h"
  20408. +
  20409. +#define TL_MR3020_GPIO_LED_3G 27
  20410. +#define TL_MR3020_GPIO_LED_WLAN 0
  20411. +#define TL_MR3020_GPIO_LED_LAN 17
  20412. +#define TL_MR3020_GPIO_LED_WPS 26
  20413. +
  20414. +#define TL_MR3020_GPIO_BTN_WPS 11
  20415. +#define TL_MR3020_GPIO_BTN_SW1 18
  20416. +#define TL_MR3020_GPIO_BTN_SW2 20
  20417. +
  20418. +#define TL_MR3020_GPIO_USB_POWER 8
  20419. +
  20420. +#define TL_MR3020_KEYS_POLL_INTERVAL 20 /* msecs */
  20421. +#define TL_MR3020_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3020_KEYS_POLL_INTERVAL)
  20422. +
  20423. +static const char *tl_mr3020_part_probes[] = {
  20424. + "tp-link",
  20425. + NULL,
  20426. +};
  20427. +
  20428. +static struct flash_platform_data tl_mr3020_flash_data = {
  20429. + .part_probes = tl_mr3020_part_probes,
  20430. +};
  20431. +
  20432. +static struct gpio_led tl_mr3020_leds_gpio[] __initdata = {
  20433. + {
  20434. + .name = "tp-link:green:3g",
  20435. + .gpio = TL_MR3020_GPIO_LED_3G,
  20436. + .active_low = 1,
  20437. + },
  20438. + {
  20439. + .name = "tp-link:green:wlan",
  20440. + .gpio = TL_MR3020_GPIO_LED_WLAN,
  20441. + .active_low = 0,
  20442. + },
  20443. + {
  20444. + .name = "tp-link:green:lan",
  20445. + .gpio = TL_MR3020_GPIO_LED_LAN,
  20446. + .active_low = 1,
  20447. + },
  20448. + {
  20449. + .name = "tp-link:green:wps",
  20450. + .gpio = TL_MR3020_GPIO_LED_WPS,
  20451. + .active_low = 1,
  20452. + },
  20453. +};
  20454. +
  20455. +static struct gpio_keys_button tl_mr3020_gpio_keys[] __initdata = {
  20456. + {
  20457. + .desc = "wps",
  20458. + .type = EV_KEY,
  20459. + .code = KEY_WPS_BUTTON,
  20460. + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL,
  20461. + .gpio = TL_MR3020_GPIO_BTN_WPS,
  20462. + .active_low = 0,
  20463. + },
  20464. + {
  20465. + .desc = "sw1",
  20466. + .type = EV_KEY,
  20467. + .code = BTN_0,
  20468. + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL,
  20469. + .gpio = TL_MR3020_GPIO_BTN_SW1,
  20470. + .active_low = 0,
  20471. + },
  20472. + {
  20473. + .desc = "sw2",
  20474. + .type = EV_KEY,
  20475. + .code = BTN_1,
  20476. + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL,
  20477. + .gpio = TL_MR3020_GPIO_BTN_SW2,
  20478. + .active_low = 0,
  20479. + }
  20480. +};
  20481. +
  20482. +static void __init tl_mr3020_setup(void)
  20483. +{
  20484. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  20485. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  20486. +
  20487. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  20488. + ath79_setup_ar933x_phy4_switch(false, false);
  20489. +
  20490. + ath79_register_m25p80(&tl_mr3020_flash_data);
  20491. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio),
  20492. + tl_mr3020_leds_gpio);
  20493. + ath79_register_gpio_keys_polled(-1, TL_MR3020_KEYS_POLL_INTERVAL,
  20494. + ARRAY_SIZE(tl_mr3020_gpio_keys),
  20495. + tl_mr3020_gpio_keys);
  20496. +
  20497. + gpio_request_one(TL_MR3020_GPIO_USB_POWER,
  20498. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  20499. + "USB power");
  20500. + ath79_register_usb();
  20501. +
  20502. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  20503. +
  20504. + ath79_register_mdio(0, 0x0);
  20505. + ath79_register_eth(0);
  20506. + ath79_register_wmac(ee, mac);
  20507. +}
  20508. +
  20509. +MIPS_MACHINE(ATH79_MACH_TL_MR3020, "TL-MR3020", "TP-LINK TL-MR3020",
  20510. + tl_mr3020_setup);
  20511. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr3x20.c linux-4.1.43/arch/mips/ath79/mach-tl-mr3x20.c
  20512. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-mr3x20.c 1970-01-01 01:00:00.000000000 +0100
  20513. +++ linux-4.1.43/arch/mips/ath79/mach-tl-mr3x20.c 2017-08-06 20:02:15.000000000 +0200
  20514. @@ -0,0 +1,147 @@
  20515. +/*
  20516. + * TP-LINK TL-MR3220/3420 board support
  20517. + *
  20518. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  20519. + *
  20520. + * This program is free software; you can redistribute it and/or modify it
  20521. + * under the terms of the GNU General Public License version 2 as published
  20522. + * by the Free Software Foundation.
  20523. + */
  20524. +
  20525. +#include <linux/gpio.h>
  20526. +
  20527. +#include <asm/mach-ath79/ath79.h>
  20528. +
  20529. +#include "dev-eth.h"
  20530. +#include "dev-ap9x-pci.h"
  20531. +#include "dev-gpio-buttons.h"
  20532. +#include "dev-leds-gpio.h"
  20533. +#include "dev-m25p80.h"
  20534. +#include "dev-usb.h"
  20535. +#include "machtypes.h"
  20536. +
  20537. +#define TL_MR3X20_GPIO_LED_QSS 0
  20538. +#define TL_MR3X20_GPIO_LED_SYSTEM 1
  20539. +#define TL_MR3X20_GPIO_LED_3G 8
  20540. +
  20541. +#define TL_MR3X20_GPIO_BTN_RESET 11
  20542. +#define TL_MR3X20_GPIO_BTN_QSS 12
  20543. +
  20544. +#define TL_MR3X20_GPIO_USB_POWER 6
  20545. +
  20546. +#define TL_MR3X20_KEYS_POLL_INTERVAL 20 /* msecs */
  20547. +#define TL_MR3X20_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3X20_KEYS_POLL_INTERVAL)
  20548. +
  20549. +static const char *tl_mr3x20_part_probes[] = {
  20550. + "tp-link",
  20551. + NULL,
  20552. +};
  20553. +
  20554. +static struct flash_platform_data tl_mr3x20_flash_data = {
  20555. + .part_probes = tl_mr3x20_part_probes,
  20556. +};
  20557. +
  20558. +static struct gpio_led tl_mr3x20_leds_gpio[] __initdata = {
  20559. + {
  20560. + .name = "tp-link:green:system",
  20561. + .gpio = TL_MR3X20_GPIO_LED_SYSTEM,
  20562. + .active_low = 1,
  20563. + }, {
  20564. + .name = "tp-link:green:qss",
  20565. + .gpio = TL_MR3X20_GPIO_LED_QSS,
  20566. + .active_low = 1,
  20567. + }, {
  20568. + .name = "tp-link:green:3g",
  20569. + .gpio = TL_MR3X20_GPIO_LED_3G,
  20570. + .active_low = 1,
  20571. + }
  20572. +};
  20573. +
  20574. +static struct gpio_keys_button tl_mr3x20_gpio_keys[] __initdata = {
  20575. + {
  20576. + .desc = "reset",
  20577. + .type = EV_KEY,
  20578. + .code = KEY_RESTART,
  20579. + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL,
  20580. + .gpio = TL_MR3X20_GPIO_BTN_RESET,
  20581. + .active_low = 1,
  20582. + }, {
  20583. + .desc = "qss",
  20584. + .type = EV_KEY,
  20585. + .code = KEY_WPS_BUTTON,
  20586. + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL,
  20587. + .gpio = TL_MR3X20_GPIO_BTN_QSS,
  20588. + .active_low = 1,
  20589. + }
  20590. +};
  20591. +
  20592. +static void __init tl_ap99_setup(void)
  20593. +{
  20594. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  20595. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  20596. +
  20597. + ath79_register_m25p80(&tl_mr3x20_flash_data);
  20598. +
  20599. + ath79_register_gpio_keys_polled(-1, TL_MR3X20_KEYS_POLL_INTERVAL,
  20600. + ARRAY_SIZE(tl_mr3x20_gpio_keys),
  20601. + tl_mr3x20_gpio_keys);
  20602. +
  20603. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  20604. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  20605. +
  20606. + ath79_register_mdio(0, 0x0);
  20607. +
  20608. + /* LAN ports */
  20609. + ath79_register_eth(1);
  20610. + /* WAN port */
  20611. + ath79_register_eth(0);
  20612. +
  20613. + ap91_pci_init(ee, mac);
  20614. +}
  20615. +
  20616. +static void __init tl_mr3x20_usb_setup(void)
  20617. +{
  20618. + /* enable power for the USB port */
  20619. + gpio_request_one(TL_MR3X20_GPIO_USB_POWER,
  20620. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  20621. + "USB power");
  20622. + ath79_register_usb();
  20623. +}
  20624. +
  20625. +static void __init tl_mr3220_setup(void)
  20626. +{
  20627. + tl_ap99_setup();
  20628. +
  20629. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio),
  20630. + tl_mr3x20_leds_gpio);
  20631. + ap9x_pci_setup_wmac_led_pin(0, 1);
  20632. + tl_mr3x20_usb_setup();
  20633. +}
  20634. +
  20635. +MIPS_MACHINE(ATH79_MACH_TL_MR3220, "TL-MR3220", "TP-LINK TL-MR3220",
  20636. + tl_mr3220_setup);
  20637. +
  20638. +static void __init tl_mr3420_setup(void)
  20639. +{
  20640. + tl_ap99_setup();
  20641. +
  20642. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio),
  20643. + tl_mr3x20_leds_gpio);
  20644. + ap9x_pci_setup_wmac_led_pin(0, 0);
  20645. + tl_mr3x20_usb_setup();
  20646. +}
  20647. +
  20648. +MIPS_MACHINE(ATH79_MACH_TL_MR3420, "TL-MR3420", "TP-LINK TL-MR3420",
  20649. + tl_mr3420_setup);
  20650. +
  20651. +static void __init tl_wr841n_v7_setup(void)
  20652. +{
  20653. + tl_ap99_setup();
  20654. +
  20655. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio) - 1,
  20656. + tl_mr3x20_leds_gpio);
  20657. + ap9x_pci_setup_wmac_led_pin(0, 0);
  20658. +}
  20659. +
  20660. +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V7, "TL-WR841N-v7",
  20661. + "TP-LINK TL-WR841N/ND v7", tl_wr841n_v7_setup);
  20662. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa701nd-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wa701nd-v2.c
  20663. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa701nd-v2.c 1970-01-01 01:00:00.000000000 +0100
  20664. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wa701nd-v2.c 2017-08-06 20:02:15.000000000 +0200
  20665. @@ -0,0 +1,116 @@
  20666. +/*
  20667. + * TP-LINK TL-WA701ND v2 board support
  20668. + *
  20669. + * Copyright (C) 2015 Luigi Tarenga <luigi.tarenga@gmail.com>
  20670. + *
  20671. + * This program is free software; you can redistribute it and/or modify it
  20672. + * under the terms of the GNU General Public License version 2 as published
  20673. + * by the Free Software Foundation.
  20674. + */
  20675. +
  20676. +#include <linux/gpio.h>
  20677. +
  20678. +#include <asm/mach-ath79/ath79.h>
  20679. +
  20680. +#include "dev-eth.h"
  20681. +#include "dev-gpio-buttons.h"
  20682. +#include "dev-leds-gpio.h"
  20683. +#include "dev-m25p80.h"
  20684. +#include "dev-usb.h"
  20685. +#include "dev-wmac.h"
  20686. +#include "machtypes.h"
  20687. +
  20688. +#define TL_WA701NDV2_GPIO_LED_WLAN 0
  20689. +#define TL_WA701NDV2_GPIO_LED_QSS 1
  20690. +#define TL_WA701NDV2_GPIO_LED_LAN 17
  20691. +#define TL_WA701NDV2_GPIO_LED_SYSTEM 27
  20692. +
  20693. +#define TL_WA701NDV2_GPIO_BTN_RESET 11
  20694. +#define TL_WA701NDV2_GPIO_BTN_QSS 26
  20695. +
  20696. +#define TL_WA701NDV2_GPIO_USB_POWER 8
  20697. +
  20698. +#define TL_WA701NDV2_KEYS_POLL_INTERVAL 20 /* msecs */
  20699. +#define TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA701NDV2_KEYS_POLL_INTERVAL)
  20700. +
  20701. +static const char *tl_wa701ndv2_part_probes[] = {
  20702. + "tp-link",
  20703. + NULL,
  20704. +};
  20705. +
  20706. +static struct flash_platform_data tl_wa701ndv2_flash_data = {
  20707. + .part_probes = tl_wa701ndv2_part_probes,
  20708. +};
  20709. +
  20710. +static struct gpio_led tl_wa701ndv2_leds_gpio[] __initdata = {
  20711. + {
  20712. + .name = "tp-link:green:wlan",
  20713. + .gpio = TL_WA701NDV2_GPIO_LED_WLAN,
  20714. + .active_low = 0,
  20715. + }, {
  20716. + .name = "tp-link:green:qss",
  20717. + .gpio = TL_WA701NDV2_GPIO_LED_QSS,
  20718. + .active_low = 0,
  20719. + }, {
  20720. + .name = "tp-link:green:lan",
  20721. + .gpio = TL_WA701NDV2_GPIO_LED_LAN,
  20722. + .active_low = 1,
  20723. + }, {
  20724. + .name = "tp-link:green:system",
  20725. + .gpio = TL_WA701NDV2_GPIO_LED_SYSTEM,
  20726. + .active_low = 1,
  20727. + }
  20728. +};
  20729. +
  20730. +static struct gpio_keys_button tl_wa701ndv2_gpio_keys[] __initdata = {
  20731. + {
  20732. + .desc = "reset",
  20733. + .type = EV_KEY,
  20734. + .code = KEY_RESTART,
  20735. + .debounce_interval = TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL,
  20736. + .gpio = TL_WA701NDV2_GPIO_BTN_RESET,
  20737. + .active_low = 0,
  20738. + } , {
  20739. + .desc = "qss",
  20740. + .type = EV_KEY,
  20741. + .code = KEY_WPS_BUTTON,
  20742. + .debounce_interval = TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL,
  20743. + .gpio = TL_WA701NDV2_GPIO_BTN_QSS,
  20744. + .active_low = 0,
  20745. + }
  20746. +
  20747. +};
  20748. +
  20749. +static void __init tl_wa701ndv2_setup(void)
  20750. +{
  20751. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  20752. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  20753. +
  20754. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  20755. + ath79_setup_ar933x_phy4_switch(false, false);
  20756. +
  20757. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa701ndv2_leds_gpio),
  20758. + tl_wa701ndv2_leds_gpio);
  20759. +
  20760. + ath79_register_gpio_keys_polled(-1, TL_WA701NDV2_KEYS_POLL_INTERVAL,
  20761. + ARRAY_SIZE(tl_wa701ndv2_gpio_keys),
  20762. + tl_wa701ndv2_gpio_keys);
  20763. +
  20764. + gpio_request_one(TL_WA701NDV2_GPIO_USB_POWER,
  20765. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  20766. + "USB power");
  20767. + ath79_register_usb();
  20768. +
  20769. + ath79_register_m25p80(&tl_wa701ndv2_flash_data);
  20770. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  20771. + /* ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); */
  20772. +
  20773. + ath79_register_mdio(0, 0x0);
  20774. + ath79_register_eth(0);
  20775. + ath79_register_eth(1);
  20776. +
  20777. + ath79_register_wmac(ee, mac);
  20778. +}
  20779. +
  20780. +MIPS_MACHINE(ATH79_MACH_TL_WA701ND_V2, "TL-WA701ND-v2",
  20781. + "TP-LINK TL-WA701ND v2", tl_wa701ndv2_setup);
  20782. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa7210n-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wa7210n-v2.c
  20783. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa7210n-v2.c 1970-01-01 01:00:00.000000000 +0100
  20784. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wa7210n-v2.c 2017-08-06 20:02:15.000000000 +0200
  20785. @@ -0,0 +1,125 @@
  20786. +/*
  20787. + * TP-LINK TL-WA7210N v2.1 board support
  20788. + *
  20789. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  20790. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  20791. + * Copyright (C) 2014 Nicolas Braud-Santoni <nicolas@braud-santoni.eu>
  20792. + * Copyright (C) 2014 Alexander List <alex@graz.funkfeuer.at>
  20793. + * Copyright (C) 2015 Hendrik Frenzel <hfrenzel@scunc.net>
  20794. + *
  20795. + * rebased on TL-WA7510Nv1 support,
  20796. + * Copyright (C) 2012 Stefan Helmert <helst_listen@aol.de>
  20797. + *
  20798. + * This program is free software; you can redistribute it and/or modify it
  20799. + * under the terms of the GNU General Public License version 2 as published
  20800. + * by the Free Software Foundation.
  20801. + */
  20802. +
  20803. +#include <linux/mtd/mtd.h>
  20804. +#include <linux/mtd/partitions.h>
  20805. +#include <linux/platform_device.h>
  20806. +#include <linux/gpio.h>
  20807. +
  20808. +#include <asm/mach-ath79/ar71xx_regs.h>
  20809. +#include <asm/mach-ath79/ath79.h>
  20810. +
  20811. +#include "dev-dsa.h"
  20812. +#include "dev-eth.h"
  20813. +#include "dev-gpio-buttons.h"
  20814. +#include "dev-leds-gpio.h"
  20815. +#include "dev-m25p80.h"
  20816. +#include "dev-wmac.h"
  20817. +#include "machtypes.h"
  20818. +#include "pci.h"
  20819. +
  20820. +#include "common.h"
  20821. +
  20822. +#define TL_WA7210N_V2_GPIO_BTN_RESET 11
  20823. +#define TL_WA7210N_V2_KEYS_POLL_INT 20
  20824. +#define TL_WA7210N_V2_KEYS_DEBOUNCE_INT (3 * TL_WA7210N_V2_KEYS_POLL_INT)
  20825. +
  20826. +#define TL_WA7210N_V2_GPIO_LED_LAN 17
  20827. +#define TL_WA7210N_V2_GPIO_LED_SIG1 0
  20828. +#define TL_WA7210N_V2_GPIO_LED_SIG2 1
  20829. +#define TL_WA7210N_V2_GPIO_LED_SIG3 27
  20830. +#define TL_WA7210N_V2_GPIO_LED_SIG4 26
  20831. +
  20832. +#define TL_WA7210N_V2_GPIO_LNA_EN 28
  20833. +
  20834. +static const char *tl_wa7210n_v2_part_probes[] = {
  20835. + "tp-link",
  20836. + NULL,
  20837. +};
  20838. +
  20839. +static struct gpio_keys_button tl_wa7210n_v2_gpio_keys[] __initdata = {
  20840. + {
  20841. + .desc = "reset",
  20842. + .type = EV_KEY,
  20843. + .code = KEY_RESTART,
  20844. + .debounce_interval = TL_WA7210N_V2_KEYS_DEBOUNCE_INT,
  20845. + .gpio = TL_WA7210N_V2_GPIO_BTN_RESET,
  20846. + .active_low = 0,
  20847. + },
  20848. +};
  20849. +
  20850. +static struct gpio_led tl_wa7210n_v2_leds_gpio[] __initdata = {
  20851. + {
  20852. + .name = "tp-link:green:lan",
  20853. + .gpio = TL_WA7210N_V2_GPIO_LED_LAN,
  20854. + .active_low = 1,
  20855. + }, {
  20856. + .name = "tp-link:green:signal1",
  20857. + .gpio = TL_WA7210N_V2_GPIO_LED_SIG1,
  20858. + .active_low = 0,
  20859. + }, {
  20860. + .name = "tp-link:green:signal2",
  20861. + .gpio = TL_WA7210N_V2_GPIO_LED_SIG2,
  20862. + .active_low = 0,
  20863. + }, {
  20864. + .name = "tp-link:green:signal3",
  20865. + .gpio = TL_WA7210N_V2_GPIO_LED_SIG3,
  20866. + .active_low = 1,
  20867. + }, {
  20868. + .name = "tp-link:green:signal4",
  20869. + .gpio = TL_WA7210N_V2_GPIO_LED_SIG4,
  20870. + .active_low = 1,
  20871. + },
  20872. +};
  20873. +
  20874. +static struct flash_platform_data tl_wa7210n_v2_flash_data = {
  20875. + .part_probes = tl_wa7210n_v2_part_probes,
  20876. +};
  20877. +
  20878. +static void __init tl_wa7210n_v2_setup(void)
  20879. +{
  20880. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  20881. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  20882. +
  20883. + ath79_register_gpio_keys_polled(-1, TL_WA7210N_V2_KEYS_POLL_INT,
  20884. + ARRAY_SIZE(tl_wa7210n_v2_gpio_keys),
  20885. + tl_wa7210n_v2_gpio_keys);
  20886. +
  20887. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa7210n_v2_leds_gpio),
  20888. + tl_wa7210n_v2_leds_gpio);
  20889. +
  20890. + ath79_gpio_function_enable(TL_WA7210N_V2_GPIO_LNA_EN);
  20891. +
  20892. + ath79_setup_ar933x_phy4_switch(false, false);
  20893. +
  20894. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
  20895. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  20896. +
  20897. + ath79_register_eth(0);
  20898. + ath79_register_eth(1);
  20899. +
  20900. + ath79_register_mdio(0, 0x0);
  20901. +
  20902. + ath79_register_wmac(ee, mac);
  20903. +
  20904. + ath79_register_m25p80(&tl_wa7210n_v2_flash_data);
  20905. +
  20906. + ath79_register_pci();
  20907. +}
  20908. +
  20909. +MIPS_MACHINE(ATH79_MACH_TL_WA7210N_V2, "TL-WA7210N-v2", "TP-LINK TL-WA7210N v2",
  20910. + tl_wa7210n_v2_setup);
  20911. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa830re-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wa830re-v2.c
  20912. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa830re-v2.c 1970-01-01 01:00:00.000000000 +0100
  20913. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wa830re-v2.c 2017-08-06 20:02:15.000000000 +0200
  20914. @@ -0,0 +1,132 @@
  20915. +/*
  20916. + * TP-LINK TL-WA830RE v2 board support
  20917. + *
  20918. + * Copyright (C) 2014 Fredrik Jonson <fredrik@famjonson.se>
  20919. + *
  20920. + * This program is free software; you can redistribute it and/or modify it
  20921. + * under the terms of the GNU General Public License version 2 as published
  20922. + * by the Free Software Foundation.
  20923. + */
  20924. +
  20925. +#include <linux/gpio.h>
  20926. +#include <linux/platform_device.h>
  20927. +
  20928. +#include <asm/mach-ath79/ath79.h>
  20929. +#include <asm/mach-ath79/ar71xx_regs.h>
  20930. +
  20931. +#include "common.h"
  20932. +#include "dev-eth.h"
  20933. +#include "dev-gpio-buttons.h"
  20934. +#include "dev-leds-gpio.h"
  20935. +#include "dev-m25p80.h"
  20936. +#include "dev-usb.h"
  20937. +#include "dev-wmac.h"
  20938. +#include "machtypes.h"
  20939. +
  20940. +#define TL_WA830REV2_GPIO_LED_WLAN 13
  20941. +#define TL_WA830REV2_GPIO_LED_QSS 15
  20942. +#define TL_WA830REV2_GPIO_LED_LAN 18
  20943. +#define TL_WA830REV2_GPIO_LED_SYSTEM 14
  20944. +
  20945. +#define TL_WA830REV2_GPIO_BTN_RESET 17
  20946. +#define TL_WA830REV2_GPIO_SW_RFKILL 16 /* WPS for MR3420 v2 */
  20947. +
  20948. +#define TL_WA830REV2_GPIO_USB_POWER 4
  20949. +
  20950. +#define TL_WA830REV2_KEYS_POLL_INTERVAL 20 /* msecs */
  20951. +#define TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA830REV2_KEYS_POLL_INTERVAL)
  20952. +
  20953. +static const char *tl_wa830re_v2_part_probes[] = {
  20954. + "tp-link",
  20955. + NULL,
  20956. +};
  20957. +
  20958. +static struct flash_platform_data tl_wa830re_v2_flash_data = {
  20959. + .part_probes = tl_wa830re_v2_part_probes,
  20960. +};
  20961. +
  20962. +static struct gpio_led tl_wa830re_v2_leds_gpio[] __initdata = {
  20963. + {
  20964. + .name = "tp-link:green:qss",
  20965. + .gpio = TL_WA830REV2_GPIO_LED_QSS,
  20966. + .active_low = 1,
  20967. + }, {
  20968. + .name = "tp-link:green:system",
  20969. + .gpio = TL_WA830REV2_GPIO_LED_SYSTEM,
  20970. + .active_low = 1,
  20971. + }, {
  20972. + .name = "tp-link:green:lan",
  20973. + .gpio = TL_WA830REV2_GPIO_LED_LAN,
  20974. + .active_low = 1,
  20975. + }, {
  20976. + .name = "tp-link:green:wlan",
  20977. + .gpio = TL_WA830REV2_GPIO_LED_WLAN,
  20978. + .active_low = 1,
  20979. + },
  20980. +};
  20981. +
  20982. +static struct gpio_keys_button tl_wa830re_v2_gpio_keys[] __initdata = {
  20983. + {
  20984. + .desc = "Reset button",
  20985. + .type = EV_KEY,
  20986. + .code = KEY_RESTART,
  20987. + .debounce_interval = TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL,
  20988. + .gpio = TL_WA830REV2_GPIO_BTN_RESET,
  20989. + .active_low = 1,
  20990. + }, {
  20991. + .desc = "RFKILL switch",
  20992. + .type = EV_SW,
  20993. + .code = KEY_RFKILL,
  20994. + .debounce_interval = TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL,
  20995. + .gpio = TL_WA830REV2_GPIO_SW_RFKILL,
  20996. + .active_low = 0,
  20997. + }
  20998. +};
  20999. +
  21000. +static void __init tl_ap123_setup(void)
  21001. +{
  21002. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  21003. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  21004. +
  21005. + /* Disable JTAG, enabling GPIOs 0-3 */
  21006. + /* Configure OBS4 line, for GPIO 4*/
  21007. + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
  21008. + AR934X_GPIO_FUNC_CLK_OBS4_EN);
  21009. +
  21010. + /* config gpio4 as normal gpio function */
  21011. + ath79_gpio_output_select(TL_WA830REV2_GPIO_USB_POWER,
  21012. + AR934X_GPIO_OUT_GPIO);
  21013. +
  21014. + ath79_register_m25p80(&tl_wa830re_v2_flash_data);
  21015. +
  21016. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  21017. +
  21018. + ath79_register_mdio(1, 0x0);
  21019. +
  21020. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  21021. +
  21022. + /* GMAC0 is connected to the PHY0 of the internal switch */
  21023. + ath79_switch_data.phy4_mii_en = 1;
  21024. + ath79_switch_data.phy_poll_mask = BIT(0);
  21025. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  21026. + ath79_eth0_data.phy_mask = BIT(0);
  21027. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  21028. + ath79_register_eth(0);
  21029. +
  21030. + ath79_register_wmac(ee, mac);
  21031. +}
  21032. +
  21033. +static void __init tl_wa830re_v2_setup(void)
  21034. +{
  21035. + tl_ap123_setup();
  21036. +
  21037. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa830re_v2_leds_gpio) - 1,
  21038. + tl_wa830re_v2_leds_gpio);
  21039. +
  21040. + ath79_register_gpio_keys_polled(1, TL_WA830REV2_KEYS_POLL_INTERVAL,
  21041. + ARRAY_SIZE(tl_wa830re_v2_gpio_keys),
  21042. + tl_wa830re_v2_gpio_keys);
  21043. +}
  21044. +
  21045. +MIPS_MACHINE(ATH79_MACH_TL_WA830RE_V2, "TL-WA830RE-v2", "TP-LINK TL-WA830RE v2",
  21046. + tl_wa830re_v2_setup);
  21047. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa901nd-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wa901nd-v2.c
  21048. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa901nd-v2.c 1970-01-01 01:00:00.000000000 +0100
  21049. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wa901nd-v2.c 2017-08-06 20:02:15.000000000 +0200
  21050. @@ -0,0 +1,104 @@
  21051. +/*
  21052. + * TP-LINK TL-WA901N/ND v2 board support
  21053. + *
  21054. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  21055. + * Copyright (C) 2010 Pieter Hollants <pieter@hollants.com>
  21056. + * Copyright (C) 2011 Jonathan Bennett <jbscience87@gmail.com>
  21057. + *
  21058. + * This program is free software; you can redistribute it and/or modify it
  21059. + * under the terms of the GNU General Public License version 2 as published
  21060. + * by the Free Software Foundation.
  21061. + */
  21062. +
  21063. +#include <asm/mach-ath79/ath79.h>
  21064. +#include <asm/mach-ath79/ar71xx_regs.h>
  21065. +
  21066. +#include "dev-eth.h"
  21067. +#include "dev-m25p80.h"
  21068. +#include "dev-gpio-buttons.h"
  21069. +#include "dev-leds-gpio.h"
  21070. +#include "dev-wmac.h"
  21071. +#include "machtypes.h"
  21072. +
  21073. +#define TL_WA901ND_V2_GPIO_LED_QSS 4
  21074. +#define TL_WA901ND_V2_GPIO_LED_SYSTEM 2
  21075. +#define TL_WA901ND_V2_GPIO_LED_WLAN 9
  21076. +
  21077. +#define TL_WA901ND_V2_GPIO_BTN_RESET 3
  21078. +#define TL_WA901ND_V2_GPIO_BTN_QSS 7
  21079. +
  21080. +#define TL_WA901ND_V2_KEYS_POLL_INTERVAL 20 /* msecs */
  21081. +#define TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL \
  21082. + (3 * TL_WA901ND_V2_KEYS_POLL_INTERVAL)
  21083. +
  21084. +static const char *tl_wa901nd_v2_part_probes[] = {
  21085. + "tp-link",
  21086. + NULL,
  21087. +};
  21088. +
  21089. +static struct flash_platform_data tl_wa901nd_v2_flash_data = {
  21090. + .part_probes = tl_wa901nd_v2_part_probes,
  21091. +};
  21092. +
  21093. +static struct gpio_led tl_wa901nd_v2_leds_gpio[] __initdata = {
  21094. + {
  21095. + .name = "tp-link:green:system",
  21096. + .gpio = TL_WA901ND_V2_GPIO_LED_SYSTEM,
  21097. + .active_low = 1,
  21098. + }, {
  21099. + .name = "tp-link:green:qss",
  21100. + .gpio = TL_WA901ND_V2_GPIO_LED_QSS,
  21101. + }, {
  21102. + .name = "tp-link:green:wlan",
  21103. + .gpio = TL_WA901ND_V2_GPIO_LED_WLAN,
  21104. + .active_low = 1,
  21105. + }
  21106. +};
  21107. +
  21108. +static struct gpio_keys_button tl_wa901nd_v2_gpio_keys[] __initdata = {
  21109. + {
  21110. + .desc = "reset",
  21111. + .type = EV_KEY,
  21112. + .code = KEY_RESTART,
  21113. + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL,
  21114. + .gpio = TL_WA901ND_V2_GPIO_BTN_RESET,
  21115. + .active_low = 1,
  21116. + }, {
  21117. + .desc = "qss",
  21118. + .type = EV_KEY,
  21119. + .code = KEY_WPS_BUTTON,
  21120. + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL,
  21121. + .gpio = TL_WA901ND_V2_GPIO_BTN_QSS,
  21122. + .active_low = 1,
  21123. + }
  21124. +};
  21125. +
  21126. +static void __init tl_wa901nd_v2_setup(void)
  21127. +{
  21128. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  21129. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  21130. +
  21131. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  21132. +
  21133. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  21134. + ath79_eth0_data.phy_mask = 0x00001000;
  21135. + ath79_register_mdio(0, 0x0);
  21136. +
  21137. + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC |
  21138. + AR71XX_RESET_GE0_PHY;
  21139. + ath79_register_eth(0);
  21140. +
  21141. + ath79_register_m25p80(&tl_wa901nd_v2_flash_data);
  21142. +
  21143. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio),
  21144. + tl_wa901nd_v2_leds_gpio);
  21145. +
  21146. + ath79_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL,
  21147. + ARRAY_SIZE(tl_wa901nd_v2_gpio_keys),
  21148. + tl_wa901nd_v2_gpio_keys);
  21149. +
  21150. + ath79_register_wmac(eeprom, mac);
  21151. +}
  21152. +
  21153. +MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V2, "TL-WA901ND-v2",
  21154. + "TP-LINK TL-WA901ND v2", tl_wa901nd_v2_setup);
  21155. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa901nd.c linux-4.1.43/arch/mips/ath79/mach-tl-wa901nd.c
  21156. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wa901nd.c 1970-01-01 01:00:00.000000000 +0100
  21157. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wa901nd.c 2017-08-06 20:02:15.000000000 +0200
  21158. @@ -0,0 +1,127 @@
  21159. +/*
  21160. + * TP-LINK TL-WA901N/ND v1, TL-WA7510N v1 board support
  21161. + *
  21162. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  21163. + * Copyright (C) 2010 Pieter Hollants <pieter@hollants.com>
  21164. + * Copyright (C) 2012 Stefan Helmert <helst_listen@aol.de>
  21165. + *
  21166. + * This program is free software; you can redistribute it and/or modify it
  21167. + * under the terms of the GNU General Public License version 2 as published
  21168. + * by the Free Software Foundation.
  21169. + */
  21170. +
  21171. +#include <asm/mach-ath79/ar71xx_regs.h>
  21172. +#include <asm/mach-ath79/ath79.h>
  21173. +
  21174. +#include "common.h"
  21175. +#include "dev-ap9x-pci.h"
  21176. +#include "dev-eth.h"
  21177. +#include "dev-gpio-buttons.h"
  21178. +#include "dev-leds-gpio.h"
  21179. +#include "dev-m25p80.h"
  21180. +#include "machtypes.h"
  21181. +#include "pci.h"
  21182. +
  21183. +#define TL_WA901ND_GPIO_LED_QSS 0
  21184. +#define TL_WA901ND_GPIO_LED_SYSTEM 1
  21185. +#define TL_WA901ND_GPIO_LED_LAN 13
  21186. +
  21187. +#define TL_WA901ND_GPIO_BTN_RESET 11
  21188. +#define TL_WA901ND_GPIO_BTN_QSS 12
  21189. +
  21190. +#define TL_WA901ND_KEYS_POLL_INTERVAL 20 /* msecs */
  21191. +#define TL_WA901ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA901ND_KEYS_POLL_INTERVAL)
  21192. +
  21193. +static const char *tl_wa901nd_part_probes[] = {
  21194. + "tp-link",
  21195. + NULL,
  21196. +};
  21197. +
  21198. +static struct flash_platform_data tl_wa901nd_flash_data = {
  21199. + .part_probes = tl_wa901nd_part_probes,
  21200. +};
  21201. +
  21202. +static struct gpio_led tl_wa901nd_leds_gpio[] __initdata = {
  21203. + {
  21204. + .name = "tp-link:green:lan",
  21205. + .gpio = TL_WA901ND_GPIO_LED_LAN,
  21206. + .active_low = 1,
  21207. + }, {
  21208. + .name = "tp-link:green:system",
  21209. + .gpio = TL_WA901ND_GPIO_LED_SYSTEM,
  21210. + .active_low = 1,
  21211. + }, {
  21212. + .name = "tp-link:green:qss",
  21213. + .gpio = TL_WA901ND_GPIO_LED_QSS,
  21214. + .active_low = 1,
  21215. + }
  21216. +};
  21217. +
  21218. +static struct gpio_keys_button tl_wa901nd_gpio_keys[] __initdata = {
  21219. + {
  21220. + .desc = "reset",
  21221. + .type = EV_KEY,
  21222. + .code = KEY_RESTART,
  21223. + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL,
  21224. + .gpio = TL_WA901ND_GPIO_BTN_RESET,
  21225. + .active_low = 1,
  21226. + }, {
  21227. + .desc = "qss",
  21228. + .type = EV_KEY,
  21229. + .code = KEY_WPS_BUTTON,
  21230. + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL,
  21231. + .gpio = TL_WA901ND_GPIO_BTN_QSS,
  21232. + .active_low = 1,
  21233. + }
  21234. +};
  21235. +
  21236. +static void __init common_setup(void)
  21237. +{
  21238. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  21239. +
  21240. + /*
  21241. + * ath79_eth0 would be the WAN port, but is not connected.
  21242. + * ath79_eth1 connects to the internal switch chip, however
  21243. + * we have a single LAN port only.
  21244. + */
  21245. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  21246. + ath79_register_mdio(0, 0x0);
  21247. + ath79_register_eth(1);
  21248. +
  21249. + ath79_register_m25p80(&tl_wa901nd_flash_data);
  21250. +}
  21251. +
  21252. +static void __init tl_wa901nd_setup(void)
  21253. +{
  21254. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  21255. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  21256. +
  21257. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  21258. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  21259. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  21260. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  21261. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  21262. +
  21263. + common_setup();
  21264. +
  21265. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_leds_gpio),
  21266. + tl_wa901nd_leds_gpio);
  21267. +
  21268. + ath79_register_gpio_keys_polled(-1, TL_WA901ND_KEYS_POLL_INTERVAL,
  21269. + ARRAY_SIZE(tl_wa901nd_gpio_keys),
  21270. + tl_wa901nd_gpio_keys);
  21271. +
  21272. + ap91_pci_init(ee, mac);
  21273. +}
  21274. +
  21275. +MIPS_MACHINE(ATH79_MACH_TL_WA901ND, "TL-WA901ND", "TP-LINK TL-WA901ND",
  21276. + tl_wa901nd_setup);
  21277. +
  21278. +static void __init tl_wa7510n_v1_setup(void)
  21279. +{
  21280. + common_setup();
  21281. + ath79_register_pci();
  21282. +}
  21283. +
  21284. +MIPS_MACHINE(ATH79_MACH_TL_WA7510N_V1, "TL-WA7510N", "TP-LINK TL-WA7510N v1",
  21285. + tl_wa7510n_v1_setup);
  21286. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wax50re.c linux-4.1.43/arch/mips/ath79/mach-tl-wax50re.c
  21287. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wax50re.c 1970-01-01 01:00:00.000000000 +0100
  21288. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wax50re.c 2017-08-06 20:02:15.000000000 +0200
  21289. @@ -0,0 +1,313 @@
  21290. +/*
  21291. + * TP-LINK TL-WA750RE v1/TL-WA801ND v2/TL-WA850RE v1/TL-WA901ND v3
  21292. + * board support
  21293. + *
  21294. + * Copyright (C) 2013 Martijn Zilverschoon <thefriedzombie@gmail.com>
  21295. + * Copyright (C) 2013 Jiri Pirko <jiri@resnulli.us>
  21296. + *
  21297. + * This program is free software; you can redistribute it and/or modify it
  21298. + * under the terms of the GNU General Public License version 2 as published
  21299. + * by the Free Software Foundation.
  21300. + */
  21301. +
  21302. +#include <linux/gpio.h>
  21303. +#include <linux/platform_device.h>
  21304. +
  21305. +#include <asm/mach-ath79/ath79.h>
  21306. +#include <asm/mach-ath79/ar71xx_regs.h>
  21307. +
  21308. +#include "common.h"
  21309. +#include "dev-eth.h"
  21310. +#include "dev-gpio-buttons.h"
  21311. +#include "dev-leds-gpio.h"
  21312. +#include "dev-m25p80.h"
  21313. +#include "dev-wmac.h"
  21314. +#include "machtypes.h"
  21315. +
  21316. +#define TL_WAX50RE_GPIO_LED_LAN 20
  21317. +#define TL_WAX50RE_GPIO_LED_WLAN 13
  21318. +#define TL_WAX50RE_GPIO_LED_RE 15
  21319. +#define TL_WAX50RE_GPIO_LED_SIGNAL1 0
  21320. +#define TL_WAX50RE_GPIO_LED_SIGNAL2 1
  21321. +#define TL_WAX50RE_GPIO_LED_SIGNAL3 2
  21322. +#define TL_WAX50RE_GPIO_LED_SIGNAL4 3
  21323. +#define TL_WAX50RE_GPIO_LED_SIGNAL5 4
  21324. +
  21325. +#define TL_WA860RE_GPIO_LED_WLAN_ORANGE 0
  21326. +#define TL_WA860RE_GPIO_LED_WLAN_GREEN 2
  21327. +#define TL_WA860RE_GPIO_LED_POWER_ORANGE 12
  21328. +#define TL_WA860RE_GPIO_LED_POWER_GREEN 14
  21329. +#define TL_WA860RE_GPIO_LED_LAN 20
  21330. +
  21331. +#define TL_WA801ND_V2_GPIO_LED_LAN 18
  21332. +#define TL_WA801ND_V2_GPIO_LED_SYSTEM 14
  21333. +
  21334. +#define TL_WAX50RE_GPIO_BTN_RESET 17
  21335. +#define TL_WAX50RE_GPIO_BTN_WPS 16
  21336. +
  21337. +#define TL_WA860RE_GPIO_BTN_RESET 17
  21338. +#define TL_WA860RE_GPIO_BTN_WPS 16
  21339. +#define TL_WA860RE_GPIO_BTN_ONOFF 11
  21340. +
  21341. +#define TL_WAX50RE_KEYS_POLL_INTERVAL 20 /* msecs */
  21342. +#define TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL (3 * TL_WAX50RE_KEYS_POLL_INTERVAL)
  21343. +
  21344. +static const char *tl_wax50re_part_probes[] = {
  21345. + "tp-link",
  21346. + NULL,
  21347. +};
  21348. +
  21349. +static struct flash_platform_data tl_wax50re_flash_data = {
  21350. + .part_probes = tl_wax50re_part_probes,
  21351. +};
  21352. +
  21353. +static struct gpio_led tl_wa750re_leds_gpio[] __initdata = {
  21354. + {
  21355. + .name = "tp-link:orange:lan",
  21356. + .gpio = TL_WAX50RE_GPIO_LED_LAN,
  21357. + .active_low = 1,
  21358. + }, {
  21359. + .name = "tp-link:orange:wlan",
  21360. + .gpio = TL_WAX50RE_GPIO_LED_WLAN,
  21361. + .active_low = 1,
  21362. + }, {
  21363. + .name = "tp-link:orange:re",
  21364. + .gpio = TL_WAX50RE_GPIO_LED_RE,
  21365. + .active_low = 1,
  21366. + }, {
  21367. + .name = "tp-link:orange:signal1",
  21368. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL1,
  21369. + .active_low = 1,
  21370. + }, {
  21371. + .name = "tp-link:orange:signal2",
  21372. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL2,
  21373. + .active_low = 1,
  21374. + }, {
  21375. + .name = "tp-link:orange:signal3",
  21376. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL3,
  21377. + .active_low = 1,
  21378. + }, {
  21379. + .name = "tp-link:orange:signal4",
  21380. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL4,
  21381. + .active_low = 1,
  21382. + }, {
  21383. + .name = "tp-link:orange:signal5",
  21384. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL5,
  21385. + .active_low = 1,
  21386. + },
  21387. +};
  21388. +
  21389. +static struct gpio_led tl_wa850re_leds_gpio[] __initdata = {
  21390. + {
  21391. + .name = "tp-link:blue:lan",
  21392. + .gpio = TL_WAX50RE_GPIO_LED_LAN,
  21393. + .active_low = 1,
  21394. + }, {
  21395. + .name = "tp-link:blue:wlan",
  21396. + .gpio = TL_WAX50RE_GPIO_LED_WLAN,
  21397. + .active_low = 1,
  21398. + }, {
  21399. + .name = "tp-link:blue:re",
  21400. + .gpio = TL_WAX50RE_GPIO_LED_RE,
  21401. + .active_low = 1,
  21402. + }, {
  21403. + .name = "tp-link:blue:signal1",
  21404. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL1,
  21405. + .active_low = 1,
  21406. + }, {
  21407. + .name = "tp-link:blue:signal2",
  21408. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL2,
  21409. + .active_low = 1,
  21410. + }, {
  21411. + .name = "tp-link:blue:signal3",
  21412. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL3,
  21413. + .active_low = 1,
  21414. + }, {
  21415. + .name = "tp-link:blue:signal4",
  21416. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL4,
  21417. + .active_low = 1,
  21418. + }, {
  21419. + .name = "tp-link:blue:signal5",
  21420. + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL5,
  21421. + .active_low = 1,
  21422. + },
  21423. +};
  21424. +
  21425. +static struct gpio_led tl_wa860re_leds_gpio[] __initdata = {
  21426. + {
  21427. + .name = "tp-link:green:lan",
  21428. + .gpio = TL_WA860RE_GPIO_LED_LAN,
  21429. + .active_low = 1,
  21430. + }, {
  21431. + .name = "tp-link:green:power",
  21432. + .gpio = TL_WA860RE_GPIO_LED_POWER_GREEN,
  21433. + .active_low = 1,
  21434. + }, {
  21435. + .name = "tp-link:orange:power",
  21436. + .gpio = TL_WA860RE_GPIO_LED_POWER_ORANGE,
  21437. + .active_low = 1,
  21438. + }, {
  21439. + .name = "tp-link:green:wlan",
  21440. + .gpio = TL_WA860RE_GPIO_LED_WLAN_GREEN,
  21441. + .active_low = 1,
  21442. + }, {
  21443. + .name = "tp-link:orange:wlan",
  21444. + .gpio = TL_WA860RE_GPIO_LED_WLAN_ORANGE,
  21445. + .active_low = 1,
  21446. + },
  21447. +};
  21448. +
  21449. +
  21450. +static struct gpio_keys_button tl_wax50re_gpio_keys[] __initdata = {
  21451. + {
  21452. + .desc = "Reset button",
  21453. + .type = EV_KEY,
  21454. + .code = KEY_RESTART,
  21455. + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL,
  21456. + .gpio = TL_WAX50RE_GPIO_BTN_RESET,
  21457. + .active_low = 1,
  21458. + }, {
  21459. + .desc = "WPS",
  21460. + .type = EV_KEY,
  21461. + .code = KEY_WPS_BUTTON,
  21462. + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL,
  21463. + .gpio = TL_WAX50RE_GPIO_BTN_WPS,
  21464. + .active_low = 1,
  21465. + },
  21466. +};
  21467. +
  21468. +static struct gpio_keys_button tl_wa860re_gpio_keys[] __initdata = {
  21469. + {
  21470. + .desc = "Reset button",
  21471. + .type = EV_KEY,
  21472. + .code = KEY_RESTART,
  21473. + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL,
  21474. + .gpio = TL_WA860RE_GPIO_BTN_RESET,
  21475. + .active_low = 1,
  21476. + }, {
  21477. + .desc = "WPS",
  21478. + .type = EV_KEY,
  21479. + .code = KEY_WPS_BUTTON,
  21480. + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL,
  21481. + .gpio = TL_WA860RE_GPIO_BTN_WPS,
  21482. + .active_low = 1,
  21483. + }, {
  21484. + .desc = "ONOFF",
  21485. + .type = EV_KEY,
  21486. + .code = BTN_1,
  21487. + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL,
  21488. + .gpio = TL_WA860RE_GPIO_BTN_ONOFF,
  21489. + .active_low = 1,
  21490. + },
  21491. +};
  21492. +
  21493. +static struct gpio_led tl_wa801nd_v2_leds_gpio[] __initdata = {
  21494. + {
  21495. + .name = "tp-link:green:lan",
  21496. + .gpio = TL_WA801ND_V2_GPIO_LED_LAN,
  21497. + .active_low = 1,
  21498. + }, {
  21499. + .name = "tp-link:green:wlan",
  21500. + .gpio = TL_WAX50RE_GPIO_LED_WLAN,
  21501. + .active_low = 1,
  21502. + }, {
  21503. + .name = "tp-link:green:qss",
  21504. + .gpio = TL_WAX50RE_GPIO_LED_RE,
  21505. + .active_low = 1,
  21506. + }, {
  21507. + .name = "tp-link:green:system",
  21508. + .gpio = TL_WA801ND_V2_GPIO_LED_SYSTEM,
  21509. + .active_low = 1,
  21510. + },
  21511. +};
  21512. +
  21513. +static void __init tl_ap123_setup(void)
  21514. +{
  21515. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  21516. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  21517. +
  21518. + ath79_register_m25p80(&tl_wax50re_flash_data);
  21519. +
  21520. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  21521. +
  21522. + ath79_register_mdio(1, 0x0);
  21523. +
  21524. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  21525. +
  21526. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  21527. + ath79_eth0_data.phy_mask = BIT(0);
  21528. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  21529. + ath79_register_eth(0);
  21530. +
  21531. + ath79_register_wmac(ee, mac);
  21532. +}
  21533. +
  21534. +static void __init tl_wa750re_setup(void)
  21535. +{
  21536. + tl_ap123_setup();
  21537. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa750re_leds_gpio),
  21538. + tl_wa750re_leds_gpio);
  21539. +
  21540. + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL,
  21541. + ARRAY_SIZE(tl_wax50re_gpio_keys),
  21542. + tl_wax50re_gpio_keys);
  21543. +}
  21544. +
  21545. +MIPS_MACHINE(ATH79_MACH_TL_WA750RE, "TL-WA750RE", "TP-LINK TL-WA750RE",
  21546. + tl_wa750re_setup);
  21547. +
  21548. +static void __init tl_wa801nd_v2_setup(void)
  21549. +{
  21550. + tl_ap123_setup();
  21551. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa801nd_v2_leds_gpio),
  21552. + tl_wa801nd_v2_leds_gpio);
  21553. +
  21554. + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL,
  21555. + ARRAY_SIZE(tl_wax50re_gpio_keys),
  21556. + tl_wax50re_gpio_keys);
  21557. +}
  21558. +
  21559. +MIPS_MACHINE(ATH79_MACH_TL_WA801ND_V2, "TL-WA801ND-v2", "TP-LINK TL-WA801ND v2",
  21560. + tl_wa801nd_v2_setup);
  21561. +
  21562. +static void __init tl_wa850re_setup(void)
  21563. +{
  21564. + tl_ap123_setup();
  21565. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa850re_leds_gpio),
  21566. + tl_wa850re_leds_gpio);
  21567. +
  21568. + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL,
  21569. + ARRAY_SIZE(tl_wax50re_gpio_keys),
  21570. + tl_wax50re_gpio_keys);
  21571. +}
  21572. +
  21573. +MIPS_MACHINE(ATH79_MACH_TL_WA850RE, "TL-WA850RE", "TP-LINK TL-WA850RE",
  21574. + tl_wa850re_setup);
  21575. +
  21576. +static void __init tl_wa860re_setup(void)
  21577. +{
  21578. + tl_ap123_setup();
  21579. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa860re_leds_gpio),
  21580. + tl_wa860re_leds_gpio);
  21581. +
  21582. + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL,
  21583. + ARRAY_SIZE(tl_wa860re_gpio_keys),
  21584. + tl_wa860re_gpio_keys);
  21585. +}
  21586. +
  21587. +MIPS_MACHINE(ATH79_MACH_TL_WA860RE, "TL-WA860RE", "TP-LINK TL-WA860RE",
  21588. + tl_wa860re_setup);
  21589. +
  21590. +static void __init tl_wa901nd_v3_setup(void)
  21591. +{
  21592. + tl_ap123_setup();
  21593. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa801nd_v2_leds_gpio),
  21594. + tl_wa801nd_v2_leds_gpio);
  21595. +
  21596. + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL,
  21597. + ARRAY_SIZE(tl_wax50re_gpio_keys) - 1,
  21598. + tl_wax50re_gpio_keys);
  21599. +}
  21600. +
  21601. +MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V3, "TL-WA901ND-v3", "TP-LINK TL-WA901ND v3",
  21602. + tl_wa901nd_v3_setup);
  21603. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr3320-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wdr3320-v2.c
  21604. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr3320-v2.c 1970-01-01 01:00:00.000000000 +0100
  21605. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wdr3320-v2.c 2017-08-06 20:02:15.000000000 +0200
  21606. @@ -0,0 +1,146 @@
  21607. +/*
  21608. + * TP-LINK TL-WDR3320 v2 board support
  21609. + *
  21610. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  21611. + * Copyright (C) 2015 Weijie Gao <hackpascal@gmail.com>
  21612. + *
  21613. + * This program is free software; you can redistribute it and/or modify it
  21614. + * under the terms of the GNU General Public License version 2 as published
  21615. + * by the Free Software Foundation.
  21616. + */
  21617. +
  21618. +#include <linux/pci.h>
  21619. +#include <linux/phy.h>
  21620. +#include <linux/gpio.h>
  21621. +#include <linux/platform_device.h>
  21622. +#include <linux/ath9k_platform.h>
  21623. +
  21624. +#include <asm/mach-ath79/ar71xx_regs.h>
  21625. +
  21626. +#include "common.h"
  21627. +#include "dev-ap9x-pci.h"
  21628. +#include "dev-eth.h"
  21629. +#include "dev-gpio-buttons.h"
  21630. +#include "dev-leds-gpio.h"
  21631. +#include "dev-m25p80.h"
  21632. +#include "dev-spi.h"
  21633. +#include "dev-usb.h"
  21634. +#include "dev-wmac.h"
  21635. +#include "machtypes.h"
  21636. +
  21637. +#define WDR3320_GPIO_LED_WLAN5G 12
  21638. +#define WDR3320_GPIO_LED_SYSTEM 14
  21639. +#define WDR3320_GPIO_LED_QSS 15
  21640. +#define WDR3320_GPIO_LED_WAN 4
  21641. +#define WDR3320_GPIO_LED_LAN1 18
  21642. +#define WDR3320_GPIO_LED_LAN2 20
  21643. +#define WDR3320_GPIO_LED_LAN3 21
  21644. +#define WDR3320_GPIO_LED_LAN4 22
  21645. +
  21646. +#define WDR3320_GPIO_BTN_RESET 16
  21647. +
  21648. +#define WDR3320_KEYS_POLL_INTERVAL 20 /* msecs */
  21649. +#define WDR3320_KEYS_DEBOUNCE_INTERVAL (3 * WDR3320_KEYS_POLL_INTERVAL)
  21650. +
  21651. +#define WDR3320_WMAC_CALDATA_OFFSET 0x1000
  21652. +#define WDR3320_PCIE_CALDATA_OFFSET 0x5000
  21653. +
  21654. +static const char *wdr3320_part_probes[] = {
  21655. + "tp-link",
  21656. + NULL,
  21657. +};
  21658. +
  21659. +static struct flash_platform_data wdr3320_flash_data = {
  21660. + .part_probes = wdr3320_part_probes,
  21661. +};
  21662. +
  21663. +static struct gpio_led wdr3320_leds_gpio[] __initdata = {
  21664. + {
  21665. + .name = "tp-link:green:qss",
  21666. + .gpio = WDR3320_GPIO_LED_QSS,
  21667. + .active_low = 1,
  21668. + },
  21669. + {
  21670. + .name = "tp-link:green:system",
  21671. + .gpio = WDR3320_GPIO_LED_SYSTEM,
  21672. + .active_low = 1,
  21673. + },
  21674. + {
  21675. + .name = "tp-link:green:wlan5g",
  21676. + .gpio = WDR3320_GPIO_LED_WLAN5G,
  21677. + .active_low = 1,
  21678. + },
  21679. +};
  21680. +
  21681. +static struct gpio_keys_button wdr3320_gpio_keys[] __initdata = {
  21682. + {
  21683. + .desc = "reset",
  21684. + .type = EV_KEY,
  21685. + .code = KEY_RESTART,
  21686. + .debounce_interval = WDR3320_KEYS_DEBOUNCE_INTERVAL,
  21687. + .gpio = WDR3320_GPIO_BTN_RESET,
  21688. + .active_low = 1,
  21689. + },
  21690. +};
  21691. +
  21692. +static void __init wdr3320_setup(void)
  21693. +{
  21694. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  21695. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  21696. + u8 tmpmac[ETH_ALEN];
  21697. +
  21698. + ath79_register_m25p80(&wdr3320_flash_data);
  21699. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3320_leds_gpio),
  21700. + wdr3320_leds_gpio);
  21701. + ath79_register_gpio_keys_polled(-1, WDR3320_KEYS_POLL_INTERVAL,
  21702. + ARRAY_SIZE(wdr3320_gpio_keys),
  21703. + wdr3320_gpio_keys);
  21704. +
  21705. + ath79_init_mac(tmpmac, mac, 0);
  21706. + ath79_register_wmac(art + WDR3320_WMAC_CALDATA_OFFSET, tmpmac);
  21707. +
  21708. + ath79_init_mac(tmpmac, mac, -1);
  21709. + ap9x_pci_setup_wmac_led_pin(0, 0);
  21710. + ap91_pci_init(art + WDR3320_PCIE_CALDATA_OFFSET, tmpmac);
  21711. +
  21712. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  21713. +
  21714. + ath79_register_mdio(1, 0x0);
  21715. +
  21716. + /* LAN */
  21717. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  21718. +
  21719. + /* GMAC1 is connected to the internal switch */
  21720. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  21721. +
  21722. + ath79_register_eth(1);
  21723. +
  21724. + /* WAN */
  21725. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  21726. +
  21727. + /* GMAC0 is connected to the PHY4 of the internal switch */
  21728. + ath79_switch_data.phy4_mii_en = 1;
  21729. + ath79_switch_data.phy_poll_mask = BIT(4);
  21730. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  21731. + ath79_eth0_data.phy_mask = BIT(4);
  21732. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  21733. +
  21734. + ath79_register_eth(0);
  21735. +
  21736. + ath79_register_usb();
  21737. +
  21738. + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN1,
  21739. + AR934X_GPIO_OUT_LED_LINK0);
  21740. + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN2,
  21741. + AR934X_GPIO_OUT_LED_LINK1);
  21742. + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN3,
  21743. + AR934X_GPIO_OUT_LED_LINK2);
  21744. + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN4,
  21745. + AR934X_GPIO_OUT_LED_LINK3);
  21746. + ath79_gpio_output_select(WDR3320_GPIO_LED_WAN,
  21747. + AR934X_GPIO_OUT_LED_LINK4);
  21748. +}
  21749. +
  21750. +MIPS_MACHINE(ATH79_MACH_TL_WDR3320_V2, "TL-WDR3320-v2",
  21751. + "TP-LINK TL-WDR3320 v2",
  21752. + wdr3320_setup);
  21753. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr3500.c linux-4.1.43/arch/mips/ath79/mach-tl-wdr3500.c
  21754. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr3500.c 1970-01-01 01:00:00.000000000 +0100
  21755. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wdr3500.c 2017-08-06 20:02:15.000000000 +0200
  21756. @@ -0,0 +1,169 @@
  21757. +/*
  21758. + * TP-LINK TL-WDR3500 board support
  21759. + *
  21760. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  21761. + * Copyright (C) 2013 Gui Iribarren <gui@altermundi.net>
  21762. + *
  21763. + * This program is free software; you can redistribute it and/or modify it
  21764. + * under the terms of the GNU General Public License version 2 as published
  21765. + * by the Free Software Foundation.
  21766. + */
  21767. +
  21768. +#include <linux/pci.h>
  21769. +#include <linux/phy.h>
  21770. +#include <linux/gpio.h>
  21771. +#include <linux/platform_device.h>
  21772. +#include <linux/ath9k_platform.h>
  21773. +#include <linux/ar8216_platform.h>
  21774. +
  21775. +#include <asm/mach-ath79/ar71xx_regs.h>
  21776. +
  21777. +#include "common.h"
  21778. +#include "dev-ap9x-pci.h"
  21779. +#include "dev-eth.h"
  21780. +#include "dev-gpio-buttons.h"
  21781. +#include "dev-leds-gpio.h"
  21782. +#include "dev-m25p80.h"
  21783. +#include "dev-spi.h"
  21784. +#include "dev-usb.h"
  21785. +#include "dev-wmac.h"
  21786. +#include "machtypes.h"
  21787. +
  21788. +#define WDR3500_GPIO_LED_USB 11
  21789. +#define WDR3500_GPIO_LED_WLAN2G 13
  21790. +#define WDR3500_GPIO_LED_SYSTEM 14
  21791. +#define WDR3500_GPIO_LED_QSS 15
  21792. +#define WDR3500_GPIO_LED_WAN 18
  21793. +#define WDR3500_GPIO_LED_LAN1 19
  21794. +#define WDR3500_GPIO_LED_LAN2 20
  21795. +#define WDR3500_GPIO_LED_LAN3 21
  21796. +#define WDR3500_GPIO_LED_LAN4 22
  21797. +
  21798. +#define WDR3500_GPIO_BTN_WPS 16
  21799. +#define WDR3500_GPIO_BTN_RFKILL 17
  21800. +
  21801. +#define WDR3500_GPIO_USB_POWER 12
  21802. +
  21803. +#define WDR3500_KEYS_POLL_INTERVAL 20 /* msecs */
  21804. +#define WDR3500_KEYS_DEBOUNCE_INTERVAL (3 * WDR3500_KEYS_POLL_INTERVAL)
  21805. +
  21806. +#define WDR3500_MAC0_OFFSET 0
  21807. +#define WDR3500_MAC1_OFFSET 6
  21808. +#define WDR3500_WMAC_CALDATA_OFFSET 0x1000
  21809. +#define WDR3500_PCIE_CALDATA_OFFSET 0x5000
  21810. +
  21811. +static const char *wdr3500_part_probes[] = {
  21812. + "tp-link",
  21813. + NULL,
  21814. +};
  21815. +
  21816. +static struct flash_platform_data wdr3500_flash_data = {
  21817. + .part_probes = wdr3500_part_probes,
  21818. +};
  21819. +
  21820. +static struct gpio_led wdr3500_leds_gpio[] __initdata = {
  21821. + {
  21822. + .name = "tp-link:green:qss",
  21823. + .gpio = WDR3500_GPIO_LED_QSS,
  21824. + .active_low = 1,
  21825. + },
  21826. + {
  21827. + .name = "tp-link:green:system",
  21828. + .gpio = WDR3500_GPIO_LED_SYSTEM,
  21829. + .active_low = 1,
  21830. + },
  21831. + {
  21832. + .name = "tp-link:green:usb",
  21833. + .gpio = WDR3500_GPIO_LED_USB,
  21834. + .active_low = 1,
  21835. + },
  21836. + {
  21837. + .name = "tp-link:green:wlan2g",
  21838. + .gpio = WDR3500_GPIO_LED_WLAN2G,
  21839. + .active_low = 1,
  21840. + },
  21841. +};
  21842. +
  21843. +static struct gpio_keys_button wdr3500_gpio_keys[] __initdata = {
  21844. + {
  21845. + .desc = "QSS button",
  21846. + .type = EV_KEY,
  21847. + .code = KEY_WPS_BUTTON,
  21848. + .debounce_interval = WDR3500_KEYS_DEBOUNCE_INTERVAL,
  21849. + .gpio = WDR3500_GPIO_BTN_WPS,
  21850. + .active_low = 1,
  21851. + },
  21852. + {
  21853. + .desc = "RFKILL switch",
  21854. + .type = EV_SW,
  21855. + .code = KEY_RFKILL,
  21856. + .debounce_interval = WDR3500_KEYS_DEBOUNCE_INTERVAL,
  21857. + .gpio = WDR3500_GPIO_BTN_RFKILL,
  21858. + },
  21859. +};
  21860. +
  21861. +
  21862. +static void __init wdr3500_setup(void)
  21863. +{
  21864. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  21865. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  21866. + u8 tmpmac[ETH_ALEN];
  21867. +
  21868. + ath79_register_m25p80(&wdr3500_flash_data);
  21869. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3500_leds_gpio),
  21870. + wdr3500_leds_gpio);
  21871. + ath79_register_gpio_keys_polled(-1, WDR3500_KEYS_POLL_INTERVAL,
  21872. + ARRAY_SIZE(wdr3500_gpio_keys),
  21873. + wdr3500_gpio_keys);
  21874. +
  21875. + ath79_init_mac(tmpmac, mac, 0);
  21876. + ath79_register_wmac(art + WDR3500_WMAC_CALDATA_OFFSET, tmpmac);
  21877. +
  21878. + ath79_init_mac(tmpmac, mac, 1);
  21879. + ap9x_pci_setup_wmac_led_pin(0, 0);
  21880. + ap91_pci_init(art + WDR3500_PCIE_CALDATA_OFFSET, tmpmac);
  21881. +
  21882. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  21883. +
  21884. + ath79_register_mdio(1, 0x0);
  21885. +
  21886. + /* LAN */
  21887. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  21888. +
  21889. + /* GMAC1 is connected to the internal switch */
  21890. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  21891. +
  21892. + ath79_register_eth(1);
  21893. +
  21894. + /* WAN */
  21895. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2);
  21896. +
  21897. + /* GMAC0 is connected to the PHY4 of the internal switch */
  21898. + ath79_switch_data.phy4_mii_en = 1;
  21899. + ath79_switch_data.phy_poll_mask = BIT(4);
  21900. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  21901. + ath79_eth0_data.phy_mask = BIT(4);
  21902. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  21903. +
  21904. + ath79_register_eth(0);
  21905. +
  21906. + gpio_request_one(WDR3500_GPIO_USB_POWER,
  21907. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  21908. + "USB power");
  21909. + ath79_register_usb();
  21910. +
  21911. + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN1,
  21912. + AR934X_GPIO_OUT_LED_LINK3);
  21913. + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN2,
  21914. + AR934X_GPIO_OUT_LED_LINK2);
  21915. + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN3,
  21916. + AR934X_GPIO_OUT_LED_LINK1);
  21917. + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN4,
  21918. + AR934X_GPIO_OUT_LED_LINK0);
  21919. + ath79_gpio_output_select(WDR3500_GPIO_LED_WAN,
  21920. + AR934X_GPIO_OUT_LED_LINK4);
  21921. +}
  21922. +
  21923. +MIPS_MACHINE(ATH79_MACH_TL_WDR3500, "TL-WDR3500",
  21924. + "TP-LINK TL-WDR3500",
  21925. + wdr3500_setup);
  21926. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr4300.c linux-4.1.43/arch/mips/ath79/mach-tl-wdr4300.c
  21927. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr4300.c 1970-01-01 01:00:00.000000000 +0100
  21928. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wdr4300.c 2017-08-06 20:02:15.000000000 +0200
  21929. @@ -0,0 +1,206 @@
  21930. +/*
  21931. + * TP-LINK TL-WDR4300 board support
  21932. + *
  21933. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  21934. + *
  21935. + * This program is free software; you can redistribute it and/or modify it
  21936. + * under the terms of the GNU General Public License version 2 as published
  21937. + * by the Free Software Foundation.
  21938. + */
  21939. +
  21940. +#include <linux/pci.h>
  21941. +#include <linux/phy.h>
  21942. +#include <linux/gpio.h>
  21943. +#include <linux/platform_device.h>
  21944. +#include <linux/ath9k_platform.h>
  21945. +#include <linux/ar8216_platform.h>
  21946. +
  21947. +#include <asm/mach-ath79/ar71xx_regs.h>
  21948. +
  21949. +#include "common.h"
  21950. +#include "dev-ap9x-pci.h"
  21951. +#include "dev-eth.h"
  21952. +#include "dev-gpio-buttons.h"
  21953. +#include "dev-leds-gpio.h"
  21954. +#include "dev-m25p80.h"
  21955. +#include "dev-spi.h"
  21956. +#include "dev-usb.h"
  21957. +#include "dev-wmac.h"
  21958. +#include "machtypes.h"
  21959. +
  21960. +#define WDR4300_GPIO_LED_USB1 11
  21961. +#define WDR4300_GPIO_LED_USB2 12
  21962. +#define WDR4300_GPIO_LED_WLAN2G 13
  21963. +#define WDR4300_GPIO_LED_SYSTEM 14
  21964. +#define WDR4300_GPIO_LED_QSS 15
  21965. +
  21966. +#define WDR4300_GPIO_BTN_WPS 16
  21967. +#define WDR4300_GPIO_BTN_RFKILL 17
  21968. +
  21969. +#define WDR4300_GPIO_EXTERNAL_LNA0 18
  21970. +#define WDR4300_GPIO_EXTERNAL_LNA1 19
  21971. +
  21972. +#define WDR4300_GPIO_USB1_POWER 22
  21973. +#define WDR4300_GPIO_USB2_POWER 21
  21974. +
  21975. +#define WDR4300_KEYS_POLL_INTERVAL 20 /* msecs */
  21976. +#define WDR4300_KEYS_DEBOUNCE_INTERVAL (3 * WDR4300_KEYS_POLL_INTERVAL)
  21977. +
  21978. +#define WDR4300_MAC0_OFFSET 0
  21979. +#define WDR4300_MAC1_OFFSET 6
  21980. +#define WDR4300_WMAC_CALDATA_OFFSET 0x1000
  21981. +#define WDR4300_PCIE_CALDATA_OFFSET 0x5000
  21982. +
  21983. +static const char *wdr4300_part_probes[] = {
  21984. + "tp-link",
  21985. + NULL,
  21986. +};
  21987. +
  21988. +static struct flash_platform_data wdr4300_flash_data = {
  21989. + .part_probes = wdr4300_part_probes,
  21990. +};
  21991. +
  21992. +static struct gpio_led wdr4300_leds_gpio[] __initdata = {
  21993. + {
  21994. + .name = "tp-link:blue:qss",
  21995. + .gpio = WDR4300_GPIO_LED_QSS,
  21996. + .active_low = 1,
  21997. + },
  21998. + {
  21999. + .name = "tp-link:blue:system",
  22000. + .gpio = WDR4300_GPIO_LED_SYSTEM,
  22001. + .active_low = 1,
  22002. + },
  22003. + {
  22004. + .name = "tp-link:green:usb1",
  22005. + .gpio = WDR4300_GPIO_LED_USB1,
  22006. + .active_low = 1,
  22007. + },
  22008. + {
  22009. + .name = "tp-link:green:usb2",
  22010. + .gpio = WDR4300_GPIO_LED_USB2,
  22011. + .active_low = 1,
  22012. + },
  22013. + {
  22014. + .name = "tp-link:blue:wlan2g",
  22015. + .gpio = WDR4300_GPIO_LED_WLAN2G,
  22016. + .active_low = 1,
  22017. + },
  22018. +};
  22019. +
  22020. +static struct gpio_keys_button wdr4300_gpio_keys[] __initdata = {
  22021. + {
  22022. + .desc = "QSS button",
  22023. + .type = EV_KEY,
  22024. + .code = KEY_WPS_BUTTON,
  22025. + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL,
  22026. + .gpio = WDR4300_GPIO_BTN_WPS,
  22027. + .active_low = 1,
  22028. + },
  22029. + {
  22030. + .desc = "RFKILL switch",
  22031. + .type = EV_SW,
  22032. + .code = KEY_RFKILL,
  22033. + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL,
  22034. + .gpio = WDR4300_GPIO_BTN_RFKILL,
  22035. + .active_low = 1,
  22036. + },
  22037. +};
  22038. +
  22039. +static const struct ar8327_led_info wdr4300_leds_ar8327[] __initconst = {
  22040. + AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"),
  22041. + AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"),
  22042. + AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"),
  22043. + AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"),
  22044. + AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"),
  22045. +};
  22046. +
  22047. +static struct ar8327_pad_cfg wdr4300_ar8327_pad0_cfg = {
  22048. + .mode = AR8327_PAD_MAC_RGMII,
  22049. + .txclk_delay_en = true,
  22050. + .rxclk_delay_en = true,
  22051. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  22052. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  22053. +};
  22054. +
  22055. +static struct ar8327_led_cfg wdr4300_ar8327_led_cfg = {
  22056. + .led_ctrl0 = 0xc737c737,
  22057. + .led_ctrl1 = 0x00000000,
  22058. + .led_ctrl2 = 0x00000000,
  22059. + .led_ctrl3 = 0x0030c300,
  22060. + .open_drain = false,
  22061. +};
  22062. +
  22063. +static struct ar8327_platform_data wdr4300_ar8327_data = {
  22064. + .pad0_cfg = &wdr4300_ar8327_pad0_cfg,
  22065. + .port0_cfg = {
  22066. + .force_link = 1,
  22067. + .speed = AR8327_PORT_SPEED_1000,
  22068. + .duplex = 1,
  22069. + .txpause = 1,
  22070. + .rxpause = 1,
  22071. + },
  22072. + .led_cfg = &wdr4300_ar8327_led_cfg,
  22073. + .num_leds = ARRAY_SIZE(wdr4300_leds_ar8327),
  22074. + .leds = wdr4300_leds_ar8327,
  22075. +};
  22076. +
  22077. +static struct mdio_board_info wdr4300_mdio0_info[] = {
  22078. + {
  22079. + .bus_id = "ag71xx-mdio.0",
  22080. + .phy_addr = 0,
  22081. + .platform_data = &wdr4300_ar8327_data,
  22082. + },
  22083. +};
  22084. +
  22085. +static void __init wdr4300_setup(void)
  22086. +{
  22087. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  22088. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  22089. + u8 tmpmac[ETH_ALEN];
  22090. +
  22091. + ath79_register_m25p80(&wdr4300_flash_data);
  22092. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio),
  22093. + wdr4300_leds_gpio);
  22094. + ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL,
  22095. + ARRAY_SIZE(wdr4300_gpio_keys),
  22096. + wdr4300_gpio_keys);
  22097. +
  22098. + ath79_wmac_set_ext_lna_gpio(0, WDR4300_GPIO_EXTERNAL_LNA0);
  22099. + ath79_wmac_set_ext_lna_gpio(1, WDR4300_GPIO_EXTERNAL_LNA1);
  22100. +
  22101. + ath79_init_mac(tmpmac, mac, -1);
  22102. + ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac);
  22103. +
  22104. + ath79_init_mac(tmpmac, mac, 0);
  22105. + ap9x_pci_setup_wmac_led_pin(0, 0);
  22106. + ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
  22107. +
  22108. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  22109. +
  22110. + mdiobus_register_board_info(wdr4300_mdio0_info,
  22111. + ARRAY_SIZE(wdr4300_mdio0_info));
  22112. +
  22113. + ath79_register_mdio(0, 0x0);
  22114. +
  22115. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2);
  22116. +
  22117. + /* GMAC0 is connected to an AR8327N switch */
  22118. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  22119. + ath79_eth0_data.phy_mask = BIT(0);
  22120. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  22121. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  22122. + ath79_register_eth(0);
  22123. +
  22124. + gpio_request_one(WDR4300_GPIO_USB1_POWER,
  22125. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  22126. + "USB1 power");
  22127. + gpio_request_one(WDR4300_GPIO_USB2_POWER,
  22128. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  22129. + "USB2 power");
  22130. + ath79_register_usb();
  22131. +}
  22132. +
  22133. +MIPS_MACHINE(ATH79_MACH_TL_WDR4300, "TL-WDR4300",
  22134. + "TP-LINK TL-WDR3600/4300/4310",
  22135. + wdr4300_setup);
  22136. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr6500-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wdr6500-v2.c
  22137. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wdr6500-v2.c 1970-01-01 01:00:00.000000000 +0100
  22138. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wdr6500-v2.c 2017-08-06 20:02:15.000000000 +0200
  22139. @@ -0,0 +1,141 @@
  22140. +/*
  22141. + * TP-LINK TL-WDR6500 v2
  22142. + *
  22143. + * Copyright (C) 2015 Weijie Gao <hackpascal@gmail.com>
  22144. + *
  22145. + * This program is free software; you can redistribute it and/or modify it
  22146. + * under the terms of the GNU General Public License version 2 as published
  22147. + * by the Free Software Foundation.
  22148. + */
  22149. +
  22150. +#include <linux/pci.h>
  22151. +#include <linux/gpio.h>
  22152. +#include <linux/platform_device.h>
  22153. +
  22154. +#include <asm/mach-ath79/ath79.h>
  22155. +#include <asm/mach-ath79/ar71xx_regs.h>
  22156. +
  22157. +#include "common.h"
  22158. +#include "dev-eth.h"
  22159. +#include "dev-ap9x-pci.h"
  22160. +#include "dev-gpio-buttons.h"
  22161. +#include "dev-leds-gpio.h"
  22162. +#include "dev-m25p80.h"
  22163. +#include "dev-usb.h"
  22164. +#include "dev-wmac.h"
  22165. +#include "machtypes.h"
  22166. +#include "pci.h"
  22167. +
  22168. +#define TL_WDR6500_V2_GPIO_LED_SYS 21
  22169. +#define TL_WDR6500_V2_GPIO_LED_WAN 18
  22170. +#define TL_WDR6500_V2_GPIO_LED_LAN1 17
  22171. +#define TL_WDR6500_V2_GPIO_LED_LAN2 16
  22172. +#define TL_WDR6500_V2_GPIO_LED_LAN3 15
  22173. +#define TL_WDR6500_V2_GPIO_LED_LAN4 14
  22174. +
  22175. +#define TL_WDR6500_V2_GPIO_BTN_RESET 1
  22176. +
  22177. +#define TL_WDR6500_V2_KEYS_POLL_INTERVAL 20 /* msecs */
  22178. +#define TL_WDR6500_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WDR6500_V2_KEYS_POLL_INTERVAL)
  22179. +
  22180. +#define TL_WDR6500_V2_WMAC_CALDATA_OFFSET 0x1000
  22181. +#define TL_WDR6500_V2_PCIE_CALDATA_OFFSET 0x5000
  22182. +
  22183. +static const char *tl_wdr6500_v2_part_probes[] = {
  22184. + "tp-link-64k",
  22185. + NULL,
  22186. +};
  22187. +
  22188. +static struct flash_platform_data tl_wdr6500_v2_flash_data = {
  22189. + .part_probes = tl_wdr6500_v2_part_probes,
  22190. +};
  22191. +
  22192. +static struct gpio_led tl_wdr6500_v2_leds_gpio[] __initdata = {
  22193. + {
  22194. + .name = "tp-link:green:lan1",
  22195. + .gpio = TL_WDR6500_V2_GPIO_LED_LAN1,
  22196. + .active_low = 1,
  22197. + }, {
  22198. + .name = "tp-link:green:lan2",
  22199. + .gpio = TL_WDR6500_V2_GPIO_LED_LAN2,
  22200. + .active_low = 1,
  22201. + }, {
  22202. + .name = "tp-link:green:lan3",
  22203. + .gpio = TL_WDR6500_V2_GPIO_LED_LAN3,
  22204. + .active_low = 1,
  22205. + }, {
  22206. + .name = "tp-link:green:lan4",
  22207. + .gpio = TL_WDR6500_V2_GPIO_LED_LAN4,
  22208. + .active_low = 1,
  22209. + }, {
  22210. + .name = "tp-link:green:wan",
  22211. + .gpio = TL_WDR6500_V2_GPIO_LED_WAN,
  22212. + .active_low = 1,
  22213. + }, {
  22214. + .name = "tp-link:white:system",
  22215. + .gpio = TL_WDR6500_V2_GPIO_LED_SYS,
  22216. + .active_low = 0,
  22217. + },
  22218. +};
  22219. +
  22220. +static struct gpio_keys_button tl_wdr6500_v2_gpio_keys[] __initdata = {
  22221. + {
  22222. + .desc = "Reset button",
  22223. + .type = EV_KEY,
  22224. + .code = KEY_RESTART,
  22225. + .debounce_interval = TL_WDR6500_V2_KEYS_DEBOUNCE_INTERVAL,
  22226. + .gpio = TL_WDR6500_V2_GPIO_BTN_RESET,
  22227. + .active_low = 1,
  22228. + }
  22229. +};
  22230. +
  22231. +
  22232. +static void __init tl_ap151_setup(void)
  22233. +{
  22234. + u8 *mac = (u8 *) KSEG1ADDR(0x1f00fc00);
  22235. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff0000);
  22236. + u8 tmpmac[ETH_ALEN];
  22237. +
  22238. + ath79_register_m25p80(&tl_wdr6500_v2_flash_data);
  22239. +
  22240. + ath79_setup_ar933x_phy4_switch(false, false);
  22241. +
  22242. + ath79_register_mdio(0, 0x0);
  22243. +
  22244. + /* WAN */
  22245. + ath79_switch_data.phy4_mii_en = 1;
  22246. + ath79_switch_data.phy_poll_mask = BIT(4);
  22247. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  22248. + ath79_eth0_data.phy_mask = BIT(4);
  22249. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  22250. + ath79_register_eth(0);
  22251. +
  22252. + /* LAN */
  22253. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  22254. + ath79_eth1_data.duplex = DUPLEX_FULL;
  22255. + ath79_eth1_data.speed = SPEED_1000;
  22256. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  22257. + ath79_register_eth(1);
  22258. +
  22259. + ath79_init_mac(tmpmac, mac, -1);
  22260. + ath79_register_wmac(ee + TL_WDR6500_V2_WMAC_CALDATA_OFFSET, tmpmac);
  22261. +
  22262. + ath79_register_pci();
  22263. +
  22264. + ath79_register_usb();
  22265. +}
  22266. +
  22267. +static void __init tl_wdr6500_v2_setup(void)
  22268. +{
  22269. + tl_ap151_setup();
  22270. +
  22271. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wdr6500_v2_leds_gpio),
  22272. + tl_wdr6500_v2_leds_gpio);
  22273. +
  22274. + ath79_register_gpio_keys_polled(1, TL_WDR6500_V2_KEYS_POLL_INTERVAL,
  22275. + ARRAY_SIZE(tl_wdr6500_v2_gpio_keys),
  22276. + tl_wdr6500_v2_gpio_keys);
  22277. +}
  22278. +
  22279. +MIPS_MACHINE(ATH79_MACH_TL_WDR6500_V2, "TL-WDR6500-v2", "TP-LINK TL-WDR6500 v2",
  22280. + tl_wdr6500_v2_setup);
  22281. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr1041n-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wr1041n-v2.c
  22282. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr1041n-v2.c 1970-01-01 01:00:00.000000000 +0100
  22283. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr1041n-v2.c 2017-08-06 20:02:15.000000000 +0200
  22284. @@ -0,0 +1,138 @@
  22285. +/*
  22286. + * TP-LINK TL-WR1041 v2 board support
  22287. + *
  22288. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  22289. + * Copyright (C) 2011-2012 Anan Huang <axishero@foxmail.com>
  22290. + *
  22291. + * This program is free software; you can redistribute it and/or modify it
  22292. + * under the terms of the GNU General Public License version 2 as published
  22293. + * by the Free Software Foundation.
  22294. + */
  22295. +
  22296. +#include <linux/pci.h>
  22297. +#include <linux/phy.h>
  22298. +#include <linux/platform_device.h>
  22299. +#include <linux/ath9k_platform.h>
  22300. +#include <linux/ar8216_platform.h>
  22301. +
  22302. +#include <asm/mach-ath79/ar71xx_regs.h>
  22303. +
  22304. +#include "common.h"
  22305. +#include "dev-ap9x-pci.h"
  22306. +#include "dev-eth.h"
  22307. +#include "dev-gpio-buttons.h"
  22308. +#include "dev-leds-gpio.h"
  22309. +#include "dev-m25p80.h"
  22310. +#include "dev-spi.h"
  22311. +#include "dev-wmac.h"
  22312. +#include "machtypes.h"
  22313. +
  22314. +#define TL_WR1041NV2_GPIO_BTN_RESET 14
  22315. +#define TL_WR1041NV2_GPIO_LED_WPS 13
  22316. +#define TL_WR1041NV2_GPIO_LED_WLAN 11
  22317. +
  22318. +#define TL_WR1041NV2_GPIO_LED_SYSTEM 12
  22319. +
  22320. +#define TL_WR1041NV2_KEYS_POLL_INTERVAL 20 /* msecs */
  22321. +#define TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1041NV2_KEYS_POLL_INTERVAL)
  22322. +
  22323. +#define TL_WR1041NV2_PCIE_CALDATA_OFFSET 0x5000
  22324. +
  22325. +static const char *tl_wr1041nv2_part_probes[] = {
  22326. + "tp-link",
  22327. + NULL,
  22328. +};
  22329. +
  22330. +static struct flash_platform_data tl_wr1041nv2_flash_data = {
  22331. + .part_probes = tl_wr1041nv2_part_probes,
  22332. +};
  22333. +
  22334. +static struct gpio_led tl_wr1041nv2_leds_gpio[] __initdata = {
  22335. + {
  22336. + .name = "tp-link:green:system",
  22337. + .gpio = TL_WR1041NV2_GPIO_LED_SYSTEM,
  22338. + .active_low = 1,
  22339. + }, {
  22340. + .name = "tp-link:green:wps",
  22341. + .gpio = TL_WR1041NV2_GPIO_LED_WPS,
  22342. + .active_low = 1,
  22343. + }, {
  22344. + .name = "tp-link:green:wlan",
  22345. + .gpio = TL_WR1041NV2_GPIO_LED_WLAN,
  22346. + .active_low = 1,
  22347. + }
  22348. +};
  22349. +
  22350. +static struct gpio_keys_button tl_wr1041nv2_gpio_keys[] __initdata = {
  22351. + {
  22352. + .desc = "reset",
  22353. + .type = EV_KEY,
  22354. + .code = KEY_RESTART,
  22355. + .debounce_interval = TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL,
  22356. + .gpio = TL_WR1041NV2_GPIO_BTN_RESET,
  22357. + .active_low = 1,
  22358. + }
  22359. +};
  22360. +
  22361. +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
  22362. + .mode = AR8327_PAD_MAC_RGMII,
  22363. + .txclk_delay_en = true,
  22364. + .rxclk_delay_en = true,
  22365. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  22366. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  22367. +};
  22368. +
  22369. +static struct ar8327_platform_data db120_ar8327_data = {
  22370. + .pad0_cfg = &db120_ar8327_pad0_cfg,
  22371. + .port0_cfg = {
  22372. + .force_link = 1,
  22373. + .speed = AR8327_PORT_SPEED_1000,
  22374. + .duplex = 1,
  22375. + .txpause = 1,
  22376. + .rxpause = 1,
  22377. + }
  22378. +};
  22379. +
  22380. +static struct mdio_board_info db120_mdio0_info[] = {
  22381. + {
  22382. + .bus_id = "ag71xx-mdio.0",
  22383. + .phy_addr = 0,
  22384. + .platform_data = &db120_ar8327_data,
  22385. + },
  22386. +};
  22387. +
  22388. +static void __init tl_wr1041nv2_setup(void)
  22389. +{
  22390. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  22391. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  22392. +
  22393. + ath79_register_m25p80(&tl_wr1041nv2_flash_data);
  22394. +
  22395. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1041nv2_leds_gpio),
  22396. + tl_wr1041nv2_leds_gpio);
  22397. + ath79_register_gpio_keys_polled(-1, TL_WR1041NV2_KEYS_POLL_INTERVAL,
  22398. + ARRAY_SIZE(tl_wr1041nv2_gpio_keys),
  22399. + tl_wr1041nv2_gpio_keys);
  22400. + ath79_register_wmac(ee, mac);
  22401. +
  22402. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  22403. + AR934X_ETH_CFG_SW_ONLY_MODE);
  22404. +
  22405. + ath79_register_mdio(1, 0x0);
  22406. + ath79_register_mdio(0, 0x0);
  22407. +
  22408. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  22409. +
  22410. + mdiobus_register_board_info(db120_mdio0_info,
  22411. + ARRAY_SIZE(db120_mdio0_info));
  22412. +
  22413. + /* GMAC0 is connected to an AR8327 switch */
  22414. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  22415. + ath79_eth0_data.phy_mask = BIT(0);
  22416. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  22417. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  22418. + ath79_register_eth(0);
  22419. +}
  22420. +
  22421. +MIPS_MACHINE(ATH79_MACH_TL_WR1041N_V2, "TL-WR1041N-v2",
  22422. + "TP-LINK TL-WR1041N v2", tl_wr1041nv2_setup);
  22423. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr1043nd-v2.c linux-4.1.43/arch/mips/ath79/mach-tl-wr1043nd-v2.c
  22424. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr1043nd-v2.c 1970-01-01 01:00:00.000000000 +0100
  22425. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr1043nd-v2.c 2017-08-06 20:02:15.000000000 +0200
  22426. @@ -0,0 +1,215 @@
  22427. +/*
  22428. + * TP-LINK TL-WR1043ND v2 board support
  22429. + *
  22430. + * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
  22431. + *
  22432. + * Based on the Qualcomm Atheros AP135/AP136 reference board support code
  22433. + * Copyright (c) 2012 Qualcomm Atheros
  22434. + *
  22435. + * Permission to use, copy, modify, and/or distribute this software for any
  22436. + * purpose with or without fee is hereby granted, provided that the above
  22437. + * copyright notice and this permission notice appear in all copies.
  22438. + *
  22439. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  22440. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  22441. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  22442. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  22443. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  22444. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  22445. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  22446. + *
  22447. + */
  22448. +
  22449. +#include <linux/phy.h>
  22450. +#include <linux/gpio.h>
  22451. +#include <linux/platform_device.h>
  22452. +#include <linux/ar8216_platform.h>
  22453. +
  22454. +#include <asm/mach-ath79/ar71xx_regs.h>
  22455. +
  22456. +#include "common.h"
  22457. +#include "dev-eth.h"
  22458. +#include "dev-gpio-buttons.h"
  22459. +#include "dev-leds-gpio.h"
  22460. +#include "dev-m25p80.h"
  22461. +#include "dev-spi.h"
  22462. +#include "dev-usb.h"
  22463. +#include "dev-wmac.h"
  22464. +#include "machtypes.h"
  22465. +
  22466. +#define TL_WR1043_V2_GPIO_LED_WLAN 12
  22467. +#define TL_WR1043_V2_GPIO_LED_USB 15
  22468. +#define TL_WR1043_V2_GPIO_LED_WPS 18
  22469. +#define TL_WR1043_V2_GPIO_LED_SYSTEM 19
  22470. +
  22471. +#define TL_WR1043_V2_GPIO_BTN_RESET 16
  22472. +#define TL_WR1043_V2_GPIO_BTN_RFKILL 17
  22473. +
  22474. +#define TL_WR1043_V2_GPIO_USB_POWER 21
  22475. +
  22476. +#define TL_WR1043_V2_KEYS_POLL_INTERVAL 20 /* msecs */
  22477. +#define TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043_V2_KEYS_POLL_INTERVAL)
  22478. +
  22479. +#define TL_WR1043_V2_WMAC_CALDATA_OFFSET 0x1000
  22480. +
  22481. +static const char *wr1043nd_v2_part_probes[] = {
  22482. + "tp-link",
  22483. + NULL,
  22484. +};
  22485. +
  22486. +static struct flash_platform_data wr1043nd_v2_flash_data = {
  22487. + .part_probes = wr1043nd_v2_part_probes,
  22488. +};
  22489. +
  22490. +static struct gpio_led tl_wr1043_v2_leds_gpio[] __initdata = {
  22491. + {
  22492. + .name = "tp-link:green:wps",
  22493. + .gpio = TL_WR1043_V2_GPIO_LED_WPS,
  22494. + .active_low = 1,
  22495. + },
  22496. + {
  22497. + .name = "tp-link:green:system",
  22498. + .gpio = TL_WR1043_V2_GPIO_LED_SYSTEM,
  22499. + .active_low = 1,
  22500. + },
  22501. + {
  22502. + .name = "tp-link:green:wlan",
  22503. + .gpio = TL_WR1043_V2_GPIO_LED_WLAN,
  22504. + .active_low = 1,
  22505. + },
  22506. + {
  22507. + .name = "tp-link:green:usb",
  22508. + .gpio = TL_WR1043_V2_GPIO_LED_USB,
  22509. + .active_low = 1,
  22510. + },
  22511. +};
  22512. +
  22513. +static struct gpio_keys_button tl_wr1043_v2_gpio_keys[] __initdata = {
  22514. + {
  22515. + .desc = "Reset button",
  22516. + .type = EV_KEY,
  22517. + .code = KEY_RESTART,
  22518. + .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL,
  22519. + .gpio = TL_WR1043_V2_GPIO_BTN_RESET,
  22520. + .active_low = 1,
  22521. + },
  22522. + {
  22523. + .desc = "RFKILL button",
  22524. + .type = EV_KEY,
  22525. + .code = KEY_RFKILL,
  22526. + .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL,
  22527. + .gpio = TL_WR1043_V2_GPIO_BTN_RFKILL,
  22528. + .active_low = 1,
  22529. + },
  22530. +};
  22531. +
  22532. +static const struct ar8327_led_info tl_wr1043_leds_ar8327[] = {
  22533. + AR8327_LED_INFO(PHY0_0, HW, "tp-link:green:lan4"),
  22534. + AR8327_LED_INFO(PHY1_0, HW, "tp-link:green:lan3"),
  22535. + AR8327_LED_INFO(PHY2_0, HW, "tp-link:green:lan2"),
  22536. + AR8327_LED_INFO(PHY3_0, HW, "tp-link:green:lan1"),
  22537. + AR8327_LED_INFO(PHY4_0, HW, "tp-link:green:wan"),
  22538. +};
  22539. +
  22540. +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
  22541. +static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad0_cfg = {
  22542. + .mode = AR8327_PAD_MAC_SGMII,
  22543. + .sgmii_delay_en = true,
  22544. +};
  22545. +
  22546. +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
  22547. +static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad6_cfg = {
  22548. + .mode = AR8327_PAD_MAC_RGMII,
  22549. + .txclk_delay_en = true,
  22550. + .rxclk_delay_en = true,
  22551. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  22552. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  22553. +};
  22554. +
  22555. +static struct ar8327_led_cfg wr1043nd_v2_ar8327_led_cfg = {
  22556. + .led_ctrl0 = 0xcc35cc35,
  22557. + .led_ctrl1 = 0xca35ca35,
  22558. + .led_ctrl2 = 0xc935c935,
  22559. + .led_ctrl3 = 0x03ffff00,
  22560. + .open_drain = true,
  22561. +};
  22562. +
  22563. +static struct ar8327_platform_data wr1043nd_v2_ar8327_data = {
  22564. + .pad0_cfg = &wr1043nd_v2_ar8327_pad0_cfg,
  22565. + .pad6_cfg = &wr1043nd_v2_ar8327_pad6_cfg,
  22566. + .port0_cfg = {
  22567. + .force_link = 1,
  22568. + .speed = AR8327_PORT_SPEED_1000,
  22569. + .duplex = 1,
  22570. + .txpause = 1,
  22571. + .rxpause = 1,
  22572. + },
  22573. + .port6_cfg = {
  22574. + .force_link = 1,
  22575. + .speed = AR8327_PORT_SPEED_1000,
  22576. + .duplex = 1,
  22577. + .txpause = 1,
  22578. + .rxpause = 1,
  22579. + },
  22580. + .led_cfg = &wr1043nd_v2_ar8327_led_cfg,
  22581. + .num_leds = ARRAY_SIZE(tl_wr1043_leds_ar8327),
  22582. + .leds = tl_wr1043_leds_ar8327,
  22583. +};
  22584. +
  22585. +static struct mdio_board_info wr1043nd_v2_mdio0_info[] = {
  22586. + {
  22587. + .bus_id = "ag71xx-mdio.0",
  22588. + .phy_addr = 0,
  22589. + .platform_data = &wr1043nd_v2_ar8327_data,
  22590. + },
  22591. +};
  22592. +
  22593. +static void __init tl_wr1043nd_v2_setup(void)
  22594. +{
  22595. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  22596. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  22597. +
  22598. + ath79_register_m25p80(&wr1043nd_v2_flash_data);
  22599. +
  22600. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio),
  22601. + tl_wr1043_v2_leds_gpio);
  22602. + ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL,
  22603. + ARRAY_SIZE(tl_wr1043_v2_gpio_keys),
  22604. + tl_wr1043_v2_gpio_keys);
  22605. +
  22606. + ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac);
  22607. +
  22608. + mdiobus_register_board_info(wr1043nd_v2_mdio0_info,
  22609. + ARRAY_SIZE(wr1043nd_v2_mdio0_info));
  22610. + ath79_register_mdio(0, 0x0);
  22611. +
  22612. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  22613. +
  22614. + /* GMAC0 is connected to the RMGII interface */
  22615. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  22616. + ath79_eth0_data.phy_mask = BIT(0);
  22617. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  22618. + ath79_eth0_pll_data.pll_1000 = 0x56000000;
  22619. +
  22620. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  22621. + ath79_register_eth(0);
  22622. +
  22623. + /* GMAC1 is connected to the SGMII interface */
  22624. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  22625. + ath79_eth1_data.speed = SPEED_1000;
  22626. + ath79_eth1_data.duplex = DUPLEX_FULL;
  22627. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  22628. +
  22629. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  22630. + ath79_register_eth(1);
  22631. +
  22632. + ath79_register_usb();
  22633. +
  22634. + gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER,
  22635. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  22636. + "USB power");
  22637. +}
  22638. +
  22639. +MIPS_MACHINE(ATH79_MACH_TL_WR1043ND_V2, "TL-WR1043ND-v2",
  22640. + "TP-LINK TL-WR1043ND v2", tl_wr1043nd_v2_setup);
  22641. +
  22642. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr1043nd.c linux-4.1.43/arch/mips/ath79/mach-tl-wr1043nd.c
  22643. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr1043nd.c 1970-01-01 01:00:00.000000000 +0100
  22644. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr1043nd.c 2017-08-06 20:02:15.000000000 +0200
  22645. @@ -0,0 +1,141 @@
  22646. +/*
  22647. + * TP-LINK TL-WR1043N/ND board support
  22648. + *
  22649. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  22650. + *
  22651. + * This program is free software; you can redistribute it and/or modify it
  22652. + * under the terms of the GNU General Public License version 2 as published
  22653. + * by the Free Software Foundation.
  22654. + */
  22655. +
  22656. +#include <linux/platform_device.h>
  22657. +#include <linux/rtl8366.h>
  22658. +
  22659. +#include <asm/mach-ath79/ath79.h>
  22660. +#include <asm/mach-ath79/ar71xx_regs.h>
  22661. +
  22662. +#include "dev-eth.h"
  22663. +#include "dev-m25p80.h"
  22664. +#include "dev-gpio-buttons.h"
  22665. +#include "dev-leds-gpio.h"
  22666. +#include "dev-usb.h"
  22667. +#include "dev-wmac.h"
  22668. +#include "machtypes.h"
  22669. +
  22670. +#define TL_WR1043ND_GPIO_LED_USB 1
  22671. +#define TL_WR1043ND_GPIO_LED_SYSTEM 2
  22672. +#define TL_WR1043ND_GPIO_LED_QSS 5
  22673. +#define TL_WR1043ND_GPIO_LED_WLAN 9
  22674. +
  22675. +#define TL_WR1043ND_GPIO_BTN_RESET 3
  22676. +#define TL_WR1043ND_GPIO_BTN_QSS 7
  22677. +
  22678. +#define TL_WR1043ND_GPIO_RTL8366_SDA 18
  22679. +#define TL_WR1043ND_GPIO_RTL8366_SCK 19
  22680. +
  22681. +#define TL_WR1043ND_KEYS_POLL_INTERVAL 20 /* msecs */
  22682. +#define TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043ND_KEYS_POLL_INTERVAL)
  22683. +
  22684. +static const char *tl_wr1043nd_part_probes[] = {
  22685. + "tp-link",
  22686. + NULL,
  22687. +};
  22688. +
  22689. +static struct flash_platform_data tl_wr1043nd_flash_data = {
  22690. + .part_probes = tl_wr1043nd_part_probes,
  22691. +};
  22692. +
  22693. +static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = {
  22694. + {
  22695. + .name = "tp-link:green:usb",
  22696. + .gpio = TL_WR1043ND_GPIO_LED_USB,
  22697. + .active_low = 1,
  22698. + }, {
  22699. + .name = "tp-link:green:system",
  22700. + .gpio = TL_WR1043ND_GPIO_LED_SYSTEM,
  22701. + .active_low = 1,
  22702. + }, {
  22703. + .name = "tp-link:green:qss",
  22704. + .gpio = TL_WR1043ND_GPIO_LED_QSS,
  22705. + .active_low = 0,
  22706. + }, {
  22707. + .name = "tp-link:green:wlan",
  22708. + .gpio = TL_WR1043ND_GPIO_LED_WLAN,
  22709. + .active_low = 1,
  22710. + }
  22711. +};
  22712. +
  22713. +static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = {
  22714. + {
  22715. + .desc = "reset",
  22716. + .type = EV_KEY,
  22717. + .code = KEY_RESTART,
  22718. + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL,
  22719. + .gpio = TL_WR1043ND_GPIO_BTN_RESET,
  22720. + .active_low = 1,
  22721. + }, {
  22722. + .desc = "qss",
  22723. + .type = EV_KEY,
  22724. + .code = KEY_WPS_BUTTON,
  22725. + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL,
  22726. + .gpio = TL_WR1043ND_GPIO_BTN_QSS,
  22727. + .active_low = 1,
  22728. + }
  22729. +};
  22730. +
  22731. +static void tl_wr1043nd_rtl8366rb_hw_reset(bool active)
  22732. +{
  22733. + if (active)
  22734. + ath79_device_reset_set(AR71XX_RESET_GE0_PHY);
  22735. + else
  22736. + ath79_device_reset_clear(AR71XX_RESET_GE0_PHY);
  22737. +}
  22738. +
  22739. +static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = {
  22740. + .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA,
  22741. + .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK,
  22742. + .hw_reset = tl_wr1043nd_rtl8366rb_hw_reset,
  22743. +};
  22744. +
  22745. +static struct platform_device tl_wr1043nd_rtl8366rb_device = {
  22746. + .name = RTL8366RB_DRIVER_NAME,
  22747. + .id = -1,
  22748. + .dev = {
  22749. + .platform_data = &tl_wr1043nd_rtl8366rb_data,
  22750. + }
  22751. +};
  22752. +
  22753. +static void __init tl_wr1043nd_setup(void)
  22754. +{
  22755. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  22756. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  22757. +
  22758. + tl_wr1043nd_rtl8366rb_hw_reset(true);
  22759. +
  22760. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  22761. + ath79_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev;
  22762. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  22763. + ath79_eth0_data.speed = SPEED_1000;
  22764. + ath79_eth0_data.duplex = DUPLEX_FULL;
  22765. + ath79_eth0_pll_data.pll_1000 = 0x1a000000;
  22766. +
  22767. + ath79_register_eth(0);
  22768. +
  22769. + ath79_register_usb();
  22770. +
  22771. + ath79_register_m25p80(&tl_wr1043nd_flash_data);
  22772. +
  22773. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio),
  22774. + tl_wr1043nd_leds_gpio);
  22775. +
  22776. + platform_device_register(&tl_wr1043nd_rtl8366rb_device);
  22777. +
  22778. + ath79_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL,
  22779. + ARRAY_SIZE(tl_wr1043nd_gpio_keys),
  22780. + tl_wr1043nd_gpio_keys);
  22781. +
  22782. + ath79_register_wmac(eeprom, mac);
  22783. +}
  22784. +
  22785. +MIPS_MACHINE(ATH79_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND",
  22786. + tl_wr1043nd_setup);
  22787. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr2543n.c linux-4.1.43/arch/mips/ath79/mach-tl-wr2543n.c
  22788. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr2543n.c 1970-01-01 01:00:00.000000000 +0100
  22789. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr2543n.c 2017-08-06 20:02:15.000000000 +0200
  22790. @@ -0,0 +1,156 @@
  22791. +/*
  22792. + * TP-LINK TL-WR2543N/ND board support
  22793. + *
  22794. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  22795. + *
  22796. + * This program is free software; you can redistribute it and/or modify it
  22797. + * under the terms of the GNU General Public License version 2 as published
  22798. + * by the Free Software Foundation.
  22799. + */
  22800. +
  22801. +#include <linux/platform_device.h>
  22802. +#include <linux/rtl8367.h>
  22803. +
  22804. +#include <asm/mach-ath79/ath79.h>
  22805. +
  22806. +#include "dev-eth.h"
  22807. +#include "dev-ap9x-pci.h"
  22808. +#include "dev-gpio-buttons.h"
  22809. +#include "dev-leds-gpio.h"
  22810. +#include "dev-m25p80.h"
  22811. +#include "dev-usb.h"
  22812. +#include "machtypes.h"
  22813. +
  22814. +#define TL_WR2543N_GPIO_LED_WPS 0
  22815. +#define TL_WR2543N_GPIO_LED_USB 8
  22816. +
  22817. +/* The WLAN LEDs use GPIOs on the discrete AR9380 wmac */
  22818. +#define TL_WR2543N_GPIO_WMAC_LED_WLAN2G 0
  22819. +#define TL_WR2543N_GPIO_WMAC_LED_WLAN5G 1
  22820. +
  22821. +#define TL_WR2543N_GPIO_BTN_RESET 11
  22822. +#define TL_WR2543N_GPIO_BTN_WPS 12
  22823. +
  22824. +#define TL_WR2543N_GPIO_RTL8367_SDA 1
  22825. +#define TL_WR2543N_GPIO_RTL8367_SCK 6
  22826. +
  22827. +#define TL_WR2543N_KEYS_POLL_INTERVAL 20 /* msecs */
  22828. +#define TL_WR2543N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR2543N_KEYS_POLL_INTERVAL)
  22829. +
  22830. +static const char *tl_wr2543n_part_probes[] = {
  22831. + "tp-link",
  22832. + NULL,
  22833. +};
  22834. +
  22835. +static struct flash_platform_data tl_wr2543n_flash_data = {
  22836. + .part_probes = tl_wr2543n_part_probes,
  22837. +};
  22838. +
  22839. +static struct gpio_led tl_wr2543n_leds_gpio[] __initdata = {
  22840. + {
  22841. + .name = "tp-link:green:usb",
  22842. + .gpio = TL_WR2543N_GPIO_LED_USB,
  22843. + .active_low = 1,
  22844. + }, {
  22845. + .name = "tp-link:green:wps",
  22846. + .gpio = TL_WR2543N_GPIO_LED_WPS,
  22847. + .active_low = 1,
  22848. + }
  22849. +};
  22850. +
  22851. +static struct gpio_led tl_wr2543n_wmac_leds_gpio[] = {
  22852. + {
  22853. + .name = "tp-link:green:wlan5g",
  22854. + .gpio = TL_WR2543N_GPIO_WMAC_LED_WLAN5G,
  22855. + .active_low = 1,
  22856. + },
  22857. +};
  22858. +
  22859. +static struct gpio_keys_button tl_wr2543n_gpio_keys[] __initdata = {
  22860. + {
  22861. + .desc = "reset",
  22862. + .type = EV_KEY,
  22863. + .code = KEY_RESTART,
  22864. + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL,
  22865. + .gpio = TL_WR2543N_GPIO_BTN_RESET,
  22866. + .active_low = 1,
  22867. + }, {
  22868. + .desc = "wps",
  22869. + .type = EV_KEY,
  22870. + .code = KEY_WPS_BUTTON,
  22871. + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL,
  22872. + .gpio = TL_WR2543N_GPIO_BTN_WPS,
  22873. + .active_low = 1,
  22874. + }
  22875. +};
  22876. +
  22877. +static struct rtl8367_extif_config tl_wr2543n_rtl8367_extif0_cfg = {
  22878. + .mode = RTL8367_EXTIF_MODE_RGMII,
  22879. + .txdelay = 1,
  22880. + .rxdelay = 0,
  22881. + .ability = {
  22882. + .force_mode = 1,
  22883. + .txpause = 1,
  22884. + .rxpause = 1,
  22885. + .link = 1,
  22886. + .duplex = 1,
  22887. + .speed = RTL8367_PORT_SPEED_1000,
  22888. + },
  22889. +};
  22890. +
  22891. +static struct rtl8367_platform_data tl_wr2543n_rtl8367_data = {
  22892. + .gpio_sda = TL_WR2543N_GPIO_RTL8367_SDA,
  22893. + .gpio_sck = TL_WR2543N_GPIO_RTL8367_SCK,
  22894. + .extif0_cfg = &tl_wr2543n_rtl8367_extif0_cfg,
  22895. +};
  22896. +
  22897. +static struct platform_device tl_wr2543n_rtl8367_device = {
  22898. + .name = RTL8367_DRIVER_NAME,
  22899. + .id = -1,
  22900. + .dev = {
  22901. + .platform_data = &tl_wr2543n_rtl8367_data,
  22902. + }
  22903. +};
  22904. +
  22905. +static void __init tl_wr2543n_setup(void)
  22906. +{
  22907. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  22908. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  22909. +
  22910. + ath79_register_m25p80(&tl_wr2543n_flash_data);
  22911. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr2543n_leds_gpio),
  22912. + tl_wr2543n_leds_gpio);
  22913. + ath79_register_gpio_keys_polled(-1, TL_WR2543N_KEYS_POLL_INTERVAL,
  22914. + ARRAY_SIZE(tl_wr2543n_gpio_keys),
  22915. + tl_wr2543n_gpio_keys);
  22916. + ath79_register_usb();
  22917. +
  22918. + /*
  22919. + * The ath9k driver uses this pin for its default led device, which is
  22920. + * named ath9k-phy0, and reflects activity on either the 2 GHz or 5 GHz
  22921. + * bands. This pin is connected to the WR2543's 2GHz WLAN LED.
  22922. + */
  22923. + ap9x_pci_setup_wmac_led_pin(0, TL_WR2543N_GPIO_WMAC_LED_WLAN2G);
  22924. +
  22925. + /*
  22926. + * We also have the driver set up an led device for the WR2543's
  22927. + * separate 5 GHz WLAN LED in case the user wants it.
  22928. + */
  22929. + ap9x_pci_setup_wmac_leds(0, tl_wr2543n_wmac_leds_gpio,
  22930. + ARRAY_SIZE(tl_wr2543n_wmac_leds_gpio));
  22931. + ap91_pci_init(eeprom, mac);
  22932. +
  22933. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
  22934. + ath79_eth0_data.mii_bus_dev = &tl_wr2543n_rtl8367_device.dev;
  22935. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  22936. + ath79_eth0_data.speed = SPEED_1000;
  22937. + ath79_eth0_data.duplex = DUPLEX_FULL;
  22938. + ath79_eth0_pll_data.pll_1000 = 0x1a000000;
  22939. +
  22940. + ath79_register_eth(0);
  22941. +
  22942. + platform_device_register(&tl_wr2543n_rtl8367_device);
  22943. +}
  22944. +
  22945. +MIPS_MACHINE(ATH79_MACH_TL_WR2543N, "TL-WR2543N", "TP-LINK TL-WR2543N/ND",
  22946. + tl_wr2543n_setup);
  22947. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr703n.c linux-4.1.43/arch/mips/ath79/mach-tl-wr703n.c
  22948. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr703n.c 1970-01-01 01:00:00.000000000 +0100
  22949. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr703n.c 2017-08-06 20:02:15.000000000 +0200
  22950. @@ -0,0 +1,118 @@
  22951. +/*
  22952. + * TP-LINK TL-WR703N/TL-MR10U board support
  22953. + *
  22954. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  22955. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  22956. + *
  22957. + * This program is free software; you can redistribute it and/or modify it
  22958. + * under the terms of the GNU General Public License version 2 as published
  22959. + * by the Free Software Foundation.
  22960. + */
  22961. +
  22962. +#include <linux/gpio.h>
  22963. +
  22964. +#include <asm/mach-ath79/ath79.h>
  22965. +
  22966. +#include "dev-eth.h"
  22967. +#include "dev-gpio-buttons.h"
  22968. +#include "dev-leds-gpio.h"
  22969. +#include "dev-m25p80.h"
  22970. +#include "dev-usb.h"
  22971. +#include "dev-wmac.h"
  22972. +#include "machtypes.h"
  22973. +
  22974. +#define TL_WR703N_GPIO_LED_SYSTEM 27
  22975. +#define TL_WR703N_GPIO_BTN_RESET 11
  22976. +
  22977. +#define TL_WR703N_GPIO_USB_POWER 8
  22978. +
  22979. +#define TL_MR10U_GPIO_USB_POWER 18
  22980. +
  22981. +#define TL_WR703N_KEYS_POLL_INTERVAL 20 /* msecs */
  22982. +#define TL_WR703N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR703N_KEYS_POLL_INTERVAL)
  22983. +
  22984. +static const char *tl_wr703n_part_probes[] = {
  22985. + "tp-link",
  22986. + NULL,
  22987. +};
  22988. +
  22989. +static struct flash_platform_data tl_wr703n_flash_data = {
  22990. + .part_probes = tl_wr703n_part_probes,
  22991. +};
  22992. +
  22993. +static struct gpio_led tl_wr703n_leds_gpio[] __initdata = {
  22994. + {
  22995. + .name = "tp-link:blue:system",
  22996. + .gpio = TL_WR703N_GPIO_LED_SYSTEM,
  22997. + .active_low = 1,
  22998. + },
  22999. +};
  23000. +
  23001. +static struct gpio_keys_button tl_wr703n_gpio_keys[] __initdata = {
  23002. + {
  23003. + .desc = "reset",
  23004. + .type = EV_KEY,
  23005. + .code = KEY_RESTART,
  23006. + .debounce_interval = TL_WR703N_KEYS_DEBOUNCE_INTERVAL,
  23007. + .gpio = TL_WR703N_GPIO_BTN_RESET,
  23008. + .active_low = 0,
  23009. + }
  23010. +};
  23011. +
  23012. +static void __init common_setup(unsigned usb_power_gpio, bool sec_ethernet)
  23013. +{
  23014. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  23015. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  23016. +
  23017. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  23018. + ath79_setup_ar933x_phy4_switch(false, false);
  23019. +
  23020. + ath79_register_m25p80(&tl_wr703n_flash_data);
  23021. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio),
  23022. + tl_wr703n_leds_gpio);
  23023. + ath79_register_gpio_keys_polled(-1, TL_WR703N_KEYS_POLL_INTERVAL,
  23024. + ARRAY_SIZE(tl_wr703n_gpio_keys),
  23025. + tl_wr703n_gpio_keys);
  23026. +
  23027. + gpio_request_one(usb_power_gpio,
  23028. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  23029. + "USB power");
  23030. + ath79_register_usb();
  23031. +
  23032. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  23033. +
  23034. + ath79_register_mdio(0, 0x0);
  23035. + ath79_register_eth(0);
  23036. +
  23037. + if (sec_ethernet)
  23038. + {
  23039. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  23040. + ath79_register_eth(1);
  23041. + }
  23042. +
  23043. + ath79_register_wmac(ee, mac);
  23044. +}
  23045. +
  23046. +static void __init tl_mr10u_setup(void)
  23047. +{
  23048. + common_setup(TL_MR10U_GPIO_USB_POWER, false);
  23049. +}
  23050. +
  23051. +MIPS_MACHINE(ATH79_MACH_TL_MR10U, "TL-MR10U", "TP-LINK TL-MR10U",
  23052. + tl_mr10u_setup);
  23053. +
  23054. +static void __init tl_wr703n_setup(void)
  23055. +{
  23056. + common_setup(TL_WR703N_GPIO_USB_POWER, false);
  23057. +}
  23058. +
  23059. +MIPS_MACHINE(ATH79_MACH_TL_WR703N, "TL-WR703N", "TP-LINK TL-WR703N v1",
  23060. + tl_wr703n_setup);
  23061. +
  23062. +static void __init tl_wr710n_setup(void)
  23063. +{
  23064. + common_setup(TL_WR703N_GPIO_USB_POWER, true);
  23065. +}
  23066. +
  23067. +MIPS_MACHINE(ATH79_MACH_TL_WR710N, "TL-WR710N", "TP-LINK TL-WR710N v1",
  23068. + tl_wr710n_setup);
  23069. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr720n-v3.c linux-4.1.43/arch/mips/ath79/mach-tl-wr720n-v3.c
  23070. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr720n-v3.c 1970-01-01 01:00:00.000000000 +0100
  23071. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr720n-v3.c 2017-08-06 20:02:15.000000000 +0200
  23072. @@ -0,0 +1,108 @@
  23073. +/*
  23074. + * TP-LINK TL-WR720N board support
  23075. + *
  23076. + * Copyright (C) 2011 dongyuqi <729650915@qq.com>
  23077. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  23078. + * Copyright (C) 2013 yousong <yszhou4tech@gmail.com>
  23079. + *
  23080. + * This program is free software; you can redistribute it and/or modify it
  23081. + * under the terms of the GNU General Public License version 2 as published
  23082. + * by the Free Software Foundation.
  23083. + */
  23084. +
  23085. +#include <linux/gpio.h>
  23086. +
  23087. +#include <asm/mach-ath79/ath79.h>
  23088. +
  23089. +#include "dev-eth.h"
  23090. +#include "dev-gpio-buttons.h"
  23091. +#include "dev-leds-gpio.h"
  23092. +#include "dev-m25p80.h"
  23093. +#include "dev-usb.h"
  23094. +#include "dev-wmac.h"
  23095. +#include "machtypes.h"
  23096. +
  23097. +#define TL_WR720N_GPIO_LED_SYSTEM 27
  23098. +#define TL_WR720N_GPIO_BTN_RESET 11
  23099. +#define TL_WR720N_GPIO_BTN_SW1 18
  23100. +#define TL_WR720N_GPIO_BTN_SW2 20
  23101. +
  23102. +#define TL_WR720N_GPIO_USB_POWER 8
  23103. +
  23104. +#define TL_WR720N_KEYS_POLL_INTERVAL 20 /* msecs */
  23105. +#define TL_WR720N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR720N_KEYS_POLL_INTERVAL)
  23106. +
  23107. +static const char *tl_wr720n_part_probes[] = {
  23108. + "tp-link",
  23109. + NULL,
  23110. +};
  23111. +
  23112. +static struct flash_platform_data tl_wr720n_flash_data = {
  23113. + .part_probes = tl_wr720n_part_probes,
  23114. +};
  23115. +
  23116. +static struct gpio_led tl_wr720n_leds_gpio[] __initdata = {
  23117. + {
  23118. + .name = "tp-link:blue:system",
  23119. + .gpio = TL_WR720N_GPIO_LED_SYSTEM,
  23120. + .active_low = 1,
  23121. + },
  23122. +};
  23123. +
  23124. +static struct gpio_keys_button tl_wr720n_gpio_keys[] __initdata = {
  23125. + {
  23126. + .desc = "reset",
  23127. + .type = EV_KEY,
  23128. + .code = KEY_RESTART,
  23129. + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL,
  23130. + .gpio = TL_WR720N_GPIO_BTN_RESET,
  23131. + .active_low = 0,
  23132. + }, {
  23133. + .desc = "sw1",
  23134. + .type = EV_KEY,
  23135. + .code = BTN_0,
  23136. + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL,
  23137. + .gpio = TL_WR720N_GPIO_BTN_SW1,
  23138. + .active_low = 0,
  23139. + }, {
  23140. + .desc = "sw2",
  23141. + .type = EV_KEY,
  23142. + .code = BTN_1,
  23143. + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL,
  23144. + .gpio = TL_WR720N_GPIO_BTN_SW2,
  23145. + .active_low = 0,
  23146. + }
  23147. +};
  23148. +
  23149. +static void __init tl_wr720n_v3_setup(void)
  23150. +{
  23151. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  23152. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  23153. +
  23154. + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
  23155. + ath79_setup_ar933x_phy4_switch(false, false);
  23156. +
  23157. + ath79_register_m25p80(&tl_wr720n_flash_data);
  23158. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr720n_leds_gpio),
  23159. + tl_wr720n_leds_gpio);
  23160. + ath79_register_gpio_keys_polled(-1, TL_WR720N_KEYS_POLL_INTERVAL,
  23161. + ARRAY_SIZE(tl_wr720n_gpio_keys),
  23162. + tl_wr720n_gpio_keys);
  23163. +
  23164. + gpio_request_one(TL_WR720N_GPIO_USB_POWER,
  23165. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  23166. + "USB power");
  23167. + ath79_register_usb();
  23168. +
  23169. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  23170. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2);
  23171. +
  23172. + ath79_register_mdio(0, 0x0);
  23173. + ath79_register_eth(0);
  23174. + ath79_register_eth(1);
  23175. +
  23176. + ath79_register_wmac(ee, mac);
  23177. +}
  23178. +
  23179. +MIPS_MACHINE(ATH79_MACH_TL_WR720N_V3, "TL-WR720N-v3", "TP-LINK TL-WR720N v3/v4",
  23180. + tl_wr720n_v3_setup);
  23181. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr741nd-v4.c linux-4.1.43/arch/mips/ath79/mach-tl-wr741nd-v4.c
  23182. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr741nd-v4.c 1970-01-01 01:00:00.000000000 +0100
  23183. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr741nd-v4.c 2017-08-06 20:02:15.000000000 +0200
  23184. @@ -0,0 +1,187 @@
  23185. +/*
  23186. + * TP-LINK TL-WR741ND v4/TL-MR3220 v2 board support
  23187. + *
  23188. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  23189. + *
  23190. + * This program is free software; you can redistribute it and/or modify it
  23191. + * under the terms of the GNU General Public License version 2 as published
  23192. + * by the Free Software Foundation.
  23193. + */
  23194. +
  23195. +#include <linux/gpio.h>
  23196. +
  23197. +#include <asm/mach-ath79/ath79.h>
  23198. +#include <asm/mach-ath79/ar71xx_regs.h>
  23199. +
  23200. +#include "common.h"
  23201. +#include "dev-eth.h"
  23202. +#include "dev-gpio-buttons.h"
  23203. +#include "dev-leds-gpio.h"
  23204. +#include "dev-m25p80.h"
  23205. +#include "dev-usb.h"
  23206. +#include "dev-wmac.h"
  23207. +#include "machtypes.h"
  23208. +
  23209. +#define TL_WR741NDV4_GPIO_BTN_RESET 11
  23210. +#define TL_WR741NDV4_GPIO_BTN_WPS 26
  23211. +
  23212. +#define TL_WR741NDV4_GPIO_LED_WLAN 0
  23213. +#define TL_WR741NDV4_GPIO_LED_QSS 1
  23214. +#define TL_WR741NDV4_GPIO_LED_WAN 13
  23215. +#define TL_WR741NDV4_GPIO_LED_LAN1 14
  23216. +#define TL_WR741NDV4_GPIO_LED_LAN2 15
  23217. +#define TL_WR741NDV4_GPIO_LED_LAN3 16
  23218. +#define TL_WR741NDV4_GPIO_LED_LAN4 17
  23219. +#define TL_WR741NDV4_GPIO_LED_SYSTEM 27
  23220. +
  23221. +#define TL_MR3220V2_GPIO_BTN_WPS 11
  23222. +#define TL_MR3220V2_GPIO_BTN_WIFI 24
  23223. +
  23224. +#define TL_MR3220V2_GPIO_LED_3G 26
  23225. +#define TL_MR3220V2_GPIO_USB_POWER 8
  23226. +
  23227. +#define TL_WR741NDV4_KEYS_POLL_INTERVAL 20 /* msecs */
  23228. +#define TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741NDV4_KEYS_POLL_INTERVAL)
  23229. +
  23230. +static const char *tl_wr741ndv4_part_probes[] = {
  23231. + "tp-link",
  23232. + NULL,
  23233. +};
  23234. +
  23235. +static struct flash_platform_data tl_wr741ndv4_flash_data = {
  23236. + .part_probes = tl_wr741ndv4_part_probes,
  23237. +};
  23238. +
  23239. +static struct gpio_led tl_wr741ndv4_leds_gpio[] __initdata = {
  23240. + {
  23241. + .name = "tp-link:green:lan1",
  23242. + .gpio = TL_WR741NDV4_GPIO_LED_LAN1,
  23243. + .active_low = 0,
  23244. + }, {
  23245. + .name = "tp-link:green:lan2",
  23246. + .gpio = TL_WR741NDV4_GPIO_LED_LAN2,
  23247. + .active_low = 0,
  23248. + }, {
  23249. + .name = "tp-link:green:lan3",
  23250. + .gpio = TL_WR741NDV4_GPIO_LED_LAN3,
  23251. + .active_low = 0,
  23252. + }, {
  23253. + .name = "tp-link:green:lan4",
  23254. + .gpio = TL_WR741NDV4_GPIO_LED_LAN4,
  23255. + .active_low = 1,
  23256. + }, {
  23257. + .name = "tp-link:green:qss",
  23258. + .gpio = TL_WR741NDV4_GPIO_LED_QSS,
  23259. + .active_low = 0,
  23260. + }, {
  23261. + .name = "tp-link:green:system",
  23262. + .gpio = TL_WR741NDV4_GPIO_LED_SYSTEM,
  23263. + .active_low = 1,
  23264. + }, {
  23265. + .name = "tp-link:green:wan",
  23266. + .gpio = TL_WR741NDV4_GPIO_LED_WAN,
  23267. + .active_low = 0,
  23268. + }, {
  23269. + .name = "tp-link:green:wlan",
  23270. + .gpio = TL_WR741NDV4_GPIO_LED_WLAN,
  23271. + .active_low = 0,
  23272. + }, {
  23273. + /* the 3G LED is only present on the MR3220 v2 */
  23274. + .name = "tp-link:green:3g",
  23275. + .gpio = TL_MR3220V2_GPIO_LED_3G,
  23276. + .active_low = 0,
  23277. + },
  23278. +};
  23279. +
  23280. +static struct gpio_keys_button tl_wr741ndv4_gpio_keys[] __initdata = {
  23281. + {
  23282. + .desc = "reset",
  23283. + .type = EV_KEY,
  23284. + .code = KEY_RESTART,
  23285. + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL,
  23286. + .gpio = TL_WR741NDV4_GPIO_BTN_RESET,
  23287. + .active_low = 0,
  23288. + }, {
  23289. + .desc = "WPS",
  23290. + .type = EV_KEY,
  23291. + .code = KEY_WPS_BUTTON,
  23292. + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL,
  23293. + .gpio = TL_WR741NDV4_GPIO_BTN_WPS,
  23294. + .active_low = 0,
  23295. + }
  23296. +};
  23297. +
  23298. +static struct gpio_keys_button tl_mr3220v2_gpio_keys[] __initdata = {
  23299. + {
  23300. + .desc = "WPS",
  23301. + .type = EV_KEY,
  23302. + .code = KEY_WPS_BUTTON,
  23303. + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL,
  23304. + .gpio = TL_MR3220V2_GPIO_BTN_WPS,
  23305. + .active_low = 0,
  23306. + }, {
  23307. + .desc = "WIFI button",
  23308. + .type = EV_KEY,
  23309. + .code = KEY_RFKILL,
  23310. + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL,
  23311. + .gpio = TL_MR3220V2_GPIO_BTN_WIFI,
  23312. + .active_low = 0,
  23313. + }
  23314. +};
  23315. +
  23316. +static void __init tl_ap121_setup(void)
  23317. +{
  23318. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  23319. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  23320. +
  23321. + ath79_setup_ar933x_phy4_switch(true, true);
  23322. +
  23323. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  23324. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  23325. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  23326. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  23327. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  23328. +
  23329. + ath79_register_m25p80(&tl_wr741ndv4_flash_data);
  23330. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  23331. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  23332. +
  23333. + ath79_register_mdio(0, 0x0);
  23334. + ath79_register_eth(1);
  23335. + ath79_register_eth(0);
  23336. +
  23337. + ath79_register_wmac(ee, mac);
  23338. +}
  23339. +
  23340. +static void __init tl_wr741ndv4_setup(void)
  23341. +{
  23342. + tl_ap121_setup();
  23343. +
  23344. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio) - 1,
  23345. + tl_wr741ndv4_leds_gpio);
  23346. + ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL,
  23347. + ARRAY_SIZE(tl_wr741ndv4_gpio_keys),
  23348. + tl_wr741ndv4_gpio_keys);
  23349. +}
  23350. +
  23351. +MIPS_MACHINE(ATH79_MACH_TL_WR741ND_V4, "TL-WR741ND-v4",
  23352. + "TP-LINK TL-WR741ND v4", tl_wr741ndv4_setup);
  23353. +
  23354. +static void __init tl_mr3220v2_setup(void)
  23355. +{
  23356. + tl_ap121_setup();
  23357. +
  23358. + gpio_request_one(TL_MR3220V2_GPIO_USB_POWER,
  23359. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  23360. + "USB power");
  23361. + ath79_register_usb();
  23362. +
  23363. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio),
  23364. + tl_wr741ndv4_leds_gpio);
  23365. + ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL,
  23366. + ARRAY_SIZE(tl_mr3220v2_gpio_keys),
  23367. + tl_mr3220v2_gpio_keys);
  23368. +}
  23369. +
  23370. +MIPS_MACHINE(ATH79_MACH_TL_MR3220_V2, "TL-MR3220-v2",
  23371. + "TP-LINK TL-MR3220 v2", tl_mr3220v2_setup);
  23372. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr741nd.c linux-4.1.43/arch/mips/ath79/mach-tl-wr741nd.c
  23373. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr741nd.c 1970-01-01 01:00:00.000000000 +0100
  23374. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr741nd.c 2017-08-06 20:02:15.000000000 +0200
  23375. @@ -0,0 +1,130 @@
  23376. +/*
  23377. + * TP-LINK TL-WR741ND board support
  23378. + *
  23379. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  23380. + *
  23381. + * This program is free software; you can redistribute it and/or modify it
  23382. + * under the terms of the GNU General Public License version 2 as published
  23383. + * by the Free Software Foundation.
  23384. + */
  23385. +
  23386. +#include <asm/mach-ath79/ath79.h>
  23387. +#include <asm/mach-ath79/ar71xx_regs.h>
  23388. +
  23389. +#include "common.h"
  23390. +#include "dev-ap9x-pci.h"
  23391. +#include "dev-eth.h"
  23392. +#include "dev-gpio-buttons.h"
  23393. +#include "dev-leds-gpio.h"
  23394. +#include "dev-m25p80.h"
  23395. +#include "machtypes.h"
  23396. +
  23397. +#define TL_WR741ND_GPIO_LED_QSS 0
  23398. +#define TL_WR741ND_GPIO_LED_SYSTEM 1
  23399. +#define TL_WR741ND_GPIO_LED_LAN1 13
  23400. +#define TL_WR741ND_GPIO_LED_LAN2 14
  23401. +#define TL_WR741ND_GPIO_LED_LAN3 15
  23402. +#define TL_WR741ND_GPIO_LED_LAN4 16
  23403. +#define TL_WR741ND_GPIO_LED_WAN 17
  23404. +
  23405. +#define TL_WR741ND_GPIO_BTN_RESET 11
  23406. +#define TL_WR741ND_GPIO_BTN_QSS 12
  23407. +
  23408. +#define TL_WR741ND_KEYS_POLL_INTERVAL 20 /* msecs */
  23409. +#define TL_WR741ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741ND_KEYS_POLL_INTERVAL)
  23410. +
  23411. +static const char *tl_wr741nd_part_probes[] = {
  23412. + "tp-link",
  23413. + NULL,
  23414. +};
  23415. +
  23416. +static struct flash_platform_data tl_wr741nd_flash_data = {
  23417. + .part_probes = tl_wr741nd_part_probes,
  23418. +};
  23419. +
  23420. +static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = {
  23421. + {
  23422. + .name = "tp-link:green:lan1",
  23423. + .gpio = TL_WR741ND_GPIO_LED_LAN1,
  23424. + .active_low = 1,
  23425. + }, {
  23426. + .name = "tp-link:green:lan2",
  23427. + .gpio = TL_WR741ND_GPIO_LED_LAN2,
  23428. + .active_low = 1,
  23429. + }, {
  23430. + .name = "tp-link:green:lan3",
  23431. + .gpio = TL_WR741ND_GPIO_LED_LAN3,
  23432. + .active_low = 1,
  23433. + }, {
  23434. + .name = "tp-link:green:lan4",
  23435. + .gpio = TL_WR741ND_GPIO_LED_LAN4,
  23436. + .active_low = 1,
  23437. + }, {
  23438. + .name = "tp-link:green:qss",
  23439. + .gpio = TL_WR741ND_GPIO_LED_QSS,
  23440. + .active_low = 1,
  23441. + }, {
  23442. + .name = "tp-link:green:system",
  23443. + .gpio = TL_WR741ND_GPIO_LED_SYSTEM,
  23444. + .active_low = 1,
  23445. + }, {
  23446. + .name = "tp-link:green:wan",
  23447. + .gpio = TL_WR741ND_GPIO_LED_WAN,
  23448. + .active_low = 1,
  23449. + },
  23450. +};
  23451. +
  23452. +static struct gpio_keys_button tl_wr741nd_gpio_keys[] __initdata = {
  23453. + {
  23454. + .desc = "reset",
  23455. + .type = EV_KEY,
  23456. + .code = KEY_RESTART,
  23457. + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL,
  23458. + .gpio = TL_WR741ND_GPIO_BTN_RESET,
  23459. + .active_low = 1,
  23460. + }, {
  23461. + .desc = "qss",
  23462. + .type = EV_KEY,
  23463. + .code = KEY_WPS_BUTTON,
  23464. + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL,
  23465. + .gpio = TL_WR741ND_GPIO_BTN_QSS,
  23466. + .active_low = 1,
  23467. + }
  23468. +};
  23469. +
  23470. +static void __init tl_wr741nd_setup(void)
  23471. +{
  23472. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  23473. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  23474. +
  23475. + ath79_register_m25p80(&tl_wr741nd_flash_data);
  23476. +
  23477. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  23478. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  23479. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  23480. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  23481. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  23482. +
  23483. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio),
  23484. + tl_wr741nd_leds_gpio);
  23485. +
  23486. + ath79_register_gpio_keys_polled(-1, TL_WR741ND_KEYS_POLL_INTERVAL,
  23487. + ARRAY_SIZE(tl_wr741nd_gpio_keys),
  23488. + tl_wr741nd_gpio_keys);
  23489. +
  23490. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  23491. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  23492. +
  23493. + ath79_register_mdio(0, 0x0);
  23494. +
  23495. + /* LAN ports */
  23496. + ath79_register_eth(1);
  23497. +
  23498. + /* WAN port */
  23499. + ath79_register_eth(0);
  23500. +
  23501. + ap9x_pci_setup_wmac_led_pin(0, 1);
  23502. + ap91_pci_init(ee, mac);
  23503. +}
  23504. +MIPS_MACHINE(ATH79_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND",
  23505. + tl_wr741nd_setup);
  23506. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr841n-v8.c linux-4.1.43/arch/mips/ath79/mach-tl-wr841n-v8.c
  23507. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr841n-v8.c 1970-01-01 01:00:00.000000000 +0100
  23508. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr841n-v8.c 2017-08-06 20:02:15.000000000 +0200
  23509. @@ -0,0 +1,286 @@
  23510. +/*
  23511. + * TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 board support
  23512. + *
  23513. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  23514. + *
  23515. + * This program is free software; you can redistribute it and/or modify it
  23516. + * under the terms of the GNU General Public License version 2 as published
  23517. + * by the Free Software Foundation.
  23518. + */
  23519. +
  23520. +#include <linux/gpio.h>
  23521. +#include <linux/platform_device.h>
  23522. +
  23523. +#include <asm/mach-ath79/ath79.h>
  23524. +#include <asm/mach-ath79/ar71xx_regs.h>
  23525. +
  23526. +#include "common.h"
  23527. +#include "dev-eth.h"
  23528. +#include "dev-gpio-buttons.h"
  23529. +#include "dev-leds-gpio.h"
  23530. +#include "dev-m25p80.h"
  23531. +#include "dev-usb.h"
  23532. +#include "dev-wmac.h"
  23533. +#include "machtypes.h"
  23534. +
  23535. +#define TL_WR841NV8_GPIO_LED_WLAN 13
  23536. +#define TL_WR841NV8_GPIO_LED_QSS 15
  23537. +#define TL_WR841NV8_GPIO_LED_WAN 18
  23538. +#define TL_WR841NV8_GPIO_LED_LAN1 19
  23539. +#define TL_WR841NV8_GPIO_LED_LAN2 20
  23540. +#define TL_WR841NV8_GPIO_LED_LAN3 21
  23541. +#define TL_WR841NV8_GPIO_LED_LAN4 12
  23542. +#define TL_WR841NV8_GPIO_LED_SYSTEM 14
  23543. +
  23544. +#define TL_WR841NV8_GPIO_BTN_RESET 17
  23545. +#define TL_WR841NV8_GPIO_SW_RFKILL 16 /* WPS for MR3420 v2 */
  23546. +
  23547. +#define TL_MR3420V2_GPIO_LED_3G 11
  23548. +#define TL_MR3420V2_GPIO_USB_POWER 4
  23549. +
  23550. +#define TL_WR941NDV5_GPIO_LED_WLAN 13
  23551. +#define TL_WR941NDV5_GPIO_LED_QSS 15
  23552. +#define TL_WR941NDV5_GPIO_LED_WAN 18
  23553. +#define TL_WR941NDV5_GPIO_LED_LAN1 19
  23554. +#define TL_WR941NDV5_GPIO_LED_LAN2 20
  23555. +#define TL_WR941NDV5_GPIO_LED_LAN3 2
  23556. +#define TL_WR941NDV5_GPIO_LED_LAN4 3
  23557. +#define TL_WR941NDV5_GPIO_LED_SYSTEM 14
  23558. +
  23559. +#define TL_WR841NV8_KEYS_POLL_INTERVAL 20 /* msecs */
  23560. +#define TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV8_KEYS_POLL_INTERVAL)
  23561. +
  23562. +static const char *tl_wr841n_v8_part_probes[] = {
  23563. + "tp-link",
  23564. + NULL,
  23565. +};
  23566. +
  23567. +static struct flash_platform_data tl_wr841n_v8_flash_data = {
  23568. + .part_probes = tl_wr841n_v8_part_probes,
  23569. +};
  23570. +
  23571. +static struct gpio_led tl_wr841n_v8_leds_gpio[] __initdata = {
  23572. + {
  23573. + .name = "tp-link:green:lan1",
  23574. + .gpio = TL_WR841NV8_GPIO_LED_LAN1,
  23575. + .active_low = 1,
  23576. + }, {
  23577. + .name = "tp-link:green:lan2",
  23578. + .gpio = TL_WR841NV8_GPIO_LED_LAN2,
  23579. + .active_low = 1,
  23580. + }, {
  23581. + .name = "tp-link:green:lan3",
  23582. + .gpio = TL_WR841NV8_GPIO_LED_LAN3,
  23583. + .active_low = 1,
  23584. + }, {
  23585. + .name = "tp-link:green:lan4",
  23586. + .gpio = TL_WR841NV8_GPIO_LED_LAN4,
  23587. + .active_low = 1,
  23588. + }, {
  23589. + .name = "tp-link:green:qss",
  23590. + .gpio = TL_WR841NV8_GPIO_LED_QSS,
  23591. + .active_low = 1,
  23592. + }, {
  23593. + .name = "tp-link:green:system",
  23594. + .gpio = TL_WR841NV8_GPIO_LED_SYSTEM,
  23595. + .active_low = 1,
  23596. + }, {
  23597. + .name = "tp-link:green:wan",
  23598. + .gpio = TL_WR841NV8_GPIO_LED_WAN,
  23599. + .active_low = 1,
  23600. + }, {
  23601. + .name = "tp-link:green:wlan",
  23602. + .gpio = TL_WR841NV8_GPIO_LED_WLAN,
  23603. + .active_low = 1,
  23604. + }, {
  23605. + /* the 3G LED is only present on the MR3420 v2 */
  23606. + .name = "tp-link:green:3g",
  23607. + .gpio = TL_MR3420V2_GPIO_LED_3G,
  23608. + .active_low = 1,
  23609. + },
  23610. +};
  23611. +
  23612. +static struct gpio_keys_button tl_wr841n_v8_gpio_keys[] __initdata = {
  23613. + {
  23614. + .desc = "Reset button",
  23615. + .type = EV_KEY,
  23616. + .code = KEY_RESTART,
  23617. + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL,
  23618. + .gpio = TL_WR841NV8_GPIO_BTN_RESET,
  23619. + .active_low = 1,
  23620. + }, {
  23621. + .desc = "RFKILL switch",
  23622. + .type = EV_SW,
  23623. + .code = KEY_RFKILL,
  23624. + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL,
  23625. + .gpio = TL_WR841NV8_GPIO_SW_RFKILL,
  23626. + .active_low = 0,
  23627. + }
  23628. +};
  23629. +
  23630. +static struct gpio_keys_button tl_mr3420v2_gpio_keys[] __initdata = {
  23631. + {
  23632. + .desc = "Reset button",
  23633. + .type = EV_KEY,
  23634. + .code = KEY_RESTART,
  23635. + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL,
  23636. + .gpio = TL_WR841NV8_GPIO_BTN_RESET,
  23637. + .active_low = 1,
  23638. + }, {
  23639. + .desc = "WPS",
  23640. + .type = EV_KEY,
  23641. + .code = KEY_WPS_BUTTON,
  23642. + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL,
  23643. + .gpio = TL_WR841NV8_GPIO_SW_RFKILL,
  23644. + .active_low = 0,
  23645. + }
  23646. +};
  23647. +
  23648. +static struct gpio_led tl_wr941nd_v5_leds_gpio[] __initdata = {
  23649. + {
  23650. + .name = "tp-link:green:lan1",
  23651. + .gpio = TL_WR941NDV5_GPIO_LED_LAN1,
  23652. + .active_low = 1,
  23653. + }, {
  23654. + .name = "tp-link:green:lan2",
  23655. + .gpio = TL_WR941NDV5_GPIO_LED_LAN2,
  23656. + .active_low = 1,
  23657. + }, {
  23658. + .name = "tp-link:green:lan3",
  23659. + .gpio = TL_WR941NDV5_GPIO_LED_LAN3,
  23660. + .active_low = 1,
  23661. + }, {
  23662. + .name = "tp-link:green:lan4",
  23663. + .gpio = TL_WR941NDV5_GPIO_LED_LAN4,
  23664. + .active_low = 1,
  23665. + }, {
  23666. + .name = "tp-link:green:qss",
  23667. + .gpio = TL_WR941NDV5_GPIO_LED_QSS,
  23668. + .active_low = 1,
  23669. + }, {
  23670. + .name = "tp-link:green:system",
  23671. + .gpio = TL_WR941NDV5_GPIO_LED_SYSTEM,
  23672. + .active_low = 1,
  23673. + }, {
  23674. + .name = "tp-link:green:wan",
  23675. + .gpio = TL_WR941NDV5_GPIO_LED_WAN,
  23676. + .active_low = 1,
  23677. + }, {
  23678. + .name = "tp-link:green:wlan",
  23679. + .gpio = TL_WR941NDV5_GPIO_LED_WLAN,
  23680. + .active_low = 1,
  23681. + },
  23682. +};
  23683. +
  23684. +static void __init tl_ap123_setup(void)
  23685. +{
  23686. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  23687. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  23688. +
  23689. + /* Disable JTAG, enabling GPIOs 0-3 */
  23690. + /* Configure OBS4 line, for GPIO 4*/
  23691. + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
  23692. + AR934X_GPIO_FUNC_CLK_OBS4_EN);
  23693. +
  23694. + /* config gpio4 as normal gpio function */
  23695. + ath79_gpio_output_select(TL_MR3420V2_GPIO_USB_POWER,
  23696. + AR934X_GPIO_OUT_GPIO);
  23697. +
  23698. + ath79_register_m25p80(&tl_wr841n_v8_flash_data);
  23699. +
  23700. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
  23701. +
  23702. + ath79_register_mdio(1, 0x0);
  23703. +
  23704. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
  23705. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  23706. +
  23707. + /* GMAC0 is connected to the PHY0 of the internal switch */
  23708. + ath79_switch_data.phy4_mii_en = 1;
  23709. + ath79_switch_data.phy_poll_mask = BIT(0);
  23710. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  23711. + ath79_eth0_data.phy_mask = BIT(0);
  23712. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  23713. + ath79_register_eth(0);
  23714. +
  23715. + /* GMAC1 is connected to the internal switch */
  23716. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  23717. + ath79_register_eth(1);
  23718. +
  23719. + ath79_register_wmac(ee, mac);
  23720. +}
  23721. +
  23722. +static void __init tl_wr841n_v8_setup(void)
  23723. +{
  23724. + tl_ap123_setup();
  23725. +
  23726. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio) - 1,
  23727. + tl_wr841n_v8_leds_gpio);
  23728. +
  23729. + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
  23730. + ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
  23731. + tl_wr841n_v8_gpio_keys);
  23732. +}
  23733. +
  23734. +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V8, "TL-WR841N-v8", "TP-LINK TL-WR841N/ND v8",
  23735. + tl_wr841n_v8_setup);
  23736. +
  23737. +
  23738. +static void __init tl_wr842n_v2_setup(void)
  23739. +{
  23740. + tl_ap123_setup();
  23741. +
  23742. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio),
  23743. + tl_wr841n_v8_leds_gpio);
  23744. +
  23745. + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
  23746. + ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
  23747. + tl_wr841n_v8_gpio_keys);
  23748. +
  23749. + gpio_request_one(TL_MR3420V2_GPIO_USB_POWER,
  23750. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  23751. + "USB power");
  23752. +
  23753. + ath79_register_usb();
  23754. +}
  23755. +
  23756. +MIPS_MACHINE(ATH79_MACH_TL_WR842N_V2, "TL-WR842N-v2", "TP-LINK TL-WR842N/ND v2",
  23757. + tl_wr842n_v2_setup);
  23758. +
  23759. +static void __init tl_mr3420v2_setup(void)
  23760. +{
  23761. + tl_ap123_setup();
  23762. +
  23763. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio),
  23764. + tl_wr841n_v8_leds_gpio);
  23765. +
  23766. + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
  23767. + ARRAY_SIZE(tl_mr3420v2_gpio_keys),
  23768. + tl_mr3420v2_gpio_keys);
  23769. +
  23770. + /* enable power for the USB port */
  23771. + gpio_request_one(TL_MR3420V2_GPIO_USB_POWER,
  23772. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  23773. + "USB power");
  23774. +
  23775. + ath79_register_usb();
  23776. +}
  23777. +
  23778. +MIPS_MACHINE(ATH79_MACH_TL_MR3420_V2, "TL-MR3420-v2", "TP-LINK TL-MR3420 v2",
  23779. + tl_mr3420v2_setup);
  23780. +
  23781. +
  23782. +static void __init tl_wr941nd_v5_setup(void)
  23783. +{
  23784. + tl_ap123_setup();
  23785. +
  23786. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_v5_leds_gpio),
  23787. + tl_wr941nd_v5_leds_gpio);
  23788. +
  23789. + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
  23790. + ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
  23791. + tl_wr841n_v8_gpio_keys);
  23792. +}
  23793. +
  23794. +MIPS_MACHINE(ATH79_MACH_TL_WR941ND_V5, "TL-WR941ND-v5", "TP-LINK TL-WR941N/ND v5",
  23795. + tl_wr941nd_v5_setup);
  23796. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr841n-v9.c linux-4.1.43/arch/mips/ath79/mach-tl-wr841n-v9.c
  23797. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr841n-v9.c 1970-01-01 01:00:00.000000000 +0100
  23798. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr841n-v9.c 2017-08-06 20:02:15.000000000 +0200
  23799. @@ -0,0 +1,144 @@
  23800. +/*
  23801. + * TP-LINK TL-WR841N/ND v9
  23802. + *
  23803. + * Copyright (C) 2014 Matthias Schiffer <mschiffer@universe-factory.net>
  23804. + *
  23805. + * This program is free software; you can redistribute it and/or modify it
  23806. + * under the terms of the GNU General Public License version 2 as published
  23807. + * by the Free Software Foundation.
  23808. + */
  23809. +
  23810. +#include <linux/gpio.h>
  23811. +#include <linux/platform_device.h>
  23812. +
  23813. +#include <asm/mach-ath79/ath79.h>
  23814. +#include <asm/mach-ath79/ar71xx_regs.h>
  23815. +
  23816. +#include "common.h"
  23817. +#include "dev-eth.h"
  23818. +#include "dev-gpio-buttons.h"
  23819. +#include "dev-leds-gpio.h"
  23820. +#include "dev-m25p80.h"
  23821. +#include "dev-wmac.h"
  23822. +#include "machtypes.h"
  23823. +
  23824. +#define TL_WR841NV9_GPIO_LED_WLAN 13
  23825. +#define TL_WR841NV9_GPIO_LED_QSS 3
  23826. +#define TL_WR841NV9_GPIO_LED_WAN 4
  23827. +#define TL_WR841NV9_GPIO_LED_LAN1 16
  23828. +#define TL_WR841NV9_GPIO_LED_LAN2 15
  23829. +#define TL_WR841NV9_GPIO_LED_LAN3 14
  23830. +#define TL_WR841NV9_GPIO_LED_LAN4 11
  23831. +
  23832. +#define TL_WR841NV9_GPIO_BTN_RESET 12
  23833. +#define TL_WR841NV9_GPIO_BTN_WIFI 17
  23834. +
  23835. +#define TL_WR841NV9_KEYS_POLL_INTERVAL 20 /* msecs */
  23836. +#define TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV9_KEYS_POLL_INTERVAL)
  23837. +
  23838. +static const char *tl_wr841n_v9_part_probes[] = {
  23839. + "tp-link",
  23840. + NULL,
  23841. +};
  23842. +
  23843. +static struct flash_platform_data tl_wr841n_v9_flash_data = {
  23844. + .part_probes = tl_wr841n_v9_part_probes,
  23845. +};
  23846. +
  23847. +static struct gpio_led tl_wr841n_v9_leds_gpio[] __initdata = {
  23848. + {
  23849. + .name = "tp-link:green:lan1",
  23850. + .gpio = TL_WR841NV9_GPIO_LED_LAN1,
  23851. + .active_low = 1,
  23852. + }, {
  23853. + .name = "tp-link:green:lan2",
  23854. + .gpio = TL_WR841NV9_GPIO_LED_LAN2,
  23855. + .active_low = 1,
  23856. + }, {
  23857. + .name = "tp-link:green:lan3",
  23858. + .gpio = TL_WR841NV9_GPIO_LED_LAN3,
  23859. + .active_low = 1,
  23860. + }, {
  23861. + .name = "tp-link:green:lan4",
  23862. + .gpio = TL_WR841NV9_GPIO_LED_LAN4,
  23863. + .active_low = 1,
  23864. + }, {
  23865. + .name = "tp-link:green:qss",
  23866. + .gpio = TL_WR841NV9_GPIO_LED_QSS,
  23867. + .active_low = 1,
  23868. + }, {
  23869. + .name = "tp-link:green:wan",
  23870. + .gpio = TL_WR841NV9_GPIO_LED_WAN,
  23871. + .active_low = 1,
  23872. + }, {
  23873. + .name = "tp-link:green:wlan",
  23874. + .gpio = TL_WR841NV9_GPIO_LED_WLAN,
  23875. + .active_low = 1,
  23876. + },
  23877. +};
  23878. +
  23879. +static struct gpio_keys_button tl_wr841n_v9_gpio_keys[] __initdata = {
  23880. + {
  23881. + .desc = "Reset button",
  23882. + .type = EV_KEY,
  23883. + .code = KEY_RESTART,
  23884. + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL,
  23885. + .gpio = TL_WR841NV9_GPIO_BTN_RESET,
  23886. + .active_low = 1,
  23887. + }, {
  23888. + .desc = "WIFI button",
  23889. + .type = EV_KEY,
  23890. + .code = KEY_RFKILL,
  23891. + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL,
  23892. + .gpio = TL_WR841NV9_GPIO_BTN_WIFI,
  23893. + .active_low = 1,
  23894. + }
  23895. +};
  23896. +
  23897. +
  23898. +static void __init tl_ap143_setup(void)
  23899. +{
  23900. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  23901. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  23902. + u8 tmpmac[ETH_ALEN];
  23903. +
  23904. + ath79_register_m25p80(&tl_wr841n_v9_flash_data);
  23905. +
  23906. + ath79_setup_ar933x_phy4_switch(false, false);
  23907. +
  23908. + ath79_register_mdio(0, 0x0);
  23909. +
  23910. + /* LAN */
  23911. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  23912. + ath79_eth1_data.duplex = DUPLEX_FULL;
  23913. + ath79_switch_data.phy_poll_mask |= BIT(4);
  23914. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
  23915. + ath79_register_eth(1);
  23916. +
  23917. + /* WAN */
  23918. + ath79_switch_data.phy4_mii_en = 1;
  23919. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  23920. + ath79_eth0_data.duplex = DUPLEX_FULL;
  23921. + ath79_eth0_data.speed = SPEED_100;
  23922. + ath79_eth0_data.phy_mask = BIT(4);
  23923. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  23924. + ath79_register_eth(0);
  23925. +
  23926. + ath79_init_mac(tmpmac, mac, 0);
  23927. + ath79_register_wmac(ee, tmpmac);
  23928. +}
  23929. +
  23930. +static void __init tl_wr841n_v9_setup(void)
  23931. +{
  23932. + tl_ap143_setup();
  23933. +
  23934. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v9_leds_gpio),
  23935. + tl_wr841n_v9_leds_gpio);
  23936. +
  23937. + ath79_register_gpio_keys_polled(1, TL_WR841NV9_KEYS_POLL_INTERVAL,
  23938. + ARRAY_SIZE(tl_wr841n_v9_gpio_keys),
  23939. + tl_wr841n_v9_gpio_keys);
  23940. +}
  23941. +
  23942. +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V9, "TL-WR841N-v9", "TP-LINK TL-WR841N/ND v9",
  23943. + tl_wr841n_v9_setup);
  23944. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr841n.c linux-4.1.43/arch/mips/ath79/mach-tl-wr841n.c
  23945. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr841n.c 1970-01-01 01:00:00.000000000 +0100
  23946. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr841n.c 2017-08-06 20:02:15.000000000 +0200
  23947. @@ -0,0 +1,140 @@
  23948. +/*
  23949. + * TP-LINK TL-WR841N/ND v1 board support
  23950. + *
  23951. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  23952. + *
  23953. + * This program is free software; you can redistribute it and/or modify it
  23954. + * under the terms of the GNU General Public License version 2 as published
  23955. + * by the Free Software Foundation.
  23956. + */
  23957. +
  23958. +#include <linux/mtd/mtd.h>
  23959. +#include <linux/mtd/partitions.h>
  23960. +#include <linux/platform_device.h>
  23961. +
  23962. +#include <asm/mach-ath79/ath79.h>
  23963. +
  23964. +#include "dev-dsa.h"
  23965. +#include "dev-eth.h"
  23966. +#include "dev-gpio-buttons.h"
  23967. +#include "dev-leds-gpio.h"
  23968. +#include "dev-m25p80.h"
  23969. +#include "machtypes.h"
  23970. +#include "pci.h"
  23971. +
  23972. +#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2
  23973. +#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4
  23974. +#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5
  23975. +
  23976. +#define TL_WR841ND_V1_GPIO_BTN_RESET 3
  23977. +#define TL_WR841ND_V1_GPIO_BTN_QSS 7
  23978. +
  23979. +#define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */
  23980. +#define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \
  23981. + (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL)
  23982. +
  23983. +static struct mtd_partition tl_wr841n_v1_partitions[] = {
  23984. + {
  23985. + .name = "redboot",
  23986. + .offset = 0,
  23987. + .size = 0x020000,
  23988. + .mask_flags = MTD_WRITEABLE,
  23989. + }, {
  23990. + .name = "kernel",
  23991. + .offset = 0x020000,
  23992. + .size = 0x140000,
  23993. + }, {
  23994. + .name = "rootfs",
  23995. + .offset = 0x160000,
  23996. + .size = 0x280000,
  23997. + }, {
  23998. + .name = "config",
  23999. + .offset = 0x3e0000,
  24000. + .size = 0x020000,
  24001. + .mask_flags = MTD_WRITEABLE,
  24002. + }, {
  24003. + .name = "firmware",
  24004. + .offset = 0x020000,
  24005. + .size = 0x3c0000,
  24006. + }
  24007. +};
  24008. +
  24009. +static struct flash_platform_data tl_wr841n_v1_flash_data = {
  24010. + .parts = tl_wr841n_v1_partitions,
  24011. + .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions),
  24012. +};
  24013. +
  24014. +static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = {
  24015. + {
  24016. + .name = "tp-link:green:system",
  24017. + .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM,
  24018. + .active_low = 1,
  24019. + }, {
  24020. + .name = "tp-link:red:qss",
  24021. + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED,
  24022. + }, {
  24023. + .name = "tp-link:green:qss",
  24024. + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN,
  24025. + }
  24026. +};
  24027. +
  24028. +static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = {
  24029. + {
  24030. + .desc = "reset",
  24031. + .type = EV_KEY,
  24032. + .code = KEY_RESTART,
  24033. + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL,
  24034. + .gpio = TL_WR841ND_V1_GPIO_BTN_RESET,
  24035. + .active_low = 1,
  24036. + }, {
  24037. + .desc = "qss",
  24038. + .type = EV_KEY,
  24039. + .code = KEY_WPS_BUTTON,
  24040. + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL,
  24041. + .gpio = TL_WR841ND_V1_GPIO_BTN_QSS,
  24042. + .active_low = 1,
  24043. + }
  24044. +};
  24045. +
  24046. +static struct dsa_chip_data tl_wr841n_v1_dsa_chip = {
  24047. + .port_names[0] = "wan",
  24048. + .port_names[1] = "lan1",
  24049. + .port_names[2] = "lan2",
  24050. + .port_names[3] = "lan3",
  24051. + .port_names[4] = "lan4",
  24052. + .port_names[5] = "cpu",
  24053. +};
  24054. +
  24055. +static struct dsa_platform_data tl_wr841n_v1_dsa_data = {
  24056. + .nr_chips = 1,
  24057. + .chip = &tl_wr841n_v1_dsa_chip,
  24058. +};
  24059. +
  24060. +static void __init tl_wr841n_v1_setup(void)
  24061. +{
  24062. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  24063. +
  24064. + ath79_register_mdio(0, 0x0);
  24065. +
  24066. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  24067. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  24068. + ath79_eth0_data.speed = SPEED_100;
  24069. + ath79_eth0_data.duplex = DUPLEX_FULL;
  24070. +
  24071. + ath79_register_eth(0);
  24072. + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev,
  24073. + &tl_wr841n_v1_dsa_data);
  24074. +
  24075. + ath79_register_m25p80(&tl_wr841n_v1_flash_data);
  24076. +
  24077. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio),
  24078. + tl_wr841n_v1_leds_gpio);
  24079. +
  24080. + ath79_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL,
  24081. + ARRAY_SIZE(tl_wr841n_v1_gpio_keys),
  24082. + tl_wr841n_v1_gpio_keys);
  24083. + ath79_register_pci();
  24084. +}
  24085. +
  24086. +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1",
  24087. + tl_wr841n_v1_setup);
  24088. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr941nd-v6.c linux-4.1.43/arch/mips/ath79/mach-tl-wr941nd-v6.c
  24089. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr941nd-v6.c 1970-01-01 01:00:00.000000000 +0100
  24090. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr941nd-v6.c 2017-08-06 20:02:15.000000000 +0200
  24091. @@ -0,0 +1,149 @@
  24092. +/*
  24093. + * TP-LINK TL-WR941N/ND v6 board support
  24094. + *
  24095. + * Copyright (C) 2015 Matthias Schiffer <mschiffer@universe-factory.net>
  24096. + *
  24097. + * This program is free software; you can redistribute it and/or modify it
  24098. + * under the terms of the GNU General Public License version 2 as published
  24099. + * by the Free Software Foundation.
  24100. + */
  24101. +
  24102. +#include <linux/gpio.h>
  24103. +#include <linux/platform_device.h>
  24104. +
  24105. +#include <asm/mach-ath79/ath79.h>
  24106. +#include <asm/mach-ath79/ar71xx_regs.h>
  24107. +
  24108. +#include "common.h"
  24109. +#include "dev-eth.h"
  24110. +#include "dev-gpio-buttons.h"
  24111. +#include "dev-leds-gpio.h"
  24112. +#include "dev-m25p80.h"
  24113. +#include "dev-wmac.h"
  24114. +#include "machtypes.h"
  24115. +
  24116. +
  24117. +#define TL_WR941ND_V6_GPIO_LED_QSS 3
  24118. +#define TL_WR941ND_V6_GPIO_LED_WAN 14
  24119. +#define TL_WR941ND_V6_GPIO_LED_WAN_RED 15
  24120. +#define TL_WR941ND_V6_GPIO_LED_LAN1 7
  24121. +#define TL_WR941ND_V6_GPIO_LED_LAN2 6
  24122. +#define TL_WR941ND_V6_GPIO_LED_LAN3 5
  24123. +#define TL_WR941ND_V6_GPIO_LED_LAN4 4
  24124. +#define TL_WR941ND_V6_GPIO_LED_WLAN 8
  24125. +#define TL_WR941ND_V6_GPIO_LED_SYSTEM 18
  24126. +
  24127. +#define TL_WR941ND_V6_GPIO_BTN_RESET 1
  24128. +#define TL_WR941ND_V6_GPIO_BTN_RFKILL 2
  24129. +
  24130. +#define TL_WR941ND_V6_KEYS_POLL_INTERVAL 20
  24131. +#define TL_WR941ND_V6_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_V6_KEYS_POLL_INTERVAL)
  24132. +
  24133. +
  24134. +static struct gpio_led tl_wr941nd_v6_leds_gpio[] __initdata = {
  24135. + {
  24136. + .name = "tp-link:blue:qss",
  24137. + .gpio = TL_WR941ND_V6_GPIO_LED_QSS,
  24138. + .active_low = 1,
  24139. + },
  24140. + {
  24141. + .name = "tp-link:blue:wan",
  24142. + .gpio = TL_WR941ND_V6_GPIO_LED_WAN,
  24143. + .active_low = 1,
  24144. + },
  24145. + {
  24146. + .name = "tp-link:red:wan",
  24147. + .gpio = TL_WR941ND_V6_GPIO_LED_WAN_RED,
  24148. + .active_low = 0,
  24149. + },
  24150. + {
  24151. + .name = "tp-link:blue:lan1",
  24152. + .gpio = TL_WR941ND_V6_GPIO_LED_LAN1,
  24153. + .active_low = 1,
  24154. + },
  24155. + {
  24156. + .name = "tp-link:blue:lan2",
  24157. + .gpio = TL_WR941ND_V6_GPIO_LED_LAN2,
  24158. + .active_low = 1,
  24159. + },
  24160. + {
  24161. + .name = "tp-link:blue:lan3",
  24162. + .gpio = TL_WR941ND_V6_GPIO_LED_LAN3,
  24163. + .active_low = 1,
  24164. + },
  24165. + {
  24166. + .name = "tp-link:blue:lan4",
  24167. + .gpio = TL_WR941ND_V6_GPIO_LED_LAN4,
  24168. + .active_low = 1,
  24169. + },
  24170. + {
  24171. + .name = "tp-link:blue:wlan",
  24172. + .gpio = TL_WR941ND_V6_GPIO_LED_WLAN,
  24173. + .active_low = 1,
  24174. + },
  24175. + {
  24176. + .name = "tp-link:blue:system",
  24177. + .gpio = TL_WR941ND_V6_GPIO_LED_SYSTEM,
  24178. + .active_low = 1,
  24179. + },
  24180. +};
  24181. +
  24182. +static struct gpio_keys_button tl_wr941nd_v6_gpio_keys[] __initdata = {
  24183. + {
  24184. + .desc = "Reset button",
  24185. + .type = EV_KEY,
  24186. + .code = KEY_RESTART,
  24187. + .debounce_interval = TL_WR941ND_V6_KEYS_DEBOUNCE_INTERVAL,
  24188. + .gpio = TL_WR941ND_V6_GPIO_BTN_RESET,
  24189. + .active_low = 1,
  24190. + }, {
  24191. + .desc = "RFKILL button",
  24192. + .type = EV_KEY,
  24193. + .code = KEY_RFKILL,
  24194. + .debounce_interval = TL_WR941ND_V6_KEYS_DEBOUNCE_INTERVAL,
  24195. + .gpio = TL_WR941ND_V6_GPIO_BTN_RFKILL,
  24196. + .active_low = 1,
  24197. + }
  24198. +};
  24199. +
  24200. +
  24201. +static const char *tl_wr941n_v6_part_probes[] = {
  24202. + "tp-link",
  24203. + NULL,
  24204. +};
  24205. +
  24206. +static struct flash_platform_data tl_wr941n_v6_flash_data = {
  24207. + .part_probes = tl_wr941n_v6_part_probes,
  24208. +};
  24209. +
  24210. +
  24211. +static void __init tl_wr941nd_v6_setup(void)
  24212. +{
  24213. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  24214. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  24215. +
  24216. + ath79_register_m25p80(&tl_wr941n_v6_flash_data);
  24217. +
  24218. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_v6_leds_gpio),
  24219. + tl_wr941nd_v6_leds_gpio);
  24220. +
  24221. + ath79_register_gpio_keys_polled(-1, TL_WR941ND_V6_KEYS_POLL_INTERVAL,
  24222. + ARRAY_SIZE(tl_wr941nd_v6_gpio_keys),
  24223. + tl_wr941nd_v6_gpio_keys);
  24224. +
  24225. + ath79_register_mdio(0, 0x0);
  24226. +
  24227. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  24228. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
  24229. +
  24230. + ath79_switch_data.phy4_mii_en = 1;
  24231. +
  24232. + ath79_register_eth(0);
  24233. + ath79_register_eth(1);
  24234. +
  24235. + ath79_register_wmac(ee, mac);
  24236. +
  24237. +}
  24238. +
  24239. +MIPS_MACHINE(ATH79_MACH_TL_WR941ND_V6, "TL-WR941ND-v6", "TP-LINK TL-WR941N/ND v6",
  24240. + tl_wr941nd_v6_setup);
  24241. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr941nd.c linux-4.1.43/arch/mips/ath79/mach-tl-wr941nd.c
  24242. --- linux-4.1.43.orig/arch/mips/ath79/mach-tl-wr941nd.c 1970-01-01 01:00:00.000000000 +0100
  24243. +++ linux-4.1.43/arch/mips/ath79/mach-tl-wr941nd.c 2017-08-06 20:02:15.000000000 +0200
  24244. @@ -0,0 +1,121 @@
  24245. +/*
  24246. + * TP-LINK TL-WR941ND board support
  24247. + *
  24248. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  24249. + *
  24250. + * This program is free software; you can redistribute it and/or modify it
  24251. + * under the terms of the GNU General Public License version 2 as published
  24252. + * by the Free Software Foundation.
  24253. + */
  24254. +
  24255. +#include <linux/platform_device.h>
  24256. +
  24257. +#include <asm/mach-ath79/ath79.h>
  24258. +
  24259. +#include "dev-dsa.h"
  24260. +#include "dev-eth.h"
  24261. +#include "dev-gpio-buttons.h"
  24262. +#include "dev-leds-gpio.h"
  24263. +#include "dev-m25p80.h"
  24264. +#include "dev-wmac.h"
  24265. +#include "machtypes.h"
  24266. +
  24267. +#define TL_WR941ND_GPIO_LED_SYSTEM 2
  24268. +#define TL_WR941ND_GPIO_LED_QSS_RED 4
  24269. +#define TL_WR941ND_GPIO_LED_QSS_GREEN 5
  24270. +#define TL_WR941ND_GPIO_LED_WLAN 9
  24271. +
  24272. +#define TL_WR941ND_GPIO_BTN_RESET 3
  24273. +#define TL_WR941ND_GPIO_BTN_QSS 7
  24274. +
  24275. +#define TL_WR941ND_KEYS_POLL_INTERVAL 20 /* msecs */
  24276. +#define TL_WR941ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_KEYS_POLL_INTERVAL)
  24277. +
  24278. +static const char *tl_wr941nd_part_probes[] = {
  24279. + "tp-link",
  24280. + NULL,
  24281. +};
  24282. +
  24283. +static struct flash_platform_data tl_wr941nd_flash_data = {
  24284. + .part_probes = tl_wr941nd_part_probes,
  24285. +};
  24286. +
  24287. +static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = {
  24288. + {
  24289. + .name = "tp-link:green:system",
  24290. + .gpio = TL_WR941ND_GPIO_LED_SYSTEM,
  24291. + .active_low = 1,
  24292. + }, {
  24293. + .name = "tp-link:red:qss",
  24294. + .gpio = TL_WR941ND_GPIO_LED_QSS_RED,
  24295. + }, {
  24296. + .name = "tp-link:green:qss",
  24297. + .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN,
  24298. + }, {
  24299. + .name = "tp-link:green:wlan",
  24300. + .gpio = TL_WR941ND_GPIO_LED_WLAN,
  24301. + .active_low = 1,
  24302. + }
  24303. +};
  24304. +
  24305. +static struct gpio_keys_button tl_wr941nd_gpio_keys[] __initdata = {
  24306. + {
  24307. + .desc = "reset",
  24308. + .type = EV_KEY,
  24309. + .code = KEY_RESTART,
  24310. + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL,
  24311. + .gpio = TL_WR941ND_GPIO_BTN_RESET,
  24312. + .active_low = 1,
  24313. + }, {
  24314. + .desc = "qss",
  24315. + .type = EV_KEY,
  24316. + .code = KEY_WPS_BUTTON,
  24317. + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL,
  24318. + .gpio = TL_WR941ND_GPIO_BTN_QSS,
  24319. + .active_low = 1,
  24320. + }
  24321. +};
  24322. +
  24323. +static struct dsa_chip_data tl_wr941nd_dsa_chip = {
  24324. + .port_names[0] = "wan",
  24325. + .port_names[1] = "lan1",
  24326. + .port_names[2] = "lan2",
  24327. + .port_names[3] = "lan3",
  24328. + .port_names[4] = "lan4",
  24329. + .port_names[5] = "cpu",
  24330. +};
  24331. +
  24332. +static struct dsa_platform_data tl_wr941nd_dsa_data = {
  24333. + .nr_chips = 1,
  24334. + .chip = &tl_wr941nd_dsa_chip,
  24335. +};
  24336. +
  24337. +static void __init tl_wr941nd_setup(void)
  24338. +{
  24339. + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
  24340. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  24341. +
  24342. + ath79_register_mdio(0, 0x0);
  24343. +
  24344. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  24345. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  24346. + ath79_eth0_data.speed = SPEED_100;
  24347. + ath79_eth0_data.duplex = DUPLEX_FULL;
  24348. +
  24349. + ath79_register_eth(0);
  24350. + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev,
  24351. + &tl_wr941nd_dsa_data);
  24352. +
  24353. + ath79_register_m25p80(&tl_wr941nd_flash_data);
  24354. +
  24355. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio),
  24356. + tl_wr941nd_leds_gpio);
  24357. +
  24358. + ath79_register_gpio_keys_polled(-1, TL_WR941ND_KEYS_POLL_INTERVAL,
  24359. + ARRAY_SIZE(tl_wr941nd_gpio_keys),
  24360. + tl_wr941nd_gpio_keys);
  24361. + ath79_register_wmac(eeprom, mac);
  24362. +}
  24363. +
  24364. +MIPS_MACHINE(ATH79_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND",
  24365. + tl_wr941nd_setup);
  24366. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-tube2h.c linux-4.1.43/arch/mips/ath79/mach-tube2h.c
  24367. --- linux-4.1.43.orig/arch/mips/ath79/mach-tube2h.c 1970-01-01 01:00:00.000000000 +0100
  24368. +++ linux-4.1.43/arch/mips/ath79/mach-tube2h.c 2017-08-06 20:02:15.000000000 +0200
  24369. @@ -0,0 +1,118 @@
  24370. +/*
  24371. + * ALFA NETWORK Tube2H board support
  24372. + *
  24373. + * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
  24374. + *
  24375. + * This program is free software; you can redistribute it and/or modify it
  24376. + * under the terms of the GNU General Public License version 2 as published
  24377. + * by the Free Software Foundation.
  24378. + */
  24379. +
  24380. +#include <linux/gpio.h>
  24381. +
  24382. +#include <asm/mach-ath79/ath79.h>
  24383. +#include <asm/mach-ath79/ar71xx_regs.h>
  24384. +
  24385. +#include "common.h"
  24386. +#include "dev-eth.h"
  24387. +#include "dev-gpio-buttons.h"
  24388. +#include "dev-leds-gpio.h"
  24389. +#include "dev-m25p80.h"
  24390. +#include "dev-wmac.h"
  24391. +#include "machtypes.h"
  24392. +
  24393. +#define TUBE2H_GPIO_LED_SIGNAL4 0
  24394. +#define TUBE2H_GPIO_LED_SIGNAL3 1
  24395. +#define TUBE2H_GPIO_LED_SIGNAL2 13
  24396. +#define TUBE2H_GPIO_LED_LAN 17
  24397. +#define TUBE2H_GPIO_LED_SIGNAL1 27
  24398. +#define TUBE2H_GPIO_EXT_LNA 28
  24399. +
  24400. +#define TUBE2H_GPIO_BTN_RESET 12
  24401. +
  24402. +#define TUBE2H_KEYS_POLL_INTERVAL 20 /* msecs */
  24403. +#define TUBE2H_KEYS_DEBOUNCE_INTERVAL (3 * TUBE2H_KEYS_POLL_INTERVAL)
  24404. +
  24405. +#define TUBE2H_ART_ADDRESS 0x1f7f0000
  24406. +#define TUBE2H_LAN_MAC_OFFSET 0x06
  24407. +#define TUBE2H_CALDATA_OFFSET 0x1000
  24408. +
  24409. +static struct gpio_led tube2h_leds_gpio[] __initdata = {
  24410. + {
  24411. + .name = "alfa:blue:lan",
  24412. + .gpio = TUBE2H_GPIO_LED_LAN,
  24413. + .active_low = 1,
  24414. + },
  24415. + {
  24416. + .name = "alfa:red:signal1",
  24417. + .gpio = TUBE2H_GPIO_LED_SIGNAL1,
  24418. + .active_low = 1,
  24419. + },
  24420. + {
  24421. + .name = "alfa:orange:signal2",
  24422. + .gpio = TUBE2H_GPIO_LED_SIGNAL2,
  24423. + .active_low = 0,
  24424. + },
  24425. + {
  24426. + .name = "alfa:green:signal3",
  24427. + .gpio = TUBE2H_GPIO_LED_SIGNAL3,
  24428. + .active_low = 0,
  24429. + },
  24430. + {
  24431. + .name = "alfa:green:signal4",
  24432. + .gpio = TUBE2H_GPIO_LED_SIGNAL4,
  24433. + .active_low = 0,
  24434. + },
  24435. +};
  24436. +
  24437. +static struct gpio_keys_button tube2h_gpio_keys[] __initdata = {
  24438. + {
  24439. + .desc = "Reset button",
  24440. + .type = EV_KEY,
  24441. + .code = KEY_RESTART,
  24442. + .debounce_interval = TUBE2H_KEYS_DEBOUNCE_INTERVAL,
  24443. + .gpio = TUBE2H_GPIO_BTN_RESET,
  24444. + .active_low = 1,
  24445. + },
  24446. +};
  24447. +
  24448. +static void __init tube2h_setup(void)
  24449. +{
  24450. + u8 *art = (u8 *) KSEG1ADDR(TUBE2H_ART_ADDRESS);
  24451. + u32 t;
  24452. +
  24453. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_JTAG_DISABLE |
  24454. + AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  24455. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  24456. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  24457. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  24458. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  24459. +
  24460. + /* Ensure that GPIO26 and GPIO27 are controllable by software */
  24461. + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  24462. + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
  24463. + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
  24464. +
  24465. + gpio_request_one(TUBE2H_GPIO_EXT_LNA,
  24466. + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  24467. + "external LNA0");
  24468. +
  24469. + ath79_register_wmac(art + TUBE2H_CALDATA_OFFSET, NULL);
  24470. +
  24471. + ath79_register_m25p80(NULL);
  24472. +
  24473. + ath79_register_leds_gpio(-1, ARRAY_SIZE(tube2h_leds_gpio),
  24474. + tube2h_leds_gpio);
  24475. + ath79_register_gpio_keys_polled(-1, TUBE2H_KEYS_POLL_INTERVAL,
  24476. + ARRAY_SIZE(tube2h_gpio_keys),
  24477. + tube2h_gpio_keys);
  24478. +
  24479. + ath79_init_mac(ath79_eth0_data.mac_addr,
  24480. + art + TUBE2H_LAN_MAC_OFFSET, 0);
  24481. + ath79_register_mdio(0, 0x0);
  24482. + ath79_register_eth(0);
  24483. +}
  24484. +
  24485. +MIPS_MACHINE(ATH79_MACH_TUBE2H, "TUBE2H", "ALFA NETWORK Tube2H",
  24486. + tube2h_setup);
  24487. +
  24488. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ubnt-xm.c linux-4.1.43/arch/mips/ath79/mach-ubnt-xm.c
  24489. --- linux-4.1.43.orig/arch/mips/ath79/mach-ubnt-xm.c 2017-08-06 01:56:14.000000000 +0200
  24490. +++ linux-4.1.43/arch/mips/ath79/mach-ubnt-xm.c 2017-08-06 20:02:15.000000000 +0200
  24491. @@ -12,15 +12,26 @@
  24492. #include <linux/init.h>
  24493. #include <linux/pci.h>
  24494. +#include <linux/platform_device.h>
  24495. #include <linux/ath9k_platform.h>
  24496. +#include <linux/etherdevice.h>
  24497. +#include <linux/ar8216_platform.h>
  24498. +#include <asm/mach-ath79/ath79.h>
  24499. #include <asm/mach-ath79/irq.h>
  24500. +#include <asm/mach-ath79/ar71xx_regs.h>
  24501. -#include "machtypes.h"
  24502. +#include <linux/platform_data/phy-at803x.h>
  24503. +
  24504. +#include "common.h"
  24505. +#include "dev-ap9x-pci.h"
  24506. +#include "dev-eth.h"
  24507. #include "dev-gpio-buttons.h"
  24508. #include "dev-leds-gpio.h"
  24509. -#include "dev-spi.h"
  24510. -#include "pci.h"
  24511. +#include "dev-m25p80.h"
  24512. +#include "dev-usb.h"
  24513. +#include "dev-wmac.h"
  24514. +#include "machtypes.h"
  24515. #define UBNT_XM_GPIO_LED_L1 0
  24516. #define UBNT_XM_GPIO_LED_L2 1
  24517. @@ -32,23 +43,23 @@
  24518. #define UBNT_XM_KEYS_POLL_INTERVAL 20
  24519. #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
  24520. -#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
  24521. +#define UBNT_XM_EEPROM_ADDR 0x1fff1000
  24522. static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
  24523. {
  24524. - .name = "ubnt-xm:red:link1",
  24525. + .name = "ubnt:red:link1",
  24526. .gpio = UBNT_XM_GPIO_LED_L1,
  24527. .active_low = 0,
  24528. }, {
  24529. - .name = "ubnt-xm:orange:link2",
  24530. + .name = "ubnt:orange:link2",
  24531. .gpio = UBNT_XM_GPIO_LED_L2,
  24532. .active_low = 0,
  24533. }, {
  24534. - .name = "ubnt-xm:green:link3",
  24535. + .name = "ubnt:green:link3",
  24536. .gpio = UBNT_XM_GPIO_LED_L3,
  24537. .active_low = 0,
  24538. }, {
  24539. - .name = "ubnt-xm:green:link4",
  24540. + .name = "ubnt:green:link4",
  24541. .gpio = UBNT_XM_GPIO_LED_L4,
  24542. .active_low = 0,
  24543. },
  24544. @@ -65,62 +76,625 @@
  24545. }
  24546. };
  24547. -static struct spi_board_info ubnt_xm_spi_info[] = {
  24548. +#define UBNT_M_WAN_PHYMASK BIT(4)
  24549. +
  24550. +static void __init ubnt_xm_init(void)
  24551. +{
  24552. + u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
  24553. + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
  24554. + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
  24555. +
  24556. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
  24557. + ubnt_xm_leds_gpio);
  24558. +
  24559. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24560. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  24561. + ubnt_xm_gpio_keys);
  24562. +
  24563. + ath79_register_m25p80(NULL);
  24564. + ap91_pci_init(eeprom, NULL);
  24565. +
  24566. + ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
  24567. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  24568. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
  24569. + ath79_register_eth(0);
  24570. +}
  24571. +
  24572. +MIPS_MACHINE(ATH79_MACH_UBNT_XM,
  24573. + "UBNT-XM",
  24574. + "Ubiquiti Networks XM (rev 1.0) board",
  24575. + ubnt_xm_init);
  24576. +
  24577. +MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M",
  24578. + ubnt_xm_init);
  24579. +
  24580. +static void __init ubnt_rocket_m_setup(void)
  24581. +{
  24582. + ubnt_xm_init();
  24583. + ath79_register_usb();
  24584. +}
  24585. +
  24586. +MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M",
  24587. + ubnt_rocket_m_setup);
  24588. +
  24589. +static void __init ubnt_nano_m_setup(void)
  24590. +{
  24591. + ubnt_xm_init();
  24592. + ath79_register_eth(1);
  24593. +}
  24594. +
  24595. +MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M",
  24596. + ubnt_nano_m_setup);
  24597. +
  24598. +static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = {
  24599. {
  24600. - .bus_num = 0,
  24601. - .chip_select = 0,
  24602. - .max_speed_hz = 25000000,
  24603. - .modalias = "mx25l6405d",
  24604. + .name = "ubnt:green:globe",
  24605. + .gpio = 0,
  24606. + .active_low = 1,
  24607. + }, {
  24608. + .name = "ubnt:green:power",
  24609. + .gpio = 11,
  24610. + .active_low = 1,
  24611. + .default_state = LEDS_GPIO_DEFSTATE_ON,
  24612. }
  24613. };
  24614. -static struct ath79_spi_platform_data ubnt_xm_spi_data = {
  24615. - .bus_num = 0,
  24616. - .num_chipselect = 1,
  24617. +static void __init ubnt_airrouter_setup(void)
  24618. +{
  24619. + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
  24620. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  24621. +
  24622. + ath79_register_m25p80(NULL);
  24623. + ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
  24624. +
  24625. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  24626. + ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1);
  24627. +
  24628. + ath79_register_eth(1);
  24629. + ath79_register_eth(0);
  24630. + ath79_register_usb();
  24631. +
  24632. + ap91_pci_init(ee, NULL);
  24633. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
  24634. + ubnt_airrouter_leds_gpio);
  24635. +
  24636. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24637. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  24638. + ubnt_xm_gpio_keys);
  24639. +}
  24640. +
  24641. +MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter",
  24642. + ubnt_airrouter_setup);
  24643. +
  24644. +static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = {
  24645. + {
  24646. + .name = "ubnt:orange:dome",
  24647. + .gpio = 1,
  24648. + .active_low = 0,
  24649. + }, {
  24650. + .name = "ubnt:green:dome",
  24651. + .gpio = 0,
  24652. + .active_low = 0,
  24653. + }
  24654. };
  24655. -#ifdef CONFIG_PCI
  24656. -static struct ath9k_platform_data ubnt_xm_eeprom_data;
  24657. +static struct gpio_led ubnt_unifi_outdoor_leds_gpio[] __initdata = {
  24658. + {
  24659. + .name = "ubnt:orange:front",
  24660. + .gpio = 1,
  24661. + .active_low = 0,
  24662. + }, {
  24663. + .name = "ubnt:green:front",
  24664. + .gpio = 0,
  24665. + .active_low = 0,
  24666. + }
  24667. +};
  24668. -static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
  24669. +static struct gpio_led ubnt_unifi_outdoor_plus_leds_gpio[] __initdata = {
  24670. + {
  24671. + .name = "ubnt:white:front",
  24672. + .gpio = 1,
  24673. + .active_low = 0,
  24674. + }, {
  24675. + .name = "ubnt:blue:front",
  24676. + .gpio = 0,
  24677. + .active_low = 0,
  24678. + }
  24679. +};
  24680. +
  24681. +
  24682. +static void __init ubnt_unifi_setup(void)
  24683. {
  24684. - switch (PCI_SLOT(dev->devfn)) {
  24685. - case 0:
  24686. - dev->dev.platform_data = &ubnt_xm_eeprom_data;
  24687. - break;
  24688. + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
  24689. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  24690. +
  24691. + ath79_register_m25p80(NULL);
  24692. +
  24693. + ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
  24694. +
  24695. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  24696. + ath79_register_eth(0);
  24697. +
  24698. + ap91_pci_init(ee, NULL);
  24699. +
  24700. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio),
  24701. + ubnt_unifi_leds_gpio);
  24702. +
  24703. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24704. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  24705. + ubnt_xm_gpio_keys);
  24706. +}
  24707. +
  24708. +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi",
  24709. + ubnt_unifi_setup);
  24710. +
  24711. +
  24712. +#define UBNT_UNIFIOD_PRI_PHYMASK BIT(4)
  24713. +#define UBNT_UNIFIOD_2ND_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  24714. +
  24715. +static void __init ubnt_unifi_outdoor_setup(void)
  24716. +{
  24717. + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
  24718. + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
  24719. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  24720. +
  24721. + ath79_register_m25p80(NULL);
  24722. +
  24723. + ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK |
  24724. + UBNT_UNIFIOD_2ND_PHYMASK));
  24725. +
  24726. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  24727. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
  24728. + ath79_register_eth(0);
  24729. + ath79_register_eth(1);
  24730. +
  24731. + ap91_pci_init(ee, NULL);
  24732. +
  24733. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_leds_gpio),
  24734. + ubnt_unifi_outdoor_leds_gpio);
  24735. +
  24736. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24737. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  24738. + ubnt_xm_gpio_keys);
  24739. +}
  24740. +
  24741. +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR, "UBNT-U20",
  24742. + "Ubiquiti UniFiAP Outdoor",
  24743. + ubnt_unifi_outdoor_setup);
  24744. +
  24745. +
  24746. +static void __init ubnt_unifi_outdoor_plus_setup(void)
  24747. +{
  24748. + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
  24749. + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
  24750. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  24751. +
  24752. + ath79_register_m25p80(NULL);
  24753. +
  24754. + ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK |
  24755. + UBNT_UNIFIOD_2ND_PHYMASK));
  24756. +
  24757. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  24758. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
  24759. + ath79_register_eth(0);
  24760. + ath79_register_eth(1);
  24761. +
  24762. + ap91_pci_init(ee, NULL);
  24763. +
  24764. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_plus_leds_gpio),
  24765. + ubnt_unifi_outdoor_plus_leds_gpio);
  24766. +
  24767. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24768. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  24769. + ubnt_xm_gpio_keys);
  24770. +}
  24771. +
  24772. +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, "UBNT-UOP",
  24773. + "Ubiquiti UniFiAP Outdoor+",
  24774. + ubnt_unifi_outdoor_plus_setup);
  24775. +
  24776. +
  24777. +static struct gpio_led ubnt_uap_pro_gpio_leds[] __initdata = {
  24778. + {
  24779. + .name = "ubnt:white:dome",
  24780. + .gpio = 12,
  24781. + }, {
  24782. + .name = "ubnt:blue:dome",
  24783. + .gpio = 13,
  24784. + }
  24785. +};
  24786. +
  24787. +static struct gpio_keys_button uap_pro_gpio_keys[] __initdata = {
  24788. + {
  24789. + .desc = "reset",
  24790. + .type = EV_KEY,
  24791. + .code = KEY_RESTART,
  24792. + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
  24793. + .gpio = 17,
  24794. + .active_low = 1,
  24795. }
  24796. +};
  24797. +
  24798. +static struct ar8327_pad_cfg uap_pro_ar8327_pad0_cfg = {
  24799. + .mode = AR8327_PAD_MAC_RGMII,
  24800. + .txclk_delay_en = true,
  24801. + .rxclk_delay_en = true,
  24802. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  24803. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  24804. +};
  24805. +
  24806. +static struct ar8327_platform_data uap_pro_ar8327_data = {
  24807. + .pad0_cfg = &uap_pro_ar8327_pad0_cfg,
  24808. + .port0_cfg = {
  24809. + .force_link = 1,
  24810. + .speed = AR8327_PORT_SPEED_1000,
  24811. + .duplex = 1,
  24812. + .txpause = 1,
  24813. + .rxpause = 1,
  24814. + },
  24815. +};
  24816. +
  24817. +static struct mdio_board_info uap_pro_mdio0_info[] = {
  24818. + {
  24819. + .bus_id = "ag71xx-mdio.0",
  24820. + .phy_addr = 0,
  24821. + .platform_data = &uap_pro_ar8327_data,
  24822. + },
  24823. +};
  24824. +
  24825. +#define UAP_PRO_MAC0_OFFSET 0x0000
  24826. +#define UAP_PRO_MAC1_OFFSET 0x0006
  24827. +#define UAP_PRO_WMAC_CALDATA_OFFSET 0x1000
  24828. +#define UAP_PRO_PCI_CALDATA_OFFSET 0x5000
  24829. +
  24830. +static void __init ubnt_uap_pro_setup(void)
  24831. +{
  24832. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
  24833. +
  24834. + ath79_register_m25p80(NULL);
  24835. +
  24836. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds),
  24837. + ubnt_uap_pro_gpio_leds);
  24838. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24839. + ARRAY_SIZE(uap_pro_gpio_keys),
  24840. + uap_pro_gpio_keys);
  24841. +
  24842. + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
  24843. + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
  24844. +
  24845. + ath79_register_mdio(0, 0x0);
  24846. + mdiobus_register_board_info(uap_pro_mdio0_info,
  24847. + ARRAY_SIZE(uap_pro_mdio0_info));
  24848. +
  24849. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  24850. + ath79_init_mac(ath79_eth0_data.mac_addr,
  24851. + eeprom + UAP_PRO_MAC0_OFFSET, 0);
  24852. +
  24853. + /* GMAC0 is connected to an AR8327 switch */
  24854. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  24855. + ath79_eth0_data.phy_mask = BIT(0);
  24856. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  24857. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  24858. + ath79_register_eth(0);
  24859. +}
  24860. +
  24861. +MIPS_MACHINE(ATH79_MACH_UBNT_UAP_PRO, "UAP-PRO", "Ubiquiti UniFi AP Pro",
  24862. + ubnt_uap_pro_setup);
  24863. +
  24864. +#define UBNT_XW_GPIO_LED_L1 11
  24865. +#define UBNT_XW_GPIO_LED_L2 16
  24866. +#define UBNT_XW_GPIO_LED_L3 13
  24867. +#define UBNT_XW_GPIO_LED_L4 14
  24868. +
  24869. +static struct gpio_led ubnt_xw_leds_gpio[] __initdata = {
  24870. + {
  24871. + .name = "ubnt:red:link1",
  24872. + .gpio = UBNT_XW_GPIO_LED_L1,
  24873. + .active_low = 1,
  24874. + }, {
  24875. + .name = "ubnt:orange:link2",
  24876. + .gpio = UBNT_XW_GPIO_LED_L2,
  24877. + .active_low = 1,
  24878. + }, {
  24879. + .name = "ubnt:green:link3",
  24880. + .gpio = UBNT_XW_GPIO_LED_L3,
  24881. + .active_low = 1,
  24882. + }, {
  24883. + .name = "ubnt:green:link4",
  24884. + .gpio = UBNT_XW_GPIO_LED_L4,
  24885. + .active_low = 1,
  24886. + },
  24887. +};
  24888. +
  24889. +#define UBNT_ROCKET_TI_GPIO_LED_L1 16
  24890. +#define UBNT_ROCKET_TI_GPIO_LED_L2 17
  24891. +#define UBNT_ROCKET_TI_GPIO_LED_L3 18
  24892. +#define UBNT_ROCKET_TI_GPIO_LED_L4 19
  24893. +#define UBNT_ROCKET_TI_GPIO_LED_L5 20
  24894. +#define UBNT_ROCKET_TI_GPIO_LED_L6 21
  24895. +static struct gpio_led ubnt_rocket_ti_leds_gpio[] __initdata = {
  24896. + {
  24897. + .name = "ubnt:green:link1",
  24898. + .gpio = UBNT_ROCKET_TI_GPIO_LED_L1,
  24899. + .active_low = 1,
  24900. + }, {
  24901. + .name = "ubnt:green:link2",
  24902. + .gpio = UBNT_ROCKET_TI_GPIO_LED_L2,
  24903. + .active_low = 1,
  24904. + }, {
  24905. + .name = "ubnt:green:link3",
  24906. + .gpio = UBNT_ROCKET_TI_GPIO_LED_L3,
  24907. + .active_low = 1,
  24908. + }, {
  24909. + .name = "ubnt:green:link4",
  24910. + .gpio = UBNT_ROCKET_TI_GPIO_LED_L4,
  24911. + .active_low = 0,
  24912. + }, {
  24913. + .name = "ubnt:green:link5",
  24914. + .gpio = UBNT_ROCKET_TI_GPIO_LED_L5,
  24915. + .active_low = 0,
  24916. + }, {
  24917. + .name = "ubnt:green:link6",
  24918. + .gpio = UBNT_ROCKET_TI_GPIO_LED_L6,
  24919. + .active_low = 0,
  24920. + },
  24921. +};
  24922. - return 0;
  24923. +static void __init ubnt_xw_init(void)
  24924. +{
  24925. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
  24926. +
  24927. + ath79_register_m25p80(NULL);
  24928. +
  24929. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio),
  24930. + ubnt_xw_leds_gpio);
  24931. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24932. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  24933. + ubnt_xm_gpio_keys);
  24934. +
  24935. + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
  24936. + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
  24937. +
  24938. +
  24939. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0_SLAVE);
  24940. + ath79_init_mac(ath79_eth0_data.mac_addr,
  24941. + eeprom + UAP_PRO_MAC0_OFFSET, 0);
  24942. +
  24943. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  24944. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  24945. }
  24946. -static void __init ubnt_xm_pci_init(void)
  24947. +static void __init ubnt_nano_m_xw_setup(void)
  24948. {
  24949. - memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
  24950. - sizeof(ubnt_xm_eeprom_data.eeprom_data));
  24951. + ubnt_xw_init();
  24952. - ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
  24953. - ath79_register_pci();
  24954. + /* GMAC0 is connected to an AR8326 switch */
  24955. + ath79_register_mdio(0, ~(BIT(0) | BIT(1) | BIT(5)));
  24956. + ath79_eth0_data.phy_mask = (BIT(0) | BIT(1) | BIT(5));
  24957. + ath79_eth0_data.speed = SPEED_100;
  24958. + ath79_eth0_data.duplex = DUPLEX_FULL;
  24959. + ath79_register_eth(0);
  24960. }
  24961. -#else
  24962. -static inline void ubnt_xm_pci_init(void) {}
  24963. -#endif /* CONFIG_PCI */
  24964. -static void __init ubnt_xm_init(void)
  24965. +static void __init ubnt_loco_m_xw_setup(void)
  24966. {
  24967. - ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
  24968. - ubnt_xm_leds_gpio);
  24969. + ubnt_xw_init();
  24970. + ath79_register_mdio(0, ~BIT(1));
  24971. + ath79_eth0_data.phy_mask = BIT(1);
  24972. + ath79_register_eth(0);
  24973. +}
  24974. +
  24975. +static void __init ubnt_rocket_m_xw_setup(void)
  24976. +{
  24977. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
  24978. +
  24979. + ath79_register_m25p80(NULL);
  24980. +
  24981. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio),
  24982. + ubnt_xw_leds_gpio);
  24983. ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  24984. - ARRAY_SIZE(ubnt_xm_gpio_keys),
  24985. - ubnt_xm_gpio_keys);
  24986. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  24987. + ubnt_xm_gpio_keys);
  24988. - ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
  24989. - ARRAY_SIZE(ubnt_xm_spi_info));
  24990. + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
  24991. + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
  24992. - ubnt_xm_pci_init();
  24993. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  24994. + ath79_init_mac(ath79_eth0_data.mac_addr,
  24995. + eeprom + UAP_PRO_MAC0_OFFSET, 0);
  24996. +
  24997. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  24998. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  24999. +
  25000. + ath79_register_mdio(0, ~BIT(4));
  25001. + ath79_eth0_data.phy_mask = BIT(4);
  25002. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  25003. + ath79_register_eth(0);
  25004. }
  25005. -MIPS_MACHINE(ATH79_MACH_UBNT_XM,
  25006. - "UBNT-XM",
  25007. - "Ubiquiti Networks XM (rev 1.0) board",
  25008. - ubnt_xm_init);
  25009. +static struct at803x_platform_data ubnt_rocket_m_ti_at803_data = {
  25010. + .disable_smarteee = 1,
  25011. + .enable_rgmii_rx_delay = 1,
  25012. + .enable_rgmii_tx_delay = 1,
  25013. +};
  25014. +static struct mdio_board_info ubnt_rocket_m_ti_mdio_info[] = {
  25015. + {
  25016. + .bus_id = "ag71xx-mdio.0",
  25017. + .phy_addr = 4,
  25018. + .platform_data = &ubnt_rocket_m_ti_at803_data,
  25019. + },
  25020. +};
  25021. +
  25022. +static void __init ubnt_rocket_m_ti_setup(void)
  25023. +{
  25024. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
  25025. +
  25026. + ath79_register_m25p80(NULL);
  25027. +
  25028. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rocket_ti_leds_gpio),
  25029. + ubnt_rocket_ti_leds_gpio);
  25030. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  25031. + ARRAY_SIZE(ubnt_xm_gpio_keys),
  25032. + ubnt_xm_gpio_keys);
  25033. +
  25034. + ap91_pci_init(eeprom + 0x1000, NULL);
  25035. +
  25036. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  25037. + ath79_setup_ar934x_eth_rx_delay(3, 3);
  25038. + ath79_init_mac(ath79_eth0_data.mac_addr,
  25039. + eeprom + UAP_PRO_MAC0_OFFSET, 0);
  25040. + ath79_init_mac(ath79_eth1_data.mac_addr,
  25041. + eeprom + UAP_PRO_MAC1_OFFSET, 0);
  25042. +
  25043. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  25044. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  25045. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  25046. + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
  25047. +
  25048. + mdiobus_register_board_info(ubnt_rocket_m_ti_mdio_info,
  25049. + ARRAY_SIZE(ubnt_rocket_m_ti_mdio_info));
  25050. + ath79_register_mdio(0, 0x0);
  25051. +
  25052. +
  25053. + ath79_eth0_data.phy_mask = BIT(4);
  25054. + /* read out from vendor */
  25055. + ath79_eth0_pll_data.pll_1000 = 0x2000000;
  25056. + ath79_eth0_pll_data.pll_10 = 0x1313;
  25057. + ath79_register_eth(0);
  25058. +
  25059. + ath79_register_mdio(1, 0x0);
  25060. + ath79_eth1_data.phy_mask = BIT(3);
  25061. + ath79_register_eth(1);
  25062. +}
  25063. +
  25064. +
  25065. +MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M_XW, "UBNT-NM-XW", "Ubiquiti Nanostation M XW",
  25066. + ubnt_nano_m_xw_setup);
  25067. +
  25068. +MIPS_MACHINE(ATH79_MACH_UBNT_LOCO_M_XW, "UBNT-LOCO-XW", "Ubiquiti Loco M XW",
  25069. + ubnt_loco_m_xw_setup);
  25070. +
  25071. +MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_XW, "UBNT-RM-XW", "Ubiquiti Rocket M XW",
  25072. + ubnt_rocket_m_xw_setup);
  25073. +
  25074. +MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_TI, "UBNT-RM-TI", "Ubiquiti Rocket M TI",
  25075. + ubnt_rocket_m_ti_setup);
  25076. +
  25077. +static struct gpio_led ubnt_airgateway_gpio_leds[] __initdata = {
  25078. + {
  25079. + .name = "ubnt:blue:wlan",
  25080. + .gpio = 0,
  25081. + }, {
  25082. + .name = "ubnt:white:status",
  25083. + .gpio = 1,
  25084. + },
  25085. +};
  25086. +
  25087. +static struct gpio_keys_button airgateway_gpio_keys[] __initdata = {
  25088. + {
  25089. + .desc = "reset",
  25090. + .type = EV_KEY,
  25091. + .code = KEY_RESTART,
  25092. + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
  25093. + .gpio = 12,
  25094. + .active_low = 1,
  25095. + }
  25096. +};
  25097. +
  25098. +static void __init ubnt_airgateway_setup(void)
  25099. +{
  25100. + u32 t;
  25101. + u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000);
  25102. + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
  25103. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  25104. +
  25105. +
  25106. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  25107. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  25108. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  25109. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  25110. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  25111. +
  25112. + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  25113. + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
  25114. + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
  25115. +
  25116. + ath79_register_m25p80(NULL);
  25117. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_gpio_leds),
  25118. + ubnt_airgateway_gpio_leds);
  25119. +
  25120. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  25121. + ARRAY_SIZE(airgateway_gpio_keys),
  25122. + airgateway_gpio_keys);
  25123. +
  25124. + ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0);
  25125. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  25126. +
  25127. + ath79_register_mdio(0, 0x0);
  25128. +
  25129. + ath79_register_eth(1);
  25130. + ath79_register_eth(0);
  25131. +
  25132. + ath79_register_wmac(ee, NULL);
  25133. +}
  25134. +
  25135. +MIPS_MACHINE(ATH79_MACH_UBNT_AIRGW, "UBNT-AGW", "Ubiquiti AirGateway",
  25136. + ubnt_airgateway_setup);
  25137. +
  25138. +static struct gpio_led ubnt_airgateway_pro_gpio_leds[] __initdata = {
  25139. + {
  25140. + .name = "ubnt:blue:wlan",
  25141. + .gpio = 13,
  25142. + }, {
  25143. + .name = "ubnt:white:status",
  25144. + .gpio = 17,
  25145. + },
  25146. +};
  25147. +
  25148. +
  25149. +static struct gpio_keys_button airgateway_pro_gpio_keys[] __initdata = {
  25150. + {
  25151. + .desc = "reset",
  25152. + .type = EV_KEY,
  25153. + .code = KEY_RESTART,
  25154. + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
  25155. + .gpio = 12,
  25156. + .active_low = 1,
  25157. + }
  25158. +};
  25159. +
  25160. +static void __init ubnt_airgateway_pro_setup(void)
  25161. +{
  25162. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
  25163. + u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000);
  25164. +
  25165. + ath79_register_m25p80(NULL);
  25166. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_pro_gpio_leds),
  25167. + ubnt_airgateway_pro_gpio_leds);
  25168. +
  25169. + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
  25170. + ARRAY_SIZE(airgateway_pro_gpio_keys),
  25171. + airgateway_pro_gpio_keys);
  25172. +
  25173. + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
  25174. + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
  25175. +
  25176. +
  25177. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  25178. +
  25179. + ath79_register_mdio(1, 0x0);
  25180. +
  25181. + /* GMAC0 is left unused in this configuration */
  25182. +
  25183. + /* GMAC1 is connected to MAC0 on the internal switch */
  25184. + /* The PoE/WAN port connects to port 5 on the internal switch */
  25185. + /* The LAN port connects to port 4 on the internal switch */
  25186. + ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0);
  25187. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  25188. + ath79_register_eth(1);
  25189. +
  25190. +}
  25191. +
  25192. +MIPS_MACHINE(ATH79_MACH_UBNT_AIRGWP, "UBNT-AGWP", "Ubiquiti AirGateway Pro",
  25193. + ubnt_airgateway_pro_setup);
  25194. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-ubnt.c linux-4.1.43/arch/mips/ath79/mach-ubnt.c
  25195. --- linux-4.1.43.orig/arch/mips/ath79/mach-ubnt.c 1970-01-01 01:00:00.000000000 +0100
  25196. +++ linux-4.1.43/arch/mips/ath79/mach-ubnt.c 2017-08-06 20:02:15.000000000 +0200
  25197. @@ -0,0 +1,205 @@
  25198. +/*
  25199. + * Ubiquiti RouterStation support
  25200. + *
  25201. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  25202. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  25203. + * Copyright (C) 2008 Ubiquiti <support@ubnt.com>
  25204. + *
  25205. + * This program is free software; you can redistribute it and/or modify it
  25206. + * under the terms of the GNU General Public License version 2 as published
  25207. + * by the Free Software Foundation.
  25208. + */
  25209. +
  25210. +#include <asm/mach-ath79/ath79.h>
  25211. +
  25212. +#include "dev-eth.h"
  25213. +#include "dev-gpio-buttons.h"
  25214. +#include "dev-leds-gpio.h"
  25215. +#include "dev-m25p80.h"
  25216. +#include "dev-usb.h"
  25217. +#include "machtypes.h"
  25218. +#include "pci.h"
  25219. +
  25220. +#define UBNT_RS_GPIO_LED_RF 2
  25221. +#define UBNT_RS_GPIO_SW4 8
  25222. +
  25223. +#define UBNT_LS_SR71_GPIO_LED_D25 0
  25224. +#define UBNT_LS_SR71_GPIO_LED_D26 1
  25225. +#define UBNT_LS_SR71_GPIO_LED_D24 2
  25226. +#define UBNT_LS_SR71_GPIO_LED_D23 4
  25227. +#define UBNT_LS_SR71_GPIO_LED_D22 5
  25228. +#define UBNT_LS_SR71_GPIO_LED_D27 6
  25229. +#define UBNT_LS_SR71_GPIO_LED_D28 7
  25230. +
  25231. +#define UBNT_KEYS_POLL_INTERVAL 20 /* msecs */
  25232. +#define UBNT_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_KEYS_POLL_INTERVAL)
  25233. +
  25234. +static struct gpio_led ubnt_rs_leds_gpio[] __initdata = {
  25235. + {
  25236. + .name = "ubnt:green:rf",
  25237. + .gpio = UBNT_RS_GPIO_LED_RF,
  25238. + .active_low = 0,
  25239. + }
  25240. +};
  25241. +
  25242. +static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = {
  25243. + {
  25244. + .name = "ubnt:green:d22",
  25245. + .gpio = UBNT_LS_SR71_GPIO_LED_D22,
  25246. + .active_low = 0,
  25247. + }, {
  25248. + .name = "ubnt:green:d23",
  25249. + .gpio = UBNT_LS_SR71_GPIO_LED_D23,
  25250. + .active_low = 0,
  25251. + }, {
  25252. + .name = "ubnt:green:d24",
  25253. + .gpio = UBNT_LS_SR71_GPIO_LED_D24,
  25254. + .active_low = 0,
  25255. + }, {
  25256. + .name = "ubnt:red:d25",
  25257. + .gpio = UBNT_LS_SR71_GPIO_LED_D25,
  25258. + .active_low = 0,
  25259. + }, {
  25260. + .name = "ubnt:red:d26",
  25261. + .gpio = UBNT_LS_SR71_GPIO_LED_D26,
  25262. + .active_low = 0,
  25263. + }, {
  25264. + .name = "ubnt:green:d27",
  25265. + .gpio = UBNT_LS_SR71_GPIO_LED_D27,
  25266. + .active_low = 0,
  25267. + }, {
  25268. + .name = "ubnt:green:d28",
  25269. + .gpio = UBNT_LS_SR71_GPIO_LED_D28,
  25270. + .active_low = 0,
  25271. + }
  25272. +};
  25273. +
  25274. +static struct gpio_keys_button ubnt_gpio_keys[] __initdata = {
  25275. + {
  25276. + .desc = "sw4",
  25277. + .type = EV_KEY,
  25278. + .code = KEY_RESTART,
  25279. + .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL,
  25280. + .gpio = UBNT_RS_GPIO_SW4,
  25281. + .active_low = 1,
  25282. + }
  25283. +};
  25284. +
  25285. +static const char *ubnt_part_probes[] = {
  25286. + "RedBoot",
  25287. + NULL,
  25288. +};
  25289. +
  25290. +static struct flash_platform_data ubnt_flash_data = {
  25291. + .part_probes = ubnt_part_probes,
  25292. +};
  25293. +
  25294. +static void __init ubnt_generic_setup(void)
  25295. +{
  25296. + ath79_register_m25p80(&ubnt_flash_data);
  25297. +
  25298. + ath79_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL,
  25299. + ARRAY_SIZE(ubnt_gpio_keys),
  25300. + ubnt_gpio_keys);
  25301. + ath79_register_pci();
  25302. +}
  25303. +
  25304. +#define UBNT_RS_WAN_PHYMASK BIT(20)
  25305. +#define UBNT_RS_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19))
  25306. +
  25307. +static void __init ubnt_rs_setup(void)
  25308. +{
  25309. + ubnt_generic_setup();
  25310. +
  25311. + ath79_register_mdio(0, ~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK));
  25312. +
  25313. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  25314. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  25315. + ath79_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK;
  25316. +
  25317. + /*
  25318. + * There is Secondary MAC address duplicate problem with some
  25319. + * UBNT HW batches. Do not increase Secondary MAC address by 1
  25320. + * but do workaround with 'Locally Administrated' bit.
  25321. + */
  25322. + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base);
  25323. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  25324. + ath79_eth1_data.speed = SPEED_100;
  25325. + ath79_eth1_data.duplex = DUPLEX_FULL;
  25326. +
  25327. + ath79_register_eth(0);
  25328. + ath79_register_eth(1);
  25329. +
  25330. + ath79_register_usb();
  25331. +
  25332. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio),
  25333. + ubnt_rs_leds_gpio);
  25334. +}
  25335. +
  25336. +MIPS_MACHINE(ATH79_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation",
  25337. + ubnt_rs_setup);
  25338. +
  25339. +#define UBNT_RSPRO_WAN_PHYMASK BIT(4)
  25340. +#define UBNT_RSPRO_LAN_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  25341. +
  25342. +static void __init ubnt_rspro_setup(void)
  25343. +{
  25344. + ubnt_generic_setup();
  25345. +
  25346. + ath79_register_mdio(0, ~(UBNT_RSPRO_WAN_PHYMASK |
  25347. + UBNT_RSPRO_LAN_PHYMASK));
  25348. +
  25349. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  25350. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  25351. + ath79_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK;
  25352. +
  25353. + /*
  25354. + * There is Secondary MAC address duplicate problem with some
  25355. + * UBNT HW batches. Do not increase Secondary MAC address by 1
  25356. + * but do workaround with 'Locally Administrated' bit.
  25357. + */
  25358. + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base);
  25359. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  25360. + ath79_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK;
  25361. + ath79_eth1_data.speed = SPEED_1000;
  25362. + ath79_eth1_data.duplex = DUPLEX_FULL;
  25363. +
  25364. + ath79_register_eth(0);
  25365. + ath79_register_eth(1);
  25366. +
  25367. + ath79_register_usb();
  25368. +
  25369. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio),
  25370. + ubnt_rs_leds_gpio);
  25371. +}
  25372. +
  25373. +MIPS_MACHINE(ATH79_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro",
  25374. + ubnt_rspro_setup);
  25375. +
  25376. +static void __init ubnt_lsx_setup(void)
  25377. +{
  25378. + ubnt_generic_setup();
  25379. +}
  25380. +
  25381. +MIPS_MACHINE(ATH79_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup);
  25382. +
  25383. +#define UBNT_LSSR71_PHY_MASK BIT(1)
  25384. +
  25385. +static void __init ubnt_lssr71_setup(void)
  25386. +{
  25387. + ubnt_generic_setup();
  25388. +
  25389. + ath79_register_mdio(0, ~UBNT_LSSR71_PHY_MASK);
  25390. +
  25391. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  25392. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  25393. + ath79_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK;
  25394. +
  25395. + ath79_register_eth(0);
  25396. +
  25397. + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio),
  25398. + ubnt_ls_sr71_leds_gpio);
  25399. +}
  25400. +
  25401. +MIPS_MACHINE(ATH79_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71",
  25402. + ubnt_lssr71_setup);
  25403. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-weio.c linux-4.1.43/arch/mips/ath79/mach-weio.c
  25404. --- linux-4.1.43.orig/arch/mips/ath79/mach-weio.c 1970-01-01 01:00:00.000000000 +0100
  25405. +++ linux-4.1.43/arch/mips/ath79/mach-weio.c 2017-08-06 20:02:15.000000000 +0200
  25406. @@ -0,0 +1,140 @@
  25407. +/**
  25408. + * WEIO Web Of Things Platform
  25409. + *
  25410. + * Copyright (C) 2013 Drasko DRASKOVIC and Uros PETREVSKI
  25411. + *
  25412. + * ## ## ######## #### #######
  25413. + * ## ## ## ## ## ## ##
  25414. + * ## ## ## ## ## ## ##
  25415. + * ## ## ## ###### ## ## ##
  25416. + * ## ## ## ## ## ## ##
  25417. + * ## ## ## ## ## ## ##
  25418. + * ### ### ######## #### #######
  25419. + *
  25420. + * Web Of Things Platform
  25421. + *
  25422. + * This program is free software; you can redistribute it and/or
  25423. + * modify it under the terms of the GNU General Public License
  25424. + * as published by the Free Software Foundation; either version 2
  25425. + * of the License, or (at your option) any later version.
  25426. + *
  25427. + * This program is distributed in the hope that it will be useful,
  25428. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25429. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25430. + * GNU General Public License for more details.
  25431. + *
  25432. + * You should have received a copy of the GNU General Public License
  25433. + * along with this program; if not, write to the Free Software
  25434. + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  25435. + *
  25436. + * Authors :
  25437. + * Drasko DRASKOVIC <drasko.draskovic@gmail.com>
  25438. + * Uros PETREVSKI <uros@nodesign.net>
  25439. + */
  25440. +
  25441. +#include <asm/mach-ath79/ath79.h>
  25442. +#include <asm/mach-ath79/ar71xx_regs.h>
  25443. +#include <linux/i2c-gpio.h>
  25444. +#include <linux/platform_device.h>
  25445. +#include "common.h"
  25446. +#include "dev-eth.h"
  25447. +#include "dev-gpio-buttons.h"
  25448. +#include "dev-leds-gpio.h"
  25449. +#include "dev-m25p80.h"
  25450. +#include "dev-spi.h"
  25451. +#include "dev-usb.h"
  25452. +#include "dev-wmac.h"
  25453. +#include "machtypes.h"
  25454. +
  25455. +#define WEIO_GPIO_LED_STA 1
  25456. +#define WEIO_GPIO_LED_AP 16
  25457. +
  25458. +#define WEIO_GPIO_BTN_AP 20
  25459. +#define WEIO_GPIO_BTN_RESET 23
  25460. +
  25461. +#define WEIO_KEYS_POLL_INTERVAL 20 /* msecs */
  25462. +#define WEIO_KEYS_DEBOUNCE_INTERVAL (3 * WEIO_KEYS_POLL_INTERVAL)
  25463. +
  25464. +#define WEIO_MAC0_OFFSET 0x0000
  25465. +#define WEIO_MAC1_OFFSET 0x0006
  25466. +#define WEIO_CALDATA_OFFSET 0x1000
  25467. +#define WEIO_WMAC_MAC_OFFSET 0x1002
  25468. +
  25469. +static struct gpio_led weio_leds_gpio[] __initdata = {
  25470. + {
  25471. + .name = "weio:green:sta",
  25472. + .gpio = WEIO_GPIO_LED_STA,
  25473. + .active_low = 1,
  25474. + .default_state = LEDS_GPIO_DEFSTATE_ON,
  25475. + },
  25476. + {
  25477. + .name = "weio:green:ap",
  25478. + .gpio = WEIO_GPIO_LED_AP,
  25479. + .active_low = 1,
  25480. + .default_state = LEDS_GPIO_DEFSTATE_ON,
  25481. + }
  25482. +};
  25483. +
  25484. +static struct gpio_keys_button weio_gpio_keys[] __initdata = {
  25485. + {
  25486. + .desc = "ap button",
  25487. + .type = EV_KEY,
  25488. + .code = BTN_0,
  25489. + .debounce_interval = WEIO_KEYS_DEBOUNCE_INTERVAL,
  25490. + .gpio = WEIO_GPIO_BTN_AP,
  25491. + .active_low = 1,
  25492. + },
  25493. + {
  25494. + .desc = "soft-reset button",
  25495. + .type = EV_KEY,
  25496. + .code = BTN_1,
  25497. + .debounce_interval = WEIO_KEYS_DEBOUNCE_INTERVAL,
  25498. + .gpio = WEIO_GPIO_BTN_RESET,
  25499. + .active_low = 1,
  25500. + }
  25501. +};
  25502. +
  25503. +static struct i2c_gpio_platform_data weio_i2c_gpio_data = {
  25504. + .sda_pin = 18,
  25505. + .scl_pin = 19,
  25506. +};
  25507. +
  25508. +static struct platform_device weio_i2c_gpio = {
  25509. + .name = "i2c-gpio",
  25510. + .id = 0,
  25511. + .dev = {
  25512. + .platform_data = &weio_i2c_gpio_data,
  25513. + },
  25514. +};
  25515. +
  25516. +static void __init weio_common_setup(void)
  25517. +{
  25518. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  25519. +
  25520. + ath79_register_m25p80(NULL);
  25521. + ath79_register_wmac(art + WEIO_CALDATA_OFFSET, art + WEIO_WMAC_MAC_OFFSET);
  25522. +}
  25523. +
  25524. +static void __init weio_setup(void)
  25525. +{
  25526. + weio_common_setup();
  25527. +
  25528. + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  25529. + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  25530. + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  25531. + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  25532. + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  25533. +
  25534. + platform_device_register(&weio_i2c_gpio);
  25535. +
  25536. + ath79_register_leds_gpio(-1, ARRAY_SIZE(weio_leds_gpio),
  25537. + weio_leds_gpio);
  25538. +
  25539. + ath79_register_gpio_keys_polled(-1, WEIO_KEYS_POLL_INTERVAL,
  25540. + ARRAY_SIZE(weio_gpio_keys),
  25541. + weio_gpio_keys);
  25542. +
  25543. + ath79_register_usb();
  25544. +}
  25545. +
  25546. +MIPS_MACHINE(ATH79_MACH_WEIO, "WEIO", "WeIO board", weio_setup);
  25547. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-whr-hp-g300n.c linux-4.1.43/arch/mips/ath79/mach-whr-hp-g300n.c
  25548. --- linux-4.1.43.orig/arch/mips/ath79/mach-whr-hp-g300n.c 1970-01-01 01:00:00.000000000 +0100
  25549. +++ linux-4.1.43/arch/mips/ath79/mach-whr-hp-g300n.c 2017-08-06 20:02:15.000000000 +0200
  25550. @@ -0,0 +1,155 @@
  25551. +/*
  25552. + * Buffalo WHR-HP-G300N board support
  25553. + *
  25554. + * based on ...
  25555. + *
  25556. + * TP-LINK TL-WR741ND board support
  25557. + *
  25558. + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
  25559. + *
  25560. + * This program is free software; you can redistribute it and/or modify it
  25561. + * under the terms of the GNU General Public License version 2 as published
  25562. + * by the Free Software Foundation.
  25563. + */
  25564. +
  25565. +#include <asm/mach-ath79/ath79.h>
  25566. +#include <asm/mach-ath79/ar71xx_regs.h>
  25567. +
  25568. +#include "common.h"
  25569. +#include "dev-ap9x-pci.h"
  25570. +#include "dev-eth.h"
  25571. +#include "dev-gpio-buttons.h"
  25572. +#include "dev-leds-gpio.h"
  25573. +#include "dev-m25p80.h"
  25574. +#include "machtypes.h"
  25575. +
  25576. +#define WHRHPG300N_GPIO_LED_SECURITY 0
  25577. +#define WHRHPG300N_GPIO_LED_DIAG 1
  25578. +#define WHRHPG300N_GPIO_LED_ROUTER 6
  25579. +
  25580. +#define WHRHPG300N_GPIO_BTN_ROUTER_ON 7
  25581. +#define WHRHPG300N_GPIO_BTN_ROUTER_AUTO 8
  25582. +#define WHRHPG300N_GPIO_BTN_RESET 11
  25583. +#define WHRHPG300N_GPIO_BTN_AOSS 12
  25584. +#define WHRHPG300N_GPIO_LED_LAN1 13
  25585. +#define WHRHPG300N_GPIO_LED_LAN2 14
  25586. +#define WHRHPG300N_GPIO_LED_LAN3 15
  25587. +#define WHRHPG300N_GPIO_LED_LAN4 16
  25588. +#define WHRHPG300N_GPIO_LED_WAN 17
  25589. +
  25590. +#define WHRHPG300N_KEYS_POLL_INTERVAL 20 /* msecs */
  25591. +#define WHRHPG300N_KEYS_DEBOUNCE_INTERVAL (3 * WHRHPG300N_KEYS_POLL_INTERVAL)
  25592. +
  25593. +#define WHRHPG300N_MAC_OFFSET 0x20c
  25594. +
  25595. +static struct gpio_led whrhpg300n_leds_gpio[] __initdata = {
  25596. + {
  25597. + .name = "buffalo:orange:security",
  25598. + .gpio = WHRHPG300N_GPIO_LED_SECURITY,
  25599. + .active_low = 1,
  25600. + }, {
  25601. + .name = "buffalo:red:diag",
  25602. + .gpio = WHRHPG300N_GPIO_LED_DIAG,
  25603. + .active_low = 1,
  25604. + }, {
  25605. + .name = "buffalo:green:router",
  25606. + .gpio = WHRHPG300N_GPIO_LED_ROUTER,
  25607. + .active_low = 1,
  25608. + }, {
  25609. + .name = "buffalo:green:wan",
  25610. + .gpio = WHRHPG300N_GPIO_LED_WAN,
  25611. + .active_low = 1,
  25612. + }, {
  25613. + .name = "buffalo:green:lan1",
  25614. + .gpio = WHRHPG300N_GPIO_LED_LAN1,
  25615. + .active_low = 1,
  25616. + }, {
  25617. + .name = "buffalo:green:lan2",
  25618. + .gpio = WHRHPG300N_GPIO_LED_LAN2,
  25619. + .active_low = 1,
  25620. + }, {
  25621. + .name = "buffalo:green:lan3",
  25622. + .gpio = WHRHPG300N_GPIO_LED_LAN3,
  25623. + .active_low = 1,
  25624. + }, {
  25625. + .name = "buffalo:green:lan4",
  25626. + .gpio = WHRHPG300N_GPIO_LED_LAN4,
  25627. + .active_low = 1,
  25628. + }
  25629. +};
  25630. +
  25631. +static struct gpio_keys_button whrhpg300n_gpio_keys[] __initdata = {
  25632. + {
  25633. + .desc = "reset",
  25634. + .type = EV_KEY,
  25635. + .code = KEY_RESTART,
  25636. + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
  25637. + .gpio = WHRHPG300N_GPIO_BTN_RESET,
  25638. + .active_low = 1,
  25639. + }, {
  25640. + .desc = "aoss/wps",
  25641. + .type = EV_KEY,
  25642. + .code = KEY_WPS_BUTTON,
  25643. + .gpio = WHRHPG300N_GPIO_BTN_AOSS,
  25644. + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
  25645. + .active_low = 1,
  25646. + }, {
  25647. + .desc = "router_on",
  25648. + .type = EV_KEY,
  25649. + .code = BTN_2,
  25650. + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_ON,
  25651. + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
  25652. + .active_low = 1,
  25653. + }, {
  25654. + .desc = "router_auto",
  25655. + .type = EV_KEY,
  25656. + .code = BTN_3,
  25657. + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_AUTO,
  25658. + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
  25659. + .active_low = 1,
  25660. + }
  25661. +};
  25662. +
  25663. +static void __init whrhpg300n_setup(void)
  25664. +{
  25665. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  25666. + u8 *mac = (u8 *) KSEG1ADDR(ee + WHRHPG300N_MAC_OFFSET);
  25667. +
  25668. + ath79_register_m25p80(NULL);
  25669. +
  25670. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  25671. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  25672. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  25673. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  25674. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  25675. +
  25676. + ath79_register_leds_gpio(-1, ARRAY_SIZE(whrhpg300n_leds_gpio),
  25677. + whrhpg300n_leds_gpio);
  25678. +
  25679. + ath79_register_gpio_keys_polled(-1, WHRHPG300N_KEYS_POLL_INTERVAL,
  25680. + ARRAY_SIZE(whrhpg300n_gpio_keys),
  25681. + whrhpg300n_gpio_keys);
  25682. +
  25683. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  25684. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  25685. +
  25686. + ath79_register_mdio(0, 0x0);
  25687. +
  25688. + /* LAN ports */
  25689. + ath79_register_eth(1);
  25690. + /* WAN port */
  25691. + ath79_register_eth(0);
  25692. +
  25693. + ap9x_pci_setup_wmac_led_pin(0, 1);
  25694. +
  25695. + ap91_pci_init(ee, mac);
  25696. +}
  25697. +
  25698. +MIPS_MACHINE(ATH79_MACH_WHR_HP_G300N, "WHR-HP-G300N", "Buffalo WHR-HP-G300N",
  25699. + whrhpg300n_setup);
  25700. +
  25701. +MIPS_MACHINE(ATH79_MACH_WHR_G301N, "WHR-G301N", "Buffalo WHR-G301N",
  25702. + whrhpg300n_setup);
  25703. +
  25704. +MIPS_MACHINE(ATH79_MACH_WHR_HP_GN, "WHR-HP-GN", "Buffalo WHR-HP-GN",
  25705. + whrhpg300n_setup);
  25706. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wlae-ag300n.c linux-4.1.43/arch/mips/ath79/mach-wlae-ag300n.c
  25707. --- linux-4.1.43.orig/arch/mips/ath79/mach-wlae-ag300n.c 1970-01-01 01:00:00.000000000 +0100
  25708. +++ linux-4.1.43/arch/mips/ath79/mach-wlae-ag300n.c 2017-08-06 20:02:15.000000000 +0200
  25709. @@ -0,0 +1,114 @@
  25710. +/*
  25711. + * Buffalo WLAE-AG300N board support
  25712. + */
  25713. +
  25714. +#include <linux/gpio.h>
  25715. +#include <linux/mtd/mtd.h>
  25716. +#include <linux/mtd/partitions.h>
  25717. +
  25718. +#include <asm/mach-ath79/ath79.h>
  25719. +
  25720. +#include "dev-eth.h"
  25721. +#include "dev-ap9x-pci.h"
  25722. +#include "dev-gpio-buttons.h"
  25723. +#include "dev-leds-gpio.h"
  25724. +#include "dev-m25p80.h"
  25725. +#include "dev-usb.h"
  25726. +#include "machtypes.h"
  25727. +
  25728. +#define WLAEAG300N_MAC_OFFSET 0x20c
  25729. +#define WLAEAG300N_KEYS_POLL_INTERVAL 20 /* msecs */
  25730. +#define WLAEAG300N_KEYS_DEBOUNCE_INTERVAL (3 * WLAEAG300N_KEYS_POLL_INTERVAL)
  25731. +
  25732. +
  25733. +static struct gpio_led wlaeag300n_leds_gpio[] __initdata = {
  25734. + /*
  25735. + * Note: Writing 1 into GPIO 13 will power down the device.
  25736. + */
  25737. + {
  25738. + .name = "buffalo:green:wireless",
  25739. + .gpio = 14,
  25740. + .active_low = 1,
  25741. + }, {
  25742. + .name = "buffalo:red:wireless",
  25743. + .gpio = 15,
  25744. + .active_low = 1,
  25745. + }, {
  25746. + .name = "buffalo:green:status",
  25747. + .gpio = 16,
  25748. + .active_low = 1,
  25749. + }, {
  25750. + .name = "buffalo:red:status",
  25751. + .gpio = 17,
  25752. + .active_low = 1,
  25753. + }
  25754. +};
  25755. +
  25756. +
  25757. +static struct gpio_keys_button wlaeag300n_gpio_keys[] __initdata = {
  25758. + {
  25759. + .desc = "function",
  25760. + .type = EV_KEY,
  25761. + .code = KEY_MODE,
  25762. + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL,
  25763. + .gpio = 0,
  25764. + .active_low = 1,
  25765. + }, {
  25766. + .desc = "reset",
  25767. + .type = EV_KEY,
  25768. + .code = KEY_RESTART,
  25769. + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL,
  25770. + .gpio = 1,
  25771. + .active_low = 1,
  25772. + }, {
  25773. + .desc = "power",
  25774. + .type = EV_KEY,
  25775. + .code = KEY_POWER,
  25776. + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL,
  25777. + .gpio = 11,
  25778. + .active_low = 1,
  25779. + }, {
  25780. + .desc = "aoss",
  25781. + .type = EV_KEY,
  25782. + .code = KEY_WPS_BUTTON,
  25783. + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL,
  25784. + .gpio = 12,
  25785. + .active_low = 1,
  25786. + }
  25787. +};
  25788. +
  25789. +static void __init wlaeag300n_setup(void)
  25790. +{
  25791. + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1fff1000);
  25792. + u8 *mac1 = eeprom1 + WLAEAG300N_MAC_OFFSET;
  25793. +
  25794. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  25795. + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 1);
  25796. +
  25797. + ath79_register_mdio(0, ~(BIT(0) | BIT(4)));
  25798. +
  25799. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  25800. + ath79_eth0_data.speed = SPEED_1000;
  25801. + ath79_eth0_data.duplex = DUPLEX_FULL;
  25802. + ath79_eth0_data.phy_mask = BIT(0);
  25803. +
  25804. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  25805. + ath79_eth1_data.phy_mask = BIT(4);
  25806. +
  25807. + ath79_register_eth(0);
  25808. + ath79_register_eth(1);
  25809. +
  25810. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wlaeag300n_leds_gpio),
  25811. + wlaeag300n_leds_gpio);
  25812. +
  25813. + ath79_register_gpio_keys_polled(-1, WLAEAG300N_KEYS_POLL_INTERVAL,
  25814. + ARRAY_SIZE(wlaeag300n_gpio_keys),
  25815. + wlaeag300n_gpio_keys);
  25816. +
  25817. + ath79_register_m25p80(NULL);
  25818. +
  25819. + ap91_pci_init(eeprom1, mac1);
  25820. +}
  25821. +
  25822. +MIPS_MACHINE(ATH79_MACH_WLAE_AG300N, "WLAE-AG300N",
  25823. + "Buffalo WLAE-AG300N", wlaeag300n_setup);
  25824. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wlr8100.c linux-4.1.43/arch/mips/ath79/mach-wlr8100.c
  25825. --- linux-4.1.43.orig/arch/mips/ath79/mach-wlr8100.c 1970-01-01 01:00:00.000000000 +0100
  25826. +++ linux-4.1.43/arch/mips/ath79/mach-wlr8100.c 2017-08-06 20:02:15.000000000 +0200
  25827. @@ -0,0 +1,206 @@
  25828. +/*
  25829. + * Sitecom X8 AC1750 WLR-8100 board support
  25830. + *
  25831. + * Based on the Qualcomm Atheros AP135/AP136 reference board support code
  25832. + * Copyright (c) 2012 Qualcomm Atheros
  25833. + * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
  25834. + *
  25835. + * Permission to use, copy, modify, and/or distribute this software for any
  25836. + * purpose with or without fee is hereby granted, provided that the above
  25837. + * copyright notice and this permission notice appear in all copies.
  25838. + *
  25839. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  25840. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  25841. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  25842. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  25843. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  25844. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  25845. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  25846. + *
  25847. + */
  25848. +
  25849. +#include <linux/platform_device.h>
  25850. +#include <linux/ar8216_platform.h>
  25851. +
  25852. +#include <asm/mach-ath79/ar71xx_regs.h>
  25853. +
  25854. +#include "common.h"
  25855. +#include "pci.h"
  25856. +#include "dev-ap9x-pci.h"
  25857. +#include "dev-gpio-buttons.h"
  25858. +#include "dev-eth.h"
  25859. +#include "dev-leds-gpio.h"
  25860. +#include "dev-m25p80.h"
  25861. +#include "dev-usb.h"
  25862. +#include "dev-wmac.h"
  25863. +#include "machtypes.h"
  25864. +
  25865. +#define WLR8100_GPIO_LED_USB 4
  25866. +#define WLR8100_GPIO_LED_WLAN_5G 12
  25867. +#define WLR8100_GPIO_LED_WLAN_2G 13
  25868. +#define WLR8100_GPIO_LED_STATUS_RED 14
  25869. +#define WLR8100_GPIO_LED_WPS_RED 15
  25870. +#define WLR8100_GPIO_LED_STATUS_AMBER 19
  25871. +#define WLR8100_GPIO_LED_WPS_GREEN 20
  25872. +
  25873. +#define WLR8100_GPIO_BTN_WPS 16
  25874. +#define WLR8100_GPIO_BTN_RFKILL 21
  25875. +
  25876. +#define WLR8100_KEYS_POLL_INTERVAL 20 /* msecs */
  25877. +#define WLR8100_KEYS_DEBOUNCE_INTERVAL (3 * WLR8100_KEYS_POLL_INTERVAL)
  25878. +
  25879. +#define WLR8100_MAC0_OFFSET 0
  25880. +#define WLR8100_MAC1_OFFSET 6
  25881. +#define WLR8100_WMAC_CALDATA_OFFSET 0x1000
  25882. +#define WLR8100_PCIE_CALDATA_OFFSET 0x5000
  25883. +
  25884. +static struct gpio_led wlr8100_leds_gpio[] __initdata = {
  25885. + {
  25886. + .name = "wlr8100:amber:status",
  25887. + .gpio = WLR8100_GPIO_LED_STATUS_AMBER,
  25888. + .active_low = 1,
  25889. + },
  25890. + {
  25891. + .name = "wlr8100:red:status",
  25892. + .gpio = WLR8100_GPIO_LED_STATUS_RED,
  25893. + .active_low = 1,
  25894. + },
  25895. + {
  25896. + .name = "wlr8100:green:wps",
  25897. + .gpio = WLR8100_GPIO_LED_WPS_GREEN,
  25898. + .active_low = 1,
  25899. + },
  25900. + {
  25901. + .name = "wlr8100:red:wps",
  25902. + .gpio = WLR8100_GPIO_LED_WPS_RED,
  25903. + .active_low = 1,
  25904. + },
  25905. + {
  25906. + .name = "wlr8100:red:wlan-2g",
  25907. + .gpio = WLR8100_GPIO_LED_WLAN_2G,
  25908. + .active_low = 1,
  25909. + },
  25910. + {
  25911. + .name = "wlr8100:red:usb",
  25912. + .gpio = WLR8100_GPIO_LED_USB,
  25913. + .active_low = 1,
  25914. + }
  25915. +};
  25916. +
  25917. +static struct gpio_keys_button wlr8100_gpio_keys[] __initdata = {
  25918. + {
  25919. + .desc = "WPS button",
  25920. + .type = EV_KEY,
  25921. + .code = KEY_WPS_BUTTON,
  25922. + .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL,
  25923. + .gpio = WLR8100_GPIO_BTN_WPS,
  25924. + .active_low = 1,
  25925. + },
  25926. + {
  25927. + .desc = "RFKILL button",
  25928. + .type = EV_KEY,
  25929. + .code = KEY_RFKILL,
  25930. + .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL,
  25931. + .gpio = WLR8100_GPIO_BTN_RFKILL,
  25932. + .active_low = 1,
  25933. + },
  25934. +};
  25935. +
  25936. +static struct ar8327_pad_cfg wlr8100_ar8327_pad0_cfg;
  25937. +static struct ar8327_pad_cfg wlr8100_ar8327_pad6_cfg;
  25938. +
  25939. +static struct ar8327_platform_data wlr8100_ar8327_data = {
  25940. + .pad0_cfg = &wlr8100_ar8327_pad0_cfg,
  25941. + .pad6_cfg = &wlr8100_ar8327_pad6_cfg,
  25942. + .port0_cfg = {
  25943. + .force_link = 1,
  25944. + .speed = AR8327_PORT_SPEED_1000,
  25945. + .duplex = 1,
  25946. + .txpause = 1,
  25947. + .rxpause = 1,
  25948. + },
  25949. + .port6_cfg = {
  25950. + .force_link = 1,
  25951. + .speed = AR8327_PORT_SPEED_1000,
  25952. + .duplex = 1,
  25953. + .txpause = 1,
  25954. + .rxpause = 1,
  25955. + },
  25956. +};
  25957. +
  25958. +static struct mdio_board_info wlr8100_mdio0_info[] = {
  25959. + {
  25960. + .bus_id = "ag71xx-mdio.0",
  25961. + .phy_addr = 0,
  25962. + .platform_data = &wlr8100_ar8327_data,
  25963. + },
  25964. +};
  25965. +
  25966. +static void __init wlr8100_common_setup(void)
  25967. +{
  25968. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  25969. +
  25970. + ath79_register_m25p80(NULL);
  25971. +
  25972. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wlr8100_leds_gpio),
  25973. + wlr8100_leds_gpio);
  25974. + ath79_register_gpio_keys_polled(-1, WLR8100_KEYS_POLL_INTERVAL,
  25975. + ARRAY_SIZE(wlr8100_gpio_keys),
  25976. + wlr8100_gpio_keys);
  25977. +
  25978. + ath79_register_usb();
  25979. +
  25980. + ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
  25981. +
  25982. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  25983. +
  25984. + ath79_register_mdio(0, 0x0);
  25985. +
  25986. + ath79_init_mac(ath79_eth0_data.mac_addr, art + WLR8100_MAC0_OFFSET, 0);
  25987. +
  25988. + mdiobus_register_board_info(wlr8100_mdio0_info,
  25989. + ARRAY_SIZE(wlr8100_mdio0_info));
  25990. +
  25991. + /* GMAC0 is connected to the RMGII interface */
  25992. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  25993. + ath79_eth0_data.phy_mask = BIT(0);
  25994. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  25995. +
  25996. + ath79_register_eth(0);
  25997. +
  25998. + /* GMAC1 is connected tot eh SGMII interface */
  25999. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  26000. + ath79_eth1_data.speed = SPEED_1000;
  26001. + ath79_eth1_data.duplex = DUPLEX_FULL;
  26002. +
  26003. + ath79_register_eth(1);
  26004. +}
  26005. +
  26006. +static void __init wlr8100_010_setup(void)
  26007. +{
  26008. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  26009. +
  26010. + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
  26011. + wlr8100_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
  26012. + wlr8100_ar8327_pad0_cfg.txclk_delay_en = true;
  26013. + wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true;
  26014. + wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
  26015. + wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
  26016. + wlr8100_ar8327_pad0_cfg.mac06_exchange_en = true;
  26017. +
  26018. + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
  26019. + wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
  26020. + wlr8100_ar8327_pad6_cfg.rxclk_delay_en = true;
  26021. + wlr8100_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
  26022. +
  26023. + ath79_eth0_pll_data.pll_1000 = 0xa6000000;
  26024. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  26025. +
  26026. + wlr8100_common_setup();
  26027. + ap91_pci_init(art + WLR8100_PCIE_CALDATA_OFFSET, NULL);
  26028. +}
  26029. +
  26030. +MIPS_MACHINE(ATH79_MACH_WLR8100, "WLR8100",
  26031. + "Sitecom WLR-8100",
  26032. + wlr8100_010_setup);
  26033. +
  26034. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wndap360.c linux-4.1.43/arch/mips/ath79/mach-wndap360.c
  26035. --- linux-4.1.43.orig/arch/mips/ath79/mach-wndap360.c 1970-01-01 01:00:00.000000000 +0100
  26036. +++ linux-4.1.43/arch/mips/ath79/mach-wndap360.c 2017-08-06 20:02:15.000000000 +0200
  26037. @@ -0,0 +1,105 @@
  26038. +/*
  26039. + * Netgear WNDAP360 board support (proper leds / button support missing)
  26040. + *
  26041. + * Based on AP96
  26042. + * Copyright (C) 2013 Jacek Kikiewicz
  26043. + * Copyright (C) 2009 Marco Porsch
  26044. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  26045. + * Copyright (C) 2010 Atheros Communications
  26046. + *
  26047. + * This program is free software; you can redistribute it and/or modify it
  26048. + * under the terms of the GNU General Public License version 2 as published
  26049. + * by the Free Software Foundation.
  26050. + */
  26051. +
  26052. +#include <linux/platform_device.h>
  26053. +#include <linux/delay.h>
  26054. +
  26055. +#include <asm/mach-ath79/ath79.h>
  26056. +
  26057. +#include "dev-ap9x-pci.h"
  26058. +#include "dev-eth.h"
  26059. +#include "dev-gpio-buttons.h"
  26060. +#include "dev-leds-gpio.h"
  26061. +#include "dev-m25p80.h"
  26062. +#include "machtypes.h"
  26063. +
  26064. +#define WNDAP360_GPIO_LED_POWER_ORANGE 0
  26065. +#define WNDAP360_GPIO_LED_POWER_GREEN 2
  26066. +
  26067. +/* Reset button - next to the power connector */
  26068. +#define WNDAP360_GPIO_BTN_RESET 8
  26069. +
  26070. +#define WNDAP360_KEYS_POLL_INTERVAL 20 /* msecs */
  26071. +#define WNDAP360_KEYS_DEBOUNCE_INTERVAL (3 * WNDAP360_KEYS_POLL_INTERVAL)
  26072. +
  26073. +#define WNDAP360_WMAC0_MAC_OFFSET 0x120c
  26074. +#define WNDAP360_WMAC1_MAC_OFFSET 0x520c
  26075. +#define WNDAP360_CALDATA0_OFFSET 0x1000
  26076. +#define WNDAP360_CALDATA1_OFFSET 0x5000
  26077. +
  26078. +/*
  26079. + * WNDAP360 this still uses leds definitions from AP96
  26080. + *
  26081. + */
  26082. +static struct gpio_led wndap360_leds_gpio[] __initdata = {
  26083. + {
  26084. + .name = "netgear:green:power",
  26085. + .gpio = WNDAP360_GPIO_LED_POWER_GREEN,
  26086. + .active_low = 1,
  26087. + }, {
  26088. + .name = "netgear:orange:power",
  26089. + .gpio = WNDAP360_GPIO_LED_POWER_ORANGE,
  26090. + .active_low = 1,
  26091. + }
  26092. +};
  26093. +
  26094. +static struct gpio_keys_button wndap360_gpio_keys[] __initdata = {
  26095. + {
  26096. + .desc = "reset",
  26097. + .type = EV_KEY,
  26098. + .code = KEY_RESTART,
  26099. + .debounce_interval = WNDAP360_KEYS_DEBOUNCE_INTERVAL,
  26100. + .gpio = WNDAP360_GPIO_BTN_RESET,
  26101. + .active_low = 1,
  26102. + }
  26103. +};
  26104. +
  26105. +#define WNDAP360_LAN_PHYMASK 0x0f
  26106. +
  26107. +static void __init wndap360_setup(void)
  26108. +{
  26109. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  26110. +
  26111. + ath79_register_mdio(0, ~(WNDAP360_LAN_PHYMASK));
  26112. +
  26113. + /* Reusing wifi MAC with offset of 1 as eth0 MAC */
  26114. + ath79_init_mac(ath79_eth0_data.mac_addr,
  26115. + art + WNDAP360_WMAC0_MAC_OFFSET, 1);
  26116. + ath79_eth0_pll_data.pll_1000 = 0x11110000;
  26117. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  26118. + ath79_eth0_data.phy_mask = WNDAP360_LAN_PHYMASK;
  26119. + ath79_eth0_data.speed = SPEED_1000;
  26120. + ath79_eth0_data.duplex = DUPLEX_FULL;
  26121. +
  26122. + ath79_register_eth(0);
  26123. +
  26124. + ath79_register_m25p80(NULL);
  26125. +
  26126. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndap360_leds_gpio),
  26127. + wndap360_leds_gpio);
  26128. +
  26129. + ath79_register_gpio_keys_polled(-1, WNDAP360_KEYS_POLL_INTERVAL,
  26130. + ARRAY_SIZE(wndap360_gpio_keys),
  26131. + wndap360_gpio_keys);
  26132. +
  26133. + ap9x_pci_setup_wmac_led_pin(0, 5);
  26134. + ap9x_pci_setup_wmac_led_pin(1, 5);
  26135. +
  26136. + ap94_pci_init(art + WNDAP360_CALDATA0_OFFSET,
  26137. + art + WNDAP360_WMAC0_MAC_OFFSET,
  26138. + art + WNDAP360_CALDATA1_OFFSET,
  26139. + art + WNDAP360_WMAC1_MAC_OFFSET);
  26140. +}
  26141. +
  26142. +MIPS_MACHINE(ATH79_MACH_WNDAP360, "WNDAP360", "Netgear WNDAP360", wndap360_setup);
  26143. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wndr3700.c linux-4.1.43/arch/mips/ath79/mach-wndr3700.c
  26144. --- linux-4.1.43.orig/arch/mips/ath79/mach-wndr3700.c 1970-01-01 01:00:00.000000000 +0100
  26145. +++ linux-4.1.43/arch/mips/ath79/mach-wndr3700.c 2017-08-06 20:02:15.000000000 +0200
  26146. @@ -0,0 +1,172 @@
  26147. +/*
  26148. + * Netgear WNDR3700 board support
  26149. + *
  26150. + * Copyright (C) 2009 Marco Porsch
  26151. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  26152. + *
  26153. + * This program is free software; you can redistribute it and/or modify it
  26154. + * under the terms of the GNU General Public License version 2 as published
  26155. + * by the Free Software Foundation.
  26156. + */
  26157. +
  26158. +#include <linux/platform_device.h>
  26159. +#include <linux/mtd/mtd.h>
  26160. +#include <linux/mtd/partitions.h>
  26161. +#include <linux/delay.h>
  26162. +#include <linux/rtl8366.h>
  26163. +
  26164. +#include <asm/mach-ath79/ath79.h>
  26165. +
  26166. +#include "dev-ap9x-pci.h"
  26167. +#include "dev-eth.h"
  26168. +#include "dev-gpio-buttons.h"
  26169. +#include "dev-leds-gpio.h"
  26170. +#include "dev-m25p80.h"
  26171. +#include "dev-usb.h"
  26172. +#include "machtypes.h"
  26173. +
  26174. +#define WNDR3700_GPIO_LED_WPS_ORANGE 0
  26175. +#define WNDR3700_GPIO_LED_POWER_ORANGE 1
  26176. +#define WNDR3700_GPIO_LED_POWER_GREEN 2
  26177. +#define WNDR3700_GPIO_LED_WPS_GREEN 4
  26178. +#define WNDR3700_GPIO_LED_WAN_GREEN 6
  26179. +
  26180. +#define WNDR3700_GPIO_BTN_WPS 3
  26181. +#define WNDR3700_GPIO_BTN_RESET 8
  26182. +#define WNDR3700_GPIO_BTN_WIFI 11
  26183. +
  26184. +#define WNDR3700_GPIO_RTL8366_SDA 5
  26185. +#define WNDR3700_GPIO_RTL8366_SCK 7
  26186. +
  26187. +#define WNDR3700_KEYS_POLL_INTERVAL 20 /* msecs */
  26188. +#define WNDR3700_KEYS_DEBOUNCE_INTERVAL (3 * WNDR3700_KEYS_POLL_INTERVAL)
  26189. +
  26190. +#define WNDR3700_ETH0_MAC_OFFSET 0
  26191. +#define WNDR3700_ETH1_MAC_OFFSET 0x6
  26192. +
  26193. +#define WNDR3700_WMAC0_MAC_OFFSET 0
  26194. +#define WNDR3700_WMAC1_MAC_OFFSET 0xc
  26195. +#define WNDR3700_CALDATA0_OFFSET 0x1000
  26196. +#define WNDR3700_CALDATA1_OFFSET 0x5000
  26197. +
  26198. +static struct gpio_led wndr3700_leds_gpio[] __initdata = {
  26199. + {
  26200. + .name = "netgear:green:power",
  26201. + .gpio = WNDR3700_GPIO_LED_POWER_GREEN,
  26202. + .active_low = 1,
  26203. + }, {
  26204. + .name = "netgear:orange:power",
  26205. + .gpio = WNDR3700_GPIO_LED_POWER_ORANGE,
  26206. + .active_low = 1,
  26207. + }, {
  26208. + .name = "netgear:green:wps",
  26209. + .gpio = WNDR3700_GPIO_LED_WPS_GREEN,
  26210. + .active_low = 1,
  26211. + }, {
  26212. + .name = "netgear:orange:wps",
  26213. + .gpio = WNDR3700_GPIO_LED_WPS_ORANGE,
  26214. + .active_low = 1,
  26215. + }, {
  26216. + .name = "netgear:green:wan",
  26217. + .gpio = WNDR3700_GPIO_LED_WAN_GREEN,
  26218. + .active_low = 1,
  26219. + }
  26220. +};
  26221. +
  26222. +static struct gpio_keys_button wndr3700_gpio_keys[] __initdata = {
  26223. + {
  26224. + .desc = "reset",
  26225. + .type = EV_KEY,
  26226. + .code = KEY_RESTART,
  26227. + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL,
  26228. + .gpio = WNDR3700_GPIO_BTN_RESET,
  26229. + .active_low = 1,
  26230. + }, {
  26231. + .desc = "wps",
  26232. + .type = EV_KEY,
  26233. + .code = KEY_WPS_BUTTON,
  26234. + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL,
  26235. + .gpio = WNDR3700_GPIO_BTN_WPS,
  26236. + .active_low = 1,
  26237. + }, {
  26238. + .desc = "wifi",
  26239. + .type = EV_KEY,
  26240. + .code = BTN_2,
  26241. + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL,
  26242. + .gpio = WNDR3700_GPIO_BTN_WIFI,
  26243. + .active_low = 1,
  26244. + }
  26245. +};
  26246. +
  26247. +static struct rtl8366_platform_data wndr3700_rtl8366s_data = {
  26248. + .gpio_sda = WNDR3700_GPIO_RTL8366_SDA,
  26249. + .gpio_sck = WNDR3700_GPIO_RTL8366_SCK,
  26250. +};
  26251. +
  26252. +static struct platform_device wndr3700_rtl8366s_device = {
  26253. + .name = RTL8366S_DRIVER_NAME,
  26254. + .id = -1,
  26255. + .dev = {
  26256. + .platform_data = &wndr3700_rtl8366s_data,
  26257. + }
  26258. +};
  26259. +
  26260. +static void __init wndr3700_setup(void)
  26261. +{
  26262. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  26263. +
  26264. + /*
  26265. + * The eth0 and wmac0 interfaces share the same MAC address which
  26266. + * can lead to problems if operated unbridged. Set the locally
  26267. + * administered bit on the eth0 MAC to make it unique.
  26268. + */
  26269. + ath79_init_local_mac(ath79_eth0_data.mac_addr,
  26270. + art + WNDR3700_ETH0_MAC_OFFSET);
  26271. + ath79_eth0_pll_data.pll_1000 = 0x11110000;
  26272. + ath79_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev;
  26273. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  26274. + ath79_eth0_data.speed = SPEED_1000;
  26275. + ath79_eth0_data.duplex = DUPLEX_FULL;
  26276. +
  26277. + ath79_init_mac(ath79_eth1_data.mac_addr,
  26278. + art + WNDR3700_ETH1_MAC_OFFSET, 0);
  26279. + ath79_eth1_pll_data.pll_1000 = 0x11110000;
  26280. + ath79_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev;
  26281. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  26282. + ath79_eth1_data.phy_mask = 0x10;
  26283. +
  26284. + ath79_register_eth(0);
  26285. + ath79_register_eth(1);
  26286. +
  26287. + ath79_register_usb();
  26288. +
  26289. + ath79_register_m25p80(NULL);
  26290. +
  26291. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio),
  26292. + wndr3700_leds_gpio);
  26293. +
  26294. + ath79_register_gpio_keys_polled(-1, WNDR3700_KEYS_POLL_INTERVAL,
  26295. + ARRAY_SIZE(wndr3700_gpio_keys),
  26296. + wndr3700_gpio_keys);
  26297. +
  26298. + platform_device_register(&wndr3700_rtl8366s_device);
  26299. + platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0);
  26300. +
  26301. + ap9x_pci_setup_wmac_led_pin(0, 5);
  26302. + ap9x_pci_setup_wmac_led_pin(1, 5);
  26303. +
  26304. + /* 2.4 GHz uses the first fixed antenna group (1, 0, 1, 0) */
  26305. + ap9x_pci_setup_wmac_gpio(0, (0xf << 6), (0xa << 6));
  26306. +
  26307. + /* 5 GHz uses the second fixed antenna group (0, 1, 1, 0) */
  26308. + ap9x_pci_setup_wmac_gpio(1, (0xf << 6), (0x6 << 6));
  26309. +
  26310. + ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET,
  26311. + art + WNDR3700_WMAC0_MAC_OFFSET,
  26312. + art + WNDR3700_CALDATA1_OFFSET,
  26313. + art + WNDR3700_WMAC1_MAC_OFFSET);
  26314. +}
  26315. +
  26316. +MIPS_MACHINE(ATH79_MACH_WNDR3700, "WNDR3700",
  26317. + "NETGEAR WNDR3700/WNDR3800/WNDRMAC",
  26318. + wndr3700_setup);
  26319. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wndr4300.c linux-4.1.43/arch/mips/ath79/mach-wndr4300.c
  26320. --- linux-4.1.43.orig/arch/mips/ath79/mach-wndr4300.c 1970-01-01 01:00:00.000000000 +0100
  26321. +++ linux-4.1.43/arch/mips/ath79/mach-wndr4300.c 2017-08-06 20:02:15.000000000 +0200
  26322. @@ -0,0 +1,210 @@
  26323. +/*
  26324. + * NETGEAR WNDR3700v4/WNDR4300 board support
  26325. + *
  26326. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  26327. + * Copyright (C) 2014 Ralph Perlich <rpsoft@arcor.de>
  26328. + *
  26329. + * This program is free software; you can redistribute it and/or modify it
  26330. + * under the terms of the GNU General Public License version 2 as published
  26331. + * by the Free Software Foundation.
  26332. + */
  26333. +
  26334. +#include <linux/pci.h>
  26335. +#include <linux/phy.h>
  26336. +#include <linux/gpio.h>
  26337. +#include <linux/platform_device.h>
  26338. +#include <linux/ath9k_platform.h>
  26339. +#include <linux/ar8216_platform.h>
  26340. +#include <linux/mtd/mtd.h>
  26341. +#include <linux/mtd/nand.h>
  26342. +#include <linux/platform/ar934x_nfc.h>
  26343. +
  26344. +#include <asm/mach-ath79/ar71xx_regs.h>
  26345. +
  26346. +#include "common.h"
  26347. +#include "dev-ap9x-pci.h"
  26348. +#include "dev-eth.h"
  26349. +#include "dev-gpio-buttons.h"
  26350. +#include "dev-leds-gpio.h"
  26351. +#include "dev-nfc.h"
  26352. +#include "dev-usb.h"
  26353. +#include "dev-wmac.h"
  26354. +#include "machtypes.h"
  26355. +
  26356. +/* AR9344 GPIOs */
  26357. +#define WNDR4300_GPIO_LED_POWER_GREEN 0
  26358. +#define WNDR4300_GPIO_LED_POWER_AMBER 2
  26359. +#define WNDR4300_GPIO_LED_USB 13
  26360. +#define WNDR4300_GPIO_LED_WAN_GREEN 1
  26361. +#define WNDR4300_GPIO_LED_WAN_AMBER 3
  26362. +#define WNDR4300_GPIO_LED_WLAN2G 11
  26363. +#define WNDR4300_GPIO_LED_WLAN5G 14
  26364. +#define WNDR4300_GPIO_LED_WPS_GREEN 16
  26365. +#define WNDR4300_GPIO_LED_WPS_AMBER 17
  26366. +
  26367. +#define WNDR4300_GPIO_BTN_RESET 21
  26368. +#define WNDR4300_GPIO_BTN_WIRELESS 15
  26369. +#define WNDR4300_GPIO_BTN_WPS 12
  26370. +
  26371. +/* AR9580 GPIOs */
  26372. +#define WNDR4300_GPIO_USB_5V 0
  26373. +
  26374. +#define WNDR4300_KEYS_POLL_INTERVAL 20 /* msecs */
  26375. +#define WNDR4300_KEYS_DEBOUNCE_INTERVAL (3 * WNDR4300_KEYS_POLL_INTERVAL)
  26376. +
  26377. +static struct gpio_led wndr4300_leds_gpio[] __initdata = {
  26378. + {
  26379. + .name = "netgear:green:power",
  26380. + .gpio = WNDR4300_GPIO_LED_POWER_GREEN,
  26381. + .active_low = 1,
  26382. + },
  26383. + {
  26384. + .name = "netgear:amber:power",
  26385. + .gpio = WNDR4300_GPIO_LED_POWER_AMBER,
  26386. + .active_low = 1,
  26387. + },
  26388. + {
  26389. + .name = "netgear:green:wan",
  26390. + .gpio = WNDR4300_GPIO_LED_WAN_GREEN,
  26391. + .active_low = 1,
  26392. + },
  26393. + {
  26394. + .name = "netgear:amber:wan",
  26395. + .gpio = WNDR4300_GPIO_LED_WAN_AMBER,
  26396. + .active_low = 1,
  26397. + },
  26398. + {
  26399. + .name = "netgear:green:usb",
  26400. + .gpio = WNDR4300_GPIO_LED_USB,
  26401. + .active_low = 1,
  26402. + },
  26403. + {
  26404. + .name = "netgear:green:wps",
  26405. + .gpio = WNDR4300_GPIO_LED_WPS_GREEN,
  26406. + .active_low = 1,
  26407. + },
  26408. + {
  26409. + .name = "netgear:amber:wps",
  26410. + .gpio = WNDR4300_GPIO_LED_WPS_AMBER,
  26411. + .active_low = 1,
  26412. + },
  26413. + {
  26414. + .name = "netgear:green:wlan2g",
  26415. + .gpio = WNDR4300_GPIO_LED_WLAN2G,
  26416. + .active_low = 1,
  26417. + },
  26418. + {
  26419. + .name = "netgear:blue:wlan5g",
  26420. + .gpio = WNDR4300_GPIO_LED_WLAN5G,
  26421. + .active_low = 1,
  26422. + },
  26423. +};
  26424. +
  26425. +static struct gpio_keys_button wndr4300_gpio_keys[] __initdata = {
  26426. + {
  26427. + .desc = "Reset button",
  26428. + .type = EV_KEY,
  26429. + .code = KEY_RESTART,
  26430. + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL,
  26431. + .gpio = WNDR4300_GPIO_BTN_RESET,
  26432. + .active_low = 1,
  26433. + },
  26434. + {
  26435. + .desc = "WPS button",
  26436. + .type = EV_KEY,
  26437. + .code = KEY_WPS_BUTTON,
  26438. + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL,
  26439. + .gpio = WNDR4300_GPIO_BTN_WPS,
  26440. + .active_low = 1,
  26441. + },
  26442. + {
  26443. + .desc = "Wireless button",
  26444. + .type = EV_KEY,
  26445. + .code = KEY_RFKILL,
  26446. + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL,
  26447. + .gpio = WNDR4300_GPIO_BTN_WIRELESS,
  26448. + .active_low = 1,
  26449. + },
  26450. +};
  26451. +
  26452. +static struct ar8327_pad_cfg wndr4300_ar8327_pad0_cfg = {
  26453. + .mode = AR8327_PAD_MAC_RGMII,
  26454. + .txclk_delay_en = true,
  26455. + .rxclk_delay_en = true,
  26456. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  26457. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  26458. +};
  26459. +
  26460. +static struct ar8327_led_cfg wndr4300_ar8327_led_cfg = {
  26461. + .led_ctrl0 = 0xc737c737,
  26462. + .led_ctrl1 = 0x00000000,
  26463. + .led_ctrl2 = 0x00000000,
  26464. + .led_ctrl3 = 0x0030c300,
  26465. + .open_drain = false,
  26466. +};
  26467. +
  26468. +static struct ar8327_platform_data wndr4300_ar8327_data = {
  26469. + .pad0_cfg = &wndr4300_ar8327_pad0_cfg,
  26470. + .port0_cfg = {
  26471. + .force_link = 1,
  26472. + .speed = AR8327_PORT_SPEED_1000,
  26473. + .duplex = 1,
  26474. + .txpause = 1,
  26475. + .rxpause = 1,
  26476. + },
  26477. + .led_cfg = &wndr4300_ar8327_led_cfg,
  26478. +};
  26479. +
  26480. +static struct mdio_board_info wndr4300_mdio0_info[] = {
  26481. + {
  26482. + .bus_id = "ag71xx-mdio.0",
  26483. + .phy_addr = 0,
  26484. + .platform_data = &wndr4300_ar8327_data,
  26485. + },
  26486. +};
  26487. +
  26488. +static void __init wndr4300_setup(void)
  26489. +{
  26490. + int i;
  26491. +
  26492. + for (i = 0; i < ARRAY_SIZE(wndr4300_leds_gpio); i++)
  26493. + ath79_gpio_output_select(wndr4300_leds_gpio[i].gpio,
  26494. + AR934X_GPIO_OUT_GPIO);
  26495. +
  26496. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio),
  26497. + wndr4300_leds_gpio);
  26498. + ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL,
  26499. + ARRAY_SIZE(wndr4300_gpio_keys),
  26500. + wndr4300_gpio_keys);
  26501. +
  26502. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
  26503. +
  26504. + mdiobus_register_board_info(wndr4300_mdio0_info,
  26505. + ARRAY_SIZE(wndr4300_mdio0_info));
  26506. +
  26507. + ath79_register_mdio(0, 0x0);
  26508. +
  26509. + /* GMAC0 is connected to an AR8327N switch */
  26510. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  26511. + ath79_eth0_data.phy_mask = BIT(0);
  26512. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  26513. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  26514. + ath79_register_eth(0);
  26515. +
  26516. + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
  26517. + ath79_register_nfc();
  26518. + ath79_register_usb();
  26519. +
  26520. + ath79_register_wmac_simple();
  26521. +
  26522. + /* enable power for the USB port */
  26523. + ap9x_pci_setup_wmac_gpio(0, BIT(WNDR4300_GPIO_USB_5V),
  26524. + BIT(WNDR4300_GPIO_USB_5V));
  26525. +
  26526. + ap91_pci_init_simple();
  26527. +}
  26528. +
  26529. +MIPS_MACHINE(ATH79_MACH_WNDR3700_V4, "WNDR3700_V4", "NETGEAR WNDR3700v4",
  26530. + wndr4300_setup);
  26531. +MIPS_MACHINE(ATH79_MACH_WNDR4300, "WNDR4300", "NETGEAR WNDR4300",
  26532. + wndr4300_setup);
  26533. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wnr2000-v3.c linux-4.1.43/arch/mips/ath79/mach-wnr2000-v3.c
  26534. --- linux-4.1.43.orig/arch/mips/ath79/mach-wnr2000-v3.c 1970-01-01 01:00:00.000000000 +0100
  26535. +++ linux-4.1.43/arch/mips/ath79/mach-wnr2000-v3.c 2017-08-06 20:02:15.000000000 +0200
  26536. @@ -0,0 +1,140 @@
  26537. +/*
  26538. + * NETGEAR WNR2000v3/WNR612v2/WNR1000v2 board support
  26539. + *
  26540. + * Copytight (C) 2013 Mathieu Olivari <mathieu.olivari@gmail.com>
  26541. + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  26542. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  26543. + * Copyright (C) 2008-2009 Andy Boyett <agb@openwrt.org>
  26544. + *
  26545. + * This program is free software; you can redistribute it and/or modify it
  26546. + * under the terms of the GNU General Public License version 2 as published
  26547. + * by the Free Software Foundation.
  26548. + */
  26549. +
  26550. +#include <linux/mtd/mtd.h>
  26551. +#include <linux/mtd/partitions.h>
  26552. +
  26553. +#include <asm/mach-ath79/ath79.h>
  26554. +
  26555. +#include "dev-ap9x-pci.h"
  26556. +#include "dev-eth.h"
  26557. +#include "dev-gpio-buttons.h"
  26558. +#include "dev-leds-gpio.h"
  26559. +#include "dev-m25p80.h"
  26560. +#include "machtypes.h"
  26561. +
  26562. +#define WNR2000V3_GPIO_LED_WAN_GREEN 0
  26563. +#define WNR2000V3_GPIO_LED_LAN1_AMBER 1
  26564. +#define WNR2000V3_GPIO_LED_LAN4_AMBER 12
  26565. +#define WNR2000V3_GPIO_LED_PWR_GREEN 14
  26566. +#define WNR2000V3_GPIO_BTN_WPS 11
  26567. +
  26568. +#define WNR612V2_GPIO_LED_PWR_GREEN 11
  26569. +
  26570. +#define WNR1000V2_GPIO_LED_PWR_AMBER 1
  26571. +#define WNR1000V2_GPIO_LED_PWR_GREEN 11
  26572. +
  26573. +#define WNR2000V3_KEYS_POLL_INTERVAL 20 /* msecs */
  26574. +#define WNR2000V3_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000V3_KEYS_POLL_INTERVAL)
  26575. +
  26576. +#define WNR2000V3_MAC0_OFFSET 0
  26577. +#define WNR2000V3_MAC1_OFFSET 6
  26578. +#define WNR2000V3_PCIE_CALDATA_OFFSET 0x1000
  26579. +
  26580. +static struct gpio_led wnr2000v3_leds_gpio[] __initdata = {
  26581. + {
  26582. + .name = "wnr2000v3:green:power",
  26583. + .gpio = WNR2000V3_GPIO_LED_PWR_GREEN,
  26584. + .active_low = 1,
  26585. + }, {
  26586. + .name = "wnr2000v3:green:wan",
  26587. + .gpio = WNR2000V3_GPIO_LED_WAN_GREEN,
  26588. + .active_low = 1,
  26589. + }
  26590. +};
  26591. +
  26592. +static struct gpio_led wnr612v2_leds_gpio[] __initdata = {
  26593. + {
  26594. + .name = "netgear:green:power",
  26595. + .gpio = WNR612V2_GPIO_LED_PWR_GREEN,
  26596. + .active_low = 1,
  26597. + }
  26598. +};
  26599. +
  26600. +static struct gpio_led wnr1000v2_leds_gpio[] __initdata = {
  26601. + {
  26602. + .name = "netgear:green:power",
  26603. + .gpio = WNR1000V2_GPIO_LED_PWR_GREEN,
  26604. + .active_low = 1,
  26605. + }, {
  26606. + .name = "netgear:amber:power",
  26607. + .gpio = WNR1000V2_GPIO_LED_PWR_AMBER,
  26608. + .active_low = 1,
  26609. + }
  26610. +};
  26611. +
  26612. +static struct gpio_keys_button wnr2000v3_gpio_keys[] __initdata = {
  26613. + {
  26614. + .desc = "wps",
  26615. + .type = EV_KEY,
  26616. + .code = KEY_WPS_BUTTON,
  26617. + .debounce_interval = WNR2000V3_KEYS_DEBOUNCE_INTERVAL,
  26618. + .gpio = WNR2000V3_GPIO_BTN_WPS,
  26619. + }
  26620. +};
  26621. +
  26622. +static void __init wnr_common_setup(void)
  26623. +{
  26624. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  26625. +
  26626. + ath79_register_mdio(0, 0x0);
  26627. +
  26628. + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V3_MAC0_OFFSET, 0);
  26629. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  26630. + ath79_eth0_data.speed = SPEED_100;
  26631. + ath79_eth0_data.duplex = DUPLEX_FULL;
  26632. +
  26633. + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V3_MAC1_OFFSET, 0);
  26634. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  26635. + ath79_eth1_data.phy_mask = 0x10;
  26636. +
  26637. + ath79_register_eth(0);
  26638. + ath79_register_eth(1);
  26639. +
  26640. + ath79_register_m25p80(NULL);
  26641. + ap91_pci_init(art + WNR2000V3_PCIE_CALDATA_OFFSET, NULL);
  26642. +}
  26643. +
  26644. +static void __init wnr2000v3_setup(void)
  26645. +{
  26646. + wnr_common_setup();
  26647. +
  26648. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000v3_leds_gpio),
  26649. + wnr2000v3_leds_gpio);
  26650. +
  26651. + ath79_register_gpio_keys_polled(-1, WNR2000V3_KEYS_POLL_INTERVAL,
  26652. + ARRAY_SIZE(wnr2000v3_gpio_keys),
  26653. + wnr2000v3_gpio_keys);
  26654. +}
  26655. +
  26656. +MIPS_MACHINE(ATH79_MACH_WNR2000_V3, "WNR2000V3", "NETGEAR WNR2000 V3", wnr2000v3_setup);
  26657. +
  26658. +static void __init wnr612v2_setup(void)
  26659. +{
  26660. + wnr_common_setup();
  26661. +
  26662. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr612v2_leds_gpio),
  26663. + wnr612v2_leds_gpio);
  26664. +}
  26665. +
  26666. +MIPS_MACHINE(ATH79_MACH_WNR612_V2, "WNR612V2", "NETGEAR WNR612 V2", wnr612v2_setup);
  26667. +
  26668. +static void __init wnr1000v2_setup(void)
  26669. +{
  26670. + wnr_common_setup();
  26671. +
  26672. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr1000v2_leds_gpio),
  26673. + wnr1000v2_leds_gpio);
  26674. +}
  26675. +
  26676. +MIPS_MACHINE(ATH79_MACH_WNR1000_V2, "WNR1000V2", "NETGEAR WNR1000 V2", wnr1000v2_setup);
  26677. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wnr2000-v4.c linux-4.1.43/arch/mips/ath79/mach-wnr2000-v4.c
  26678. --- linux-4.1.43.orig/arch/mips/ath79/mach-wnr2000-v4.c 1970-01-01 01:00:00.000000000 +0100
  26679. +++ linux-4.1.43/arch/mips/ath79/mach-wnr2000-v4.c 2017-08-06 20:02:15.000000000 +0200
  26680. @@ -0,0 +1,214 @@
  26681. +/*
  26682. + * NETGEAR WNR2000v4 board support
  26683. + *
  26684. + * Copyright (C) 2015 Michael Bazzinotti <mbazzinotti@gmail.com>
  26685. + * Copyright (C) 2014 Michaël Burtin <mburtin@gmail.com>
  26686. + * Copyright (C) 2013 Mathieu Olivari <mathieu.olivari@gmail.com>
  26687. + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  26688. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  26689. + * Copyright (C) 2008-2009 Andy Boyett <agb@openwrt.org>
  26690. + *
  26691. + * This program is free software; you can redistribute it and/or modify it
  26692. + * under the terms of the GNU General Public License version 2 as published
  26693. + * by the Free Software Foundation.
  26694. + */
  26695. +
  26696. +#include <linux/mtd/mtd.h>
  26697. +#include <linux/mtd/partitions.h>
  26698. +#include <linux/platform_device.h>
  26699. +
  26700. +#include <asm/mach-ath79/ath79.h>
  26701. +#include <asm/mach-ath79/ar71xx_regs.h>
  26702. +
  26703. +#include "common.h"
  26704. +#include "dev-eth.h"
  26705. +#include "dev-gpio-buttons.h"
  26706. +#include "dev-leds-gpio.h"
  26707. +#include "dev-m25p80.h"
  26708. +#include "dev-usb.h"
  26709. +#include "dev-wmac.h"
  26710. +#include "machtypes.h"
  26711. +
  26712. +/* AR9341 GPIOs */
  26713. +#define WNR2000V4_GPIO_LED_PWR_GREEN 0
  26714. +#define WNR2000V4_GPIO_LED_PWR_AMBER 1
  26715. +#define WNR2000V4_GPIO_LED_WPS 2
  26716. +#define WNR2000V4_GPIO_LED_WLAN 12
  26717. +#define WNR2000V4_GPIO_LED_LAN1_GREEN 13
  26718. +#define WNR2000V4_GPIO_LED_LAN2_GREEN 14
  26719. +#define WNR2000V4_GPIO_LED_LAN3_GREEN 15
  26720. +#define WNR2000V4_GPIO_LED_LAN4_GREEN 16
  26721. +#define WNR2000V4_GPIO_LED_LAN1_AMBER 18
  26722. +#define WNR2000V4_GPIO_LED_LAN2_AMBER 19
  26723. +#define WNR2000V4_GPIO_LED_LAN3_AMBER 20
  26724. +#define WNR2000V4_GPIO_LED_LAN4_AMBER 21
  26725. +#define WNR2000V4_GPIO_LED_WAN_GREEN 17
  26726. +#define WNR2000V4_GPIO_LED_WAN_AMBER 22
  26727. +/* Buttons */
  26728. +#define WNR2000V4_GPIO_BTN_WPS 3
  26729. +#define WNR2000V4_GPIO_BTN_RESET 4
  26730. +#define WNR2000V4_GPIO_BTN_WLAN 11
  26731. +#define WNR2000V4_KEYS_POLL_INTERVAL 20 /* msecs */
  26732. +#define WNR2000V4_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000V4_KEYS_POLL_INTERVAL)
  26733. +
  26734. +
  26735. +/* ART offsets */
  26736. +#define WNR2000V4_MAC0_OFFSET 0 /* WAN/WLAN0 MAC */
  26737. +#define WNR2000V4_MAC1_OFFSET 6 /* Eth-switch0 MAC */
  26738. +
  26739. +static struct gpio_led wnr2000v4_leds_gpio[] __initdata = {
  26740. + {
  26741. + .name = "netgear:green:power",
  26742. + .gpio = WNR2000V4_GPIO_LED_PWR_GREEN,
  26743. + .active_low = 1,
  26744. + .default_trigger = "default-on",
  26745. + },
  26746. + {
  26747. + .name = "netgear:amber:status",
  26748. + .gpio = WNR2000V4_GPIO_LED_PWR_AMBER,
  26749. + .active_low = 1,
  26750. + },
  26751. + {
  26752. + .name = "netgear:green:wan",
  26753. + .gpio = WNR2000V4_GPIO_LED_WAN_GREEN,
  26754. + .active_low = 1,
  26755. + },
  26756. + {
  26757. + .name = "netgear:amber:wan",
  26758. + .gpio = WNR2000V4_GPIO_LED_WAN_AMBER,
  26759. + .active_low = 1,
  26760. + },
  26761. + {
  26762. + .name = "netgear:blue:wlan",
  26763. + .gpio = WNR2000V4_GPIO_LED_WLAN,
  26764. + .active_low = 1,
  26765. + },
  26766. + /* LAN LEDS */
  26767. + {
  26768. + .name = "netgear:green:lan1",
  26769. + .gpio = WNR2000V4_GPIO_LED_LAN1_GREEN,
  26770. + .active_low = 1,
  26771. + },
  26772. + {
  26773. + .name = "netgear:green:lan2",
  26774. + .gpio = WNR2000V4_GPIO_LED_LAN2_GREEN,
  26775. + .active_low = 1,
  26776. + },
  26777. + {
  26778. + .name = "netgear:green:lan3",
  26779. + .gpio = WNR2000V4_GPIO_LED_LAN3_GREEN,
  26780. + .active_low = 1,
  26781. + },
  26782. + {
  26783. + .name = "netgear:green:lan4",
  26784. + .gpio = WNR2000V4_GPIO_LED_LAN4_GREEN,
  26785. + .active_low = 1,
  26786. + },
  26787. + {
  26788. + .name = "netgear:amber:lan1",
  26789. + .gpio = WNR2000V4_GPIO_LED_LAN1_AMBER,
  26790. + .active_low = 1,
  26791. + },
  26792. + {
  26793. + .name = "netgear:amber:lan2",
  26794. + .gpio = WNR2000V4_GPIO_LED_LAN2_AMBER,
  26795. + .active_low = 1,
  26796. + },
  26797. + {
  26798. + .name = "netgear:amber:lan3",
  26799. + .gpio = WNR2000V4_GPIO_LED_LAN3_AMBER,
  26800. + .active_low = 1,
  26801. + },
  26802. + {
  26803. + .name = "netgear:amber:lan4",
  26804. + .gpio = WNR2000V4_GPIO_LED_LAN4_AMBER,
  26805. + .active_low = 1,
  26806. + },
  26807. + {
  26808. + .name = "netgear:green:wps",
  26809. + .gpio = WNR2000V4_GPIO_LED_WPS,
  26810. + .active_low = 1,
  26811. + },
  26812. +};
  26813. +
  26814. +static struct gpio_keys_button wnr2000v4_gpio_keys[] __initdata = {
  26815. + {
  26816. + .desc = "WPS button",
  26817. + .type = EV_KEY,
  26818. + .code = KEY_WPS_BUTTON,
  26819. + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL,
  26820. + .gpio = WNR2000V4_GPIO_BTN_WPS,
  26821. + .active_low = 1,
  26822. + },
  26823. + {
  26824. + .desc = "Reset button",
  26825. + .type = EV_KEY,
  26826. + .code = KEY_RESTART,
  26827. + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL,
  26828. + .gpio = WNR2000V4_GPIO_BTN_RESET,
  26829. + .active_low = 1,
  26830. + },
  26831. + {
  26832. + .desc = "WLAN button",
  26833. + .type = EV_KEY,
  26834. + .code = KEY_RFKILL,
  26835. + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL,
  26836. + .gpio = WNR2000V4_GPIO_BTN_WLAN,
  26837. + .active_low = 1,
  26838. + },
  26839. +};
  26840. +
  26841. +static void __init wnr_common_setup(void)
  26842. +{
  26843. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  26844. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  26845. +
  26846. + ath79_register_mdio(1, 0x0);
  26847. +
  26848. + ath79_register_usb();
  26849. +
  26850. + ath79_register_m25p80(NULL);
  26851. +
  26852. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
  26853. +
  26854. + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0);
  26855. + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0);
  26856. +
  26857. + /* GMAC0 is connected to the PHY0 of the internal switch, GE0 */
  26858. + ath79_switch_data.phy4_mii_en = 1;
  26859. + ath79_switch_data.phy_poll_mask = BIT(4);
  26860. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  26861. + ath79_eth0_data.phy_mask = BIT(4);
  26862. + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
  26863. + ath79_register_eth(0);
  26864. +
  26865. + /* GMAC1 is connected to the internal switch, GE1 */
  26866. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  26867. + ath79_register_eth(1);
  26868. +
  26869. + ath79_register_wmac(ee, art);
  26870. +}
  26871. +
  26872. +static void __init wnr2000v4_setup(void)
  26873. +{
  26874. + int i;
  26875. +
  26876. + wnr_common_setup();
  26877. +
  26878. + /* Ensure no LED has an internal MUX signal, otherwise
  26879. + control of LED could be lost... This is especially important
  26880. + for most green LEDS (Eth,WAN).. who arrive in this function with
  26881. + MUX signals set. */
  26882. + for (i = 0; i < ARRAY_SIZE(wnr2000v4_leds_gpio); i++)
  26883. + ath79_gpio_output_select(wnr2000v4_leds_gpio[i].gpio,
  26884. + AR934X_GPIO_OUT_GPIO);
  26885. +
  26886. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000v4_leds_gpio),
  26887. + wnr2000v4_leds_gpio);
  26888. +
  26889. + ath79_register_gpio_keys_polled(-1, WNR2000V4_KEYS_POLL_INTERVAL,
  26890. + ARRAY_SIZE(wnr2000v4_gpio_keys),
  26891. + wnr2000v4_gpio_keys);
  26892. +}
  26893. +
  26894. +MIPS_MACHINE(ATH79_MACH_WNR2000_V4, "WNR2000V4", "NETGEAR WNR2000 V4", wnr2000v4_setup);
  26895. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wnr2000.c linux-4.1.43/arch/mips/ath79/mach-wnr2000.c
  26896. --- linux-4.1.43.orig/arch/mips/ath79/mach-wnr2000.c 1970-01-01 01:00:00.000000000 +0100
  26897. +++ linux-4.1.43/arch/mips/ath79/mach-wnr2000.c 2017-08-06 20:02:15.000000000 +0200
  26898. @@ -0,0 +1,145 @@
  26899. +/*
  26900. + * NETGEAR WNR2000 board support
  26901. + *
  26902. + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  26903. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  26904. + * Copyright (C) 2008-2009 Andy Boyett <agb@openwrt.org>
  26905. + *
  26906. + * This program is free software; you can redistribute it and/or modify it
  26907. + * under the terms of the GNU General Public License version 2 as published
  26908. + * by the Free Software Foundation.
  26909. + */
  26910. +
  26911. +#include <linux/mtd/mtd.h>
  26912. +#include <linux/mtd/partitions.h>
  26913. +
  26914. +#include <asm/mach-ath79/ath79.h>
  26915. +
  26916. +#include "dev-eth.h"
  26917. +#include "dev-gpio-buttons.h"
  26918. +#include "dev-leds-gpio.h"
  26919. +#include "dev-m25p80.h"
  26920. +#include "dev-wmac.h"
  26921. +#include "machtypes.h"
  26922. +
  26923. +#define WNR2000_GPIO_LED_PWR_GREEN 14
  26924. +#define WNR2000_GPIO_LED_PWR_AMBER 7
  26925. +#define WNR2000_GPIO_LED_WPS 4
  26926. +#define WNR2000_GPIO_LED_WLAN 6
  26927. +#define WNR2000_GPIO_BTN_RESET 21
  26928. +#define WNR2000_GPIO_BTN_WPS 8
  26929. +
  26930. +#define WNR2000_KEYS_POLL_INTERVAL 20 /* msecs */
  26931. +#define WNR2000_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000_KEYS_POLL_INTERVAL)
  26932. +
  26933. +static struct mtd_partition wnr2000_partitions[] = {
  26934. + {
  26935. + .name = "u-boot",
  26936. + .offset = 0,
  26937. + .size = 0x040000,
  26938. + .mask_flags = MTD_WRITEABLE,
  26939. + }, {
  26940. + .name = "u-boot-env",
  26941. + .offset = 0x040000,
  26942. + .size = 0x010000,
  26943. + }, {
  26944. + .name = "rootfs",
  26945. + .offset = 0x050000,
  26946. + .size = 0x240000,
  26947. + }, {
  26948. + .name = "user-config",
  26949. + .offset = 0x290000,
  26950. + .size = 0x010000,
  26951. + }, {
  26952. + .name = "uImage",
  26953. + .offset = 0x2a0000,
  26954. + .size = 0x120000,
  26955. + }, {
  26956. + .name = "language_table",
  26957. + .offset = 0x3c0000,
  26958. + .size = 0x020000,
  26959. + }, {
  26960. + .name = "rootfs_checksum",
  26961. + .offset = 0x3e0000,
  26962. + .size = 0x010000,
  26963. + }, {
  26964. + .name = "art",
  26965. + .offset = 0x3f0000,
  26966. + .size = 0x010000,
  26967. + .mask_flags = MTD_WRITEABLE,
  26968. + }
  26969. +};
  26970. +
  26971. +static struct flash_platform_data wnr2000_flash_data = {
  26972. + .parts = wnr2000_partitions,
  26973. + .nr_parts = ARRAY_SIZE(wnr2000_partitions),
  26974. +};
  26975. +
  26976. +static struct gpio_led wnr2000_leds_gpio[] __initdata = {
  26977. + {
  26978. + .name = "netgear:green:power",
  26979. + .gpio = WNR2000_GPIO_LED_PWR_GREEN,
  26980. + .active_low = 1,
  26981. + }, {
  26982. + .name = "netgear:amber:power",
  26983. + .gpio = WNR2000_GPIO_LED_PWR_AMBER,
  26984. + .active_low = 1,
  26985. + }, {
  26986. + .name = "netgear:green:wps",
  26987. + .gpio = WNR2000_GPIO_LED_WPS,
  26988. + .active_low = 1,
  26989. + }, {
  26990. + .name = "netgear:blue:wlan",
  26991. + .gpio = WNR2000_GPIO_LED_WLAN,
  26992. + .active_low = 1,
  26993. + }
  26994. +};
  26995. +
  26996. +static struct gpio_keys_button wnr2000_gpio_keys[] __initdata = {
  26997. + {
  26998. + .desc = "reset",
  26999. + .type = EV_KEY,
  27000. + .code = KEY_RESTART,
  27001. + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL,
  27002. + .gpio = WNR2000_GPIO_BTN_RESET,
  27003. + }, {
  27004. + .desc = "wps",
  27005. + .type = EV_KEY,
  27006. + .code = KEY_WPS_BUTTON,
  27007. + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL,
  27008. + .gpio = WNR2000_GPIO_BTN_WPS,
  27009. + }
  27010. +};
  27011. +
  27012. +static void __init wnr2000_setup(void)
  27013. +{
  27014. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  27015. +
  27016. + ath79_register_mdio(0, 0x0);
  27017. +
  27018. + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
  27019. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  27020. + ath79_eth0_data.speed = SPEED_100;
  27021. + ath79_eth0_data.duplex = DUPLEX_FULL;
  27022. + ath79_eth0_data.has_ar8216 = 1;
  27023. +
  27024. + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
  27025. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  27026. + ath79_eth1_data.phy_mask = 0x10;
  27027. +
  27028. + ath79_register_eth(0);
  27029. + ath79_register_eth(1);
  27030. +
  27031. + ath79_register_m25p80(&wnr2000_flash_data);
  27032. +
  27033. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio),
  27034. + wnr2000_leds_gpio);
  27035. +
  27036. + ath79_register_gpio_keys_polled(-1, WNR2000_KEYS_POLL_INTERVAL,
  27037. + ARRAY_SIZE(wnr2000_gpio_keys),
  27038. + wnr2000_gpio_keys);
  27039. +
  27040. + ath79_register_wmac(eeprom, NULL);
  27041. +}
  27042. +
  27043. +MIPS_MACHINE(ATH79_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup);
  27044. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wnr2200.c linux-4.1.43/arch/mips/ath79/mach-wnr2200.c
  27045. --- linux-4.1.43.orig/arch/mips/ath79/mach-wnr2200.c 1970-01-01 01:00:00.000000000 +0100
  27046. +++ linux-4.1.43/arch/mips/ath79/mach-wnr2200.c 2017-08-06 20:02:15.000000000 +0200
  27047. @@ -0,0 +1,137 @@
  27048. +/*
  27049. + * NETGEAR WNR2200 board support
  27050. + *
  27051. + * Copyright (C) 2013 Aidan Kissane <aidankissane at googlemail.com>
  27052. + *
  27053. + * This program is free software; you can redistribute it and/or modify it
  27054. + * under the terms of the GNU General Public License version 2 as published
  27055. + * by the Free Software Foundation.
  27056. + */
  27057. +
  27058. +#include <linux/gpio.h>
  27059. +
  27060. +#include <linux/mtd/mtd.h>
  27061. +#include <linux/mtd/partitions.h>
  27062. +
  27063. +#include <asm/mach-ath79/ath79.h>
  27064. +
  27065. +#include "dev-ap9x-pci.h"
  27066. +#include "dev-eth.h"
  27067. +#include "dev-gpio-buttons.h"
  27068. +#include "dev-leds-gpio.h"
  27069. +#include "dev-m25p80.h"
  27070. +#include "dev-usb.h"
  27071. +#include "machtypes.h"
  27072. +
  27073. +#define WNR2200_GPIO_LED_LAN2_AMBER 0
  27074. +#define WNR2200_GPIO_LED_LAN4_AMBER 1
  27075. +#define WNR2200_GPIO_LED_WPS 5
  27076. +#define WNR2200_GPIO_LED_WAN_GREEN 7
  27077. +#define WNR2200_GPIO_LED_USB 8
  27078. +#define WNR2200_GPIO_LED_LAN3_AMBER 11
  27079. +#define WNR2200_GPIO_LED_WAN_AMBER 12
  27080. +#define WNR2200_GPIO_LED_LAN1_GREEN 13
  27081. +#define WNR2200_GPIO_LED_LAN2_GREEN 14
  27082. +#define WNR2200_GPIO_LED_LAN3_GREEN 15
  27083. +#define WNR2200_GPIO_LED_LAN4_GREEN 16
  27084. +#define WNR2200_GPIO_LED_PWR_AMBER 21
  27085. +#define WNR2200_GPIO_LED_PWR_GREEN 22
  27086. +#define WNR2200_GPIO_USB_5V 4
  27087. +#define WNR2200_GPIO_USB_POWER 24
  27088. +
  27089. +#define WNR2200_KEYS_POLL_INTERVAL 20 /* msecs */
  27090. +#define WNR2200_KEYS_DEBOUNCE_INTERVAL (3 * WNR2200_KEYS_POLL_INTERVAL)
  27091. +
  27092. +#define WNR2200_MAC0_OFFSET 0
  27093. +#define WNR2200_MAC1_OFFSET 6
  27094. +#define WNR2200_PCIE_CALDATA_OFFSET 0x1000
  27095. +
  27096. +static struct gpio_led wnr2200_leds_gpio[] __initdata = {
  27097. + {
  27098. + .name = "netgear:amber:lan2",
  27099. + .gpio = WNR2200_GPIO_LED_LAN2_AMBER,
  27100. + .active_low = 1,
  27101. + }, {
  27102. + .name = "netgear:amber:lan4",
  27103. + .gpio = WNR2200_GPIO_LED_LAN4_AMBER,
  27104. + .active_low = 1,
  27105. + }, {
  27106. + .name = "netgear:green:wps",
  27107. + .gpio = WNR2200_GPIO_LED_WPS,
  27108. + .active_low = 1,
  27109. + }, {
  27110. + .name = "netgear:green:wan",
  27111. + .gpio = WNR2200_GPIO_LED_WAN_GREEN,
  27112. + .active_low = 1,
  27113. + }, {
  27114. + .name = "netgear:green:usb",
  27115. + .gpio = WNR2200_GPIO_LED_USB,
  27116. + .active_low = 1,
  27117. + }, {
  27118. + .name = "netgear:amber:lan3",
  27119. + .gpio = WNR2200_GPIO_LED_LAN3_AMBER,
  27120. + .active_low = 1,
  27121. + }, {
  27122. + .name = "netgear:amber:wan",
  27123. + .gpio = WNR2200_GPIO_LED_WAN_AMBER,
  27124. + .active_low = 1,
  27125. + }, {
  27126. + .name = "netgear:green:lan1",
  27127. + .gpio = WNR2200_GPIO_LED_LAN1_GREEN,
  27128. + .active_low = 1,
  27129. + }, {
  27130. + .name = "netgear:green:lan2",
  27131. + .gpio = WNR2200_GPIO_LED_LAN2_GREEN,
  27132. + .active_low = 1,
  27133. + }, {
  27134. + .name = "netgear:green:lan3",
  27135. + .gpio = WNR2200_GPIO_LED_LAN3_GREEN,
  27136. + .active_low = 1,
  27137. + }, {
  27138. + .name = "netgear:green:lan4",
  27139. + .gpio = WNR2200_GPIO_LED_LAN4_GREEN,
  27140. + .active_low = 1,
  27141. + }, {
  27142. + .name = "netgear:amber:power",
  27143. + .gpio = WNR2200_GPIO_LED_PWR_AMBER,
  27144. + .active_low = 1,
  27145. + }, {
  27146. + .name = "netgear:green:power",
  27147. + .gpio = WNR2200_GPIO_LED_PWR_GREEN,
  27148. + .active_low = 1,
  27149. + }
  27150. +};
  27151. +
  27152. +static void __init wnr2200_setup(void)
  27153. +{
  27154. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  27155. +
  27156. + ath79_register_mdio(0, 0x0);
  27157. +
  27158. + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2200_MAC0_OFFSET, 0);
  27159. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  27160. + ath79_eth0_data.speed = SPEED_100;
  27161. + ath79_eth0_data.duplex = DUPLEX_FULL;
  27162. +
  27163. + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2200_MAC1_OFFSET, 0);
  27164. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  27165. + ath79_eth1_data.phy_mask = 0x10;
  27166. +
  27167. + ath79_register_eth(0);
  27168. + ath79_register_eth(1);
  27169. +
  27170. + ath79_register_m25p80(NULL);
  27171. + ap91_pci_init(art + WNR2200_PCIE_CALDATA_OFFSET, NULL);
  27172. +
  27173. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2200_leds_gpio),
  27174. + wnr2200_leds_gpio);
  27175. +
  27176. + /* enable power for the USB port */
  27177. + ap9x_pci_setup_wmac_gpio(0,
  27178. + BIT(WNR2200_GPIO_USB_5V),
  27179. + BIT(WNR2200_GPIO_USB_5V));
  27180. +
  27181. + ath79_register_usb();
  27182. +}
  27183. +
  27184. +MIPS_MACHINE(ATH79_MACH_WNR2200, "WNR2200", "NETGEAR WNR2200", wnr2200_setup);
  27185. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wp543.c linux-4.1.43/arch/mips/ath79/mach-wp543.c
  27186. --- linux-4.1.43.orig/arch/mips/ath79/mach-wp543.c 1970-01-01 01:00:00.000000000 +0100
  27187. +++ linux-4.1.43/arch/mips/ath79/mach-wp543.c 2017-08-06 20:02:15.000000000 +0200
  27188. @@ -0,0 +1,109 @@
  27189. +/*
  27190. + * Compex WP543/WPJ543 board support
  27191. + *
  27192. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  27193. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  27194. + *
  27195. + * This program is free software; you can redistribute it and/or modify it
  27196. + * under the terms of the GNU General Public License version 2 as published
  27197. + * by the Free Software Foundation.
  27198. + */
  27199. +
  27200. +#include <asm/mach-ath79/ar71xx_regs.h>
  27201. +#include <asm/mach-ath79/ath79.h>
  27202. +
  27203. +#include "dev-eth.h"
  27204. +#include "dev-gpio-buttons.h"
  27205. +#include "dev-leds-gpio.h"
  27206. +#include "dev-m25p80.h"
  27207. +#include "dev-usb.h"
  27208. +#include "machtypes.h"
  27209. +#include "pci.h"
  27210. +
  27211. +#define WP543_GPIO_SW6 2
  27212. +#define WP543_GPIO_LED_1 3
  27213. +#define WP543_GPIO_LED_2 4
  27214. +#define WP543_GPIO_LED_WLAN 5
  27215. +#define WP543_GPIO_LED_CONN 6
  27216. +#define WP543_GPIO_LED_DIAG 7
  27217. +#define WP543_GPIO_SW4 8
  27218. +
  27219. +#define WP543_KEYS_POLL_INTERVAL 20 /* msecs */
  27220. +#define WP543_KEYS_DEBOUNCE_INTERVAL (3 * WP543_KEYS_POLL_INTERVAL)
  27221. +
  27222. +static struct gpio_led wp543_leds_gpio[] __initdata = {
  27223. + {
  27224. + .name = "wp543:green:led1",
  27225. + .gpio = WP543_GPIO_LED_1,
  27226. + .active_low = 1,
  27227. + }, {
  27228. + .name = "wp543:green:led2",
  27229. + .gpio = WP543_GPIO_LED_2,
  27230. + .active_low = 1,
  27231. + }, {
  27232. + .name = "wp543:green:wlan",
  27233. + .gpio = WP543_GPIO_LED_WLAN,
  27234. + .active_low = 1,
  27235. + }, {
  27236. + .name = "wp543:green:conn",
  27237. + .gpio = WP543_GPIO_LED_CONN,
  27238. + .active_low = 1,
  27239. + }, {
  27240. + .name = "wp543:green:diag",
  27241. + .gpio = WP543_GPIO_LED_DIAG,
  27242. + .active_low = 1,
  27243. + }
  27244. +};
  27245. +
  27246. +static struct gpio_keys_button wp543_gpio_keys[] __initdata = {
  27247. + {
  27248. + .desc = "sw6",
  27249. + .type = EV_KEY,
  27250. + .code = BTN_0,
  27251. + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL,
  27252. + .gpio = WP543_GPIO_SW6,
  27253. + .active_low = 1,
  27254. + }, {
  27255. + .desc = "sw4",
  27256. + .type = EV_KEY,
  27257. + .code = KEY_RESTART,
  27258. + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL,
  27259. + .gpio = WP543_GPIO_SW4,
  27260. + .active_low = 1,
  27261. + }
  27262. +};
  27263. +
  27264. +static const char *wp543_part_probes[] = {
  27265. + "MyLoader",
  27266. + NULL,
  27267. +};
  27268. +
  27269. +static struct flash_platform_data wp543_flash_data = {
  27270. + .part_probes = wp543_part_probes,
  27271. +};
  27272. +
  27273. +static void __init wp543_setup(void)
  27274. +{
  27275. + ath79_register_m25p80(&wp543_flash_data);
  27276. +
  27277. + ath79_register_mdio(0, 0xfffffff0);
  27278. +
  27279. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  27280. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  27281. + ath79_eth0_data.phy_mask = 0x0f;
  27282. + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC |
  27283. + AR71XX_RESET_GE0_PHY;
  27284. + ath79_register_eth(0);
  27285. +
  27286. + ath79_register_usb();
  27287. + ath79_register_pci();
  27288. +
  27289. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio),
  27290. + wp543_leds_gpio);
  27291. +
  27292. + ath79_register_gpio_keys_polled(-1, WP543_KEYS_POLL_INTERVAL,
  27293. + ARRAY_SIZE(wp543_gpio_keys),
  27294. + wp543_gpio_keys);
  27295. +}
  27296. +
  27297. +MIPS_MACHINE(ATH79_MACH_WP543, "WP543", "Compex WP543", wp543_setup);
  27298. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wpe72.c linux-4.1.43/arch/mips/ath79/mach-wpe72.c
  27299. --- linux-4.1.43.orig/arch/mips/ath79/mach-wpe72.c 1970-01-01 01:00:00.000000000 +0100
  27300. +++ linux-4.1.43/arch/mips/ath79/mach-wpe72.c 2017-08-06 20:02:15.000000000 +0200
  27301. @@ -0,0 +1,97 @@
  27302. +/*
  27303. + * Compex WPE72 board support
  27304. + *
  27305. + * Copyright (C) 2012 Johnathan Boyce<jon.boyce@globalreach.eu.com>
  27306. + *
  27307. + * This program is free software; you can redistribute it and/or modify it
  27308. + * under the terms of the GNU General Public License version 2 as published
  27309. + * by the Free Software Foundation.
  27310. + */
  27311. +
  27312. +#include <asm/mach-ath79/ath79.h>
  27313. +
  27314. +#include "dev-eth.h"
  27315. +#include "dev-gpio-buttons.h"
  27316. +#include "dev-leds-gpio.h"
  27317. +#include "dev-m25p80.h"
  27318. +#include "dev-usb.h"
  27319. +#include "machtypes.h"
  27320. +#include "pci.h"
  27321. +
  27322. +#define WPE72_GPIO_RESET 12
  27323. +#define WPE72_GPIO_LED_DIAG 13
  27324. +#define WPE72_GPIO_LED_1 14
  27325. +#define WPE72_GPIO_LED_2 15
  27326. +#define WPE72_GPIO_LED_3 16
  27327. +#define WPE72_GPIO_LED_4 17
  27328. +
  27329. +#define WPE72_KEYS_POLL_INTERVAL 20 /* msecs */
  27330. +#define WPE72_KEYS_DEBOUNCE_INTERVAL (3 * WPE72_KEYS_POLL_INTERVAL)
  27331. +
  27332. +static struct gpio_led wpe72_leds_gpio[] __initdata = {
  27333. + {
  27334. + .name = "wpe72:green:led1",
  27335. + .gpio = WPE72_GPIO_LED_1,
  27336. + .active_low = 1,
  27337. + }, {
  27338. + .name = "wpe72:green:led2",
  27339. + .gpio = WPE72_GPIO_LED_2,
  27340. + .active_low = 1,
  27341. + }, {
  27342. + .name = "wpe72:green:led3",
  27343. + .gpio = WPE72_GPIO_LED_3,
  27344. + .active_low = 1,
  27345. + }, {
  27346. + .name = "wpe72:green:led4",
  27347. + .gpio = WPE72_GPIO_LED_4,
  27348. + .active_low = 1,
  27349. + }, {
  27350. + .name = "wpe72:green:diag",
  27351. + .gpio = WPE72_GPIO_LED_DIAG,
  27352. + .active_low = 1,
  27353. + }
  27354. +};
  27355. +
  27356. +static struct gpio_keys_button wpe72_gpio_keys[] __initdata = {
  27357. + {
  27358. + .desc = "reset",
  27359. + .type = EV_KEY,
  27360. + .code = KEY_RESTART,
  27361. + .debounce_interval = WPE72_KEYS_DEBOUNCE_INTERVAL,
  27362. + .gpio = WPE72_GPIO_RESET,
  27363. + .active_low = 1,
  27364. + }
  27365. +};
  27366. +
  27367. +static const char *wpe72_part_probes[] = {
  27368. + "MyLoader",
  27369. + NULL,
  27370. +};
  27371. +
  27372. +static struct flash_platform_data wpe72_flash_data = {
  27373. + .part_probes = wpe72_part_probes,
  27374. +};
  27375. +
  27376. +static void __init wpe72_setup(void)
  27377. +{
  27378. + ath79_register_m25p80(&wpe72_flash_data);
  27379. + ath79_register_mdio(0, 0x0);
  27380. +
  27381. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  27382. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  27383. +
  27384. + ath79_register_eth(0);
  27385. + ath79_register_eth(1);
  27386. +
  27387. + ath79_register_usb();
  27388. + ath79_register_pci();
  27389. +
  27390. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpe72_leds_gpio),
  27391. + wpe72_leds_gpio);
  27392. +
  27393. + ath79_register_gpio_keys_polled(-1, WPE72_KEYS_POLL_INTERVAL,
  27394. + ARRAY_SIZE(wpe72_gpio_keys),
  27395. + wpe72_gpio_keys);
  27396. +}
  27397. +
  27398. +MIPS_MACHINE(ATH79_MACH_WPE72, "WPE72", "Compex WPE72", wpe72_setup);
  27399. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wpj344.c linux-4.1.43/arch/mips/ath79/mach-wpj344.c
  27400. --- linux-4.1.43.orig/arch/mips/ath79/mach-wpj344.c 1970-01-01 01:00:00.000000000 +0100
  27401. +++ linux-4.1.43/arch/mips/ath79/mach-wpj344.c 2017-08-06 20:02:15.000000000 +0200
  27402. @@ -0,0 +1,175 @@
  27403. +/*
  27404. + * Compex WPJ344 board support
  27405. + *
  27406. + * Copyright (c) 2011 Qualcomm Atheros
  27407. + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  27408. + *
  27409. + * Permission to use, copy, modify, and/or distribute this software for any
  27410. + * purpose with or without fee is hereby granted, provided that the above
  27411. + * copyright notice and this permission notice appear in all copies.
  27412. + *
  27413. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  27414. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  27415. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  27416. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  27417. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  27418. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  27419. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  27420. + *
  27421. + */
  27422. +
  27423. +#include <linux/phy.h>
  27424. +#include <linux/platform_device.h>
  27425. +#include <linux/ath9k_platform.h>
  27426. +#include <linux/ar8216_platform.h>
  27427. +
  27428. +#include <asm/mach-ath79/ar71xx_regs.h>
  27429. +
  27430. +#include "common.h"
  27431. +#include "pci.h"
  27432. +#include "dev-ap9x-pci.h"
  27433. +#include "dev-gpio-buttons.h"
  27434. +#include "dev-eth.h"
  27435. +#include "dev-usb.h"
  27436. +#include "dev-leds-gpio.h"
  27437. +#include "dev-m25p80.h"
  27438. +#include "dev-spi.h"
  27439. +#include "dev-wmac.h"
  27440. +#include "machtypes.h"
  27441. +
  27442. +#define WPJ344_GPIO_LED_SIG1 15
  27443. +#define WPJ344_GPIO_LED_SIG2 20
  27444. +#define WPJ344_GPIO_LED_SIG3 21
  27445. +#define WPJ344_GPIO_LED_SIG4 22
  27446. +#define WPJ344_GPIO_LED_STATUS 14
  27447. +
  27448. +#define WPJ344_GPIO_BTN_RESET 12
  27449. +
  27450. +#define WPJ344_KEYS_POLL_INTERVAL 20 /* msecs */
  27451. +#define WPJ344_KEYS_DEBOUNCE_INTERVAL (3 * WPJ344_KEYS_POLL_INTERVAL)
  27452. +
  27453. +#define WPJ344_MAC0_OFFSET 0
  27454. +#define WPJ344_MAC1_OFFSET 6
  27455. +#define WPJ344_WMAC_CALDATA_OFFSET 0x1000
  27456. +#define WPJ344_PCIE_CALDATA_OFFSET 0x5000
  27457. +
  27458. +static struct gpio_led wpj344_leds_gpio[] __initdata = {
  27459. + {
  27460. + .name = "wpj344:green:status",
  27461. + .gpio = WPJ344_GPIO_LED_STATUS,
  27462. + .active_low = 1,
  27463. + },
  27464. + {
  27465. + .name = "wpj344:red:sig1",
  27466. + .gpio = WPJ344_GPIO_LED_SIG1,
  27467. + .active_low = 1,
  27468. + },
  27469. + {
  27470. + .name = "wpj344:yellow:sig2",
  27471. + .gpio = WPJ344_GPIO_LED_SIG2,
  27472. + .active_low = 1,
  27473. + },
  27474. + {
  27475. + .name = "wpj344:green:sig3",
  27476. + .gpio = WPJ344_GPIO_LED_SIG3,
  27477. + .active_low = 1,
  27478. + },
  27479. + {
  27480. + .name = "wpj344:green:sig4",
  27481. + .gpio = WPJ344_GPIO_LED_SIG4,
  27482. + .active_low = 1,
  27483. + }
  27484. +};
  27485. +
  27486. +static struct gpio_keys_button wpj344_gpio_keys[] __initdata = {
  27487. + {
  27488. + .desc = "reset",
  27489. + .type = EV_KEY,
  27490. + .code = KEY_RESTART,
  27491. + .debounce_interval = WPJ344_KEYS_DEBOUNCE_INTERVAL,
  27492. + .gpio = WPJ344_GPIO_BTN_RESET,
  27493. + .active_low = 1,
  27494. + },
  27495. +};
  27496. +
  27497. +static struct ar8327_pad_cfg wpj344_ar8327_pad0_cfg = {
  27498. + .mode = AR8327_PAD_MAC_RGMII,
  27499. + .txclk_delay_en = true,
  27500. + .rxclk_delay_en = true,
  27501. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  27502. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  27503. +};
  27504. +
  27505. +static struct ar8327_led_cfg wpj344_ar8327_led_cfg = {
  27506. + .led_ctrl0 = 0x00000000,
  27507. + .led_ctrl1 = 0xc737c737,
  27508. + .led_ctrl2 = 0x00000000,
  27509. + .led_ctrl3 = 0x00c30c00,
  27510. + .open_drain = true,
  27511. +};
  27512. +
  27513. +static struct ar8327_platform_data wpj344_ar8327_data = {
  27514. + .pad0_cfg = &wpj344_ar8327_pad0_cfg,
  27515. + .port0_cfg = {
  27516. + .force_link = 1,
  27517. + .speed = AR8327_PORT_SPEED_1000,
  27518. + .duplex = 1,
  27519. + .txpause = 1,
  27520. + .rxpause = 1,
  27521. + },
  27522. + .led_cfg = &wpj344_ar8327_led_cfg,
  27523. +};
  27524. +
  27525. +static struct mdio_board_info wpj344_mdio0_info[] = {
  27526. + {
  27527. + .bus_id = "ag71xx-mdio.0",
  27528. + .phy_addr = 0,
  27529. + .platform_data = &wpj344_ar8327_data,
  27530. + },
  27531. +};
  27532. +
  27533. +static void __init wpj344_setup(void)
  27534. +{
  27535. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  27536. +
  27537. + ath79_register_m25p80(NULL);
  27538. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj344_leds_gpio),
  27539. + wpj344_leds_gpio);
  27540. + ath79_register_gpio_keys_polled(-1, WPJ344_KEYS_POLL_INTERVAL,
  27541. + ARRAY_SIZE(wpj344_gpio_keys),
  27542. + wpj344_gpio_keys);
  27543. +
  27544. + ath79_register_usb();
  27545. +
  27546. + ath79_register_wmac(art + WPJ344_WMAC_CALDATA_OFFSET, NULL);
  27547. +
  27548. + ath79_register_pci();
  27549. +
  27550. + mdiobus_register_board_info(wpj344_mdio0_info,
  27551. + ARRAY_SIZE(wpj344_mdio0_info));
  27552. +
  27553. + ath79_register_mdio(1, 0x0);
  27554. + ath79_register_mdio(0, 0x0);
  27555. +
  27556. + ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ344_MAC0_OFFSET, 0);
  27557. + ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ344_MAC1_OFFSET, 0);
  27558. +
  27559. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  27560. + AR934X_ETH_CFG_SW_ONLY_MODE);
  27561. +
  27562. + /* GMAC0 is connected to an AR8327 switch */
  27563. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  27564. + ath79_eth0_data.phy_mask = BIT(0);
  27565. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  27566. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  27567. +
  27568. + /* GMAC1 is connected to the internal switch */
  27569. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  27570. + ath79_eth1_data.speed = SPEED_1000;
  27571. + ath79_eth1_data.duplex = DUPLEX_FULL;
  27572. +
  27573. + ath79_register_eth(0);
  27574. + ath79_register_eth(1);
  27575. +}
  27576. +
  27577. +MIPS_MACHINE(ATH79_MACH_WPJ344, "WPJ344", "Compex WPJ344", wpj344_setup);
  27578. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wpj531.c linux-4.1.43/arch/mips/ath79/mach-wpj531.c
  27579. --- linux-4.1.43.orig/arch/mips/ath79/mach-wpj531.c 1970-01-01 01:00:00.000000000 +0100
  27580. +++ linux-4.1.43/arch/mips/ath79/mach-wpj531.c 2017-08-06 20:02:15.000000000 +0200
  27581. @@ -0,0 +1,143 @@
  27582. +/*
  27583. + * Compex WPJ531 board support
  27584. + *
  27585. + * Copyright (c) 2012 Qualcomm Atheros
  27586. + * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
  27587. + *
  27588. + * Permission to use, copy, modify, and/or distribute this software for any
  27589. + * purpose with or without fee is hereby granted, provided that the above
  27590. + * copyright notice and this permission notice appear in all copies.
  27591. + *
  27592. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  27593. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  27594. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  27595. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  27596. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  27597. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  27598. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  27599. + *
  27600. + */
  27601. +
  27602. +#include <linux/irq.h>
  27603. +#include <linux/platform_device.h>
  27604. +#include <linux/ar8216_platform.h>
  27605. +
  27606. +#include <asm/mach-ath79/ar71xx_regs.h>
  27607. +
  27608. +#include "pci.h"
  27609. +#include "common.h"
  27610. +#include "dev-ap9x-pci.h"
  27611. +#include "dev-gpio-buttons.h"
  27612. +#include "dev-eth.h"
  27613. +#include "dev-leds-gpio.h"
  27614. +#include "dev-m25p80.h"
  27615. +#include "dev-usb.h"
  27616. +#include "dev-wmac.h"
  27617. +#include "machtypes.h"
  27618. +
  27619. +#define WPJ531_GPIO_LED_SIG1 14
  27620. +#define WPJ531_GPIO_LED_SIG2 15
  27621. +#define WPJ531_GPIO_LED_SIG3 22
  27622. +#define WPJ531_GPIO_LED_SIG4 23
  27623. +#define WPJ531_GPIO_BUZZER 4
  27624. +
  27625. +#define WPJ531_GPIO_BTN_RESET 17
  27626. +
  27627. +#define WPJ531_KEYS_POLL_INTERVAL 20 /* msecs */
  27628. +#define WPJ531_KEYS_DEBOUNCE_INTERVAL (3 * WPJ531_KEYS_POLL_INTERVAL)
  27629. +
  27630. +#define WPJ531_MAC0_OFFSET 0x10
  27631. +#define WPJ531_MAC1_OFFSET 0x18
  27632. +#define WPJ531_WMAC_CALDATA_OFFSET 0x1000
  27633. +#define WPJ531_PCIE_CALDATA_OFFSET 0x5000
  27634. +
  27635. +#define WPJ531_ART_SIZE 0x8000
  27636. +
  27637. +static struct gpio_led wpj531_leds_gpio[] __initdata = {
  27638. + {
  27639. + .name = "wpj531:red:sig1",
  27640. + .gpio = WPJ531_GPIO_LED_SIG1,
  27641. + .active_low = 1,
  27642. + },
  27643. + {
  27644. + .name = "wpj531:yellow:sig2",
  27645. + .gpio = WPJ531_GPIO_LED_SIG2,
  27646. + .active_low = 1,
  27647. + },
  27648. + {
  27649. + .name = "wpj531:green:sig3",
  27650. + .gpio = WPJ531_GPIO_LED_SIG3,
  27651. + .active_low = 1,
  27652. + },
  27653. + {
  27654. + .name = "wpj531:green:sig4",
  27655. + .gpio = WPJ531_GPIO_LED_SIG4,
  27656. + .active_low = 1,
  27657. + },
  27658. + {
  27659. + .name = "wpj531:buzzer",
  27660. + .gpio = WPJ531_GPIO_BUZZER,
  27661. + .active_low = 0,
  27662. + }
  27663. +};
  27664. +
  27665. +static struct gpio_keys_button wpj531_gpio_keys[] __initdata = {
  27666. + {
  27667. + .desc = "reset",
  27668. + .type = EV_KEY,
  27669. + .code = KEY_RESTART,
  27670. + .debounce_interval = WPJ531_KEYS_DEBOUNCE_INTERVAL,
  27671. + .gpio = WPJ531_GPIO_BTN_RESET,
  27672. + .active_low = 1,
  27673. + },
  27674. +};
  27675. +
  27676. +static void __init common_setup(void)
  27677. +{
  27678. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  27679. + u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
  27680. +
  27681. + ath79_register_m25p80(NULL);
  27682. +
  27683. + ath79_setup_ar933x_phy4_switch(false, false);
  27684. +
  27685. + ath79_register_mdio(0, 0x0);
  27686. +
  27687. + /* LAN */
  27688. + ath79_eth0_data.duplex = DUPLEX_FULL;
  27689. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  27690. + ath79_eth0_data.speed = SPEED_100;
  27691. + ath79_eth0_data.phy_mask = BIT(4);
  27692. + ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ531_MAC0_OFFSET, 0);
  27693. + ath79_register_eth(0);
  27694. +
  27695. + /* WAN */
  27696. + ath79_switch_data.phy4_mii_en = 1;
  27697. + ath79_eth1_data.duplex = DUPLEX_FULL;
  27698. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  27699. + ath79_eth1_data.speed = SPEED_1000;
  27700. + ath79_switch_data.phy_poll_mask |= BIT(4);
  27701. + ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ531_MAC1_OFFSET, 0);
  27702. + ath79_register_eth(1);
  27703. +
  27704. + ath79_register_wmac(art + WPJ531_WMAC_CALDATA_OFFSET, NULL);
  27705. +
  27706. + ath79_register_pci();
  27707. + ath79_register_usb();
  27708. +}
  27709. +
  27710. +static void __init wpj531_setup(void)
  27711. +{
  27712. + common_setup();
  27713. +
  27714. + ath79_register_leds_gpio(-1,
  27715. + ARRAY_SIZE(wpj531_leds_gpio),
  27716. + wpj531_leds_gpio);
  27717. +
  27718. + ath79_register_gpio_keys_polled(-1,
  27719. + WPJ531_KEYS_POLL_INTERVAL,
  27720. + ARRAY_SIZE(wpj531_gpio_keys),
  27721. + wpj531_gpio_keys);
  27722. +}
  27723. +
  27724. +MIPS_MACHINE(ATH79_MACH_WPJ531, "WPJ531", "Compex WPJ531", wpj531_setup);
  27725. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wpj558.c linux-4.1.43/arch/mips/ath79/mach-wpj558.c
  27726. --- linux-4.1.43.orig/arch/mips/ath79/mach-wpj558.c 1970-01-01 01:00:00.000000000 +0100
  27727. +++ linux-4.1.43/arch/mips/ath79/mach-wpj558.c 2017-08-06 20:02:15.000000000 +0200
  27728. @@ -0,0 +1,177 @@
  27729. +/*
  27730. + * Compex WPJ558 board support
  27731. + *
  27732. + * Copyright (c) 2012 Qualcomm Atheros
  27733. + * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
  27734. + *
  27735. + * Permission to use, copy, modify, and/or distribute this software for any
  27736. + * purpose with or without fee is hereby granted, provided that the above
  27737. + * copyright notice and this permission notice appear in all copies.
  27738. + *
  27739. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  27740. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  27741. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  27742. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  27743. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  27744. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  27745. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  27746. + *
  27747. + */
  27748. +
  27749. +#include <linux/pci.h>
  27750. +#include <linux/phy.h>
  27751. +#include <linux/gpio.h>
  27752. +#include <linux/platform_device.h>
  27753. +#include <linux/ath9k_platform.h>
  27754. +#include <linux/ar8216_platform.h>
  27755. +
  27756. +#include <asm/mach-ath79/ar71xx_regs.h>
  27757. +
  27758. +#include "common.h"
  27759. +#include "pci.h"
  27760. +#include "dev-ap9x-pci.h"
  27761. +#include "dev-gpio-buttons.h"
  27762. +#include "dev-eth.h"
  27763. +#include "dev-usb.h"
  27764. +#include "dev-leds-gpio.h"
  27765. +#include "dev-m25p80.h"
  27766. +#include "dev-spi.h"
  27767. +#include "dev-wmac.h"
  27768. +#include "machtypes.h"
  27769. +
  27770. +#define WPJ558_GPIO_LED_SIG1 14
  27771. +#define WPJ558_GPIO_LED_SIG2 15
  27772. +#define WPJ558_GPIO_LED_SIG3 22
  27773. +#define WPJ558_GPIO_LED_SIG4 23
  27774. +#define WPJ558_GPIO_BUZZER 4
  27775. +
  27776. +#define WPJ558_GPIO_BTN_RESET 17
  27777. +
  27778. +#define WPJ558_KEYS_POLL_INTERVAL 20 /* msecs */
  27779. +#define WPJ558_KEYS_DEBOUNCE_INTERVAL (3 * WPJ558_KEYS_POLL_INTERVAL)
  27780. +
  27781. +#define WPJ558_MAC_OFFSET 0x1002
  27782. +#define WPJ558_WMAC_CALDATA_OFFSET 0x1000
  27783. +
  27784. +static struct gpio_led wpj558_leds_gpio[] __initdata = {
  27785. + {
  27786. + .name = "wpj558:red:sig1",
  27787. + .gpio = WPJ558_GPIO_LED_SIG1,
  27788. + .active_low = 1,
  27789. + },
  27790. + {
  27791. + .name = "wpj558:yellow:sig2",
  27792. + .gpio = WPJ558_GPIO_LED_SIG2,
  27793. + .active_low = 1,
  27794. + },
  27795. + {
  27796. + .name = "wpj558:green:sig3",
  27797. + .gpio = WPJ558_GPIO_LED_SIG3,
  27798. + .active_low = 1,
  27799. + },
  27800. + {
  27801. + .name = "wpj558:green:sig4",
  27802. + .gpio = WPJ558_GPIO_LED_SIG4,
  27803. + .active_low = 1,
  27804. + },
  27805. + {
  27806. + .name = "wpj558:buzzer",
  27807. + .gpio = WPJ558_GPIO_BUZZER,
  27808. + .active_low = 0,
  27809. + }
  27810. +};
  27811. +
  27812. +static struct gpio_keys_button wpj558_gpio_keys[] __initdata = {
  27813. + {
  27814. + .desc = "reset",
  27815. + .type = EV_KEY,
  27816. + .code = KEY_RESTART,
  27817. + .debounce_interval = WPJ558_KEYS_DEBOUNCE_INTERVAL,
  27818. + .gpio = WPJ558_GPIO_BTN_RESET,
  27819. + .active_low = 1,
  27820. + },
  27821. +};
  27822. +
  27823. +static struct ar8327_pad_cfg wpj558_ar8327_pad0_cfg = {
  27824. + .mode = AR8327_PAD_MAC_SGMII,
  27825. + .sgmii_delay_en = true,
  27826. +};
  27827. +
  27828. +static struct ar8327_pad_cfg wpj558_ar8327_pad6_cfg = {
  27829. + .mode = AR8327_PAD_MAC_RGMII,
  27830. + .txclk_delay_en = true,
  27831. + .rxclk_delay_en = true,
  27832. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  27833. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  27834. +};
  27835. +
  27836. +static struct ar8327_platform_data wpj558_ar8327_data = {
  27837. + .pad0_cfg = &wpj558_ar8327_pad0_cfg,
  27838. + .pad6_cfg = &wpj558_ar8327_pad6_cfg,
  27839. + .port0_cfg = {
  27840. + .force_link = 1,
  27841. + .speed = AR8327_PORT_SPEED_1000,
  27842. + .duplex = 1,
  27843. + .txpause = 1,
  27844. + .rxpause = 1,
  27845. + },
  27846. + .port6_cfg = {
  27847. + .force_link = 1,
  27848. + .speed = AR8327_PORT_SPEED_1000,
  27849. + .duplex = 1,
  27850. + .txpause = 1,
  27851. + .rxpause = 1,
  27852. + },
  27853. +};
  27854. +
  27855. +static struct mdio_board_info wpj558_mdio0_info[] = {
  27856. + {
  27857. + .bus_id = "ag71xx-mdio.0",
  27858. + .phy_addr = 0,
  27859. + .platform_data = &wpj558_ar8327_data,
  27860. + },
  27861. +};
  27862. +
  27863. +static void __init wpj558_setup(void)
  27864. +{
  27865. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  27866. +
  27867. + ath79_register_m25p80(NULL);
  27868. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj558_leds_gpio),
  27869. + wpj558_leds_gpio);
  27870. + ath79_register_gpio_keys_polled(-1, WPJ558_KEYS_POLL_INTERVAL,
  27871. + ARRAY_SIZE(wpj558_gpio_keys),
  27872. + wpj558_gpio_keys);
  27873. +
  27874. + ath79_register_usb();
  27875. +
  27876. + ath79_register_wmac(art + WPJ558_WMAC_CALDATA_OFFSET, NULL);
  27877. +
  27878. + ath79_register_pci();
  27879. +
  27880. + mdiobus_register_board_info(wpj558_mdio0_info,
  27881. + ARRAY_SIZE(wpj558_mdio0_info));
  27882. + ath79_register_mdio(0, 0x0);
  27883. +
  27884. + ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
  27885. + ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
  27886. +
  27887. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  27888. +
  27889. + /* GMAC0 is connected to an AR8327 switch */
  27890. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  27891. + ath79_eth0_data.phy_mask = BIT(0);
  27892. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  27893. + ath79_eth0_pll_data.pll_1000 = 0x56000000;
  27894. +
  27895. + /* GMAC1 is connected to the SGMII interface */
  27896. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  27897. + ath79_eth1_data.speed = SPEED_1000;
  27898. + ath79_eth1_data.duplex = DUPLEX_FULL;
  27899. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  27900. +
  27901. + ath79_register_eth(0);
  27902. + ath79_register_eth(1);
  27903. +}
  27904. +
  27905. +MIPS_MACHINE(ATH79_MACH_WPJ558, "WPJ558", "Compex WPJ558", wpj558_setup);
  27906. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wrt160nl.c linux-4.1.43/arch/mips/ath79/mach-wrt160nl.c
  27907. --- linux-4.1.43.orig/arch/mips/ath79/mach-wrt160nl.c 1970-01-01 01:00:00.000000000 +0100
  27908. +++ linux-4.1.43/arch/mips/ath79/mach-wrt160nl.c 2017-08-06 20:02:15.000000000 +0200
  27909. @@ -0,0 +1,126 @@
  27910. +/*
  27911. + * Linksys WRT160NL board support
  27912. + *
  27913. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  27914. + *
  27915. + * This program is free software; you can redistribute it and/or modify it
  27916. + * under the terms of the GNU General Public License version 2 as published
  27917. + * by the Free Software Foundation.
  27918. + */
  27919. +
  27920. +#include <asm/mach-ath79/ath79.h>
  27921. +
  27922. +#include "dev-eth.h"
  27923. +#include "dev-gpio-buttons.h"
  27924. +#include "dev-leds-gpio.h"
  27925. +#include "dev-m25p80.h"
  27926. +#include "dev-usb.h"
  27927. +#include "dev-wmac.h"
  27928. +#include "nvram.h"
  27929. +#include "machtypes.h"
  27930. +
  27931. +#define WRT160NL_GPIO_LED_POWER 14
  27932. +#define WRT160NL_GPIO_LED_WPS_AMBER 9
  27933. +#define WRT160NL_GPIO_LED_WPS_BLUE 8
  27934. +#define WRT160NL_GPIO_LED_WLAN 6
  27935. +
  27936. +#define WRT160NL_GPIO_BTN_WPS 7
  27937. +#define WRT160NL_GPIO_BTN_RESET 21
  27938. +
  27939. +#define WRT160NL_KEYS_POLL_INTERVAL 20 /* msecs */
  27940. +#define WRT160NL_KEYS_DEBOUNCE_INTERVAL (3 * WRT160NL_KEYS_POLL_INTERVAL)
  27941. +
  27942. +#define WRT160NL_NVRAM_ADDR 0x1f7e0000
  27943. +#define WRT160NL_NVRAM_SIZE 0x10000
  27944. +
  27945. +static const char *wrt160nl_part_probes[] = {
  27946. + "cybertan",
  27947. + NULL,
  27948. +};
  27949. +
  27950. +static struct flash_platform_data wrt160nl_flash_data = {
  27951. + .part_probes = wrt160nl_part_probes,
  27952. +};
  27953. +
  27954. +static struct gpio_led wrt160nl_leds_gpio[] __initdata = {
  27955. + {
  27956. + .name = "wrt160nl:blue:power",
  27957. + .gpio = WRT160NL_GPIO_LED_POWER,
  27958. + .active_low = 1,
  27959. + .default_trigger = "default-on",
  27960. + }, {
  27961. + .name = "wrt160nl:amber:wps",
  27962. + .gpio = WRT160NL_GPIO_LED_WPS_AMBER,
  27963. + .active_low = 1,
  27964. + }, {
  27965. + .name = "wrt160nl:blue:wps",
  27966. + .gpio = WRT160NL_GPIO_LED_WPS_BLUE,
  27967. + .active_low = 1,
  27968. + }, {
  27969. + .name = "wrt160nl:blue:wlan",
  27970. + .gpio = WRT160NL_GPIO_LED_WLAN,
  27971. + .active_low = 1,
  27972. + }
  27973. +};
  27974. +
  27975. +static struct gpio_keys_button wrt160nl_gpio_keys[] __initdata = {
  27976. + {
  27977. + .desc = "reset",
  27978. + .type = EV_KEY,
  27979. + .code = KEY_RESTART,
  27980. + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL,
  27981. + .gpio = WRT160NL_GPIO_BTN_RESET,
  27982. + .active_low = 1,
  27983. + }, {
  27984. + .desc = "wps",
  27985. + .type = EV_KEY,
  27986. + .code = KEY_WPS_BUTTON,
  27987. + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL,
  27988. + .gpio = WRT160NL_GPIO_BTN_WPS,
  27989. + .active_low = 1,
  27990. + }
  27991. +};
  27992. +
  27993. +static void __init wrt160nl_setup(void)
  27994. +{
  27995. + const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR);
  27996. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  27997. + u8 mac[6];
  27998. +
  27999. + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE,
  28000. + "lan_hwaddr=", mac) == 0) {
  28001. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  28002. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  28003. + }
  28004. +
  28005. + ath79_register_mdio(0, 0x0);
  28006. +
  28007. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  28008. + ath79_eth0_data.phy_mask = 0x01;
  28009. +
  28010. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  28011. + ath79_eth1_data.phy_mask = 0x10;
  28012. +
  28013. + ath79_register_eth(0);
  28014. + ath79_register_eth(1);
  28015. +
  28016. + ath79_register_m25p80(&wrt160nl_flash_data);
  28017. +
  28018. + ath79_register_usb();
  28019. +
  28020. + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE,
  28021. + "wl0_hwaddr=", mac) == 0)
  28022. + ath79_register_wmac(eeprom, mac);
  28023. + else
  28024. + ath79_register_wmac(eeprom, NULL);
  28025. +
  28026. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio),
  28027. + wrt160nl_leds_gpio);
  28028. +
  28029. + ath79_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL,
  28030. + ARRAY_SIZE(wrt160nl_gpio_keys),
  28031. + wrt160nl_gpio_keys);
  28032. +}
  28033. +
  28034. +MIPS_MACHINE(ATH79_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL",
  28035. + wrt160nl_setup);
  28036. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wrt400n.c linux-4.1.43/arch/mips/ath79/mach-wrt400n.c
  28037. --- linux-4.1.43.orig/arch/mips/ath79/mach-wrt400n.c 1970-01-01 01:00:00.000000000 +0100
  28038. +++ linux-4.1.43/arch/mips/ath79/mach-wrt400n.c 2017-08-06 20:02:15.000000000 +0200
  28039. @@ -0,0 +1,161 @@
  28040. +/*
  28041. + * Linksys WRT400N board support
  28042. + *
  28043. + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
  28044. + * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
  28045. + *
  28046. + * This program is free software; you can redistribute it and/or modify it
  28047. + * under the terms of the GNU General Public License version 2 as published
  28048. + * by the Free Software Foundation.
  28049. + */
  28050. +
  28051. +#include <linux/mtd/mtd.h>
  28052. +#include <linux/mtd/partitions.h>
  28053. +
  28054. +#include <asm/mach-ath79/ath79.h>
  28055. +
  28056. +#include "dev-ap9x-pci.h"
  28057. +#include "dev-eth.h"
  28058. +#include "dev-gpio-buttons.h"
  28059. +#include "dev-leds-gpio.h"
  28060. +#include "dev-m25p80.h"
  28061. +#include "machtypes.h"
  28062. +
  28063. +#define WRT400N_GPIO_LED_POWER 1
  28064. +#define WRT400N_GPIO_LED_WPS_BLUE 4
  28065. +#define WRT400N_GPIO_LED_WPS_AMBER 5
  28066. +#define WRT400N_GPIO_LED_WLAN 6
  28067. +
  28068. +#define WRT400N_GPIO_BTN_RESET 8
  28069. +#define WRT400N_GPIO_BTN_WLSEC 3
  28070. +
  28071. +#define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */
  28072. +#define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL)
  28073. +
  28074. +#define WRT400N_MAC_ADDR_OFFSET 0x120c
  28075. +#define WRT400N_CALDATA0_OFFSET 0x1000
  28076. +#define WRT400N_CALDATA1_OFFSET 0x5000
  28077. +
  28078. +static struct mtd_partition wrt400n_partitions[] = {
  28079. + {
  28080. + .name = "uboot",
  28081. + .offset = 0,
  28082. + .size = 0x030000,
  28083. + .mask_flags = MTD_WRITEABLE,
  28084. + }, {
  28085. + .name = "env",
  28086. + .offset = 0x030000,
  28087. + .size = 0x010000,
  28088. + .mask_flags = MTD_WRITEABLE,
  28089. + }, {
  28090. + .name = "linux",
  28091. + .offset = 0x040000,
  28092. + .size = 0x140000,
  28093. + }, {
  28094. + .name = "rootfs",
  28095. + .offset = 0x180000,
  28096. + .size = 0x630000,
  28097. + }, {
  28098. + .name = "nvram",
  28099. + .offset = 0x7b0000,
  28100. + .size = 0x010000,
  28101. + .mask_flags = MTD_WRITEABLE,
  28102. + }, {
  28103. + .name = "factory",
  28104. + .offset = 0x7c0000,
  28105. + .size = 0x010000,
  28106. + .mask_flags = MTD_WRITEABLE,
  28107. + }, {
  28108. + .name = "language",
  28109. + .offset = 0x7d0000,
  28110. + .size = 0x020000,
  28111. + .mask_flags = MTD_WRITEABLE,
  28112. + }, {
  28113. + .name = "caldata",
  28114. + .offset = 0x7f0000,
  28115. + .size = 0x010000,
  28116. + .mask_flags = MTD_WRITEABLE,
  28117. + }, {
  28118. + .name = "firmware",
  28119. + .offset = 0x040000,
  28120. + .size = 0x770000,
  28121. + }
  28122. +};
  28123. +
  28124. +static struct flash_platform_data wrt400n_flash_data = {
  28125. + .parts = wrt400n_partitions,
  28126. + .nr_parts = ARRAY_SIZE(wrt400n_partitions),
  28127. +};
  28128. +
  28129. +static struct gpio_led wrt400n_leds_gpio[] __initdata = {
  28130. + {
  28131. + .name = "wrt400n:blue:wps",
  28132. + .gpio = WRT400N_GPIO_LED_WPS_BLUE,
  28133. + .active_low = 1,
  28134. + }, {
  28135. + .name = "wrt400n:amber:wps",
  28136. + .gpio = WRT400N_GPIO_LED_WPS_AMBER,
  28137. + .active_low = 1,
  28138. + }, {
  28139. + .name = "wrt400n:blue:wlan",
  28140. + .gpio = WRT400N_GPIO_LED_WLAN,
  28141. + .active_low = 1,
  28142. + }, {
  28143. + .name = "wrt400n:blue:power",
  28144. + .gpio = WRT400N_GPIO_LED_POWER,
  28145. + .active_low = 0,
  28146. + .default_trigger = "default-on",
  28147. + }
  28148. +};
  28149. +
  28150. +static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = {
  28151. + {
  28152. + .desc = "reset",
  28153. + .type = EV_KEY,
  28154. + .code = KEY_RESTART,
  28155. + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL,
  28156. + .gpio = WRT400N_GPIO_BTN_RESET,
  28157. + .active_low = 1,
  28158. + }, {
  28159. + .desc = "wlsec",
  28160. + .type = EV_KEY,
  28161. + .code = KEY_WPS_BUTTON,
  28162. + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL,
  28163. + .gpio = WRT400N_GPIO_BTN_WLSEC,
  28164. + .active_low = 1,
  28165. + }
  28166. +};
  28167. +
  28168. +static void __init wrt400n_setup(void)
  28169. +{
  28170. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  28171. + u8 *mac = art + WRT400N_MAC_ADDR_OFFSET;
  28172. +
  28173. + ath79_register_mdio(0, 0x0);
  28174. +
  28175. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
  28176. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  28177. + ath79_eth0_data.speed = SPEED_100;
  28178. + ath79_eth0_data.duplex = DUPLEX_FULL;
  28179. +
  28180. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2);
  28181. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  28182. + ath79_eth1_data.phy_mask = 0x10;
  28183. +
  28184. + ath79_register_eth(0);
  28185. + ath79_register_eth(1);
  28186. +
  28187. + ath79_register_m25p80(&wrt400n_flash_data);
  28188. +
  28189. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio),
  28190. + wrt400n_leds_gpio);
  28191. +
  28192. + ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL,
  28193. + ARRAY_SIZE(wrt400n_gpio_keys),
  28194. + wrt400n_gpio_keys);
  28195. +
  28196. + ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL,
  28197. + art + WRT400N_CALDATA1_OFFSET, NULL);
  28198. +}
  28199. +
  28200. +MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup);
  28201. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wzr-450hp2.c linux-4.1.43/arch/mips/ath79/mach-wzr-450hp2.c
  28202. --- linux-4.1.43.orig/arch/mips/ath79/mach-wzr-450hp2.c 1970-01-01 01:00:00.000000000 +0100
  28203. +++ linux-4.1.43/arch/mips/ath79/mach-wzr-450hp2.c 2017-08-06 20:02:15.000000000 +0200
  28204. @@ -0,0 +1,221 @@
  28205. +/*
  28206. + * Buffalo WZR-450HP2 board support
  28207. + *
  28208. + * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
  28209. + *
  28210. + * Based on the Qualcomm Atheros AP135/AP136 reference board support code
  28211. + * Copyright (c) 2012 Qualcomm Atheros
  28212. + *
  28213. + * Permission to use, copy, modify, and/or distribute this software for any
  28214. + * purpose with or without fee is hereby granted, provided that the above
  28215. + * copyright notice and this permission notice appear in all copies.
  28216. + *
  28217. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  28218. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  28219. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  28220. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  28221. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  28222. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  28223. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  28224. + *
  28225. + */
  28226. +
  28227. +#include <linux/phy.h>
  28228. +#include <linux/gpio.h>
  28229. +#include <linux/mtd/mtd.h>
  28230. +#include <linux/mtd/partitions.h>
  28231. +#include <linux/platform_device.h>
  28232. +#include <linux/ar8216_platform.h>
  28233. +
  28234. +#include <asm/mach-ath79/ar71xx_regs.h>
  28235. +
  28236. +#include "common.h"
  28237. +#include "dev-eth.h"
  28238. +#include "dev-gpio-buttons.h"
  28239. +#include "dev-leds-gpio.h"
  28240. +#include "dev-m25p80.h"
  28241. +#include "dev-spi.h"
  28242. +#include "dev-usb.h"
  28243. +#include "dev-wmac.h"
  28244. +#include "machtypes.h"
  28245. +
  28246. +#define WZR_450HP2_KEYS_POLL_INTERVAL 20 /* msecs */
  28247. +#define WZR_450HP2_KEYS_DEBOUNCE_INTERVAL (3 * WZR_450HP2_KEYS_POLL_INTERVAL)
  28248. +
  28249. +#define WZR_450HP2_WMAC_CALDATA_OFFSET 0x1000
  28250. +
  28251. +static struct mtd_partition wzrhpg450h_partitions[] = {
  28252. + {
  28253. + .name = "u-boot",
  28254. + .offset = 0,
  28255. + .size = 0x0040000,
  28256. + .mask_flags = MTD_WRITEABLE,
  28257. + }, {
  28258. + .name = "u-boot-env",
  28259. + .offset = 0x0040000,
  28260. + .size = 0x0010000,
  28261. + }, {
  28262. + .name = "ART",
  28263. + .offset = 0x0ff0000,
  28264. + .size = 0x0010000,
  28265. + .mask_flags = MTD_WRITEABLE,
  28266. + }, {
  28267. + .name = "firmware",
  28268. + .offset = 0x0050000,
  28269. + .size = 0x0f90000,
  28270. + }, {
  28271. + .name = "user_property",
  28272. + .offset = 0x0fe0000,
  28273. + .size = 0x0010000,
  28274. + }
  28275. +};
  28276. +
  28277. +static struct flash_platform_data wzr_450hp2_flash_data = {
  28278. + .parts = wzrhpg450h_partitions,
  28279. + .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions),
  28280. +};
  28281. +
  28282. +static struct gpio_led wzr_450hp2_leds_gpio[] __initdata = {
  28283. + {
  28284. + .name = "buffalo:green:wps",
  28285. + .gpio = 3,
  28286. + .active_low = 1,
  28287. + },
  28288. + {
  28289. + .name = "buffalo:green:system",
  28290. + .gpio = 20,
  28291. + .active_low = 1,
  28292. + },
  28293. + {
  28294. + .name = "buffalo:green:wlan",
  28295. + .gpio = 18,
  28296. + .active_low = 1,
  28297. + },
  28298. +};
  28299. +
  28300. +static struct gpio_keys_button wzr_450hp2_gpio_keys[] __initdata = {
  28301. + {
  28302. + .desc = "Reset button",
  28303. + .type = EV_KEY,
  28304. + .code = KEY_RESTART,
  28305. + .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL,
  28306. + .gpio = 17,
  28307. + .active_low = 1,
  28308. + },
  28309. + {
  28310. + .desc = "RFKILL button",
  28311. + .type = EV_KEY,
  28312. + .code = KEY_RFKILL,
  28313. + .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL,
  28314. + .gpio = 21,
  28315. + .active_low = 1,
  28316. + },
  28317. +};
  28318. +
  28319. +static const struct ar8327_led_info wzr_450hp2_leds_ar8327[] = {
  28320. + AR8327_LED_INFO(PHY0_0, HW, "buffalo:green:lan1"),
  28321. + AR8327_LED_INFO(PHY1_0, HW, "buffalo:green:lan2"),
  28322. + AR8327_LED_INFO(PHY2_0, HW, "buffalo:green:lan3"),
  28323. + AR8327_LED_INFO(PHY3_0, HW, "buffalo:green:lan4"),
  28324. + AR8327_LED_INFO(PHY4_0, HW, "buffalo:green:wan"),
  28325. +};
  28326. +
  28327. +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
  28328. +static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad0_cfg = {
  28329. + .mode = AR8327_PAD_MAC_SGMII,
  28330. + .sgmii_delay_en = true,
  28331. +};
  28332. +
  28333. +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
  28334. +static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad6_cfg = {
  28335. + .mode = AR8327_PAD_MAC_RGMII,
  28336. + .txclk_delay_en = true,
  28337. + .rxclk_delay_en = true,
  28338. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  28339. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  28340. +};
  28341. +
  28342. +static struct ar8327_led_cfg wzr_450hp2_ar8327_led_cfg = {
  28343. + .led_ctrl0 = 0xcc35cc35,
  28344. + .led_ctrl1 = 0xca35ca35,
  28345. + .led_ctrl2 = 0xc935c935,
  28346. + .led_ctrl3 = 0x03ffff00,
  28347. + .open_drain = true,
  28348. +};
  28349. +
  28350. +static struct ar8327_platform_data wzr_450hp2_ar8327_data = {
  28351. + .pad0_cfg = &wzr_450hp2_ar8327_pad0_cfg,
  28352. + .pad6_cfg = &wzr_450hp2_ar8327_pad6_cfg,
  28353. + .port0_cfg = {
  28354. + .force_link = 1,
  28355. + .speed = AR8327_PORT_SPEED_1000,
  28356. + .duplex = 1,
  28357. + .txpause = 1,
  28358. + .rxpause = 1,
  28359. + },
  28360. + .port6_cfg = {
  28361. + .force_link = 1,
  28362. + .speed = AR8327_PORT_SPEED_1000,
  28363. + .duplex = 1,
  28364. + .txpause = 1,
  28365. + .rxpause = 1,
  28366. + },
  28367. + .led_cfg = &wzr_450hp2_ar8327_led_cfg,
  28368. + .num_leds = ARRAY_SIZE(wzr_450hp2_leds_ar8327),
  28369. + .leds = wzr_450hp2_leds_ar8327,
  28370. +};
  28371. +
  28372. +static struct mdio_board_info wzr_450hp2_mdio0_info[] = {
  28373. + {
  28374. + .bus_id = "ag71xx-mdio.0",
  28375. + .phy_addr = 0,
  28376. + .platform_data = &wzr_450hp2_ar8327_data,
  28377. + },
  28378. +};
  28379. +
  28380. +static void __init wzr_450hp2_setup(void)
  28381. +{
  28382. + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  28383. + u8 *mac_wan = art;
  28384. + u8 *mac_lan = mac_wan + ETH_ALEN;
  28385. +
  28386. + ath79_register_m25p80(&wzr_450hp2_flash_data);
  28387. +
  28388. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzr_450hp2_leds_gpio),
  28389. + wzr_450hp2_leds_gpio);
  28390. + ath79_register_gpio_keys_polled(-1, WZR_450HP2_KEYS_POLL_INTERVAL,
  28391. + ARRAY_SIZE(wzr_450hp2_gpio_keys),
  28392. + wzr_450hp2_gpio_keys);
  28393. +
  28394. + ath79_register_wmac(art + WZR_450HP2_WMAC_CALDATA_OFFSET, mac_lan);
  28395. +
  28396. + mdiobus_register_board_info(wzr_450hp2_mdio0_info,
  28397. + ARRAY_SIZE(wzr_450hp2_mdio0_info));
  28398. + ath79_register_mdio(0, 0x0);
  28399. +
  28400. + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  28401. +
  28402. + /* GMAC0 is connected to the RMGII interface */
  28403. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  28404. + ath79_eth0_data.phy_mask = BIT(0);
  28405. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  28406. + ath79_eth0_pll_data.pll_1000 = 0x56000000;
  28407. +
  28408. + ath79_init_mac(ath79_eth0_data.mac_addr, mac_wan, 0);
  28409. + ath79_register_eth(0);
  28410. +
  28411. + /* GMAC1 is connected to the SGMII interface */
  28412. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
  28413. + ath79_eth1_data.speed = SPEED_1000;
  28414. + ath79_eth1_data.duplex = DUPLEX_FULL;
  28415. + ath79_eth1_pll_data.pll_1000 = 0x03000101;
  28416. +
  28417. + ath79_init_mac(ath79_eth1_data.mac_addr, mac_lan, 0);
  28418. + ath79_register_eth(1);
  28419. +
  28420. + ath79_register_usb();
  28421. +}
  28422. +
  28423. +MIPS_MACHINE(ATH79_MACH_WZR_450HP2, "WZR-450HP2",
  28424. + "Buffalo WZR-450HP2", wzr_450hp2_setup);
  28425. +
  28426. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-ag300h.c linux-4.1.43/arch/mips/ath79/mach-wzr-hp-ag300h.c
  28427. --- linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-ag300h.c 1970-01-01 01:00:00.000000000 +0100
  28428. +++ linux-4.1.43/arch/mips/ath79/mach-wzr-hp-ag300h.c 2017-08-06 20:02:15.000000000 +0200
  28429. @@ -0,0 +1,205 @@
  28430. +/*
  28431. + * Buffalo WZR-HP-AG300H board support
  28432. + *
  28433. + * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org>
  28434. + *
  28435. + * This program is free software; you can redistribute it and/or modify it
  28436. + * under the terms of the GNU General Public License version 2 as published
  28437. + * by the Free Software Foundation.
  28438. + */
  28439. +
  28440. +#include <linux/gpio.h>
  28441. +#include <linux/mtd/mtd.h>
  28442. +#include <linux/mtd/partitions.h>
  28443. +
  28444. +#include <asm/mach-ath79/ath79.h>
  28445. +
  28446. +#include "dev-eth.h"
  28447. +#include "dev-ap9x-pci.h"
  28448. +#include "dev-gpio-buttons.h"
  28449. +#include "dev-leds-gpio.h"
  28450. +#include "dev-m25p80.h"
  28451. +#include "dev-usb.h"
  28452. +#include "machtypes.h"
  28453. +
  28454. +#define WZRHPAG300H_MAC_OFFSET 0x20c
  28455. +#define WZRHPAG300H_KEYS_POLL_INTERVAL 20 /* msecs */
  28456. +#define WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPAG300H_KEYS_POLL_INTERVAL)
  28457. +
  28458. +static struct mtd_partition wzrhpag300h_flash_partitions[] = {
  28459. + {
  28460. + .name = "u-boot",
  28461. + .offset = 0,
  28462. + .size = 0x0040000,
  28463. + .mask_flags = MTD_WRITEABLE,
  28464. + }, {
  28465. + .name = "u-boot-env",
  28466. + .offset = 0x0040000,
  28467. + .size = 0x0010000,
  28468. + .mask_flags = MTD_WRITEABLE,
  28469. + }, {
  28470. + .name = "art",
  28471. + .offset = 0x0050000,
  28472. + .size = 0x0010000,
  28473. + .mask_flags = MTD_WRITEABLE,
  28474. + }, {
  28475. + .name = "firmware",
  28476. + .offset = 0x0060000,
  28477. + .size = 0x1f90000,
  28478. + }, {
  28479. + .name = "user_property",
  28480. + .offset = 0x1ff0000,
  28481. + .size = 0x0010000,
  28482. + .mask_flags = MTD_WRITEABLE,
  28483. + }
  28484. +};
  28485. +
  28486. +static struct flash_platform_data wzrhpag300h_flash_data = {
  28487. + .parts = wzrhpag300h_flash_partitions,
  28488. + .nr_parts = ARRAY_SIZE(wzrhpag300h_flash_partitions),
  28489. +};
  28490. +
  28491. +static struct gpio_led wzrhpag300h_leds_gpio[] __initdata = {
  28492. + {
  28493. + .name = "buffalo:red:diag",
  28494. + .gpio = 1,
  28495. + .active_low = 1,
  28496. + },
  28497. +};
  28498. +
  28499. +static struct gpio_led wzrhpag300h_wmac0_leds_gpio[] = {
  28500. + {
  28501. + .name = "buffalo:amber:band2g",
  28502. + .gpio = 1,
  28503. + .active_low = 1,
  28504. + },
  28505. + {
  28506. + .name = "buffalo:green:usb",
  28507. + .gpio = 3,
  28508. + .active_low = 1,
  28509. + },
  28510. + {
  28511. + .name = "buffalo:green:band2g",
  28512. + .gpio = 5,
  28513. + .active_low = 1,
  28514. + },
  28515. +};
  28516. +
  28517. +static struct gpio_led wzrhpag300h_wmac1_leds_gpio[] = {
  28518. + {
  28519. + .name = "buffalo:green:band5g",
  28520. + .gpio = 1,
  28521. + .active_low = 1,
  28522. + },
  28523. + {
  28524. + .name = "buffalo:green:router",
  28525. + .gpio = 3,
  28526. + .active_low = 1,
  28527. + },
  28528. + {
  28529. + .name = "buffalo:blue:movie_engine",
  28530. + .gpio = 4,
  28531. + .active_low = 1,
  28532. + },
  28533. + {
  28534. + .name = "buffalo:amber:band5g",
  28535. + .gpio = 5,
  28536. + .active_low = 1,
  28537. + },
  28538. +};
  28539. +
  28540. +static struct gpio_keys_button wzrhpag300h_gpio_keys[] __initdata = {
  28541. + {
  28542. + .desc = "reset",
  28543. + .type = EV_KEY,
  28544. + .code = KEY_RESTART,
  28545. + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
  28546. + .gpio = 11,
  28547. + .active_low = 1,
  28548. + }, {
  28549. + .desc = "usb",
  28550. + .type = EV_KEY,
  28551. + .code = BTN_2,
  28552. + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
  28553. + .gpio = 3,
  28554. + .active_low = 1,
  28555. + }, {
  28556. + .desc = "aoss",
  28557. + .type = EV_KEY,
  28558. + .code = KEY_WPS_BUTTON,
  28559. + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
  28560. + .gpio = 5,
  28561. + .active_low = 1,
  28562. + }, {
  28563. + .desc = "router_auto",
  28564. + .type = EV_SW,
  28565. + .code = BTN_6,
  28566. + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
  28567. + .gpio = 6,
  28568. + .active_low = 1,
  28569. + }, {
  28570. + .desc = "router_off",
  28571. + .type = EV_SW,
  28572. + .code = BTN_5,
  28573. + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
  28574. + .gpio = 7,
  28575. + .active_low = 1,
  28576. + }, {
  28577. + .desc = "movie_engine",
  28578. + .type = EV_SW,
  28579. + .code = BTN_7,
  28580. + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
  28581. + .gpio = 8,
  28582. + .active_low = 1,
  28583. + }
  28584. +};
  28585. +
  28586. +static void __init wzrhpag300h_setup(void)
  28587. +{
  28588. + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000);
  28589. + u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000);
  28590. + u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET;
  28591. + u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET;
  28592. +
  28593. + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
  28594. + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1);
  28595. +
  28596. + ath79_register_mdio(0, ~(BIT(0) | BIT(4)));
  28597. +
  28598. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  28599. + ath79_eth0_data.speed = SPEED_1000;
  28600. + ath79_eth0_data.duplex = DUPLEX_FULL;
  28601. + ath79_eth0_data.phy_mask = BIT(0);
  28602. +
  28603. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  28604. + ath79_eth1_data.phy_mask = BIT(4);
  28605. +
  28606. + ath79_register_eth(0);
  28607. + ath79_register_eth(1);
  28608. +
  28609. + gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  28610. + "USB power");
  28611. + ath79_register_usb();
  28612. +
  28613. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio),
  28614. + wzrhpag300h_leds_gpio);
  28615. +
  28616. + ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL,
  28617. + ARRAY_SIZE(wzrhpag300h_gpio_keys),
  28618. + wzrhpag300h_gpio_keys);
  28619. +
  28620. + ath79_register_m25p80_multi(&wzrhpag300h_flash_data);
  28621. +
  28622. + ap94_pci_init(eeprom1, mac1, eeprom2, mac2);
  28623. +
  28624. + ap9x_pci_setup_wmac_led_pin(0, 1);
  28625. + ap9x_pci_setup_wmac_led_pin(1, 5);
  28626. +
  28627. + ap9x_pci_setup_wmac_leds(0, wzrhpag300h_wmac0_leds_gpio,
  28628. + ARRAY_SIZE(wzrhpag300h_wmac0_leds_gpio));
  28629. + ap9x_pci_setup_wmac_leds(1, wzrhpag300h_wmac1_leds_gpio,
  28630. + ARRAY_SIZE(wzrhpag300h_wmac1_leds_gpio));
  28631. +}
  28632. +
  28633. +MIPS_MACHINE(ATH79_MACH_WZR_HP_AG300H, "WZR-HP-AG300H",
  28634. + "Buffalo WZR-HP-AG300H/WZR-600DHP", wzrhpag300h_setup);
  28635. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-g300nh.c linux-4.1.43/arch/mips/ath79/mach-wzr-hp-g300nh.c
  28636. --- linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-g300nh.c 1970-01-01 01:00:00.000000000 +0100
  28637. +++ linux-4.1.43/arch/mips/ath79/mach-wzr-hp-g300nh.c 2017-08-06 20:02:15.000000000 +0200
  28638. @@ -0,0 +1,279 @@
  28639. +/*
  28640. + * Buffalo WZR-HP-G300NH board support
  28641. + *
  28642. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  28643. + *
  28644. + * This program is free software; you can redistribute it and/or modify it
  28645. + * under the terms of the GNU General Public License version 2 as published
  28646. + * by the Free Software Foundation.
  28647. + */
  28648. +
  28649. +#include <linux/platform_device.h>
  28650. +#include <linux/mtd/mtd.h>
  28651. +#include <linux/mtd/partitions.h>
  28652. +#include <linux/mtd/physmap.h>
  28653. +#include <linux/nxp_74hc153.h>
  28654. +#include <linux/rtl8366.h>
  28655. +
  28656. +#include <asm/mach-ath79/ath79.h>
  28657. +
  28658. +#include "dev-eth.h"
  28659. +#include "dev-gpio-buttons.h"
  28660. +#include "dev-leds-gpio.h"
  28661. +#include "dev-usb.h"
  28662. +#include "dev-wmac.h"
  28663. +#include "machtypes.h"
  28664. +
  28665. +#define WZRHPG300NH_GPIO_LED_USB 0
  28666. +#define WZRHPG300NH_GPIO_LED_DIAG 1
  28667. +#define WZRHPG300NH_GPIO_LED_WIRELESS 6
  28668. +#define WZRHPG300NH_GPIO_LED_SECURITY 17
  28669. +#define WZRHPG300NH_GPIO_LED_ROUTER 18
  28670. +
  28671. +#define WZRHPG300NH_GPIO_RTL8366_SDA 19
  28672. +#define WZRHPG300NH_GPIO_RTL8366_SCK 20
  28673. +
  28674. +#define WZRHPG300NH_GPIO_74HC153_S0 9
  28675. +#define WZRHPG300NH_GPIO_74HC153_S1 11
  28676. +#define WZRHPG300NH_GPIO_74HC153_1Y 12
  28677. +#define WZRHPG300NH_GPIO_74HC153_2Y 14
  28678. +
  28679. +#define WZRHPG300NH_GPIO_EXP_BASE 32
  28680. +#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0)
  28681. +#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1)
  28682. +#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2)
  28683. +#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3)
  28684. +#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5)
  28685. +#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6)
  28686. +#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7)
  28687. +
  28688. +#define WZRHPG300NH_KEYS_POLL_INTERVAL 20 /* msecs */
  28689. +#define WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH_KEYS_POLL_INTERVAL)
  28690. +
  28691. +#define WZRHPG300NH_MAC_OFFSET 0x20c
  28692. +
  28693. +static struct mtd_partition wzrhpg300nh_flash_partitions[] = {
  28694. + {
  28695. + .name = "u-boot",
  28696. + .offset = 0,
  28697. + .size = 0x0040000,
  28698. + .mask_flags = MTD_WRITEABLE,
  28699. + }, {
  28700. + .name = "u-boot-env",
  28701. + .offset = 0x0040000,
  28702. + .size = 0x0020000,
  28703. + .mask_flags = MTD_WRITEABLE,
  28704. + }, {
  28705. + .name = "firmware",
  28706. + .offset = 0x0060000,
  28707. + .size = 0x1f60000,
  28708. + }, {
  28709. + .name = "user_property",
  28710. + .offset = 0x1fc0000,
  28711. + .size = 0x0020000,
  28712. + .mask_flags = MTD_WRITEABLE,
  28713. + }, {
  28714. + .name = "art",
  28715. + .offset = 0x1fe0000,
  28716. + .size = 0x0020000,
  28717. + .mask_flags = MTD_WRITEABLE,
  28718. + }
  28719. +};
  28720. +
  28721. +static struct physmap_flash_data wzrhpg300nh_flash_data = {
  28722. + .width = 2,
  28723. + .parts = wzrhpg300nh_flash_partitions,
  28724. + .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions),
  28725. +};
  28726. +
  28727. +#define WZRHPG300NH_FLASH_BASE 0x1e000000
  28728. +#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024)
  28729. +
  28730. +static struct resource wzrhpg300nh_flash_resources[] = {
  28731. + [0] = {
  28732. + .start = WZRHPG300NH_FLASH_BASE,
  28733. + .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1,
  28734. + .flags = IORESOURCE_MEM,
  28735. + },
  28736. +};
  28737. +
  28738. +static struct platform_device wzrhpg300nh_flash_device = {
  28739. + .name = "physmap-flash",
  28740. + .id = -1,
  28741. + .resource = wzrhpg300nh_flash_resources,
  28742. + .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources),
  28743. + .dev = {
  28744. + .platform_data = &wzrhpg300nh_flash_data,
  28745. + }
  28746. +};
  28747. +
  28748. +static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = {
  28749. + {
  28750. + .name = "buffalo:orange:security",
  28751. + .gpio = WZRHPG300NH_GPIO_LED_SECURITY,
  28752. + .active_low = 1,
  28753. + }, {
  28754. + .name = "buffalo:green:wireless",
  28755. + .gpio = WZRHPG300NH_GPIO_LED_WIRELESS,
  28756. + .active_low = 1,
  28757. + }, {
  28758. + .name = "buffalo:green:router",
  28759. + .gpio = WZRHPG300NH_GPIO_LED_ROUTER,
  28760. + .active_low = 1,
  28761. + }, {
  28762. + .name = "buffalo:red:diag",
  28763. + .gpio = WZRHPG300NH_GPIO_LED_DIAG,
  28764. + .active_low = 1,
  28765. + }, {
  28766. + .name = "buffalo:blue:usb",
  28767. + .gpio = WZRHPG300NH_GPIO_LED_USB,
  28768. + .active_low = 1,
  28769. + }
  28770. +};
  28771. +
  28772. +static struct gpio_keys_button wzrhpg300nh_gpio_keys[] __initdata = {
  28773. + {
  28774. + .desc = "reset",
  28775. + .type = EV_KEY,
  28776. + .code = KEY_RESTART,
  28777. + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
  28778. + .gpio = WZRHPG300NH_GPIO_BTN_RESET,
  28779. + .active_low = 1,
  28780. + }, {
  28781. + .desc = "aoss",
  28782. + .type = EV_KEY,
  28783. + .code = KEY_WPS_BUTTON,
  28784. + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
  28785. + .gpio = WZRHPG300NH_GPIO_BTN_AOSS,
  28786. + .active_low = 1,
  28787. + }, {
  28788. + .desc = "usb",
  28789. + .type = EV_KEY,
  28790. + .code = BTN_2,
  28791. + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
  28792. + .gpio = WZRHPG300NH_GPIO_BTN_USB,
  28793. + .active_low = 1,
  28794. + }, {
  28795. + .desc = "qos_on",
  28796. + .type = EV_KEY,
  28797. + .code = BTN_3,
  28798. + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
  28799. + .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON,
  28800. + .active_low = 0,
  28801. + }, {
  28802. + .desc = "qos_off",
  28803. + .type = EV_KEY,
  28804. + .code = BTN_4,
  28805. + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
  28806. + .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF,
  28807. + .active_low = 0,
  28808. + }, {
  28809. + .desc = "router_on",
  28810. + .type = EV_KEY,
  28811. + .code = BTN_5,
  28812. + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
  28813. + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON,
  28814. + .active_low = 0,
  28815. + }, {
  28816. + .desc = "router_auto",
  28817. + .type = EV_KEY,
  28818. + .code = BTN_6,
  28819. + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
  28820. + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO,
  28821. + .active_low = 0,
  28822. + }
  28823. +};
  28824. +
  28825. +static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = {
  28826. + .gpio_base = WZRHPG300NH_GPIO_EXP_BASE,
  28827. + .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0,
  28828. + .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1,
  28829. + .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y,
  28830. + .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y,
  28831. +};
  28832. +
  28833. +static struct platform_device wzrhpg300nh_74hc153_device = {
  28834. + .name = NXP_74HC153_DRIVER_NAME,
  28835. + .id = -1,
  28836. + .dev = {
  28837. + .platform_data = &wzrhpg300nh_74hc153_data,
  28838. + }
  28839. +};
  28840. +
  28841. +static struct rtl8366_platform_data wzrhpg300nh_rtl8366_data = {
  28842. + .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA,
  28843. + .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK,
  28844. +};
  28845. +
  28846. +static struct platform_device wzrhpg300nh_rtl8366s_device = {
  28847. + .name = RTL8366S_DRIVER_NAME,
  28848. + .id = -1,
  28849. + .dev = {
  28850. + .platform_data = &wzrhpg300nh_rtl8366_data,
  28851. + }
  28852. +};
  28853. +
  28854. +static struct platform_device wzrhpg300nh_rtl8366rb_device = {
  28855. + .name = RTL8366RB_DRIVER_NAME,
  28856. + .id = -1,
  28857. + .dev = {
  28858. + .platform_data = &wzrhpg300nh_rtl8366_data,
  28859. + }
  28860. +};
  28861. +
  28862. +static void __init wzrhpg300nh_setup(void)
  28863. +{
  28864. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
  28865. + u8 *mac = eeprom + WZRHPG300NH_MAC_OFFSET;
  28866. + bool hasrtl8366rb = false;
  28867. +
  28868. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  28869. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  28870. +
  28871. + if (rtl8366_smi_detect(&wzrhpg300nh_rtl8366_data) == RTL8366_TYPE_RB)
  28872. + hasrtl8366rb = true;
  28873. +
  28874. + if (hasrtl8366rb) {
  28875. + ath79_eth0_pll_data.pll_1000 = 0x1f000000;
  28876. + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev;
  28877. + ath79_eth1_pll_data.pll_1000 = 0x100;
  28878. + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev;
  28879. + } else {
  28880. + ath79_eth0_pll_data.pll_1000 = 0x1e000100;
  28881. + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev;
  28882. + ath79_eth1_pll_data.pll_1000 = 0x1e000100;
  28883. + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev;
  28884. + }
  28885. +
  28886. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  28887. + ath79_eth0_data.speed = SPEED_1000;
  28888. + ath79_eth0_data.duplex = DUPLEX_FULL;
  28889. +
  28890. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  28891. + ath79_eth1_data.phy_mask = 0x10;
  28892. +
  28893. + ath79_register_eth(0);
  28894. + ath79_register_eth(1);
  28895. +
  28896. + ath79_register_usb();
  28897. + ath79_register_wmac(eeprom, NULL);
  28898. +
  28899. + platform_device_register(&wzrhpg300nh_74hc153_device);
  28900. + platform_device_register(&wzrhpg300nh_flash_device);
  28901. +
  28902. + if (hasrtl8366rb)
  28903. + platform_device_register(&wzrhpg300nh_rtl8366rb_device);
  28904. + else
  28905. + platform_device_register(&wzrhpg300nh_rtl8366s_device);
  28906. +
  28907. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio),
  28908. + wzrhpg300nh_leds_gpio);
  28909. +
  28910. + ath79_register_gpio_keys_polled(-1, WZRHPG300NH_KEYS_POLL_INTERVAL,
  28911. + ARRAY_SIZE(wzrhpg300nh_gpio_keys),
  28912. + wzrhpg300nh_gpio_keys);
  28913. +
  28914. +}
  28915. +
  28916. +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH, "WZR-HP-G300NH",
  28917. + "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup);
  28918. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-g300nh2.c linux-4.1.43/arch/mips/ath79/mach-wzr-hp-g300nh2.c
  28919. --- linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-g300nh2.c 1970-01-01 01:00:00.000000000 +0100
  28920. +++ linux-4.1.43/arch/mips/ath79/mach-wzr-hp-g300nh2.c 2017-08-06 20:02:15.000000000 +0200
  28921. @@ -0,0 +1,170 @@
  28922. +/*
  28923. + * Buffalo WZR-HP-G300NH2 board support
  28924. + *
  28925. + * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org>
  28926. + * Copyright (C) 2011 Mark Deneen <mdeneen@gmail.com>
  28927. + *
  28928. + * This program is free software; you can redistribute it and/or modify it
  28929. + * under the terms of the GNU General Public License version 2 as published
  28930. + * by the Free Software Foundation.
  28931. + */
  28932. +
  28933. +#include <linux/gpio.h>
  28934. +#include <linux/mtd/mtd.h>
  28935. +#include <linux/mtd/partitions.h>
  28936. +
  28937. +#include <asm/mach-ath79/ath79.h>
  28938. +
  28939. +#include "dev-ap9x-pci.h"
  28940. +#include "dev-eth.h"
  28941. +#include "dev-gpio-buttons.h"
  28942. +#include "dev-leds-gpio.h"
  28943. +#include "dev-m25p80.h"
  28944. +#include "dev-usb.h"
  28945. +#include "machtypes.h"
  28946. +
  28947. +#define WZRHPG300NH2_MAC_OFFSET 0x20c
  28948. +#define WZRHPG300NH2_KEYS_POLL_INTERVAL 20 /* msecs */
  28949. +#define WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH2_KEYS_POLL_INTERVAL)
  28950. +
  28951. +static struct mtd_partition wzrhpg300nh2_flash_partitions[] = {
  28952. + {
  28953. + .name = "u-boot",
  28954. + .offset = 0,
  28955. + .size = 0x0040000,
  28956. + .mask_flags = MTD_WRITEABLE,
  28957. + }, {
  28958. + .name = "u-boot-env",
  28959. + .offset = 0x0040000,
  28960. + .size = 0x0010000,
  28961. + .mask_flags = MTD_WRITEABLE,
  28962. + }, {
  28963. + .name = "art",
  28964. + .offset = 0x0050000,
  28965. + .size = 0x0010000,
  28966. + .mask_flags = MTD_WRITEABLE,
  28967. + }, {
  28968. + .name = "firmware",
  28969. + .offset = 0x0060000,
  28970. + .size = 0x1f90000,
  28971. + }, {
  28972. + .name = "user_property",
  28973. + .offset = 0x1ff0000,
  28974. + .size = 0x0010000,
  28975. + .mask_flags = MTD_WRITEABLE,
  28976. + }
  28977. +};
  28978. +
  28979. +static struct flash_platform_data wzrhpg300nh2_flash_data = {
  28980. + .parts = wzrhpg300nh2_flash_partitions,
  28981. + .nr_parts = ARRAY_SIZE(wzrhpg300nh2_flash_partitions),
  28982. +};
  28983. +
  28984. +static struct gpio_led wzrhpg300nh2_leds_gpio[] __initdata = {
  28985. + {
  28986. + .name = "buffalo:red:diag",
  28987. + .gpio = 16,
  28988. + .active_low = 1,
  28989. + },
  28990. +};
  28991. +
  28992. +static struct gpio_led wzrhpg300nh2_wmac_leds_gpio[] = {
  28993. + {
  28994. + .name = "buffalo:blue:usb",
  28995. + .gpio = 4,
  28996. + .active_low = 1,
  28997. + },
  28998. + {
  28999. + .name = "buffalo:orange:security",
  29000. + .gpio = 6,
  29001. + .active_low = 1,
  29002. + },
  29003. + {
  29004. + .name = "buffalo:green:router",
  29005. + .gpio = 7,
  29006. + .active_low = 1,
  29007. + },
  29008. + {
  29009. + .name = "buffalo:blue:movie_engine_on",
  29010. + .gpio = 8,
  29011. + .active_low = 1,
  29012. + },
  29013. + {
  29014. + .name = "buffalo:blue:movie_engine_off",
  29015. + .gpio = 9,
  29016. + .active_low = 1,
  29017. + },
  29018. +};
  29019. +
  29020. +/* The AOSS button is wmac gpio 12 */
  29021. +static struct gpio_keys_button wzrhpg300nh2_gpio_keys[] __initdata = {
  29022. + {
  29023. + .desc = "reset",
  29024. + .type = EV_KEY,
  29025. + .code = KEY_RESTART,
  29026. + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
  29027. + .gpio = 1,
  29028. + .active_low = 1,
  29029. + }, {
  29030. + .desc = "usb",
  29031. + .type = EV_KEY,
  29032. + .code = BTN_2,
  29033. + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
  29034. + .gpio = 7,
  29035. + .active_low = 1,
  29036. + }, {
  29037. + .desc = "qos",
  29038. + .type = EV_KEY,
  29039. + .code = BTN_3,
  29040. + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
  29041. + .gpio = 11,
  29042. + .active_low = 0,
  29043. + }, {
  29044. + .desc = "router_on",
  29045. + .type = EV_KEY,
  29046. + .code = BTN_5,
  29047. + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
  29048. + .gpio = 8,
  29049. + .active_low = 0,
  29050. + },
  29051. +};
  29052. +
  29053. +static void __init wzrhpg300nh2_setup(void)
  29054. +{
  29055. +
  29056. + u8 *eeprom = (u8 *) KSEG1ADDR(0x1f051000);
  29057. + u8 *mac0 = eeprom + WZRHPG300NH2_MAC_OFFSET;
  29058. + /* There is an eth1 but it is not connected to the switch */
  29059. +
  29060. + ath79_register_m25p80_multi(&wzrhpg300nh2_flash_data);
  29061. +
  29062. + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
  29063. + ath79_register_mdio(0, ~(BIT(0)));
  29064. +
  29065. + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
  29066. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  29067. + ath79_eth0_data.speed = SPEED_1000;
  29068. + ath79_eth0_data.duplex = DUPLEX_FULL;
  29069. + ath79_eth0_data.phy_mask = BIT(0);
  29070. +
  29071. + ath79_register_eth(0);
  29072. +
  29073. + /* gpio13 is usb power. Turn it on. */
  29074. + gpio_request_one(13, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  29075. + "USB power");
  29076. + ath79_register_usb();
  29077. +
  29078. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh2_leds_gpio),
  29079. + wzrhpg300nh2_leds_gpio);
  29080. + ath79_register_gpio_keys_polled(-1, WZRHPG300NH2_KEYS_POLL_INTERVAL,
  29081. + ARRAY_SIZE(wzrhpg300nh2_gpio_keys),
  29082. + wzrhpg300nh2_gpio_keys);
  29083. + ap9x_pci_setup_wmac_led_pin(0, 5);
  29084. + ap9x_pci_setup_wmac_leds(0, wzrhpg300nh2_wmac_leds_gpio,
  29085. + ARRAY_SIZE(wzrhpg300nh2_wmac_leds_gpio));
  29086. +
  29087. + ap91_pci_init(eeprom, mac0);
  29088. +}
  29089. +
  29090. +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH2, "WZR-HP-G300NH2",
  29091. + "Buffalo WZR-HP-G300NH2", wzrhpg300nh2_setup);
  29092. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-g450h.c linux-4.1.43/arch/mips/ath79/mach-wzr-hp-g450h.c
  29093. --- linux-4.1.43.orig/arch/mips/ath79/mach-wzr-hp-g450h.c 1970-01-01 01:00:00.000000000 +0100
  29094. +++ linux-4.1.43/arch/mips/ath79/mach-wzr-hp-g450h.c 2017-08-06 20:02:15.000000000 +0200
  29095. @@ -0,0 +1,165 @@
  29096. +/*
  29097. + * Buffalo WZR-HP-G450G board support
  29098. + *
  29099. + * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org>
  29100. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  29101. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  29102. + *
  29103. + * This program is free software; you can redistribute it and/or modify it
  29104. + * under the terms of the GNU General Public License version 2 as published
  29105. + * by the Free Software Foundation.
  29106. + */
  29107. +
  29108. +#include <linux/gpio.h>
  29109. +#include <linux/mtd/mtd.h>
  29110. +#include <linux/mtd/partitions.h>
  29111. +#include <linux/ath9k_platform.h>
  29112. +
  29113. +#include <asm/mach-ath79/ath79.h>
  29114. +
  29115. +#include "dev-eth.h"
  29116. +#include "dev-m25p80.h"
  29117. +#include "dev-ap9x-pci.h"
  29118. +#include "dev-gpio-buttons.h"
  29119. +#include "dev-leds-gpio.h"
  29120. +#include "dev-usb.h"
  29121. +#include "machtypes.h"
  29122. +
  29123. +#define WZRHPG450H_KEYS_POLL_INTERVAL 20 /* msecs */
  29124. +#define WZRHPG450H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG450H_KEYS_POLL_INTERVAL)
  29125. +
  29126. +static struct mtd_partition wzrhpg450h_partitions[] = {
  29127. + {
  29128. + .name = "u-boot",
  29129. + .offset = 0,
  29130. + .size = 0x0040000,
  29131. + .mask_flags = MTD_WRITEABLE,
  29132. + }, {
  29133. + .name = "u-boot-env",
  29134. + .offset = 0x0040000,
  29135. + .size = 0x0010000,
  29136. + }, {
  29137. + .name = "ART",
  29138. + .offset = 0x0050000,
  29139. + .size = 0x0010000,
  29140. + .mask_flags = MTD_WRITEABLE,
  29141. + }, {
  29142. + .name = "firmware",
  29143. + .offset = 0x0060000,
  29144. + .size = 0x1f80000,
  29145. + }, {
  29146. + .name = "user_property",
  29147. + .offset = 0x1fe0000,
  29148. + .size = 0x0020000,
  29149. + }
  29150. +};
  29151. +
  29152. +static struct flash_platform_data wzrhpg450h_flash_data = {
  29153. + .parts = wzrhpg450h_partitions,
  29154. + .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions),
  29155. +};
  29156. +
  29157. +static struct gpio_led wzrhpg450h_leds_gpio[] __initdata = {
  29158. + {
  29159. + .name = "buffalo:red:diag",
  29160. + .gpio = 14,
  29161. + .active_low = 1,
  29162. + },
  29163. + {
  29164. + .name = "buffalo:orange:security",
  29165. + .gpio = 13,
  29166. + .active_low = 1,
  29167. + },
  29168. +};
  29169. +
  29170. +
  29171. +static struct gpio_led wzrhpg450h_wmac_leds_gpio[] = {
  29172. + {
  29173. + .name = "buffalo:blue:movie_engine",
  29174. + .gpio = 13,
  29175. + .active_low = 1,
  29176. + },
  29177. + {
  29178. + .name = "buffalo:green:router",
  29179. + .gpio = 14,
  29180. + .active_low = 1,
  29181. + },
  29182. +};
  29183. +
  29184. +static struct gpio_keys_button wzrhpg450h_gpio_keys[] __initdata = {
  29185. + {
  29186. + .desc = "reset",
  29187. + .type = EV_KEY,
  29188. + .code = KEY_RESTART,
  29189. + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
  29190. + .gpio = 6,
  29191. + .active_low = 1,
  29192. + }, {
  29193. + .desc = "usb",
  29194. + .type = EV_KEY,
  29195. + .code = BTN_2,
  29196. + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
  29197. + .gpio = 1,
  29198. + .active_low = 1,
  29199. + }, {
  29200. + .desc = "aoss",
  29201. + .type = EV_KEY,
  29202. + .code = KEY_WPS_BUTTON,
  29203. + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
  29204. + .gpio = 8,
  29205. + .active_low = 1,
  29206. + }, {
  29207. + .desc = "movie_engine",
  29208. + .type = EV_KEY,
  29209. + .code = BTN_6,
  29210. + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
  29211. + .gpio = 7,
  29212. + .active_low = 0,
  29213. + }, {
  29214. + .desc = "router_off",
  29215. + .type = EV_KEY,
  29216. + .code = BTN_5,
  29217. + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
  29218. + .gpio = 12,
  29219. + .active_low = 0,
  29220. + }
  29221. +};
  29222. +
  29223. +
  29224. +static void __init wzrhpg450h_init(void)
  29225. +{
  29226. + u8 *ee = (u8 *) KSEG1ADDR(0x1f051000);
  29227. + u8 *mac = (u8 *) ee + 2;
  29228. +
  29229. + ath79_register_m25p80_multi(&wzrhpg450h_flash_data);
  29230. +
  29231. + ath79_register_mdio(0, ~BIT(0));
  29232. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  29233. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  29234. + ath79_eth0_data.speed = SPEED_1000;
  29235. + ath79_eth0_data.duplex = DUPLEX_FULL;
  29236. + ath79_eth0_data.phy_mask = BIT(0);
  29237. +
  29238. + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg450h_leds_gpio),
  29239. + wzrhpg450h_leds_gpio);
  29240. +
  29241. + ath79_register_gpio_keys_polled(-1, WZRHPG450H_KEYS_POLL_INTERVAL,
  29242. + ARRAY_SIZE(wzrhpg450h_gpio_keys),
  29243. + wzrhpg450h_gpio_keys);
  29244. +
  29245. + ath79_register_eth(0);
  29246. +
  29247. + gpio_request_one(16, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
  29248. + "USB power");
  29249. + ath79_register_usb();
  29250. +
  29251. + ap91_pci_init(ee, NULL);
  29252. + ap9x_pci_get_wmac_data(0)->tx_gain_buffalo = true;
  29253. + ap9x_pci_get_wmac_data(1)->tx_gain_buffalo = true;
  29254. + ap9x_pci_setup_wmac_led_pin(0, 15);
  29255. + ap9x_pci_setup_wmac_leds(0, wzrhpg450h_wmac_leds_gpio,
  29256. + ARRAY_SIZE(wzrhpg450h_wmac_leds_gpio));
  29257. +}
  29258. +
  29259. +MIPS_MACHINE(ATH79_MACH_WZR_HP_G450H, "WZR-HP-G450H", "Buffalo WZR-HP-G450H",
  29260. + wzrhpg450h_init);
  29261. diff -Nur linux-4.1.43.orig/arch/mips/ath79/mach-zcn-1523h.c linux-4.1.43/arch/mips/ath79/mach-zcn-1523h.c
  29262. --- linux-4.1.43.orig/arch/mips/ath79/mach-zcn-1523h.c 1970-01-01 01:00:00.000000000 +0100
  29263. +++ linux-4.1.43/arch/mips/ath79/mach-zcn-1523h.c 2017-08-06 20:02:15.000000000 +0200
  29264. @@ -0,0 +1,154 @@
  29265. +/*
  29266. + * Zcomax ZCN-1523H-2-8/5-16 board support
  29267. + *
  29268. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  29269. + *
  29270. + * This program is free software; you can redistribute it and/or modify it
  29271. + * under the terms of the GNU General Public License version 2 as published
  29272. + * by the Free Software Foundation.
  29273. + */
  29274. +
  29275. +#include <asm/mach-ath79/ath79.h>
  29276. +#include <asm/mach-ath79/ar71xx_regs.h>
  29277. +
  29278. +#include "common.h"
  29279. +#include "dev-eth.h"
  29280. +#include "dev-m25p80.h"
  29281. +#include "dev-ap9x-pci.h"
  29282. +#include "dev-gpio-buttons.h"
  29283. +#include "dev-leds-gpio.h"
  29284. +#include "machtypes.h"
  29285. +
  29286. +#define ZCN_1523H_GPIO_BTN_RESET 0
  29287. +#define ZCN_1523H_GPIO_LED_INIT 11
  29288. +#define ZCN_1523H_GPIO_LED_LAN1 17
  29289. +
  29290. +#define ZCN_1523H_2_GPIO_LED_WEAK 13
  29291. +#define ZCN_1523H_2_GPIO_LED_MEDIUM 14
  29292. +#define ZCN_1523H_2_GPIO_LED_STRONG 15
  29293. +
  29294. +#define ZCN_1523H_5_GPIO_LAN2_POWER 1
  29295. +#define ZCN_1523H_5_GPIO_LED_LAN2 13
  29296. +#define ZCN_1523H_5_GPIO_LED_WEAK 14
  29297. +#define ZCN_1523H_5_GPIO_LED_MEDIUM 15
  29298. +#define ZCN_1523H_5_GPIO_LED_STRONG 16
  29299. +
  29300. +#define ZCN_1523H_KEYS_POLL_INTERVAL 20 /* msecs */
  29301. +#define ZCN_1523H_KEYS_DEBOUNCE_INTERVAL (3 * ZCN_1523H_KEYS_POLL_INTERVAL)
  29302. +
  29303. +static struct gpio_keys_button zcn_1523h_gpio_keys[] __initdata = {
  29304. + {
  29305. + .desc = "reset",
  29306. + .type = EV_KEY,
  29307. + .code = KEY_RESTART,
  29308. + .debounce_interval = ZCN_1523H_KEYS_DEBOUNCE_INTERVAL,
  29309. + .gpio = ZCN_1523H_GPIO_BTN_RESET,
  29310. + .active_low = 1,
  29311. + }
  29312. +};
  29313. +
  29314. +static struct gpio_led zcn_1523h_leds_gpio[] __initdata = {
  29315. + {
  29316. + .name = "zcn-1523h:amber:init",
  29317. + .gpio = ZCN_1523H_GPIO_LED_INIT,
  29318. + .active_low = 1,
  29319. + }, {
  29320. + .name = "zcn-1523h:green:lan1",
  29321. + .gpio = ZCN_1523H_GPIO_LED_LAN1,
  29322. + .active_low = 1,
  29323. + }
  29324. +};
  29325. +
  29326. +static struct gpio_led zcn_1523h_2_leds_gpio[] __initdata = {
  29327. + {
  29328. + .name = "zcn-1523h:red:weak",
  29329. + .gpio = ZCN_1523H_2_GPIO_LED_WEAK,
  29330. + .active_low = 1,
  29331. + }, {
  29332. + .name = "zcn-1523h:amber:medium",
  29333. + .gpio = ZCN_1523H_2_GPIO_LED_MEDIUM,
  29334. + .active_low = 1,
  29335. + }, {
  29336. + .name = "zcn-1523h:green:strong",
  29337. + .gpio = ZCN_1523H_2_GPIO_LED_STRONG,
  29338. + .active_low = 1,
  29339. + }
  29340. +};
  29341. +
  29342. +static struct gpio_led zcn_1523h_5_leds_gpio[] __initdata = {
  29343. + {
  29344. + .name = "zcn-1523h:red:weak",
  29345. + .gpio = ZCN_1523H_5_GPIO_LED_WEAK,
  29346. + .active_low = 1,
  29347. + }, {
  29348. + .name = "zcn-1523h:amber:medium",
  29349. + .gpio = ZCN_1523H_5_GPIO_LED_MEDIUM,
  29350. + .active_low = 1,
  29351. + }, {
  29352. + .name = "zcn-1523h:green:strong",
  29353. + .gpio = ZCN_1523H_5_GPIO_LED_STRONG,
  29354. + .active_low = 1,
  29355. + }, {
  29356. + .name = "zcn-1523h:green:lan2",
  29357. + .gpio = ZCN_1523H_5_GPIO_LED_LAN2,
  29358. + .active_low = 1,
  29359. + }
  29360. +};
  29361. +
  29362. +static void __init zcn_1523h_generic_setup(void)
  29363. +{
  29364. + u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004);
  29365. + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
  29366. +
  29367. + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
  29368. + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
  29369. + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
  29370. + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
  29371. + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
  29372. +
  29373. + ath79_register_m25p80(NULL);
  29374. +
  29375. + ath79_register_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio),
  29376. + zcn_1523h_leds_gpio);
  29377. +
  29378. + ath79_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL,
  29379. + ARRAY_SIZE(zcn_1523h_gpio_keys),
  29380. + zcn_1523h_gpio_keys);
  29381. +
  29382. + ap91_pci_init(ee, mac);
  29383. +
  29384. + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
  29385. + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
  29386. +
  29387. + ath79_register_mdio(0, 0x0);
  29388. +
  29389. + /* LAN1 port */
  29390. + ath79_register_eth(0);
  29391. +}
  29392. +
  29393. +static void __init zcn_1523h_2_setup(void)
  29394. +{
  29395. + zcn_1523h_generic_setup();
  29396. + ap9x_pci_setup_wmac_gpio(0, BIT(9), 0);
  29397. +
  29398. + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_2_leds_gpio),
  29399. + zcn_1523h_2_leds_gpio);
  29400. +}
  29401. +
  29402. +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_2, "ZCN-1523H-2", "Zcomax ZCN-1523H-2",
  29403. + zcn_1523h_2_setup);
  29404. +
  29405. +static void __init zcn_1523h_5_setup(void)
  29406. +{
  29407. + zcn_1523h_generic_setup();
  29408. + ap9x_pci_setup_wmac_gpio(0, BIT(8), 0);
  29409. +
  29410. + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_5_leds_gpio),
  29411. + zcn_1523h_5_leds_gpio);
  29412. +
  29413. + /* LAN2 port */
  29414. + ath79_register_eth(1);
  29415. +}
  29416. +
  29417. +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_5, "ZCN-1523H-5", "Zcomax ZCN-1523H-5",
  29418. + zcn_1523h_5_setup);
  29419. diff -Nur linux-4.1.43.orig/arch/mips/ath79/machtypes.h linux-4.1.43/arch/mips/ath79/machtypes.h
  29420. --- linux-4.1.43.orig/arch/mips/ath79/machtypes.h 2017-08-06 01:56:14.000000000 +0200
  29421. +++ linux-4.1.43/arch/mips/ath79/machtypes.h 2017-08-06 20:02:15.000000000 +0200
  29422. @@ -16,12 +16,224 @@
  29423. enum ath79_mach_type {
  29424. ATH79_MACH_GENERIC = 0,
  29425. + ATH79_MACH_ALFA_AP96, /* ALFA Network AP96 board */
  29426. + ATH79_MACH_ALFA_NX, /* ALFA Network N2/N5 board */
  29427. + ATH79_MACH_ALL0258N, /* Allnet ALL0258N */
  29428. + ATH79_MACH_ALL0305, /* Allnet ALL0305 */
  29429. + ATH79_MACH_ALL0315N, /* Allnet ALL0315N */
  29430. + ATH79_MACH_ANTMINER_S1, /* Antminer S1 */
  29431. + ATH79_MACH_ANTMINER_S3, /* Antminer S3 */
  29432. + ATH79_MACH_ARDUINO_YUN, /* Yun */
  29433. + ATH79_MACH_AP113, /* Atheros AP113 reference board */
  29434. ATH79_MACH_AP121, /* Atheros AP121 reference board */
  29435. + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
  29436. + ATH79_MACH_AP132, /* Atheros AP132 reference board */
  29437. + ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */
  29438. ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
  29439. + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */
  29440. + ATH79_MACH_AP143, /* Atheros AP143 reference board */
  29441. + ATH79_MACH_AP147_010, /* Atheros AP147-010 reference board */
  29442. + ATH79_MACH_AP152, /* Atheros AP152 reference board */
  29443. ATH79_MACH_AP81, /* Atheros AP81 reference board */
  29444. + ATH79_MACH_AP83, /* Atheros AP83 */
  29445. + ATH79_MACH_AP96, /* Atheros AP96 */
  29446. + ATH79_MACH_ARCHER_C5, /* TP-LINK Archer C5 board */
  29447. + ATH79_MACH_ARCHER_C7, /* TP-LINK Archer C7 board */
  29448. + ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */
  29449. + ATH79_MACH_BHU_BXU2000N2_A1, /* BHU BXU2000n-2 A1 */
  29450. + ATH79_MACH_BSB, /* Smart Electronics Black Swift board */
  29451. + ATH79_MACH_CAP4200AG, /* Senao CAP4200AG */
  29452. + ATH79_MACH_CARAMBOLA2, /* 8devices Carambola2 */
  29453. + ATH79_MACH_CF_E316N_V2, /* COMFAST CF-E316N v2 */
  29454. + ATH79_MACH_CPE510, /* TP-LINK CPE510 */
  29455. ATH79_MACH_DB120, /* Atheros DB120 reference board */
  29456. ATH79_MACH_PB44, /* Atheros PB44 reference board */
  29457. + ATH79_MACH_DGL_5500_A1, /* D-link DGL-5500 rev. A1 */
  29458. + ATH79_MACH_DHP_1565_A1, /* D-Link DHP-1565 rev. A1 */
  29459. + ATH79_MACH_DIR_505_A1, /* D-Link DIR-505 rev. A1 */
  29460. + ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */
  29461. + ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */
  29462. + ATH79_MACH_DIR_615_E1, /* D-Link DIR-615 rev. E1 */
  29463. + ATH79_MACH_DIR_615_E4, /* D-Link DIR-615 rev. E4 */
  29464. + ATH79_MACH_DIR_615_I1, /* D-Link DIR-615 rev. I1 */
  29465. + ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
  29466. + ATH79_MACH_DIR_825_C1, /* D-Link DIR-825 rev. C1 */
  29467. + ATH79_MACH_DIR_835_A1, /* D-Link DIR-835 rev. A1 */
  29468. + ATH79_MACH_DLAN_HOTSPOT, /* devolo dLAN Hotspot */
  29469. + ATH79_MACH_DLAN_PRO_500_WP, /* devolo dLAN pro 500 Wireless+ */
  29470. + ATH79_MACH_DLAN_PRO_1200_AC, /* devolo dLAN pro 1200+ WiFi ac*/
  29471. + ATH79_MACH_DRAGINO2, /* Dragino Version 2 */
  29472. + ATH79_MACH_ESR900, /* EnGenius ESR900 */
  29473. + ATH79_MACH_EW_DORIN, /* embedded wireless Dorin Platform */
  29474. + ATH79_MACH_EW_DORIN_ROUTER, /* embedded wireless Dorin Router Platform */
  29475. + ATH79_MACH_EAP300V2, /* EnGenius EAP300 v2 */
  29476. + ATH79_MACH_EAP7660D, /* Senao EAP7660D */
  29477. + ATH79_MACH_EL_M150, /* EasyLink EL-M150 */
  29478. + ATH79_MACH_EL_MINI, /* EasyLink EL-MINI */
  29479. + ATH79_MACH_ESR1750, /* EnGenius ESR1750 */
  29480. + ATH79_MACH_EPG5000, /* EnGenius EPG5000 */
  29481. + ATH79_MACH_F9K1115V2, /* Belkin AC1750DB */
  29482. + ATH79_MACH_GL_AR150, /* GL-AR150 support */
  29483. + ATH79_MACH_GL_AR300, /* GL-AR300 */
  29484. + ATH79_MACH_GL_DOMINO, /* Domino */
  29485. + ATH79_MACH_GL_INET, /* GL-CONNECT GL-INET */
  29486. + ATH79_MACH_GS_MINIBOX_V1, /* Gainstrong MiniBox V1.0 */
  29487. + ATH79_MACH_GS_OOLITE, /* GS OOLITE V1.0 */
  29488. + ATH79_MACH_HIWIFI_HC6361, /* HiWiFi HC6361 */
  29489. + ATH79_MACH_JA76PF, /* jjPlus JA76PF */
  29490. + ATH79_MACH_JA76PF2, /* jjPlus JA76PF2 */
  29491. + ATH79_MACH_JWAP003, /* jjPlus JWAP003 */
  29492. + ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */
  29493. + ATH79_MACH_MR12, /* Cisco Meraki MR12 */
  29494. + ATH79_MACH_MR16, /* Cisco Meraki MR16 */
  29495. + ATH79_MACH_MR1750, /* OpenMesh MR1750 */
  29496. + ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */
  29497. + ATH79_MACH_MR600, /* OpenMesh MR600 */
  29498. + ATH79_MACH_MR900, /* OpenMesh MR900 */
  29499. + ATH79_MACH_MR900v2, /* OpenMesh MR900v2 */
  29500. + ATH79_MACH_MYNET_N600, /* WD My Net N600 */
  29501. + ATH79_MACH_MYNET_N750, /* WD My Net N750 */
  29502. + ATH79_MACH_MYNET_REXT, /* WD My Net Wi-Fi Range Extender */
  29503. + ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */
  29504. + ATH79_MACH_MZK_W300NH, /* Planex MZK-W300NH */
  29505. + ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */
  29506. + ATH79_MACH_NBG6616, /* Zyxel NBG6616 */
  29507. + ATH79_MACH_NBG6716, /* Zyxel NBG6716 */
  29508. + ATH79_MACH_OM2P_HSv2, /* OpenMesh OM2P-HSv2 */
  29509. + ATH79_MACH_OM2P_HS, /* OpenMesh OM2P-HS */
  29510. + ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */
  29511. + ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */
  29512. + ATH79_MACH_OM2P, /* OpenMesh OM2P */
  29513. + ATH79_MACH_OM5P_AN, /* OpenMesh OM5P-AN */
  29514. + ATH79_MACH_OM5P, /* OpenMesh OM5P */
  29515. + ATH79_MACH_ONION_OMEGA, /* ONION OMEGA */
  29516. + ATH79_MACH_PB42, /* Atheros PB42 */
  29517. + ATH79_MACH_PB92, /* Atheros PB92 */
  29518. + ATH79_MACH_QIHOO_C301, /* Qihoo 360 C301 */
  29519. + ATH79_MACH_R6100, /* NETGEAR R6100 */
  29520. + ATH79_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */
  29521. + ATH79_MACH_RB_411U, /* MikroTik RouterBOARD 411U */
  29522. + ATH79_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */
  29523. + ATH79_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */
  29524. + ATH79_MACH_RB_435G, /* MikroTik RouterBOARD 435G */
  29525. + ATH79_MACH_RB_450G, /* MikroTik RouterBOARD 450G */
  29526. + ATH79_MACH_RB_450, /* MikroTik RouterBOARD 450 */
  29527. + ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
  29528. + ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */
  29529. + ATH79_MACH_RB_711GR100, /* Mikrotik RouterBOARD 911/912 boards */
  29530. + ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
  29531. + ATH79_MACH_RB_750G_R3, /* MikroTik RouterBOARD 750GL */
  29532. + ATH79_MACH_RB_751, /* MikroTik RouterBOARD 751 */
  29533. + ATH79_MACH_RB_751G, /* Mikrotik RouterBOARD 751G */
  29534. + ATH79_MACH_RB_922GS, /* Mikrotik RouterBOARD 911/922GS boards */
  29535. + ATH79_MACH_RB_951G, /* Mikrotik RouterBOARD 951G */
  29536. + ATH79_MACH_RB_951U, /* Mikrotik RouterBOARD 951Ui-2HnD */
  29537. + ATH79_MACH_RB_2011G, /* Mikrotik RouterBOARD 2011UAS-2HnD */
  29538. + ATH79_MACH_RB_2011L, /* Mikrotik RouterBOARD 2011L */
  29539. + ATH79_MACH_RB_2011US, /* Mikrotik RouterBOARD 2011UAS */
  29540. + ATH79_MACH_RB_2011R5, /* Mikrotik RouterBOARD 2011UiAS(-2Hnd) */
  29541. + ATH79_MACH_RB_SXTLITE2ND, /* Mikrotik RouterBOARD SXT Lite 2nD */
  29542. + ATH79_MACH_RB_SXTLITE5ND, /* Mikrotik RouterBOARD SXT Lite 5nD */
  29543. + ATH79_MACH_RW2458N, /* Redwave RW2458N */
  29544. + ATH79_MACH_SMART_300, /* NC-LINK SMART-300 */
  29545. + ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
  29546. + ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */
  29547. + ATH79_MACH_TEW_712BR, /* TRENDnet TEW-712BR */
  29548. + ATH79_MACH_TEW_732BR, /* TRENDnet TEW-732BR */
  29549. + ATH79_MACH_MC_MAC1200R, /* MERCURY MAC1200R*/
  29550. + ATH79_MACH_TL_MR10U, /* TP-LINK TL-MR10U */
  29551. + ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */
  29552. + ATH79_MACH_TL_MR13U, /* TP-LINK TL-MR13U */
  29553. + ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */
  29554. + ATH79_MACH_TL_MR3040, /* TP-LINK TL-MR3040 */
  29555. + ATH79_MACH_TL_MR3040_V2, /* TP-LINK TL-MR3040 v2 */
  29556. + ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */
  29557. + ATH79_MACH_TL_MR3220_V2, /* TP-LINK TL-MR3220 v2 */
  29558. + ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */
  29559. + ATH79_MACH_TL_MR3420_V2, /* TP-LINK TL-MR3420 v2 */
  29560. + ATH79_MACH_TL_WA701ND_V2, /* TP-LINK TL-WA701ND v2 */
  29561. + ATH79_MACH_TL_WA750RE, /* TP-LINK TL-WA750RE */
  29562. + ATH79_MACH_TL_WA7210N_V2, /* TP-LINK TL-WA7210N v2 */
  29563. + ATH79_MACH_TL_WA7510N_V1, /* TP-LINK TL-WA7510N v1*/
  29564. + ATH79_MACH_TL_WA850RE, /* TP-LINK TL-WA850RE */
  29565. + ATH79_MACH_TL_WA860RE, /* TP-LINK TL-WA860RE */
  29566. + ATH79_MACH_TL_WA801ND_V2, /* TP-LINK TL-WA801ND v2 */
  29567. + ATH79_MACH_TL_WA830RE_V2, /* TP-LINK TL-WA830RE v2 */
  29568. + ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */
  29569. + ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */
  29570. + ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */
  29571. + ATH79_MACH_TL_WDR3320_V2, /* TP-LINK TL-WDR3320 v2 */
  29572. + ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */
  29573. + ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */
  29574. + ATH79_MACH_TL_WDR6500_V2, /* TP-LINK TL-WDR6500 v2 */
  29575. + ATH79_MACH_TL_WDR4900_V2, /* TP-LINK TL-WDR4900 v2 */
  29576. + ATH79_MACH_TL_WR1041N_V2, /* TP-LINK TL-WR1041N v2 */
  29577. + ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1043ND */
  29578. + ATH79_MACH_TL_WR1043ND_V2, /* TP-LINK TL-WR1043ND v2 */
  29579. + ATH79_MACH_TL_WR2543N, /* TP-LINK TL-WR2543N/ND */
  29580. + ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */
  29581. + ATH79_MACH_TL_WR710N, /* TP-LINK TL-WR710N */
  29582. + ATH79_MACH_TL_WR720N_V3, /* TP-LINK TL-WR720N v3/v4 */
  29583. + ATH79_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */
  29584. + ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/
  29585. + ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */
  29586. + ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */
  29587. + ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */
  29588. + ATH79_MACH_TL_WR841N_V9, /* TP-LINK TL-WR841N/ND v9 */
  29589. + ATH79_MACH_TL_WR842N_V2, /* TP-LINK TL-WR842N/ND v2 */
  29590. + ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
  29591. + ATH79_MACH_TL_WR941ND_V5, /* TP-LINK TL-WR941ND v5 */
  29592. + ATH79_MACH_TL_WR941ND_V6, /* TP-LINK TL-WR941ND v6 */
  29593. + ATH79_MACH_TUBE2H, /* Alfa Network Tube2H */
  29594. + ATH79_MACH_UBNT_AIRGW, /* Ubiquiti AirGateway */
  29595. + ATH79_MACH_UBNT_AIRGWP, /* Ubiquiti AirGateway Pro */
  29596. + ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
  29597. + ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
  29598. + ATH79_MACH_UBNT_LOCO_M_XW, /* Ubiquiti Loco M XW */
  29599. + ATH79_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */
  29600. + ATH79_MACH_UBNT_LSX, /* Ubiquiti LSX */
  29601. + ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
  29602. + ATH79_MACH_UBNT_NANO_M_XW, /* Ubiquiti NanoStation M XW */
  29603. + ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
  29604. + ATH79_MACH_UBNT_ROCKET_M_XW, /* Ubiquiti Rocket M XW*/
  29605. + ATH79_MACH_UBNT_ROCKET_M_TI, /* Ubiquiti Rocket M TI*/
  29606. + ATH79_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */
  29607. + ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */
  29608. + ATH79_MACH_UBNT_UAP_PRO, /* Ubiquiti UniFi AP Pro */
  29609. + ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */
  29610. + ATH79_MACH_UBNT_UNIFI_OUTDOOR, /* Ubiquiti UnifiAP Outdoor */
  29611. + ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, /* Ubiquiti UnifiAP Outdoor+ */
  29612. ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
  29613. + ATH79_MACH_WEIO, /* WeIO board */
  29614. + ATH79_MACH_WHR_G301N, /* Buffalo WHR-G301N */
  29615. + ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */
  29616. + ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */
  29617. + ATH79_MACH_WLAE_AG300N, /* Buffalo WLAE-AG300N */
  29618. + ATH79_MACH_WLR8100, /* SITECOM WLR-8100 */
  29619. + ATH79_MACH_WNDAP360, /* NETGEAR WNDAP360 */
  29620. + ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
  29621. + ATH79_MACH_WNDR3700_V4, /* NETGEAR WNDR3700v4 */
  29622. + ATH79_MACH_WNDR4300, /* NETGEAR WNDR4300 */
  29623. + ATH79_MACH_WNR2000, /* NETGEAR WNR2000 */
  29624. + ATH79_MACH_WNR2000_V3, /* NETGEAR WNR2000 v3 */
  29625. + ATH79_MACH_WNR2000_V4, /* NETGEAR WNR2000 v4 */
  29626. + ATH79_MACH_WNR2200, /* NETGEAR WNR2200 */
  29627. + ATH79_MACH_WNR612_V2, /* NETGEAR WNR612 v2 */
  29628. + ATH79_MACH_WNR1000_V2, /* NETGEAR WNR1000 v2 */
  29629. + ATH79_MACH_WP543, /* Compex WP543 */
  29630. + ATH79_MACH_WPE72, /* Compex WPE72 */
  29631. + ATH79_MACH_WPJ344, /* Compex WPJ344 */
  29632. + ATH79_MACH_WPJ531, /* Compex WPJ531 */
  29633. + ATH79_MACH_WPJ558, /* Compex WPJ558 */
  29634. + ATH79_MACH_WRT160NL, /* Linksys WRT160NL */
  29635. + ATH79_MACH_WRT400N, /* Linksys WRT400N */
  29636. + ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */
  29637. + ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */
  29638. + ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */
  29639. + ATH79_MACH_WZR_HP_G450H, /* Buffalo WZR-HP-G450H */
  29640. + ATH79_MACH_WZR_450HP2, /* Buffalo WZR-450HP2 */
  29641. + ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */
  29642. + ATH79_MACH_ZCN_1523H_5, /* Zcomax ZCN-1523H-5-xx */
  29643. };
  29644. #endif /* _ATH79_MACHTYPE_H */
  29645. diff -Nur linux-4.1.43.orig/arch/mips/ath79/nvram.c linux-4.1.43/arch/mips/ath79/nvram.c
  29646. --- linux-4.1.43.orig/arch/mips/ath79/nvram.c 1970-01-01 01:00:00.000000000 +0100
  29647. +++ linux-4.1.43/arch/mips/ath79/nvram.c 2017-08-06 20:02:15.000000000 +0200
  29648. @@ -0,0 +1,80 @@
  29649. +/*
  29650. + * Atheros AR71xx minimal nvram support
  29651. + *
  29652. + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  29653. + *
  29654. + * This program is free software; you can redistribute it and/or modify it
  29655. + * under the terms of the GNU General Public License version 2 as published
  29656. + * by the Free Software Foundation.
  29657. + */
  29658. +
  29659. +#include <linux/kernel.h>
  29660. +#include <linux/vmalloc.h>
  29661. +#include <linux/errno.h>
  29662. +#include <linux/init.h>
  29663. +#include <linux/string.h>
  29664. +
  29665. +#include "nvram.h"
  29666. +
  29667. +char *ath79_nvram_find_var(const char *name, const char *buf, unsigned buf_len)
  29668. +{
  29669. + unsigned len = strlen(name);
  29670. + char *cur, *last;
  29671. +
  29672. + if (buf_len == 0 || len == 0)
  29673. + return NULL;
  29674. +
  29675. + if (buf_len < len)
  29676. + return NULL;
  29677. +
  29678. + if (len == 1)
  29679. + return memchr(buf, (int) *name, buf_len);
  29680. +
  29681. + last = (char *) buf + buf_len - len;
  29682. + for (cur = (char *) buf; cur <= last; cur++)
  29683. + if (cur[0] == name[0] && memcmp(cur, name, len) == 0)
  29684. + return cur + len;
  29685. +
  29686. + return NULL;
  29687. +}
  29688. +
  29689. +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len,
  29690. + const char *name, char *mac)
  29691. +{
  29692. + char *buf;
  29693. + char *mac_str;
  29694. + int ret;
  29695. + int t;
  29696. +
  29697. + buf = vmalloc(nvram_len);
  29698. + if (!buf)
  29699. + return -ENOMEM;
  29700. +
  29701. + memcpy(buf, nvram, nvram_len);
  29702. + buf[nvram_len - 1] = '\0';
  29703. +
  29704. + mac_str = ath79_nvram_find_var(name, buf, nvram_len);
  29705. + if (!mac_str) {
  29706. + ret = -EINVAL;
  29707. + goto free;
  29708. + }
  29709. +
  29710. + if (strlen(mac_str) == 19 && mac_str[0] == '"' && mac_str[18] == '"') {
  29711. + mac_str[18] = 0;
  29712. + mac_str++;
  29713. + }
  29714. +
  29715. + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
  29716. + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
  29717. +
  29718. + if (t != 6) {
  29719. + ret = -EINVAL;
  29720. + goto free;
  29721. + }
  29722. +
  29723. + ret = 0;
  29724. +
  29725. +free:
  29726. + vfree(buf);
  29727. + return ret;
  29728. +}
  29729. diff -Nur linux-4.1.43.orig/arch/mips/ath79/nvram.h linux-4.1.43/arch/mips/ath79/nvram.h
  29730. --- linux-4.1.43.orig/arch/mips/ath79/nvram.h 1970-01-01 01:00:00.000000000 +0100
  29731. +++ linux-4.1.43/arch/mips/ath79/nvram.h 2017-08-06 20:02:15.000000000 +0200
  29732. @@ -0,0 +1,19 @@
  29733. +/*
  29734. + * Atheros AR71xx minimal nvram support
  29735. + *
  29736. + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  29737. + *
  29738. + * This program is free software; you can redistribute it and/or modify it
  29739. + * under the terms of the GNU General Public License version 2 as published
  29740. + * by the Free Software Foundation.
  29741. + */
  29742. +
  29743. +#ifndef _ATH79_NVRAM_H
  29744. +#define _ATH79_NVRAM_H
  29745. +
  29746. +char *ath79_nvram_find_var(const char *name, const char *buf,
  29747. + unsigned buf_len);
  29748. +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len,
  29749. + const char *name, char *mac);
  29750. +
  29751. +#endif /* _ATH79_NVRAM_H */
  29752. diff -Nur linux-4.1.43.orig/arch/mips/ath79/pci-ath9k-fixup.c linux-4.1.43/arch/mips/ath79/pci-ath9k-fixup.c
  29753. --- linux-4.1.43.orig/arch/mips/ath79/pci-ath9k-fixup.c 1970-01-01 01:00:00.000000000 +0100
  29754. +++ linux-4.1.43/arch/mips/ath79/pci-ath9k-fixup.c 2017-08-06 20:02:15.000000000 +0200
  29755. @@ -0,0 +1,126 @@
  29756. +/*
  29757. + * Atheros AP94 reference board PCI initialization
  29758. + *
  29759. + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
  29760. + *
  29761. + * This program is free software; you can redistribute it and/or modify it
  29762. + * under the terms of the GNU General Public License version 2 as published
  29763. + * by the Free Software Foundation.
  29764. + */
  29765. +
  29766. +#include <linux/pci.h>
  29767. +#include <linux/delay.h>
  29768. +
  29769. +#include <asm/mach-ath79/ar71xx_regs.h>
  29770. +#include <asm/mach-ath79/ath79.h>
  29771. +
  29772. +struct ath9k_fixup {
  29773. + u16 *cal_data;
  29774. + unsigned slot;
  29775. +};
  29776. +
  29777. +static int ath9k_num_fixups;
  29778. +static struct ath9k_fixup ath9k_fixups[2];
  29779. +
  29780. +static void ath9k_pci_fixup(struct pci_dev *dev)
  29781. +{
  29782. + void __iomem *mem;
  29783. + u16 *cal_data = NULL;
  29784. + u16 cmd;
  29785. + u32 bar0;
  29786. + u32 val;
  29787. + unsigned i;
  29788. +
  29789. + for (i = 0; i < ath9k_num_fixups; i++) {
  29790. + if (ath9k_fixups[i].cal_data == NULL)
  29791. + continue;
  29792. +
  29793. + if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn))
  29794. + continue;
  29795. +
  29796. + cal_data = ath9k_fixups[i].cal_data;
  29797. + break;
  29798. + }
  29799. +
  29800. + if (cal_data == NULL)
  29801. + return;
  29802. +
  29803. + if (*cal_data != 0xa55a) {
  29804. + pr_err("pci %s: invalid calibration data\n", pci_name(dev));
  29805. + return;
  29806. + }
  29807. +
  29808. + pr_info("pci %s: fixup device configuration\n", pci_name(dev));
  29809. +
  29810. + mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
  29811. + if (!mem) {
  29812. + pr_err("pci %s: ioremap error\n", pci_name(dev));
  29813. + return;
  29814. + }
  29815. +
  29816. + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
  29817. +
  29818. + switch (ath79_soc) {
  29819. + case ATH79_SOC_AR7161:
  29820. + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
  29821. + AR71XX_PCI_MEM_BASE);
  29822. + break;
  29823. + case ATH79_SOC_AR7240:
  29824. + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
  29825. + break;
  29826. +
  29827. + case ATH79_SOC_AR7241:
  29828. + case ATH79_SOC_AR7242:
  29829. + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff);
  29830. + break;
  29831. + case ATH79_SOC_AR9344:
  29832. + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff);
  29833. + break;
  29834. +
  29835. + default:
  29836. + BUG();
  29837. + }
  29838. +
  29839. + pci_read_config_word(dev, PCI_COMMAND, &cmd);
  29840. + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  29841. + pci_write_config_word(dev, PCI_COMMAND, cmd);
  29842. +
  29843. + /* set pointer to first reg address */
  29844. + cal_data += 3;
  29845. + while (*cal_data != 0xffff) {
  29846. + u32 reg;
  29847. + reg = *cal_data++;
  29848. + val = *cal_data++;
  29849. + val |= (*cal_data++) << 16;
  29850. +
  29851. + __raw_writel(val, mem + reg);
  29852. + udelay(100);
  29853. + }
  29854. +
  29855. + pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
  29856. + dev->vendor = val & 0xffff;
  29857. + dev->device = (val >> 16) & 0xffff;
  29858. +
  29859. + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
  29860. + dev->revision = val & 0xff;
  29861. + dev->class = val >> 8; /* upper 3 bytes */
  29862. +
  29863. + pci_read_config_word(dev, PCI_COMMAND, &cmd);
  29864. + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  29865. + pci_write_config_word(dev, PCI_COMMAND, cmd);
  29866. +
  29867. + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
  29868. +
  29869. + iounmap(mem);
  29870. +}
  29871. +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);
  29872. +
  29873. +void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data)
  29874. +{
  29875. + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))
  29876. + return;
  29877. +
  29878. + ath9k_fixups[ath9k_num_fixups].slot = slot;
  29879. + ath9k_fixups[ath9k_num_fixups].cal_data = cal_data;
  29880. + ath9k_num_fixups++;
  29881. +}
  29882. diff -Nur linux-4.1.43.orig/arch/mips/ath79/pci-ath9k-fixup.h linux-4.1.43/arch/mips/ath79/pci-ath9k-fixup.h
  29883. --- linux-4.1.43.orig/arch/mips/ath79/pci-ath9k-fixup.h 1970-01-01 01:00:00.000000000 +0100
  29884. +++ linux-4.1.43/arch/mips/ath79/pci-ath9k-fixup.h 2017-08-06 20:02:15.000000000 +0200
  29885. @@ -0,0 +1,6 @@
  29886. +#ifndef _PCI_ATH9K_FIXUP
  29887. +#define _PCI_ATH9K_FIXUP
  29888. +
  29889. +void pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) __init;
  29890. +
  29891. +#endif /* _PCI_ATH9K_FIXUP */
  29892. diff -Nur linux-4.1.43.orig/arch/mips/ath79/pci.c linux-4.1.43/arch/mips/ath79/pci.c
  29893. --- linux-4.1.43.orig/arch/mips/ath79/pci.c 2017-08-06 01:56:14.000000000 +0200
  29894. +++ linux-4.1.43/arch/mips/ath79/pci.c 2017-08-06 20:02:15.000000000 +0200
  29895. @@ -13,6 +13,7 @@
  29896. */
  29897. #include <linux/init.h>
  29898. +#include <linux/export.h>
  29899. #include <linux/pci.h>
  29900. #include <linux/resource.h>
  29901. #include <linux/platform_device.h>
  29902. @@ -25,6 +26,9 @@
  29903. static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
  29904. static unsigned ath79_pci_nr_irqs __initdata;
  29905. +static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
  29906. +static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
  29907. +
  29908. static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
  29909. {
  29910. .slot = 17,
  29911. @@ -49,6 +53,15 @@
  29912. }
  29913. };
  29914. +static const struct ath79_pci_irq qca953x_pci_irq_map[] __initconst = {
  29915. + {
  29916. + .bus = 0,
  29917. + .slot = 0,
  29918. + .pin = 1,
  29919. + .irq = ATH79_PCI_IRQ(0),
  29920. + },
  29921. +};
  29922. +
  29923. static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
  29924. {
  29925. .bus = 0,
  29926. @@ -64,6 +77,21 @@
  29927. },
  29928. };
  29929. +static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
  29930. + {
  29931. + .bus = 0,
  29932. + .slot = 0,
  29933. + .pin = 1,
  29934. + .irq = ATH79_PCI_IRQ(0),
  29935. + },
  29936. + {
  29937. + .bus = 1,
  29938. + .slot = 0,
  29939. + .pin = 1,
  29940. + .irq = ATH79_PCI_IRQ(1),
  29941. + },
  29942. +};
  29943. +
  29944. int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
  29945. {
  29946. int irq = -1;
  29947. @@ -79,9 +107,15 @@
  29948. soc_is_ar9344()) {
  29949. ath79_pci_irq_map = ar724x_pci_irq_map;
  29950. ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
  29951. + } else if (soc_is_qca953x()) {
  29952. + ath79_pci_irq_map = qca953x_pci_irq_map;
  29953. + ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map);
  29954. } else if (soc_is_qca955x()) {
  29955. ath79_pci_irq_map = qca955x_pci_irq_map;
  29956. ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
  29957. + } else if (soc_is_qca9561()) {
  29958. + ath79_pci_irq_map = qca956x_pci_irq_map;
  29959. + ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
  29960. } else {
  29961. pr_crit("pci %s: invalid irq map\n",
  29962. pci_name((struct pci_dev *) dev));
  29963. @@ -212,12 +246,50 @@
  29964. return pdev;
  29965. }
  29966. +static inline bool ar71xx_is_pci_addr(unsigned long port)
  29967. +{
  29968. + unsigned long phys = CPHYSADDR(port);
  29969. +
  29970. + return (phys >= AR71XX_PCI_MEM_BASE &&
  29971. + phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
  29972. +}
  29973. +
  29974. +static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
  29975. +{
  29976. + return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
  29977. +}
  29978. +
  29979. +static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
  29980. +{
  29981. + return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
  29982. +}
  29983. +
  29984. +unsigned long ath79_pci_swizzle_b(unsigned long port)
  29985. +{
  29986. + if (__ath79_pci_swizzle_b)
  29987. + return __ath79_pci_swizzle_b(port);
  29988. +
  29989. + return port;
  29990. +}
  29991. +EXPORT_SYMBOL(ath79_pci_swizzle_b);
  29992. +
  29993. +unsigned long ath79_pci_swizzle_w(unsigned long port)
  29994. +{
  29995. + if (__ath79_pci_swizzle_w)
  29996. + return __ath79_pci_swizzle_w(port);
  29997. +
  29998. + return port;
  29999. +}
  30000. +EXPORT_SYMBOL(ath79_pci_swizzle_w);
  30001. +
  30002. int __init ath79_register_pci(void)
  30003. {
  30004. struct platform_device *pdev = NULL;
  30005. if (soc_is_ar71xx()) {
  30006. pdev = ath79_register_pci_ar71xx();
  30007. + __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
  30008. + __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
  30009. } else if (soc_is_ar724x()) {
  30010. pdev = ath79_register_pci_ar724x(-1,
  30011. AR724X_PCI_CFG_BASE,
  30012. @@ -243,6 +315,15 @@
  30013. AR724X_PCI_MEM_SIZE,
  30014. 0,
  30015. ATH79_IP2_IRQ(0));
  30016. + } else if (soc_is_qca9533()) {
  30017. + pdev = ath79_register_pci_ar724x(0,
  30018. + QCA953X_PCI_CFG_BASE0,
  30019. + QCA953X_PCI_CTRL_BASE0,
  30020. + QCA953X_PCI_CRP_BASE0,
  30021. + QCA953X_PCI_MEM_BASE0,
  30022. + QCA953X_PCI_MEM_SIZE,
  30023. + 0,
  30024. + ATH79_IP2_IRQ(0));
  30025. } else if (soc_is_qca9558()) {
  30026. pdev = ath79_register_pci_ar724x(0,
  30027. QCA955X_PCI_CFG_BASE0,
  30028. @@ -261,6 +342,15 @@
  30029. QCA955X_PCI_MEM_SIZE,
  30030. 1,
  30031. ATH79_IP3_IRQ(2));
  30032. + } else if (soc_is_qca9561()) {
  30033. + pdev = ath79_register_pci_ar724x(0,
  30034. + QCA956X_PCI_CFG_BASE1,
  30035. + QCA956X_PCI_CTRL_BASE1,
  30036. + QCA956X_PCI_CRP_BASE1,
  30037. + QCA956X_PCI_MEM_BASE1,
  30038. + QCA956X_PCI_MEM_SIZE,
  30039. + 1,
  30040. + ATH79_IP3_IRQ(2));
  30041. } else {
  30042. /* No PCI support */
  30043. return -ENODEV;
  30044. diff -Nur linux-4.1.43.orig/arch/mips/ath79/prom.c linux-4.1.43/arch/mips/ath79/prom.c
  30045. --- linux-4.1.43.orig/arch/mips/ath79/prom.c 2017-08-06 01:56:14.000000000 +0200
  30046. +++ linux-4.1.43/arch/mips/ath79/prom.c 2017-08-06 20:02:15.000000000 +0200
  30047. @@ -19,12 +19,114 @@
  30048. #include <asm/bootinfo.h>
  30049. #include <asm/addrspace.h>
  30050. #include <asm/fw/fw.h>
  30051. +#include <asm/fw/myloader/myloader.h>
  30052. #include "common.h"
  30053. +static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
  30054. +
  30055. +static void __init ath79_prom_append_cmdline(const char *name,
  30056. + const char *value)
  30057. +{
  30058. + snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
  30059. + " %s=%s", name, value);
  30060. + strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
  30061. +}
  30062. +
  30063. +#ifdef CONFIG_IMAGE_CMDLINE_HACK
  30064. +extern char __image_cmdline[];
  30065. +
  30066. +static int __init ath79_use_image_cmdline(void)
  30067. +{
  30068. + char *p = __image_cmdline;
  30069. + int replace = 0;
  30070. +
  30071. + if (*p == '-') {
  30072. + replace = 1;
  30073. + p++;
  30074. + }
  30075. +
  30076. + if (*p == '\0')
  30077. + return 0;
  30078. +
  30079. + if (replace) {
  30080. + strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
  30081. + } else {
  30082. + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
  30083. + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
  30084. + }
  30085. +
  30086. + /* Validate and setup environment pointer */
  30087. + if (fw_arg2 < CKSEG0)
  30088. + _fw_envp = NULL;
  30089. + else
  30090. + _fw_envp = (int *)fw_arg2;
  30091. +
  30092. + return 1;
  30093. +}
  30094. +#else
  30095. +static inline int ath79_use_image_cmdline(void) { return 0; }
  30096. +#endif
  30097. +
  30098. +static int __init ath79_prom_init_myloader(void)
  30099. +{
  30100. + struct myloader_info *mylo;
  30101. + char mac_buf[32];
  30102. + unsigned char *mac;
  30103. +
  30104. + mylo = myloader_get_info();
  30105. + if (!mylo)
  30106. + return 0;
  30107. +
  30108. + switch (mylo->did) {
  30109. + case DEVID_COMPEX_WP543:
  30110. + ath79_prom_append_cmdline("board", "WP543");
  30111. + break;
  30112. + case DEVID_COMPEX_WPE72:
  30113. + ath79_prom_append_cmdline("board", "WPE72");
  30114. + break;
  30115. + default:
  30116. + pr_warn("prom: unknown device id: %x\n", mylo->did);
  30117. + return 0;
  30118. + }
  30119. +
  30120. + mac = mylo->macs[0];
  30121. + snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
  30122. + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  30123. +
  30124. + ath79_prom_append_cmdline("ethaddr", mac_buf);
  30125. +
  30126. + ath79_use_image_cmdline();
  30127. +
  30128. + return 1;
  30129. +}
  30130. +
  30131. void __init prom_init(void)
  30132. {
  30133. - fw_init_cmdline();
  30134. + const char *env;
  30135. +
  30136. + if (ath79_prom_init_myloader())
  30137. + return;
  30138. +
  30139. + if (!ath79_use_image_cmdline())
  30140. + fw_init_cmdline();
  30141. +
  30142. + env = fw_getenv("ethaddr");
  30143. + if (env)
  30144. + ath79_prom_append_cmdline("ethaddr", env);
  30145. +
  30146. + env = fw_getenv("board");
  30147. + if (env) {
  30148. + /* Workaround for buggy bootloaders */
  30149. + if (strcmp(env, "RouterStation") == 0 ||
  30150. + strcmp(env, "Ubiquiti AR71xx-based board") == 0)
  30151. + env = "UBNT-RS";
  30152. +
  30153. + if (strcmp(env, "RouterStation PRO") == 0)
  30154. + env = "UBNT-RSPRO";
  30155. +
  30156. + ath79_prom_append_cmdline("board", env);
  30157. + }
  30158. #ifdef CONFIG_BLK_DEV_INITRD
  30159. /* Read the initrd address from the firmware environment */
  30160. @@ -34,6 +136,13 @@
  30161. initrd_end = initrd_start + fw_getenvl("initrd_size");
  30162. }
  30163. #endif
  30164. +
  30165. + if (strstr(arcs_cmdline, "board=750Gr3") ||
  30166. + strstr(arcs_cmdline, "board=951G") ||
  30167. + strstr(arcs_cmdline, "board=2011L") ||
  30168. + strstr(arcs_cmdline, "board=711Gr100") ||
  30169. + strstr(arcs_cmdline, "board=922gs"))
  30170. + ath79_prom_append_cmdline("console", "ttyS0,115200");
  30171. }
  30172. void __init prom_free_prom_memory(void)
  30173. diff -Nur linux-4.1.43.orig/arch/mips/ath79/routerboot.c linux-4.1.43/arch/mips/ath79/routerboot.c
  30174. --- linux-4.1.43.orig/arch/mips/ath79/routerboot.c 1970-01-01 01:00:00.000000000 +0100
  30175. +++ linux-4.1.43/arch/mips/ath79/routerboot.c 2017-08-06 20:02:15.000000000 +0200
  30176. @@ -0,0 +1,358 @@
  30177. +/*
  30178. + * RouterBoot helper routines
  30179. + *
  30180. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  30181. + *
  30182. + * This program is free software; you can redistribute it and/or modify it
  30183. + * under the terms of the GNU General Public License version 2 as published
  30184. + * by the Free Software Foundation.
  30185. + */
  30186. +
  30187. +#define pr_fmt(fmt) "rb: " fmt
  30188. +
  30189. +#include <linux/kernel.h>
  30190. +#include <linux/kobject.h>
  30191. +#include <linux/slab.h>
  30192. +#include <linux/errno.h>
  30193. +#include <linux/routerboot.h>
  30194. +#include <linux/rle.h>
  30195. +#include <linux/lzo.h>
  30196. +
  30197. +#include "routerboot.h"
  30198. +
  30199. +#define RB_BLOCK_SIZE 0x1000
  30200. +#define RB_ART_SIZE 0x10000
  30201. +#define RB_MAGIC_ERD 0x00455244 /* extended radio data */
  30202. +
  30203. +static struct rb_info rb_info;
  30204. +
  30205. +static u32 get_u32(void *buf)
  30206. +{
  30207. + u8 *p = buf;
  30208. +
  30209. + return ((u32) p[3] + ((u32) p[2] << 8) + ((u32) p[1] << 16) +
  30210. + ((u32) p[0] << 24));
  30211. +}
  30212. +
  30213. +static u16 get_u16(void *buf)
  30214. +{
  30215. + u8 *p = buf;
  30216. +
  30217. + return (u16) p[1] + ((u16) p[0] << 8);
  30218. +}
  30219. +
  30220. +__init int
  30221. +routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard)
  30222. +{
  30223. + u32 magic_ref = hard ? RB_MAGIC_HARD : RB_MAGIC_SOFT;
  30224. + u32 magic;
  30225. + u32 cur = *offset;
  30226. +
  30227. + while (cur < buflen) {
  30228. + magic = get_u32(buf + cur);
  30229. + if (magic == magic_ref) {
  30230. + *offset = cur;
  30231. + return 0;
  30232. + }
  30233. +
  30234. + cur += 0x1000;
  30235. + }
  30236. +
  30237. + return -ENOENT;
  30238. +}
  30239. +
  30240. +__init int
  30241. +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id,
  30242. + u8 **tag_data, u16 *tag_len)
  30243. +{
  30244. + uint32_t magic;
  30245. + bool align = false;
  30246. + int ret;
  30247. +
  30248. + if (buflen < 4)
  30249. + return -EINVAL;
  30250. +
  30251. + magic = get_u32(buf);
  30252. + switch (magic) {
  30253. + case RB_MAGIC_ERD:
  30254. + align = true;
  30255. + /* fall trough */
  30256. + case RB_MAGIC_HARD:
  30257. + /* skip magic value */
  30258. + buf += 4;
  30259. + buflen -= 4;
  30260. + break;
  30261. +
  30262. + case RB_MAGIC_SOFT:
  30263. + if (buflen < 8)
  30264. + return -EINVAL;
  30265. +
  30266. + /* skip magic and CRC value */
  30267. + buf += 8;
  30268. + buflen -= 8;
  30269. +
  30270. + break;
  30271. +
  30272. + default:
  30273. + return -EINVAL;
  30274. + }
  30275. +
  30276. + ret = -ENOENT;
  30277. + while (buflen > 2) {
  30278. + u16 id;
  30279. + u16 len;
  30280. +
  30281. + len = get_u16(buf);
  30282. + buf += 2;
  30283. + buflen -= 2;
  30284. +
  30285. + if (buflen < 2)
  30286. + break;
  30287. +
  30288. + id = get_u16(buf);
  30289. + buf += 2;
  30290. + buflen -= 2;
  30291. +
  30292. + if (id == RB_ID_TERMINATOR)
  30293. + break;
  30294. +
  30295. + if (buflen < len)
  30296. + break;
  30297. +
  30298. + if (id == tag_id) {
  30299. + if (tag_len)
  30300. + *tag_len = len;
  30301. + if (tag_data)
  30302. + *tag_data = buf;
  30303. + ret = 0;
  30304. + break;
  30305. + }
  30306. +
  30307. + if (align)
  30308. + len = (len + 3) / 4;
  30309. +
  30310. + buf += len;
  30311. + buflen -= len;
  30312. + }
  30313. +
  30314. + return ret;
  30315. +}
  30316. +
  30317. +static inline int
  30318. +rb_find_hard_cfg_tag(u16 tag_id, u8 **tag_data, u16 *tag_len)
  30319. +{
  30320. + if (!rb_info.hard_cfg_data ||
  30321. + !rb_info.hard_cfg_size)
  30322. + return -ENOENT;
  30323. +
  30324. + return routerboot_find_tag(rb_info.hard_cfg_data,
  30325. + rb_info.hard_cfg_size,
  30326. + tag_id, tag_data, tag_len);
  30327. +}
  30328. +
  30329. +__init const char *
  30330. +rb_get_board_name(void)
  30331. +{
  30332. + u16 tag_len;
  30333. + u8 *tag;
  30334. + int err;
  30335. +
  30336. + err = rb_find_hard_cfg_tag(RB_ID_BOARD_NAME, &tag, &tag_len);
  30337. + if (err)
  30338. + return NULL;
  30339. +
  30340. + return tag;
  30341. +}
  30342. +
  30343. +__init u32
  30344. +rb_get_hw_options(void)
  30345. +{
  30346. + u16 tag_len;
  30347. + u8 *tag;
  30348. + int err;
  30349. +
  30350. + err = rb_find_hard_cfg_tag(RB_ID_HW_OPTIONS, &tag, &tag_len);
  30351. + if (err)
  30352. + return 0;
  30353. +
  30354. + return get_u32(tag);
  30355. +}
  30356. +
  30357. +static void * __init
  30358. +__rb_get_wlan_data(u16 id)
  30359. +{
  30360. + u16 tag_len;
  30361. + u8 *tag;
  30362. + void *buf;
  30363. + int err;
  30364. + u32 magic;
  30365. + size_t src_done;
  30366. + size_t dst_done;
  30367. +
  30368. + err = rb_find_hard_cfg_tag(RB_ID_WLAN_DATA, &tag, &tag_len);
  30369. + if (err) {
  30370. + pr_err("no calibration data found\n");
  30371. + goto err;
  30372. + }
  30373. +
  30374. + buf = kmalloc(RB_ART_SIZE, GFP_KERNEL);
  30375. + if (buf == NULL) {
  30376. + pr_err("no memory for calibration data\n");
  30377. + goto err;
  30378. + }
  30379. +
  30380. + magic = get_u32(tag);
  30381. + if (magic == RB_MAGIC_ERD) {
  30382. + u8 *erd_data;
  30383. + u16 erd_len;
  30384. +
  30385. + if (id == 0)
  30386. + goto err_free;
  30387. +
  30388. + err = routerboot_find_tag(tag, tag_len, id,
  30389. + &erd_data, &erd_len);
  30390. + if (err) {
  30391. + pr_err("no ERD data found for id %u\n", id);
  30392. + goto err_free;
  30393. + }
  30394. +
  30395. + dst_done = RB_ART_SIZE;
  30396. + err = lzo1x_decompress_safe(erd_data, erd_len, buf, &dst_done);
  30397. + if (err) {
  30398. + pr_err("unable to decompress calibration data %d\n",
  30399. + err);
  30400. + goto err_free;
  30401. + }
  30402. + } else {
  30403. + if (id != 0)
  30404. + goto err_free;
  30405. +
  30406. + err = rle_decode((char *) tag, tag_len, buf, RB_ART_SIZE,
  30407. + &src_done, &dst_done);
  30408. + if (err) {
  30409. + pr_err("unable to decode calibration data\n");
  30410. + goto err_free;
  30411. + }
  30412. + }
  30413. +
  30414. + return buf;
  30415. +
  30416. +err_free:
  30417. + kfree(buf);
  30418. +err:
  30419. + return NULL;
  30420. +}
  30421. +
  30422. +__init void *
  30423. +rb_get_wlan_data(void)
  30424. +{
  30425. + return __rb_get_wlan_data(0);
  30426. +}
  30427. +
  30428. +__init void *
  30429. +rb_get_ext_wlan_data(u16 id)
  30430. +{
  30431. + return __rb_get_wlan_data(id);
  30432. +}
  30433. +
  30434. +__init const struct rb_info *
  30435. +rb_init_info(void *data, unsigned int size)
  30436. +{
  30437. + unsigned int offset;
  30438. +
  30439. + if (size == 0 || (size % RB_BLOCK_SIZE) != 0)
  30440. + return NULL;
  30441. +
  30442. + for (offset = 0; offset < size; offset += RB_BLOCK_SIZE) {
  30443. + u32 magic;
  30444. +
  30445. + magic = get_u32(data + offset);
  30446. + switch (magic) {
  30447. + case RB_MAGIC_HARD:
  30448. + rb_info.hard_cfg_offs = offset;
  30449. + break;
  30450. +
  30451. + case RB_MAGIC_SOFT:
  30452. + rb_info.soft_cfg_offs = offset;
  30453. + break;
  30454. + }
  30455. + }
  30456. +
  30457. + if (!rb_info.hard_cfg_offs) {
  30458. + pr_err("could not find a valid RouterBOOT hard config\n");
  30459. + return NULL;
  30460. + }
  30461. +
  30462. + if (!rb_info.soft_cfg_offs) {
  30463. + pr_err("could not find a valid RouterBOOT soft config\n");
  30464. + return NULL;
  30465. + }
  30466. +
  30467. + rb_info.hard_cfg_size = RB_BLOCK_SIZE;
  30468. + rb_info.hard_cfg_data = kmemdup(data + rb_info.hard_cfg_offs,
  30469. + RB_BLOCK_SIZE, GFP_KERNEL);
  30470. + if (!rb_info.hard_cfg_data)
  30471. + return NULL;
  30472. +
  30473. + rb_info.board_name = rb_get_board_name();
  30474. + rb_info.hw_options = rb_get_hw_options();
  30475. +
  30476. + return &rb_info;
  30477. +}
  30478. +
  30479. +static char *rb_ext_wlan_data;
  30480. +
  30481. +static ssize_t
  30482. +rb_ext_wlan_data_read(struct file *filp, struct kobject *kobj,
  30483. + struct bin_attribute *attr, char *buf,
  30484. + loff_t off, size_t count)
  30485. +{
  30486. + if (off + count > attr->size)
  30487. + return -EFBIG;
  30488. +
  30489. + memcpy(buf, &rb_ext_wlan_data[off], count);
  30490. +
  30491. + return count;
  30492. +}
  30493. +
  30494. +static const struct bin_attribute rb_ext_wlan_data_attr = {
  30495. + .attr = {
  30496. + .name = "ext_wlan_data",
  30497. + .mode = S_IRUSR | S_IWUSR,
  30498. + },
  30499. + .read = rb_ext_wlan_data_read,
  30500. + .size = RB_ART_SIZE,
  30501. +};
  30502. +
  30503. +static int __init rb_sysfs_init(void)
  30504. +{
  30505. + struct kobject *rb_kobj;
  30506. + int ret;
  30507. +
  30508. + rb_ext_wlan_data = rb_get_ext_wlan_data(1);
  30509. + if (rb_ext_wlan_data == NULL)
  30510. + return -ENOENT;
  30511. +
  30512. + rb_kobj = kobject_create_and_add("routerboot", firmware_kobj);
  30513. + if (rb_kobj == NULL) {
  30514. + ret = -ENOMEM;
  30515. + pr_err("unable to create sysfs entry\n");
  30516. + goto err_free_wlan_data;
  30517. + }
  30518. +
  30519. + ret = sysfs_create_bin_file(rb_kobj, &rb_ext_wlan_data_attr);
  30520. + if (ret) {
  30521. + pr_err("unable to create sysfs file, %d\n", ret);
  30522. + goto err_put_kobj;
  30523. + }
  30524. +
  30525. + return 0;
  30526. +
  30527. +err_put_kobj:
  30528. + kobject_put(rb_kobj);
  30529. +err_free_wlan_data:
  30530. + kfree(rb_ext_wlan_data);
  30531. + return ret;
  30532. +}
  30533. +
  30534. +late_initcall(rb_sysfs_init);
  30535. diff -Nur linux-4.1.43.orig/arch/mips/ath79/routerboot.h linux-4.1.43/arch/mips/ath79/routerboot.h
  30536. --- linux-4.1.43.orig/arch/mips/ath79/routerboot.h 1970-01-01 01:00:00.000000000 +0100
  30537. +++ linux-4.1.43/arch/mips/ath79/routerboot.h 2017-08-06 20:02:15.000000000 +0200
  30538. @@ -0,0 +1,63 @@
  30539. +/*
  30540. + * RouterBoot definitions
  30541. + *
  30542. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  30543. + *
  30544. + * This program is free software; you can redistribute it and/or modify it
  30545. + * under the terms of the GNU General Public License version 2 as published
  30546. + * by the Free Software Foundation.
  30547. + */
  30548. +
  30549. +#ifndef _ATH79_ROUTERBOOT_H_
  30550. +#define _ATH79_ROUTERBOOT_H_
  30551. +
  30552. +struct rb_info {
  30553. + unsigned int hard_cfg_offs;
  30554. + unsigned int hard_cfg_size;
  30555. + void *hard_cfg_data;
  30556. + unsigned int soft_cfg_offs;
  30557. +
  30558. + const char *board_name;
  30559. + u32 hw_options;
  30560. +};
  30561. +
  30562. +#ifdef CONFIG_ATH79_ROUTERBOOT
  30563. +const struct rb_info *rb_init_info(void *data, unsigned int size);
  30564. +void *rb_get_wlan_data(void);
  30565. +void *rb_get_ext_wlan_data(u16 id);
  30566. +
  30567. +int routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id,
  30568. + u8 **tag_data, u16 *tag_len);
  30569. +int routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard);
  30570. +#else
  30571. +static inline const struct rb_info *
  30572. +rb_init_info(void *data, unsigned int size)
  30573. +{
  30574. + return NULL;
  30575. +}
  30576. +
  30577. +static inline void *rb_get_wlan_data(void)
  30578. +{
  30579. + return NULL;
  30580. +}
  30581. +
  30582. +static inline void *rb_get_wlan_data(u16 id)
  30583. +{
  30584. + return NULL;
  30585. +}
  30586. +
  30587. +static inline int
  30588. +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id,
  30589. + u8 **tag_data, u16 *tag_len)
  30590. +{
  30591. + return -ENOENT;
  30592. +}
  30593. +
  30594. +static inline int
  30595. +routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard)
  30596. +{
  30597. + return -ENOENT;
  30598. +}
  30599. +#endif
  30600. +
  30601. +#endif /* _ATH79_ROUTERBOOT_H_ */
  30602. diff -Nur linux-4.1.43.orig/arch/mips/ath79/setup.c linux-4.1.43/arch/mips/ath79/setup.c
  30603. --- linux-4.1.43.orig/arch/mips/ath79/setup.c 2017-08-06 01:56:14.000000000 +0200
  30604. +++ linux-4.1.43/arch/mips/ath79/setup.c 2017-08-06 20:02:15.000000000 +0200
  30605. @@ -40,6 +40,7 @@
  30606. static void ath79_restart(char *command)
  30607. {
  30608. + local_irq_disable();
  30609. ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
  30610. for (;;)
  30611. if (cpu_wait)
  30612. @@ -59,6 +60,7 @@
  30613. u32 major;
  30614. u32 minor;
  30615. u32 rev = 0;
  30616. + u32 ver = 1;
  30617. id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
  30618. major = id & REV_ID_MAJOR_MASK;
  30619. @@ -151,6 +153,17 @@
  30620. rev = id & AR934X_REV_ID_REVISION_MASK;
  30621. break;
  30622. + case REV_ID_MAJOR_QCA9533_V2:
  30623. + ver = 2;
  30624. + ath79_soc_rev = 2;
  30625. + /* drop through */
  30626. +
  30627. + case REV_ID_MAJOR_QCA9533:
  30628. + ath79_soc = ATH79_SOC_QCA9533;
  30629. + chip = "9533";
  30630. + rev = id & QCA953X_REV_ID_REVISION_MASK;
  30631. + break;
  30632. +
  30633. case REV_ID_MAJOR_QCA9556:
  30634. ath79_soc = ATH79_SOC_QCA9556;
  30635. chip = "9556";
  30636. @@ -163,14 +176,30 @@
  30637. rev = id & QCA955X_REV_ID_REVISION_MASK;
  30638. break;
  30639. + case REV_ID_MAJOR_TP9343:
  30640. + ath79_soc = ATH79_SOC_TP9343;
  30641. + chip = "9343";
  30642. + rev = id & QCA956X_REV_ID_REVISION_MASK;
  30643. + break;
  30644. +
  30645. + case REV_ID_MAJOR_QCA9561:
  30646. + ath79_soc = ATH79_SOC_QCA9561;
  30647. + chip = "9561";
  30648. + rev = id & QCA956X_REV_ID_REVISION_MASK;
  30649. + break;
  30650. +
  30651. default:
  30652. panic("ath79: unknown SoC, id:0x%08x", id);
  30653. }
  30654. - ath79_soc_rev = rev;
  30655. + if (ver == 1)
  30656. + ath79_soc_rev = rev;
  30657. - if (soc_is_qca955x())
  30658. - sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
  30659. + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
  30660. + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
  30661. + chip, ver, rev);
  30662. + else if (soc_is_tp9343())
  30663. + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
  30664. chip, rev);
  30665. else
  30666. sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
  30667. @@ -235,6 +264,8 @@
  30668. mips_hpt_frequency = cpu_clk_rate / 2;
  30669. }
  30670. +__setup("board=", mips_machtype_setup);
  30671. +
  30672. static int __init ath79_setup(void)
  30673. {
  30674. ath79_gpio_init();
  30675. diff -Nur linux-4.1.43.orig/arch/mips/fw/lib/cmdline.c linux-4.1.43/arch/mips/fw/lib/cmdline.c
  30676. --- linux-4.1.43.orig/arch/mips/fw/lib/cmdline.c 2017-08-06 01:56:14.000000000 +0200
  30677. +++ linux-4.1.43/arch/mips/fw/lib/cmdline.c 2017-08-06 20:02:15.000000000 +0200
  30678. @@ -35,6 +35,7 @@
  30679. else
  30680. _fw_envp = (int *)fw_arg2;
  30681. + arcs_cmdline[0] = '\0';
  30682. for (i = 1; i < fw_argc; i++) {
  30683. strlcat(arcs_cmdline, fw_argv(i), COMMAND_LINE_SIZE);
  30684. if (i < (fw_argc - 1))
  30685. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/checksum.h linux-4.1.43/arch/mips/include/asm/checksum.h
  30686. --- linux-4.1.43.orig/arch/mips/include/asm/checksum.h 2017-08-06 01:56:14.000000000 +0200
  30687. +++ linux-4.1.43/arch/mips/include/asm/checksum.h 2017-08-06 20:02:15.000000000 +0200
  30688. @@ -134,26 +134,30 @@
  30689. const unsigned int *stop = word + ihl;
  30690. unsigned int csum;
  30691. int carry;
  30692. + unsigned int w;
  30693. - csum = word[0];
  30694. - csum += word[1];
  30695. - carry = (csum < word[1]);
  30696. + csum = net_hdr_word(word++);
  30697. +
  30698. + w = net_hdr_word(word++);
  30699. + csum += w;
  30700. + carry = (csum < w);
  30701. csum += carry;
  30702. - csum += word[2];
  30703. - carry = (csum < word[2]);
  30704. + w = net_hdr_word(word++);
  30705. + csum += w;
  30706. + carry = (csum < w);
  30707. csum += carry;
  30708. - csum += word[3];
  30709. - carry = (csum < word[3]);
  30710. + w = net_hdr_word(word++);
  30711. + csum += w;
  30712. + carry = (csum < w);
  30713. csum += carry;
  30714. - word += 4;
  30715. do {
  30716. - csum += *word;
  30717. - carry = (csum < *word);
  30718. + w = net_hdr_word(word++);
  30719. + csum += w;
  30720. + carry = (csum < w);
  30721. csum += carry;
  30722. - word++;
  30723. } while (word != stop);
  30724. return csum_fold(csum);
  30725. @@ -214,73 +218,6 @@
  30726. return csum_fold(csum_partial(buff, len, 0));
  30727. }
  30728. -#define _HAVE_ARCH_IPV6_CSUM
  30729. -static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
  30730. - const struct in6_addr *daddr,
  30731. - __u32 len, unsigned short proto,
  30732. - __wsum sum)
  30733. -{
  30734. - __wsum tmp;
  30735. -
  30736. - __asm__(
  30737. - " .set push # csum_ipv6_magic\n"
  30738. - " .set noreorder \n"
  30739. - " .set noat \n"
  30740. - " addu %0, %5 # proto (long in network byte order)\n"
  30741. - " sltu $1, %0, %5 \n"
  30742. - " addu %0, $1 \n"
  30743. -
  30744. - " addu %0, %6 # csum\n"
  30745. - " sltu $1, %0, %6 \n"
  30746. - " lw %1, 0(%2) # four words source address\n"
  30747. - " addu %0, $1 \n"
  30748. - " addu %0, %1 \n"
  30749. - " sltu $1, %0, %1 \n"
  30750. -
  30751. - " lw %1, 4(%2) \n"
  30752. - " addu %0, $1 \n"
  30753. - " addu %0, %1 \n"
  30754. - " sltu $1, %0, %1 \n"
  30755. -
  30756. - " lw %1, 8(%2) \n"
  30757. - " addu %0, $1 \n"
  30758. - " addu %0, %1 \n"
  30759. - " sltu $1, %0, %1 \n"
  30760. -
  30761. - " lw %1, 12(%2) \n"
  30762. - " addu %0, $1 \n"
  30763. - " addu %0, %1 \n"
  30764. - " sltu $1, %0, %1 \n"
  30765. -
  30766. - " lw %1, 0(%3) \n"
  30767. - " addu %0, $1 \n"
  30768. - " addu %0, %1 \n"
  30769. - " sltu $1, %0, %1 \n"
  30770. -
  30771. - " lw %1, 4(%3) \n"
  30772. - " addu %0, $1 \n"
  30773. - " addu %0, %1 \n"
  30774. - " sltu $1, %0, %1 \n"
  30775. -
  30776. - " lw %1, 8(%3) \n"
  30777. - " addu %0, $1 \n"
  30778. - " addu %0, %1 \n"
  30779. - " sltu $1, %0, %1 \n"
  30780. -
  30781. - " lw %1, 12(%3) \n"
  30782. - " addu %0, $1 \n"
  30783. - " addu %0, %1 \n"
  30784. - " sltu $1, %0, %1 \n"
  30785. -
  30786. - " addu %0, $1 # Add final carry\n"
  30787. - " .set pop"
  30788. - : "=&r" (sum), "=&r" (tmp)
  30789. - : "r" (saddr), "r" (daddr),
  30790. - "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
  30791. -
  30792. - return csum_fold(sum);
  30793. -}
  30794. -
  30795. #include <asm-generic/checksum.h>
  30796. #endif /* CONFIG_GENERIC_CSUM */
  30797. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/fw/myloader/myloader.h linux-4.1.43/arch/mips/include/asm/fw/myloader/myloader.h
  30798. --- linux-4.1.43.orig/arch/mips/include/asm/fw/myloader/myloader.h 1970-01-01 01:00:00.000000000 +0100
  30799. +++ linux-4.1.43/arch/mips/include/asm/fw/myloader/myloader.h 2017-08-06 20:02:15.000000000 +0200
  30800. @@ -0,0 +1,34 @@
  30801. +/*
  30802. + * Compex's MyLoader specific definitions
  30803. + *
  30804. + * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
  30805. + *
  30806. + * This program is free software; you can redistribute it and/or modify it
  30807. + * under the terms of the GNU General Public License version 2 as published
  30808. + * by the Free Software Foundation.
  30809. + *
  30810. + */
  30811. +
  30812. +#ifndef _ASM_MIPS_FW_MYLOADER_H
  30813. +#define _ASM_MIPS_FW_MYLOADER_H
  30814. +
  30815. +#include <linux/myloader.h>
  30816. +
  30817. +struct myloader_info {
  30818. + uint32_t vid;
  30819. + uint32_t did;
  30820. + uint32_t svid;
  30821. + uint32_t sdid;
  30822. + uint8_t macs[MYLO_ETHADDR_COUNT][6];
  30823. +};
  30824. +
  30825. +#ifdef CONFIG_MYLOADER
  30826. +extern struct myloader_info *myloader_get_info(void) __init;
  30827. +#else
  30828. +static inline struct myloader_info *myloader_get_info(void)
  30829. +{
  30830. + return NULL;
  30831. +}
  30832. +#endif /* CONFIG_MYLOADER */
  30833. +
  30834. +#endif /* _ASM_MIPS_FW_MYLOADER_H */
  30835. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ag71xx_platform.h linux-4.1.43/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
  30836. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ag71xx_platform.h 1970-01-01 01:00:00.000000000 +0100
  30837. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/ag71xx_platform.h 2017-08-06 20:02:15.000000000 +0200
  30838. @@ -0,0 +1,65 @@
  30839. +/*
  30840. + * Atheros AR71xx SoC specific platform data definitions
  30841. + *
  30842. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  30843. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  30844. + *
  30845. + * This program is free software; you can redistribute it and/or modify it
  30846. + * under the terms of the GNU General Public License version 2 as published
  30847. + * by the Free Software Foundation.
  30848. + */
  30849. +
  30850. +#ifndef __ASM_MACH_ATH79_PLATFORM_H
  30851. +#define __ASM_MACH_ATH79_PLATFORM_H
  30852. +
  30853. +#include <linux/if_ether.h>
  30854. +#include <linux/skbuff.h>
  30855. +#include <linux/phy.h>
  30856. +#include <linux/spi/spi.h>
  30857. +
  30858. +struct ag71xx_switch_platform_data {
  30859. + u8 phy4_mii_en:1;
  30860. + u8 phy_poll_mask;
  30861. +};
  30862. +
  30863. +struct ag71xx_platform_data {
  30864. + phy_interface_t phy_if_mode;
  30865. + u32 phy_mask;
  30866. + int speed;
  30867. + int duplex;
  30868. + u32 reset_bit;
  30869. + u8 mac_addr[ETH_ALEN];
  30870. + struct device *mii_bus_dev;
  30871. +
  30872. + u8 has_gbit:1;
  30873. + u8 is_ar91xx:1;
  30874. + u8 is_ar7240:1;
  30875. + u8 is_ar724x:1;
  30876. + u8 has_ar8216:1;
  30877. +
  30878. + struct ag71xx_switch_platform_data *switch_data;
  30879. +
  30880. + void (*ddr_flush)(void);
  30881. + void (*set_speed)(int speed);
  30882. +
  30883. + u32 fifo_cfg1;
  30884. + u32 fifo_cfg2;
  30885. + u32 fifo_cfg3;
  30886. +
  30887. + unsigned int max_frame_len;
  30888. + unsigned int desc_pktlen_mask;
  30889. +};
  30890. +
  30891. +struct ag71xx_mdio_platform_data {
  30892. + u32 phy_mask;
  30893. + u8 builtin_switch:1;
  30894. + u8 is_ar7240:1;
  30895. + u8 is_ar9330:1;
  30896. + u8 is_ar934x:1;
  30897. + unsigned long mdio_clock;
  30898. + unsigned long ref_clock;
  30899. +
  30900. + void (*reset)(struct mii_bus *bus);
  30901. +};
  30902. +
  30903. +#endif /* __ASM_MACH_ATH79_PLATFORM_H */
  30904. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h linux-4.1.43/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  30905. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2017-08-06 01:56:14.000000000 +0200
  30906. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2017-08-06 20:02:15.000000000 +0200
  30907. @@ -20,6 +20,10 @@
  30908. #include <linux/bitops.h>
  30909. #define AR71XX_APB_BASE 0x18000000
  30910. +#define AR71XX_GE0_BASE 0x19000000
  30911. +#define AR71XX_GE0_SIZE 0x10000
  30912. +#define AR71XX_GE1_BASE 0x1a000000
  30913. +#define AR71XX_GE1_SIZE 0x10000
  30914. #define AR71XX_EHCI_BASE 0x1b000000
  30915. #define AR71XX_EHCI_SIZE 0x1000
  30916. #define AR71XX_OHCI_BASE 0x1c000000
  30917. @@ -39,6 +43,8 @@
  30918. #define AR71XX_PLL_SIZE 0x100
  30919. #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
  30920. #define AR71XX_RESET_SIZE 0x100
  30921. +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
  30922. +#define AR71XX_MII_SIZE 0x100
  30923. #define AR71XX_PCI_MEM_BASE 0x10000000
  30924. #define AR71XX_PCI_MEM_SIZE 0x07000000
  30925. @@ -81,18 +87,39 @@
  30926. #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
  30927. #define AR933X_UART_SIZE 0x14
  30928. +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  30929. +#define AR933X_GMAC_SIZE 0x04
  30930. #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  30931. #define AR933X_WMAC_SIZE 0x20000
  30932. #define AR933X_EHCI_BASE 0x1b000000
  30933. #define AR933X_EHCI_SIZE 0x1000
  30934. +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  30935. +#define AR934X_GMAC_SIZE 0x14
  30936. #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  30937. #define AR934X_WMAC_SIZE 0x20000
  30938. #define AR934X_EHCI_BASE 0x1b000000
  30939. #define AR934X_EHCI_SIZE 0x200
  30940. +#define AR934X_NFC_BASE 0x1b000200
  30941. +#define AR934X_NFC_SIZE 0xb8
  30942. #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
  30943. #define AR934X_SRIF_SIZE 0x1000
  30944. +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  30945. +#define QCA953X_GMAC_SIZE 0x14
  30946. +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  30947. +#define QCA953X_WMAC_SIZE 0x20000
  30948. +#define QCA953X_EHCI_BASE 0x1b000000
  30949. +#define QCA953X_EHCI_SIZE 0x200
  30950. +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
  30951. +#define QCA953X_SRIF_SIZE 0x1000
  30952. +
  30953. +#define QCA953X_PCI_CFG_BASE0 0x14000000
  30954. +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
  30955. +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
  30956. +#define QCA953X_PCI_MEM_BASE0 0x10000000
  30957. +#define QCA953X_PCI_MEM_SIZE 0x02000000
  30958. +
  30959. #define QCA955X_PCI_MEM_BASE0 0x10000000
  30960. #define QCA955X_PCI_MEM_BASE1 0x12000000
  30961. #define QCA955X_PCI_MEM_SIZE 0x02000000
  30962. @@ -106,11 +133,40 @@
  30963. #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
  30964. #define QCA955X_PCI_CTRL_SIZE 0x100
  30965. +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  30966. +#define QCA955X_GMAC_SIZE 0x40
  30967. #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  30968. #define QCA955X_WMAC_SIZE 0x20000
  30969. #define QCA955X_EHCI0_BASE 0x1b000000
  30970. #define QCA955X_EHCI1_BASE 0x1b400000
  30971. #define QCA955X_EHCI_SIZE 0x1000
  30972. +#define QCA955X_NFC_BASE 0x1b800200
  30973. +#define QCA955X_NFC_SIZE 0xb8
  30974. +
  30975. +#define QCA956X_PCI_MEM_BASE1 0x12000000
  30976. +#define QCA956X_PCI_MEM_SIZE 0x02000000
  30977. +#define QCA956X_PCI_CFG_BASE1 0x16000000
  30978. +#define QCA956X_PCI_CFG_SIZE 0x1000
  30979. +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
  30980. +#define QCA956X_PCI_CRP_SIZE 0x1000
  30981. +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
  30982. +#define QCA956X_PCI_CTRL_SIZE 0x100
  30983. +
  30984. +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  30985. +#define QCA956X_WMAC_SIZE 0x20000
  30986. +#define QCA956X_EHCI0_BASE 0x1b000000
  30987. +#define QCA956X_EHCI1_BASE 0x1b400000
  30988. +#define QCA956X_EHCI_SIZE 0x200
  30989. +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  30990. +#define QCA956X_GMAC_SIZE 0x64
  30991. +
  30992. +#define AR9300_OTP_BASE 0x14000
  30993. +#define AR9300_OTP_STATUS 0x15f18
  30994. +#define AR9300_OTP_STATUS_TYPE 0x7
  30995. +#define AR9300_OTP_STATUS_VALID 0x4
  30996. +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
  30997. +#define AR9300_OTP_STATUS_SM_BUSY 0x1
  30998. +#define AR9300_OTP_READ_DATA 0x15f1c
  30999. /*
  31000. * DDR_CTRL block
  31001. @@ -149,6 +205,12 @@
  31002. #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
  31003. #define AR934X_DDR_REG_FLUSH_WMAC 0xac
  31004. +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
  31005. +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
  31006. +#define QCA953X_DDR_REG_FLUSH_USB 0xa4
  31007. +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
  31008. +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
  31009. +
  31010. /*
  31011. * PLL block
  31012. */
  31013. @@ -166,6 +228,9 @@
  31014. #define AR71XX_AHB_DIV_SHIFT 20
  31015. #define AR71XX_AHB_DIV_MASK 0x7
  31016. +#define AR71XX_ETH0_PLL_SHIFT 17
  31017. +#define AR71XX_ETH1_PLL_SHIFT 19
  31018. +
  31019. #define AR724X_PLL_REG_CPU_CONFIG 0x00
  31020. #define AR724X_PLL_REG_PCIE_CONFIG 0x18
  31021. @@ -178,6 +243,8 @@
  31022. #define AR724X_DDR_DIV_SHIFT 22
  31023. #define AR724X_DDR_DIV_MASK 0x3
  31024. +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
  31025. +
  31026. #define AR913X_PLL_REG_CPU_CONFIG 0x00
  31027. #define AR913X_PLL_REG_ETH_CONFIG 0x04
  31028. #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
  31029. @@ -190,6 +257,9 @@
  31030. #define AR913X_AHB_DIV_SHIFT 19
  31031. #define AR913X_AHB_DIV_MASK 0x1
  31032. +#define AR913X_ETH0_PLL_SHIFT 20
  31033. +#define AR913X_ETH1_PLL_SHIFT 22
  31034. +
  31035. #define AR933X_PLL_CPU_CONFIG_REG 0x00
  31036. #define AR933X_PLL_CLOCK_CTRL_REG 0x08
  31037. @@ -211,6 +281,8 @@
  31038. #define AR934X_PLL_CPU_CONFIG_REG 0x00
  31039. #define AR934X_PLL_DDR_CONFIG_REG 0x04
  31040. #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
  31041. +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
  31042. +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
  31043. #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
  31044. #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
  31045. @@ -243,9 +315,51 @@
  31046. #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  31047. #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  31048. +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
  31049. +
  31050. +#define QCA953X_PLL_CPU_CONFIG_REG 0x00
  31051. +#define QCA953X_PLL_DDR_CONFIG_REG 0x04
  31052. +#define QCA953X_PLL_CLK_CTRL_REG 0x08
  31053. +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
  31054. +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
  31055. +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
  31056. +
  31057. +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
  31058. +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
  31059. +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
  31060. +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
  31061. +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
  31062. +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
  31063. +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
  31064. +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
  31065. +
  31066. +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
  31067. +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
  31068. +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
  31069. +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
  31070. +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
  31071. +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
  31072. +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
  31073. +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
  31074. +
  31075. +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
  31076. +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
  31077. +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
  31078. +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
  31079. +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
  31080. +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
  31081. +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
  31082. +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
  31083. +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
  31084. +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
  31085. +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  31086. +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  31087. +
  31088. #define QCA955X_PLL_CPU_CONFIG_REG 0x00
  31089. #define QCA955X_PLL_DDR_CONFIG_REG 0x04
  31090. #define QCA955X_PLL_CLK_CTRL_REG 0x08
  31091. +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
  31092. +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
  31093. #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
  31094. #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
  31095. @@ -278,6 +392,49 @@
  31096. #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  31097. #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  31098. +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
  31099. +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
  31100. +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
  31101. +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
  31102. +#define QCA956X_PLL_CLK_CTRL_REG 0x10
  31103. +
  31104. +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
  31105. +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
  31106. +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
  31107. +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
  31108. +
  31109. +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
  31110. +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
  31111. +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
  31112. +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
  31113. +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
  31114. +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
  31115. +
  31116. +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
  31117. +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
  31118. +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
  31119. +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
  31120. +
  31121. +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
  31122. +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
  31123. +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
  31124. +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
  31125. +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
  31126. +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
  31127. +
  31128. +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
  31129. +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
  31130. +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
  31131. +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
  31132. +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
  31133. +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
  31134. +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
  31135. +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
  31136. +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
  31137. +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
  31138. +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
  31139. +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  31140. +
  31141. /*
  31142. * USB_CONFIG block
  31143. */
  31144. @@ -317,10 +474,19 @@
  31145. #define AR934X_RESET_REG_BOOTSTRAP 0xb0
  31146. #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  31147. +#define QCA953X_RESET_REG_RESET_MODULE 0x1c
  31148. +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
  31149. +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  31150. +
  31151. #define QCA955X_RESET_REG_RESET_MODULE 0x1c
  31152. #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
  31153. #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
  31154. +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
  31155. +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
  31156. +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
  31157. +
  31158. +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
  31159. #define MISC_INT_ETHSW BIT(12)
  31160. #define MISC_INT_TIMER4 BIT(10)
  31161. #define MISC_INT_TIMER3 BIT(9)
  31162. @@ -370,16 +536,104 @@
  31163. #define AR913X_RESET_USB_HOST BIT(5)
  31164. #define AR913X_RESET_USB_PHY BIT(4)
  31165. +#define AR933X_RESET_GE1_MDIO BIT(23)
  31166. +#define AR933X_RESET_GE0_MDIO BIT(22)
  31167. +#define AR933X_RESET_GE1_MAC BIT(13)
  31168. #define AR933X_RESET_WMAC BIT(11)
  31169. +#define AR933X_RESET_GE0_MAC BIT(9)
  31170. #define AR933X_RESET_USB_HOST BIT(5)
  31171. #define AR933X_RESET_USB_PHY BIT(4)
  31172. #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
  31173. +#define AR934X_RESET_HOST BIT(31)
  31174. +#define AR934X_RESET_SLIC BIT(30)
  31175. +#define AR934X_RESET_HDMA BIT(29)
  31176. +#define AR934X_RESET_EXTERNAL BIT(28)
  31177. +#define AR934X_RESET_RTC BIT(27)
  31178. +#define AR934X_RESET_PCIE_EP_INT BIT(26)
  31179. +#define AR934X_RESET_CHKSUM_ACC BIT(25)
  31180. +#define AR934X_RESET_FULL_CHIP BIT(24)
  31181. +#define AR934X_RESET_GE1_MDIO BIT(23)
  31182. +#define AR934X_RESET_GE0_MDIO BIT(22)
  31183. +#define AR934X_RESET_CPU_NMI BIT(21)
  31184. +#define AR934X_RESET_CPU_COLD BIT(20)
  31185. +#define AR934X_RESET_HOST_RESET_INT BIT(19)
  31186. +#define AR934X_RESET_PCIE_EP BIT(18)
  31187. +#define AR934X_RESET_UART1 BIT(17)
  31188. +#define AR934X_RESET_DDR BIT(16)
  31189. +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
  31190. +#define AR934X_RESET_NANDF BIT(14)
  31191. +#define AR934X_RESET_GE1_MAC BIT(13)
  31192. +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
  31193. #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
  31194. +#define AR934X_RESET_HOST_DMA_INT BIT(10)
  31195. +#define AR934X_RESET_GE0_MAC BIT(9)
  31196. +#define AR934X_RESET_ETH_SWITCH BIT(8)
  31197. +#define AR934X_RESET_PCIE_PHY BIT(7)
  31198. +#define AR934X_RESET_PCIE BIT(6)
  31199. #define AR934X_RESET_USB_HOST BIT(5)
  31200. #define AR934X_RESET_USB_PHY BIT(4)
  31201. #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
  31202. +#define AR934X_RESET_LUT BIT(2)
  31203. +#define AR934X_RESET_MBOX BIT(1)
  31204. +#define AR934X_RESET_I2S BIT(0)
  31205. +
  31206. +#define QCA953X_RESET_USB_EXT_PWR BIT(29)
  31207. +#define QCA953X_RESET_EXTERNAL BIT(28)
  31208. +#define QCA953X_RESET_RTC BIT(27)
  31209. +#define QCA953X_RESET_FULL_CHIP BIT(24)
  31210. +#define QCA953X_RESET_GE1_MDIO BIT(23)
  31211. +#define QCA953X_RESET_GE0_MDIO BIT(22)
  31212. +#define QCA953X_RESET_CPU_NMI BIT(21)
  31213. +#define QCA953X_RESET_CPU_COLD BIT(20)
  31214. +#define QCA953X_RESET_DDR BIT(16)
  31215. +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
  31216. +#define QCA953X_RESET_GE1_MAC BIT(13)
  31217. +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
  31218. +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
  31219. +#define QCA953X_RESET_GE0_MAC BIT(9)
  31220. +#define QCA953X_RESET_ETH_SWITCH BIT(8)
  31221. +#define QCA953X_RESET_PCIE_PHY BIT(7)
  31222. +#define QCA953X_RESET_PCIE BIT(6)
  31223. +#define QCA953X_RESET_USB_HOST BIT(5)
  31224. +#define QCA953X_RESET_USB_PHY BIT(4)
  31225. +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
  31226. +
  31227. +#define QCA955X_RESET_HOST BIT(31)
  31228. +#define QCA955X_RESET_SLIC BIT(30)
  31229. +#define QCA955X_RESET_HDMA BIT(29)
  31230. +#define QCA955X_RESET_EXTERNAL BIT(28)
  31231. +#define QCA955X_RESET_RTC BIT(27)
  31232. +#define QCA955X_RESET_PCIE_EP_INT BIT(26)
  31233. +#define QCA955X_RESET_CHKSUM_ACC BIT(25)
  31234. +#define QCA955X_RESET_FULL_CHIP BIT(24)
  31235. +#define QCA955X_RESET_GE1_MDIO BIT(23)
  31236. +#define QCA955X_RESET_GE0_MDIO BIT(22)
  31237. +#define QCA955X_RESET_CPU_NMI BIT(21)
  31238. +#define QCA955X_RESET_CPU_COLD BIT(20)
  31239. +#define QCA955X_RESET_HOST_RESET_INT BIT(19)
  31240. +#define QCA955X_RESET_PCIE_EP BIT(18)
  31241. +#define QCA955X_RESET_UART1 BIT(17)
  31242. +#define QCA955X_RESET_DDR BIT(16)
  31243. +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
  31244. +#define QCA955X_RESET_NANDF BIT(14)
  31245. +#define QCA955X_RESET_GE1_MAC BIT(13)
  31246. +#define QCA955X_RESET_SGMII_ANALOG BIT(12)
  31247. +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
  31248. +#define QCA955X_RESET_HOST_DMA_INT BIT(10)
  31249. +#define QCA955X_RESET_GE0_MAC BIT(9)
  31250. +#define QCA955X_RESET_SGMII BIT(8)
  31251. +#define QCA955X_RESET_PCIE_PHY BIT(7)
  31252. +#define QCA955X_RESET_PCIE BIT(6)
  31253. +#define QCA955X_RESET_USB_HOST BIT(5)
  31254. +#define QCA955X_RESET_USB_PHY BIT(4)
  31255. +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
  31256. +#define QCA955X_RESET_LUT BIT(2)
  31257. +#define QCA955X_RESET_MBOX BIT(1)
  31258. +#define QCA955X_RESET_I2S BIT(0)
  31259. +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
  31260. +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
  31261. #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
  31262. #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
  31263. @@ -398,8 +652,17 @@
  31264. #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  31265. #define AR934X_BOOTSTRAP_DDR1 BIT(0)
  31266. +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
  31267. +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
  31268. +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
  31269. +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
  31270. +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  31271. +#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
  31272. +
  31273. #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
  31274. +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
  31275. +
  31276. #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
  31277. #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
  31278. #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
  31279. @@ -418,6 +681,24 @@
  31280. AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
  31281. AR934X_PCIE_WMAC_INT_PCIE_RC3)
  31282. +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
  31283. +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
  31284. +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
  31285. +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
  31286. +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
  31287. +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
  31288. +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
  31289. +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
  31290. +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
  31291. +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
  31292. + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
  31293. + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
  31294. +
  31295. +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
  31296. + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
  31297. + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
  31298. + QCA953X_PCIE_WMAC_INT_PCIE_RC3)
  31299. +
  31300. #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
  31301. #define QCA955X_EXT_INT_WMAC_TX BIT(1)
  31302. #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
  31303. @@ -449,6 +730,37 @@
  31304. QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
  31305. QCA955X_EXT_INT_PCIE_RC2_INT3)
  31306. +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
  31307. +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
  31308. +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
  31309. +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
  31310. +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
  31311. +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
  31312. +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
  31313. +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
  31314. +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
  31315. +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
  31316. +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
  31317. +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
  31318. +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
  31319. +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
  31320. +#define QCA956X_EXT_INT_USB1 BIT(24)
  31321. +#define QCA956X_EXT_INT_USB2 BIT(28)
  31322. +
  31323. +#define QCA956X_EXT_INT_WMAC_ALL \
  31324. + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
  31325. + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
  31326. +
  31327. +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
  31328. + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
  31329. + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
  31330. + QCA956X_EXT_INT_PCIE_RC1_INT3)
  31331. +
  31332. +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
  31333. + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
  31334. + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
  31335. + QCA956X_EXT_INT_PCIE_RC2_INT3)
  31336. +
  31337. #define REV_ID_MAJOR_MASK 0xfff0
  31338. #define REV_ID_MAJOR_AR71XX 0x00a0
  31339. #define REV_ID_MAJOR_AR913X 0x00b0
  31340. @@ -460,8 +772,12 @@
  31341. #define REV_ID_MAJOR_AR9341 0x0120
  31342. #define REV_ID_MAJOR_AR9342 0x1120
  31343. #define REV_ID_MAJOR_AR9344 0x2120
  31344. +#define REV_ID_MAJOR_QCA9533 0x0140
  31345. +#define REV_ID_MAJOR_QCA9533_V2 0x0160
  31346. #define REV_ID_MAJOR_QCA9556 0x0130
  31347. #define REV_ID_MAJOR_QCA9558 0x1130
  31348. +#define REV_ID_MAJOR_TP9343 0x0150
  31349. +#define REV_ID_MAJOR_QCA9561 0x1150
  31350. #define AR71XX_REV_ID_MINOR_MASK 0x3
  31351. #define AR71XX_REV_ID_MINOR_AR7130 0x0
  31352. @@ -482,8 +798,12 @@
  31353. #define AR934X_REV_ID_REVISION_MASK 0xf
  31354. +#define QCA953X_REV_ID_REVISION_MASK 0xf
  31355. +
  31356. #define QCA955X_REV_ID_REVISION_MASK 0xf
  31357. +#define QCA956X_REV_ID_REVISION_MASK 0xf
  31358. +
  31359. /*
  31360. * SPI block
  31361. */
  31362. @@ -520,16 +840,65 @@
  31363. #define AR71XX_GPIO_REG_INT_PENDING 0x20
  31364. #define AR71XX_GPIO_REG_INT_ENABLE 0x24
  31365. #define AR71XX_GPIO_REG_FUNC 0x28
  31366. +#define AR71XX_GPIO_REG_FUNC_2 0x30
  31367. +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
  31368. +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
  31369. +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
  31370. +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
  31371. +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
  31372. +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
  31373. #define AR934X_GPIO_REG_FUNC 0x6c
  31374. +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
  31375. +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
  31376. +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
  31377. +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
  31378. +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
  31379. +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
  31380. +#define QCA953X_GPIO_REG_FUNC 0x6c
  31381. +
  31382. +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
  31383. +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
  31384. +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
  31385. +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
  31386. +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
  31387. +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
  31388. +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
  31389. +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
  31390. +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
  31391. +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
  31392. +
  31393. +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
  31394. +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
  31395. +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
  31396. +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
  31397. +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
  31398. +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
  31399. +#define QCA955X_GPIO_REG_FUNC 0x6c
  31400. +
  31401. +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
  31402. +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
  31403. +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
  31404. +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
  31405. +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
  31406. +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
  31407. +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
  31408. +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
  31409. +#define QCA956X_GPIO_REG_FUNC 0x6c
  31410. +
  31411. +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
  31412. +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
  31413. +
  31414. #define AR71XX_GPIO_COUNT 16
  31415. #define AR7240_GPIO_COUNT 18
  31416. #define AR7241_GPIO_COUNT 20
  31417. #define AR913X_GPIO_COUNT 22
  31418. #define AR933X_GPIO_COUNT 30
  31419. #define AR934X_GPIO_COUNT 23
  31420. +#define QCA953X_GPIO_COUNT 18
  31421. #define QCA955X_GPIO_COUNT 24
  31422. +#define QCA956X_GPIO_COUNT 23
  31423. /*
  31424. * SRIF block
  31425. @@ -552,4 +921,185 @@
  31426. #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
  31427. #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  31428. +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
  31429. +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
  31430. +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
  31431. +
  31432. +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
  31433. +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
  31434. +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
  31435. +
  31436. +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
  31437. +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
  31438. +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
  31439. +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
  31440. +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
  31441. +
  31442. +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
  31443. +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
  31444. +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
  31445. +
  31446. +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
  31447. +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
  31448. +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
  31449. +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
  31450. +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
  31451. +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
  31452. +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
  31453. +
  31454. +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
  31455. +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
  31456. +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
  31457. +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
  31458. +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
  31459. +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
  31460. +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
  31461. +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
  31462. +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
  31463. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
  31464. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
  31465. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
  31466. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
  31467. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
  31468. +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
  31469. +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
  31470. +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
  31471. +
  31472. +#define AR933X_GPIO_FUNC2_JUMPSTART_DISABLE BIT(9)
  31473. +
  31474. +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
  31475. +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
  31476. +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
  31477. +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
  31478. +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
  31479. +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
  31480. +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
  31481. +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
  31482. +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
  31483. +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
  31484. +
  31485. +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
  31486. +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
  31487. +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
  31488. +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
  31489. +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
  31490. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
  31491. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
  31492. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
  31493. +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
  31494. +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
  31495. +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
  31496. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
  31497. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
  31498. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
  31499. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
  31500. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
  31501. +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
  31502. +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
  31503. +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
  31504. +
  31505. +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
  31506. +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
  31507. +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
  31508. +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
  31509. +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
  31510. +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
  31511. +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
  31512. +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
  31513. +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
  31514. +
  31515. +#define AR934X_GPIO_OUT_GPIO 0
  31516. +#define AR934X_GPIO_OUT_SPI_CS1 7
  31517. +#define AR934X_GPIO_OUT_LED_LINK0 41
  31518. +#define AR934X_GPIO_OUT_LED_LINK1 42
  31519. +#define AR934X_GPIO_OUT_LED_LINK2 43
  31520. +#define AR934X_GPIO_OUT_LED_LINK3 44
  31521. +#define AR934X_GPIO_OUT_LED_LINK4 45
  31522. +#define AR934X_GPIO_OUT_EXT_LNA0 46
  31523. +#define AR934X_GPIO_OUT_EXT_LNA1 47
  31524. +
  31525. +#define QCA955X_GPIO_OUT_GPIO 0
  31526. +
  31527. +/*
  31528. + * MII_CTRL block
  31529. + */
  31530. +#define AR71XX_MII_REG_MII0_CTRL 0x00
  31531. +#define AR71XX_MII_REG_MII1_CTRL 0x04
  31532. +
  31533. +#define AR71XX_MII_CTRL_IF_MASK 3
  31534. +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
  31535. +#define AR71XX_MII_CTRL_SPEED_MASK 3
  31536. +#define AR71XX_MII_CTRL_SPEED_10 0
  31537. +#define AR71XX_MII_CTRL_SPEED_100 1
  31538. +#define AR71XX_MII_CTRL_SPEED_1000 2
  31539. +
  31540. +#define AR71XX_MII0_CTRL_IF_GMII 0
  31541. +#define AR71XX_MII0_CTRL_IF_MII 1
  31542. +#define AR71XX_MII0_CTRL_IF_RGMII 2
  31543. +#define AR71XX_MII0_CTRL_IF_RMII 3
  31544. +
  31545. +#define AR71XX_MII1_CTRL_IF_RGMII 0
  31546. +#define AR71XX_MII1_CTRL_IF_RMII 1
  31547. +
  31548. +/*
  31549. + * AR933X GMAC interface
  31550. + */
  31551. +#define AR933X_GMAC_REG_ETH_CFG 0x00
  31552. +
  31553. +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
  31554. +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
  31555. +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
  31556. +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
  31557. +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
  31558. +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
  31559. +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
  31560. +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
  31561. +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
  31562. +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
  31563. +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
  31564. +
  31565. +/*
  31566. + * AR934X GMAC Interface
  31567. + */
  31568. +#define AR934X_GMAC_REG_ETH_CFG 0x00
  31569. +
  31570. +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
  31571. +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
  31572. +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
  31573. +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
  31574. +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
  31575. +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
  31576. +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
  31577. +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
  31578. +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
  31579. +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
  31580. +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
  31581. +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
  31582. +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
  31583. +#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
  31584. +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
  31585. +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
  31586. +#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
  31587. +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
  31588. +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
  31589. +
  31590. +/*
  31591. + * QCA953X GMAC Interface
  31592. + */
  31593. +#define QCA953X_GMAC_REG_ETH_CFG 0x00
  31594. +
  31595. +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
  31596. +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
  31597. +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
  31598. +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
  31599. +
  31600. +/*
  31601. + * QCA955X GMAC Interface
  31602. + */
  31603. +
  31604. +#define QCA955X_GMAC_REG_ETH_CFG 0x00
  31605. +
  31606. +#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
  31607. +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
  31608. +
  31609. #endif /* __ASM_MACH_AR71XX_REGS_H */
  31610. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ath79.h linux-4.1.43/arch/mips/include/asm/mach-ath79/ath79.h
  31611. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ath79.h 2017-08-06 01:56:14.000000000 +0200
  31612. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/ath79.h 2017-08-06 20:02:15.000000000 +0200
  31613. @@ -32,8 +32,11 @@
  31614. ATH79_SOC_AR9341,
  31615. ATH79_SOC_AR9342,
  31616. ATH79_SOC_AR9344,
  31617. + ATH79_SOC_QCA9533,
  31618. ATH79_SOC_QCA9556,
  31619. ATH79_SOC_QCA9558,
  31620. + ATH79_SOC_TP9343,
  31621. + ATH79_SOC_QCA9561,
  31622. };
  31623. extern enum ath79_soc_type ath79_soc;
  31624. @@ -100,6 +103,16 @@
  31625. return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
  31626. }
  31627. +static inline int soc_is_qca9533(void)
  31628. +{
  31629. + return ath79_soc == ATH79_SOC_QCA9533;
  31630. +}
  31631. +
  31632. +static inline int soc_is_qca953x(void)
  31633. +{
  31634. + return soc_is_qca9533();
  31635. +}
  31636. +
  31637. static inline int soc_is_qca9556(void)
  31638. {
  31639. return ath79_soc == ATH79_SOC_QCA9556;
  31640. @@ -115,7 +128,23 @@
  31641. return soc_is_qca9556() || soc_is_qca9558();
  31642. }
  31643. +static inline int soc_is_tp9343(void)
  31644. +{
  31645. + return ath79_soc == ATH79_SOC_TP9343;
  31646. +}
  31647. +
  31648. +static inline int soc_is_qca9561(void)
  31649. +{
  31650. + return ath79_soc == ATH79_SOC_QCA9561;
  31651. +}
  31652. +
  31653. +static inline int soc_is_qca956x(void)
  31654. +{
  31655. + return soc_is_tp9343() || soc_is_qca9561();
  31656. +}
  31657. +
  31658. extern void __iomem *ath79_ddr_base;
  31659. +extern void __iomem *ath79_gpio_base;
  31660. extern void __iomem *ath79_pll_base;
  31661. extern void __iomem *ath79_reset_base;
  31662. @@ -132,6 +161,7 @@
  31663. static inline void ath79_reset_wr(unsigned reg, u32 val)
  31664. {
  31665. __raw_writel(val, ath79_reset_base + reg);
  31666. + (void) __raw_readl(ath79_reset_base + reg); /* flush */
  31667. }
  31668. static inline u32 ath79_reset_rr(unsigned reg)
  31669. @@ -141,5 +171,9 @@
  31670. void ath79_device_reset_set(u32 mask);
  31671. void ath79_device_reset_clear(u32 mask);
  31672. +u32 ath79_device_reset_get(u32 mask);
  31673. +
  31674. +void ath79_flash_acquire(void);
  31675. +void ath79_flash_release(void);
  31676. #endif /* __ASM_MACH_ATH79_H */
  31677. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h linux-4.1.43/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
  31678. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h 2017-08-06 01:56:14.000000000 +0200
  31679. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h 2017-08-06 20:02:15.000000000 +0200
  31680. @@ -16,8 +16,15 @@
  31681. unsigned num_chipselect;
  31682. };
  31683. +enum ath79_spi_cs_type {
  31684. + ATH79_SPI_CS_TYPE_INTERNAL,
  31685. + ATH79_SPI_CS_TYPE_GPIO,
  31686. +};
  31687. +
  31688. struct ath79_spi_controller_data {
  31689. - unsigned gpio;
  31690. + enum ath79_spi_cs_type cs_type;
  31691. + unsigned cs_line;
  31692. + bool is_flash;
  31693. };
  31694. #endif /* _ATH79_SPI_PLATFORM_H */
  31695. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h linux-4.1.43/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
  31696. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h 2017-08-06 01:56:14.000000000 +0200
  31697. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h 2017-08-06 20:02:15.000000000 +0200
  31698. @@ -36,6 +36,7 @@
  31699. #define cpu_has_mdmx 0
  31700. #define cpu_has_mips3d 0
  31701. #define cpu_has_smartmips 0
  31702. +#define cpu_has_rixi 0
  31703. #define cpu_has_mips32r1 1
  31704. #define cpu_has_mips32r2 1
  31705. @@ -43,6 +44,7 @@
  31706. #define cpu_has_mips64r2 0
  31707. #define cpu_has_mipsmt 0
  31708. +#define cpu_has_userlocal 0
  31709. #define cpu_has_64bits 0
  31710. #define cpu_has_64bit_zero_reg 0
  31711. @@ -51,5 +53,9 @@
  31712. #define cpu_dcache_line_size() 32
  31713. #define cpu_icache_line_size() 32
  31714. +#define cpu_has_vtag_icache 0
  31715. +#define cpu_has_dc_aliases 1
  31716. +#define cpu_has_ic_fills_f_dc 0
  31717. +#define cpu_has_pindexed_dcache 0
  31718. #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
  31719. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/irq.h linux-4.1.43/arch/mips/include/asm/mach-ath79/irq.h
  31720. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/irq.h 2017-08-06 01:56:14.000000000 +0200
  31721. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/irq.h 2017-08-06 20:02:15.000000000 +0200
  31722. @@ -10,7 +10,7 @@
  31723. #define __ASM_MACH_ATH79_IRQ_H
  31724. #define MIPS_CPU_IRQ_BASE 0
  31725. -#define NR_IRQS 51
  31726. +#define NR_IRQS 83
  31727. #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
  31728. @@ -30,6 +30,10 @@
  31729. #define ATH79_IP3_IRQ_COUNT 3
  31730. #define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
  31731. +#define ATH79_GPIO_IRQ_BASE (ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT)
  31732. +#define ATH79_GPIO_IRQ_COUNT 32
  31733. +#define ATH79_GPIO_IRQ(_x) (ATH79_GPIO_IRQ_BASE + (_x))
  31734. +
  31735. #include_next <irq.h>
  31736. #endif /* __ASM_MACH_ATH79_IRQ_H */
  31737. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/mach-rb750.h linux-4.1.43/arch/mips/include/asm/mach-ath79/mach-rb750.h
  31738. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/mach-rb750.h 1970-01-01 01:00:00.000000000 +0100
  31739. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/mach-rb750.h 2017-08-06 20:02:15.000000000 +0200
  31740. @@ -0,0 +1,84 @@
  31741. +/*
  31742. + * MikroTik RouterBOARD 750 definitions
  31743. + *
  31744. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  31745. + *
  31746. + * This program is free software; you can redistribute it and/or modify it
  31747. + * under the terms of the GNU General Public License version 2 as published
  31748. + * by the Free Software Foundation.
  31749. + */
  31750. +#ifndef _MACH_RB750_H
  31751. +#define _MACH_RB750_H
  31752. +
  31753. +#include <linux/bitops.h>
  31754. +
  31755. +#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */
  31756. +#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */
  31757. +#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */
  31758. +#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */
  31759. +#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */
  31760. +#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */
  31761. +#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */
  31762. +#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */
  31763. +#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */
  31764. +#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */
  31765. +#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */
  31766. +#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */
  31767. +#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */
  31768. +#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */
  31769. +#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */
  31770. +
  31771. +#define RB750_GPIO_BTN_RESET 1
  31772. +#define RB750_GPIO_SPI_CS0 2
  31773. +#define RB750_GPIO_LED_ACT 12
  31774. +#define RB750_GPIO_LED_PORT1 13
  31775. +#define RB750_GPIO_LED_PORT2 14
  31776. +#define RB750_GPIO_LED_PORT3 15
  31777. +#define RB750_GPIO_LED_PORT4 16
  31778. +#define RB750_GPIO_LED_PORT5 17
  31779. +
  31780. +#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT)
  31781. +#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1)
  31782. +#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2)
  31783. +#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
  31784. +#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
  31785. +#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
  31786. +#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE)
  31787. +
  31788. +#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
  31789. +
  31790. +#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \
  31791. + RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT)
  31792. +
  31793. +#define RB7XX_GPIO_NAND_NCE 0
  31794. +#define RB7XX_GPIO_MON 9
  31795. +#define RB7XX_GPIO_LED_ACT 11
  31796. +#define RB7XX_GPIO_USB_POWERON 13
  31797. +
  31798. +#define RB7XX_NAND_NCE BIT(RB7XX_GPIO_NAND_NCE)
  31799. +#define RB7XX_LED_ACT BIT(RB7XX_GPIO_LED_ACT)
  31800. +#define RB7XX_MONITOR BIT(RB7XX_GPIO_MON)
  31801. +#define RB7XX_USB_POWERON BIT(RB7XX_GPIO_USB_POWERON)
  31802. +
  31803. +struct rb750_led_data {
  31804. + char *name;
  31805. + char *default_trigger;
  31806. + u32 mask;
  31807. + int active_low;
  31808. +};
  31809. +
  31810. +struct rb750_led_platform_data {
  31811. + int num_leds;
  31812. + struct rb750_led_data *leds;
  31813. + void (*latch_change)(u32 clear, u32 set);
  31814. +};
  31815. +
  31816. +struct rb7xx_nand_platform_data {
  31817. + u32 nce_line;
  31818. +
  31819. + void (*enable_pins)(void);
  31820. + void (*disable_pins)(void);
  31821. + void (*latch_change)(u32, u32);
  31822. +};
  31823. +
  31824. +#endif /* _MACH_RB750_H */
  31825. \ No newline at end of file
  31826. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/mangle-port.h linux-4.1.43/arch/mips/include/asm/mach-ath79/mangle-port.h
  31827. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/mangle-port.h 1970-01-01 01:00:00.000000000 +0100
  31828. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/mangle-port.h 2017-08-06 20:02:15.000000000 +0200
  31829. @@ -0,0 +1,37 @@
  31830. +/*
  31831. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  31832. + *
  31833. + * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
  31834. + * Copyright (C) 2003, 2004 Ralf Baechle
  31835. + *
  31836. + * This program is free software; you can redistribute it and/or modify it
  31837. + * under the terms of the GNU General Public License version 2 as published
  31838. + * by the Free Software Foundation.
  31839. + */
  31840. +
  31841. +#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
  31842. +#define __ASM_MACH_ATH79_MANGLE_PORT_H
  31843. +
  31844. +#ifdef CONFIG_PCI
  31845. +extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
  31846. +extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
  31847. +#else
  31848. +#define ath79_pci_swizzle_b(port) (port)
  31849. +#define ath79_pci_swizzle_w(port) (port)
  31850. +#endif
  31851. +
  31852. +#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
  31853. +#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
  31854. +#define __swizzle_addr_l(port) (port)
  31855. +#define __swizzle_addr_q(port) (port)
  31856. +
  31857. +# define ioswabb(a, x) (x)
  31858. +# define __mem_ioswabb(a, x) (x)
  31859. +# define ioswabw(a, x) (x)
  31860. +# define __mem_ioswabw(a, x) cpu_to_le16(x)
  31861. +# define ioswabl(a, x) (x)
  31862. +# define __mem_ioswabl(a, x) cpu_to_le32(x)
  31863. +# define ioswabq(a, x) (x)
  31864. +# define __mem_ioswabq(a, x) cpu_to_le64(x)
  31865. +
  31866. +#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
  31867. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h linux-4.1.43/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h
  31868. --- linux-4.1.43.orig/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h 1970-01-01 01:00:00.000000000 +0100
  31869. +++ linux-4.1.43/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h 2017-08-06 20:02:15.000000000 +0200
  31870. @@ -0,0 +1,48 @@
  31871. +/*
  31872. + * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards
  31873. + *
  31874. + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  31875. + *
  31876. + * This file was based on the patches for Linux 2.6.27.39 published by
  31877. + * MikroTik for their RouterBoard 4xx series devices.
  31878. + *
  31879. + * This program is free software; you can redistribute it and/or modify it
  31880. + * under the terms of the GNU General Public License version 2 as published
  31881. + * by the Free Software Foundation.
  31882. + */
  31883. +
  31884. +#define CPLD_GPIO_nLED1 0
  31885. +#define CPLD_GPIO_nLED2 1
  31886. +#define CPLD_GPIO_nLED3 2
  31887. +#define CPLD_GPIO_nLED4 3
  31888. +#define CPLD_GPIO_FAN 4
  31889. +#define CPLD_GPIO_ALE 5
  31890. +#define CPLD_GPIO_CLE 6
  31891. +#define CPLD_GPIO_nCE 7
  31892. +#define CPLD_GPIO_nLED5 8
  31893. +
  31894. +#define CPLD_NUM_GPIOS 9
  31895. +
  31896. +#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1)
  31897. +#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2)
  31898. +#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3)
  31899. +#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4)
  31900. +#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN)
  31901. +#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE)
  31902. +#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE)
  31903. +#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE)
  31904. +#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5)
  31905. +
  31906. +struct rb4xx_cpld_platform_data {
  31907. + unsigned gpio_base;
  31908. +};
  31909. +
  31910. +extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value);
  31911. +extern int rb4xx_cpld_read(unsigned char *rx_buf,
  31912. + const unsigned char *verify_buf,
  31913. + unsigned cnt);
  31914. +extern int rb4xx_cpld_read_from(unsigned addr,
  31915. + unsigned char *rx_buf,
  31916. + const unsigned char *verify_buf,
  31917. + unsigned cnt);
  31918. +extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count);
  31919. diff -Nur linux-4.1.43.orig/arch/mips/include/asm/mips_machine.h linux-4.1.43/arch/mips/include/asm/mips_machine.h
  31920. --- linux-4.1.43.orig/arch/mips/include/asm/mips_machine.h 2017-08-06 01:56:14.000000000 +0200
  31921. +++ linux-4.1.43/arch/mips/include/asm/mips_machine.h 2017-08-06 20:02:15.000000000 +0200
  31922. @@ -36,6 +36,18 @@
  31923. .mach_setup = _setup, \
  31924. };
  31925. +#define MIPS_MACHINE_NONAME(_type, _id, _setup) \
  31926. +static const char machine_id_##_type[] __initconst \
  31927. + __aligned(1) = _id; \
  31928. +static struct mips_machine machine_##_type \
  31929. + __used __section(.mips.machines.init) = \
  31930. +{ \
  31931. + .mach_type = _type, \
  31932. + .mach_id = machine_id_##_type, \
  31933. + .mach_name = NULL, \
  31934. + .mach_setup = _setup, \
  31935. +};
  31936. +
  31937. extern long __mips_machines_start;
  31938. extern long __mips_machines_end;
  31939. diff -Nur linux-4.1.43.orig/drivers/Makefile linux-4.1.43/drivers/Makefile
  31940. --- linux-4.1.43.orig/drivers/Makefile 2017-08-06 01:56:14.000000000 +0200
  31941. +++ linux-4.1.43/drivers/Makefile 2017-08-06 20:02:16.000000000 +0200
  31942. @@ -71,8 +71,8 @@
  31943. obj-$(CONFIG_SCSI) += scsi/
  31944. obj-$(CONFIG_ATA) += ata/
  31945. obj-$(CONFIG_TARGET_CORE) += target/
  31946. -obj-$(CONFIG_MTD) += mtd/
  31947. obj-$(CONFIG_SPI) += spi/
  31948. +obj-$(CONFIG_MTD) += mtd/
  31949. obj-$(CONFIG_SPMI) += spmi/
  31950. obj-y += hsi/
  31951. obj-y += net/
  31952. diff -Nur linux-4.1.43.orig/drivers/gpio/Kconfig linux-4.1.43/drivers/gpio/Kconfig
  31953. --- linux-4.1.43.orig/drivers/gpio/Kconfig 2017-08-06 01:56:14.000000000 +0200
  31954. +++ linux-4.1.43/drivers/gpio/Kconfig 2017-08-06 20:02:15.000000000 +0200
  31955. @@ -942,7 +942,7 @@
  31956. config GPIO_74X164
  31957. tristate "74x164 serial-in/parallel-out 8-bits shift register"
  31958. - depends on SPI_MASTER && OF
  31959. + depends on SPI_MASTER
  31960. help
  31961. Driver for 74x164 compatible serial-in/parallel-out 8-outputs
  31962. shift registers. This driver can be used to provide access
  31963. @@ -989,4 +989,17 @@
  31964. endmenu
  31965. +comment "Other GPIO expanders"
  31966. +
  31967. +config GPIO_NXP_74HC153
  31968. + tristate "NXP 74HC153 Dual 4-input multiplexer"
  31969. + help
  31970. + Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
  31971. + provides a GPIO interface supporting input mode only.
  31972. +
  31973. +config GPIO_LATCH
  31974. + tristate "GPIO latch driver"
  31975. + help
  31976. + Say yes here to enable a GPIO latch driver.
  31977. +
  31978. endif
  31979. diff -Nur linux-4.1.43.orig/drivers/gpio/Makefile linux-4.1.43/drivers/gpio/Makefile
  31980. --- linux-4.1.43.orig/drivers/gpio/Makefile 2017-08-06 01:56:14.000000000 +0200
  31981. +++ linux-4.1.43/drivers/gpio/Makefile 2017-08-06 20:02:16.000000000 +0200
  31982. @@ -42,6 +42,7 @@
  31983. obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o
  31984. obj-$(CONFIG_ARCH_KS8695) += gpio-ks8695.o
  31985. obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o
  31986. +obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o
  31987. obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o
  31988. obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o
  31989. obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
  31990. @@ -64,6 +65,7 @@
  31991. obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o
  31992. obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
  31993. obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
  31994. +obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o
  31995. obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o
  31996. obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o
  31997. obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
  31998. diff -Nur linux-4.1.43.orig/drivers/gpio/gpio-74x164.c linux-4.1.43/drivers/gpio/gpio-74x164.c
  31999. --- linux-4.1.43.orig/drivers/gpio/gpio-74x164.c 2017-08-06 01:56:14.000000000 +0200
  32000. +++ linux-4.1.43/drivers/gpio/gpio-74x164.c 2017-08-06 20:02:15.000000000 +0200
  32001. @@ -12,6 +12,7 @@
  32002. #include <linux/init.h>
  32003. #include <linux/mutex.h>
  32004. #include <linux/spi/spi.h>
  32005. +#include <linux/spi/74x164.h>
  32006. #include <linux/gpio.h>
  32007. #include <linux/of_gpio.h>
  32008. #include <linux/slab.h>
  32009. @@ -107,8 +108,18 @@
  32010. static int gen_74x164_probe(struct spi_device *spi)
  32011. {
  32012. struct gen_74x164_chip *chip;
  32013. + struct gen_74x164_chip_platform_data *pdata;
  32014. + struct device_node *np;
  32015. int ret;
  32016. + pdata = spi->dev.platform_data;
  32017. + np = spi->dev.of_node;
  32018. +
  32019. + if (!np && !pdata) {
  32020. + dev_err(&spi->dev, "No configuration data available.\n");
  32021. + return -EINVAL;
  32022. + }
  32023. +
  32024. /*
  32025. * bits_per_word cannot be configured in platform data
  32026. */
  32027. @@ -130,18 +141,28 @@
  32028. chip->gpio_chip.set = gen_74x164_set_value;
  32029. chip->gpio_chip.base = -1;
  32030. - if (of_property_read_u32(spi->dev.of_node, "registers-number",
  32031. - &chip->registers)) {
  32032. - dev_err(&spi->dev,
  32033. - "Missing registers-number property in the DT.\n");
  32034. - return -EINVAL;
  32035. + if (np) {
  32036. + if (of_property_read_u32(spi->dev.of_node, "registers-number", &chip->registers)) {
  32037. + dev_err(&spi->dev, "Missing registers-number property in the DT.\n");
  32038. + ret = -EINVAL;
  32039. + goto exit_destroy;
  32040. + }
  32041. + } else if (pdata) {
  32042. + chip->gpio_chip.base = pdata->base;
  32043. + chip->registers = pdata->num_registers;
  32044. }
  32045. + if (!chip->registers)
  32046. + chip->registers = 1;
  32047. +
  32048. chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
  32049. chip->buffer = devm_kzalloc(&spi->dev, chip->registers, GFP_KERNEL);
  32050. if (!chip->buffer)
  32051. return -ENOMEM;
  32052. + if (pdata && pdata->init_data)
  32053. + memcpy(chip->buffer, pdata->init_data, chip->registers);
  32054. +
  32055. chip->gpio_chip.can_sleep = true;
  32056. chip->gpio_chip.dev = &spi->dev;
  32057. chip->gpio_chip.owner = THIS_MODULE;
  32058. @@ -174,17 +195,19 @@
  32059. return 0;
  32060. }
  32061. +#ifdef CONFIG_OF
  32062. static const struct of_device_id gen_74x164_dt_ids[] = {
  32063. { .compatible = "fairchild,74hc595" },
  32064. {},
  32065. };
  32066. MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
  32067. +#endif /* CONFIG_OF */
  32068. static struct spi_driver gen_74x164_driver = {
  32069. .driver = {
  32070. .name = "74x164",
  32071. .owner = THIS_MODULE,
  32072. - .of_match_table = gen_74x164_dt_ids,
  32073. + .of_match_table = of_match_ptr(gen_74x164_dt_ids),
  32074. },
  32075. .probe = gen_74x164_probe,
  32076. .remove = gen_74x164_remove,
  32077. diff -Nur linux-4.1.43.orig/drivers/gpio/gpio-latch.c linux-4.1.43/drivers/gpio/gpio-latch.c
  32078. --- linux-4.1.43.orig/drivers/gpio/gpio-latch.c 1970-01-01 01:00:00.000000000 +0100
  32079. +++ linux-4.1.43/drivers/gpio/gpio-latch.c 2017-08-06 20:02:15.000000000 +0200
  32080. @@ -0,0 +1,220 @@
  32081. +/*
  32082. + * GPIO latch driver
  32083. + *
  32084. + * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
  32085. + *
  32086. + * This program is free software; you can redistribute it and/or modify it
  32087. + * under the terms of the GNU General Public License version 2 as published
  32088. + * by the Free Software Foundation.
  32089. + */
  32090. +
  32091. +#include <linux/kernel.h>
  32092. +#include <linux/init.h>
  32093. +#include <linux/module.h>
  32094. +#include <linux/types.h>
  32095. +#include <linux/gpio.h>
  32096. +#include <linux/slab.h>
  32097. +#include <linux/platform_device.h>
  32098. +
  32099. +#include <linux/platform_data/gpio-latch.h>
  32100. +
  32101. +struct gpio_latch_chip {
  32102. + struct gpio_chip gc;
  32103. +
  32104. + struct mutex mutex;
  32105. + struct mutex latch_mutex;
  32106. + bool latch_enabled;
  32107. + int le_gpio;
  32108. + bool le_active_low;
  32109. + int *gpios;
  32110. +};
  32111. +
  32112. +static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc)
  32113. +{
  32114. + return container_of(gc, struct gpio_latch_chip, gc);
  32115. +}
  32116. +
  32117. +static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable)
  32118. +{
  32119. + mutex_lock(&glc->mutex);
  32120. +
  32121. + if (enable)
  32122. + glc->latch_enabled = true;
  32123. +
  32124. + if (glc->latch_enabled)
  32125. + mutex_lock(&glc->latch_mutex);
  32126. +}
  32127. +
  32128. +static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable)
  32129. +{
  32130. + if (glc->latch_enabled)
  32131. + mutex_unlock(&glc->latch_mutex);
  32132. +
  32133. + if (disable)
  32134. + glc->latch_enabled = true;
  32135. +
  32136. + mutex_unlock(&glc->mutex);
  32137. +}
  32138. +
  32139. +static int
  32140. +gpio_latch_get(struct gpio_chip *gc, unsigned offset)
  32141. +{
  32142. + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
  32143. + int ret;
  32144. +
  32145. + gpio_latch_lock(glc, false);
  32146. + ret = gpio_get_value(glc->gpios[offset]);
  32147. + gpio_latch_unlock(glc, false);
  32148. +
  32149. + return ret;
  32150. +}
  32151. +
  32152. +static void
  32153. +gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value)
  32154. +{
  32155. + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
  32156. + bool enable_latch = false;
  32157. + bool disable_latch = false;
  32158. + int gpio;
  32159. +
  32160. + gpio = glc->gpios[offset];
  32161. +
  32162. + if (gpio == glc->le_gpio) {
  32163. + enable_latch = value ^ glc->le_active_low;
  32164. + disable_latch = !enable_latch;
  32165. + }
  32166. +
  32167. + gpio_latch_lock(glc, enable_latch);
  32168. + gpio_set_value(gpio, value);
  32169. + gpio_latch_unlock(glc, disable_latch);
  32170. +}
  32171. +
  32172. +static int
  32173. +gpio_latch_direction_input(struct gpio_chip *gc, unsigned offset)
  32174. +{
  32175. + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
  32176. + int ret;
  32177. +
  32178. + gpio_latch_lock(glc, false);
  32179. + ret = gpio_direction_input(glc->gpios[offset]);
  32180. + gpio_latch_unlock(glc, false);
  32181. +
  32182. + return ret;
  32183. +}
  32184. +
  32185. +static int
  32186. +gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value)
  32187. +{
  32188. + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
  32189. + bool enable_latch = false;
  32190. + bool disable_latch = false;
  32191. + int gpio;
  32192. + int ret;
  32193. +
  32194. + gpio = glc->gpios[offset];
  32195. +
  32196. + if (gpio == glc->le_gpio) {
  32197. + enable_latch = value ^ glc->le_active_low;
  32198. + disable_latch = !enable_latch;
  32199. + }
  32200. +
  32201. + gpio_latch_lock(glc, enable_latch);
  32202. + ret = gpio_direction_output(gpio, value);
  32203. + gpio_latch_unlock(glc, disable_latch);
  32204. +
  32205. + return ret;
  32206. +}
  32207. +
  32208. +static int gpio_latch_probe(struct platform_device *pdev)
  32209. +{
  32210. + struct gpio_latch_chip *glc;
  32211. + struct gpio_latch_platform_data *pdata;
  32212. + struct gpio_chip *gc;
  32213. + int size;
  32214. + int ret;
  32215. + int i;
  32216. +
  32217. + pdata = dev_get_platdata(&pdev->dev);
  32218. + if (!pdata)
  32219. + return -EINVAL;
  32220. +
  32221. + if (pdata->le_gpio_index >= pdata->num_gpios ||
  32222. + !pdata->num_gpios ||
  32223. + !pdata->gpios)
  32224. + return -EINVAL;
  32225. +
  32226. + for (i = 0; i < pdata->num_gpios; i++) {
  32227. + int gpio = pdata->gpios[i];
  32228. +
  32229. + ret = devm_gpio_request(&pdev->dev, gpio,
  32230. + GPIO_LATCH_DRIVER_NAME);
  32231. + if (ret)
  32232. + return ret;
  32233. + }
  32234. +
  32235. + glc = devm_kzalloc(&pdev->dev, sizeof(*glc), GFP_KERNEL);
  32236. + if (!glc)
  32237. + return -ENOMEM;
  32238. +
  32239. + mutex_init(&glc->mutex);
  32240. + mutex_init(&glc->latch_mutex);
  32241. +
  32242. + size = pdata->num_gpios * sizeof(glc->gpios[0]);
  32243. + glc->gpios = devm_kzalloc(&pdev->dev, size , GFP_KERNEL);
  32244. + if (!glc->gpios)
  32245. + return -ENOMEM;
  32246. +
  32247. + memcpy(glc->gpios, pdata->gpios, size);
  32248. +
  32249. + glc->le_gpio = glc->gpios[pdata->le_gpio_index];
  32250. + glc->le_active_low = pdata->le_active_low;
  32251. +
  32252. + gc = &glc->gc;
  32253. +
  32254. + gc->label = GPIO_LATCH_DRIVER_NAME;
  32255. + gc->base = pdata->base;
  32256. + gc->can_sleep = true;
  32257. + gc->ngpio = pdata->num_gpios;
  32258. + gc->get = gpio_latch_get;
  32259. + gc->set = gpio_latch_set;
  32260. + gc->direction_input = gpio_latch_direction_input,
  32261. + gc->direction_output = gpio_latch_direction_output;
  32262. +
  32263. + platform_set_drvdata(pdev, glc);
  32264. +
  32265. + ret = gpiochip_add(&glc->gc);
  32266. + if (ret)
  32267. + return ret;
  32268. +
  32269. + return 0;
  32270. +}
  32271. +
  32272. +static int gpio_latch_remove(struct platform_device *pdev)
  32273. +{
  32274. + struct gpio_latch_chip *glc = platform_get_drvdata(pdev);
  32275. +
  32276. + gpiochip_remove(&glc->gc);
  32277. + return 0;
  32278. +}
  32279. +
  32280. +
  32281. +static struct platform_driver gpio_latch_driver = {
  32282. + .probe = gpio_latch_probe,
  32283. + .remove = gpio_latch_remove,
  32284. + .driver = {
  32285. + .name = GPIO_LATCH_DRIVER_NAME,
  32286. + .owner = THIS_MODULE,
  32287. + },
  32288. +};
  32289. +
  32290. +static int __init gpio_latch_init(void)
  32291. +{
  32292. + return platform_driver_register(&gpio_latch_driver);
  32293. +}
  32294. +
  32295. +postcore_initcall(gpio_latch_init);
  32296. +
  32297. +MODULE_DESCRIPTION("GPIO latch driver");
  32298. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  32299. +MODULE_LICENSE("GPL v2");
  32300. +MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME);
  32301. diff -Nur linux-4.1.43.orig/drivers/gpio/gpio-nxp-74hc153.c linux-4.1.43/drivers/gpio/gpio-nxp-74hc153.c
  32302. --- linux-4.1.43.orig/drivers/gpio/gpio-nxp-74hc153.c 1970-01-01 01:00:00.000000000 +0100
  32303. +++ linux-4.1.43/drivers/gpio/gpio-nxp-74hc153.c 2017-08-06 20:02:15.000000000 +0200
  32304. @@ -0,0 +1,251 @@
  32305. +/*
  32306. + * NXP 74HC153 - Dual 4-input multiplexer GPIO driver
  32307. + *
  32308. + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  32309. + *
  32310. + * This program is free software; you can redistribute it and/or modify
  32311. + * it under the terms of the GNU General Public License version 2 as
  32312. + * published by the Free Software Foundation.
  32313. + */
  32314. +
  32315. +#include <linux/version.h>
  32316. +#include <linux/module.h>
  32317. +#include <linux/init.h>
  32318. +#include <linux/gpio.h>
  32319. +#include <linux/slab.h>
  32320. +#include <linux/platform_device.h>
  32321. +#include <linux/nxp_74hc153.h>
  32322. +
  32323. +#define NXP_74HC153_NUM_GPIOS 8
  32324. +#define NXP_74HC153_S0_MASK 0x1
  32325. +#define NXP_74HC153_S1_MASK 0x2
  32326. +#define NXP_74HC153_BANK_MASK 0x4
  32327. +
  32328. +struct nxp_74hc153_chip {
  32329. + struct device *parent;
  32330. + struct gpio_chip gpio_chip;
  32331. + struct mutex lock;
  32332. +};
  32333. +
  32334. +static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc)
  32335. +{
  32336. + return container_of(gc, struct nxp_74hc153_chip, gpio_chip);
  32337. +}
  32338. +
  32339. +static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset)
  32340. +{
  32341. + return 0;
  32342. +}
  32343. +
  32344. +static int nxp_74hc153_direction_output(struct gpio_chip *gc,
  32345. + unsigned offset, int val)
  32346. +{
  32347. + return -EINVAL;
  32348. +}
  32349. +
  32350. +static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset)
  32351. +{
  32352. + struct nxp_74hc153_chip *nxp;
  32353. + struct nxp_74hc153_platform_data *pdata;
  32354. + unsigned s0;
  32355. + unsigned s1;
  32356. + unsigned pin;
  32357. + int ret;
  32358. +
  32359. + nxp = gpio_to_nxp(gc);
  32360. + pdata = nxp->parent->platform_data;
  32361. +
  32362. + s0 = !!(offset & NXP_74HC153_S0_MASK);
  32363. + s1 = !!(offset & NXP_74HC153_S1_MASK);
  32364. + pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y
  32365. + : pdata->gpio_pin_1y;
  32366. +
  32367. + mutex_lock(&nxp->lock);
  32368. + gpio_set_value(pdata->gpio_pin_s0, s0);
  32369. + gpio_set_value(pdata->gpio_pin_s1, s1);
  32370. + ret = gpio_get_value(pin);
  32371. + mutex_unlock(&nxp->lock);
  32372. +
  32373. + return ret;
  32374. +}
  32375. +
  32376. +static void nxp_74hc153_set_value(struct gpio_chip *gc,
  32377. + unsigned offset, int val)
  32378. +{
  32379. + /* not supported */
  32380. +}
  32381. +
  32382. +static int nxp_74hc153_probe(struct platform_device *pdev)
  32383. +{
  32384. + struct nxp_74hc153_platform_data *pdata;
  32385. + struct nxp_74hc153_chip *nxp;
  32386. + struct gpio_chip *gc;
  32387. + int err;
  32388. +
  32389. + pdata = pdev->dev.platform_data;
  32390. + if (pdata == NULL) {
  32391. + dev_dbg(&pdev->dev, "no platform data specified\n");
  32392. + return -EINVAL;
  32393. + }
  32394. +
  32395. + nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL);
  32396. + if (nxp == NULL) {
  32397. + dev_err(&pdev->dev, "no memory for private data\n");
  32398. + return -ENOMEM;
  32399. + }
  32400. +
  32401. + err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev));
  32402. + if (err) {
  32403. + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n",
  32404. + pdata->gpio_pin_s0, err);
  32405. + goto err_free_nxp;
  32406. + }
  32407. +
  32408. + err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev));
  32409. + if (err) {
  32410. + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n",
  32411. + pdata->gpio_pin_s1, err);
  32412. + goto err_free_s0;
  32413. + }
  32414. +
  32415. + err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev));
  32416. + if (err) {
  32417. + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n",
  32418. + pdata->gpio_pin_1y, err);
  32419. + goto err_free_s1;
  32420. + }
  32421. +
  32422. + err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev));
  32423. + if (err) {
  32424. + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n",
  32425. + pdata->gpio_pin_2y, err);
  32426. + goto err_free_1y;
  32427. + }
  32428. +
  32429. + err = gpio_direction_output(pdata->gpio_pin_s0, 0);
  32430. + if (err) {
  32431. + dev_err(&pdev->dev,
  32432. + "unable to set direction of gpio %u, err=%d\n",
  32433. + pdata->gpio_pin_s0, err);
  32434. + goto err_free_2y;
  32435. + }
  32436. +
  32437. + err = gpio_direction_output(pdata->gpio_pin_s1, 0);
  32438. + if (err) {
  32439. + dev_err(&pdev->dev,
  32440. + "unable to set direction of gpio %u, err=%d\n",
  32441. + pdata->gpio_pin_s1, err);
  32442. + goto err_free_2y;
  32443. + }
  32444. +
  32445. + err = gpio_direction_input(pdata->gpio_pin_1y);
  32446. + if (err) {
  32447. + dev_err(&pdev->dev,
  32448. + "unable to set direction of gpio %u, err=%d\n",
  32449. + pdata->gpio_pin_1y, err);
  32450. + goto err_free_2y;
  32451. + }
  32452. +
  32453. + err = gpio_direction_input(pdata->gpio_pin_2y);
  32454. + if (err) {
  32455. + dev_err(&pdev->dev,
  32456. + "unable to set direction of gpio %u, err=%d\n",
  32457. + pdata->gpio_pin_2y, err);
  32458. + goto err_free_2y;
  32459. + }
  32460. +
  32461. + nxp->parent = &pdev->dev;
  32462. + mutex_init(&nxp->lock);
  32463. +
  32464. + gc = &nxp->gpio_chip;
  32465. +
  32466. + gc->direction_input = nxp_74hc153_direction_input;
  32467. + gc->direction_output = nxp_74hc153_direction_output;
  32468. + gc->get = nxp_74hc153_get_value;
  32469. + gc->set = nxp_74hc153_set_value;
  32470. + gc->can_sleep = 1;
  32471. +
  32472. + gc->base = pdata->gpio_base;
  32473. + gc->ngpio = NXP_74HC153_NUM_GPIOS;
  32474. + gc->label = dev_name(nxp->parent);
  32475. + gc->dev = nxp->parent;
  32476. + gc->owner = THIS_MODULE;
  32477. +
  32478. + err = gpiochip_add(&nxp->gpio_chip);
  32479. + if (err) {
  32480. + dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err);
  32481. + goto err_free_2y;
  32482. + }
  32483. +
  32484. + platform_set_drvdata(pdev, nxp);
  32485. + return 0;
  32486. +
  32487. +err_free_2y:
  32488. + gpio_free(pdata->gpio_pin_2y);
  32489. +err_free_1y:
  32490. + gpio_free(pdata->gpio_pin_1y);
  32491. +err_free_s1:
  32492. + gpio_free(pdata->gpio_pin_s1);
  32493. +err_free_s0:
  32494. + gpio_free(pdata->gpio_pin_s0);
  32495. +err_free_nxp:
  32496. + kfree(nxp);
  32497. + return err;
  32498. +}
  32499. +
  32500. +static int nxp_74hc153_remove(struct platform_device *pdev)
  32501. +{
  32502. + struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev);
  32503. + struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data;
  32504. +
  32505. + if (nxp) {
  32506. +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
  32507. + int err;
  32508. +
  32509. + err = gpiochip_remove(&nxp->gpio_chip);
  32510. + if (err) {
  32511. + dev_err(&pdev->dev,
  32512. + "unable to remove gpio chip, err=%d\n",
  32513. + err);
  32514. + return err;
  32515. + }
  32516. +#else
  32517. + gpiochip_remove(&nxp->gpio_chip);
  32518. +#endif
  32519. + gpio_free(pdata->gpio_pin_2y);
  32520. + gpio_free(pdata->gpio_pin_1y);
  32521. + gpio_free(pdata->gpio_pin_s1);
  32522. + gpio_free(pdata->gpio_pin_s0);
  32523. +
  32524. + kfree(nxp);
  32525. + platform_set_drvdata(pdev, NULL);
  32526. + }
  32527. +
  32528. + return 0;
  32529. +}
  32530. +
  32531. +static struct platform_driver nxp_74hc153_driver = {
  32532. + .probe = nxp_74hc153_probe,
  32533. + .remove = nxp_74hc153_remove,
  32534. + .driver = {
  32535. + .name = NXP_74HC153_DRIVER_NAME,
  32536. + .owner = THIS_MODULE,
  32537. + },
  32538. +};
  32539. +
  32540. +static int __init nxp_74hc153_init(void)
  32541. +{
  32542. + return platform_driver_register(&nxp_74hc153_driver);
  32543. +}
  32544. +subsys_initcall(nxp_74hc153_init);
  32545. +
  32546. +static void __exit nxp_74hc153_exit(void)
  32547. +{
  32548. + platform_driver_unregister(&nxp_74hc153_driver);
  32549. +}
  32550. +module_exit(nxp_74hc153_exit);
  32551. +
  32552. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  32553. +MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153");
  32554. +MODULE_LICENSE("GPL v2");
  32555. +MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME);
  32556. diff -Nur linux-4.1.43.orig/drivers/leds/Kconfig linux-4.1.43/drivers/leds/Kconfig
  32557. --- linux-4.1.43.orig/drivers/leds/Kconfig 2017-08-06 01:56:14.000000000 +0200
  32558. +++ linux-4.1.43/drivers/leds/Kconfig 2017-08-06 20:02:16.000000000 +0200
  32559. @@ -534,6 +534,17 @@
  32560. This option enables support for the 'White' LED block
  32561. on Qualcomm PM8941 PMICs.
  32562. +config LEDS_WNDR3700_USB
  32563. + tristate "NETGEAR WNDR3700 USB LED driver"
  32564. + depends on LEDS_CLASS && ATH79_MACH_WNDR3700
  32565. + help
  32566. + This option enables support for the USB LED found on the
  32567. + NETGEAR WNDR3700 board.
  32568. +
  32569. +config LEDS_RB750
  32570. + tristate "LED driver for the Mikrotik RouterBOARD 750"
  32571. + depends on LEDS_CLASS && ATH79_MACH_RB750
  32572. +
  32573. comment "LED Triggers"
  32574. source "drivers/leds/trigger/Kconfig"
  32575. diff -Nur linux-4.1.43.orig/drivers/leds/Makefile linux-4.1.43/drivers/leds/Makefile
  32576. --- linux-4.1.43.orig/drivers/leds/Makefile 2017-08-06 01:56:14.000000000 +0200
  32577. +++ linux-4.1.43/drivers/leds/Makefile 2017-08-06 20:02:16.000000000 +0200
  32578. @@ -43,12 +43,14 @@
  32579. obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
  32580. obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
  32581. obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
  32582. +obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o
  32583. obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
  32584. obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
  32585. obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
  32586. obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o
  32587. obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o
  32588. obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o
  32589. +obj-$(CONFIG_LEDS_RB750) += leds-rb750.o
  32590. obj-$(CONFIG_LEDS_NS2) += leds-ns2.o
  32591. obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o
  32592. obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o
  32593. diff -Nur linux-4.1.43.orig/drivers/leds/leds-rb750.c linux-4.1.43/drivers/leds/leds-rb750.c
  32594. --- linux-4.1.43.orig/drivers/leds/leds-rb750.c 1970-01-01 01:00:00.000000000 +0100
  32595. +++ linux-4.1.43/drivers/leds/leds-rb750.c 2017-08-06 20:02:16.000000000 +0200
  32596. @@ -0,0 +1,144 @@
  32597. +/*
  32598. + * LED driver for the RouterBOARD 750
  32599. + *
  32600. + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  32601. + *
  32602. + * This program is free software; you can redistribute it and/or modify
  32603. + * it under the terms of the GNU General Public License version 2 as
  32604. + * published by the Free Software Foundation.
  32605. + *
  32606. + */
  32607. +#include <linux/kernel.h>
  32608. +#include <linux/module.h>
  32609. +#include <linux/init.h>
  32610. +#include <linux/platform_device.h>
  32611. +#include <linux/leds.h>
  32612. +#include <linux/slab.h>
  32613. +
  32614. +#include <asm/mach-ath79/mach-rb750.h>
  32615. +
  32616. +#define DRV_NAME "leds-rb750"
  32617. +
  32618. +struct rb750_led_dev {
  32619. + struct led_classdev cdev;
  32620. + u32 mask;
  32621. + int active_low;
  32622. + void (*latch_change)(u32 clear, u32 set);
  32623. +};
  32624. +
  32625. +struct rb750_led_drvdata {
  32626. + struct rb750_led_dev *led_devs;
  32627. + int num_leds;
  32628. +};
  32629. +
  32630. +static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev)
  32631. +{
  32632. + return (struct rb750_led_dev *)container_of(led_cdev,
  32633. + struct rb750_led_dev, cdev);
  32634. +}
  32635. +
  32636. +static void rb750_led_brightness_set(struct led_classdev *led_cdev,
  32637. + enum led_brightness value)
  32638. +{
  32639. + struct rb750_led_dev *rbled = to_rbled(led_cdev);
  32640. + int level;
  32641. +
  32642. + level = (value == LED_OFF) ? 0 : 1;
  32643. + level ^= rbled->active_low;
  32644. +
  32645. + if (level)
  32646. + rbled->latch_change(0, rbled->mask);
  32647. + else
  32648. + rbled->latch_change(rbled->mask, 0);
  32649. +}
  32650. +
  32651. +static int rb750_led_probe(struct platform_device *pdev)
  32652. +{
  32653. + struct rb750_led_platform_data *pdata;
  32654. + struct rb750_led_drvdata *drvdata;
  32655. + int ret = 0;
  32656. + int i;
  32657. +
  32658. + pdata = pdev->dev.platform_data;
  32659. + if (!pdata)
  32660. + return -EINVAL;
  32661. +
  32662. + drvdata = kzalloc(sizeof(struct rb750_led_drvdata) +
  32663. + sizeof(struct rb750_led_dev) * pdata->num_leds,
  32664. + GFP_KERNEL);
  32665. + if (!drvdata)
  32666. + return -ENOMEM;
  32667. +
  32668. + drvdata->num_leds = pdata->num_leds;
  32669. + drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1];
  32670. +
  32671. + for (i = 0; i < drvdata->num_leds; i++) {
  32672. + struct rb750_led_dev *rbled = &drvdata->led_devs[i];
  32673. + struct rb750_led_data *led_data = &pdata->leds[i];
  32674. +
  32675. + rbled->cdev.name = led_data->name;
  32676. + rbled->cdev.default_trigger = led_data->default_trigger;
  32677. + rbled->cdev.brightness_set = rb750_led_brightness_set;
  32678. + rbled->cdev.brightness = LED_OFF;
  32679. +
  32680. + rbled->mask = led_data->mask;
  32681. + rbled->active_low = !!led_data->active_low;
  32682. + rbled->latch_change = pdata->latch_change;
  32683. +
  32684. + ret = led_classdev_register(&pdev->dev, &rbled->cdev);
  32685. + if (ret)
  32686. + goto err;
  32687. + }
  32688. +
  32689. + platform_set_drvdata(pdev, drvdata);
  32690. + return 0;
  32691. +
  32692. +err:
  32693. + for (i = i - 1; i >= 0; i--)
  32694. + led_classdev_unregister(&drvdata->led_devs[i].cdev);
  32695. +
  32696. + kfree(drvdata);
  32697. + return ret;
  32698. +}
  32699. +
  32700. +static int rb750_led_remove(struct platform_device *pdev)
  32701. +{
  32702. + struct rb750_led_drvdata *drvdata;
  32703. + int i;
  32704. +
  32705. + drvdata = platform_get_drvdata(pdev);
  32706. + for (i = 0; i < drvdata->num_leds; i++)
  32707. + led_classdev_unregister(&drvdata->led_devs[i].cdev);
  32708. +
  32709. + kfree(drvdata);
  32710. + return 0;
  32711. +}
  32712. +
  32713. +static struct platform_driver rb750_led_driver = {
  32714. + .probe = rb750_led_probe,
  32715. + .remove = rb750_led_remove,
  32716. + .driver = {
  32717. + .name = DRV_NAME,
  32718. + .owner = THIS_MODULE,
  32719. + },
  32720. +};
  32721. +
  32722. +MODULE_ALIAS("platform:leds-rb750");
  32723. +
  32724. +static int __init rb750_led_init(void)
  32725. +{
  32726. + return platform_driver_register(&rb750_led_driver);
  32727. +}
  32728. +
  32729. +static void __exit rb750_led_exit(void)
  32730. +{
  32731. + platform_driver_unregister(&rb750_led_driver);
  32732. +}
  32733. +
  32734. +module_init(rb750_led_init);
  32735. +module_exit(rb750_led_exit);
  32736. +
  32737. +MODULE_DESCRIPTION(DRV_NAME);
  32738. +MODULE_DESCRIPTION("LED driver for the RouterBOARD 750");
  32739. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  32740. +MODULE_LICENSE("GPL v2");
  32741. diff -Nur linux-4.1.43.orig/drivers/leds/leds-wndr3700-usb.c linux-4.1.43/drivers/leds/leds-wndr3700-usb.c
  32742. --- linux-4.1.43.orig/drivers/leds/leds-wndr3700-usb.c 1970-01-01 01:00:00.000000000 +0100
  32743. +++ linux-4.1.43/drivers/leds/leds-wndr3700-usb.c 2017-08-06 20:02:16.000000000 +0200
  32744. @@ -0,0 +1,76 @@
  32745. +/*
  32746. + * USB LED driver for the NETGEAR WNDR3700
  32747. + *
  32748. + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  32749. + *
  32750. + * This program is free software; you can redistribute it and/or modify it
  32751. + * under the terms of the GNU General Public License version 2 as published
  32752. + * by the Free Software Foundation.
  32753. + */
  32754. +
  32755. +#include <linux/leds.h>
  32756. +#include <linux/module.h>
  32757. +#include <linux/platform_device.h>
  32758. +
  32759. +#include <asm/mach-ath79/ar71xx_regs.h>
  32760. +#include <asm/mach-ath79/ath79.h>
  32761. +
  32762. +#define DRIVER_NAME "wndr3700-led-usb"
  32763. +
  32764. +static void wndr3700_usb_led_set(struct led_classdev *cdev,
  32765. + enum led_brightness brightness)
  32766. +{
  32767. + if (brightness)
  32768. + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
  32769. + else
  32770. + ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
  32771. +}
  32772. +
  32773. +static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev)
  32774. +{
  32775. + return ath79_device_reset_get(AR71XX_RESET_GE1_PHY) ? LED_OFF : LED_FULL;
  32776. +}
  32777. +
  32778. +static struct led_classdev wndr3700_usb_led = {
  32779. + .name = "netgear:green:usb",
  32780. + .brightness_set = wndr3700_usb_led_set,
  32781. + .brightness_get = wndr3700_usb_led_get,
  32782. +};
  32783. +
  32784. +static int wndr3700_usb_led_probe(struct platform_device *pdev)
  32785. +{
  32786. + return led_classdev_register(&pdev->dev, &wndr3700_usb_led);
  32787. +}
  32788. +
  32789. +static int wndr3700_usb_led_remove(struct platform_device *pdev)
  32790. +{
  32791. + led_classdev_unregister(&wndr3700_usb_led);
  32792. + return 0;
  32793. +}
  32794. +
  32795. +static struct platform_driver wndr3700_usb_led_driver = {
  32796. + .probe = wndr3700_usb_led_probe,
  32797. + .remove = wndr3700_usb_led_remove,
  32798. + .driver = {
  32799. + .name = DRIVER_NAME,
  32800. + .owner = THIS_MODULE,
  32801. + },
  32802. +};
  32803. +
  32804. +static int __init wndr3700_usb_led_init(void)
  32805. +{
  32806. + return platform_driver_register(&wndr3700_usb_led_driver);
  32807. +}
  32808. +
  32809. +static void __exit wndr3700_usb_led_exit(void)
  32810. +{
  32811. + platform_driver_unregister(&wndr3700_usb_led_driver);
  32812. +}
  32813. +
  32814. +module_init(wndr3700_usb_led_init);
  32815. +module_exit(wndr3700_usb_led_exit);
  32816. +
  32817. +MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700");
  32818. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  32819. +MODULE_LICENSE("GPL v2");
  32820. +MODULE_ALIAS("platform:" DRIVER_NAME);
  32821. diff -Nur linux-4.1.43.orig/drivers/mtd/Kconfig linux-4.1.43/drivers/mtd/Kconfig
  32822. --- linux-4.1.43.orig/drivers/mtd/Kconfig 2017-08-06 01:56:14.000000000 +0200
  32823. +++ linux-4.1.43/drivers/mtd/Kconfig 2017-08-06 20:02:16.000000000 +0200
  32824. @@ -155,6 +155,12 @@
  32825. This provides partitions parser for devices based on BCM47xx
  32826. boards.
  32827. +config MTD_TPLINK_PARTS
  32828. + tristate "TP-Link AR7XXX/AR9XXX partitioning support"
  32829. + depends on ATH79
  32830. + ---help---
  32831. + TBD.
  32832. +
  32833. comment "User Modules And Translation Layers"
  32834. #
  32835. diff -Nur linux-4.1.43.orig/drivers/mtd/chips/cfi_cmdset_0002.c linux-4.1.43/drivers/mtd/chips/cfi_cmdset_0002.c
  32836. --- linux-4.1.43.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2017-08-06 01:56:14.000000000 +0200
  32837. +++ linux-4.1.43/drivers/mtd/chips/cfi_cmdset_0002.c 2017-08-06 20:02:16.000000000 +0200
  32838. @@ -40,7 +40,7 @@
  32839. #include <linux/mtd/xip.h>
  32840. #define AMD_BOOTLOC_BUG
  32841. -#define FORCE_WORD_WRITE 0
  32842. +#define FORCE_WORD_WRITE 1
  32843. #define MAX_WORD_RETRIES 3
  32844. @@ -51,7 +51,9 @@
  32845. static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
  32846. static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
  32847. +#if !FORCE_WORD_WRITE
  32848. static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
  32849. +#endif
  32850. static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
  32851. static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
  32852. static void cfi_amdstd_sync (struct mtd_info *);
  32853. @@ -202,6 +204,7 @@
  32854. }
  32855. #endif
  32856. +#if !FORCE_WORD_WRITE
  32857. static void fixup_use_write_buffers(struct mtd_info *mtd)
  32858. {
  32859. struct map_info *map = mtd->priv;
  32860. @@ -211,6 +214,7 @@
  32861. mtd->_write = cfi_amdstd_write_buffers;
  32862. }
  32863. }
  32864. +#endif /* !FORCE_WORD_WRITE */
  32865. /* Atmel chips don't use the same PRI format as AMD chips */
  32866. static void fixup_convert_atmel_pri(struct mtd_info *mtd)
  32867. @@ -1632,8 +1636,8 @@
  32868. break;
  32869. }
  32870. - if (chip_ready(map, adr))
  32871. - break;
  32872. + if (chip_good(map, adr, datum))
  32873. + goto enable_xip;
  32874. /* Latency issues. Drop the lock, wait a while and retry */
  32875. UDELAY(map, chip, adr, 1);
  32876. @@ -1649,6 +1653,8 @@
  32877. ret = -EIO;
  32878. }
  32879. +
  32880. + enable_xip:
  32881. xip_enable(map, chip, adr);
  32882. op_done:
  32883. if (mode == FL_OTP_WRITE)
  32884. @@ -1789,6 +1795,7 @@
  32885. /*
  32886. * FIXME: interleaved mode not tested, and probably not supported!
  32887. */
  32888. +#if !FORCE_WORD_WRITE
  32889. static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
  32890. unsigned long adr, const u_char *buf,
  32891. int len)
  32892. @@ -1916,7 +1923,6 @@
  32893. return ret;
  32894. }
  32895. -
  32896. static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
  32897. size_t *retlen, const u_char *buf)
  32898. {
  32899. @@ -1991,6 +1997,7 @@
  32900. return 0;
  32901. }
  32902. +#endif /* !FORCE_WORD_WRITE */
  32903. /*
  32904. * Wait for the flash chip to become ready to write data
  32905. @@ -2226,7 +2233,6 @@
  32906. return 0;
  32907. }
  32908. -
  32909. /*
  32910. * Handle devices with one erase region, that only implement
  32911. * the chip erase command.
  32912. @@ -2290,8 +2296,8 @@
  32913. chip->erase_suspended = 0;
  32914. }
  32915. - if (chip_ready(map, adr))
  32916. - break;
  32917. + if (chip_good(map, adr, map_word_ff(map)))
  32918. + goto op_done;
  32919. if (time_after(jiffies, timeo)) {
  32920. printk(KERN_WARNING "MTD %s(): software timeout\n",
  32921. @@ -2311,6 +2317,7 @@
  32922. ret = -EIO;
  32923. }
  32924. + op_done:
  32925. chip->state = FL_READY;
  32926. xip_enable(map, chip, adr);
  32927. DISABLE_VPP(map);
  32928. @@ -2379,9 +2386,9 @@
  32929. chip->erase_suspended = 0;
  32930. }
  32931. - if (chip_ready(map, adr)) {
  32932. + if (chip_good(map, adr, map_word_ff(map))) {
  32933. xip_enable(map, chip, adr);
  32934. - break;
  32935. + goto op_done;
  32936. }
  32937. if (time_after(jiffies, timeo)) {
  32938. @@ -2403,6 +2410,7 @@
  32939. ret = -EIO;
  32940. }
  32941. + op_done:
  32942. chip->state = FL_READY;
  32943. DISABLE_VPP(map);
  32944. put_chip(map, chip, adr);
  32945. diff -Nur linux-4.1.43.orig/drivers/mtd/chips/jedec_probe.c linux-4.1.43/drivers/mtd/chips/jedec_probe.c
  32946. --- linux-4.1.43.orig/drivers/mtd/chips/jedec_probe.c 2017-08-06 01:56:14.000000000 +0200
  32947. +++ linux-4.1.43/drivers/mtd/chips/jedec_probe.c 2017-08-06 20:02:16.000000000 +0200
  32948. @@ -148,6 +148,7 @@
  32949. #define SST39LF160 0x2782
  32950. #define SST39VF1601 0x234b
  32951. #define SST39VF3201 0x235b
  32952. +#define SST39VF6401B 0x236d
  32953. #define SST39WF1601 0x274b
  32954. #define SST39WF1602 0x274a
  32955. #define SST39LF512 0x00D4
  32956. @@ -1569,6 +1570,18 @@
  32957. ERASEINFO(0x10000,64),
  32958. }
  32959. }, {
  32960. + .mfr_id = CFI_MFR_SST,
  32961. + .dev_id = SST39VF6401B,
  32962. + .name = "SST 39VF6401B",
  32963. + .devtypes = CFI_DEVICETYPE_X16,
  32964. + .uaddr = MTD_UADDR_0xAAAA_0x5555,
  32965. + .dev_size = SIZE_8MiB,
  32966. + .cmd_set = P_ID_AMD_STD,
  32967. + .nr_regions = 1,
  32968. + .regions = {
  32969. + ERASEINFO(0x10000,128)
  32970. + }
  32971. + }, {
  32972. .mfr_id = CFI_MFR_ST,
  32973. .dev_id = M29F800AB,
  32974. .name = "ST M29F800AB",
  32975. diff -Nur linux-4.1.43.orig/drivers/mtd/cybertan_part.c linux-4.1.43/drivers/mtd/cybertan_part.c
  32976. --- linux-4.1.43.orig/drivers/mtd/cybertan_part.c 1970-01-01 01:00:00.000000000 +0100
  32977. +++ linux-4.1.43/drivers/mtd/cybertan_part.c 2017-08-06 20:02:16.000000000 +0200
  32978. @@ -0,0 +1,201 @@
  32979. +/*
  32980. + * Copyright (C) 2009 Christian Daniel <cd@maintech.de>
  32981. + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  32982. + *
  32983. + * This program is free software; you can redistribute it and/or modify
  32984. + * it under the terms of the GNU General Public License as published by
  32985. + * the Free Software Foundation; either version 2 of the License, or
  32986. + * (at your option) any later version.
  32987. + *
  32988. + * This program is distributed in the hope that it will be useful,
  32989. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32990. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  32991. + * GNU General Public License for more details.
  32992. + *
  32993. + * You should have received a copy of the GNU General Public License
  32994. + * along with this program; if not, write to the Free Software
  32995. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  32996. + *
  32997. + * TRX flash partition table.
  32998. + * Based on ar7 map by Felix Fietkau <nbd@openwrt.org>
  32999. + *
  33000. + */
  33001. +
  33002. +#include <linux/kernel.h>
  33003. +#include <linux/module.h>
  33004. +#include <linux/slab.h>
  33005. +#include <linux/vmalloc.h>
  33006. +
  33007. +#include <linux/mtd/mtd.h>
  33008. +#include <linux/mtd/partitions.h>
  33009. +
  33010. +struct cybertan_header {
  33011. + char magic[4];
  33012. + u8 res1[4];
  33013. + char fw_date[3];
  33014. + char fw_ver[3];
  33015. + char id[4];
  33016. + char hw_ver;
  33017. + char unused;
  33018. + u8 flags[2];
  33019. + u8 res2[10];
  33020. +};
  33021. +
  33022. +#define TRX_PARTS 6
  33023. +#define TRX_MAGIC 0x30524448
  33024. +#define TRX_MAX_OFFSET 3
  33025. +
  33026. +struct trx_header {
  33027. + uint32_t magic; /* "HDR0" */
  33028. + uint32_t len; /* Length of file including header */
  33029. + uint32_t crc32; /* 32-bit CRC from flag_version to end of file */
  33030. + uint32_t flag_version; /* 0:15 flags, 16:31 version */
  33031. + uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
  33032. +};
  33033. +
  33034. +#define IH_MAGIC 0x27051956 /* Image Magic Number */
  33035. +#define IH_NMLEN 32 /* Image Name Length */
  33036. +
  33037. +struct uimage_header {
  33038. + uint32_t ih_magic; /* Image Header Magic Number */
  33039. + uint32_t ih_hcrc; /* Image Header CRC Checksum */
  33040. + uint32_t ih_time; /* Image Creation Timestamp */
  33041. + uint32_t ih_size; /* Image Data Size */
  33042. + uint32_t ih_load; /* Data» Load Address */
  33043. + uint32_t ih_ep; /* Entry Point Address */
  33044. + uint32_t ih_dcrc; /* Image Data CRC Checksum */
  33045. + uint8_t ih_os; /* Operating System */
  33046. + uint8_t ih_arch; /* CPU architecture */
  33047. + uint8_t ih_type; /* Image Type */
  33048. + uint8_t ih_comp; /* Compression Type */
  33049. + uint8_t ih_name[IH_NMLEN]; /* Image Name */
  33050. +};
  33051. +
  33052. +struct firmware_header {
  33053. + struct cybertan_header cybertan;
  33054. + struct trx_header trx;
  33055. + struct uimage_header uimage;
  33056. +} __packed;
  33057. +
  33058. +#define UBOOT_LEN 0x40000
  33059. +#define ART_LEN 0x10000
  33060. +#define NVRAM_LEN 0x10000
  33061. +
  33062. +static int cybertan_parse_partitions(struct mtd_info *master,
  33063. + struct mtd_partition **pparts,
  33064. + struct mtd_part_parser_data *data)
  33065. +{
  33066. + struct firmware_header *header;
  33067. + struct trx_header *theader;
  33068. + struct uimage_header *uheader;
  33069. + struct mtd_partition *trx_parts;
  33070. + size_t retlen;
  33071. + unsigned int kernel_len;
  33072. + unsigned int uboot_len;
  33073. + unsigned int nvram_len;
  33074. + unsigned int art_len;
  33075. + int ret;
  33076. +
  33077. + uboot_len = max_t(unsigned int, master->erasesize, UBOOT_LEN);
  33078. + nvram_len = max_t(unsigned int, master->erasesize, NVRAM_LEN);
  33079. + art_len = max_t(unsigned int, master->erasesize, ART_LEN);
  33080. +
  33081. + trx_parts = kzalloc(TRX_PARTS * sizeof(struct mtd_partition),
  33082. + GFP_KERNEL);
  33083. + if (!trx_parts) {
  33084. + ret = -ENOMEM;
  33085. + goto out;
  33086. + }
  33087. +
  33088. + header = vmalloc(sizeof(*header));
  33089. + if (!header) {
  33090. + return -ENOMEM;
  33091. + goto free_parts;
  33092. + }
  33093. +
  33094. + ret = mtd_read(master, uboot_len, sizeof(*header),
  33095. + &retlen, (void *) header);
  33096. + if (ret)
  33097. + goto free_hdr;
  33098. +
  33099. + if (retlen != sizeof(*header)) {
  33100. + ret = -EIO;
  33101. + goto free_hdr;
  33102. + }
  33103. +
  33104. + theader = &header->trx;
  33105. + if (le32_to_cpu(theader->magic) != TRX_MAGIC) {
  33106. + printk(KERN_NOTICE "%s: no TRX header found\n", master->name);
  33107. + goto free_hdr;
  33108. + }
  33109. +
  33110. + uheader = &header->uimage;
  33111. + if (uheader->ih_magic != IH_MAGIC) {
  33112. + printk(KERN_NOTICE "%s: no uImage found\n", master->name);
  33113. + goto free_hdr;
  33114. + }
  33115. +
  33116. + kernel_len = le32_to_cpu(theader->offsets[1]) +
  33117. + sizeof(struct cybertan_header);
  33118. +
  33119. + trx_parts[0].name = "u-boot";
  33120. + trx_parts[0].offset = 0;
  33121. + trx_parts[0].size = uboot_len;
  33122. + trx_parts[0].mask_flags = MTD_WRITEABLE;
  33123. +
  33124. + trx_parts[1].name = "kernel";
  33125. + trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;
  33126. + trx_parts[1].size = kernel_len;
  33127. + trx_parts[1].mask_flags = 0;
  33128. +
  33129. + trx_parts[2].name = "rootfs";
  33130. + trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
  33131. + trx_parts[2].size = master->size - uboot_len - nvram_len - art_len -
  33132. + trx_parts[1].size;
  33133. + trx_parts[2].mask_flags = 0;
  33134. +
  33135. + trx_parts[3].name = "nvram";
  33136. + trx_parts[3].offset = master->size - nvram_len - art_len;
  33137. + trx_parts[3].size = nvram_len;
  33138. + trx_parts[3].mask_flags = MTD_WRITEABLE;
  33139. +
  33140. + trx_parts[4].name = "art";
  33141. + trx_parts[4].offset = master->size - art_len;
  33142. + trx_parts[4].size = art_len;
  33143. + trx_parts[4].mask_flags = MTD_WRITEABLE;
  33144. +
  33145. + trx_parts[5].name = "firmware";
  33146. + trx_parts[5].offset = uboot_len;
  33147. + trx_parts[5].size = master->size - uboot_len - nvram_len - art_len;
  33148. + trx_parts[5].mask_flags = 0;
  33149. +
  33150. + vfree(header);
  33151. +
  33152. + *pparts = trx_parts;
  33153. + return TRX_PARTS;
  33154. +
  33155. +free_hdr:
  33156. + vfree(header);
  33157. +free_parts:
  33158. + kfree(trx_parts);
  33159. +out:
  33160. + return ret;
  33161. +}
  33162. +
  33163. +static struct mtd_part_parser cybertan_parser = {
  33164. + .owner = THIS_MODULE,
  33165. + .parse_fn = cybertan_parse_partitions,
  33166. + .name = "cybertan",
  33167. +};
  33168. +
  33169. +static int __init cybertan_parser_init(void)
  33170. +{
  33171. + register_mtd_parser(&cybertan_parser);
  33172. +
  33173. + return 0;
  33174. +}
  33175. +
  33176. +module_init(cybertan_parser_init);
  33177. +
  33178. +MODULE_LICENSE("GPL");
  33179. +MODULE_AUTHOR("Christian Daniel <cd@maintech.de>");
  33180. diff -Nur linux-4.1.43.orig/drivers/mtd/devices/m25p80.c linux-4.1.43/drivers/mtd/devices/m25p80.c
  33181. --- linux-4.1.43.orig/drivers/mtd/devices/m25p80.c 2017-08-06 01:56:14.000000000 +0200
  33182. +++ linux-4.1.43/drivers/mtd/devices/m25p80.c 2017-08-06 20:02:16.000000000 +0200
  33183. @@ -139,10 +139,15 @@
  33184. flash->command[0] = nor->read_opcode;
  33185. m25p_addr2cmd(nor, from, flash->command);
  33186. + if (dummy == 1)
  33187. + t[0].dummy = true;
  33188. +
  33189. + t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
  33190. t[0].tx_buf = flash->command;
  33191. t[0].len = m25p_cmdsz(nor) + dummy;
  33192. spi_message_add_tail(&t[0], &m);
  33193. + t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
  33194. t[1].rx_buf = buf;
  33195. t[1].rx_nbits = m25p80_rx_nbits(nor);
  33196. t[1].len = len;
  33197. @@ -232,6 +237,7 @@
  33198. if (ret)
  33199. return ret;
  33200. + memset(&ppdata, '\0', sizeof(ppdata));
  33201. ppdata.of_node = spi->dev.of_node;
  33202. return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
  33203. diff -Nur linux-4.1.43.orig/drivers/mtd/maps/physmap.c linux-4.1.43/drivers/mtd/maps/physmap.c
  33204. --- linux-4.1.43.orig/drivers/mtd/maps/physmap.c 2017-08-06 01:56:14.000000000 +0200
  33205. +++ linux-4.1.43/drivers/mtd/maps/physmap.c 2017-08-06 20:02:16.000000000 +0200
  33206. @@ -31,6 +31,66 @@
  33207. int vpp_refcnt;
  33208. };
  33209. +static struct platform_device *physmap_map2pdev(struct map_info *map)
  33210. +{
  33211. + return (struct platform_device *) map->map_priv_1;
  33212. +}
  33213. +
  33214. +static void physmap_lock(struct map_info *map)
  33215. +{
  33216. + struct platform_device *pdev;
  33217. + struct physmap_flash_data *physmap_data;
  33218. +
  33219. + pdev = physmap_map2pdev(map);
  33220. + physmap_data = pdev->dev.platform_data;
  33221. + physmap_data->lock(pdev);
  33222. +}
  33223. +
  33224. +static void physmap_unlock(struct map_info *map)
  33225. +{
  33226. + struct platform_device *pdev;
  33227. + struct physmap_flash_data *physmap_data;
  33228. +
  33229. + pdev = physmap_map2pdev(map);
  33230. + physmap_data = pdev->dev.platform_data;
  33231. + physmap_data->unlock(pdev);
  33232. +}
  33233. +
  33234. +static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
  33235. +{
  33236. + map_word ret;
  33237. +
  33238. + physmap_lock(map);
  33239. + ret = inline_map_read(map, ofs);
  33240. + physmap_unlock(map);
  33241. +
  33242. + return ret;
  33243. +}
  33244. +
  33245. +static void physmap_flash_write_lock(struct map_info *map, map_word d,
  33246. + unsigned long ofs)
  33247. +{
  33248. + physmap_lock(map);
  33249. + inline_map_write(map, d, ofs);
  33250. + physmap_unlock(map);
  33251. +}
  33252. +
  33253. +static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
  33254. + unsigned long from, ssize_t len)
  33255. +{
  33256. + physmap_lock(map);
  33257. + inline_map_copy_from(map, to, from, len);
  33258. + physmap_unlock(map);
  33259. +}
  33260. +
  33261. +static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
  33262. + const void *from, ssize_t len)
  33263. +{
  33264. + physmap_lock(map);
  33265. + inline_map_copy_to(map, to, from, len);
  33266. + physmap_unlock(map);
  33267. +}
  33268. +
  33269. static int physmap_flash_remove(struct platform_device *dev)
  33270. {
  33271. struct physmap_flash_info *info;
  33272. @@ -153,6 +213,13 @@
  33273. simple_map_init(&info->map[i]);
  33274. + if (physmap_data->lock && physmap_data->unlock) {
  33275. + info->map[i].read = physmap_flash_read_lock;
  33276. + info->map[i].write = physmap_flash_write_lock;
  33277. + info->map[i].copy_from = physmap_flash_copy_from_lock;
  33278. + info->map[i].copy_to = physmap_flash_copy_to_lock;
  33279. + }
  33280. +
  33281. probe_type = rom_probe_types;
  33282. if (physmap_data->probe_type == NULL) {
  33283. for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
  33284. diff -Nur linux-4.1.43.orig/drivers/mtd/nand/Kconfig linux-4.1.43/drivers/mtd/nand/Kconfig
  33285. --- linux-4.1.43.orig/drivers/mtd/nand/Kconfig 2017-08-06 01:56:14.000000000 +0200
  33286. +++ linux-4.1.43/drivers/mtd/nand/Kconfig 2017-08-06 20:02:16.000000000 +0200
  33287. @@ -530,4 +530,24 @@
  33288. help
  33289. Enables support for NAND controller on Hisilicon SoC Hip04.
  33290. +config MTD_NAND_RB4XX
  33291. + tristate "NAND flash driver for RouterBoard 4xx series"
  33292. + depends on MTD_NAND && ATH79_MACH_RB4XX
  33293. +
  33294. +config MTD_NAND_RB750
  33295. + tristate "NAND flash driver for the RouterBoard 750"
  33296. + depends on MTD_NAND && ATH79_MACH_RB750
  33297. +
  33298. +config MTD_NAND_RB91X
  33299. + tristate "NAND flash driver for the RouterBOARD 91x series"
  33300. + depends on MTD_NAND && ATH79_MACH_RB91X
  33301. +
  33302. +config MTD_NAND_AR934X
  33303. + tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
  33304. + depends on (SOC_AR934X || SOC_QCA955X)
  33305. +
  33306. +config MTD_NAND_AR934X_HW_ECC
  33307. + bool "Hardware ECC support for the AR934X NAND Controller (EXPERIMENTAL)"
  33308. + depends on MTD_NAND_AR934X
  33309. +
  33310. endif # MTD_NAND
  33311. diff -Nur linux-4.1.43.orig/drivers/mtd/nand/Makefile linux-4.1.43/drivers/mtd/nand/Makefile
  33312. --- linux-4.1.43.orig/drivers/mtd/nand/Makefile 2017-08-06 01:56:14.000000000 +0200
  33313. +++ linux-4.1.43/drivers/mtd/nand/Makefile 2017-08-06 20:02:16.000000000 +0200
  33314. @@ -13,6 +13,7 @@
  33315. obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
  33316. obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o
  33317. obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
  33318. +obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nfc.o
  33319. obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
  33320. obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
  33321. obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
  33322. @@ -32,6 +33,9 @@
  33323. obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
  33324. obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
  33325. obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
  33326. +obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
  33327. +obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
  33328. +obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o
  33329. obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
  33330. obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
  33331. obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
  33332. diff -Nur linux-4.1.43.orig/drivers/mtd/nand/ar934x_nfc.c linux-4.1.43/drivers/mtd/nand/ar934x_nfc.c
  33333. --- linux-4.1.43.orig/drivers/mtd/nand/ar934x_nfc.c 1970-01-01 01:00:00.000000000 +0100
  33334. +++ linux-4.1.43/drivers/mtd/nand/ar934x_nfc.c 2017-08-06 20:02:16.000000000 +0200
  33335. @@ -0,0 +1,1508 @@
  33336. +/*
  33337. + * Driver for the built-in NAND controller of the Atheros AR934x SoCs
  33338. + *
  33339. + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  33340. + *
  33341. + * This program is free software; you can redistribute it and/or modify it
  33342. + * under the terms of the GNU General Public License version 2 as published
  33343. + * by the Free Software Foundation.
  33344. + */
  33345. +
  33346. +#include <linux/init.h>
  33347. +#include <linux/interrupt.h>
  33348. +#include <linux/module.h>
  33349. +#include <linux/dma-mapping.h>
  33350. +#include <linux/mtd/mtd.h>
  33351. +#include <linux/mtd/nand.h>
  33352. +#include <linux/mtd/partitions.h>
  33353. +#include <linux/platform_device.h>
  33354. +#include <linux/delay.h>
  33355. +#include <linux/slab.h>
  33356. +
  33357. +#include <linux/platform/ar934x_nfc.h>
  33358. +
  33359. +#define AR934X_NFC_REG_CMD 0x00
  33360. +#define AR934X_NFC_REG_CTRL 0x04
  33361. +#define AR934X_NFC_REG_STATUS 0x08
  33362. +#define AR934X_NFC_REG_INT_MASK 0x0c
  33363. +#define AR934X_NFC_REG_INT_STATUS 0x10
  33364. +#define AR934X_NFC_REG_ECC_CTRL 0x14
  33365. +#define AR934X_NFC_REG_ECC_OFFSET 0x18
  33366. +#define AR934X_NFC_REG_ADDR0_0 0x1c
  33367. +#define AR934X_NFC_REG_ADDR0_1 0x24
  33368. +#define AR934X_NFC_REG_ADDR1_0 0x20
  33369. +#define AR934X_NFC_REG_ADDR1_1 0x28
  33370. +#define AR934X_NFC_REG_SPARE_SIZE 0x30
  33371. +#define AR934X_NFC_REG_PROTECT 0x38
  33372. +#define AR934X_NFC_REG_LOOKUP_EN 0x40
  33373. +#define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
  33374. +#define AR934X_NFC_REG_DMA_ADDR 0x64
  33375. +#define AR934X_NFC_REG_DMA_COUNT 0x68
  33376. +#define AR934X_NFC_REG_DMA_CTRL 0x6c
  33377. +#define AR934X_NFC_REG_MEM_CTRL 0x80
  33378. +#define AR934X_NFC_REG_DATA_SIZE 0x84
  33379. +#define AR934X_NFC_REG_READ_STATUS 0x88
  33380. +#define AR934X_NFC_REG_TIME_SEQ 0x8c
  33381. +#define AR934X_NFC_REG_TIMINGS_ASYN 0x90
  33382. +#define AR934X_NFC_REG_TIMINGS_SYN 0x94
  33383. +#define AR934X_NFC_REG_FIFO_DATA 0x98
  33384. +#define AR934X_NFC_REG_TIME_MODE 0x9c
  33385. +#define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
  33386. +#define AR934X_NFC_REG_FIFO_INIT 0xb0
  33387. +#define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
  33388. +
  33389. +#define AR934X_NFC_CMD_CMD_SEQ_S 0
  33390. +#define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
  33391. +#define AR934X_NFC_CMD_SEQ_1C 0x00
  33392. +#define AR934X_NFC_CMD_SEQ_ERASE 0x0e
  33393. +#define AR934X_NFC_CMD_SEQ_12 0x0c
  33394. +#define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
  33395. +#define AR934X_NFC_CMD_SEQ_S 0x24
  33396. +#define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
  33397. +#define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
  33398. +#define AR934X_NFC_CMD_SEQ_18 0x32
  33399. +#define AR934X_NFC_CMD_INPUT_SEL_SIU 0
  33400. +#define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
  33401. +#define AR934X_NFC_CMD_ADDR_SEL_0 0
  33402. +#define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
  33403. +#define AR934X_NFC_CMD_CMD0_S 8
  33404. +#define AR934X_NFC_CMD_CMD0_M 0xff
  33405. +#define AR934X_NFC_CMD_CMD1_S 16
  33406. +#define AR934X_NFC_CMD_CMD1_M 0xff
  33407. +#define AR934X_NFC_CMD_CMD2_S 24
  33408. +#define AR934X_NFC_CMD_CMD2_M 0xff
  33409. +
  33410. +#define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
  33411. +#define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
  33412. +#define AR934X_NFC_CTRL_SPARE_EN BIT(3)
  33413. +#define AR934X_NFC_CTRL_INT_EN BIT(4)
  33414. +#define AR934X_NFC_CTRL_ECC_EN BIT(5)
  33415. +#define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
  33416. +#define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
  33417. +#define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
  33418. +#define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
  33419. +#define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
  33420. +#define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
  33421. +#define AR934X_NFC_CTRL_PAGE_SIZE_S 8
  33422. +#define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
  33423. +#define AR934X_NFC_CTRL_PAGE_SIZE_256 0
  33424. +#define AR934X_NFC_CTRL_PAGE_SIZE_512 1
  33425. +#define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
  33426. +#define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
  33427. +#define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
  33428. +#define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
  33429. +#define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
  33430. +#define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
  33431. +#define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
  33432. +#define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
  33433. +#define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
  33434. +#define AR934X_NFC_CTRL_PROT_EN BIT(14)
  33435. +#define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
  33436. +#define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
  33437. +#define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
  33438. +#define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
  33439. +#define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
  33440. +#define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
  33441. +#define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
  33442. +
  33443. +#define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
  33444. +#define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
  33445. +#define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
  33446. +#define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
  33447. +#define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
  33448. +#define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
  33449. +#define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
  33450. +#define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
  33451. +#define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
  33452. +#define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
  33453. +#define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
  33454. +#define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
  33455. +#define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
  33456. +
  33457. +#define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
  33458. +#define AR934X_NFC_INT_CMD_END BIT(1)
  33459. +
  33460. +#define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
  33461. +#define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
  33462. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
  33463. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
  33464. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
  33465. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
  33466. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
  33467. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
  33468. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
  33469. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
  33470. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
  33471. +#define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
  33472. +#define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
  33473. +#define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
  33474. +#define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
  33475. +
  33476. +#define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
  33477. +
  33478. +/* default timing values */
  33479. +#define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
  33480. +#define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
  33481. +#define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
  33482. +
  33483. +#define AR934X_NFC_ID_BUF_SIZE 8
  33484. +#define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
  33485. +#define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
  33486. +#define AR934X_NFC_DONE_TIMEOUT 1000
  33487. +#define AR934X_NFC_DMA_RETRIES 20
  33488. +
  33489. +#define AR934X_NFC_USE_IRQ true
  33490. +#define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
  33491. +
  33492. +#define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
  33493. +
  33494. +#undef AR934X_NFC_DEBUG_DATA
  33495. +#undef AR934X_NFC_DEBUG
  33496. +
  33497. +struct ar934x_nfc;
  33498. +
  33499. +static inline __attribute__ ((format (printf, 2, 3)))
  33500. +void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
  33501. +{
  33502. +}
  33503. +
  33504. +#ifdef AR934X_NFC_DEBUG
  33505. +#define nfc_dbg(_nfc, fmt, ...) \
  33506. + dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
  33507. +#else
  33508. +#define nfc_dbg(_nfc, fmt, ...) \
  33509. + _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
  33510. +#endif /* AR934X_NFC_DEBUG */
  33511. +
  33512. +#ifdef AR934X_NFC_DEBUG_DATA
  33513. +static void
  33514. +nfc_debug_data(const char *label, void *data, int len)
  33515. +{
  33516. + print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
  33517. + data, len, 0);
  33518. +}
  33519. +#else
  33520. +static inline void
  33521. +nfc_debug_data(const char *label, void *data, int len) {}
  33522. +#endif /* AR934X_NFC_DEBUG_DATA */
  33523. +
  33524. +struct ar934x_nfc {
  33525. + struct mtd_info mtd;
  33526. + struct nand_chip nand_chip;
  33527. + struct device *parent;
  33528. + void __iomem *base;
  33529. + void (*select_chip)(int chip_no);
  33530. + bool swap_dma;
  33531. + int irq;
  33532. + wait_queue_head_t irq_waitq;
  33533. +
  33534. + bool spurious_irq_expected;
  33535. + u32 irq_status;
  33536. +
  33537. + u32 ctrl_reg;
  33538. + u32 ecc_ctrl_reg;
  33539. + u32 ecc_offset_reg;
  33540. + u32 ecc_thres;
  33541. + u32 ecc_oob_pos;
  33542. +
  33543. + bool small_page;
  33544. + unsigned int addr_count0;
  33545. + unsigned int addr_count1;
  33546. +
  33547. + u8 *buf;
  33548. + dma_addr_t buf_dma;
  33549. + unsigned int buf_size;
  33550. + int buf_index;
  33551. +
  33552. + bool read_id;
  33553. +
  33554. + int erase1_page_addr;
  33555. +
  33556. + int rndout_page_addr;
  33557. + int rndout_read_cmd;
  33558. +
  33559. + int seqin_page_addr;
  33560. + int seqin_column;
  33561. + int seqin_read_cmd;
  33562. +};
  33563. +
  33564. +static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
  33565. +
  33566. +static inline bool
  33567. +is_all_ff(u8 *buf, int len)
  33568. +{
  33569. + while (len--)
  33570. + if (buf[len] != 0xff)
  33571. + return false;
  33572. +
  33573. + return true;
  33574. +}
  33575. +
  33576. +static inline void
  33577. +ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
  33578. +{
  33579. + __raw_writel(val, nfc->base + reg);
  33580. +}
  33581. +
  33582. +static inline u32
  33583. +ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
  33584. +{
  33585. + return __raw_readl(nfc->base + reg);
  33586. +}
  33587. +
  33588. +static inline struct ar934x_nfc_platform_data *
  33589. +ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
  33590. +{
  33591. + return nfc->parent->platform_data;
  33592. +}
  33593. +
  33594. +static inline struct
  33595. +ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
  33596. +{
  33597. + return container_of(mtd, struct ar934x_nfc, mtd);
  33598. +}
  33599. +
  33600. +static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
  33601. +{
  33602. + return AR934X_NFC_USE_IRQ;
  33603. +}
  33604. +
  33605. +static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
  33606. +{
  33607. + wmb();
  33608. +
  33609. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
  33610. + /* flush write */
  33611. + ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
  33612. +}
  33613. +
  33614. +static bool
  33615. +__ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
  33616. +{
  33617. + u32 status;
  33618. +
  33619. + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
  33620. + return (status & 0xff) == 0xff;
  33621. +}
  33622. +
  33623. +static inline bool
  33624. +__ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
  33625. +{
  33626. + u32 status;
  33627. +
  33628. + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
  33629. + return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
  33630. +}
  33631. +
  33632. +static int
  33633. +ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
  33634. +{
  33635. + unsigned long timeout;
  33636. +
  33637. + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
  33638. + do {
  33639. + if (__ar934x_nfc_dev_ready(nfc))
  33640. + return 0;
  33641. + } while time_before(jiffies, timeout);
  33642. +
  33643. + nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
  33644. + ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
  33645. + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
  33646. + return -ETIMEDOUT;
  33647. +}
  33648. +
  33649. +static int
  33650. +ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
  33651. +{
  33652. + unsigned long timeout;
  33653. +
  33654. + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
  33655. + do {
  33656. + if (__ar934x_nfc_is_dma_ready(nfc))
  33657. + return 0;
  33658. + } while time_before(jiffies, timeout);
  33659. +
  33660. + nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
  33661. + ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
  33662. + return -ETIMEDOUT;
  33663. +}
  33664. +
  33665. +static int
  33666. +ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
  33667. +{
  33668. + long timeout;
  33669. + int ret;
  33670. +
  33671. + timeout = wait_event_timeout(nfc->irq_waitq,
  33672. + (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
  33673. + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
  33674. +
  33675. + ret = 0;
  33676. + if (!timeout) {
  33677. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
  33678. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
  33679. + /* flush write */
  33680. + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
  33681. +
  33682. + nfc_dbg(nfc,
  33683. + "timeout waiting for interrupt, status:%08x\n",
  33684. + nfc->irq_status);
  33685. + ret = -ETIMEDOUT;
  33686. + }
  33687. +
  33688. + nfc->irq_status = 0;
  33689. + return ret;
  33690. +}
  33691. +
  33692. +static int
  33693. +ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
  33694. +{
  33695. + int ret;
  33696. +
  33697. + if (ar934x_nfc_use_irq(nfc))
  33698. + ret = ar934x_nfc_wait_irq(nfc);
  33699. + else
  33700. + ret = ar934x_nfc_wait_dev_ready(nfc);
  33701. +
  33702. + if (ret)
  33703. + return ret;
  33704. +
  33705. + return ar934x_nfc_wait_dma_ready(nfc);
  33706. +}
  33707. +
  33708. +static int
  33709. +ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
  33710. +{
  33711. + nfc->buf = dma_alloc_coherent(nfc->parent, size,
  33712. + &nfc->buf_dma, GFP_KERNEL);
  33713. + if (nfc->buf == NULL) {
  33714. + dev_err(nfc->parent, "no memory for DMA buffer\n");
  33715. + return -ENOMEM;
  33716. + }
  33717. +
  33718. + nfc->buf_size = size;
  33719. + nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
  33720. +
  33721. + return 0;
  33722. +}
  33723. +
  33724. +static void
  33725. +ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
  33726. +{
  33727. + dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
  33728. +}
  33729. +
  33730. +static void
  33731. +ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
  33732. + u32 *addr0, u32 *addr1)
  33733. +{
  33734. + u32 a0, a1;
  33735. +
  33736. + a0 = 0;
  33737. + a1 = 0;
  33738. +
  33739. + if (column == -1) {
  33740. + /* ERASE1 */
  33741. + a0 = (page_addr & 0xffff) << 16;
  33742. + a1 = (page_addr >> 16) & 0xf;
  33743. + } else if (page_addr != -1) {
  33744. + /* SEQIN, READ0, etc.. */
  33745. +
  33746. + /* TODO: handle 16bit bus width */
  33747. + if (nfc->small_page) {
  33748. + a0 = column & 0xff;
  33749. + a0 |= (page_addr & 0xff) << 8;
  33750. + a0 |= ((page_addr >> 8) & 0xff) << 16;
  33751. + a0 |= ((page_addr >> 16) & 0xff) << 24;
  33752. + } else {
  33753. + a0 = column & 0x0FFF;
  33754. + a0 |= (page_addr & 0xffff) << 16;
  33755. +
  33756. + if (nfc->addr_count0 > 4)
  33757. + a1 = (page_addr >> 16) & 0xf;
  33758. + }
  33759. + }
  33760. +
  33761. + *addr0 = a0;
  33762. + *addr1 = a1;
  33763. +}
  33764. +
  33765. +static void
  33766. +ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
  33767. +{
  33768. + u32 cmd_reg;
  33769. +
  33770. + cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
  33771. + AR934X_NFC_CMD_SEQ_1C;
  33772. + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
  33773. +
  33774. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
  33775. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
  33776. +
  33777. + ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
  33778. + ar934x_nfc_wait_dev_ready(nfc);
  33779. +}
  33780. +
  33781. +static int
  33782. +ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
  33783. + int len, u32 cmd_reg, u32 ctrl_reg, bool write)
  33784. +{
  33785. + u32 addr0, addr1;
  33786. + u32 dma_ctrl;
  33787. + int dir;
  33788. + int err;
  33789. + int retries = 0;
  33790. +
  33791. + WARN_ON(len & 3);
  33792. +
  33793. + if (WARN_ON(len > nfc->buf_size))
  33794. + dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
  33795. +
  33796. + if (write) {
  33797. + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
  33798. + dir = DMA_TO_DEVICE;
  33799. + } else {
  33800. + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
  33801. + dir = DMA_FROM_DEVICE;
  33802. + }
  33803. +
  33804. + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
  33805. +
  33806. + dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
  33807. + (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
  33808. + AR934X_NFC_DMA_CTRL_DMA_BURST_S);
  33809. +
  33810. + cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
  33811. + ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
  33812. +
  33813. + nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
  33814. + (write) ? "write" : "read",
  33815. + addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
  33816. +
  33817. +retry:
  33818. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
  33819. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
  33820. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
  33821. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
  33822. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
  33823. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
  33824. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
  33825. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
  33826. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg);
  33827. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg);
  33828. +
  33829. + if (ar934x_nfc_use_irq(nfc)) {
  33830. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
  33831. + /* flush write */
  33832. + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
  33833. + }
  33834. +
  33835. + ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
  33836. + err = ar934x_nfc_wait_done(nfc);
  33837. + if (err) {
  33838. + dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
  33839. + (write) ? "write" : "read", page_addr);
  33840. +
  33841. + ar934x_nfc_restart(nfc);
  33842. + if (retries++ < AR934X_NFC_DMA_RETRIES)
  33843. + goto retry;
  33844. +
  33845. + dev_err(nfc->parent, "%s operation failed on page %d\n",
  33846. + (write) ? "write" : "read", page_addr);
  33847. + }
  33848. +
  33849. + return err;
  33850. +}
  33851. +
  33852. +static int
  33853. +ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
  33854. +{
  33855. + u32 cmd_reg;
  33856. + int err;
  33857. +
  33858. + nfc_dbg(nfc, "readid, cmd:%02x\n", command);
  33859. +
  33860. + cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
  33861. + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
  33862. +
  33863. + err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE,
  33864. + cmd_reg, nfc->ctrl_reg, false);
  33865. +
  33866. + nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
  33867. +
  33868. + return err;
  33869. +}
  33870. +
  33871. +static int
  33872. +ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
  33873. + int page_addr, int len)
  33874. +{
  33875. + u32 cmd_reg;
  33876. + int err;
  33877. +
  33878. + nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
  33879. + column, page_addr, len);
  33880. +
  33881. + cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
  33882. +
  33883. + if (nfc->small_page) {
  33884. + cmd_reg |= AR934X_NFC_CMD_SEQ_18;
  33885. + } else {
  33886. + cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
  33887. + cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
  33888. + }
  33889. +
  33890. + err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
  33891. + cmd_reg, nfc->ctrl_reg, false);
  33892. +
  33893. + nfc_debug_data("[data] ", nfc->buf, len);
  33894. +
  33895. + return err;
  33896. +}
  33897. +
  33898. +static void
  33899. +ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
  33900. + int page_addr)
  33901. +{
  33902. + u32 addr0, addr1;
  33903. + u32 ctrl_reg;
  33904. + u32 cmd_reg;
  33905. +
  33906. + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
  33907. +
  33908. + ctrl_reg = nfc->ctrl_reg;
  33909. + if (nfc->small_page) {
  33910. + /* override number of address cycles for the erase command */
  33911. + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
  33912. + AR934X_NFC_CTRL_ADDR_CYCLE0_S);
  33913. + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
  33914. + AR934X_NFC_CTRL_ADDR_CYCLE1_S);
  33915. + ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
  33916. + ctrl_reg |= (nfc->addr_count0 + 1) <<
  33917. + AR934X_NFC_CTRL_ADDR_CYCLE0_S;
  33918. + }
  33919. +
  33920. + cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
  33921. + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
  33922. + cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
  33923. +
  33924. + nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
  33925. + page_addr, addr0, addr1, cmd_reg, ctrl_reg);
  33926. +
  33927. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
  33928. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
  33929. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
  33930. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
  33931. +
  33932. + ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
  33933. + ar934x_nfc_wait_dev_ready(nfc);
  33934. +}
  33935. +
  33936. +static int
  33937. +ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
  33938. + int page_addr, int len)
  33939. +{
  33940. + u32 cmd_reg;
  33941. +
  33942. + nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
  33943. + column, page_addr, len);
  33944. +
  33945. + nfc_debug_data("[data] ", nfc->buf, len);
  33946. +
  33947. + cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
  33948. + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
  33949. + cmd_reg |= AR934X_NFC_CMD_SEQ_12;
  33950. +
  33951. + return ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
  33952. + cmd_reg, nfc->ctrl_reg, true);
  33953. +}
  33954. +
  33955. +static void
  33956. +ar934x_nfc_read_status(struct ar934x_nfc *nfc)
  33957. +{
  33958. + u32 cmd_reg;
  33959. + u32 status;
  33960. +
  33961. + cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
  33962. + cmd_reg |= AR934X_NFC_CMD_SEQ_S;
  33963. +
  33964. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
  33965. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
  33966. +
  33967. + ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
  33968. + ar934x_nfc_wait_dev_ready(nfc);
  33969. +
  33970. + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
  33971. +
  33972. + nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
  33973. + cmd_reg, (status & 0xff));
  33974. +
  33975. + if (nfc->swap_dma)
  33976. + nfc->buf[0 ^ 3] = status;
  33977. + else
  33978. + nfc->buf[0] = status;
  33979. +}
  33980. +
  33981. +static void
  33982. +ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
  33983. + int page_addr)
  33984. +{
  33985. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  33986. + struct nand_chip *nand = mtd->priv;
  33987. +
  33988. + nfc->read_id = false;
  33989. + if (command != NAND_CMD_PAGEPROG)
  33990. + nfc->buf_index = 0;
  33991. +
  33992. + switch (command) {
  33993. + case NAND_CMD_RESET:
  33994. + ar934x_nfc_send_cmd(nfc, command);
  33995. + break;
  33996. +
  33997. + case NAND_CMD_READID:
  33998. + nfc->read_id = true;
  33999. + ar934x_nfc_send_readid(nfc, command);
  34000. + break;
  34001. +
  34002. + case NAND_CMD_READ0:
  34003. + case NAND_CMD_READ1:
  34004. + if (nfc->small_page) {
  34005. + ar934x_nfc_send_read(nfc, command, column, page_addr,
  34006. + mtd->writesize + mtd->oobsize);
  34007. + } else {
  34008. + ar934x_nfc_send_read(nfc, command, 0, page_addr,
  34009. + mtd->writesize + mtd->oobsize);
  34010. + nfc->buf_index = column;
  34011. + nfc->rndout_page_addr = page_addr;
  34012. + nfc->rndout_read_cmd = command;
  34013. + }
  34014. + break;
  34015. +
  34016. + case NAND_CMD_READOOB:
  34017. + if (nfc->small_page)
  34018. + ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
  34019. + column, page_addr,
  34020. + mtd->oobsize);
  34021. + else
  34022. + ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
  34023. + mtd->writesize, page_addr,
  34024. + mtd->oobsize);
  34025. + break;
  34026. +
  34027. + case NAND_CMD_RNDOUT:
  34028. + if (WARN_ON(nfc->small_page))
  34029. + break;
  34030. +
  34031. + /* emulate subpage read */
  34032. + ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
  34033. + nfc->rndout_page_addr,
  34034. + mtd->writesize + mtd->oobsize);
  34035. + nfc->buf_index = column;
  34036. + break;
  34037. +
  34038. + case NAND_CMD_ERASE1:
  34039. + nfc->erase1_page_addr = page_addr;
  34040. + break;
  34041. +
  34042. + case NAND_CMD_ERASE2:
  34043. + ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
  34044. + break;
  34045. +
  34046. + case NAND_CMD_STATUS:
  34047. + ar934x_nfc_read_status(nfc);
  34048. + break;
  34049. +
  34050. + case NAND_CMD_SEQIN:
  34051. + if (nfc->small_page) {
  34052. + /* output read command */
  34053. + if (column >= mtd->writesize) {
  34054. + column -= mtd->writesize;
  34055. + nfc->seqin_read_cmd = NAND_CMD_READOOB;
  34056. + } else if (column < 256) {
  34057. + nfc->seqin_read_cmd = NAND_CMD_READ0;
  34058. + } else {
  34059. + column -= 256;
  34060. + nfc->seqin_read_cmd = NAND_CMD_READ1;
  34061. + }
  34062. + } else {
  34063. + nfc->seqin_read_cmd = NAND_CMD_READ0;
  34064. + }
  34065. + nfc->seqin_column = column;
  34066. + nfc->seqin_page_addr = page_addr;
  34067. + break;
  34068. +
  34069. + case NAND_CMD_PAGEPROG:
  34070. + if (nand->ecc.mode == NAND_ECC_HW) {
  34071. + /* the data is already written */
  34072. + break;
  34073. + }
  34074. +
  34075. + if (nfc->small_page)
  34076. + ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
  34077. +
  34078. + ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
  34079. + nfc->seqin_page_addr,
  34080. + nfc->buf_index);
  34081. + break;
  34082. +
  34083. + default:
  34084. + dev_err(nfc->parent,
  34085. + "unsupported command: %x, column:%d page_addr=%d\n",
  34086. + command, column, page_addr);
  34087. + break;
  34088. + }
  34089. +}
  34090. +
  34091. +static int
  34092. +ar934x_nfc_dev_ready(struct mtd_info *mtd)
  34093. +{
  34094. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34095. +
  34096. + return __ar934x_nfc_dev_ready(nfc);
  34097. +}
  34098. +
  34099. +static void
  34100. +ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
  34101. +{
  34102. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34103. +
  34104. + if (nfc->select_chip)
  34105. + nfc->select_chip(chip_no);
  34106. +}
  34107. +
  34108. +static u8
  34109. +ar934x_nfc_read_byte(struct mtd_info *mtd)
  34110. +{
  34111. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34112. + u8 data;
  34113. +
  34114. + WARN_ON(nfc->buf_index >= nfc->buf_size);
  34115. +
  34116. + if (nfc->swap_dma || nfc->read_id)
  34117. + data = nfc->buf[nfc->buf_index ^ 3];
  34118. + else
  34119. + data = nfc->buf[nfc->buf_index];
  34120. +
  34121. + nfc->buf_index++;
  34122. +
  34123. + return data;
  34124. +}
  34125. +
  34126. +static void
  34127. +ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  34128. +{
  34129. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34130. + int i;
  34131. +
  34132. + WARN_ON(nfc->buf_index + len > nfc->buf_size);
  34133. +
  34134. + if (nfc->swap_dma) {
  34135. + for (i = 0; i < len; i++) {
  34136. + nfc->buf[nfc->buf_index ^ 3] = buf[i];
  34137. + nfc->buf_index++;
  34138. + }
  34139. + } else {
  34140. + for (i = 0; i < len; i++) {
  34141. + nfc->buf[nfc->buf_index] = buf[i];
  34142. + nfc->buf_index++;
  34143. + }
  34144. + }
  34145. +}
  34146. +
  34147. +static void
  34148. +ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  34149. +{
  34150. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34151. + int buf_index;
  34152. + int i;
  34153. +
  34154. + WARN_ON(nfc->buf_index + len > nfc->buf_size);
  34155. +
  34156. + buf_index = nfc->buf_index;
  34157. +
  34158. + if (nfc->swap_dma || nfc->read_id) {
  34159. + for (i = 0; i < len; i++) {
  34160. + buf[i] = nfc->buf[buf_index ^ 3];
  34161. + buf_index++;
  34162. + }
  34163. + } else {
  34164. + for (i = 0; i < len; i++) {
  34165. + buf[i] = nfc->buf[buf_index];
  34166. + buf_index++;
  34167. + }
  34168. + }
  34169. +
  34170. + nfc->buf_index = buf_index;
  34171. +}
  34172. +
  34173. +static inline void
  34174. +ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc)
  34175. +{
  34176. + nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN;
  34177. + nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
  34178. +}
  34179. +
  34180. +static inline void
  34181. +ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
  34182. +{
  34183. + nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN;
  34184. + nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
  34185. +}
  34186. +
  34187. +static int
  34188. +ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  34189. + int page)
  34190. +{
  34191. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34192. + int err;
  34193. +
  34194. + nfc_dbg(nfc, "read_oob: page:%d\n", page);
  34195. +
  34196. + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page,
  34197. + mtd->oobsize);
  34198. + if (err)
  34199. + return err;
  34200. +
  34201. + memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
  34202. +
  34203. + return 0;
  34204. +}
  34205. +
  34206. +static int
  34207. +ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  34208. + int page)
  34209. +{
  34210. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34211. +
  34212. + nfc_dbg(nfc, "write_oob: page:%d\n", page);
  34213. +
  34214. + memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
  34215. +
  34216. + return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize,
  34217. + page, mtd->oobsize);
  34218. +}
  34219. +
  34220. +static int
  34221. +ar934x_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  34222. + u8 *buf, int oob_required, int page)
  34223. +{
  34224. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34225. + int len;
  34226. + int err;
  34227. +
  34228. + nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required);
  34229. +
  34230. + len = mtd->writesize;
  34231. + if (oob_required)
  34232. + len += mtd->oobsize;
  34233. +
  34234. + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len);
  34235. + if (err)
  34236. + return err;
  34237. +
  34238. + memcpy(buf, nfc->buf, mtd->writesize);
  34239. +
  34240. + if (oob_required)
  34241. + memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize);
  34242. +
  34243. + return 0;
  34244. +}
  34245. +
  34246. +static int
  34247. +ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  34248. + u8 *buf, int oob_required, int page)
  34249. +{
  34250. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34251. + u32 ecc_ctrl;
  34252. + int max_bitflips = 0;
  34253. + bool ecc_failed;
  34254. + bool ecc_corrected;
  34255. + int err;
  34256. +
  34257. + nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required);
  34258. +
  34259. + ar934x_nfc_enable_hwecc(nfc);
  34260. + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page,
  34261. + mtd->writesize);
  34262. + ar934x_nfc_disable_hwecc(nfc);
  34263. +
  34264. + if (err)
  34265. + return err;
  34266. +
  34267. + /* TODO: optimize to avoid memcpy */
  34268. + memcpy(buf, nfc->buf, mtd->writesize);
  34269. +
  34270. + /* read the ECC status */
  34271. + ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL);
  34272. + ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT;
  34273. + ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT;
  34274. +
  34275. + if (oob_required || ecc_failed) {
  34276. + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize,
  34277. + page, mtd->oobsize);
  34278. + if (err)
  34279. + return err;
  34280. +
  34281. + if (oob_required)
  34282. + memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
  34283. + }
  34284. +
  34285. + if (ecc_failed) {
  34286. + /*
  34287. + * The hardware ECC engine reports uncorrectable errors
  34288. + * on empty pages. Check the ECC bytes and the data. If
  34289. + * both contains 0xff bytes only, dont report a failure.
  34290. + *
  34291. + * TODO: prebuild a buffer with 0xff bytes and use memcmp
  34292. + * for better performance?
  34293. + */
  34294. + if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) ||
  34295. + !is_all_ff(buf, mtd->writesize))
  34296. + mtd->ecc_stats.failed++;
  34297. + } else if (ecc_corrected) {
  34298. + /*
  34299. + * The hardware does not report the exact count of the
  34300. + * corrected bitflips, use assumptions based on the
  34301. + * threshold.
  34302. + */
  34303. + if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) {
  34304. + /*
  34305. + * The number of corrected bitflips exceeds the
  34306. + * threshold. Assume the maximum.
  34307. + */
  34308. + max_bitflips = chip->ecc.strength * chip->ecc.steps;
  34309. + } else {
  34310. + max_bitflips = nfc->ecc_thres * chip->ecc.steps;
  34311. + }
  34312. +
  34313. + mtd->ecc_stats.corrected += max_bitflips;
  34314. + }
  34315. +
  34316. + return max_bitflips;
  34317. +}
  34318. +
  34319. +static int
  34320. +ar934x_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  34321. + const u8 *buf, int oob_required)
  34322. +{
  34323. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34324. + int page;
  34325. + int len;
  34326. +
  34327. + page = nfc->seqin_page_addr;
  34328. +
  34329. + nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
  34330. +
  34331. + memcpy(nfc->buf, buf, mtd->writesize);
  34332. + len = mtd->writesize;
  34333. +
  34334. + if (oob_required) {
  34335. + memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize);
  34336. + len += mtd->oobsize;
  34337. + }
  34338. +
  34339. + return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
  34340. +}
  34341. +
  34342. +static int
  34343. +ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  34344. + const u8 *buf, int oob_required)
  34345. +{
  34346. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34347. + int page;
  34348. + int err;
  34349. +
  34350. + page = nfc->seqin_page_addr;
  34351. +
  34352. + nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
  34353. +
  34354. + /* write OOB first */
  34355. + if (oob_required &&
  34356. + !is_all_ff(chip->oob_poi, mtd->oobsize)) {
  34357. + err = ar934x_nfc_write_oob(mtd, chip, page);
  34358. + if (err)
  34359. + return err;
  34360. + }
  34361. +
  34362. + /* TODO: optimize to avoid memcopy */
  34363. + memcpy(nfc->buf, buf, mtd->writesize);
  34364. +
  34365. + ar934x_nfc_enable_hwecc(nfc);
  34366. + err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page,
  34367. + mtd->writesize);
  34368. + ar934x_nfc_disable_hwecc(nfc);
  34369. +
  34370. + return err;
  34371. +}
  34372. +
  34373. +static void
  34374. +ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
  34375. +{
  34376. + struct ar934x_nfc_platform_data *pdata;
  34377. +
  34378. + pdata = ar934x_nfc_get_platform_data(nfc);
  34379. + if (pdata->hw_reset) {
  34380. + pdata->hw_reset(true);
  34381. + pdata->hw_reset(false);
  34382. + }
  34383. +
  34384. + /*
  34385. + * setup timings
  34386. + * TODO: make it configurable via platform data
  34387. + */
  34388. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
  34389. + AR934X_NFC_TIME_SEQ_DEFAULT);
  34390. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
  34391. + AR934X_NFC_TIMINGS_ASYN_DEFAULT);
  34392. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
  34393. + AR934X_NFC_TIMINGS_SYN_DEFAULT);
  34394. +
  34395. + /* disable WP on all chips, and select chip 0 */
  34396. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
  34397. +
  34398. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
  34399. +
  34400. + /* initialize Control register */
  34401. + nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
  34402. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
  34403. +
  34404. + if (nfc->small_page) {
  34405. + /* Setup generic sequence register for small page reads. */
  34406. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
  34407. + AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
  34408. + }
  34409. +}
  34410. +
  34411. +static void
  34412. +ar934x_nfc_restart(struct ar934x_nfc *nfc)
  34413. +{
  34414. + u32 ctrl_reg;
  34415. +
  34416. + if (nfc->select_chip)
  34417. + nfc->select_chip(-1);
  34418. +
  34419. + ctrl_reg = nfc->ctrl_reg;
  34420. + ar934x_nfc_hw_init(nfc);
  34421. + nfc->ctrl_reg = ctrl_reg;
  34422. +
  34423. + if (nfc->select_chip)
  34424. + nfc->select_chip(0);
  34425. +
  34426. + ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
  34427. +}
  34428. +
  34429. +static irqreturn_t
  34430. +ar934x_nfc_irq_handler(int irq, void *data)
  34431. +{
  34432. + struct ar934x_nfc *nfc = data;
  34433. + u32 status;
  34434. +
  34435. + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
  34436. +
  34437. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
  34438. + /* flush write */
  34439. + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
  34440. +
  34441. + status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
  34442. + if (status) {
  34443. + nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
  34444. +
  34445. + nfc->irq_status = status;
  34446. + nfc->spurious_irq_expected = true;
  34447. + wake_up(&nfc->irq_waitq);
  34448. + } else {
  34449. + if (nfc->spurious_irq_expected) {
  34450. + nfc->spurious_irq_expected = false;
  34451. + } else {
  34452. + dev_warn(nfc->parent, "spurious interrupt\n");
  34453. + }
  34454. + }
  34455. +
  34456. + return IRQ_HANDLED;
  34457. +}
  34458. +
  34459. +static int
  34460. +ar934x_nfc_init_tail(struct mtd_info *mtd)
  34461. +{
  34462. + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
  34463. + struct nand_chip *chip = &nfc->nand_chip;
  34464. + u32 ctrl;
  34465. + u32 t;
  34466. + int err;
  34467. +
  34468. + switch (mtd->oobsize) {
  34469. + case 16:
  34470. + case 64:
  34471. + case 128:
  34472. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
  34473. + break;
  34474. +
  34475. + default:
  34476. + dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
  34477. + mtd->oobsize);
  34478. + return -ENXIO;
  34479. + }
  34480. +
  34481. + ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
  34482. +
  34483. + switch (mtd->erasesize / mtd->writesize) {
  34484. + case 32:
  34485. + t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
  34486. + break;
  34487. +
  34488. + case 64:
  34489. + t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
  34490. + break;
  34491. +
  34492. + case 128:
  34493. + t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
  34494. + break;
  34495. +
  34496. + case 256:
  34497. + t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
  34498. + break;
  34499. +
  34500. + default:
  34501. + dev_err(nfc->parent, "unsupported block size: %u\n",
  34502. + mtd->erasesize / mtd->writesize);
  34503. + return -ENXIO;
  34504. + }
  34505. +
  34506. + ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
  34507. +
  34508. + switch (mtd->writesize) {
  34509. + case 256:
  34510. + nfc->small_page = 1;
  34511. + t = AR934X_NFC_CTRL_PAGE_SIZE_256;
  34512. + break;
  34513. +
  34514. + case 512:
  34515. + nfc->small_page = 1;
  34516. + t = AR934X_NFC_CTRL_PAGE_SIZE_512;
  34517. + break;
  34518. +
  34519. + case 1024:
  34520. + t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
  34521. + break;
  34522. +
  34523. + case 2048:
  34524. + t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
  34525. + break;
  34526. +
  34527. + case 4096:
  34528. + t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
  34529. + break;
  34530. +
  34531. + case 8192:
  34532. + t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
  34533. + break;
  34534. +
  34535. + case 16384:
  34536. + t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
  34537. + break;
  34538. +
  34539. + default:
  34540. + dev_err(nfc->parent, "unsupported write size: %d bytes\n",
  34541. + mtd->writesize);
  34542. + return -ENXIO;
  34543. + }
  34544. +
  34545. + ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
  34546. +
  34547. + if (nfc->small_page) {
  34548. + ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
  34549. +
  34550. + if (chip->chipsize > (32 << 20)) {
  34551. + nfc->addr_count0 = 4;
  34552. + nfc->addr_count1 = 3;
  34553. + } else if (chip->chipsize > (2 << 16)) {
  34554. + nfc->addr_count0 = 3;
  34555. + nfc->addr_count1 = 2;
  34556. + } else {
  34557. + nfc->addr_count0 = 2;
  34558. + nfc->addr_count1 = 1;
  34559. + }
  34560. + } else {
  34561. + if (chip->chipsize > (128 << 20)) {
  34562. + nfc->addr_count0 = 5;
  34563. + nfc->addr_count1 = 3;
  34564. + } else if (chip->chipsize > (8 << 16)) {
  34565. + nfc->addr_count0 = 4;
  34566. + nfc->addr_count1 = 2;
  34567. + } else {
  34568. + nfc->addr_count0 = 3;
  34569. + nfc->addr_count1 = 1;
  34570. + }
  34571. + }
  34572. +
  34573. + ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
  34574. + ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
  34575. +
  34576. + nfc->ctrl_reg = ctrl;
  34577. + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
  34578. +
  34579. + ar934x_nfc_free_buf(nfc);
  34580. + err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
  34581. +
  34582. + return err;
  34583. +}
  34584. +
  34585. +static struct nand_ecclayout ar934x_nfc_oob_64_hwecc = {
  34586. + .eccbytes = 28,
  34587. + .eccpos = {
  34588. + 20, 21, 22, 23, 24, 25, 26,
  34589. + 27, 28, 29, 30, 31, 32, 33,
  34590. + 34, 35, 36, 37, 38, 39, 40,
  34591. + 41, 42, 43, 44, 45, 46, 47,
  34592. + },
  34593. + .oobfree = {
  34594. + {
  34595. + .offset = 4,
  34596. + .length = 16,
  34597. + },
  34598. + {
  34599. + .offset = 48,
  34600. + .length = 16,
  34601. + },
  34602. + },
  34603. +};
  34604. +
  34605. +static int
  34606. +ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
  34607. +{
  34608. + struct nand_chip *nand = &nfc->nand_chip;
  34609. + u32 ecc_cap;
  34610. + u32 ecc_thres;
  34611. +
  34612. + if (!config_enabled(CONFIG_MTD_NAND_AR934X_HW_ECC)) {
  34613. + dev_err(nfc->parent, "hardware ECC support is disabled\n");
  34614. + return -EINVAL;
  34615. + }
  34616. +
  34617. + switch (nfc->mtd.writesize) {
  34618. + case 2048:
  34619. + /*
  34620. + * Writing a subpage separately is not supported, because
  34621. + * the controller only does ECC on full-page accesses.
  34622. + */
  34623. + nand->options = NAND_NO_SUBPAGE_WRITE;
  34624. +
  34625. + nand->ecc.size = 512;
  34626. + nand->ecc.bytes = 7;
  34627. + nand->ecc.strength = 4;
  34628. + nand->ecc.layout = &ar934x_nfc_oob_64_hwecc;
  34629. + break;
  34630. +
  34631. + default:
  34632. + dev_err(nfc->parent,
  34633. + "hardware ECC is not available for %d byte pages\n",
  34634. + nfc->mtd.writesize);
  34635. + return -EINVAL;
  34636. + }
  34637. +
  34638. + BUG_ON(!nand->ecc.layout);
  34639. +
  34640. + switch (nand->ecc.strength) {
  34641. + case 4:
  34642. + ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4;
  34643. + ecc_thres = 4;
  34644. + break;
  34645. +
  34646. + default:
  34647. + dev_err(nfc->parent, "unsupported ECC strength %u\n",
  34648. + nand->ecc.strength);
  34649. + return -EINVAL;
  34650. + }
  34651. +
  34652. + nfc->ecc_thres = ecc_thres;
  34653. + nfc->ecc_oob_pos = nand->ecc.layout->eccpos[0];
  34654. +
  34655. + nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;
  34656. + nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;
  34657. +
  34658. + nfc->ecc_offset_reg = nfc->mtd.writesize + nfc->ecc_oob_pos;
  34659. +
  34660. + nand->ecc.mode = NAND_ECC_HW;
  34661. + nand->ecc.read_page = ar934x_nfc_read_page;
  34662. + nand->ecc.read_page_raw = ar934x_nfc_read_page_raw;
  34663. + nand->ecc.write_page = ar934x_nfc_write_page;
  34664. + nand->ecc.write_page_raw = ar934x_nfc_write_page_raw;
  34665. + nand->ecc.read_oob = ar934x_nfc_read_oob;
  34666. + nand->ecc.write_oob = ar934x_nfc_write_oob;
  34667. +
  34668. + return 0;
  34669. +}
  34670. +
  34671. +static int
  34672. +ar934x_nfc_probe(struct platform_device *pdev)
  34673. +{
  34674. + static const char *part_probes[] = { "cmdlinepart", NULL, };
  34675. + struct ar934x_nfc_platform_data *pdata;
  34676. + struct ar934x_nfc *nfc;
  34677. + struct resource *res;
  34678. + struct mtd_info *mtd;
  34679. + struct nand_chip *nand;
  34680. + struct mtd_part_parser_data ppdata;
  34681. + int ret;
  34682. +
  34683. + pdata = pdev->dev.platform_data;
  34684. + if (pdata == NULL) {
  34685. + dev_err(&pdev->dev, "no platform data defined\n");
  34686. + return -EINVAL;
  34687. + }
  34688. +
  34689. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  34690. + if (!res) {
  34691. + dev_err(&pdev->dev, "failed to get I/O memory\n");
  34692. + return -EINVAL;
  34693. + }
  34694. +
  34695. + nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL);
  34696. + if (!nfc) {
  34697. + dev_err(&pdev->dev, "failed to allocate driver data\n");
  34698. + return -ENOMEM;
  34699. + }
  34700. +
  34701. + nfc->base = devm_ioremap_resource(&pdev->dev, res);
  34702. + if (IS_ERR(nfc->base)) {
  34703. + dev_err(&pdev->dev, "failed to remap I/O memory\n");
  34704. + return PTR_ERR(nfc->base);
  34705. + }
  34706. +
  34707. + nfc->irq = platform_get_irq(pdev, 0);
  34708. + if (nfc->irq < 0) {
  34709. + dev_err(&pdev->dev, "no IRQ resource specified\n");
  34710. + return -EINVAL;
  34711. + }
  34712. +
  34713. + init_waitqueue_head(&nfc->irq_waitq);
  34714. + ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, 0,
  34715. + dev_name(&pdev->dev), nfc);
  34716. + if (ret) {
  34717. + dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
  34718. + return ret;
  34719. + }
  34720. +
  34721. + nfc->parent = &pdev->dev;
  34722. + nfc->select_chip = pdata->select_chip;
  34723. + nfc->swap_dma = pdata->swap_dma;
  34724. +
  34725. + nand = &nfc->nand_chip;
  34726. + mtd = &nfc->mtd;
  34727. +
  34728. + mtd->priv = nand;
  34729. + mtd->owner = THIS_MODULE;
  34730. + if (pdata->name)
  34731. + mtd->name = pdata->name;
  34732. + else
  34733. + mtd->name = dev_name(&pdev->dev);
  34734. +
  34735. + nand->chip_delay = 25;
  34736. +
  34737. + nand->dev_ready = ar934x_nfc_dev_ready;
  34738. + nand->cmdfunc = ar934x_nfc_cmdfunc;
  34739. + nand->read_byte = ar934x_nfc_read_byte;
  34740. + nand->write_buf = ar934x_nfc_write_buf;
  34741. + nand->read_buf = ar934x_nfc_read_buf;
  34742. + nand->select_chip = ar934x_nfc_select_chip;
  34743. +
  34744. + ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
  34745. + if (ret)
  34746. + goto err_free_irq;
  34747. +
  34748. + platform_set_drvdata(pdev, nfc);
  34749. +
  34750. + ar934x_nfc_hw_init(nfc);
  34751. +
  34752. + ret = nand_scan_ident(mtd, 1, NULL);
  34753. + if (ret) {
  34754. + dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
  34755. + goto err_free_buf;
  34756. + }
  34757. +
  34758. + ret = ar934x_nfc_init_tail(mtd);
  34759. + if (ret) {
  34760. + dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
  34761. + goto err_free_buf;
  34762. + }
  34763. +
  34764. + if (pdata->scan_fixup) {
  34765. + ret = pdata->scan_fixup(mtd);
  34766. + if (ret)
  34767. + goto err_free_buf;
  34768. + }
  34769. +
  34770. + switch (pdata->ecc_mode) {
  34771. + case AR934X_NFC_ECC_SOFT:
  34772. + nand->ecc.mode = NAND_ECC_SOFT;
  34773. + break;
  34774. +
  34775. + case AR934X_NFC_ECC_SOFT_BCH:
  34776. + nand->ecc.mode = NAND_ECC_SOFT_BCH;
  34777. + break;
  34778. +
  34779. + case AR934X_NFC_ECC_HW:
  34780. + ret = ar934x_nfc_setup_hwecc(nfc);
  34781. + if (ret)
  34782. + goto err_free_buf;
  34783. +
  34784. + break;
  34785. +
  34786. + default:
  34787. + dev_err(nfc->parent, "unknown ECC mode %d\n", pdata->ecc_mode);
  34788. + return -EINVAL;
  34789. + }
  34790. +
  34791. + ret = nand_scan_tail(mtd);
  34792. + if (ret) {
  34793. + dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
  34794. + goto err_free_buf;
  34795. + }
  34796. +
  34797. + memset(&ppdata, '\0', sizeof(ppdata));
  34798. + ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
  34799. + pdata->parts, pdata->nr_parts);
  34800. + if (ret) {
  34801. + dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
  34802. + goto err_free_buf;
  34803. + }
  34804. +
  34805. + return 0;
  34806. +
  34807. +err_free_buf:
  34808. + ar934x_nfc_free_buf(nfc);
  34809. +err_free_irq:
  34810. + free_irq(nfc->irq, nfc);
  34811. + return ret;
  34812. +}
  34813. +
  34814. +static int
  34815. +ar934x_nfc_remove(struct platform_device *pdev)
  34816. +{
  34817. + struct ar934x_nfc *nfc;
  34818. +
  34819. + nfc = platform_get_drvdata(pdev);
  34820. + if (nfc) {
  34821. + nand_release(&nfc->mtd);
  34822. + ar934x_nfc_free_buf(nfc);
  34823. + free_irq(nfc->irq, nfc);
  34824. + }
  34825. +
  34826. + return 0;
  34827. +}
  34828. +
  34829. +static struct platform_driver ar934x_nfc_driver = {
  34830. + .probe = ar934x_nfc_probe,
  34831. + .remove = ar934x_nfc_remove,
  34832. + .driver = {
  34833. + .name = AR934X_NFC_DRIVER_NAME,
  34834. + .owner = THIS_MODULE,
  34835. + },
  34836. +};
  34837. +
  34838. +module_platform_driver(ar934x_nfc_driver);
  34839. +
  34840. +MODULE_LICENSE("GPL v2");
  34841. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  34842. +MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
  34843. +MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
  34844. diff -Nur linux-4.1.43.orig/drivers/mtd/nand/rb4xx_nand.c linux-4.1.43/drivers/mtd/nand/rb4xx_nand.c
  34845. --- linux-4.1.43.orig/drivers/mtd/nand/rb4xx_nand.c 1970-01-01 01:00:00.000000000 +0100
  34846. +++ linux-4.1.43/drivers/mtd/nand/rb4xx_nand.c 2017-08-06 20:02:16.000000000 +0200
  34847. @@ -0,0 +1,305 @@
  34848. +/*
  34849. + * NAND flash driver for the MikroTik RouterBoard 4xx series
  34850. + *
  34851. + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  34852. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  34853. + *
  34854. + * This file was based on the driver for Linux 2.6.22 published by
  34855. + * MikroTik for their RouterBoard 4xx series devices.
  34856. + *
  34857. + * This program is free software; you can redistribute it and/or modify it
  34858. + * under the terms of the GNU General Public License version 2 as published
  34859. + * by the Free Software Foundation.
  34860. + */
  34861. +
  34862. +#include <linux/kernel.h>
  34863. +#include <linux/module.h>
  34864. +#include <linux/init.h>
  34865. +#include <linux/mtd/nand.h>
  34866. +#include <linux/mtd/mtd.h>
  34867. +#include <linux/mtd/partitions.h>
  34868. +#include <linux/platform_device.h>
  34869. +#include <linux/delay.h>
  34870. +#include <linux/io.h>
  34871. +#include <linux/gpio.h>
  34872. +#include <linux/slab.h>
  34873. +
  34874. +#include <asm/mach-ath79/ath79.h>
  34875. +#include <asm/mach-ath79/rb4xx_cpld.h>
  34876. +
  34877. +#define DRV_NAME "rb4xx-nand"
  34878. +#define DRV_VERSION "0.2.0"
  34879. +#define DRV_DESC "NAND flash driver for RouterBoard 4xx series"
  34880. +
  34881. +#define RB4XX_NAND_GPIO_READY 5
  34882. +#define RB4XX_NAND_GPIO_ALE 37
  34883. +#define RB4XX_NAND_GPIO_CLE 38
  34884. +#define RB4XX_NAND_GPIO_NCE 39
  34885. +
  34886. +struct rb4xx_nand_info {
  34887. + struct nand_chip chip;
  34888. + struct mtd_info mtd;
  34889. +};
  34890. +
  34891. +/*
  34892. + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  34893. + * will not be able to find the kernel that we load.
  34894. + */
  34895. +static struct nand_ecclayout rb4xx_nand_ecclayout = {
  34896. + .eccbytes = 6,
  34897. + .eccpos = { 8, 9, 10, 13, 14, 15 },
  34898. + .oobavail = 9,
  34899. + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  34900. +};
  34901. +
  34902. +static struct mtd_partition rb4xx_nand_partitions[] = {
  34903. + {
  34904. + .name = "booter",
  34905. + .offset = 0,
  34906. + .size = (256 * 1024),
  34907. + .mask_flags = MTD_WRITEABLE,
  34908. + },
  34909. + {
  34910. + .name = "kernel",
  34911. + .offset = (256 * 1024),
  34912. + .size = (4 * 1024 * 1024) - (256 * 1024),
  34913. + },
  34914. + {
  34915. + .name = "rootfs",
  34916. + .offset = MTDPART_OFS_NXTBLK,
  34917. + .size = MTDPART_SIZ_FULL,
  34918. + },
  34919. +};
  34920. +
  34921. +static int rb4xx_nand_dev_ready(struct mtd_info *mtd)
  34922. +{
  34923. + return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY);
  34924. +}
  34925. +
  34926. +static void rb4xx_nand_write_cmd(unsigned char cmd)
  34927. +{
  34928. + unsigned char data = cmd;
  34929. + int err;
  34930. +
  34931. + err = rb4xx_cpld_write(&data, 1);
  34932. + if (err)
  34933. + pr_err("rb4xx_nand: write cmd failed, err=%d\n", err);
  34934. +}
  34935. +
  34936. +static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
  34937. + unsigned int ctrl)
  34938. +{
  34939. + if (ctrl & NAND_CTRL_CHANGE) {
  34940. + gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE,
  34941. + (ctrl & NAND_CLE) ? 1 : 0);
  34942. + gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE,
  34943. + (ctrl & NAND_ALE) ? 1 : 0);
  34944. + gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE,
  34945. + (ctrl & NAND_NCE) ? 0 : 1);
  34946. + }
  34947. +
  34948. + if (cmd != NAND_CMD_NONE)
  34949. + rb4xx_nand_write_cmd(cmd);
  34950. +}
  34951. +
  34952. +static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd)
  34953. +{
  34954. + unsigned char data = 0;
  34955. + int err;
  34956. +
  34957. + err = rb4xx_cpld_read(&data, NULL, 1);
  34958. + if (err) {
  34959. + pr_err("rb4xx_nand: read data failed, err=%d\n", err);
  34960. + data = 0xff;
  34961. + }
  34962. +
  34963. + return data;
  34964. +}
  34965. +
  34966. +static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf,
  34967. + int len)
  34968. +{
  34969. + int err;
  34970. +
  34971. + err = rb4xx_cpld_write(buf, len);
  34972. + if (err)
  34973. + pr_err("rb4xx_nand: write buf failed, err=%d\n", err);
  34974. +}
  34975. +
  34976. +static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf,
  34977. + int len)
  34978. +{
  34979. + int err;
  34980. +
  34981. + err = rb4xx_cpld_read(buf, NULL, len);
  34982. + if (err)
  34983. + pr_err("rb4xx_nand: read buf failed, err=%d\n", err);
  34984. +}
  34985. +
  34986. +static int rb4xx_nand_probe(struct platform_device *pdev)
  34987. +{
  34988. + struct rb4xx_nand_info *info;
  34989. + int ret;
  34990. +
  34991. + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
  34992. +
  34993. + ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY");
  34994. + if (ret) {
  34995. + dev_err(&pdev->dev, "unable to request gpio %d\n",
  34996. + RB4XX_NAND_GPIO_READY);
  34997. + goto err;
  34998. + }
  34999. +
  35000. + ret = gpio_direction_input(RB4XX_NAND_GPIO_READY);
  35001. + if (ret) {
  35002. + dev_err(&pdev->dev, "unable to set input mode on gpio %d\n",
  35003. + RB4XX_NAND_GPIO_READY);
  35004. + goto err_free_gpio_ready;
  35005. + }
  35006. +
  35007. + ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE");
  35008. + if (ret) {
  35009. + dev_err(&pdev->dev, "unable to request gpio %d\n",
  35010. + RB4XX_NAND_GPIO_ALE);
  35011. + goto err_free_gpio_ready;
  35012. + }
  35013. +
  35014. + ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0);
  35015. + if (ret) {
  35016. + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
  35017. + RB4XX_NAND_GPIO_ALE);
  35018. + goto err_free_gpio_ale;
  35019. + }
  35020. +
  35021. + ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE");
  35022. + if (ret) {
  35023. + dev_err(&pdev->dev, "unable to request gpio %d\n",
  35024. + RB4XX_NAND_GPIO_CLE);
  35025. + goto err_free_gpio_ale;
  35026. + }
  35027. +
  35028. + ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0);
  35029. + if (ret) {
  35030. + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
  35031. + RB4XX_NAND_GPIO_CLE);
  35032. + goto err_free_gpio_cle;
  35033. + }
  35034. +
  35035. + ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE");
  35036. + if (ret) {
  35037. + dev_err(&pdev->dev, "unable to request gpio %d\n",
  35038. + RB4XX_NAND_GPIO_NCE);
  35039. + goto err_free_gpio_cle;
  35040. + }
  35041. +
  35042. + ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1);
  35043. + if (ret) {
  35044. + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
  35045. + RB4XX_NAND_GPIO_ALE);
  35046. + goto err_free_gpio_nce;
  35047. + }
  35048. +
  35049. + info = kzalloc(sizeof(*info), GFP_KERNEL);
  35050. + if (!info) {
  35051. + dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n");
  35052. + ret = -ENOMEM;
  35053. + goto err_free_gpio_nce;
  35054. + }
  35055. +
  35056. + info->chip.priv = &info;
  35057. + info->mtd.priv = &info->chip;
  35058. + info->mtd.owner = THIS_MODULE;
  35059. +
  35060. + info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl;
  35061. + info->chip.dev_ready = rb4xx_nand_dev_ready;
  35062. + info->chip.read_byte = rb4xx_nand_read_byte;
  35063. + info->chip.write_buf = rb4xx_nand_write_buf;
  35064. + info->chip.read_buf = rb4xx_nand_read_buf;
  35065. +
  35066. + info->chip.chip_delay = 25;
  35067. + info->chip.ecc.mode = NAND_ECC_SOFT;
  35068. +
  35069. + platform_set_drvdata(pdev, info);
  35070. +
  35071. + ret = nand_scan_ident(&info->mtd, 1, NULL);
  35072. + if (ret) {
  35073. + ret = -ENXIO;
  35074. + goto err_free_info;
  35075. + }
  35076. +
  35077. + if (info->mtd.writesize == 512)
  35078. + info->chip.ecc.layout = &rb4xx_nand_ecclayout;
  35079. +
  35080. + ret = nand_scan_tail(&info->mtd);
  35081. + if (ret) {
  35082. + return -ENXIO;
  35083. + goto err_set_drvdata;
  35084. + }
  35085. +
  35086. + mtd_device_register(&info->mtd, rb4xx_nand_partitions,
  35087. + ARRAY_SIZE(rb4xx_nand_partitions));
  35088. + if (ret)
  35089. + goto err_release_nand;
  35090. +
  35091. + return 0;
  35092. +
  35093. +err_release_nand:
  35094. + nand_release(&info->mtd);
  35095. +err_set_drvdata:
  35096. + platform_set_drvdata(pdev, NULL);
  35097. +err_free_info:
  35098. + kfree(info);
  35099. +err_free_gpio_nce:
  35100. + gpio_free(RB4XX_NAND_GPIO_NCE);
  35101. +err_free_gpio_cle:
  35102. + gpio_free(RB4XX_NAND_GPIO_CLE);
  35103. +err_free_gpio_ale:
  35104. + gpio_free(RB4XX_NAND_GPIO_ALE);
  35105. +err_free_gpio_ready:
  35106. + gpio_free(RB4XX_NAND_GPIO_READY);
  35107. +err:
  35108. + return ret;
  35109. +}
  35110. +
  35111. +static int rb4xx_nand_remove(struct platform_device *pdev)
  35112. +{
  35113. + struct rb4xx_nand_info *info = platform_get_drvdata(pdev);
  35114. +
  35115. + nand_release(&info->mtd);
  35116. + platform_set_drvdata(pdev, NULL);
  35117. + kfree(info);
  35118. + gpio_free(RB4XX_NAND_GPIO_NCE);
  35119. + gpio_free(RB4XX_NAND_GPIO_CLE);
  35120. + gpio_free(RB4XX_NAND_GPIO_ALE);
  35121. + gpio_free(RB4XX_NAND_GPIO_READY);
  35122. +
  35123. + return 0;
  35124. +}
  35125. +
  35126. +static struct platform_driver rb4xx_nand_driver = {
  35127. + .probe = rb4xx_nand_probe,
  35128. + .remove = rb4xx_nand_remove,
  35129. + .driver = {
  35130. + .name = DRV_NAME,
  35131. + .owner = THIS_MODULE,
  35132. + },
  35133. +};
  35134. +
  35135. +static int __init rb4xx_nand_init(void)
  35136. +{
  35137. + return platform_driver_register(&rb4xx_nand_driver);
  35138. +}
  35139. +
  35140. +static void __exit rb4xx_nand_exit(void)
  35141. +{
  35142. + platform_driver_unregister(&rb4xx_nand_driver);
  35143. +}
  35144. +
  35145. +module_init(rb4xx_nand_init);
  35146. +module_exit(rb4xx_nand_exit);
  35147. +
  35148. +MODULE_DESCRIPTION(DRV_DESC);
  35149. +MODULE_VERSION(DRV_VERSION);
  35150. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  35151. +MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
  35152. +MODULE_LICENSE("GPL v2");
  35153. diff -Nur linux-4.1.43.orig/drivers/mtd/nand/rb750_nand.c linux-4.1.43/drivers/mtd/nand/rb750_nand.c
  35154. --- linux-4.1.43.orig/drivers/mtd/nand/rb750_nand.c 1970-01-01 01:00:00.000000000 +0100
  35155. +++ linux-4.1.43/drivers/mtd/nand/rb750_nand.c 2017-08-06 20:02:16.000000000 +0200
  35156. @@ -0,0 +1,354 @@
  35157. +/*
  35158. + * NAND flash driver for the MikroTik RouterBOARD 750
  35159. + *
  35160. + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  35161. + *
  35162. + * This program is free software; you can redistribute it and/or modify it
  35163. + * under the terms of the GNU General Public License version 2 as published
  35164. + * by the Free Software Foundation.
  35165. + */
  35166. +
  35167. +#include <linux/kernel.h>
  35168. +#include <linux/module.h>
  35169. +#include <linux/mtd/nand.h>
  35170. +#include <linux/mtd/mtd.h>
  35171. +#include <linux/mtd/partitions.h>
  35172. +#include <linux/platform_device.h>
  35173. +#include <linux/io.h>
  35174. +#include <linux/slab.h>
  35175. +
  35176. +#include <asm/mach-ath79/ar71xx_regs.h>
  35177. +#include <asm/mach-ath79/ath79.h>
  35178. +#include <asm/mach-ath79/mach-rb750.h>
  35179. +
  35180. +#define DRV_NAME "rb750-nand"
  35181. +#define DRV_VERSION "0.1.0"
  35182. +#define DRV_DESC "NAND flash driver for the RouterBOARD 750"
  35183. +
  35184. +#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0)
  35185. +#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE)
  35186. +#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE)
  35187. +#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE)
  35188. +#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE)
  35189. +#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY)
  35190. +
  35191. +#define RB750_NAND_DATA_SHIFT 1
  35192. +#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT)
  35193. +#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY)
  35194. +#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \
  35195. + RB750_NAND_NRE | RB750_NAND_NWE)
  35196. +
  35197. +struct rb750_nand_info {
  35198. + struct nand_chip chip;
  35199. + struct mtd_info mtd;
  35200. + struct rb7xx_nand_platform_data *pdata;
  35201. +};
  35202. +
  35203. +static inline struct rb750_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
  35204. +{
  35205. + return container_of(mtd, struct rb750_nand_info, mtd);
  35206. +}
  35207. +
  35208. +/*
  35209. + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  35210. + * will not be able to find the kernel that we load.
  35211. + */
  35212. +static struct nand_ecclayout rb750_nand_ecclayout = {
  35213. + .eccbytes = 6,
  35214. + .eccpos = { 8, 9, 10, 13, 14, 15 },
  35215. + .oobavail = 9,
  35216. + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  35217. +};
  35218. +
  35219. +static struct mtd_partition rb750_nand_partitions[] = {
  35220. + {
  35221. + .name = "booter",
  35222. + .offset = 0,
  35223. + .size = (256 * 1024),
  35224. + .mask_flags = MTD_WRITEABLE,
  35225. + }, {
  35226. + .name = "kernel",
  35227. + .offset = (256 * 1024),
  35228. + .size = (4 * 1024 * 1024) - (256 * 1024),
  35229. + }, {
  35230. + .name = "rootfs",
  35231. + .offset = MTDPART_OFS_NXTBLK,
  35232. + .size = MTDPART_SIZ_FULL,
  35233. + },
  35234. +};
  35235. +
  35236. +static void rb750_nand_write(const u8 *buf, unsigned len)
  35237. +{
  35238. + void __iomem *base = ath79_gpio_base;
  35239. + u32 out;
  35240. + u32 t;
  35241. + unsigned i;
  35242. +
  35243. + /* set data lines to output mode */
  35244. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35245. + __raw_writel(t | RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE);
  35246. +
  35247. + out = __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35248. + out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE);
  35249. + for (i = 0; i != len; i++) {
  35250. + u32 data;
  35251. +
  35252. + data = buf[i];
  35253. + data <<= RB750_NAND_DATA_SHIFT;
  35254. + data |= out;
  35255. + __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
  35256. +
  35257. + __raw_writel(data | RB750_NAND_NWE, base + AR71XX_GPIO_REG_OUT);
  35258. + /* flush write */
  35259. + __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35260. + }
  35261. +
  35262. + /* set data lines to input mode */
  35263. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35264. + __raw_writel(t & ~RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE);
  35265. + /* flush write */
  35266. + __raw_readl(base + AR71XX_GPIO_REG_OE);
  35267. +}
  35268. +
  35269. +static void rb750_nand_read(u8 *read_buf, unsigned len)
  35270. +{
  35271. + void __iomem *base = ath79_gpio_base;
  35272. + unsigned i;
  35273. +
  35274. + for (i = 0; i < len; i++) {
  35275. + u8 data;
  35276. +
  35277. + /* activate RE line */
  35278. + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_CLEAR);
  35279. + /* flush write */
  35280. + __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
  35281. +
  35282. + /* read input lines */
  35283. + data = __raw_readl(base + AR71XX_GPIO_REG_IN) >>
  35284. + RB750_NAND_DATA_SHIFT;
  35285. +
  35286. + /* deactivate RE line */
  35287. + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_SET);
  35288. +
  35289. + read_buf[i] = data;
  35290. + }
  35291. +}
  35292. +
  35293. +static void rb750_nand_select_chip(struct mtd_info *mtd, int chip)
  35294. +{
  35295. + struct rb750_nand_info *rbinfo = mtd_to_rbinfo(mtd);
  35296. + void __iomem *base = ath79_gpio_base;
  35297. + u32 t;
  35298. +
  35299. + if (chip >= 0) {
  35300. + rbinfo->pdata->enable_pins();
  35301. +
  35302. + /* set input mode for data lines */
  35303. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35304. + __raw_writel(t & ~RB750_NAND_INPUT_BITS,
  35305. + base + AR71XX_GPIO_REG_OE);
  35306. +
  35307. + /* deactivate RE and WE lines */
  35308. + __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE,
  35309. + base + AR71XX_GPIO_REG_SET);
  35310. + /* flush write */
  35311. + (void) __raw_readl(base + AR71XX_GPIO_REG_SET);
  35312. +
  35313. + /* activate CE line */
  35314. + __raw_writel(rbinfo->pdata->nce_line,
  35315. + base + AR71XX_GPIO_REG_CLEAR);
  35316. + } else {
  35317. + /* deactivate CE line */
  35318. + __raw_writel(rbinfo->pdata->nce_line,
  35319. + base + AR71XX_GPIO_REG_SET);
  35320. + /* flush write */
  35321. + (void) __raw_readl(base + AR71XX_GPIO_REG_SET);
  35322. +
  35323. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35324. + __raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY,
  35325. + base + AR71XX_GPIO_REG_OE);
  35326. +
  35327. + rbinfo->pdata->disable_pins();
  35328. + }
  35329. +}
  35330. +
  35331. +static int rb750_nand_dev_ready(struct mtd_info *mtd)
  35332. +{
  35333. + void __iomem *base = ath79_gpio_base;
  35334. +
  35335. + return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB750_NAND_RDY);
  35336. +}
  35337. +
  35338. +static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
  35339. + unsigned int ctrl)
  35340. +{
  35341. + if (ctrl & NAND_CTRL_CHANGE) {
  35342. + void __iomem *base = ath79_gpio_base;
  35343. + u32 t;
  35344. +
  35345. + t = __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35346. +
  35347. + t &= ~(RB750_NAND_CLE | RB750_NAND_ALE);
  35348. + t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0;
  35349. + t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0;
  35350. +
  35351. + __raw_writel(t, base + AR71XX_GPIO_REG_OUT);
  35352. + /* flush write */
  35353. + __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35354. + }
  35355. +
  35356. + if (cmd != NAND_CMD_NONE) {
  35357. + u8 t = cmd;
  35358. + rb750_nand_write(&t, 1);
  35359. + }
  35360. +}
  35361. +
  35362. +static u8 rb750_nand_read_byte(struct mtd_info *mtd)
  35363. +{
  35364. + u8 data = 0;
  35365. + rb750_nand_read(&data, 1);
  35366. + return data;
  35367. +}
  35368. +
  35369. +static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  35370. +{
  35371. + rb750_nand_read(buf, len);
  35372. +}
  35373. +
  35374. +static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  35375. +{
  35376. + rb750_nand_write(buf, len);
  35377. +}
  35378. +
  35379. +static void __init rb750_nand_gpio_init(struct rb750_nand_info *info)
  35380. +{
  35381. + void __iomem *base = ath79_gpio_base;
  35382. + u32 out;
  35383. + u32 t;
  35384. +
  35385. + out = __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35386. +
  35387. + /* setup output levels */
  35388. + __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE,
  35389. + base + AR71XX_GPIO_REG_SET);
  35390. +
  35391. + __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE,
  35392. + base + AR71XX_GPIO_REG_CLEAR);
  35393. +
  35394. + /* setup input lines */
  35395. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35396. + __raw_writel(t & ~(RB750_NAND_INPUT_BITS), base + AR71XX_GPIO_REG_OE);
  35397. +
  35398. + /* setup output lines */
  35399. + t = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35400. + t |= RB750_NAND_OUTPUT_BITS;
  35401. + t |= info->pdata->nce_line;
  35402. + __raw_writel(t, base + AR71XX_GPIO_REG_OE);
  35403. +
  35404. + info->pdata->latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0);
  35405. +}
  35406. +
  35407. +static int rb750_nand_probe(struct platform_device *pdev)
  35408. +{
  35409. + struct rb750_nand_info *info;
  35410. + struct rb7xx_nand_platform_data *pdata;
  35411. + int ret;
  35412. +
  35413. + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
  35414. +
  35415. + pdata = pdev->dev.platform_data;
  35416. + if (!pdata)
  35417. + return -EINVAL;
  35418. +
  35419. + info = kzalloc(sizeof(*info), GFP_KERNEL);
  35420. + if (!info)
  35421. + return -ENOMEM;
  35422. +
  35423. + info->chip.priv = &info;
  35424. + info->mtd.priv = &info->chip;
  35425. + info->mtd.owner = THIS_MODULE;
  35426. +
  35427. + info->chip.select_chip = rb750_nand_select_chip;
  35428. + info->chip.cmd_ctrl = rb750_nand_cmd_ctrl;
  35429. + info->chip.dev_ready = rb750_nand_dev_ready;
  35430. + info->chip.read_byte = rb750_nand_read_byte;
  35431. + info->chip.write_buf = rb750_nand_write_buf;
  35432. + info->chip.read_buf = rb750_nand_read_buf;
  35433. +
  35434. + info->chip.chip_delay = 25;
  35435. + info->chip.ecc.mode = NAND_ECC_SOFT;
  35436. +
  35437. + info->pdata = pdata;
  35438. +
  35439. + platform_set_drvdata(pdev, info);
  35440. +
  35441. + rb750_nand_gpio_init(info);
  35442. +
  35443. + ret = nand_scan_ident(&info->mtd, 1, NULL);
  35444. + if (ret) {
  35445. + ret = -ENXIO;
  35446. + goto err_free_info;
  35447. + }
  35448. +
  35449. + if (info->mtd.writesize == 512)
  35450. + info->chip.ecc.layout = &rb750_nand_ecclayout;
  35451. +
  35452. + ret = nand_scan_tail(&info->mtd);
  35453. + if (ret) {
  35454. + return -ENXIO;
  35455. + goto err_set_drvdata;
  35456. + }
  35457. +
  35458. + ret = mtd_device_register(&info->mtd, rb750_nand_partitions,
  35459. + ARRAY_SIZE(rb750_nand_partitions));
  35460. + if (ret)
  35461. + goto err_release_nand;
  35462. +
  35463. + return 0;
  35464. +
  35465. +err_release_nand:
  35466. + nand_release(&info->mtd);
  35467. +err_set_drvdata:
  35468. + platform_set_drvdata(pdev, NULL);
  35469. +err_free_info:
  35470. + kfree(info);
  35471. + return ret;
  35472. +}
  35473. +
  35474. +static int rb750_nand_remove(struct platform_device *pdev)
  35475. +{
  35476. + struct rb750_nand_info *info = platform_get_drvdata(pdev);
  35477. +
  35478. + nand_release(&info->mtd);
  35479. + platform_set_drvdata(pdev, NULL);
  35480. + kfree(info);
  35481. +
  35482. + return 0;
  35483. +}
  35484. +
  35485. +static struct platform_driver rb750_nand_driver = {
  35486. + .probe = rb750_nand_probe,
  35487. + .remove = rb750_nand_remove,
  35488. + .driver = {
  35489. + .name = DRV_NAME,
  35490. + .owner = THIS_MODULE,
  35491. + },
  35492. +};
  35493. +
  35494. +static int __init rb750_nand_init(void)
  35495. +{
  35496. + return platform_driver_register(&rb750_nand_driver);
  35497. +}
  35498. +
  35499. +static void __exit rb750_nand_exit(void)
  35500. +{
  35501. + platform_driver_unregister(&rb750_nand_driver);
  35502. +}
  35503. +
  35504. +module_init(rb750_nand_init);
  35505. +module_exit(rb750_nand_exit);
  35506. +
  35507. +MODULE_DESCRIPTION(DRV_DESC);
  35508. +MODULE_VERSION(DRV_VERSION);
  35509. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  35510. +MODULE_LICENSE("GPL v2");
  35511. diff -Nur linux-4.1.43.orig/drivers/mtd/nand/rb91x_nand.c linux-4.1.43/drivers/mtd/nand/rb91x_nand.c
  35512. --- linux-4.1.43.orig/drivers/mtd/nand/rb91x_nand.c 1970-01-01 01:00:00.000000000 +0100
  35513. +++ linux-4.1.43/drivers/mtd/nand/rb91x_nand.c 2017-08-06 20:02:16.000000000 +0200
  35514. @@ -0,0 +1,377 @@
  35515. +/*
  35516. + * NAND flash driver for the MikroTik RouterBOARD 91x series
  35517. + *
  35518. + * Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
  35519. + *
  35520. + * This program is free software; you can redistribute it and/or modify it
  35521. + * under the terms of the GNU General Public License version 2 as published
  35522. + * by the Free Software Foundation.
  35523. + */
  35524. +
  35525. +#include <linux/kernel.h>
  35526. +#include <linux/spinlock.h>
  35527. +#include <linux/module.h>
  35528. +#include <linux/mtd/nand.h>
  35529. +#include <linux/mtd/mtd.h>
  35530. +#include <linux/mtd/partitions.h>
  35531. +#include <linux/platform_device.h>
  35532. +#include <linux/io.h>
  35533. +#include <linux/slab.h>
  35534. +#include <linux/gpio.h>
  35535. +#include <linux/platform_data/rb91x_nand.h>
  35536. +
  35537. +#include <asm/mach-ath79/ar71xx_regs.h>
  35538. +#include <asm/mach-ath79/ath79.h>
  35539. +
  35540. +#define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
  35541. +
  35542. +#define RB91X_NAND_NRWE BIT(12)
  35543. +
  35544. +#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
  35545. + BIT(13) | BIT(14) | BIT(15))
  35546. +
  35547. +#define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
  35548. +#define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
  35549. +
  35550. +#define RB91X_NAND_LOW_DATA_MASK 0x1f
  35551. +#define RB91X_NAND_HIGH_DATA_MASK 0xe0
  35552. +#define RB91X_NAND_HIGH_DATA_SHIFT 8
  35553. +
  35554. +struct rb91x_nand_info {
  35555. + struct nand_chip chip;
  35556. + struct mtd_info mtd;
  35557. + struct device *dev;
  35558. +
  35559. + int gpio_nce;
  35560. + int gpio_ale;
  35561. + int gpio_cle;
  35562. + int gpio_rdy;
  35563. + int gpio_read;
  35564. + int gpio_nrw;
  35565. + int gpio_nle;
  35566. +};
  35567. +
  35568. +static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
  35569. +{
  35570. + return container_of(mtd, struct rb91x_nand_info, mtd);
  35571. +}
  35572. +
  35573. +/*
  35574. + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  35575. + * will not be able to find the kernel that we load.
  35576. + */
  35577. +static struct nand_ecclayout rb91x_nand_ecclayout = {
  35578. + .eccbytes = 6,
  35579. + .eccpos = { 8, 9, 10, 13, 14, 15 },
  35580. + .oobavail = 9,
  35581. + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  35582. +};
  35583. +
  35584. +static struct mtd_partition rb91x_nand_partitions[] = {
  35585. + {
  35586. + .name = "booter",
  35587. + .offset = 0,
  35588. + .size = (256 * 1024),
  35589. + .mask_flags = MTD_WRITEABLE,
  35590. + }, {
  35591. + .name = "kernel",
  35592. + .offset = (256 * 1024),
  35593. + .size = (4 * 1024 * 1024) - (256 * 1024),
  35594. + }, {
  35595. + .name = "rootfs",
  35596. + .offset = MTDPART_OFS_NXTBLK,
  35597. + .size = MTDPART_SIZ_FULL,
  35598. + },
  35599. +};
  35600. +
  35601. +static void rb91x_nand_write(struct rb91x_nand_info *rbni,
  35602. + const u8 *buf,
  35603. + unsigned len)
  35604. +{
  35605. + void __iomem *base = ath79_gpio_base;
  35606. + u32 oe_reg;
  35607. + u32 out_reg;
  35608. + u32 out;
  35609. + unsigned i;
  35610. +
  35611. + /* enable the latch */
  35612. + gpio_set_value_cansleep(rbni->gpio_nle, 0);
  35613. +
  35614. + oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35615. + out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35616. +
  35617. + /* set data lines to output mode */
  35618. + __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
  35619. + base + AR71XX_GPIO_REG_OE);
  35620. +
  35621. + out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
  35622. + for (i = 0; i != len; i++) {
  35623. + u32 data;
  35624. +
  35625. + data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
  35626. + RB91X_NAND_HIGH_DATA_SHIFT;
  35627. + data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
  35628. + data |= out;
  35629. + __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
  35630. +
  35631. + /* deactivate WE line */
  35632. + data |= RB91X_NAND_NRWE;
  35633. + __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
  35634. + /* flush write */
  35635. + __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35636. + }
  35637. +
  35638. + /* restore registers */
  35639. + __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
  35640. + __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
  35641. + /* flush write */
  35642. + __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35643. +
  35644. + /* disable the latch */
  35645. + gpio_set_value_cansleep(rbni->gpio_nle, 1);
  35646. +}
  35647. +
  35648. +static void rb91x_nand_read(struct rb91x_nand_info *rbni,
  35649. + u8 *read_buf,
  35650. + unsigned len)
  35651. +{
  35652. + void __iomem *base = ath79_gpio_base;
  35653. + u32 oe_reg;
  35654. + u32 out_reg;
  35655. + unsigned i;
  35656. +
  35657. + /* enable read mode */
  35658. + gpio_set_value_cansleep(rbni->gpio_read, 1);
  35659. +
  35660. + /* enable latch */
  35661. + gpio_set_value_cansleep(rbni->gpio_nle, 0);
  35662. +
  35663. + /* save registers */
  35664. + oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
  35665. + out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35666. +
  35667. + /* set data lines to input mode */
  35668. + __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
  35669. + base + AR71XX_GPIO_REG_OE);
  35670. +
  35671. + for (i = 0; i < len; i++) {
  35672. + u32 in;
  35673. + u8 data;
  35674. +
  35675. + /* activate RE line */
  35676. + __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
  35677. + /* flush write */
  35678. + __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
  35679. +
  35680. + /* read input lines */
  35681. + in = __raw_readl(base + AR71XX_GPIO_REG_IN);
  35682. +
  35683. + /* deactivate RE line */
  35684. + __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
  35685. +
  35686. + data = (in & RB91X_NAND_LOW_DATA_MASK);
  35687. + data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
  35688. + RB91X_NAND_HIGH_DATA_MASK;
  35689. +
  35690. + read_buf[i] = data;
  35691. + }
  35692. +
  35693. + /* restore registers */
  35694. + __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
  35695. + __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
  35696. + /* flush write */
  35697. + __raw_readl(base + AR71XX_GPIO_REG_OUT);
  35698. +
  35699. + /* disable latch */
  35700. + gpio_set_value_cansleep(rbni->gpio_nle, 1);
  35701. +
  35702. + /* disable read mode */
  35703. + gpio_set_value_cansleep(rbni->gpio_read, 0);
  35704. +}
  35705. +
  35706. +static int rb91x_nand_dev_ready(struct mtd_info *mtd)
  35707. +{
  35708. + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
  35709. +
  35710. + return gpio_get_value_cansleep(rbni->gpio_rdy);
  35711. +}
  35712. +
  35713. +static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
  35714. + unsigned int ctrl)
  35715. +{
  35716. + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
  35717. +
  35718. + if (ctrl & NAND_CTRL_CHANGE) {
  35719. + gpio_set_value_cansleep(rbni->gpio_cle,
  35720. + (ctrl & NAND_CLE) ? 1 : 0);
  35721. + gpio_set_value_cansleep(rbni->gpio_ale,
  35722. + (ctrl & NAND_ALE) ? 1 : 0);
  35723. + gpio_set_value_cansleep(rbni->gpio_nce,
  35724. + (ctrl & NAND_NCE) ? 0 : 1);
  35725. + }
  35726. +
  35727. + if (cmd != NAND_CMD_NONE) {
  35728. + u8 t = cmd;
  35729. +
  35730. + rb91x_nand_write(rbni, &t, 1);
  35731. + }
  35732. +}
  35733. +
  35734. +static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
  35735. +{
  35736. + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
  35737. + u8 data = 0xff;
  35738. +
  35739. + rb91x_nand_read(rbni, &data, 1);
  35740. +
  35741. + return data;
  35742. +}
  35743. +
  35744. +static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  35745. +{
  35746. + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
  35747. +
  35748. + rb91x_nand_read(rbni, buf, len);
  35749. +}
  35750. +
  35751. +static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  35752. +{
  35753. + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
  35754. +
  35755. + rb91x_nand_write(rbni, buf, len);
  35756. +}
  35757. +
  35758. +static int rb91x_nand_gpio_init(struct rb91x_nand_info *info)
  35759. +{
  35760. + int ret;
  35761. +
  35762. + /*
  35763. + * Ensure that the LATCH is disabled before initializing
  35764. + * control lines.
  35765. + */
  35766. + ret = devm_gpio_request_one(info->dev, info->gpio_nle,
  35767. + GPIOF_OUT_INIT_HIGH, "LATCH enable");
  35768. + if (ret)
  35769. + return ret;
  35770. +
  35771. + ret = devm_gpio_request_one(info->dev, info->gpio_nce,
  35772. + GPIOF_OUT_INIT_HIGH, "NAND nCE");
  35773. + if (ret)
  35774. + return ret;
  35775. +
  35776. + ret = devm_gpio_request_one(info->dev, info->gpio_nrw,
  35777. + GPIOF_OUT_INIT_HIGH, "NAND nRW");
  35778. + if (ret)
  35779. + return ret;
  35780. +
  35781. + ret = devm_gpio_request_one(info->dev, info->gpio_cle,
  35782. + GPIOF_OUT_INIT_LOW, "NAND CLE");
  35783. + if (ret)
  35784. + return ret;
  35785. +
  35786. + ret = devm_gpio_request_one(info->dev, info->gpio_ale,
  35787. + GPIOF_OUT_INIT_LOW, "NAND ALE");
  35788. + if (ret)
  35789. + return ret;
  35790. +
  35791. + ret = devm_gpio_request_one(info->dev, info->gpio_read,
  35792. + GPIOF_OUT_INIT_LOW, "NAND READ");
  35793. + if (ret)
  35794. + return ret;
  35795. +
  35796. + ret = devm_gpio_request_one(info->dev, info->gpio_rdy,
  35797. + GPIOF_IN, "NAND RDY");
  35798. + return ret;
  35799. +}
  35800. +
  35801. +static int rb91x_nand_probe(struct platform_device *pdev)
  35802. +{
  35803. + struct rb91x_nand_info *rbni;
  35804. + struct rb91x_nand_platform_data *pdata;
  35805. + int ret;
  35806. +
  35807. + pr_info(DRV_DESC "\n");
  35808. +
  35809. + pdata = dev_get_platdata(&pdev->dev);
  35810. + if (!pdata)
  35811. + return -EINVAL;
  35812. +
  35813. + rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL);
  35814. + if (!rbni)
  35815. + return -ENOMEM;
  35816. +
  35817. + rbni->dev = &pdev->dev;
  35818. + rbni->gpio_nce = pdata->gpio_nce;
  35819. + rbni->gpio_ale = pdata->gpio_ale;
  35820. + rbni->gpio_cle = pdata->gpio_cle;
  35821. + rbni->gpio_read = pdata->gpio_read;
  35822. + rbni->gpio_nrw = pdata->gpio_nrw;
  35823. + rbni->gpio_rdy = pdata->gpio_rdy;
  35824. + rbni->gpio_nle = pdata->gpio_nle;
  35825. +
  35826. + rbni->chip.priv = &rbni;
  35827. + rbni->mtd.priv = &rbni->chip;
  35828. + rbni->mtd.owner = THIS_MODULE;
  35829. +
  35830. + rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl;
  35831. + rbni->chip.dev_ready = rb91x_nand_dev_ready;
  35832. + rbni->chip.read_byte = rb91x_nand_read_byte;
  35833. + rbni->chip.write_buf = rb91x_nand_write_buf;
  35834. + rbni->chip.read_buf = rb91x_nand_read_buf;
  35835. +
  35836. + rbni->chip.chip_delay = 25;
  35837. + rbni->chip.ecc.mode = NAND_ECC_SOFT;
  35838. +
  35839. + platform_set_drvdata(pdev, rbni);
  35840. +
  35841. + ret = rb91x_nand_gpio_init(rbni);
  35842. + if (ret)
  35843. + return ret;
  35844. +
  35845. + ret = nand_scan_ident(&rbni->mtd, 1, NULL);
  35846. + if (ret)
  35847. + return ret;
  35848. +
  35849. + if (rbni->mtd.writesize == 512)
  35850. + rbni->chip.ecc.layout = &rb91x_nand_ecclayout;
  35851. +
  35852. + ret = nand_scan_tail(&rbni->mtd);
  35853. + if (ret)
  35854. + return ret;
  35855. +
  35856. + ret = mtd_device_register(&rbni->mtd, rb91x_nand_partitions,
  35857. + ARRAY_SIZE(rb91x_nand_partitions));
  35858. + if (ret)
  35859. + goto err_release_nand;
  35860. +
  35861. + return 0;
  35862. +
  35863. +err_release_nand:
  35864. + nand_release(&rbni->mtd);
  35865. + return ret;
  35866. +}
  35867. +
  35868. +static int rb91x_nand_remove(struct platform_device *pdev)
  35869. +{
  35870. + struct rb91x_nand_info *info = platform_get_drvdata(pdev);
  35871. +
  35872. + nand_release(&info->mtd);
  35873. +
  35874. + return 0;
  35875. +}
  35876. +
  35877. +static struct platform_driver rb91x_nand_driver = {
  35878. + .probe = rb91x_nand_probe,
  35879. + .remove = rb91x_nand_remove,
  35880. + .driver = {
  35881. + .name = RB91X_NAND_DRIVER_NAME,
  35882. + .owner = THIS_MODULE,
  35883. + },
  35884. +};
  35885. +
  35886. +module_platform_driver(rb91x_nand_driver);
  35887. +
  35888. +MODULE_DESCRIPTION(DRV_DESC);
  35889. +MODULE_VERSION(DRV_VERSION);
  35890. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  35891. +MODULE_LICENSE("GPL v2");
  35892. diff -Nur linux-4.1.43.orig/drivers/mtd/redboot.c linux-4.1.43/drivers/mtd/redboot.c
  35893. --- linux-4.1.43.orig/drivers/mtd/redboot.c 2017-08-06 01:56:14.000000000 +0200
  35894. +++ linux-4.1.43/drivers/mtd/redboot.c 2017-08-06 20:02:16.000000000 +0200
  35895. @@ -76,12 +76,18 @@
  35896. static char nullstring[] = "unallocated";
  35897. #endif
  35898. + buf = vmalloc(master->erasesize);
  35899. + if (!buf)
  35900. + return -ENOMEM;
  35901. +
  35902. + restart:
  35903. if ( directory < 0 ) {
  35904. offset = master->size + directory * master->erasesize;
  35905. while (mtd_block_isbad(master, offset)) {
  35906. if (!offset) {
  35907. nogood:
  35908. printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
  35909. + vfree(buf);
  35910. return -EIO;
  35911. }
  35912. offset -= master->erasesize;
  35913. @@ -94,10 +100,6 @@
  35914. goto nogood;
  35915. }
  35916. }
  35917. - buf = vmalloc(master->erasesize);
  35918. -
  35919. - if (!buf)
  35920. - return -ENOMEM;
  35921. printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
  35922. master->name, offset);
  35923. @@ -170,6 +172,11 @@
  35924. }
  35925. if (i == numslots) {
  35926. /* Didn't find it */
  35927. + if (offset + master->erasesize < master->size) {
  35928. + /* not at the end of the flash yet, maybe next block :) */
  35929. + directory++;
  35930. + goto restart;
  35931. + }
  35932. printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
  35933. master->name);
  35934. ret = 0;
  35935. diff -Nur linux-4.1.43.orig/drivers/mtd/tplinkpart.c linux-4.1.43/drivers/mtd/tplinkpart.c
  35936. --- linux-4.1.43.orig/drivers/mtd/tplinkpart.c 1970-01-01 01:00:00.000000000 +0100
  35937. +++ linux-4.1.43/drivers/mtd/tplinkpart.c 2017-08-06 20:02:16.000000000 +0200
  35938. @@ -0,0 +1,222 @@
  35939. +/*
  35940. + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  35941. + *
  35942. + * This program is free software; you can redistribute it and/or modify it
  35943. + * under the terms of the GNU General Public License version 2 as published
  35944. + * by the Free Software Foundation.
  35945. + *
  35946. + */
  35947. +
  35948. +#include <linux/kernel.h>
  35949. +#include <linux/module.h>
  35950. +#include <linux/slab.h>
  35951. +#include <linux/vmalloc.h>
  35952. +#include <linux/magic.h>
  35953. +
  35954. +#include <linux/mtd/mtd.h>
  35955. +#include <linux/mtd/partitions.h>
  35956. +
  35957. +#define TPLINK_NUM_PARTS 5
  35958. +#define TPLINK_HEADER_V1 0x01000000
  35959. +#define TPLINK_HEADER_V2 0x02000000
  35960. +#define MD5SUM_LEN 16
  35961. +
  35962. +#define TPLINK_ART_LEN 0x10000
  35963. +#define TPLINK_KERNEL_OFFS 0x20000
  35964. +#define TPLINK_64K_KERNEL_OFFS 0x10000
  35965. +
  35966. +struct tplink_fw_header {
  35967. + uint32_t version; /* header version */
  35968. + char vendor_name[24];
  35969. + char fw_version[36];
  35970. + uint32_t hw_id; /* hardware id */
  35971. + uint32_t hw_rev; /* hardware revision */
  35972. + uint32_t unk1;
  35973. + uint8_t md5sum1[MD5SUM_LEN];
  35974. + uint32_t unk2;
  35975. + uint8_t md5sum2[MD5SUM_LEN];
  35976. + uint32_t unk3;
  35977. + uint32_t kernel_la; /* kernel load address */
  35978. + uint32_t kernel_ep; /* kernel entry point */
  35979. + uint32_t fw_length; /* total length of the firmware */
  35980. + uint32_t kernel_ofs; /* kernel data offset */
  35981. + uint32_t kernel_len; /* kernel data length */
  35982. + uint32_t rootfs_ofs; /* rootfs data offset */
  35983. + uint32_t rootfs_len; /* rootfs data length */
  35984. + uint32_t boot_ofs; /* bootloader data offset */
  35985. + uint32_t boot_len; /* bootloader data length */
  35986. + uint8_t pad[360];
  35987. +} __attribute__ ((packed));
  35988. +
  35989. +static struct tplink_fw_header *
  35990. +tplink_read_header(struct mtd_info *mtd, size_t offset)
  35991. +{
  35992. + struct tplink_fw_header *header;
  35993. + size_t header_len;
  35994. + size_t retlen;
  35995. + int ret;
  35996. + u32 t;
  35997. +
  35998. + header = vmalloc(sizeof(*header));
  35999. + if (!header)
  36000. + goto err;
  36001. +
  36002. + header_len = sizeof(struct tplink_fw_header);
  36003. + ret = mtd_read(mtd, offset, header_len, &retlen,
  36004. + (unsigned char *) header);
  36005. + if (ret)
  36006. + goto err_free_header;
  36007. +
  36008. + if (retlen != header_len)
  36009. + goto err_free_header;
  36010. +
  36011. + /* sanity checks */
  36012. + t = be32_to_cpu(header->version);
  36013. + if ((t != TPLINK_HEADER_V1) && (t != TPLINK_HEADER_V2))
  36014. + goto err_free_header;
  36015. +
  36016. + t = be32_to_cpu(header->kernel_ofs);
  36017. + if (t != header_len)
  36018. + goto err_free_header;
  36019. +
  36020. + return header;
  36021. +
  36022. +err_free_header:
  36023. + vfree(header);
  36024. +err:
  36025. + return NULL;
  36026. +}
  36027. +
  36028. +static int tplink_check_rootfs_magic(struct mtd_info *mtd, size_t offset)
  36029. +{
  36030. + u32 magic;
  36031. + size_t retlen;
  36032. + int ret;
  36033. +
  36034. + ret = mtd_read(mtd, offset, sizeof(magic), &retlen,
  36035. + (unsigned char *) &magic);
  36036. + if (ret)
  36037. + return ret;
  36038. +
  36039. + if (retlen != sizeof(magic))
  36040. + return -EIO;
  36041. +
  36042. + if (le32_to_cpu(magic) != SQUASHFS_MAGIC &&
  36043. + magic != 0x19852003)
  36044. + return -EINVAL;
  36045. +
  36046. + return 0;
  36047. +}
  36048. +
  36049. +static int tplink_parse_partitions_offset(struct mtd_info *master,
  36050. + struct mtd_partition **pparts,
  36051. + struct mtd_part_parser_data *data,
  36052. + size_t offset)
  36053. +{
  36054. + struct mtd_partition *parts;
  36055. + struct tplink_fw_header *header;
  36056. + int nr_parts;
  36057. + size_t art_offset;
  36058. + size_t rootfs_offset;
  36059. + size_t squashfs_offset;
  36060. + int ret;
  36061. +
  36062. + nr_parts = TPLINK_NUM_PARTS;
  36063. + parts = kzalloc(nr_parts * sizeof(struct mtd_partition), GFP_KERNEL);
  36064. + if (!parts) {
  36065. + ret = -ENOMEM;
  36066. + goto err;
  36067. + }
  36068. +
  36069. + header = tplink_read_header(master, offset);
  36070. + if (!header) {
  36071. + pr_notice("%s: no TP-Link header found\n", master->name);
  36072. + ret = -ENODEV;
  36073. + goto err_free_parts;
  36074. + }
  36075. +
  36076. + squashfs_offset = offset + sizeof(struct tplink_fw_header) +
  36077. + be32_to_cpu(header->kernel_len);
  36078. +
  36079. + ret = tplink_check_rootfs_magic(master, squashfs_offset);
  36080. + if (ret == 0)
  36081. + rootfs_offset = squashfs_offset;
  36082. + else
  36083. + rootfs_offset = offset + be32_to_cpu(header->rootfs_ofs);
  36084. +
  36085. + art_offset = master->size - TPLINK_ART_LEN;
  36086. +
  36087. + parts[0].name = "u-boot";
  36088. + parts[0].offset = 0;
  36089. + parts[0].size = offset;
  36090. + parts[0].mask_flags = MTD_WRITEABLE;
  36091. +
  36092. + parts[1].name = "kernel";
  36093. + parts[1].offset = offset;
  36094. + parts[1].size = rootfs_offset - offset;
  36095. +
  36096. + parts[2].name = "rootfs";
  36097. + parts[2].offset = rootfs_offset;
  36098. + parts[2].size = art_offset - rootfs_offset;
  36099. +
  36100. + parts[3].name = "art";
  36101. + parts[3].offset = art_offset;
  36102. + parts[3].size = TPLINK_ART_LEN;
  36103. + parts[3].mask_flags = MTD_WRITEABLE;
  36104. +
  36105. + parts[4].name = "firmware";
  36106. + parts[4].offset = offset;
  36107. + parts[4].size = art_offset - offset;
  36108. +
  36109. + vfree(header);
  36110. +
  36111. + *pparts = parts;
  36112. + return nr_parts;
  36113. +
  36114. +err_free_parts:
  36115. + kfree(parts);
  36116. +err:
  36117. + *pparts = NULL;
  36118. + return ret;
  36119. +}
  36120. +
  36121. +static int tplink_parse_partitions(struct mtd_info *master,
  36122. + struct mtd_partition **pparts,
  36123. + struct mtd_part_parser_data *data)
  36124. +{
  36125. + return tplink_parse_partitions_offset(master, pparts, data,
  36126. + TPLINK_KERNEL_OFFS);
  36127. +}
  36128. +
  36129. +static int tplink_parse_64k_partitions(struct mtd_info *master,
  36130. + struct mtd_partition **pparts,
  36131. + struct mtd_part_parser_data *data)
  36132. +{
  36133. + return tplink_parse_partitions_offset(master, pparts, data,
  36134. + TPLINK_64K_KERNEL_OFFS);
  36135. +}
  36136. +
  36137. +static struct mtd_part_parser tplink_parser = {
  36138. + .owner = THIS_MODULE,
  36139. + .parse_fn = tplink_parse_partitions,
  36140. + .name = "tp-link",
  36141. +};
  36142. +
  36143. +static struct mtd_part_parser tplink_64k_parser = {
  36144. + .owner = THIS_MODULE,
  36145. + .parse_fn = tplink_parse_64k_partitions,
  36146. + .name = "tp-link-64k",
  36147. +};
  36148. +
  36149. +static int __init tplink_parser_init(void)
  36150. +{
  36151. + register_mtd_parser(&tplink_parser);
  36152. + register_mtd_parser(&tplink_64k_parser);
  36153. +
  36154. + return 0;
  36155. +}
  36156. +
  36157. +module_init(tplink_parser_init);
  36158. +
  36159. +MODULE_LICENSE("GPL v2");
  36160. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  36161. diff -Nur linux-4.1.43.orig/drivers/net/dsa/Kconfig linux-4.1.43/drivers/net/dsa/Kconfig
  36162. --- linux-4.1.43.orig/drivers/net/dsa/Kconfig 2017-08-06 01:56:14.000000000 +0200
  36163. +++ linux-4.1.43/drivers/net/dsa/Kconfig 2017-08-06 20:02:16.000000000 +0200
  36164. @@ -13,6 +13,13 @@
  36165. This enables support for the Marvell 88E6060 ethernet switch
  36166. chip.
  36167. +config NET_DSA_MV88E6063
  36168. + bool "Marvell 88E6063 ethernet switch chip support"
  36169. + select NET_DSA_TAG_TRAILER
  36170. + ---help---
  36171. + This enables support for the Marvell 88E6063 ethernet switch
  36172. + chip
  36173. +
  36174. config NET_DSA_MV88E6XXX_NEED_PPU
  36175. bool
  36176. default n
  36177. diff -Nur linux-4.1.43.orig/drivers/net/dsa/Makefile linux-4.1.43/drivers/net/dsa/Makefile
  36178. --- linux-4.1.43.orig/drivers/net/dsa/Makefile 2017-08-06 01:56:14.000000000 +0200
  36179. +++ linux-4.1.43/drivers/net/dsa/Makefile 2017-08-06 20:02:16.000000000 +0200
  36180. @@ -1,4 +1,5 @@
  36181. obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
  36182. +obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
  36183. obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o
  36184. mv88e6xxx_drv-y += mv88e6xxx.o
  36185. ifdef CONFIG_NET_DSA_MV88E6123_61_65
  36186. diff -Nur linux-4.1.43.orig/drivers/net/dsa/mv88e6063.c linux-4.1.43/drivers/net/dsa/mv88e6063.c
  36187. --- linux-4.1.43.orig/drivers/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100
  36188. +++ linux-4.1.43/drivers/net/dsa/mv88e6063.c 2017-08-06 20:02:16.000000000 +0200
  36189. @@ -0,0 +1,311 @@
  36190. +/*
  36191. + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips
  36192. + * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
  36193. + *
  36194. + * This driver was base on: net/dsa/mv88e6060.c
  36195. + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips
  36196. + * Copyright (c) 2008-2009 Marvell Semiconductor
  36197. + *
  36198. + * This program is free software; you can redistribute it and/or modify
  36199. + * it under the terms of the GNU General Public License as published by
  36200. + * the Free Software Foundation; either version 2 of the License, or
  36201. + * (at your option) any later version.
  36202. + */
  36203. +
  36204. +#include <linux/version.h>
  36205. +#include <linux/list.h>
  36206. +#include <linux/netdevice.h>
  36207. +#include <linux/phy.h>
  36208. +#include <net/dsa.h>
  36209. +
  36210. +#define REG_BASE 0x10
  36211. +#define REG_PHY(p) (REG_BASE + (p))
  36212. +#define REG_PORT(p) (REG_BASE + 8 + (p))
  36213. +#define REG_GLOBAL (REG_BASE + 0x0f)
  36214. +#define NUM_PORTS 7
  36215. +
  36216. +static int reg_read(struct dsa_switch *ds, int addr, int reg)
  36217. +{
  36218. +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
  36219. + return mdiobus_read(ds->master_mii_bus, addr, reg);
  36220. +#else
  36221. + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  36222. + return mdiobus_read(bus, addr, reg);
  36223. +#endif
  36224. +}
  36225. +
  36226. +#define REG_READ(addr, reg) \
  36227. + ({ \
  36228. + int __ret; \
  36229. + \
  36230. + __ret = reg_read(ds, addr, reg); \
  36231. + if (__ret < 0) \
  36232. + return __ret; \
  36233. + __ret; \
  36234. + })
  36235. +
  36236. +
  36237. +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  36238. +{
  36239. +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
  36240. + return mdiobus_write(ds->master_mii_bus, addr, reg, val);
  36241. +#else
  36242. + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  36243. + return mdiobus_write(bus, addr, reg, val);
  36244. +#endif
  36245. +}
  36246. +
  36247. +#define REG_WRITE(addr, reg, val) \
  36248. + ({ \
  36249. + int __ret; \
  36250. + \
  36251. + __ret = reg_write(ds, addr, reg, val); \
  36252. + if (__ret < 0) \
  36253. + return __ret; \
  36254. + })
  36255. +
  36256. +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
  36257. +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr)
  36258. +{
  36259. +#else
  36260. +static char *mv88e6063_probe(struct device *host_dev, int sw_addr)
  36261. +{
  36262. + struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  36263. +#endif
  36264. + int ret;
  36265. +
  36266. + ret = mdiobus_read(bus, REG_PORT(0), 0x03);
  36267. + if (ret >= 0) {
  36268. + ret &= 0xfff0;
  36269. + if (ret == 0x1530)
  36270. + return "Marvell 88E6063";
  36271. + }
  36272. +
  36273. + return NULL;
  36274. +}
  36275. +
  36276. +static int mv88e6063_switch_reset(struct dsa_switch *ds)
  36277. +{
  36278. + int i;
  36279. + int ret;
  36280. +
  36281. + /*
  36282. + * Set all ports to the disabled state.
  36283. + */
  36284. + for (i = 0; i < NUM_PORTS; i++) {
  36285. + ret = REG_READ(REG_PORT(i), 0x04);
  36286. + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  36287. + }
  36288. +
  36289. + /*
  36290. + * Wait for transmit queues to drain.
  36291. + */
  36292. + msleep(2);
  36293. +
  36294. + /*
  36295. + * Reset the switch.
  36296. + */
  36297. + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
  36298. +
  36299. + /*
  36300. + * Wait up to one second for reset to complete.
  36301. + */
  36302. + for (i = 0; i < 1000; i++) {
  36303. + ret = REG_READ(REG_GLOBAL, 0x00);
  36304. + if ((ret & 0x8000) == 0x0000)
  36305. + break;
  36306. +
  36307. + msleep(1);
  36308. + }
  36309. + if (i == 1000)
  36310. + return -ETIMEDOUT;
  36311. +
  36312. + return 0;
  36313. +}
  36314. +
  36315. +static int mv88e6063_setup_global(struct dsa_switch *ds)
  36316. +{
  36317. + /*
  36318. + * Disable discarding of frames with excessive collisions,
  36319. + * set the maximum frame size to 1536 bytes, and mask all
  36320. + * interrupt sources.
  36321. + */
  36322. + REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
  36323. +
  36324. + /*
  36325. + * Enable automatic address learning, set the address
  36326. + * database size to 1024 entries, and set the default aging
  36327. + * time to 5 minutes.
  36328. + */
  36329. + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
  36330. +
  36331. + return 0;
  36332. +}
  36333. +
  36334. +static int mv88e6063_setup_port(struct dsa_switch *ds, int p)
  36335. +{
  36336. + int addr = REG_PORT(p);
  36337. +
  36338. + /*
  36339. + * Do not force flow control, disable Ingress and Egress
  36340. + * Header tagging, disable VLAN tunneling, and set the port
  36341. + * state to Forwarding. Additionally, if this is the CPU
  36342. + * port, enable Ingress and Egress Trailer tagging mode.
  36343. + */
  36344. + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
  36345. +
  36346. + /*
  36347. + * Port based VLAN map: give each port its own address
  36348. + * database, allow the CPU port to talk to each of the 'real'
  36349. + * ports, and allow each of the 'real' ports to only talk to
  36350. + * the CPU port.
  36351. + */
  36352. + REG_WRITE(addr, 0x06,
  36353. + ((p & 0xf) << 12) |
  36354. + (dsa_is_cpu_port(ds, p) ?
  36355. + ds->phys_port_mask :
  36356. + (1 << ds->dst->cpu_port)));
  36357. +
  36358. + /*
  36359. + * Port Association Vector: when learning source addresses
  36360. + * of packets, add the address to the address database using
  36361. + * a port bitmap that has only the bit for this port set and
  36362. + * the other bits clear.
  36363. + */
  36364. + REG_WRITE(addr, 0x0b, 1 << p);
  36365. +
  36366. + return 0;
  36367. +}
  36368. +
  36369. +static int mv88e6063_setup(struct dsa_switch *ds)
  36370. +{
  36371. + int i;
  36372. + int ret;
  36373. +
  36374. + ret = mv88e6063_switch_reset(ds);
  36375. + if (ret < 0)
  36376. + return ret;
  36377. +
  36378. + /* @@@ initialise atu */
  36379. +
  36380. + ret = mv88e6063_setup_global(ds);
  36381. + if (ret < 0)
  36382. + return ret;
  36383. +
  36384. + for (i = 0; i < NUM_PORTS; i++) {
  36385. + ret = mv88e6063_setup_port(ds, i);
  36386. + if (ret < 0)
  36387. + return ret;
  36388. + }
  36389. +
  36390. + return 0;
  36391. +}
  36392. +
  36393. +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr)
  36394. +{
  36395. + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
  36396. + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
  36397. + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
  36398. +
  36399. + return 0;
  36400. +}
  36401. +
  36402. +static int mv88e6063_port_to_phy_addr(int port)
  36403. +{
  36404. + if (port >= 0 && port <= NUM_PORTS)
  36405. + return REG_PHY(port);
  36406. + return -1;
  36407. +}
  36408. +
  36409. +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum)
  36410. +{
  36411. + int addr;
  36412. +
  36413. + addr = mv88e6063_port_to_phy_addr(port);
  36414. + if (addr == -1)
  36415. + return 0xffff;
  36416. +
  36417. + return reg_read(ds, addr, regnum);
  36418. +}
  36419. +
  36420. +static int
  36421. +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
  36422. +{
  36423. + int addr;
  36424. +
  36425. + addr = mv88e6063_port_to_phy_addr(port);
  36426. + if (addr == -1)
  36427. + return 0xffff;
  36428. +
  36429. + return reg_write(ds, addr, regnum, val);
  36430. +}
  36431. +
  36432. +static void mv88e6063_poll_link(struct dsa_switch *ds)
  36433. +{
  36434. + int i;
  36435. +
  36436. + for (i = 0; i < DSA_MAX_PORTS; i++) {
  36437. + struct net_device *dev;
  36438. + int uninitialized_var(port_status);
  36439. + int link;
  36440. + int speed;
  36441. + int duplex;
  36442. + int fc;
  36443. +
  36444. + dev = ds->ports[i];
  36445. + if (dev == NULL)
  36446. + continue;
  36447. +
  36448. + link = 0;
  36449. + if (dev->flags & IFF_UP) {
  36450. + port_status = reg_read(ds, REG_PORT(i), 0x00);
  36451. + if (port_status < 0)
  36452. + continue;
  36453. +
  36454. + link = !!(port_status & 0x1000);
  36455. + }
  36456. +
  36457. + if (!link) {
  36458. + if (netif_carrier_ok(dev)) {
  36459. + printk(KERN_INFO "%s: link down\n", dev->name);
  36460. + netif_carrier_off(dev);
  36461. + }
  36462. + continue;
  36463. + }
  36464. +
  36465. + speed = (port_status & 0x0100) ? 100 : 10;
  36466. + duplex = (port_status & 0x0200) ? 1 : 0;
  36467. + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
  36468. +
  36469. + if (!netif_carrier_ok(dev)) {
  36470. + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
  36471. + "flow control %sabled\n", dev->name,
  36472. + speed, duplex ? "full" : "half",
  36473. + fc ? "en" : "dis");
  36474. + netif_carrier_on(dev);
  36475. + }
  36476. + }
  36477. +}
  36478. +
  36479. +static struct dsa_switch_driver mv88e6063_switch_driver = {
  36480. + .tag_protocol = htons(ETH_P_TRAILER),
  36481. + .probe = mv88e6063_probe,
  36482. + .setup = mv88e6063_setup,
  36483. + .set_addr = mv88e6063_set_addr,
  36484. + .phy_read = mv88e6063_phy_read,
  36485. + .phy_write = mv88e6063_phy_write,
  36486. + .poll_link = mv88e6063_poll_link,
  36487. +};
  36488. +
  36489. +static int __init mv88e6063_init(void)
  36490. +{
  36491. + register_switch_driver(&mv88e6063_switch_driver);
  36492. + return 0;
  36493. +}
  36494. +module_init(mv88e6063_init);
  36495. +
  36496. +static void __exit mv88e6063_cleanup(void)
  36497. +{
  36498. + unregister_switch_driver(&mv88e6063_switch_driver);
  36499. +}
  36500. +module_exit(mv88e6063_cleanup);
  36501. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/Kconfig linux-4.1.43/drivers/net/ethernet/atheros/Kconfig
  36502. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/Kconfig 2017-08-06 01:56:14.000000000 +0200
  36503. +++ linux-4.1.43/drivers/net/ethernet/atheros/Kconfig 2017-08-06 20:02:16.000000000 +0200
  36504. @@ -5,7 +5,7 @@
  36505. config NET_VENDOR_ATHEROS
  36506. bool "Atheros devices"
  36507. default y
  36508. - depends on PCI
  36509. + depends on (PCI || ATH79)
  36510. ---help---
  36511. If you have a network (Ethernet) card belonging to this class, say Y
  36512. and read the Ethernet-HOWTO, available from
  36513. @@ -80,4 +80,6 @@
  36514. To compile this driver as a module, choose M here. The module
  36515. will be called alx.
  36516. +source drivers/net/ethernet/atheros/ag71xx/Kconfig
  36517. +
  36518. endif # NET_VENDOR_ATHEROS
  36519. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/Makefile linux-4.1.43/drivers/net/ethernet/atheros/Makefile
  36520. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/Makefile 2017-08-06 01:56:14.000000000 +0200
  36521. +++ linux-4.1.43/drivers/net/ethernet/atheros/Makefile 2017-08-06 20:02:16.000000000 +0200
  36522. @@ -2,6 +2,7 @@
  36523. # Makefile for the Atheros network device drivers.
  36524. #
  36525. +obj-$(CONFIG_AG71XX) += ag71xx/
  36526. obj-$(CONFIG_ATL1) += atlx/
  36527. obj-$(CONFIG_ATL2) += atlx/
  36528. obj-$(CONFIG_ATL1E) += atl1e/
  36529. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/Kconfig linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/Kconfig
  36530. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100
  36531. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/Kconfig 2017-08-06 20:02:16.000000000 +0200
  36532. @@ -0,0 +1,33 @@
  36533. +config AG71XX
  36534. + tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
  36535. + depends on ATH79
  36536. + select PHYLIB
  36537. + help
  36538. + If you wish to compile a kernel for AR7XXX/91XXX and enable
  36539. + ethernet support, then you should always answer Y to this.
  36540. +
  36541. +if AG71XX
  36542. +
  36543. +config AG71XX_DEBUG
  36544. + bool "Atheros AR71xx built-in ethernet driver debugging"
  36545. + default n
  36546. + help
  36547. + Atheros AR71xx built-in ethernet driver debugging messages.
  36548. +
  36549. +config AG71XX_DEBUG_FS
  36550. + bool "Atheros AR71xx built-in ethernet driver debugfs support"
  36551. + depends on DEBUG_FS
  36552. + default n
  36553. + help
  36554. + Say Y, if you need access to various statistics provided by
  36555. + the ag71xx driver.
  36556. +
  36557. +config AG71XX_AR8216_SUPPORT
  36558. + bool "special support for the Atheros AR8216 switch"
  36559. + default n
  36560. + default y if ATH79_MACH_WNR2000 || ATH79_MACH_MZK_W04NU
  36561. + help
  36562. + Say 'y' here if you want to enable special support for the
  36563. + Atheros AR8216 switch found on some boards.
  36564. +
  36565. +endif
  36566. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/Makefile linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/Makefile
  36567. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/Makefile 1970-01-01 01:00:00.000000000 +0100
  36568. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/Makefile 2017-08-06 20:02:16.000000000 +0200
  36569. @@ -0,0 +1,15 @@
  36570. +#
  36571. +# Makefile for the Atheros AR71xx built-in ethernet macs
  36572. +#
  36573. +
  36574. +ag71xx-y += ag71xx_main.o
  36575. +ag71xx-y += ag71xx_ethtool.o
  36576. +ag71xx-y += ag71xx_phy.o
  36577. +ag71xx-y += ag71xx_mdio.o
  36578. +ag71xx-y += ag71xx_ar7240.o
  36579. +
  36580. +ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o
  36581. +ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o
  36582. +
  36583. +obj-$(CONFIG_AG71XX) += ag71xx.o
  36584. +
  36585. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx.h linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
  36586. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx.h 1970-01-01 01:00:00.000000000 +0100
  36587. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx.h 2017-08-06 20:02:16.000000000 +0200
  36588. @@ -0,0 +1,485 @@
  36589. +/*
  36590. + * Atheros AR71xx built-in ethernet mac driver
  36591. + *
  36592. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  36593. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  36594. + *
  36595. + * Based on Atheros' AG7100 driver
  36596. + *
  36597. + * This program is free software; you can redistribute it and/or modify it
  36598. + * under the terms of the GNU General Public License version 2 as published
  36599. + * by the Free Software Foundation.
  36600. + */
  36601. +
  36602. +#ifndef __AG71XX_H
  36603. +#define __AG71XX_H
  36604. +
  36605. +#include <linux/kernel.h>
  36606. +#include <linux/version.h>
  36607. +#include <linux/module.h>
  36608. +#include <linux/init.h>
  36609. +#include <linux/types.h>
  36610. +#include <linux/random.h>
  36611. +#include <linux/spinlock.h>
  36612. +#include <linux/interrupt.h>
  36613. +#include <linux/platform_device.h>
  36614. +#include <linux/ethtool.h>
  36615. +#include <linux/etherdevice.h>
  36616. +#include <linux/if_vlan.h>
  36617. +#include <linux/phy.h>
  36618. +#include <linux/skbuff.h>
  36619. +#include <linux/dma-mapping.h>
  36620. +#include <linux/workqueue.h>
  36621. +
  36622. +#include <linux/bitops.h>
  36623. +
  36624. +#include <asm/mach-ath79/ar71xx_regs.h>
  36625. +#include <asm/mach-ath79/ath79.h>
  36626. +#include <asm/mach-ath79/ag71xx_platform.h>
  36627. +
  36628. +#define AG71XX_DRV_NAME "ag71xx"
  36629. +#define AG71XX_DRV_VERSION "0.5.35"
  36630. +
  36631. +#define AG71XX_NAPI_WEIGHT 64
  36632. +#define AG71XX_OOM_REFILL (1 + HZ/10)
  36633. +
  36634. +#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  36635. +#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
  36636. +#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  36637. +
  36638. +#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  36639. +#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  36640. +
  36641. +#define AG71XX_TX_MTU_LEN 1540
  36642. +
  36643. +#define AG71XX_TX_RING_SPLIT 512
  36644. +#define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
  36645. + AG71XX_TX_RING_SPLIT)
  36646. +#define AG71XX_TX_RING_SIZE_DEFAULT 48
  36647. +#define AG71XX_RX_RING_SIZE_DEFAULT 128
  36648. +
  36649. +#define AG71XX_TX_RING_SIZE_MAX 48
  36650. +#define AG71XX_RX_RING_SIZE_MAX 128
  36651. +
  36652. +#ifdef CONFIG_AG71XX_DEBUG
  36653. +#define DBG(fmt, args...) pr_debug(fmt, ## args)
  36654. +#else
  36655. +#define DBG(fmt, args...) do {} while (0)
  36656. +#endif
  36657. +
  36658. +#define ag71xx_assert(_cond) \
  36659. +do { \
  36660. + if (_cond) \
  36661. + break; \
  36662. + printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
  36663. + BUG(); \
  36664. +} while (0)
  36665. +
  36666. +struct ag71xx_desc {
  36667. + u32 data;
  36668. + u32 ctrl;
  36669. +#define DESC_EMPTY BIT(31)
  36670. +#define DESC_MORE BIT(24)
  36671. +#define DESC_PKTLEN_M 0xfff
  36672. + u32 next;
  36673. + u32 pad;
  36674. +} __attribute__((aligned(4)));
  36675. +
  36676. +struct ag71xx_buf {
  36677. + union {
  36678. + struct sk_buff *skb;
  36679. + void *rx_buf;
  36680. + };
  36681. + union {
  36682. + dma_addr_t dma_addr;
  36683. + unsigned long timestamp;
  36684. + };
  36685. + unsigned int len;
  36686. +};
  36687. +
  36688. +struct ag71xx_ring {
  36689. + struct ag71xx_buf *buf;
  36690. + u8 *descs_cpu;
  36691. + dma_addr_t descs_dma;
  36692. + u16 desc_split;
  36693. + u16 desc_size;
  36694. + unsigned int curr;
  36695. + unsigned int dirty;
  36696. + unsigned int size;
  36697. +};
  36698. +
  36699. +struct ag71xx_mdio {
  36700. + struct mii_bus *mii_bus;
  36701. + int mii_irq[PHY_MAX_ADDR];
  36702. + void __iomem *mdio_base;
  36703. + struct ag71xx_mdio_platform_data *pdata;
  36704. +};
  36705. +
  36706. +struct ag71xx_int_stats {
  36707. + unsigned long rx_pr;
  36708. + unsigned long rx_be;
  36709. + unsigned long rx_of;
  36710. + unsigned long tx_ps;
  36711. + unsigned long tx_be;
  36712. + unsigned long tx_ur;
  36713. + unsigned long total;
  36714. +};
  36715. +
  36716. +struct ag71xx_napi_stats {
  36717. + unsigned long napi_calls;
  36718. + unsigned long rx_count;
  36719. + unsigned long rx_packets;
  36720. + unsigned long rx_packets_max;
  36721. + unsigned long tx_count;
  36722. + unsigned long tx_packets;
  36723. + unsigned long tx_packets_max;
  36724. +
  36725. + unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
  36726. + unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
  36727. +};
  36728. +
  36729. +struct ag71xx_debug {
  36730. + struct dentry *debugfs_dir;
  36731. +
  36732. + struct ag71xx_int_stats int_stats;
  36733. + struct ag71xx_napi_stats napi_stats;
  36734. +};
  36735. +
  36736. +struct ag71xx {
  36737. + void __iomem *mac_base;
  36738. +
  36739. + spinlock_t lock;
  36740. + struct platform_device *pdev;
  36741. + struct net_device *dev;
  36742. + struct napi_struct napi;
  36743. + u32 msg_enable;
  36744. +
  36745. + struct ag71xx_desc *stop_desc;
  36746. + dma_addr_t stop_desc_dma;
  36747. +
  36748. + struct ag71xx_ring rx_ring;
  36749. + struct ag71xx_ring tx_ring;
  36750. +
  36751. + struct mii_bus *mii_bus;
  36752. + struct phy_device *phy_dev;
  36753. + void *phy_priv;
  36754. +
  36755. + unsigned int link;
  36756. + unsigned int speed;
  36757. + int duplex;
  36758. +
  36759. + unsigned int max_frame_len;
  36760. + unsigned int desc_pktlen_mask;
  36761. + unsigned int rx_buf_size;
  36762. +
  36763. + struct work_struct restart_work;
  36764. + struct delayed_work link_work;
  36765. + struct timer_list oom_timer;
  36766. +
  36767. +#ifdef CONFIG_AG71XX_DEBUG_FS
  36768. + struct ag71xx_debug debug;
  36769. +#endif
  36770. +};
  36771. +
  36772. +extern struct ethtool_ops ag71xx_ethtool_ops;
  36773. +void ag71xx_link_adjust(struct ag71xx *ag);
  36774. +
  36775. +int ag71xx_mdio_driver_init(void) __init;
  36776. +void ag71xx_mdio_driver_exit(void);
  36777. +
  36778. +int ag71xx_phy_connect(struct ag71xx *ag);
  36779. +void ag71xx_phy_disconnect(struct ag71xx *ag);
  36780. +void ag71xx_phy_start(struct ag71xx *ag);
  36781. +void ag71xx_phy_stop(struct ag71xx *ag);
  36782. +
  36783. +static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
  36784. +{
  36785. + return ag->pdev->dev.platform_data;
  36786. +}
  36787. +
  36788. +static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
  36789. +{
  36790. + return (desc->ctrl & DESC_EMPTY) != 0;
  36791. +}
  36792. +
  36793. +static inline struct ag71xx_desc *
  36794. +ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
  36795. +{
  36796. + return (struct ag71xx_desc *) &ring->descs_cpu[idx * ring->desc_size];
  36797. +}
  36798. +
  36799. +/* Register offsets */
  36800. +#define AG71XX_REG_MAC_CFG1 0x0000
  36801. +#define AG71XX_REG_MAC_CFG2 0x0004
  36802. +#define AG71XX_REG_MAC_IPG 0x0008
  36803. +#define AG71XX_REG_MAC_HDX 0x000c
  36804. +#define AG71XX_REG_MAC_MFL 0x0010
  36805. +#define AG71XX_REG_MII_CFG 0x0020
  36806. +#define AG71XX_REG_MII_CMD 0x0024
  36807. +#define AG71XX_REG_MII_ADDR 0x0028
  36808. +#define AG71XX_REG_MII_CTRL 0x002c
  36809. +#define AG71XX_REG_MII_STATUS 0x0030
  36810. +#define AG71XX_REG_MII_IND 0x0034
  36811. +#define AG71XX_REG_MAC_IFCTL 0x0038
  36812. +#define AG71XX_REG_MAC_ADDR1 0x0040
  36813. +#define AG71XX_REG_MAC_ADDR2 0x0044
  36814. +#define AG71XX_REG_FIFO_CFG0 0x0048
  36815. +#define AG71XX_REG_FIFO_CFG1 0x004c
  36816. +#define AG71XX_REG_FIFO_CFG2 0x0050
  36817. +#define AG71XX_REG_FIFO_CFG3 0x0054
  36818. +#define AG71XX_REG_FIFO_CFG4 0x0058
  36819. +#define AG71XX_REG_FIFO_CFG5 0x005c
  36820. +#define AG71XX_REG_FIFO_RAM0 0x0060
  36821. +#define AG71XX_REG_FIFO_RAM1 0x0064
  36822. +#define AG71XX_REG_FIFO_RAM2 0x0068
  36823. +#define AG71XX_REG_FIFO_RAM3 0x006c
  36824. +#define AG71XX_REG_FIFO_RAM4 0x0070
  36825. +#define AG71XX_REG_FIFO_RAM5 0x0074
  36826. +#define AG71XX_REG_FIFO_RAM6 0x0078
  36827. +#define AG71XX_REG_FIFO_RAM7 0x007c
  36828. +
  36829. +#define AG71XX_REG_TX_CTRL 0x0180
  36830. +#define AG71XX_REG_TX_DESC 0x0184
  36831. +#define AG71XX_REG_TX_STATUS 0x0188
  36832. +#define AG71XX_REG_RX_CTRL 0x018c
  36833. +#define AG71XX_REG_RX_DESC 0x0190
  36834. +#define AG71XX_REG_RX_STATUS 0x0194
  36835. +#define AG71XX_REG_INT_ENABLE 0x0198
  36836. +#define AG71XX_REG_INT_STATUS 0x019c
  36837. +
  36838. +#define AG71XX_REG_FIFO_DEPTH 0x01a8
  36839. +#define AG71XX_REG_RX_SM 0x01b0
  36840. +#define AG71XX_REG_TX_SM 0x01b4
  36841. +
  36842. +#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
  36843. +#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
  36844. +#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
  36845. +#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
  36846. +#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
  36847. +#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
  36848. +#define MAC_CFG1_LB BIT(8) /* Loopback mode */
  36849. +#define MAC_CFG1_SR BIT(31) /* Soft Reset */
  36850. +
  36851. +#define MAC_CFG2_FDX BIT(0)
  36852. +#define MAC_CFG2_CRC_EN BIT(1)
  36853. +#define MAC_CFG2_PAD_CRC_EN BIT(2)
  36854. +#define MAC_CFG2_LEN_CHECK BIT(4)
  36855. +#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
  36856. +#define MAC_CFG2_IF_1000 BIT(9)
  36857. +#define MAC_CFG2_IF_10_100 BIT(8)
  36858. +
  36859. +#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
  36860. +#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
  36861. +#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
  36862. +#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
  36863. +#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
  36864. +#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
  36865. + | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
  36866. +
  36867. +#define FIFO_CFG0_ENABLE_SHIFT 8
  36868. +
  36869. +#define FIFO_CFG4_DE BIT(0) /* Drop Event */
  36870. +#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
  36871. +#define FIFO_CFG4_FC BIT(2) /* False Carrier */
  36872. +#define FIFO_CFG4_CE BIT(3) /* Code Error */
  36873. +#define FIFO_CFG4_CR BIT(4) /* CRC error */
  36874. +#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
  36875. +#define FIFO_CFG4_LO BIT(6) /* Length out of range */
  36876. +#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
  36877. +#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
  36878. +#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
  36879. +#define FIFO_CFG4_DR BIT(10) /* Dribble */
  36880. +#define FIFO_CFG4_LE BIT(11) /* Long Event */
  36881. +#define FIFO_CFG4_CF BIT(12) /* Control Frame */
  36882. +#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
  36883. +#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
  36884. +#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
  36885. +#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
  36886. +#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
  36887. +
  36888. +#define FIFO_CFG5_DE BIT(0) /* Drop Event */
  36889. +#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
  36890. +#define FIFO_CFG5_FC BIT(2) /* False Carrier */
  36891. +#define FIFO_CFG5_CE BIT(3) /* Code Error */
  36892. +#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
  36893. +#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
  36894. +#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
  36895. +#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
  36896. +#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
  36897. +#define FIFO_CFG5_DR BIT(9) /* Dribble */
  36898. +#define FIFO_CFG5_CF BIT(10) /* Control Frame */
  36899. +#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
  36900. +#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
  36901. +#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
  36902. +#define FIFO_CFG5_LE BIT(14) /* Long Event */
  36903. +#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
  36904. +#define FIFO_CFG5_16 BIT(16) /* unknown */
  36905. +#define FIFO_CFG5_17 BIT(17) /* unknown */
  36906. +#define FIFO_CFG5_SF BIT(18) /* Short Frame */
  36907. +#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
  36908. +
  36909. +#define AG71XX_INT_TX_PS BIT(0)
  36910. +#define AG71XX_INT_TX_UR BIT(1)
  36911. +#define AG71XX_INT_TX_BE BIT(3)
  36912. +#define AG71XX_INT_RX_PR BIT(4)
  36913. +#define AG71XX_INT_RX_OF BIT(6)
  36914. +#define AG71XX_INT_RX_BE BIT(7)
  36915. +
  36916. +#define MAC_IFCTL_SPEED BIT(16)
  36917. +
  36918. +#define MII_CFG_CLK_DIV_4 0
  36919. +#define MII_CFG_CLK_DIV_6 2
  36920. +#define MII_CFG_CLK_DIV_8 3
  36921. +#define MII_CFG_CLK_DIV_10 4
  36922. +#define MII_CFG_CLK_DIV_14 5
  36923. +#define MII_CFG_CLK_DIV_20 6
  36924. +#define MII_CFG_CLK_DIV_28 7
  36925. +#define MII_CFG_CLK_DIV_34 8
  36926. +#define MII_CFG_CLK_DIV_42 9
  36927. +#define MII_CFG_CLK_DIV_50 10
  36928. +#define MII_CFG_CLK_DIV_58 11
  36929. +#define MII_CFG_CLK_DIV_66 12
  36930. +#define MII_CFG_CLK_DIV_74 13
  36931. +#define MII_CFG_CLK_DIV_82 14
  36932. +#define MII_CFG_CLK_DIV_98 15
  36933. +#define MII_CFG_RESET BIT(31)
  36934. +
  36935. +#define MII_CMD_WRITE 0x0
  36936. +#define MII_CMD_READ 0x1
  36937. +#define MII_ADDR_SHIFT 8
  36938. +#define MII_IND_BUSY BIT(0)
  36939. +#define MII_IND_INVALID BIT(2)
  36940. +
  36941. +#define TX_CTRL_TXE BIT(0) /* Tx Enable */
  36942. +
  36943. +#define TX_STATUS_PS BIT(0) /* Packet Sent */
  36944. +#define TX_STATUS_UR BIT(1) /* Tx Underrun */
  36945. +#define TX_STATUS_BE BIT(3) /* Bus Error */
  36946. +
  36947. +#define RX_CTRL_RXE BIT(0) /* Rx Enable */
  36948. +
  36949. +#define RX_STATUS_PR BIT(0) /* Packet Received */
  36950. +#define RX_STATUS_OF BIT(2) /* Rx Overflow */
  36951. +#define RX_STATUS_BE BIT(3) /* Bus Error */
  36952. +
  36953. +static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
  36954. +{
  36955. + switch (reg) {
  36956. + case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
  36957. + case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
  36958. + case AG71XX_REG_MII_CFG:
  36959. + break;
  36960. +
  36961. + default:
  36962. + BUG();
  36963. + }
  36964. +}
  36965. +
  36966. +static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
  36967. +{
  36968. + ag71xx_check_reg_offset(ag, reg);
  36969. +
  36970. + __raw_writel(value, ag->mac_base + reg);
  36971. + /* flush write */
  36972. + (void) __raw_readl(ag->mac_base + reg);
  36973. +}
  36974. +
  36975. +static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
  36976. +{
  36977. + ag71xx_check_reg_offset(ag, reg);
  36978. +
  36979. + return __raw_readl(ag->mac_base + reg);
  36980. +}
  36981. +
  36982. +static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
  36983. +{
  36984. + void __iomem *r;
  36985. +
  36986. + ag71xx_check_reg_offset(ag, reg);
  36987. +
  36988. + r = ag->mac_base + reg;
  36989. + __raw_writel(__raw_readl(r) | mask, r);
  36990. + /* flush write */
  36991. + (void)__raw_readl(r);
  36992. +}
  36993. +
  36994. +static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
  36995. +{
  36996. + void __iomem *r;
  36997. +
  36998. + ag71xx_check_reg_offset(ag, reg);
  36999. +
  37000. + r = ag->mac_base + reg;
  37001. + __raw_writel(__raw_readl(r) & ~mask, r);
  37002. + /* flush write */
  37003. + (void) __raw_readl(r);
  37004. +}
  37005. +
  37006. +static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
  37007. +{
  37008. + ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
  37009. +}
  37010. +
  37011. +static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
  37012. +{
  37013. + ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
  37014. +}
  37015. +
  37016. +#ifdef CONFIG_AG71XX_AR8216_SUPPORT
  37017. +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
  37018. +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
  37019. + int pktlen);
  37020. +static inline int ag71xx_has_ar8216(struct ag71xx *ag)
  37021. +{
  37022. + return ag71xx_get_pdata(ag)->has_ar8216;
  37023. +}
  37024. +#else
  37025. +static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
  37026. + struct sk_buff *skb)
  37027. +{
  37028. +}
  37029. +
  37030. +static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
  37031. + struct sk_buff *skb,
  37032. + int pktlen)
  37033. +{
  37034. + return 0;
  37035. +}
  37036. +static inline int ag71xx_has_ar8216(struct ag71xx *ag)
  37037. +{
  37038. + return 0;
  37039. +}
  37040. +#endif
  37041. +
  37042. +#ifdef CONFIG_AG71XX_DEBUG_FS
  37043. +int ag71xx_debugfs_root_init(void);
  37044. +void ag71xx_debugfs_root_exit(void);
  37045. +int ag71xx_debugfs_init(struct ag71xx *ag);
  37046. +void ag71xx_debugfs_exit(struct ag71xx *ag);
  37047. +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
  37048. +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
  37049. +#else
  37050. +static inline int ag71xx_debugfs_root_init(void) { return 0; }
  37051. +static inline void ag71xx_debugfs_root_exit(void) {}
  37052. +static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
  37053. +static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
  37054. +static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
  37055. + u32 status) {}
  37056. +static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
  37057. + int rx, int tx) {}
  37058. +#endif /* CONFIG_AG71XX_DEBUG_FS */
  37059. +
  37060. +void ag71xx_ar7240_start(struct ag71xx *ag);
  37061. +void ag71xx_ar7240_stop(struct ag71xx *ag);
  37062. +int ag71xx_ar7240_init(struct ag71xx *ag);
  37063. +void ag71xx_ar7240_cleanup(struct ag71xx *ag);
  37064. +
  37065. +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
  37066. +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
  37067. +
  37068. +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
  37069. + unsigned reg_addr);
  37070. +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
  37071. + unsigned reg_addr, u16 reg_val);
  37072. +
  37073. +#endif /* _AG71XX_H */
  37074. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
  37075. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c 1970-01-01 01:00:00.000000000 +0100
  37076. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c 2017-08-06 20:02:16.000000000 +0200
  37077. @@ -0,0 +1,1229 @@
  37078. +/*
  37079. + * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
  37080. + * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
  37081. + * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
  37082. + *
  37083. + * This program is free software; you can redistribute it and/or modify it
  37084. + * under the terms of the GNU General Public License version 2 as published
  37085. + * by the Free Software Foundation.
  37086. + *
  37087. + */
  37088. +
  37089. +#include <linux/etherdevice.h>
  37090. +#include <linux/list.h>
  37091. +#include <linux/netdevice.h>
  37092. +#include <linux/phy.h>
  37093. +#include <linux/mii.h>
  37094. +#include <linux/bitops.h>
  37095. +#include <linux/switch.h>
  37096. +#include "ag71xx.h"
  37097. +
  37098. +#define BITM(_count) (BIT(_count) - 1)
  37099. +#define BITS(_shift, _count) (BITM(_count) << _shift)
  37100. +
  37101. +#define AR7240_REG_MASK_CTRL 0x00
  37102. +#define AR7240_MASK_CTRL_REVISION_M BITM(8)
  37103. +#define AR7240_MASK_CTRL_VERSION_M BITM(8)
  37104. +#define AR7240_MASK_CTRL_VERSION_S 8
  37105. +#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
  37106. +#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
  37107. +#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
  37108. +
  37109. +#define AR7240_REG_MAC_ADDR0 0x20
  37110. +#define AR7240_REG_MAC_ADDR1 0x24
  37111. +
  37112. +#define AR7240_REG_FLOOD_MASK 0x2c
  37113. +#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
  37114. +
  37115. +#define AR7240_REG_GLOBAL_CTRL 0x30
  37116. +#define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
  37117. +#define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
  37118. +
  37119. +#define AR7240_REG_VTU 0x0040
  37120. +#define AR7240_VTU_OP BITM(3)
  37121. +#define AR7240_VTU_OP_NOOP 0x0
  37122. +#define AR7240_VTU_OP_FLUSH 0x1
  37123. +#define AR7240_VTU_OP_LOAD 0x2
  37124. +#define AR7240_VTU_OP_PURGE 0x3
  37125. +#define AR7240_VTU_OP_REMOVE_PORT 0x4
  37126. +#define AR7240_VTU_ACTIVE BIT(3)
  37127. +#define AR7240_VTU_FULL BIT(4)
  37128. +#define AR7240_VTU_PORT BITS(8, 4)
  37129. +#define AR7240_VTU_PORT_S 8
  37130. +#define AR7240_VTU_VID BITS(16, 12)
  37131. +#define AR7240_VTU_VID_S 16
  37132. +#define AR7240_VTU_PRIO BITS(28, 3)
  37133. +#define AR7240_VTU_PRIO_S 28
  37134. +#define AR7240_VTU_PRIO_EN BIT(31)
  37135. +
  37136. +#define AR7240_REG_VTU_DATA 0x0044
  37137. +#define AR7240_VTUDATA_MEMBER BITS(0, 10)
  37138. +#define AR7240_VTUDATA_VALID BIT(11)
  37139. +
  37140. +#define AR7240_REG_ATU 0x50
  37141. +#define AR7240_ATU_FLUSH_ALL 0x1
  37142. +
  37143. +#define AR7240_REG_AT_CTRL 0x5c
  37144. +#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
  37145. +#define AR7240_AT_CTRL_AGE_EN BIT(17)
  37146. +#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
  37147. +#define AR7240_AT_CTRL_RESERVED BIT(19)
  37148. +#define AR7240_AT_CTRL_ARP_EN BIT(20)
  37149. +
  37150. +#define AR7240_REG_TAG_PRIORITY 0x70
  37151. +
  37152. +#define AR7240_REG_SERVICE_TAG 0x74
  37153. +#define AR7240_SERVICE_TAG_M BITM(16)
  37154. +
  37155. +#define AR7240_REG_CPU_PORT 0x78
  37156. +#define AR7240_MIRROR_PORT_S 4
  37157. +#define AR7240_CPU_PORT_EN BIT(8)
  37158. +
  37159. +#define AR7240_REG_MIB_FUNCTION0 0x80
  37160. +#define AR7240_MIB_TIMER_M BITM(16)
  37161. +#define AR7240_MIB_AT_HALF_EN BIT(16)
  37162. +#define AR7240_MIB_BUSY BIT(17)
  37163. +#define AR7240_MIB_FUNC_S 24
  37164. +#define AR7240_MIB_FUNC_M BITM(3)
  37165. +#define AR7240_MIB_FUNC_NO_OP 0x0
  37166. +#define AR7240_MIB_FUNC_FLUSH 0x1
  37167. +#define AR7240_MIB_FUNC_CAPTURE 0x3
  37168. +
  37169. +#define AR7240_REG_MDIO_CTRL 0x98
  37170. +#define AR7240_MDIO_CTRL_DATA_M BITM(16)
  37171. +#define AR7240_MDIO_CTRL_REG_ADDR_S 16
  37172. +#define AR7240_MDIO_CTRL_PHY_ADDR_S 21
  37173. +#define AR7240_MDIO_CTRL_CMD_WRITE 0
  37174. +#define AR7240_MDIO_CTRL_CMD_READ BIT(27)
  37175. +#define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
  37176. +#define AR7240_MDIO_CTRL_BUSY BIT(31)
  37177. +
  37178. +#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
  37179. +
  37180. +#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
  37181. +#define AR7240_PORT_STATUS_SPEED_S 0
  37182. +#define AR7240_PORT_STATUS_SPEED_M BITM(2)
  37183. +#define AR7240_PORT_STATUS_SPEED_10 0
  37184. +#define AR7240_PORT_STATUS_SPEED_100 1
  37185. +#define AR7240_PORT_STATUS_SPEED_1000 2
  37186. +#define AR7240_PORT_STATUS_TXMAC BIT(2)
  37187. +#define AR7240_PORT_STATUS_RXMAC BIT(3)
  37188. +#define AR7240_PORT_STATUS_TXFLOW BIT(4)
  37189. +#define AR7240_PORT_STATUS_RXFLOW BIT(5)
  37190. +#define AR7240_PORT_STATUS_DUPLEX BIT(6)
  37191. +#define AR7240_PORT_STATUS_LINK_UP BIT(8)
  37192. +#define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
  37193. +#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
  37194. +
  37195. +#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
  37196. +#define AR7240_PORT_CTRL_STATE_M BITM(3)
  37197. +#define AR7240_PORT_CTRL_STATE_DISABLED 0
  37198. +#define AR7240_PORT_CTRL_STATE_BLOCK 1
  37199. +#define AR7240_PORT_CTRL_STATE_LISTEN 2
  37200. +#define AR7240_PORT_CTRL_STATE_LEARN 3
  37201. +#define AR7240_PORT_CTRL_STATE_FORWARD 4
  37202. +#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
  37203. +#define AR7240_PORT_CTRL_VLAN_MODE_S 8
  37204. +#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
  37205. +#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
  37206. +#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
  37207. +#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
  37208. +#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
  37209. +#define AR7240_PORT_CTRL_HEADER BIT(11)
  37210. +#define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
  37211. +#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
  37212. +#define AR7240_PORT_CTRL_LEARN BIT(14)
  37213. +#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
  37214. +#define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
  37215. +#define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
  37216. +
  37217. +#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
  37218. +
  37219. +#define AR7240_PORT_VLAN_DEFAULT_ID_S 0
  37220. +#define AR7240_PORT_VLAN_DEST_PORTS_S 16
  37221. +#define AR7240_PORT_VLAN_MODE_S 30
  37222. +#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
  37223. +#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
  37224. +#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
  37225. +#define AR7240_PORT_VLAN_MODE_SECURE 3
  37226. +
  37227. +
  37228. +#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
  37229. +
  37230. +#define AR7240_STATS_RXBROAD 0x00
  37231. +#define AR7240_STATS_RXPAUSE 0x04
  37232. +#define AR7240_STATS_RXMULTI 0x08
  37233. +#define AR7240_STATS_RXFCSERR 0x0c
  37234. +#define AR7240_STATS_RXALIGNERR 0x10
  37235. +#define AR7240_STATS_RXRUNT 0x14
  37236. +#define AR7240_STATS_RXFRAGMENT 0x18
  37237. +#define AR7240_STATS_RX64BYTE 0x1c
  37238. +#define AR7240_STATS_RX128BYTE 0x20
  37239. +#define AR7240_STATS_RX256BYTE 0x24
  37240. +#define AR7240_STATS_RX512BYTE 0x28
  37241. +#define AR7240_STATS_RX1024BYTE 0x2c
  37242. +#define AR7240_STATS_RX1518BYTE 0x30
  37243. +#define AR7240_STATS_RXMAXBYTE 0x34
  37244. +#define AR7240_STATS_RXTOOLONG 0x38
  37245. +#define AR7240_STATS_RXGOODBYTE 0x3c
  37246. +#define AR7240_STATS_RXBADBYTE 0x44
  37247. +#define AR7240_STATS_RXOVERFLOW 0x4c
  37248. +#define AR7240_STATS_FILTERED 0x50
  37249. +#define AR7240_STATS_TXBROAD 0x54
  37250. +#define AR7240_STATS_TXPAUSE 0x58
  37251. +#define AR7240_STATS_TXMULTI 0x5c
  37252. +#define AR7240_STATS_TXUNDERRUN 0x60
  37253. +#define AR7240_STATS_TX64BYTE 0x64
  37254. +#define AR7240_STATS_TX128BYTE 0x68
  37255. +#define AR7240_STATS_TX256BYTE 0x6c
  37256. +#define AR7240_STATS_TX512BYTE 0x70
  37257. +#define AR7240_STATS_TX1024BYTE 0x74
  37258. +#define AR7240_STATS_TX1518BYTE 0x78
  37259. +#define AR7240_STATS_TXMAXBYTE 0x7c
  37260. +#define AR7240_STATS_TXOVERSIZE 0x80
  37261. +#define AR7240_STATS_TXBYTE 0x84
  37262. +#define AR7240_STATS_TXCOLLISION 0x8c
  37263. +#define AR7240_STATS_TXABORTCOL 0x90
  37264. +#define AR7240_STATS_TXMULTICOL 0x94
  37265. +#define AR7240_STATS_TXSINGLECOL 0x98
  37266. +#define AR7240_STATS_TXEXCDEFER 0x9c
  37267. +#define AR7240_STATS_TXDEFER 0xa0
  37268. +#define AR7240_STATS_TXLATECOL 0xa4
  37269. +
  37270. +#define AR7240_PORT_CPU 0
  37271. +#define AR7240_NUM_PORTS 6
  37272. +#define AR7240_NUM_PHYS 5
  37273. +
  37274. +#define AR7240_PHY_ID1 0x004d
  37275. +#define AR7240_PHY_ID2 0xd041
  37276. +
  37277. +#define AR934X_PHY_ID1 0x004d
  37278. +#define AR934X_PHY_ID2 0xd042
  37279. +
  37280. +#define AR7240_MAX_VLANS 16
  37281. +
  37282. +#define AR934X_REG_OPER_MODE0 0x04
  37283. +#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
  37284. +#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
  37285. +
  37286. +#define AR934X_REG_OPER_MODE1 0x08
  37287. +#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
  37288. +
  37289. +#define AR934X_REG_FLOOD_MASK 0x2c
  37290. +#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
  37291. +#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
  37292. +
  37293. +#define AR934X_REG_QM_CTRL 0x3c
  37294. +#define AR934X_QM_CTRL_ARP_EN BIT(15)
  37295. +
  37296. +#define AR934X_REG_AT_CTRL 0x5c
  37297. +#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
  37298. +#define AR934X_AT_CTRL_AGE_EN BIT(17)
  37299. +#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
  37300. +
  37301. +#define AR934X_MIB_ENABLE BIT(30)
  37302. +
  37303. +#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
  37304. +
  37305. +#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
  37306. +#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
  37307. +#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
  37308. +#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
  37309. +#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
  37310. +#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
  37311. +#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
  37312. +#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
  37313. +#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
  37314. +
  37315. +#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
  37316. +#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
  37317. +#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
  37318. +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
  37319. +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
  37320. +#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
  37321. +#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
  37322. +
  37323. +#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
  37324. +
  37325. +struct ar7240sw_port_stat {
  37326. + unsigned long rx_broadcast;
  37327. + unsigned long rx_pause;
  37328. + unsigned long rx_multicast;
  37329. + unsigned long rx_fcs_error;
  37330. + unsigned long rx_align_error;
  37331. + unsigned long rx_runt;
  37332. + unsigned long rx_fragments;
  37333. + unsigned long rx_64byte;
  37334. + unsigned long rx_128byte;
  37335. + unsigned long rx_256byte;
  37336. + unsigned long rx_512byte;
  37337. + unsigned long rx_1024byte;
  37338. + unsigned long rx_1518byte;
  37339. + unsigned long rx_maxbyte;
  37340. + unsigned long rx_toolong;
  37341. + unsigned long rx_good_byte;
  37342. + unsigned long rx_bad_byte;
  37343. + unsigned long rx_overflow;
  37344. + unsigned long filtered;
  37345. +
  37346. + unsigned long tx_broadcast;
  37347. + unsigned long tx_pause;
  37348. + unsigned long tx_multicast;
  37349. + unsigned long tx_underrun;
  37350. + unsigned long tx_64byte;
  37351. + unsigned long tx_128byte;
  37352. + unsigned long tx_256byte;
  37353. + unsigned long tx_512byte;
  37354. + unsigned long tx_1024byte;
  37355. + unsigned long tx_1518byte;
  37356. + unsigned long tx_maxbyte;
  37357. + unsigned long tx_oversize;
  37358. + unsigned long tx_byte;
  37359. + unsigned long tx_collision;
  37360. + unsigned long tx_abortcol;
  37361. + unsigned long tx_multicol;
  37362. + unsigned long tx_singlecol;
  37363. + unsigned long tx_excdefer;
  37364. + unsigned long tx_defer;
  37365. + unsigned long tx_xlatecol;
  37366. +};
  37367. +
  37368. +struct ar7240sw {
  37369. + struct mii_bus *mii_bus;
  37370. + struct ag71xx_switch_platform_data *swdata;
  37371. + struct switch_dev swdev;
  37372. + int num_ports;
  37373. + u8 ver;
  37374. + bool vlan;
  37375. + u16 vlan_id[AR7240_MAX_VLANS];
  37376. + u8 vlan_table[AR7240_MAX_VLANS];
  37377. + u8 vlan_tagged;
  37378. + u16 pvid[AR7240_NUM_PORTS];
  37379. + char buf[80];
  37380. +
  37381. + rwlock_t stats_lock;
  37382. + struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
  37383. +};
  37384. +
  37385. +struct ar7240sw_hw_stat {
  37386. + char string[ETH_GSTRING_LEN];
  37387. + int sizeof_stat;
  37388. + int reg;
  37389. +};
  37390. +
  37391. +static DEFINE_MUTEX(reg_mutex);
  37392. +
  37393. +static inline int sw_is_ar7240(struct ar7240sw *as)
  37394. +{
  37395. + return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
  37396. +}
  37397. +
  37398. +static inline int sw_is_ar934x(struct ar7240sw *as)
  37399. +{
  37400. + return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
  37401. +}
  37402. +
  37403. +static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
  37404. +{
  37405. + return BIT(port);
  37406. +}
  37407. +
  37408. +static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
  37409. +{
  37410. + return BIT(as->swdev.ports) - 1;
  37411. +}
  37412. +
  37413. +static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
  37414. +{
  37415. + return ar7240sw_port_mask_all(as) & ~BIT(port);
  37416. +}
  37417. +
  37418. +static inline u16 mk_phy_addr(u32 reg)
  37419. +{
  37420. + return 0x17 & ((reg >> 4) | 0x10);
  37421. +}
  37422. +
  37423. +static inline u16 mk_phy_reg(u32 reg)
  37424. +{
  37425. + return (reg << 1) & 0x1e;
  37426. +}
  37427. +
  37428. +static inline u16 mk_high_addr(u32 reg)
  37429. +{
  37430. + return (reg >> 7) & 0x1ff;
  37431. +}
  37432. +
  37433. +static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
  37434. +{
  37435. + unsigned long flags;
  37436. + u16 phy_addr;
  37437. + u16 phy_reg;
  37438. + u32 hi, lo;
  37439. +
  37440. + reg = (reg & 0xfffffffc) >> 2;
  37441. + phy_addr = mk_phy_addr(reg);
  37442. + phy_reg = mk_phy_reg(reg);
  37443. +
  37444. + local_irq_save(flags);
  37445. + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
  37446. + lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
  37447. + hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
  37448. + local_irq_restore(flags);
  37449. +
  37450. + return (hi << 16) | lo;
  37451. +}
  37452. +
  37453. +static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
  37454. +{
  37455. + unsigned long flags;
  37456. + u16 phy_addr;
  37457. + u16 phy_reg;
  37458. +
  37459. + reg = (reg & 0xfffffffc) >> 2;
  37460. + phy_addr = mk_phy_addr(reg);
  37461. + phy_reg = mk_phy_reg(reg);
  37462. +
  37463. + local_irq_save(flags);
  37464. + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
  37465. + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
  37466. + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
  37467. + local_irq_restore(flags);
  37468. +}
  37469. +
  37470. +static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
  37471. +{
  37472. + u32 ret;
  37473. +
  37474. + mutex_lock(&reg_mutex);
  37475. + ret = __ar7240sw_reg_read(mii, reg_addr);
  37476. + mutex_unlock(&reg_mutex);
  37477. +
  37478. + return ret;
  37479. +}
  37480. +
  37481. +static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
  37482. +{
  37483. + mutex_lock(&reg_mutex);
  37484. + __ar7240sw_reg_write(mii, reg_addr, reg_val);
  37485. + mutex_unlock(&reg_mutex);
  37486. +}
  37487. +
  37488. +static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
  37489. +{
  37490. + u32 t;
  37491. +
  37492. + mutex_lock(&reg_mutex);
  37493. + t = __ar7240sw_reg_read(mii, reg);
  37494. + t &= ~mask;
  37495. + t |= val;
  37496. + __ar7240sw_reg_write(mii, reg, t);
  37497. + mutex_unlock(&reg_mutex);
  37498. +
  37499. + return t;
  37500. +}
  37501. +
  37502. +static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
  37503. +{
  37504. + u32 t;
  37505. +
  37506. + mutex_lock(&reg_mutex);
  37507. + t = __ar7240sw_reg_read(mii, reg);
  37508. + t |= val;
  37509. + __ar7240sw_reg_write(mii, reg, t);
  37510. + mutex_unlock(&reg_mutex);
  37511. +}
  37512. +
  37513. +static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
  37514. + unsigned timeout)
  37515. +{
  37516. + int i;
  37517. +
  37518. + for (i = 0; i < timeout; i++) {
  37519. + u32 t;
  37520. +
  37521. + t = __ar7240sw_reg_read(mii, reg);
  37522. + if ((t & mask) == val)
  37523. + return 0;
  37524. +
  37525. + usleep_range(1000, 2000);
  37526. + }
  37527. +
  37528. + return -ETIMEDOUT;
  37529. +}
  37530. +
  37531. +static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
  37532. + unsigned timeout)
  37533. +{
  37534. + int ret;
  37535. +
  37536. + mutex_lock(&reg_mutex);
  37537. + ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
  37538. + mutex_unlock(&reg_mutex);
  37539. + return ret;
  37540. +}
  37541. +
  37542. +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
  37543. + unsigned reg_addr)
  37544. +{
  37545. + u32 t, val = 0xffff;
  37546. + int err;
  37547. +
  37548. + if (phy_addr >= AR7240_NUM_PHYS)
  37549. + return 0xffff;
  37550. +
  37551. + mutex_lock(&reg_mutex);
  37552. + t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
  37553. + (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
  37554. + AR7240_MDIO_CTRL_MASTER_EN |
  37555. + AR7240_MDIO_CTRL_BUSY |
  37556. + AR7240_MDIO_CTRL_CMD_READ;
  37557. +
  37558. + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
  37559. + err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
  37560. + AR7240_MDIO_CTRL_BUSY, 0, 5);
  37561. + if (!err)
  37562. + val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
  37563. + mutex_unlock(&reg_mutex);
  37564. +
  37565. + return val & AR7240_MDIO_CTRL_DATA_M;
  37566. +}
  37567. +
  37568. +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
  37569. + unsigned reg_addr, u16 reg_val)
  37570. +{
  37571. + u32 t;
  37572. + int ret;
  37573. +
  37574. + if (phy_addr >= AR7240_NUM_PHYS)
  37575. + return -EINVAL;
  37576. +
  37577. + mutex_lock(&reg_mutex);
  37578. + t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
  37579. + (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
  37580. + AR7240_MDIO_CTRL_MASTER_EN |
  37581. + AR7240_MDIO_CTRL_BUSY |
  37582. + AR7240_MDIO_CTRL_CMD_WRITE |
  37583. + reg_val;
  37584. +
  37585. + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
  37586. + ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
  37587. + AR7240_MDIO_CTRL_BUSY, 0, 5);
  37588. + mutex_unlock(&reg_mutex);
  37589. +
  37590. + return ret;
  37591. +}
  37592. +
  37593. +static int ar7240sw_capture_stats(struct ar7240sw *as)
  37594. +{
  37595. + struct mii_bus *mii = as->mii_bus;
  37596. + int port;
  37597. + int ret;
  37598. +
  37599. + write_lock(&as->stats_lock);
  37600. +
  37601. + /* Capture the hardware statistics for all ports */
  37602. + ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
  37603. + (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
  37604. + (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
  37605. +
  37606. + /* Wait for the capturing to complete. */
  37607. + ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
  37608. + AR7240_MIB_BUSY, 0, 10);
  37609. +
  37610. + if (ret)
  37611. + goto unlock;
  37612. +
  37613. + for (port = 0; port < AR7240_NUM_PORTS; port++) {
  37614. + unsigned int base;
  37615. + struct ar7240sw_port_stat *stats;
  37616. +
  37617. + base = AR7240_REG_STATS_BASE(port);
  37618. + stats = &as->port_stats[port];
  37619. +
  37620. +#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
  37621. +
  37622. + stats->rx_good_byte += READ_STAT(RXGOODBYTE);
  37623. + stats->tx_byte += READ_STAT(TXBYTE);
  37624. +
  37625. +#undef READ_STAT
  37626. + }
  37627. +
  37628. + ret = 0;
  37629. +
  37630. +unlock:
  37631. + write_unlock(&as->stats_lock);
  37632. + return ret;
  37633. +}
  37634. +
  37635. +static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
  37636. +{
  37637. + ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
  37638. + AR7240_PORT_CTRL_STATE_DISABLED);
  37639. +}
  37640. +
  37641. +static void ar7240sw_setup(struct ar7240sw *as)
  37642. +{
  37643. + struct mii_bus *mii = as->mii_bus;
  37644. +
  37645. + /* Enable CPU port, and disable mirror port */
  37646. + ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
  37647. + AR7240_CPU_PORT_EN |
  37648. + (15 << AR7240_MIRROR_PORT_S));
  37649. +
  37650. + /* Setup TAG priority mapping */
  37651. + ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
  37652. +
  37653. + if (sw_is_ar934x(as)) {
  37654. + /* Enable aging, MAC replacing */
  37655. + ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
  37656. + 0x2b /* 5 min age time */ |
  37657. + AR934X_AT_CTRL_AGE_EN |
  37658. + AR934X_AT_CTRL_LEARN_CHANGE);
  37659. + /* Enable ARP frame acknowledge */
  37660. + ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
  37661. + AR934X_QM_CTRL_ARP_EN);
  37662. + /* Enable Broadcast/Multicast frames transmitted to the CPU */
  37663. + ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
  37664. + AR934X_FLOOD_MASK_BC_DP(0) |
  37665. + AR934X_FLOOD_MASK_MC_DP(0));
  37666. +
  37667. + /* setup MTU */
  37668. + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
  37669. + AR9340_GLOBAL_CTRL_MTU_M,
  37670. + AR9340_GLOBAL_CTRL_MTU_M);
  37671. +
  37672. + /* Enable MIB counters */
  37673. + ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
  37674. + AR934X_MIB_ENABLE);
  37675. +
  37676. + } else {
  37677. + /* Enable ARP frame acknowledge, aging, MAC replacing */
  37678. + ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
  37679. + AR7240_AT_CTRL_RESERVED |
  37680. + 0x2b /* 5 min age time */ |
  37681. + AR7240_AT_CTRL_AGE_EN |
  37682. + AR7240_AT_CTRL_ARP_EN |
  37683. + AR7240_AT_CTRL_LEARN_CHANGE);
  37684. + /* Enable Broadcast frames transmitted to the CPU */
  37685. + ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
  37686. + AR7240_FLOOD_MASK_BROAD_TO_CPU);
  37687. +
  37688. + /* setup MTU */
  37689. + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
  37690. + AR7240_GLOBAL_CTRL_MTU_M,
  37691. + AR7240_GLOBAL_CTRL_MTU_M);
  37692. + }
  37693. +
  37694. + /* setup Service TAG */
  37695. + ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
  37696. +}
  37697. +
  37698. +/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
  37699. +static int
  37700. +ar7240sw_phy_poll_reset(struct mii_bus *bus)
  37701. +{
  37702. + const unsigned int sleep_msecs = 20;
  37703. + int ret, elapsed, i;
  37704. +
  37705. + for (elapsed = sleep_msecs; elapsed <= 600;
  37706. + elapsed += sleep_msecs) {
  37707. + msleep(sleep_msecs);
  37708. + for (i = 0; i < AR7240_NUM_PHYS; i++) {
  37709. + ret = ar7240sw_phy_read(bus, i, MII_BMCR);
  37710. + if (ret < 0)
  37711. + return ret;
  37712. + if (ret & BMCR_RESET)
  37713. + break;
  37714. + if (i == AR7240_NUM_PHYS - 1) {
  37715. + usleep_range(1000, 2000);
  37716. + return 0;
  37717. + }
  37718. + }
  37719. + }
  37720. + return -ETIMEDOUT;
  37721. +}
  37722. +
  37723. +static int ar7240sw_reset(struct ar7240sw *as)
  37724. +{
  37725. + struct mii_bus *mii = as->mii_bus;
  37726. + int ret;
  37727. + int i;
  37728. +
  37729. + /* Set all ports to disabled state. */
  37730. + for (i = 0; i < AR7240_NUM_PORTS; i++)
  37731. + ar7240sw_disable_port(as, i);
  37732. +
  37733. + /* Wait for transmit queues to drain. */
  37734. + usleep_range(2000, 3000);
  37735. +
  37736. + /* Reset the switch. */
  37737. + ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
  37738. + AR7240_MASK_CTRL_SOFT_RESET);
  37739. +
  37740. + ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
  37741. + AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
  37742. +
  37743. + /* setup PHYs */
  37744. + for (i = 0; i < AR7240_NUM_PHYS; i++) {
  37745. + ar7240sw_phy_write(mii, i, MII_ADVERTISE,
  37746. + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
  37747. + ADVERTISE_PAUSE_ASYM);
  37748. + ar7240sw_phy_write(mii, i, MII_BMCR,
  37749. + BMCR_RESET | BMCR_ANENABLE);
  37750. + }
  37751. + ret = ar7240sw_phy_poll_reset(mii);
  37752. + if (ret)
  37753. + return ret;
  37754. +
  37755. + ar7240sw_setup(as);
  37756. + return ret;
  37757. +}
  37758. +
  37759. +static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
  37760. +{
  37761. + struct mii_bus *mii = as->mii_bus;
  37762. + u32 ctrl;
  37763. + u32 vid, mode;
  37764. +
  37765. + ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
  37766. + AR7240_PORT_CTRL_SINGLE_VLAN;
  37767. +
  37768. + if (port == AR7240_PORT_CPU) {
  37769. + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
  37770. + AR7240_PORT_STATUS_SPEED_1000 |
  37771. + AR7240_PORT_STATUS_TXFLOW |
  37772. + AR7240_PORT_STATUS_RXFLOW |
  37773. + AR7240_PORT_STATUS_TXMAC |
  37774. + AR7240_PORT_STATUS_RXMAC |
  37775. + AR7240_PORT_STATUS_DUPLEX);
  37776. + } else {
  37777. + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
  37778. + AR7240_PORT_STATUS_LINK_AUTO);
  37779. + }
  37780. +
  37781. + /* Set the default VID for this port */
  37782. + if (as->vlan) {
  37783. + vid = as->vlan_id[as->pvid[port]];
  37784. + mode = AR7240_PORT_VLAN_MODE_SECURE;
  37785. + } else {
  37786. + vid = port;
  37787. + mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
  37788. + }
  37789. +
  37790. + if (as->vlan) {
  37791. + if (as->vlan_tagged & BIT(port))
  37792. + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
  37793. + AR7240_PORT_CTRL_VLAN_MODE_S;
  37794. + else
  37795. + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
  37796. + AR7240_PORT_CTRL_VLAN_MODE_S;
  37797. + } else {
  37798. + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
  37799. + AR7240_PORT_CTRL_VLAN_MODE_S;
  37800. + }
  37801. +
  37802. + if (!portmask) {
  37803. + if (port == AR7240_PORT_CPU)
  37804. + portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
  37805. + else
  37806. + portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
  37807. + }
  37808. +
  37809. + /* allow the port to talk to all other ports, but exclude its
  37810. + * own ID to prevent frames from being reflected back to the
  37811. + * port that they came from */
  37812. + portmask &= ar7240sw_port_mask_but(as, port);
  37813. +
  37814. + ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
  37815. + if (sw_is_ar934x(as)) {
  37816. + u32 vlan1, vlan2;
  37817. +
  37818. + vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
  37819. + vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
  37820. + (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
  37821. + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
  37822. + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
  37823. + } else {
  37824. + u32 vlan;
  37825. +
  37826. + vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
  37827. + (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
  37828. +
  37829. + ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
  37830. + }
  37831. +}
  37832. +
  37833. +static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
  37834. +{
  37835. + struct mii_bus *mii = as->mii_bus;
  37836. + u32 t;
  37837. +
  37838. + t = (addr[4] << 8) | addr[5];
  37839. + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
  37840. +
  37841. + t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
  37842. + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
  37843. +
  37844. + return 0;
  37845. +}
  37846. +
  37847. +static int
  37848. +ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
  37849. + struct switch_val *val)
  37850. +{
  37851. + struct ar7240sw *as = sw_to_ar7240(dev);
  37852. + as->vlan_id[val->port_vlan] = val->value.i;
  37853. + return 0;
  37854. +}
  37855. +
  37856. +static int
  37857. +ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
  37858. + struct switch_val *val)
  37859. +{
  37860. + struct ar7240sw *as = sw_to_ar7240(dev);
  37861. + val->value.i = as->vlan_id[val->port_vlan];
  37862. + return 0;
  37863. +}
  37864. +
  37865. +static int
  37866. +ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
  37867. +{
  37868. + struct ar7240sw *as = sw_to_ar7240(dev);
  37869. +
  37870. + /* make sure no invalid PVIDs get set */
  37871. +
  37872. + if (vlan >= dev->vlans)
  37873. + return -EINVAL;
  37874. +
  37875. + as->pvid[port] = vlan;
  37876. + return 0;
  37877. +}
  37878. +
  37879. +static int
  37880. +ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
  37881. +{
  37882. + struct ar7240sw *as = sw_to_ar7240(dev);
  37883. + *vlan = as->pvid[port];
  37884. + return 0;
  37885. +}
  37886. +
  37887. +static int
  37888. +ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
  37889. +{
  37890. + struct ar7240sw *as = sw_to_ar7240(dev);
  37891. + u8 ports = as->vlan_table[val->port_vlan];
  37892. + int i;
  37893. +
  37894. + val->len = 0;
  37895. + for (i = 0; i < as->swdev.ports; i++) {
  37896. + struct switch_port *p;
  37897. +
  37898. + if (!(ports & (1 << i)))
  37899. + continue;
  37900. +
  37901. + p = &val->value.ports[val->len++];
  37902. + p->id = i;
  37903. + if (as->vlan_tagged & (1 << i))
  37904. + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
  37905. + else
  37906. + p->flags = 0;
  37907. + }
  37908. + return 0;
  37909. +}
  37910. +
  37911. +static int
  37912. +ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
  37913. +{
  37914. + struct ar7240sw *as = sw_to_ar7240(dev);
  37915. + u8 *vt = &as->vlan_table[val->port_vlan];
  37916. + int i, j;
  37917. +
  37918. + *vt = 0;
  37919. + for (i = 0; i < val->len; i++) {
  37920. + struct switch_port *p = &val->value.ports[i];
  37921. +
  37922. + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
  37923. + as->vlan_tagged |= (1 << p->id);
  37924. + else {
  37925. + as->vlan_tagged &= ~(1 << p->id);
  37926. + as->pvid[p->id] = val->port_vlan;
  37927. +
  37928. + /* make sure that an untagged port does not
  37929. + * appear in other vlans */
  37930. + for (j = 0; j < AR7240_MAX_VLANS; j++) {
  37931. + if (j == val->port_vlan)
  37932. + continue;
  37933. + as->vlan_table[j] &= ~(1 << p->id);
  37934. + }
  37935. + }
  37936. +
  37937. + *vt |= 1 << p->id;
  37938. + }
  37939. + return 0;
  37940. +}
  37941. +
  37942. +static int
  37943. +ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  37944. + struct switch_val *val)
  37945. +{
  37946. + struct ar7240sw *as = sw_to_ar7240(dev);
  37947. + as->vlan = !!val->value.i;
  37948. + return 0;
  37949. +}
  37950. +
  37951. +static int
  37952. +ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  37953. + struct switch_val *val)
  37954. +{
  37955. + struct ar7240sw *as = sw_to_ar7240(dev);
  37956. + val->value.i = as->vlan;
  37957. + return 0;
  37958. +}
  37959. +
  37960. +static void
  37961. +ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
  37962. +{
  37963. + struct mii_bus *mii = as->mii_bus;
  37964. +
  37965. + if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
  37966. + return;
  37967. +
  37968. + if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
  37969. + val &= AR7240_VTUDATA_MEMBER;
  37970. + val |= AR7240_VTUDATA_VALID;
  37971. + ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
  37972. + }
  37973. + op |= AR7240_VTU_ACTIVE;
  37974. + ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
  37975. +}
  37976. +
  37977. +static int
  37978. +ar7240_hw_apply(struct switch_dev *dev)
  37979. +{
  37980. + struct ar7240sw *as = sw_to_ar7240(dev);
  37981. + u8 portmask[AR7240_NUM_PORTS];
  37982. + int i, j;
  37983. +
  37984. + /* flush all vlan translation unit entries */
  37985. + ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
  37986. +
  37987. + memset(portmask, 0, sizeof(portmask));
  37988. + if (as->vlan) {
  37989. + /* calculate the port destination masks and load vlans
  37990. + * into the vlan translation unit */
  37991. + for (j = 0; j < AR7240_MAX_VLANS; j++) {
  37992. + u8 vp = as->vlan_table[j];
  37993. +
  37994. + if (!vp)
  37995. + continue;
  37996. +
  37997. + for (i = 0; i < as->swdev.ports; i++) {
  37998. + u8 mask = (1 << i);
  37999. + if (vp & mask)
  38000. + portmask[i] |= vp & ~mask;
  38001. + }
  38002. +
  38003. + ar7240_vtu_op(as,
  38004. + AR7240_VTU_OP_LOAD |
  38005. + (as->vlan_id[j] << AR7240_VTU_VID_S),
  38006. + as->vlan_table[j]);
  38007. + }
  38008. + } else {
  38009. + /* vlan disabled:
  38010. + * isolate all ports, but connect them to the cpu port */
  38011. + for (i = 0; i < as->swdev.ports; i++) {
  38012. + if (i == AR7240_PORT_CPU)
  38013. + continue;
  38014. +
  38015. + portmask[i] = 1 << AR7240_PORT_CPU;
  38016. + portmask[AR7240_PORT_CPU] |= (1 << i);
  38017. + }
  38018. + }
  38019. +
  38020. + /* update the port destination mask registers and tag settings */
  38021. + for (i = 0; i < as->swdev.ports; i++)
  38022. + ar7240sw_setup_port(as, i, portmask[i]);
  38023. +
  38024. + return 0;
  38025. +}
  38026. +
  38027. +static int
  38028. +ar7240_reset_switch(struct switch_dev *dev)
  38029. +{
  38030. + struct ar7240sw *as = sw_to_ar7240(dev);
  38031. + ar7240sw_reset(as);
  38032. + return 0;
  38033. +}
  38034. +
  38035. +static int
  38036. +ar7240_get_port_link(struct switch_dev *dev, int port,
  38037. + struct switch_port_link *link)
  38038. +{
  38039. + struct ar7240sw *as = sw_to_ar7240(dev);
  38040. + struct mii_bus *mii = as->mii_bus;
  38041. + u32 status;
  38042. +
  38043. + if (port > AR7240_NUM_PORTS)
  38044. + return -EINVAL;
  38045. +
  38046. + status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
  38047. + link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
  38048. + if (link->aneg) {
  38049. + link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
  38050. + if (!link->link)
  38051. + return 0;
  38052. + } else {
  38053. + link->link = true;
  38054. + }
  38055. +
  38056. + link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
  38057. + link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
  38058. + link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
  38059. + switch (status & AR7240_PORT_STATUS_SPEED_M) {
  38060. + case AR7240_PORT_STATUS_SPEED_10:
  38061. + link->speed = SWITCH_PORT_SPEED_10;
  38062. + break;
  38063. + case AR7240_PORT_STATUS_SPEED_100:
  38064. + link->speed = SWITCH_PORT_SPEED_100;
  38065. + break;
  38066. + case AR7240_PORT_STATUS_SPEED_1000:
  38067. + link->speed = SWITCH_PORT_SPEED_1000;
  38068. + break;
  38069. + }
  38070. +
  38071. + return 0;
  38072. +}
  38073. +
  38074. +static int
  38075. +ar7240_get_port_stats(struct switch_dev *dev, int port,
  38076. + struct switch_port_stats *stats)
  38077. +{
  38078. + struct ar7240sw *as = sw_to_ar7240(dev);
  38079. +
  38080. + if (port > AR7240_NUM_PORTS)
  38081. + return -EINVAL;
  38082. +
  38083. + ar7240sw_capture_stats(as);
  38084. +
  38085. + read_lock(&as->stats_lock);
  38086. + stats->rx_bytes = as->port_stats[port].rx_good_byte;
  38087. + stats->tx_bytes = as->port_stats[port].tx_byte;
  38088. + read_unlock(&as->stats_lock);
  38089. +
  38090. + return 0;
  38091. +}
  38092. +
  38093. +static struct switch_attr ar7240_globals[] = {
  38094. + {
  38095. + .type = SWITCH_TYPE_INT,
  38096. + .name = "enable_vlan",
  38097. + .description = "Enable VLAN mode",
  38098. + .set = ar7240_set_vlan,
  38099. + .get = ar7240_get_vlan,
  38100. + .max = 1
  38101. + },
  38102. +};
  38103. +
  38104. +static struct switch_attr ar7240_port[] = {
  38105. +};
  38106. +
  38107. +static struct switch_attr ar7240_vlan[] = {
  38108. + {
  38109. + .type = SWITCH_TYPE_INT,
  38110. + .name = "vid",
  38111. + .description = "VLAN ID",
  38112. + .set = ar7240_set_vid,
  38113. + .get = ar7240_get_vid,
  38114. + .max = 4094,
  38115. + },
  38116. +};
  38117. +
  38118. +static const struct switch_dev_ops ar7240_ops = {
  38119. + .attr_global = {
  38120. + .attr = ar7240_globals,
  38121. + .n_attr = ARRAY_SIZE(ar7240_globals),
  38122. + },
  38123. + .attr_port = {
  38124. + .attr = ar7240_port,
  38125. + .n_attr = ARRAY_SIZE(ar7240_port),
  38126. + },
  38127. + .attr_vlan = {
  38128. + .attr = ar7240_vlan,
  38129. + .n_attr = ARRAY_SIZE(ar7240_vlan),
  38130. + },
  38131. + .get_port_pvid = ar7240_get_pvid,
  38132. + .set_port_pvid = ar7240_set_pvid,
  38133. + .get_vlan_ports = ar7240_get_ports,
  38134. + .set_vlan_ports = ar7240_set_ports,
  38135. + .apply_config = ar7240_hw_apply,
  38136. + .reset_switch = ar7240_reset_switch,
  38137. + .get_port_link = ar7240_get_port_link,
  38138. + .get_port_stats = ar7240_get_port_stats,
  38139. +};
  38140. +
  38141. +static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
  38142. +{
  38143. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  38144. + struct mii_bus *mii = ag->mii_bus;
  38145. + struct ar7240sw *as;
  38146. + struct switch_dev *swdev;
  38147. + u32 ctrl;
  38148. + u16 phy_id1;
  38149. + u16 phy_id2;
  38150. + int i;
  38151. +
  38152. + phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
  38153. + phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
  38154. + if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
  38155. + (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
  38156. + pr_err("%s: unknown phy id '%04x:%04x'\n",
  38157. + dev_name(&mii->dev), phy_id1, phy_id2);
  38158. + return NULL;
  38159. + }
  38160. +
  38161. + as = kzalloc(sizeof(*as), GFP_KERNEL);
  38162. + if (!as)
  38163. + return NULL;
  38164. +
  38165. + as->mii_bus = mii;
  38166. + as->swdata = pdata->switch_data;
  38167. +
  38168. + swdev = &as->swdev;
  38169. +
  38170. + ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
  38171. + as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
  38172. + AR7240_MASK_CTRL_VERSION_M;
  38173. +
  38174. + if (sw_is_ar7240(as)) {
  38175. + swdev->name = "AR7240/AR9330 built-in switch";
  38176. + swdev->ports = AR7240_NUM_PORTS - 1;
  38177. + } else if (sw_is_ar934x(as)) {
  38178. + swdev->name = "AR934X built-in switch";
  38179. +
  38180. + if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
  38181. + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
  38182. + AR934X_OPER_MODE0_MAC_GMII_EN);
  38183. + } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
  38184. + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
  38185. + AR934X_OPER_MODE0_PHY_MII_EN);
  38186. + } else {
  38187. + pr_err("%s: invalid PHY interface mode\n",
  38188. + dev_name(&mii->dev));
  38189. + goto err_free;
  38190. + }
  38191. +
  38192. + if (as->swdata->phy4_mii_en) {
  38193. + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
  38194. + AR934X_REG_OPER_MODE1_PHY4_MII_EN);
  38195. + swdev->ports = AR7240_NUM_PORTS - 1;
  38196. + } else {
  38197. + swdev->ports = AR7240_NUM_PORTS;
  38198. + }
  38199. + } else {
  38200. + pr_err("%s: unsupported chip, ctrl=%08x\n",
  38201. + dev_name(&mii->dev), ctrl);
  38202. + goto err_free;
  38203. + }
  38204. +
  38205. + swdev->cpu_port = AR7240_PORT_CPU;
  38206. + swdev->vlans = AR7240_MAX_VLANS;
  38207. + swdev->ops = &ar7240_ops;
  38208. +
  38209. + if (register_switch(&as->swdev, ag->dev) < 0)
  38210. + goto err_free;
  38211. +
  38212. + pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name);
  38213. +
  38214. + /* initialize defaults */
  38215. + for (i = 0; i < AR7240_MAX_VLANS; i++)
  38216. + as->vlan_id[i] = i;
  38217. +
  38218. + as->vlan_table[0] = ar7240sw_port_mask_all(as);
  38219. +
  38220. + return as;
  38221. +
  38222. +err_free:
  38223. + kfree(as);
  38224. + return NULL;
  38225. +}
  38226. +
  38227. +static void link_function(struct work_struct *work) {
  38228. + struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
  38229. + struct ar7240sw *as = ag->phy_priv;
  38230. + unsigned long flags;
  38231. + u8 mask;
  38232. + int i;
  38233. + int status = 0;
  38234. +
  38235. + mask = ~as->swdata->phy_poll_mask;
  38236. + for (i = 0; i < AR7240_NUM_PHYS; i++) {
  38237. + int link;
  38238. +
  38239. + if (!(mask & BIT(i)))
  38240. + continue;
  38241. +
  38242. + link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
  38243. + if (link & BMSR_LSTATUS) {
  38244. + status = 1;
  38245. + break;
  38246. + }
  38247. + }
  38248. +
  38249. + spin_lock_irqsave(&ag->lock, flags);
  38250. + if (status != ag->link) {
  38251. + ag->link = status;
  38252. + ag71xx_link_adjust(ag);
  38253. + }
  38254. + spin_unlock_irqrestore(&ag->lock, flags);
  38255. +
  38256. + schedule_delayed_work(&ag->link_work, HZ / 2);
  38257. +}
  38258. +
  38259. +void ag71xx_ar7240_start(struct ag71xx *ag)
  38260. +{
  38261. + struct ar7240sw *as = ag->phy_priv;
  38262. +
  38263. + ar7240sw_reset(as);
  38264. +
  38265. + ag->speed = SPEED_1000;
  38266. + ag->duplex = 1;
  38267. +
  38268. + ar7240_set_addr(as, ag->dev->dev_addr);
  38269. + ar7240_hw_apply(&as->swdev);
  38270. +
  38271. + schedule_delayed_work(&ag->link_work, HZ / 10);
  38272. +}
  38273. +
  38274. +void ag71xx_ar7240_stop(struct ag71xx *ag)
  38275. +{
  38276. + cancel_delayed_work_sync(&ag->link_work);
  38277. +}
  38278. +
  38279. +int ag71xx_ar7240_init(struct ag71xx *ag)
  38280. +{
  38281. + struct ar7240sw *as;
  38282. +
  38283. + as = ar7240_probe(ag);
  38284. + if (!as)
  38285. + return -ENODEV;
  38286. +
  38287. + ag->phy_priv = as;
  38288. + ar7240sw_reset(as);
  38289. +
  38290. + rwlock_init(&as->stats_lock);
  38291. + INIT_DELAYED_WORK(&ag->link_work, link_function);
  38292. +
  38293. + return 0;
  38294. +}
  38295. +
  38296. +void ag71xx_ar7240_cleanup(struct ag71xx *ag)
  38297. +{
  38298. + struct ar7240sw *as = ag->phy_priv;
  38299. +
  38300. + if (!as)
  38301. + return;
  38302. +
  38303. + unregister_switch(&as->swdev);
  38304. + kfree(as);
  38305. + ag->phy_priv = NULL;
  38306. +}
  38307. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c
  38308. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100
  38309. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c 2017-08-06 20:02:16.000000000 +0200
  38310. @@ -0,0 +1,44 @@
  38311. +/*
  38312. + * Atheros AR71xx built-in ethernet mac driver
  38313. + * Special support for the Atheros ar8216 switch chip
  38314. + *
  38315. + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
  38316. + *
  38317. + * Based on Atheros' AG7100 driver
  38318. + *
  38319. + * This program is free software; you can redistribute it and/or modify it
  38320. + * under the terms of the GNU General Public License version 2 as published
  38321. + * by the Free Software Foundation.
  38322. + */
  38323. +
  38324. +#include "ag71xx.h"
  38325. +
  38326. +#define AR8216_PACKET_TYPE_MASK 0xf
  38327. +#define AR8216_PACKET_TYPE_NORMAL 0
  38328. +
  38329. +#define AR8216_HEADER_LEN 2
  38330. +
  38331. +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb)
  38332. +{
  38333. + skb_push(skb, AR8216_HEADER_LEN);
  38334. + skb->data[0] = 0x10;
  38335. + skb->data[1] = 0x80;
  38336. +}
  38337. +
  38338. +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
  38339. + int pktlen)
  38340. +{
  38341. + u8 type;
  38342. +
  38343. + type = skb->data[1] & AR8216_PACKET_TYPE_MASK;
  38344. + switch (type) {
  38345. + case AR8216_PACKET_TYPE_NORMAL:
  38346. + break;
  38347. +
  38348. + default:
  38349. + return -EINVAL;
  38350. + }
  38351. +
  38352. + skb_pull(skb, AR8216_HEADER_LEN);
  38353. + return 0;
  38354. +}
  38355. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c
  38356. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100
  38357. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c 2017-08-06 20:02:16.000000000 +0200
  38358. @@ -0,0 +1,285 @@
  38359. +/*
  38360. + * Atheros AR71xx built-in ethernet mac driver
  38361. + *
  38362. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  38363. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  38364. + *
  38365. + * Based on Atheros' AG7100 driver
  38366. + *
  38367. + * This program is free software; you can redistribute it and/or modify it
  38368. + * under the terms of the GNU General Public License version 2 as published
  38369. + * by the Free Software Foundation.
  38370. + */
  38371. +
  38372. +#include <linux/debugfs.h>
  38373. +
  38374. +#include "ag71xx.h"
  38375. +
  38376. +static struct dentry *ag71xx_debugfs_root;
  38377. +
  38378. +static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file)
  38379. +{
  38380. + file->private_data = inode->i_private;
  38381. + return 0;
  38382. +}
  38383. +
  38384. +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status)
  38385. +{
  38386. + if (status)
  38387. + ag->debug.int_stats.total++;
  38388. + if (status & AG71XX_INT_TX_PS)
  38389. + ag->debug.int_stats.tx_ps++;
  38390. + if (status & AG71XX_INT_TX_UR)
  38391. + ag->debug.int_stats.tx_ur++;
  38392. + if (status & AG71XX_INT_TX_BE)
  38393. + ag->debug.int_stats.tx_be++;
  38394. + if (status & AG71XX_INT_RX_PR)
  38395. + ag->debug.int_stats.rx_pr++;
  38396. + if (status & AG71XX_INT_RX_OF)
  38397. + ag->debug.int_stats.rx_of++;
  38398. + if (status & AG71XX_INT_RX_BE)
  38399. + ag->debug.int_stats.rx_be++;
  38400. +}
  38401. +
  38402. +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
  38403. + size_t count, loff_t *ppos)
  38404. +{
  38405. +#define PR_INT_STAT(_label, _field) \
  38406. + len += snprintf(buf + len, sizeof(buf) - len, \
  38407. + "%20s: %10lu\n", _label, ag->debug.int_stats._field);
  38408. +
  38409. + struct ag71xx *ag = file->private_data;
  38410. + char buf[256];
  38411. + unsigned int len = 0;
  38412. +
  38413. + PR_INT_STAT("TX Packet Sent", tx_ps);
  38414. + PR_INT_STAT("TX Underrun", tx_ur);
  38415. + PR_INT_STAT("TX Bus Error", tx_be);
  38416. + PR_INT_STAT("RX Packet Received", rx_pr);
  38417. + PR_INT_STAT("RX Overflow", rx_of);
  38418. + PR_INT_STAT("RX Bus Error", rx_be);
  38419. + len += snprintf(buf + len, sizeof(buf) - len, "\n");
  38420. + PR_INT_STAT("Total", total);
  38421. +
  38422. + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  38423. +#undef PR_INT_STAT
  38424. +}
  38425. +
  38426. +static const struct file_operations ag71xx_fops_int_stats = {
  38427. + .open = ag71xx_debugfs_generic_open,
  38428. + .read = read_file_int_stats,
  38429. + .owner = THIS_MODULE
  38430. +};
  38431. +
  38432. +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx)
  38433. +{
  38434. + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
  38435. +
  38436. + if (rx) {
  38437. + stats->rx_count++;
  38438. + stats->rx_packets += rx;
  38439. + if (rx <= AG71XX_NAPI_WEIGHT)
  38440. + stats->rx[rx]++;
  38441. + if (rx > stats->rx_packets_max)
  38442. + stats->rx_packets_max = rx;
  38443. + }
  38444. +
  38445. + if (tx) {
  38446. + stats->tx_count++;
  38447. + stats->tx_packets += tx;
  38448. + if (tx <= AG71XX_NAPI_WEIGHT)
  38449. + stats->tx[tx]++;
  38450. + if (tx > stats->tx_packets_max)
  38451. + stats->tx_packets_max = tx;
  38452. + }
  38453. +}
  38454. +
  38455. +static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf,
  38456. + size_t count, loff_t *ppos)
  38457. +{
  38458. + struct ag71xx *ag = file->private_data;
  38459. + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
  38460. + char *buf;
  38461. + unsigned int buflen;
  38462. + unsigned int len = 0;
  38463. + unsigned long rx_avg = 0;
  38464. + unsigned long tx_avg = 0;
  38465. + int ret;
  38466. + int i;
  38467. +
  38468. + buflen = 2048;
  38469. + buf = kmalloc(buflen, GFP_KERNEL);
  38470. + if (!buf)
  38471. + return -ENOMEM;
  38472. +
  38473. + if (stats->rx_count)
  38474. + rx_avg = stats->rx_packets / stats->rx_count;
  38475. +
  38476. + if (stats->tx_count)
  38477. + tx_avg = stats->tx_packets / stats->tx_count;
  38478. +
  38479. + len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n",
  38480. + "len", "rx", "tx");
  38481. +
  38482. + for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++)
  38483. + len += snprintf(buf + len, buflen - len,
  38484. + "%3d: %10lu %10lu\n",
  38485. + i, stats->rx[i], stats->tx[i]);
  38486. +
  38487. + len += snprintf(buf + len, buflen - len, "\n");
  38488. +
  38489. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  38490. + "sum", stats->rx_count, stats->tx_count);
  38491. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  38492. + "avg", rx_avg, tx_avg);
  38493. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  38494. + "max", stats->rx_packets_max, stats->tx_packets_max);
  38495. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  38496. + "pkt", stats->rx_packets, stats->tx_packets);
  38497. +
  38498. + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  38499. + kfree(buf);
  38500. +
  38501. + return ret;
  38502. +}
  38503. +
  38504. +static const struct file_operations ag71xx_fops_napi_stats = {
  38505. + .open = ag71xx_debugfs_generic_open,
  38506. + .read = read_file_napi_stats,
  38507. + .owner = THIS_MODULE
  38508. +};
  38509. +
  38510. +#define DESC_PRINT_LEN 64
  38511. +
  38512. +static ssize_t read_file_ring(struct file *file, char __user *user_buf,
  38513. + size_t count, loff_t *ppos,
  38514. + struct ag71xx *ag,
  38515. + struct ag71xx_ring *ring,
  38516. + unsigned desc_reg)
  38517. +{
  38518. + char *buf;
  38519. + unsigned int buflen;
  38520. + unsigned int len = 0;
  38521. + unsigned long flags;
  38522. + ssize_t ret;
  38523. + int curr;
  38524. + int dirty;
  38525. + u32 desc_hw;
  38526. + int i;
  38527. +
  38528. + buflen = (ring->size * DESC_PRINT_LEN);
  38529. + buf = kmalloc(buflen, GFP_KERNEL);
  38530. + if (!buf)
  38531. + return -ENOMEM;
  38532. +
  38533. + len += snprintf(buf + len, buflen - len,
  38534. + "Idx ... %-8s %-8s %-8s %-8s . %-10s\n",
  38535. + "desc", "next", "data", "ctrl", "timestamp");
  38536. +
  38537. + spin_lock_irqsave(&ag->lock, flags);
  38538. +
  38539. + curr = (ring->curr % ring->size);
  38540. + dirty = (ring->dirty % ring->size);
  38541. + desc_hw = ag71xx_rr(ag, desc_reg);
  38542. + for (i = 0; i < ring->size; i++) {
  38543. + struct ag71xx_buf *ab = &ring->buf[i];
  38544. + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
  38545. + u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size;
  38546. +
  38547. + len += snprintf(buf + len, buflen - len,
  38548. + "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n",
  38549. + i,
  38550. + (i == curr) ? 'C' : ' ',
  38551. + (i == dirty) ? 'D' : ' ',
  38552. + (desc_hw == desc_dma) ? 'H' : ' ',
  38553. + desc_dma,
  38554. + desc->next,
  38555. + desc->data,
  38556. + desc->ctrl,
  38557. + (desc->ctrl & DESC_EMPTY) ? 'E' : '*',
  38558. + ab->timestamp);
  38559. + }
  38560. +
  38561. + spin_unlock_irqrestore(&ag->lock, flags);
  38562. +
  38563. + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  38564. + kfree(buf);
  38565. +
  38566. + return ret;
  38567. +}
  38568. +
  38569. +static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf,
  38570. + size_t count, loff_t *ppos)
  38571. +{
  38572. + struct ag71xx *ag = file->private_data;
  38573. +
  38574. + return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring,
  38575. + AG71XX_REG_TX_DESC);
  38576. +}
  38577. +
  38578. +static const struct file_operations ag71xx_fops_tx_ring = {
  38579. + .open = ag71xx_debugfs_generic_open,
  38580. + .read = read_file_tx_ring,
  38581. + .owner = THIS_MODULE
  38582. +};
  38583. +
  38584. +static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf,
  38585. + size_t count, loff_t *ppos)
  38586. +{
  38587. + struct ag71xx *ag = file->private_data;
  38588. +
  38589. + return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring,
  38590. + AG71XX_REG_RX_DESC);
  38591. +}
  38592. +
  38593. +static const struct file_operations ag71xx_fops_rx_ring = {
  38594. + .open = ag71xx_debugfs_generic_open,
  38595. + .read = read_file_rx_ring,
  38596. + .owner = THIS_MODULE
  38597. +};
  38598. +
  38599. +void ag71xx_debugfs_exit(struct ag71xx *ag)
  38600. +{
  38601. + debugfs_remove_recursive(ag->debug.debugfs_dir);
  38602. +}
  38603. +
  38604. +int ag71xx_debugfs_init(struct ag71xx *ag)
  38605. +{
  38606. + struct device *dev = &ag->pdev->dev;
  38607. +
  38608. + ag->debug.debugfs_dir = debugfs_create_dir(dev_name(dev),
  38609. + ag71xx_debugfs_root);
  38610. + if (!ag->debug.debugfs_dir) {
  38611. + dev_err(dev, "unable to create debugfs directory\n");
  38612. + return -ENOENT;
  38613. + }
  38614. +
  38615. + debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir,
  38616. + ag, &ag71xx_fops_int_stats);
  38617. + debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir,
  38618. + ag, &ag71xx_fops_napi_stats);
  38619. + debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir,
  38620. + ag, &ag71xx_fops_tx_ring);
  38621. + debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir,
  38622. + ag, &ag71xx_fops_rx_ring);
  38623. +
  38624. + return 0;
  38625. +}
  38626. +
  38627. +int ag71xx_debugfs_root_init(void)
  38628. +{
  38629. + if (ag71xx_debugfs_root)
  38630. + return -EBUSY;
  38631. +
  38632. + ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
  38633. + if (!ag71xx_debugfs_root)
  38634. + return -ENOENT;
  38635. +
  38636. + return 0;
  38637. +}
  38638. +
  38639. +void ag71xx_debugfs_root_exit(void)
  38640. +{
  38641. + debugfs_remove(ag71xx_debugfs_root);
  38642. + ag71xx_debugfs_root = NULL;
  38643. +}
  38644. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c
  38645. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100
  38646. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c 2017-08-06 20:02:16.000000000 +0200
  38647. @@ -0,0 +1,130 @@
  38648. +/*
  38649. + * Atheros AR71xx built-in ethernet mac driver
  38650. + *
  38651. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  38652. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  38653. + *
  38654. + * Based on Atheros' AG7100 driver
  38655. + *
  38656. + * This program is free software; you can redistribute it and/or modify it
  38657. + * under the terms of the GNU General Public License version 2 as published
  38658. + * by the Free Software Foundation.
  38659. + */
  38660. +
  38661. +#include "ag71xx.h"
  38662. +
  38663. +static int ag71xx_ethtool_get_settings(struct net_device *dev,
  38664. + struct ethtool_cmd *cmd)
  38665. +{
  38666. + struct ag71xx *ag = netdev_priv(dev);
  38667. + struct phy_device *phydev = ag->phy_dev;
  38668. +
  38669. + if (!phydev)
  38670. + return -ENODEV;
  38671. +
  38672. + return phy_ethtool_gset(phydev, cmd);
  38673. +}
  38674. +
  38675. +static int ag71xx_ethtool_set_settings(struct net_device *dev,
  38676. + struct ethtool_cmd *cmd)
  38677. +{
  38678. + struct ag71xx *ag = netdev_priv(dev);
  38679. + struct phy_device *phydev = ag->phy_dev;
  38680. +
  38681. + if (!phydev)
  38682. + return -ENODEV;
  38683. +
  38684. + return phy_ethtool_sset(phydev, cmd);
  38685. +}
  38686. +
  38687. +static void ag71xx_ethtool_get_drvinfo(struct net_device *dev,
  38688. + struct ethtool_drvinfo *info)
  38689. +{
  38690. + struct ag71xx *ag = netdev_priv(dev);
  38691. +
  38692. + strcpy(info->driver, ag->pdev->dev.driver->name);
  38693. + strcpy(info->version, AG71XX_DRV_VERSION);
  38694. + strcpy(info->bus_info, dev_name(&ag->pdev->dev));
  38695. +}
  38696. +
  38697. +static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev)
  38698. +{
  38699. + struct ag71xx *ag = netdev_priv(dev);
  38700. +
  38701. + return ag->msg_enable;
  38702. +}
  38703. +
  38704. +static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level)
  38705. +{
  38706. + struct ag71xx *ag = netdev_priv(dev);
  38707. +
  38708. + ag->msg_enable = msg_level;
  38709. +}
  38710. +
  38711. +static void ag71xx_ethtool_get_ringparam(struct net_device *dev,
  38712. + struct ethtool_ringparam *er)
  38713. +{
  38714. + struct ag71xx *ag = netdev_priv(dev);
  38715. +
  38716. + er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX;
  38717. + er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX;
  38718. + er->rx_mini_max_pending = 0;
  38719. + er->rx_jumbo_max_pending = 0;
  38720. +
  38721. + er->tx_pending = ag->tx_ring.size;
  38722. + er->rx_pending = ag->rx_ring.size;
  38723. + er->rx_mini_pending = 0;
  38724. + er->rx_jumbo_pending = 0;
  38725. +
  38726. + if (ag->tx_ring.desc_split)
  38727. + er->tx_pending /= AG71XX_TX_RING_DS_PER_PKT;
  38728. +}
  38729. +
  38730. +static int ag71xx_ethtool_set_ringparam(struct net_device *dev,
  38731. + struct ethtool_ringparam *er)
  38732. +{
  38733. + struct ag71xx *ag = netdev_priv(dev);
  38734. + unsigned tx_size;
  38735. + unsigned rx_size;
  38736. + int err;
  38737. +
  38738. + if (er->rx_mini_pending != 0||
  38739. + er->rx_jumbo_pending != 0 ||
  38740. + er->rx_pending == 0 ||
  38741. + er->tx_pending == 0)
  38742. + return -EINVAL;
  38743. +
  38744. + tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ?
  38745. + er->tx_pending : AG71XX_TX_RING_SIZE_MAX;
  38746. +
  38747. + rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ?
  38748. + er->rx_pending : AG71XX_RX_RING_SIZE_MAX;
  38749. +
  38750. + if (netif_running(dev)) {
  38751. + err = dev->netdev_ops->ndo_stop(dev);
  38752. + if (err)
  38753. + return err;
  38754. + }
  38755. +
  38756. + if (ag->tx_ring.desc_split)
  38757. + tx_size *= AG71XX_TX_RING_DS_PER_PKT;
  38758. +
  38759. + ag->tx_ring.size = tx_size;
  38760. + ag->rx_ring.size = rx_size;
  38761. +
  38762. + if (netif_running(dev))
  38763. + err = dev->netdev_ops->ndo_open(dev);
  38764. +
  38765. + return err;
  38766. +}
  38767. +
  38768. +struct ethtool_ops ag71xx_ethtool_ops = {
  38769. + .set_settings = ag71xx_ethtool_set_settings,
  38770. + .get_settings = ag71xx_ethtool_get_settings,
  38771. + .get_drvinfo = ag71xx_ethtool_get_drvinfo,
  38772. + .get_msglevel = ag71xx_ethtool_get_msglevel,
  38773. + .set_msglevel = ag71xx_ethtool_set_msglevel,
  38774. + .get_ringparam = ag71xx_ethtool_get_ringparam,
  38775. + .set_ringparam = ag71xx_ethtool_set_ringparam,
  38776. + .get_link = ethtool_op_get_link,
  38777. +};
  38778. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
  38779. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c 1970-01-01 01:00:00.000000000 +0100
  38780. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c 2017-08-06 20:02:16.000000000 +0200
  38781. @@ -0,0 +1,1406 @@
  38782. +/*
  38783. + * Atheros AR71xx built-in ethernet mac driver
  38784. + *
  38785. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  38786. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  38787. + *
  38788. + * Based on Atheros' AG7100 driver
  38789. + *
  38790. + * This program is free software; you can redistribute it and/or modify it
  38791. + * under the terms of the GNU General Public License version 2 as published
  38792. + * by the Free Software Foundation.
  38793. + */
  38794. +
  38795. +#include "ag71xx.h"
  38796. +
  38797. +#define AG71XX_DEFAULT_MSG_ENABLE \
  38798. + (NETIF_MSG_DRV \
  38799. + | NETIF_MSG_PROBE \
  38800. + | NETIF_MSG_LINK \
  38801. + | NETIF_MSG_TIMER \
  38802. + | NETIF_MSG_IFDOWN \
  38803. + | NETIF_MSG_IFUP \
  38804. + | NETIF_MSG_RX_ERR \
  38805. + | NETIF_MSG_TX_ERR)
  38806. +
  38807. +static int ag71xx_msg_level = -1;
  38808. +
  38809. +module_param_named(msg_level, ag71xx_msg_level, int, 0);
  38810. +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  38811. +
  38812. +#define ETH_SWITCH_HEADER_LEN 2
  38813. +
  38814. +static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
  38815. +{
  38816. + return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
  38817. +}
  38818. +
  38819. +static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  38820. +{
  38821. + DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  38822. + ag->dev->name,
  38823. + ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  38824. + ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  38825. + ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38826. +
  38827. + DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  38828. + ag->dev->name,
  38829. + ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  38830. + ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  38831. + ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  38832. +}
  38833. +
  38834. +static void ag71xx_dump_regs(struct ag71xx *ag)
  38835. +{
  38836. + DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  38837. + ag->dev->name,
  38838. + ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  38839. + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  38840. + ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  38841. + ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  38842. + ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  38843. + DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  38844. + ag->dev->name,
  38845. + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  38846. + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  38847. + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  38848. + DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  38849. + ag->dev->name,
  38850. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  38851. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  38852. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  38853. + DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  38854. + ag->dev->name,
  38855. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  38856. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  38857. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  38858. +}
  38859. +
  38860. +static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  38861. +{
  38862. + DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  38863. + ag->dev->name, label, intr,
  38864. + (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  38865. + (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  38866. + (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  38867. + (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  38868. + (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  38869. + (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  38870. +}
  38871. +
  38872. +static void ag71xx_ring_free(struct ag71xx_ring *ring)
  38873. +{
  38874. + kfree(ring->buf);
  38875. +
  38876. + if (ring->descs_cpu)
  38877. + dma_free_coherent(NULL, ring->size * ring->desc_size,
  38878. + ring->descs_cpu, ring->descs_dma);
  38879. +}
  38880. +
  38881. +static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
  38882. +{
  38883. + int err;
  38884. +
  38885. + ring->desc_size = sizeof(struct ag71xx_desc);
  38886. + if (ring->desc_size % cache_line_size()) {
  38887. + DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
  38888. + ring, ring->desc_size,
  38889. + roundup(ring->desc_size, cache_line_size()));
  38890. + ring->desc_size = roundup(ring->desc_size, cache_line_size());
  38891. + }
  38892. +
  38893. + ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
  38894. + &ring->descs_dma, GFP_ATOMIC);
  38895. + if (!ring->descs_cpu) {
  38896. + err = -ENOMEM;
  38897. + goto err;
  38898. + }
  38899. +
  38900. +
  38901. + ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
  38902. + if (!ring->buf) {
  38903. + err = -ENOMEM;
  38904. + goto err;
  38905. + }
  38906. +
  38907. + return 0;
  38908. +
  38909. +err:
  38910. + return err;
  38911. +}
  38912. +
  38913. +static void ag71xx_ring_tx_clean(struct ag71xx *ag)
  38914. +{
  38915. + struct ag71xx_ring *ring = &ag->tx_ring;
  38916. + struct net_device *dev = ag->dev;
  38917. + u32 bytes_compl = 0, pkts_compl = 0;
  38918. +
  38919. + while (ring->curr != ring->dirty) {
  38920. + struct ag71xx_desc *desc;
  38921. + u32 i = ring->dirty % ring->size;
  38922. +
  38923. + desc = ag71xx_ring_desc(ring, i);
  38924. + if (!ag71xx_desc_empty(desc)) {
  38925. + desc->ctrl = 0;
  38926. + dev->stats.tx_errors++;
  38927. + }
  38928. +
  38929. + if (ring->buf[i].skb) {
  38930. + bytes_compl += ring->buf[i].len;
  38931. + pkts_compl++;
  38932. + dev_kfree_skb_any(ring->buf[i].skb);
  38933. + }
  38934. + ring->buf[i].skb = NULL;
  38935. + ring->dirty++;
  38936. + }
  38937. +
  38938. + /* flush descriptors */
  38939. + wmb();
  38940. +
  38941. + netdev_completed_queue(dev, pkts_compl, bytes_compl);
  38942. +}
  38943. +
  38944. +static void ag71xx_ring_tx_init(struct ag71xx *ag)
  38945. +{
  38946. + struct ag71xx_ring *ring = &ag->tx_ring;
  38947. + int i;
  38948. +
  38949. + for (i = 0; i < ring->size; i++) {
  38950. + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
  38951. +
  38952. + desc->next = (u32) (ring->descs_dma +
  38953. + ring->desc_size * ((i + 1) % ring->size));
  38954. +
  38955. + desc->ctrl = DESC_EMPTY;
  38956. + ring->buf[i].skb = NULL;
  38957. + }
  38958. +
  38959. + /* flush descriptors */
  38960. + wmb();
  38961. +
  38962. + ring->curr = 0;
  38963. + ring->dirty = 0;
  38964. + netdev_reset_queue(ag->dev);
  38965. +}
  38966. +
  38967. +static void ag71xx_ring_rx_clean(struct ag71xx *ag)
  38968. +{
  38969. + struct ag71xx_ring *ring = &ag->rx_ring;
  38970. + int i;
  38971. +
  38972. + if (!ring->buf)
  38973. + return;
  38974. +
  38975. + for (i = 0; i < ring->size; i++)
  38976. + if (ring->buf[i].rx_buf) {
  38977. + dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
  38978. + ag->rx_buf_size, DMA_FROM_DEVICE);
  38979. + kfree(ring->buf[i].rx_buf);
  38980. + }
  38981. +}
  38982. +
  38983. +static int ag71xx_buffer_offset(struct ag71xx *ag)
  38984. +{
  38985. + int offset = NET_SKB_PAD;
  38986. +
  38987. + /*
  38988. + * On AR71xx/AR91xx packets must be 4-byte aligned.
  38989. + *
  38990. + * When using builtin AR8216 support, hardware adds a 2-byte header,
  38991. + * so we don't need any extra alignment in that case.
  38992. + */
  38993. + if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
  38994. + return offset;
  38995. +
  38996. + return offset + NET_IP_ALIGN;
  38997. +}
  38998. +
  38999. +static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
  39000. + int offset)
  39001. +{
  39002. + struct ag71xx_ring *ring = &ag->rx_ring;
  39003. + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
  39004. + void *data;
  39005. +
  39006. + data = kmalloc(ag->rx_buf_size +
  39007. + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
  39008. + GFP_ATOMIC);
  39009. + if (!data)
  39010. + return false;
  39011. +
  39012. + buf->rx_buf = data;
  39013. + buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
  39014. + DMA_FROM_DEVICE);
  39015. + desc->data = (u32) buf->dma_addr + offset;
  39016. + return true;
  39017. +}
  39018. +
  39019. +static int ag71xx_ring_rx_init(struct ag71xx *ag)
  39020. +{
  39021. + struct ag71xx_ring *ring = &ag->rx_ring;
  39022. + unsigned int i;
  39023. + int ret;
  39024. + int offset = ag71xx_buffer_offset(ag);
  39025. +
  39026. + ret = 0;
  39027. + for (i = 0; i < ring->size; i++) {
  39028. + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
  39029. +
  39030. + desc->next = (u32) (ring->descs_dma +
  39031. + ring->desc_size * ((i + 1) % ring->size));
  39032. +
  39033. + DBG("ag71xx: RX desc at %p, next is %08x\n",
  39034. + desc, desc->next);
  39035. + }
  39036. +
  39037. + for (i = 0; i < ring->size; i++) {
  39038. + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
  39039. +
  39040. + if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
  39041. + ret = -ENOMEM;
  39042. + break;
  39043. + }
  39044. +
  39045. + desc->ctrl = DESC_EMPTY;
  39046. + }
  39047. +
  39048. + /* flush descriptors */
  39049. + wmb();
  39050. +
  39051. + ring->curr = 0;
  39052. + ring->dirty = 0;
  39053. +
  39054. + return ret;
  39055. +}
  39056. +
  39057. +static int ag71xx_ring_rx_refill(struct ag71xx *ag)
  39058. +{
  39059. + struct ag71xx_ring *ring = &ag->rx_ring;
  39060. + unsigned int count;
  39061. + int offset = ag71xx_buffer_offset(ag);
  39062. +
  39063. + count = 0;
  39064. + for (; ring->curr - ring->dirty > 0; ring->dirty++) {
  39065. + struct ag71xx_desc *desc;
  39066. + unsigned int i;
  39067. +
  39068. + i = ring->dirty % ring->size;
  39069. + desc = ag71xx_ring_desc(ring, i);
  39070. +
  39071. + if (!ring->buf[i].rx_buf &&
  39072. + !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
  39073. + break;
  39074. +
  39075. + desc->ctrl = DESC_EMPTY;
  39076. + count++;
  39077. + }
  39078. +
  39079. + /* flush descriptors */
  39080. + wmb();
  39081. +
  39082. + DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
  39083. +
  39084. + return count;
  39085. +}
  39086. +
  39087. +static int ag71xx_rings_init(struct ag71xx *ag)
  39088. +{
  39089. + int ret;
  39090. +
  39091. + ret = ag71xx_ring_alloc(&ag->tx_ring);
  39092. + if (ret)
  39093. + return ret;
  39094. +
  39095. + ag71xx_ring_tx_init(ag);
  39096. +
  39097. + ret = ag71xx_ring_alloc(&ag->rx_ring);
  39098. + if (ret)
  39099. + return ret;
  39100. +
  39101. + ret = ag71xx_ring_rx_init(ag);
  39102. + return ret;
  39103. +}
  39104. +
  39105. +static void ag71xx_rings_cleanup(struct ag71xx *ag)
  39106. +{
  39107. + ag71xx_ring_rx_clean(ag);
  39108. + ag71xx_ring_free(&ag->rx_ring);
  39109. +
  39110. + ag71xx_ring_tx_clean(ag);
  39111. + netdev_reset_queue(ag->dev);
  39112. + ag71xx_ring_free(&ag->tx_ring);
  39113. +}
  39114. +
  39115. +static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
  39116. +{
  39117. + switch (ag->speed) {
  39118. + case SPEED_1000:
  39119. + return "1000";
  39120. + case SPEED_100:
  39121. + return "100";
  39122. + case SPEED_10:
  39123. + return "10";
  39124. + }
  39125. +
  39126. + return "?";
  39127. +}
  39128. +
  39129. +static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
  39130. +{
  39131. + u32 t;
  39132. +
  39133. + t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
  39134. + | (((u32) mac[3]) << 8) | ((u32) mac[2]);
  39135. +
  39136. + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
  39137. +
  39138. + t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
  39139. + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
  39140. +}
  39141. +
  39142. +static void ag71xx_dma_reset(struct ag71xx *ag)
  39143. +{
  39144. + u32 val;
  39145. + int i;
  39146. +
  39147. + ag71xx_dump_dma_regs(ag);
  39148. +
  39149. + /* stop RX and TX */
  39150. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
  39151. + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
  39152. +
  39153. + /*
  39154. + * give the hardware some time to really stop all rx/tx activity
  39155. + * clearing the descriptors too early causes random memory corruption
  39156. + */
  39157. + mdelay(1);
  39158. +
  39159. + /* clear descriptor addresses */
  39160. + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
  39161. + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
  39162. +
  39163. + /* clear pending RX/TX interrupts */
  39164. + for (i = 0; i < 256; i++) {
  39165. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
  39166. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
  39167. + }
  39168. +
  39169. + /* clear pending errors */
  39170. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
  39171. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
  39172. +
  39173. + val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
  39174. + if (val)
  39175. + pr_alert("%s: unable to clear DMA Rx status: %08x\n",
  39176. + ag->dev->name, val);
  39177. +
  39178. + val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
  39179. +
  39180. + /* mask out reserved bits */
  39181. + val &= ~0xff000000;
  39182. +
  39183. + if (val)
  39184. + pr_alert("%s: unable to clear DMA Tx status: %08x\n",
  39185. + ag->dev->name, val);
  39186. +
  39187. + ag71xx_dump_dma_regs(ag);
  39188. +}
  39189. +
  39190. +#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
  39191. + MAC_CFG1_SRX | MAC_CFG1_STX)
  39192. +
  39193. +#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
  39194. +
  39195. +#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
  39196. + FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
  39197. + FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
  39198. + FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
  39199. + FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
  39200. + FIFO_CFG4_VT)
  39201. +
  39202. +#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
  39203. + FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
  39204. + FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
  39205. + FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
  39206. + FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
  39207. + FIFO_CFG5_17 | FIFO_CFG5_SF)
  39208. +
  39209. +static void ag71xx_hw_stop(struct ag71xx *ag)
  39210. +{
  39211. + /* disable all interrupts and stop the rx/tx engine */
  39212. + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
  39213. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
  39214. + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
  39215. +}
  39216. +
  39217. +static void ag71xx_hw_setup(struct ag71xx *ag)
  39218. +{
  39219. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  39220. +
  39221. + /* setup MAC configuration registers */
  39222. + ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
  39223. +
  39224. + ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
  39225. + MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
  39226. +
  39227. + /* setup max frame length to zero */
  39228. + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
  39229. +
  39230. + /* setup FIFO configuration registers */
  39231. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
  39232. + if (pdata->is_ar724x) {
  39233. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
  39234. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
  39235. + } else {
  39236. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
  39237. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
  39238. + }
  39239. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
  39240. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
  39241. +}
  39242. +
  39243. +static void ag71xx_hw_init(struct ag71xx *ag)
  39244. +{
  39245. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  39246. + u32 reset_mask = pdata->reset_bit;
  39247. +
  39248. + ag71xx_hw_stop(ag);
  39249. +
  39250. + if (pdata->is_ar724x) {
  39251. + u32 reset_phy = reset_mask;
  39252. +
  39253. + reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
  39254. + reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
  39255. +
  39256. + ath79_device_reset_set(reset_phy);
  39257. + msleep(50);
  39258. + ath79_device_reset_clear(reset_phy);
  39259. + msleep(200);
  39260. + }
  39261. +
  39262. + ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
  39263. + udelay(20);
  39264. +
  39265. + ath79_device_reset_set(reset_mask);
  39266. + msleep(100);
  39267. + ath79_device_reset_clear(reset_mask);
  39268. + msleep(200);
  39269. +
  39270. + ag71xx_hw_setup(ag);
  39271. +
  39272. + ag71xx_dma_reset(ag);
  39273. +}
  39274. +
  39275. +static void ag71xx_fast_reset(struct ag71xx *ag)
  39276. +{
  39277. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  39278. + struct net_device *dev = ag->dev;
  39279. + u32 reset_mask = pdata->reset_bit;
  39280. + u32 rx_ds, tx_ds;
  39281. + u32 mii_reg;
  39282. +
  39283. + reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
  39284. +
  39285. + mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
  39286. + rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
  39287. + tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
  39288. +
  39289. + ath79_device_reset_set(reset_mask);
  39290. + udelay(10);
  39291. + ath79_device_reset_clear(reset_mask);
  39292. + udelay(10);
  39293. +
  39294. + ag71xx_dma_reset(ag);
  39295. + ag71xx_hw_setup(ag);
  39296. +
  39297. + /* setup max frame length */
  39298. + ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
  39299. + ag71xx_max_frame_len(ag->dev->mtu));
  39300. +
  39301. + ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
  39302. + ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
  39303. + ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
  39304. +
  39305. + ag71xx_hw_set_macaddr(ag, dev->dev_addr);
  39306. +}
  39307. +
  39308. +static void ag71xx_hw_start(struct ag71xx *ag)
  39309. +{
  39310. + /* start RX engine */
  39311. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
  39312. +
  39313. + /* enable interrupts */
  39314. + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
  39315. +}
  39316. +
  39317. +void ag71xx_link_adjust(struct ag71xx *ag)
  39318. +{
  39319. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  39320. + u32 cfg2;
  39321. + u32 ifctl;
  39322. + u32 fifo5;
  39323. + u32 fifo3;
  39324. +
  39325. + if (!ag->link) {
  39326. + ag71xx_hw_stop(ag);
  39327. + netif_carrier_off(ag->dev);
  39328. + if (netif_msg_link(ag))
  39329. + pr_info("%s: link down\n", ag->dev->name);
  39330. + return;
  39331. + }
  39332. +
  39333. + if (pdata->is_ar724x)
  39334. + ag71xx_fast_reset(ag);
  39335. +
  39336. + cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
  39337. + cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
  39338. + cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
  39339. +
  39340. + ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
  39341. + ifctl &= ~(MAC_IFCTL_SPEED);
  39342. +
  39343. + fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
  39344. + fifo5 &= ~FIFO_CFG5_BM;
  39345. +
  39346. + switch (ag->speed) {
  39347. + case SPEED_1000:
  39348. + cfg2 |= MAC_CFG2_IF_1000;
  39349. + fifo5 |= FIFO_CFG5_BM;
  39350. + break;
  39351. + case SPEED_100:
  39352. + cfg2 |= MAC_CFG2_IF_10_100;
  39353. + ifctl |= MAC_IFCTL_SPEED;
  39354. + break;
  39355. + case SPEED_10:
  39356. + cfg2 |= MAC_CFG2_IF_10_100;
  39357. + break;
  39358. + default:
  39359. + BUG();
  39360. + return;
  39361. + }
  39362. +
  39363. + if (pdata->is_ar91xx)
  39364. + fifo3 = 0x00780fff;
  39365. + else if (pdata->is_ar724x)
  39366. + fifo3 = pdata->fifo_cfg3;
  39367. + else
  39368. + fifo3 = 0x008001ff;
  39369. +
  39370. + if (ag->tx_ring.desc_split) {
  39371. + fifo3 &= 0xffff;
  39372. + fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
  39373. + }
  39374. +
  39375. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
  39376. +
  39377. + if (pdata->set_speed)
  39378. + pdata->set_speed(ag->speed);
  39379. +
  39380. + ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
  39381. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
  39382. + ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
  39383. + ag71xx_hw_start(ag);
  39384. +
  39385. + netif_carrier_on(ag->dev);
  39386. + if (netif_msg_link(ag))
  39387. + pr_info("%s: link up (%sMbps/%s duplex)\n",
  39388. + ag->dev->name,
  39389. + ag71xx_speed_str(ag),
  39390. + (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
  39391. +
  39392. + DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
  39393. + ag->dev->name,
  39394. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  39395. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  39396. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  39397. +
  39398. + DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
  39399. + ag->dev->name,
  39400. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  39401. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  39402. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  39403. +
  39404. + DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
  39405. + ag->dev->name,
  39406. + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  39407. + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
  39408. +}
  39409. +
  39410. +static int ag71xx_open(struct net_device *dev)
  39411. +{
  39412. + struct ag71xx *ag = netdev_priv(dev);
  39413. + unsigned int max_frame_len;
  39414. + int ret;
  39415. +
  39416. + max_frame_len = ag71xx_max_frame_len(dev->mtu);
  39417. + ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
  39418. +
  39419. + /* setup max frame length */
  39420. + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
  39421. +
  39422. + ret = ag71xx_rings_init(ag);
  39423. + if (ret)
  39424. + goto err;
  39425. +
  39426. + napi_enable(&ag->napi);
  39427. +
  39428. + netif_carrier_off(dev);
  39429. + ag71xx_phy_start(ag);
  39430. +
  39431. + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
  39432. + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
  39433. +
  39434. + ag71xx_hw_set_macaddr(ag, dev->dev_addr);
  39435. +
  39436. + netif_start_queue(dev);
  39437. +
  39438. + return 0;
  39439. +
  39440. +err:
  39441. + ag71xx_rings_cleanup(ag);
  39442. + return ret;
  39443. +}
  39444. +
  39445. +static int ag71xx_stop(struct net_device *dev)
  39446. +{
  39447. + struct ag71xx *ag = netdev_priv(dev);
  39448. + unsigned long flags;
  39449. +
  39450. + netif_carrier_off(dev);
  39451. + ag71xx_phy_stop(ag);
  39452. +
  39453. + spin_lock_irqsave(&ag->lock, flags);
  39454. +
  39455. + netif_stop_queue(dev);
  39456. +
  39457. + ag71xx_hw_stop(ag);
  39458. + ag71xx_dma_reset(ag);
  39459. +
  39460. + napi_disable(&ag->napi);
  39461. + del_timer_sync(&ag->oom_timer);
  39462. +
  39463. + spin_unlock_irqrestore(&ag->lock, flags);
  39464. +
  39465. + ag71xx_rings_cleanup(ag);
  39466. +
  39467. + return 0;
  39468. +}
  39469. +
  39470. +static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
  39471. +{
  39472. + int i;
  39473. + struct ag71xx_desc *desc;
  39474. + int ndesc = 0;
  39475. + int split = ring->desc_split;
  39476. +
  39477. + if (!split)
  39478. + split = len;
  39479. +
  39480. + while (len > 0) {
  39481. + unsigned int cur_len = len;
  39482. +
  39483. + i = (ring->curr + ndesc) % ring->size;
  39484. + desc = ag71xx_ring_desc(ring, i);
  39485. +
  39486. + if (!ag71xx_desc_empty(desc))
  39487. + return -1;
  39488. +
  39489. + if (cur_len > split) {
  39490. + cur_len = split;
  39491. +
  39492. + /*
  39493. + * TX will hang if DMA transfers <= 4 bytes,
  39494. + * make sure next segment is more than 4 bytes long.
  39495. + */
  39496. + if (len <= split + 4)
  39497. + cur_len -= 4;
  39498. + }
  39499. +
  39500. + desc->data = addr;
  39501. + addr += cur_len;
  39502. + len -= cur_len;
  39503. +
  39504. + if (len > 0)
  39505. + cur_len |= DESC_MORE;
  39506. +
  39507. + /* prevent early tx attempt of this descriptor */
  39508. + if (!ndesc)
  39509. + cur_len |= DESC_EMPTY;
  39510. +
  39511. + desc->ctrl = cur_len;
  39512. + ndesc++;
  39513. + }
  39514. +
  39515. + return ndesc;
  39516. +}
  39517. +
  39518. +static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
  39519. + struct net_device *dev)
  39520. +{
  39521. + struct ag71xx *ag = netdev_priv(dev);
  39522. + struct ag71xx_ring *ring = &ag->tx_ring;
  39523. + struct ag71xx_desc *desc;
  39524. + dma_addr_t dma_addr;
  39525. + int i, n, ring_min;
  39526. +
  39527. + if (ag71xx_has_ar8216(ag))
  39528. + ag71xx_add_ar8216_header(ag, skb);
  39529. +
  39530. + if (skb->len <= 4) {
  39531. + DBG("%s: packet len is too small\n", ag->dev->name);
  39532. + goto err_drop;
  39533. + }
  39534. +
  39535. + dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
  39536. + DMA_TO_DEVICE);
  39537. +
  39538. + i = ring->curr % ring->size;
  39539. + desc = ag71xx_ring_desc(ring, i);
  39540. +
  39541. + /* setup descriptor fields */
  39542. + n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
  39543. + if (n < 0)
  39544. + goto err_drop_unmap;
  39545. +
  39546. + i = (ring->curr + n - 1) % ring->size;
  39547. + ring->buf[i].len = skb->len;
  39548. + ring->buf[i].skb = skb;
  39549. + ring->buf[i].timestamp = jiffies;
  39550. +
  39551. + netdev_sent_queue(dev, skb->len);
  39552. +
  39553. + desc->ctrl &= ~DESC_EMPTY;
  39554. + ring->curr += n;
  39555. +
  39556. + /* flush descriptor */
  39557. + wmb();
  39558. +
  39559. + ring_min = 2;
  39560. + if (ring->desc_split)
  39561. + ring_min *= AG71XX_TX_RING_DS_PER_PKT;
  39562. +
  39563. + if (ring->curr - ring->dirty >= ring->size - ring_min) {
  39564. + DBG("%s: tx queue full\n", dev->name);
  39565. + netif_stop_queue(dev);
  39566. + }
  39567. +
  39568. + DBG("%s: packet injected into TX queue\n", ag->dev->name);
  39569. +
  39570. + /* enable TX engine */
  39571. + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
  39572. +
  39573. + return NETDEV_TX_OK;
  39574. +
  39575. +err_drop_unmap:
  39576. + dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
  39577. +
  39578. +err_drop:
  39579. + dev->stats.tx_dropped++;
  39580. +
  39581. + dev_kfree_skb(skb);
  39582. + return NETDEV_TX_OK;
  39583. +}
  39584. +
  39585. +static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  39586. +{
  39587. + struct ag71xx *ag = netdev_priv(dev);
  39588. + int ret;
  39589. +
  39590. + switch (cmd) {
  39591. + case SIOCETHTOOL:
  39592. + if (ag->phy_dev == NULL)
  39593. + break;
  39594. +
  39595. + spin_lock_irq(&ag->lock);
  39596. + ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
  39597. + spin_unlock_irq(&ag->lock);
  39598. + return ret;
  39599. +
  39600. + case SIOCSIFHWADDR:
  39601. + if (copy_from_user
  39602. + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
  39603. + return -EFAULT;
  39604. + return 0;
  39605. +
  39606. + case SIOCGIFHWADDR:
  39607. + if (copy_to_user
  39608. + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
  39609. + return -EFAULT;
  39610. + return 0;
  39611. +
  39612. + case SIOCGMIIPHY:
  39613. + case SIOCGMIIREG:
  39614. + case SIOCSMIIREG:
  39615. + if (ag->phy_dev == NULL)
  39616. + break;
  39617. +
  39618. + return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
  39619. +
  39620. + default:
  39621. + break;
  39622. + }
  39623. +
  39624. + return -EOPNOTSUPP;
  39625. +}
  39626. +
  39627. +static void ag71xx_oom_timer_handler(unsigned long data)
  39628. +{
  39629. + struct net_device *dev = (struct net_device *) data;
  39630. + struct ag71xx *ag = netdev_priv(dev);
  39631. +
  39632. + napi_schedule(&ag->napi);
  39633. +}
  39634. +
  39635. +static void ag71xx_tx_timeout(struct net_device *dev)
  39636. +{
  39637. + struct ag71xx *ag = netdev_priv(dev);
  39638. +
  39639. + if (netif_msg_tx_err(ag))
  39640. + pr_info("%s: tx timeout\n", ag->dev->name);
  39641. +
  39642. + schedule_work(&ag->restart_work);
  39643. +}
  39644. +
  39645. +static void ag71xx_restart_work_func(struct work_struct *work)
  39646. +{
  39647. + struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
  39648. +
  39649. + if (ag71xx_get_pdata(ag)->is_ar724x) {
  39650. + ag->link = 0;
  39651. + ag71xx_link_adjust(ag);
  39652. + return;
  39653. + }
  39654. +
  39655. + ag71xx_stop(ag->dev);
  39656. + ag71xx_open(ag->dev);
  39657. +}
  39658. +
  39659. +static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
  39660. +{
  39661. + u32 rx_sm, tx_sm, rx_fd;
  39662. +
  39663. + if (likely(time_before(jiffies, timestamp + HZ/10)))
  39664. + return false;
  39665. +
  39666. + if (!netif_carrier_ok(ag->dev))
  39667. + return false;
  39668. +
  39669. + rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
  39670. + if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
  39671. + return true;
  39672. +
  39673. + tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
  39674. + rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
  39675. + if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
  39676. + ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
  39677. + return true;
  39678. +
  39679. + return false;
  39680. +}
  39681. +
  39682. +static int ag71xx_tx_packets(struct ag71xx *ag)
  39683. +{
  39684. + struct ag71xx_ring *ring = &ag->tx_ring;
  39685. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  39686. + int sent = 0;
  39687. + int bytes_compl = 0;
  39688. + int n = 0;
  39689. +
  39690. + DBG("%s: processing TX ring\n", ag->dev->name);
  39691. +
  39692. + while (ring->dirty + n != ring->curr) {
  39693. + unsigned int i = (ring->dirty + n) % ring->size;
  39694. + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
  39695. + struct sk_buff *skb = ring->buf[i].skb;
  39696. +
  39697. + if (!ag71xx_desc_empty(desc)) {
  39698. + if (pdata->is_ar7240 &&
  39699. + ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
  39700. + schedule_work(&ag->restart_work);
  39701. + break;
  39702. + }
  39703. +
  39704. + n++;
  39705. + if (!skb)
  39706. + continue;
  39707. +
  39708. + dev_kfree_skb_any(skb);
  39709. + ring->buf[i].skb = NULL;
  39710. +
  39711. + bytes_compl += ring->buf[i].len;
  39712. +
  39713. + sent++;
  39714. + ring->dirty += n;
  39715. +
  39716. + while (n > 0) {
  39717. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
  39718. + n--;
  39719. + }
  39720. + }
  39721. +
  39722. + DBG("%s: %d packets sent out\n", ag->dev->name, sent);
  39723. +
  39724. + ag->dev->stats.tx_bytes += bytes_compl;
  39725. + ag->dev->stats.tx_packets += sent;
  39726. +
  39727. + if (!sent)
  39728. + return 0;
  39729. +
  39730. + netdev_completed_queue(ag->dev, sent, bytes_compl);
  39731. + if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
  39732. + netif_wake_queue(ag->dev);
  39733. +
  39734. + return sent;
  39735. +}
  39736. +
  39737. +static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
  39738. +{
  39739. + struct net_device *dev = ag->dev;
  39740. + struct ag71xx_ring *ring = &ag->rx_ring;
  39741. + int offset = ag71xx_buffer_offset(ag);
  39742. + unsigned int pktlen_mask = ag->desc_pktlen_mask;
  39743. + int done = 0;
  39744. +
  39745. + DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
  39746. + dev->name, limit, ring->curr, ring->dirty);
  39747. +
  39748. + while (done < limit) {
  39749. + unsigned int i = ring->curr % ring->size;
  39750. + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
  39751. + struct sk_buff *skb;
  39752. + int pktlen;
  39753. + int err = 0;
  39754. +
  39755. + if (ag71xx_desc_empty(desc))
  39756. + break;
  39757. +
  39758. + if ((ring->dirty + ring->size) == ring->curr) {
  39759. + ag71xx_assert(0);
  39760. + break;
  39761. + }
  39762. +
  39763. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
  39764. +
  39765. + pktlen = desc->ctrl & pktlen_mask;
  39766. + pktlen -= ETH_FCS_LEN;
  39767. +
  39768. + dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
  39769. + ag->rx_buf_size, DMA_FROM_DEVICE);
  39770. +
  39771. + dev->stats.rx_packets++;
  39772. + dev->stats.rx_bytes += pktlen;
  39773. +
  39774. + skb = build_skb(ring->buf[i].rx_buf, 0);
  39775. + if (!skb) {
  39776. + kfree(ring->buf[i].rx_buf);
  39777. + goto next;
  39778. + }
  39779. +
  39780. + skb_reserve(skb, offset);
  39781. + skb_put(skb, pktlen);
  39782. +
  39783. + if (ag71xx_has_ar8216(ag))
  39784. + err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
  39785. +
  39786. + if (err) {
  39787. + dev->stats.rx_dropped++;
  39788. + kfree_skb(skb);
  39789. + } else {
  39790. + skb->dev = dev;
  39791. + skb->ip_summed = CHECKSUM_NONE;
  39792. + skb->protocol = eth_type_trans(skb, dev);
  39793. + netif_receive_skb(skb);
  39794. + }
  39795. +
  39796. +next:
  39797. + ring->buf[i].rx_buf = NULL;
  39798. + done++;
  39799. +
  39800. + ring->curr++;
  39801. + }
  39802. +
  39803. + ag71xx_ring_rx_refill(ag);
  39804. +
  39805. + DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
  39806. + dev->name, ring->curr, ring->dirty, done);
  39807. +
  39808. + return done;
  39809. +}
  39810. +
  39811. +static int ag71xx_poll(struct napi_struct *napi, int limit)
  39812. +{
  39813. + struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
  39814. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  39815. + struct net_device *dev = ag->dev;
  39816. + struct ag71xx_ring *rx_ring;
  39817. + unsigned long flags;
  39818. + u32 status;
  39819. + int tx_done;
  39820. + int rx_done;
  39821. +
  39822. + pdata->ddr_flush();
  39823. + tx_done = ag71xx_tx_packets(ag);
  39824. +
  39825. + DBG("%s: processing RX ring\n", dev->name);
  39826. + rx_done = ag71xx_rx_packets(ag, limit);
  39827. +
  39828. + ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
  39829. +
  39830. + rx_ring = &ag->rx_ring;
  39831. + if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
  39832. + goto oom;
  39833. +
  39834. + status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
  39835. + if (unlikely(status & RX_STATUS_OF)) {
  39836. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
  39837. + dev->stats.rx_fifo_errors++;
  39838. +
  39839. + /* restart RX */
  39840. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
  39841. + }
  39842. +
  39843. + if (rx_done < limit) {
  39844. + if (status & RX_STATUS_PR)
  39845. + goto more;
  39846. +
  39847. + status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
  39848. + if (status & TX_STATUS_PS)
  39849. + goto more;
  39850. +
  39851. + DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
  39852. + dev->name, rx_done, tx_done, limit);
  39853. +
  39854. + napi_complete(napi);
  39855. +
  39856. + /* enable interrupts */
  39857. + spin_lock_irqsave(&ag->lock, flags);
  39858. + ag71xx_int_enable(ag, AG71XX_INT_POLL);
  39859. + spin_unlock_irqrestore(&ag->lock, flags);
  39860. + return rx_done;
  39861. + }
  39862. +
  39863. +more:
  39864. + DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
  39865. + dev->name, rx_done, tx_done, limit);
  39866. + return limit;
  39867. +
  39868. +oom:
  39869. + if (netif_msg_rx_err(ag))
  39870. + pr_info("%s: out of memory\n", dev->name);
  39871. +
  39872. + mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
  39873. + napi_complete(napi);
  39874. + return 0;
  39875. +}
  39876. +
  39877. +static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
  39878. +{
  39879. + struct net_device *dev = dev_id;
  39880. + struct ag71xx *ag = netdev_priv(dev);
  39881. + u32 status;
  39882. +
  39883. + status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
  39884. + ag71xx_dump_intr(ag, "raw", status);
  39885. +
  39886. + if (unlikely(!status))
  39887. + return IRQ_NONE;
  39888. +
  39889. + if (unlikely(status & AG71XX_INT_ERR)) {
  39890. + if (status & AG71XX_INT_TX_BE) {
  39891. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
  39892. + dev_err(&dev->dev, "TX BUS error\n");
  39893. + }
  39894. + if (status & AG71XX_INT_RX_BE) {
  39895. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
  39896. + dev_err(&dev->dev, "RX BUS error\n");
  39897. + }
  39898. + }
  39899. +
  39900. + if (likely(status & AG71XX_INT_POLL)) {
  39901. + ag71xx_int_disable(ag, AG71XX_INT_POLL);
  39902. + DBG("%s: enable polling mode\n", dev->name);
  39903. + napi_schedule(&ag->napi);
  39904. + }
  39905. +
  39906. + ag71xx_debugfs_update_int_stats(ag, status);
  39907. +
  39908. + return IRQ_HANDLED;
  39909. +}
  39910. +
  39911. +#ifdef CONFIG_NET_POLL_CONTROLLER
  39912. +/*
  39913. + * Polling 'interrupt' - used by things like netconsole to send skbs
  39914. + * without having to re-enable interrupts. It's not called while
  39915. + * the interrupt routine is executing.
  39916. + */
  39917. +static void ag71xx_netpoll(struct net_device *dev)
  39918. +{
  39919. + disable_irq(dev->irq);
  39920. + ag71xx_interrupt(dev->irq, dev);
  39921. + enable_irq(dev->irq);
  39922. +}
  39923. +#endif
  39924. +
  39925. +static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
  39926. +{
  39927. + struct ag71xx *ag = netdev_priv(dev);
  39928. + unsigned int max_frame_len;
  39929. +
  39930. + max_frame_len = ag71xx_max_frame_len(new_mtu);
  39931. + if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
  39932. + return -EINVAL;
  39933. +
  39934. + if (netif_running(dev))
  39935. + return -EBUSY;
  39936. +
  39937. + dev->mtu = new_mtu;
  39938. + return 0;
  39939. +}
  39940. +
  39941. +static const struct net_device_ops ag71xx_netdev_ops = {
  39942. + .ndo_open = ag71xx_open,
  39943. + .ndo_stop = ag71xx_stop,
  39944. + .ndo_start_xmit = ag71xx_hard_start_xmit,
  39945. + .ndo_do_ioctl = ag71xx_do_ioctl,
  39946. + .ndo_tx_timeout = ag71xx_tx_timeout,
  39947. + .ndo_change_mtu = ag71xx_change_mtu,
  39948. + .ndo_set_mac_address = eth_mac_addr,
  39949. + .ndo_validate_addr = eth_validate_addr,
  39950. +#ifdef CONFIG_NET_POLL_CONTROLLER
  39951. + .ndo_poll_controller = ag71xx_netpoll,
  39952. +#endif
  39953. +};
  39954. +
  39955. +static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
  39956. +{
  39957. + switch (mode) {
  39958. + case PHY_INTERFACE_MODE_MII:
  39959. + return "MII";
  39960. + case PHY_INTERFACE_MODE_GMII:
  39961. + return "GMII";
  39962. + case PHY_INTERFACE_MODE_RMII:
  39963. + return "RMII";
  39964. + case PHY_INTERFACE_MODE_RGMII:
  39965. + return "RGMII";
  39966. + case PHY_INTERFACE_MODE_SGMII:
  39967. + return "SGMII";
  39968. + default:
  39969. + break;
  39970. + }
  39971. +
  39972. + return "unknown";
  39973. +}
  39974. +
  39975. +
  39976. +static int ag71xx_probe(struct platform_device *pdev)
  39977. +{
  39978. + struct net_device *dev;
  39979. + struct resource *res;
  39980. + struct ag71xx *ag;
  39981. + struct ag71xx_platform_data *pdata;
  39982. + int err;
  39983. +
  39984. + pdata = pdev->dev.platform_data;
  39985. + if (!pdata) {
  39986. + dev_err(&pdev->dev, "no platform data specified\n");
  39987. + err = -ENXIO;
  39988. + goto err_out;
  39989. + }
  39990. +
  39991. + if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
  39992. + dev_err(&pdev->dev, "no MII bus device specified\n");
  39993. + err = -EINVAL;
  39994. + goto err_out;
  39995. + }
  39996. +
  39997. + dev = alloc_etherdev(sizeof(*ag));
  39998. + if (!dev) {
  39999. + dev_err(&pdev->dev, "alloc_etherdev failed\n");
  40000. + err = -ENOMEM;
  40001. + goto err_out;
  40002. + }
  40003. +
  40004. + if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
  40005. + return -EINVAL;
  40006. +
  40007. + SET_NETDEV_DEV(dev, &pdev->dev);
  40008. +
  40009. + ag = netdev_priv(dev);
  40010. + ag->pdev = pdev;
  40011. + ag->dev = dev;
  40012. + ag->msg_enable = netif_msg_init(ag71xx_msg_level,
  40013. + AG71XX_DEFAULT_MSG_ENABLE);
  40014. + spin_lock_init(&ag->lock);
  40015. +
  40016. + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
  40017. + if (!res) {
  40018. + dev_err(&pdev->dev, "no mac_base resource found\n");
  40019. + err = -ENXIO;
  40020. + goto err_out;
  40021. + }
  40022. +
  40023. + ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
  40024. + if (!ag->mac_base) {
  40025. + dev_err(&pdev->dev, "unable to ioremap mac_base\n");
  40026. + err = -ENOMEM;
  40027. + goto err_free_dev;
  40028. + }
  40029. +
  40030. + dev->irq = platform_get_irq(pdev, 0);
  40031. + err = request_irq(dev->irq, ag71xx_interrupt,
  40032. + 0x0,
  40033. + dev->name, dev);
  40034. + if (err) {
  40035. + dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
  40036. + goto err_unmap_base;
  40037. + }
  40038. +
  40039. + dev->base_addr = (unsigned long)ag->mac_base;
  40040. + dev->netdev_ops = &ag71xx_netdev_ops;
  40041. + dev->ethtool_ops = &ag71xx_ethtool_ops;
  40042. +
  40043. + INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
  40044. +
  40045. + init_timer(&ag->oom_timer);
  40046. + ag->oom_timer.data = (unsigned long) dev;
  40047. + ag->oom_timer.function = ag71xx_oom_timer_handler;
  40048. +
  40049. + ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
  40050. + ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
  40051. +
  40052. + ag->max_frame_len = pdata->max_frame_len;
  40053. + ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
  40054. +
  40055. + if (!pdata->is_ar724x && !pdata->is_ar91xx) {
  40056. + ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
  40057. + ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT;
  40058. + }
  40059. +
  40060. + ag->stop_desc = dma_alloc_coherent(NULL,
  40061. + sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
  40062. +
  40063. + if (!ag->stop_desc)
  40064. + goto err_free_irq;
  40065. +
  40066. + ag->stop_desc->data = 0;
  40067. + ag->stop_desc->ctrl = 0;
  40068. + ag->stop_desc->next = (u32) ag->stop_desc_dma;
  40069. +
  40070. + memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
  40071. +
  40072. + netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
  40073. +
  40074. + ag71xx_dump_regs(ag);
  40075. +
  40076. + ag71xx_hw_init(ag);
  40077. +
  40078. + ag71xx_dump_regs(ag);
  40079. +
  40080. + err = ag71xx_phy_connect(ag);
  40081. + if (err)
  40082. + goto err_free_desc;
  40083. +
  40084. + err = ag71xx_debugfs_init(ag);
  40085. + if (err)
  40086. + goto err_phy_disconnect;
  40087. +
  40088. + platform_set_drvdata(pdev, dev);
  40089. +
  40090. + err = register_netdev(dev);
  40091. + if (err) {
  40092. + dev_err(&pdev->dev, "unable to register net device\n");
  40093. + goto err_debugfs_exit;
  40094. + }
  40095. +
  40096. + pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
  40097. + dev->name, dev->base_addr, dev->irq,
  40098. + ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
  40099. +
  40100. + return 0;
  40101. +
  40102. +err_debugfs_exit:
  40103. + ag71xx_debugfs_exit(ag);
  40104. +err_phy_disconnect:
  40105. + ag71xx_phy_disconnect(ag);
  40106. +err_free_desc:
  40107. + dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
  40108. + ag->stop_desc_dma);
  40109. +err_free_irq:
  40110. + free_irq(dev->irq, dev);
  40111. +err_unmap_base:
  40112. + iounmap(ag->mac_base);
  40113. +err_free_dev:
  40114. + kfree(dev);
  40115. +err_out:
  40116. + platform_set_drvdata(pdev, NULL);
  40117. + return err;
  40118. +}
  40119. +
  40120. +static int ag71xx_remove(struct platform_device *pdev)
  40121. +{
  40122. + struct net_device *dev = platform_get_drvdata(pdev);
  40123. +
  40124. + if (dev) {
  40125. + struct ag71xx *ag = netdev_priv(dev);
  40126. +
  40127. + ag71xx_debugfs_exit(ag);
  40128. + ag71xx_phy_disconnect(ag);
  40129. + unregister_netdev(dev);
  40130. + free_irq(dev->irq, dev);
  40131. + iounmap(ag->mac_base);
  40132. + kfree(dev);
  40133. + platform_set_drvdata(pdev, NULL);
  40134. + }
  40135. +
  40136. + return 0;
  40137. +}
  40138. +
  40139. +static struct platform_driver ag71xx_driver = {
  40140. + .probe = ag71xx_probe,
  40141. + .remove = ag71xx_remove,
  40142. + .driver = {
  40143. + .name = AG71XX_DRV_NAME,
  40144. + }
  40145. +};
  40146. +
  40147. +static int __init ag71xx_module_init(void)
  40148. +{
  40149. + int ret;
  40150. +
  40151. + ret = ag71xx_debugfs_root_init();
  40152. + if (ret)
  40153. + goto err_out;
  40154. +
  40155. + ret = ag71xx_mdio_driver_init();
  40156. + if (ret)
  40157. + goto err_debugfs_exit;
  40158. +
  40159. + ret = platform_driver_register(&ag71xx_driver);
  40160. + if (ret)
  40161. + goto err_mdio_exit;
  40162. +
  40163. + return 0;
  40164. +
  40165. +err_mdio_exit:
  40166. + ag71xx_mdio_driver_exit();
  40167. +err_debugfs_exit:
  40168. + ag71xx_debugfs_root_exit();
  40169. +err_out:
  40170. + return ret;
  40171. +}
  40172. +
  40173. +static void __exit ag71xx_module_exit(void)
  40174. +{
  40175. + platform_driver_unregister(&ag71xx_driver);
  40176. + ag71xx_mdio_driver_exit();
  40177. + ag71xx_debugfs_root_exit();
  40178. +}
  40179. +
  40180. +module_init(ag71xx_module_init);
  40181. +module_exit(ag71xx_module_exit);
  40182. +
  40183. +MODULE_VERSION(AG71XX_DRV_VERSION);
  40184. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  40185. +MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
  40186. +MODULE_LICENSE("GPL v2");
  40187. +MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
  40188. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c
  40189. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c 1970-01-01 01:00:00.000000000 +0100
  40190. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c 2017-08-06 20:02:16.000000000 +0200
  40191. @@ -0,0 +1,318 @@
  40192. +/*
  40193. + * Atheros AR71xx built-in ethernet mac driver
  40194. + *
  40195. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  40196. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  40197. + *
  40198. + * Based on Atheros' AG7100 driver
  40199. + *
  40200. + * This program is free software; you can redistribute it and/or modify it
  40201. + * under the terms of the GNU General Public License version 2 as published
  40202. + * by the Free Software Foundation.
  40203. + */
  40204. +
  40205. +#include "ag71xx.h"
  40206. +
  40207. +#define AG71XX_MDIO_RETRY 1000
  40208. +#define AG71XX_MDIO_DELAY 5
  40209. +
  40210. +static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg,
  40211. + u32 value)
  40212. +{
  40213. + void __iomem *r;
  40214. +
  40215. + r = am->mdio_base + reg;
  40216. + __raw_writel(value, r);
  40217. +
  40218. + /* flush write */
  40219. + (void) __raw_readl(r);
  40220. +}
  40221. +
  40222. +static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg)
  40223. +{
  40224. + return __raw_readl(am->mdio_base + reg);
  40225. +}
  40226. +
  40227. +static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am)
  40228. +{
  40229. + DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n",
  40230. + am->mii_bus->name,
  40231. + ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG),
  40232. + ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD),
  40233. + ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR));
  40234. + DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n",
  40235. + am->mii_bus->name,
  40236. + ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL),
  40237. + ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS),
  40238. + ag71xx_mdio_rr(am, AG71XX_REG_MII_IND));
  40239. +}
  40240. +
  40241. +static int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am)
  40242. +{
  40243. + int i;
  40244. +
  40245. + for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
  40246. + u32 busy;
  40247. +
  40248. + udelay(AG71XX_MDIO_DELAY);
  40249. +
  40250. + busy = ag71xx_mdio_rr(am, AG71XX_REG_MII_IND);
  40251. + if (!busy)
  40252. + return 0;
  40253. +
  40254. + udelay(AG71XX_MDIO_DELAY);
  40255. + }
  40256. +
  40257. + pr_err("%s: MDIO operation timed out\n", am->mii_bus->name);
  40258. +
  40259. + return -ETIMEDOUT;
  40260. +}
  40261. +
  40262. +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg)
  40263. +{
  40264. + int err;
  40265. + int ret;
  40266. +
  40267. + err = ag71xx_mdio_wait_busy(am);
  40268. + if (err)
  40269. + return 0xffff;
  40270. +
  40271. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  40272. + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  40273. + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  40274. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ);
  40275. +
  40276. + err = ag71xx_mdio_wait_busy(am);
  40277. + if (err)
  40278. + return 0xffff;
  40279. +
  40280. + ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff;
  40281. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  40282. +
  40283. + DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
  40284. +
  40285. + return ret;
  40286. +}
  40287. +
  40288. +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val)
  40289. +{
  40290. + DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
  40291. +
  40292. + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  40293. + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  40294. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val);
  40295. +
  40296. + ag71xx_mdio_wait_busy(am);
  40297. +}
  40298. +
  40299. +static const u32 ar71xx_mdio_div_table[] = {
  40300. + 4, 4, 6, 8, 10, 14, 20, 28,
  40301. +};
  40302. +
  40303. +static const u32 ar7240_mdio_div_table[] = {
  40304. + 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
  40305. +};
  40306. +
  40307. +static const u32 ar933x_mdio_div_table[] = {
  40308. + 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
  40309. +};
  40310. +
  40311. +static int ag71xx_mdio_get_divider(struct ag71xx_mdio *am, u32 *div)
  40312. +{
  40313. + unsigned long ref_clock, mdio_clock;
  40314. + const u32 *table;
  40315. + int ndivs;
  40316. + int i;
  40317. +
  40318. + ref_clock = am->pdata->ref_clock;
  40319. + mdio_clock = am->pdata->mdio_clock;
  40320. +
  40321. + if (!ref_clock || !mdio_clock)
  40322. + return -EINVAL;
  40323. +
  40324. + if (am->pdata->is_ar9330 || am->pdata->is_ar934x) {
  40325. + table = ar933x_mdio_div_table;
  40326. + ndivs = ARRAY_SIZE(ar933x_mdio_div_table);
  40327. + } else if (am->pdata->is_ar7240) {
  40328. + table = ar7240_mdio_div_table;
  40329. + ndivs = ARRAY_SIZE(ar7240_mdio_div_table);
  40330. + } else {
  40331. + table = ar71xx_mdio_div_table;
  40332. + ndivs = ARRAY_SIZE(ar71xx_mdio_div_table);
  40333. + }
  40334. +
  40335. + for (i = 0; i < ndivs; i++) {
  40336. + unsigned long t;
  40337. +
  40338. + t = ref_clock / table[i];
  40339. + if (t <= mdio_clock) {
  40340. + *div = i;
  40341. + return 0;
  40342. + }
  40343. + }
  40344. +
  40345. + dev_err(&am->mii_bus->dev, "no divider found for %lu/%lu\n",
  40346. + ref_clock, mdio_clock);
  40347. + return -ENOENT;
  40348. +}
  40349. +
  40350. +static int ag71xx_mdio_reset(struct mii_bus *bus)
  40351. +{
  40352. + struct ag71xx_mdio *am = bus->priv;
  40353. + u32 t;
  40354. + int err;
  40355. +
  40356. + err = ag71xx_mdio_get_divider(am, &t);
  40357. + if (err) {
  40358. + /* fallback */
  40359. + if (am->pdata->is_ar7240)
  40360. + t = MII_CFG_CLK_DIV_6;
  40361. + else if (am->pdata->builtin_switch && !am->pdata->is_ar934x)
  40362. + t = MII_CFG_CLK_DIV_10;
  40363. + else if (!am->pdata->builtin_switch && am->pdata->is_ar934x)
  40364. + t = MII_CFG_CLK_DIV_58;
  40365. + else
  40366. + t = MII_CFG_CLK_DIV_28;
  40367. + }
  40368. +
  40369. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
  40370. + udelay(100);
  40371. +
  40372. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t);
  40373. + udelay(100);
  40374. +
  40375. + if (am->pdata->reset)
  40376. + am->pdata->reset(bus);
  40377. +
  40378. + return 0;
  40379. +}
  40380. +
  40381. +static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg)
  40382. +{
  40383. + struct ag71xx_mdio *am = bus->priv;
  40384. +
  40385. + if (am->pdata->builtin_switch)
  40386. + return ar7240sw_phy_read(bus, addr, reg);
  40387. + else
  40388. + return ag71xx_mdio_mii_read(am, addr, reg);
  40389. +}
  40390. +
  40391. +static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
  40392. +{
  40393. + struct ag71xx_mdio *am = bus->priv;
  40394. +
  40395. + if (am->pdata->builtin_switch)
  40396. + ar7240sw_phy_write(bus, addr, reg, val);
  40397. + else
  40398. + ag71xx_mdio_mii_write(am, addr, reg, val);
  40399. + return 0;
  40400. +}
  40401. +
  40402. +static int ag71xx_mdio_probe(struct platform_device *pdev)
  40403. +{
  40404. + struct ag71xx_mdio_platform_data *pdata;
  40405. + struct ag71xx_mdio *am;
  40406. + struct resource *res;
  40407. + int i;
  40408. + int err;
  40409. +
  40410. + pdata = pdev->dev.platform_data;
  40411. + if (!pdata) {
  40412. + dev_err(&pdev->dev, "no platform data specified\n");
  40413. + return -EINVAL;
  40414. + }
  40415. +
  40416. + am = kzalloc(sizeof(*am), GFP_KERNEL);
  40417. + if (!am) {
  40418. + err = -ENOMEM;
  40419. + goto err_out;
  40420. + }
  40421. +
  40422. + am->pdata = pdata;
  40423. +
  40424. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  40425. + if (!res) {
  40426. + dev_err(&pdev->dev, "no iomem resource found\n");
  40427. + err = -ENXIO;
  40428. + goto err_out;
  40429. + }
  40430. +
  40431. + am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1);
  40432. + if (!am->mdio_base) {
  40433. + dev_err(&pdev->dev, "unable to ioremap registers\n");
  40434. + err = -ENOMEM;
  40435. + goto err_free_mdio;
  40436. + }
  40437. +
  40438. + am->mii_bus = mdiobus_alloc();
  40439. + if (am->mii_bus == NULL) {
  40440. + err = -ENOMEM;
  40441. + goto err_iounmap;
  40442. + }
  40443. +
  40444. + am->mii_bus->name = "ag71xx_mdio";
  40445. + am->mii_bus->read = ag71xx_mdio_read;
  40446. + am->mii_bus->write = ag71xx_mdio_write;
  40447. + am->mii_bus->reset = ag71xx_mdio_reset;
  40448. + am->mii_bus->irq = am->mii_irq;
  40449. + am->mii_bus->priv = am;
  40450. + am->mii_bus->parent = &pdev->dev;
  40451. + snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
  40452. + am->mii_bus->phy_mask = pdata->phy_mask;
  40453. +
  40454. + for (i = 0; i < PHY_MAX_ADDR; i++)
  40455. + am->mii_irq[i] = PHY_POLL;
  40456. +
  40457. + ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0);
  40458. +
  40459. + err = mdiobus_register(am->mii_bus);
  40460. + if (err)
  40461. + goto err_free_bus;
  40462. +
  40463. + ag71xx_mdio_dump_regs(am);
  40464. +
  40465. + platform_set_drvdata(pdev, am);
  40466. + return 0;
  40467. +
  40468. +err_free_bus:
  40469. + mdiobus_free(am->mii_bus);
  40470. +err_iounmap:
  40471. + iounmap(am->mdio_base);
  40472. +err_free_mdio:
  40473. + kfree(am);
  40474. +err_out:
  40475. + return err;
  40476. +}
  40477. +
  40478. +static int ag71xx_mdio_remove(struct platform_device *pdev)
  40479. +{
  40480. + struct ag71xx_mdio *am = platform_get_drvdata(pdev);
  40481. +
  40482. + if (am) {
  40483. + mdiobus_unregister(am->mii_bus);
  40484. + mdiobus_free(am->mii_bus);
  40485. + iounmap(am->mdio_base);
  40486. + kfree(am);
  40487. + platform_set_drvdata(pdev, NULL);
  40488. + }
  40489. +
  40490. + return 0;
  40491. +}
  40492. +
  40493. +static struct platform_driver ag71xx_mdio_driver = {
  40494. + .probe = ag71xx_mdio_probe,
  40495. + .remove = ag71xx_mdio_remove,
  40496. + .driver = {
  40497. + .name = "ag71xx-mdio",
  40498. + }
  40499. +};
  40500. +
  40501. +int __init ag71xx_mdio_driver_init(void)
  40502. +{
  40503. + return platform_driver_register(&ag71xx_mdio_driver);
  40504. +}
  40505. +
  40506. +void ag71xx_mdio_driver_exit(void)
  40507. +{
  40508. + platform_driver_unregister(&ag71xx_mdio_driver);
  40509. +}
  40510. diff -Nur linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
  40511. --- linux-4.1.43.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c 1970-01-01 01:00:00.000000000 +0100
  40512. +++ linux-4.1.43/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c 2017-08-06 20:02:16.000000000 +0200
  40513. @@ -0,0 +1,235 @@
  40514. +/*
  40515. + * Atheros AR71xx built-in ethernet mac driver
  40516. + *
  40517. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  40518. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  40519. + *
  40520. + * Based on Atheros' AG7100 driver
  40521. + *
  40522. + * This program is free software; you can redistribute it and/or modify it
  40523. + * under the terms of the GNU General Public License version 2 as published
  40524. + * by the Free Software Foundation.
  40525. + */
  40526. +
  40527. +#include "ag71xx.h"
  40528. +
  40529. +static void ag71xx_phy_link_adjust(struct net_device *dev)
  40530. +{
  40531. + struct ag71xx *ag = netdev_priv(dev);
  40532. + struct phy_device *phydev = ag->phy_dev;
  40533. + unsigned long flags;
  40534. + int status_change = 0;
  40535. +
  40536. + spin_lock_irqsave(&ag->lock, flags);
  40537. +
  40538. + if (phydev->link) {
  40539. + if (ag->duplex != phydev->duplex
  40540. + || ag->speed != phydev->speed) {
  40541. + status_change = 1;
  40542. + }
  40543. + }
  40544. +
  40545. + if (phydev->link != ag->link)
  40546. + status_change = 1;
  40547. +
  40548. + ag->link = phydev->link;
  40549. + ag->duplex = phydev->duplex;
  40550. + ag->speed = phydev->speed;
  40551. +
  40552. + if (status_change)
  40553. + ag71xx_link_adjust(ag);
  40554. +
  40555. + spin_unlock_irqrestore(&ag->lock, flags);
  40556. +}
  40557. +
  40558. +void ag71xx_phy_start(struct ag71xx *ag)
  40559. +{
  40560. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  40561. +
  40562. + if (ag->phy_dev) {
  40563. + phy_start(ag->phy_dev);
  40564. + } else if (pdata->mii_bus_dev && pdata->switch_data) {
  40565. + ag71xx_ar7240_start(ag);
  40566. + } else {
  40567. + ag->link = 1;
  40568. + ag71xx_link_adjust(ag);
  40569. + }
  40570. +}
  40571. +
  40572. +void ag71xx_phy_stop(struct ag71xx *ag)
  40573. +{
  40574. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  40575. + unsigned long flags;
  40576. +
  40577. + if (ag->phy_dev)
  40578. + phy_stop(ag->phy_dev);
  40579. + else if (pdata->mii_bus_dev && pdata->switch_data)
  40580. + ag71xx_ar7240_stop(ag);
  40581. +
  40582. + spin_lock_irqsave(&ag->lock, flags);
  40583. + if (ag->link) {
  40584. + ag->link = 0;
  40585. + ag71xx_link_adjust(ag);
  40586. + }
  40587. + spin_unlock_irqrestore(&ag->lock, flags);
  40588. +}
  40589. +
  40590. +static int ag71xx_phy_connect_fixed(struct ag71xx *ag)
  40591. +{
  40592. + struct device *dev = &ag->pdev->dev;
  40593. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  40594. + int ret = 0;
  40595. +
  40596. + /* use fixed settings */
  40597. + switch (pdata->speed) {
  40598. + case SPEED_10:
  40599. + case SPEED_100:
  40600. + case SPEED_1000:
  40601. + break;
  40602. + default:
  40603. + dev_err(dev, "invalid speed specified\n");
  40604. + ret = -EINVAL;
  40605. + break;
  40606. + }
  40607. +
  40608. + dev_dbg(dev, "using fixed link parameters\n");
  40609. +
  40610. + ag->duplex = pdata->duplex;
  40611. + ag->speed = pdata->speed;
  40612. +
  40613. + return ret;
  40614. +}
  40615. +
  40616. +static int ag71xx_phy_connect_multi(struct ag71xx *ag)
  40617. +{
  40618. + struct device *dev = &ag->pdev->dev;
  40619. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  40620. + struct phy_device *phydev = NULL;
  40621. + int phy_addr;
  40622. + int ret = 0;
  40623. +
  40624. + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  40625. + if (!(pdata->phy_mask & (1 << phy_addr)))
  40626. + continue;
  40627. +
  40628. + if (ag->mii_bus->phy_map[phy_addr] == NULL)
  40629. + continue;
  40630. +
  40631. + DBG("%s: PHY found at %s, uid=%08x\n",
  40632. + dev_name(dev),
  40633. + dev_name(&ag->mii_bus->phy_map[phy_addr]->dev),
  40634. + ag->mii_bus->phy_map[phy_addr]->phy_id);
  40635. +
  40636. + if (phydev == NULL)
  40637. + phydev = ag->mii_bus->phy_map[phy_addr];
  40638. + }
  40639. +
  40640. + if (!phydev) {
  40641. + dev_err(dev, "no PHY found with phy_mask=%08x\n",
  40642. + pdata->phy_mask);
  40643. + return -ENODEV;
  40644. + }
  40645. +
  40646. + ag->phy_dev = phy_connect(ag->dev, dev_name(&phydev->dev),
  40647. + &ag71xx_phy_link_adjust,
  40648. + pdata->phy_if_mode);
  40649. +
  40650. + if (IS_ERR(ag->phy_dev)) {
  40651. + dev_err(dev, "could not connect to PHY at %s\n",
  40652. + dev_name(&phydev->dev));
  40653. + return PTR_ERR(ag->phy_dev);
  40654. + }
  40655. +
  40656. + /* mask with MAC supported features */
  40657. + if (pdata->has_gbit)
  40658. + phydev->supported &= PHY_GBIT_FEATURES;
  40659. + else
  40660. + phydev->supported &= PHY_BASIC_FEATURES;
  40661. +
  40662. + phydev->advertising = phydev->supported;
  40663. +
  40664. + dev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n",
  40665. + dev_name(&phydev->dev), phydev->phy_id, phydev->drv->name);
  40666. +
  40667. + ag->link = 0;
  40668. + ag->speed = 0;
  40669. + ag->duplex = -1;
  40670. +
  40671. + return ret;
  40672. +}
  40673. +
  40674. +static int dev_is_class(struct device *dev, void *class)
  40675. +{
  40676. + if (dev->class != NULL && !strcmp(dev->class->name, class))
  40677. + return 1;
  40678. +
  40679. + return 0;
  40680. +}
  40681. +
  40682. +static struct device *dev_find_class(struct device *parent, char *class)
  40683. +{
  40684. + if (dev_is_class(parent, class)) {
  40685. + get_device(parent);
  40686. + return parent;
  40687. + }
  40688. +
  40689. + return device_find_child(parent, class, dev_is_class);
  40690. +}
  40691. +
  40692. +static struct mii_bus *dev_to_mii_bus(struct device *dev)
  40693. +{
  40694. + struct device *d;
  40695. +
  40696. + d = dev_find_class(dev, "mdio_bus");
  40697. + if (d != NULL) {
  40698. + struct mii_bus *bus;
  40699. +
  40700. + bus = to_mii_bus(d);
  40701. + put_device(d);
  40702. +
  40703. + return bus;
  40704. + }
  40705. +
  40706. + return NULL;
  40707. +}
  40708. +
  40709. +int ag71xx_phy_connect(struct ag71xx *ag)
  40710. +{
  40711. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  40712. +
  40713. + if (pdata->mii_bus_dev == NULL ||
  40714. + pdata->mii_bus_dev->bus == NULL )
  40715. + return ag71xx_phy_connect_fixed(ag);
  40716. +
  40717. + ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev);
  40718. + if (ag->mii_bus == NULL) {
  40719. + dev_err(&ag->pdev->dev, "unable to find MII bus on device '%s'\n",
  40720. + dev_name(pdata->mii_bus_dev));
  40721. + return -ENODEV;
  40722. + }
  40723. +
  40724. + /* Reset the mdio bus explicitly */
  40725. + if (ag->mii_bus->reset) {
  40726. + mutex_lock(&ag->mii_bus->mdio_lock);
  40727. + ag->mii_bus->reset(ag->mii_bus);
  40728. + mutex_unlock(&ag->mii_bus->mdio_lock);
  40729. + }
  40730. +
  40731. + if (pdata->switch_data)
  40732. + return ag71xx_ar7240_init(ag);
  40733. +
  40734. + if (pdata->phy_mask)
  40735. + return ag71xx_phy_connect_multi(ag);
  40736. +
  40737. + return ag71xx_phy_connect_fixed(ag);
  40738. +}
  40739. +
  40740. +void ag71xx_phy_disconnect(struct ag71xx *ag)
  40741. +{
  40742. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  40743. +
  40744. + if (pdata->switch_data)
  40745. + ag71xx_ar7240_cleanup(ag);
  40746. + else if (ag->phy_dev)
  40747. + phy_disconnect(ag->phy_dev);
  40748. +}
  40749. diff -Nur linux-4.1.43.orig/drivers/net/phy/Kconfig linux-4.1.43/drivers/net/phy/Kconfig
  40750. --- linux-4.1.43.orig/drivers/net/phy/Kconfig 2017-08-06 01:56:14.000000000 +0200
  40751. +++ linux-4.1.43/drivers/net/phy/Kconfig 2017-08-06 20:02:16.000000000 +0200
  40752. @@ -12,6 +12,16 @@
  40753. if PHYLIB
  40754. +config SWCONFIG
  40755. + tristate "Switch configuration API"
  40756. + ---help---
  40757. + Switch configuration API using netlink. This allows
  40758. + you to configure the VLAN features of certain switches.
  40759. +
  40760. +config SWCONFIG_LEDS
  40761. + bool "Switch LED trigger support"
  40762. + depends on (SWCONFIG && LEDS_TRIGGERS)
  40763. +
  40764. comment "MII PHY device drivers"
  40765. config AT803X_PHY
  40766. diff -Nur linux-4.1.43.orig/drivers/net/phy/Makefile linux-4.1.43/drivers/net/phy/Makefile
  40767. --- linux-4.1.43.orig/drivers/net/phy/Makefile 2017-08-06 01:56:14.000000000 +0200
  40768. +++ linux-4.1.43/drivers/net/phy/Makefile 2017-08-06 20:02:16.000000000 +0200
  40769. @@ -3,6 +3,7 @@
  40770. libphy-objs := phy.o phy_device.o mdio_bus.o
  40771. obj-$(CONFIG_PHYLIB) += libphy.o
  40772. +obj-$(CONFIG_SWCONFIG) += swconfig.o
  40773. obj-$(CONFIG_MARVELL_PHY) += marvell.o
  40774. obj-$(CONFIG_DAVICOM_PHY) += davicom.o
  40775. obj-$(CONFIG_CICADA_PHY) += cicada.o
  40776. diff -Nur linux-4.1.43.orig/drivers/net/phy/at803x.c linux-4.1.43/drivers/net/phy/at803x.c
  40777. --- linux-4.1.43.orig/drivers/net/phy/at803x.c 2017-08-06 01:56:14.000000000 +0200
  40778. +++ linux-4.1.43/drivers/net/phy/at803x.c 2017-08-06 20:02:16.000000000 +0200
  40779. @@ -12,12 +12,14 @@
  40780. */
  40781. #include <linux/phy.h>
  40782. +#include <linux/mdio.h>
  40783. #include <linux/module.h>
  40784. #include <linux/string.h>
  40785. #include <linux/netdevice.h>
  40786. #include <linux/etherdevice.h>
  40787. #include <linux/of_gpio.h>
  40788. #include <linux/gpio/consumer.h>
  40789. +#include <linux/platform_data/phy-at803x.h>
  40790. #define AT803X_INTR_ENABLE 0x12
  40791. #define AT803X_INTR_STATUS 0x13
  40792. @@ -34,8 +36,16 @@
  40793. #define AT803X_INER 0x0012
  40794. #define AT803X_INER_INIT 0xec00
  40795. #define AT803X_INSR 0x0013
  40796. +
  40797. +#define AT803X_PCS_SMART_EEE_CTRL3 0x805D
  40798. +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_MASK 0x3
  40799. +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT 12
  40800. +#define AT803X_SMART_EEE_CTRL3_LPI_EN BIT(8)
  40801. +
  40802. #define AT803X_DEBUG_ADDR 0x1D
  40803. #define AT803X_DEBUG_DATA 0x1E
  40804. +#define AT803X_DBG0_REG 0x00
  40805. +#define AT803X_DEBUG_RGMII_RX_CLK_DLY BIT(8)
  40806. #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
  40807. #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
  40808. @@ -50,6 +60,7 @@
  40809. struct at803x_priv {
  40810. bool phy_reset:1;
  40811. struct gpio_desc *gpiod_reset;
  40812. + int prev_speed;
  40813. };
  40814. struct at803x_context {
  40815. @@ -61,6 +72,43 @@
  40816. u16 led_control;
  40817. };
  40818. +static u16
  40819. +at803x_dbg_reg_rmw(struct phy_device *phydev, u16 reg, u16 clear, u16 set)
  40820. +{
  40821. + struct mii_bus *bus = phydev->bus;
  40822. + int val;
  40823. +
  40824. + mutex_lock(&bus->mdio_lock);
  40825. +
  40826. + bus->write(bus, phydev->addr, AT803X_DEBUG_ADDR, reg);
  40827. + val = bus->read(bus, phydev->addr, AT803X_DEBUG_DATA);
  40828. + if (val < 0) {
  40829. + val = 0xffff;
  40830. + goto out;
  40831. + }
  40832. +
  40833. + val &= ~clear;
  40834. + val |= set;
  40835. + bus->write(bus, phydev->addr, AT803X_DEBUG_DATA, val);
  40836. +
  40837. +out:
  40838. + mutex_unlock(&bus->mdio_lock);
  40839. + return val;
  40840. +}
  40841. +
  40842. +static inline void
  40843. +at803x_dbg_reg_set(struct phy_device *phydev, u16 reg, u16 set)
  40844. +{
  40845. + at803x_dbg_reg_rmw(phydev, reg, 0, set);
  40846. +}
  40847. +
  40848. +static inline void
  40849. +at803x_dbg_reg_clr(struct phy_device *phydev, u16 reg, u16 clear)
  40850. +{
  40851. + at803x_dbg_reg_rmw(phydev, reg, clear, 0);
  40852. +}
  40853. +
  40854. +
  40855. /* save relevant PHY registers to private copy */
  40856. static void at803x_context_save(struct phy_device *phydev,
  40857. struct at803x_context *context)
  40858. @@ -209,8 +257,16 @@
  40859. return 0;
  40860. }
  40861. +static void at803x_disable_smarteee(struct phy_device *phydev)
  40862. +{
  40863. + phy_write_mmd(phydev, MDIO_MMD_PCS, AT803X_PCS_SMART_EEE_CTRL3,
  40864. + 1 << AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT);
  40865. + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
  40866. +}
  40867. +
  40868. static int at803x_config_init(struct phy_device *phydev)
  40869. {
  40870. + struct at803x_platform_data *pdata;
  40871. int ret;
  40872. ret = genphy_config_init(phydev);
  40873. @@ -228,6 +284,26 @@
  40874. return ret;
  40875. }
  40876. + pdata = dev_get_platdata(&phydev->dev);
  40877. + if (pdata) {
  40878. + if (pdata->disable_smarteee)
  40879. + at803x_disable_smarteee(phydev);
  40880. +
  40881. + if (pdata->enable_rgmii_rx_delay)
  40882. + at803x_dbg_reg_set(phydev, AT803X_DBG0_REG,
  40883. + AT803X_DEBUG_RGMII_RX_CLK_DLY);
  40884. + else
  40885. + at803x_dbg_reg_clr(phydev, AT803X_DBG0_REG,
  40886. + AT803X_DEBUG_RGMII_RX_CLK_DLY);
  40887. +
  40888. + if (pdata->enable_rgmii_tx_delay)
  40889. + at803x_dbg_reg_set(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL,
  40890. + AT803X_DEBUG_RGMII_TX_CLK_DLY);
  40891. + else
  40892. + at803x_dbg_reg_clr(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL,
  40893. + AT803X_DEBUG_RGMII_TX_CLK_DLY);
  40894. + }
  40895. +
  40896. return 0;
  40897. }
  40898. @@ -259,6 +335,8 @@
  40899. static void at803x_link_change_notify(struct phy_device *phydev)
  40900. {
  40901. struct at803x_priv *priv = phydev->priv;
  40902. + struct at803x_platform_data *pdata;
  40903. + pdata = dev_get_platdata(&phydev->dev);
  40904. /*
  40905. * Conduct a hardware reset for AT8030 every time a link loss is
  40906. @@ -289,6 +367,26 @@
  40907. priv->phy_reset = false;
  40908. }
  40909. }
  40910. + if (pdata && pdata->fixup_rgmii_tx_delay &&
  40911. + phydev->speed != priv->prev_speed) {
  40912. + switch (phydev->speed) {
  40913. + case SPEED_10:
  40914. + case SPEED_100:
  40915. + at803x_dbg_reg_set(phydev,
  40916. + AT803X_DEBUG_SYSTEM_MODE_CTRL,
  40917. + AT803X_DEBUG_RGMII_TX_CLK_DLY);
  40918. + break;
  40919. + case SPEED_1000:
  40920. + at803x_dbg_reg_clr(phydev,
  40921. + AT803X_DEBUG_SYSTEM_MODE_CTRL,
  40922. + AT803X_DEBUG_RGMII_TX_CLK_DLY);
  40923. + break;
  40924. + default:
  40925. + break;
  40926. + }
  40927. +
  40928. + priv->prev_speed = phydev->speed;
  40929. + }
  40930. }
  40931. static struct phy_driver at803x_driver[] = {
  40932. diff -Nur linux-4.1.43.orig/drivers/net/phy/mdio-bitbang.c linux-4.1.43/drivers/net/phy/mdio-bitbang.c
  40933. --- linux-4.1.43.orig/drivers/net/phy/mdio-bitbang.c 2017-08-06 01:56:14.000000000 +0200
  40934. +++ linux-4.1.43/drivers/net/phy/mdio-bitbang.c 2017-08-06 20:02:16.000000000 +0200
  40935. @@ -17,6 +17,7 @@
  40936. * kind, whether express or implied.
  40937. */
  40938. +#include <linux/irqflags.h>
  40939. #include <linux/module.h>
  40940. #include <linux/mdio-bitbang.h>
  40941. #include <linux/types.h>
  40942. @@ -156,7 +157,9 @@
  40943. {
  40944. struct mdiobb_ctrl *ctrl = bus->priv;
  40945. int ret, i;
  40946. + long flags;
  40947. + local_irq_save(flags);
  40948. if (reg & MII_ADDR_C45) {
  40949. reg = mdiobb_cmd_addr(ctrl, phy, reg);
  40950. mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);
  40951. @@ -165,26 +168,21 @@
  40952. ctrl->ops->set_mdio_dir(ctrl, 0);
  40953. - /* check the turnaround bit: the PHY should be driving it to zero */
  40954. - if (mdiobb_get_bit(ctrl) != 0) {
  40955. - /* PHY didn't drive TA low -- flush any bits it
  40956. - * may be trying to send.
  40957. - */
  40958. - for (i = 0; i < 32; i++)
  40959. - mdiobb_get_bit(ctrl);
  40960. -
  40961. - return 0xffff;
  40962. - }
  40963. + mdiobb_get_bit(ctrl);
  40964. ret = mdiobb_get_num(ctrl, 16);
  40965. mdiobb_get_bit(ctrl);
  40966. + local_irq_restore(flags);
  40967. +
  40968. return ret;
  40969. }
  40970. static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
  40971. {
  40972. struct mdiobb_ctrl *ctrl = bus->priv;
  40973. + long flags;
  40974. + local_irq_save(flags);
  40975. if (reg & MII_ADDR_C45) {
  40976. reg = mdiobb_cmd_addr(ctrl, phy, reg);
  40977. mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);
  40978. @@ -199,6 +197,8 @@
  40979. ctrl->ops->set_mdio_dir(ctrl, 0);
  40980. mdiobb_get_bit(ctrl);
  40981. + local_irq_restore(flags);
  40982. +
  40983. return 0;
  40984. }
  40985. diff -Nur linux-4.1.43.orig/drivers/net/phy/phy.c linux-4.1.43/drivers/net/phy/phy.c
  40986. --- linux-4.1.43.orig/drivers/net/phy/phy.c 2017-08-06 01:56:14.000000000 +0200
  40987. +++ linux-4.1.43/drivers/net/phy/phy.c 2017-08-06 20:02:16.000000000 +0200
  40988. @@ -357,6 +357,50 @@
  40989. }
  40990. EXPORT_SYMBOL(phy_ethtool_gset);
  40991. +int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr)
  40992. +{
  40993. + u32 cmd;
  40994. + int tmp;
  40995. + struct ethtool_cmd ecmd = { ETHTOOL_GSET };
  40996. + struct ethtool_value edata = { ETHTOOL_GLINK };
  40997. +
  40998. + if (get_user(cmd, (u32 *) useraddr))
  40999. + return -EFAULT;
  41000. +
  41001. + switch (cmd) {
  41002. + case ETHTOOL_GSET:
  41003. + phy_ethtool_gset(phydev, &ecmd);
  41004. + if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
  41005. + return -EFAULT;
  41006. + return 0;
  41007. +
  41008. + case ETHTOOL_SSET:
  41009. + if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
  41010. + return -EFAULT;
  41011. + return phy_ethtool_sset(phydev, &ecmd);
  41012. +
  41013. + case ETHTOOL_NWAY_RST:
  41014. + /* if autoneg is off, it's an error */
  41015. + tmp = phy_read(phydev, MII_BMCR);
  41016. + if (tmp & BMCR_ANENABLE) {
  41017. + tmp |= (BMCR_ANRESTART);
  41018. + phy_write(phydev, MII_BMCR, tmp);
  41019. + return 0;
  41020. + }
  41021. + return -EINVAL;
  41022. +
  41023. + case ETHTOOL_GLINK:
  41024. + edata.data = (phy_read(phydev,
  41025. + MII_BMSR) & BMSR_LSTATUS) ? 1 : 0;
  41026. + if (copy_to_user(useraddr, &edata, sizeof(edata)))
  41027. + return -EFAULT;
  41028. + return 0;
  41029. + }
  41030. +
  41031. + return -EOPNOTSUPP;
  41032. +}
  41033. +EXPORT_SYMBOL(phy_ethtool_ioctl);
  41034. +
  41035. /**
  41036. * phy_mii_ioctl - generic PHY MII ioctl interface
  41037. * @phydev: the phy_device struct
  41038. diff -Nur linux-4.1.43.orig/drivers/net/phy/swconfig.c linux-4.1.43/drivers/net/phy/swconfig.c
  41039. --- linux-4.1.43.orig/drivers/net/phy/swconfig.c 1970-01-01 01:00:00.000000000 +0100
  41040. +++ linux-4.1.43/drivers/net/phy/swconfig.c 2017-08-06 20:02:16.000000000 +0200
  41041. @@ -0,0 +1,1153 @@
  41042. +/*
  41043. + * swconfig.c: Switch configuration API
  41044. + *
  41045. + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
  41046. + *
  41047. + * This program is free software; you can redistribute it and/or
  41048. + * modify it under the terms of the GNU General Public License
  41049. + * as published by the Free Software Foundation; either version 2
  41050. + * of the License, or (at your option) any later version.
  41051. + *
  41052. + * This program is distributed in the hope that it will be useful,
  41053. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  41054. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  41055. + * GNU General Public License for more details.
  41056. + */
  41057. +
  41058. +#include <linux/types.h>
  41059. +#include <linux/module.h>
  41060. +#include <linux/init.h>
  41061. +#include <linux/list.h>
  41062. +#include <linux/if.h>
  41063. +#include <linux/if_ether.h>
  41064. +#include <linux/capability.h>
  41065. +#include <linux/skbuff.h>
  41066. +#include <linux/switch.h>
  41067. +#include <linux/of.h>
  41068. +#include <linux/version.h>
  41069. +
  41070. +#define SWCONFIG_DEVNAME "switch%d"
  41071. +
  41072. +#include "swconfig_leds.c"
  41073. +
  41074. +MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
  41075. +MODULE_LICENSE("GPL");
  41076. +
  41077. +static int swdev_id;
  41078. +static struct list_head swdevs;
  41079. +static DEFINE_SPINLOCK(swdevs_lock);
  41080. +struct swconfig_callback;
  41081. +
  41082. +struct swconfig_callback {
  41083. + struct sk_buff *msg;
  41084. + struct genlmsghdr *hdr;
  41085. + struct genl_info *info;
  41086. + int cmd;
  41087. +
  41088. + /* callback for filling in the message data */
  41089. + int (*fill)(struct swconfig_callback *cb, void *arg);
  41090. +
  41091. + /* callback for closing the message before sending it */
  41092. + int (*close)(struct swconfig_callback *cb, void *arg);
  41093. +
  41094. + struct nlattr *nest[4];
  41095. + int args[4];
  41096. +};
  41097. +
  41098. +/* defaults */
  41099. +
  41100. +static int
  41101. +swconfig_get_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr,
  41102. + struct switch_val *val)
  41103. +{
  41104. + int ret;
  41105. + if (val->port_vlan >= dev->vlans)
  41106. + return -EINVAL;
  41107. +
  41108. + if (!dev->ops->get_vlan_ports)
  41109. + return -EOPNOTSUPP;
  41110. +
  41111. + ret = dev->ops->get_vlan_ports(dev, val);
  41112. + return ret;
  41113. +}
  41114. +
  41115. +static int
  41116. +swconfig_set_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr,
  41117. + struct switch_val *val)
  41118. +{
  41119. + struct switch_port *ports = val->value.ports;
  41120. + const struct switch_dev_ops *ops = dev->ops;
  41121. + int i;
  41122. +
  41123. + if (val->port_vlan >= dev->vlans)
  41124. + return -EINVAL;
  41125. +
  41126. + /* validate ports */
  41127. + if (val->len > dev->ports)
  41128. + return -EINVAL;
  41129. +
  41130. + if (!ops->set_vlan_ports)
  41131. + return -EOPNOTSUPP;
  41132. +
  41133. + for (i = 0; i < val->len; i++) {
  41134. + if (ports[i].id >= dev->ports)
  41135. + return -EINVAL;
  41136. +
  41137. + if (ops->set_port_pvid &&
  41138. + !(ports[i].flags & (1 << SWITCH_PORT_FLAG_TAGGED)))
  41139. + ops->set_port_pvid(dev, ports[i].id, val->port_vlan);
  41140. + }
  41141. +
  41142. + return ops->set_vlan_ports(dev, val);
  41143. +}
  41144. +
  41145. +static int
  41146. +swconfig_set_pvid(struct switch_dev *dev, const struct switch_attr *attr,
  41147. + struct switch_val *val)
  41148. +{
  41149. + if (val->port_vlan >= dev->ports)
  41150. + return -EINVAL;
  41151. +
  41152. + if (!dev->ops->set_port_pvid)
  41153. + return -EOPNOTSUPP;
  41154. +
  41155. + return dev->ops->set_port_pvid(dev, val->port_vlan, val->value.i);
  41156. +}
  41157. +
  41158. +static int
  41159. +swconfig_get_pvid(struct switch_dev *dev, const struct switch_attr *attr,
  41160. + struct switch_val *val)
  41161. +{
  41162. + if (val->port_vlan >= dev->ports)
  41163. + return -EINVAL;
  41164. +
  41165. + if (!dev->ops->get_port_pvid)
  41166. + return -EOPNOTSUPP;
  41167. +
  41168. + return dev->ops->get_port_pvid(dev, val->port_vlan, &val->value.i);
  41169. +}
  41170. +
  41171. +static const char *
  41172. +swconfig_speed_str(enum switch_port_speed speed)
  41173. +{
  41174. + switch (speed) {
  41175. + case SWITCH_PORT_SPEED_10:
  41176. + return "10baseT";
  41177. + case SWITCH_PORT_SPEED_100:
  41178. + return "100baseT";
  41179. + case SWITCH_PORT_SPEED_1000:
  41180. + return "1000baseT";
  41181. + default:
  41182. + break;
  41183. + }
  41184. +
  41185. + return "unknown";
  41186. +}
  41187. +
  41188. +static int
  41189. +swconfig_get_link(struct switch_dev *dev, const struct switch_attr *attr,
  41190. + struct switch_val *val)
  41191. +{
  41192. + struct switch_port_link link;
  41193. + int len;
  41194. + int ret;
  41195. +
  41196. + if (val->port_vlan >= dev->ports)
  41197. + return -EINVAL;
  41198. +
  41199. + if (!dev->ops->get_port_link)
  41200. + return -EOPNOTSUPP;
  41201. +
  41202. + memset(&link, 0, sizeof(link));
  41203. + ret = dev->ops->get_port_link(dev, val->port_vlan, &link);
  41204. + if (ret)
  41205. + return ret;
  41206. +
  41207. + memset(dev->buf, 0, sizeof(dev->buf));
  41208. +
  41209. + if (link.link)
  41210. + len = snprintf(dev->buf, sizeof(dev->buf),
  41211. + "port:%d link:up speed:%s %s-duplex %s%s%s%s%s",
  41212. + val->port_vlan,
  41213. + swconfig_speed_str(link.speed),
  41214. + link.duplex ? "full" : "half",
  41215. + link.tx_flow ? "txflow " : "",
  41216. + link.rx_flow ? "rxflow " : "",
  41217. + link.eee & ADVERTISED_100baseT_Full ? "eee100 " : "",
  41218. + link.eee & ADVERTISED_1000baseT_Full ? "eee1000 " : "",
  41219. + link.aneg ? "auto" : "");
  41220. + else
  41221. + len = snprintf(dev->buf, sizeof(dev->buf), "port:%d link:down",
  41222. + val->port_vlan);
  41223. +
  41224. + val->value.s = dev->buf;
  41225. + val->len = len;
  41226. +
  41227. + return 0;
  41228. +}
  41229. +
  41230. +static int
  41231. +swconfig_apply_config(struct switch_dev *dev, const struct switch_attr *attr,
  41232. + struct switch_val *val)
  41233. +{
  41234. + /* don't complain if not supported by the switch driver */
  41235. + if (!dev->ops->apply_config)
  41236. + return 0;
  41237. +
  41238. + return dev->ops->apply_config(dev);
  41239. +}
  41240. +
  41241. +static int
  41242. +swconfig_reset_switch(struct switch_dev *dev, const struct switch_attr *attr,
  41243. + struct switch_val *val)
  41244. +{
  41245. + /* don't complain if not supported by the switch driver */
  41246. + if (!dev->ops->reset_switch)
  41247. + return 0;
  41248. +
  41249. + return dev->ops->reset_switch(dev);
  41250. +}
  41251. +
  41252. +enum global_defaults {
  41253. + GLOBAL_APPLY,
  41254. + GLOBAL_RESET,
  41255. +};
  41256. +
  41257. +enum vlan_defaults {
  41258. + VLAN_PORTS,
  41259. +};
  41260. +
  41261. +enum port_defaults {
  41262. + PORT_PVID,
  41263. + PORT_LINK,
  41264. +};
  41265. +
  41266. +static struct switch_attr default_global[] = {
  41267. + [GLOBAL_APPLY] = {
  41268. + .type = SWITCH_TYPE_NOVAL,
  41269. + .name = "apply",
  41270. + .description = "Activate changes in the hardware",
  41271. + .set = swconfig_apply_config,
  41272. + },
  41273. + [GLOBAL_RESET] = {
  41274. + .type = SWITCH_TYPE_NOVAL,
  41275. + .name = "reset",
  41276. + .description = "Reset the switch",
  41277. + .set = swconfig_reset_switch,
  41278. + }
  41279. +};
  41280. +
  41281. +static struct switch_attr default_port[] = {
  41282. + [PORT_PVID] = {
  41283. + .type = SWITCH_TYPE_INT,
  41284. + .name = "pvid",
  41285. + .description = "Primary VLAN ID",
  41286. + .set = swconfig_set_pvid,
  41287. + .get = swconfig_get_pvid,
  41288. + },
  41289. + [PORT_LINK] = {
  41290. + .type = SWITCH_TYPE_STRING,
  41291. + .name = "link",
  41292. + .description = "Get port link information",
  41293. + .set = NULL,
  41294. + .get = swconfig_get_link,
  41295. + }
  41296. +};
  41297. +
  41298. +static struct switch_attr default_vlan[] = {
  41299. + [VLAN_PORTS] = {
  41300. + .type = SWITCH_TYPE_PORTS,
  41301. + .name = "ports",
  41302. + .description = "VLAN port mapping",
  41303. + .set = swconfig_set_vlan_ports,
  41304. + .get = swconfig_get_vlan_ports,
  41305. + },
  41306. +};
  41307. +
  41308. +static const struct switch_attr *
  41309. +swconfig_find_attr_by_name(const struct switch_attrlist *alist,
  41310. + const char *name)
  41311. +{
  41312. + int i;
  41313. +
  41314. + for (i = 0; i < alist->n_attr; i++)
  41315. + if (strcmp(name, alist->attr[i].name) == 0)
  41316. + return &alist->attr[i];
  41317. +
  41318. + return NULL;
  41319. +}
  41320. +
  41321. +static void swconfig_defaults_init(struct switch_dev *dev)
  41322. +{
  41323. + const struct switch_dev_ops *ops = dev->ops;
  41324. +
  41325. + dev->def_global = 0;
  41326. + dev->def_vlan = 0;
  41327. + dev->def_port = 0;
  41328. +
  41329. + if (ops->get_vlan_ports || ops->set_vlan_ports)
  41330. + set_bit(VLAN_PORTS, &dev->def_vlan);
  41331. +
  41332. + if (ops->get_port_pvid || ops->set_port_pvid)
  41333. + set_bit(PORT_PVID, &dev->def_port);
  41334. +
  41335. + if (ops->get_port_link &&
  41336. + !swconfig_find_attr_by_name(&ops->attr_port, "link"))
  41337. + set_bit(PORT_LINK, &dev->def_port);
  41338. +
  41339. + /* always present, can be no-op */
  41340. + set_bit(GLOBAL_APPLY, &dev->def_global);
  41341. + set_bit(GLOBAL_RESET, &dev->def_global);
  41342. +}
  41343. +
  41344. +
  41345. +static struct genl_family switch_fam = {
  41346. + .id = GENL_ID_GENERATE,
  41347. + .name = "switch",
  41348. + .hdrsize = 0,
  41349. + .version = 1,
  41350. + .maxattr = SWITCH_ATTR_MAX,
  41351. +};
  41352. +
  41353. +static const struct nla_policy switch_policy[SWITCH_ATTR_MAX+1] = {
  41354. + [SWITCH_ATTR_ID] = { .type = NLA_U32 },
  41355. + [SWITCH_ATTR_OP_ID] = { .type = NLA_U32 },
  41356. + [SWITCH_ATTR_OP_PORT] = { .type = NLA_U32 },
  41357. + [SWITCH_ATTR_OP_VLAN] = { .type = NLA_U32 },
  41358. + [SWITCH_ATTR_OP_VALUE_INT] = { .type = NLA_U32 },
  41359. + [SWITCH_ATTR_OP_VALUE_STR] = { .type = NLA_NUL_STRING },
  41360. + [SWITCH_ATTR_OP_VALUE_PORTS] = { .type = NLA_NESTED },
  41361. + [SWITCH_ATTR_TYPE] = { .type = NLA_U32 },
  41362. +};
  41363. +
  41364. +static const struct nla_policy port_policy[SWITCH_PORT_ATTR_MAX+1] = {
  41365. + [SWITCH_PORT_ID] = { .type = NLA_U32 },
  41366. + [SWITCH_PORT_FLAG_TAGGED] = { .type = NLA_FLAG },
  41367. +};
  41368. +
  41369. +static inline void
  41370. +swconfig_lock(void)
  41371. +{
  41372. + spin_lock(&swdevs_lock);
  41373. +}
  41374. +
  41375. +static inline void
  41376. +swconfig_unlock(void)
  41377. +{
  41378. + spin_unlock(&swdevs_lock);
  41379. +}
  41380. +
  41381. +static struct switch_dev *
  41382. +swconfig_get_dev(struct genl_info *info)
  41383. +{
  41384. + struct switch_dev *dev = NULL;
  41385. + struct switch_dev *p;
  41386. + int id;
  41387. +
  41388. + if (!info->attrs[SWITCH_ATTR_ID])
  41389. + goto done;
  41390. +
  41391. + id = nla_get_u32(info->attrs[SWITCH_ATTR_ID]);
  41392. + swconfig_lock();
  41393. + list_for_each_entry(p, &swdevs, dev_list) {
  41394. + if (id != p->id)
  41395. + continue;
  41396. +
  41397. + dev = p;
  41398. + break;
  41399. + }
  41400. + if (dev)
  41401. + mutex_lock(&dev->sw_mutex);
  41402. + else
  41403. + pr_debug("device %d not found\n", id);
  41404. + swconfig_unlock();
  41405. +done:
  41406. + return dev;
  41407. +}
  41408. +
  41409. +static inline void
  41410. +swconfig_put_dev(struct switch_dev *dev)
  41411. +{
  41412. + mutex_unlock(&dev->sw_mutex);
  41413. +}
  41414. +
  41415. +static int
  41416. +swconfig_dump_attr(struct swconfig_callback *cb, void *arg)
  41417. +{
  41418. + struct switch_attr *op = arg;
  41419. + struct genl_info *info = cb->info;
  41420. + struct sk_buff *msg = cb->msg;
  41421. + int id = cb->args[0];
  41422. + void *hdr;
  41423. +
  41424. + hdr = genlmsg_put(msg, info->snd_portid, info->snd_seq, &switch_fam,
  41425. + NLM_F_MULTI, SWITCH_CMD_NEW_ATTR);
  41426. + if (IS_ERR(hdr))
  41427. + return -1;
  41428. +
  41429. + if (nla_put_u32(msg, SWITCH_ATTR_OP_ID, id))
  41430. + goto nla_put_failure;
  41431. + if (nla_put_u32(msg, SWITCH_ATTR_OP_TYPE, op->type))
  41432. + goto nla_put_failure;
  41433. + if (nla_put_string(msg, SWITCH_ATTR_OP_NAME, op->name))
  41434. + goto nla_put_failure;
  41435. + if (op->description)
  41436. + if (nla_put_string(msg, SWITCH_ATTR_OP_DESCRIPTION,
  41437. + op->description))
  41438. + goto nla_put_failure;
  41439. +
  41440. + genlmsg_end(msg, hdr);
  41441. + return msg->len;
  41442. +nla_put_failure:
  41443. + genlmsg_cancel(msg, hdr);
  41444. + return -EMSGSIZE;
  41445. +}
  41446. +
  41447. +/* spread multipart messages across multiple message buffers */
  41448. +static int
  41449. +swconfig_send_multipart(struct swconfig_callback *cb, void *arg)
  41450. +{
  41451. + struct genl_info *info = cb->info;
  41452. + int restart = 0;
  41453. + int err;
  41454. +
  41455. + do {
  41456. + if (!cb->msg) {
  41457. + cb->msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);
  41458. + if (cb->msg == NULL)
  41459. + goto error;
  41460. + }
  41461. +
  41462. + if (!(cb->fill(cb, arg) < 0))
  41463. + break;
  41464. +
  41465. + /* fill failed, check if this was already the second attempt */
  41466. + if (restart)
  41467. + goto error;
  41468. +
  41469. + /* try again in a new message, send the current one */
  41470. + restart = 1;
  41471. + if (cb->close) {
  41472. + if (cb->close(cb, arg) < 0)
  41473. + goto error;
  41474. + }
  41475. + err = genlmsg_reply(cb->msg, info);
  41476. + cb->msg = NULL;
  41477. + if (err < 0)
  41478. + goto error;
  41479. +
  41480. + } while (restart);
  41481. +
  41482. + return 0;
  41483. +
  41484. +error:
  41485. + if (cb->msg)
  41486. + nlmsg_free(cb->msg);
  41487. + return -1;
  41488. +}
  41489. +
  41490. +static int
  41491. +swconfig_list_attrs(struct sk_buff *skb, struct genl_info *info)
  41492. +{
  41493. + struct genlmsghdr *hdr = nlmsg_data(info->nlhdr);
  41494. + const struct switch_attrlist *alist;
  41495. + struct switch_dev *dev;
  41496. + struct swconfig_callback cb;
  41497. + int err = -EINVAL;
  41498. + int i;
  41499. +
  41500. + /* defaults */
  41501. + struct switch_attr *def_list;
  41502. + unsigned long *def_active;
  41503. + int n_def;
  41504. +
  41505. + dev = swconfig_get_dev(info);
  41506. + if (!dev)
  41507. + return -EINVAL;
  41508. +
  41509. + switch (hdr->cmd) {
  41510. + case SWITCH_CMD_LIST_GLOBAL:
  41511. + alist = &dev->ops->attr_global;
  41512. + def_list = default_global;
  41513. + def_active = &dev->def_global;
  41514. + n_def = ARRAY_SIZE(default_global);
  41515. + break;
  41516. + case SWITCH_CMD_LIST_VLAN:
  41517. + alist = &dev->ops->attr_vlan;
  41518. + def_list = default_vlan;
  41519. + def_active = &dev->def_vlan;
  41520. + n_def = ARRAY_SIZE(default_vlan);
  41521. + break;
  41522. + case SWITCH_CMD_LIST_PORT:
  41523. + alist = &dev->ops->attr_port;
  41524. + def_list = default_port;
  41525. + def_active = &dev->def_port;
  41526. + n_def = ARRAY_SIZE(default_port);
  41527. + break;
  41528. + default:
  41529. + WARN_ON(1);
  41530. + goto out;
  41531. + }
  41532. +
  41533. + memset(&cb, 0, sizeof(cb));
  41534. + cb.info = info;
  41535. + cb.fill = swconfig_dump_attr;
  41536. + for (i = 0; i < alist->n_attr; i++) {
  41537. + if (alist->attr[i].disabled)
  41538. + continue;
  41539. + cb.args[0] = i;
  41540. + err = swconfig_send_multipart(&cb, (void *) &alist->attr[i]);
  41541. + if (err < 0)
  41542. + goto error;
  41543. + }
  41544. +
  41545. + /* defaults */
  41546. + for (i = 0; i < n_def; i++) {
  41547. + if (!test_bit(i, def_active))
  41548. + continue;
  41549. + cb.args[0] = SWITCH_ATTR_DEFAULTS_OFFSET + i;
  41550. + err = swconfig_send_multipart(&cb, (void *) &def_list[i]);
  41551. + if (err < 0)
  41552. + goto error;
  41553. + }
  41554. + swconfig_put_dev(dev);
  41555. +
  41556. + if (!cb.msg)
  41557. + return 0;
  41558. +
  41559. + return genlmsg_reply(cb.msg, info);
  41560. +
  41561. +error:
  41562. + if (cb.msg)
  41563. + nlmsg_free(cb.msg);
  41564. +out:
  41565. + swconfig_put_dev(dev);
  41566. + return err;
  41567. +}
  41568. +
  41569. +static const struct switch_attr *
  41570. +swconfig_lookup_attr(struct switch_dev *dev, struct genl_info *info,
  41571. + struct switch_val *val)
  41572. +{
  41573. + struct genlmsghdr *hdr = nlmsg_data(info->nlhdr);
  41574. + const struct switch_attrlist *alist;
  41575. + const struct switch_attr *attr = NULL;
  41576. + int attr_id;
  41577. +
  41578. + /* defaults */
  41579. + struct switch_attr *def_list;
  41580. + unsigned long *def_active;
  41581. + int n_def;
  41582. +
  41583. + if (!info->attrs[SWITCH_ATTR_OP_ID])
  41584. + goto done;
  41585. +
  41586. + switch (hdr->cmd) {
  41587. + case SWITCH_CMD_SET_GLOBAL:
  41588. + case SWITCH_CMD_GET_GLOBAL:
  41589. + alist = &dev->ops->attr_global;
  41590. + def_list = default_global;
  41591. + def_active = &dev->def_global;
  41592. + n_def = ARRAY_SIZE(default_global);
  41593. + break;
  41594. + case SWITCH_CMD_SET_VLAN:
  41595. + case SWITCH_CMD_GET_VLAN:
  41596. + alist = &dev->ops->attr_vlan;
  41597. + def_list = default_vlan;
  41598. + def_active = &dev->def_vlan;
  41599. + n_def = ARRAY_SIZE(default_vlan);
  41600. + if (!info->attrs[SWITCH_ATTR_OP_VLAN])
  41601. + goto done;
  41602. + val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_VLAN]);
  41603. + if (val->port_vlan >= dev->vlans)
  41604. + goto done;
  41605. + break;
  41606. + case SWITCH_CMD_SET_PORT:
  41607. + case SWITCH_CMD_GET_PORT:
  41608. + alist = &dev->ops->attr_port;
  41609. + def_list = default_port;
  41610. + def_active = &dev->def_port;
  41611. + n_def = ARRAY_SIZE(default_port);
  41612. + if (!info->attrs[SWITCH_ATTR_OP_PORT])
  41613. + goto done;
  41614. + val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_PORT]);
  41615. + if (val->port_vlan >= dev->ports)
  41616. + goto done;
  41617. + break;
  41618. + default:
  41619. + WARN_ON(1);
  41620. + goto done;
  41621. + }
  41622. +
  41623. + if (!alist)
  41624. + goto done;
  41625. +
  41626. + attr_id = nla_get_u32(info->attrs[SWITCH_ATTR_OP_ID]);
  41627. + if (attr_id >= SWITCH_ATTR_DEFAULTS_OFFSET) {
  41628. + attr_id -= SWITCH_ATTR_DEFAULTS_OFFSET;
  41629. + if (attr_id >= n_def)
  41630. + goto done;
  41631. + if (!test_bit(attr_id, def_active))
  41632. + goto done;
  41633. + attr = &def_list[attr_id];
  41634. + } else {
  41635. + if (attr_id >= alist->n_attr)
  41636. + goto done;
  41637. + attr = &alist->attr[attr_id];
  41638. + }
  41639. +
  41640. + if (attr->disabled)
  41641. + attr = NULL;
  41642. +
  41643. +done:
  41644. + if (!attr)
  41645. + pr_debug("attribute lookup failed\n");
  41646. + val->attr = attr;
  41647. + return attr;
  41648. +}
  41649. +
  41650. +static int
  41651. +swconfig_parse_ports(struct sk_buff *msg, struct nlattr *head,
  41652. + struct switch_val *val, int max)
  41653. +{
  41654. + struct nlattr *nla;
  41655. + int rem;
  41656. +
  41657. + val->len = 0;
  41658. + nla_for_each_nested(nla, head, rem) {
  41659. + struct nlattr *tb[SWITCH_PORT_ATTR_MAX+1];
  41660. + struct switch_port *port = &val->value.ports[val->len];
  41661. +
  41662. + if (val->len >= max)
  41663. + return -EINVAL;
  41664. +
  41665. + if (nla_parse_nested(tb, SWITCH_PORT_ATTR_MAX, nla,
  41666. + port_policy))
  41667. + return -EINVAL;
  41668. +
  41669. + if (!tb[SWITCH_PORT_ID])
  41670. + return -EINVAL;
  41671. +
  41672. + port->id = nla_get_u32(tb[SWITCH_PORT_ID]);
  41673. + if (tb[SWITCH_PORT_FLAG_TAGGED])
  41674. + port->flags |= (1 << SWITCH_PORT_FLAG_TAGGED);
  41675. + val->len++;
  41676. + }
  41677. +
  41678. + return 0;
  41679. +}
  41680. +
  41681. +static int
  41682. +swconfig_set_attr(struct sk_buff *skb, struct genl_info *info)
  41683. +{
  41684. + const struct switch_attr *attr;
  41685. + struct switch_dev *dev;
  41686. + struct switch_val val;
  41687. + int err = -EINVAL;
  41688. +
  41689. + dev = swconfig_get_dev(info);
  41690. + if (!dev)
  41691. + return -EINVAL;
  41692. +
  41693. + memset(&val, 0, sizeof(val));
  41694. + attr = swconfig_lookup_attr(dev, info, &val);
  41695. + if (!attr || !attr->set)
  41696. + goto error;
  41697. +
  41698. + val.attr = attr;
  41699. + switch (attr->type) {
  41700. + case SWITCH_TYPE_NOVAL:
  41701. + break;
  41702. + case SWITCH_TYPE_INT:
  41703. + if (!info->attrs[SWITCH_ATTR_OP_VALUE_INT])
  41704. + goto error;
  41705. + val.value.i =
  41706. + nla_get_u32(info->attrs[SWITCH_ATTR_OP_VALUE_INT]);
  41707. + break;
  41708. + case SWITCH_TYPE_STRING:
  41709. + if (!info->attrs[SWITCH_ATTR_OP_VALUE_STR])
  41710. + goto error;
  41711. + val.value.s =
  41712. + nla_data(info->attrs[SWITCH_ATTR_OP_VALUE_STR]);
  41713. + break;
  41714. + case SWITCH_TYPE_PORTS:
  41715. + val.value.ports = dev->portbuf;
  41716. + memset(dev->portbuf, 0,
  41717. + sizeof(struct switch_port) * dev->ports);
  41718. +
  41719. + /* TODO: implement multipart? */
  41720. + if (info->attrs[SWITCH_ATTR_OP_VALUE_PORTS]) {
  41721. + err = swconfig_parse_ports(skb,
  41722. + info->attrs[SWITCH_ATTR_OP_VALUE_PORTS],
  41723. + &val, dev->ports);
  41724. + if (err < 0)
  41725. + goto error;
  41726. + } else {
  41727. + val.len = 0;
  41728. + err = 0;
  41729. + }
  41730. + break;
  41731. + default:
  41732. + goto error;
  41733. + }
  41734. +
  41735. + err = attr->set(dev, attr, &val);
  41736. +error:
  41737. + swconfig_put_dev(dev);
  41738. + return err;
  41739. +}
  41740. +
  41741. +static int
  41742. +swconfig_close_portlist(struct swconfig_callback *cb, void *arg)
  41743. +{
  41744. + if (cb->nest[0])
  41745. + nla_nest_end(cb->msg, cb->nest[0]);
  41746. + return 0;
  41747. +}
  41748. +
  41749. +static int
  41750. +swconfig_send_port(struct swconfig_callback *cb, void *arg)
  41751. +{
  41752. + const struct switch_port *port = arg;
  41753. + struct nlattr *p = NULL;
  41754. +
  41755. + if (!cb->nest[0]) {
  41756. + cb->nest[0] = nla_nest_start(cb->msg, cb->cmd);
  41757. + if (!cb->nest[0])
  41758. + return -1;
  41759. + }
  41760. +
  41761. + p = nla_nest_start(cb->msg, SWITCH_ATTR_PORT);
  41762. + if (!p)
  41763. + goto error;
  41764. +
  41765. + if (nla_put_u32(cb->msg, SWITCH_PORT_ID, port->id))
  41766. + goto nla_put_failure;
  41767. + if (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
  41768. + if (nla_put_flag(cb->msg, SWITCH_PORT_FLAG_TAGGED))
  41769. + goto nla_put_failure;
  41770. + }
  41771. +
  41772. + nla_nest_end(cb->msg, p);
  41773. + return 0;
  41774. +
  41775. +nla_put_failure:
  41776. + nla_nest_cancel(cb->msg, p);
  41777. +error:
  41778. + nla_nest_cancel(cb->msg, cb->nest[0]);
  41779. + return -1;
  41780. +}
  41781. +
  41782. +static int
  41783. +swconfig_send_ports(struct sk_buff **msg, struct genl_info *info, int attr,
  41784. + const struct switch_val *val)
  41785. +{
  41786. + struct swconfig_callback cb;
  41787. + int err = 0;
  41788. + int i;
  41789. +
  41790. + if (!val->value.ports)
  41791. + return -EINVAL;
  41792. +
  41793. + memset(&cb, 0, sizeof(cb));
  41794. + cb.cmd = attr;
  41795. + cb.msg = *msg;
  41796. + cb.info = info;
  41797. + cb.fill = swconfig_send_port;
  41798. + cb.close = swconfig_close_portlist;
  41799. +
  41800. + cb.nest[0] = nla_nest_start(cb.msg, cb.cmd);
  41801. + for (i = 0; i < val->len; i++) {
  41802. + err = swconfig_send_multipart(&cb, &val->value.ports[i]);
  41803. + if (err)
  41804. + goto done;
  41805. + }
  41806. + err = val->len;
  41807. + swconfig_close_portlist(&cb, NULL);
  41808. + *msg = cb.msg;
  41809. +
  41810. +done:
  41811. + return err;
  41812. +}
  41813. +
  41814. +static int
  41815. +swconfig_get_attr(struct sk_buff *skb, struct genl_info *info)
  41816. +{
  41817. + struct genlmsghdr *hdr = nlmsg_data(info->nlhdr);
  41818. + const struct switch_attr *attr;
  41819. + struct switch_dev *dev;
  41820. + struct sk_buff *msg = NULL;
  41821. + struct switch_val val;
  41822. + int err = -EINVAL;
  41823. + int cmd = hdr->cmd;
  41824. +
  41825. + dev = swconfig_get_dev(info);
  41826. + if (!dev)
  41827. + return -EINVAL;
  41828. +
  41829. + memset(&val, 0, sizeof(val));
  41830. + attr = swconfig_lookup_attr(dev, info, &val);
  41831. + if (!attr || !attr->get)
  41832. + goto error;
  41833. +
  41834. + if (attr->type == SWITCH_TYPE_PORTS) {
  41835. + val.value.ports = dev->portbuf;
  41836. + memset(dev->portbuf, 0,
  41837. + sizeof(struct switch_port) * dev->ports);
  41838. + }
  41839. +
  41840. + err = attr->get(dev, attr, &val);
  41841. + if (err)
  41842. + goto error;
  41843. +
  41844. + msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);
  41845. + if (!msg)
  41846. + goto error;
  41847. +
  41848. + hdr = genlmsg_put(msg, info->snd_portid, info->snd_seq, &switch_fam,
  41849. + 0, cmd);
  41850. + if (IS_ERR(hdr))
  41851. + goto nla_put_failure;
  41852. +
  41853. + switch (attr->type) {
  41854. + case SWITCH_TYPE_INT:
  41855. + if (nla_put_u32(msg, SWITCH_ATTR_OP_VALUE_INT, val.value.i))
  41856. + goto nla_put_failure;
  41857. + break;
  41858. + case SWITCH_TYPE_STRING:
  41859. + if (nla_put_string(msg, SWITCH_ATTR_OP_VALUE_STR, val.value.s))
  41860. + goto nla_put_failure;
  41861. + break;
  41862. + case SWITCH_TYPE_PORTS:
  41863. + err = swconfig_send_ports(&msg, info,
  41864. + SWITCH_ATTR_OP_VALUE_PORTS, &val);
  41865. + if (err < 0)
  41866. + goto nla_put_failure;
  41867. + break;
  41868. + default:
  41869. + pr_debug("invalid type in attribute\n");
  41870. + err = -EINVAL;
  41871. + goto error;
  41872. + }
  41873. + genlmsg_end(msg, hdr);
  41874. + err = msg->len;
  41875. + if (err < 0)
  41876. + goto nla_put_failure;
  41877. +
  41878. + swconfig_put_dev(dev);
  41879. + return genlmsg_reply(msg, info);
  41880. +
  41881. +nla_put_failure:
  41882. + if (msg)
  41883. + nlmsg_free(msg);
  41884. +error:
  41885. + swconfig_put_dev(dev);
  41886. + if (!err)
  41887. + err = -ENOMEM;
  41888. + return err;
  41889. +}
  41890. +
  41891. +static int
  41892. +swconfig_send_switch(struct sk_buff *msg, u32 pid, u32 seq, int flags,
  41893. + const struct switch_dev *dev)
  41894. +{
  41895. + struct nlattr *p = NULL, *m = NULL;
  41896. + void *hdr;
  41897. + int i;
  41898. +
  41899. + hdr = genlmsg_put(msg, pid, seq, &switch_fam, flags,
  41900. + SWITCH_CMD_NEW_ATTR);
  41901. + if (IS_ERR(hdr))
  41902. + return -1;
  41903. +
  41904. + if (nla_put_u32(msg, SWITCH_ATTR_ID, dev->id))
  41905. + goto nla_put_failure;
  41906. + if (nla_put_string(msg, SWITCH_ATTR_DEV_NAME, dev->devname))
  41907. + goto nla_put_failure;
  41908. + if (nla_put_string(msg, SWITCH_ATTR_ALIAS, dev->alias))
  41909. + goto nla_put_failure;
  41910. + if (nla_put_string(msg, SWITCH_ATTR_NAME, dev->name))
  41911. + goto nla_put_failure;
  41912. + if (nla_put_u32(msg, SWITCH_ATTR_VLANS, dev->vlans))
  41913. + goto nla_put_failure;
  41914. + if (nla_put_u32(msg, SWITCH_ATTR_PORTS, dev->ports))
  41915. + goto nla_put_failure;
  41916. + if (nla_put_u32(msg, SWITCH_ATTR_CPU_PORT, dev->cpu_port))
  41917. + goto nla_put_failure;
  41918. +
  41919. + m = nla_nest_start(msg, SWITCH_ATTR_PORTMAP);
  41920. + if (!m)
  41921. + goto nla_put_failure;
  41922. + for (i = 0; i < dev->ports; i++) {
  41923. + p = nla_nest_start(msg, SWITCH_ATTR_PORTS);
  41924. + if (!p)
  41925. + continue;
  41926. + if (dev->portmap[i].s) {
  41927. + if (nla_put_string(msg, SWITCH_PORTMAP_SEGMENT,
  41928. + dev->portmap[i].s))
  41929. + goto nla_put_failure;
  41930. + if (nla_put_u32(msg, SWITCH_PORTMAP_VIRT,
  41931. + dev->portmap[i].virt))
  41932. + goto nla_put_failure;
  41933. + }
  41934. + nla_nest_end(msg, p);
  41935. + }
  41936. + nla_nest_end(msg, m);
  41937. + genlmsg_end(msg, hdr);
  41938. + return msg->len;
  41939. +nla_put_failure:
  41940. + genlmsg_cancel(msg, hdr);
  41941. + return -EMSGSIZE;
  41942. +}
  41943. +
  41944. +static int swconfig_dump_switches(struct sk_buff *skb,
  41945. + struct netlink_callback *cb)
  41946. +{
  41947. + struct switch_dev *dev;
  41948. + int start = cb->args[0];
  41949. + int idx = 0;
  41950. +
  41951. + swconfig_lock();
  41952. + list_for_each_entry(dev, &swdevs, dev_list) {
  41953. + if (++idx <= start)
  41954. + continue;
  41955. + if (swconfig_send_switch(skb, NETLINK_CB(cb->skb).portid,
  41956. + cb->nlh->nlmsg_seq, NLM_F_MULTI,
  41957. + dev) < 0)
  41958. + break;
  41959. + }
  41960. + swconfig_unlock();
  41961. + cb->args[0] = idx;
  41962. +
  41963. + return skb->len;
  41964. +}
  41965. +
  41966. +static int
  41967. +swconfig_done(struct netlink_callback *cb)
  41968. +{
  41969. + return 0;
  41970. +}
  41971. +
  41972. +static struct genl_ops swconfig_ops[] = {
  41973. + {
  41974. + .cmd = SWITCH_CMD_LIST_GLOBAL,
  41975. + .doit = swconfig_list_attrs,
  41976. + .policy = switch_policy,
  41977. + },
  41978. + {
  41979. + .cmd = SWITCH_CMD_LIST_VLAN,
  41980. + .doit = swconfig_list_attrs,
  41981. + .policy = switch_policy,
  41982. + },
  41983. + {
  41984. + .cmd = SWITCH_CMD_LIST_PORT,
  41985. + .doit = swconfig_list_attrs,
  41986. + .policy = switch_policy,
  41987. + },
  41988. + {
  41989. + .cmd = SWITCH_CMD_GET_GLOBAL,
  41990. + .doit = swconfig_get_attr,
  41991. + .policy = switch_policy,
  41992. + },
  41993. + {
  41994. + .cmd = SWITCH_CMD_GET_VLAN,
  41995. + .doit = swconfig_get_attr,
  41996. + .policy = switch_policy,
  41997. + },
  41998. + {
  41999. + .cmd = SWITCH_CMD_GET_PORT,
  42000. + .doit = swconfig_get_attr,
  42001. + .policy = switch_policy,
  42002. + },
  42003. + {
  42004. + .cmd = SWITCH_CMD_SET_GLOBAL,
  42005. + .doit = swconfig_set_attr,
  42006. + .policy = switch_policy,
  42007. + },
  42008. + {
  42009. + .cmd = SWITCH_CMD_SET_VLAN,
  42010. + .doit = swconfig_set_attr,
  42011. + .policy = switch_policy,
  42012. + },
  42013. + {
  42014. + .cmd = SWITCH_CMD_SET_PORT,
  42015. + .doit = swconfig_set_attr,
  42016. + .policy = switch_policy,
  42017. + },
  42018. + {
  42019. + .cmd = SWITCH_CMD_GET_SWITCH,
  42020. + .dumpit = swconfig_dump_switches,
  42021. + .policy = switch_policy,
  42022. + .done = swconfig_done,
  42023. + }
  42024. +};
  42025. +
  42026. +#ifdef CONFIG_OF
  42027. +void
  42028. +of_switch_load_portmap(struct switch_dev *dev)
  42029. +{
  42030. + struct device_node *port;
  42031. +
  42032. + if (!dev->of_node)
  42033. + return;
  42034. +
  42035. + for_each_child_of_node(dev->of_node, port) {
  42036. + const __be32 *prop;
  42037. + const char *segment;
  42038. + int size, phys;
  42039. +
  42040. + if (!of_device_is_compatible(port, "swconfig,port"))
  42041. + continue;
  42042. +
  42043. + if (of_property_read_string(port, "swconfig,segment", &segment))
  42044. + continue;
  42045. +
  42046. + prop = of_get_property(port, "swconfig,portmap", &size);
  42047. + if (!prop)
  42048. + continue;
  42049. +
  42050. + if (size != (2 * sizeof(*prop))) {
  42051. + pr_err("%s: failed to parse port mapping\n",
  42052. + port->name);
  42053. + continue;
  42054. + }
  42055. +
  42056. + phys = be32_to_cpup(prop++);
  42057. + if ((phys < 0) | (phys >= dev->ports)) {
  42058. + pr_err("%s: physical port index out of range\n",
  42059. + port->name);
  42060. + continue;
  42061. + }
  42062. +
  42063. + dev->portmap[phys].s = kstrdup(segment, GFP_KERNEL);
  42064. + dev->portmap[phys].virt = be32_to_cpup(prop);
  42065. + pr_debug("Found port: %s, physical: %d, virtual: %d\n",
  42066. + segment, phys, dev->portmap[phys].virt);
  42067. + }
  42068. +}
  42069. +#endif
  42070. +
  42071. +int
  42072. +register_switch(struct switch_dev *dev, struct net_device *netdev)
  42073. +{
  42074. + struct switch_dev *sdev;
  42075. + const int max_switches = 8 * sizeof(unsigned long);
  42076. + unsigned long in_use = 0;
  42077. + int err;
  42078. + int i;
  42079. +
  42080. + INIT_LIST_HEAD(&dev->dev_list);
  42081. + if (netdev) {
  42082. + dev->netdev = netdev;
  42083. + if (!dev->alias)
  42084. + dev->alias = netdev->name;
  42085. + }
  42086. + BUG_ON(!dev->alias);
  42087. +
  42088. + if (dev->ports > 0) {
  42089. + dev->portbuf = kzalloc(sizeof(struct switch_port) *
  42090. + dev->ports, GFP_KERNEL);
  42091. + if (!dev->portbuf)
  42092. + return -ENOMEM;
  42093. + dev->portmap = kzalloc(sizeof(struct switch_portmap) *
  42094. + dev->ports, GFP_KERNEL);
  42095. + if (!dev->portmap) {
  42096. + kfree(dev->portbuf);
  42097. + return -ENOMEM;
  42098. + }
  42099. + }
  42100. + swconfig_defaults_init(dev);
  42101. + mutex_init(&dev->sw_mutex);
  42102. + swconfig_lock();
  42103. + dev->id = ++swdev_id;
  42104. +
  42105. + list_for_each_entry(sdev, &swdevs, dev_list) {
  42106. + if (!sscanf(sdev->devname, SWCONFIG_DEVNAME, &i))
  42107. + continue;
  42108. + if (i < 0 || i > max_switches)
  42109. + continue;
  42110. +
  42111. + set_bit(i, &in_use);
  42112. + }
  42113. + i = find_first_zero_bit(&in_use, max_switches);
  42114. +
  42115. + if (i == max_switches) {
  42116. + swconfig_unlock();
  42117. + return -ENFILE;
  42118. + }
  42119. +
  42120. +#ifdef CONFIG_OF
  42121. + if (dev->ports)
  42122. + of_switch_load_portmap(dev);
  42123. +#endif
  42124. +
  42125. + /* fill device name */
  42126. + snprintf(dev->devname, IFNAMSIZ, SWCONFIG_DEVNAME, i);
  42127. +
  42128. + list_add_tail(&dev->dev_list, &swdevs);
  42129. + swconfig_unlock();
  42130. +
  42131. + err = swconfig_create_led_trigger(dev);
  42132. + if (err)
  42133. + return err;
  42134. +
  42135. + return 0;
  42136. +}
  42137. +EXPORT_SYMBOL_GPL(register_switch);
  42138. +
  42139. +void
  42140. +unregister_switch(struct switch_dev *dev)
  42141. +{
  42142. + swconfig_destroy_led_trigger(dev);
  42143. + kfree(dev->portbuf);
  42144. + mutex_lock(&dev->sw_mutex);
  42145. + swconfig_lock();
  42146. + list_del(&dev->dev_list);
  42147. + swconfig_unlock();
  42148. + mutex_unlock(&dev->sw_mutex);
  42149. +}
  42150. +EXPORT_SYMBOL_GPL(unregister_switch);
  42151. +
  42152. +
  42153. +static int __init
  42154. +swconfig_init(void)
  42155. +{
  42156. + int err;
  42157. +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0))
  42158. + int i;
  42159. +#endif
  42160. +
  42161. + INIT_LIST_HEAD(&swdevs);
  42162. +
  42163. +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0))
  42164. + err = genl_register_family(&switch_fam);
  42165. + if (err)
  42166. + return err;
  42167. +
  42168. + for (i = 0; i < ARRAY_SIZE(swconfig_ops); i++) {
  42169. + err = genl_register_ops(&switch_fam, &swconfig_ops[i]);
  42170. + if (err)
  42171. + goto unregister;
  42172. + }
  42173. + return 0;
  42174. +
  42175. +unregister:
  42176. + genl_unregister_family(&switch_fam);
  42177. + return err;
  42178. +#else
  42179. + err = genl_register_family_with_ops(&switch_fam, swconfig_ops);
  42180. + if (err)
  42181. + return err;
  42182. + return 0;
  42183. +#endif
  42184. +}
  42185. +
  42186. +static void __exit
  42187. +swconfig_exit(void)
  42188. +{
  42189. + genl_unregister_family(&switch_fam);
  42190. +}
  42191. +
  42192. +module_init(swconfig_init);
  42193. +module_exit(swconfig_exit);
  42194. +
  42195. diff -Nur linux-4.1.43.orig/drivers/net/phy/swconfig_leds.c linux-4.1.43/drivers/net/phy/swconfig_leds.c
  42196. --- linux-4.1.43.orig/drivers/net/phy/swconfig_leds.c 1970-01-01 01:00:00.000000000 +0100
  42197. +++ linux-4.1.43/drivers/net/phy/swconfig_leds.c 2017-08-06 20:02:16.000000000 +0200
  42198. @@ -0,0 +1,354 @@
  42199. +/*
  42200. + * swconfig_led.c: LED trigger support for the switch configuration API
  42201. + *
  42202. + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  42203. + *
  42204. + * This program is free software; you can redistribute it and/or
  42205. + * modify it under the terms of the GNU General Public License
  42206. + * as published by the Free Software Foundation; either version 2
  42207. + * of the License, or (at your option) any later version.
  42208. + *
  42209. + */
  42210. +
  42211. +#ifdef CONFIG_SWCONFIG_LEDS
  42212. +
  42213. +#include <linux/leds.h>
  42214. +#include <linux/ctype.h>
  42215. +#include <linux/device.h>
  42216. +#include <linux/workqueue.h>
  42217. +
  42218. +#define SWCONFIG_LED_TIMER_INTERVAL (HZ / 10)
  42219. +#define SWCONFIG_LED_NUM_PORTS 32
  42220. +
  42221. +struct switch_led_trigger {
  42222. + struct led_trigger trig;
  42223. + struct switch_dev *swdev;
  42224. +
  42225. + struct delayed_work sw_led_work;
  42226. + u32 port_mask;
  42227. + u32 port_link;
  42228. + unsigned long port_traffic[SWCONFIG_LED_NUM_PORTS];
  42229. +};
  42230. +
  42231. +struct swconfig_trig_data {
  42232. + struct led_classdev *led_cdev;
  42233. + struct switch_dev *swdev;
  42234. +
  42235. + rwlock_t lock;
  42236. + u32 port_mask;
  42237. +
  42238. + bool prev_link;
  42239. + unsigned long prev_traffic;
  42240. + enum led_brightness prev_brightness;
  42241. +};
  42242. +
  42243. +static void
  42244. +swconfig_trig_set_brightness(struct swconfig_trig_data *trig_data,
  42245. + enum led_brightness brightness)
  42246. +{
  42247. + led_set_brightness(trig_data->led_cdev, brightness);
  42248. + trig_data->prev_brightness = brightness;
  42249. +}
  42250. +
  42251. +static void
  42252. +swconfig_trig_update_port_mask(struct led_trigger *trigger)
  42253. +{
  42254. + struct list_head *entry;
  42255. + struct switch_led_trigger *sw_trig;
  42256. + u32 port_mask;
  42257. +
  42258. + if (!trigger)
  42259. + return;
  42260. +
  42261. + sw_trig = (void *) trigger;
  42262. +
  42263. + port_mask = 0;
  42264. + read_lock(&trigger->leddev_list_lock);
  42265. + list_for_each(entry, &trigger->led_cdevs) {
  42266. + struct led_classdev *led_cdev;
  42267. + struct swconfig_trig_data *trig_data;
  42268. +
  42269. + led_cdev = list_entry(entry, struct led_classdev, trig_list);
  42270. + trig_data = led_cdev->trigger_data;
  42271. + if (trig_data) {
  42272. + read_lock(&trig_data->lock);
  42273. + port_mask |= trig_data->port_mask;
  42274. + read_unlock(&trig_data->lock);
  42275. + }
  42276. + }
  42277. + read_unlock(&trigger->leddev_list_lock);
  42278. +
  42279. + sw_trig->port_mask = port_mask;
  42280. +
  42281. + if (port_mask)
  42282. + schedule_delayed_work(&sw_trig->sw_led_work,
  42283. + SWCONFIG_LED_TIMER_INTERVAL);
  42284. + else
  42285. + cancel_delayed_work_sync(&sw_trig->sw_led_work);
  42286. +}
  42287. +
  42288. +static ssize_t
  42289. +swconfig_trig_port_mask_store(struct device *dev, struct device_attribute *attr,
  42290. + const char *buf, size_t size)
  42291. +{
  42292. + struct led_classdev *led_cdev = dev_get_drvdata(dev);
  42293. + struct swconfig_trig_data *trig_data = led_cdev->trigger_data;
  42294. + unsigned long port_mask;
  42295. + ssize_t ret = -EINVAL;
  42296. + char *after;
  42297. + size_t count;
  42298. +
  42299. + port_mask = simple_strtoul(buf, &after, 16);
  42300. + count = after - buf;
  42301. +
  42302. + if (*after && isspace(*after))
  42303. + count++;
  42304. +
  42305. + if (count == size) {
  42306. + bool changed;
  42307. +
  42308. + write_lock(&trig_data->lock);
  42309. +
  42310. + changed = (trig_data->port_mask != port_mask);
  42311. + if (changed) {
  42312. + trig_data->port_mask = port_mask;
  42313. + if (port_mask == 0)
  42314. + swconfig_trig_set_brightness(trig_data, LED_OFF);
  42315. + }
  42316. +
  42317. + write_unlock(&trig_data->lock);
  42318. +
  42319. + if (changed)
  42320. + swconfig_trig_update_port_mask(led_cdev->trigger);
  42321. +
  42322. + ret = count;
  42323. + }
  42324. +
  42325. + return ret;
  42326. +}
  42327. +
  42328. +static ssize_t
  42329. +swconfig_trig_port_mask_show(struct device *dev, struct device_attribute *attr,
  42330. + char *buf)
  42331. +{
  42332. + struct led_classdev *led_cdev = dev_get_drvdata(dev);
  42333. + struct swconfig_trig_data *trig_data = led_cdev->trigger_data;
  42334. +
  42335. + read_lock(&trig_data->lock);
  42336. + sprintf(buf, "%#x\n", trig_data->port_mask);
  42337. + read_unlock(&trig_data->lock);
  42338. +
  42339. + return strlen(buf) + 1;
  42340. +}
  42341. +
  42342. +static DEVICE_ATTR(port_mask, 0644, swconfig_trig_port_mask_show,
  42343. + swconfig_trig_port_mask_store);
  42344. +
  42345. +static void
  42346. +swconfig_trig_activate(struct led_classdev *led_cdev)
  42347. +{
  42348. + struct switch_led_trigger *sw_trig;
  42349. + struct swconfig_trig_data *trig_data;
  42350. + int err;
  42351. +
  42352. + if (led_cdev->trigger->activate != swconfig_trig_activate)
  42353. + return;
  42354. +
  42355. + trig_data = kzalloc(sizeof(struct swconfig_trig_data), GFP_KERNEL);
  42356. + if (!trig_data)
  42357. + return;
  42358. +
  42359. + sw_trig = (void *) led_cdev->trigger;
  42360. +
  42361. + rwlock_init(&trig_data->lock);
  42362. + trig_data->led_cdev = led_cdev;
  42363. + trig_data->swdev = sw_trig->swdev;
  42364. + led_cdev->trigger_data = trig_data;
  42365. +
  42366. + err = device_create_file(led_cdev->dev, &dev_attr_port_mask);
  42367. + if (err)
  42368. + goto err_free;
  42369. +
  42370. + return;
  42371. +
  42372. +err_free:
  42373. + led_cdev->trigger_data = NULL;
  42374. + kfree(trig_data);
  42375. +}
  42376. +
  42377. +static void
  42378. +swconfig_trig_deactivate(struct led_classdev *led_cdev)
  42379. +{
  42380. + struct swconfig_trig_data *trig_data;
  42381. +
  42382. + swconfig_trig_update_port_mask(led_cdev->trigger);
  42383. +
  42384. + trig_data = (void *) led_cdev->trigger_data;
  42385. + if (trig_data) {
  42386. + device_remove_file(led_cdev->dev, &dev_attr_port_mask);
  42387. + kfree(trig_data);
  42388. + }
  42389. +}
  42390. +
  42391. +static void
  42392. +swconfig_trig_led_event(struct switch_led_trigger *sw_trig,
  42393. + struct led_classdev *led_cdev)
  42394. +{
  42395. + struct swconfig_trig_data *trig_data;
  42396. + u32 port_mask;
  42397. + bool link;
  42398. +
  42399. + trig_data = led_cdev->trigger_data;
  42400. + if (!trig_data)
  42401. + return;
  42402. +
  42403. + read_lock(&trig_data->lock);
  42404. + port_mask = trig_data->port_mask;
  42405. + read_unlock(&trig_data->lock);
  42406. +
  42407. + link = !!(sw_trig->port_link & port_mask);
  42408. + if (!link) {
  42409. + if (link != trig_data->prev_link)
  42410. + swconfig_trig_set_brightness(trig_data, LED_OFF);
  42411. + } else {
  42412. + unsigned long traffic;
  42413. + int i;
  42414. +
  42415. + traffic = 0;
  42416. + for (i = 0; i < SWCONFIG_LED_NUM_PORTS; i++) {
  42417. + if (port_mask & (1 << i))
  42418. + traffic += sw_trig->port_traffic[i];
  42419. + }
  42420. +
  42421. + if (trig_data->prev_brightness != LED_FULL)
  42422. + swconfig_trig_set_brightness(trig_data, LED_FULL);
  42423. + else if (traffic != trig_data->prev_traffic)
  42424. + swconfig_trig_set_brightness(trig_data, LED_OFF);
  42425. +
  42426. + trig_data->prev_traffic = traffic;
  42427. + }
  42428. +
  42429. + trig_data->prev_link = link;
  42430. +}
  42431. +
  42432. +static void
  42433. +swconfig_trig_update_leds(struct switch_led_trigger *sw_trig)
  42434. +{
  42435. + struct list_head *entry;
  42436. + struct led_trigger *trigger;
  42437. +
  42438. + trigger = &sw_trig->trig;
  42439. + read_lock(&trigger->leddev_list_lock);
  42440. + list_for_each(entry, &trigger->led_cdevs) {
  42441. + struct led_classdev *led_cdev;
  42442. +
  42443. + led_cdev = list_entry(entry, struct led_classdev, trig_list);
  42444. + swconfig_trig_led_event(sw_trig, led_cdev);
  42445. + }
  42446. + read_unlock(&trigger->leddev_list_lock);
  42447. +}
  42448. +
  42449. +static void
  42450. +swconfig_led_work_func(struct work_struct *work)
  42451. +{
  42452. + struct switch_led_trigger *sw_trig;
  42453. + struct switch_dev *swdev;
  42454. + u32 port_mask;
  42455. + u32 link;
  42456. + int i;
  42457. +
  42458. + sw_trig = container_of(work, struct switch_led_trigger,
  42459. + sw_led_work.work);
  42460. +
  42461. + port_mask = sw_trig->port_mask;
  42462. + swdev = sw_trig->swdev;
  42463. +
  42464. + link = 0;
  42465. + for (i = 0; i < SWCONFIG_LED_NUM_PORTS; i++) {
  42466. + u32 port_bit;
  42467. +
  42468. + port_bit = BIT(i);
  42469. + if ((port_mask & port_bit) == 0)
  42470. + continue;
  42471. +
  42472. + if (swdev->ops->get_port_link) {
  42473. + struct switch_port_link port_link;
  42474. +
  42475. + memset(&port_link, '\0', sizeof(port_link));
  42476. + swdev->ops->get_port_link(swdev, i, &port_link);
  42477. +
  42478. + if (port_link.link)
  42479. + link |= port_bit;
  42480. + }
  42481. +
  42482. + if (swdev->ops->get_port_stats) {
  42483. + struct switch_port_stats port_stats;
  42484. +
  42485. + memset(&port_stats, '\0', sizeof(port_stats));
  42486. + swdev->ops->get_port_stats(swdev, i, &port_stats);
  42487. + sw_trig->port_traffic[i] = port_stats.tx_bytes +
  42488. + port_stats.rx_bytes;
  42489. + }
  42490. + }
  42491. +
  42492. + sw_trig->port_link = link;
  42493. +
  42494. + swconfig_trig_update_leds(sw_trig);
  42495. +
  42496. + schedule_delayed_work(&sw_trig->sw_led_work,
  42497. + SWCONFIG_LED_TIMER_INTERVAL);
  42498. +}
  42499. +
  42500. +static int
  42501. +swconfig_create_led_trigger(struct switch_dev *swdev)
  42502. +{
  42503. + struct switch_led_trigger *sw_trig;
  42504. + int err;
  42505. +
  42506. + if (!swdev->ops->get_port_link)
  42507. + return 0;
  42508. +
  42509. + sw_trig = kzalloc(sizeof(struct switch_led_trigger), GFP_KERNEL);
  42510. + if (!sw_trig)
  42511. + return -ENOMEM;
  42512. +
  42513. + sw_trig->swdev = swdev;
  42514. + sw_trig->trig.name = swdev->devname;
  42515. + sw_trig->trig.activate = swconfig_trig_activate;
  42516. + sw_trig->trig.deactivate = swconfig_trig_deactivate;
  42517. +
  42518. + INIT_DELAYED_WORK(&sw_trig->sw_led_work, swconfig_led_work_func);
  42519. +
  42520. + err = led_trigger_register(&sw_trig->trig);
  42521. + if (err)
  42522. + goto err_free;
  42523. +
  42524. + swdev->led_trigger = sw_trig;
  42525. +
  42526. + return 0;
  42527. +
  42528. +err_free:
  42529. + kfree(sw_trig);
  42530. + return err;
  42531. +}
  42532. +
  42533. +static void
  42534. +swconfig_destroy_led_trigger(struct switch_dev *swdev)
  42535. +{
  42536. + struct switch_led_trigger *sw_trig;
  42537. +
  42538. + sw_trig = swdev->led_trigger;
  42539. + if (sw_trig) {
  42540. + cancel_delayed_work_sync(&sw_trig->sw_led_work);
  42541. + led_trigger_unregister(&sw_trig->trig);
  42542. + kfree(sw_trig);
  42543. + }
  42544. +}
  42545. +
  42546. +#else /* SWCONFIG_LEDS */
  42547. +static inline int
  42548. +swconfig_create_led_trigger(struct switch_dev *swdev) { return 0; }
  42549. +
  42550. +static inline void
  42551. +swconfig_destroy_led_trigger(struct switch_dev *swdev) { }
  42552. +#endif /* CONFIG_SWCONFIG_LEDS */
  42553. diff -Nur linux-4.1.43.orig/drivers/spi/Kconfig linux-4.1.43/drivers/spi/Kconfig
  42554. --- linux-4.1.43.orig/drivers/spi/Kconfig 2017-08-06 01:56:14.000000000 +0200
  42555. +++ linux-4.1.43/drivers/spi/Kconfig 2017-08-06 20:02:16.000000000 +0200
  42556. @@ -59,6 +59,14 @@
  42557. help
  42558. This is the driver for the Altera SPI Controller.
  42559. +config SPI_AP83
  42560. + tristate "Atheros AP83 specific SPI Controller"
  42561. + depends on SPI_MASTER && ATH79_MACH_AP83
  42562. + select SPI_BITBANG
  42563. + help
  42564. + This is a specific SPI controller driver for the Atheros AP83
  42565. + reference board.
  42566. +
  42567. config SPI_ATH79
  42568. tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
  42569. depends on ATH79 && GPIOLIB
  42570. @@ -448,6 +456,12 @@
  42571. This driver can also be built as a module. If so, the module
  42572. will be called spi_qup.
  42573. +config SPI_RB4XX
  42574. + tristate "Mikrotik RB4XX SPI master"
  42575. + depends on SPI_MASTER && ATH79_MACH_RB4XX
  42576. + help
  42577. + SPI controller driver for the Mikrotik RB4xx series boards.
  42578. +
  42579. config SPI_S3C24XX
  42580. tristate "Samsung S3C24XX series SPI"
  42581. depends on ARCH_S3C24XX
  42582. @@ -661,6 +675,18 @@
  42583. sysfs interface, with each line presented as a kind of GPIO
  42584. exposing both switch control and diagnostic feedback.
  42585. +config SPI_RB4XX_CPLD
  42586. + tristate "MikroTik RB4XX CPLD driver"
  42587. + depends on ATH79_MACH_RB4XX
  42588. + help
  42589. + SPI driver for the Xilinx CPLD chip present on the
  42590. + MikroTik RB4xx boards.
  42591. +
  42592. +config SPI_VSC7385
  42593. + tristate "Vitesse VSC7385 ethernet switch driver"
  42594. + help
  42595. + SPI driver for the Vitesse VSC7385 ethernet switch.
  42596. +
  42597. #
  42598. # Add new SPI protocol masters in alphabetical order above this line
  42599. #
  42600. diff -Nur linux-4.1.43.orig/drivers/spi/Makefile linux-4.1.43/drivers/spi/Makefile
  42601. --- linux-4.1.43.orig/drivers/spi/Makefile 2017-08-06 01:56:14.000000000 +0200
  42602. +++ linux-4.1.43/drivers/spi/Makefile 2017-08-06 20:02:16.000000000 +0200
  42603. @@ -12,6 +12,7 @@
  42604. # SPI master controller drivers (bus)
  42605. obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
  42606. obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
  42607. +obj-$(CONFIG_SPI_AP83) += spi-ap83.o
  42608. obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
  42609. obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
  42610. obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
  42611. @@ -64,6 +65,8 @@
  42612. spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
  42613. obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
  42614. obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
  42615. +obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
  42616. +obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o
  42617. obj-$(CONFIG_SPI_QUP) += spi-qup.o
  42618. obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
  42619. obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
  42620. @@ -86,6 +89,7 @@
  42621. obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
  42622. obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
  42623. obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
  42624. +obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o
  42625. obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
  42626. obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
  42627. obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
  42628. diff -Nur linux-4.1.43.orig/drivers/spi/spi-ap83.c linux-4.1.43/drivers/spi/spi-ap83.c
  42629. --- linux-4.1.43.orig/drivers/spi/spi-ap83.c 1970-01-01 01:00:00.000000000 +0100
  42630. +++ linux-4.1.43/drivers/spi/spi-ap83.c 2017-08-06 20:02:16.000000000 +0200
  42631. @@ -0,0 +1,283 @@
  42632. +/*
  42633. + * Atheros AP83 board specific SPI Controller driver
  42634. + *
  42635. + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  42636. + *
  42637. + * This program is free software; you can redistribute it and/or modify
  42638. + * it under the terms of the GNU General Public License version 2 as
  42639. + * published by the Free Software Foundation.
  42640. + *
  42641. + */
  42642. +
  42643. +#include <linux/kernel.h>
  42644. +#include <linux/module.h>
  42645. +#include <linux/init.h>
  42646. +#include <linux/delay.h>
  42647. +#include <linux/spinlock.h>
  42648. +#include <linux/workqueue.h>
  42649. +#include <linux/platform_device.h>
  42650. +#include <linux/io.h>
  42651. +#include <linux/spi/spi.h>
  42652. +#include <linux/spi/spi_bitbang.h>
  42653. +#include <linux/bitops.h>
  42654. +#include <linux/gpio.h>
  42655. +
  42656. +#include <asm/mach-ath79/ath79.h>
  42657. +
  42658. +#define DRV_DESC "Atheros AP83 board SPI Controller driver"
  42659. +#define DRV_VERSION "0.1.0"
  42660. +#define DRV_NAME "ap83-spi"
  42661. +
  42662. +#define AP83_SPI_CLK_HIGH (1 << 23)
  42663. +#define AP83_SPI_CLK_LOW 0
  42664. +#define AP83_SPI_MOSI_HIGH (1 << 22)
  42665. +#define AP83_SPI_MOSI_LOW 0
  42666. +
  42667. +#define AP83_SPI_GPIO_CS 1
  42668. +#define AP83_SPI_GPIO_MISO 3
  42669. +
  42670. +struct ap83_spi {
  42671. + struct spi_bitbang bitbang;
  42672. + void __iomem *base;
  42673. + u32 addr;
  42674. +
  42675. + struct platform_device *pdev;
  42676. +};
  42677. +
  42678. +static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg)
  42679. +{
  42680. + return __raw_readl(sp->base + reg);
  42681. +}
  42682. +
  42683. +static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi)
  42684. +{
  42685. + return spi_master_get_devdata(spi->master);
  42686. +}
  42687. +
  42688. +static inline void setsck(struct spi_device *spi, int val)
  42689. +{
  42690. + struct ap83_spi *sp = spidev_to_sp(spi);
  42691. +
  42692. + if (val)
  42693. + sp->addr |= AP83_SPI_CLK_HIGH;
  42694. + else
  42695. + sp->addr &= ~AP83_SPI_CLK_HIGH;
  42696. +
  42697. + dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n",
  42698. + sp->addr, (val) ? "HIGH" : "LOW");
  42699. +
  42700. + ap83_spi_rr(sp, sp->addr);
  42701. +}
  42702. +
  42703. +static inline void setmosi(struct spi_device *spi, int val)
  42704. +{
  42705. + struct ap83_spi *sp = spidev_to_sp(spi);
  42706. +
  42707. + if (val)
  42708. + sp->addr |= AP83_SPI_MOSI_HIGH;
  42709. + else
  42710. + sp->addr &= ~AP83_SPI_MOSI_HIGH;
  42711. +
  42712. + dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n",
  42713. + sp->addr, (val) ? "HIGH" : "LOW");
  42714. +
  42715. + ap83_spi_rr(sp, sp->addr);
  42716. +}
  42717. +
  42718. +static inline u32 getmiso(struct spi_device *spi)
  42719. +{
  42720. + u32 ret;
  42721. +
  42722. + ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0;
  42723. + dev_dbg(&spi->dev, "get MISO: %d\n", ret);
  42724. +
  42725. + return ret;
  42726. +}
  42727. +
  42728. +static inline void do_spidelay(struct spi_device *spi, unsigned nsecs)
  42729. +{
  42730. + ndelay(nsecs);
  42731. +}
  42732. +
  42733. +static void ap83_spi_chipselect(struct spi_device *spi, int on)
  42734. +{
  42735. + struct ap83_spi *sp = spidev_to_sp(spi);
  42736. +
  42737. + dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1);
  42738. +
  42739. + if (on) {
  42740. + ath79_flash_acquire();
  42741. +
  42742. + sp->addr = 0;
  42743. + ap83_spi_rr(sp, sp->addr);
  42744. +
  42745. + gpio_set_value(AP83_SPI_GPIO_CS, 0);
  42746. + } else {
  42747. + gpio_set_value(AP83_SPI_GPIO_CS, 1);
  42748. + ath79_flash_release();
  42749. + }
  42750. +}
  42751. +
  42752. +#define spidelay(nsecs) \
  42753. + do { \
  42754. + /* Steal the spi_device pointer from our caller. \
  42755. + * The bitbang-API should probably get fixed here... */ \
  42756. + do_spidelay(spi, nsecs); \
  42757. + } while (0)
  42758. +
  42759. +#define EXPAND_BITBANG_TXRX
  42760. +#include <linux/spi/spi_bitbang.h>
  42761. +#include "spi-bitbang-txrx.h"
  42762. +
  42763. +static u32 ap83_spi_txrx_mode0(struct spi_device *spi,
  42764. + unsigned nsecs, u32 word, u8 bits)
  42765. +{
  42766. + dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits);
  42767. + return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits);
  42768. +}
  42769. +
  42770. +static u32 ap83_spi_txrx_mode1(struct spi_device *spi,
  42771. + unsigned nsecs, u32 word, u8 bits)
  42772. +{
  42773. + dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits);
  42774. + return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits);
  42775. +}
  42776. +
  42777. +static u32 ap83_spi_txrx_mode2(struct spi_device *spi,
  42778. + unsigned nsecs, u32 word, u8 bits)
  42779. +{
  42780. + dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits);
  42781. + return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits);
  42782. +}
  42783. +
  42784. +static u32 ap83_spi_txrx_mode3(struct spi_device *spi,
  42785. + unsigned nsecs, u32 word, u8 bits)
  42786. +{
  42787. + dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits);
  42788. + return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits);
  42789. +}
  42790. +
  42791. +static int ap83_spi_probe(struct platform_device *pdev)
  42792. +{
  42793. + struct spi_master *master;
  42794. + struct ap83_spi *sp;
  42795. + struct ap83_spi_platform_data *pdata;
  42796. + struct resource *r;
  42797. + int ret;
  42798. +
  42799. + ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso");
  42800. + if (ret) {
  42801. + dev_err(&pdev->dev, "gpio request failed for MISO\n");
  42802. + return ret;
  42803. + }
  42804. +
  42805. + ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs");
  42806. + if (ret) {
  42807. + dev_err(&pdev->dev, "gpio request failed for CS\n");
  42808. + goto err_free_miso;
  42809. + }
  42810. +
  42811. + ret = gpio_direction_input(AP83_SPI_GPIO_MISO);
  42812. + if (ret) {
  42813. + dev_err(&pdev->dev, "unable to set direction of MISO\n");
  42814. + goto err_free_cs;
  42815. + }
  42816. +
  42817. + ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0);
  42818. + if (ret) {
  42819. + dev_err(&pdev->dev, "unable to set direction of CS\n");
  42820. + goto err_free_cs;
  42821. + }
  42822. +
  42823. + master = spi_alloc_master(&pdev->dev, sizeof(*sp));
  42824. + if (master == NULL) {
  42825. + dev_err(&pdev->dev, "failed to allocate spi master\n");
  42826. + return -ENOMEM;
  42827. + }
  42828. +
  42829. + sp = spi_master_get_devdata(master);
  42830. + platform_set_drvdata(pdev, sp);
  42831. +
  42832. + pdata = pdev->dev.platform_data;
  42833. +
  42834. + sp->bitbang.master = spi_master_get(master);
  42835. + sp->bitbang.chipselect = ap83_spi_chipselect;
  42836. + sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0;
  42837. + sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1;
  42838. + sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2;
  42839. + sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3;
  42840. +
  42841. + sp->bitbang.master->bus_num = pdev->id;
  42842. + sp->bitbang.master->num_chipselect = 1;
  42843. +
  42844. + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  42845. + if (r == NULL) {
  42846. + ret = -ENOENT;
  42847. + goto err_spi_put;
  42848. + }
  42849. +
  42850. + sp->base = ioremap_nocache(r->start, r->end - r->start + 1);
  42851. + if (!sp->base) {
  42852. + ret = -ENXIO;
  42853. + goto err_spi_put;
  42854. + }
  42855. +
  42856. + ret = spi_bitbang_start(&sp->bitbang);
  42857. + if (!ret)
  42858. + goto err_unmap;
  42859. +
  42860. + dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start);
  42861. +
  42862. + return 0;
  42863. +
  42864. +err_unmap:
  42865. + iounmap(sp->base);
  42866. +err_spi_put:
  42867. + platform_set_drvdata(pdev, NULL);
  42868. + spi_master_put(sp->bitbang.master);
  42869. +
  42870. +err_free_cs:
  42871. + gpio_free(AP83_SPI_GPIO_CS);
  42872. +err_free_miso:
  42873. + gpio_free(AP83_SPI_GPIO_MISO);
  42874. + return ret;
  42875. +}
  42876. +
  42877. +static int ap83_spi_remove(struct platform_device *pdev)
  42878. +{
  42879. + struct ap83_spi *sp = platform_get_drvdata(pdev);
  42880. +
  42881. + spi_bitbang_stop(&sp->bitbang);
  42882. + iounmap(sp->base);
  42883. + platform_set_drvdata(pdev, NULL);
  42884. + spi_master_put(sp->bitbang.master);
  42885. +
  42886. + return 0;
  42887. +}
  42888. +
  42889. +static struct platform_driver ap83_spi_drv = {
  42890. + .probe = ap83_spi_probe,
  42891. + .remove = ap83_spi_remove,
  42892. + .driver = {
  42893. + .name = DRV_NAME,
  42894. + .owner = THIS_MODULE,
  42895. + },
  42896. +};
  42897. +
  42898. +static int __init ap83_spi_init(void)
  42899. +{
  42900. + return platform_driver_register(&ap83_spi_drv);
  42901. +}
  42902. +module_init(ap83_spi_init);
  42903. +
  42904. +static void __exit ap83_spi_exit(void)
  42905. +{
  42906. + platform_driver_unregister(&ap83_spi_drv);
  42907. +}
  42908. +module_exit(ap83_spi_exit);
  42909. +
  42910. +MODULE_ALIAS("platform:" DRV_NAME);
  42911. +MODULE_DESCRIPTION(DRV_DESC);
  42912. +MODULE_VERSION(DRV_VERSION);
  42913. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  42914. +MODULE_LICENSE("GPL v2");
  42915. diff -Nur linux-4.1.43.orig/drivers/spi/spi-ath79.c linux-4.1.43/drivers/spi/spi-ath79.c
  42916. --- linux-4.1.43.orig/drivers/spi/spi-ath79.c 2017-08-06 01:56:14.000000000 +0200
  42917. +++ linux-4.1.43/drivers/spi/spi-ath79.c 2017-08-06 20:02:16.000000000 +0200
  42918. @@ -33,6 +33,13 @@
  42919. #define ATH79_SPI_RRW_DELAY_FACTOR 12000
  42920. #define MHZ (1000 * 1000)
  42921. +#define ATH79_SPI_CS_LINE_MAX 2
  42922. +
  42923. +enum ath79_spi_state {
  42924. + ATH79_SPI_STATE_WAIT_CMD = 0,
  42925. + ATH79_SPI_STATE_WAIT_READ,
  42926. +};
  42927. +
  42928. struct ath79_spi {
  42929. struct spi_bitbang bitbang;
  42930. u32 ioc_base;
  42931. @@ -40,6 +47,11 @@
  42932. void __iomem *base;
  42933. struct clk *clk;
  42934. unsigned rrw_delay;
  42935. +
  42936. + enum ath79_spi_state state;
  42937. + u32 clk_div;
  42938. + unsigned long read_addr;
  42939. + unsigned long ahb_rate;
  42940. };
  42941. static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
  42942. @@ -67,6 +79,7 @@
  42943. {
  42944. struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  42945. int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
  42946. + struct ath79_spi_controller_data *cdata = spi->controller_data;
  42947. if (is_active) {
  42948. /* set initial clock polarity */
  42949. @@ -78,20 +91,24 @@
  42950. ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  42951. }
  42952. - if (spi->chip_select) {
  42953. - struct ath79_spi_controller_data *cdata = spi->controller_data;
  42954. -
  42955. - /* SPI is normally active-low */
  42956. - gpio_set_value(cdata->gpio, cs_high);
  42957. - } else {
  42958. + switch (cdata->cs_type) {
  42959. + case ATH79_SPI_CS_TYPE_INTERNAL:
  42960. if (cs_high)
  42961. - sp->ioc_base |= AR71XX_SPI_IOC_CS0;
  42962. + sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
  42963. else
  42964. - sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
  42965. + sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
  42966. ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  42967. - }
  42968. + break;
  42969. + case ATH79_SPI_CS_TYPE_GPIO:
  42970. + /* SPI is normally active-low */
  42971. + if (gpio_cansleep(cdata->cs_line))
  42972. + gpio_set_value_cansleep(cdata->cs_line, cs_high);
  42973. + else
  42974. + gpio_set_value(cdata->cs_line, cs_high);
  42975. + break;
  42976. + }
  42977. }
  42978. static void ath79_spi_enable(struct ath79_spi *sp)
  42979. @@ -102,9 +119,6 @@
  42980. /* save CTRL register */
  42981. sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
  42982. sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
  42983. -
  42984. - /* TODO: setup speed? */
  42985. - ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
  42986. }
  42987. static void ath79_spi_disable(struct ath79_spi *sp)
  42988. @@ -118,24 +132,30 @@
  42989. static int ath79_spi_setup_cs(struct spi_device *spi)
  42990. {
  42991. struct ath79_spi_controller_data *cdata;
  42992. + unsigned long flags;
  42993. int status;
  42994. cdata = spi->controller_data;
  42995. - if (spi->chip_select && !cdata)
  42996. + if (!cdata)
  42997. return -EINVAL;
  42998. status = 0;
  42999. - if (spi->chip_select) {
  43000. - unsigned long flags;
  43001. + switch (cdata->cs_type) {
  43002. + case ATH79_SPI_CS_TYPE_INTERNAL:
  43003. + if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
  43004. + status = -EINVAL;
  43005. + break;
  43006. + case ATH79_SPI_CS_TYPE_GPIO:
  43007. flags = GPIOF_DIR_OUT;
  43008. if (spi->mode & SPI_CS_HIGH)
  43009. flags |= GPIOF_INIT_LOW;
  43010. else
  43011. flags |= GPIOF_INIT_HIGH;
  43012. - status = gpio_request_one(cdata->gpio, flags,
  43013. + status = gpio_request_one(cdata->cs_line, flags,
  43014. dev_name(&spi->dev));
  43015. + break;
  43016. }
  43017. return status;
  43018. @@ -143,9 +163,19 @@
  43019. static void ath79_spi_cleanup_cs(struct spi_device *spi)
  43020. {
  43021. - if (spi->chip_select) {
  43022. - struct ath79_spi_controller_data *cdata = spi->controller_data;
  43023. - gpio_free(cdata->gpio);
  43024. + struct ath79_spi_controller_data *cdata;
  43025. +
  43026. + cdata = spi->controller_data;
  43027. + if (!cdata)
  43028. + return;
  43029. +
  43030. + switch (cdata->cs_type) {
  43031. + case ATH79_SPI_CS_TYPE_INTERNAL:
  43032. + /* nothing to do */
  43033. + break;
  43034. + case ATH79_SPI_CS_TYPE_GPIO:
  43035. + gpio_free(cdata->cs_line);
  43036. + break;
  43037. }
  43038. }
  43039. @@ -201,6 +231,114 @@
  43040. return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
  43041. }
  43042. +static int ath79_spi_do_read_flash_data(struct spi_device *spi,
  43043. + struct spi_transfer *t)
  43044. +{
  43045. + struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  43046. +
  43047. + /* disable GPIO mode */
  43048. + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
  43049. +
  43050. + memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
  43051. +
  43052. + /* enable GPIO mode */
  43053. + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
  43054. +
  43055. + /* restore IOC register */
  43056. + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  43057. +
  43058. + return t->len;
  43059. +}
  43060. +
  43061. +static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
  43062. + struct spi_transfer *t)
  43063. +{
  43064. + struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  43065. + int len;
  43066. + const u8 *p;
  43067. +
  43068. + sp->read_addr = 0;
  43069. +
  43070. + len = t->len - 1;
  43071. +
  43072. + if (t->dummy)
  43073. + len -= 1;
  43074. +
  43075. + p = t->tx_buf;
  43076. +
  43077. + while (len--) {
  43078. + p++;
  43079. + sp->read_addr <<= 8;
  43080. + sp->read_addr |= *p;
  43081. + }
  43082. +
  43083. + return t->len;
  43084. +}
  43085. +
  43086. +static bool ath79_spi_is_read_cmd(struct spi_device *spi,
  43087. + struct spi_transfer *t)
  43088. +{
  43089. + return t->type == SPI_TRANSFER_FLASH_READ_CMD;
  43090. +}
  43091. +
  43092. +static bool ath79_spi_is_data_read(struct spi_device *spi,
  43093. + struct spi_transfer *t)
  43094. +{
  43095. + return t->type == SPI_TRANSFER_FLASH_READ_DATA;
  43096. +}
  43097. +
  43098. +static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
  43099. +{
  43100. + struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  43101. + int ret;
  43102. +
  43103. + switch (sp->state) {
  43104. + case ATH79_SPI_STATE_WAIT_CMD:
  43105. + if (ath79_spi_is_read_cmd(spi, t)) {
  43106. + ret = ath79_spi_do_read_flash_cmd(spi, t);
  43107. + sp->state = ATH79_SPI_STATE_WAIT_READ;
  43108. + } else {
  43109. + ret = spi_bitbang_bufs(spi, t);
  43110. + }
  43111. + break;
  43112. +
  43113. + case ATH79_SPI_STATE_WAIT_READ:
  43114. + if (ath79_spi_is_data_read(spi, t)) {
  43115. + ret = ath79_spi_do_read_flash_data(spi, t);
  43116. + } else {
  43117. + dev_warn(&spi->dev, "flash data read expected\n");
  43118. + ret = -EIO;
  43119. + }
  43120. + sp->state = ATH79_SPI_STATE_WAIT_CMD;
  43121. + break;
  43122. +
  43123. + default:
  43124. + BUG();
  43125. + }
  43126. +
  43127. + return ret;
  43128. +}
  43129. +
  43130. +static int ath79_spi_setup_transfer(struct spi_device *spi,
  43131. + struct spi_transfer *t)
  43132. +{
  43133. + struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  43134. + struct ath79_spi_controller_data *cdata;
  43135. + int ret;
  43136. +
  43137. + ret = spi_bitbang_setup_transfer(spi, t);
  43138. + if (ret)
  43139. + return ret;
  43140. +
  43141. + cdata = spi->controller_data;
  43142. + if (cdata->is_flash)
  43143. + sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
  43144. + else
  43145. + sp->bitbang.txrx_bufs = spi_bitbang_bufs;
  43146. +
  43147. + return ret;
  43148. +}
  43149. +
  43150. static int ath79_spi_probe(struct platform_device *pdev)
  43151. {
  43152. struct spi_master *master;
  43153. @@ -210,6 +348,10 @@
  43154. unsigned long rate;
  43155. int ret;
  43156. + pdata = pdev->dev.platform_data;
  43157. + if (!pdata)
  43158. + return -EINVAL;
  43159. +
  43160. master = spi_alloc_master(&pdev->dev, sizeof(*sp));
  43161. if (master == NULL) {
  43162. dev_err(&pdev->dev, "failed to allocate spi master\n");
  43163. @@ -219,20 +361,18 @@
  43164. sp = spi_master_get_devdata(master);
  43165. platform_set_drvdata(pdev, sp);
  43166. - pdata = dev_get_platdata(&pdev->dev);
  43167. + sp->state = ATH79_SPI_STATE_WAIT_CMD;
  43168. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
  43169. master->setup = ath79_spi_setup;
  43170. master->cleanup = ath79_spi_cleanup;
  43171. - if (pdata) {
  43172. - master->bus_num = pdata->bus_num;
  43173. - master->num_chipselect = pdata->num_chipselect;
  43174. - }
  43175. + master->bus_num = pdata->bus_num;
  43176. + master->num_chipselect = pdata->num_chipselect;
  43177. sp->bitbang.master = master;
  43178. sp->bitbang.chipselect = ath79_spi_chipselect;
  43179. sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
  43180. - sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
  43181. + sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
  43182. sp->bitbang.flags = SPI_CS_HIGH;
  43183. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  43184. @@ -257,7 +397,8 @@
  43185. if (ret)
  43186. goto err_put_master;
  43187. - rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
  43188. + sp->ahb_rate = clk_get_rate(sp->clk);
  43189. + rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
  43190. if (!rate) {
  43191. ret = -EINVAL;
  43192. goto err_clk_disable;
  43193. diff -Nur linux-4.1.43.orig/drivers/spi/spi-bitbang.c linux-4.1.43/drivers/spi/spi-bitbang.c
  43194. --- linux-4.1.43.orig/drivers/spi/spi-bitbang.c 2017-08-06 01:56:14.000000000 +0200
  43195. +++ linux-4.1.43/drivers/spi/spi-bitbang.c 2017-08-06 20:02:16.000000000 +0200
  43196. @@ -230,13 +230,14 @@
  43197. }
  43198. EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
  43199. -static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
  43200. +int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
  43201. {
  43202. struct spi_bitbang_cs *cs = spi->controller_state;
  43203. unsigned nsecs = cs->nsecs;
  43204. return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
  43205. }
  43206. +EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
  43207. /*----------------------------------------------------------------------*/
  43208. diff -Nur linux-4.1.43.orig/drivers/spi/spi-rb4xx-cpld.c linux-4.1.43/drivers/spi/spi-rb4xx-cpld.c
  43209. --- linux-4.1.43.orig/drivers/spi/spi-rb4xx-cpld.c 1970-01-01 01:00:00.000000000 +0100
  43210. +++ linux-4.1.43/drivers/spi/spi-rb4xx-cpld.c 2017-08-06 20:02:16.000000000 +0200
  43211. @@ -0,0 +1,441 @@
  43212. +/*
  43213. + * SPI driver for the CPLD chip on the Mikrotik RB4xx boards
  43214. + *
  43215. + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  43216. + *
  43217. + * This file was based on the patches for Linux 2.6.27.39 published by
  43218. + * MikroTik for their RouterBoard 4xx series devices.
  43219. + *
  43220. + * This program is free software; you can redistribute it and/or modify it
  43221. + * under the terms of the GNU General Public License version 2 as published
  43222. + * by the Free Software Foundation.
  43223. + */
  43224. +
  43225. +#include <linux/types.h>
  43226. +#include <linux/kernel.h>
  43227. +#include <linux/module.h>
  43228. +#include <linux/init.h>
  43229. +#include <linux/module.h>
  43230. +#include <linux/device.h>
  43231. +#include <linux/bitops.h>
  43232. +#include <linux/spi/spi.h>
  43233. +#include <linux/gpio.h>
  43234. +#include <linux/slab.h>
  43235. +
  43236. +#include <asm/mach-ath79/rb4xx_cpld.h>
  43237. +
  43238. +#define DRV_NAME "spi-rb4xx-cpld"
  43239. +#define DRV_DESC "RB4xx CPLD driver"
  43240. +#define DRV_VERSION "0.1.0"
  43241. +
  43242. +#define CPLD_CMD_WRITE_NAND 0x08 /* send cmd, n x send data, send indle */
  43243. +#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */
  43244. +#define CPLD_CMD_READ_NAND 0x0a /* send cmd, send idle, n x read data */
  43245. +#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */
  43246. +#define CPLD_CMD_LED5_ON 0x0c /* send cmd */
  43247. +#define CPLD_CMD_LED5_OFF 0x0d /* send cmd */
  43248. +
  43249. +struct rb4xx_cpld {
  43250. + struct spi_device *spi;
  43251. + struct mutex lock;
  43252. + struct gpio_chip chip;
  43253. + unsigned int config;
  43254. +};
  43255. +
  43256. +static struct rb4xx_cpld *rb4xx_cpld;
  43257. +
  43258. +static inline struct rb4xx_cpld *gpio_to_cpld(struct gpio_chip *chip)
  43259. +{
  43260. + return container_of(chip, struct rb4xx_cpld, chip);
  43261. +}
  43262. +
  43263. +static int rb4xx_cpld_write_cmd(struct rb4xx_cpld *cpld, unsigned char cmd)
  43264. +{
  43265. + struct spi_transfer t[1];
  43266. + struct spi_message m;
  43267. + unsigned char tx_buf[1];
  43268. + int err;
  43269. +
  43270. + spi_message_init(&m);
  43271. + memset(&t, 0, sizeof(t));
  43272. +
  43273. + t[0].tx_buf = tx_buf;
  43274. + t[0].len = sizeof(tx_buf);
  43275. + spi_message_add_tail(&t[0], &m);
  43276. +
  43277. + tx_buf[0] = cmd;
  43278. +
  43279. + err = spi_sync(cpld->spi, &m);
  43280. + return err;
  43281. +}
  43282. +
  43283. +static int rb4xx_cpld_write_cfg(struct rb4xx_cpld *cpld, unsigned char config)
  43284. +{
  43285. + struct spi_transfer t[1];
  43286. + struct spi_message m;
  43287. + unsigned char cmd[2];
  43288. + int err;
  43289. +
  43290. + spi_message_init(&m);
  43291. + memset(&t, 0, sizeof(t));
  43292. +
  43293. + t[0].tx_buf = cmd;
  43294. + t[0].len = sizeof(cmd);
  43295. + spi_message_add_tail(&t[0], &m);
  43296. +
  43297. + cmd[0] = CPLD_CMD_WRITE_CFG;
  43298. + cmd[1] = config;
  43299. +
  43300. + err = spi_sync(cpld->spi, &m);
  43301. + return err;
  43302. +}
  43303. +
  43304. +static int __rb4xx_cpld_change_cfg(struct rb4xx_cpld *cpld, unsigned mask,
  43305. + unsigned value)
  43306. +{
  43307. + unsigned int config;
  43308. + int err;
  43309. +
  43310. + config = cpld->config & ~mask;
  43311. + config |= value;
  43312. +
  43313. + if ((cpld->config ^ config) & 0xff) {
  43314. + err = rb4xx_cpld_write_cfg(cpld, config);
  43315. + if (err)
  43316. + return err;
  43317. + }
  43318. +
  43319. + if ((cpld->config ^ config) & CPLD_CFG_nLED5) {
  43320. + err = rb4xx_cpld_write_cmd(cpld, (value) ? CPLD_CMD_LED5_ON :
  43321. + CPLD_CMD_LED5_OFF);
  43322. + if (err)
  43323. + return err;
  43324. + }
  43325. +
  43326. + cpld->config = config;
  43327. + return 0;
  43328. +}
  43329. +
  43330. +int rb4xx_cpld_change_cfg(unsigned mask, unsigned value)
  43331. +{
  43332. + int ret;
  43333. +
  43334. + if (rb4xx_cpld == NULL)
  43335. + return -ENODEV;
  43336. +
  43337. + mutex_lock(&rb4xx_cpld->lock);
  43338. + ret = __rb4xx_cpld_change_cfg(rb4xx_cpld, mask, value);
  43339. + mutex_unlock(&rb4xx_cpld->lock);
  43340. +
  43341. + return ret;
  43342. +}
  43343. +EXPORT_SYMBOL_GPL(rb4xx_cpld_change_cfg);
  43344. +
  43345. +int rb4xx_cpld_read_from(unsigned addr, unsigned char *rx_buf,
  43346. + const unsigned char *verify_buf, unsigned count)
  43347. +{
  43348. + const unsigned char cmd[5] = {
  43349. + CPLD_CMD_READ_FAST,
  43350. + (addr >> 16) & 0xff,
  43351. + (addr >> 8) & 0xff,
  43352. + addr & 0xff,
  43353. + 0
  43354. + };
  43355. + struct spi_transfer t[2] = {
  43356. + {
  43357. + .tx_buf = &cmd,
  43358. + .len = 5,
  43359. + },
  43360. + {
  43361. + .tx_buf = verify_buf,
  43362. + .rx_buf = rx_buf,
  43363. + .len = count,
  43364. + .verify = (verify_buf != NULL),
  43365. + },
  43366. + };
  43367. + struct spi_message m;
  43368. +
  43369. + if (rb4xx_cpld == NULL)
  43370. + return -ENODEV;
  43371. +
  43372. + spi_message_init(&m);
  43373. + m.fast_read = 1;
  43374. + spi_message_add_tail(&t[0], &m);
  43375. + spi_message_add_tail(&t[1], &m);
  43376. + return spi_sync(rb4xx_cpld->spi, &m);
  43377. +}
  43378. +EXPORT_SYMBOL_GPL(rb4xx_cpld_read_from);
  43379. +
  43380. +#if 0
  43381. +int rb4xx_cpld_read(unsigned char *buf, unsigned char *verify_buf,
  43382. + unsigned count)
  43383. +{
  43384. + struct spi_transfer t[2];
  43385. + struct spi_message m;
  43386. + unsigned char cmd[2];
  43387. +
  43388. + if (rb4xx_cpld == NULL)
  43389. + return -ENODEV;
  43390. +
  43391. + spi_message_init(&m);
  43392. + memset(&t, 0, sizeof(t));
  43393. +
  43394. + /* send command */
  43395. + t[0].tx_buf = cmd;
  43396. + t[0].len = sizeof(cmd);
  43397. + spi_message_add_tail(&t[0], &m);
  43398. +
  43399. + cmd[0] = CPLD_CMD_READ_NAND;
  43400. + cmd[1] = 0;
  43401. +
  43402. + /* read data */
  43403. + t[1].rx_buf = buf;
  43404. + t[1].len = count;
  43405. + spi_message_add_tail(&t[1], &m);
  43406. +
  43407. + return spi_sync(rb4xx_cpld->spi, &m);
  43408. +}
  43409. +#else
  43410. +int rb4xx_cpld_read(unsigned char *rx_buf, const unsigned char *verify_buf,
  43411. + unsigned count)
  43412. +{
  43413. + static const unsigned char cmd[2] = { CPLD_CMD_READ_NAND, 0 };
  43414. + struct spi_transfer t[2] = {
  43415. + {
  43416. + .tx_buf = &cmd,
  43417. + .len = 2,
  43418. + }, {
  43419. + .tx_buf = verify_buf,
  43420. + .rx_buf = rx_buf,
  43421. + .len = count,
  43422. + .verify = (verify_buf != NULL),
  43423. + },
  43424. + };
  43425. + struct spi_message m;
  43426. +
  43427. + if (rb4xx_cpld == NULL)
  43428. + return -ENODEV;
  43429. +
  43430. + spi_message_init(&m);
  43431. + spi_message_add_tail(&t[0], &m);
  43432. + spi_message_add_tail(&t[1], &m);
  43433. + return spi_sync(rb4xx_cpld->spi, &m);
  43434. +}
  43435. +#endif
  43436. +EXPORT_SYMBOL_GPL(rb4xx_cpld_read);
  43437. +
  43438. +int rb4xx_cpld_write(const unsigned char *buf, unsigned count)
  43439. +{
  43440. +#if 0
  43441. + struct spi_transfer t[3];
  43442. + struct spi_message m;
  43443. + unsigned char cmd[1];
  43444. +
  43445. + if (rb4xx_cpld == NULL)
  43446. + return -ENODEV;
  43447. +
  43448. + memset(&t, 0, sizeof(t));
  43449. + spi_message_init(&m);
  43450. +
  43451. + /* send command */
  43452. + t[0].tx_buf = cmd;
  43453. + t[0].len = sizeof(cmd);
  43454. + spi_message_add_tail(&t[0], &m);
  43455. +
  43456. + cmd[0] = CPLD_CMD_WRITE_NAND;
  43457. +
  43458. + /* write data */
  43459. + t[1].tx_buf = buf;
  43460. + t[1].len = count;
  43461. + spi_message_add_tail(&t[1], &m);
  43462. +
  43463. + /* send idle */
  43464. + t[2].len = 1;
  43465. + spi_message_add_tail(&t[2], &m);
  43466. +
  43467. + return spi_sync(rb4xx_cpld->spi, &m);
  43468. +#else
  43469. + static const unsigned char cmd = CPLD_CMD_WRITE_NAND;
  43470. + struct spi_transfer t[3] = {
  43471. + {
  43472. + .tx_buf = &cmd,
  43473. + .len = 1,
  43474. + }, {
  43475. + .tx_buf = buf,
  43476. + .len = count,
  43477. + .fast_write = 1,
  43478. + }, {
  43479. + .len = 1,
  43480. + .fast_write = 1,
  43481. + },
  43482. + };
  43483. + struct spi_message m;
  43484. +
  43485. + if (rb4xx_cpld == NULL)
  43486. + return -ENODEV;
  43487. +
  43488. + spi_message_init(&m);
  43489. + spi_message_add_tail(&t[0], &m);
  43490. + spi_message_add_tail(&t[1], &m);
  43491. + spi_message_add_tail(&t[2], &m);
  43492. + return spi_sync(rb4xx_cpld->spi, &m);
  43493. +#endif
  43494. +}
  43495. +EXPORT_SYMBOL_GPL(rb4xx_cpld_write);
  43496. +
  43497. +static int rb4xx_cpld_gpio_get(struct gpio_chip *chip, unsigned offset)
  43498. +{
  43499. + struct rb4xx_cpld *cpld = gpio_to_cpld(chip);
  43500. + int ret;
  43501. +
  43502. + mutex_lock(&cpld->lock);
  43503. + ret = (cpld->config >> offset) & 1;
  43504. + mutex_unlock(&cpld->lock);
  43505. +
  43506. + return ret;
  43507. +}
  43508. +
  43509. +static void rb4xx_cpld_gpio_set(struct gpio_chip *chip, unsigned offset,
  43510. + int value)
  43511. +{
  43512. + struct rb4xx_cpld *cpld = gpio_to_cpld(chip);
  43513. +
  43514. + mutex_lock(&cpld->lock);
  43515. + __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset);
  43516. + mutex_unlock(&cpld->lock);
  43517. +}
  43518. +
  43519. +static int rb4xx_cpld_gpio_direction_input(struct gpio_chip *chip,
  43520. + unsigned offset)
  43521. +{
  43522. + return -EOPNOTSUPP;
  43523. +}
  43524. +
  43525. +static int rb4xx_cpld_gpio_direction_output(struct gpio_chip *chip,
  43526. + unsigned offset,
  43527. + int value)
  43528. +{
  43529. + struct rb4xx_cpld *cpld = gpio_to_cpld(chip);
  43530. + int ret;
  43531. +
  43532. + mutex_lock(&cpld->lock);
  43533. + ret = __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset);
  43534. + mutex_unlock(&cpld->lock);
  43535. +
  43536. + return ret;
  43537. +}
  43538. +
  43539. +static int rb4xx_cpld_gpio_init(struct rb4xx_cpld *cpld, unsigned int base)
  43540. +{
  43541. + int err;
  43542. +
  43543. + /* init config */
  43544. + cpld->config = CPLD_CFG_nLED1 | CPLD_CFG_nLED2 | CPLD_CFG_nLED3 |
  43545. + CPLD_CFG_nLED4 | CPLD_CFG_nCE;
  43546. + rb4xx_cpld_write_cfg(cpld, cpld->config);
  43547. +
  43548. + /* setup GPIO chip */
  43549. + cpld->chip.label = DRV_NAME;
  43550. +
  43551. + cpld->chip.get = rb4xx_cpld_gpio_get;
  43552. + cpld->chip.set = rb4xx_cpld_gpio_set;
  43553. + cpld->chip.direction_input = rb4xx_cpld_gpio_direction_input;
  43554. + cpld->chip.direction_output = rb4xx_cpld_gpio_direction_output;
  43555. +
  43556. + cpld->chip.base = base;
  43557. + cpld->chip.ngpio = CPLD_NUM_GPIOS;
  43558. + cpld->chip.can_sleep = 1;
  43559. + cpld->chip.dev = &cpld->spi->dev;
  43560. + cpld->chip.owner = THIS_MODULE;
  43561. +
  43562. + err = gpiochip_add(&cpld->chip);
  43563. + if (err)
  43564. + dev_err(&cpld->spi->dev, "adding GPIO chip failed, err=%d\n",
  43565. + err);
  43566. +
  43567. + return err;
  43568. +}
  43569. +
  43570. +static int rb4xx_cpld_probe(struct spi_device *spi)
  43571. +{
  43572. + struct rb4xx_cpld *cpld;
  43573. + struct rb4xx_cpld_platform_data *pdata;
  43574. + int err;
  43575. +
  43576. + pdata = spi->dev.platform_data;
  43577. + if (!pdata) {
  43578. + dev_dbg(&spi->dev, "no platform data\n");
  43579. + return -EINVAL;
  43580. + }
  43581. +
  43582. + cpld = kzalloc(sizeof(*cpld), GFP_KERNEL);
  43583. + if (!cpld) {
  43584. + dev_err(&spi->dev, "no memory for private data\n");
  43585. + return -ENOMEM;
  43586. + }
  43587. +
  43588. + mutex_init(&cpld->lock);
  43589. + cpld->spi = spi_dev_get(spi);
  43590. + dev_set_drvdata(&spi->dev, cpld);
  43591. +
  43592. + spi->mode = SPI_MODE_0;
  43593. + spi->bits_per_word = 8;
  43594. + err = spi_setup(spi);
  43595. + if (err) {
  43596. + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err);
  43597. + goto err_drvdata;
  43598. + }
  43599. +
  43600. + err = rb4xx_cpld_gpio_init(cpld, pdata->gpio_base);
  43601. + if (err)
  43602. + goto err_drvdata;
  43603. +
  43604. + rb4xx_cpld = cpld;
  43605. +
  43606. + return 0;
  43607. +
  43608. +err_drvdata:
  43609. + dev_set_drvdata(&spi->dev, NULL);
  43610. + kfree(cpld);
  43611. +
  43612. + return err;
  43613. +}
  43614. +
  43615. +static int rb4xx_cpld_remove(struct spi_device *spi)
  43616. +{
  43617. + struct rb4xx_cpld *cpld;
  43618. +
  43619. + rb4xx_cpld = NULL;
  43620. + cpld = dev_get_drvdata(&spi->dev);
  43621. + dev_set_drvdata(&spi->dev, NULL);
  43622. + kfree(cpld);
  43623. +
  43624. + return 0;
  43625. +}
  43626. +
  43627. +static struct spi_driver rb4xx_cpld_driver = {
  43628. + .driver = {
  43629. + .name = DRV_NAME,
  43630. + .bus = &spi_bus_type,
  43631. + .owner = THIS_MODULE,
  43632. + },
  43633. + .probe = rb4xx_cpld_probe,
  43634. + .remove = rb4xx_cpld_remove,
  43635. +};
  43636. +
  43637. +static int __init rb4xx_cpld_init(void)
  43638. +{
  43639. + return spi_register_driver(&rb4xx_cpld_driver);
  43640. +}
  43641. +module_init(rb4xx_cpld_init);
  43642. +
  43643. +static void __exit rb4xx_cpld_exit(void)
  43644. +{
  43645. + spi_unregister_driver(&rb4xx_cpld_driver);
  43646. +}
  43647. +module_exit(rb4xx_cpld_exit);
  43648. +
  43649. +MODULE_DESCRIPTION(DRV_DESC);
  43650. +MODULE_VERSION(DRV_VERSION);
  43651. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  43652. +MODULE_LICENSE("GPL v2");
  43653. diff -Nur linux-4.1.43.orig/drivers/spi/spi-rb4xx.c linux-4.1.43/drivers/spi/spi-rb4xx.c
  43654. --- linux-4.1.43.orig/drivers/spi/spi-rb4xx.c 1970-01-01 01:00:00.000000000 +0100
  43655. +++ linux-4.1.43/drivers/spi/spi-rb4xx.c 2017-08-06 20:02:16.000000000 +0200
  43656. @@ -0,0 +1,507 @@
  43657. +/*
  43658. + * SPI controller driver for the Mikrotik RB4xx boards
  43659. + *
  43660. + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  43661. + *
  43662. + * This file was based on the patches for Linux 2.6.27.39 published by
  43663. + * MikroTik for their RouterBoard 4xx series devices.
  43664. + *
  43665. + * This program is free software; you can redistribute it and/or modify
  43666. + * it under the terms of the GNU General Public License version 2 as
  43667. + * published by the Free Software Foundation.
  43668. + *
  43669. + */
  43670. +
  43671. +#include <linux/clk.h>
  43672. +#include <linux/err.h>
  43673. +#include <linux/kernel.h>
  43674. +#include <linux/module.h>
  43675. +#include <linux/init.h>
  43676. +#include <linux/delay.h>
  43677. +#include <linux/spinlock.h>
  43678. +#include <linux/workqueue.h>
  43679. +#include <linux/platform_device.h>
  43680. +#include <linux/spi/spi.h>
  43681. +
  43682. +#include <asm/mach-ath79/ar71xx_regs.h>
  43683. +#include <asm/mach-ath79/ath79.h>
  43684. +
  43685. +#define DRV_NAME "rb4xx-spi"
  43686. +#define DRV_DESC "Mikrotik RB4xx SPI controller driver"
  43687. +#define DRV_VERSION "0.1.0"
  43688. +
  43689. +#define SPI_CTRL_FASTEST 0x40
  43690. +#define SPI_FLASH_HZ 33333334
  43691. +#define SPI_CPLD_HZ 33333334
  43692. +
  43693. +#define CPLD_CMD_READ_FAST 0x0b
  43694. +
  43695. +#undef RB4XX_SPI_DEBUG
  43696. +
  43697. +struct rb4xx_spi {
  43698. + void __iomem *base;
  43699. + struct spi_master *master;
  43700. +
  43701. + unsigned spi_ctrl_flash;
  43702. + unsigned spi_ctrl_fread;
  43703. +
  43704. + struct clk *ahb_clk;
  43705. + unsigned long ahb_freq;
  43706. +
  43707. + spinlock_t lock;
  43708. + struct list_head queue;
  43709. + int busy:1;
  43710. + int cs_wait;
  43711. +};
  43712. +
  43713. +static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
  43714. +
  43715. +#ifdef RB4XX_SPI_DEBUG
  43716. +static inline void do_spi_delay(void)
  43717. +{
  43718. + ndelay(20000);
  43719. +}
  43720. +#else
  43721. +static inline void do_spi_delay(void) { }
  43722. +#endif
  43723. +
  43724. +static inline void do_spi_init(struct spi_device *spi)
  43725. +{
  43726. + unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
  43727. +
  43728. + if (!(spi->mode & SPI_CS_HIGH))
  43729. + cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
  43730. + AR71XX_SPI_IOC_CS0;
  43731. +
  43732. + spi_clk_low = cs;
  43733. +}
  43734. +
  43735. +static inline void do_spi_finish(void __iomem *base)
  43736. +{
  43737. + do_spi_delay();
  43738. + __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
  43739. + base + AR71XX_SPI_REG_IOC);
  43740. +}
  43741. +
  43742. +static inline void do_spi_clk(void __iomem *base, int bit)
  43743. +{
  43744. + unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
  43745. +
  43746. + do_spi_delay();
  43747. + __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
  43748. + do_spi_delay();
  43749. + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
  43750. +}
  43751. +
  43752. +static void do_spi_byte(void __iomem *base, unsigned char byte)
  43753. +{
  43754. + do_spi_clk(base, byte >> 7);
  43755. + do_spi_clk(base, byte >> 6);
  43756. + do_spi_clk(base, byte >> 5);
  43757. + do_spi_clk(base, byte >> 4);
  43758. + do_spi_clk(base, byte >> 3);
  43759. + do_spi_clk(base, byte >> 2);
  43760. + do_spi_clk(base, byte >> 1);
  43761. + do_spi_clk(base, byte);
  43762. +
  43763. + pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
  43764. + (unsigned)byte,
  43765. + (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
  43766. +}
  43767. +
  43768. +static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
  43769. + unsigned bit2)
  43770. +{
  43771. + unsigned bval = (spi_clk_low |
  43772. + ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
  43773. + ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
  43774. + do_spi_delay();
  43775. + __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
  43776. + do_spi_delay();
  43777. + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
  43778. +}
  43779. +
  43780. +static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
  43781. +{
  43782. + do_spi_clk_fast(base, byte >> 7, byte >> 6);
  43783. + do_spi_clk_fast(base, byte >> 5, byte >> 4);
  43784. + do_spi_clk_fast(base, byte >> 3, byte >> 2);
  43785. + do_spi_clk_fast(base, byte >> 1, byte >> 0);
  43786. +
  43787. + pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
  43788. + (unsigned)byte,
  43789. + (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
  43790. +}
  43791. +
  43792. +static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
  43793. +{
  43794. + const unsigned char *rxv_ptr = NULL;
  43795. + const unsigned char *tx_ptr = t->tx_buf;
  43796. + unsigned char *rx_ptr = t->rx_buf;
  43797. + unsigned i;
  43798. +
  43799. + pr_debug("spi_txrx len %u tx %u rx %u\n",
  43800. + t->len,
  43801. + (t->tx_buf ? 1 : 0),
  43802. + (t->rx_buf ? 1 : 0));
  43803. +
  43804. + if (t->verify) {
  43805. + rxv_ptr = tx_ptr;
  43806. + tx_ptr = NULL;
  43807. + }
  43808. +
  43809. + for (i = 0; i < t->len; ++i) {
  43810. + unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
  43811. +
  43812. + if (t->fast_write)
  43813. + do_spi_byte_fast(base, sdata);
  43814. + else
  43815. + do_spi_byte(base, sdata);
  43816. +
  43817. + if (rx_ptr) {
  43818. + rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
  43819. + } else if (rxv_ptr) {
  43820. + unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS);
  43821. + if (rxv_ptr[i] != c)
  43822. + return i;
  43823. + }
  43824. + }
  43825. +
  43826. + return i;
  43827. +}
  43828. +
  43829. +static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi,
  43830. + struct spi_message *m)
  43831. +{
  43832. + struct spi_transfer *t;
  43833. + const unsigned char *tx_ptr;
  43834. + unsigned addr;
  43835. + void __iomem *base = rbspi->base;
  43836. +
  43837. + /* check for exactly two transfers */
  43838. + if (list_empty(&m->transfers) ||
  43839. + list_is_last(m->transfers.next, &m->transfers) ||
  43840. + !list_is_last(m->transfers.next->next, &m->transfers)) {
  43841. + return -1;
  43842. + }
  43843. +
  43844. + /* first transfer contains command and address */
  43845. + t = list_entry(m->transfers.next,
  43846. + struct spi_transfer, transfer_list);
  43847. +
  43848. + if (t->len != 5 || t->tx_buf == NULL)
  43849. + return -1;
  43850. +
  43851. + tx_ptr = t->tx_buf;
  43852. + if (tx_ptr[0] != CPLD_CMD_READ_FAST)
  43853. + return -1;
  43854. +
  43855. + addr = tx_ptr[1];
  43856. + addr = tx_ptr[2] | (addr << 8);
  43857. + addr = tx_ptr[3] | (addr << 8);
  43858. + addr += (unsigned) base;
  43859. +
  43860. + m->actual_length += t->len;
  43861. +
  43862. + /* second transfer contains data itself */
  43863. + t = list_entry(m->transfers.next->next,
  43864. + struct spi_transfer, transfer_list);
  43865. +
  43866. + if (t->tx_buf && !t->verify)
  43867. + return -1;
  43868. +
  43869. + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
  43870. + __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL);
  43871. + __raw_writel(0, base + AR71XX_SPI_REG_FS);
  43872. +
  43873. + if (t->rx_buf) {
  43874. + memcpy(t->rx_buf, (const void *)addr, t->len);
  43875. + } else if (t->tx_buf) {
  43876. + unsigned char buf[t->len];
  43877. + memcpy(buf, (const void *)addr, t->len);
  43878. + if (memcmp(t->tx_buf, buf, t->len) != 0)
  43879. + m->status = -EMSGSIZE;
  43880. + }
  43881. + m->actual_length += t->len;
  43882. +
  43883. + if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
  43884. + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
  43885. + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
  43886. + __raw_writel(0, base + AR71XX_SPI_REG_FS);
  43887. + }
  43888. +
  43889. + return 0;
  43890. +}
  43891. +
  43892. +static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
  43893. +{
  43894. + struct spi_transfer *t = NULL;
  43895. + void __iomem *base = rbspi->base;
  43896. +
  43897. + m->status = 0;
  43898. + if (list_empty(&m->transfers))
  43899. + return -1;
  43900. +
  43901. + if (m->fast_read)
  43902. + if (rb4xx_spi_read_fast(rbspi, m) == 0)
  43903. + return -1;
  43904. +
  43905. + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
  43906. + __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
  43907. + do_spi_init(m->spi);
  43908. +
  43909. + list_for_each_entry(t, &m->transfers, transfer_list) {
  43910. + int len;
  43911. +
  43912. + len = rb4xx_spi_txrx(base, t);
  43913. + if (len != t->len) {
  43914. + m->status = -EMSGSIZE;
  43915. + break;
  43916. + }
  43917. + m->actual_length += len;
  43918. +
  43919. + if (t->cs_change) {
  43920. + if (list_is_last(&t->transfer_list, &m->transfers)) {
  43921. + /* wait for continuation */
  43922. + return m->spi->chip_select;
  43923. + }
  43924. + do_spi_finish(base);
  43925. + ndelay(100);
  43926. + }
  43927. + }
  43928. +
  43929. + do_spi_finish(base);
  43930. + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
  43931. + __raw_writel(0, base + AR71XX_SPI_REG_FS);
  43932. + return -1;
  43933. +}
  43934. +
  43935. +static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
  43936. + unsigned long *flags)
  43937. +{
  43938. + int cs = rbspi->cs_wait;
  43939. +
  43940. + rbspi->busy = 1;
  43941. + while (!list_empty(&rbspi->queue)) {
  43942. + struct spi_message *m;
  43943. +
  43944. + list_for_each_entry(m, &rbspi->queue, queue)
  43945. + if (cs < 0 || cs == m->spi->chip_select)
  43946. + break;
  43947. +
  43948. + if (&m->queue == &rbspi->queue)
  43949. + break;
  43950. +
  43951. + list_del_init(&m->queue);
  43952. + spin_unlock_irqrestore(&rbspi->lock, *flags);
  43953. +
  43954. + cs = rb4xx_spi_msg(rbspi, m);
  43955. + m->complete(m->context);
  43956. +
  43957. + spin_lock_irqsave(&rbspi->lock, *flags);
  43958. + }
  43959. +
  43960. + rbspi->cs_wait = cs;
  43961. + rbspi->busy = 0;
  43962. +
  43963. + if (cs >= 0) {
  43964. + /* TODO: add timer to unlock cs after 1s inactivity */
  43965. + }
  43966. +}
  43967. +
  43968. +static int rb4xx_spi_transfer(struct spi_device *spi,
  43969. + struct spi_message *m)
  43970. +{
  43971. + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
  43972. + unsigned long flags;
  43973. +
  43974. + m->actual_length = 0;
  43975. + m->status = -EINPROGRESS;
  43976. +
  43977. + spin_lock_irqsave(&rbspi->lock, flags);
  43978. + list_add_tail(&m->queue, &rbspi->queue);
  43979. + if (rbspi->busy ||
  43980. + (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
  43981. + /* job will be done later */
  43982. + spin_unlock_irqrestore(&rbspi->lock, flags);
  43983. + return 0;
  43984. + }
  43985. +
  43986. + /* process job in current context */
  43987. + rb4xx_spi_process_queue_locked(rbspi, &flags);
  43988. + spin_unlock_irqrestore(&rbspi->lock, flags);
  43989. +
  43990. + return 0;
  43991. +}
  43992. +
  43993. +static int rb4xx_spi_setup(struct spi_device *spi)
  43994. +{
  43995. + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
  43996. + unsigned long flags;
  43997. +
  43998. + if (spi->mode & ~(SPI_CS_HIGH)) {
  43999. + dev_err(&spi->dev, "mode %x not supported\n",
  44000. + (unsigned) spi->mode);
  44001. + return -EINVAL;
  44002. + }
  44003. +
  44004. + if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
  44005. + dev_err(&spi->dev, "bits_per_word %u not supported\n",
  44006. + (unsigned) spi->bits_per_word);
  44007. + return -EINVAL;
  44008. + }
  44009. +
  44010. + spin_lock_irqsave(&rbspi->lock, flags);
  44011. + if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
  44012. + rbspi->cs_wait = -1;
  44013. + rb4xx_spi_process_queue_locked(rbspi, &flags);
  44014. + }
  44015. + spin_unlock_irqrestore(&rbspi->lock, flags);
  44016. +
  44017. + return 0;
  44018. +}
  44019. +
  44020. +static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
  44021. + const char *name)
  44022. +{
  44023. + unsigned div;
  44024. +
  44025. + div = (rbspi->ahb_freq - 1) / (2 * hz_max);
  44026. +
  44027. + /*
  44028. + * CPU has a bug at (div == 0) - first bit read is random
  44029. + */
  44030. + if (div == 0)
  44031. + ++div;
  44032. +
  44033. + if (name) {
  44034. + unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
  44035. + unsigned div_real = 2 * (div + 1);
  44036. + pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
  44037. + name,
  44038. + ahb_khz / div_real,
  44039. + ahb_khz, div_real);
  44040. + }
  44041. +
  44042. + return SPI_CTRL_FASTEST + div;
  44043. +}
  44044. +
  44045. +static int rb4xx_spi_probe(struct platform_device *pdev)
  44046. +{
  44047. + struct spi_master *master;
  44048. + struct rb4xx_spi *rbspi;
  44049. + struct resource *r;
  44050. + int err = 0;
  44051. +
  44052. + master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
  44053. + if (master == NULL) {
  44054. + dev_err(&pdev->dev, "no memory for spi_master\n");
  44055. + err = -ENOMEM;
  44056. + goto err_out;
  44057. + }
  44058. +
  44059. + master->bus_num = 0;
  44060. + master->num_chipselect = 3;
  44061. + master->setup = rb4xx_spi_setup;
  44062. + master->transfer = rb4xx_spi_transfer;
  44063. +
  44064. + rbspi = spi_master_get_devdata(master);
  44065. +
  44066. + rbspi->ahb_clk = clk_get(&pdev->dev, "ahb");
  44067. + if (IS_ERR(rbspi->ahb_clk)) {
  44068. + err = PTR_ERR(rbspi->ahb_clk);
  44069. + goto err_put_master;
  44070. + }
  44071. +
  44072. + err = clk_enable(rbspi->ahb_clk);
  44073. + if (err)
  44074. + goto err_clk_put;
  44075. +
  44076. + rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
  44077. + if (!rbspi->ahb_freq) {
  44078. + err = -EINVAL;
  44079. + goto err_clk_disable;
  44080. + }
  44081. +
  44082. + platform_set_drvdata(pdev, rbspi);
  44083. +
  44084. + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  44085. + if (r == NULL) {
  44086. + err = -ENOENT;
  44087. + goto err_clk_disable;
  44088. + }
  44089. +
  44090. + rbspi->base = ioremap(r->start, r->end - r->start + 1);
  44091. + if (!rbspi->base) {
  44092. + err = -ENXIO;
  44093. + goto err_clk_disable;
  44094. + }
  44095. +
  44096. + rbspi->master = master;
  44097. + rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
  44098. + rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
  44099. + rbspi->cs_wait = -1;
  44100. +
  44101. + spin_lock_init(&rbspi->lock);
  44102. + INIT_LIST_HEAD(&rbspi->queue);
  44103. +
  44104. + err = spi_register_master(master);
  44105. + if (err) {
  44106. + dev_err(&pdev->dev, "failed to register SPI master\n");
  44107. + goto err_iounmap;
  44108. + }
  44109. +
  44110. + return 0;
  44111. +
  44112. +err_iounmap:
  44113. + iounmap(rbspi->base);
  44114. +err_clk_disable:
  44115. + clk_disable(rbspi->ahb_clk);
  44116. +err_clk_put:
  44117. + clk_put(rbspi->ahb_clk);
  44118. +err_put_master:
  44119. + platform_set_drvdata(pdev, NULL);
  44120. + spi_master_put(master);
  44121. +err_out:
  44122. + return err;
  44123. +}
  44124. +
  44125. +static int rb4xx_spi_remove(struct platform_device *pdev)
  44126. +{
  44127. + struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
  44128. +
  44129. + iounmap(rbspi->base);
  44130. + clk_disable(rbspi->ahb_clk);
  44131. + clk_put(rbspi->ahb_clk);
  44132. + platform_set_drvdata(pdev, NULL);
  44133. + spi_master_put(rbspi->master);
  44134. +
  44135. + return 0;
  44136. +}
  44137. +
  44138. +static struct platform_driver rb4xx_spi_drv = {
  44139. + .probe = rb4xx_spi_probe,
  44140. + .remove = rb4xx_spi_remove,
  44141. + .driver = {
  44142. + .name = DRV_NAME,
  44143. + .owner = THIS_MODULE,
  44144. + },
  44145. +};
  44146. +
  44147. +static int __init rb4xx_spi_init(void)
  44148. +{
  44149. + return platform_driver_register(&rb4xx_spi_drv);
  44150. +}
  44151. +subsys_initcall(rb4xx_spi_init);
  44152. +
  44153. +static void __exit rb4xx_spi_exit(void)
  44154. +{
  44155. + platform_driver_unregister(&rb4xx_spi_drv);
  44156. +}
  44157. +
  44158. +module_exit(rb4xx_spi_exit);
  44159. +
  44160. +MODULE_DESCRIPTION(DRV_DESC);
  44161. +MODULE_VERSION(DRV_VERSION);
  44162. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  44163. +MODULE_LICENSE("GPL v2");
  44164. diff -Nur linux-4.1.43.orig/drivers/spi/spi-vsc7385.c linux-4.1.43/drivers/spi/spi-vsc7385.c
  44165. --- linux-4.1.43.orig/drivers/spi/spi-vsc7385.c 1970-01-01 01:00:00.000000000 +0100
  44166. +++ linux-4.1.43/drivers/spi/spi-vsc7385.c 2017-08-06 20:02:16.000000000 +0200
  44167. @@ -0,0 +1,621 @@
  44168. +/*
  44169. + * SPI driver for the Vitesse VSC7385 ethernet switch
  44170. + *
  44171. + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  44172. + *
  44173. + * Parts of this file are based on Atheros' 2.6.15 BSP
  44174. + *
  44175. + * This program is free software; you can redistribute it and/or modify it
  44176. + * under the terms of the GNU General Public License version 2 as published
  44177. + * by the Free Software Foundation.
  44178. + */
  44179. +
  44180. +#include <linux/types.h>
  44181. +#include <linux/kernel.h>
  44182. +#include <linux/init.h>
  44183. +#include <linux/module.h>
  44184. +#include <linux/delay.h>
  44185. +#include <linux/device.h>
  44186. +#include <linux/bitops.h>
  44187. +#include <linux/firmware.h>
  44188. +#include <linux/spi/spi.h>
  44189. +#include <linux/spi/vsc7385.h>
  44190. +
  44191. +#define DRV_NAME "spi-vsc7385"
  44192. +#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver"
  44193. +#define DRV_VERSION "0.1.0"
  44194. +
  44195. +#define VSC73XX_BLOCK_MAC 0x1
  44196. +#define VSC73XX_BLOCK_2 0x2
  44197. +#define VSC73XX_BLOCK_MII 0x3
  44198. +#define VSC73XX_BLOCK_4 0x4
  44199. +#define VSC73XX_BLOCK_5 0x5
  44200. +#define VSC73XX_BLOCK_SYSTEM 0x7
  44201. +
  44202. +#define VSC73XX_SUBBLOCK_PORT_0 0
  44203. +#define VSC73XX_SUBBLOCK_PORT_1 1
  44204. +#define VSC73XX_SUBBLOCK_PORT_2 2
  44205. +#define VSC73XX_SUBBLOCK_PORT_3 3
  44206. +#define VSC73XX_SUBBLOCK_PORT_4 4
  44207. +#define VSC73XX_SUBBLOCK_PORT_MAC 6
  44208. +
  44209. +/* MAC Block registers */
  44210. +#define VSC73XX_MAC_CFG 0x0
  44211. +#define VSC73XX_ADVPORTM 0x19
  44212. +#define VSC73XX_RXOCT 0x50
  44213. +#define VSC73XX_TXOCT 0x51
  44214. +#define VSC73XX_C_RX0 0x52
  44215. +#define VSC73XX_C_RX1 0x53
  44216. +#define VSC73XX_C_RX2 0x54
  44217. +#define VSC73XX_C_TX0 0x55
  44218. +#define VSC73XX_C_TX1 0x56
  44219. +#define VSC73XX_C_TX2 0x57
  44220. +#define VSC73XX_C_CFG 0x58
  44221. +
  44222. +/* MAC_CFG register bits */
  44223. +#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31)
  44224. +#define VSC73XX_MAC_CFG_PORT_RST (1 << 29)
  44225. +#define VSC73XX_MAC_CFG_TX_EN (1 << 28)
  44226. +#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27)
  44227. +#define VSC73XX_MAC_CFG_FDX (1 << 18)
  44228. +#define VSC73XX_MAC_CFG_GIGE (1 << 17)
  44229. +#define VSC73XX_MAC_CFG_RX_EN (1 << 16)
  44230. +#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15)
  44231. +#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14)
  44232. +#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13)
  44233. +#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6)
  44234. +#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5)
  44235. +#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4)
  44236. +#define VSC73XX_MAC_CFG_BIT2 (1 << 2)
  44237. +#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3)
  44238. +
  44239. +/* ADVPORTM register bits */
  44240. +#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7)
  44241. +#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6)
  44242. +#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5)
  44243. +#define VSC73XX_ADVPORTM_INV_GTX (1 << 4)
  44244. +#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3)
  44245. +#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2)
  44246. +#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1)
  44247. +#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0)
  44248. +
  44249. +/* MII Block registers */
  44250. +#define VSC73XX_MII_STAT 0x0
  44251. +#define VSC73XX_MII_CMD 0x1
  44252. +#define VSC73XX_MII_DATA 0x2
  44253. +
  44254. +/* System Block registers */
  44255. +#define VSC73XX_ICPU_SIPAD 0x01
  44256. +#define VSC73XX_ICPU_CLOCK_DELAY 0x05
  44257. +#define VSC73XX_ICPU_CTRL 0x10
  44258. +#define VSC73XX_ICPU_ADDR 0x11
  44259. +#define VSC73XX_ICPU_SRAM 0x12
  44260. +#define VSC73XX_ICPU_MBOX_VAL 0x15
  44261. +#define VSC73XX_ICPU_MBOX_SET 0x16
  44262. +#define VSC73XX_ICPU_MBOX_CLR 0x17
  44263. +#define VSC73XX_ICPU_CHIPID 0x18
  44264. +#define VSC73XX_ICPU_GPIO 0x34
  44265. +
  44266. +#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8)
  44267. +#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7)
  44268. +#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3)
  44269. +#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2)
  44270. +#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1)
  44271. +#define VSC73XX_ICPU_CTRL_SRST (1 << 0)
  44272. +
  44273. +#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12
  44274. +#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff
  44275. +#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28
  44276. +#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf
  44277. +#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385
  44278. +#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395
  44279. +
  44280. +#define VSC73XX_CMD_MODE_READ 0
  44281. +#define VSC73XX_CMD_MODE_WRITE 1
  44282. +#define VSC73XX_CMD_MODE_SHIFT 4
  44283. +#define VSC73XX_CMD_BLOCK_SHIFT 5
  44284. +#define VSC73XX_CMD_BLOCK_MASK 0x7
  44285. +#define VSC73XX_CMD_SUBBLOCK_MASK 0xf
  44286. +
  44287. +#define VSC7385_CLOCK_DELAY ((3 << 4) | 3)
  44288. +#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3)
  44289. +
  44290. +#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \
  44291. + VSC73XX_ICPU_CTRL_BOOT_EN | \
  44292. + VSC73XX_ICPU_CTRL_EXT_ACC_EN)
  44293. +
  44294. +#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \
  44295. + VSC73XX_ICPU_CTRL_BOOT_EN | \
  44296. + VSC73XX_ICPU_CTRL_CLK_EN | \
  44297. + VSC73XX_ICPU_CTRL_SRST)
  44298. +
  44299. +#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \
  44300. + VSC73XX_ADVPORTM_EXC_COL_CONT | \
  44301. + VSC73XX_ADVPORTM_EXT_PORT | \
  44302. + VSC73XX_ADVPORTM_INV_GTX | \
  44303. + VSC73XX_ADVPORTM_ENA_GTX | \
  44304. + VSC73XX_ADVPORTM_DDR_MODE | \
  44305. + VSC73XX_ADVPORTM_IO_LOOPBACK | \
  44306. + VSC73XX_ADVPORTM_HOST_LOOPBACK)
  44307. +
  44308. +#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \
  44309. + VSC73XX_ADVPORTM_ENA_GTX | \
  44310. + VSC73XX_ADVPORTM_DDR_MODE)
  44311. +
  44312. +#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \
  44313. + VSC73XX_MAC_CFG_MAC_RX_RST | \
  44314. + VSC73XX_MAC_CFG_MAC_TX_RST)
  44315. +
  44316. +#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \
  44317. + VSC73XX_MAC_CFG_FDX | \
  44318. + VSC73XX_MAC_CFG_GIGE | \
  44319. + VSC73XX_MAC_CFG_RX_EN)
  44320. +
  44321. +#define VSC73XX_RESET_DELAY 100
  44322. +
  44323. +struct vsc7385 {
  44324. + struct spi_device *spi;
  44325. + struct mutex lock;
  44326. + struct vsc7385_platform_data *pdata;
  44327. +};
  44328. +
  44329. +static int vsc7385_is_addr_valid(u8 block, u8 subblock)
  44330. +{
  44331. + switch (block) {
  44332. + case VSC73XX_BLOCK_MAC:
  44333. + switch (subblock) {
  44334. + case 0 ... 4:
  44335. + case 6:
  44336. + return 1;
  44337. + }
  44338. + break;
  44339. +
  44340. + case VSC73XX_BLOCK_2:
  44341. + case VSC73XX_BLOCK_SYSTEM:
  44342. + switch (subblock) {
  44343. + case 0:
  44344. + return 1;
  44345. + }
  44346. + break;
  44347. +
  44348. + case VSC73XX_BLOCK_MII:
  44349. + case VSC73XX_BLOCK_4:
  44350. + case VSC73XX_BLOCK_5:
  44351. + switch (subblock) {
  44352. + case 0 ... 1:
  44353. + return 1;
  44354. + }
  44355. + break;
  44356. + }
  44357. +
  44358. + return 0;
  44359. +}
  44360. +
  44361. +static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock)
  44362. +{
  44363. + u8 ret;
  44364. +
  44365. + ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT;
  44366. + ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT;
  44367. + ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK;
  44368. +
  44369. + return ret;
  44370. +}
  44371. +
  44372. +static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
  44373. + u32 *value)
  44374. +{
  44375. + u8 cmd[4];
  44376. + u8 buf[4];
  44377. + struct spi_transfer t[2];
  44378. + struct spi_message m;
  44379. + int err;
  44380. +
  44381. + if (!vsc7385_is_addr_valid(block, subblock))
  44382. + return -EINVAL;
  44383. +
  44384. + spi_message_init(&m);
  44385. +
  44386. + memset(&t, 0, sizeof(t));
  44387. +
  44388. + t[0].tx_buf = cmd;
  44389. + t[0].len = sizeof(cmd);
  44390. + spi_message_add_tail(&t[0], &m);
  44391. +
  44392. + t[1].rx_buf = buf;
  44393. + t[1].len = sizeof(buf);
  44394. + spi_message_add_tail(&t[1], &m);
  44395. +
  44396. + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock);
  44397. + cmd[1] = reg;
  44398. + cmd[2] = 0;
  44399. + cmd[3] = 0;
  44400. +
  44401. + mutex_lock(&vsc->lock);
  44402. + err = spi_sync(vsc->spi, &m);
  44403. + mutex_unlock(&vsc->lock);
  44404. +
  44405. + if (err)
  44406. + return err;
  44407. +
  44408. + *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) |
  44409. + (((u32) buf[2]) << 8) | ((u32) buf[3]);
  44410. +
  44411. + return 0;
  44412. +}
  44413. +
  44414. +
  44415. +static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
  44416. + u32 value)
  44417. +{
  44418. + u8 cmd[2];
  44419. + u8 buf[4];
  44420. + struct spi_transfer t[2];
  44421. + struct spi_message m;
  44422. + int err;
  44423. +
  44424. + if (!vsc7385_is_addr_valid(block, subblock))
  44425. + return -EINVAL;
  44426. +
  44427. + spi_message_init(&m);
  44428. +
  44429. + memset(&t, 0, sizeof(t));
  44430. +
  44431. + t[0].tx_buf = cmd;
  44432. + t[0].len = sizeof(cmd);
  44433. + spi_message_add_tail(&t[0], &m);
  44434. +
  44435. + t[1].tx_buf = buf;
  44436. + t[1].len = sizeof(buf);
  44437. + spi_message_add_tail(&t[1], &m);
  44438. +
  44439. + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock);
  44440. + cmd[1] = reg;
  44441. +
  44442. + buf[0] = (value >> 24) & 0xff;
  44443. + buf[1] = (value >> 16) & 0xff;
  44444. + buf[2] = (value >> 8) & 0xff;
  44445. + buf[3] = value & 0xff;
  44446. +
  44447. + mutex_lock(&vsc->lock);
  44448. + err = spi_sync(vsc->spi, &m);
  44449. + mutex_unlock(&vsc->lock);
  44450. +
  44451. + return err;
  44452. +}
  44453. +
  44454. +static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block,
  44455. + u8 subblock, u8 reg, u32 value,
  44456. + u32 read_mask, u32 read_val)
  44457. +{
  44458. + struct spi_device *spi = vsc->spi;
  44459. + u32 t;
  44460. + int err;
  44461. +
  44462. + err = vsc7385_write(vsc, block, subblock, reg, value);
  44463. + if (err)
  44464. + return err;
  44465. +
  44466. + err = vsc7385_read(vsc, block, subblock, reg, &t);
  44467. + if (err)
  44468. + return err;
  44469. +
  44470. + if ((t & read_mask) != read_val) {
  44471. + dev_err(&spi->dev, "register write error\n");
  44472. + return -EIO;
  44473. + }
  44474. +
  44475. + return 0;
  44476. +}
  44477. +
  44478. +static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val)
  44479. +{
  44480. + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
  44481. + VSC73XX_ICPU_CLOCK_DELAY, val);
  44482. +}
  44483. +
  44484. +static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val)
  44485. +{
  44486. + return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
  44487. + VSC73XX_ICPU_CLOCK_DELAY, val);
  44488. +}
  44489. +
  44490. +static inline int vsc7385_icpu_stop(struct vsc7385 *vsc)
  44491. +{
  44492. + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
  44493. + VSC73XX_ICPU_CTRL_STOP);
  44494. +}
  44495. +
  44496. +static inline int vsc7385_icpu_start(struct vsc7385 *vsc)
  44497. +{
  44498. + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
  44499. + VSC73XX_ICPU_CTRL_START);
  44500. +}
  44501. +
  44502. +static inline int vsc7385_icpu_reset(struct vsc7385 *vsc)
  44503. +{
  44504. + int rc;
  44505. +
  44506. + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR,
  44507. + 0x0000);
  44508. + if (rc)
  44509. + dev_err(&vsc->spi->dev,
  44510. + "could not reset microcode, err=%d\n", rc);
  44511. +
  44512. + return rc;
  44513. +}
  44514. +
  44515. +static int vsc7385_upload_ucode(struct vsc7385 *vsc)
  44516. +{
  44517. + struct spi_device *spi = vsc->spi;
  44518. + const struct firmware *firmware;
  44519. + char *ucode_name;
  44520. + unsigned char *dp;
  44521. + unsigned int curVal;
  44522. + int i;
  44523. + int diffs;
  44524. + int rc;
  44525. +
  44526. + ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name
  44527. + : "vsc7385_ucode.bin";
  44528. + rc = request_firmware(&firmware, ucode_name, &spi->dev);
  44529. + if (rc) {
  44530. + dev_err(&spi->dev, "request_firmware failed, err=%d\n",
  44531. + rc);
  44532. + return rc;
  44533. + }
  44534. +
  44535. + rc = vsc7385_icpu_stop(vsc);
  44536. + if (rc)
  44537. + goto out;
  44538. +
  44539. + rc = vsc7385_icpu_reset(vsc);
  44540. + if (rc)
  44541. + goto out;
  44542. +
  44543. + dev_info(&spi->dev, "uploading microcode...\n");
  44544. +
  44545. + dp = (unsigned char *) firmware->data;
  44546. + for (i = 0; i < firmware->size; i++) {
  44547. + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
  44548. + VSC73XX_ICPU_SRAM, *dp++);
  44549. + if (rc) {
  44550. + dev_err(&spi->dev, "could not load microcode, err=%d\n",
  44551. + rc);
  44552. + goto out;
  44553. + }
  44554. + }
  44555. +
  44556. + rc = vsc7385_icpu_reset(vsc);
  44557. + if (rc)
  44558. + goto out;
  44559. +
  44560. + dev_info(&spi->dev, "verifying microcode...\n");
  44561. +
  44562. + dp = (unsigned char *) firmware->data;
  44563. + diffs = 0;
  44564. + for (i = 0; i < firmware->size; i++) {
  44565. + rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
  44566. + VSC73XX_ICPU_SRAM, &curVal);
  44567. + if (rc) {
  44568. + dev_err(&spi->dev, "could not read microcode %d\n",
  44569. + rc);
  44570. + goto out;
  44571. + }
  44572. +
  44573. + if (curVal > 0xff) {
  44574. + dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n",
  44575. + i, *dp, curVal);
  44576. + rc = -EIO;
  44577. + goto out;
  44578. + }
  44579. +
  44580. + if ((curVal & 0xff) != *dp) {
  44581. + diffs++;
  44582. + dev_err(&spi->dev, "verify error: %04x : %02x %02x\n",
  44583. + i, *dp, curVal);
  44584. +
  44585. + if (diffs > 4)
  44586. + break;
  44587. + }
  44588. + dp++;
  44589. + }
  44590. +
  44591. + if (diffs) {
  44592. + dev_err(&spi->dev, "microcode verification failed\n");
  44593. + rc = -EIO;
  44594. + goto out;
  44595. + }
  44596. +
  44597. + dev_info(&spi->dev, "microcode uploaded\n");
  44598. +
  44599. + rc = vsc7385_icpu_start(vsc);
  44600. +
  44601. +out:
  44602. + release_firmware(firmware);
  44603. + return rc;
  44604. +}
  44605. +
  44606. +static int vsc7385_setup(struct vsc7385 *vsc)
  44607. +{
  44608. + struct vsc7385_platform_data *pdata = vsc->pdata;
  44609. + u32 t;
  44610. + int err;
  44611. +
  44612. + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0,
  44613. + VSC73XX_ICPU_CLOCK_DELAY,
  44614. + VSC7385_CLOCK_DELAY,
  44615. + VSC7385_CLOCK_DELAY_MASK,
  44616. + VSC7385_CLOCK_DELAY);
  44617. + if (err)
  44618. + goto err;
  44619. +
  44620. + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC,
  44621. + VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM,
  44622. + VSC7385_ADVPORTM_INIT,
  44623. + VSC7385_ADVPORTM_MASK,
  44624. + VSC7385_ADVPORTM_INIT);
  44625. + if (err)
  44626. + goto err;
  44627. +
  44628. + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
  44629. + VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET);
  44630. + if (err)
  44631. + goto err;
  44632. +
  44633. + t = VSC73XX_MAC_CFG_INIT;
  44634. + t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg);
  44635. + t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel);
  44636. + if (pdata->mac_cfg.bit2)
  44637. + t |= VSC73XX_MAC_CFG_BIT2;
  44638. +
  44639. + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
  44640. + VSC73XX_MAC_CFG, t);
  44641. + if (err)
  44642. + goto err;
  44643. +
  44644. + return 0;
  44645. +
  44646. +err:
  44647. + return err;
  44648. +}
  44649. +
  44650. +static int vsc7385_detect(struct vsc7385 *vsc)
  44651. +{
  44652. + struct spi_device *spi = vsc->spi;
  44653. + u32 t;
  44654. + u32 id;
  44655. + u32 rev;
  44656. + int err;
  44657. +
  44658. + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
  44659. + VSC73XX_ICPU_MBOX_VAL, &t);
  44660. + if (err) {
  44661. + dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err);
  44662. + return err;
  44663. + }
  44664. +
  44665. + if (t == 0xffffffff) {
  44666. + dev_dbg(&spi->dev, "assert chip reset\n");
  44667. + if (vsc->pdata->reset)
  44668. + vsc->pdata->reset();
  44669. +
  44670. + }
  44671. +
  44672. + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
  44673. + VSC73XX_ICPU_CHIPID, &t);
  44674. + if (err) {
  44675. + dev_err(&spi->dev, "unable to read chip id, err=%d\n", err);
  44676. + return err;
  44677. + }
  44678. +
  44679. + id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK;
  44680. + switch (id) {
  44681. + case VSC73XX_ICPU_CHIPID_ID_7385:
  44682. + case VSC73XX_ICPU_CHIPID_ID_7395:
  44683. + break;
  44684. + default:
  44685. + dev_err(&spi->dev, "unsupported chip, id=%04x\n", id);
  44686. + return -ENODEV;
  44687. + }
  44688. +
  44689. + rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) &
  44690. + VSC73XX_ICPU_CHIPID_REV_MASK;
  44691. + dev_info(&spi->dev, "VSC%04X (rev. %d) switch found\n", id, rev);
  44692. +
  44693. + return 0;
  44694. +}
  44695. +
  44696. +static int vsc7385_probe(struct spi_device *spi)
  44697. +{
  44698. + struct vsc7385 *vsc;
  44699. + struct vsc7385_platform_data *pdata;
  44700. + int err;
  44701. +
  44702. + printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n");
  44703. +
  44704. + pdata = spi->dev.platform_data;
  44705. + if (!pdata) {
  44706. + dev_err(&spi->dev, "no platform data specified\n");
  44707. + return -ENODEV;
  44708. + }
  44709. +
  44710. + vsc = kzalloc(sizeof(*vsc), GFP_KERNEL);
  44711. + if (!vsc) {
  44712. + dev_err(&spi->dev, "no memory for private data\n");
  44713. + return -ENOMEM;
  44714. + }
  44715. +
  44716. + mutex_init(&vsc->lock);
  44717. + vsc->pdata = pdata;
  44718. + vsc->spi = spi_dev_get(spi);
  44719. + dev_set_drvdata(&spi->dev, vsc);
  44720. +
  44721. + spi->mode = SPI_MODE_0;
  44722. + spi->bits_per_word = 8;
  44723. + err = spi_setup(spi);
  44724. + if (err) {
  44725. + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err);
  44726. + goto err_drvdata;
  44727. + }
  44728. +
  44729. + err = vsc7385_detect(vsc);
  44730. + if (err) {
  44731. + dev_err(&spi->dev, "no chip found, err=%d\n", err);
  44732. + goto err_drvdata;
  44733. + }
  44734. +
  44735. + err = vsc7385_upload_ucode(vsc);
  44736. + if (err)
  44737. + goto err_drvdata;
  44738. +
  44739. + err = vsc7385_setup(vsc);
  44740. + if (err)
  44741. + goto err_drvdata;
  44742. +
  44743. + return 0;
  44744. +
  44745. +err_drvdata:
  44746. + dev_set_drvdata(&spi->dev, NULL);
  44747. + kfree(vsc);
  44748. + return err;
  44749. +}
  44750. +
  44751. +static int vsc7385_remove(struct spi_device *spi)
  44752. +{
  44753. + struct vsc7385_data *vsc;
  44754. +
  44755. + vsc = dev_get_drvdata(&spi->dev);
  44756. + dev_set_drvdata(&spi->dev, NULL);
  44757. + kfree(vsc);
  44758. +
  44759. + return 0;
  44760. +}
  44761. +
  44762. +static struct spi_driver vsc7385_driver = {
  44763. + .driver = {
  44764. + .name = DRV_NAME,
  44765. + .bus = &spi_bus_type,
  44766. + .owner = THIS_MODULE,
  44767. + },
  44768. + .probe = vsc7385_probe,
  44769. + .remove = vsc7385_remove,
  44770. +};
  44771. +
  44772. +static int __init vsc7385_init(void)
  44773. +{
  44774. + return spi_register_driver(&vsc7385_driver);
  44775. +}
  44776. +module_init(vsc7385_init);
  44777. +
  44778. +static void __exit vsc7385_exit(void)
  44779. +{
  44780. + spi_unregister_driver(&vsc7385_driver);
  44781. +}
  44782. +module_exit(vsc7385_exit);
  44783. +
  44784. +MODULE_DESCRIPTION(DRV_DESC);
  44785. +MODULE_VERSION(DRV_VERSION);
  44786. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  44787. +MODULE_LICENSE("GPL v2");
  44788. +
  44789. diff -Nur linux-4.1.43.orig/drivers/tty/serial/serial_core.c linux-4.1.43/drivers/tty/serial/serial_core.c
  44790. --- linux-4.1.43.orig/drivers/tty/serial/serial_core.c 2017-08-06 01:56:14.000000000 +0200
  44791. +++ linux-4.1.43/drivers/tty/serial/serial_core.c 2017-08-06 20:02:16.000000000 +0200
  44792. @@ -164,6 +164,8 @@
  44793. if (retval == 0) {
  44794. if (uart_console(uport) && uport->cons->cflag) {
  44795. tty->termios.c_cflag = uport->cons->cflag;
  44796. + tty->termios.c_ospeed = uport->cons->baud;
  44797. + tty->termios.c_ispeed = uport->cons->baud;
  44798. uport->cons->cflag = 0;
  44799. }
  44800. /*
  44801. @@ -1901,7 +1903,7 @@
  44802. { 4800, B4800 },
  44803. { 2400, B2400 },
  44804. { 1200, B1200 },
  44805. - { 0, B38400 }
  44806. + { 0, BOTHER }
  44807. };
  44808. /**
  44809. @@ -1940,10 +1942,13 @@
  44810. * Construct a cflag setting.
  44811. */
  44812. for (i = 0; baud_rates[i].rate; i++)
  44813. - if (baud_rates[i].rate <= baud)
  44814. + if (baud_rates[i].rate == baud)
  44815. break;
  44816. termios.c_cflag |= baud_rates[i].cflag;
  44817. + if (!baud_rates[i].rate) {
  44818. + termios.c_ospeed = baud;
  44819. + }
  44820. if (bits == 7)
  44821. termios.c_cflag |= CS7;
  44822. @@ -1973,8 +1978,10 @@
  44823. * Allow the setting of the UART parameters with a NULL console
  44824. * too:
  44825. */
  44826. - if (co)
  44827. + if (co) {
  44828. co->cflag = termios.c_cflag;
  44829. + co->baud = baud;
  44830. + }
  44831. return 0;
  44832. }
  44833. diff -Nur linux-4.1.43.orig/drivers/usb/host/ehci-hcd.c linux-4.1.43/drivers/usb/host/ehci-hcd.c
  44834. --- linux-4.1.43.orig/drivers/usb/host/ehci-hcd.c 2017-08-06 01:56:14.000000000 +0200
  44835. +++ linux-4.1.43/drivers/usb/host/ehci-hcd.c 2017-08-06 20:02:16.000000000 +0200
  44836. @@ -252,6 +252,37 @@
  44837. command |= CMD_RESET;
  44838. dbg_cmd (ehci, "reset", command);
  44839. ehci_writel(ehci, command, &ehci->regs->command);
  44840. +
  44841. + if (ehci->qca_force_host_mode) {
  44842. + u32 usbmode;
  44843. +
  44844. + udelay(1000);
  44845. +
  44846. + usbmode = ehci_readl(ehci, &ehci->regs->usbmode);
  44847. + usbmode |= USBMODE_CM_HC | (1 << 4);
  44848. + ehci_writel(ehci, usbmode, &ehci->regs->usbmode);
  44849. +
  44850. + ehci_dbg(ehci, "forced host mode, usbmode: %08x\n",
  44851. + ehci_readl(ehci, &ehci->regs->usbmode));
  44852. + }
  44853. +
  44854. + if (ehci->qca_force_16bit_ptw) {
  44855. + u32 port_status;
  44856. +
  44857. + udelay(1000);
  44858. +
  44859. + /* enable 16-bit UTMI interface */
  44860. + port_status = ehci_readl(ehci, &ehci->regs->port_status[0]);
  44861. + port_status |= BIT(28);
  44862. + ehci_writel(ehci, port_status, &ehci->regs->port_status[0]);
  44863. +
  44864. + ehci_dbg(ehci, "16-bit UTMI interface enabled, status: %08x\n",
  44865. + ehci_readl(ehci, &ehci->regs->port_status[0]));
  44866. + }
  44867. +
  44868. + if (ehci->reset_notifier)
  44869. + ehci->reset_notifier(ehci_to_hcd(ehci));
  44870. +
  44871. ehci->rh_state = EHCI_RH_HALTED;
  44872. ehci->next_statechange = jiffies;
  44873. retval = ehci_handshake(ehci, &ehci->regs->command,
  44874. diff -Nur linux-4.1.43.orig/drivers/usb/host/ehci-platform.c linux-4.1.43/drivers/usb/host/ehci-platform.c
  44875. --- linux-4.1.43.orig/drivers/usb/host/ehci-platform.c 2017-08-06 01:56:14.000000000 +0200
  44876. +++ linux-4.1.43/drivers/usb/host/ehci-platform.c 2017-08-06 20:02:16.000000000 +0200
  44877. @@ -49,6 +49,14 @@
  44878. static const char hcd_name[] = "ehci-platform";
  44879. +static void ehci_platform_reset_notifier(struct usb_hcd *hcd)
  44880. +{
  44881. + struct platform_device *pdev = to_platform_device(hcd->self.controller);
  44882. + struct usb_ehci_pdata *pdata = pdev->dev.platform_data;
  44883. +
  44884. + pdata->reset_notifier(pdev);
  44885. +}
  44886. +
  44887. static int ehci_platform_reset(struct usb_hcd *hcd)
  44888. {
  44889. struct platform_device *pdev = to_platform_device(hcd->self.controller);
  44890. diff -Nur linux-4.1.43.orig/drivers/watchdog/ath79_wdt.c linux-4.1.43/drivers/watchdog/ath79_wdt.c
  44891. --- linux-4.1.43.orig/drivers/watchdog/ath79_wdt.c 2017-08-06 01:56:14.000000000 +0200
  44892. +++ linux-4.1.43/drivers/watchdog/ath79_wdt.c 2017-08-06 20:02:16.000000000 +0200
  44893. @@ -114,10 +114,14 @@
  44894. static int ath79_wdt_set_timeout(int val)
  44895. {
  44896. - if (val < 1 || val > max_timeout)
  44897. + if (val < 1)
  44898. return -EINVAL;
  44899. - timeout = val;
  44900. + if (val > max_timeout)
  44901. + timeout = max_timeout;
  44902. + else
  44903. + timeout = val;
  44904. +
  44905. ath79_wdt_keepalive();
  44906. return 0;
  44907. diff -Nur linux-4.1.43.orig/include/linux/console.h linux-4.1.43/include/linux/console.h
  44908. --- linux-4.1.43.orig/include/linux/console.h 2017-08-06 01:56:14.000000000 +0200
  44909. +++ linux-4.1.43/include/linux/console.h 2017-08-06 20:02:16.000000000 +0200
  44910. @@ -127,6 +127,7 @@
  44911. short flags;
  44912. short index;
  44913. int cflag;
  44914. + int baud;
  44915. void *data;
  44916. struct console *next;
  44917. };
  44918. diff -Nur linux-4.1.43.orig/include/linux/ipv6.h linux-4.1.43/include/linux/ipv6.h
  44919. --- linux-4.1.43.orig/include/linux/ipv6.h 2017-08-06 01:56:14.000000000 +0200
  44920. +++ linux-4.1.43/include/linux/ipv6.h 2017-08-06 20:02:16.000000000 +0200
  44921. @@ -5,6 +5,7 @@
  44922. #define ipv6_optlen(p) (((p)->hdrlen+1) << 3)
  44923. #define ipv6_authlen(p) (((p)->hdrlen+2) << 2)
  44924. +
  44925. /*
  44926. * This structure contains configuration options per IPv6 link.
  44927. */
  44928. diff -Nur linux-4.1.43.orig/include/linux/mtd/physmap.h linux-4.1.43/include/linux/mtd/physmap.h
  44929. --- linux-4.1.43.orig/include/linux/mtd/physmap.h 2017-08-06 01:56:14.000000000 +0200
  44930. +++ linux-4.1.43/include/linux/mtd/physmap.h 2017-08-06 20:02:16.000000000 +0200
  44931. @@ -25,6 +25,8 @@
  44932. unsigned int width;
  44933. int (*init)(struct platform_device *);
  44934. void (*exit)(struct platform_device *);
  44935. + void (*lock)(struct platform_device *);
  44936. + void (*unlock)(struct platform_device *);
  44937. void (*set_vpp)(struct platform_device *, int);
  44938. unsigned int nr_parts;
  44939. unsigned int pfow_base;
  44940. diff -Nur linux-4.1.43.orig/include/linux/myloader.h linux-4.1.43/include/linux/myloader.h
  44941. --- linux-4.1.43.orig/include/linux/myloader.h 1970-01-01 01:00:00.000000000 +0100
  44942. +++ linux-4.1.43/include/linux/myloader.h 2017-08-06 20:02:16.000000000 +0200
  44943. @@ -0,0 +1,121 @@
  44944. +/*
  44945. + * Compex's MyLoader specific definitions
  44946. + *
  44947. + * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
  44948. + *
  44949. + * This program is free software; you can redistribute it and/or modify it
  44950. + * under the terms of the GNU General Public License version 2 as published
  44951. + * by the Free Software Foundation.
  44952. + *
  44953. + */
  44954. +
  44955. +#ifndef _MYLOADER_H_
  44956. +#define _MYLOADER_H_
  44957. +
  44958. +/* Myloader specific magic numbers */
  44959. +#define MYLO_MAGIC_SYS_PARAMS 0x20021107
  44960. +#define MYLO_MAGIC_PARTITIONS 0x20021103
  44961. +#define MYLO_MAGIC_BOARD_PARAMS 0x20021103
  44962. +
  44963. +/* Vendor ID's (seems to be same as the PCI vendor ID's) */
  44964. +#define VENID_COMPEX 0x11F6
  44965. +
  44966. +/* Devices based on the ADM5120 */
  44967. +#define DEVID_COMPEX_NP27G 0x0078
  44968. +#define DEVID_COMPEX_NP28G 0x044C
  44969. +#define DEVID_COMPEX_NP28GHS 0x044E
  44970. +#define DEVID_COMPEX_WP54Gv1C 0x0514
  44971. +#define DEVID_COMPEX_WP54G 0x0515
  44972. +#define DEVID_COMPEX_WP54AG 0x0546
  44973. +#define DEVID_COMPEX_WPP54AG 0x0550
  44974. +#define DEVID_COMPEX_WPP54G 0x0555
  44975. +
  44976. +/* Devices based on the Atheros AR2317 */
  44977. +#define DEVID_COMPEX_NP25G 0x05E6
  44978. +#define DEVID_COMPEX_WPE53G 0x05DC
  44979. +
  44980. +/* Devices based on the Atheros AR71xx */
  44981. +#define DEVID_COMPEX_WP543 0x0640
  44982. +#define DEVID_COMPEX_WPE72 0x0672
  44983. +
  44984. +/* Devices based on the IXP422 */
  44985. +#define DEVID_COMPEX_WP18 0x047E
  44986. +#define DEVID_COMPEX_NP18A 0x0489
  44987. +
  44988. +/* Other devices */
  44989. +#define DEVID_COMPEX_NP26G8M 0x03E8
  44990. +#define DEVID_COMPEX_NP26G16M 0x03E9
  44991. +
  44992. +struct mylo_partition {
  44993. + uint16_t flags; /* partition flags */
  44994. + uint16_t type; /* type of the partition */
  44995. + uint32_t addr; /* relative address of the partition from the
  44996. + flash start */
  44997. + uint32_t size; /* size of the partition in bytes */
  44998. + uint32_t param; /* if this is the active partition, the
  44999. + MyLoader load code to this address */
  45000. +};
  45001. +
  45002. +#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition,
  45003. + * MyLoader loads firmware from here */
  45004. +#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */
  45005. +#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */
  45006. +#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM
  45007. + * before decompression */
  45008. +#define PARTITION_FLAG_LZMA 0x0100 /* partition data compressed by LZMA */
  45009. +#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */
  45010. +
  45011. +#define PARTITION_TYPE_FREE 0
  45012. +#define PARTITION_TYPE_USED 1
  45013. +
  45014. +#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the
  45015. + partition table */
  45016. +
  45017. +struct mylo_partition_table {
  45018. + uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */
  45019. + uint32_t res0; /* unknown/unused */
  45020. + uint32_t res1; /* unknown/unused */
  45021. + uint32_t res2; /* unknown/unused */
  45022. + struct mylo_partition partitions[MYLO_MAX_PARTITIONS];
  45023. +};
  45024. +
  45025. +struct mylo_partition_header {
  45026. + uint32_t len; /* length of the partition data */
  45027. + uint32_t crc; /* CRC value of the partition data */
  45028. +};
  45029. +
  45030. +struct mylo_system_params {
  45031. + uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */
  45032. + uint32_t res0;
  45033. + uint32_t res1;
  45034. + uint32_t mylo_ver;
  45035. + uint16_t vid; /* Vendor ID */
  45036. + uint16_t did; /* Device ID */
  45037. + uint16_t svid; /* Sub Vendor ID */
  45038. + uint16_t sdid; /* Sub Device ID */
  45039. + uint32_t rev; /* device revision */
  45040. + uint32_t fwhi;
  45041. + uint32_t fwlo;
  45042. + uint32_t tftp_addr;
  45043. + uint32_t prog_start;
  45044. + uint32_t flash_size; /* size of boot FLASH in bytes */
  45045. + uint32_t dram_size; /* size of onboard RAM in bytes */
  45046. +};
  45047. +
  45048. +struct mylo_eth_addr {
  45049. + uint8_t mac[6];
  45050. + uint8_t csum[2];
  45051. +};
  45052. +
  45053. +#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address
  45054. + in the board parameters */
  45055. +
  45056. +struct mylo_board_params {
  45057. + uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */
  45058. + uint32_t res0;
  45059. + uint32_t res1;
  45060. + uint32_t res2;
  45061. + struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT];
  45062. +};
  45063. +
  45064. +#endif /* _MYLOADER_H_*/
  45065. diff -Nur linux-4.1.43.orig/include/linux/nxp_74hc153.h linux-4.1.43/include/linux/nxp_74hc153.h
  45066. --- linux-4.1.43.orig/include/linux/nxp_74hc153.h 1970-01-01 01:00:00.000000000 +0100
  45067. +++ linux-4.1.43/include/linux/nxp_74hc153.h 2017-08-06 20:02:16.000000000 +0200
  45068. @@ -0,0 +1,24 @@
  45069. +/*
  45070. + * NXP 74HC153 - Dual 4-input multiplexer defines
  45071. + *
  45072. + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  45073. + *
  45074. + * This program is free software; you can redistribute it and/or modify
  45075. + * it under the terms of the GNU General Public License version 2 as
  45076. + * published by the Free Software Foundation.
  45077. + */
  45078. +
  45079. +#ifndef _NXP_74HC153_H
  45080. +#define _NXP_74HC153_H
  45081. +
  45082. +#define NXP_74HC153_DRIVER_NAME "nxp-74hc153"
  45083. +
  45084. +struct nxp_74hc153_platform_data {
  45085. + unsigned gpio_base;
  45086. + unsigned gpio_pin_s0;
  45087. + unsigned gpio_pin_s1;
  45088. + unsigned gpio_pin_1y;
  45089. + unsigned gpio_pin_2y;
  45090. +};
  45091. +
  45092. +#endif /* _NXP_74HC153_H */
  45093. diff -Nur linux-4.1.43.orig/include/linux/phy.h linux-4.1.43/include/linux/phy.h
  45094. --- linux-4.1.43.orig/include/linux/phy.h 2017-08-06 01:56:14.000000000 +0200
  45095. +++ linux-4.1.43/include/linux/phy.h 2017-08-06 20:02:16.000000000 +0200
  45096. @@ -762,6 +762,7 @@
  45097. void phy_stop_machine(struct phy_device *phydev);
  45098. int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
  45099. int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd);
  45100. +int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr);
  45101. int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
  45102. int phy_start_interrupts(struct phy_device *phydev);
  45103. void phy_print_status(struct phy_device *phydev);
  45104. diff -Nur linux-4.1.43.orig/include/linux/platform/ar934x_nfc.h linux-4.1.43/include/linux/platform/ar934x_nfc.h
  45105. --- linux-4.1.43.orig/include/linux/platform/ar934x_nfc.h 1970-01-01 01:00:00.000000000 +0100
  45106. +++ linux-4.1.43/include/linux/platform/ar934x_nfc.h 2017-08-06 20:02:16.000000000 +0200
  45107. @@ -0,0 +1,39 @@
  45108. +/*
  45109. + * Platform data definition for the built-in NAND controller of the
  45110. + * Atheros AR934x SoCs
  45111. + *
  45112. + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  45113. + *
  45114. + * This program is free software; you can redistribute it and/or modify it
  45115. + * under the terms of the GNU General Public License version 2 as published
  45116. + * by the Free Software Foundation.
  45117. + */
  45118. +
  45119. +#ifndef _AR934X_NFC_PLATFORM_H
  45120. +#define _AR934X_NFC_PLATFORM_H
  45121. +
  45122. +#define AR934X_NFC_DRIVER_NAME "ar934x-nfc"
  45123. +
  45124. +struct mtd_info;
  45125. +struct mtd_partition;
  45126. +
  45127. +enum ar934x_nfc_ecc_mode {
  45128. + AR934X_NFC_ECC_SOFT = 0,
  45129. + AR934X_NFC_ECC_HW,
  45130. + AR934X_NFC_ECC_SOFT_BCH,
  45131. +};
  45132. +
  45133. +struct ar934x_nfc_platform_data {
  45134. + const char *name;
  45135. + struct mtd_partition *parts;
  45136. + int nr_parts;
  45137. +
  45138. + bool swap_dma;
  45139. + enum ar934x_nfc_ecc_mode ecc_mode;
  45140. +
  45141. + void (*hw_reset)(bool active);
  45142. + void (*select_chip)(int chip_no);
  45143. + int (*scan_fixup)(struct mtd_info *mtd);
  45144. +};
  45145. +
  45146. +#endif /* _AR934X_NFC_PLATFORM_H */
  45147. diff -Nur linux-4.1.43.orig/include/linux/platform_data/gpio-latch.h linux-4.1.43/include/linux/platform_data/gpio-latch.h
  45148. --- linux-4.1.43.orig/include/linux/platform_data/gpio-latch.h 1970-01-01 01:00:00.000000000 +0100
  45149. +++ linux-4.1.43/include/linux/platform_data/gpio-latch.h 2017-08-06 20:02:16.000000000 +0200
  45150. @@ -0,0 +1,14 @@
  45151. +#ifndef _GPIO_LATCH_H_
  45152. +#define _GPIO_LATCH_H_
  45153. +
  45154. +#define GPIO_LATCH_DRIVER_NAME "gpio-latch"
  45155. +
  45156. +struct gpio_latch_platform_data {
  45157. + int base;
  45158. + int num_gpios;
  45159. + int *gpios;
  45160. + int le_gpio_index;
  45161. + bool le_active_low;
  45162. +};
  45163. +
  45164. +#endif /* _GPIO_LATCH_H_ */
  45165. diff -Nur linux-4.1.43.orig/include/linux/platform_data/phy-at803x.h linux-4.1.43/include/linux/platform_data/phy-at803x.h
  45166. --- linux-4.1.43.orig/include/linux/platform_data/phy-at803x.h 1970-01-01 01:00:00.000000000 +0100
  45167. +++ linux-4.1.43/include/linux/platform_data/phy-at803x.h 2017-08-06 20:02:16.000000000 +0200
  45168. @@ -0,0 +1,11 @@
  45169. +#ifndef _PHY_AT803X_PDATA_H
  45170. +#define _PHY_AT803X_PDATA_H
  45171. +
  45172. +struct at803x_platform_data {
  45173. + int disable_smarteee:1;
  45174. + int enable_rgmii_tx_delay:1;
  45175. + int enable_rgmii_rx_delay:1;
  45176. + int fixup_rgmii_tx_delay:1;
  45177. +};
  45178. +
  45179. +#endif /* _PHY_AT803X_PDATA_H */
  45180. diff -Nur linux-4.1.43.orig/include/linux/platform_data/rb91x_nand.h linux-4.1.43/include/linux/platform_data/rb91x_nand.h
  45181. --- linux-4.1.43.orig/include/linux/platform_data/rb91x_nand.h 1970-01-01 01:00:00.000000000 +0100
  45182. +++ linux-4.1.43/include/linux/platform_data/rb91x_nand.h 2017-08-06 20:02:16.000000000 +0200
  45183. @@ -0,0 +1,16 @@
  45184. +#ifndef _RB91X_NAND_H_
  45185. +#define _RB91X_NAND_H_
  45186. +
  45187. +#define RB91X_NAND_DRIVER_NAME "rb91x-nand"
  45188. +
  45189. +struct rb91x_nand_platform_data {
  45190. + int gpio_nce; /* chip enable, active low */
  45191. + int gpio_ale; /* address latch enable */
  45192. + int gpio_cle; /* command latch enable */
  45193. + int gpio_rdy;
  45194. + int gpio_read;
  45195. + int gpio_nrw; /* read/write enable, active low */
  45196. + int gpio_nle; /* latch enable, active low */
  45197. +};
  45198. +
  45199. +#endif /* _RB91X_NAND_H_ */
  45200. \ No newline at end of file
  45201. diff -Nur linux-4.1.43.orig/include/linux/rle.h linux-4.1.43/include/linux/rle.h
  45202. --- linux-4.1.43.orig/include/linux/rle.h 1970-01-01 01:00:00.000000000 +0100
  45203. +++ linux-4.1.43/include/linux/rle.h 2017-08-06 20:02:16.000000000 +0200
  45204. @@ -0,0 +1,18 @@
  45205. +#ifndef _RLE_H_
  45206. +#define _RLE_H_
  45207. +
  45208. +#ifdef CONFIG_RLE_DECOMPRESS
  45209. +int rle_decode(const unsigned char *src, size_t srclen,
  45210. + unsigned char *dst, size_t dstlen,
  45211. + size_t *src_done, size_t *dst_done);
  45212. +#else
  45213. +static inline int
  45214. +rle_decode(const unsigned char *src, size_t srclen,
  45215. + unsigned char *dst, size_t dstlen,
  45216. + size_t *src_done, size_t *dst_done)
  45217. +{
  45218. + return -ENOTSUPP;
  45219. +}
  45220. +#endif /* CONFIG_RLE_DECOMPRESS */
  45221. +
  45222. +#endif /* _RLE_H_ */
  45223. diff -Nur linux-4.1.43.orig/include/linux/spi/74x164.h linux-4.1.43/include/linux/spi/74x164.h
  45224. --- linux-4.1.43.orig/include/linux/spi/74x164.h 1970-01-01 01:00:00.000000000 +0100
  45225. +++ linux-4.1.43/include/linux/spi/74x164.h 2017-08-06 20:02:16.000000000 +0200
  45226. @@ -0,0 +1,13 @@
  45227. +#ifndef LINUX_SPI_74X164_H
  45228. +#define LINUX_SPI_74X164_H
  45229. +
  45230. +struct gen_74x164_chip_platform_data {
  45231. + /* number assigned to the first GPIO */
  45232. + unsigned base;
  45233. + /* number of chained registers */
  45234. + unsigned num_registers;
  45235. + /* address of a buffer containing initial data */
  45236. + u8 *init_data;
  45237. +};
  45238. +
  45239. +#endif
  45240. diff -Nur linux-4.1.43.orig/include/linux/spi/flash.h linux-4.1.43/include/linux/spi/flash.h
  45241. --- linux-4.1.43.orig/include/linux/spi/flash.h 2017-08-06 01:56:14.000000000 +0200
  45242. +++ linux-4.1.43/include/linux/spi/flash.h 2017-08-06 20:02:17.000000000 +0200
  45243. @@ -24,6 +24,7 @@
  45244. unsigned int nr_parts;
  45245. char *type;
  45246. + const char **part_probes;
  45247. /* we'll likely add more ... use JEDEC IDs, etc */
  45248. };
  45249. diff -Nur linux-4.1.43.orig/include/linux/spi/spi.h linux-4.1.43/include/linux/spi/spi.h
  45250. --- linux-4.1.43.orig/include/linux/spi/spi.h 2017-08-06 01:56:14.000000000 +0200
  45251. +++ linux-4.1.43/include/linux/spi/spi.h 2017-08-06 20:02:17.000000000 +0200
  45252. @@ -506,6 +506,12 @@
  45253. /*---------------------------------------------------------------------------*/
  45254. +enum spi_transfer_type {
  45255. + SPI_TRANSFER_GENERIC = 0,
  45256. + SPI_TRANSFER_FLASH_READ_CMD,
  45257. + SPI_TRANSFER_FLASH_READ_DATA,
  45258. +};
  45259. +
  45260. /*
  45261. * I/O INTERFACE between SPI controller and protocol drivers
  45262. *
  45263. @@ -618,12 +624,16 @@
  45264. unsigned cs_change:1;
  45265. unsigned tx_nbits:3;
  45266. unsigned rx_nbits:3;
  45267. + unsigned verify:1;
  45268. + unsigned fast_write:1;
  45269. #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
  45270. #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
  45271. #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
  45272. u8 bits_per_word;
  45273. u16 delay_usecs;
  45274. u32 speed_hz;
  45275. + enum spi_transfer_type type;
  45276. + bool dummy;
  45277. struct list_head transfer_list;
  45278. };
  45279. @@ -663,6 +673,7 @@
  45280. struct spi_device *spi;
  45281. unsigned is_dma_mapped:1;
  45282. + unsigned fast_read:1;
  45283. /* REVISIT: we might want a flag affecting the behavior of the
  45284. * last transfer ... allowing things like "read 16 bit length L"
  45285. diff -Nur linux-4.1.43.orig/include/linux/spi/spi_bitbang.h linux-4.1.43/include/linux/spi/spi_bitbang.h
  45286. --- linux-4.1.43.orig/include/linux/spi/spi_bitbang.h 2017-08-06 01:56:14.000000000 +0200
  45287. +++ linux-4.1.43/include/linux/spi/spi_bitbang.h 2017-08-06 20:02:17.000000000 +0200
  45288. @@ -39,6 +39,7 @@
  45289. extern void spi_bitbang_cleanup(struct spi_device *spi);
  45290. extern int spi_bitbang_setup_transfer(struct spi_device *spi,
  45291. struct spi_transfer *t);
  45292. +extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
  45293. /* start or stop queue processing */
  45294. extern int spi_bitbang_start(struct spi_bitbang *spi);
  45295. diff -Nur linux-4.1.43.orig/include/linux/spi/vsc7385.h linux-4.1.43/include/linux/spi/vsc7385.h
  45296. --- linux-4.1.43.orig/include/linux/spi/vsc7385.h 1970-01-01 01:00:00.000000000 +0100
  45297. +++ linux-4.1.43/include/linux/spi/vsc7385.h 2017-08-06 20:02:17.000000000 +0200
  45298. @@ -0,0 +1,19 @@
  45299. +/*
  45300. + * Platform data definition for the Vitesse VSC7385 ethernet switch driver
  45301. + *
  45302. + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  45303. + *
  45304. + * This program is free software; you can redistribute it and/or modify it
  45305. + * under the terms of the GNU General Public License version 2 as published
  45306. + * by the Free Software Foundation.
  45307. + */
  45308. +
  45309. +struct vsc7385_platform_data {
  45310. + void (*reset)(void);
  45311. + char *ucode_name;
  45312. + struct {
  45313. + u32 tx_ipg:5;
  45314. + u32 bit2:1;
  45315. + u32 clk_sel:3;
  45316. + } mac_cfg;
  45317. +};
  45318. diff -Nur linux-4.1.43.orig/include/linux/switch.h linux-4.1.43/include/linux/switch.h
  45319. --- linux-4.1.43.orig/include/linux/switch.h 1970-01-01 01:00:00.000000000 +0100
  45320. +++ linux-4.1.43/include/linux/switch.h 2017-08-06 20:02:17.000000000 +0200
  45321. @@ -0,0 +1,169 @@
  45322. +/*
  45323. + * switch.h: Switch configuration API
  45324. + *
  45325. + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
  45326. + *
  45327. + * This program is free software; you can redistribute it and/or
  45328. + * modify it under the terms of the GNU General Public License
  45329. + * as published by the Free Software Foundation; either version 2
  45330. + * of the License, or (at your option) any later version.
  45331. + *
  45332. + * This program is distributed in the hope that it will be useful,
  45333. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  45334. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  45335. + * GNU General Public License for more details.
  45336. + */
  45337. +#ifndef _LINUX_SWITCH_H
  45338. +#define _LINUX_SWITCH_H
  45339. +
  45340. +#include <net/genetlink.h>
  45341. +#include <uapi/linux/switch.h>
  45342. +
  45343. +struct switch_dev;
  45344. +struct switch_op;
  45345. +struct switch_val;
  45346. +struct switch_attr;
  45347. +struct switch_attrlist;
  45348. +struct switch_led_trigger;
  45349. +
  45350. +int register_switch(struct switch_dev *dev, struct net_device *netdev);
  45351. +void unregister_switch(struct switch_dev *dev);
  45352. +
  45353. +/**
  45354. + * struct switch_attrlist - attribute list
  45355. + *
  45356. + * @n_attr: number of attributes
  45357. + * @attr: pointer to the attributes array
  45358. + */
  45359. +struct switch_attrlist {
  45360. + int n_attr;
  45361. + const struct switch_attr *attr;
  45362. +};
  45363. +
  45364. +enum switch_port_speed {
  45365. + SWITCH_PORT_SPEED_UNKNOWN = 0,
  45366. + SWITCH_PORT_SPEED_10 = 10,
  45367. + SWITCH_PORT_SPEED_100 = 100,
  45368. + SWITCH_PORT_SPEED_1000 = 1000,
  45369. +};
  45370. +
  45371. +struct switch_port_link {
  45372. + bool link;
  45373. + bool duplex;
  45374. + bool aneg;
  45375. + bool tx_flow;
  45376. + bool rx_flow;
  45377. + enum switch_port_speed speed;
  45378. + /* in ethtool adv_t format */
  45379. + u32 eee;
  45380. +};
  45381. +
  45382. +struct switch_port_stats {
  45383. + unsigned long tx_bytes;
  45384. + unsigned long rx_bytes;
  45385. +};
  45386. +
  45387. +/**
  45388. + * struct switch_dev_ops - switch driver operations
  45389. + *
  45390. + * @attr_global: global switch attribute list
  45391. + * @attr_port: port attribute list
  45392. + * @attr_vlan: vlan attribute list
  45393. + *
  45394. + * Callbacks:
  45395. + *
  45396. + * @get_vlan_ports: read the port list of a VLAN
  45397. + * @set_vlan_ports: set the port list of a VLAN
  45398. + *
  45399. + * @get_port_pvid: get the primary VLAN ID of a port
  45400. + * @set_port_pvid: set the primary VLAN ID of a port
  45401. + *
  45402. + * @apply_config: apply all changed settings to the switch
  45403. + * @reset_switch: resetting the switch
  45404. + */
  45405. +struct switch_dev_ops {
  45406. + struct switch_attrlist attr_global, attr_port, attr_vlan;
  45407. +
  45408. + int (*get_vlan_ports)(struct switch_dev *dev, struct switch_val *val);
  45409. + int (*set_vlan_ports)(struct switch_dev *dev, struct switch_val *val);
  45410. +
  45411. + int (*get_port_pvid)(struct switch_dev *dev, int port, int *val);
  45412. + int (*set_port_pvid)(struct switch_dev *dev, int port, int val);
  45413. +
  45414. + int (*apply_config)(struct switch_dev *dev);
  45415. + int (*reset_switch)(struct switch_dev *dev);
  45416. +
  45417. + int (*get_port_link)(struct switch_dev *dev, int port,
  45418. + struct switch_port_link *link);
  45419. + int (*get_port_stats)(struct switch_dev *dev, int port,
  45420. + struct switch_port_stats *stats);
  45421. +};
  45422. +
  45423. +struct switch_dev {
  45424. + struct device_node *of_node;
  45425. + const struct switch_dev_ops *ops;
  45426. + /* will be automatically filled */
  45427. + char devname[IFNAMSIZ];
  45428. +
  45429. + const char *name;
  45430. + /* NB: either alias or netdev must be set */
  45431. + const char *alias;
  45432. + struct net_device *netdev;
  45433. +
  45434. + int ports;
  45435. + int vlans;
  45436. + int cpu_port;
  45437. +
  45438. + /* the following fields are internal for swconfig */
  45439. + int id;
  45440. + struct list_head dev_list;
  45441. + unsigned long def_global, def_port, def_vlan;
  45442. +
  45443. + struct mutex sw_mutex;
  45444. + struct switch_port *portbuf;
  45445. + struct switch_portmap *portmap;
  45446. +
  45447. + char buf[128];
  45448. +
  45449. +#ifdef CONFIG_SWCONFIG_LEDS
  45450. + struct switch_led_trigger *led_trigger;
  45451. +#endif
  45452. +};
  45453. +
  45454. +struct switch_port {
  45455. + u32 id;
  45456. + u32 flags;
  45457. +};
  45458. +
  45459. +struct switch_portmap {
  45460. + u32 virt;
  45461. + const char *s;
  45462. +};
  45463. +
  45464. +struct switch_val {
  45465. + const struct switch_attr *attr;
  45466. + int port_vlan;
  45467. + int len;
  45468. + union {
  45469. + const char *s;
  45470. + u32 i;
  45471. + struct switch_port *ports;
  45472. + } value;
  45473. +};
  45474. +
  45475. +struct switch_attr {
  45476. + int disabled;
  45477. + int type;
  45478. + const char *name;
  45479. + const char *description;
  45480. +
  45481. + int (*set)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val);
  45482. + int (*get)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val);
  45483. +
  45484. + /* for driver internal use */
  45485. + int id;
  45486. + int ofs;
  45487. + int max;
  45488. +};
  45489. +
  45490. +#endif /* _LINUX_SWITCH_H */
  45491. diff -Nur linux-4.1.43.orig/include/linux/types.h linux-4.1.43/include/linux/types.h
  45492. --- linux-4.1.43.orig/include/linux/types.h 2017-08-06 01:56:14.000000000 +0200
  45493. +++ linux-4.1.43/include/linux/types.h 2017-08-06 20:02:17.000000000 +0200
  45494. @@ -215,5 +215,11 @@
  45495. /* clocksource cycle base type */
  45496. typedef u64 cycle_t;
  45497. +struct net_hdr_word {
  45498. + u32 words[1];
  45499. +} __attribute__((packed, aligned(2)));
  45500. +
  45501. +#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
  45502. +
  45503. #endif /* __ASSEMBLY__ */
  45504. #endif /* _LINUX_TYPES_H */
  45505. diff -Nur linux-4.1.43.orig/include/linux/usb/ehci_pdriver.h linux-4.1.43/include/linux/usb/ehci_pdriver.h
  45506. --- linux-4.1.43.orig/include/linux/usb/ehci_pdriver.h 2017-08-06 01:56:14.000000000 +0200
  45507. +++ linux-4.1.43/include/linux/usb/ehci_pdriver.h 2017-08-06 20:02:17.000000000 +0200
  45508. @@ -49,6 +49,8 @@
  45509. unsigned no_io_watchdog:1;
  45510. unsigned reset_on_resume:1;
  45511. unsigned dma_mask_64:1;
  45512. + unsigned qca_force_host_mode:1;
  45513. + unsigned qca_force_16bit_ptw:1;
  45514. /* Turn on all power and clocks */
  45515. int (*power_on)(struct platform_device *pdev);
  45516. @@ -58,6 +60,7 @@
  45517. * turn off everything else */
  45518. void (*power_suspend)(struct platform_device *pdev);
  45519. int (*pre_setup)(struct usb_hcd *hcd);
  45520. + void (*reset_notifier)(struct platform_device *pdev);
  45521. };
  45522. #endif /* __USB_CORE_EHCI_PDRIVER_H */
  45523. diff -Nur linux-4.1.43.orig/include/net/addrconf.h linux-4.1.43/include/net/addrconf.h
  45524. --- linux-4.1.43.orig/include/net/addrconf.h 2017-08-06 01:56:14.000000000 +0200
  45525. +++ linux-4.1.43/include/net/addrconf.h 2017-08-06 20:02:17.000000000 +0200
  45526. @@ -45,7 +45,7 @@
  45527. __be32 reserved2;
  45528. struct in6_addr prefix;
  45529. -};
  45530. +} __attribute__((packed, aligned(2)));
  45531. #include <linux/netdevice.h>
  45532. diff -Nur linux-4.1.43.orig/include/net/ipv6.h linux-4.1.43/include/net/ipv6.h
  45533. --- linux-4.1.43.orig/include/net/ipv6.h 2017-08-06 01:56:14.000000000 +0200
  45534. +++ linux-4.1.43/include/net/ipv6.h 2017-08-06 20:02:17.000000000 +0200
  45535. @@ -107,7 +107,7 @@
  45536. __u8 reserved;
  45537. __be16 frag_off;
  45538. __be32 identification;
  45539. -};
  45540. +} __attribute__((packed, aligned(2)));
  45541. #define IP6_MF 0x0001
  45542. #define IP6_OFFSET 0xFFF8
  45543. @@ -415,8 +415,8 @@
  45544. }
  45545. #endif
  45546. #endif
  45547. - addr[0] = wh;
  45548. - addr[1] = wl;
  45549. + net_hdr_word(&addr[0]) = wh;
  45550. + net_hdr_word(&addr[1]) = wl;
  45551. }
  45552. static inline void ipv6_addr_set(struct in6_addr *addr,
  45553. @@ -475,6 +475,8 @@
  45554. const __be32 *a1 = addr1->s6_addr32;
  45555. const __be32 *a2 = addr2->s6_addr32;
  45556. unsigned int pdw, pbi;
  45557. + /* Used for last <32-bit fraction of prefix */
  45558. + u32 pbia1, pbia2;
  45559. /* check complete u32 in prefix */
  45560. pdw = prefixlen >> 5;
  45561. @@ -483,7 +485,9 @@
  45562. /* check incomplete u32 in prefix */
  45563. pbi = prefixlen & 0x1f;
  45564. - if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi))))
  45565. + pbia1 = net_hdr_word(&a1[pdw]);
  45566. + pbia2 = net_hdr_word(&a2[pdw]);
  45567. + if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi))))
  45568. return false;
  45569. return true;
  45570. @@ -627,13 +631,13 @@
  45571. */
  45572. static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)
  45573. {
  45574. - const __be32 *a1 = token1, *a2 = token2;
  45575. + const struct in6_addr *a1 = token1, *a2 = token2;
  45576. int i;
  45577. addrlen >>= 2;
  45578. for (i = 0; i < addrlen; i++) {
  45579. - __be32 xb = a1[i] ^ a2[i];
  45580. + __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i];
  45581. if (xb)
  45582. return i * 32 + 31 - __fls(ntohl(xb));
  45583. }
  45584. @@ -759,17 +763,18 @@
  45585. static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,
  45586. __be32 flowlabel)
  45587. {
  45588. - *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel;
  45589. + net_hdr_word((__be32 *)hdr) =
  45590. + htonl(0x60000000 | (tclass << 20)) | flowlabel;
  45591. }
  45592. static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr)
  45593. {
  45594. - return *(__be32 *)hdr & IPV6_FLOWINFO_MASK;
  45595. + return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK;
  45596. }
  45597. static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr)
  45598. {
  45599. - return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK;
  45600. + return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK;
  45601. }
  45602. static inline u8 ip6_tclass(__be32 flowinfo)
  45603. diff -Nur linux-4.1.43.orig/include/net/ndisc.h linux-4.1.43/include/net/ndisc.h
  45604. --- linux-4.1.43.orig/include/net/ndisc.h 2017-08-06 01:56:14.000000000 +0200
  45605. +++ linux-4.1.43/include/net/ndisc.h 2017-08-06 20:02:17.000000000 +0200
  45606. @@ -76,7 +76,7 @@
  45607. struct icmp6hdr icmph;
  45608. __be32 reachable_time;
  45609. __be32 retrans_timer;
  45610. -};
  45611. +} __attribute__((packed, aligned(2)));
  45612. struct rd_msg {
  45613. struct icmp6hdr icmph;
  45614. @@ -148,10 +148,10 @@
  45615. {
  45616. const u32 *p32 = pkey;
  45617. - return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
  45618. - (p32[1] * hash_rnd[1]) +
  45619. - (p32[2] * hash_rnd[2]) +
  45620. - (p32[3] * hash_rnd[3]));
  45621. + return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
  45622. + (net_hdr_word(&p32[1]) * hash_rnd[1]) +
  45623. + (net_hdr_word(&p32[2]) * hash_rnd[2]) +
  45624. + (net_hdr_word(&p32[3]) * hash_rnd[3]));
  45625. }
  45626. static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)
  45627. diff -Nur linux-4.1.43.orig/include/net/neighbour.h linux-4.1.43/include/net/neighbour.h
  45628. --- linux-4.1.43.orig/include/net/neighbour.h 2017-08-06 01:56:14.000000000 +0200
  45629. +++ linux-4.1.43/include/net/neighbour.h 2017-08-06 20:02:17.000000000 +0200
  45630. @@ -262,8 +262,10 @@
  45631. const u32 *n32 = (const u32 *)n->primary_key;
  45632. const u32 *p32 = pkey;
  45633. - return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) |
  45634. - (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0;
  45635. + return ((n32[0] ^ net_hdr_word(&p32[0])) |
  45636. + (n32[1] ^ net_hdr_word(&p32[1])) |
  45637. + (n32[2] ^ net_hdr_word(&p32[2])) |
  45638. + (n32[3] ^ net_hdr_word(&p32[3]))) == 0;
  45639. }
  45640. static inline struct neighbour *___neigh_lookup_noref(
  45641. diff -Nur linux-4.1.43.orig/include/net/secure_seq.h linux-4.1.43/include/net/secure_seq.h
  45642. --- linux-4.1.43.orig/include/net/secure_seq.h 2017-08-06 01:56:14.000000000 +0200
  45643. +++ linux-4.1.43/include/net/secure_seq.h 2017-08-06 20:02:17.000000000 +0200
  45644. @@ -2,6 +2,7 @@
  45645. #define _NET_SECURE_SEQ
  45646. #include <linux/types.h>
  45647. +#include <linux/in6.h>
  45648. u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport);
  45649. u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr,
  45650. diff -Nur linux-4.1.43.orig/include/uapi/linux/Kbuild linux-4.1.43/include/uapi/linux/Kbuild
  45651. --- linux-4.1.43.orig/include/uapi/linux/Kbuild 2017-08-06 01:56:14.000000000 +0200
  45652. +++ linux-4.1.43/include/uapi/linux/Kbuild 2017-08-06 20:02:17.000000000 +0200
  45653. @@ -380,6 +380,7 @@
  45654. header-y += string.h
  45655. header-y += suspend_ioctls.h
  45656. header-y += swab.h
  45657. +header-y += switch.h
  45658. header-y += synclink.h
  45659. header-y += sysctl.h
  45660. header-y += sysinfo.h
  45661. diff -Nur linux-4.1.43.orig/include/uapi/linux/icmp.h linux-4.1.43/include/uapi/linux/icmp.h
  45662. --- linux-4.1.43.orig/include/uapi/linux/icmp.h 2017-08-06 01:56:14.000000000 +0200
  45663. +++ linux-4.1.43/include/uapi/linux/icmp.h 2017-08-06 20:02:17.000000000 +0200
  45664. @@ -80,7 +80,7 @@
  45665. __be16 mtu;
  45666. } frag;
  45667. } un;
  45668. -};
  45669. +} __attribute__((packed, aligned(2)));
  45670. /*
  45671. diff -Nur linux-4.1.43.orig/include/uapi/linux/icmpv6.h linux-4.1.43/include/uapi/linux/icmpv6.h
  45672. --- linux-4.1.43.orig/include/uapi/linux/icmpv6.h 2017-08-06 01:56:14.000000000 +0200
  45673. +++ linux-4.1.43/include/uapi/linux/icmpv6.h 2017-08-06 20:02:17.000000000 +0200
  45674. @@ -76,7 +76,7 @@
  45675. #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other
  45676. #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime
  45677. #define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref
  45678. -};
  45679. +} __attribute__((packed, aligned(2)));
  45680. #define ICMPV6_ROUTER_PREF_LOW 0x3
  45681. diff -Nur linux-4.1.43.orig/include/uapi/linux/if_pppox.h linux-4.1.43/include/uapi/linux/if_pppox.h
  45682. --- linux-4.1.43.orig/include/uapi/linux/if_pppox.h 2017-08-06 01:56:14.000000000 +0200
  45683. +++ linux-4.1.43/include/uapi/linux/if_pppox.h 2017-08-06 20:02:17.000000000 +0200
  45684. @@ -47,6 +47,7 @@
  45685. */
  45686. struct pptp_addr {
  45687. __u16 call_id;
  45688. + __u16 pad;
  45689. struct in_addr sin_addr;
  45690. };
  45691. diff -Nur linux-4.1.43.orig/include/uapi/linux/igmp.h linux-4.1.43/include/uapi/linux/igmp.h
  45692. --- linux-4.1.43.orig/include/uapi/linux/igmp.h 2017-08-06 01:56:14.000000000 +0200
  45693. +++ linux-4.1.43/include/uapi/linux/igmp.h 2017-08-06 20:02:17.000000000 +0200
  45694. @@ -32,7 +32,7 @@
  45695. __u8 code; /* For newer IGMP */
  45696. __sum16 csum;
  45697. __be32 group;
  45698. -};
  45699. +} __attribute__((packed, aligned(2)));
  45700. /* V3 group record types [grec_type] */
  45701. #define IGMPV3_MODE_IS_INCLUDE 1
  45702. @@ -48,7 +48,7 @@
  45703. __be16 grec_nsrcs;
  45704. __be32 grec_mca;
  45705. __be32 grec_src[0];
  45706. -};
  45707. +} __attribute__((packed, aligned(2)));
  45708. struct igmpv3_report {
  45709. __u8 type;
  45710. @@ -57,7 +57,7 @@
  45711. __be16 resv2;
  45712. __be16 ngrec;
  45713. struct igmpv3_grec grec[0];
  45714. -};
  45715. +} __attribute__((packed, aligned(2)));
  45716. struct igmpv3_query {
  45717. __u8 type;
  45718. @@ -78,7 +78,7 @@
  45719. __u8 qqic;
  45720. __be16 nsrcs;
  45721. __be32 srcs[0];
  45722. -};
  45723. +} __attribute__((packed, aligned(2)));
  45724. #define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */
  45725. #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */
  45726. diff -Nur linux-4.1.43.orig/include/uapi/linux/in.h linux-4.1.43/include/uapi/linux/in.h
  45727. --- linux-4.1.43.orig/include/uapi/linux/in.h 2017-08-06 01:56:14.000000000 +0200
  45728. +++ linux-4.1.43/include/uapi/linux/in.h 2017-08-06 20:02:17.000000000 +0200
  45729. @@ -78,7 +78,7 @@
  45730. /* Internet address. */
  45731. struct in_addr {
  45732. __be32 s_addr;
  45733. -};
  45734. +} __attribute__((packed, aligned(2)));
  45735. #define IP_TOS 1
  45736. #define IP_TTL 2
  45737. diff -Nur linux-4.1.43.orig/include/uapi/linux/in6.h linux-4.1.43/include/uapi/linux/in6.h
  45738. --- linux-4.1.43.orig/include/uapi/linux/in6.h 2017-08-06 01:56:14.000000000 +0200
  45739. +++ linux-4.1.43/include/uapi/linux/in6.h 2017-08-06 20:02:17.000000000 +0200
  45740. @@ -42,7 +42,7 @@
  45741. #define s6_addr16 in6_u.u6_addr16
  45742. #define s6_addr32 in6_u.u6_addr32
  45743. #endif
  45744. -};
  45745. +} __attribute__((packed, aligned(2)));
  45746. #endif /* __UAPI_DEF_IN6_ADDR */
  45747. #if __UAPI_DEF_SOCKADDR_IN6
  45748. diff -Nur linux-4.1.43.orig/include/uapi/linux/ip.h linux-4.1.43/include/uapi/linux/ip.h
  45749. --- linux-4.1.43.orig/include/uapi/linux/ip.h 2017-08-06 01:56:14.000000000 +0200
  45750. +++ linux-4.1.43/include/uapi/linux/ip.h 2017-08-06 20:02:17.000000000 +0200
  45751. @@ -102,7 +102,7 @@
  45752. __be32 saddr;
  45753. __be32 daddr;
  45754. /*The options start here. */
  45755. -};
  45756. +} __attribute__((packed, aligned(2)));
  45757. struct ip_auth_hdr {
  45758. diff -Nur linux-4.1.43.orig/include/uapi/linux/ipv6.h linux-4.1.43/include/uapi/linux/ipv6.h
  45759. --- linux-4.1.43.orig/include/uapi/linux/ipv6.h 2017-08-06 01:56:14.000000000 +0200
  45760. +++ linux-4.1.43/include/uapi/linux/ipv6.h 2017-08-06 20:02:17.000000000 +0200
  45761. @@ -129,7 +129,7 @@
  45762. struct in6_addr saddr;
  45763. struct in6_addr daddr;
  45764. -};
  45765. +} __attribute__((packed, aligned(2)));
  45766. /* index values for the variables in ipv6_devconf */
  45767. diff -Nur linux-4.1.43.orig/include/uapi/linux/netfilter_arp/arp_tables.h linux-4.1.43/include/uapi/linux/netfilter_arp/arp_tables.h
  45768. --- linux-4.1.43.orig/include/uapi/linux/netfilter_arp/arp_tables.h 2017-08-06 01:56:14.000000000 +0200
  45769. +++ linux-4.1.43/include/uapi/linux/netfilter_arp/arp_tables.h 2017-08-06 20:02:17.000000000 +0200
  45770. @@ -68,7 +68,7 @@
  45771. __u8 flags;
  45772. /* Inverse flags */
  45773. __u16 invflags;
  45774. -};
  45775. +} __attribute__((aligned(4)));
  45776. /* Values for "flag" field in struct arpt_ip (general arp structure).
  45777. * No flags defined yet.
  45778. diff -Nur linux-4.1.43.orig/include/uapi/linux/switch.h linux-4.1.43/include/uapi/linux/switch.h
  45779. --- linux-4.1.43.orig/include/uapi/linux/switch.h 1970-01-01 01:00:00.000000000 +0100
  45780. +++ linux-4.1.43/include/uapi/linux/switch.h 2017-08-06 20:02:17.000000000 +0200
  45781. @@ -0,0 +1,103 @@
  45782. +/*
  45783. + * switch.h: Switch configuration API
  45784. + *
  45785. + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
  45786. + *
  45787. + * This program is free software; you can redistribute it and/or
  45788. + * modify it under the terms of the GNU General Public License
  45789. + * as published by the Free Software Foundation; either version 2
  45790. + * of the License, or (at your option) any later version.
  45791. + *
  45792. + * This program is distributed in the hope that it will be useful,
  45793. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  45794. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  45795. + * GNU General Public License for more details.
  45796. + */
  45797. +
  45798. +#ifndef _UAPI_LINUX_SWITCH_H
  45799. +#define _UAPI_LINUX_SWITCH_H
  45800. +
  45801. +#include <linux/types.h>
  45802. +#include <linux/netdevice.h>
  45803. +#include <linux/netlink.h>
  45804. +#include <linux/genetlink.h>
  45805. +#ifndef __KERNEL__
  45806. +#include <netlink/netlink.h>
  45807. +#include <netlink/genl/genl.h>
  45808. +#include <netlink/genl/ctrl.h>
  45809. +#endif
  45810. +
  45811. +/* main attributes */
  45812. +enum {
  45813. + SWITCH_ATTR_UNSPEC,
  45814. + /* global */
  45815. + SWITCH_ATTR_TYPE,
  45816. + /* device */
  45817. + SWITCH_ATTR_ID,
  45818. + SWITCH_ATTR_DEV_NAME,
  45819. + SWITCH_ATTR_ALIAS,
  45820. + SWITCH_ATTR_NAME,
  45821. + SWITCH_ATTR_VLANS,
  45822. + SWITCH_ATTR_PORTS,
  45823. + SWITCH_ATTR_PORTMAP,
  45824. + SWITCH_ATTR_CPU_PORT,
  45825. + /* attributes */
  45826. + SWITCH_ATTR_OP_ID,
  45827. + SWITCH_ATTR_OP_TYPE,
  45828. + SWITCH_ATTR_OP_NAME,
  45829. + SWITCH_ATTR_OP_PORT,
  45830. + SWITCH_ATTR_OP_VLAN,
  45831. + SWITCH_ATTR_OP_VALUE_INT,
  45832. + SWITCH_ATTR_OP_VALUE_STR,
  45833. + SWITCH_ATTR_OP_VALUE_PORTS,
  45834. + SWITCH_ATTR_OP_DESCRIPTION,
  45835. + /* port lists */
  45836. + SWITCH_ATTR_PORT,
  45837. + SWITCH_ATTR_MAX
  45838. +};
  45839. +
  45840. +enum {
  45841. + /* port map */
  45842. + SWITCH_PORTMAP_PORTS,
  45843. + SWITCH_PORTMAP_SEGMENT,
  45844. + SWITCH_PORTMAP_VIRT,
  45845. + SWITCH_PORTMAP_MAX
  45846. +};
  45847. +
  45848. +/* commands */
  45849. +enum {
  45850. + SWITCH_CMD_UNSPEC,
  45851. + SWITCH_CMD_GET_SWITCH,
  45852. + SWITCH_CMD_NEW_ATTR,
  45853. + SWITCH_CMD_LIST_GLOBAL,
  45854. + SWITCH_CMD_GET_GLOBAL,
  45855. + SWITCH_CMD_SET_GLOBAL,
  45856. + SWITCH_CMD_LIST_PORT,
  45857. + SWITCH_CMD_GET_PORT,
  45858. + SWITCH_CMD_SET_PORT,
  45859. + SWITCH_CMD_LIST_VLAN,
  45860. + SWITCH_CMD_GET_VLAN,
  45861. + SWITCH_CMD_SET_VLAN
  45862. +};
  45863. +
  45864. +/* data types */
  45865. +enum switch_val_type {
  45866. + SWITCH_TYPE_UNSPEC,
  45867. + SWITCH_TYPE_INT,
  45868. + SWITCH_TYPE_STRING,
  45869. + SWITCH_TYPE_PORTS,
  45870. + SWITCH_TYPE_NOVAL,
  45871. +};
  45872. +
  45873. +/* port nested attributes */
  45874. +enum {
  45875. + SWITCH_PORT_UNSPEC,
  45876. + SWITCH_PORT_ID,
  45877. + SWITCH_PORT_FLAG_TAGGED,
  45878. + SWITCH_PORT_ATTR_MAX
  45879. +};
  45880. +
  45881. +#define SWITCH_ATTR_DEFAULTS_OFFSET 0x1000
  45882. +
  45883. +
  45884. +#endif /* _UAPI_LINUX_SWITCH_H */
  45885. diff -Nur linux-4.1.43.orig/include/uapi/linux/tcp.h linux-4.1.43/include/uapi/linux/tcp.h
  45886. --- linux-4.1.43.orig/include/uapi/linux/tcp.h 2017-08-06 01:56:14.000000000 +0200
  45887. +++ linux-4.1.43/include/uapi/linux/tcp.h 2017-08-06 20:02:17.000000000 +0200
  45888. @@ -54,7 +54,7 @@
  45889. __be16 window;
  45890. __sum16 check;
  45891. __be16 urg_ptr;
  45892. -};
  45893. +} __attribute__((packed, aligned(2)));
  45894. /*
  45895. * The union cast uses a gcc extension to avoid aliasing problems
  45896. @@ -64,7 +64,7 @@
  45897. union tcp_word_hdr {
  45898. struct tcphdr hdr;
  45899. __be32 words[5];
  45900. -};
  45901. +} __attribute__((packed, aligned(2)));
  45902. #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3])
  45903. diff -Nur linux-4.1.43.orig/include/uapi/linux/udp.h linux-4.1.43/include/uapi/linux/udp.h
  45904. --- linux-4.1.43.orig/include/uapi/linux/udp.h 2017-08-06 01:56:14.000000000 +0200
  45905. +++ linux-4.1.43/include/uapi/linux/udp.h 2017-08-06 20:02:17.000000000 +0200
  45906. @@ -24,7 +24,7 @@
  45907. __be16 dest;
  45908. __be16 len;
  45909. __sum16 check;
  45910. -};
  45911. +} __attribute__((packed, aligned(2)));
  45912. /* UDP socket options */
  45913. #define UDP_CORK 1 /* Never send partially complete segments */
  45914. diff -Nur linux-4.1.43.orig/lib/Kconfig linux-4.1.43/lib/Kconfig
  45915. --- linux-4.1.43.orig/lib/Kconfig 2017-08-06 01:56:14.000000000 +0200
  45916. +++ linux-4.1.43/lib/Kconfig 2017-08-06 20:02:17.000000000 +0200
  45917. @@ -235,6 +235,9 @@
  45918. source "lib/xz/Kconfig"
  45919. +config RLE_DECOMPRESS
  45920. + tristate
  45921. +
  45922. #
  45923. # These all provide a common interface (hence the apparent duplication with
  45924. # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
  45925. diff -Nur linux-4.1.43.orig/lib/rle.c linux-4.1.43/lib/rle.c
  45926. --- linux-4.1.43.orig/lib/rle.c 1970-01-01 01:00:00.000000000 +0100
  45927. +++ linux-4.1.43/lib/rle.c 2017-08-06 20:02:17.000000000 +0200
  45928. @@ -0,0 +1,78 @@
  45929. +/*
  45930. + * RLE decoding routine
  45931. + *
  45932. + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  45933. + *
  45934. + * This program is free software; you can redistribute it and/or modify it
  45935. + * under the terms of the GNU General Public License version 2 as published
  45936. + * by the Free Software Foundation.
  45937. + */
  45938. +
  45939. +#include <linux/kernel.h>
  45940. +#include <linux/module.h>
  45941. +#include <linux/rle.h>
  45942. +
  45943. +int rle_decode(const unsigned char *src, size_t srclen,
  45944. + unsigned char *dst, size_t dstlen,
  45945. + size_t *src_done, size_t *dst_done)
  45946. +{
  45947. + size_t srcpos, dstpos;
  45948. + int ret;
  45949. +
  45950. + srcpos = 0;
  45951. + dstpos = 0;
  45952. + ret = -EINVAL;
  45953. +
  45954. + /* sanity checks */
  45955. + if (!src || !srclen || !dst || !dstlen)
  45956. + goto out;
  45957. +
  45958. + while (1) {
  45959. + char count;
  45960. +
  45961. + if (srcpos >= srclen)
  45962. + break;
  45963. +
  45964. + count = (char) src[srcpos++];
  45965. + if (count == 0) {
  45966. + ret = 0;
  45967. + break;
  45968. + }
  45969. +
  45970. + if (count > 0) {
  45971. + unsigned char c;
  45972. +
  45973. + if (srcpos >= srclen)
  45974. + break;
  45975. +
  45976. + c = src[srcpos++];
  45977. +
  45978. + while (count--) {
  45979. + if (dstpos >= dstlen)
  45980. + break;
  45981. +
  45982. + dst[dstpos++] = c;
  45983. + }
  45984. + } else {
  45985. + count *= -1;
  45986. +
  45987. + while (count--) {
  45988. + if (srcpos >= srclen)
  45989. + break;
  45990. + if (dstpos >= dstlen)
  45991. + break;
  45992. + dst[dstpos++] = src[srcpos++];
  45993. + }
  45994. + }
  45995. + }
  45996. +
  45997. +out:
  45998. + if (src_done)
  45999. + *src_done = srcpos;
  46000. + if (dst_done)
  46001. + *dst_done = dstpos;
  46002. +
  46003. + return ret;
  46004. +}
  46005. +
  46006. +EXPORT_SYMBOL_GPL(rle_decode);
  46007. diff -Nur linux-4.1.43.orig/net/core/flow_dissector.c linux-4.1.43/net/core/flow_dissector.c
  46008. --- linux-4.1.43.orig/net/core/flow_dissector.c 2017-08-06 01:56:14.000000000 +0200
  46009. +++ linux-4.1.43/net/core/flow_dissector.c 2017-08-06 20:02:17.000000000 +0200
  46010. @@ -53,7 +53,7 @@
  46011. ports = __skb_header_pointer(skb, thoff + poff,
  46012. sizeof(_ports), data, hlen, &_ports);
  46013. if (ports)
  46014. - return *ports;
  46015. + return (__be32)net_hdr_word(ports);
  46016. }
  46017. return 0;
  46018. diff -Nur linux-4.1.43.orig/net/core/secure_seq.c linux-4.1.43/net/core/secure_seq.c
  46019. --- linux-4.1.43.orig/net/core/secure_seq.c 2017-08-06 01:56:14.000000000 +0200
  46020. +++ linux-4.1.43/net/core/secure_seq.c 2017-08-06 20:02:17.000000000 +0200
  46021. @@ -46,11 +46,12 @@
  46022. u32 secret[MD5_MESSAGE_BYTES / 4];
  46023. u32 hash[MD5_DIGEST_WORDS];
  46024. u32 i;
  46025. + const struct in6_addr *daddr6 = (struct in6_addr *) daddr;
  46026. net_secret_init();
  46027. memcpy(hash, saddr, 16);
  46028. for (i = 0; i < 4; i++)
  46029. - secret[i] = net_secret[i] + (__force u32)daddr[i];
  46030. + secret[i] = net_secret[i] + (__force u32)daddr6->s6_addr32[i];
  46031. secret[4] = net_secret[4] +
  46032. (((__force u16)sport << 16) + (__force u16)dport);
  46033. for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++)
  46034. @@ -68,11 +69,12 @@
  46035. u32 secret[MD5_MESSAGE_BYTES / 4];
  46036. u32 hash[MD5_DIGEST_WORDS];
  46037. u32 i;
  46038. + const struct in6_addr *daddr6 = (struct in6_addr *) daddr;
  46039. net_secret_init();
  46040. memcpy(hash, saddr, 16);
  46041. for (i = 0; i < 4; i++)
  46042. - secret[i] = net_secret[i] + (__force u32) daddr[i];
  46043. + secret[i] = net_secret[i] + (__force u32) daddr6->s6_addr32[i];
  46044. secret[4] = net_secret[4] + (__force u32)dport;
  46045. for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++)
  46046. secret[i] = net_secret[i];
  46047. @@ -150,11 +152,12 @@
  46048. u32 hash[MD5_DIGEST_WORDS];
  46049. u64 seq;
  46050. u32 i;
  46051. + const struct in6_addr *daddr6 = (struct in6_addr *) daddr;
  46052. net_secret_init();
  46053. memcpy(hash, saddr, 16);
  46054. for (i = 0; i < 4; i++)
  46055. - secret[i] = net_secret[i] + daddr[i];
  46056. + secret[i] = net_secret[i] + daddr6->s6_addr32[i];
  46057. secret[4] = net_secret[4] +
  46058. (((__force u16)sport << 16) + (__force u16)dport);
  46059. for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++)
  46060. diff -Nur linux-4.1.43.orig/net/dsa/mv88e6063.c linux-4.1.43/net/dsa/mv88e6063.c
  46061. --- linux-4.1.43.orig/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100
  46062. +++ linux-4.1.43/net/dsa/mv88e6063.c 2017-08-06 20:02:17.000000000 +0200
  46063. @@ -0,0 +1,294 @@
  46064. +/*
  46065. + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips
  46066. + * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
  46067. + *
  46068. + * This driver was base on: net/dsa/mv88e6060.c
  46069. + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips
  46070. + * Copyright (c) 2008-2009 Marvell Semiconductor
  46071. + *
  46072. + * This program is free software; you can redistribute it and/or modify
  46073. + * it under the terms of the GNU General Public License as published by
  46074. + * the Free Software Foundation; either version 2 of the License, or
  46075. + * (at your option) any later version.
  46076. + */
  46077. +
  46078. +#include <linux/list.h>
  46079. +#include <linux/netdevice.h>
  46080. +#include <linux/phy.h>
  46081. +#include "dsa_priv.h"
  46082. +
  46083. +#define REG_BASE 0x10
  46084. +#define REG_PHY(p) (REG_BASE + (p))
  46085. +#define REG_PORT(p) (REG_BASE + 8 + (p))
  46086. +#define REG_GLOBAL (REG_BASE + 0x0f)
  46087. +#define NUM_PORTS 7
  46088. +
  46089. +static int reg_read(struct dsa_switch *ds, int addr, int reg)
  46090. +{
  46091. + return mdiobus_read(ds->master_mii_bus, addr, reg);
  46092. +}
  46093. +
  46094. +#define REG_READ(addr, reg) \
  46095. + ({ \
  46096. + int __ret; \
  46097. + \
  46098. + __ret = reg_read(ds, addr, reg); \
  46099. + if (__ret < 0) \
  46100. + return __ret; \
  46101. + __ret; \
  46102. + })
  46103. +
  46104. +
  46105. +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  46106. +{
  46107. + return mdiobus_write(ds->master_mii_bus, addr, reg, val);
  46108. +}
  46109. +
  46110. +#define REG_WRITE(addr, reg, val) \
  46111. + ({ \
  46112. + int __ret; \
  46113. + \
  46114. + __ret = reg_write(ds, addr, reg, val); \
  46115. + if (__ret < 0) \
  46116. + return __ret; \
  46117. + })
  46118. +
  46119. +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr)
  46120. +{
  46121. + int ret;
  46122. +
  46123. + ret = mdiobus_read(bus, REG_PORT(0), 0x03);
  46124. + if (ret >= 0) {
  46125. + ret &= 0xfff0;
  46126. + if (ret == 0x1530)
  46127. + return "Marvell 88E6063";
  46128. + }
  46129. +
  46130. + return NULL;
  46131. +}
  46132. +
  46133. +static int mv88e6063_switch_reset(struct dsa_switch *ds)
  46134. +{
  46135. + int i;
  46136. + int ret;
  46137. +
  46138. + /*
  46139. + * Set all ports to the disabled state.
  46140. + */
  46141. + for (i = 0; i < NUM_PORTS; i++) {
  46142. + ret = REG_READ(REG_PORT(i), 0x04);
  46143. + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  46144. + }
  46145. +
  46146. + /*
  46147. + * Wait for transmit queues to drain.
  46148. + */
  46149. + msleep(2);
  46150. +
  46151. + /*
  46152. + * Reset the switch.
  46153. + */
  46154. + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
  46155. +
  46156. + /*
  46157. + * Wait up to one second for reset to complete.
  46158. + */
  46159. + for (i = 0; i < 1000; i++) {
  46160. + ret = REG_READ(REG_GLOBAL, 0x00);
  46161. + if ((ret & 0x8000) == 0x0000)
  46162. + break;
  46163. +
  46164. + msleep(1);
  46165. + }
  46166. + if (i == 1000)
  46167. + return -ETIMEDOUT;
  46168. +
  46169. + return 0;
  46170. +}
  46171. +
  46172. +static int mv88e6063_setup_global(struct dsa_switch *ds)
  46173. +{
  46174. + /*
  46175. + * Disable discarding of frames with excessive collisions,
  46176. + * set the maximum frame size to 1536 bytes, and mask all
  46177. + * interrupt sources.
  46178. + */
  46179. + REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
  46180. +
  46181. + /*
  46182. + * Enable automatic address learning, set the address
  46183. + * database size to 1024 entries, and set the default aging
  46184. + * time to 5 minutes.
  46185. + */
  46186. + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
  46187. +
  46188. + return 0;
  46189. +}
  46190. +
  46191. +static int mv88e6063_setup_port(struct dsa_switch *ds, int p)
  46192. +{
  46193. + int addr = REG_PORT(p);
  46194. +
  46195. + /*
  46196. + * Do not force flow control, disable Ingress and Egress
  46197. + * Header tagging, disable VLAN tunneling, and set the port
  46198. + * state to Forwarding. Additionally, if this is the CPU
  46199. + * port, enable Ingress and Egress Trailer tagging mode.
  46200. + */
  46201. + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
  46202. +
  46203. + /*
  46204. + * Port based VLAN map: give each port its own address
  46205. + * database, allow the CPU port to talk to each of the 'real'
  46206. + * ports, and allow each of the 'real' ports to only talk to
  46207. + * the CPU port.
  46208. + */
  46209. + REG_WRITE(addr, 0x06,
  46210. + ((p & 0xf) << 12) |
  46211. + (dsa_is_cpu_port(ds, p) ?
  46212. + ds->phys_port_mask :
  46213. + (1 << ds->dst->cpu_port)));
  46214. +
  46215. + /*
  46216. + * Port Association Vector: when learning source addresses
  46217. + * of packets, add the address to the address database using
  46218. + * a port bitmap that has only the bit for this port set and
  46219. + * the other bits clear.
  46220. + */
  46221. + REG_WRITE(addr, 0x0b, 1 << p);
  46222. +
  46223. + return 0;
  46224. +}
  46225. +
  46226. +static int mv88e6063_setup(struct dsa_switch *ds)
  46227. +{
  46228. + int i;
  46229. + int ret;
  46230. +
  46231. + ret = mv88e6063_switch_reset(ds);
  46232. + if (ret < 0)
  46233. + return ret;
  46234. +
  46235. + /* @@@ initialise atu */
  46236. +
  46237. + ret = mv88e6063_setup_global(ds);
  46238. + if (ret < 0)
  46239. + return ret;
  46240. +
  46241. + for (i = 0; i < NUM_PORTS; i++) {
  46242. + ret = mv88e6063_setup_port(ds, i);
  46243. + if (ret < 0)
  46244. + return ret;
  46245. + }
  46246. +
  46247. + return 0;
  46248. +}
  46249. +
  46250. +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr)
  46251. +{
  46252. + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
  46253. + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
  46254. + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
  46255. +
  46256. + return 0;
  46257. +}
  46258. +
  46259. +static int mv88e6063_port_to_phy_addr(int port)
  46260. +{
  46261. + if (port >= 0 && port <= NUM_PORTS)
  46262. + return REG_PHY(port);
  46263. + return -1;
  46264. +}
  46265. +
  46266. +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum)
  46267. +{
  46268. + int addr;
  46269. +
  46270. + addr = mv88e6063_port_to_phy_addr(port);
  46271. + if (addr == -1)
  46272. + return 0xffff;
  46273. +
  46274. + return reg_read(ds, addr, regnum);
  46275. +}
  46276. +
  46277. +static int
  46278. +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
  46279. +{
  46280. + int addr;
  46281. +
  46282. + addr = mv88e6063_port_to_phy_addr(port);
  46283. + if (addr == -1)
  46284. + return 0xffff;
  46285. +
  46286. + return reg_write(ds, addr, regnum, val);
  46287. +}
  46288. +
  46289. +static void mv88e6063_poll_link(struct dsa_switch *ds)
  46290. +{
  46291. + int i;
  46292. +
  46293. + for (i = 0; i < DSA_MAX_PORTS; i++) {
  46294. + struct net_device *dev;
  46295. + int uninitialized_var(port_status);
  46296. + int link;
  46297. + int speed;
  46298. + int duplex;
  46299. + int fc;
  46300. +
  46301. + dev = ds->ports[i];
  46302. + if (dev == NULL)
  46303. + continue;
  46304. +
  46305. + link = 0;
  46306. + if (dev->flags & IFF_UP) {
  46307. + port_status = reg_read(ds, REG_PORT(i), 0x00);
  46308. + if (port_status < 0)
  46309. + continue;
  46310. +
  46311. + link = !!(port_status & 0x1000);
  46312. + }
  46313. +
  46314. + if (!link) {
  46315. + if (netif_carrier_ok(dev)) {
  46316. + printk(KERN_INFO "%s: link down\n", dev->name);
  46317. + netif_carrier_off(dev);
  46318. + }
  46319. + continue;
  46320. + }
  46321. +
  46322. + speed = (port_status & 0x0100) ? 100 : 10;
  46323. + duplex = (port_status & 0x0200) ? 1 : 0;
  46324. + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
  46325. +
  46326. + if (!netif_carrier_ok(dev)) {
  46327. + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
  46328. + "flow control %sabled\n", dev->name,
  46329. + speed, duplex ? "full" : "half",
  46330. + fc ? "en" : "dis");
  46331. + netif_carrier_on(dev);
  46332. + }
  46333. + }
  46334. +}
  46335. +
  46336. +static struct dsa_switch_driver mv88e6063_switch_driver = {
  46337. + .tag_protocol = htons(ETH_P_TRAILER),
  46338. + .probe = mv88e6063_probe,
  46339. + .setup = mv88e6063_setup,
  46340. + .set_addr = mv88e6063_set_addr,
  46341. + .phy_read = mv88e6063_phy_read,
  46342. + .phy_write = mv88e6063_phy_write,
  46343. + .poll_link = mv88e6063_poll_link,
  46344. +};
  46345. +
  46346. +static int __init mv88e6063_init(void)
  46347. +{
  46348. + register_switch_driver(&mv88e6063_switch_driver);
  46349. + return 0;
  46350. +}
  46351. +module_init(mv88e6063_init);
  46352. +
  46353. +static void __exit mv88e6063_cleanup(void)
  46354. +{
  46355. + unregister_switch_driver(&mv88e6063_switch_driver);
  46356. +}
  46357. +module_exit(mv88e6063_cleanup);
  46358. diff -Nur linux-4.1.43.orig/net/dsa/tag_trailer.c linux-4.1.43/net/dsa/tag_trailer.c
  46359. --- linux-4.1.43.orig/net/dsa/tag_trailer.c 2017-08-06 01:56:14.000000000 +0200
  46360. +++ linux-4.1.43/net/dsa/tag_trailer.c 2017-08-06 20:02:17.000000000 +0200
  46361. @@ -84,7 +84,7 @@
  46362. trailer = skb_tail_pointer(skb) - 4;
  46363. if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
  46364. - (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
  46365. + (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
  46366. goto out_drop;
  46367. source_port = trailer[1] & 7;
  46368. diff -Nur linux-4.1.43.orig/net/ipv4/af_inet.c linux-4.1.43/net/ipv4/af_inet.c
  46369. --- linux-4.1.43.orig/net/ipv4/af_inet.c 2017-08-06 01:56:14.000000000 +0200
  46370. +++ linux-4.1.43/net/ipv4/af_inet.c 2017-08-06 20:02:17.000000000 +0200
  46371. @@ -1326,8 +1326,8 @@
  46372. if (unlikely(ip_fast_csum((u8 *)iph, 5)))
  46373. goto out_unlock;
  46374. - id = ntohl(*(__be32 *)&iph->id);
  46375. - flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));
  46376. + id = ntohl(net_hdr_word(&iph->id));
  46377. + flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));
  46378. id >>= 16;
  46379. for (p = *head; p; p = p->next) {
  46380. diff -Nur linux-4.1.43.orig/net/ipv4/igmp.c linux-4.1.43/net/ipv4/igmp.c
  46381. --- linux-4.1.43.orig/net/ipv4/igmp.c 2017-08-06 01:56:14.000000000 +0200
  46382. +++ linux-4.1.43/net/ipv4/igmp.c 2017-08-06 20:02:17.000000000 +0200
  46383. @@ -495,7 +495,7 @@
  46384. if (!skb)
  46385. return NULL;
  46386. psrc = (__be32 *)skb_put(skb, sizeof(__be32));
  46387. - *psrc = psf->sf_inaddr;
  46388. + net_hdr_word(psrc) = psf->sf_inaddr;
  46389. scount++; stotal++;
  46390. if ((type == IGMPV3_ALLOW_NEW_SOURCES ||
  46391. type == IGMPV3_BLOCK_OLD_SOURCES) && psf->sf_crcount) {
  46392. diff -Nur linux-4.1.43.orig/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c linux-4.1.43/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
  46393. --- linux-4.1.43.orig/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c 2017-08-06 01:56:14.000000000 +0200
  46394. +++ linux-4.1.43/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c 2017-08-06 20:02:17.000000000 +0200
  46395. @@ -41,8 +41,8 @@
  46396. if (ap == NULL)
  46397. return false;
  46398. - tuple->src.u3.ip = ap[0];
  46399. - tuple->dst.u3.ip = ap[1];
  46400. + tuple->src.u3.ip = net_hdr_word(ap++);
  46401. + tuple->dst.u3.ip = net_hdr_word(ap);
  46402. return true;
  46403. }
  46404. diff -Nur linux-4.1.43.orig/net/ipv4/route.c linux-4.1.43/net/ipv4/route.c
  46405. --- linux-4.1.43.orig/net/ipv4/route.c 2017-08-06 01:56:14.000000000 +0200
  46406. +++ linux-4.1.43/net/ipv4/route.c 2017-08-06 20:02:17.000000000 +0200
  46407. @@ -451,7 +451,7 @@
  46408. else if (skb)
  46409. pkey = &ip_hdr(skb)->daddr;
  46410. - n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey);
  46411. + n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey));
  46412. if (n)
  46413. return n;
  46414. return neigh_create(&arp_tbl, pkey, dev);
  46415. diff -Nur linux-4.1.43.orig/net/ipv4/tcp_input.c linux-4.1.43/net/ipv4/tcp_input.c
  46416. --- linux-4.1.43.orig/net/ipv4/tcp_input.c 2017-08-06 01:56:14.000000000 +0200
  46417. +++ linux-4.1.43/net/ipv4/tcp_input.c 2017-08-06 20:02:17.000000000 +0200
  46418. @@ -3771,14 +3771,16 @@
  46419. {
  46420. const __be32 *ptr = (const __be32 *)(th + 1);
  46421. - if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
  46422. - | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
  46423. + if (net_hdr_word(ptr) ==
  46424. + htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
  46425. + (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
  46426. tp->rx_opt.saw_tstamp = 1;
  46427. ++ptr;
  46428. - tp->rx_opt.rcv_tsval = ntohl(*ptr);
  46429. + tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);
  46430. ++ptr;
  46431. - if (*ptr)
  46432. - tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset;
  46433. + if (net_hdr_word(ptr))
  46434. + tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) -
  46435. + tp->tsoffset;
  46436. else
  46437. tp->rx_opt.rcv_tsecr = 0;
  46438. return true;
  46439. diff -Nur linux-4.1.43.orig/net/ipv4/tcp_output.c linux-4.1.43/net/ipv4/tcp_output.c
  46440. --- linux-4.1.43.orig/net/ipv4/tcp_output.c 2017-08-06 01:56:14.000000000 +0200
  46441. +++ linux-4.1.43/net/ipv4/tcp_output.c 2017-08-06 20:02:17.000000000 +0200
  46442. @@ -452,48 +452,53 @@
  46443. u16 options = opts->options; /* mungable copy */
  46444. if (unlikely(OPTION_MD5 & options)) {
  46445. - *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
  46446. - (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
  46447. + net_hdr_word(ptr++) =
  46448. + htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
  46449. + (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
  46450. /* overload cookie hash location */
  46451. opts->hash_location = (__u8 *)ptr;
  46452. ptr += 4;
  46453. }
  46454. if (unlikely(opts->mss)) {
  46455. - *ptr++ = htonl((TCPOPT_MSS << 24) |
  46456. - (TCPOLEN_MSS << 16) |
  46457. - opts->mss);
  46458. + net_hdr_word(ptr++) =
  46459. + htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
  46460. + opts->mss);
  46461. }
  46462. if (likely(OPTION_TS & options)) {
  46463. if (unlikely(OPTION_SACK_ADVERTISE & options)) {
  46464. - *ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
  46465. - (TCPOLEN_SACK_PERM << 16) |
  46466. - (TCPOPT_TIMESTAMP << 8) |
  46467. - TCPOLEN_TIMESTAMP);
  46468. + net_hdr_word(ptr++) =
  46469. + htonl((TCPOPT_SACK_PERM << 24) |
  46470. + (TCPOLEN_SACK_PERM << 16) |
  46471. + (TCPOPT_TIMESTAMP << 8) |
  46472. + TCPOLEN_TIMESTAMP);
  46473. options &= ~OPTION_SACK_ADVERTISE;
  46474. } else {
  46475. - *ptr++ = htonl((TCPOPT_NOP << 24) |
  46476. - (TCPOPT_NOP << 16) |
  46477. - (TCPOPT_TIMESTAMP << 8) |
  46478. - TCPOLEN_TIMESTAMP);
  46479. + net_hdr_word(ptr++) =
  46480. + htonl((TCPOPT_NOP << 24) |
  46481. + (TCPOPT_NOP << 16) |
  46482. + (TCPOPT_TIMESTAMP << 8) |
  46483. + TCPOLEN_TIMESTAMP);
  46484. }
  46485. - *ptr++ = htonl(opts->tsval);
  46486. - *ptr++ = htonl(opts->tsecr);
  46487. + net_hdr_word(ptr++) = htonl(opts->tsval);
  46488. + net_hdr_word(ptr++) = htonl(opts->tsecr);
  46489. }
  46490. if (unlikely(OPTION_SACK_ADVERTISE & options)) {
  46491. - *ptr++ = htonl((TCPOPT_NOP << 24) |
  46492. - (TCPOPT_NOP << 16) |
  46493. - (TCPOPT_SACK_PERM << 8) |
  46494. - TCPOLEN_SACK_PERM);
  46495. + net_hdr_word(ptr++) =
  46496. + htonl((TCPOPT_NOP << 24) |
  46497. + (TCPOPT_NOP << 16) |
  46498. + (TCPOPT_SACK_PERM << 8) |
  46499. + TCPOLEN_SACK_PERM);
  46500. }
  46501. if (unlikely(OPTION_WSCALE & options)) {
  46502. - *ptr++ = htonl((TCPOPT_NOP << 24) |
  46503. - (TCPOPT_WINDOW << 16) |
  46504. - (TCPOLEN_WINDOW << 8) |
  46505. - opts->ws);
  46506. + net_hdr_word(ptr++) =
  46507. + htonl((TCPOPT_NOP << 24) |
  46508. + (TCPOPT_WINDOW << 16) |
  46509. + (TCPOLEN_WINDOW << 8) |
  46510. + opts->ws);
  46511. }
  46512. if (unlikely(opts->num_sack_blocks)) {
  46513. @@ -501,16 +506,17 @@
  46514. tp->duplicate_sack : tp->selective_acks;
  46515. int this_sack;
  46516. - *ptr++ = htonl((TCPOPT_NOP << 24) |
  46517. - (TCPOPT_NOP << 16) |
  46518. - (TCPOPT_SACK << 8) |
  46519. - (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
  46520. + net_hdr_word(ptr++) =
  46521. + htonl((TCPOPT_NOP << 24) |
  46522. + (TCPOPT_NOP << 16) |
  46523. + (TCPOPT_SACK << 8) |
  46524. + (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
  46525. TCPOLEN_SACK_PERBLOCK)));
  46526. for (this_sack = 0; this_sack < opts->num_sack_blocks;
  46527. ++this_sack) {
  46528. - *ptr++ = htonl(sp[this_sack].start_seq);
  46529. - *ptr++ = htonl(sp[this_sack].end_seq);
  46530. + net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
  46531. + net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
  46532. }
  46533. tp->rx_opt.dsack = 0;
  46534. @@ -523,13 +529,14 @@
  46535. if (foc->exp) {
  46536. len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
  46537. - *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |
  46538. + net_hdr_word(ptr) =
  46539. + htonl((TCPOPT_EXP << 24) | (len << 16) |
  46540. TCPOPT_FASTOPEN_MAGIC);
  46541. p += TCPOLEN_EXP_FASTOPEN_BASE;
  46542. } else {
  46543. len = TCPOLEN_FASTOPEN_BASE + foc->len;
  46544. - *p++ = TCPOPT_FASTOPEN;
  46545. - *p++ = len;
  46546. + net_hdr_word(p++) = TCPOPT_FASTOPEN;
  46547. + net_hdr_word(p++) = len;
  46548. }
  46549. memcpy(p, foc->val, foc->len);
  46550. diff -Nur linux-4.1.43.orig/net/ipv6/datagram.c linux-4.1.43/net/ipv6/datagram.c
  46551. --- linux-4.1.43.orig/net/ipv6/datagram.c 2017-08-06 01:56:14.000000000 +0200
  46552. +++ linux-4.1.43/net/ipv6/datagram.c 2017-08-06 20:02:17.000000000 +0200
  46553. @@ -433,7 +433,7 @@
  46554. ipv6_iface_scope_id(&sin->sin6_addr,
  46555. IP6CB(skb)->iif);
  46556. } else {
  46557. - ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
  46558. + ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
  46559. &sin->sin6_addr);
  46560. sin->sin6_scope_id = 0;
  46561. }
  46562. @@ -770,12 +770,12 @@
  46563. }
  46564. if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
  46565. - if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
  46566. + if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
  46567. err = -EINVAL;
  46568. goto exit_f;
  46569. }
  46570. }
  46571. - fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
  46572. + fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
  46573. break;
  46574. case IPV6_2292HOPOPTS:
  46575. diff -Nur linux-4.1.43.orig/net/ipv6/exthdrs.c linux-4.1.43/net/ipv6/exthdrs.c
  46576. --- linux-4.1.43.orig/net/ipv6/exthdrs.c 2017-08-06 01:56:14.000000000 +0200
  46577. +++ linux-4.1.43/net/ipv6/exthdrs.c 2017-08-06 20:02:17.000000000 +0200
  46578. @@ -573,7 +573,7 @@
  46579. goto drop;
  46580. }
  46581. - pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
  46582. + pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
  46583. if (pkt_len <= IPV6_MAXPLEN) {
  46584. IP6_INC_STATS_BH(net, ipv6_skb_idev(skb),
  46585. IPSTATS_MIB_INHDRERRORS);
  46586. diff -Nur linux-4.1.43.orig/net/ipv6/ip6_fib.c linux-4.1.43/net/ipv6/ip6_fib.c
  46587. --- linux-4.1.43.orig/net/ipv6/ip6_fib.c 2017-08-06 01:56:14.000000000 +0200
  46588. +++ linux-4.1.43/net/ipv6/ip6_fib.c 2017-08-06 20:02:17.000000000 +0200
  46589. @@ -137,7 +137,7 @@
  46590. * See include/asm-generic/bitops/le.h.
  46591. */
  46592. return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) &
  46593. - addr[fn_bit >> 5];
  46594. + net_hdr_word(&addr[fn_bit >> 5]);
  46595. }
  46596. static struct fib6_node *node_alloc(void)
  46597. diff -Nur linux-4.1.43.orig/net/ipv6/ip6_gre.c linux-4.1.43/net/ipv6/ip6_gre.c
  46598. --- linux-4.1.43.orig/net/ipv6/ip6_gre.c 2017-08-06 01:56:14.000000000 +0200
  46599. +++ linux-4.1.43/net/ipv6/ip6_gre.c 2017-08-06 20:02:17.000000000 +0200
  46600. @@ -394,7 +394,7 @@
  46601. t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr,
  46602. flags & GRE_KEY ?
  46603. - *(((__be32 *)p) + (grehlen / 4) - 1) : 0,
  46604. + net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1) : 0,
  46605. p[1]);
  46606. if (!t)
  46607. return;
  46608. @@ -476,11 +476,11 @@
  46609. offset += 4;
  46610. }
  46611. if (flags&GRE_KEY) {
  46612. - key = *(__be32 *)(h + offset);
  46613. + key = net_hdr_word(h + offset);
  46614. offset += 4;
  46615. }
  46616. if (flags&GRE_SEQ) {
  46617. - seqno = ntohl(*(__be32 *)(h + offset));
  46618. + seqno = ntohl(net_hdr_word(h + offset));
  46619. offset += 4;
  46620. }
  46621. }
  46622. @@ -745,7 +745,7 @@
  46623. if (tunnel->parms.o_flags&GRE_SEQ) {
  46624. ++tunnel->o_seqno;
  46625. - *ptr = htonl(tunnel->o_seqno);
  46626. + net_hdr_word(ptr) = htonl(tunnel->o_seqno);
  46627. ptr--;
  46628. }
  46629. if (tunnel->parms.o_flags&GRE_KEY) {
  46630. @@ -843,7 +843,7 @@
  46631. dsfield = ipv6_get_dsfield(ipv6h);
  46632. if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
  46633. - fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
  46634. + fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
  46635. if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
  46636. fl6.flowlabel |= ip6_flowlabel(ipv6h);
  46637. if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
  46638. diff -Nur linux-4.1.43.orig/net/ipv6/ip6_offload.c linux-4.1.43/net/ipv6/ip6_offload.c
  46639. --- linux-4.1.43.orig/net/ipv6/ip6_offload.c 2017-08-06 01:56:14.000000000 +0200
  46640. +++ linux-4.1.43/net/ipv6/ip6_offload.c 2017-08-06 20:02:17.000000000 +0200
  46641. @@ -224,7 +224,7 @@
  46642. continue;
  46643. iph2 = (struct ipv6hdr *)(p->data + off);
  46644. - first_word = *(__be32 *)iph ^ *(__be32 *)iph2;
  46645. + first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
  46646. /* All fields must match except length and Traffic Class.
  46647. * XXX skbs on the gro_list have all been parsed and pulled
  46648. diff -Nur linux-4.1.43.orig/net/ipv6/ip6_tunnel.c linux-4.1.43/net/ipv6/ip6_tunnel.c
  46649. --- linux-4.1.43.orig/net/ipv6/ip6_tunnel.c 2017-08-06 01:56:14.000000000 +0200
  46650. +++ linux-4.1.43/net/ipv6/ip6_tunnel.c 2017-08-06 20:02:17.000000000 +0200
  46651. @@ -1192,7 +1192,7 @@
  46652. dsfield = ipv6_get_dsfield(ipv6h);
  46653. if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
  46654. - fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
  46655. + fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
  46656. if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
  46657. fl6.flowlabel |= ip6_flowlabel(ipv6h);
  46658. if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
  46659. diff -Nur linux-4.1.43.orig/net/ipv6/netfilter/nf_log_ipv6.c linux-4.1.43/net/ipv6/netfilter/nf_log_ipv6.c
  46660. --- linux-4.1.43.orig/net/ipv6/netfilter/nf_log_ipv6.c 2017-08-06 01:56:14.000000000 +0200
  46661. +++ linux-4.1.43/net/ipv6/netfilter/nf_log_ipv6.c 2017-08-06 20:02:17.000000000 +0200
  46662. @@ -66,9 +66,9 @@
  46663. /* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */
  46664. nf_log_buf_add(m, "LEN=%Zu TC=%u HOPLIMIT=%u FLOWLBL=%u ",
  46665. ntohs(ih->payload_len) + sizeof(struct ipv6hdr),
  46666. - (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20,
  46667. + (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20,
  46668. ih->hop_limit,
  46669. - (ntohl(*(__be32 *)ih) & 0x000fffff));
  46670. + (ntohl(net_hdr_word(ih)) & 0x000fffff));
  46671. fragment = 0;
  46672. ptr = ip6hoff + sizeof(struct ipv6hdr);
  46673. diff -Nur linux-4.1.43.orig/net/ipv6/tcp_ipv6.c linux-4.1.43/net/ipv6/tcp_ipv6.c
  46674. --- linux-4.1.43.orig/net/ipv6/tcp_ipv6.c 2017-08-06 01:56:14.000000000 +0200
  46675. +++ linux-4.1.43/net/ipv6/tcp_ipv6.c 2017-08-06 20:02:17.000000000 +0200
  46676. @@ -39,6 +39,7 @@
  46677. #include <linux/ipsec.h>
  46678. #include <linux/times.h>
  46679. #include <linux/slab.h>
  46680. +#include <asm/unaligned.h>
  46681. #include <linux/uaccess.h>
  46682. #include <linux/ipv6.h>
  46683. #include <linux/icmpv6.h>
  46684. @@ -781,10 +782,10 @@
  46685. topt = (__be32 *)(t1 + 1);
  46686. if (tsecr) {
  46687. - *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
  46688. - (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
  46689. - *topt++ = htonl(tsval);
  46690. - *topt++ = htonl(tsecr);
  46691. + put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
  46692. + (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
  46693. + put_unaligned_be32(tsval, topt++);
  46694. + put_unaligned_be32(tsecr, topt++);
  46695. }
  46696. #ifdef CONFIG_TCP_MD5SIG
  46697. diff -Nur linux-4.1.43.orig/net/netfilter/nf_conntrack_proto_tcp.c linux-4.1.43/net/netfilter/nf_conntrack_proto_tcp.c
  46698. --- linux-4.1.43.orig/net/netfilter/nf_conntrack_proto_tcp.c 2017-08-06 01:56:14.000000000 +0200
  46699. +++ linux-4.1.43/net/netfilter/nf_conntrack_proto_tcp.c 2017-08-06 20:02:17.000000000 +0200
  46700. @@ -453,7 +453,7 @@
  46701. /* Fast path for timestamp-only option */
  46702. if (length == TCPOLEN_TSTAMP_ALIGNED
  46703. - && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24)
  46704. + && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24)
  46705. | (TCPOPT_NOP << 16)
  46706. | (TCPOPT_TIMESTAMP << 8)
  46707. | TCPOLEN_TIMESTAMP))
  46708. diff -Nur linux-4.1.43.orig/net/sched/cls_u32.c linux-4.1.43/net/sched/cls_u32.c
  46709. --- linux-4.1.43.orig/net/sched/cls_u32.c 2017-08-06 01:56:14.000000000 +0200
  46710. +++ linux-4.1.43/net/sched/cls_u32.c 2017-08-06 20:02:17.000000000 +0200
  46711. @@ -151,7 +151,7 @@
  46712. data = skb_header_pointer(skb, toff, 4, &hdata);
  46713. if (!data)
  46714. goto out;
  46715. - if ((*data ^ key->val) & key->mask) {
  46716. + if ((net_hdr_word(data) ^ key->val) & key->mask) {
  46717. n = rcu_dereference_bh(n->next);
  46718. goto next_knode;
  46719. }
  46720. @@ -204,8 +204,8 @@
  46721. &hdata);
  46722. if (!data)
  46723. goto out;
  46724. - sel = ht->divisor & u32_hash_fold(*data, &n->sel,
  46725. - n->fshift);
  46726. + sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
  46727. + &n->sel, n->fshift);
  46728. }
  46729. if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
  46730. goto next_ht;
  46731. diff -Nur linux-4.1.43.orig/net/xfrm/xfrm_input.c linux-4.1.43/net/xfrm/xfrm_input.c
  46732. --- linux-4.1.43.orig/net/xfrm/xfrm_input.c 2017-08-06 01:56:14.000000000 +0200
  46733. +++ linux-4.1.43/net/xfrm/xfrm_input.c 2017-08-06 20:02:17.000000000 +0200
  46734. @@ -154,8 +154,8 @@
  46735. if (!pskb_may_pull(skb, hlen))
  46736. return -EINVAL;
  46737. - *spi = *(__be32 *)(skb_transport_header(skb) + offset);
  46738. - *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq);
  46739. + *spi = net_hdr_word(skb_transport_header(skb) + offset);
  46740. + *seq = net_hdr_word(skb_transport_header(skb) + offset_seq);
  46741. return 0;
  46742. }