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j2.patch 60 KB

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  1. diff -Nur binutils-2.27.orig/bfd/archures.c binutils-2.27/bfd/archures.c
  2. --- binutils-2.27.orig/bfd/archures.c 2016-08-03 09:36:50.000000000 +0200
  3. +++ binutils-2.27/bfd/archures.c 2016-12-10 15:34:01.954875361 +0100
  4. @@ -310,10 +310,12 @@
  5. .#define bfd_mach_sh_dsp 0x2d
  6. .#define bfd_mach_sh2a 0x2a
  7. .#define bfd_mach_sh2a_nofpu 0x2b
  8. +.#define bfd_mach_shj2 0x2c
  9. .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
  10. .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
  11. .#define bfd_mach_sh2a_or_sh4 0x2a3
  12. .#define bfd_mach_sh2a_or_sh3e 0x2a4
  13. +.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
  14. .#define bfd_mach_sh2e 0x2e
  15. .#define bfd_mach_sh3 0x30
  16. .#define bfd_mach_sh3_nommu 0x31
  17. diff -Nur binutils-2.27.orig/bfd/bfd-in2.h binutils-2.27/bfd/bfd-in2.h
  18. --- binutils-2.27.orig/bfd/bfd-in2.h 2016-08-03 09:36:50.000000000 +0200
  19. +++ binutils-2.27/bfd/bfd-in2.h 2016-12-10 15:34:01.978874153 +0100
  20. @@ -2121,10 +2121,12 @@
  21. #define bfd_mach_sh_dsp 0x2d
  22. #define bfd_mach_sh2a 0x2a
  23. #define bfd_mach_sh2a_nofpu 0x2b
  24. +#define bfd_mach_shj2 0x2c
  25. #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
  26. #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
  27. #define bfd_mach_sh2a_or_sh4 0x2a3
  28. #define bfd_mach_sh2a_or_sh3e 0x2a4
  29. +#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
  30. #define bfd_mach_sh2e 0x2e
  31. #define bfd_mach_sh3 0x30
  32. #define bfd_mach_sh3_nommu 0x31
  33. diff -Nur binutils-2.27.orig/bfd/cpu-sh.c binutils-2.27/bfd/cpu-sh.c
  34. --- binutils-2.27.orig/bfd/cpu-sh.c 2016-08-03 09:36:50.000000000 +0200
  35. +++ binutils-2.27/bfd/cpu-sh.c 2016-12-10 15:34:01.978874153 +0100
  36. @@ -44,7 +44,9 @@
  37. #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
  38. #define SH2A_OR_SH4_NEXT arch_info_struct + 18
  39. #define SH2A_OR_SH3E_NEXT arch_info_struct + 19
  40. -#define SH64_NEXT NULL
  41. +#define SH64_NEXT arch_info_struct + 20
  42. +#define SHJ2_NEXT arch_info_struct + 21
  43. +#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
  44. static const bfd_arch_info_type arch_info_struct[] =
  45. {
  46. @@ -348,6 +350,36 @@
  47. bfd_arch_default_fill,
  48. SH64_NEXT
  49. },
  50. + {
  51. + 32, /* 32 bits in a word. */
  52. + 32, /* 32 bits in an address. */
  53. + 8, /* 8 bits in a byte. */
  54. + bfd_arch_sh,
  55. + bfd_mach_shj2,
  56. + "sh", /* Architecture name. . */
  57. + "j2", /* Machine name. */
  58. + 1,
  59. + FALSE, /* Not the default. */
  60. + bfd_default_compatible,
  61. + bfd_default_scan,
  62. + bfd_arch_default_fill,
  63. + SHJ2_NEXT
  64. + },
  65. + {
  66. + 32, /* 32 bits in a word. */
  67. + 32, /* 32 bits in an address. */
  68. + 8, /* 8 bits in a byte. */
  69. + bfd_arch_sh,
  70. + bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
  71. + "sh", /* Architecture name. . */
  72. + "sh2a-or-sh3e-or-j2", /* Machine name. */
  73. + 1,
  74. + FALSE, /* Not the default. */
  75. + bfd_default_compatible,
  76. + bfd_default_scan,
  77. + bfd_arch_default_fill,
  78. + SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
  79. + },
  80. };
  81. const bfd_arch_info_type bfd_sh_arch =
  82. @@ -398,6 +430,8 @@
  83. { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
  84. { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
  85. { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
  86. + { bfd_mach_shj2, arch_shj2, arch_shj2_up },
  87. + { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
  88. { 0, 0, 0 } /* Terminator. */
  89. };
  90. diff -Nur binutils-2.27.orig/bfd/elf32-sh.c binutils-2.27/bfd/elf32-sh.c
  91. --- binutils-2.27.orig/bfd/elf32-sh.c 2016-08-03 09:36:51.000000000 +0200
  92. +++ binutils-2.27/bfd/elf32-sh.c 2016-12-10 15:34:06.138680918 +0100
  93. @@ -5682,220 +5682,6 @@
  94. return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
  95. }
  96. -/* Update the got entry reference counts for the section being removed. */
  97. -
  98. -static bfd_boolean
  99. -sh_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info,
  100. - asection *sec, const Elf_Internal_Rela *relocs)
  101. -{
  102. - Elf_Internal_Shdr *symtab_hdr;
  103. - struct elf_link_hash_entry **sym_hashes;
  104. - bfd_signed_vma *local_got_refcounts;
  105. - union gotref *local_funcdesc;
  106. - const Elf_Internal_Rela *rel, *relend;
  107. -
  108. - if (bfd_link_relocatable (info))
  109. - return TRUE;
  110. -
  111. - elf_section_data (sec)->local_dynrel = NULL;
  112. -
  113. - symtab_hdr = &elf_symtab_hdr (abfd);
  114. - sym_hashes = elf_sym_hashes (abfd);
  115. - local_got_refcounts = elf_local_got_refcounts (abfd);
  116. - local_funcdesc = sh_elf_local_funcdesc (abfd);
  117. -
  118. - relend = relocs + sec->reloc_count;
  119. - for (rel = relocs; rel < relend; rel++)
  120. - {
  121. - unsigned long r_symndx;
  122. - unsigned int r_type;
  123. - struct elf_link_hash_entry *h = NULL;
  124. -#ifdef INCLUDE_SHMEDIA
  125. - int seen_stt_datalabel = 0;
  126. -#endif
  127. -
  128. - r_symndx = ELF32_R_SYM (rel->r_info);
  129. - if (r_symndx >= symtab_hdr->sh_info)
  130. - {
  131. - struct elf_sh_link_hash_entry *eh;
  132. - struct elf_sh_dyn_relocs **pp;
  133. - struct elf_sh_dyn_relocs *p;
  134. -
  135. - h = sym_hashes[r_symndx - symtab_hdr->sh_info];
  136. - while (h->root.type == bfd_link_hash_indirect
  137. - || h->root.type == bfd_link_hash_warning)
  138. - {
  139. -#ifdef INCLUDE_SHMEDIA
  140. - seen_stt_datalabel |= h->type == STT_DATALABEL;
  141. -#endif
  142. - h = (struct elf_link_hash_entry *) h->root.u.i.link;
  143. - }
  144. - eh = (struct elf_sh_link_hash_entry *) h;
  145. - for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next)
  146. - if (p->sec == sec)
  147. - {
  148. - /* Everything must go for SEC. */
  149. - *pp = p->next;
  150. - break;
  151. - }
  152. - }
  153. -
  154. - r_type = ELF32_R_TYPE (rel->r_info);
  155. - switch (sh_elf_optimized_tls_reloc (info, r_type, h != NULL))
  156. - {
  157. - case R_SH_TLS_LD_32:
  158. - if (sh_elf_hash_table (info)->tls_ldm_got.refcount > 0)
  159. - sh_elf_hash_table (info)->tls_ldm_got.refcount -= 1;
  160. - break;
  161. -
  162. - case R_SH_GOT32:
  163. - case R_SH_GOT20:
  164. - case R_SH_GOTOFF:
  165. - case R_SH_GOTOFF20:
  166. - case R_SH_GOTPC:
  167. -#ifdef INCLUDE_SHMEDIA
  168. - case R_SH_GOT_LOW16:
  169. - case R_SH_GOT_MEDLOW16:
  170. - case R_SH_GOT_MEDHI16:
  171. - case R_SH_GOT_HI16:
  172. - case R_SH_GOT10BY4:
  173. - case R_SH_GOT10BY8:
  174. - case R_SH_GOTOFF_LOW16:
  175. - case R_SH_GOTOFF_MEDLOW16:
  176. - case R_SH_GOTOFF_MEDHI16:
  177. - case R_SH_GOTOFF_HI16:
  178. - case R_SH_GOTPC_LOW16:
  179. - case R_SH_GOTPC_MEDLOW16:
  180. - case R_SH_GOTPC_MEDHI16:
  181. - case R_SH_GOTPC_HI16:
  182. -#endif
  183. - case R_SH_TLS_GD_32:
  184. - case R_SH_TLS_IE_32:
  185. - case R_SH_GOTFUNCDESC:
  186. - case R_SH_GOTFUNCDESC20:
  187. - if (h != NULL)
  188. - {
  189. -#ifdef INCLUDE_SHMEDIA
  190. - if (seen_stt_datalabel)
  191. - {
  192. - struct elf_sh_link_hash_entry *eh;
  193. - eh = (struct elf_sh_link_hash_entry *) h;
  194. - if (eh->datalabel_got.refcount > 0)
  195. - eh->datalabel_got.refcount -= 1;
  196. - }
  197. - else
  198. -#endif
  199. - if (h->got.refcount > 0)
  200. - h->got.refcount -= 1;
  201. - }
  202. - else if (local_got_refcounts != NULL)
  203. - {
  204. -#ifdef INCLUDE_SHMEDIA
  205. - if (rel->r_addend & 1)
  206. - {
  207. - if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0)
  208. - local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1;
  209. - }
  210. - else
  211. -#endif
  212. - if (local_got_refcounts[r_symndx] > 0)
  213. - local_got_refcounts[r_symndx] -= 1;
  214. - }
  215. - break;
  216. -
  217. - case R_SH_FUNCDESC:
  218. - if (h != NULL)
  219. - sh_elf_hash_entry (h)->abs_funcdesc_refcount -= 1;
  220. - else if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info))
  221. - sh_elf_hash_table (info)->srofixup->size -= 4;
  222. -
  223. - /* Fall through. */
  224. -
  225. - case R_SH_GOTOFFFUNCDESC:
  226. - case R_SH_GOTOFFFUNCDESC20:
  227. - if (h != NULL)
  228. - sh_elf_hash_entry (h)->funcdesc.refcount -= 1;
  229. - else
  230. - local_funcdesc[r_symndx].refcount -= 1;
  231. - break;
  232. -
  233. - case R_SH_DIR32:
  234. - if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info)
  235. - && (sec->flags & SEC_ALLOC) != 0)
  236. - sh_elf_hash_table (info)->srofixup->size -= 4;
  237. - /* Fall thru */
  238. -
  239. - case R_SH_REL32:
  240. - if (bfd_link_pic (info))
  241. - break;
  242. - /* Fall thru */
  243. -
  244. - case R_SH_PLT32:
  245. -#ifdef INCLUDE_SHMEDIA
  246. - case R_SH_PLT_LOW16:
  247. - case R_SH_PLT_MEDLOW16:
  248. - case R_SH_PLT_MEDHI16:
  249. - case R_SH_PLT_HI16:
  250. -#endif
  251. - if (h != NULL)
  252. - {
  253. - if (h->plt.refcount > 0)
  254. - h->plt.refcount -= 1;
  255. - }
  256. - break;
  257. -
  258. - case R_SH_GOTPLT32:
  259. -#ifdef INCLUDE_SHMEDIA
  260. - case R_SH_GOTPLT_LOW16:
  261. - case R_SH_GOTPLT_MEDLOW16:
  262. - case R_SH_GOTPLT_MEDHI16:
  263. - case R_SH_GOTPLT_HI16:
  264. - case R_SH_GOTPLT10BY4:
  265. - case R_SH_GOTPLT10BY8:
  266. -#endif
  267. - if (h != NULL)
  268. - {
  269. - struct elf_sh_link_hash_entry *eh;
  270. - eh = (struct elf_sh_link_hash_entry *) h;
  271. - if (eh->gotplt_refcount > 0)
  272. - {
  273. - eh->gotplt_refcount -= 1;
  274. - if (h->plt.refcount > 0)
  275. - h->plt.refcount -= 1;
  276. - }
  277. -#ifdef INCLUDE_SHMEDIA
  278. - else if (seen_stt_datalabel)
  279. - {
  280. - if (eh->datalabel_got.refcount > 0)
  281. - eh->datalabel_got.refcount -= 1;
  282. - }
  283. -#endif
  284. - else if (h->got.refcount > 0)
  285. - h->got.refcount -= 1;
  286. - }
  287. - else if (local_got_refcounts != NULL)
  288. - {
  289. -#ifdef INCLUDE_SHMEDIA
  290. - if (rel->r_addend & 1)
  291. - {
  292. - if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0)
  293. - local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1;
  294. - }
  295. - else
  296. -#endif
  297. - if (local_got_refcounts[r_symndx] > 0)
  298. - local_got_refcounts[r_symndx] -= 1;
  299. - }
  300. - break;
  301. -
  302. - default:
  303. - break;
  304. - }
  305. - }
  306. -
  307. - return TRUE;
  308. -}
  309. -
  310. /* Copy the extra info we tack onto an elf_link_hash_entry. */
  311. static void
  312. @@ -7455,7 +7241,6 @@
  313. sh_elf_merge_private_data
  314. #define elf_backend_gc_mark_hook sh_elf_gc_mark_hook
  315. -#define elf_backend_gc_sweep_hook sh_elf_gc_sweep_hook
  316. #define elf_backend_check_relocs sh_elf_check_relocs
  317. #define elf_backend_copy_indirect_symbol \
  318. sh_elf_copy_indirect_symbol
  319. diff -Nur binutils-2.27.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c
  320. --- binutils-2.27.orig/binutils/readelf.c 2016-08-03 09:36:51.000000000 +0200
  321. +++ binutils-2.27/binutils/readelf.c 2016-12-10 15:34:01.978874153 +0100
  322. @@ -3307,6 +3307,8 @@
  323. case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
  324. case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
  325. case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
  326. + case EF_SHJ2: strcat (buf, ", j2"); break;
  327. + case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
  328. default: strcat (buf, _(", unknown ISA")); break;
  329. }
  330. diff -Nur binutils-2.27.orig/gas/config/tc-sh.c binutils-2.27/gas/config/tc-sh.c
  331. --- binutils-2.27.orig/gas/config/tc-sh.c 2016-08-03 09:36:51.000000000 +0200
  332. +++ binutils-2.27/gas/config/tc-sh.c 2016-12-10 15:34:01.982873978 +0100
  333. @@ -1648,6 +1648,8 @@
  334. ptr++;
  335. }
  336. get_operand (&ptr, operand + 2);
  337. + if (strcmp (info->name,"cas") == 0)
  338. + operand[2].type = A_IND_0;
  339. }
  340. else
  341. {
  342. @@ -2187,7 +2189,10 @@
  343. goto fail;
  344. reg_m = 4;
  345. break;
  346. -
  347. + case A_IND_0:
  348. + if (user->reg != 0)
  349. + goto fail;
  350. + break;
  351. default:
  352. printf (_("unhandled %d\n"), arg);
  353. goto fail;
  354. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
  355. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2015-11-13 09:27:41.000000000 +0100
  356. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2016-12-10 15:34:01.994873426 +0100
  357. @@ -12,8 +12,6 @@
  358. sh2a_nofpu_or_sh3_nommu:
  359. ! Instructions introduced into sh2a-nofpu-or-sh3-nommu
  360. pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
  361. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  362. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  363. ! Instructions inherited from ancestors: sh sh2
  364. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  365. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
  366. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  367. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2016-12-10 15:34:02.006872864 +0100
  368. @@ -12,7 +12,7 @@
  369. sh2a_nofpu_or_sh4_nommu_nofpu:
  370. ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
  371. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
  372. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
  373. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  374. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  375. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  376. @@ -119,8 +119,8 @@
  377. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  378. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  379. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  380. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  381. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  382. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  383. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  384. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  385. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  386. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  387. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
  388. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  389. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2016-12-10 15:34:02.006872864 +0100
  390. @@ -64,7 +64,7 @@
  391. movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
  392. movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
  393. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
  394. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
  395. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  396. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  397. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  398. @@ -171,8 +171,8 @@
  399. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  400. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  401. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  402. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  403. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  404. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  405. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  406. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  407. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  408. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  409. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
  410. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2015-11-13 09:27:41.000000000 +0100
  411. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2016-12-10 15:34:02.006872864 +0100
  412. @@ -13,7 +13,7 @@
  413. ! Instructions introduced into sh2a-or-sh3e
  414. fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
  415. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
  416. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
  417. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  418. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  419. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  420. @@ -124,8 +124,8 @@
  421. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  422. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  423. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  424. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  425. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  426. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  427. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  428. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  429. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  430. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  431. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
  432. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2015-11-13 09:27:41.000000000 +0100
  433. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2016-12-10 15:34:02.010872679 +0100
  434. @@ -39,7 +39,7 @@
  435. fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
  436. ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
  437. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
  438. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
  439. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  440. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  441. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  442. @@ -150,8 +150,8 @@
  443. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  444. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  445. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  446. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  447. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  448. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  449. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  450. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  451. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  452. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  453. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s
  454. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s 2015-11-13 09:27:41.000000000 +0100
  455. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s 2016-12-10 15:34:02.010872679 +0100
  456. @@ -16,7 +16,7 @@
  457. fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
  458. fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
  459. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
  460. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
  461. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  462. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  463. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  464. @@ -140,8 +140,8 @@
  465. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  466. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  467. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  468. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  469. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  470. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  471. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  472. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  473. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  474. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  475. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s
  476. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2015-11-13 09:27:41.000000000 +0100
  477. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s 2016-12-10 15:34:02.010872679 +0100
  478. @@ -12,7 +12,7 @@
  479. sh3_dsp:
  480. ! Instructions introduced into sh3-dsp
  481. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
  482. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
  483. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  484. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  485. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  486. @@ -152,8 +152,8 @@
  487. setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
  488. repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
  489. repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
  490. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  491. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  492. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  493. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  494. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  495. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  496. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  497. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s
  498. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s 2015-11-13 09:27:41.000000000 +0100
  499. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s 2016-12-10 15:34:02.010872679 +0100
  500. @@ -12,7 +12,7 @@
  501. sh3e:
  502. ! Instructions introduced into sh3e
  503. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
  504. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
  505. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  506. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  507. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  508. @@ -132,8 +132,8 @@
  509. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  510. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  511. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  512. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  513. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  514. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  515. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  516. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  517. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  518. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  519. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s
  520. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2015-11-13 09:27:41.000000000 +0100
  521. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s 2016-12-10 15:34:02.010872679 +0100
  522. @@ -26,7 +26,7 @@
  523. stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
  524. stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
  525. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
  526. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
  527. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  528. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  529. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  530. @@ -133,8 +133,8 @@
  531. rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
  532. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  533. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  534. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  535. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  536. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  537. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  538. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  539. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  540. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  541. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s
  542. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s 2015-11-13 09:27:41.000000000 +0100
  543. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s 2016-12-10 15:34:02.010872679 +0100
  544. @@ -13,7 +13,7 @@
  545. ! Instructions introduced into sh3
  546. ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
  547. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
  548. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
  549. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  550. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  551. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  552. @@ -128,8 +128,8 @@
  553. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  554. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  555. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  556. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  557. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  558. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  559. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  560. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  561. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  562. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  563. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s
  564. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2015-11-13 09:27:41.000000000 +0100
  565. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2016-12-10 15:34:02.018872308 +0100
  566. @@ -48,7 +48,7 @@
  567. dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
  568. dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
  569. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  570. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  571. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  572. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  573. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  574. @@ -202,8 +202,8 @@
  575. setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
  576. repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
  577. repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
  578. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  579. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  580. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  581. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  582. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  583. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  584. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  585. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
  586. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  587. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2016-12-10 15:34:02.014872493 +0100
  588. @@ -19,7 +19,7 @@
  589. prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
  590. synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
  591. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
  592. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
  593. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  594. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  595. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  596. @@ -143,8 +143,8 @@
  597. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  598. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  599. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  600. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  601. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  602. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  603. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  604. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  605. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  606. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  607. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s
  608. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s 2015-11-13 09:27:41.000000000 +0100
  609. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s 2016-12-10 15:34:02.014872493 +0100
  610. @@ -13,7 +13,7 @@
  611. ! Instructions introduced into sh4a
  612. fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
  613. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  614. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
  615. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  616. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  617. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  618. @@ -147,8 +147,8 @@
  619. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  620. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  621. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  622. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  623. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  624. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  625. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  626. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  627. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  628. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  629. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s
  630. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  631. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2016-12-10 15:34:02.014872493 +0100
  632. @@ -12,7 +12,7 @@
  633. sh4_nofpu:
  634. ! Instructions introduced into sh4-nofpu
  635. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
  636. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
  637. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  638. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  639. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  640. @@ -136,8 +136,8 @@
  641. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  642. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  643. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  644. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  645. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  646. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  647. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  648. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  649. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  650. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  651. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
  652. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2015-11-13 09:27:41.000000000 +0100
  653. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2016-12-10 15:34:02.014872493 +0100
  654. @@ -24,7 +24,7 @@
  655. stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
  656. stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
  657. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
  658. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
  659. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  660. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  661. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  662. @@ -139,8 +139,8 @@
  663. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  664. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  665. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  666. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  667. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  668. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  669. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  670. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  671. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  672. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  673. diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s
  674. --- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s 2015-11-13 09:27:41.000000000 +0100
  675. +++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s 2016-12-10 15:34:02.014872493 +0100
  676. @@ -17,7 +17,7 @@
  677. fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
  678. ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
  679. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
  680. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
  681. add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
  682. add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
  683. addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
  684. @@ -145,8 +145,8 @@
  685. rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
  686. sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
  687. sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
  688. - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
  689. - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
  690. + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  691. + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
  692. shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
  693. shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
  694. shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
  695. diff -Nur binutils-2.27.orig/include/elf/sh.h binutils-2.27/include/elf/sh.h
  696. --- binutils-2.27.orig/include/elf/sh.h 2016-08-03 09:36:53.000000000 +0200
  697. +++ binutils-2.27/include/elf/sh.h 2016-12-10 15:34:02.018872308 +0100
  698. @@ -39,6 +39,7 @@
  699. #define EF_SH2E 11
  700. #define EF_SH4A 12
  701. #define EF_SH2A 13
  702. +#define EF_SHJ2 14
  703. #define EF_SH4_NOFPU 16
  704. #define EF_SH4A_NOFPU 17
  705. @@ -50,6 +51,7 @@
  706. #define EF_SH2A_SH3_NOFPU 22
  707. #define EF_SH2A_SH4 23
  708. #define EF_SH2A_SH3E 24
  709. +#define EF_SH2A_SH3_SHJ2 25
  710. /* This one can only mix in objects from other EF_SH5 objects. */
  711. #define EF_SH5 10
  712. @@ -72,7 +74,8 @@
  713. /* EF_SH2E */ bfd_mach_sh2e , \
  714. /* EF_SH4A */ bfd_mach_sh4a , \
  715. /* EF_SH2A */ bfd_mach_sh2a , \
  716. -/* 14, 15 */ 0, 0, \
  717. +/* EF_SHJ2 */ bfd_mach_shj2 , \
  718. +/* 15 */ 0, \
  719. /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
  720. /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
  721. /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
  722. @@ -81,7 +84,8 @@
  723. /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
  724. /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
  725. /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
  726. -/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
  727. +/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
  728. +/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
  729. /* Convert arch_sh* into EF_SH*. */
  730. int sh_find_elf_flags (unsigned int arch_set);
  731. diff -Nur binutils-2.27.orig/ld/emulparams/shelf32.sh binutils-2.27/ld/emulparams/shelf32.sh
  732. --- binutils-2.27.orig/ld/emulparams/shelf32.sh 2013-11-04 16:33:39.000000000 +0100
  733. +++ binutils-2.27/ld/emulparams/shelf32.sh 2016-12-10 15:34:06.138680918 +0100
  734. @@ -11,6 +11,9 @@
  735. TEMPLATE_NAME=elf32
  736. GENERATE_SHLIB_SCRIPT=yes
  737. EMBEDDED=yes
  738. +# PR 17739. Delay checking relocs until after all files have
  739. +# been opened and linker garbage collection has taken place.
  740. +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
  741. DATA_START_SYMBOLS='PROVIDE (___data = .);'
  742. diff -Nur binutils-2.27.orig/ld/emulparams/shelf_nto.sh binutils-2.27/ld/emulparams/shelf_nto.sh
  743. --- binutils-2.27.orig/ld/emulparams/shelf_nto.sh 2013-11-04 16:33:39.000000000 +0100
  744. +++ binutils-2.27/ld/emulparams/shelf_nto.sh 2016-12-10 15:34:06.138680918 +0100
  745. @@ -9,3 +9,6 @@
  746. GENERATE_SHLIB_SCRIPT=yes
  747. TEXT_START_SYMBOLS='_btext = .;'
  748. ENTRY=_start
  749. +# PR 17739. Delay checking relocs until after all files have
  750. +# been opened and linker garbage collection has taken place.
  751. +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
  752. diff -Nur binutils-2.27.orig/ld/emulparams/shelf.sh binutils-2.27/ld/emulparams/shelf.sh
  753. --- binutils-2.27.orig/ld/emulparams/shelf.sh 2016-08-03 09:36:54.000000000 +0200
  754. +++ binutils-2.27/ld/emulparams/shelf.sh 2016-12-10 15:34:06.138680918 +0100
  755. @@ -11,6 +11,9 @@
  756. TEMPLATE_NAME=elf32
  757. GENERATE_SHLIB_SCRIPT=yes
  758. EMBEDDED=yes
  759. +# PR 17739. Delay checking relocs until after all files have
  760. +# been opened and linker garbage collection has taken place.
  761. +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
  762. # These are for compatibility with the COFF toolchain.
  763. ENTRY=start
  764. diff -Nur binutils-2.27.orig/ld/emulparams/shelf_vxworks.sh binutils-2.27/ld/emulparams/shelf_vxworks.sh
  765. --- binutils-2.27.orig/ld/emulparams/shelf_vxworks.sh 2013-11-04 16:33:39.000000000 +0100
  766. +++ binutils-2.27/ld/emulparams/shelf_vxworks.sh 2016-12-10 15:34:06.138680918 +0100
  767. @@ -14,6 +14,10 @@
  768. GENERATE_SHLIB_SCRIPT=yes
  769. ENTRY=__start
  770. SYMPREFIX=_
  771. +# PR 17739. Delay checking relocs until after all files have
  772. +# been opened and linker garbage collection has taken place.
  773. +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
  774. +
  775. GOT=".got ${RELOCATING-0} : {
  776. PROVIDE(__GLOBAL_OFFSET_TABLE_ = .);
  777. *(.got.plt) *(.got) }"
  778. diff -Nur binutils-2.27.orig/ld/emulparams/shlelf32_linux.sh binutils-2.27/ld/emulparams/shlelf32_linux.sh
  779. --- binutils-2.27.orig/ld/emulparams/shlelf32_linux.sh 2013-11-04 16:33:39.000000000 +0100
  780. +++ binutils-2.27/ld/emulparams/shlelf32_linux.sh 2016-12-10 15:34:06.138680918 +0100
  781. @@ -13,7 +13,9 @@
  782. TEMPLATE_NAME=elf32
  783. GENERATE_SHLIB_SCRIPT=yes
  784. GENERATE_PIE_SCRIPT=yes
  785. -
  786. +# PR 17739. Delay checking relocs until after all files have
  787. +# been opened and linker garbage collection has taken place.
  788. +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
  789. DATA_START_SYMBOLS='PROVIDE (___data = .);'
  790. diff -Nur binutils-2.27.orig/ld/emulparams/shlelf_linux.sh binutils-2.27/ld/emulparams/shlelf_linux.sh
  791. --- binutils-2.27.orig/ld/emulparams/shlelf_linux.sh 2013-11-04 16:33:39.000000000 +0100
  792. +++ binutils-2.27/ld/emulparams/shlelf_linux.sh 2016-12-10 15:34:06.138680918 +0100
  793. @@ -12,6 +12,9 @@
  794. TEMPLATE_NAME=elf32
  795. GENERATE_SHLIB_SCRIPT=yes
  796. GENERATE_PIE_SCRIPT=yes
  797. +# PR 17739. Delay checking relocs until after all files have
  798. +# been opened and linker garbage collection has taken place.
  799. +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
  800. DATA_START_SYMBOLS='PROVIDE (__data_start = .);';
  801. diff -Nur binutils-2.27.orig/ld/emulparams/shlelf_nto.sh binutils-2.27/ld/emulparams/shlelf_nto.sh
  802. --- binutils-2.27.orig/ld/emulparams/shlelf_nto.sh 2013-11-04 16:33:39.000000000 +0100
  803. +++ binutils-2.27/ld/emulparams/shlelf_nto.sh 2016-12-10 15:34:06.138680918 +0100
  804. @@ -9,3 +9,6 @@
  805. GENERATE_SHLIB_SCRIPT=yes
  806. TEXT_START_SYMBOLS='_btext = .;'
  807. ENTRY=_start
  808. +# PR 17739. Delay checking relocs until after all files have
  809. +# been opened and linker garbage collection has taken place.
  810. +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
  811. diff -Nur binutils-2.27.orig/opcodes/sh-dis.c binutils-2.27/opcodes/sh-dis.c
  812. --- binutils-2.27.orig/opcodes/sh-dis.c 2016-08-03 09:36:55.000000000 +0200
  813. +++ binutils-2.27/opcodes/sh-dis.c 2016-12-10 15:34:02.038871379 +0100
  814. @@ -868,6 +868,9 @@
  815. case XMTRX_M4:
  816. fprintf_fn (stream, "xmtrx");
  817. break;
  818. + case A_IND_0:
  819. + fprintf_fn (stream, "@r0");
  820. + break;
  821. default:
  822. abort ();
  823. }
  824. diff -Nur binutils-2.27.orig/opcodes/sh-opc.h binutils-2.27/opcodes/sh-opc.h
  825. --- binutils-2.27.orig/opcodes/sh-opc.h 2016-08-03 09:36:55.000000000 +0200
  826. +++ binutils-2.27/opcodes/sh-opc.h 2016-12-10 15:34:02.046871007 +0100
  827. @@ -191,7 +191,8 @@
  828. FPUL_N,
  829. FPUL_M,
  830. FPSCR_N,
  831. - FPSCR_M
  832. + FPSCR_M,
  833. + A_IND_0
  834. }
  835. sh_arg_type;
  836. @@ -218,9 +219,11 @@
  837. #define arch_sh4_base (1 << 5)
  838. #define arch_sh4a_base (1 << 6)
  839. #define arch_sh2a_base (1 << 7)
  840. -#define arch_sh_base_mask MASK (0, 7)
  841. +#define arch_shj2_base (1 << 8)
  842. +#define arch_sh2a_sh3_shj2_base (1 << 9)
  843. +#define arch_sh_base_mask MASK (0, 9)
  844. -/* Bits 8 ... 24 are currently free. */
  845. +/* Bits 10 ... 24 are currently free. */
  846. /* This is an annotation on instruction types, but we
  847. abuse the arch field in instructions to denote it. */
  848. @@ -258,6 +261,8 @@
  849. #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
  850. #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
  851. #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
  852. +#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
  853. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
  854. #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
  855. #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
  856. @@ -323,7 +328,8 @@
  857. #define arch_sh2_up (arch_sh2 \
  858. | arch_sh2e_up \
  859. | arch_sh2a_nofpu_or_sh3_nommu_up \
  860. - | arch_sh_dsp_up)
  861. + | arch_sh_dsp_up \
  862. + | arch_shj2_up)
  863. #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
  864. | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
  865. | arch_sh2a_or_sh3e_up \
  866. @@ -349,6 +355,12 @@
  867. #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
  868. | arch_sh4a_up \
  869. | arch_sh4al_dsp_up)
  870. +#define arch_shj2_up ( arch_shj2)
  871. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
  872. + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
  873. + | arch_sh2a_or_sh3e_up \
  874. + | arch_sh3_nommu_up \
  875. + | arch_shj2_up)
  876. /* Right branches. */
  877. #define arch_sh2e_up (arch_sh2e \
  878. @@ -717,9 +729,9 @@
  879. /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
  880. -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
  881. +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
  882. -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
  883. +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
  884. /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
  885. @@ -1197,7 +1209,7 @@
  886. {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
  887. /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
  888. {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
  889. -
  890. + /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
  891. { 0, {0}, {0}, 0 }
  892. };