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crisv32_ethernet_driver.patch 118 KB

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  1. diff -Nur linux-4.7.3.orig/arch/cris/arch-v32/drivers/Kconfig linux-4.7.3/arch/cris/arch-v32/drivers/Kconfig
  2. --- linux-4.7.3.orig/arch/cris/arch-v32/drivers/Kconfig 2016-09-07 08:35:12.000000000 +0200
  3. +++ linux-4.7.3/arch/cris/arch-v32/drivers/Kconfig 2016-09-13 01:47:09.507717605 +0200
  4. @@ -8,9 +8,18 @@
  5. This option enables the ETRAX FS built-in 10/100Mbit Ethernet
  6. controller.
  7. +config ETRAX_HAVE_PHY
  8. + bool "PHY present"
  9. + default y
  10. + help
  11. + Search and use the first PHY available on the MDIO bus. Fail
  12. + if none is found. Say Y here if you are not in a switched
  13. + environment (single port device).
  14. +
  15. config ETRAX_NO_PHY
  16. bool "PHY not present"
  17. depends on ETRAX_ETHERNET
  18. + default n
  19. help
  20. This option disables all MDIO communication with an ethernet
  21. transceiver connected to the MII interface. This option shall
  22. @@ -18,6 +27,70 @@
  23. switch. This option should normally be disabled. If enabled,
  24. speed and duplex will be locked to 100 Mbit and full duplex.
  25. +config ETRAX_PHY_FALLBACK
  26. + bool "Fixed PHY fallback"
  27. + depends on ETRAX_ETHERNET
  28. + default n
  29. + help
  30. + If no PHY is found on the MDIO bus, fall back on a fixed
  31. + 100/Full fixed PHY. Say Y here if you need dynamic PHY
  32. + presence detection (switch connection where some but not
  33. + all ports have integrated PHYs), otherwise say N.
  34. +
  35. +config ETRAX_ETHERNET_IFACE0
  36. + depends on ETRAX_ETHERNET
  37. + bool "Enable network interface 0"
  38. +
  39. +config ETRAX_ETHERNET_IFACE1
  40. + depends on (ETRAX_ETHERNET && ETRAXFS)
  41. + bool "Enable network interface 1 (uses DMA6 and DMA7)"
  42. +
  43. +choice
  44. + prompt "Eth0 led group"
  45. + depends on ETRAX_ETHERNET_IFACE0
  46. + default ETRAX_ETH0_USE_LEDGRP0
  47. +
  48. +config ETRAX_ETH0_USE_LEDGRP0
  49. + bool "Use LED grp 0"
  50. + depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
  51. + help
  52. + Use LED grp 0 for eth0
  53. +
  54. +config ETRAX_ETH0_USE_LEDGRP1
  55. + bool "Use LED grp 1"
  56. + depends on ETRAX_NBR_LED_GRP_TWO
  57. + help
  58. + Use LED grp 1 for eth0
  59. +
  60. +config ETRAX_ETH0_USE_LEDGRPNULL
  61. + bool "Use no LEDs for eth0"
  62. + help
  63. + Use no LEDs for eth0
  64. +endchoice
  65. +
  66. +choice
  67. + prompt "Eth1 led group"
  68. + depends on ETRAX_ETHERNET_IFACE1
  69. + default ETRAX_ETH1_USE_LEDGRP1
  70. +
  71. +config ETRAX_ETH1_USE_LEDGRP0
  72. + bool "Use LED grp 0"
  73. + depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
  74. + help
  75. + Use LED grp 0 for eth1
  76. +
  77. +config ETRAX_ETH1_USE_LEDGRP1
  78. + bool "Use LED grp 1"
  79. + depends on ETRAX_NBR_LED_GRP_TWO
  80. + help
  81. + Use LED grp 1 for eth1
  82. +
  83. +config ETRAX_ETH1_USE_LEDGRPNULL
  84. + bool "Use no LEDs for eth1"
  85. + help
  86. + Use no LEDs for eth1
  87. +endchoice
  88. +
  89. config ETRAXFS_SERIAL
  90. bool "Serial-port support"
  91. depends on ETRAX_ARCH_V32
  92. diff -Nur linux-4.7.3.orig/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h linux-4.7.3/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h
  93. --- linux-4.7.3.orig/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h 2016-09-07 08:35:12.000000000 +0200
  94. +++ linux-4.7.3/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h 2016-09-13 01:47:09.527718381 +0200
  95. @@ -2,69 +2,64 @@
  96. #define __eth_defs_h
  97. /*
  98. - * This file is autogenerated from
  99. - * file: eth.r
  100. - * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
  101. - * last modfied: Mon Jan 9 06:06:41 2006
  102. - *
  103. - * by /n/asic/design/tools/rdesc/rdes2c eth.r
  104. - * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
  105. - * Any changes here will be lost.
  106. - *
  107. - * -*- buffer-read-only: t -*-
  108. + * Note: Previously this was autogenerated code from the hardware
  109. + * implementation. However, to enable the same file to be used
  110. + * for both ARTPEC-3 and ETRAX FS this file is now hand-edited.
  111. + * Be careful.
  112. */
  113. +
  114. /* Main access macros */
  115. #ifndef REG_RD
  116. #define REG_RD( scope, inst, reg ) \
  117. - REG_READ( reg_##scope##_##reg, \
  118. - (inst) + REG_RD_ADDR_##scope##_##reg )
  119. + REG_READ( reg_##scope##_##reg, \
  120. + (inst) + REG_RD_ADDR_##scope##_##reg )
  121. #endif
  122. #ifndef REG_WR
  123. #define REG_WR( scope, inst, reg, val ) \
  124. - REG_WRITE( reg_##scope##_##reg, \
  125. - (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  126. + REG_WRITE( reg_##scope##_##reg, \
  127. + (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  128. #endif
  129. #ifndef REG_RD_VECT
  130. #define REG_RD_VECT( scope, inst, reg, index ) \
  131. - REG_READ( reg_##scope##_##reg, \
  132. - (inst) + REG_RD_ADDR_##scope##_##reg + \
  133. - (index) * STRIDE_##scope##_##reg )
  134. + REG_READ( reg_##scope##_##reg, \
  135. + (inst) + REG_RD_ADDR_##scope##_##reg + \
  136. + (index) * STRIDE_##scope##_##reg )
  137. #endif
  138. #ifndef REG_WR_VECT
  139. #define REG_WR_VECT( scope, inst, reg, index, val ) \
  140. - REG_WRITE( reg_##scope##_##reg, \
  141. - (inst) + REG_WR_ADDR_##scope##_##reg + \
  142. - (index) * STRIDE_##scope##_##reg, (val) )
  143. + REG_WRITE( reg_##scope##_##reg, \
  144. + (inst) + REG_WR_ADDR_##scope##_##reg + \
  145. + (index) * STRIDE_##scope##_##reg, (val) )
  146. #endif
  147. #ifndef REG_RD_INT
  148. #define REG_RD_INT( scope, inst, reg ) \
  149. - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  150. + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  151. #endif
  152. #ifndef REG_WR_INT
  153. #define REG_WR_INT( scope, inst, reg, val ) \
  154. - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  155. + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  156. #endif
  157. #ifndef REG_RD_INT_VECT
  158. #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  159. - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  160. - (index) * STRIDE_##scope##_##reg )
  161. + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  162. + (index) * STRIDE_##scope##_##reg )
  163. #endif
  164. #ifndef REG_WR_INT_VECT
  165. #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  166. - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  167. - (index) * STRIDE_##scope##_##reg, (val) )
  168. + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  169. + (index) * STRIDE_##scope##_##reg, (val) )
  170. #endif
  171. #ifndef REG_TYPE_CONV
  172. #define REG_TYPE_CONV( type, orgtype, val ) \
  173. - ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  174. + ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  175. #endif
  176. #ifndef reg_page_size
  177. @@ -73,306 +68,332 @@
  178. #ifndef REG_ADDR
  179. #define REG_ADDR( scope, inst, reg ) \
  180. - ( (inst) + REG_RD_ADDR_##scope##_##reg )
  181. + ( (inst) + REG_RD_ADDR_##scope##_##reg )
  182. #endif
  183. #ifndef REG_ADDR_VECT
  184. #define REG_ADDR_VECT( scope, inst, reg, index ) \
  185. - ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  186. - (index) * STRIDE_##scope##_##reg )
  187. + ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  188. + (index) * STRIDE_##scope##_##reg )
  189. #endif
  190. /* C-code for register scope eth */
  191. /* Register rw_ma0_lo, scope eth, type rw */
  192. typedef struct {
  193. - unsigned int addr : 32;
  194. + unsigned int addr : 32;
  195. } reg_eth_rw_ma0_lo;
  196. #define REG_RD_ADDR_eth_rw_ma0_lo 0
  197. #define REG_WR_ADDR_eth_rw_ma0_lo 0
  198. /* Register rw_ma0_hi, scope eth, type rw */
  199. typedef struct {
  200. - unsigned int addr : 16;
  201. - unsigned int dummy1 : 16;
  202. + unsigned int addr : 16;
  203. + unsigned int dummy1 : 16;
  204. } reg_eth_rw_ma0_hi;
  205. #define REG_RD_ADDR_eth_rw_ma0_hi 4
  206. #define REG_WR_ADDR_eth_rw_ma0_hi 4
  207. /* Register rw_ma1_lo, scope eth, type rw */
  208. typedef struct {
  209. - unsigned int addr : 32;
  210. + unsigned int addr : 32;
  211. } reg_eth_rw_ma1_lo;
  212. #define REG_RD_ADDR_eth_rw_ma1_lo 8
  213. #define REG_WR_ADDR_eth_rw_ma1_lo 8
  214. /* Register rw_ma1_hi, scope eth, type rw */
  215. typedef struct {
  216. - unsigned int addr : 16;
  217. - unsigned int dummy1 : 16;
  218. + unsigned int addr : 16;
  219. + unsigned int dummy1 : 16;
  220. } reg_eth_rw_ma1_hi;
  221. #define REG_RD_ADDR_eth_rw_ma1_hi 12
  222. #define REG_WR_ADDR_eth_rw_ma1_hi 12
  223. /* Register rw_ga_lo, scope eth, type rw */
  224. typedef struct {
  225. - unsigned int tbl : 32;
  226. + unsigned int table : 32;
  227. } reg_eth_rw_ga_lo;
  228. #define REG_RD_ADDR_eth_rw_ga_lo 16
  229. #define REG_WR_ADDR_eth_rw_ga_lo 16
  230. /* Register rw_ga_hi, scope eth, type rw */
  231. typedef struct {
  232. - unsigned int tbl : 32;
  233. + unsigned int table : 32;
  234. } reg_eth_rw_ga_hi;
  235. #define REG_RD_ADDR_eth_rw_ga_hi 20
  236. #define REG_WR_ADDR_eth_rw_ga_hi 20
  237. /* Register rw_gen_ctrl, scope eth, type rw */
  238. typedef struct {
  239. - unsigned int en : 1;
  240. - unsigned int phy : 2;
  241. - unsigned int protocol : 1;
  242. - unsigned int loopback : 1;
  243. - unsigned int flow_ctrl : 1;
  244. - unsigned int gtxclk_out : 1;
  245. - unsigned int phyrst_n : 1;
  246. - unsigned int dummy1 : 24;
  247. + unsigned int en : 1;
  248. + unsigned int phy : 2;
  249. + unsigned int protocol : 1;
  250. + unsigned int loopback : 1;
  251. + unsigned int flow_ctrl : 1;
  252. + unsigned int gtxclk_out : 1;
  253. + unsigned int phyrst_n : 1;
  254. + unsigned int dummy1 : 24;
  255. } reg_eth_rw_gen_ctrl;
  256. #define REG_RD_ADDR_eth_rw_gen_ctrl 24
  257. #define REG_WR_ADDR_eth_rw_gen_ctrl 24
  258. /* Register rw_rec_ctrl, scope eth, type rw */
  259. typedef struct {
  260. - unsigned int ma0 : 1;
  261. - unsigned int ma1 : 1;
  262. - unsigned int individual : 1;
  263. - unsigned int broadcast : 1;
  264. - unsigned int undersize : 1;
  265. - unsigned int oversize : 1;
  266. - unsigned int bad_crc : 1;
  267. - unsigned int duplex : 1;
  268. - unsigned int max_size : 16;
  269. - unsigned int dummy1 : 8;
  270. + unsigned int ma0 : 1;
  271. + unsigned int ma1 : 1;
  272. + unsigned int individual : 1;
  273. + unsigned int broadcast : 1;
  274. + unsigned int undersize : 1;
  275. + unsigned int oversize : 1;
  276. + unsigned int bad_crc : 1;
  277. + unsigned int duplex : 1;
  278. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  279. + unsigned int max_size : 16;
  280. + unsigned int dummy1 : 8;
  281. +#else
  282. + unsigned int max_size : 1;
  283. + unsigned int dummy1 : 23;
  284. +#endif
  285. } reg_eth_rw_rec_ctrl;
  286. #define REG_RD_ADDR_eth_rw_rec_ctrl 28
  287. #define REG_WR_ADDR_eth_rw_rec_ctrl 28
  288. /* Register rw_tr_ctrl, scope eth, type rw */
  289. typedef struct {
  290. - unsigned int crc : 1;
  291. - unsigned int pad : 1;
  292. - unsigned int retry : 1;
  293. - unsigned int ignore_col : 1;
  294. - unsigned int cancel : 1;
  295. - unsigned int hsh_delay : 1;
  296. - unsigned int ignore_crs : 1;
  297. - unsigned int carrier_ext : 1;
  298. - unsigned int dummy1 : 24;
  299. + unsigned int crc : 1;
  300. + unsigned int pad : 1;
  301. + unsigned int retry : 1;
  302. + unsigned int ignore_col : 1;
  303. + unsigned int cancel : 1;
  304. + unsigned int hsh_delay : 1;
  305. + unsigned int ignore_crs : 1;
  306. + unsigned int carrier_ext : 1;
  307. + unsigned int dummy1 : 24;
  308. } reg_eth_rw_tr_ctrl;
  309. #define REG_RD_ADDR_eth_rw_tr_ctrl 32
  310. #define REG_WR_ADDR_eth_rw_tr_ctrl 32
  311. /* Register rw_clr_err, scope eth, type rw */
  312. typedef struct {
  313. - unsigned int clr : 1;
  314. - unsigned int dummy1 : 31;
  315. + unsigned int clr : 1;
  316. + unsigned int dummy1 : 31;
  317. } reg_eth_rw_clr_err;
  318. #define REG_RD_ADDR_eth_rw_clr_err 36
  319. #define REG_WR_ADDR_eth_rw_clr_err 36
  320. /* Register rw_mgm_ctrl, scope eth, type rw */
  321. typedef struct {
  322. - unsigned int mdio : 1;
  323. - unsigned int mdoe : 1;
  324. - unsigned int mdc : 1;
  325. - unsigned int dummy1 : 29;
  326. + unsigned int mdio : 1;
  327. + unsigned int mdoe : 1;
  328. + unsigned int mdc : 1;
  329. + unsigned int phyclk : 1;
  330. + unsigned int txdata : 4;
  331. + unsigned int txen : 1;
  332. + unsigned int dummy1 : 23;
  333. } reg_eth_rw_mgm_ctrl;
  334. #define REG_RD_ADDR_eth_rw_mgm_ctrl 40
  335. #define REG_WR_ADDR_eth_rw_mgm_ctrl 40
  336. /* Register r_stat, scope eth, type r */
  337. typedef struct {
  338. - unsigned int mdio : 1;
  339. - unsigned int exc_col : 1;
  340. - unsigned int urun : 1;
  341. - unsigned int clk_125 : 1;
  342. - unsigned int dummy1 : 28;
  343. + unsigned int mdio : 1;
  344. + unsigned int exc_col : 1;
  345. + unsigned int urun : 1;
  346. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  347. + unsigned int clk_125 : 1;
  348. +#else
  349. + unsigned int phyclk : 1;
  350. +#endif
  351. + unsigned int txdata : 4;
  352. + unsigned int txen : 1;
  353. + unsigned int col : 1;
  354. + unsigned int crs : 1;
  355. + unsigned int txclk : 1;
  356. + unsigned int rxdata : 4;
  357. + unsigned int rxer : 1;
  358. + unsigned int rxdv : 1;
  359. + unsigned int rxclk : 1;
  360. + unsigned int dummy1 : 13;
  361. } reg_eth_r_stat;
  362. #define REG_RD_ADDR_eth_r_stat 44
  363. /* Register rs_rec_cnt, scope eth, type rs */
  364. typedef struct {
  365. - unsigned int crc_err : 8;
  366. - unsigned int align_err : 8;
  367. - unsigned int oversize : 8;
  368. - unsigned int congestion : 8;
  369. + unsigned int crc_err : 8;
  370. + unsigned int align_err : 8;
  371. + unsigned int oversize : 8;
  372. + unsigned int congestion : 8;
  373. } reg_eth_rs_rec_cnt;
  374. #define REG_RD_ADDR_eth_rs_rec_cnt 48
  375. /* Register r_rec_cnt, scope eth, type r */
  376. typedef struct {
  377. - unsigned int crc_err : 8;
  378. - unsigned int align_err : 8;
  379. - unsigned int oversize : 8;
  380. - unsigned int congestion : 8;
  381. + unsigned int crc_err : 8;
  382. + unsigned int align_err : 8;
  383. + unsigned int oversize : 8;
  384. + unsigned int congestion : 8;
  385. } reg_eth_r_rec_cnt;
  386. #define REG_RD_ADDR_eth_r_rec_cnt 52
  387. /* Register rs_tr_cnt, scope eth, type rs */
  388. typedef struct {
  389. - unsigned int single_col : 8;
  390. - unsigned int mult_col : 8;
  391. - unsigned int late_col : 8;
  392. - unsigned int deferred : 8;
  393. + unsigned int single_col : 8;
  394. + unsigned int mult_col : 8;
  395. + unsigned int late_col : 8;
  396. + unsigned int deferred : 8;
  397. } reg_eth_rs_tr_cnt;
  398. #define REG_RD_ADDR_eth_rs_tr_cnt 56
  399. /* Register r_tr_cnt, scope eth, type r */
  400. typedef struct {
  401. - unsigned int single_col : 8;
  402. - unsigned int mult_col : 8;
  403. - unsigned int late_col : 8;
  404. - unsigned int deferred : 8;
  405. + unsigned int single_col : 8;
  406. + unsigned int mult_col : 8;
  407. + unsigned int late_col : 8;
  408. + unsigned int deferred : 8;
  409. } reg_eth_r_tr_cnt;
  410. #define REG_RD_ADDR_eth_r_tr_cnt 60
  411. /* Register rs_phy_cnt, scope eth, type rs */
  412. typedef struct {
  413. - unsigned int carrier_loss : 8;
  414. - unsigned int sqe_err : 8;
  415. - unsigned int dummy1 : 16;
  416. + unsigned int carrier_loss : 8;
  417. + unsigned int sqe_err : 8;
  418. + unsigned int dummy1 : 16;
  419. } reg_eth_rs_phy_cnt;
  420. #define REG_RD_ADDR_eth_rs_phy_cnt 64
  421. /* Register r_phy_cnt, scope eth, type r */
  422. typedef struct {
  423. - unsigned int carrier_loss : 8;
  424. - unsigned int sqe_err : 8;
  425. - unsigned int dummy1 : 16;
  426. + unsigned int carrier_loss : 8;
  427. + unsigned int sqe_err : 8;
  428. + unsigned int dummy1 : 16;
  429. } reg_eth_r_phy_cnt;
  430. #define REG_RD_ADDR_eth_r_phy_cnt 68
  431. /* Register rw_test_ctrl, scope eth, type rw */
  432. typedef struct {
  433. - unsigned int snmp_inc : 1;
  434. - unsigned int snmp : 1;
  435. - unsigned int backoff : 1;
  436. - unsigned int dummy1 : 29;
  437. + unsigned int snmp_inc : 1;
  438. + unsigned int snmp : 1;
  439. + unsigned int backoff : 1;
  440. + unsigned int dummy1 : 29;
  441. } reg_eth_rw_test_ctrl;
  442. #define REG_RD_ADDR_eth_rw_test_ctrl 72
  443. #define REG_WR_ADDR_eth_rw_test_ctrl 72
  444. /* Register rw_intr_mask, scope eth, type rw */
  445. typedef struct {
  446. - unsigned int crc : 1;
  447. - unsigned int align : 1;
  448. - unsigned int oversize : 1;
  449. - unsigned int congestion : 1;
  450. - unsigned int single_col : 1;
  451. - unsigned int mult_col : 1;
  452. - unsigned int late_col : 1;
  453. - unsigned int deferred : 1;
  454. - unsigned int carrier_loss : 1;
  455. - unsigned int sqe_test_err : 1;
  456. - unsigned int orun : 1;
  457. - unsigned int urun : 1;
  458. - unsigned int exc_col : 1;
  459. - unsigned int mdio : 1;
  460. - unsigned int dummy1 : 18;
  461. + unsigned int crc : 1;
  462. + unsigned int align : 1;
  463. + unsigned int oversize : 1;
  464. + unsigned int congestion : 1;
  465. + unsigned int single_col : 1;
  466. + unsigned int mult_col : 1;
  467. + unsigned int late_col : 1;
  468. + unsigned int deferred : 1;
  469. + unsigned int carrier_loss : 1;
  470. + unsigned int sqe_test_err : 1;
  471. + unsigned int orun : 1;
  472. + unsigned int urun : 1;
  473. + unsigned int exc_col : 1;
  474. + unsigned int mdio : 1;
  475. + unsigned int dummy1 : 18;
  476. } reg_eth_rw_intr_mask;
  477. #define REG_RD_ADDR_eth_rw_intr_mask 76
  478. #define REG_WR_ADDR_eth_rw_intr_mask 76
  479. /* Register rw_ack_intr, scope eth, type rw */
  480. typedef struct {
  481. - unsigned int crc : 1;
  482. - unsigned int align : 1;
  483. - unsigned int oversize : 1;
  484. - unsigned int congestion : 1;
  485. - unsigned int single_col : 1;
  486. - unsigned int mult_col : 1;
  487. - unsigned int late_col : 1;
  488. - unsigned int deferred : 1;
  489. - unsigned int carrier_loss : 1;
  490. - unsigned int sqe_test_err : 1;
  491. - unsigned int orun : 1;
  492. - unsigned int urun : 1;
  493. - unsigned int exc_col : 1;
  494. - unsigned int mdio : 1;
  495. - unsigned int dummy1 : 18;
  496. + unsigned int crc : 1;
  497. + unsigned int align : 1;
  498. + unsigned int oversize : 1;
  499. + unsigned int congestion : 1;
  500. + unsigned int single_col : 1;
  501. + unsigned int mult_col : 1;
  502. + unsigned int late_col : 1;
  503. + unsigned int deferred : 1;
  504. + unsigned int carrier_loss : 1;
  505. + unsigned int sqe_test_err : 1;
  506. + unsigned int orun : 1;
  507. + unsigned int urun : 1;
  508. + unsigned int exc_col : 1;
  509. + unsigned int mdio : 1;
  510. + unsigned int dummy1 : 18;
  511. } reg_eth_rw_ack_intr;
  512. #define REG_RD_ADDR_eth_rw_ack_intr 80
  513. #define REG_WR_ADDR_eth_rw_ack_intr 80
  514. /* Register r_intr, scope eth, type r */
  515. typedef struct {
  516. - unsigned int crc : 1;
  517. - unsigned int align : 1;
  518. - unsigned int oversize : 1;
  519. - unsigned int congestion : 1;
  520. - unsigned int single_col : 1;
  521. - unsigned int mult_col : 1;
  522. - unsigned int late_col : 1;
  523. - unsigned int deferred : 1;
  524. - unsigned int carrier_loss : 1;
  525. - unsigned int sqe_test_err : 1;
  526. - unsigned int orun : 1;
  527. - unsigned int urun : 1;
  528. - unsigned int exc_col : 1;
  529. - unsigned int mdio : 1;
  530. - unsigned int dummy1 : 18;
  531. + unsigned int crc : 1;
  532. + unsigned int align : 1;
  533. + unsigned int oversize : 1;
  534. + unsigned int congestion : 1;
  535. + unsigned int single_col : 1;
  536. + unsigned int mult_col : 1;
  537. + unsigned int late_col : 1;
  538. + unsigned int deferred : 1;
  539. + unsigned int carrier_loss : 1;
  540. + unsigned int sqe_test_err : 1;
  541. + unsigned int orun : 1;
  542. + unsigned int urun : 1;
  543. + unsigned int exc_col : 1;
  544. + unsigned int mdio : 1;
  545. + unsigned int dummy1 : 18;
  546. } reg_eth_r_intr;
  547. #define REG_RD_ADDR_eth_r_intr 84
  548. /* Register r_masked_intr, scope eth, type r */
  549. typedef struct {
  550. - unsigned int crc : 1;
  551. - unsigned int align : 1;
  552. - unsigned int oversize : 1;
  553. - unsigned int congestion : 1;
  554. - unsigned int single_col : 1;
  555. - unsigned int mult_col : 1;
  556. - unsigned int late_col : 1;
  557. - unsigned int deferred : 1;
  558. - unsigned int carrier_loss : 1;
  559. - unsigned int sqe_test_err : 1;
  560. - unsigned int orun : 1;
  561. - unsigned int urun : 1;
  562. - unsigned int exc_col : 1;
  563. - unsigned int mdio : 1;
  564. - unsigned int dummy1 : 18;
  565. + unsigned int crc : 1;
  566. + unsigned int align : 1;
  567. + unsigned int oversize : 1;
  568. + unsigned int congestion : 1;
  569. + unsigned int single_col : 1;
  570. + unsigned int mult_col : 1;
  571. + unsigned int late_col : 1;
  572. + unsigned int deferred : 1;
  573. + unsigned int carrier_loss : 1;
  574. + unsigned int sqe_test_err : 1;
  575. + unsigned int orun : 1;
  576. + unsigned int urun : 1;
  577. + unsigned int exc_col : 1;
  578. + unsigned int mdio : 1;
  579. + unsigned int dummy1 : 18;
  580. } reg_eth_r_masked_intr;
  581. #define REG_RD_ADDR_eth_r_masked_intr 88
  582. -
  583. /* Constants */
  584. enum {
  585. - regk_eth_discard = 0x00000000,
  586. - regk_eth_ether = 0x00000000,
  587. - regk_eth_full = 0x00000001,
  588. - regk_eth_gmii = 0x00000003,
  589. - regk_eth_gtxclk = 0x00000001,
  590. - regk_eth_half = 0x00000000,
  591. - regk_eth_hsh = 0x00000001,
  592. - regk_eth_mii = 0x00000001,
  593. - regk_eth_mii_arec = 0x00000002,
  594. - regk_eth_mii_clk = 0x00000000,
  595. - regk_eth_no = 0x00000000,
  596. - regk_eth_phyrst = 0x00000000,
  597. - regk_eth_rec = 0x00000001,
  598. - regk_eth_rw_ga_hi_default = 0x00000000,
  599. - regk_eth_rw_ga_lo_default = 0x00000000,
  600. - regk_eth_rw_gen_ctrl_default = 0x00000000,
  601. - regk_eth_rw_intr_mask_default = 0x00000000,
  602. - regk_eth_rw_ma0_hi_default = 0x00000000,
  603. - regk_eth_rw_ma0_lo_default = 0x00000000,
  604. - regk_eth_rw_ma1_hi_default = 0x00000000,
  605. - regk_eth_rw_ma1_lo_default = 0x00000000,
  606. - regk_eth_rw_mgm_ctrl_default = 0x00000000,
  607. - regk_eth_rw_test_ctrl_default = 0x00000000,
  608. - regk_eth_size1518 = 0x000005ee,
  609. - regk_eth_size1522 = 0x000005f2,
  610. - regk_eth_yes = 0x00000001
  611. + regk_eth_discard = 0x00000000,
  612. + regk_eth_ether = 0x00000000,
  613. + regk_eth_full = 0x00000001,
  614. + regk_eth_gmii = 0x00000003,
  615. + regk_eth_gtxclk = 0x00000001,
  616. + regk_eth_half = 0x00000000,
  617. + regk_eth_hsh = 0x00000001,
  618. + regk_eth_mii = 0x00000001,
  619. + regk_eth_mii_arec = 0x00000002,
  620. + regk_eth_mii_clk = 0x00000000,
  621. + regk_eth_no = 0x00000000,
  622. + regk_eth_phyrst = 0x00000000,
  623. + regk_eth_rec = 0x00000001,
  624. + regk_eth_rw_ga_hi_default = 0x00000000,
  625. + regk_eth_rw_ga_lo_default = 0x00000000,
  626. + regk_eth_rw_gen_ctrl_default = 0x00000000,
  627. + regk_eth_rw_intr_mask_default = 0x00000000,
  628. + regk_eth_rw_ma0_hi_default = 0x00000000,
  629. + regk_eth_rw_ma0_lo_default = 0x00000000,
  630. + regk_eth_rw_ma1_hi_default = 0x00000000,
  631. + regk_eth_rw_ma1_lo_default = 0x00000000,
  632. + regk_eth_rw_mgm_ctrl_default = 0x00000000,
  633. + regk_eth_rw_test_ctrl_default = 0x00000000,
  634. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  635. + regk_eth_size1518 = 0x000005ee,
  636. + regk_eth_size1522 = 0x000005f2,
  637. +#else
  638. + regk_eth_size1518 = 0x00000000,
  639. + regk_eth_size1522 = 0x00000001,
  640. +#endif
  641. + regk_eth_yes = 0x00000001
  642. };
  643. +
  644. #endif /* __eth_defs_h */
  645. diff -Nur linux-4.7.3.orig/drivers/net/cris/eth_v32.c linux-4.7.3/drivers/net/cris/eth_v32.c
  646. --- linux-4.7.3.orig/drivers/net/cris/eth_v32.c 1970-01-01 01:00:00.000000000 +0100
  647. +++ linux-4.7.3/drivers/net/cris/eth_v32.c 2016-09-13 01:48:05.953910422 +0200
  648. @@ -0,0 +1,3060 @@
  649. +/*
  650. + * Driver for the ETRAX FS/Artpec-3 network controller.
  651. + *
  652. + * Copyright (c) 2003-2008 Axis Communications AB.
  653. + *
  654. + * TODO:
  655. + * * Decrease the amount of code running with interrupts disabled.
  656. + * * Rework the error handling so that we do not need to touch the tx
  657. + * ring from the error interrupts. When done, we should be able to
  658. + * do tx completition from the NAPI loop without disabling interrupts.
  659. + * * Remove the gigabit code. It's probably never going to be used.
  660. + */
  661. +
  662. +#include <linux/module.h>
  663. +
  664. +#include <linux/kernel.h>
  665. +#include <linux/sched.h>
  666. +#include <linux/delay.h>
  667. +#include <linux/types.h>
  668. +#include <linux/fcntl.h>
  669. +#include <linux/interrupt.h>
  670. +#include <linux/spinlock.h>
  671. +#include <linux/errno.h>
  672. +#include <linux/init.h>
  673. +
  674. +#include <linux/netdevice.h>
  675. +#include <linux/etherdevice.h>
  676. +#include <linux/skbuff.h>
  677. +#include <linux/ethtool.h>
  678. +#include <linux/mii.h>
  679. +
  680. +#include <asm/io.h> /* CRIS_LED_* I/O functions */
  681. +#include <asm/irq.h>
  682. +#include <hwregs/reg_map.h>
  683. +#include <hwregs/reg_rdwr.h>
  684. +#include <hwregs/dma.h>
  685. +#include <hwregs/eth_defs.h>
  686. +#ifdef CONFIG_ETRAXFS
  687. +#include <hwregs/config_defs.h>
  688. +#else
  689. +#include <hwregs/clkgen_defs.h>
  690. +#endif
  691. +#include <hwregs/intr_vect_defs.h>
  692. +#include <hwregs/strmux_defs.h>
  693. +#include <asm/bitops.h>
  694. +#include <asm/ethernet.h>
  695. +#include <mach/dma.h>
  696. +#include <pinmux.h>
  697. +
  698. +#include "eth_v32.h"
  699. +
  700. +#ifndef CONFIG_ETRAXFS
  701. +#define ETH0_INTR_VECT ETH_INTR_VECT
  702. +#define ETH1_INTR_VECT ETH_INTR_VECT
  703. +#define regi_eth0 regi_eth
  704. +#define regi_eth1 regi_
  705. +#endif
  706. +
  707. +#define DEBUG(x)
  708. +#define GET_BIT(bit,val) (((val) >> (bit)) & 0x01)
  709. +
  710. +#if defined(CONFIG_ETRAX_HAVE_PHY) || defined(CONFIG_ETRAX_PHY_FALLBACK)
  711. +#define RESET_PHY 1
  712. +#else
  713. +#define RESET_PHY 0
  714. +#endif
  715. +
  716. +enum {
  717. + HAVE_PHY,
  718. + NO_PHY,
  719. + FALLBACK_PHY,
  720. +};
  721. +#if defined(CONFIG_ETRAX_PHY_FALLBACK)
  722. +#define PHY_MODE (FALLBACK_PHY)
  723. +#elif defined(CONFIG_ETRAX_NO_PHY)
  724. +#define PHY_MODE (NO_PHY)
  725. +#elif defined(CONFIG_ETRAX_HAVE_PHY)
  726. +#define PHY_MODE (HAVE_PHY)
  727. +#else
  728. +#error Unknown PHY behaviour
  729. +#endif
  730. +
  731. +static struct {
  732. + const char str[ETH_GSTRING_LEN];
  733. +} const ethtool_stats_keys[] = {
  734. + { "tx_dma_restarts" },
  735. + { "tx_mac_resets" },
  736. + { "rx_dma_restarts" },
  737. + { "rx_dma_timeouts" },
  738. + { " dropped_rx" }
  739. +};
  740. +
  741. +static void crisv32_eth_check_speed(unsigned long idev);
  742. +static void crisv32_eth_check_duplex(unsigned long idev);
  743. +static void update_rx_stats(struct crisv32_ethernet_local *np);
  744. +static void update_tx_stats(struct crisv32_ethernet_local *np);
  745. +static int crisv32_eth_poll(struct napi_struct *napi, int budget);
  746. +static void crisv32_eth_setup_controller(struct net_device *dev);
  747. +static int crisv32_eth_request_irqdma(struct net_device *dev);
  748. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  749. +static void
  750. +crisv32_eth_restart_rx_dma(struct net_device* dev,
  751. + struct crisv32_ethernet_local *np);
  752. +#endif
  753. +#if 0
  754. +static void crisv32_ethernet_bug(struct net_device *dev);
  755. +#endif
  756. +
  757. +/*
  758. + * The name of the card. Is used for messages and in the requests for
  759. + * io regions, irqs and dma channels.
  760. + */
  761. +#ifdef CONFIG_ETRAXFS
  762. +static const char cardname[] = "ETRAX FS built-in ethernet controller";
  763. +#else
  764. +static const char cardname[] = "ARTPEC-3 built-in ethernet controller";
  765. +#endif
  766. +
  767. +/* Some chipset needs special care. */
  768. +#ifndef CONFIG_ETRAX_NO_PHY
  769. +struct transceiver_ops transceivers[] = {
  770. + {0x1018, broadcom_check_speed, broadcom_check_duplex},
  771. + {0x50EF, broadcom_check_speed, broadcom_check_duplex},
  772. + /* TDK 2120 and TDK 2120C */
  773. + {0xC039, tdk_check_speed, tdk_check_duplex},
  774. + {0x039C, tdk_check_speed, tdk_check_duplex},
  775. + /* Intel LXT972A*/
  776. + {0x04de, intel_check_speed, intel_check_duplex},
  777. + /* National Semiconductor DP83865 */
  778. + {0x0017, national_check_speed, national_check_duplex},
  779. + /* Vitesse VCS8641 */
  780. + {0x01c1, vitesse_check_speed, vitesse_check_duplex},
  781. + /* Davicom DM9161 */
  782. + {0x606E, davicom_check_speed, davicom_check_duplex},
  783. + /* Generic, must be last. */
  784. + {0x0000, generic_check_speed, generic_check_duplex}
  785. +};
  786. +#endif
  787. +
  788. +static struct net_device *crisv32_dev[2];
  789. +static struct crisv32_eth_leds *crisv32_leds[3];
  790. +
  791. +/* Default MAC address for interface 0.
  792. + * The real one will be set later. */
  793. +static struct sockaddr default_mac_iface0 =
  794. + {0, {0x00, 0x40, 0x8C, 0xCD, 0x00, 0x00}};
  795. +
  796. +#ifdef CONFIG_CPU_FREQ
  797. +static int
  798. +crisv32_ethernet_freq_notifier(struct notifier_block *nb, unsigned long val,
  799. + void *data);
  800. +
  801. +static struct notifier_block crisv32_ethernet_freq_notifier_block = {
  802. + .notifier_call = crisv32_ethernet_freq_notifier
  803. +};
  804. +#endif
  805. +
  806. +static void receive_timeout(unsigned long arg);
  807. +static void receive_timeout_work(struct work_struct* work);
  808. +static void transmit_timeout(unsigned long arg);
  809. +
  810. +/*
  811. + * mask in and out tx/rx interrupts.
  812. + */
  813. +static inline void crisv32_disable_tx_ints(struct crisv32_ethernet_local *np)
  814. +{
  815. + reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_no };
  816. + REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx);
  817. +}
  818. +
  819. +static inline void crisv32_enable_tx_ints(struct crisv32_ethernet_local *np)
  820. +{
  821. + reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_yes };
  822. + REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx);
  823. +}
  824. +
  825. +static inline void crisv32_disable_rx_ints(struct crisv32_ethernet_local *np)
  826. +{
  827. + reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_no };
  828. + REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx);
  829. +}
  830. +
  831. +static inline void crisv32_enable_rx_ints(struct crisv32_ethernet_local *np)
  832. +{
  833. + reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_yes };
  834. + REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx);
  835. +}
  836. +
  837. +static inline void crisv32_disable_eth_ints(struct crisv32_ethernet_local *np)
  838. +{
  839. + int intr_mask_nw = 0x0;
  840. + REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw);
  841. +}
  842. +
  843. +static inline void crisv32_enable_eth_ints(struct crisv32_ethernet_local *np)
  844. +{
  845. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  846. + /* For Artpec-3 we use overrun to workaround voodoo TR 87 */
  847. + int intr_mask_nw = 0x1c00;
  848. +#else
  849. + int intr_mask_nw = 0x1800;
  850. +#endif
  851. + REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw);
  852. +}
  853. +
  854. +static inline int crisv32_eth_gigabit(struct crisv32_ethernet_local *np)
  855. +{
  856. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  857. + return np->gigabit_mode;
  858. +#else
  859. + return 0;
  860. +#endif
  861. +}
  862. +
  863. +static inline void crisv32_eth_set_gigabit(struct crisv32_ethernet_local *np,
  864. + int g)
  865. +{
  866. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  867. + np->gigabit_mode = g;
  868. +#endif
  869. +}
  870. +
  871. +/* start/stop receiver */
  872. +static inline void crisv32_start_receiver(struct crisv32_ethernet_local *np)
  873. +{
  874. + reg_eth_rw_rec_ctrl rec_ctrl;
  875. +
  876. + rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl);
  877. + rec_ctrl.ma0 = regk_eth_yes;
  878. + rec_ctrl.broadcast = regk_eth_rec;
  879. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  880. +}
  881. +
  882. +static inline void crisv32_stop_receiver(struct crisv32_ethernet_local *np)
  883. +{
  884. + reg_eth_rw_rec_ctrl rec_ctrl;
  885. +
  886. + rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl);
  887. + rec_ctrl.ma0 = regk_eth_no;
  888. + rec_ctrl.broadcast = regk_eth_discard;
  889. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  890. +}
  891. +
  892. +static inline void crisv32_eth_reset(struct crisv32_ethernet_local *np)
  893. +{
  894. + reg_eth_rw_gen_ctrl gen_ctrl = { 0 };
  895. +
  896. + gen_ctrl = REG_RD(eth, np->eth_inst, rw_gen_ctrl);
  897. + gen_ctrl.en = regk_eth_no;
  898. + REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
  899. + gen_ctrl.en = regk_eth_yes;
  900. + REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
  901. +}
  902. +
  903. +static void crisv32_eth_tx_cancel_frame(struct crisv32_ethernet_local *np)
  904. +{
  905. + reg_eth_rw_tr_ctrl tr_ctrl;
  906. +
  907. + /* Cancel any pending transmits. This should bring us to the
  908. + excessive collisions state but it doesn't always do it. */
  909. + tr_ctrl = REG_RD(eth, np->eth_inst, rw_tr_ctrl);
  910. + tr_ctrl.cancel = 1;
  911. + REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl);
  912. + tr_ctrl.cancel = 0;
  913. + REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl);
  914. +}
  915. +
  916. +/*
  917. + * Hack to disconnect/reconnect the dma from the ethernet block while we reset
  918. + * things. TODO: verify that we don't need to disconnect out channels and
  919. + * remove that code.
  920. + *
  921. + * ARTPEC-3 has only a single ethernet block so np->eth_inst is always eth0.
  922. + * The strmux values are named slightly different, redefine to avoid #ifdefs
  923. + * in the code blocks. For artpec3 only regk_strmux_eth0 and channel 0/1
  924. + * should be used.
  925. + */
  926. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  927. +#define regk_strmux_eth0 regk_strmux_eth
  928. +#define regk_strmux_eth1 regk_strmux_eth
  929. +#endif
  930. +static inline void
  931. +crisv32_disconnect_eth_tx_dma(struct crisv32_ethernet_local *np)
  932. +{
  933. + reg_strmux_rw_cfg strmux_cfg;
  934. +
  935. + strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
  936. + if (np->eth_inst == regi_eth0)
  937. + strmux_cfg.dma0 = regk_strmux_off;
  938. + else
  939. + strmux_cfg.dma6 = regk_strmux_off;
  940. + REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
  941. +}
  942. +
  943. +static inline void crisv32_connect_eth_tx_dma(struct crisv32_ethernet_local *np)
  944. +{
  945. + reg_strmux_rw_cfg strmux_cfg;
  946. +
  947. + strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
  948. + if (np->eth_inst == regi_eth0)
  949. + strmux_cfg.dma0 = regk_strmux_eth0;
  950. + else
  951. + strmux_cfg.dma6 = regk_strmux_eth1;
  952. + REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
  953. +}
  954. +
  955. +static inline void
  956. +crisv32_disconnect_eth_rx_dma(struct crisv32_ethernet_local *np)
  957. +{
  958. + reg_strmux_rw_cfg strmux_cfg;
  959. +
  960. + strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
  961. + if (np->eth_inst == regi_eth0)
  962. + strmux_cfg.dma1 = regk_strmux_off;
  963. + else
  964. + strmux_cfg.dma7 = regk_strmux_off;
  965. + REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
  966. +}
  967. +
  968. +static inline void crisv32_connect_eth_rx_dma(struct crisv32_ethernet_local *np)
  969. +{
  970. + reg_strmux_rw_cfg strmux_cfg;
  971. +
  972. + strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
  973. + if (np->eth_inst == regi_eth0)
  974. + strmux_cfg.dma1 = regk_strmux_eth0;
  975. + else
  976. + strmux_cfg.dma7 = regk_strmux_eth1;
  977. + REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
  978. +}
  979. +
  980. +static int dma_wait_busy(int inst, int timeout)
  981. +{
  982. + reg_dma_rw_stream_cmd dma_sc;
  983. +
  984. + do {
  985. + dma_sc = REG_RD(dma, inst, rw_stream_cmd);
  986. + } while (timeout-- > 0 && dma_sc.busy);
  987. + return dma_sc.busy;
  988. +}
  989. +
  990. +static int __init crisv32_eth_request_irqdma(struct net_device *dev)
  991. +{
  992. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  993. +
  994. + /* Allocate IRQs and DMAs. */
  995. + if (np->eth_inst == regi_eth0) {
  996. + if (request_irq(DMA0_INTR_VECT, crisv32tx_eth_interrupt,
  997. + 0, "Ethernet TX", dev)) {
  998. + return -EAGAIN;
  999. + }
  1000. +
  1001. + if (request_irq(DMA1_INTR_VECT, crisv32rx_eth_interrupt,
  1002. + 0, "Ethernet RX", dev))
  1003. + goto err0_1;
  1004. +
  1005. + if (crisv32_request_dma(0, cardname, DMA_VERBOSE_ON_ERROR,
  1006. + 12500000, dma_eth0))
  1007. + goto err0_2;
  1008. +
  1009. + if (crisv32_request_dma(1, cardname, DMA_VERBOSE_ON_ERROR,
  1010. + 12500000, dma_eth0))
  1011. + goto err0_3;
  1012. +
  1013. + if (request_irq(ETH0_INTR_VECT, crisv32nw_eth_interrupt, 0,
  1014. + cardname, dev)) {
  1015. + crisv32_free_dma(1);
  1016. +err0_3:
  1017. + crisv32_free_dma(0);
  1018. +err0_2:
  1019. + free_irq(DMA1_INTR_VECT, dev);
  1020. +err0_1:
  1021. + free_irq(DMA0_INTR_VECT, dev);
  1022. + return -EAGAIN;
  1023. + }
  1024. + } else {
  1025. + if (request_irq(DMA6_INTR_VECT, crisv32tx_eth_interrupt,
  1026. + 0, cardname, dev))
  1027. + return -EAGAIN;
  1028. +
  1029. + if (request_irq(DMA7_INTR_VECT, crisv32rx_eth_interrupt,
  1030. + 0, cardname, dev))
  1031. + goto err1_1;
  1032. +
  1033. + if (crisv32_request_dma(6, cardname, DMA_VERBOSE_ON_ERROR,
  1034. + 0, dma_eth1))
  1035. + goto err1_2;
  1036. +
  1037. + if (crisv32_request_dma(7, cardname, DMA_VERBOSE_ON_ERROR,
  1038. + 0, dma_eth1))
  1039. + goto err1_3;
  1040. +
  1041. + if (request_irq(ETH1_INTR_VECT, crisv32nw_eth_interrupt, 0,
  1042. + cardname, dev)) {
  1043. + crisv32_free_dma(7);
  1044. +err1_3:
  1045. + crisv32_free_dma(6);
  1046. +err1_2:
  1047. + free_irq(DMA7_INTR_VECT, dev);
  1048. +err1_1:
  1049. + free_irq(DMA6_INTR_VECT, dev);
  1050. + return -EAGAIN;
  1051. + }
  1052. + }
  1053. + return 0;
  1054. +}
  1055. +
  1056. +static int __init crisv32_eth_init_phy(struct net_device *dev)
  1057. +{
  1058. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1059. + struct timer_list timer_init = TIMER_INITIALIZER(NULL, 0, 0);
  1060. +
  1061. + if (RESET_PHY) {
  1062. +#ifdef CONFIG_ETRAXFS
  1063. + reg_config_rw_pad_ctrl pad_ctrl;
  1064. + pad_ctrl = REG_RD(config, regi_config, rw_pad_ctrl);
  1065. + pad_ctrl.phyrst_n = 0;
  1066. + REG_WR(config, regi_config, rw_pad_ctrl, pad_ctrl);
  1067. +
  1068. + udelay(500); /* RESET_LEN */
  1069. +
  1070. + pad_ctrl.phyrst_n = 1;
  1071. + REG_WR(config, regi_config, rw_pad_ctrl, pad_ctrl);
  1072. +#else
  1073. + reg_eth_rw_gen_ctrl gen_ctrl = REG_RD(eth, np->eth_inst, rw_gen_ctrl);
  1074. + gen_ctrl.phyrst_n = 0;
  1075. + REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
  1076. +
  1077. + udelay(500); /* RESET_LEN */
  1078. +
  1079. + gen_ctrl.phyrst_n = 1;
  1080. + REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
  1081. +#endif
  1082. +
  1083. + udelay(200); /* RESET_WAIT */
  1084. + }
  1085. +
  1086. + switch (PHY_MODE) {
  1087. + case FALLBACK_PHY:
  1088. + /* Fall back on using fixed iff there is no PHY on */
  1089. + /* the MDIO bus */
  1090. + np->fixed_phy = crisv32_eth_probe_transceiver(dev) != 0;
  1091. + if (np->fixed_phy)
  1092. + printk(KERN_WARNING
  1093. + "eth: No transciever found, falling back "
  1094. + "to fixed phy mode\n");
  1095. + break;
  1096. +
  1097. + case NO_PHY:
  1098. + /* Don't even bother looking for a PHY, always rely */
  1099. + /* on fixed PHY */
  1100. + np->fixed_phy = 1;
  1101. + break;
  1102. +
  1103. + default: /* HAVE_PHY */
  1104. + /* Look for a PHY and abort if there is none, */
  1105. + /* otherwise just carry on */
  1106. + if (crisv32_eth_probe_transceiver(dev)) {
  1107. + printk(KERN_WARNING
  1108. + "eth: No transceiver found, "
  1109. + "removing interface\n");
  1110. + return -ENODEV;
  1111. + }
  1112. + np->fixed_phy = 0;
  1113. + }
  1114. +
  1115. + if (np->fixed_phy) {
  1116. + reg_eth_rw_rec_ctrl rec_ctrl;
  1117. +
  1118. + /* speed */
  1119. + np->current_speed = 100;
  1120. + np->current_speed_selection = 100; /* Auto. */
  1121. +
  1122. + /* duplex */
  1123. + np->full_duplex = 1;
  1124. + np->current_duplex = full;
  1125. +
  1126. + rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl);
  1127. + rec_ctrl.duplex = regk_eth_full;
  1128. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  1129. + } else {
  1130. + np->mii_if.supports_gmii = mii_check_gmii_support(&np->mii_if);
  1131. +
  1132. + /* speed */
  1133. + np->current_speed = 10;
  1134. + np->current_speed_selection = 0; /* Auto. */
  1135. + np->speed_timer = timer_init;
  1136. + np->speed_timer.expires = jiffies + NET_LINK_UP_CHECK_INTERVAL;
  1137. + np->speed_timer.data = (unsigned long) dev;
  1138. + np->speed_timer.function = crisv32_eth_check_speed;
  1139. +
  1140. + /* duplex */
  1141. + np->full_duplex = 0;
  1142. + np->current_duplex = autoneg;
  1143. + np->duplex_timer = timer_init;
  1144. + np->duplex_timer.expires = jiffies + NET_DUPLEX_CHECK_INTERVAL;
  1145. + np->duplex_timer.data = (unsigned long) dev;
  1146. + np->duplex_timer.function = crisv32_eth_check_duplex;
  1147. + }
  1148. +
  1149. + return 0;
  1150. +}
  1151. +
  1152. +static void __init crisv32_eth_setup_controller(struct net_device *dev)
  1153. +{
  1154. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1155. + reg_eth_rw_gen_ctrl gen_ctrl;
  1156. +
  1157. + reg_eth_rw_tr_ctrl tr_ctrl = {
  1158. + /* SW retransmits to avoid transmitter bugs. */
  1159. + .retry = regk_eth_no,
  1160. + .pad = regk_eth_yes,
  1161. + .crc = regk_eth_yes
  1162. + };
  1163. +
  1164. + reg_eth_rw_rec_ctrl rec_ctrl = {
  1165. + .ma0 = regk_eth_no, /* enable at open() */
  1166. + .broadcast = regk_eth_no,
  1167. + .max_size = regk_eth_size1522
  1168. + };
  1169. +
  1170. + reg_eth_rw_ga_lo ga_lo = { 0 };
  1171. + reg_eth_rw_ga_hi ga_hi = { 0 };
  1172. +
  1173. + /*
  1174. + * Initialize group address registers to make sure that no
  1175. + * unwanted addresses are matched.
  1176. + */
  1177. + REG_WR(eth, np->eth_inst, rw_ga_lo, ga_lo);
  1178. + REG_WR(eth, np->eth_inst, rw_ga_hi, ga_hi);
  1179. +
  1180. + /* Configure receiver and transmitter */
  1181. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  1182. + REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl);
  1183. +
  1184. + /*
  1185. + * Read from rw_gen_ctrl so that we don't override any previous
  1186. + * configuration.
  1187. + */
  1188. + gen_ctrl = REG_RD(eth, np->eth_inst, rw_gen_ctrl);
  1189. + gen_ctrl.phy = regk_eth_mii_clk;
  1190. +#ifdef CONFIG_ETRAXFS
  1191. + /* On ETRAX FS, this bit has reversed meaning */
  1192. + gen_ctrl.flow_ctrl = regk_eth_no;
  1193. +#else
  1194. + gen_ctrl.flow_ctrl = regk_eth_yes;
  1195. +#endif
  1196. +
  1197. + /* Enable ethernet controller with mii clk. */
  1198. + REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
  1199. + gen_ctrl.en = regk_eth_yes;
  1200. + REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
  1201. +}
  1202. +
  1203. +static void crisv32_eth_reset_rx_ring(struct net_device *dev)
  1204. +{
  1205. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1206. + int i;
  1207. +
  1208. + /* cleanup the rx-ring */
  1209. + for (i = 0; i < NBR_RX_DESC; i++) {
  1210. + struct sk_buff *skb;
  1211. + skb = np->dma_rx_descr_list[i].skb;
  1212. + if (!skb
  1213. + || (np->dma_rx_descr_list[i].descr.buf !=
  1214. + (void *)virt_to_phys(skb->data))) {
  1215. + if (skb)
  1216. + dev_kfree_skb(skb);
  1217. + skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
  1218. + np->dma_rx_descr_list[i].skb = skb;
  1219. + np->dma_rx_descr_list[i].descr.buf =
  1220. + (char*)virt_to_phys(skb->data);
  1221. + }
  1222. + if (np->dma_rx_descr_list[i].descr.in_eop)
  1223. + np->rx_restarts_dropped++;
  1224. + np->dma_rx_descr_list[i].descr.after =
  1225. + (char*)virt_to_phys(skb->data
  1226. + + MAX_MEDIA_DATA_SIZE);
  1227. + np->dma_rx_descr_list[i].descr.eol = 0;
  1228. + np->dma_rx_descr_list[i].descr.in_eop = 0;
  1229. + /* Workaround cache bug */
  1230. + flush_dma_descr(&np->dma_rx_descr_list[i].descr, 1);
  1231. + }
  1232. +
  1233. + /* reset rx-ring */
  1234. + np->active_rx_desc = &np->dma_rx_descr_list[0];
  1235. + np->prev_rx_desc = &np->dma_rx_descr_list[NBR_RX_DESC - 1];
  1236. + np->last_rx_desc = np->prev_rx_desc;
  1237. + np->dma_rx_descr_list[NBR_RX_DESC - 1].descr.eol = 1;
  1238. + flush_dma_descr(&np->dma_rx_descr_list[NBR_RX_DESC - 1].descr, 0);
  1239. + /* ready to accept new packets. */
  1240. + np->new_rx_package = 1;
  1241. +
  1242. + /* Fill context descriptors. */
  1243. + np->ctxt_in.next = 0;
  1244. + np->ctxt_in.saved_data =
  1245. + (void *)virt_to_phys(&np->active_rx_desc->descr);
  1246. + np->ctxt_in.saved_data_buf = np->active_rx_desc->descr.buf;
  1247. +}
  1248. +
  1249. +static inline int crisv32_eth_tx_ring_full(struct crisv32_ethernet_local *np)
  1250. +{
  1251. + crisv32_eth_descr *active = np->active_tx_desc;
  1252. +
  1253. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  1254. + active = phys_to_virt((unsigned long)active->descr.next);
  1255. +#endif
  1256. + if (active == np->catch_tx_desc)
  1257. + return 1;
  1258. + return 0;
  1259. +}
  1260. +
  1261. +static void crisv32_eth_reset_tx_ring(struct net_device *dev)
  1262. +{
  1263. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1264. +
  1265. + /* free un-handled tx packets */
  1266. + while (np->txpackets || np->catch_tx_desc != np->active_tx_desc) {
  1267. + np->txpackets--;
  1268. + if (np->catch_tx_desc->skb)
  1269. + dev_kfree_skb(np->catch_tx_desc->skb);
  1270. +
  1271. + np->catch_tx_desc->skb = 0;
  1272. + np->catch_tx_desc =
  1273. + phys_to_virt((int)np->catch_tx_desc->descr.next);
  1274. + }
  1275. +
  1276. + WARN_ON(np->txpackets != 0);
  1277. + np->txpackets = 0;
  1278. +
  1279. + /* reset tx-ring */
  1280. + np->dma_tx_descr_list[0].descr.buf =
  1281. + np->dma_tx_descr_list[0].descr.after = 0;
  1282. + np->dma_tx_descr_list[0].descr.eol = 1;
  1283. +
  1284. + np->active_tx_desc = &np->dma_tx_descr_list[0];
  1285. + np->prev_tx_desc = &np->dma_tx_descr_list[NBR_TX_DESC - 1];
  1286. + np->catch_tx_desc = &np->dma_tx_descr_list[0];
  1287. +
  1288. + np->ctxt_out.next = 0;
  1289. + np->ctxt_out.saved_data =
  1290. + (void *)virt_to_phys(&np->dma_tx_descr_list[0].descr);
  1291. +
  1292. +}
  1293. +
  1294. +static void crisv32_eth_reset_rings(struct net_device *dev)
  1295. +{
  1296. + crisv32_eth_reset_tx_ring(dev);
  1297. + crisv32_eth_reset_rx_ring(dev);
  1298. +}
  1299. +
  1300. +/*
  1301. + * Really advance the receive ring. RX interrupts must be off.
  1302. + */
  1303. +static void __crisv32_eth_rx_ring_advance(struct crisv32_ethernet_local *np)
  1304. +{
  1305. + if (np->newbuf)
  1306. + np->active_rx_desc->descr.buf = (void *) np->newbuf;
  1307. + np->active_rx_desc->descr.after =
  1308. + np->active_rx_desc->descr.buf + MAX_MEDIA_DATA_SIZE;
  1309. + np->active_rx_desc->descr.eol = 1;
  1310. + np->active_rx_desc->descr.in_eop = 0;
  1311. + np->active_rx_desc = phys_to_virt((int)np->active_rx_desc->descr.next);
  1312. + barrier();
  1313. + np->prev_rx_desc->descr.eol = 0;
  1314. +
  1315. + /* Workaround cache bug. */
  1316. + flush_dma_descr(&np->prev_rx_desc->descr, 0);
  1317. + np->prev_rx_desc = phys_to_virt((int)np->prev_rx_desc->descr.next);
  1318. + flush_dma_descr(&np->prev_rx_desc->descr, 1);
  1319. +}
  1320. +
  1321. +/*
  1322. + * Advance the receive ring. RX interrupts must be off.
  1323. + */
  1324. +static inline void
  1325. +crisv32_eth_rx_ring_advance(struct crisv32_ethernet_local *np)
  1326. +{
  1327. + /*
  1328. + * When the input DMA reaches eol precaution must be taken, otherwise
  1329. + * the DMA could stop. The problem occurs if the eol flag is re-placed
  1330. + * on the descriptor that the DMA stands on before the DMA proceed to
  1331. + * the next descriptor. This case could, for example, happen if there
  1332. + * is a traffic burst and then the network goes silent. To prevent this
  1333. + * we make sure that we do not set the eol flag on the descriptor that
  1334. + * the DMA stands on.
  1335. + */
  1336. + unsigned long dma_pos;
  1337. +
  1338. + /* Get the current input dma position. */
  1339. + dma_pos = REG_RD_INT(dma, np->dma_in_inst, rw_saved_data);
  1340. +
  1341. + if (virt_to_phys(&np->active_rx_desc->descr) != dma_pos) {
  1342. + crisv32_eth_descr *cur, *nxt;
  1343. +
  1344. + /* Now really advance the ring one step. */
  1345. + __crisv32_eth_rx_ring_advance(np);
  1346. +
  1347. + cur = np->active_rx_desc;
  1348. + nxt = (void *)phys_to_virt((unsigned long)cur->descr.next);
  1349. + flush_dma_descr(&cur->descr, 0);
  1350. + flush_dma_descr(&nxt->descr, 0);
  1351. + if (!cur->descr.in_eop && nxt->descr.in_eop) {
  1352. + /* TODO: Investigate this more. The DMA seems to have
  1353. + skipped a descriptor, possibly due to incoherence
  1354. + between the CPU L1 cache and the DMA updates to the
  1355. + descriptor. */
  1356. + np->newbuf = (unsigned long) np->active_rx_desc->descr.buf;
  1357. + __crisv32_eth_rx_ring_advance(np);
  1358. + }
  1359. + /* flush after peek. */
  1360. + flush_dma_descr(&cur->descr, 0);
  1361. + flush_dma_descr(&nxt->descr, 0);
  1362. + } else {
  1363. + /* delay the advancing of the ring. */
  1364. + np->new_rx_package = 0;
  1365. + }
  1366. +}
  1367. +
  1368. +static void __init crisv32_eth_init_rings(struct net_device *dev)
  1369. +{
  1370. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1371. + int i;
  1372. +
  1373. + /* Initialise receive descriptors for interface. */
  1374. + for (i = 0; i < NBR_RX_DESC; i++) {
  1375. + struct sk_buff *skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
  1376. +
  1377. + np->dma_rx_descr_list[i].skb = skb;
  1378. + np->dma_rx_descr_list[i].descr.buf =
  1379. + (char*)virt_to_phys(skb->data);
  1380. + np->dma_rx_descr_list[i].descr.after =
  1381. + (char*)virt_to_phys(skb->data + MAX_MEDIA_DATA_SIZE);
  1382. +
  1383. + np->dma_rx_descr_list[i].descr.eol = 0;
  1384. + np->dma_rx_descr_list[i].descr.in_eop = 0;
  1385. + np->dma_rx_descr_list[i].descr.next =
  1386. + (void *) virt_to_phys(&np->dma_rx_descr_list[i + 1].descr);
  1387. + }
  1388. + /* bend the list into a ring */
  1389. + np->dma_rx_descr_list[NBR_RX_DESC - 1].descr.next =
  1390. + (void *) virt_to_phys(&np->dma_rx_descr_list[0].descr);
  1391. +
  1392. + /* Initialize transmit descriptors. */
  1393. + for (i = 0; i < NBR_TX_DESC; i++) {
  1394. + np->dma_tx_descr_list[i].descr.wait = 1;
  1395. + np->dma_tx_descr_list[i].descr.eol = 0;
  1396. + np->dma_tx_descr_list[i].descr.out_eop = 0;
  1397. + np->dma_tx_descr_list[i].descr.next =
  1398. + (void*)virt_to_phys(&np->dma_tx_descr_list[i+1].descr);
  1399. + }
  1400. + /* bend the list into a ring */
  1401. + np->dma_tx_descr_list[NBR_TX_DESC - 1].descr.next =
  1402. + (void *) virt_to_phys(&np->dma_tx_descr_list[0].descr);
  1403. +
  1404. + crisv32_eth_reset_rings(dev);
  1405. +}
  1406. +
  1407. +static void __init crisv32_init_leds(int ledgrp, struct net_device *dev)
  1408. +{
  1409. + struct timer_list timer_init = TIMER_INITIALIZER(NULL, 0, 0);
  1410. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1411. +
  1412. + /* Use already allocated led grp if initialized */
  1413. + if (crisv32_leds[ledgrp] != NULL) {
  1414. + np->leds = crisv32_leds[ledgrp];
  1415. + return;
  1416. + }
  1417. +
  1418. + crisv32_leds[ledgrp] =
  1419. + kmalloc(sizeof(struct crisv32_eth_leds), GFP_KERNEL);
  1420. +
  1421. + crisv32_leds[ledgrp]->ledgrp = ledgrp;
  1422. + crisv32_leds[ledgrp]->led_active = 0;
  1423. + crisv32_leds[ledgrp]->ifisup[0] = 0;
  1424. + crisv32_leds[ledgrp]->ifisup[1] = 0;
  1425. + /* NOTE: Should this value be set to zero as the jiffies timer
  1426. + can wrap? */
  1427. + crisv32_leds[ledgrp]->led_next_time = jiffies;
  1428. +
  1429. + crisv32_leds[ledgrp]->clear_led_timer = timer_init;
  1430. + crisv32_leds[ledgrp]->clear_led_timer.function =
  1431. + crisv32_clear_network_leds;
  1432. + crisv32_leds[ledgrp]->clear_led_timer.data = (unsigned long) dev;
  1433. +
  1434. + spin_lock_init(&crisv32_leds[ledgrp]->led_lock);
  1435. +
  1436. + np->leds = crisv32_leds[ledgrp];
  1437. +}
  1438. +
  1439. +static int __init crisv32_ethernet_init(void)
  1440. +{
  1441. + struct crisv32_ethernet_local *np;
  1442. + int ret = 0;
  1443. +
  1444. +#ifdef CONFIG_ETRAXFS
  1445. + printk("ETRAX FS 10/100MBit ethernet v0.01 (c)"
  1446. + " 2003 Axis Communications AB\n");
  1447. +#else
  1448. + printk("ARTPEC-3 10/100 MBit ethernet (c)"
  1449. + " 2003-2009 Axis Communications AB\n");
  1450. +#endif
  1451. +
  1452. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  1453. + {
  1454. + reg_clkgen_rw_clk_ctrl clk_ctrl = REG_RD(clkgen, regi_clkgen,
  1455. + rw_clk_ctrl);
  1456. + clk_ctrl.eth = clk_ctrl.dma0_1_eth = regk_clkgen_yes;
  1457. + REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
  1458. + }
  1459. +#endif
  1460. +{
  1461. + int iface0 = 0;
  1462. +
  1463. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  1464. + if (crisv32_pinmux_alloc_fixed(pinmux_eth))
  1465. + panic("Eth pinmux\n");
  1466. +#endif
  1467. +
  1468. + if (!(crisv32_dev[iface0] = alloc_etherdev(sizeof *np)))
  1469. + return -ENOMEM;
  1470. +
  1471. + ret |= crisv32_ethernet_device_init(crisv32_dev[iface0]);
  1472. +
  1473. + crisv32_init_leds(CRIS_LED_GRP_NONE,crisv32_dev[iface0]);
  1474. +
  1475. + np = (struct crisv32_ethernet_local *) netdev_priv(crisv32_dev[iface0]);
  1476. + np->eth_inst = regi_eth0;
  1477. + np->dma_out_inst = regi_dma0;
  1478. + np->dma_in_inst = regi_dma1;
  1479. +
  1480. + np->mii_if.dev = crisv32_dev[iface0];
  1481. + np->mii_if.mdio_read = crisv32_eth_get_mdio_reg;
  1482. + np->mii_if.mdio_write = crisv32_eth_set_mdio_reg;
  1483. + np->mii_if.phy_id_mask = 0x1f;
  1484. + np->mii_if.reg_num_mask = 0x1f;
  1485. +
  1486. + np->use_leds = 1;
  1487. + np->autoneg_normal = 1;
  1488. +
  1489. +
  1490. + register_netdev(crisv32_dev[iface0]);
  1491. +
  1492. + /* Set up default MAC address */
  1493. + memcpy(crisv32_dev[iface0]->dev_addr, default_mac_iface0.sa_data, 6);
  1494. + crisv32_eth_set_mac_address(crisv32_dev[iface0], &default_mac_iface0);
  1495. + if (crisv32_eth_request_irqdma(crisv32_dev[iface0]))
  1496. + printk("%s: eth0 unable to allocate IRQ and DMA resources\n",
  1497. + __func__);
  1498. + np->txpackets = 0;
  1499. + crisv32_eth_init_rings(crisv32_dev[iface0]);
  1500. + crisv32_eth_setup_controller(crisv32_dev[iface0]);
  1501. + ret |= crisv32_eth_init_phy(crisv32_dev[iface0]);
  1502. + if (ret) {
  1503. + unregister_netdev(crisv32_dev[iface0]);
  1504. + return ret;
  1505. + }
  1506. +}
  1507. +
  1508. +#ifdef CONFIG_ETRAX_ETHERNET_IFACE1
  1509. +{
  1510. + int iface1 = 0;
  1511. + /* Default MAC address for interface 1.
  1512. + * The real one will be set later. */
  1513. + static struct sockaddr default_mac_iface1 =
  1514. + {0, {0x00, 0x40, 0x8C, 0xCD, 0x00, 0x01}};
  1515. +
  1516. + if (crisv32_pinmux_alloc_fixed(pinmux_eth1))
  1517. + panic("Eth pinmux\n");
  1518. +
  1519. + /* Increase index to device array if interface 0 is enabled as well.*/
  1520. +#ifdef CONFIG_ETRAX_ETHERNET_IFACE0
  1521. + iface1++;
  1522. +#endif
  1523. + if (!(crisv32_dev[iface1] = alloc_etherdev(sizeof *np)))
  1524. + return -ENOMEM;
  1525. +
  1526. + ret |= crisv32_ethernet_device_init(crisv32_dev[iface1]);
  1527. +
  1528. + crisv32_init_leds(CRIS_LED_GRP_NONE,crisv32_dev[iface1]);
  1529. +
  1530. + np = (struct crisv32_ethernet_local *) netdev_priv(crisv32_dev[iface1]);
  1531. + np->eth_inst = regi_eth1;
  1532. + np->dma_out_inst = regi_dma6;
  1533. + np->dma_in_inst = regi_dma7;
  1534. +
  1535. + np->mii_if.dev = crisv32_dev[iface1];
  1536. + np->mii_if.mdio_read = crisv32_eth_get_mdio_reg;
  1537. + np->mii_if.mdio_write = crisv32_eth_set_mdio_reg;
  1538. + np->mii_if.phy_id_mask = 0x1f;
  1539. + np->mii_if.reg_num_mask = 0x1f;
  1540. +
  1541. +
  1542. + register_netdev(crisv32_dev[iface1]);
  1543. +
  1544. + /* Set up default MAC address */
  1545. + memcpy(crisv32_dev[iface1]->dev_addr, default_mac_iface1.sa_data, 6);
  1546. + crisv32_eth_set_mac_address(crisv32_dev[iface1], &default_mac_iface1);
  1547. +
  1548. + if (crisv32_eth_request_irqdma(crisv32_dev[iface1]))
  1549. + printk("%s: eth1 unable to allocate IRQ and DMA resources\n",
  1550. + __func__);
  1551. + np->txpackets = 0;
  1552. + crisv32_eth_init_rings(crisv32_dev[iface1]);
  1553. + crisv32_eth_setup_controller(crisv32_dev[iface1]);
  1554. + ret |= crisv32_eth_init_phy(crisv32_dev[iface1]);
  1555. + if (ret) {
  1556. + unregister_netdev(crisv32_dev[iface1]);
  1557. + return ret;
  1558. + }
  1559. +}
  1560. +#endif /* CONFIG_ETRAX_ETHERNET_IFACE1 */
  1561. +
  1562. +#ifdef CONFIG_CPU_FREQ
  1563. + cpufreq_register_notifier(&crisv32_ethernet_freq_notifier_block,
  1564. + CPUFREQ_TRANSITION_NOTIFIER);
  1565. +#endif
  1566. +
  1567. + return ret;
  1568. +}
  1569. +
  1570. +static struct net_device_ops crisv32_netdev_ops = {
  1571. + .ndo_open = crisv32_eth_open,
  1572. + .ndo_stop = crisv32_eth_close,
  1573. + .ndo_start_xmit = crisv32_eth_send_packet,
  1574. + .ndo_set_rx_mode = crisv32_eth_set_rx_mode,
  1575. + .ndo_validate_addr = eth_validate_addr,
  1576. + .ndo_set_mac_address = crisv32_eth_set_mac_address,
  1577. + .ndo_do_ioctl =crisv32_eth_ioctl,
  1578. + .ndo_get_stats = crisv32_get_stats,
  1579. + .ndo_tx_timeout = crisv32_eth_do_tx_recovery,
  1580. + .ndo_set_config = crisv32_eth_set_config,
  1581. +};
  1582. +
  1583. +static int __init crisv32_ethernet_device_init(struct net_device *dev)
  1584. +{
  1585. + struct crisv32_ethernet_local *np;
  1586. + struct timer_list timer_init = TIMER_INITIALIZER(NULL, 0, 0);
  1587. +
  1588. + dev->base_addr = 0; /* Just to have something to show. */
  1589. +
  1590. + /* we do our own locking */
  1591. + dev->features |= NETIF_F_LLTX;
  1592. +
  1593. + /* We use several IRQs and DMAs so just report 0 here. */
  1594. + dev->irq = 0;
  1595. + dev->dma = 0;
  1596. +
  1597. + /*
  1598. + * Fill in our handlers so the network layer can talk to us in the
  1599. + * future.
  1600. + */
  1601. + dev->netdev_ops = &crisv32_netdev_ops;
  1602. + dev->ethtool_ops = &crisv32_ethtool_ops;
  1603. + dev->watchdog_timeo = HZ * 10;
  1604. +#ifdef CONFIG_NET_POLL_CONTROLLER
  1605. + dev->poll_controller = crisv32_netpoll;
  1606. +#endif
  1607. + np = netdev_priv(dev);
  1608. + np->dev = dev;
  1609. +
  1610. + /*
  1611. + * 8 skbs keeps the system very reponsive even under high load.
  1612. + * At 64 the system locks, pretty much the same way as without NAPI.
  1613. + *
  1614. + * TODO: meassure with 2 interfaces
  1615. + */
  1616. + netif_napi_add(dev, &np->napi, crisv32_eth_poll, 8);
  1617. +
  1618. + spin_lock_init(&np->lock);
  1619. + spin_lock_init(&np->transceiver_lock);
  1620. +
  1621. + np->receive_timer = timer_init;
  1622. + np->receive_timer.data = (unsigned)dev;
  1623. + np->receive_timer.function = receive_timeout;
  1624. +
  1625. + INIT_WORK(&np->receive_work, receive_timeout_work);
  1626. +
  1627. + np->transmit_timer = timer_init;
  1628. + np->transmit_timer.data = (unsigned)dev;
  1629. + np->transmit_timer.function = transmit_timeout;
  1630. +
  1631. + return 0;
  1632. +}
  1633. +
  1634. +static int crisv32_eth_open(struct net_device *dev)
  1635. +{
  1636. + struct sockaddr mac_addr;
  1637. + reg_dma_rw_ack_intr ack_intr = { .data = 1, .in_eop = 1 };
  1638. + reg_eth_rw_clr_err clr_err = {.clr = regk_eth_yes};
  1639. + /*
  1640. + * dont interrupt us at any stat counter thresholds, only at urun
  1641. + * and exc_col.
  1642. + */
  1643. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  1644. + /* For Artpec-3 we use overrun to workaround voodoo TR 87 */
  1645. + int intr_mask_nw = 0x1c00;
  1646. +#else
  1647. + int intr_mask_nw = 0x1800;
  1648. +#endif
  1649. + int eth_ack_intr = 0xffff;
  1650. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1651. +
  1652. + spin_lock(&np->lock);
  1653. + crisv32_eth_set_gigabit(np, 0);
  1654. +
  1655. + crisv32_disable_tx_ints(np);
  1656. + crisv32_disable_rx_ints(np);
  1657. +
  1658. + REG_WR(eth, np->eth_inst, rw_clr_err, clr_err);
  1659. + REG_WR_INT(eth, np->eth_inst, rw_ack_intr, eth_ack_intr);
  1660. + REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw);
  1661. + crisv32_eth_reset_rings(dev);
  1662. +
  1663. + /* Give the hardware an idea of what MAC address we want. */
  1664. + memcpy(mac_addr.sa_data, dev->dev_addr, dev->addr_len);
  1665. + crisv32_eth_set_mac_address(dev, &mac_addr);
  1666. +
  1667. + /* Enable irq and make sure that the irqs are cleared. */
  1668. + REG_WR(dma, np->dma_out_inst, rw_ack_intr, ack_intr);
  1669. + REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
  1670. +
  1671. + crisv32_disconnect_eth_rx_dma(np);
  1672. +
  1673. + /* Prepare input DMA. */
  1674. + DMA_RESET(np->dma_in_inst);
  1675. + DMA_ENABLE(np->dma_in_inst);
  1676. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  1677. + DMA_WR_CMD(np->dma_in_inst, regk_dma_set_w_size2);
  1678. +#endif
  1679. + DMA_START_CONTEXT(np->dma_in_inst, virt_to_phys(&np->ctxt_in));
  1680. + DMA_CONTINUE(np->dma_in_inst);
  1681. + crisv32_enable_rx_ints(np);
  1682. + crisv32_start_receiver(np);
  1683. +
  1684. + /* Prepare output DMA. */
  1685. + DMA_RESET(np->dma_out_inst);
  1686. + DMA_ENABLE(np->dma_out_inst);
  1687. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  1688. + DMA_WR_CMD(np->dma_out_inst, regk_dma_set_w_size4);
  1689. +#endif
  1690. + crisv32_connect_eth_rx_dma(np);
  1691. +
  1692. + netif_start_queue(dev);
  1693. + crisv32_enable_tx_ints(np);
  1694. +
  1695. + if (!np->fixed_phy) {
  1696. + /* Start duplex/speed timers */
  1697. + if (!timer_pending(&np->speed_timer))
  1698. + add_timer(&np->speed_timer);
  1699. + if (!timer_pending(&np->duplex_timer))
  1700. + add_timer(&np->duplex_timer);
  1701. + }
  1702. +
  1703. + spin_unlock(&np->lock);
  1704. + /*
  1705. + * We are now ready to accept transmit requests from the queueing
  1706. + * layer of the networking.
  1707. + */
  1708. + np->link = 1;
  1709. + netif_carrier_on(dev);
  1710. + napi_enable(&np->napi);
  1711. +
  1712. + return 0;
  1713. +}
  1714. +
  1715. +static int crisv32_eth_close(struct net_device *dev)
  1716. +{
  1717. + reg_dma_rw_ack_intr ack_intr = {0};
  1718. +
  1719. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1720. + unsigned long flags;
  1721. +
  1722. + del_timer(&np->transmit_timer);
  1723. + spin_lock_irqsave(&np->lock, flags);
  1724. +
  1725. + /* stop the receiver before the DMA channels to avoid overruns. */
  1726. + crisv32_disable_rx_ints(np);
  1727. + napi_disable(&np->napi);
  1728. + crisv32_stop_receiver(np);
  1729. +
  1730. + netif_stop_queue(dev);
  1731. +
  1732. + /* Reset the TX DMA in case it has hung on something. */
  1733. + DMA_RESET(np->dma_in_inst);
  1734. +
  1735. + /* Stop DMA */
  1736. + DMA_STOP(np->dma_in_inst);
  1737. + DMA_STOP(np->dma_out_inst);
  1738. +
  1739. + /* Disable irq and make sure that the irqs are cleared. */
  1740. + crisv32_disable_tx_ints(np);
  1741. + ack_intr.data = 1;
  1742. + REG_WR(dma, np->dma_out_inst, rw_ack_intr, ack_intr);
  1743. +
  1744. + ack_intr.in_eop = 1;
  1745. + REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
  1746. +
  1747. + np->sender_started = 0;
  1748. + spin_unlock_irqrestore(&np->lock, flags);
  1749. +
  1750. + /* Update the statistics. */
  1751. + update_rx_stats(np);
  1752. + update_tx_stats(np);
  1753. +
  1754. + if (!np->fixed_phy) {
  1755. + /* Stop speed/duplex timers */
  1756. + del_timer(&np->speed_timer);
  1757. + del_timer(&np->duplex_timer);
  1758. + }
  1759. +
  1760. + return 0;
  1761. +}
  1762. +
  1763. +static int crisv32_eth_set_mac_address(struct net_device *dev, void *vpntr)
  1764. +{
  1765. + int i;
  1766. + static int first = 1;
  1767. +
  1768. + unsigned char *addr = ((struct sockaddr*)vpntr)->sa_data;
  1769. +
  1770. + reg_eth_rw_ma0_lo ma0_lo =
  1771. + { addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24)};
  1772. +
  1773. + reg_eth_rw_ma0_hi ma0_hi = { addr[4] | (addr[5] << 8) };
  1774. +
  1775. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1776. +
  1777. + /* Remember the address. */
  1778. + memcpy(dev->dev_addr, addr, dev->addr_len);
  1779. +
  1780. + /*
  1781. + * Write the address to the hardware.
  1782. + * Note the way the address is wrapped:
  1783. + * ma0_l0 = a0_0 | (a0_1 << 8) | (a0_2 << 16) | (a0_3 << 24);
  1784. + * ma0_hi = a0_4 | (a0_5 << 8);
  1785. + */
  1786. + REG_WR(eth, np->eth_inst, rw_ma0_lo, ma0_lo);
  1787. + REG_WR(eth, np->eth_inst, rw_ma0_hi, ma0_hi);
  1788. +
  1789. + if (first) {
  1790. + printk(KERN_INFO "%s: changed MAC to ", dev->name);
  1791. +
  1792. + for (i = 0; i < 5; i++)
  1793. + printk("%02X:", dev->dev_addr[i]);
  1794. + printk("%02X\n", dev->dev_addr[i]);
  1795. +
  1796. + first = 0;
  1797. + }
  1798. +
  1799. + return 0;
  1800. +}
  1801. +
  1802. +static irqreturn_t crisv32rx_eth_interrupt(int irq, void *dev_id)
  1803. +{
  1804. + struct net_device *dev = (struct net_device *) dev_id;
  1805. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1806. + reg_dma_r_masked_intr masked_in;
  1807. +
  1808. + masked_in = REG_RD(dma, np->dma_in_inst, r_masked_intr);
  1809. +
  1810. + if (masked_in.in_eop) {
  1811. + reg_dma_rw_ack_intr ack_intr = {0};
  1812. +
  1813. + /*
  1814. + * Ack the rx irq even if we are not prepared to start
  1815. + * polling. This is needed to handle incomming packets
  1816. + * during the stop sequence.
  1817. + */
  1818. + ack_intr.in_eop = 1;
  1819. + REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
  1820. +
  1821. + mod_timer(&np->receive_timer, jiffies + HZ);
  1822. + np->do_rx_recovery = 0;
  1823. +
  1824. + if (napi_schedule_prep(&np->napi)) {
  1825. + crisv32_disable_rx_ints(np);
  1826. + crisv32_disable_tx_ints(np);
  1827. + /* put us onto the poll list */
  1828. + __napi_schedule(&np->napi);
  1829. + }
  1830. + } else {
  1831. + /* Unexpected, ACK it and hope for the best. */
  1832. + reg_dma_rw_ack_intr ack_intr = {
  1833. + .group = 1,
  1834. + .ctxt = 1,
  1835. + .data = 1,
  1836. + .in_eop = 0,
  1837. + .stream_cmd = 1,
  1838. + .dummy1 = ~0
  1839. + };
  1840. + REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
  1841. + }
  1842. +
  1843. + return IRQ_HANDLED;
  1844. +}
  1845. +
  1846. +static inline void crisv32_eth_roll_tx_timer(struct crisv32_ethernet_local *np)
  1847. +{
  1848. + /* If there are more packets in the ring, roll the tx timer. */
  1849. + if (np->txpackets) {
  1850. + /* Eth pause frames may halt us for up to 320ms (100mbit). */
  1851. + unsigned long timeout = jiffies + (HZ / 3) + 1;
  1852. + mod_timer(&np->transmit_timer, timeout);
  1853. + }
  1854. + else
  1855. + del_timer(&np->transmit_timer);
  1856. +}
  1857. +
  1858. +/* Call with np->lock held. */
  1859. +static void _crisv32_tx_ring_advance(struct crisv32_ethernet_local *np,
  1860. + int cleanup)
  1861. +{
  1862. + reg_dma_rw_stat stat;
  1863. + dma_descr_data *dma_pos;
  1864. + struct net_device *dev = np->dev;
  1865. + int eol;
  1866. +
  1867. + /* Get the current output dma position. */
  1868. + dma_pos = phys_to_virt(REG_RD_INT(dma, np->dma_out_inst, rw_data));
  1869. + stat = REG_RD(dma, np->dma_out_inst, rw_stat);
  1870. + eol = stat.list_state == regk_dma_data_at_eol;
  1871. + if (cleanup || eol)
  1872. + dma_pos = &np->active_tx_desc->descr;
  1873. +
  1874. + /* Take care of transmited dma descriptors and report sent packet. */
  1875. + while (np->txpackets && (&np->catch_tx_desc->descr != dma_pos)) {
  1876. + /* Update sent packet statistics. */
  1877. + np->stats.tx_bytes += np->catch_tx_desc->skb->len;
  1878. + np->stats.tx_packets++;
  1879. +
  1880. + dev_kfree_skb_any(np->catch_tx_desc->skb);
  1881. + np->catch_tx_desc->skb = 0;
  1882. + np->txpackets--;
  1883. + np->catch_tx_desc->descr.buf = 0;
  1884. + np->catch_tx_desc =
  1885. + phys_to_virt((int)np->catch_tx_desc->descr.next);
  1886. + np->do_tx_recovery = 0;
  1887. + np->retrans = 0;
  1888. +
  1889. + netif_wake_queue(dev);
  1890. + }
  1891. +}
  1892. +
  1893. +static inline void crisv32_tx_ring_advance(struct crisv32_ethernet_local *np)
  1894. +{
  1895. + unsigned long flags;
  1896. +
  1897. + spin_lock_irqsave(&np->lock, flags);
  1898. + _crisv32_tx_ring_advance(np, 0);
  1899. + crisv32_eth_roll_tx_timer(np);
  1900. + spin_unlock_irqrestore(&np->lock, flags);
  1901. +}
  1902. +
  1903. +static inline int crisv32_tx_complete(struct crisv32_ethernet_local *np)
  1904. +{
  1905. + reg_dma_rw_ack_intr ack_intr = { .data = 1 };
  1906. + reg_dma_r_intr ints;
  1907. + int r = 0;
  1908. +
  1909. + /* We are interested in the unmasked raw interrupt source here. When
  1910. + polling with tx interrupts masked off we still want to do
  1911. + tx completition when the DMA makes progress. */
  1912. + ints = REG_RD(dma, np->dma_out_inst, r_intr);
  1913. + if (ints.data)
  1914. + {
  1915. + /* ack the interrupt, if it was active */
  1916. + REG_WR(dma, np->dma_out_inst, rw_ack_intr, ack_intr);
  1917. + crisv32_tx_ring_advance(np);
  1918. + r = 1;
  1919. + }
  1920. + return r;
  1921. +}
  1922. +
  1923. +static irqreturn_t crisv32tx_eth_interrupt(int irq, void *dev_id)
  1924. +{
  1925. + struct crisv32_ethernet_local *np = netdev_priv(dev_id);
  1926. +
  1927. + crisv32_tx_complete(np);
  1928. + return IRQ_HANDLED;
  1929. +}
  1930. +
  1931. +
  1932. +/* Update receive errors. */
  1933. +static void
  1934. +update_rx_stats(struct crisv32_ethernet_local *np)
  1935. +{
  1936. + reg_eth_rs_rec_cnt r;
  1937. +
  1938. + r = REG_RD(eth, np->eth_inst, rs_rec_cnt);
  1939. +
  1940. + np->stats.rx_over_errors += r.congestion;
  1941. + np->stats.rx_crc_errors += r.crc_err;
  1942. + np->stats.rx_frame_errors += r.align_err;
  1943. + np->stats.rx_length_errors += r.oversize;
  1944. + np->stats.rx_errors += r.crc_err + r.align_err +
  1945. + r.oversize + r.congestion;
  1946. +}
  1947. +
  1948. +/* Update transmit errors. */
  1949. +static void update_tx_stats(struct crisv32_ethernet_local *np)
  1950. +{
  1951. + reg_eth_rs_tr_cnt r;
  1952. + reg_eth_rs_phy_cnt rp;
  1953. +
  1954. + r = REG_RD(eth, np->eth_inst, rs_tr_cnt);
  1955. + rp = REG_RD(eth, np->eth_inst, rs_phy_cnt);
  1956. +
  1957. + /* r.deferred is not good for counting collisions because it also
  1958. + includes frames that have to wait for the interframe gap. That
  1959. + means we get deferred frames even when in full duplex.
  1960. + Here we don't actually count the number of collisions that
  1961. + occured (artpec3 seems to lack such a counter), instead we count
  1962. + the number of frames that collide once or more. */
  1963. + np->stats.collisions += r.mult_col + r.single_col;
  1964. + np->stats.tx_window_errors += r.late_col;
  1965. + np->stats.tx_carrier_errors += rp.carrier_loss;
  1966. +
  1967. + /* Ordinary collisions are not errors, they are just part of
  1968. + ethernet's bus arbitration and congestion control mechanisms.
  1969. + Late collisions are serious errors though. */
  1970. + np->stats.tx_errors += r.late_col;
  1971. +}
  1972. +
  1973. +/* Get current statistics. */
  1974. +static struct net_device_stats *crisv32_get_stats(struct net_device *dev)
  1975. +{
  1976. + unsigned long flags;
  1977. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1978. +
  1979. + spin_lock_irqsave(&np->lock, flags);
  1980. +
  1981. + update_rx_stats(np);
  1982. + update_tx_stats(np);
  1983. +
  1984. + spin_unlock_irqrestore(&np->lock, flags);
  1985. +
  1986. + return &np->stats;
  1987. +}
  1988. +
  1989. +/* Check for network errors. This acknowledge the received interrupt. */
  1990. +static irqreturn_t crisv32nw_eth_interrupt(int irq, void *dev_id)
  1991. +{
  1992. + struct net_device *dev = (struct net_device *) dev_id;
  1993. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  1994. + reg_eth_r_masked_intr intr_mask;
  1995. + int ack_intr = 0xffff;
  1996. + reg_eth_rw_clr_err clr_err;
  1997. +
  1998. + intr_mask = REG_RD(eth, np->eth_inst, r_masked_intr);
  1999. +
  2000. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  2001. + /* Only apply the workaround if it is not already pending.
  2002. + enable_eth_ints will re-enable the orun interrupt regardless
  2003. + of pending_overrun. */
  2004. + if (intr_mask.orun && !np->pending_overrun) {
  2005. + reg_eth_rw_rec_ctrl rec_ctrl =
  2006. + REG_RD(eth, np->eth_inst, rw_rec_ctrl);
  2007. + np->saved_rec_ctrl = rec_ctrl;
  2008. + np->overrun_set = 1;
  2009. + DMA_STOP(np->dma_in_inst);
  2010. + rec_ctrl.ma0 = regk_eth_no;
  2011. + rec_ctrl.broadcast = regk_eth_no;
  2012. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  2013. + np->saved_ga_lo = REG_RD_INT(eth, np->eth_inst, rw_ga_lo);
  2014. + np->saved_ga_hi = REG_RD_INT(eth, np->eth_inst, rw_ga_hi);
  2015. + REG_WR_INT(eth, np->eth_inst, rw_ga_lo, 0);
  2016. + REG_WR_INT(eth, np->eth_inst, rw_ga_hi, 0);
  2017. + REG_WR_INT(eth, np->eth_inst, rw_intr_mask,
  2018. + REG_RD_INT(eth, np->eth_inst, rw_intr_mask) & 0xfbff);
  2019. + REG_WR_INT(eth, np->eth_inst, rw_ack_intr, 0x400);
  2020. + intr_mask.orun = 0;
  2021. + np->pending_overrun = 1;
  2022. + if (!np->napi_processing)
  2023. + crisv32_eth_restart_rx_dma(np->dev, np);
  2024. +
  2025. + return IRQ_HANDLED;
  2026. + }
  2027. +#endif
  2028. +
  2029. + /*
  2030. + * Check for underrun and/or excessive collisions. Note that the
  2031. + * rw_clr_err register clears both underrun and excessive collision
  2032. + * errors, so there's no need to check them separately.
  2033. + */
  2034. + if (np->sender_started
  2035. + && (intr_mask.urun || intr_mask.exc_col)) {
  2036. + unsigned long flags;
  2037. +
  2038. + /* Underrun are considered to be tx-errors. */
  2039. + np->stats.tx_errors += intr_mask.urun;
  2040. + np->stats.tx_fifo_errors += intr_mask.urun;
  2041. +
  2042. + /*
  2043. + * Protect against the tx-interrupt messing with
  2044. + * the tx-ring.
  2045. + */
  2046. + spin_lock_irqsave(&np->lock, flags);
  2047. +
  2048. + /* DMA should have stopped now, eat from the ring before
  2049. + removing anything due to tx errors. */
  2050. + _crisv32_tx_ring_advance(np, 0);
  2051. +
  2052. + /*
  2053. + * Drop packets after 15 retries.
  2054. + * TODO: Add backoff.
  2055. + */
  2056. + if (np->retrans > 15 && np->txpackets) {
  2057. + dev_kfree_skb_irq(np->catch_tx_desc->skb);
  2058. + np->catch_tx_desc->skb = 0;
  2059. + np->catch_tx_desc->descr.buf = 0;
  2060. + np->catch_tx_desc =
  2061. + phys_to_virt((int)
  2062. + np->catch_tx_desc->descr.next);
  2063. + flush_dma_descr(&np->catch_tx_desc->descr, 0);
  2064. +
  2065. + np->txpackets--;
  2066. + np->retrans = 0;
  2067. + netif_wake_queue(dev);
  2068. + np->stats.tx_dropped++;
  2069. + }
  2070. + np->ctxt_out.next = 0;
  2071. + if (np->txpackets) {
  2072. + np->retrans++;
  2073. + np->ctxt_out.saved_data = (void *)
  2074. + virt_to_phys(&np->catch_tx_desc->descr);
  2075. + np->ctxt_out.saved_data_buf =
  2076. + np->catch_tx_desc->descr.buf;
  2077. + WARN_ON(!np->ctxt_out.saved_data_buf);
  2078. + flush_dma_descr(&np->catch_tx_desc->descr, 0);
  2079. + cris_flush_cache_range(&np->ctxt_out,
  2080. + sizeof np->ctxt_out);
  2081. +
  2082. + /* restart the DMA */
  2083. + DMA_START_CONTEXT(np->dma_out_inst,
  2084. + (int) virt_to_phys(&np->ctxt_out));
  2085. + np->sender_started = 1;
  2086. + }
  2087. + else {
  2088. + /* Load dummy context but do not load the data
  2089. + descriptor nor start the burst. This brings the
  2090. + buggy eth transmitter back in sync with the DMA
  2091. + avoiding malformed frames. */
  2092. + REG_WR(dma, np->dma_out_inst, rw_group_down,
  2093. + (int) virt_to_phys(&np->ctxt_out));
  2094. + DMA_WR_CMD(np->dma_out_inst, regk_dma_load_c);
  2095. + np->sender_started = 0;
  2096. + }
  2097. + crisv32_eth_roll_tx_timer(np);
  2098. + spin_unlock_irqrestore(&np->lock, flags);
  2099. + }
  2100. +
  2101. + ack_intr = *(u32 *)&intr_mask;
  2102. + REG_WR_INT(eth, np->eth_inst, rw_ack_intr, ack_intr);
  2103. + clr_err.clr = 1;
  2104. + REG_WR(eth, np->eth_inst, rw_clr_err, clr_err);
  2105. +
  2106. + update_rx_stats(np);
  2107. + update_tx_stats(np);
  2108. +
  2109. + return IRQ_HANDLED;
  2110. +}
  2111. +
  2112. +/* We have a good packet(s), get it/them out of the buffers. */
  2113. +static int crisv32_eth_receive_packet(struct net_device *dev)
  2114. +{
  2115. + int length;
  2116. + struct sk_buff *skb;
  2117. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2118. + struct sk_buff *tmp;
  2119. + unsigned long flags;
  2120. +
  2121. + DEBUG(printk("crisv32_receive_packet\n"));
  2122. +
  2123. + /* Roll the rx bug timer. */
  2124. + mod_timer(&np->receive_timer, jiffies + HZ);
  2125. +
  2126. + /* Activate LED */
  2127. + spin_lock_irqsave(&np->leds->led_lock, flags);
  2128. + if (!np->leds->led_active && time_after(jiffies,
  2129. + np->leds->led_next_time)) {
  2130. + /* light the network leds depending on the current speed. */
  2131. + crisv32_set_network_leds(CRIS_LED_ACTIVITY, dev);
  2132. +
  2133. + /* Set the earliest time we may clear the LED */
  2134. + np->leds->led_next_time = jiffies + NET_FLASH_TIME;
  2135. + np->leds->led_active = 1;
  2136. + np->leds->clear_led_timer.data = (unsigned long) dev;
  2137. + mod_timer(&np->leds->clear_led_timer, jiffies + HZ/10);
  2138. + }
  2139. + spin_unlock_irqrestore(&np->leds->led_lock, flags);
  2140. +
  2141. + /* Discard CRC (4 bytes). */
  2142. + length = (np->active_rx_desc->descr.after) -
  2143. + (np->active_rx_desc->descr.buf) - 4;
  2144. +
  2145. + tmp = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
  2146. + if (!tmp) {
  2147. + np->stats.rx_errors++;
  2148. + printk(KERN_NOTICE "%s: memory squeeze,"
  2149. + " dropping packet.",
  2150. + dev->name);
  2151. + return 0;
  2152. + }
  2153. + skb = np->active_rx_desc->skb;
  2154. + np->active_rx_desc->skb = tmp;
  2155. + skb_put(skb, length);
  2156. +
  2157. + np->newbuf = virt_to_phys(np->active_rx_desc->skb->data);
  2158. +
  2159. + skb->dev = dev;
  2160. + skb->protocol = eth_type_trans(skb, dev);
  2161. + skb->ip_summed = CHECKSUM_NONE;
  2162. +
  2163. + np->stats.multicast += skb->pkt_type == PACKET_MULTICAST;
  2164. + /* Send the packet to the upper layer. */
  2165. + netif_receive_skb(skb);
  2166. + np->last_rx_desc =
  2167. + phys_to_virt((int)
  2168. + np->last_rx_desc->descr.next);
  2169. +
  2170. + /* Forward rotate the receive ring. */
  2171. + crisv32_eth_rx_ring_advance(np);
  2172. + return length;
  2173. +}
  2174. +
  2175. +/* Must be called with the np-lock held. */
  2176. +static void
  2177. +__crisv32_eth_restart_rx_dma(struct net_device* dev,
  2178. + struct crisv32_ethernet_local *np)
  2179. +{
  2180. + reg_dma_rw_ack_intr ack_intr = {0};
  2181. + reg_dma_rw_stream_cmd dma_sc = {0};
  2182. + reg_dma_rw_stat stat;
  2183. + int resets = 0;
  2184. + reg_eth_rw_intr_mask eth_intr_mask;
  2185. +
  2186. + np->rx_dma_restarts++;
  2187. +
  2188. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  2189. + if (np->pending_overrun) {
  2190. + np->pending_overrun = 0;
  2191. + REG_WR_INT(eth, np->eth_inst, rw_ga_lo, np->saved_ga_lo);
  2192. + REG_WR_INT(eth, np->eth_inst, rw_ga_hi, np->saved_ga_hi);
  2193. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, np->saved_rec_ctrl);
  2194. + REG_WR_INT(eth, np->eth_inst, rw_intr_mask,
  2195. + REG_RD_INT(eth, regi_eth, rw_intr_mask) | 0x400);
  2196. + DMA_CONTINUE(np->dma_in_inst);
  2197. + }
  2198. +#endif
  2199. + /* Bring down the receiver. */
  2200. + crisv32_disable_rx_ints(np);
  2201. + crisv32_disconnect_eth_rx_dma(np);
  2202. +
  2203. + /* Stop DMA and ack possible ints. */
  2204. + DMA_STOP(np->dma_in_inst);
  2205. + ack_intr.in_eop = 1;
  2206. + REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
  2207. +
  2208. + crisv32_stop_receiver(np);
  2209. +
  2210. + /* Disable overrun interrupts while receive is shut off. */
  2211. + eth_intr_mask = REG_RD(eth, np->eth_inst, rw_intr_mask);
  2212. + eth_intr_mask.orun = regk_eth_no;
  2213. + REG_WR(eth, np->eth_inst, rw_intr_mask, eth_intr_mask);
  2214. + /* ACK overrun. */
  2215. + REG_WR_INT(eth, np->eth_inst, rw_ack_intr, 0x400);
  2216. +
  2217. + crisv32_eth_reset_rx_ring(dev);
  2218. + reset:
  2219. + /* TODO: if nr resets grows to high we should reboot. */
  2220. + if (resets++ > 0)
  2221. + printk("reset DMA %d.\n", resets);
  2222. +
  2223. + DMA_RESET(np->dma_in_inst);
  2224. + /* Wait for the channel to reset. */
  2225. + do {
  2226. + stat = REG_RD(dma, np->dma_in_inst, rw_stat);
  2227. + } while (stat.mode != regk_dma_rst);
  2228. +
  2229. + /* Now bring the rx path back up. */
  2230. + DMA_ENABLE(np->dma_in_inst);
  2231. + if (dma_wait_busy(np->dma_in_inst, 100))
  2232. + goto reset;
  2233. +
  2234. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  2235. +// DMA_WR_CMD(np->dma_in_inst, regk_dma_set_w_size2);
  2236. + dma_sc.cmd = (regk_dma_set_w_size2);
  2237. + REG_WR(dma, np->dma_in_inst, rw_stream_cmd, dma_sc);
  2238. + if (dma_wait_busy(np->dma_in_inst, 100))
  2239. + goto reset;
  2240. +#endif
  2241. +
  2242. +// DMA_START_CONTEXT(np->dma_in_inst, virt_to_phys(&np->ctxt_in));
  2243. + REG_WR_INT(dma, np->dma_in_inst, rw_group_down, (int)&np->ctxt_in);
  2244. +
  2245. +// DMA_WR_CMD(np->dma_in_inst, regk_dma_load_c);
  2246. + dma_sc.cmd = (regk_dma_load_c);
  2247. + REG_WR(dma, np->dma_in_inst, rw_stream_cmd, dma_sc);
  2248. + if (dma_wait_busy(np->dma_in_inst, 100))
  2249. + goto reset;
  2250. +
  2251. +// DMA_WR_CMD(np->dma_in_inst, regk_dma_load_d | regk_dma_burst);
  2252. + dma_sc.cmd = (regk_dma_load_d | regk_dma_burst);
  2253. + REG_WR(dma, np->dma_in_inst, rw_stream_cmd, dma_sc);
  2254. +
  2255. + if (dma_wait_busy(np->dma_in_inst, 100))
  2256. + goto reset;
  2257. +
  2258. + /* Now things get critical again. Don't give us any interrupts until
  2259. + the following sequence is complete. */
  2260. + DMA_CONTINUE(np->dma_in_inst);
  2261. + np->overrun_set = 0;
  2262. + crisv32_enable_rx_ints(np);
  2263. + crisv32_start_receiver(np);
  2264. +
  2265. + /* Reenable overrun interrupts when receive is started again. */
  2266. + eth_intr_mask = REG_RD(eth, np->eth_inst, rw_intr_mask);
  2267. + eth_intr_mask.orun = regk_eth_yes;
  2268. + REG_WR(eth, np->eth_inst, rw_intr_mask, eth_intr_mask);
  2269. +
  2270. + crisv32_connect_eth_rx_dma(np);
  2271. +}
  2272. +
  2273. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  2274. +static void
  2275. +crisv32_eth_restart_rx_dma(struct net_device* dev,
  2276. + struct crisv32_ethernet_local *np)
  2277. +{
  2278. + unsigned long flags;
  2279. +
  2280. + spin_lock_irqsave(&np->lock, flags);
  2281. + __crisv32_eth_restart_rx_dma(dev, np);
  2282. + spin_unlock_irqrestore(&np->lock, flags);
  2283. +}
  2284. +#endif
  2285. +
  2286. +/*
  2287. + * Is there work to do in the rx-path?
  2288. + */
  2289. +static inline int crisv32_has_rx_work(struct crisv32_ethernet_local *np,
  2290. + dma_descr_data *active)
  2291. +{
  2292. + int mw;
  2293. + mw = (active->in_eop && np->new_rx_package);
  2294. + return mw;
  2295. +}
  2296. +
  2297. +static void crisv32_eth_do_rx_recovery(struct net_device* dev,
  2298. + struct crisv32_ethernet_local *np)
  2299. +{
  2300. + unsigned long flags;
  2301. + static int r = 0;
  2302. +
  2303. + r++;
  2304. +
  2305. + /* Bring down the receiver. */
  2306. + spin_lock_irqsave(&np->lock, flags);
  2307. + if (!np->do_rx_recovery)
  2308. + goto done;
  2309. +
  2310. + napi_disable(&np->napi);
  2311. +
  2312. + np->rx_dma_timeouts++;
  2313. +
  2314. + __crisv32_eth_restart_rx_dma(dev, np);
  2315. +
  2316. + np->do_rx_recovery = 0;
  2317. +
  2318. + napi_enable(&np->napi);
  2319. + done:
  2320. + spin_unlock_irqrestore(&np->lock, flags);
  2321. +
  2322. + WARN_ON(r != 1);
  2323. + r--;
  2324. +}
  2325. +
  2326. +static void receive_timeout_work(struct work_struct* work)
  2327. +{
  2328. + struct dma_descr_data* descr;
  2329. + struct dma_descr_data* descr2;
  2330. + struct net_device* dev = crisv32_dev[0];
  2331. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2332. + reg_eth_r_intr intr_mask;
  2333. +
  2334. + descr = &np->active_rx_desc->descr;
  2335. + descr2 = phys_to_virt(REG_RD_INT(dma, np->dma_in_inst, rw_data));
  2336. +
  2337. + intr_mask = REG_RD(eth, np->eth_inst, r_intr);
  2338. +
  2339. + if (!np->overrun_set
  2340. + && !intr_mask.orun
  2341. + && !descr->in_eop
  2342. + && !descr2->in_eop)
  2343. + return;
  2344. +
  2345. + crisv32_eth_do_rx_recovery(dev, np);
  2346. +}
  2347. +
  2348. +static void receive_timeout(unsigned long arg)
  2349. +{
  2350. + struct net_device* dev = (struct net_device*)arg;
  2351. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2352. +
  2353. + np->do_rx_recovery++;
  2354. + schedule_work(&np->receive_work);
  2355. + mod_timer(&np->receive_timer, jiffies + 1*HZ);
  2356. +}
  2357. +
  2358. +static void transmit_timeout(unsigned long arg)
  2359. +{
  2360. + struct net_device* dev = (struct net_device*)arg;
  2361. + crisv32_eth_do_tx_recovery(dev);
  2362. +}
  2363. +
  2364. +/*
  2365. + * NAPI poll
  2366. + *
  2367. + * We are allowed to pull up to budget number of frames from the rx ring.
  2368. + * If we are done, remove us from the poll list and re-enable rx interrupts.
  2369. + * Always return number of pulled frames from the rx ring.
  2370. + */
  2371. +static int crisv32_eth_poll(struct napi_struct *napi, int budget)
  2372. +{
  2373. + struct crisv32_ethernet_local *np;
  2374. + int work_done = 0;
  2375. + int morework;
  2376. + int rx_bytes = 0;
  2377. + reg_dma_rw_ack_intr ack_intr = {0};
  2378. +
  2379. + np = container_of(napi, struct crisv32_ethernet_local, napi);
  2380. + crisv32_disable_eth_ints(np);
  2381. + np->napi_processing = 1;
  2382. + ack_intr.in_eop = 1;
  2383. +
  2384. + if (np->new_rx_package == 0) {
  2385. + /*
  2386. + * In the previous round we pulled a packet from the ring but
  2387. + * we didn't advance the ring due to hw DMA bug. Try to do it
  2388. + * now.
  2389. + */
  2390. + np->new_rx_package = 1;
  2391. + crisv32_eth_rx_ring_advance(np);
  2392. + }
  2393. +
  2394. + morework = crisv32_has_rx_work(np, &np->active_rx_desc->descr);
  2395. +
  2396. + /* See if tx needs attention. */
  2397. + crisv32_tx_complete(np);
  2398. +
  2399. + while (morework)
  2400. + {
  2401. + rx_bytes += crisv32_eth_receive_packet(np->dev);
  2402. + work_done++;
  2403. +
  2404. + /* Ack irq and restart rx dma */
  2405. + REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
  2406. + DMA_CONTINUE_DATA(np->dma_in_inst);
  2407. +
  2408. + if (unlikely(work_done >= budget))
  2409. + break;
  2410. +
  2411. + /* See if tx needs attention. */
  2412. + crisv32_tx_complete(np);
  2413. +
  2414. + morework = crisv32_has_rx_work(np, &np->active_rx_desc->descr);
  2415. + }
  2416. + crisv32_enable_eth_ints(np);
  2417. +
  2418. + if (!morework) {
  2419. + np->napi_processing = 0;
  2420. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  2421. + if (np->pending_overrun) {
  2422. + crisv32_eth_restart_rx_dma(np->dev, np);
  2423. + }
  2424. +#endif
  2425. + if (irqs_disabled())
  2426. + printk("WARNING: %s irqs disabled!\n", __func__);
  2427. +
  2428. + if (work_done < budget) {
  2429. + /* first mark as done, then enable irq's */
  2430. + napi_complete(napi);
  2431. + crisv32_enable_rx_ints(np);
  2432. + crisv32_enable_tx_ints(np);
  2433. + }
  2434. + }
  2435. + np->napi_processing = 0;
  2436. +
  2437. + np->stats.rx_bytes += rx_bytes;
  2438. + np->stats.rx_packets += work_done;
  2439. + update_rx_stats(np);
  2440. + return work_done;
  2441. +}
  2442. +
  2443. +/*
  2444. + * This function (i.e. hard_start_xmit) is protected from concurent calls by a
  2445. + * spinlock (xmit_lock) in the net_device structure.
  2446. + */
  2447. +static int
  2448. +crisv32_eth_send_packet(struct sk_buff *skb, struct net_device *dev)
  2449. +{
  2450. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2451. + unsigned char *buf = skb->data;
  2452. + unsigned long flags;
  2453. +
  2454. + /*
  2455. + * Need to disable irq to avoid updating pointer in interrupt while
  2456. + * sending packets.
  2457. + */
  2458. + spin_lock_irqsave(&np->lock, flags);
  2459. +
  2460. + np->active_tx_desc->skb = skb;
  2461. + crisv32_eth_hw_send_packet(buf, skb->len, np);
  2462. +
  2463. + /* Stop queue if full. */
  2464. + if (crisv32_eth_tx_ring_full(np))
  2465. + netif_stop_queue(dev);
  2466. +
  2467. + np->txpackets++;
  2468. + crisv32_eth_roll_tx_timer(np);
  2469. + spin_unlock_irqrestore(&np->lock, flags);
  2470. +
  2471. + spin_lock_irqsave(&np->leds->led_lock, flags);
  2472. + if (!np->leds->led_active && time_after(jiffies,
  2473. + np->leds->led_next_time)) {
  2474. + /* light the network leds depending on the current speed. */
  2475. + crisv32_set_network_leds(CRIS_LED_ACTIVITY, dev);
  2476. +
  2477. + /* Set the earliest time we may clear the LED */
  2478. + np->leds->led_next_time = jiffies + NET_FLASH_TIME;
  2479. + np->leds->led_active = 1;
  2480. + np->leds->clear_led_timer.data = (unsigned long) dev;
  2481. + mod_timer(&np->leds->clear_led_timer, jiffies + HZ/10);
  2482. + }
  2483. + spin_unlock_irqrestore(&np->leds->led_lock, flags);
  2484. +
  2485. + return 0;
  2486. +}
  2487. +
  2488. +
  2489. +static void
  2490. +crisv32_eth_hw_send_packet(unsigned char *buf, int length, void *priv)
  2491. +{
  2492. + struct crisv32_ethernet_local *np =
  2493. + (struct crisv32_ethernet_local *) priv;
  2494. +
  2495. + /* Configure the tx dma descriptor. */
  2496. + np->active_tx_desc->descr.buf = (unsigned char *)virt_to_phys(buf);
  2497. +
  2498. + np->active_tx_desc->descr.after = np->active_tx_desc->descr.buf +
  2499. + length;
  2500. + np->active_tx_desc->descr.intr = 1;
  2501. + np->active_tx_desc->descr.out_eop = 1;
  2502. +
  2503. + /* Move eol. */
  2504. + np->active_tx_desc->descr.eol = 1;
  2505. + flush_dma_descr(&np->active_tx_desc->descr, 1);
  2506. +
  2507. + if (np->sender_started)
  2508. + WARN_ON(!np->prev_tx_desc->descr.eol);
  2509. + np->prev_tx_desc->descr.eol = 0;
  2510. + flush_dma_descr(&np->prev_tx_desc->descr, 0);
  2511. +
  2512. + /* Update pointers. */
  2513. + np->prev_tx_desc = np->active_tx_desc;
  2514. + np->active_tx_desc = phys_to_virt((int)np->active_tx_desc->descr.next);
  2515. +
  2516. + /* Start DMA. */
  2517. + crisv32_start_dma_out(np);
  2518. +}
  2519. +
  2520. +static void crisv32_start_dma_out(struct crisv32_ethernet_local *np)
  2521. +{
  2522. + if (!np->sender_started) {
  2523. + /* Start DMA for the first time. */
  2524. + np->ctxt_out.saved_data =
  2525. + (void *)virt_to_phys(&np->prev_tx_desc->descr);
  2526. + np->ctxt_out.saved_data_buf = np->prev_tx_desc->descr.buf;
  2527. + WARN_ON(!np->ctxt_out.saved_data_buf);
  2528. +
  2529. + cris_flush_cache_range(&np->ctxt_out, sizeof np->ctxt_out);
  2530. + REG_WR(dma, np->dma_out_inst, rw_group_down,
  2531. + (int) virt_to_phys(&np->ctxt_out));
  2532. + DMA_WR_CMD(np->dma_out_inst, regk_dma_load_c);
  2533. + DMA_WR_CMD(np->dma_out_inst, regk_dma_load_d | regk_dma_burst);
  2534. + np->sender_started = 1;
  2535. + } else {
  2536. + DMA_CONTINUE_DATA(np->dma_out_inst);
  2537. + }
  2538. +}
  2539. +
  2540. +/*
  2541. + * Bring the transmitter back to life.
  2542. + */
  2543. +static void
  2544. +crisv32_eth_do_tx_recovery(struct net_device *dev)
  2545. +{
  2546. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2547. + reg_eth_rw_clr_err clr_err;
  2548. + reg_dma_rw_stat stat = {0};
  2549. + unsigned long flags;
  2550. + /* ACK urun and exc_col. */
  2551. + int ack_intr = 0x1800;
  2552. + int do_full;
  2553. +
  2554. + /* Give the tx recovery some time without link state polling. */
  2555. + if (!np->fixed_phy)
  2556. + mod_timer(&np->speed_timer, jiffies + 4 * HZ);
  2557. +
  2558. + np->tx_dma_restarts++;
  2559. +
  2560. + spin_lock_irqsave(&np->lock, flags);
  2561. +
  2562. + do_full = 1;
  2563. + update_tx_stats(np);
  2564. +
  2565. + /* Cancel ongoing frame. */
  2566. + crisv32_eth_tx_cancel_frame(np);
  2567. +
  2568. + /* In case TR 125 just hit us. */
  2569. + DMA_WR_CMD(np->dma_out_inst, regk_dma_ack_pkt);
  2570. + dma_wait_busy(np->dma_out_inst, 100);
  2571. +
  2572. + /* At this point, the transmit block should be idle or waiting for us
  2573. + to clear the excessive collision error. Let's reset the DMA. */
  2574. + DMA_STOP(np->dma_out_inst);
  2575. +
  2576. + crisv32_disconnect_eth_tx_dma(np);
  2577. +
  2578. + /* Eat from the tx ring. */
  2579. + _crisv32_tx_ring_advance(np, 1);
  2580. + np->do_tx_recovery++;
  2581. +
  2582. + DMA_RESET(np->dma_out_inst);
  2583. + do {
  2584. + stat = REG_RD(dma, np->dma_out_inst, rw_stat);
  2585. + } while (stat.mode != regk_dma_rst);
  2586. +
  2587. + /* Next packet will restart output DMA. */
  2588. + np->sender_started = 0;
  2589. +
  2590. + crisv32_enable_tx_ints(np);
  2591. +
  2592. + DMA_ENABLE(np->dma_out_inst);
  2593. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  2594. + DMA_WR_CMD(np->dma_out_inst, regk_dma_set_w_size4);
  2595. +#endif
  2596. + DMA_CONTINUE(np->dma_out_inst);
  2597. +
  2598. + /* Clear pending errors. */
  2599. + REG_WR_INT(eth, np->eth_inst, rw_ack_intr, ack_intr);
  2600. + clr_err.clr = 1;
  2601. + REG_WR(eth, np->eth_inst, rw_clr_err, clr_err);
  2602. +
  2603. + /* Do a full reset of the MAC block. */
  2604. + if (do_full) {
  2605. + np->tx_mac_resets++;
  2606. + crisv32_eth_reset(np);
  2607. + }
  2608. +
  2609. + crisv32_connect_eth_tx_dma(np);
  2610. +
  2611. + if (np->txpackets) {
  2612. + WARN_ON(!np->catch_tx_desc->skb);
  2613. + np->catch_tx_desc->descr.intr = 1;
  2614. + np->catch_tx_desc->descr.out_eop = 1;
  2615. +
  2616. + /* Start DMA for the first time. */
  2617. + np->ctxt_out.saved_data =
  2618. + (void *)virt_to_phys(&np->catch_tx_desc->descr);
  2619. + np->ctxt_out.saved_data_buf = np->catch_tx_desc->descr.buf;
  2620. + WARN_ON(!np->ctxt_out.saved_data_buf);
  2621. + flush_dma_descr(&np->catch_tx_desc->descr, 0);
  2622. + cris_flush_cache_range(&np->ctxt_out, sizeof np->ctxt_out);
  2623. +
  2624. + REG_WR(dma, np->dma_out_inst, rw_group_down,
  2625. + (int) virt_to_phys(&np->ctxt_out));
  2626. + DMA_WR_CMD(np->dma_out_inst, regk_dma_load_c);
  2627. + DMA_WR_CMD(np->dma_out_inst, regk_dma_load_d | regk_dma_burst);
  2628. + crisv32_eth_roll_tx_timer(np);
  2629. + np->sender_started = 1;
  2630. + }
  2631. +
  2632. + if (np->txpackets && crisv32_eth_tx_ring_full(np))
  2633. + netif_stop_queue(dev);
  2634. + else
  2635. + netif_wake_queue(dev);
  2636. +
  2637. + spin_unlock_irqrestore(&np->lock, flags);
  2638. +}
  2639. +
  2640. +/*
  2641. + * Set or clear the multicast filter for this adaptor.
  2642. + * num_addrs == -1 Promiscuous mode, receive all packets
  2643. + * num_addrs == 0 Normal mode, clear multicast list
  2644. + * num_addrs > 0 Multicast mode, receive normal and MC packets,
  2645. + * and do best-effort filtering.
  2646. + */
  2647. +static void crisv32_eth_set_rx_mode(struct net_device *dev)
  2648. +{
  2649. + int num_addr = netdev_mc_count(dev);
  2650. + unsigned long int lo_bits;
  2651. + unsigned long int hi_bits;
  2652. + reg_eth_rw_rec_ctrl rec_ctrl = {0};
  2653. + reg_eth_rw_ga_lo ga_lo = {0};
  2654. + reg_eth_rw_ga_hi ga_hi = {0};
  2655. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2656. +
  2657. + if (dev->flags & IFF_PROMISC) {
  2658. + /* Promiscuous mode. */
  2659. + lo_bits = 0xfffffffful;
  2660. + hi_bits = 0xfffffffful;
  2661. +
  2662. + /* Enable individual receive. */
  2663. + rec_ctrl = (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst,
  2664. + rw_rec_ctrl);
  2665. + rec_ctrl.individual = regk_eth_yes;
  2666. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  2667. + } else if (dev->flags & IFF_ALLMULTI) {
  2668. + /* Enable all multicasts. */
  2669. + lo_bits = 0xfffffffful;
  2670. + hi_bits = 0xfffffffful;
  2671. +
  2672. + /* Disable individual receive */
  2673. + rec_ctrl =
  2674. + (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst, rw_rec_ctrl);
  2675. + rec_ctrl.individual = regk_eth_no;
  2676. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  2677. + } else if (num_addr == 0) {
  2678. + /* Normal, clear the mc list. */
  2679. + lo_bits = 0x00000000ul;
  2680. + hi_bits = 0x00000000ul;
  2681. +
  2682. + /* Disable individual receive */
  2683. + rec_ctrl =
  2684. + (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst, rw_rec_ctrl);
  2685. + rec_ctrl.individual = regk_eth_no;
  2686. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  2687. + } else {
  2688. + /* MC mode, receive normal and MC packets. */
  2689. + char hash_ix;
  2690. + struct netdev_hw_addr *ha;
  2691. + char *baddr;
  2692. + lo_bits = 0x00000000ul;
  2693. + hi_bits = 0x00000000ul;
  2694. +
  2695. + netdev_for_each_mc_addr(ha, dev) {
  2696. + /* Calculate the hash index for the GA registers. */
  2697. + hash_ix = 0;
  2698. + baddr = ha->addr;
  2699. + hash_ix ^= (*baddr) & 0x3f;
  2700. + hash_ix ^= ((*baddr) >> 6) & 0x03;
  2701. + ++baddr;
  2702. + hash_ix ^= ((*baddr) << 2) & 0x03c;
  2703. + hash_ix ^= ((*baddr) >> 4) & 0xf;
  2704. + ++baddr;
  2705. + hash_ix ^= ((*baddr) << 4) & 0x30;
  2706. + hash_ix ^= ((*baddr) >> 2) & 0x3f;
  2707. + ++baddr;
  2708. + hash_ix ^= (*baddr) & 0x3f;
  2709. + hash_ix ^= ((*baddr) >> 6) & 0x03;
  2710. + ++baddr;
  2711. + hash_ix ^= ((*baddr) << 2) & 0x03c;
  2712. + hash_ix ^= ((*baddr) >> 4) & 0xf;
  2713. + ++baddr;
  2714. + hash_ix ^= ((*baddr) << 4) & 0x30;
  2715. + hash_ix ^= ((*baddr) >> 2) & 0x3f;
  2716. +
  2717. + hash_ix &= 0x3f;
  2718. +
  2719. + if (hash_ix > 32)
  2720. + hi_bits |= (1 << (hash_ix - 32));
  2721. + else
  2722. + lo_bits |= (1 << hash_ix);
  2723. + }
  2724. +
  2725. + /* Disable individual receive. */
  2726. + rec_ctrl =
  2727. + (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst, rw_rec_ctrl);
  2728. + rec_ctrl.individual = regk_eth_no;
  2729. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  2730. + }
  2731. +
  2732. + ga_lo.table = (unsigned int) lo_bits;
  2733. + ga_hi.table = (unsigned int) hi_bits;
  2734. +
  2735. + REG_WR(eth, np->eth_inst, rw_ga_lo, ga_lo);
  2736. + REG_WR(eth, np->eth_inst, rw_ga_hi, ga_hi);
  2737. +}
  2738. +
  2739. +static int
  2740. +crisv32_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  2741. +{
  2742. + struct mii_ioctl_data *data = if_mii(ifr);
  2743. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2744. + int old_autoneg;
  2745. + int rc = 0;
  2746. +
  2747. + spin_lock(&np->lock); /* Preempt protection */
  2748. + switch (cmd) {
  2749. + case SET_ETH_ENABLE_LEDS:
  2750. + np->use_leds = 1;
  2751. + break;
  2752. + case SET_ETH_DISABLE_LEDS:
  2753. + np->use_leds = 0;
  2754. + break;
  2755. + case SET_ETH_AUTONEG:
  2756. + old_autoneg = np->autoneg_normal;
  2757. + np->autoneg_normal = *(int*)data;
  2758. + if (np->autoneg_normal != old_autoneg)
  2759. + crisv32_eth_negotiate(dev);
  2760. + break;
  2761. + default:
  2762. + rc = generic_mii_ioctl(&np->mii_if,
  2763. + if_mii(ifr), cmd, NULL);
  2764. + break;
  2765. + }
  2766. + spin_unlock(&np->lock);
  2767. + return rc;
  2768. +}
  2769. +
  2770. +static int crisv32_eth_get_settings(struct net_device *dev,
  2771. + struct ethtool_cmd *cmd)
  2772. +{
  2773. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2774. + int err;
  2775. +
  2776. + spin_lock_irq(&np->lock);
  2777. + err = mii_ethtool_gset(&np->mii_if, cmd);
  2778. + spin_unlock_irq(&np->lock);
  2779. +
  2780. + /* The PHY may support 1000baseT, but the EtraxFS does not. */
  2781. + cmd->supported &= ~(SUPPORTED_1000baseT_Half
  2782. + | SUPPORTED_1000baseT_Full);
  2783. + return err;
  2784. +}
  2785. +
  2786. +static int crisv32_eth_set_settings(struct net_device *dev,
  2787. + struct ethtool_cmd *ecmd)
  2788. +{
  2789. + if (ecmd->autoneg == AUTONEG_ENABLE) {
  2790. + crisv32_eth_set_duplex(dev, autoneg);
  2791. + crisv32_eth_set_speed(dev, 0);
  2792. + } else {
  2793. + crisv32_eth_set_duplex(dev, ecmd->duplex);
  2794. + crisv32_eth_set_speed(dev, ecmd->speed);
  2795. + }
  2796. +
  2797. + return 0;
  2798. +}
  2799. +
  2800. +static void crisv32_eth_get_drvinfo(struct net_device *dev,
  2801. + struct ethtool_drvinfo *info)
  2802. +{
  2803. +#ifdef CONFIG_ETRAXFS
  2804. + strncpy(info->driver, "ETRAX FS", sizeof(info->driver) - 1);
  2805. +#else
  2806. + strncpy(info->driver, "ARTPEC-3", sizeof(info->driver) - 1);
  2807. +#endif
  2808. + strncpy(info->version, "$Revision: 1.197 $", sizeof(info->version) - 1);
  2809. + strncpy(info->fw_version, "N/A", sizeof(info->fw_version) - 1);
  2810. + strncpy(info->bus_info, "N/A", sizeof(info->bus_info) - 1);
  2811. +}
  2812. +
  2813. +static int crisv32_eth_get_ethtool_sset_count(struct net_device *dev,
  2814. + int stringset)
  2815. +{
  2816. + if (stringset != ETH_SS_STATS)
  2817. + return -EINVAL;
  2818. +
  2819. + return ARRAY_SIZE(ethtool_stats_keys);
  2820. +}
  2821. +
  2822. +static void crisv32_eth_get_ethtool_stats(struct net_device *dev,
  2823. + struct ethtool_stats *stats,
  2824. + u64 *data)
  2825. +{
  2826. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2827. +
  2828. + data[0] = np->tx_dma_restarts;
  2829. + data[1] = np->tx_mac_resets;
  2830. + data[2] = np->rx_dma_restarts;
  2831. + data[3] = np->rx_dma_timeouts;
  2832. + data[4] = np->rx_restarts_dropped;
  2833. +}
  2834. +
  2835. +static void crisv32_eth_get_strings(struct net_device *dev,
  2836. + u32 stringset, u8 *data)
  2837. +{
  2838. + switch (stringset) {
  2839. + case ETH_SS_STATS:
  2840. + memcpy(data, &ethtool_stats_keys,
  2841. + sizeof(ethtool_stats_keys));
  2842. + break;
  2843. + default:
  2844. + WARN_ON(1);
  2845. + break;
  2846. + }
  2847. +}
  2848. +
  2849. +static int crisv32_eth_nway_reset(struct net_device *dev)
  2850. +{
  2851. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2852. +
  2853. + if (np->current_duplex == autoneg && np->current_speed_selection == 0)
  2854. + crisv32_eth_negotiate(dev);
  2855. + return 0;
  2856. +}
  2857. +/* The FS/A3 ethernet block has 23 32-bit config registers. */
  2858. +/* plus 2 dma_descr_context */
  2859. +/* plus 2 sets of ring pointers (active, prev, last) */
  2860. +/* plus 2 sets of DMA registers 40*4 bytes = 0xA0 */
  2861. +#define ETRAX_ETH_REGDUMP_LEN (23 * 4 + 2 * sizeof (dma_descr_context) + 2*3*4 + 2*0xA0)
  2862. +static int crisv32_eth_get_regs_len(struct net_device *dev)
  2863. +{
  2864. + return ETRAX_ETH_REGDUMP_LEN;
  2865. +}
  2866. +
  2867. +static void crisv32_eth_get_regs(struct net_device *dev,
  2868. + struct ethtool_regs *regs, void *_p)
  2869. +{
  2870. + u32 *p = _p;
  2871. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2872. + int i;
  2873. +
  2874. + /* Let's call this major version 0, minor version 1 with some
  2875. + * undecided field separation in the version data. Previously
  2876. + * only the eth regs were dumped (version=0: maj 0, min 0).*/
  2877. + regs->version = 1;
  2878. + memset(p, 0, ETRAX_ETH_REGDUMP_LEN);
  2879. +
  2880. +#define GET_REG32_LOOP(base, len) \
  2881. + do { \
  2882. + for (i = 0; i < len; i += 4) \
  2883. + *(p)++ = REG_READ(u32, (base) + i); \
  2884. + } while (0)
  2885. +
  2886. + GET_REG32_LOOP(np->eth_inst, 0x30);
  2887. + /* Do not dump registers with read side effects. */
  2888. + GET_REG32_LOOP(np->eth_inst + 0x34, 1);
  2889. + GET_REG32_LOOP(np->eth_inst + 0x3c, 1);
  2890. + GET_REG32_LOOP(np->eth_inst + 0x44, 0x5c - 0x44);
  2891. +
  2892. +
  2893. + memcpy(p, &np->ctxt_out, sizeof (dma_descr_context));
  2894. + p += sizeof (dma_descr_context)/4;
  2895. + *(p++) = (u32) np->active_tx_desc;
  2896. + *(p++) = (u32) np->prev_tx_desc;
  2897. + *(p++) = (u32) np->catch_tx_desc;
  2898. +
  2899. + GET_REG32_LOOP(np->dma_out_inst, 0xa0);
  2900. +
  2901. + memcpy(p, &np->ctxt_in, sizeof (dma_descr_context));
  2902. + p += sizeof (dma_descr_context)/4;
  2903. + *(p++) = (u32)np->active_rx_desc;
  2904. + *(p++) = (u32)np->prev_rx_desc;
  2905. + *(p++) = (u32)np->last_rx_desc;
  2906. +
  2907. + GET_REG32_LOOP(np->dma_in_inst, 0xa0);
  2908. +#undef GET_REG32_LOOP
  2909. +}
  2910. +
  2911. +static struct ethtool_ops crisv32_ethtool_ops = {
  2912. + .get_settings = crisv32_eth_get_settings,
  2913. + .set_settings = crisv32_eth_set_settings,
  2914. + .get_drvinfo = crisv32_eth_get_drvinfo,
  2915. + .get_regs_len = crisv32_eth_get_regs_len,
  2916. + .get_regs = crisv32_eth_get_regs,
  2917. + .nway_reset = crisv32_eth_nway_reset,
  2918. + .get_link = ethtool_op_get_link,
  2919. + .get_strings = crisv32_eth_get_strings,
  2920. + .get_ethtool_stats = crisv32_eth_get_ethtool_stats,
  2921. + .get_sset_count = crisv32_eth_get_ethtool_sset_count
  2922. +};
  2923. +
  2924. +/* Is this function really needed? Use ethtool instead? */
  2925. +static int crisv32_eth_set_config(struct net_device *dev, struct ifmap *map)
  2926. +{
  2927. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2928. +
  2929. + spin_lock(&np->lock); /* Preempt protection */
  2930. +
  2931. + switch (map->port) {
  2932. + case IF_PORT_UNKNOWN:
  2933. + /* Use autoneg */
  2934. + crisv32_eth_set_speed(dev, 0);
  2935. + crisv32_eth_set_duplex(dev, autoneg);
  2936. + break;
  2937. + case IF_PORT_10BASET:
  2938. + crisv32_eth_set_speed(dev, 10);
  2939. + crisv32_eth_set_duplex(dev, autoneg);
  2940. + break;
  2941. + case IF_PORT_100BASET:
  2942. + case IF_PORT_100BASETX:
  2943. + crisv32_eth_set_speed(dev, 100);
  2944. + crisv32_eth_set_duplex(dev, autoneg);
  2945. + break;
  2946. + case IF_PORT_100BASEFX:
  2947. + case IF_PORT_10BASE2:
  2948. + case IF_PORT_AUI:
  2949. + spin_unlock(&np->lock);
  2950. + return -EOPNOTSUPP;
  2951. + break;
  2952. + default:
  2953. + printk(KERN_ERR "%s: Invalid media selected",
  2954. + dev->name);
  2955. + spin_unlock(&np->lock);
  2956. + return -EINVAL;
  2957. + }
  2958. + spin_unlock(&np->lock);
  2959. + return 0;
  2960. +}
  2961. +
  2962. +static void crisv32_eth_negotiate(struct net_device *dev)
  2963. +{
  2964. + unsigned short data;
  2965. + unsigned short ctrl1000;
  2966. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  2967. +
  2968. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_ADVERTISE);
  2969. + ctrl1000 = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  2970. + MII_CTRL1000);
  2971. +
  2972. + /* Make all capabilities available */
  2973. + data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
  2974. + ADVERTISE_100HALF | ADVERTISE_100FULL;
  2975. + ctrl1000 |= ADVERTISE_1000HALF | ADVERTISE_1000FULL;
  2976. +
  2977. + /* Remove the speed capabilities that we that do not want */
  2978. + switch (np->current_speed_selection) {
  2979. + case 10 :
  2980. + data &= ~(ADVERTISE_100HALF | ADVERTISE_100FULL);
  2981. + ctrl1000 &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
  2982. + break;
  2983. + case 100 :
  2984. + data &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL);
  2985. + ctrl1000 &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
  2986. + break;
  2987. + case 1000 :
  2988. + data &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2989. + ADVERTISE_100HALF | ADVERTISE_100FULL);
  2990. + break;
  2991. + }
  2992. +
  2993. + /* Remove the duplex capabilites that we do not want */
  2994. + if (np->current_duplex == full) {
  2995. + data &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
  2996. + ctrl1000 &= ~(ADVERTISE_1000HALF);
  2997. + }
  2998. + else if (np->current_duplex == half) {
  2999. + data &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
  3000. + ctrl1000 &= ~(ADVERTISE_1000FULL);
  3001. + }
  3002. +
  3003. + crisv32_eth_set_mdio_reg(dev, np->mii_if.phy_id, MII_ADVERTISE, data);
  3004. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  3005. + crisv32_eth_set_mdio_reg(dev, np->mii_if.phy_id,
  3006. + MII_CTRL1000, ctrl1000);
  3007. +#endif
  3008. +
  3009. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR);
  3010. + if (np->autoneg_normal) {
  3011. + /* Renegotiate with link partner */
  3012. + data |= BMCR_ANENABLE | BMCR_ANRESTART;
  3013. + } else {
  3014. + /* Don't negitiate speed or duplex */
  3015. + data &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
  3016. +
  3017. + /* Set speed and duplex static */
  3018. + if (np->current_speed_selection == 10) {
  3019. + data &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
  3020. + }
  3021. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  3022. + else if (np->current_speed_selection == 1000) {
  3023. + data &= ~BMCR_SPEED100;
  3024. + data |= BMCR_SPEED1000;
  3025. + }
  3026. +#endif
  3027. + else {
  3028. + data |= BMCR_SPEED100;
  3029. + data &= ~BMCR_SPEED1000;
  3030. + }
  3031. +
  3032. + if (np->current_duplex != full) {
  3033. + data &= ~BMCR_FULLDPLX;
  3034. + } else {
  3035. + data |= BMCR_FULLDPLX;
  3036. + }
  3037. + }
  3038. + crisv32_eth_set_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR, data);
  3039. +}
  3040. +
  3041. +static void crisv32_eth_check_speed(unsigned long idev)
  3042. +{
  3043. +#ifndef CONFIG_ETRAX_NO_PHY
  3044. + static int led_initiated = 0;
  3045. + struct net_device *dev = (struct net_device *) idev;
  3046. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3047. +
  3048. + unsigned long data;
  3049. + int old_speed;
  3050. + unsigned long flags;
  3051. +
  3052. + BUG_ON(!np);
  3053. + BUG_ON(!np->transceiver);
  3054. +
  3055. + spin_lock(&np->transceiver_lock);
  3056. +
  3057. + old_speed = np->current_speed;
  3058. +
  3059. + /* Do a fake read. This is needed for DM9161, otherwise the link will
  3060. + * go up and down all the time.
  3061. + */
  3062. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMSR);
  3063. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMSR);
  3064. +
  3065. + if (!(data & BMSR_LSTATUS))
  3066. + np->current_speed = 0;
  3067. + else
  3068. + np->transceiver->check_speed(dev);
  3069. +
  3070. + spin_lock_irqsave(&np->leds->led_lock, flags);
  3071. + if ((old_speed != np->current_speed) || !led_initiated) {
  3072. + led_initiated = 1;
  3073. + np->leds->clear_led_timer.data = (unsigned long) dev;
  3074. + if (np->current_speed) {
  3075. + if (!np->link)
  3076. + netif_carrier_on(dev);
  3077. + crisv32_set_network_leds(CRIS_LED_LINK, dev);
  3078. + np->link = 1;
  3079. + } else {
  3080. + if (np->link)
  3081. + netif_carrier_off(dev);
  3082. + crisv32_set_network_leds(CRIS_LED_NOLINK, dev);
  3083. + np->link = 0;
  3084. + }
  3085. + }
  3086. + spin_unlock_irqrestore(&np->leds->led_lock, flags);
  3087. +
  3088. + /* Reinitialize the timer. */
  3089. + np->speed_timer.expires = jiffies + NET_LINK_UP_CHECK_INTERVAL;
  3090. + add_timer(&np->speed_timer);
  3091. +
  3092. + spin_unlock(&np->transceiver_lock);
  3093. +#endif
  3094. +}
  3095. +
  3096. +static void crisv32_eth_set_speed(struct net_device *dev, unsigned long speed)
  3097. +{
  3098. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3099. +
  3100. + spin_lock(&np->transceiver_lock);
  3101. + if (np->current_speed_selection != speed) {
  3102. + np->current_speed_selection = speed;
  3103. + crisv32_eth_negotiate(dev);
  3104. + }
  3105. + spin_unlock(&np->transceiver_lock);
  3106. +}
  3107. +
  3108. +static void crisv32_eth_check_duplex(unsigned long idev)
  3109. +{
  3110. +#ifndef CONFIG_ETRAX_NO_PHY
  3111. + struct net_device *dev = (struct net_device *) idev;
  3112. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3113. + reg_eth_rw_rec_ctrl rec_ctrl;
  3114. + int old_duplex = np->full_duplex;
  3115. +
  3116. + np->transceiver->check_duplex(dev);
  3117. +
  3118. + if (old_duplex != np->full_duplex) {
  3119. + /* Duplex changed. */
  3120. + rec_ctrl = (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst,
  3121. + rw_rec_ctrl);
  3122. + rec_ctrl.duplex = np->full_duplex;
  3123. + REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
  3124. + }
  3125. +
  3126. + /* Reinitialize the timer. */
  3127. + np->duplex_timer.expires = jiffies + NET_DUPLEX_CHECK_INTERVAL;
  3128. + add_timer(&np->duplex_timer);
  3129. +#endif
  3130. +}
  3131. +
  3132. +static void
  3133. +crisv32_eth_set_duplex(struct net_device *dev, enum duplex new_duplex)
  3134. +{
  3135. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3136. + spin_lock(&np->transceiver_lock);
  3137. + if (np->current_duplex != new_duplex) {
  3138. + np->current_duplex = new_duplex;
  3139. + crisv32_eth_negotiate(dev);
  3140. + }
  3141. + spin_unlock(&np->transceiver_lock);
  3142. +}
  3143. +
  3144. +static int crisv32_eth_probe_transceiver(struct net_device *dev)
  3145. +{
  3146. +#ifndef CONFIG_ETRAX_NO_PHY
  3147. + unsigned int phyid_high;
  3148. + unsigned int phyid_low;
  3149. + unsigned int oui;
  3150. + struct transceiver_ops *ops = NULL;
  3151. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3152. +
  3153. + /* Probe MDIO physical address. */
  3154. + for (np->mii_if.phy_id = 0;
  3155. + np->mii_if.phy_id <= 31; np->mii_if.phy_id++) {
  3156. + if (crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMSR)
  3157. + != 0xffff)
  3158. + break;
  3159. + }
  3160. +
  3161. + if (np->mii_if.phy_id == 32)
  3162. + return -ENODEV;
  3163. +
  3164. + /* Get manufacturer. */
  3165. + phyid_high = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3166. + MII_PHYSID1);
  3167. + phyid_low = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3168. + MII_PHYSID2);
  3169. +
  3170. + oui = (phyid_high << 6) | (phyid_low >> 10);
  3171. +
  3172. + for (ops = &transceivers[0]; ops->oui; ops++) {
  3173. + if (ops->oui == oui)
  3174. + break;
  3175. + }
  3176. +
  3177. + np->transceiver = ops;
  3178. +
  3179. + if (oui == DM9161_OUI) {
  3180. + /* Do not bypass the scrambler/descrambler, this is needed
  3181. + * to make 10Mbit work.
  3182. + */
  3183. + crisv32_eth_set_mdio_reg(dev, np->mii_if.phy_id,
  3184. + MII_DM9161_SCR,MII_DM9161_SCR_INIT);
  3185. + /* Clear 10BTCSR to default */
  3186. + crisv32_eth_set_mdio_reg(dev, np->mii_if.phy_id,
  3187. + MII_DM9161_10BTCSR,
  3188. + MII_DM9161_10BTCSR_INIT);
  3189. + }
  3190. + return 0;
  3191. +#else
  3192. + return -ENODEV;
  3193. +#endif
  3194. +}
  3195. +
  3196. +#ifndef CONFIG_ETRAX_NO_PHY
  3197. +static void generic_check_speed(struct net_device *dev)
  3198. +{
  3199. + unsigned long data;
  3200. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3201. +
  3202. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_ADVERTISE);
  3203. + if ((data & ADVERTISE_100FULL) ||
  3204. + (data & ADVERTISE_100HALF))
  3205. + np->current_speed = 100;
  3206. + else
  3207. + np->current_speed = 10;
  3208. +}
  3209. +
  3210. +static void generic_check_duplex(struct net_device *dev)
  3211. +{
  3212. + unsigned long data;
  3213. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3214. +
  3215. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_ADVERTISE);
  3216. + if ((data & ADVERTISE_10FULL) ||
  3217. + (data & ADVERTISE_100FULL))
  3218. + np->full_duplex = 1;
  3219. + else
  3220. + np->full_duplex = 0;
  3221. +}
  3222. +
  3223. +static void broadcom_check_speed(struct net_device *dev)
  3224. +{
  3225. + unsigned long data;
  3226. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3227. +
  3228. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3229. + MDIO_AUX_CTRL_STATUS_REG);
  3230. + np->current_speed = (data & MDIO_BC_SPEED ? 100 : 10);
  3231. +}
  3232. +
  3233. +static void broadcom_check_duplex(struct net_device *dev)
  3234. +{
  3235. + unsigned long data;
  3236. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3237. +
  3238. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3239. + MDIO_AUX_CTRL_STATUS_REG);
  3240. + np->full_duplex = (data & MDIO_BC_FULL_DUPLEX_IND) ? 1 : 0;
  3241. +}
  3242. +
  3243. +static void tdk_check_speed(struct net_device *dev)
  3244. +{
  3245. + unsigned long data;
  3246. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3247. +
  3248. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3249. + MDIO_TDK_DIAGNOSTIC_REG);
  3250. + np->current_speed = (data & MDIO_TDK_DIAGNOSTIC_RATE ? 100 : 10);
  3251. +}
  3252. +
  3253. +static void tdk_check_duplex(struct net_device *dev)
  3254. +{
  3255. + unsigned long data;
  3256. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3257. +
  3258. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3259. + MDIO_TDK_DIAGNOSTIC_REG);
  3260. + np->full_duplex = (data & MDIO_TDK_DIAGNOSTIC_DPLX) ? 1 : 0;
  3261. +
  3262. +}
  3263. +
  3264. +static void intel_check_speed(struct net_device *dev)
  3265. +{
  3266. + unsigned long data;
  3267. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3268. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3269. + MDIO_INT_STATUS_REG_2);
  3270. + np->current_speed = (data & MDIO_INT_SPEED ? 100 : 10);
  3271. +}
  3272. +
  3273. +static void intel_check_duplex(struct net_device *dev)
  3274. +{
  3275. + unsigned long data;
  3276. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3277. +
  3278. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3279. + MDIO_INT_STATUS_REG_2);
  3280. + np->full_duplex = (data & MDIO_INT_FULL_DUPLEX_IND) ? 1 : 0;
  3281. +}
  3282. +
  3283. +static void national_check_speed(struct net_device *dev)
  3284. +{
  3285. + unsigned long data;
  3286. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3287. +
  3288. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3289. + MDIO_NAT_LINK_AN_REG);
  3290. + if (data & MDIO_NAT_1000)
  3291. + np->current_speed = 1000;
  3292. + else if (data & MDIO_NAT_100)
  3293. + np->current_speed = 100;
  3294. + else
  3295. + np->current_speed = 10;
  3296. +}
  3297. +
  3298. +static void national_check_duplex(struct net_device *dev)
  3299. +{
  3300. + unsigned long data;
  3301. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3302. +
  3303. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3304. + MDIO_NAT_LINK_AN_REG);
  3305. + if (data & MDIO_NAT_FULL_DUPLEX_IND)
  3306. + np->full_duplex = 1;
  3307. + else
  3308. + np->full_duplex = 0;
  3309. +}
  3310. +
  3311. +static void vitesse_check_speed(struct net_device *dev)
  3312. +{
  3313. + unsigned long data;
  3314. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3315. +
  3316. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3317. + MDIO_VIT_AUX_STAT);
  3318. + if ((data & 0x18) == MDIO_VIT_1000)
  3319. + np->current_speed = 1000;
  3320. + else if ((data & 0x18) == MDIO_VIT_100)
  3321. + np->current_speed = 100;
  3322. + else
  3323. + np->current_speed = 10;
  3324. +}
  3325. +
  3326. +static void vitesse_check_duplex(struct net_device *dev)
  3327. +{
  3328. + unsigned long data;
  3329. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3330. +
  3331. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3332. + MDIO_VIT_AUX_STAT);
  3333. + if (data & 0x20)
  3334. + np->full_duplex = 1;
  3335. + else
  3336. + np->full_duplex = 0;
  3337. +}
  3338. +
  3339. +static void davicom_check_speed(struct net_device *dev)
  3340. +{
  3341. + unsigned long data;
  3342. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3343. +
  3344. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR);
  3345. + np->current_speed = (data & BMCR_SPEED100) ? 100 : 10;
  3346. +}
  3347. +
  3348. +static void davicom_check_duplex(struct net_device *dev)
  3349. +{
  3350. + unsigned long data;
  3351. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3352. +
  3353. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR);
  3354. + np->full_duplex = (data & BMCR_FULLDPLX) ? 1 : 0;
  3355. +}
  3356. +#endif
  3357. +
  3358. +#if 0
  3359. +static void crisv32_eth_reset_tranceiver(struct net_device *dev)
  3360. +{
  3361. + int i;
  3362. + unsigned short cmd;
  3363. + unsigned short data;
  3364. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3365. +
  3366. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR);
  3367. +
  3368. + cmd = (MDIO_START << 14)
  3369. + | (MDIO_WRITE << 12)
  3370. + | (np->mii_if.phy_id << 7)
  3371. + | (MII_BMCR << 2);
  3372. +
  3373. + crisv32_eth_send_mdio_cmd(dev, cmd, 1);
  3374. +
  3375. + data |= 0x8000;
  3376. +
  3377. + /* Magic value is number of bits. */
  3378. + for (i = 15; i >= 0; i--)
  3379. + crisv32_eth_send_mdio_bit(dev, GET_BIT(i, data));
  3380. +}
  3381. +#endif
  3382. +
  3383. +static int
  3384. +crisv32_eth_get_mdio_reg(struct net_device *dev, int phyid, int reg_num)
  3385. +{
  3386. + int i;
  3387. + unsigned short cmd; /* Data to be sent on MDIO port. */
  3388. + unsigned short data; /* Data read from MDIO. */
  3389. +
  3390. +#ifdef CONFIG_ETRAX_NO_PHY
  3391. + return 0;
  3392. +#endif
  3393. +
  3394. + /* Start of frame, OP Code, Physical Address, Register Address. */
  3395. + cmd = (MDIO_START << 14)
  3396. + | (MDIO_READ << 12)
  3397. + | (phyid << 7)
  3398. + | (reg_num << 2);
  3399. +
  3400. + crisv32_eth_send_mdio_cmd(dev, cmd, 0);
  3401. +
  3402. + data = 0;
  3403. +
  3404. + /* Receive data. Magic value is number of bits. */
  3405. + for (i = 15; i >= 0; i--)
  3406. + data |= (crisv32_eth_receive_mdio_bit(dev) << i);
  3407. +
  3408. + return data;
  3409. +}
  3410. +
  3411. +static void
  3412. +crisv32_eth_set_mdio_reg(struct net_device *dev, int phyid, int reg, int value)
  3413. +{
  3414. + int bitCounter;
  3415. + unsigned short cmd;
  3416. +
  3417. +#ifdef CONFIG_ETRAX_NO_PHY
  3418. + return;
  3419. +#endif
  3420. + cmd = (MDIO_START << 14)
  3421. + | (MDIO_WRITE << 12)
  3422. + | (phyid << 7)
  3423. + | (reg << 2);
  3424. +
  3425. + crisv32_eth_send_mdio_cmd(dev, cmd, 1);
  3426. +
  3427. + /* Data... */
  3428. + for (bitCounter=15; bitCounter>=0 ; bitCounter--) {
  3429. + crisv32_eth_send_mdio_bit(dev, GET_BIT(bitCounter, value));
  3430. + }
  3431. +}
  3432. +
  3433. +static void
  3434. +crisv32_eth_send_mdio_cmd(struct net_device *dev, unsigned short cmd,
  3435. + int write_cmd)
  3436. +{
  3437. + int i;
  3438. + unsigned char data = 0x2;
  3439. +
  3440. + /* Preamble. Magic value is number of bits. */
  3441. + for (i = 31; i >= 0; i--)
  3442. + crisv32_eth_send_mdio_bit(dev, GET_BIT(i, MDIO_PREAMBLE));
  3443. +
  3444. + for (i = 15; i >= 2; i--)
  3445. + crisv32_eth_send_mdio_bit(dev, GET_BIT(i, cmd));
  3446. +
  3447. + /* Turnaround. */
  3448. + for (i = 1; i >= 0; i--)
  3449. + if (write_cmd)
  3450. + crisv32_eth_send_mdio_bit(dev, GET_BIT(i, data));
  3451. + else
  3452. + crisv32_eth_receive_mdio_bit(dev);
  3453. +}
  3454. +
  3455. +static void crisv32_eth_send_mdio_bit(struct net_device *dev, unsigned char bit)
  3456. +{
  3457. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3458. +
  3459. + reg_eth_rw_mgm_ctrl mgm_ctrl = {
  3460. + .mdoe = regk_eth_yes,
  3461. + .mdio = bit & 1
  3462. + };
  3463. +
  3464. + REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);
  3465. +
  3466. + udelay(1);
  3467. +
  3468. + mgm_ctrl.mdc = 1;
  3469. + REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);
  3470. +
  3471. + udelay(1);
  3472. +}
  3473. +
  3474. +static unsigned char crisv32_eth_receive_mdio_bit(struct net_device *dev)
  3475. +{
  3476. + reg_eth_r_stat stat;
  3477. + reg_eth_rw_mgm_ctrl mgm_ctrl = {0};
  3478. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3479. +
  3480. + REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);
  3481. + stat = REG_RD(eth, np->eth_inst, r_stat);
  3482. +
  3483. + udelay(1);
  3484. +
  3485. + mgm_ctrl.mdc = 1;
  3486. + REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);
  3487. +
  3488. + udelay(1);
  3489. + return stat.mdio;
  3490. +}
  3491. +
  3492. +static void crisv32_clear_network_leds(unsigned long priv)
  3493. +{
  3494. + struct net_device *dev = (struct net_device *)priv;
  3495. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3496. + unsigned long flags;
  3497. +
  3498. + spin_lock_irqsave(&np->leds->led_lock, flags);
  3499. + if (np->leds->led_active && time_after(jiffies,
  3500. + np->leds->led_next_time)) {
  3501. + crisv32_set_network_leds(CRIS_LED_NOACTIVITY, dev);
  3502. +
  3503. + /* Set the earliest time we may set the LED */
  3504. + np->leds->led_next_time = jiffies + NET_FLASH_PAUSE;
  3505. + np->leds->led_active = 0;
  3506. + }
  3507. + spin_unlock_irqrestore(&np->leds->led_lock, flags);
  3508. +}
  3509. +
  3510. +static void crisv32_set_network_leds(int active, struct net_device *dev)
  3511. +{
  3512. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3513. + int light_leds = 0;
  3514. +
  3515. + if (np->leds->ledgrp == CRIS_LED_GRP_NONE)
  3516. + return;
  3517. +
  3518. + if (!np->use_leds)
  3519. + return;
  3520. +
  3521. + if (active == CRIS_LED_NOLINK) {
  3522. + if (dev == crisv32_dev[0])
  3523. + np->leds->ifisup[0] = 0;
  3524. + else
  3525. + np->leds->ifisup[1] = 0;
  3526. + }
  3527. + else if (active == CRIS_LED_LINK) {
  3528. + if (dev == crisv32_dev[0])
  3529. + np->leds->ifisup[0] = 1;
  3530. + else
  3531. + np->leds->ifisup[1] = 1;
  3532. +#if defined(CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK)
  3533. + light_leds = 1;
  3534. + } else {
  3535. + light_leds = (active == CRIS_LED_NOACTIVITY);
  3536. +#elif defined(CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY)
  3537. + light_leds = 0;
  3538. + } else {
  3539. + light_leds = (active == CRIS_LED_ACTIVITY);
  3540. +#else
  3541. +#error "Define either CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK or CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY"
  3542. +#endif
  3543. + }
  3544. +}
  3545. +
  3546. +#ifdef CONFIG_NET_POLL_CONTROLLER
  3547. +static void crisv32_netpoll(struct net_device *netdev)
  3548. +{
  3549. + crisv32rx_eth_interrupt(DMA0_INTR_VECT, netdev);
  3550. +}
  3551. +#endif
  3552. +
  3553. +#ifdef CONFIG_CPU_FREQ
  3554. +static int crisv32_ethernet_freq_notifier(struct notifier_block *nb,
  3555. + unsigned long val, void *data)
  3556. +{
  3557. + struct cpufreq_freqs *freqs = data;
  3558. + int i;
  3559. + if (val != CPUFREQ_POSTCHANGE)
  3560. + return 0;
  3561. +
  3562. + for (i = 0; i < 2; i++) {
  3563. + struct net_device *dev = crisv32_dev[i];
  3564. + unsigned short data;
  3565. + if (dev == NULL)
  3566. + continue;
  3567. +
  3568. + data = crisv32_eth_get_mdio_reg(dev, np->mii_if.phy_id,
  3569. + MII_BMCR);
  3570. + if (freqs->new == 200000)
  3571. + data &= ~BMCR_PDOWN;
  3572. + else
  3573. + data |= BMCR_PDOWN;
  3574. + crisv32_eth_set_mdio_reg(dev, np->mii_if.phy_id,
  3575. + MII_BMCR, data);
  3576. + }
  3577. + return 0;
  3578. +}
  3579. +#endif
  3580. +
  3581. +#if 0
  3582. +/*
  3583. + * Must be called with the np->lock held.
  3584. + */
  3585. +static void crisv32_ethernet_bug(struct net_device *dev)
  3586. +{
  3587. + struct crisv32_ethernet_local *np = netdev_priv(dev);
  3588. + dma_descr_data *dma_pos;
  3589. + dma_descr_data *in_dma_pos;
  3590. + reg_dma_rw_stat stat = {0};
  3591. + reg_dma_rw_stat in_stat = {0};
  3592. + int i;
  3593. +
  3594. + /* Get the current output dma position. */
  3595. + stat = REG_RD(dma, np->dma_out_inst, rw_stat);
  3596. +
  3597. + dma_pos = phys_to_virt(REG_RD_INT(dma, np->dma_out_inst, rw_data));
  3598. + in_dma_pos = phys_to_virt(REG_RD_INT(dma, np->dma_in_inst, rw_data));
  3599. + in_stat = REG_RD(dma, np->dma_in_inst, rw_stat);
  3600. +
  3601. + printk("%s:\n"
  3602. + "stat.list_state=%x\n"
  3603. + "stat.mode=%x\n"
  3604. + "stat.stream_cmd_src=%x\n"
  3605. + "dma_pos=%x\n"
  3606. + "tx catch=%x active=%x\n"
  3607. + "packets=%d queue=%d sender_started=%d\n"
  3608. + "intr_vect.r_vect=%x\n"
  3609. + "dma.r_masked_intr=%x dma.rw_ack_intr=%x "
  3610. + "dma.r_intr=%x dma.rw_intr_masked=%x\n"
  3611. + "eth.r_stat=%x\n",
  3612. + __func__,
  3613. + stat.list_state, stat.mode, stat.stream_cmd_src,
  3614. + (unsigned int)dma_pos,
  3615. + (unsigned int)&np->catch_tx_desc->descr,
  3616. + (unsigned int)&np->active_tx_desc->descr,
  3617. + np->txpackets,
  3618. + netif_queue_stopped(dev), np->sender_started,
  3619. + REG_RD_INT(intr_vect, regi_irq, r_vect),
  3620. + REG_RD_INT(dma, np->dma_out_inst, r_masked_intr),
  3621. + REG_RD_INT(dma, np->dma_out_inst, rw_ack_intr),
  3622. + REG_RD_INT(dma, np->dma_out_inst, r_intr),
  3623. + REG_RD_INT(dma, np->dma_out_inst, rw_intr_mask),
  3624. + REG_RD_INT(eth, np->eth_inst, r_stat));
  3625. +
  3626. + printk("in_stat.list_state=%x\n"
  3627. + "in_stat.mode=%x\n"
  3628. + "in_stat.stream_cmd_src=%x\n"
  3629. + "in_dma_pos=%x\n"
  3630. + "rx last=%x prev=%x active=%x\n",
  3631. + in_stat.list_state, in_stat.mode, in_stat.stream_cmd_src,
  3632. + (unsigned int)in_dma_pos,
  3633. + (unsigned int)&np->last_rx_desc->descr,
  3634. + (unsigned int)&np->prev_rx_desc->descr,
  3635. + (unsigned int)&np->active_rx_desc->descr);
  3636. +
  3637. +#if 0
  3638. + printk("rx-descriptors:\n");
  3639. + for (i = 0; i < NBR_RX_DESC; i++) {
  3640. + printk("rxdesc[%d]=0x%x\n", i, (unsigned int)
  3641. + virt_to_phys(&np->dma_rx_descr_list[i].descr));
  3642. + printk("rxdesc[%d].skb=0x%x\n", i,
  3643. + (unsigned int)np->dma_rx_descr_list[i].skb);
  3644. + printk("rxdesc[%d].buf=0x%x\n", i,
  3645. + (unsigned int)np->dma_rx_descr_list[i].descr.buf);
  3646. + printk("rxdesc[%d].after=0x%x\n", i,
  3647. + (unsigned int)np->dma_rx_descr_list[i].descr.after);
  3648. + printk("rxdesc[%d].intr=%x\n", i,
  3649. + np->dma_rx_descr_list[i].descr.intr);
  3650. + printk("rxdesc[%d].eol=%x\n", i,
  3651. + np->dma_rx_descr_list[i].descr.eol);
  3652. + printk("rxdesc[%d].out_eop=%x\n", i,
  3653. + np->dma_rx_descr_list[i].descr.out_eop);
  3654. + printk("rxdesc[%d].in_eop=%x\n", i,
  3655. + np->dma_rx_descr_list[i].descr.in_eop);
  3656. + printk("rxdesc[%d].wait=%x\n", i,
  3657. + np->dma_rx_descr_list[i].descr.wait);
  3658. + }
  3659. +#endif
  3660. +
  3661. +#if 1
  3662. + printk("tx-descriptors:\n");
  3663. + for (i = 0; i < NBR_TX_DESC; i++) {
  3664. + printk("txdesc[%d]=0x%x\n", i, (unsigned int)
  3665. + virt_to_phys(&np->dma_tx_descr_list[i].descr));
  3666. + printk("txdesc[%d].skb=0x%x\n", i,
  3667. + (unsigned int)np->dma_tx_descr_list[i].skb);
  3668. + printk("txdesc[%d].buf=0x%x\n", i,
  3669. + (unsigned int)np->dma_tx_descr_list[i].descr.buf);
  3670. + printk("txdesc[%d].after=0x%x\n", i,
  3671. + (unsigned int)np->dma_tx_descr_list[i].descr.after);
  3672. + printk("txdesc[%d].intr=%x\n", i,
  3673. + np->dma_tx_descr_list[i].descr.intr);
  3674. + printk("txdesc[%d].eol=%x\n", i,
  3675. + np->dma_tx_descr_list[i].descr.eol);
  3676. + printk("txdesc[%d].out_eop=%x\n", i,
  3677. + np->dma_tx_descr_list[i].descr.out_eop);
  3678. + printk("txdesc[%d].in_eop=%x\n", i,
  3679. + np->dma_tx_descr_list[i].descr.in_eop);
  3680. + printk("txdesc[%d].wait=%x\n", i,
  3681. + np->dma_tx_descr_list[i].descr.wait);
  3682. + }
  3683. +#endif
  3684. +}
  3685. +#endif
  3686. +
  3687. +static int __init crisv32_boot_setup(char *str)
  3688. +{
  3689. + struct sockaddr sa = {0};
  3690. + int i;
  3691. +
  3692. + /* Parse the colon separated Ethernet station address */
  3693. + for (i = 0; i < ETH_ALEN; i++) {
  3694. + unsigned int tmp;
  3695. + if (sscanf(str + 3*i, "%2x", &tmp) != 1) {
  3696. + printk(KERN_WARNING "Malformed station address");
  3697. + return 0;
  3698. + }
  3699. + sa.sa_data[i] = (char)tmp;
  3700. + }
  3701. +
  3702. + default_mac_iface0 = sa;
  3703. + return 1;
  3704. +}
  3705. +
  3706. +__setup("crisv32_eth=", crisv32_boot_setup);
  3707. +
  3708. +module_init(crisv32_ethernet_init);
  3709. diff -Nur linux-4.7.3.orig/drivers/net/cris/eth_v32.h linux-4.7.3/drivers/net/cris/eth_v32.h
  3710. --- linux-4.7.3.orig/drivers/net/cris/eth_v32.h 1970-01-01 01:00:00.000000000 +0100
  3711. +++ linux-4.7.3/drivers/net/cris/eth_v32.h 2016-09-13 01:47:09.527718381 +0200
  3712. @@ -0,0 +1,291 @@
  3713. +/*
  3714. + * Definitions for ETRAX FS ethernet driver.
  3715. + *
  3716. + * Copyright (C) 2003, 2004, 2005 Axis Communications.
  3717. + */
  3718. +
  3719. +#ifndef _ETRAX_ETHERNET_H_
  3720. +#define _ETRAX_ETHERNET_H_
  3721. +
  3722. +#include <hwregs/dma.h>
  3723. +
  3724. +#define MAX_MEDIA_DATA_SIZE 1522 /* Max packet size. */
  3725. +
  3726. +#define NBR_RX_DESC 128 /* Number of RX descriptors. */
  3727. +#define NBR_TX_DESC 16 /* Number of TX descriptors. */
  3728. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  3729. +#define NBR_INTMEM_RX_DESC 16 /* Number of RX descriptors in int. mem.
  3730. + * when running in gigabit mode.
  3731. + * Should be less then NBR_RX_DESC
  3732. + */
  3733. +#define NBR_INTMEM_TX_BUF 4 /* Number of TX buffers in int. mem
  3734. + * when running in gigabit mode.
  3735. + * Should be less than NBR_TX_DESC
  3736. + */
  3737. +#endif
  3738. +
  3739. +/* Large packets are sent directly to upper layers while small packets
  3740. + * are copied (to reduce memory waste). The following constant
  3741. + * decides the breakpoint.
  3742. + */
  3743. +#define RX_COPYBREAK (256)
  3744. +
  3745. +#define ETHER_HEAD_LEN (14)
  3746. +
  3747. +/*
  3748. + * MDIO constants.
  3749. + */
  3750. +#define MDIO_START 0x1
  3751. +#define MDIO_READ 0x2
  3752. +#define MDIO_WRITE 0x1
  3753. +#define MDIO_PREAMBLE 0xfffffffful
  3754. +
  3755. +/* Broadcom specific */
  3756. +#define MDIO_AUX_CTRL_STATUS_REG 0x18
  3757. +#define MDIO_BC_FULL_DUPLEX_IND 0x1
  3758. +#define MDIO_BC_SPEED 0x2
  3759. +
  3760. +/* TDK specific */
  3761. +#define MDIO_TDK_DIAGNOSTIC_REG 18
  3762. +#define MDIO_TDK_DIAGNOSTIC_RATE 0x400
  3763. +#define MDIO_TDK_DIAGNOSTIC_DPLX 0x800
  3764. +
  3765. +/*Intel LXT972A specific*/
  3766. +#define MDIO_INT_STATUS_REG_2 0x0011
  3767. +#define MDIO_INT_FULL_DUPLEX_IND ( 0x0001 << 9 )
  3768. +#define MDIO_INT_SPEED ( 0x0001 << 14 )
  3769. +
  3770. +/*National Semiconductor DP83865 specific*/
  3771. +#define MDIO_NAT_LINK_AN_REG 0x11
  3772. +#define MDIO_NAT_1000 (0x0001 << 4)
  3773. +#define MDIO_NAT_100 (0x0001 << 3)
  3774. +#define MDIO_NAT_FULL_DUPLEX_IND (0x0001 << 1)
  3775. +
  3776. +/* Vitesse VCS8641 specific */
  3777. +#define MDIO_VIT_AUX_STAT 0x1c
  3778. +#define MDIO_VIT_1000 (0x2 << 3)
  3779. +#define MDIO_VIT_100 (0x1 << 3)
  3780. +#define MDIO_VIT_10 0
  3781. +#define MDIO_VIT_FD (0x1 << 5)
  3782. +
  3783. +/* Davicom DM9161 specific */
  3784. +#define DM9161_OUI 0x606E
  3785. +#define MII_DM9161_SCR 0x10
  3786. +#define MII_DM9161_SCR_INIT 0x0610
  3787. +#define MII_DM9161_SCR_RMII 0x0100
  3788. +#define MII_DM9161_10BTCSR 0x12
  3789. +#define MII_DM9161_10BTCSR_INIT 0x7800
  3790. +
  3791. +/* Network flash constants */
  3792. +#define NET_FLASH_TIME (HZ/50) /* 20 ms */
  3793. +#define NET_FLASH_PAUSE (HZ/100) /* 10 ms */
  3794. +#define NET_LINK_UP_CHECK_INTERVAL (2*HZ) /* 2 seconds. */
  3795. +#define NET_DUPLEX_CHECK_INTERVAL (2*HZ) /* 2 seconds. */
  3796. +
  3797. +/* Duplex settings. */
  3798. +enum duplex {
  3799. + half,
  3800. + full,
  3801. + autoneg
  3802. +};
  3803. +
  3804. +/* Some transceivers requires special handling. */
  3805. +struct transceiver_ops {
  3806. + unsigned int oui;
  3807. + void (*check_speed) (struct net_device * dev);
  3808. + void (*check_duplex) (struct net_device * dev);
  3809. +};
  3810. +
  3811. +typedef struct crisv32_eth_descr {
  3812. + dma_descr_data descr __attribute__ ((__aligned__(32)));
  3813. + struct sk_buff *skb;
  3814. + unsigned char *linearized_packet;
  3815. +} crisv32_eth_descr;
  3816. +
  3817. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  3818. +struct tx_buffer_list {
  3819. + struct tx_buffer_list *next;
  3820. + unsigned char *buf;
  3821. + char free;
  3822. +};
  3823. +#endif
  3824. +
  3825. +/* LED stuff */
  3826. +#define CRIS_LED_GRP_0 0
  3827. +#define CRIS_LED_GRP_1 1
  3828. +#define CRIS_LED_GRP_NONE 2
  3829. +
  3830. +#define CRIS_LED_ACTIVITY 0
  3831. +#define CRIS_LED_NOACTIVITY 1
  3832. +#define CRIS_LED_LINK 2
  3833. +#define CRIS_LED_NOLINK 3
  3834. +
  3835. +struct crisv32_eth_leds {
  3836. + unsigned int ledgrp;
  3837. + int led_active;
  3838. + unsigned long led_next_time;
  3839. + struct timer_list clear_led_timer;
  3840. + spinlock_t led_lock; /* Protect LED state */
  3841. + int ifisup[2];
  3842. +};
  3843. +
  3844. +/* Information that need to be kept for each device. */
  3845. +struct crisv32_ethernet_local {
  3846. + /* FIXME: These align attributes don't really help. If they are really
  3847. + * needed alignment has to be enforced at runtime, these objects
  3848. + * are dynamically allocated. */
  3849. + dma_descr_context ctxt_in __attribute__ ((__aligned__(32)));
  3850. + dma_descr_context ctxt_out __attribute__ ((__aligned__(32)));
  3851. +
  3852. + crisv32_eth_descr dma_rx_descr_list[NBR_RX_DESC];
  3853. + crisv32_eth_descr dma_tx_descr_list[NBR_TX_DESC];
  3854. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  3855. + struct tx_buffer_list tx_intmem_buf_list[NBR_INTMEM_TX_BUF];
  3856. + struct tx_buffer_list *intmem_tx_buf_active;
  3857. + struct tx_buffer_list *intmem_tx_buf_catch;
  3858. + int gigabit_mode;
  3859. +#endif
  3860. + /* Transmit data path. */
  3861. + int dma_out_inst;
  3862. + int sender_started;
  3863. +
  3864. + /* TX-ring state. */
  3865. + crisv32_eth_descr *active_tx_desc;
  3866. + crisv32_eth_descr *prev_tx_desc;
  3867. + crisv32_eth_descr *catch_tx_desc;
  3868. + int txpackets;
  3869. + int retrans;
  3870. + int do_tx_recovery;
  3871. + struct timer_list transmit_timer;
  3872. +
  3873. + /* Receive data path. */
  3874. + struct napi_struct napi;
  3875. + int dma_in_inst;
  3876. +
  3877. + /* RX-ring state. */
  3878. + crisv32_eth_descr *active_rx_desc;
  3879. + crisv32_eth_descr *prev_rx_desc;
  3880. + crisv32_eth_descr *last_rx_desc;
  3881. +
  3882. + unsigned long newbuf;
  3883. + u8 new_rx_package;
  3884. + u8 pending_overrun;
  3885. + u8 overrun_set;
  3886. + u8 link;
  3887. + int napi_processing;
  3888. + struct timer_list receive_timer;
  3889. + struct work_struct receive_work;
  3890. + reg_eth_rw_rec_ctrl saved_rec_ctrl;
  3891. + int saved_ga_lo;
  3892. + int saved_ga_hi;
  3893. + int do_rx_recovery;
  3894. +
  3895. + /* Control paths. */
  3896. + spinlock_t lock;
  3897. + struct net_device *dev;
  3898. + int eth_inst;
  3899. +
  3900. + /* Toggle network LEDs usage at runtime */
  3901. + int use_leds;
  3902. + struct crisv32_eth_leds *leds;
  3903. +
  3904. + /* PHY control. */
  3905. + int fixed_phy;
  3906. + spinlock_t transceiver_lock; /* Protect transceiver state. */
  3907. + struct transceiver_ops *transceiver;
  3908. + struct mii_if_info mii_if;
  3909. +
  3910. + /* Specifies if we should do autonegotiation or not.
  3911. + * TODO: This ad-hoc hack should be removed. Ethtool already supports
  3912. + * this kind of control.
  3913. + */
  3914. + int autoneg_normal;
  3915. +
  3916. + struct timer_list duplex_timer;
  3917. + int full_duplex;
  3918. + enum duplex current_duplex;
  3919. +
  3920. + struct timer_list speed_timer;
  3921. + int current_speed; /* Speed read from tranceiver */
  3922. + int current_speed_selection; /* Speed selected by user */
  3923. +
  3924. + /* Statistics. */
  3925. + u64 tx_dma_restarts;
  3926. + u64 tx_mac_resets;
  3927. + u64 rx_dma_restarts;
  3928. + u64 rx_dma_timeouts;
  3929. + u64 rx_restarts_dropped;
  3930. +
  3931. + struct net_device_stats stats;
  3932. +};
  3933. +
  3934. +/* Function prototypes. */
  3935. +static int crisv32_ethernet_init(void);
  3936. +static int crisv32_ethernet_device_init(struct net_device *dev);
  3937. +static int crisv32_eth_open(struct net_device *dev);
  3938. +static int crisv32_eth_close(struct net_device *dev);
  3939. +static int crisv32_eth_set_mac_address(struct net_device *dev, void *vpntr);
  3940. +static irqreturn_t crisv32rx_eth_interrupt(int irq, void *dev_id);
  3941. +static irqreturn_t crisv32tx_eth_interrupt(int irq, void *dev_id);
  3942. +static irqreturn_t crisv32nw_eth_interrupt(int irq, void *dev_id);
  3943. +static int crisv32_eth_send_packet(struct sk_buff *skb, struct net_device *dev);
  3944. +static void crisv32_eth_hw_send_packet(unsigned char *buf, int length,
  3945. + void *priv);
  3946. +static void crisv32_eth_do_tx_recovery(struct net_device *dev);
  3947. +static void crisv32_eth_set_rx_mode(struct net_device *dev);
  3948. +static int crisv32_eth_ioctl(struct net_device *dev, struct ifreq *ifr,
  3949. + int cmd);
  3950. +static int crisv32_eth_set_config(struct net_device *dev, struct ifmap *map);
  3951. +#ifdef CONFIG_CRIS_MACH_ARTPEC3
  3952. +static void crisv32_eth_switch_intmem_usage(struct net_device *dev);
  3953. +#endif
  3954. +static void crisv32_eth_negotiate(struct net_device *dev);
  3955. +static void crisv32_eth_set_speed(struct net_device *dev, unsigned long speed);
  3956. +#ifndef CONFIG_ETRAX_NO_PHY
  3957. +static void crisv32_eth_check_duplex(unsigned long idev);
  3958. +static void crisv32_eth_check_speed(unsigned long idev);
  3959. +#endif
  3960. +
  3961. +static void crisv32_eth_set_duplex(struct net_device *dev, enum duplex);
  3962. +static int crisv32_eth_probe_transceiver(struct net_device *dev);
  3963. +
  3964. +static struct ethtool_ops crisv32_ethtool_ops;
  3965. +
  3966. +#ifndef CONFIG_ETRAX_NO_PHY
  3967. +static void generic_check_speed(struct net_device *dev);
  3968. +static void generic_check_duplex(struct net_device *dev);
  3969. +static void broadcom_check_speed(struct net_device *dev);
  3970. +static void broadcom_check_duplex(struct net_device *dev);
  3971. +static void tdk_check_speed(struct net_device *dev);
  3972. +static void tdk_check_duplex(struct net_device *dev);
  3973. +static void intel_check_speed(struct net_device *dev);
  3974. +static void intel_check_duplex(struct net_device *dev);
  3975. +static void national_check_speed(struct net_device *dev);
  3976. +static void national_check_duplex(struct net_device *dev);
  3977. +static void vitesse_check_speed(struct net_device *dev);
  3978. +static void vitesse_check_duplex(struct net_device *dev);
  3979. +static void davicom_check_speed(struct net_device *dev);
  3980. +static void davicom_check_duplex(struct net_device *dev);
  3981. +#endif
  3982. +
  3983. +#ifdef CONFIG_NET_POLL_CONTROLLER
  3984. +static void crisv32_netpoll(struct net_device *dev);
  3985. +#endif
  3986. +
  3987. +static void crisv32_clear_network_leds(unsigned long dummy);
  3988. +static void crisv32_set_network_leds(int active, struct net_device *dev);
  3989. +
  3990. +static int crisv32_eth_get_mdio_reg(struct net_device *dev,
  3991. + int phyid, int reg_num);
  3992. +static void crisv32_eth_set_mdio_reg(struct net_device *dev,
  3993. + int phyid, int reg_num, int val);
  3994. +static void crisv32_eth_send_mdio_cmd(struct net_device *dev,
  3995. + unsigned short cmd, int write_cmd);
  3996. +static void crisv32_eth_send_mdio_bit(struct net_device *dev,
  3997. + unsigned char bit);
  3998. +static unsigned char crisv32_eth_receive_mdio_bit(struct net_device *dev);
  3999. +
  4000. +static struct net_device_stats *crisv32_get_stats(struct net_device *dev);
  4001. +static void crisv32_start_dma_out(struct crisv32_ethernet_local *np);
  4002. +
  4003. +#endif /* _ETRAX_ETHERNET_H_ */
  4004. diff -Nur linux-4.7.3.orig/drivers/net/cris/Makefile linux-4.7.3/drivers/net/cris/Makefile
  4005. --- linux-4.7.3.orig/drivers/net/cris/Makefile 2016-09-07 08:35:12.000000000 +0200
  4006. +++ linux-4.7.3/drivers/net/cris/Makefile 2016-09-13 01:47:09.527718381 +0200
  4007. @@ -1 +1,2 @@
  4008. obj-$(CONFIG_ETRAX_ARCH_V10) += eth_v10.o
  4009. +obj-$(CONFIG_ETRAX_ARCH_V32) += eth_v32.o