lemote.patch 113 KB

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  1. diff -Nur linux-2.6.36.orig/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig
  2. --- linux-2.6.36.orig/arch/mips/Kconfig 2010-10-20 22:30:22.000000000 +0200
  3. +++ linux-2.6.36/arch/mips/Kconfig 2010-12-17 23:12:59.000000000 +0100
  4. @@ -205,7 +205,7 @@
  5. config MACH_LOONGSON
  6. bool "Loongson family of machines"
  7. - select SYS_SUPPORTS_ZBOOT
  8. + select SYS_SUPPORTS_ZBOOT_UART16550
  9. help
  10. This enables the support of Loongson family of machines.
  11. @@ -1093,6 +1093,8 @@
  12. bool "Loongson 2E"
  13. depends on SYS_HAS_CPU_LOONGSON2E
  14. select CPU_LOONGSON2
  15. + select GENERIC_GPIO
  16. + select ARCH_REQUIRE_GPIOLIB
  17. help
  18. The Loongson 2E processor implements the MIPS III instruction set
  19. with many extensions.
  20. @@ -2012,6 +2014,18 @@
  21. source "kernel/time/Kconfig"
  22. #
  23. +# High Resolution sched_clock() Configuration
  24. +#
  25. +
  26. +config CPU_HAS_FIXED_C0_COUNT
  27. + bool
  28. +
  29. +config CPU_SUPPORTS_HR_SCHED_CLOCK
  30. + bool
  31. + depends on CPU_HAS_FIXED_C0_COUNT || !CPU_FREQ
  32. + default y
  33. +
  34. +#
  35. # Timer Interrupt Frequency Configuration
  36. #
  37. diff -Nur linux-2.6.36.orig/arch/mips/include/asm/dma-mapping.h linux-2.6.36/arch/mips/include/asm/dma-mapping.h
  38. --- linux-2.6.36.orig/arch/mips/include/asm/dma-mapping.h 2010-10-20 22:30:22.000000000 +0200
  39. +++ linux-2.6.36/arch/mips/include/asm/dma-mapping.h 2010-12-17 23:12:59.000000000 +0100
  40. @@ -65,4 +65,8 @@
  41. extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
  42. enum dma_data_direction direction);
  43. +#define ARCH_HAS_DMA_MMAP_COHERENT
  44. +extern int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
  45. + void *cpu_addr, dma_addr_t handle, size_t size);
  46. +
  47. #endif /* _ASM_DMA_MAPPING_H */
  48. diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
  49. --- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2010-10-20 22:30:22.000000000 +0200
  50. +++ linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2010-12-17 23:12:59.000000000 +0100
  51. @@ -255,21 +255,12 @@
  52. * IDE STANDARD
  53. */
  54. #define IDE_CAP 0x00
  55. -#define IDE_CONFIG 0x01
  56. -#define IDE_SMI 0x02
  57. -#define IDE_ERROR 0x03
  58. -#define IDE_PM 0x04
  59. -#define IDE_DIAG 0x05
  60. -
  61. -/*
  62. - * IDE SPEC.
  63. - */
  64. #define IDE_IO_BAR 0x08
  65. #define IDE_CFG 0x10
  66. #define IDE_DTC 0x12
  67. #define IDE_CAST 0x13
  68. #define IDE_ETC 0x14
  69. -#define IDE_INTERNAL_PM 0x15
  70. +#define IDE_PM 0x15
  71. /*
  72. * ACC STANDARD
  73. @@ -301,5 +292,40 @@
  74. /* GPIO : I/O SPACE; REG : 32BITS */
  75. #define GPIOL_OUT_VAL 0x00
  76. #define GPIOL_OUT_EN 0x04
  77. +#define GPIOL_OUT_AUX1_SEL 0x10
  78. +/* SMB : I/O SPACE, REG : 8BITS WIDTH */
  79. +#define SMB_SDA 0x00
  80. +#define SMB_STS 0x01
  81. +#define SMB_STS_SLVSTP (1 << 7)
  82. +#define SMB_STS_SDAST (1 << 6)
  83. +#define SMB_STS_BER (1 << 5)
  84. +#define SMB_STS_NEGACK (1 << 4)
  85. +#define SMB_STS_STASTR (1 << 3)
  86. +#define SMB_STS_NMATCH (1 << 2)
  87. +#define SMB_STS_MASTER (1 << 1)
  88. +#define SMB_STS_XMIT (1 << 0)
  89. +#define SMB_CTRL_STS 0x02
  90. +#define SMB_CSTS_TGSTL (1 << 5)
  91. +#define SMB_CSTS_TSDA (1 << 4)
  92. +#define SMB_CSTS_GCMTCH (1 << 3)
  93. +#define SMB_CSTS_MATCH (1 << 2)
  94. +#define SMB_CSTS_BB (1 << 1)
  95. +#define SMB_CSTS_BUSY (1 << 0)
  96. +#define SMB_CTRL1 0x03
  97. +#define SMB_CTRL1_STASTRE (1 << 7)
  98. +#define SMB_CTRL1_NMINTE (1 << 6)
  99. +#define SMB_CTRL1_GCMEN (1 << 5)
  100. +#define SMB_CTRL1_ACK (1 << 4)
  101. +#define SMB_CTRL1_RSVD (1 << 3)
  102. +#define SMB_CTRL1_INTEN (1 << 2)
  103. +#define SMB_CTRL1_STOP (1 << 1)
  104. +#define SMB_CTRL1_START (1 << 0)
  105. +#define SMB_ADDR 0x04
  106. +#define SMB_ADDR_SAEN (1 << 7)
  107. +#define SMB_CONTROLLER_ADDR (0xef << 0)
  108. +#define SMB_CTRL2 0x05
  109. +#define SMB_FREQ (0x20 << 1)
  110. +#define SMB_ENABLE (0x01 << 0)
  111. +#define SMB_CTRL3 0x06
  112. #endif /* _CS5536_H */
  113. diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
  114. --- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2010-10-20 22:30:22.000000000 +0200
  115. +++ linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2010-12-17 23:12:59.000000000 +0100
  116. @@ -32,4 +32,9 @@
  117. #define MFGPT0_CNT (MFGPT_BASE + 4)
  118. #define MFGPT0_SETUP (MFGPT_BASE + 6)
  119. +#define MFGPT2_CMP1 (MFGPT_BASE + 0x10)
  120. +#define MFGPT2_CMP2 (MFGPT_BASE + 0x12)
  121. +#define MFGPT2_CNT (MFGPT_BASE + 0x14)
  122. +#define MFGPT2_SETUP (MFGPT_BASE + 0x16)
  123. +
  124. #endif /*!_CS5536_MFGPT_H */
  125. diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h linux-2.6.36/arch/mips/include/asm/mach-loongson/ec_kb3310b.h
  126. --- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 1970-01-01 01:00:00.000000000 +0100
  127. +++ linux-2.6.36/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 2010-12-17 23:12:59.000000000 +0100
  128. @@ -0,0 +1,191 @@
  129. +/*
  130. + * KB3310B Embedded Controller
  131. + *
  132. + * Copyright (C) 2008 Lemote Inc.
  133. + * Author: liujl <liujl@lemote.com>, 2008-03-14
  134. + * Copyright (C) 2009 Lemote Inc.
  135. + * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  136. + *
  137. + * This program is free software; you can redistribute it and/or modify
  138. + * it under the terms of the GNU General Public License as published by
  139. + * the Free Software Foundation; either version 2 of the License, or
  140. + * (at your option) any later version.
  141. + */
  142. +
  143. +#ifndef _EC_KB3310B_H
  144. +#define _EC_KB3310B_H
  145. +
  146. +extern unsigned char ec_read(unsigned short addr);
  147. +extern void ec_write(unsigned short addr, unsigned char val);
  148. +extern int ec_query_seq(unsigned char cmd);
  149. +extern int ec_query_event_num(void);
  150. +extern int ec_get_event_num(void);
  151. +
  152. +typedef int (*sci_handler) (int status);
  153. +extern sci_handler yeeloong_report_lid_status;
  154. +
  155. +#define SCI_IRQ_NUM 0x0A
  156. +
  157. +/*
  158. + * The following registers are determined by the EC index configuration.
  159. + * 1, fill the PORT_HIGH as EC register high part.
  160. + * 2, fill the PORT_LOW as EC register low part.
  161. + * 3, fill the PORT_DATA as EC register write data or get the data from it.
  162. + */
  163. +#define EC_IO_PORT_HIGH 0x0381
  164. +#define EC_IO_PORT_LOW 0x0382
  165. +#define EC_IO_PORT_DATA 0x0383
  166. +
  167. +/*
  168. + * EC delay time is 500us for register and status access
  169. + */
  170. +#define EC_REG_DELAY 500 /* unit : us */
  171. +#define EC_CMD_TIMEOUT 0x1000
  172. +
  173. +/*
  174. + * EC access port for SCI communication
  175. + */
  176. +#define EC_CMD_PORT 0x66
  177. +#define EC_STS_PORT 0x66
  178. +#define EC_DAT_PORT 0x62
  179. +#define CMD_INIT_IDLE_MODE 0xdd
  180. +#define CMD_EXIT_IDLE_MODE 0xdf
  181. +#define CMD_INIT_RESET_MODE 0xd8
  182. +#define CMD_REBOOT_SYSTEM 0x8c
  183. +#define CMD_GET_EVENT_NUM 0x84
  184. +#define CMD_PROGRAM_PIECE 0xda
  185. +
  186. +/* Temperature & Fan registers */
  187. +#define REG_TEMPERATURE_VALUE 0xF458
  188. +#define REG_FAN_AUTO_MAN_SWITCH 0xF459
  189. +#define BIT_FAN_AUTO 0
  190. +#define BIT_FAN_MANUAL 1
  191. +#define REG_FAN_CONTROL 0xF4D2
  192. +#define BIT_FAN_CONTROL_ON (1 << 0)
  193. +#define BIT_FAN_CONTROL_OFF (0 << 0)
  194. +#define REG_FAN_STATUS 0xF4DA
  195. +#define BIT_FAN_STATUS_ON (1 << 0)
  196. +#define BIT_FAN_STATUS_OFF (0 << 0)
  197. +#define REG_FAN_SPEED_HIGH 0xFE22
  198. +#define REG_FAN_SPEED_LOW 0xFE23
  199. +#define REG_FAN_SPEED_LEVEL 0xF4CC
  200. +/* Fan speed divider */
  201. +#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/
  202. +
  203. +/* Battery registers */
  204. +#define REG_BAT_DESIGN_CAP_HIGH 0xF77D
  205. +#define REG_BAT_DESIGN_CAP_LOW 0xF77E
  206. +#define REG_BAT_FULLCHG_CAP_HIGH 0xF780
  207. +#define REG_BAT_FULLCHG_CAP_LOW 0xF781
  208. +#define REG_BAT_DESIGN_VOL_HIGH 0xF782
  209. +#define REG_BAT_DESIGN_VOL_LOW 0xF783
  210. +#define REG_BAT_CURRENT_HIGH 0xF784
  211. +#define REG_BAT_CURRENT_LOW 0xF785
  212. +#define REG_BAT_VOLTAGE_HIGH 0xF786
  213. +#define REG_BAT_VOLTAGE_LOW 0xF787
  214. +#define REG_BAT_TEMPERATURE_HIGH 0xF788
  215. +#define REG_BAT_TEMPERATURE_LOW 0xF789
  216. +#define REG_BAT_RELATIVE_CAP_HIGH 0xF492
  217. +#define REG_BAT_RELATIVE_CAP_LOW 0xF493
  218. +#define REG_BAT_VENDOR 0xF4C4
  219. +#define FLAG_BAT_VENDOR_SANYO 0x01
  220. +#define FLAG_BAT_VENDOR_SIMPLO 0x02
  221. +#define REG_BAT_CELL_COUNT 0xF4C6
  222. +#define FLAG_BAT_CELL_3S1P 0x03
  223. +#define FLAG_BAT_CELL_3S2P 0x06
  224. +#define REG_BAT_CHARGE 0xF4A2
  225. +#define FLAG_BAT_CHARGE_DISCHARGE 0x01
  226. +#define FLAG_BAT_CHARGE_CHARGE 0x02
  227. +#define FLAG_BAT_CHARGE_ACPOWER 0x00
  228. +#define REG_BAT_STATUS 0xF4B0
  229. +#define BIT_BAT_STATUS_LOW (1 << 5)
  230. +#define BIT_BAT_STATUS_DESTROY (1 << 2)
  231. +#define BIT_BAT_STATUS_FULL (1 << 1)
  232. +#define BIT_BAT_STATUS_IN (1 << 0)
  233. +#define REG_BAT_CHARGE_STATUS 0xF4B1
  234. +#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2)
  235. +#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1)
  236. +#define REG_BAT_STATE 0xF482
  237. +#define BIT_BAT_STATE_CHARGING (1 << 1)
  238. +#define BIT_BAT_STATE_DISCHARGING (1 << 0)
  239. +#define REG_BAT_POWER 0xF440
  240. +#define BIT_BAT_POWER_S3 (1 << 2)
  241. +#define BIT_BAT_POWER_ON (1 << 1)
  242. +#define BIT_BAT_POWER_ACIN (1 << 0)
  243. +
  244. +/* Audio: rd/wr */
  245. +#define REG_AUDIO_VOLUME 0xF46C
  246. +#define REG_AUDIO_MUTE 0xF4E7
  247. +#define REG_AUDIO_BEEP 0xF4D0
  248. +/* USB port power or not: rd/wr */
  249. +#define REG_USB0_FLAG 0xF461
  250. +#define REG_USB1_FLAG 0xF462
  251. +#define REG_USB2_FLAG 0xF463
  252. +#define BIT_USB_FLAG_ON 1
  253. +#define BIT_USB_FLAG_OFF 0
  254. +/* LID */
  255. +#define REG_LID_DETECT 0xF4BD
  256. +#define BIT_LID_DETECT_ON 1
  257. +#define BIT_LID_DETECT_OFF 0
  258. +/* CRT */
  259. +#define REG_CRT_DETECT 0xF4AD
  260. +#define BIT_CRT_DETECT_PLUG 1
  261. +#define BIT_CRT_DETECT_UNPLUG 0
  262. +/* LCD backlight brightness adjust: 9 levels */
  263. +#define REG_DISPLAY_BRIGHTNESS 0xF4F5
  264. +/* Black screen Status */
  265. +#define BIT_DISPLAY_LCD_ON 1
  266. +#define BIT_DISPLAY_LCD_OFF 0
  267. +/* LCD backlight control: off/restore */
  268. +#define REG_BACKLIGHT_CTRL 0xF7BD
  269. +#define BIT_BACKLIGHT_ON 1
  270. +#define BIT_BACKLIGHT_OFF 0
  271. +/* Reset the machine auto-clear: rd/wr */
  272. +#define REG_RESET 0xF4EC
  273. +#define BIT_RESET_ON 1
  274. +/* Light the led: rd/wr */
  275. +#define REG_LED 0xF4C8
  276. +#define BIT_LED_RED_POWER (1 << 0)
  277. +#define BIT_LED_ORANGE_POWER (1 << 1)
  278. +#define BIT_LED_GREEN_CHARGE (1 << 2)
  279. +#define BIT_LED_RED_CHARGE (1 << 3)
  280. +#define BIT_LED_NUMLOCK (1 << 4)
  281. +/* Test led mode, all led on/off */
  282. +#define REG_LED_TEST 0xF4C2
  283. +#define BIT_LED_TEST_IN 1
  284. +#define BIT_LED_TEST_OUT 0
  285. +/* Camera on/off */
  286. +#define REG_CAMERA_STATUS 0xF46A
  287. +#define BIT_CAMERA_STATUS_ON 1
  288. +#define BIT_CAMERA_STATUS_OFF 0
  289. +#define REG_CAMERA_CONTROL 0xF7B7
  290. +#define BIT_CAMERA_CONTROL_OFF 0
  291. +#define BIT_CAMERA_CONTROL_ON 1
  292. +/* Wlan Status */
  293. +#define REG_WLAN 0xF4FA
  294. +#define BIT_WLAN_ON 1
  295. +#define BIT_WLAN_OFF 0
  296. +#define REG_DISPLAY_LCD 0xF79F
  297. +
  298. +/* SCI Event Number from EC */
  299. +enum {
  300. + EVENT_LID = 0x23, /* Turn on/off LID */
  301. + EVENT_SWITCHVIDEOMODE, /* Fn+F3 for display switch */
  302. + EVENT_SLEEP, /* Fn+F1 for entering sleep mode */
  303. + EVENT_OVERTEMP, /* Over-temperature happened */
  304. + EVENT_CRT_DETECT, /* CRT is connected */
  305. + EVENT_CAMERA, /* Camera on/off */
  306. + EVENT_USB_OC2, /* USB2 Over Current occurred */
  307. + EVENT_USB_OC0, /* USB0 Over Current occurred */
  308. + EVENT_DISPLAYTOGGLE, /* Fn+F2, Turn on/off backlight */
  309. + EVENT_AUDIO_MUTE, /* Fn+F4, Mute on/off */
  310. + EVENT_DISPLAY_BRIGHTNESS,/* Fn+^/V, LCD backlight brightness adjust */
  311. + EVENT_AC_BAT, /* AC & Battery relative issue */
  312. + EVENT_AUDIO_VOLUME, /* Fn+<|>, Volume adjust */
  313. + EVENT_WLAN, /* Wlan on/off */
  314. +};
  315. +
  316. +#define EVENT_START EVENT_LID
  317. +#define EVENT_END EVENT_WLAN
  318. +
  319. +#endif /* !_EC_KB3310B_H */
  320. diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/loongson.h linux-2.6.36/arch/mips/include/asm/mach-loongson/loongson.h
  321. --- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/loongson.h 2010-10-20 22:30:22.000000000 +0200
  322. +++ linux-2.6.36/arch/mips/include/asm/mach-loongson/loongson.h 2010-12-17 23:12:59.000000000 +0100
  323. @@ -42,6 +42,12 @@
  324. #endif
  325. }
  326. +/*
  327. + * Copy kernel command line from arcs_cmdline
  328. + */
  329. +#include <asm/setup.h>
  330. +extern char loongson_cmdline[COMMAND_LINE_SIZE];
  331. +
  332. /* irq operation functions */
  333. extern void bonito_irqdispatch(void);
  334. extern void __init bonito_irq_init(void);
  335. diff -Nur linux-2.6.36.orig/arch/mips/kernel/csrc-r4k.c linux-2.6.36/arch/mips/kernel/csrc-r4k.c
  336. --- linux-2.6.36.orig/arch/mips/kernel/csrc-r4k.c 2010-10-20 22:30:22.000000000 +0200
  337. +++ linux-2.6.36/arch/mips/kernel/csrc-r4k.c 2010-12-17 23:12:59.000000000 +0100
  338. @@ -6,10 +6,66 @@
  339. * Copyright (C) 2007 by Ralf Baechle
  340. */
  341. #include <linux/clocksource.h>
  342. +#include <linux/cnt32_to_63.h>
  343. #include <linux/init.h>
  344. +#include <linux/timer.h>
  345. #include <asm/time.h>
  346. +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK
  347. +/*
  348. + * MIPS sched_clock implementation.
  349. + *
  350. + * Because the hardware timer period is quite short and because cnt32_to_63()
  351. + * needs to be called at least once per half period to work properly, a kernel
  352. + * timer is set up to ensure this requirement is always met.
  353. + *
  354. + * Please refer to include/linux/cnt32_to_63.h and arch/arm/plat-orion/time.c
  355. + */
  356. +#define CLOCK2NS_SCALE_FACTOR 8
  357. +
  358. +static unsigned long clock2ns_scale __read_mostly;
  359. +
  360. +unsigned long long notrace sched_clock(void)
  361. +{
  362. + unsigned long long v = cnt32_to_63(read_c0_count());
  363. + return (v * clock2ns_scale) >> CLOCK2NS_SCALE_FACTOR;
  364. +}
  365. +
  366. +static struct timer_list cnt32_to_63_keepwarm_timer;
  367. +
  368. +static void cnt32_to_63_keepwarm(unsigned long data)
  369. +{
  370. + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
  371. + sched_clock();
  372. +}
  373. +#endif
  374. +
  375. +static inline void setup_hres_sched_clock(unsigned long clock)
  376. +{
  377. +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK
  378. + unsigned long long v;
  379. + unsigned long data;
  380. +
  381. + v = NSEC_PER_SEC;
  382. + v <<= CLOCK2NS_SCALE_FACTOR;
  383. + v += clock/2;
  384. + do_div(v, clock);
  385. + /*
  386. + * We want an even value to automatically clear the top bit
  387. + * returned by cnt32_to_63() without an additional run time
  388. + * instruction. So if the LSB is 1 then round it up.
  389. + */
  390. + if (v & 1)
  391. + v++;
  392. + clock2ns_scale = v;
  393. +
  394. + data = 0x80000000UL / clock * HZ;
  395. + setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data);
  396. + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
  397. +#endif
  398. +}
  399. +
  400. static cycle_t c0_hpt_read(struct clocksource *cs)
  401. {
  402. return read_c0_count();
  403. @@ -27,6 +83,8 @@
  404. if (!cpu_has_counter || !mips_hpt_frequency)
  405. return -ENXIO;
  406. + setup_hres_sched_clock(mips_hpt_frequency);
  407. +
  408. /* Calculate a somewhat reasonable rating value */
  409. clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
  410. diff -Nur linux-2.6.36.orig/arch/mips/kernel/time.c linux-2.6.36/arch/mips/kernel/time.c
  411. --- linux-2.6.36.orig/arch/mips/kernel/time.c 2010-10-20 22:30:22.000000000 +0200
  412. +++ linux-2.6.36/arch/mips/kernel/time.c 2010-12-17 23:12:59.000000000 +0100
  413. @@ -119,6 +119,11 @@
  414. void __init time_init(void)
  415. {
  416. +#ifdef CONFIG_HR_SCHED_CLOCK
  417. + if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
  418. + write_c0_count(0);
  419. +#endif
  420. +
  421. plat_time_init();
  422. if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
  423. diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cmdline.c linux-2.6.36/arch/mips/loongson/common/cmdline.c
  424. --- linux-2.6.36.orig/arch/mips/loongson/common/cmdline.c 2010-10-20 22:30:22.000000000 +0200
  425. +++ linux-2.6.36/arch/mips/loongson/common/cmdline.c 2010-12-17 23:12:59.000000000 +0100
  426. @@ -17,10 +17,15 @@
  427. * Free Software Foundation; either version 2 of the License, or (at your
  428. * option) any later version.
  429. */
  430. +#include <linux/module.h>
  431. #include <asm/bootinfo.h>
  432. #include <loongson.h>
  433. +/* the kernel command line copied from arcs_cmdline */
  434. +char loongson_cmdline[COMMAND_LINE_SIZE];
  435. +EXPORT_SYMBOL(loongson_cmdline);
  436. +
  437. void __init prom_init_cmdline(void)
  438. {
  439. int prom_argc;
  440. @@ -50,4 +55,26 @@
  441. strcat(arcs_cmdline, " root=/dev/hda1");
  442. prom_init_machtype();
  443. +
  444. + /* append machine specific command line */
  445. + switch (mips_machtype) {
  446. + case MACH_LEMOTE_LL2F:
  447. + if ((strstr(arcs_cmdline, "video=")) == NULL)
  448. + strcat(arcs_cmdline, " video=sisfb:1360x768-16@60");
  449. + break;
  450. + case MACH_LEMOTE_FL2F:
  451. + if ((strstr(arcs_cmdline, "ide_core.ignore_cable=")) == NULL)
  452. + strcat(arcs_cmdline, " ide_core.ignore_cable=0");
  453. + break;
  454. + case MACH_LEMOTE_ML2F7:
  455. + /* Mengloong-2F has a 800x480 screen */
  456. + if ((strstr(arcs_cmdline, "vga=")) == NULL)
  457. + strcat(arcs_cmdline, " vga=0x313");
  458. + break;
  459. + default:
  460. + break;
  461. + }
  462. +
  463. + /* copy arcs_cmdline into loongson_cmdline */
  464. + strncpy(loongson_cmdline, arcs_cmdline, COMMAND_LINE_SIZE);
  465. }
  466. diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_acc.c
  467. --- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c 2010-10-20 22:30:22.000000000 +0200
  468. +++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_acc.c 2010-12-17 23:12:59.000000000 +0100
  469. @@ -18,7 +18,7 @@
  470. void pci_acc_write_reg(int reg, u32 value)
  471. {
  472. - u32 hi = 0, lo = value;
  473. + u32 hi, lo;
  474. switch (reg) {
  475. case PCI_COMMAND:
  476. @@ -66,75 +66,73 @@
  477. u32 pci_acc_read_reg(int reg)
  478. {
  479. u32 hi, lo;
  480. - u32 conf_data = 0;
  481. + u32 cfg = 0;
  482. switch (reg) {
  483. case PCI_VENDOR_ID:
  484. - conf_data =
  485. - CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
  486. + cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID,
  487. + CS5536_VENDOR_ID);
  488. break;
  489. case PCI_COMMAND:
  490. _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
  491. if (((lo & 0xfff00000) || (hi & 0x000000ff))
  492. && ((hi & 0xf0000000) == 0xa0000000))
  493. - conf_data |= PCI_COMMAND_IO;
  494. + cfg |= PCI_COMMAND_IO;
  495. _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
  496. if ((lo & 0x300) == 0x300)
  497. - conf_data |= PCI_COMMAND_MASTER;
  498. + cfg |= PCI_COMMAND_MASTER;
  499. break;
  500. case PCI_STATUS:
  501. - conf_data |= PCI_STATUS_66MHZ;
  502. - conf_data |= PCI_STATUS_FAST_BACK;
  503. + cfg |= PCI_STATUS_66MHZ;
  504. + cfg |= PCI_STATUS_FAST_BACK;
  505. _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  506. if (lo & SB_PARE_ERR_FLAG)
  507. - conf_data |= PCI_STATUS_PARITY;
  508. - conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
  509. + cfg |= PCI_STATUS_PARITY;
  510. + cfg |= PCI_STATUS_DEVSEL_MEDIUM;
  511. break;
  512. case PCI_CLASS_REVISION:
  513. _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
  514. - conf_data = lo & 0x000000ff;
  515. - conf_data |= (CS5536_ACC_CLASS_CODE << 8);
  516. + cfg = lo & 0x000000ff;
  517. + cfg |= (CS5536_ACC_CLASS_CODE << 8);
  518. break;
  519. case PCI_CACHE_LINE_SIZE:
  520. - conf_data =
  521. - CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  522. - PCI_NORMAL_LATENCY_TIMER);
  523. + cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  524. + PCI_NORMAL_LATENCY_TIMER);
  525. break;
  526. case PCI_BAR0_REG:
  527. _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  528. if (lo & SOFT_BAR_ACC_FLAG) {
  529. - conf_data = CS5536_ACC_RANGE |
  530. + cfg = CS5536_ACC_RANGE |
  531. PCI_BASE_ADDRESS_SPACE_IO;
  532. lo &= ~SOFT_BAR_ACC_FLAG;
  533. _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  534. } else {
  535. _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
  536. - conf_data = (hi & 0x000000ff) << 12;
  537. - conf_data |= (lo & 0xfff00000) >> 20;
  538. - conf_data |= 0x01;
  539. - conf_data &= ~0x02;
  540. + cfg = (hi & 0x000000ff) << 12;
  541. + cfg |= (lo & 0xfff00000) >> 20;
  542. + cfg |= 0x01;
  543. + cfg &= ~0x02;
  544. }
  545. break;
  546. case PCI_CARDBUS_CIS:
  547. - conf_data = PCI_CARDBUS_CIS_POINTER;
  548. + cfg = PCI_CARDBUS_CIS_POINTER;
  549. break;
  550. case PCI_SUBSYSTEM_VENDOR_ID:
  551. - conf_data =
  552. - CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
  553. + cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID,
  554. + CS5536_SUB_VENDOR_ID);
  555. break;
  556. case PCI_ROM_ADDRESS:
  557. - conf_data = PCI_EXPANSION_ROM_BAR;
  558. + cfg = PCI_EXPANSION_ROM_BAR;
  559. break;
  560. case PCI_CAPABILITY_LIST:
  561. - conf_data = PCI_CAPLIST_USB_POINTER;
  562. + cfg = PCI_CAPLIST_USB_POINTER;
  563. break;
  564. case PCI_INTERRUPT_LINE:
  565. - conf_data =
  566. - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
  567. + cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
  568. break;
  569. default:
  570. break;
  571. }
  572. - return conf_data;
  573. + return cfg;
  574. }
  575. diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ehci.c
  576. --- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2010-10-20 22:30:22.000000000 +0200
  577. +++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2010-12-17 23:12:59.000000000 +0100
  578. @@ -18,7 +18,7 @@
  579. void pci_ehci_write_reg(int reg, u32 value)
  580. {
  581. - u32 hi = 0, lo = value;
  582. + u32 hi, lo;
  583. switch (reg) {
  584. case PCI_COMMAND:
  585. @@ -78,83 +78,81 @@
  586. u32 pci_ehci_read_reg(int reg)
  587. {
  588. - u32 conf_data = 0;
  589. + u32 cfg = 0;
  590. u32 hi, lo;
  591. switch (reg) {
  592. case PCI_VENDOR_ID:
  593. - conf_data =
  594. - CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
  595. + cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID,
  596. + CS5536_VENDOR_ID);
  597. break;
  598. case PCI_COMMAND:
  599. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  600. if (hi & PCI_COMMAND_MASTER)
  601. - conf_data |= PCI_COMMAND_MASTER;
  602. + cfg |= PCI_COMMAND_MASTER;
  603. if (hi & PCI_COMMAND_MEMORY)
  604. - conf_data |= PCI_COMMAND_MEMORY;
  605. + cfg |= PCI_COMMAND_MEMORY;
  606. break;
  607. case PCI_STATUS:
  608. - conf_data |= PCI_STATUS_66MHZ;
  609. - conf_data |= PCI_STATUS_FAST_BACK;
  610. + cfg |= PCI_STATUS_66MHZ;
  611. + cfg |= PCI_STATUS_FAST_BACK;
  612. _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  613. if (lo & SB_PARE_ERR_FLAG)
  614. - conf_data |= PCI_STATUS_PARITY;
  615. - conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
  616. + cfg |= PCI_STATUS_PARITY;
  617. + cfg |= PCI_STATUS_DEVSEL_MEDIUM;
  618. break;
  619. case PCI_CLASS_REVISION:
  620. _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
  621. - conf_data = lo & 0x000000ff;
  622. - conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
  623. + cfg = lo & 0x000000ff;
  624. + cfg |= (CS5536_EHCI_CLASS_CODE << 8);
  625. break;
  626. case PCI_CACHE_LINE_SIZE:
  627. - conf_data =
  628. - CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  629. - PCI_NORMAL_LATENCY_TIMER);
  630. + cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  631. + PCI_NORMAL_LATENCY_TIMER);
  632. break;
  633. case PCI_BAR0_REG:
  634. _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  635. if (lo & SOFT_BAR_EHCI_FLAG) {
  636. - conf_data = CS5536_EHCI_RANGE |
  637. + cfg = CS5536_EHCI_RANGE |
  638. PCI_BASE_ADDRESS_SPACE_MEMORY;
  639. lo &= ~SOFT_BAR_EHCI_FLAG;
  640. _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  641. } else {
  642. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  643. - conf_data = lo & 0xfffff000;
  644. + cfg = lo & 0xfffff000;
  645. }
  646. break;
  647. case PCI_CARDBUS_CIS:
  648. - conf_data = PCI_CARDBUS_CIS_POINTER;
  649. + cfg = PCI_CARDBUS_CIS_POINTER;
  650. break;
  651. case PCI_SUBSYSTEM_VENDOR_ID:
  652. - conf_data =
  653. - CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
  654. + cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID,
  655. + CS5536_SUB_VENDOR_ID);
  656. break;
  657. case PCI_ROM_ADDRESS:
  658. - conf_data = PCI_EXPANSION_ROM_BAR;
  659. + cfg = PCI_EXPANSION_ROM_BAR;
  660. break;
  661. case PCI_CAPABILITY_LIST:
  662. - conf_data = PCI_CAPLIST_USB_POINTER;
  663. + cfg = PCI_CAPLIST_USB_POINTER;
  664. break;
  665. case PCI_INTERRUPT_LINE:
  666. - conf_data =
  667. - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
  668. + cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
  669. break;
  670. case PCI_EHCI_LEGSMIEN_REG:
  671. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  672. - conf_data = (hi & 0x003f0000) >> 16;
  673. + cfg = (hi & 0x003f0000) >> 16;
  674. break;
  675. case PCI_EHCI_LEGSMISTS_REG:
  676. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  677. - conf_data = (hi & 0x3f000000) >> 24;
  678. + cfg = (hi & 0x3f000000) >> 24;
  679. break;
  680. case PCI_EHCI_FLADJ_REG:
  681. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  682. - conf_data = hi & 0x00003f00;
  683. + cfg = hi & 0x00003f00;
  684. break;
  685. default:
  686. break;
  687. }
  688. - return conf_data;
  689. + return cfg;
  690. }
  691. diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ide.c
  692. --- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c 2010-10-20 22:30:22.000000000 +0200
  693. +++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ide.c 2010-12-17 23:12:59.000000000 +0100
  694. @@ -18,7 +18,7 @@
  695. void pci_ide_write_reg(int reg, u32 value)
  696. {
  697. - u32 hi = 0, lo = value;
  698. + u32 hi, lo;
  699. switch (reg) {
  700. case PCI_COMMAND:
  701. @@ -72,26 +72,16 @@
  702. _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
  703. }
  704. break;
  705. - case PCI_IDE_DTC_REG:
  706. - _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
  707. - lo = value;
  708. - _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
  709. - break;
  710. - case PCI_IDE_CAST_REG:
  711. - _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
  712. - lo = value;
  713. - _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
  714. - break;
  715. - case PCI_IDE_ETC_REG:
  716. - _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
  717. - lo = value;
  718. - _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
  719. - break;
  720. - case PCI_IDE_PM_REG:
  721. - _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
  722. - lo = value;
  723. - _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
  724. - break;
  725. +#define SET_PCI_IDE_REG(r) \
  726. + case PCI_IDE_##r##_REG: \
  727. + _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &lo); \
  728. + lo = value; \
  729. + _wrmsr(IDE_MSR_REG(IDE_##r), hi, lo); \
  730. + break;
  731. + SET_PCI_IDE_REG(DTC)
  732. + SET_PCI_IDE_REG(CAST)
  733. + SET_PCI_IDE_REG(ETC)
  734. + SET_PCI_IDE_REG(PM)
  735. default:
  736. break;
  737. }
  738. @@ -99,94 +89,82 @@
  739. u32 pci_ide_read_reg(int reg)
  740. {
  741. - u32 conf_data = 0;
  742. + u32 cfg = 0;
  743. u32 hi, lo;
  744. switch (reg) {
  745. case PCI_VENDOR_ID:
  746. - conf_data =
  747. - CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
  748. + cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID,
  749. + CS5536_VENDOR_ID);
  750. break;
  751. case PCI_COMMAND:
  752. _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
  753. if (lo & 0xfffffff0)
  754. - conf_data |= PCI_COMMAND_IO;
  755. + cfg |= PCI_COMMAND_IO;
  756. _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
  757. if ((lo & 0x30) == 0x30)
  758. - conf_data |= PCI_COMMAND_MASTER;
  759. + cfg |= PCI_COMMAND_MASTER;
  760. break;
  761. case PCI_STATUS:
  762. - conf_data |= PCI_STATUS_66MHZ;
  763. - conf_data |= PCI_STATUS_FAST_BACK;
  764. + cfg |= PCI_STATUS_66MHZ;
  765. + cfg |= PCI_STATUS_FAST_BACK;
  766. _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  767. if (lo & SB_PARE_ERR_FLAG)
  768. - conf_data |= PCI_STATUS_PARITY;
  769. - conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
  770. + cfg |= PCI_STATUS_PARITY;
  771. + cfg |= PCI_STATUS_DEVSEL_MEDIUM;
  772. break;
  773. case PCI_CLASS_REVISION:
  774. _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
  775. - conf_data = lo & 0x000000ff;
  776. - conf_data |= (CS5536_IDE_CLASS_CODE << 8);
  777. + cfg = lo & 0x000000ff;
  778. + cfg |= (CS5536_IDE_CLASS_CODE << 8);
  779. break;
  780. case PCI_CACHE_LINE_SIZE:
  781. _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
  782. hi &= 0x000000f8;
  783. - conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
  784. + cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
  785. break;
  786. case PCI_BAR4_REG:
  787. _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  788. if (lo & SOFT_BAR_IDE_FLAG) {
  789. - conf_data = CS5536_IDE_RANGE |
  790. + cfg = CS5536_IDE_RANGE |
  791. PCI_BASE_ADDRESS_SPACE_IO;
  792. lo &= ~SOFT_BAR_IDE_FLAG;
  793. _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  794. } else {
  795. _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
  796. - conf_data = lo & 0xfffffff0;
  797. - conf_data |= 0x01;
  798. - conf_data &= ~0x02;
  799. + cfg = lo & 0xfffffff0;
  800. + cfg |= 0x01;
  801. + cfg &= ~0x02;
  802. }
  803. break;
  804. case PCI_CARDBUS_CIS:
  805. - conf_data = PCI_CARDBUS_CIS_POINTER;
  806. + cfg = PCI_CARDBUS_CIS_POINTER;
  807. break;
  808. case PCI_SUBSYSTEM_VENDOR_ID:
  809. - conf_data =
  810. - CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
  811. + cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID,
  812. + CS5536_SUB_VENDOR_ID);
  813. break;
  814. case PCI_ROM_ADDRESS:
  815. - conf_data = PCI_EXPANSION_ROM_BAR;
  816. + cfg = PCI_EXPANSION_ROM_BAR;
  817. break;
  818. case PCI_CAPABILITY_LIST:
  819. - conf_data = PCI_CAPLIST_POINTER;
  820. + cfg = PCI_CAPLIST_POINTER;
  821. break;
  822. case PCI_INTERRUPT_LINE:
  823. - conf_data =
  824. - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
  825. - break;
  826. - case PCI_IDE_CFG_REG:
  827. - _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
  828. - conf_data = lo;
  829. - break;
  830. - case PCI_IDE_DTC_REG:
  831. - _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
  832. - conf_data = lo;
  833. - break;
  834. - case PCI_IDE_CAST_REG:
  835. - _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
  836. - conf_data = lo;
  837. - break;
  838. - case PCI_IDE_ETC_REG:
  839. - _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
  840. - conf_data = lo;
  841. - break;
  842. - case PCI_IDE_PM_REG:
  843. - _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
  844. - conf_data = lo;
  845. + cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
  846. break;
  847. +#define GET_PCI_IDE_REG(r) \
  848. + case PCI_IDE_##r##_REG: \
  849. + _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &cfg); \
  850. + break;
  851. + GET_PCI_IDE_REG(CFG)
  852. + GET_PCI_IDE_REG(DTC)
  853. + GET_PCI_IDE_REG(CAST)
  854. + GET_PCI_IDE_REG(ETC)
  855. + GET_PCI_IDE_REG(PM)
  856. default:
  857. break;
  858. }
  859. - return conf_data;
  860. + return cfg;
  861. }
  862. diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ohci.c
  863. --- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2010-10-20 22:30:22.000000000 +0200
  864. +++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2010-12-17 23:12:59.000000000 +0100
  865. @@ -18,7 +18,7 @@
  866. void pci_ohci_write_reg(int reg, u32 value)
  867. {
  868. - u32 hi = 0, lo = value;
  869. + u32 hi, lo;
  870. switch (reg) {
  871. case PCI_COMMAND:
  872. @@ -73,77 +73,75 @@
  873. u32 pci_ohci_read_reg(int reg)
  874. {
  875. - u32 conf_data = 0;
  876. + u32 cfg = 0;
  877. u32 hi, lo;
  878. switch (reg) {
  879. case PCI_VENDOR_ID:
  880. - conf_data =
  881. - CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
  882. + cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID,
  883. + CS5536_VENDOR_ID);
  884. break;
  885. case PCI_COMMAND:
  886. _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
  887. if (hi & PCI_COMMAND_MASTER)
  888. - conf_data |= PCI_COMMAND_MASTER;
  889. + cfg |= PCI_COMMAND_MASTER;
  890. if (hi & PCI_COMMAND_MEMORY)
  891. - conf_data |= PCI_COMMAND_MEMORY;
  892. + cfg |= PCI_COMMAND_MEMORY;
  893. break;
  894. case PCI_STATUS:
  895. - conf_data |= PCI_STATUS_66MHZ;
  896. - conf_data |= PCI_STATUS_FAST_BACK;
  897. + cfg |= PCI_STATUS_66MHZ;
  898. + cfg |= PCI_STATUS_FAST_BACK;
  899. _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  900. if (lo & SB_PARE_ERR_FLAG)
  901. - conf_data |= PCI_STATUS_PARITY;
  902. - conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
  903. + cfg |= PCI_STATUS_PARITY;
  904. + cfg |= PCI_STATUS_DEVSEL_MEDIUM;
  905. break;
  906. case PCI_CLASS_REVISION:
  907. _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
  908. - conf_data = lo & 0x000000ff;
  909. - conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
  910. + cfg = lo & 0x000000ff;
  911. + cfg |= (CS5536_OHCI_CLASS_CODE << 8);
  912. break;
  913. case PCI_CACHE_LINE_SIZE:
  914. - conf_data =
  915. - CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  916. - PCI_NORMAL_LATENCY_TIMER);
  917. + cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  918. + PCI_NORMAL_LATENCY_TIMER);
  919. break;
  920. case PCI_BAR0_REG:
  921. _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  922. if (lo & SOFT_BAR_OHCI_FLAG) {
  923. - conf_data = CS5536_OHCI_RANGE |
  924. + cfg = CS5536_OHCI_RANGE |
  925. PCI_BASE_ADDRESS_SPACE_MEMORY;
  926. lo &= ~SOFT_BAR_OHCI_FLAG;
  927. _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  928. } else {
  929. _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
  930. - conf_data = lo & 0xffffff00;
  931. - conf_data &= ~0x0000000f; /* 32bit mem */
  932. + cfg = lo & 0xffffff00;
  933. + cfg &= ~0x0000000f; /* 32bit mem */
  934. }
  935. break;
  936. case PCI_CARDBUS_CIS:
  937. - conf_data = PCI_CARDBUS_CIS_POINTER;
  938. + cfg = PCI_CARDBUS_CIS_POINTER;
  939. break;
  940. case PCI_SUBSYSTEM_VENDOR_ID:
  941. - conf_data =
  942. - CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
  943. + cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID,
  944. + CS5536_SUB_VENDOR_ID);
  945. break;
  946. case PCI_ROM_ADDRESS:
  947. - conf_data = PCI_EXPANSION_ROM_BAR;
  948. + cfg = PCI_EXPANSION_ROM_BAR;
  949. break;
  950. case PCI_CAPABILITY_LIST:
  951. - conf_data = PCI_CAPLIST_USB_POINTER;
  952. + cfg = PCI_CAPLIST_USB_POINTER;
  953. break;
  954. case PCI_INTERRUPT_LINE:
  955. - conf_data =
  956. - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
  957. + cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
  958. break;
  959. case PCI_OHCI_INT_REG:
  960. _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
  961. if ((lo & 0x00000f00) == CS5536_USB_INTR)
  962. - conf_data = 1;
  963. + cfg = 1;
  964. break;
  965. default:
  966. break;
  967. }
  968. - return conf_data;
  969. + return cfg;
  970. }
  971. diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/mtd.c linux-2.6.36/arch/mips/loongson/common/mtd.c
  972. --- linux-2.6.36.orig/arch/mips/loongson/common/mtd.c 1970-01-01 01:00:00.000000000 +0100
  973. +++ linux-2.6.36/arch/mips/loongson/common/mtd.c 2010-12-17 23:12:59.000000000 +0100
  974. @@ -0,0 +1,91 @@
  975. +/*
  976. + * Driver for flushing/dumping ROM of PMON on loongson family machines
  977. + *
  978. + * Copyright (C) 2008-2009 Lemote Inc.
  979. + * Author: Yan Hua <yanh@lemote.com>
  980. + *
  981. + * This program is free software; you can redistribute it and/or modify it
  982. + * under the terms of the GNU General Public License as published by the
  983. + * Free Software Foundation; either version 2 of the License, or (at your
  984. + * option) any later version.
  985. + */
  986. +
  987. +#include <linux/module.h>
  988. +#include <linux/types.h>
  989. +#include <linux/kernel.h>
  990. +#include <linux/init.h>
  991. +#include <linux/mtd/mtd.h>
  992. +#include <linux/mtd/map.h>
  993. +#include <linux/mtd/partitions.h>
  994. +
  995. +#include <asm/io.h>
  996. +
  997. +#include <loongson.h>
  998. +
  999. +#define FLASH_PHYS_ADDR LOONGSON_BOOT_BASE
  1000. +#define FLASH_SIZE 0x080000
  1001. +
  1002. +#define FLASH_PARTITION0_ADDR 0x00000000
  1003. +#define FLASH_PARTITION0_SIZE 0x00080000
  1004. +
  1005. +struct map_info flash_map = {
  1006. + .name = "flash device",
  1007. + .size = FLASH_SIZE,
  1008. + .bankwidth = 1,
  1009. +};
  1010. +
  1011. +struct mtd_partition flash_parts[] = {
  1012. + {
  1013. + .name = "Bootloader",
  1014. + .offset = FLASH_PARTITION0_ADDR,
  1015. + .size = FLASH_PARTITION0_SIZE},
  1016. +};
  1017. +
  1018. +#define PARTITION_COUNT ARRAY_SIZE(flash_parts)
  1019. +
  1020. +static struct mtd_info *mymtd;
  1021. +
  1022. +int __init init_flash(void)
  1023. +{
  1024. + printk(KERN_NOTICE "flash device: %x at %x\n",
  1025. + FLASH_SIZE, FLASH_PHYS_ADDR);
  1026. +
  1027. + flash_map.phys = FLASH_PHYS_ADDR;
  1028. + flash_map.virt = ioremap(FLASH_PHYS_ADDR, FLASH_SIZE);
  1029. +
  1030. + if (!flash_map.virt) {
  1031. + printk(KERN_NOTICE "Failed to ioremap\n");
  1032. + return -EIO;
  1033. + }
  1034. +
  1035. + simple_map_init(&flash_map);
  1036. +
  1037. + mymtd = do_map_probe("cfi_probe", &flash_map);
  1038. + if (mymtd) {
  1039. + add_mtd_partitions(mymtd, flash_parts, PARTITION_COUNT);
  1040. + printk(KERN_NOTICE "pmon flash device initialized\n");
  1041. + return 0;
  1042. + }
  1043. +
  1044. + iounmap((void *)flash_map.virt);
  1045. + return -ENXIO;
  1046. +}
  1047. +
  1048. +static void __exit cleanup_flash(void)
  1049. +{
  1050. + if (mymtd) {
  1051. + del_mtd_partitions(mymtd);
  1052. + map_destroy(mymtd);
  1053. + }
  1054. + if (flash_map.virt) {
  1055. + iounmap((void *)flash_map.virt);
  1056. + flash_map.virt = 0;
  1057. + }
  1058. +}
  1059. +
  1060. +module_init(init_flash);
  1061. +module_exit(cleanup_flash);
  1062. +
  1063. +MODULE_LICENSE("GPL");
  1064. +MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
  1065. +MODULE_DESCRIPTION("MTD driver for pmon flushing/dumping");
  1066. diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/Makefile linux-2.6.36/arch/mips/loongson/lemote-2f/Makefile
  1067. --- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/Makefile 2010-10-20 22:30:22.000000000 +0200
  1068. +++ linux-2.6.36/arch/mips/loongson/lemote-2f/Makefile 2010-12-17 23:12:59.000000000 +0100
  1069. @@ -2,7 +2,7 @@
  1070. # Makefile for lemote loongson2f family machines
  1071. #
  1072. -obj-y += machtype.o irq.o reset.o ec_kb3310b.o
  1073. +obj-y += machtype.o irq.o reset.o ec_kb3310b.o platform.o
  1074. #
  1075. # Suspend Support
  1076. diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.c linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.c
  1077. --- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.c 2010-10-20 22:30:22.000000000 +0200
  1078. +++ linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.c 2010-12-17 23:12:59.000000000 +0100
  1079. @@ -14,7 +14,7 @@
  1080. #include <linux/spinlock.h>
  1081. #include <linux/delay.h>
  1082. -#include "ec_kb3310b.h"
  1083. +#include <ec_kb3310b.h>
  1084. static DEFINE_SPINLOCK(index_access_lock);
  1085. static DEFINE_SPINLOCK(port_access_lock);
  1086. @@ -78,12 +78,9 @@
  1087. spin_unlock_irqrestore(&port_access_lock, flags);
  1088. if (timeout <= 0) {
  1089. - printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
  1090. + pr_err("%s: deadable error : timeout...\n", __func__);
  1091. ret = -EINVAL;
  1092. - } else
  1093. - printk(KERN_INFO
  1094. - "(%x/%d)ec issued command %d status : 0x%x\n",
  1095. - timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
  1096. + }
  1097. return ret;
  1098. }
  1099. @@ -118,8 +115,7 @@
  1100. udelay(EC_REG_DELAY);
  1101. }
  1102. if (timeout <= 0) {
  1103. - pr_info("%s: get event number timeout.\n", __func__);
  1104. -
  1105. + pr_err("%s: get event number timeout.\n", __func__);
  1106. return -EINVAL;
  1107. }
  1108. value = inb(EC_DAT_PORT);
  1109. diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.h linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.h
  1110. --- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.h 2010-10-20 22:30:22.000000000 +0200
  1111. +++ linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.h 1970-01-01 01:00:00.000000000 +0100
  1112. @@ -1,188 +0,0 @@
  1113. -/*
  1114. - * KB3310B Embedded Controller
  1115. - *
  1116. - * Copyright (C) 2008 Lemote Inc.
  1117. - * Author: liujl <liujl@lemote.com>, 2008-03-14
  1118. - *
  1119. - * This program is free software; you can redistribute it and/or modify
  1120. - * it under the terms of the GNU General Public License as published by
  1121. - * the Free Software Foundation; either version 2 of the License, or
  1122. - * (at your option) any later version.
  1123. - */
  1124. -
  1125. -#ifndef _EC_KB3310B_H
  1126. -#define _EC_KB3310B_H
  1127. -
  1128. -extern unsigned char ec_read(unsigned short addr);
  1129. -extern void ec_write(unsigned short addr, unsigned char val);
  1130. -extern int ec_query_seq(unsigned char cmd);
  1131. -extern int ec_query_event_num(void);
  1132. -extern int ec_get_event_num(void);
  1133. -
  1134. -typedef int (*sci_handler) (int status);
  1135. -extern sci_handler yeeloong_report_lid_status;
  1136. -
  1137. -#define SCI_IRQ_NUM 0x0A
  1138. -
  1139. -/*
  1140. - * The following registers are determined by the EC index configuration.
  1141. - * 1, fill the PORT_HIGH as EC register high part.
  1142. - * 2, fill the PORT_LOW as EC register low part.
  1143. - * 3, fill the PORT_DATA as EC register write data or get the data from it.
  1144. - */
  1145. -#define EC_IO_PORT_HIGH 0x0381
  1146. -#define EC_IO_PORT_LOW 0x0382
  1147. -#define EC_IO_PORT_DATA 0x0383
  1148. -
  1149. -/*
  1150. - * EC delay time is 500us for register and status access
  1151. - */
  1152. -#define EC_REG_DELAY 500 /* unit : us */
  1153. -#define EC_CMD_TIMEOUT 0x1000
  1154. -
  1155. -/*
  1156. - * EC access port for SCI communication
  1157. - */
  1158. -#define EC_CMD_PORT 0x66
  1159. -#define EC_STS_PORT 0x66
  1160. -#define EC_DAT_PORT 0x62
  1161. -#define CMD_INIT_IDLE_MODE 0xdd
  1162. -#define CMD_EXIT_IDLE_MODE 0xdf
  1163. -#define CMD_INIT_RESET_MODE 0xd8
  1164. -#define CMD_REBOOT_SYSTEM 0x8c
  1165. -#define CMD_GET_EVENT_NUM 0x84
  1166. -#define CMD_PROGRAM_PIECE 0xda
  1167. -
  1168. -/* temperature & fan registers */
  1169. -#define REG_TEMPERATURE_VALUE 0xF458
  1170. -#define REG_FAN_AUTO_MAN_SWITCH 0xF459
  1171. -#define BIT_FAN_AUTO 0
  1172. -#define BIT_FAN_MANUAL 1
  1173. -#define REG_FAN_CONTROL 0xF4D2
  1174. -#define BIT_FAN_CONTROL_ON (1 << 0)
  1175. -#define BIT_FAN_CONTROL_OFF (0 << 0)
  1176. -#define REG_FAN_STATUS 0xF4DA
  1177. -#define BIT_FAN_STATUS_ON (1 << 0)
  1178. -#define BIT_FAN_STATUS_OFF (0 << 0)
  1179. -#define REG_FAN_SPEED_HIGH 0xFE22
  1180. -#define REG_FAN_SPEED_LOW 0xFE23
  1181. -#define REG_FAN_SPEED_LEVEL 0xF4CC
  1182. -/* fan speed divider */
  1183. -#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/
  1184. -
  1185. -/* battery registers */
  1186. -#define REG_BAT_DESIGN_CAP_HIGH 0xF77D
  1187. -#define REG_BAT_DESIGN_CAP_LOW 0xF77E
  1188. -#define REG_BAT_FULLCHG_CAP_HIGH 0xF780
  1189. -#define REG_BAT_FULLCHG_CAP_LOW 0xF781
  1190. -#define REG_BAT_DESIGN_VOL_HIGH 0xF782
  1191. -#define REG_BAT_DESIGN_VOL_LOW 0xF783
  1192. -#define REG_BAT_CURRENT_HIGH 0xF784
  1193. -#define REG_BAT_CURRENT_LOW 0xF785
  1194. -#define REG_BAT_VOLTAGE_HIGH 0xF786
  1195. -#define REG_BAT_VOLTAGE_LOW 0xF787
  1196. -#define REG_BAT_TEMPERATURE_HIGH 0xF788
  1197. -#define REG_BAT_TEMPERATURE_LOW 0xF789
  1198. -#define REG_BAT_RELATIVE_CAP_HIGH 0xF492
  1199. -#define REG_BAT_RELATIVE_CAP_LOW 0xF493
  1200. -#define REG_BAT_VENDOR 0xF4C4
  1201. -#define FLAG_BAT_VENDOR_SANYO 0x01
  1202. -#define FLAG_BAT_VENDOR_SIMPLO 0x02
  1203. -#define REG_BAT_CELL_COUNT 0xF4C6
  1204. -#define FLAG_BAT_CELL_3S1P 0x03
  1205. -#define FLAG_BAT_CELL_3S2P 0x06
  1206. -#define REG_BAT_CHARGE 0xF4A2
  1207. -#define FLAG_BAT_CHARGE_DISCHARGE 0x01
  1208. -#define FLAG_BAT_CHARGE_CHARGE 0x02
  1209. -#define FLAG_BAT_CHARGE_ACPOWER 0x00
  1210. -#define REG_BAT_STATUS 0xF4B0
  1211. -#define BIT_BAT_STATUS_LOW (1 << 5)
  1212. -#define BIT_BAT_STATUS_DESTROY (1 << 2)
  1213. -#define BIT_BAT_STATUS_FULL (1 << 1)
  1214. -#define BIT_BAT_STATUS_IN (1 << 0)
  1215. -#define REG_BAT_CHARGE_STATUS 0xF4B1
  1216. -#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2)
  1217. -#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1)
  1218. -#define REG_BAT_STATE 0xF482
  1219. -#define BIT_BAT_STATE_CHARGING (1 << 1)
  1220. -#define BIT_BAT_STATE_DISCHARGING (1 << 0)
  1221. -#define REG_BAT_POWER 0xF440
  1222. -#define BIT_BAT_POWER_S3 (1 << 2)
  1223. -#define BIT_BAT_POWER_ON (1 << 1)
  1224. -#define BIT_BAT_POWER_ACIN (1 << 0)
  1225. -
  1226. -/* other registers */
  1227. -/* Audio: rd/wr */
  1228. -#define REG_AUDIO_VOLUME 0xF46C
  1229. -#define REG_AUDIO_MUTE 0xF4E7
  1230. -#define REG_AUDIO_BEEP 0xF4D0
  1231. -/* USB port power or not: rd/wr */
  1232. -#define REG_USB0_FLAG 0xF461
  1233. -#define REG_USB1_FLAG 0xF462
  1234. -#define REG_USB2_FLAG 0xF463
  1235. -#define BIT_USB_FLAG_ON 1
  1236. -#define BIT_USB_FLAG_OFF 0
  1237. -/* LID */
  1238. -#define REG_LID_DETECT 0xF4BD
  1239. -#define BIT_LID_DETECT_ON 1
  1240. -#define BIT_LID_DETECT_OFF 0
  1241. -/* CRT */
  1242. -#define REG_CRT_DETECT 0xF4AD
  1243. -#define BIT_CRT_DETECT_PLUG 1
  1244. -#define BIT_CRT_DETECT_UNPLUG 0
  1245. -/* LCD backlight brightness adjust: 9 levels */
  1246. -#define REG_DISPLAY_BRIGHTNESS 0xF4F5
  1247. -/* Black screen Status */
  1248. -#define BIT_DISPLAY_LCD_ON 1
  1249. -#define BIT_DISPLAY_LCD_OFF 0
  1250. -/* LCD backlight control: off/restore */
  1251. -#define REG_BACKLIGHT_CTRL 0xF7BD
  1252. -#define BIT_BACKLIGHT_ON 1
  1253. -#define BIT_BACKLIGHT_OFF 0
  1254. -/* Reset the machine auto-clear: rd/wr */
  1255. -#define REG_RESET 0xF4EC
  1256. -#define BIT_RESET_ON 1
  1257. -/* Light the led: rd/wr */
  1258. -#define REG_LED 0xF4C8
  1259. -#define BIT_LED_RED_POWER (1 << 0)
  1260. -#define BIT_LED_ORANGE_POWER (1 << 1)
  1261. -#define BIT_LED_GREEN_CHARGE (1 << 2)
  1262. -#define BIT_LED_RED_CHARGE (1 << 3)
  1263. -#define BIT_LED_NUMLOCK (1 << 4)
  1264. -/* Test led mode, all led on/off */
  1265. -#define REG_LED_TEST 0xF4C2
  1266. -#define BIT_LED_TEST_IN 1
  1267. -#define BIT_LED_TEST_OUT 0
  1268. -/* Camera on/off */
  1269. -#define REG_CAMERA_STATUS 0xF46A
  1270. -#define BIT_CAMERA_STATUS_ON 1
  1271. -#define BIT_CAMERA_STATUS_OFF 0
  1272. -#define REG_CAMERA_CONTROL 0xF7B7
  1273. -#define BIT_CAMERA_CONTROL_OFF 0
  1274. -#define BIT_CAMERA_CONTROL_ON 1
  1275. -/* Wlan Status */
  1276. -#define REG_WLAN 0xF4FA
  1277. -#define BIT_WLAN_ON 1
  1278. -#define BIT_WLAN_OFF 0
  1279. -#define REG_DISPLAY_LCD 0xF79F
  1280. -
  1281. -/* SCI Event Number from EC */
  1282. -enum {
  1283. - EVENT_LID = 0x23, /* LID open/close */
  1284. - EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */
  1285. - EVENT_SLEEP, /* Fn+F1 for entering sleep mode */
  1286. - EVENT_OVERTEMP, /* Over-temperature happened */
  1287. - EVENT_CRT_DETECT, /* CRT is connected */
  1288. - EVENT_CAMERA, /* Camera on/off */
  1289. - EVENT_USB_OC2, /* USB2 Over Current occurred */
  1290. - EVENT_USB_OC0, /* USB0 Over Current occurred */
  1291. - EVENT_BLACK_SCREEN, /* Turn on/off backlight */
  1292. - EVENT_AUDIO_MUTE, /* Mute on/off */
  1293. - EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
  1294. - EVENT_AC_BAT, /* AC & Battery relative issue */
  1295. - EVENT_AUDIO_VOLUME, /* Volume adjust */
  1296. - EVENT_WLAN, /* Wlan on/off */
  1297. - EVENT_END
  1298. -};
  1299. -
  1300. -#endif /* !_EC_KB3310B_H */
  1301. diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/platform.c linux-2.6.36/arch/mips/loongson/lemote-2f/platform.c
  1302. --- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/platform.c 1970-01-01 01:00:00.000000000 +0100
  1303. +++ linux-2.6.36/arch/mips/loongson/lemote-2f/platform.c 2010-12-17 23:12:59.000000000 +0100
  1304. @@ -0,0 +1,48 @@
  1305. +/*
  1306. + * Copyright (C) 2009 Lemote Inc.
  1307. + * Author: Wu Zhangjin, wuzhangjin@gmail.com
  1308. + *
  1309. + * This program is free software; you can redistribute it and/or modify it
  1310. + * under the terms of the GNU General Public License as published by the
  1311. + * Free Software Foundation; either version 2 of the License, or (at your
  1312. + * option) any later version.
  1313. + */
  1314. +
  1315. +#include <linux/err.h>
  1316. +#include <linux/platform_device.h>
  1317. +
  1318. +#include <asm/bootinfo.h>
  1319. +
  1320. +static struct platform_device yeeloong_pdev = {
  1321. + .name = "yeeloong_laptop",
  1322. + .id = -1,
  1323. +};
  1324. +
  1325. +static struct platform_device lynloong_pdev = {
  1326. + .name = "lynloong_pc",
  1327. + .id = -1,
  1328. +};
  1329. +
  1330. +static int __init lemote2f_platform_init(void)
  1331. +{
  1332. + struct platform_device *pdev = NULL;
  1333. +
  1334. + switch (mips_machtype) {
  1335. + case MACH_LEMOTE_YL2F89:
  1336. + pdev = &yeeloong_pdev;
  1337. + break;
  1338. + case MACH_LEMOTE_LL2F:
  1339. + pdev = &lynloong_pdev;
  1340. + break;
  1341. + default:
  1342. + break;
  1343. +
  1344. + }
  1345. +
  1346. + if (pdev != NULL)
  1347. + return platform_device_register(pdev);
  1348. +
  1349. + return -ENODEV;
  1350. +}
  1351. +
  1352. +arch_initcall(lemote2f_platform_init);
  1353. diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/pm.c linux-2.6.36/arch/mips/loongson/lemote-2f/pm.c
  1354. --- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/pm.c 2010-10-20 22:30:22.000000000 +0200
  1355. +++ linux-2.6.36/arch/mips/loongson/lemote-2f/pm.c 2010-12-17 23:12:59.000000000 +0100
  1356. @@ -23,7 +23,7 @@
  1357. #include <loongson.h>
  1358. #include <cs5536/cs5536_mfgpt.h>
  1359. -#include "ec_kb3310b.h"
  1360. +#include <ec_kb3310b.h>
  1361. #define I8042_KBD_IRQ 1
  1362. #define I8042_CTR_KBDINT 0x01
  1363. @@ -100,7 +100,7 @@
  1364. if (irq < 0)
  1365. return 0;
  1366. - printk(KERN_INFO "%s: irq = %d\n", __func__, irq);
  1367. + pr_info("%s: irq = %d\n", __func__, irq);
  1368. if (irq == I8042_KBD_IRQ)
  1369. return 1;
  1370. diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/reset.c linux-2.6.36/arch/mips/loongson/lemote-2f/reset.c
  1371. --- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/reset.c 2010-10-20 22:30:22.000000000 +0200
  1372. +++ linux-2.6.36/arch/mips/loongson/lemote-2f/reset.c 2010-12-17 23:12:59.000000000 +0100
  1373. @@ -20,7 +20,7 @@
  1374. #include <loongson.h>
  1375. #include <cs5536/cs5536.h>
  1376. -#include "ec_kb3310b.h"
  1377. +#include <ec_kb3310b.h>
  1378. static void reset_cpu(void)
  1379. {
  1380. diff -Nur linux-2.6.36.orig/arch/mips/mm/dma-default.c linux-2.6.36/arch/mips/mm/dma-default.c
  1381. --- linux-2.6.36.orig/arch/mips/mm/dma-default.c 2010-10-20 22:30:22.000000000 +0200
  1382. +++ linux-2.6.36/arch/mips/mm/dma-default.c 2010-12-17 23:12:59.000000000 +0100
  1383. @@ -380,3 +380,16 @@
  1384. }
  1385. EXPORT_SYMBOL(dma_cache_sync);
  1386. +
  1387. +int __weak dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
  1388. + void *cpu_addr, dma_addr_t handle, size_t size)
  1389. +{
  1390. + struct page *pg;
  1391. + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1392. + cpu_addr = (void *)dma_addr_to_virt(dev, handle);
  1393. + pg = virt_to_page(cpu_addr);
  1394. + return remap_pfn_range(vma, vma->vm_start,
  1395. + page_to_pfn(pg) + vma->vm_pgoff,
  1396. + size, vma->vm_page_prot);
  1397. +}
  1398. +EXPORT_SYMBOL(dma_mmap_coherent);
  1399. diff -Nur linux-2.6.36.orig/drivers/ide/ide-iops.c linux-2.6.36/drivers/ide/ide-iops.c
  1400. --- linux-2.6.36.orig/drivers/ide/ide-iops.c 2010-10-20 22:30:22.000000000 +0200
  1401. +++ linux-2.6.36/drivers/ide/ide-iops.c 2010-12-17 23:12:59.000000000 +0100
  1402. @@ -27,6 +27,8 @@
  1403. #include <asm/uaccess.h>
  1404. #include <asm/io.h>
  1405. +#include <asm/bootinfo.h>
  1406. +
  1407. void SELECT_MASK(ide_drive_t *drive, int mask)
  1408. {
  1409. const struct ide_port_ops *port_ops = drive->hwif->port_ops;
  1410. @@ -300,6 +302,9 @@
  1411. {
  1412. const char **list, *m = (char *)&drive->id[ATA_ID_PROD];
  1413. + if (mips_machtype != MACH_LEMOTE_YL2F89)
  1414. + return;
  1415. +
  1416. for (list = nien_quirk_list; *list != NULL; list++)
  1417. if (strstr(m, *list) != NULL) {
  1418. drive->dev_flags |= IDE_DFLAG_NIEN_QUIRK;
  1419. diff -Nur linux-2.6.36.orig/drivers/platform/Kconfig linux-2.6.36/drivers/platform/Kconfig
  1420. --- linux-2.6.36.orig/drivers/platform/Kconfig 2010-10-20 22:30:22.000000000 +0200
  1421. +++ linux-2.6.36/drivers/platform/Kconfig 2010-12-17 23:12:59.000000000 +0100
  1422. @@ -1,3 +1,7 @@
  1423. if X86
  1424. source "drivers/platform/x86/Kconfig"
  1425. endif
  1426. +
  1427. +if MIPS
  1428. +source "drivers/platform/mips/Kconfig"
  1429. +endif
  1430. diff -Nur linux-2.6.36.orig/drivers/platform/Makefile linux-2.6.36/drivers/platform/Makefile
  1431. --- linux-2.6.36.orig/drivers/platform/Makefile 2010-10-20 22:30:22.000000000 +0200
  1432. +++ linux-2.6.36/drivers/platform/Makefile 2010-12-17 23:12:59.000000000 +0100
  1433. @@ -3,3 +3,4 @@
  1434. #
  1435. obj-$(CONFIG_X86) += x86/
  1436. +obj-$(CONFIG_MIPS) += mips/
  1437. diff -Nur linux-2.6.36.orig/drivers/platform/mips/Kconfig linux-2.6.36/drivers/platform/mips/Kconfig
  1438. --- linux-2.6.36.orig/drivers/platform/mips/Kconfig 1970-01-01 01:00:00.000000000 +0100
  1439. +++ linux-2.6.36/drivers/platform/mips/Kconfig 2010-12-17 23:12:59.000000000 +0100
  1440. @@ -0,0 +1,43 @@
  1441. +#
  1442. +# MIPS Platform Specific Drivers
  1443. +#
  1444. +
  1445. +menuconfig MIPS_PLATFORM_DEVICES
  1446. + bool "MIPS Platform Specific Device Drivers"
  1447. + default y
  1448. + help
  1449. + Say Y here to get to see options for device drivers of various
  1450. + MIPS platforms, including vendor-specific netbook/laptop/pc extension
  1451. + drivers. This option alone does not add any kernel code.
  1452. +
  1453. + If you say N, all options in this submenu will be skipped and disabled.
  1454. +
  1455. +if MIPS_PLATFORM_DEVICES
  1456. +
  1457. +config LEMOTE_YEELOONG2F
  1458. + tristate "Lemote YeeLoong Laptop"
  1459. + depends on LEMOTE_MACH2F
  1460. + select BACKLIGHT_CLASS_DEVICE
  1461. + select POWER_SUPPLY
  1462. + select HWMON
  1463. + select VIDEO_OUTPUT_CONTROL
  1464. + select INPUT_SPARSEKMAP
  1465. + depends on INPUT
  1466. + help
  1467. + YeeLoong netbook is a mini laptop made by Lemote, which is basically
  1468. + compatible to FuLoong2F mini PC, but it has an extra Embedded
  1469. + Controller(kb3310b) for battery, hotkey, backlight, temperature and
  1470. + fan management.
  1471. +
  1472. +config LEMOTE_LYNLOONG2F
  1473. + tristate "Lemote LynLoong PC"
  1474. + depends on LEMOTE_MACH2F
  1475. + select BACKLIGHT_CLASS_DEVICE
  1476. + select VIDEO_OUTPUT_CONTROL
  1477. + help
  1478. + LynLoong PC is an AllINONE machine made by Lemote, which is basically
  1479. + compatible to FuLoong2F Mini PC, the only difference is that it has a
  1480. + size-fixed screen: 1360x768 with sisfb video driver. and also, it has
  1481. + its own specific suspend support.
  1482. +
  1483. +endif # MIPS_PLATFORM_DEVICES
  1484. diff -Nur linux-2.6.36.orig/drivers/platform/mips/Makefile linux-2.6.36/drivers/platform/mips/Makefile
  1485. --- linux-2.6.36.orig/drivers/platform/mips/Makefile 1970-01-01 01:00:00.000000000 +0100
  1486. +++ linux-2.6.36/drivers/platform/mips/Makefile 2010-12-17 23:12:59.000000000 +0100
  1487. @@ -0,0 +1,7 @@
  1488. +#
  1489. +# Makefile for MIPS Platform-Specific Drivers
  1490. +#
  1491. +
  1492. +obj-$(CONFIG_LEMOTE_YEELOONG2F) += yeeloong_laptop.o
  1493. +
  1494. +obj-$(CONFIG_LEMOTE_LYNLOONG2F) += lynloong_pc.o
  1495. diff -Nur linux-2.6.36.orig/drivers/platform/mips/lynloong_pc.c linux-2.6.36/drivers/platform/mips/lynloong_pc.c
  1496. --- linux-2.6.36.orig/drivers/platform/mips/lynloong_pc.c 1970-01-01 01:00:00.000000000 +0100
  1497. +++ linux-2.6.36/drivers/platform/mips/lynloong_pc.c 2010-12-17 23:12:59.000000000 +0100
  1498. @@ -0,0 +1,513 @@
  1499. +/*
  1500. + * Driver for LynLoong PC extras
  1501. + *
  1502. + * Copyright (C) 2009 Lemote Inc.
  1503. + * Author: Wu Zhangjin <wuzhangjin@gmail.com>, Xiang Yu <xiangy@lemote.com>
  1504. + *
  1505. + * This program is free software; you can redistribute it and/or modify
  1506. + * it under the terms of the GNU General Public License version 2 as
  1507. + * published by the Free Software Foundation.
  1508. + */
  1509. +
  1510. +#include <linux/err.h>
  1511. +#include <linux/platform_device.h>
  1512. +#include <linux/backlight.h> /* for backlight subdriver */
  1513. +#include <linux/fb.h>
  1514. +#include <linux/video_output.h> /* for video output subdriver */
  1515. +#include <linux/delay.h> /* for suspend support */
  1516. +
  1517. +#include <cs5536/cs5536.h>
  1518. +#include <cs5536/cs5536_mfgpt.h>
  1519. +
  1520. +#include <loongson.h>
  1521. +
  1522. +static u32 gpio_base, mfgpt_base;
  1523. +
  1524. +static void set_gpio_reg_high(int gpio, int reg)
  1525. +{
  1526. + u32 val;
  1527. +
  1528. + val = inl(gpio_base + reg);
  1529. + val |= (1 << gpio);
  1530. + val &= ~(1 << (16 + gpio));
  1531. + outl(val, gpio_base + reg);
  1532. + mmiowb();
  1533. +}
  1534. +
  1535. +static void set_gpio_reg_low(int gpio, int reg)
  1536. +{
  1537. + u32 val;
  1538. +
  1539. + val = inl(gpio_base + reg);
  1540. + val |= (1 << (16 + gpio));
  1541. + val &= ~(1 << gpio);
  1542. + outl(val, gpio_base + reg);
  1543. + mmiowb();
  1544. +}
  1545. +
  1546. +static void set_gpio_output_low(int gpio)
  1547. +{
  1548. + set_gpio_reg_high(gpio, GPIOL_OUT_EN);
  1549. + set_gpio_reg_low(gpio, GPIOL_OUT_VAL);
  1550. +}
  1551. +
  1552. +static void set_gpio_output_high(int gpio)
  1553. +{
  1554. + set_gpio_reg_high(gpio, GPIOL_OUT_EN);
  1555. + set_gpio_reg_high(gpio, GPIOL_OUT_VAL);
  1556. +}
  1557. +
  1558. +/* backlight subdriver */
  1559. +
  1560. +#define MAX_BRIGHTNESS 100
  1561. +#define DEFAULT_BRIGHTNESS 50
  1562. +#define MIN_BRIGHTNESS 0
  1563. +static unsigned int level;
  1564. +
  1565. +DEFINE_SPINLOCK(backlight_lock);
  1566. +/* Tune the brightness */
  1567. +static void setup_mfgpt2(void)
  1568. +{
  1569. + unsigned long flags;
  1570. +
  1571. + spin_lock_irqsave(&backlight_lock, flags);
  1572. +
  1573. + /* Set MFGPT2 comparator 1,2 */
  1574. + outw(MAX_BRIGHTNESS-level, MFGPT2_CMP1);
  1575. + outw(MAX_BRIGHTNESS, MFGPT2_CMP2);
  1576. + /* Clear MFGPT2 UP COUNTER */
  1577. + outw(0, MFGPT2_CNT);
  1578. + /* Enable counter, compare mode, 32k */
  1579. + outw(0x8280, MFGPT2_SETUP);
  1580. +
  1581. + spin_unlock_irqrestore(&backlight_lock, flags);
  1582. +}
  1583. +
  1584. +static int lynloong_set_brightness(struct backlight_device *bd)
  1585. +{
  1586. + level = (bd->props.fb_blank == FB_BLANK_UNBLANK &&
  1587. + bd->props.power == FB_BLANK_UNBLANK) ?
  1588. + bd->props.brightness : 0;
  1589. +
  1590. + if (level > MAX_BRIGHTNESS)
  1591. + level = MAX_BRIGHTNESS;
  1592. + else if (level < MIN_BRIGHTNESS)
  1593. + level = MIN_BRIGHTNESS;
  1594. +
  1595. + setup_mfgpt2();
  1596. +
  1597. + return 0;
  1598. +}
  1599. +
  1600. +static int lynloong_get_brightness(struct backlight_device *bd)
  1601. +{
  1602. + return level;
  1603. +}
  1604. +
  1605. +static struct backlight_ops backlight_ops = {
  1606. + .get_brightness = lynloong_get_brightness,
  1607. + .update_status = lynloong_set_brightness,
  1608. +};
  1609. +
  1610. +static struct backlight_device *lynloong_backlight_dev;
  1611. +
  1612. +static int lynloong_backlight_init(void)
  1613. +{
  1614. + int ret;
  1615. + u32 hi;
  1616. + struct backlight_properties props;
  1617. +
  1618. + /* Get gpio_base */
  1619. + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &gpio_base);
  1620. + /* Get mfgpt_base */
  1621. + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &hi, &mfgpt_base);
  1622. + /* Get gpio_base */
  1623. + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &gpio_base);
  1624. +
  1625. + /* Select for mfgpt */
  1626. + set_gpio_reg_high(7, GPIOL_OUT_AUX1_SEL);
  1627. + /* Enable brightness controlling */
  1628. + set_gpio_output_high(7);
  1629. +
  1630. + memset(&props, 0, sizeof(struct backlight_properties));
  1631. + props.max_brightness = MAX_BRIGHTNESS;
  1632. + lynloong_backlight_dev = backlight_device_register("backlight0", NULL,
  1633. + NULL, &backlight_ops, &props);
  1634. +
  1635. + if (IS_ERR(lynloong_backlight_dev)) {
  1636. + ret = PTR_ERR(lynloong_backlight_dev);
  1637. + return ret;
  1638. + }
  1639. +
  1640. + lynloong_backlight_dev->props.brightness = DEFAULT_BRIGHTNESS;
  1641. + backlight_update_status(lynloong_backlight_dev);
  1642. +
  1643. + return 0;
  1644. +}
  1645. +
  1646. +static void lynloong_backlight_exit(void)
  1647. +{
  1648. + if (lynloong_backlight_dev) {
  1649. + backlight_device_unregister(lynloong_backlight_dev);
  1650. + lynloong_backlight_dev = NULL;
  1651. + }
  1652. + /* Disable brightness controlling */
  1653. + set_gpio_output_low(7);
  1654. +}
  1655. +
  1656. +/* video output driver */
  1657. +static int vo_status = 1;
  1658. +
  1659. +static int lcd_video_output_get(struct output_device *od)
  1660. +{
  1661. + return vo_status;
  1662. +}
  1663. +
  1664. +static int lcd_video_output_set(struct output_device *od)
  1665. +{
  1666. + int i;
  1667. + unsigned long status;
  1668. +
  1669. + status = !!od->request_state;
  1670. +
  1671. + if (status == 0) {
  1672. + /* Set the current status as off */
  1673. + vo_status = 0;
  1674. + /* Turn off the backlight */
  1675. + set_gpio_output_low(11);
  1676. + for (i = 0; i < 0x500; i++)
  1677. + delay();
  1678. + /* Turn off the LCD */
  1679. + set_gpio_output_high(8);
  1680. + } else {
  1681. + /* Turn on the LCD */
  1682. + set_gpio_output_low(8);
  1683. + for (i = 0; i < 0x500; i++)
  1684. + delay();
  1685. + /* Turn on the backlight */
  1686. + set_gpio_output_high(11);
  1687. + /* Set the current status as on */
  1688. + vo_status = 1;
  1689. + }
  1690. +
  1691. + return 0;
  1692. +}
  1693. +
  1694. +static struct output_properties lcd_output_properties = {
  1695. + .set_state = lcd_video_output_set,
  1696. + .get_status = lcd_video_output_get,
  1697. +};
  1698. +
  1699. +static struct output_device *lcd_output_dev;
  1700. +
  1701. +static void lynloong_lcd_vo_set(int status)
  1702. +{
  1703. + lcd_output_dev->request_state = status;
  1704. + lcd_video_output_set(lcd_output_dev);
  1705. +}
  1706. +
  1707. +static int lynloong_vo_init(void)
  1708. +{
  1709. + int ret;
  1710. +
  1711. + /* Register video output device: lcd */
  1712. + lcd_output_dev = video_output_register("LCD", NULL, NULL,
  1713. + &lcd_output_properties);
  1714. +
  1715. + if (IS_ERR(lcd_output_dev)) {
  1716. + ret = PTR_ERR(lcd_output_dev);
  1717. + lcd_output_dev = NULL;
  1718. + return ret;
  1719. + }
  1720. + /* Ensure LCD is on by default */
  1721. + lynloong_lcd_vo_set(1);
  1722. +
  1723. + return 0;
  1724. +}
  1725. +
  1726. +static void lynloong_vo_exit(void)
  1727. +{
  1728. + if (lcd_output_dev) {
  1729. + video_output_unregister(lcd_output_dev);
  1730. + lcd_output_dev = NULL;
  1731. + }
  1732. +}
  1733. +
  1734. +/* suspend support */
  1735. +
  1736. +#ifdef CONFIG_PM
  1737. +
  1738. +static u32 smb_base;
  1739. +
  1740. +/* I2C operations */
  1741. +
  1742. +static int i2c_wait(void)
  1743. +{
  1744. + char c;
  1745. + int i;
  1746. +
  1747. + udelay(1000);
  1748. + for (i = 0; i < 20; i++) {
  1749. + c = inb(smb_base | SMB_STS);
  1750. + if (c & (SMB_STS_BER | SMB_STS_NEGACK))
  1751. + return -1;
  1752. + if (c & SMB_STS_SDAST)
  1753. + return 0;
  1754. + udelay(100);
  1755. + }
  1756. + return -2;
  1757. +}
  1758. +
  1759. +static void i2c_read_single(int addr, int regNo, char *value)
  1760. +{
  1761. + unsigned char c;
  1762. +
  1763. + /* Start condition */
  1764. + c = inb(smb_base | SMB_CTRL1);
  1765. + outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1);
  1766. + i2c_wait();
  1767. +
  1768. + /* Send slave address */
  1769. + outb(addr & 0xfe, smb_base | SMB_SDA);
  1770. + i2c_wait();
  1771. +
  1772. + /* Acknowledge smbus */
  1773. + c = inb(smb_base | SMB_CTRL1);
  1774. + outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1);
  1775. +
  1776. + /* Send register index */
  1777. + outb(regNo, smb_base | SMB_SDA);
  1778. + i2c_wait();
  1779. +
  1780. + /* Acknowledge smbus */
  1781. + c = inb(smb_base | SMB_CTRL1);
  1782. + outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1);
  1783. +
  1784. + /* Start condition again */
  1785. + c = inb(smb_base | SMB_CTRL1);
  1786. + outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1);
  1787. + i2c_wait();
  1788. +
  1789. + /* Send salve address again */
  1790. + outb(1 | addr, smb_base | SMB_SDA);
  1791. + i2c_wait();
  1792. +
  1793. + /* Acknowledge smbus */
  1794. + c = inb(smb_base | SMB_CTRL1);
  1795. + outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1);
  1796. +
  1797. + /* Read data */
  1798. + *value = inb(smb_base | SMB_SDA);
  1799. +
  1800. + /* Stop condition */
  1801. + outb(SMB_CTRL1_STOP, smb_base | SMB_CTRL1);
  1802. + i2c_wait();
  1803. +}
  1804. +
  1805. +static void i2c_write_single(int addr, int regNo, char value)
  1806. +{
  1807. + unsigned char c;
  1808. +
  1809. + /* Start condition */
  1810. + c = inb(smb_base | SMB_CTRL1);
  1811. + outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1);
  1812. + i2c_wait();
  1813. + /* Send slave address */
  1814. + outb(addr & 0xfe, smb_base | SMB_SDA);
  1815. + i2c_wait();;
  1816. +
  1817. + /* Send register index */
  1818. + outb(regNo, smb_base | SMB_SDA);
  1819. + i2c_wait();
  1820. +
  1821. + /* Write data */
  1822. + outb(value, smb_base | SMB_SDA);
  1823. + i2c_wait();
  1824. + /* Stop condition */
  1825. + outb(SMB_CTRL1_STOP, smb_base | SMB_CTRL1);
  1826. + i2c_wait();
  1827. +}
  1828. +
  1829. +static void stop_clock(int clk_reg, int clk_sel)
  1830. +{
  1831. + u8 value;
  1832. +
  1833. + i2c_read_single(0xd3, clk_reg, &value);
  1834. + value &= ~(1 << clk_sel);
  1835. + i2c_write_single(0xd2, clk_reg, value);
  1836. +}
  1837. +
  1838. +static void enable_clock(int clk_reg, int clk_sel)
  1839. +{
  1840. + u8 value;
  1841. +
  1842. + i2c_read_single(0xd3, clk_reg, &value);
  1843. + value |= (1 << clk_sel);
  1844. + i2c_write_single(0xd2, clk_reg, value);
  1845. +}
  1846. +
  1847. +static char cached_clk_freq;
  1848. +static char cached_pci_fixed_freq;
  1849. +
  1850. +static void decrease_clk_freq(void)
  1851. +{
  1852. + char value;
  1853. +
  1854. + i2c_read_single(0xd3, 1, &value);
  1855. + cached_clk_freq = value;
  1856. +
  1857. + /* Select frequency by software */
  1858. + value |= (1 << 1);
  1859. + /* CPU, 3V66, PCI : 100, 66, 33(1) */
  1860. + value |= (1 << 2);
  1861. + i2c_write_single(0xd2, 1, value);
  1862. +
  1863. + /* Cache the pci frequency */
  1864. + i2c_read_single(0xd3, 14, &value);
  1865. + cached_pci_fixed_freq = value;
  1866. +
  1867. + /* Enable PCI fix mode */
  1868. + value |= (1 << 5);
  1869. + /* 3V66, PCI : 64MHz, 32MHz */
  1870. + value |= (1 << 3);
  1871. + i2c_write_single(0xd2, 14, value);
  1872. +
  1873. +}
  1874. +
  1875. +static void resume_clk_freq(void)
  1876. +{
  1877. + i2c_write_single(0xd2, 1, cached_clk_freq);
  1878. + i2c_write_single(0xd2, 14, cached_pci_fixed_freq);
  1879. +}
  1880. +
  1881. +static void stop_clocks(void)
  1882. +{
  1883. + /* CPU Clock Register */
  1884. + stop_clock(2, 5); /* not used */
  1885. + stop_clock(2, 6); /* not used */
  1886. + stop_clock(2, 7); /* not used */
  1887. +
  1888. + /* PCI Clock Register */
  1889. + stop_clock(3, 1); /* 8100 */
  1890. + stop_clock(3, 5); /* SIS */
  1891. + stop_clock(3, 0); /* not used */
  1892. + stop_clock(3, 6); /* not used */
  1893. +
  1894. + /* PCI 48M Clock Register */
  1895. + stop_clock(4, 6); /* USB grounding */
  1896. + stop_clock(4, 5); /* REF(5536_14M) */
  1897. +
  1898. + /* 3V66 Control Register */
  1899. + stop_clock(5, 0); /* VCH_CLK..., grounding */
  1900. +}
  1901. +
  1902. +static void enable_clocks(void)
  1903. +{
  1904. + enable_clock(3, 1); /* 8100 */
  1905. + enable_clock(3, 5); /* SIS */
  1906. +
  1907. + enable_clock(4, 6);
  1908. + enable_clock(4, 5); /* REF(5536_14M) */
  1909. +
  1910. + enable_clock(5, 0); /* VCH_CLOCK, grounding */
  1911. +}
  1912. +
  1913. +static int lynloong_suspend(struct device *dev)
  1914. +{
  1915. + /* Disable AMP */
  1916. + set_gpio_output_high(6);
  1917. + /* Turn off LCD */
  1918. + lynloong_lcd_vo_set(0);
  1919. +
  1920. + /* Stop the clocks of some devices */
  1921. + stop_clocks();
  1922. +
  1923. + /* Decrease the external clock frequency */
  1924. + decrease_clk_freq();
  1925. +
  1926. + return 0;
  1927. +}
  1928. +
  1929. +static int lynloong_resume(struct device *dev)
  1930. +{
  1931. + /* Turn on the LCD */
  1932. + lynloong_lcd_vo_set(1);
  1933. +
  1934. + /* Resume clock frequency, enable the relative clocks */
  1935. + resume_clk_freq();
  1936. + enable_clocks();
  1937. +
  1938. + /* Enable AMP */
  1939. + set_gpio_output_low(6);
  1940. +
  1941. + return 0;
  1942. +}
  1943. +
  1944. +static const SIMPLE_DEV_PM_OPS(lynloong_pm_ops, lynloong_suspend,
  1945. + lynloong_resume);
  1946. +#endif /* !CONFIG_PM */
  1947. +
  1948. +static struct platform_device_id platform_device_ids[] = {
  1949. + {
  1950. + .name = "lynloong_pc",
  1951. + },
  1952. + {}
  1953. +};
  1954. +
  1955. +MODULE_DEVICE_TABLE(platform, platform_device_ids);
  1956. +
  1957. +static struct platform_driver platform_driver = {
  1958. + .driver = {
  1959. + .name = "lynloong_pc",
  1960. + .owner = THIS_MODULE,
  1961. +#ifdef CONFIG_PM
  1962. + .pm = &lynloong_pm_ops,
  1963. +#endif
  1964. + },
  1965. + .id_table = platform_device_ids,
  1966. +};
  1967. +
  1968. +static int __init lynloong_init(void)
  1969. +{
  1970. + int ret;
  1971. +
  1972. + pr_info("Load LynLoong Platform Specific Driver.\n");
  1973. +
  1974. + /* Register platform stuff */
  1975. + ret = platform_driver_register(&platform_driver);
  1976. + if (ret) {
  1977. + pr_err("Fail to register lynloong platform driver.\n");
  1978. + return ret;
  1979. + }
  1980. +
  1981. + ret = lynloong_backlight_init();
  1982. + if (ret) {
  1983. + pr_err("Fail to register lynloong backlight driver.\n");
  1984. + return ret;
  1985. + }
  1986. +
  1987. + ret = lynloong_vo_init();
  1988. + if (ret) {
  1989. + pr_err("Fail to register lynloong backlight driver.\n");
  1990. + lynloong_vo_exit();
  1991. + return ret;
  1992. + }
  1993. +
  1994. + return 0;
  1995. +}
  1996. +
  1997. +static void __exit lynloong_exit(void)
  1998. +{
  1999. + lynloong_vo_exit();
  2000. + lynloong_backlight_exit();
  2001. + platform_driver_unregister(&platform_driver);
  2002. +
  2003. + pr_info("Unload LynLoong Platform Specific Driver.\n");
  2004. +}
  2005. +
  2006. +module_init(lynloong_init);
  2007. +module_exit(lynloong_exit);
  2008. +
  2009. +MODULE_AUTHOR("Wu Zhangjin <wuzhangjin@gmail.com>; Xiang Yu <xiangy@lemote.com>");
  2010. +MODULE_DESCRIPTION("LynLoong PC driver");
  2011. +MODULE_LICENSE("GPL");
  2012. diff -Nur linux-2.6.36.orig/drivers/platform/mips/yeeloong_ecrom.c linux-2.6.36/drivers/platform/mips/yeeloong_ecrom.c
  2013. --- linux-2.6.36.orig/drivers/platform/mips/yeeloong_ecrom.c 1970-01-01 01:00:00.000000000 +0100
  2014. +++ linux-2.6.36/drivers/platform/mips/yeeloong_ecrom.c 2010-12-17 23:12:59.000000000 +0100
  2015. @@ -0,0 +1,943 @@
  2016. +/*
  2017. + * Driver for flushing/dumping ROM of EC on YeeLoong laptop
  2018. + *
  2019. + * Copyright (C) 2009 Lemote Inc.
  2020. + * Author: liujl <liujl@lemote.com>
  2021. + *
  2022. + * NOTE :
  2023. + * The EC resources accessing and programming are supported.
  2024. + */
  2025. +
  2026. +#include <linux/proc_fs.h>
  2027. +#include <linux/miscdevice.h>
  2028. +#include <linux/init.h>
  2029. +#include <linux/delay.h>
  2030. +
  2031. +#include <ec_kb3310b.h>
  2032. +
  2033. +#define EC_MISC_DEV "ec_misc"
  2034. +#define EC_IOC_MAGIC 'E'
  2035. +
  2036. +/* ec registers range */
  2037. +#define EC_MAX_REGADDR 0xFFFF
  2038. +#define EC_MIN_REGADDR 0xF000
  2039. +#define EC_RAM_ADDR 0xF800
  2040. +
  2041. +/* version burned address */
  2042. +#define VER_ADDR 0xf7a1
  2043. +#define VER_MAX_SIZE 7
  2044. +#define EC_ROM_MAX_SIZE 0x10000
  2045. +
  2046. +/* ec internal register */
  2047. +#define REG_POWER_MODE 0xF710
  2048. +#define FLAG_NORMAL_MODE 0x00
  2049. +#define FLAG_IDLE_MODE 0x01
  2050. +#define FLAG_RESET_MODE 0x02
  2051. +
  2052. +/* ec update program flag */
  2053. +#define PROGRAM_FLAG_NONE 0x00
  2054. +#define PROGRAM_FLAG_IE 0x01
  2055. +#define PROGRAM_FLAG_ROM 0x02
  2056. +
  2057. +/* XBI relative registers */
  2058. +#define REG_XBISEG0 0xFEA0
  2059. +#define REG_XBISEG1 0xFEA1
  2060. +#define REG_XBIRSV2 0xFEA2
  2061. +#define REG_XBIRSV3 0xFEA3
  2062. +#define REG_XBIRSV4 0xFEA4
  2063. +#define REG_XBICFG 0xFEA5
  2064. +#define REG_XBICS 0xFEA6
  2065. +#define REG_XBIWE 0xFEA7
  2066. +#define REG_XBISPIA0 0xFEA8
  2067. +#define REG_XBISPIA1 0xFEA9
  2068. +#define REG_XBISPIA2 0xFEAA
  2069. +#define REG_XBISPIDAT 0xFEAB
  2070. +#define REG_XBISPICMD 0xFEAC
  2071. +#define REG_XBISPICFG 0xFEAD
  2072. +#define REG_XBISPIDATR 0xFEAE
  2073. +#define REG_XBISPICFG2 0xFEAF
  2074. +
  2075. +/* commands definition for REG_XBISPICMD */
  2076. +#define SPICMD_WRITE_STATUS 0x01
  2077. +#define SPICMD_BYTE_PROGRAM 0x02
  2078. +#define SPICMD_READ_BYTE 0x03
  2079. +#define SPICMD_WRITE_DISABLE 0x04
  2080. +#define SPICMD_READ_STATUS 0x05
  2081. +#define SPICMD_WRITE_ENABLE 0x06
  2082. +#define SPICMD_HIGH_SPEED_READ 0x0B
  2083. +#define SPICMD_POWER_DOWN 0xB9
  2084. +#define SPICMD_SST_EWSR 0x50
  2085. +#define SPICMD_SST_SEC_ERASE 0x20
  2086. +#define SPICMD_SST_BLK_ERASE 0x52
  2087. +#define SPICMD_SST_CHIP_ERASE 0x60
  2088. +#define SPICMD_FRDO 0x3B
  2089. +#define SPICMD_SEC_ERASE 0xD7
  2090. +#define SPICMD_BLK_ERASE 0xD8
  2091. +#define SPICMD_CHIP_ERASE 0xC7
  2092. +
  2093. +/* bits definition for REG_XBISPICFG */
  2094. +#define SPICFG_AUTO_CHECK 0x01
  2095. +#define SPICFG_SPI_BUSY 0x02
  2096. +#define SPICFG_DUMMY_READ 0x04
  2097. +#define SPICFG_EN_SPICMD 0x08
  2098. +#define SPICFG_LOW_SPICS 0x10
  2099. +#define SPICFG_EN_SHORT_READ 0x20
  2100. +#define SPICFG_EN_OFFSET_READ 0x40
  2101. +#define SPICFG_EN_FAST_READ 0x80
  2102. +
  2103. +/* watchdog timer registers */
  2104. +#define REG_WDTCFG 0xfe80
  2105. +#define REG_WDTPF 0xfe81
  2106. +#define REG_WDT 0xfe82
  2107. +
  2108. +/* lpc configure register */
  2109. +#define REG_LPCCFG 0xfe95
  2110. +
  2111. +/* 8051 reg */
  2112. +#define REG_PXCFG 0xff14
  2113. +
  2114. +/* Fan register in KB3310 */
  2115. +#define REG_ECFAN_SPEED_LEVEL 0xf4e4
  2116. +#define REG_ECFAN_SWITCH 0xf4d2
  2117. +
  2118. +/* the ec flash rom id number */
  2119. +#define EC_ROM_PRODUCT_ID_SPANSION 0x01
  2120. +#define EC_ROM_PRODUCT_ID_MXIC 0xC2
  2121. +#define EC_ROM_PRODUCT_ID_AMIC 0x37
  2122. +#define EC_ROM_PRODUCT_ID_EONIC 0x1C
  2123. +
  2124. +/* misc ioctl operations */
  2125. +#define IOCTL_RDREG _IOR(EC_IOC_MAGIC, 1, int)
  2126. +#define IOCTL_WRREG _IOW(EC_IOC_MAGIC, 2, int)
  2127. +#define IOCTL_READ_EC _IOR(EC_IOC_MAGIC, 3, int)
  2128. +#define IOCTL_PROGRAM_IE _IOW(EC_IOC_MAGIC, 4, int)
  2129. +#define IOCTL_PROGRAM_EC _IOW(EC_IOC_MAGIC, 5, int)
  2130. +
  2131. +/* start address for programming of EC content or IE */
  2132. +/* ec running code start address */
  2133. +#define EC_START_ADDR 0x00000000
  2134. +/* ec information element storing address */
  2135. +#define IE_START_ADDR 0x00020000
  2136. +
  2137. +/* EC state */
  2138. +#define EC_STATE_IDLE 0x00 /* ec in idle state */
  2139. +#define EC_STATE_BUSY 0x01 /* ec in busy state */
  2140. +
  2141. +/* timeout value for programming */
  2142. +#define EC_FLASH_TIMEOUT 0x1000 /* ec program timeout */
  2143. +/* command checkout timeout including cmd to port or state flag check */
  2144. +#define EC_CMD_TIMEOUT 0x1000
  2145. +#define EC_SPICMD_STANDARD_TIMEOUT (4 * 1000) /* unit : us */
  2146. +#define EC_MAX_DELAY_UNIT (10) /* every time for polling */
  2147. +#define SPI_FINISH_WAIT_TIME 10
  2148. +/* EC content max size */
  2149. +#define EC_CONTENT_MAX_SIZE (64 * 1024)
  2150. +#define IE_CONTENT_MAX_SIZE (0x100000 - IE_START_ADDR)
  2151. +
  2152. +/* the register operation access struct */
  2153. +struct ec_reg {
  2154. + u32 addr; /* the address of kb3310 registers */
  2155. + u8 val; /* the register value */
  2156. +};
  2157. +
  2158. +struct ec_info {
  2159. + u32 start_addr;
  2160. + u32 size;
  2161. + u8 *buf;
  2162. +};
  2163. +
  2164. +/* open for using rom protection action */
  2165. +#define EC_ROM_PROTECTION
  2166. +
  2167. +/* enable the chip reset mode */
  2168. +static int ec_init_reset_mode(void)
  2169. +{
  2170. + int timeout;
  2171. + unsigned char status = 0;
  2172. + int ret = 0;
  2173. +
  2174. + /* make chip goto reset mode */
  2175. + ret = ec_query_seq(CMD_INIT_RESET_MODE);
  2176. + if (ret < 0) {
  2177. + printk(KERN_ERR "ec init reset mode failed.\n");
  2178. + goto out;
  2179. + }
  2180. +
  2181. + /* make the action take active */
  2182. + timeout = EC_CMD_TIMEOUT;
  2183. + status = ec_read(REG_POWER_MODE) & FLAG_RESET_MODE;
  2184. + while (timeout--) {
  2185. + if (status) {
  2186. + udelay(EC_REG_DELAY);
  2187. + break;
  2188. + }
  2189. + status = ec_read(REG_POWER_MODE) & FLAG_RESET_MODE;
  2190. + udelay(EC_REG_DELAY);
  2191. + }
  2192. + if (timeout <= 0) {
  2193. + printk(KERN_ERR "ec rom fixup : can't check reset status.\n");
  2194. + ret = -EINVAL;
  2195. + } else
  2196. + printk(KERN_INFO "(%d/%d)reset 0xf710 : 0x%x\n", timeout,
  2197. + EC_CMD_TIMEOUT - timeout, status);
  2198. +
  2199. + /* set MCU to reset mode */
  2200. + udelay(EC_REG_DELAY);
  2201. + status = ec_read(REG_PXCFG);
  2202. + status |= (1 << 0);
  2203. + ec_write(REG_PXCFG, status);
  2204. + udelay(EC_REG_DELAY);
  2205. +
  2206. + /* disable FWH/LPC */
  2207. + udelay(EC_REG_DELAY);
  2208. + status = ec_read(REG_LPCCFG);
  2209. + status &= ~(1 << 7);
  2210. + ec_write(REG_LPCCFG, status);
  2211. + udelay(EC_REG_DELAY);
  2212. +
  2213. + printk(KERN_INFO "entering reset mode ok..............\n");
  2214. +
  2215. + out:
  2216. + return ret;
  2217. +}
  2218. +
  2219. +/* make ec exit from reset mode */
  2220. +static void ec_exit_reset_mode(void)
  2221. +{
  2222. + unsigned char regval;
  2223. +
  2224. + udelay(EC_REG_DELAY);
  2225. + regval = ec_read(REG_LPCCFG);
  2226. + regval |= (1 << 7);
  2227. + ec_write(REG_LPCCFG, regval);
  2228. + regval = ec_read(REG_PXCFG);
  2229. + regval &= ~(1 << 0);
  2230. + ec_write(REG_PXCFG, regval);
  2231. + printk(KERN_INFO "exit reset mode ok..................\n");
  2232. +
  2233. + return;
  2234. +}
  2235. +
  2236. +/* make ec disable WDD */
  2237. +static void ec_disable_WDD(void)
  2238. +{
  2239. + unsigned char status;
  2240. +
  2241. + udelay(EC_REG_DELAY);
  2242. + status = ec_read(REG_WDTCFG);
  2243. + ec_write(REG_WDTPF, 0x03);
  2244. + ec_write(REG_WDTCFG, (status & 0x80) | 0x48);
  2245. + printk(KERN_INFO "Disable WDD ok..................\n");
  2246. +
  2247. + return;
  2248. +}
  2249. +
  2250. +/* make ec enable WDD */
  2251. +static void ec_enable_WDD(void)
  2252. +{
  2253. + unsigned char status;
  2254. +
  2255. + udelay(EC_REG_DELAY);
  2256. + status = ec_read(REG_WDTCFG);
  2257. + ec_write(REG_WDT, 0x28); /* set WDT 5sec(0x28) */
  2258. + ec_write(REG_WDTCFG, (status & 0x80) | 0x03);
  2259. + printk(KERN_INFO "Enable WDD ok..................\n");
  2260. +
  2261. + return;
  2262. +}
  2263. +
  2264. +/* make ec goto idle mode */
  2265. +static int ec_init_idle_mode(void)
  2266. +{
  2267. + int timeout;
  2268. + unsigned char status = 0;
  2269. + int ret = 0;
  2270. +
  2271. + ec_query_seq(CMD_INIT_IDLE_MODE);
  2272. +
  2273. + /* make the action take active */
  2274. + timeout = EC_CMD_TIMEOUT;
  2275. + status = ec_read(REG_POWER_MODE) & FLAG_IDLE_MODE;
  2276. + while (timeout--) {
  2277. + if (status) {
  2278. + udelay(EC_REG_DELAY);
  2279. + break;
  2280. + }
  2281. + status = ec_read(REG_POWER_MODE) & FLAG_IDLE_MODE;
  2282. + udelay(EC_REG_DELAY);
  2283. + }
  2284. + if (timeout <= 0) {
  2285. + printk(KERN_ERR "ec rom fixup : can't check out the status.\n");
  2286. + ret = -EINVAL;
  2287. + } else
  2288. + printk(KERN_INFO "(%d/%d)0xf710 : 0x%x\n", timeout,
  2289. + EC_CMD_TIMEOUT - timeout, ec_read(REG_POWER_MODE));
  2290. +
  2291. + printk(KERN_INFO "entering idle mode ok...................\n");
  2292. +
  2293. + return ret;
  2294. +}
  2295. +
  2296. +/* make ec exit from idle mode */
  2297. +static int ec_exit_idle_mode(void)
  2298. +{
  2299. +
  2300. + ec_query_seq(CMD_EXIT_IDLE_MODE);
  2301. +
  2302. + printk(KERN_INFO "exit idle mode ok...................\n");
  2303. +
  2304. + return 0;
  2305. +}
  2306. +
  2307. +static int ec_instruction_cycle(void)
  2308. +{
  2309. + unsigned long timeout;
  2310. + int ret = 0;
  2311. +
  2312. + timeout = EC_FLASH_TIMEOUT;
  2313. + while (timeout-- >= 0) {
  2314. + if (!(ec_read(REG_XBISPICFG) & SPICFG_SPI_BUSY))
  2315. + break;
  2316. + }
  2317. + if (timeout <= 0) {
  2318. + printk(KERN_ERR
  2319. + "EC_INSTRUCTION_CYCLE : timeout for check flag.\n");
  2320. + ret = -EINVAL;
  2321. + goto out;
  2322. + }
  2323. +
  2324. + out:
  2325. + return ret;
  2326. +}
  2327. +
  2328. +/* To see if the ec is in busy state or not. */
  2329. +static inline int ec_flash_busy(unsigned long timeout)
  2330. +{
  2331. + /* assurance the first command be going to rom */
  2332. + if (ec_instruction_cycle() < 0)
  2333. + return EC_STATE_BUSY;
  2334. +#if 1
  2335. + timeout = timeout / EC_MAX_DELAY_UNIT;
  2336. + while (timeout-- > 0) {
  2337. + /* check the rom's status of busy flag */
  2338. + ec_write(REG_XBISPICMD, SPICMD_READ_STATUS);
  2339. + if (ec_instruction_cycle() < 0)
  2340. + return EC_STATE_BUSY;
  2341. + if ((ec_read(REG_XBISPIDAT) & 0x01) == 0x00)
  2342. + return EC_STATE_IDLE;
  2343. + udelay(EC_MAX_DELAY_UNIT);
  2344. + }
  2345. + if (timeout <= 0) {
  2346. + printk(KERN_ERR
  2347. + "EC_FLASH_BUSY : timeout for check rom flag.\n");
  2348. + return EC_STATE_BUSY;
  2349. + }
  2350. +#else
  2351. + /* check the rom's status of busy flag */
  2352. + ec_write(REG_XBISPICMD, SPICMD_READ_STATUS);
  2353. + if (ec_instruction_cycle() < 0)
  2354. + return EC_STATE_BUSY;
  2355. +
  2356. + timeout = timeout / EC_MAX_DELAY_UNIT;
  2357. + while (timeout-- > 0) {
  2358. + if ((ec_read(REG_XBISPIDAT) & 0x01) == 0x00)
  2359. + return EC_STATE_IDLE;
  2360. + udelay(EC_MAX_DELAY_UNIT);
  2361. + }
  2362. + if (timeout <= 0) {
  2363. + printk(KERN_ERR
  2364. + "EC_FLASH_BUSY : timeout for check rom flag.\n");
  2365. + return EC_STATE_BUSY;
  2366. + }
  2367. +#endif
  2368. +
  2369. + return EC_STATE_IDLE;
  2370. +}
  2371. +
  2372. +static int rom_instruction_cycle(unsigned char cmd)
  2373. +{
  2374. + unsigned long timeout = 0;
  2375. +
  2376. + switch (cmd) {
  2377. + case SPICMD_READ_STATUS:
  2378. + case SPICMD_WRITE_ENABLE:
  2379. + case SPICMD_WRITE_DISABLE:
  2380. + case SPICMD_READ_BYTE:
  2381. + case SPICMD_HIGH_SPEED_READ:
  2382. + timeout = 0;
  2383. + break;
  2384. + case SPICMD_WRITE_STATUS:
  2385. + timeout = 300 * 1000;
  2386. + break;
  2387. + case SPICMD_BYTE_PROGRAM:
  2388. + timeout = 5 * 1000;
  2389. + break;
  2390. + case SPICMD_SST_SEC_ERASE:
  2391. + case SPICMD_SEC_ERASE:
  2392. + timeout = 1000 * 1000;
  2393. + break;
  2394. + case SPICMD_SST_BLK_ERASE:
  2395. + case SPICMD_BLK_ERASE:
  2396. + timeout = 3 * 1000 * 1000;
  2397. + break;
  2398. + case SPICMD_SST_CHIP_ERASE:
  2399. + case SPICMD_CHIP_ERASE:
  2400. + timeout = 20 * 1000 * 1000;
  2401. + break;
  2402. + default:
  2403. + timeout = EC_SPICMD_STANDARD_TIMEOUT;
  2404. + }
  2405. + if (timeout == 0)
  2406. + return ec_instruction_cycle();
  2407. + if (timeout < EC_SPICMD_STANDARD_TIMEOUT)
  2408. + timeout = EC_SPICMD_STANDARD_TIMEOUT;
  2409. +
  2410. + return ec_flash_busy(timeout);
  2411. +}
  2412. +
  2413. +/* delay for start/stop action */
  2414. +static void delay_spi(int n)
  2415. +{
  2416. + while (n--)
  2417. + inb(EC_IO_PORT_HIGH);
  2418. +}
  2419. +
  2420. +/* start the action to spi rom function */
  2421. +static void ec_start_spi(void)
  2422. +{
  2423. + unsigned char val;
  2424. +
  2425. + delay_spi(SPI_FINISH_WAIT_TIME);
  2426. + val = ec_read(REG_XBISPICFG) | SPICFG_EN_SPICMD | SPICFG_AUTO_CHECK;
  2427. + ec_write(REG_XBISPICFG, val);
  2428. + delay_spi(SPI_FINISH_WAIT_TIME);
  2429. +}
  2430. +
  2431. +/* stop the action to spi rom function */
  2432. +static void ec_stop_spi(void)
  2433. +{
  2434. + unsigned char val;
  2435. +
  2436. + delay_spi(SPI_FINISH_WAIT_TIME);
  2437. + val =
  2438. + ec_read(REG_XBISPICFG) & (~(SPICFG_EN_SPICMD | SPICFG_AUTO_CHECK));
  2439. + ec_write(REG_XBISPICFG, val);
  2440. + delay_spi(SPI_FINISH_WAIT_TIME);
  2441. +}
  2442. +
  2443. +/* read one byte from xbi interface */
  2444. +static int ec_read_byte(unsigned int addr, unsigned char *byte)
  2445. +{
  2446. + int ret = 0;
  2447. +
  2448. + /* enable spicmd writing. */
  2449. + ec_start_spi();
  2450. +
  2451. + /* enable write spi flash */
  2452. + ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE);
  2453. + if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) {
  2454. + printk(KERN_ERR "EC_READ_BYTE : SPICMD_WRITE_ENABLE failed.\n");
  2455. + ret = -EINVAL;
  2456. + goto out;
  2457. + }
  2458. +
  2459. + /* write the address */
  2460. + ec_write(REG_XBISPIA2, (addr & 0xff0000) >> 16);
  2461. + ec_write(REG_XBISPIA1, (addr & 0x00ff00) >> 8);
  2462. + ec_write(REG_XBISPIA0, (addr & 0x0000ff) >> 0);
  2463. + /* start action */
  2464. + ec_write(REG_XBISPICMD, SPICMD_HIGH_SPEED_READ);
  2465. + if (rom_instruction_cycle(SPICMD_HIGH_SPEED_READ) == EC_STATE_BUSY) {
  2466. + printk(KERN_ERR
  2467. + "EC_READ_BYTE : SPICMD_HIGH_SPEED_READ failed.\n");
  2468. + ret = -EINVAL;
  2469. + goto out;
  2470. + }
  2471. +
  2472. + *byte = ec_read(REG_XBISPIDAT);
  2473. +
  2474. + out:
  2475. + /* disable spicmd writing. */
  2476. + ec_stop_spi();
  2477. +
  2478. + return ret;
  2479. +}
  2480. +
  2481. +/* write one byte to ec rom */
  2482. +static int ec_write_byte(unsigned int addr, unsigned char byte)
  2483. +{
  2484. + int ret = 0;
  2485. +
  2486. + /* enable spicmd writing. */
  2487. + ec_start_spi();
  2488. +
  2489. + /* enable write spi flash */
  2490. + ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE);
  2491. + if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) {
  2492. + printk(KERN_ERR
  2493. + "EC_WRITE_BYTE : SPICMD_WRITE_ENABLE failed.\n");
  2494. + ret = -EINVAL;
  2495. + goto out;
  2496. + }
  2497. +
  2498. + /* write the address */
  2499. + ec_write(REG_XBISPIA2, (addr & 0xff0000) >> 16);
  2500. + ec_write(REG_XBISPIA1, (addr & 0x00ff00) >> 8);
  2501. + ec_write(REG_XBISPIA0, (addr & 0x0000ff) >> 0);
  2502. + ec_write(REG_XBISPIDAT, byte);
  2503. + /* start action */
  2504. + ec_write(REG_XBISPICMD, SPICMD_BYTE_PROGRAM);
  2505. + if (rom_instruction_cycle(SPICMD_BYTE_PROGRAM) == EC_STATE_BUSY) {
  2506. + printk(KERN_ERR
  2507. + "EC_WRITE_BYTE : SPICMD_BYTE_PROGRAM failed.\n");
  2508. + ret = -EINVAL;
  2509. + goto out;
  2510. + }
  2511. +
  2512. + out:
  2513. + /* disable spicmd writing. */
  2514. + ec_stop_spi();
  2515. +
  2516. + return ret;
  2517. +}
  2518. +
  2519. +/* unprotect SPI ROM */
  2520. +/* EC_ROM_unprotect function code */
  2521. +static int EC_ROM_unprotect(void)
  2522. +{
  2523. + unsigned char status;
  2524. +
  2525. + /* enable write spi flash */
  2526. + ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE);
  2527. + if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) {
  2528. + printk(KERN_ERR
  2529. + "EC_UNIT_ERASE : SPICMD_WRITE_ENABLE failed.\n");
  2530. + return 1;
  2531. + }
  2532. +
  2533. + /* unprotect the status register of rom */
  2534. + ec_write(REG_XBISPICMD, SPICMD_READ_STATUS);
  2535. + if (rom_instruction_cycle(SPICMD_READ_STATUS) == EC_STATE_BUSY) {
  2536. + printk(KERN_ERR "EC_UNIT_ERASE : SPICMD_READ_STATUS failed.\n");
  2537. + return 1;
  2538. + }
  2539. + status = ec_read(REG_XBISPIDAT);
  2540. + ec_write(REG_XBISPIDAT, status & 0x02);
  2541. + if (ec_instruction_cycle() < 0) {
  2542. + printk(KERN_ERR "EC_UNIT_ERASE : write status value failed.\n");
  2543. + return 1;
  2544. + }
  2545. +
  2546. + ec_write(REG_XBISPICMD, SPICMD_WRITE_STATUS);
  2547. + if (rom_instruction_cycle(SPICMD_WRITE_STATUS) == EC_STATE_BUSY) {
  2548. + printk(KERN_ERR
  2549. + "EC_UNIT_ERASE : SPICMD_WRITE_STATUS failed.\n");
  2550. + return 1;
  2551. + }
  2552. +
  2553. + /* enable write spi flash */
  2554. + ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE);
  2555. + if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) {
  2556. + printk(KERN_ERR
  2557. + "EC_UNIT_ERASE : SPICMD_WRITE_ENABLE failed.\n");
  2558. + return 1;
  2559. + }
  2560. +
  2561. + return 0;
  2562. +}
  2563. +
  2564. +/* erase one block or chip or sector as needed */
  2565. +static int ec_unit_erase(unsigned char erase_cmd, unsigned int addr)
  2566. +{
  2567. + unsigned char status;
  2568. + int ret = 0, i = 0;
  2569. + int unprotect_count = 3;
  2570. + int check_flag = 0;
  2571. +
  2572. + /* enable spicmd writing. */
  2573. + ec_start_spi();
  2574. +
  2575. +#ifdef EC_ROM_PROTECTION
  2576. + /* added for re-check SPICMD_READ_STATUS */
  2577. + while (unprotect_count-- > 0) {
  2578. + if (EC_ROM_unprotect()) {
  2579. + ret = -EINVAL;
  2580. + goto out;
  2581. + }
  2582. +
  2583. + /* first time:500ms --> 5.5sec -->10.5sec */
  2584. + for (i = 0; i < ((2 - unprotect_count) * 100 + 10); i++)
  2585. + udelay(50000);
  2586. + ec_write(REG_XBISPICMD, SPICMD_READ_STATUS);
  2587. + if (rom_instruction_cycle(SPICMD_READ_STATUS)
  2588. + == EC_STATE_BUSY) {
  2589. + printk(KERN_ERR
  2590. + "EC_PROGRAM_ROM : SPICMD_READ_STATUS failed.\n");
  2591. + } else {
  2592. + status = ec_read(REG_XBISPIDAT);
  2593. + printk(KERN_INFO "Read unprotect status : 0x%x\n",
  2594. + status);
  2595. + if ((status & 0x1C) == 0x00) {
  2596. + printk(KERN_INFO
  2597. + "Read unprotect status OK1 : 0x%x\n",
  2598. + status & 0x1C);
  2599. + check_flag = 1;
  2600. + break;
  2601. + }
  2602. + }
  2603. + }
  2604. +
  2605. + if (!check_flag) {
  2606. + printk(KERN_INFO "SPI ROM unprotect fail.\n");
  2607. + return 1;
  2608. + }
  2609. +#endif
  2610. +
  2611. + /* block address fill */
  2612. + if (erase_cmd == SPICMD_BLK_ERASE) {
  2613. + ec_write(REG_XBISPIA2, (addr & 0x00ff0000) >> 16);
  2614. + ec_write(REG_XBISPIA1, (addr & 0x0000ff00) >> 8);
  2615. + ec_write(REG_XBISPIA0, (addr & 0x000000ff) >> 0);
  2616. + }
  2617. +
  2618. + /* erase the whole chip first */
  2619. + ec_write(REG_XBISPICMD, erase_cmd);
  2620. + if (rom_instruction_cycle(erase_cmd) == EC_STATE_BUSY) {
  2621. + printk(KERN_ERR "EC_UNIT_ERASE : erase failed.\n");
  2622. + ret = -EINVAL;
  2623. + goto out;
  2624. + }
  2625. +
  2626. + out:
  2627. + /* disable spicmd writing. */
  2628. + ec_stop_spi();
  2629. +
  2630. + return ret;
  2631. +}
  2632. +
  2633. +/* update the whole rom content with H/W mode
  2634. + * PLEASE USING ec_unit_erase() FIRSTLY
  2635. + */
  2636. +static int ec_program_rom(struct ec_info *info, int flag)
  2637. +{
  2638. + unsigned int addr = 0;
  2639. + unsigned long size = 0;
  2640. + unsigned char *ptr = NULL;
  2641. + unsigned char data;
  2642. + unsigned char val = 0;
  2643. + int ret = 0;
  2644. + int i, j;
  2645. + unsigned char status;
  2646. +
  2647. + /* modify for program serial No.
  2648. + * set IE_START_ADDR & use idle mode,
  2649. + * disable WDD
  2650. + */
  2651. + if (flag == PROGRAM_FLAG_ROM) {
  2652. + ret = ec_init_reset_mode();
  2653. + addr = info->start_addr + EC_START_ADDR;
  2654. + printk(KERN_INFO "PROGRAM_FLAG_ROM..............\n");
  2655. + } else if (flag == PROGRAM_FLAG_IE) {
  2656. + ret = ec_init_idle_mode();
  2657. + ec_disable_WDD();
  2658. + addr = info->start_addr + IE_START_ADDR;
  2659. + printk(KERN_INFO "PROGRAM_FLAG_IE..............\n");
  2660. + } else {
  2661. + return 0;
  2662. + }
  2663. +
  2664. + if (ret < 0) {
  2665. + if (flag == PROGRAM_FLAG_IE)
  2666. + ec_enable_WDD();
  2667. + return ret;
  2668. + }
  2669. +
  2670. + size = info->size;
  2671. + ptr = info->buf;
  2672. + printk(KERN_INFO "starting update ec ROM..............\n");
  2673. +
  2674. + ret = ec_unit_erase(SPICMD_BLK_ERASE, addr);
  2675. + if (ret) {
  2676. + printk(KERN_ERR "program ec : erase block failed.\n");
  2677. + goto out;
  2678. + }
  2679. + printk(KERN_ERR "program ec : erase block OK.\n");
  2680. +
  2681. + i = 0;
  2682. + while (i < size) {
  2683. + data = *(ptr + i);
  2684. + ec_write_byte(addr, data);
  2685. + ec_read_byte(addr, &val);
  2686. + if (val != data) {
  2687. + ec_write_byte(addr, data);
  2688. + ec_read_byte(addr, &val);
  2689. + if (val != data) {
  2690. + printk(KERN_INFO
  2691. + "EC : Second flash program failed at:\t");
  2692. + printk(KERN_INFO
  2693. + "addr : 0x%x, source : 0x%x, dest: 0x%x\n",
  2694. + addr, data, val);
  2695. + printk(KERN_INFO "This should not happen... STOP\n");
  2696. + break;
  2697. + }
  2698. + }
  2699. + i++;
  2700. + addr++;
  2701. + }
  2702. +
  2703. +#ifdef EC_ROM_PROTECTION
  2704. + /* we should start spi access firstly */
  2705. + ec_start_spi();
  2706. +
  2707. + /* enable write spi flash */
  2708. + ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE);
  2709. + if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) {
  2710. + printk(KERN_ERR
  2711. + "EC_PROGRAM_ROM : SPICMD_WRITE_ENABLE failed.\n");
  2712. + goto out1;
  2713. + }
  2714. +
  2715. + /* protect the status register of rom */
  2716. + ec_write(REG_XBISPICMD, SPICMD_READ_STATUS);
  2717. + if (rom_instruction_cycle(SPICMD_READ_STATUS) == EC_STATE_BUSY) {
  2718. + printk(KERN_ERR
  2719. + "EC_PROGRAM_ROM : SPICMD_READ_STATUS failed.\n");
  2720. + goto out1;
  2721. + }
  2722. + status = ec_read(REG_XBISPIDAT);
  2723. +
  2724. + ec_write(REG_XBISPIDAT, status | 0x1C);
  2725. + if (ec_instruction_cycle() < 0) {
  2726. + printk(KERN_ERR
  2727. + "EC_PROGRAM_ROM : write status value failed.\n");
  2728. + goto out1;
  2729. + }
  2730. +
  2731. + ec_write(REG_XBISPICMD, SPICMD_WRITE_STATUS);
  2732. + if (rom_instruction_cycle(SPICMD_WRITE_STATUS) == EC_STATE_BUSY) {
  2733. + printk(KERN_ERR
  2734. + "EC_PROGRAM_ROM : SPICMD_WRITE_STATUS failed.\n");
  2735. + goto out1;
  2736. + }
  2737. +#endif
  2738. +
  2739. + /* disable the write action to spi rom */
  2740. + ec_write(REG_XBISPICMD, SPICMD_WRITE_DISABLE);
  2741. + if (rom_instruction_cycle(SPICMD_WRITE_DISABLE) == EC_STATE_BUSY) {
  2742. + printk(KERN_ERR
  2743. + "EC_PROGRAM_ROM : SPICMD_WRITE_DISABLE failed.\n");
  2744. + goto out1;
  2745. + }
  2746. +
  2747. + out1:
  2748. + /* we should stop spi access firstly */
  2749. + ec_stop_spi();
  2750. + out:
  2751. + /* for security */
  2752. + for (j = 0; j < 2000; j++)
  2753. + udelay(1000);
  2754. +
  2755. + /* modify for program serial No.
  2756. + * after program No exit idle mode
  2757. + * and enable WDD
  2758. + */
  2759. + if (flag == PROGRAM_FLAG_ROM) {
  2760. + /* exit from the reset mode */
  2761. + ec_exit_reset_mode();
  2762. + } else {
  2763. + /* ec exit from idle mode */
  2764. + ret = ec_exit_idle_mode();
  2765. + ec_enable_WDD();
  2766. + if (ret < 0)
  2767. + return ret;
  2768. + }
  2769. +
  2770. + return 0;
  2771. +}
  2772. +
  2773. +/* ioctl */
  2774. +static int misc_ioctl(struct inode *inode, struct file *filp, u_int cmd,
  2775. + u_long arg)
  2776. +{
  2777. + struct ec_info ecinfo;
  2778. + void __user *ptr = (void __user *)arg;
  2779. + struct ec_reg *ecreg = (struct ec_reg *)(filp->private_data);
  2780. + int ret = 0;
  2781. +
  2782. + switch (cmd) {
  2783. + case IOCTL_RDREG:
  2784. + ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg));
  2785. + if (ret) {
  2786. + printk(KERN_ERR "reg read : copy from user error.\n");
  2787. + return -EFAULT;
  2788. + }
  2789. + if ((ecreg->addr > EC_MAX_REGADDR)
  2790. + || (ecreg->addr < EC_MIN_REGADDR)) {
  2791. + printk(KERN_ERR
  2792. + "reg read : out of register address range.\n");
  2793. + return -EINVAL;
  2794. + }
  2795. + ecreg->val = ec_read(ecreg->addr);
  2796. + ret = copy_to_user(ptr, ecreg, sizeof(struct ec_reg));
  2797. + if (ret) {
  2798. + printk(KERN_ERR "reg read : copy to user error.\n");
  2799. + return -EFAULT;
  2800. + }
  2801. + break;
  2802. + case IOCTL_WRREG:
  2803. + ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg));
  2804. + if (ret) {
  2805. + printk(KERN_ERR "reg write : copy from user error.\n");
  2806. + return -EFAULT;
  2807. + }
  2808. + if ((ecreg->addr > EC_MAX_REGADDR)
  2809. + || (ecreg->addr < EC_MIN_REGADDR)) {
  2810. + printk(KERN_ERR
  2811. + "reg write : out of register address range.\n");
  2812. + return -EINVAL;
  2813. + }
  2814. + ec_write(ecreg->addr, ecreg->val);
  2815. + break;
  2816. + case IOCTL_READ_EC:
  2817. + ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg));
  2818. + if (ret) {
  2819. + printk(KERN_ERR "spi read : copy from user error.\n");
  2820. + return -EFAULT;
  2821. + }
  2822. + if ((ecreg->addr > EC_RAM_ADDR)
  2823. + && (ecreg->addr < EC_MAX_REGADDR)) {
  2824. + printk(KERN_ERR
  2825. + "spi read : out of register address range.\n");
  2826. + return -EINVAL;
  2827. + }
  2828. + ec_read_byte(ecreg->addr, &(ecreg->val));
  2829. + ret = copy_to_user(ptr, ecreg, sizeof(struct ec_reg));
  2830. + if (ret) {
  2831. + printk(KERN_ERR "spi read : copy to user error.\n");
  2832. + return -EFAULT;
  2833. + }
  2834. + break;
  2835. + case IOCTL_PROGRAM_IE:
  2836. + ecinfo.start_addr = EC_START_ADDR;
  2837. + ecinfo.size = EC_CONTENT_MAX_SIZE;
  2838. + ecinfo.buf = (u8 *) kmalloc(ecinfo.size, GFP_KERNEL);
  2839. + if (ecinfo.buf == NULL) {
  2840. + printk(KERN_ERR "program ie : kmalloc failed.\n");
  2841. + return -ENOMEM;
  2842. + }
  2843. + ret = copy_from_user(ecinfo.buf, (u8 *) ptr, ecinfo.size);
  2844. + if (ret) {
  2845. + printk(KERN_ERR "program ie : copy from user error.\n");
  2846. + kfree(ecinfo.buf);
  2847. + ecinfo.buf = NULL;
  2848. + return -EFAULT;
  2849. + }
  2850. +
  2851. + /* use ec_program_rom to write serial No */
  2852. + ec_program_rom(&ecinfo, PROGRAM_FLAG_IE);
  2853. +
  2854. + kfree(ecinfo.buf);
  2855. + ecinfo.buf = NULL;
  2856. + break;
  2857. + case IOCTL_PROGRAM_EC:
  2858. + ecinfo.start_addr = EC_START_ADDR;
  2859. + if (get_user((ecinfo.size), (u32 *) ptr)) {
  2860. + printk(KERN_ERR "program ec : get user error.\n");
  2861. + return -EFAULT;
  2862. + }
  2863. + if ((ecinfo.size) > EC_CONTENT_MAX_SIZE) {
  2864. + printk(KERN_ERR "program ec : size out of limited.\n");
  2865. + return -EINVAL;
  2866. + }
  2867. + ecinfo.buf = (u8 *) kmalloc(ecinfo.size, GFP_KERNEL);
  2868. + if (ecinfo.buf == NULL) {
  2869. + printk(KERN_ERR "program ec : kmalloc failed.\n");
  2870. + return -ENOMEM;
  2871. + }
  2872. + ret = copy_from_user(ecinfo.buf, ((u8 *) ptr + 4), ecinfo.size);
  2873. + if (ret) {
  2874. + printk(KERN_ERR "program ec : copy from user error.\n");
  2875. + kfree(ecinfo.buf);
  2876. + ecinfo.buf = NULL;
  2877. + return -EFAULT;
  2878. + }
  2879. +
  2880. + ec_program_rom(&ecinfo, PROGRAM_FLAG_ROM);
  2881. +
  2882. + kfree(ecinfo.buf);
  2883. + ecinfo.buf = NULL;
  2884. + break;
  2885. +
  2886. + default:
  2887. + break;
  2888. + }
  2889. +
  2890. + return 0;
  2891. +}
  2892. +
  2893. +static long misc_compat_ioctl(struct file *file, unsigned int cmd,
  2894. + unsigned long arg)
  2895. +{
  2896. + return misc_ioctl(file->f_dentry->d_inode, file, cmd, arg);
  2897. +}
  2898. +
  2899. +static int misc_open(struct inode *inode, struct file *filp)
  2900. +{
  2901. + struct ec_reg *ecreg = NULL;
  2902. + ecreg = kmalloc(sizeof(struct ec_reg), GFP_KERNEL);
  2903. + if (ecreg)
  2904. + filp->private_data = ecreg;
  2905. +
  2906. + return ecreg ? 0 : -ENOMEM;
  2907. +}
  2908. +
  2909. +static int misc_release(struct inode *inode, struct file *filp)
  2910. +{
  2911. + struct ec_reg *ecreg = (struct ec_reg *)(filp->private_data);
  2912. +
  2913. + filp->private_data = NULL;
  2914. + kfree(ecreg);
  2915. +
  2916. + return 0;
  2917. +}
  2918. +
  2919. +static const struct file_operations ecmisc_fops = {
  2920. + .open = misc_open,
  2921. + .release = misc_release,
  2922. + .read = NULL,
  2923. + .write = NULL,
  2924. +#ifdef CONFIG_64BIT
  2925. + .compat_ioctl = misc_compat_ioctl,
  2926. +#else
  2927. + .ioctl = misc_ioctl,
  2928. +#endif
  2929. +};
  2930. +
  2931. +static struct miscdevice ecmisc_device = {
  2932. + .minor = MISC_DYNAMIC_MINOR,
  2933. + .name = EC_MISC_DEV,
  2934. + .fops = &ecmisc_fops
  2935. +};
  2936. +
  2937. +static int __init ecmisc_init(void)
  2938. +{
  2939. + int ret;
  2940. +
  2941. + printk(KERN_INFO "EC misc device init.\n");
  2942. + ret = misc_register(&ecmisc_device);
  2943. +
  2944. + return ret;
  2945. +}
  2946. +
  2947. +static void __exit ecmisc_exit(void)
  2948. +{
  2949. + printk(KERN_INFO "EC misc device exit.\n");
  2950. + misc_deregister(&ecmisc_device);
  2951. +}
  2952. +
  2953. +module_init(ecmisc_init);
  2954. +module_exit(ecmisc_exit);
  2955. +
  2956. +MODULE_AUTHOR("liujl <liujl@lemote.com>");
  2957. +MODULE_DESCRIPTION("Driver for flushing/dumping ROM of EC on YeeLoong laptop");
  2958. +MODULE_LICENSE("GPL");
  2959. diff -Nur linux-2.6.36.orig/drivers/platform/mips/yeeloong_laptop.c linux-2.6.36/drivers/platform/mips/yeeloong_laptop.c
  2960. --- linux-2.6.36.orig/drivers/platform/mips/yeeloong_laptop.c 1970-01-01 01:00:00.000000000 +0100
  2961. +++ linux-2.6.36/drivers/platform/mips/yeeloong_laptop.c 2010-12-17 23:12:59.000000000 +0100
  2962. @@ -0,0 +1,1200 @@
  2963. +/*
  2964. + * Driver for YeeLoong laptop extras
  2965. + *
  2966. + * Copyright (C) 2009 Lemote Inc.
  2967. + * Author: Wu Zhangjin <wuzhangjin@gmail.com>, Liu Junliang <liujl@lemote.com>
  2968. + *
  2969. + * This program is free software; you can redistribute it and/or modify
  2970. + * it under the terms of the GNU General Public License version 2 as
  2971. + * published by the Free Software Foundation.
  2972. + */
  2973. +
  2974. +#include <linux/err.h>
  2975. +#include <linux/platform_device.h>
  2976. +#include <linux/backlight.h> /* for backlight subdriver */
  2977. +#include <linux/fb.h>
  2978. +#include <linux/hwmon.h> /* for hwmon subdriver */
  2979. +#include <linux/hwmon-sysfs.h>
  2980. +#include <linux/video_output.h> /* for video output subdriver */
  2981. +#include <linux/input.h> /* for hotkey subdriver */
  2982. +#include <linux/input/sparse-keymap.h>
  2983. +#include <linux/interrupt.h>
  2984. +#include <linux/delay.h>
  2985. +#include <linux/power_supply.h> /* for AC & Battery subdriver */
  2986. +
  2987. +#include <cs5536/cs5536.h>
  2988. +
  2989. +#include <loongson.h> /* for loongson_cmdline */
  2990. +#include <ec_kb3310b.h>
  2991. +
  2992. +/* common function */
  2993. +#define EC_VER_LEN 64
  2994. +
  2995. +static int ec_version_before(char *version)
  2996. +{
  2997. + char *p, ec_ver[EC_VER_LEN];
  2998. +
  2999. + p = strstr(loongson_cmdline, "EC_VER=");
  3000. + if (!p)
  3001. + memset(ec_ver, 0, EC_VER_LEN);
  3002. + else {
  3003. + strncpy(ec_ver, p, EC_VER_LEN);
  3004. + p = strstr(ec_ver, " ");
  3005. + if (p)
  3006. + *p = '\0';
  3007. + }
  3008. +
  3009. + return (strncasecmp(ec_ver, version, 64) < 0);
  3010. +}
  3011. +
  3012. +/* backlight subdriver */
  3013. +#define MAX_BRIGHTNESS 8
  3014. +
  3015. +static int yeeloong_set_brightness(struct backlight_device *bd)
  3016. +{
  3017. + unsigned int level, current_level;
  3018. + static unsigned int old_level;
  3019. +
  3020. + level = (bd->props.fb_blank == FB_BLANK_UNBLANK &&
  3021. + bd->props.power == FB_BLANK_UNBLANK) ?
  3022. + bd->props.brightness : 0;
  3023. +
  3024. + level = SENSORS_LIMIT(level, 0, MAX_BRIGHTNESS);
  3025. +
  3026. + /* Avoid to modify the brightness when EC is tuning it */
  3027. + if (old_level != level) {
  3028. + current_level = ec_read(REG_DISPLAY_BRIGHTNESS);
  3029. + if (old_level == current_level)
  3030. + ec_write(REG_DISPLAY_BRIGHTNESS, level);
  3031. + old_level = level;
  3032. + }
  3033. +
  3034. + return 0;
  3035. +}
  3036. +
  3037. +static int yeeloong_get_brightness(struct backlight_device *bd)
  3038. +{
  3039. + return ec_read(REG_DISPLAY_BRIGHTNESS);
  3040. +}
  3041. +
  3042. +static struct backlight_ops backlight_ops = {
  3043. + .get_brightness = yeeloong_get_brightness,
  3044. + .update_status = yeeloong_set_brightness,
  3045. +};
  3046. +
  3047. +static struct backlight_device *yeeloong_backlight_dev;
  3048. +
  3049. +static int yeeloong_backlight_init(void)
  3050. +{
  3051. + int ret;
  3052. + struct backlight_properties props;
  3053. +
  3054. + memset(&props, 0, sizeof(struct backlight_properties));
  3055. + props.max_brightness = MAX_BRIGHTNESS;
  3056. + yeeloong_backlight_dev = backlight_device_register("backlight0", NULL,
  3057. + NULL, &backlight_ops, &props);
  3058. +
  3059. + if (IS_ERR(yeeloong_backlight_dev)) {
  3060. + ret = PTR_ERR(yeeloong_backlight_dev);
  3061. + yeeloong_backlight_dev = NULL;
  3062. + return ret;
  3063. + }
  3064. +
  3065. + yeeloong_backlight_dev->props.brightness =
  3066. + yeeloong_get_brightness(yeeloong_backlight_dev);
  3067. + backlight_update_status(yeeloong_backlight_dev);
  3068. +
  3069. + return 0;
  3070. +}
  3071. +
  3072. +static void yeeloong_backlight_exit(void)
  3073. +{
  3074. + if (yeeloong_backlight_dev) {
  3075. + backlight_device_unregister(yeeloong_backlight_dev);
  3076. + yeeloong_backlight_dev = NULL;
  3077. + }
  3078. +}
  3079. +
  3080. +/* AC & Battery subdriver */
  3081. +
  3082. +static struct power_supply yeeloong_ac, yeeloong_bat;
  3083. +
  3084. +#define AC_OFFLINE 0
  3085. +#define AC_ONLINE 1
  3086. +
  3087. +static int yeeloong_get_ac_props(struct power_supply *psy,
  3088. + enum power_supply_property psp,
  3089. + union power_supply_propval *val)
  3090. +{
  3091. + switch (psp) {
  3092. + case POWER_SUPPLY_PROP_ONLINE:
  3093. + val->intval = ((ec_read(REG_BAT_POWER)) & BIT_BAT_POWER_ACIN) ?
  3094. + AC_ONLINE : AC_OFFLINE;
  3095. + break;
  3096. + default:
  3097. + return -EINVAL;
  3098. + }
  3099. +
  3100. + return 0;
  3101. +}
  3102. +
  3103. +static enum power_supply_property yeeloong_ac_props[] = {
  3104. + POWER_SUPPLY_PROP_ONLINE,
  3105. +};
  3106. +
  3107. +static struct power_supply yeeloong_ac = {
  3108. + .name = "yeeloong-ac",
  3109. + .type = POWER_SUPPLY_TYPE_MAINS,
  3110. + .properties = yeeloong_ac_props,
  3111. + .num_properties = ARRAY_SIZE(yeeloong_ac_props),
  3112. + .get_property = yeeloong_get_ac_props,
  3113. +};
  3114. +
  3115. +#define BAT_CAP_CRITICAL 5
  3116. +#define BAT_CAP_HIGH 99
  3117. +
  3118. +#define get_bat_info(type) \
  3119. + ((ec_read(REG_BAT_##type##_HIGH) << 8) | \
  3120. + (ec_read(REG_BAT_##type##_LOW)))
  3121. +
  3122. +static int yeeloong_bat_get_ex_property(enum power_supply_property psp,
  3123. + union power_supply_propval *val)
  3124. +{
  3125. + int bat_in, curr_cap, cap_level, status, charge, health;
  3126. +
  3127. + status = ec_read(REG_BAT_STATUS);
  3128. + bat_in = status & BIT_BAT_STATUS_IN;
  3129. + curr_cap = get_bat_info(RELATIVE_CAP);
  3130. + if (status & BIT_BAT_STATUS_FULL)
  3131. + curr_cap = 100;
  3132. +
  3133. + switch (psp) {
  3134. + case POWER_SUPPLY_PROP_PRESENT:
  3135. + val->intval = bat_in;
  3136. + break;
  3137. + case POWER_SUPPLY_PROP_CAPACITY:
  3138. + val->intval = curr_cap;
  3139. + break;
  3140. + case POWER_SUPPLY_PROP_CAPACITY_LEVEL:
  3141. + cap_level = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL;
  3142. + if (status & BIT_BAT_STATUS_LOW) {
  3143. + cap_level = POWER_SUPPLY_CAPACITY_LEVEL_LOW;
  3144. + if (curr_cap <= BAT_CAP_CRITICAL)
  3145. + cap_level =
  3146. + POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;
  3147. + } else if (status & BIT_BAT_STATUS_FULL) {
  3148. + cap_level = POWER_SUPPLY_CAPACITY_LEVEL_FULL;
  3149. + if (curr_cap >= BAT_CAP_HIGH)
  3150. + cap_level = POWER_SUPPLY_CAPACITY_LEVEL_HIGH;
  3151. + } else if (status & BIT_BAT_STATUS_DESTROY)
  3152. + cap_level = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN;
  3153. + val->intval = cap_level;
  3154. + break;
  3155. + case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
  3156. + /* seconds */
  3157. + val->intval = bat_in ? (curr_cap - 3) * 54 + 142 : 0;
  3158. + break;
  3159. + case POWER_SUPPLY_PROP_STATUS:
  3160. + if (!bat_in)
  3161. + charge = POWER_SUPPLY_STATUS_UNKNOWN;
  3162. + else {
  3163. + if (status & BIT_BAT_STATUS_FULL) {
  3164. + val->intval = POWER_SUPPLY_STATUS_FULL;
  3165. + break;
  3166. + }
  3167. +
  3168. + charge = ec_read(REG_BAT_CHARGE);
  3169. + if (charge & FLAG_BAT_CHARGE_DISCHARGE)
  3170. + charge = POWER_SUPPLY_STATUS_DISCHARGING;
  3171. + else if (charge & FLAG_BAT_CHARGE_CHARGE)
  3172. + charge = POWER_SUPPLY_STATUS_CHARGING;
  3173. + else
  3174. + charge = POWER_SUPPLY_STATUS_NOT_CHARGING;
  3175. + }
  3176. + val->intval = charge;
  3177. + break;
  3178. + case POWER_SUPPLY_PROP_HEALTH:
  3179. + if (!bat_in) /* no battery present */
  3180. + health = POWER_SUPPLY_HEALTH_UNKNOWN;
  3181. + else { /* Assume it is good */
  3182. + health = POWER_SUPPLY_HEALTH_GOOD;
  3183. + if (status &
  3184. + (BIT_BAT_STATUS_DESTROY | BIT_BAT_STATUS_LOW))
  3185. + health = POWER_SUPPLY_HEALTH_DEAD;
  3186. + if (ec_read(REG_BAT_CHARGE_STATUS) &
  3187. + BIT_BAT_CHARGE_STATUS_OVERTEMP)
  3188. + health = POWER_SUPPLY_HEALTH_OVERHEAT;
  3189. + }
  3190. + val->intval = health;
  3191. + break;
  3192. + case POWER_SUPPLY_PROP_CHARGE_NOW: /* 1/100(%)*1000 µAh */
  3193. + val->intval = curr_cap * get_bat_info(FULLCHG_CAP) * 10;
  3194. + break;
  3195. + default:
  3196. + return -EINVAL;
  3197. + }
  3198. + return 0;
  3199. +}
  3200. +
  3201. +static int get_battery_temp(void)
  3202. +{
  3203. + int value;
  3204. +
  3205. + value = get_bat_info(TEMPERATURE);
  3206. +
  3207. + return value * 1000;
  3208. +}
  3209. +
  3210. +static int get_battery_current(void)
  3211. +{
  3212. + s16 value;
  3213. +
  3214. + value = get_bat_info(CURRENT);
  3215. +
  3216. + return -value;
  3217. +}
  3218. +
  3219. +static int get_battery_voltage(void)
  3220. +{
  3221. + int value;
  3222. +
  3223. + value = get_bat_info(VOLTAGE);
  3224. +
  3225. + return value;
  3226. +}
  3227. +
  3228. +static int yeeloong_get_bat_props(struct power_supply *psy,
  3229. + enum power_supply_property psp,
  3230. + union power_supply_propval *val)
  3231. +{
  3232. + switch (psp) {
  3233. + /* Fixed information */
  3234. + case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
  3235. + val->intval = get_bat_info(DESIGN_VOL) * 1000; /* mV -> µV */
  3236. + break;
  3237. + case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
  3238. + val->intval = get_bat_info(DESIGN_CAP) * 1000; /* mAh->µAh */
  3239. + break;
  3240. + case POWER_SUPPLY_PROP_CHARGE_FULL:
  3241. + val->intval = get_bat_info(FULLCHG_CAP) * 1000; /* µAh */
  3242. + break;
  3243. + case POWER_SUPPLY_PROP_MANUFACTURER:
  3244. + val->strval = (ec_read(REG_BAT_VENDOR) ==
  3245. + FLAG_BAT_VENDOR_SANYO) ? "SANYO" : "SIMPLO";
  3246. + break;
  3247. + /* Dynamic information */
  3248. + case POWER_SUPPLY_PROP_CURRENT_NOW:
  3249. + val->intval = get_battery_current() * 1000; /* mA -> µA */
  3250. + break;
  3251. + case POWER_SUPPLY_PROP_VOLTAGE_NOW:
  3252. + val->intval = get_battery_voltage() * 1000; /* mV -> µV */
  3253. + break;
  3254. + case POWER_SUPPLY_PROP_TEMP:
  3255. + val->intval = get_battery_temp(); /* Celcius */
  3256. + break;
  3257. + /* Dynamic but related information */
  3258. + default:
  3259. + return yeeloong_bat_get_ex_property(psp, val);
  3260. + }
  3261. +
  3262. + return 0;
  3263. +}
  3264. +
  3265. +static enum power_supply_property yeeloong_bat_props[] = {
  3266. + POWER_SUPPLY_PROP_STATUS,
  3267. + POWER_SUPPLY_PROP_PRESENT,
  3268. + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
  3269. + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
  3270. + POWER_SUPPLY_PROP_CHARGE_FULL,
  3271. + POWER_SUPPLY_PROP_CHARGE_NOW,
  3272. + POWER_SUPPLY_PROP_CURRENT_NOW,
  3273. + POWER_SUPPLY_PROP_VOLTAGE_NOW,
  3274. + POWER_SUPPLY_PROP_HEALTH,
  3275. + POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
  3276. + POWER_SUPPLY_PROP_CAPACITY,
  3277. + POWER_SUPPLY_PROP_CAPACITY_LEVEL,
  3278. + POWER_SUPPLY_PROP_TEMP,
  3279. + POWER_SUPPLY_PROP_MANUFACTURER,
  3280. +};
  3281. +
  3282. +static struct power_supply yeeloong_bat = {
  3283. + .name = "yeeloong-bat",
  3284. + .type = POWER_SUPPLY_TYPE_BATTERY,
  3285. + .properties = yeeloong_bat_props,
  3286. + .num_properties = ARRAY_SIZE(yeeloong_bat_props),
  3287. + .get_property = yeeloong_get_bat_props,
  3288. +};
  3289. +
  3290. +static int ac_bat_initialized;
  3291. +
  3292. +static int yeeloong_bat_init(void)
  3293. +{
  3294. + int ret;
  3295. +
  3296. + ret = power_supply_register(NULL, &yeeloong_ac);
  3297. + if (ret)
  3298. + return ret;
  3299. + ret = power_supply_register(NULL, &yeeloong_bat);
  3300. + if (ret) {
  3301. + power_supply_unregister(&yeeloong_ac);
  3302. + return ret;
  3303. + }
  3304. + ac_bat_initialized = 1;
  3305. +
  3306. + return 0;
  3307. +}
  3308. +
  3309. +static void yeeloong_bat_exit(void)
  3310. +{
  3311. + ac_bat_initialized = 0;
  3312. +
  3313. + power_supply_unregister(&yeeloong_ac);
  3314. + power_supply_unregister(&yeeloong_bat);
  3315. +}
  3316. +/* hwmon subdriver */
  3317. +
  3318. +#define MIN_FAN_SPEED 0
  3319. +#define MAX_FAN_SPEED 3
  3320. +
  3321. +static int get_fan_pwm_enable(void)
  3322. +{
  3323. + int level, mode;
  3324. +
  3325. + level = ec_read(REG_FAN_SPEED_LEVEL);
  3326. + mode = ec_read(REG_FAN_AUTO_MAN_SWITCH);
  3327. +
  3328. + if (level == MAX_FAN_SPEED && mode == BIT_FAN_MANUAL)
  3329. + mode = 0;
  3330. + else if (mode == BIT_FAN_MANUAL)
  3331. + mode = 1;
  3332. + else
  3333. + mode = 2;
  3334. +
  3335. + return mode;
  3336. +}
  3337. +
  3338. +static void set_fan_pwm_enable(int mode)
  3339. +{
  3340. + switch (mode) {
  3341. + case 0:
  3342. + /* fullspeed */
  3343. + ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_MANUAL);
  3344. + ec_write(REG_FAN_SPEED_LEVEL, MAX_FAN_SPEED);
  3345. + break;
  3346. + case 1:
  3347. + ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_MANUAL);
  3348. + break;
  3349. + case 2:
  3350. + ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_AUTO);
  3351. + break;
  3352. + default:
  3353. + break;
  3354. + }
  3355. +}
  3356. +
  3357. +static int get_fan_pwm(void)
  3358. +{
  3359. + return ec_read(REG_FAN_SPEED_LEVEL);
  3360. +}
  3361. +
  3362. +static void set_fan_pwm(int value)
  3363. +{
  3364. + int mode;
  3365. +
  3366. + mode = ec_read(REG_FAN_AUTO_MAN_SWITCH);
  3367. + if (mode != BIT_FAN_MANUAL)
  3368. + return;
  3369. +
  3370. + value = SENSORS_LIMIT(value, 0, 3);
  3371. +
  3372. + /* We must ensure the fan is on */
  3373. + if (value > 0)
  3374. + ec_write(REG_FAN_CONTROL, BIT_FAN_CONTROL_ON);
  3375. +
  3376. + ec_write(REG_FAN_SPEED_LEVEL, value);
  3377. +}
  3378. +
  3379. +static int get_fan_rpm(void)
  3380. +{
  3381. + int value;
  3382. +
  3383. + value = FAN_SPEED_DIVIDER /
  3384. + (((ec_read(REG_FAN_SPEED_HIGH) & 0x0f) << 8) |
  3385. + ec_read(REG_FAN_SPEED_LOW));
  3386. +
  3387. + return value;
  3388. +}
  3389. +
  3390. +static int get_cpu_temp(void)
  3391. +{
  3392. + s8 value;
  3393. +
  3394. + value = ec_read(REG_TEMPERATURE_VALUE);
  3395. +
  3396. + return value * 1000;
  3397. +}
  3398. +
  3399. +static int get_cpu_temp_max(void)
  3400. +{
  3401. + return 60 * 1000;
  3402. +}
  3403. +
  3404. +static int get_battery_temp_alarm(void)
  3405. +{
  3406. + int status;
  3407. +
  3408. + status = (ec_read(REG_BAT_CHARGE_STATUS) &
  3409. + BIT_BAT_CHARGE_STATUS_OVERTEMP);
  3410. +
  3411. + return !!status;
  3412. +}
  3413. +
  3414. +static ssize_t store_sys_hwmon(void (*set) (int), const char *buf, size_t count)
  3415. +{
  3416. + int ret;
  3417. + unsigned long value;
  3418. +
  3419. + if (!count)
  3420. + return 0;
  3421. +
  3422. + ret = strict_strtoul(buf, 10, &value);
  3423. + if (ret)
  3424. + return ret;
  3425. +
  3426. + set(value);
  3427. +
  3428. + return count;
  3429. +}
  3430. +
  3431. +static ssize_t show_sys_hwmon(int (*get) (void), char *buf)
  3432. +{
  3433. + return sprintf(buf, "%d\n", get());
  3434. +}
  3435. +
  3436. +#define CREATE_SENSOR_ATTR(_name, _mode, _set, _get) \
  3437. + static ssize_t show_##_name(struct device *dev, \
  3438. + struct device_attribute *attr, \
  3439. + char *buf) \
  3440. + { \
  3441. + return show_sys_hwmon(_set, buf); \
  3442. + } \
  3443. + static ssize_t store_##_name(struct device *dev, \
  3444. + struct device_attribute *attr, \
  3445. + const char *buf, size_t count) \
  3446. + { \
  3447. + return store_sys_hwmon(_get, buf, count); \
  3448. + } \
  3449. + static SENSOR_DEVICE_ATTR(_name, _mode, show_##_name, store_##_name, 0);
  3450. +
  3451. +CREATE_SENSOR_ATTR(fan1_input, S_IRUGO, get_fan_rpm, NULL);
  3452. +CREATE_SENSOR_ATTR(pwm1, S_IRUGO | S_IWUSR, get_fan_pwm, set_fan_pwm);
  3453. +CREATE_SENSOR_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, get_fan_pwm_enable,
  3454. + set_fan_pwm_enable);
  3455. +CREATE_SENSOR_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL);
  3456. +CREATE_SENSOR_ATTR(temp1_max, S_IRUGO, get_cpu_temp_max, NULL);
  3457. +CREATE_SENSOR_ATTR(temp2_input, S_IRUGO, get_battery_temp, NULL);
  3458. +CREATE_SENSOR_ATTR(temp2_max_alarm, S_IRUGO, get_battery_temp_alarm, NULL);
  3459. +CREATE_SENSOR_ATTR(curr1_input, S_IRUGO, get_battery_current, NULL);
  3460. +CREATE_SENSOR_ATTR(in1_input, S_IRUGO, get_battery_voltage, NULL);
  3461. +
  3462. +static ssize_t
  3463. +show_name(struct device *dev, struct device_attribute *attr, char *buf)
  3464. +{
  3465. + return sprintf(buf, "yeeloong\n");
  3466. +}
  3467. +
  3468. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, 0);
  3469. +
  3470. +static struct attribute *hwmon_attributes[] = {
  3471. + &sensor_dev_attr_pwm1.dev_attr.attr,
  3472. + &sensor_dev_attr_pwm1_enable.dev_attr.attr,
  3473. + &sensor_dev_attr_fan1_input.dev_attr.attr,
  3474. + &sensor_dev_attr_temp1_input.dev_attr.attr,
  3475. + &sensor_dev_attr_temp1_max.dev_attr.attr,
  3476. + &sensor_dev_attr_temp2_input.dev_attr.attr,
  3477. + &sensor_dev_attr_temp2_max_alarm.dev_attr.attr,
  3478. + &sensor_dev_attr_curr1_input.dev_attr.attr,
  3479. + &sensor_dev_attr_in1_input.dev_attr.attr,
  3480. + &sensor_dev_attr_name.dev_attr.attr,
  3481. + NULL
  3482. +};
  3483. +
  3484. +static struct attribute_group hwmon_attribute_group = {
  3485. + .attrs = hwmon_attributes
  3486. +};
  3487. +
  3488. +static struct device *yeeloong_hwmon_dev;
  3489. +
  3490. +static int yeeloong_hwmon_init(void)
  3491. +{
  3492. + int ret;
  3493. +
  3494. + yeeloong_hwmon_dev = hwmon_device_register(NULL);
  3495. + if (IS_ERR(yeeloong_hwmon_dev)) {
  3496. + pr_err("Fail to register yeeloong hwmon device\n");
  3497. + yeeloong_hwmon_dev = NULL;
  3498. + return PTR_ERR(yeeloong_hwmon_dev);
  3499. + }
  3500. + ret = sysfs_create_group(&yeeloong_hwmon_dev->kobj,
  3501. + &hwmon_attribute_group);
  3502. + if (ret) {
  3503. + hwmon_device_unregister(yeeloong_hwmon_dev);
  3504. + yeeloong_hwmon_dev = NULL;
  3505. + return ret;
  3506. + }
  3507. + /* ensure fan is set to auto mode */
  3508. + set_fan_pwm_enable(2);
  3509. +
  3510. + return 0;
  3511. +}
  3512. +
  3513. +static void yeeloong_hwmon_exit(void)
  3514. +{
  3515. + if (yeeloong_hwmon_dev) {
  3516. + sysfs_remove_group(&yeeloong_hwmon_dev->kobj,
  3517. + &hwmon_attribute_group);
  3518. + hwmon_device_unregister(yeeloong_hwmon_dev);
  3519. + yeeloong_hwmon_dev = NULL;
  3520. + }
  3521. +}
  3522. +
  3523. +/* video output subdriver */
  3524. +
  3525. +static int lcd_video_output_get(struct output_device *od)
  3526. +{
  3527. + return ec_read(REG_DISPLAY_LCD);
  3528. +}
  3529. +
  3530. +#define LCD 0
  3531. +#define CRT 1
  3532. +
  3533. +static void display_vo_set(int display, int on)
  3534. +{
  3535. + int addr;
  3536. + unsigned long value;
  3537. +
  3538. + addr = (display == LCD) ? 0x31 : 0x21;
  3539. +
  3540. + outb(addr, 0x3c4);
  3541. + value = inb(0x3c5);
  3542. +
  3543. + if (display == LCD)
  3544. + value |= (on ? 0x03 : 0x02);
  3545. + else {
  3546. + if (on)
  3547. + clear_bit(7, &value);
  3548. + else
  3549. + set_bit(7, &value);
  3550. + }
  3551. +
  3552. + outb(addr, 0x3c4);
  3553. + outb(value, 0x3c5);
  3554. +}
  3555. +
  3556. +static int lcd_video_output_set(struct output_device *od)
  3557. +{
  3558. + unsigned long status;
  3559. +
  3560. + status = !!od->request_state;
  3561. +
  3562. + display_vo_set(LCD, status);
  3563. + ec_write(REG_BACKLIGHT_CTRL, status);
  3564. +
  3565. + return 0;
  3566. +}
  3567. +
  3568. +static struct output_properties lcd_output_properties = {
  3569. + .set_state = lcd_video_output_set,
  3570. + .get_status = lcd_video_output_get,
  3571. +};
  3572. +
  3573. +static int crt_video_output_get(struct output_device *od)
  3574. +{
  3575. + return ec_read(REG_CRT_DETECT);
  3576. +}
  3577. +
  3578. +static int crt_video_output_set(struct output_device *od)
  3579. +{
  3580. + unsigned long status;
  3581. +
  3582. + status = !!od->request_state;
  3583. +
  3584. + if (ec_read(REG_CRT_DETECT) == BIT_CRT_DETECT_PLUG)
  3585. + display_vo_set(CRT, status);
  3586. +
  3587. + return 0;
  3588. +}
  3589. +
  3590. +static struct output_properties crt_output_properties = {
  3591. + .set_state = crt_video_output_set,
  3592. + .get_status = crt_video_output_get,
  3593. +};
  3594. +
  3595. +static struct output_device *lcd_output_dev, *crt_output_dev;
  3596. +
  3597. +static void yeeloong_lcd_vo_set(int status)
  3598. +{
  3599. + lcd_output_dev->request_state = status;
  3600. + lcd_video_output_set(lcd_output_dev);
  3601. +}
  3602. +
  3603. +static void yeeloong_crt_vo_set(int status)
  3604. +{
  3605. + crt_output_dev->request_state = status;
  3606. + crt_video_output_set(crt_output_dev);
  3607. +}
  3608. +
  3609. +static int yeeloong_vo_init(void)
  3610. +{
  3611. + int ret;
  3612. +
  3613. + /* Register video output device: lcd, crt */
  3614. + lcd_output_dev = video_output_register("LCD", NULL, NULL,
  3615. + &lcd_output_properties);
  3616. +
  3617. + if (IS_ERR(lcd_output_dev)) {
  3618. + ret = PTR_ERR(lcd_output_dev);
  3619. + lcd_output_dev = NULL;
  3620. + return ret;
  3621. + }
  3622. + /* Ensure LCD is on by default */
  3623. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON);
  3624. +
  3625. + crt_output_dev = video_output_register("CRT", NULL, NULL,
  3626. + &crt_output_properties);
  3627. +
  3628. + if (IS_ERR(crt_output_dev)) {
  3629. + ret = PTR_ERR(crt_output_dev);
  3630. + crt_output_dev = NULL;
  3631. + return ret;
  3632. + }
  3633. +
  3634. + /* Turn off CRT by default, and will be enabled when the CRT
  3635. + * connectting event reported by SCI */
  3636. + yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG);
  3637. +
  3638. + return 0;
  3639. +}
  3640. +
  3641. +static void yeeloong_vo_exit(void)
  3642. +{
  3643. + if (lcd_output_dev) {
  3644. + video_output_unregister(lcd_output_dev);
  3645. + lcd_output_dev = NULL;
  3646. + }
  3647. + if (crt_output_dev) {
  3648. + video_output_unregister(crt_output_dev);
  3649. + crt_output_dev = NULL;
  3650. + }
  3651. +}
  3652. +
  3653. +/* hotkey subdriver */
  3654. +
  3655. +static struct input_dev *yeeloong_hotkey_dev;
  3656. +
  3657. +static const struct key_entry yeeloong_keymap[] = {
  3658. + {KE_SW, EVENT_LID, { SW_LID } },
  3659. + {KE_KEY, EVENT_CAMERA, { KEY_CAMERA } }, /* Fn + ESC */
  3660. + {KE_KEY, EVENT_SLEEP, { KEY_SLEEP } }, /* Fn + F1 */
  3661. + {KE_KEY, EVENT_DISPLAYTOGGLE, { KEY_DISPLAYTOGGLE } }, /* Fn + F2 */
  3662. + {KE_KEY, EVENT_SWITCHVIDEOMODE, { KEY_SWITCHVIDEOMODE } }, /* Fn + F3 */
  3663. + {KE_KEY, EVENT_AUDIO_MUTE, { KEY_MUTE } }, /* Fn + F4 */
  3664. + {KE_KEY, EVENT_WLAN, { KEY_WLAN } }, /* Fn + F5 */
  3665. + {KE_KEY, EVENT_DISPLAY_BRIGHTNESS, { KEY_BRIGHTNESSUP } }, /* Fn + up */
  3666. + {KE_KEY, EVENT_DISPLAY_BRIGHTNESS, { KEY_BRIGHTNESSDOWN } }, /* Fn + down */
  3667. + {KE_KEY, EVENT_AUDIO_VOLUME, { KEY_VOLUMEUP } }, /* Fn + right */
  3668. + {KE_KEY, EVENT_AUDIO_VOLUME, { KEY_VOLUMEDOWN } }, /* Fn + left */
  3669. + {KE_END, 0}
  3670. +};
  3671. +
  3672. +static struct key_entry *get_event_key_entry(int event, int status)
  3673. +{
  3674. + struct key_entry *ke;
  3675. + static int old_brightness_status = -1;
  3676. + static int old_volume_status = -1;
  3677. +
  3678. + ke = sparse_keymap_entry_from_scancode(yeeloong_hotkey_dev, event);
  3679. + if (!ke)
  3680. + return NULL;
  3681. +
  3682. + switch (event) {
  3683. + case EVENT_DISPLAY_BRIGHTNESS:
  3684. + /* current status > old one, means up */
  3685. + if ((status < old_brightness_status) || (0 == status))
  3686. + ke++;
  3687. + old_brightness_status = status;
  3688. + break;
  3689. + case EVENT_AUDIO_VOLUME:
  3690. + if ((status < old_volume_status) || (0 == status))
  3691. + ke++;
  3692. + old_volume_status = status;
  3693. + break;
  3694. + default:
  3695. + break;
  3696. + }
  3697. +
  3698. + return ke;
  3699. +}
  3700. +
  3701. +static int report_lid_switch(int status)
  3702. +{
  3703. + input_report_switch(yeeloong_hotkey_dev, SW_LID, !status);
  3704. + input_sync(yeeloong_hotkey_dev);
  3705. +
  3706. + return status;
  3707. +}
  3708. +
  3709. +static int crt_detect_handler(int status)
  3710. +{
  3711. + if (status) {
  3712. + yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG);
  3713. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF);
  3714. + } else {
  3715. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON);
  3716. + yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG);
  3717. + }
  3718. + return status;
  3719. +}
  3720. +
  3721. +static int displaytoggle_handler(int status)
  3722. +{
  3723. + /* EC(>=PQ1D26) does this job for us, we can not do it again,
  3724. + * otherwise, the brightness will not resume to the normal level! */
  3725. + if (ec_version_before("EC_VER=PQ1D26"))
  3726. + yeeloong_lcd_vo_set(status);
  3727. +
  3728. + return status;
  3729. +}
  3730. +
  3731. +static int switchvideomode_handler(int status)
  3732. +{
  3733. + static int video_output_status;
  3734. +
  3735. + /* Only enable switch video output button
  3736. + * when CRT is connected */
  3737. + if (ec_read(REG_CRT_DETECT) == BIT_CRT_DETECT_UNPLUG)
  3738. + return 0;
  3739. + /* 0. no CRT connected: LCD on, CRT off
  3740. + * 1. BOTH on
  3741. + * 2. LCD off, CRT on
  3742. + * 3. BOTH off
  3743. + * 4. LCD on, CRT off
  3744. + */
  3745. + video_output_status++;
  3746. + if (video_output_status > 4)
  3747. + video_output_status = 1;
  3748. +
  3749. + switch (video_output_status) {
  3750. + case 1:
  3751. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON);
  3752. + yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG);
  3753. + break;
  3754. + case 2:
  3755. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF);
  3756. + yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG);
  3757. + break;
  3758. + case 3:
  3759. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF);
  3760. + yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG);
  3761. + break;
  3762. + case 4:
  3763. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON);
  3764. + yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG);
  3765. + break;
  3766. + default:
  3767. + /* Ensure LCD is on */
  3768. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON);
  3769. + break;
  3770. + }
  3771. + return video_output_status;
  3772. +}
  3773. +
  3774. +static int camera_handler(int status)
  3775. +{
  3776. + int value;
  3777. +
  3778. + value = ec_read(REG_CAMERA_CONTROL);
  3779. + ec_write(REG_CAMERA_CONTROL, value | (1 << 1));
  3780. +
  3781. + return status;
  3782. +}
  3783. +
  3784. +static int usb2_handler(int status)
  3785. +{
  3786. + pr_emerg("USB2 Over Current occurred\n");
  3787. +
  3788. + return status;
  3789. +}
  3790. +
  3791. +static int usb0_handler(int status)
  3792. +{
  3793. + pr_emerg("USB0 Over Current occurred\n");
  3794. +
  3795. + return status;
  3796. +}
  3797. +
  3798. +static int ac_bat_handler(int status)
  3799. +{
  3800. + if (ac_bat_initialized) {
  3801. + power_supply_changed(&yeeloong_ac);
  3802. + power_supply_changed(&yeeloong_bat);
  3803. + }
  3804. + return status;
  3805. +}
  3806. +
  3807. +static void do_event_action(int event)
  3808. +{
  3809. + sci_handler handler;
  3810. + int reg, status;
  3811. + struct key_entry *ke;
  3812. +
  3813. + reg = 0;
  3814. + handler = NULL;
  3815. +
  3816. + switch (event) {
  3817. + case EVENT_LID:
  3818. + reg = REG_LID_DETECT;
  3819. + break;
  3820. + case EVENT_SWITCHVIDEOMODE:
  3821. + handler = switchvideomode_handler;
  3822. + break;
  3823. + case EVENT_CRT_DETECT:
  3824. + reg = REG_CRT_DETECT;
  3825. + handler = crt_detect_handler;
  3826. + break;
  3827. + case EVENT_CAMERA:
  3828. + reg = REG_CAMERA_STATUS;
  3829. + handler = camera_handler;
  3830. + break;
  3831. + case EVENT_USB_OC2:
  3832. + reg = REG_USB2_FLAG;
  3833. + handler = usb2_handler;
  3834. + break;
  3835. + case EVENT_USB_OC0:
  3836. + reg = REG_USB0_FLAG;
  3837. + handler = usb0_handler;
  3838. + break;
  3839. + case EVENT_DISPLAYTOGGLE:
  3840. + reg = REG_DISPLAY_LCD;
  3841. + handler = displaytoggle_handler;
  3842. + break;
  3843. + case EVENT_AUDIO_MUTE:
  3844. + reg = REG_AUDIO_MUTE;
  3845. + break;
  3846. + case EVENT_DISPLAY_BRIGHTNESS:
  3847. + reg = REG_DISPLAY_BRIGHTNESS;
  3848. + break;
  3849. + case EVENT_AUDIO_VOLUME:
  3850. + reg = REG_AUDIO_VOLUME;
  3851. + break;
  3852. + case EVENT_AC_BAT:
  3853. + handler = ac_bat_handler;
  3854. + break;
  3855. + default:
  3856. + break;
  3857. + }
  3858. +
  3859. + if (reg != 0)
  3860. + status = ec_read(reg);
  3861. +
  3862. + if (handler != NULL)
  3863. + status = handler(status);
  3864. +
  3865. + pr_info("%s: event: %d status: %d\n", __func__, event, status);
  3866. +
  3867. + /* Report current key to user-space */
  3868. + ke = get_event_key_entry(event, status);
  3869. + if (ke) {
  3870. + if (ke->keycode == SW_LID)
  3871. + report_lid_switch(status);
  3872. + else
  3873. + sparse_keymap_report_entry(yeeloong_hotkey_dev, ke, 1,
  3874. + true);
  3875. + }
  3876. +}
  3877. +
  3878. +/*
  3879. + * SCI(system control interrupt) main interrupt routine
  3880. + *
  3881. + * We will do the query and get event number together so the interrupt routine
  3882. + * should be longer than 120us now at least 3ms elpase for it.
  3883. + */
  3884. +static irqreturn_t sci_irq_handler(int irq, void *dev_id)
  3885. +{
  3886. + int ret, event;
  3887. +
  3888. + if (SCI_IRQ_NUM != irq)
  3889. + return IRQ_NONE;
  3890. +
  3891. + /* Query the event number */
  3892. + ret = ec_query_event_num();
  3893. + if (ret < 0)
  3894. + return IRQ_NONE;
  3895. +
  3896. + event = ec_get_event_num();
  3897. + if (event < EVENT_START || event > EVENT_END)
  3898. + return IRQ_NONE;
  3899. +
  3900. + /* Execute corresponding actions */
  3901. + do_event_action(event);
  3902. +
  3903. + return IRQ_HANDLED;
  3904. +}
  3905. +
  3906. +/*
  3907. + * Config and init some msr and gpio register properly.
  3908. + */
  3909. +static int sci_irq_init(void)
  3910. +{
  3911. + u32 hi, lo;
  3912. + u32 gpio_base;
  3913. + unsigned long flags;
  3914. + int ret;
  3915. +
  3916. + /* Get gpio base */
  3917. + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
  3918. + gpio_base = lo & 0xff00;
  3919. +
  3920. + /* Filter the former kb3310 interrupt for security */
  3921. + ret = ec_query_event_num();
  3922. + if (ret)
  3923. + return ret;
  3924. +
  3925. + /* For filtering next number interrupt */
  3926. + udelay(10000);
  3927. +
  3928. + /* Set gpio native registers and msrs for GPIO27 SCI EVENT PIN
  3929. + * gpio :
  3930. + * input, pull-up, no-invert, event-count and value 0,
  3931. + * no-filter, no edge mode
  3932. + * gpio27 map to Virtual gpio0
  3933. + * msr :
  3934. + * no primary and lpc
  3935. + * Unrestricted Z input to IG10 from Virtual gpio 0.
  3936. + */
  3937. + local_irq_save(flags);
  3938. + _rdmsr(0x80000024, &hi, &lo);
  3939. + lo &= ~(1 << 10);
  3940. + _wrmsr(0x80000024, hi, lo);
  3941. + _rdmsr(0x80000025, &hi, &lo);
  3942. + lo &= ~(1 << 10);
  3943. + _wrmsr(0x80000025, hi, lo);
  3944. + _rdmsr(0x80000023, &hi, &lo);
  3945. + lo |= (0x0a << 0);
  3946. + _wrmsr(0x80000023, hi, lo);
  3947. + local_irq_restore(flags);
  3948. +
  3949. + /* Set gpio27 as sci interrupt
  3950. + *
  3951. + * input, pull-up, no-fliter, no-negedge, invert
  3952. + * the sci event is just about 120us
  3953. + */
  3954. + asm(".set noreorder\n");
  3955. + /* input enable */
  3956. + outl(0x00000800, (gpio_base | 0xA0));
  3957. + /* revert the input */
  3958. + outl(0x00000800, (gpio_base | 0xA4));
  3959. + /* event-int enable */
  3960. + outl(0x00000800, (gpio_base | 0xB8));
  3961. + asm(".set reorder\n");
  3962. +
  3963. + return 0;
  3964. +}
  3965. +
  3966. +static struct irqaction sci_irqaction = {
  3967. + .handler = sci_irq_handler,
  3968. + .name = "sci",
  3969. + .flags = IRQF_SHARED,
  3970. +};
  3971. +
  3972. +static int yeeloong_hotkey_init(void)
  3973. +{
  3974. + int ret;
  3975. +
  3976. + ret = sci_irq_init();
  3977. + if (ret)
  3978. + return -EFAULT;
  3979. +
  3980. + ret = setup_irq(SCI_IRQ_NUM, &sci_irqaction);
  3981. + if (ret)
  3982. + return -EFAULT;
  3983. +
  3984. + yeeloong_hotkey_dev = input_allocate_device();
  3985. +
  3986. + if (!yeeloong_hotkey_dev) {
  3987. + remove_irq(SCI_IRQ_NUM, &sci_irqaction);
  3988. + return -ENOMEM;
  3989. + }
  3990. +
  3991. + yeeloong_hotkey_dev->name = "HotKeys";
  3992. + yeeloong_hotkey_dev->phys = "button/input0";
  3993. + yeeloong_hotkey_dev->id.bustype = BUS_HOST;
  3994. + yeeloong_hotkey_dev->dev.parent = NULL;
  3995. +
  3996. + ret = sparse_keymap_setup(yeeloong_hotkey_dev, yeeloong_keymap, NULL);
  3997. + if (ret) {
  3998. + pr_err("Fail to setup input device keymap\n");
  3999. + input_free_device(yeeloong_hotkey_dev);
  4000. + return ret;
  4001. + }
  4002. +
  4003. + ret = input_register_device(yeeloong_hotkey_dev);
  4004. + if (ret) {
  4005. + sparse_keymap_free(yeeloong_hotkey_dev);
  4006. + input_free_device(yeeloong_hotkey_dev);
  4007. + return ret;
  4008. + }
  4009. +
  4010. + /* Update the current status of LID */
  4011. + report_lid_switch(BIT_LID_DETECT_ON);
  4012. +
  4013. +#ifdef CONFIG_LOONGSON_SUSPEND
  4014. + /* Install the real yeeloong_report_lid_status for pm.c */
  4015. + yeeloong_report_lid_status = report_lid_switch;
  4016. +#endif
  4017. +
  4018. + return 0;
  4019. +}
  4020. +
  4021. +static void yeeloong_hotkey_exit(void)
  4022. +{
  4023. + /* Free irq */
  4024. + remove_irq(SCI_IRQ_NUM, &sci_irqaction);
  4025. +
  4026. +#ifdef CONFIG_LOONGSON_SUSPEND
  4027. + /* Uninstall yeeloong_report_lid_status for pm.c */
  4028. + if (yeeloong_report_lid_status == report_lid_switch)
  4029. + yeeloong_report_lid_status = NULL;
  4030. +#endif
  4031. +
  4032. + if (yeeloong_hotkey_dev) {
  4033. + sparse_keymap_free(yeeloong_hotkey_dev);
  4034. + input_unregister_device(yeeloong_hotkey_dev);
  4035. + yeeloong_hotkey_dev = NULL;
  4036. + }
  4037. +}
  4038. +
  4039. +#ifdef CONFIG_PM
  4040. +static void usb_ports_set(int status)
  4041. +{
  4042. + status = !!status;
  4043. +
  4044. + ec_write(REG_USB0_FLAG, status);
  4045. + ec_write(REG_USB1_FLAG, status);
  4046. + ec_write(REG_USB2_FLAG, status);
  4047. +}
  4048. +
  4049. +static int yeeloong_suspend(struct device *dev)
  4050. +
  4051. +{
  4052. + if (ec_version_before("EC_VER=PQ1D27"))
  4053. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF);
  4054. + yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG);
  4055. + usb_ports_set(BIT_USB_FLAG_OFF);
  4056. +
  4057. + return 0;
  4058. +}
  4059. +
  4060. +static int yeeloong_resume(struct device *dev)
  4061. +{
  4062. + if (ec_version_before("EC_VER=PQ1D27"))
  4063. + yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON);
  4064. + yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG);
  4065. + usb_ports_set(BIT_USB_FLAG_ON);
  4066. +
  4067. + return 0;
  4068. +}
  4069. +
  4070. +static const SIMPLE_DEV_PM_OPS(yeeloong_pm_ops, yeeloong_suspend,
  4071. + yeeloong_resume);
  4072. +#endif
  4073. +
  4074. +static struct platform_device_id platform_device_ids[] = {
  4075. + {
  4076. + .name = "yeeloong_laptop",
  4077. + },
  4078. + {}
  4079. +};
  4080. +
  4081. +MODULE_DEVICE_TABLE(platform, platform_device_ids);
  4082. +
  4083. +static struct platform_driver platform_driver = {
  4084. + .driver = {
  4085. + .name = "yeeloong_laptop",
  4086. + .owner = THIS_MODULE,
  4087. +#ifdef CONFIG_PM
  4088. + .pm = &yeeloong_pm_ops,
  4089. +#endif
  4090. + },
  4091. + .id_table = platform_device_ids,
  4092. +};
  4093. +
  4094. +static int __init yeeloong_init(void)
  4095. +{
  4096. + int ret;
  4097. +
  4098. + pr_info("Load YeeLoong Laptop Platform Specific Driver.\n");
  4099. +
  4100. + /* Register platform stuff */
  4101. + ret = platform_driver_register(&platform_driver);
  4102. + if (ret) {
  4103. + pr_err("Fail to register yeeloong platform driver.\n");
  4104. + return ret;
  4105. + }
  4106. +
  4107. + ret = yeeloong_backlight_init();
  4108. + if (ret) {
  4109. + pr_err("Fail to register yeeloong backlight driver.\n");
  4110. + yeeloong_backlight_exit();
  4111. + return ret;
  4112. + }
  4113. +
  4114. + ret = yeeloong_bat_init();
  4115. + if (ret) {
  4116. + pr_err("Fail to register yeeloong battery driver.\n");
  4117. + yeeloong_bat_exit();
  4118. + return ret;
  4119. + }
  4120. +
  4121. + ret = yeeloong_hwmon_init();
  4122. + if (ret) {
  4123. + pr_err("Fail to register yeeloong hwmon driver.\n");
  4124. + yeeloong_hwmon_exit();
  4125. + return ret;
  4126. + }
  4127. +
  4128. + ret = yeeloong_vo_init();
  4129. + if (ret) {
  4130. + pr_err("Fail to register yeeloong video output driver.\n");
  4131. + yeeloong_vo_exit();
  4132. + return ret;
  4133. + }
  4134. +
  4135. + ret = yeeloong_hotkey_init();
  4136. + if (ret) {
  4137. + pr_err("Fail to register yeeloong hotkey driver.\n");
  4138. + yeeloong_hotkey_exit();
  4139. + return ret;
  4140. + }
  4141. +
  4142. + return 0;
  4143. +}
  4144. +
  4145. +static void __exit yeeloong_exit(void)
  4146. +{
  4147. + yeeloong_hotkey_exit();
  4148. + yeeloong_vo_exit();
  4149. + yeeloong_hwmon_exit();
  4150. + yeeloong_bat_exit();
  4151. + yeeloong_backlight_exit();
  4152. + platform_driver_unregister(&platform_driver);
  4153. +
  4154. + pr_info("Unload YeeLoong Platform Specific Driver.\n");
  4155. +}
  4156. +
  4157. +module_init(yeeloong_init);
  4158. +module_exit(yeeloong_exit);
  4159. +
  4160. +MODULE_AUTHOR("Wu Zhangjin <wuzhangjin@gmail.com>; Liu Junliang <liujl@lemote.com>");
  4161. +MODULE_DESCRIPTION("YeeLoong laptop driver");
  4162. +MODULE_LICENSE("GPL");
  4163. diff -Nur linux-2.6.36.orig/drivers/staging/sm7xx/smtcfb.c linux-2.6.36/drivers/staging/sm7xx/smtcfb.c
  4164. --- linux-2.6.36.orig/drivers/staging/sm7xx/smtcfb.c 2010-10-20 22:30:22.000000000 +0200
  4165. +++ linux-2.6.36/drivers/staging/sm7xx/smtcfb.c 2010-12-17 23:12:59.000000000 +0100
  4166. @@ -12,6 +12,8 @@
  4167. * License. See the file COPYING in the main directory of this archive for
  4168. * more details.
  4169. *
  4170. + * - Remove the buggy 2D support for Lynx, 2010/01/06, Wu Zhangjin
  4171. + *
  4172. * Version 0.10.26192.21.01
  4173. * - Add PowerPC/Big endian support
  4174. * - Add 2D support for Lynx
  4175. @@ -107,6 +109,7 @@
  4176. {"0x307", 1280, 1024, 8},
  4177. {"0x311", 640, 480, 16},
  4178. + {"0x313", 800, 480, 16},
  4179. {"0x314", 800, 600, 16},
  4180. {"0x317", 1024, 768, 16},
  4181. {"0x31A", 1280, 1024, 16},
  4182. diff -Nur linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c linux-2.6.36/drivers/usb/host/ohci-hcd.c
  4183. --- linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c 2010-10-20 22:30:22.000000000 +0200
  4184. +++ linux-2.6.36/drivers/usb/host/ohci-hcd.c 2010-12-17 23:12:59.000000000 +0100
  4185. @@ -832,9 +832,13 @@
  4186. }
  4187. if (ints & OHCI_INTR_WDH) {
  4188. - spin_lock (&ohci->lock);
  4189. - dl_done_list (ohci);
  4190. - spin_unlock (&ohci->lock);
  4191. + if (ohci->hcca->done_head == 0) {
  4192. + ints &= ~OHCI_INTR_WDH;
  4193. + } else {
  4194. + spin_lock (&ohci->lock);
  4195. + dl_done_list (ohci);
  4196. + spin_unlock (&ohci->lock);
  4197. + }
  4198. }
  4199. if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
  4200. diff -Nur linux-2.6.36.orig/net/rfkill/core.c linux-2.6.36/net/rfkill/core.c
  4201. --- linux-2.6.36.orig/net/rfkill/core.c 2010-10-20 22:30:22.000000000 +0200
  4202. +++ linux-2.6.36/net/rfkill/core.c 2010-12-17 23:12:59.000000000 +0100
  4203. @@ -112,7 +112,7 @@
  4204. static DEFINE_MUTEX(rfkill_global_mutex);
  4205. static LIST_HEAD(rfkill_fds); /* list of open fds of /dev/rfkill */
  4206. -static unsigned int rfkill_default_state = 1;
  4207. +static unsigned int rfkill_default_state; /* default: 0 = radio off */
  4208. module_param_named(default_state, rfkill_default_state, uint, 0444);
  4209. MODULE_PARM_DESC(default_state,
  4210. "Default initial state for all radio types, 0 = radio off");