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avr32.patch 896 KB

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  1. --- a/bfd/archures.c
  2. +++ b/bfd/archures.c
  3. @@ -368,6 +368,12 @@ DESCRIPTION
  4. .#define bfd_mach_avr5 5
  5. .#define bfd_mach_avr51 51
  6. .#define bfd_mach_avr6 6
  7. +. bfd_arch_avr32, {* Atmel AVR32 *}
  8. +.#define bfd_mach_avr32_ap 7000
  9. +.#define bfd_mach_avr32_uc 3000
  10. +.#define bfd_mach_avr32_ucr1 3001
  11. +.#define bfd_mach_avr32_ucr2 3002
  12. +.#define bfd_mach_avr32_ucr3 3003
  13. . bfd_arch_bfin, {* ADI Blackfin *}
  14. .#define bfd_mach_bfin 1
  15. . bfd_arch_cr16, {* National Semiconductor CompactRISC (ie CR16). *}
  16. @@ -465,6 +471,7 @@ extern const bfd_arch_info_type bfd_alph
  17. extern const bfd_arch_info_type bfd_arc_arch;
  18. extern const bfd_arch_info_type bfd_arm_arch;
  19. extern const bfd_arch_info_type bfd_avr_arch;
  20. +extern const bfd_arch_info_type bfd_avr32_arch;
  21. extern const bfd_arch_info_type bfd_bfin_arch;
  22. extern const bfd_arch_info_type bfd_cr16_arch;
  23. extern const bfd_arch_info_type bfd_cr16c_arch;
  24. @@ -541,6 +548,7 @@ static const bfd_arch_info_type * const
  25. &bfd_arc_arch,
  26. &bfd_arm_arch,
  27. &bfd_avr_arch,
  28. + &bfd_avr32_arch,
  29. &bfd_bfin_arch,
  30. &bfd_cr16_arch,
  31. &bfd_cr16c_arch,
  32. --- a/bfd/config.bfd
  33. +++ b/bfd/config.bfd
  34. @@ -347,6 +347,10 @@ case "${targ}" in
  35. targ_underscore=yes
  36. ;;
  37. + avr32-*-*)
  38. + targ_defvec=bfd_elf32_avr32_vec
  39. + ;;
  40. +
  41. c30-*-*aout* | tic30-*-*aout*)
  42. targ_defvec=tic30_aout_vec
  43. ;;
  44. --- a/bfd/configure.in
  45. +++ b/bfd/configure.in
  46. @@ -675,6 +675,7 @@ do
  47. bfd_pei_ia64_vec) tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
  48. bfd_elf32_am33lin_vec) tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
  49. bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
  50. + bfd_elf32_avr32_vec) tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
  51. bfd_elf32_bfin_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
  52. bfd_elf32_bfinfdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
  53. bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
  54. --- /dev/null
  55. +++ b/bfd/cpu-avr32.c
  56. @@ -0,0 +1,52 @@
  57. +/* BFD library support routines for AVR32.
  58. + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  59. +
  60. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  61. +
  62. + This is part of BFD, the Binary File Descriptor library.
  63. +
  64. + This program is free software; you can redistribute it and/or modify
  65. + it under the terms of the GNU General Public License as published by
  66. + the Free Software Foundation; either version 2 of the License, or
  67. + (at your option) any later version.
  68. +
  69. + This program is distributed in the hope that it will be useful,
  70. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  71. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  72. + GNU General Public License for more details.
  73. +
  74. + You should have received a copy of the GNU General Public License
  75. + along with this program; if not, write to the Free Software
  76. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  77. +
  78. +#include "bfd.h"
  79. +#include "sysdep.h"
  80. +#include "libbfd.h"
  81. +
  82. +#define N(machine, print, default, next) \
  83. + { \
  84. + 32, /* 32 bits in a word */ \
  85. + 32, /* 32 bits in an address */ \
  86. + 8, /* 8 bits in a byte */ \
  87. + bfd_arch_avr32, /* architecture */ \
  88. + machine, /* machine */ \
  89. + "avr32", /* arch name */ \
  90. + print, /* printable name */ \
  91. + 1, /* section align power */ \
  92. + default, /* the default machine? */ \
  93. + bfd_default_compatible, \
  94. + bfd_default_scan, \
  95. + next, \
  96. + }
  97. +
  98. +static const bfd_arch_info_type cpu_info[] =
  99. +{
  100. + N(bfd_mach_avr32_ap, "avr32:ap", FALSE, &cpu_info[1]),
  101. + N(bfd_mach_avr32_uc, "avr32:uc", FALSE, &cpu_info[2]),
  102. + N(bfd_mach_avr32_ucr1, "avr32:ucr1", FALSE, &cpu_info[3]),
  103. + N(bfd_mach_avr32_ucr2, "avr32:ucr2", FALSE, &cpu_info[4]),
  104. + N(bfd_mach_avr32_ucr3, "avr32:ucr3", FALSE, NULL),
  105. +};
  106. +
  107. +const bfd_arch_info_type bfd_avr32_arch =
  108. + N(bfd_mach_avr32_ap, "avr32", TRUE, &cpu_info[0]);
  109. --- /dev/null
  110. +++ b/bfd/elf32-avr32.c
  111. @@ -0,0 +1,3915 @@
  112. +/* AVR32-specific support for 32-bit ELF.
  113. + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  114. +
  115. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  116. +
  117. + This file is part of BFD, the Binary File Descriptor library.
  118. +
  119. + This program is free software; you can redistribute it and/or modify
  120. + it under the terms of the GNU General Public License as published by
  121. + the Free Software Foundation; either version 2 of the License, or
  122. + (at your option) any later version.
  123. +
  124. + This program is distributed in the hope that it will be useful,
  125. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  126. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  127. + GNU General Public License for more details.
  128. +
  129. + You should have received a copy of the GNU General Public License
  130. + along with this program; if not, write to the Free Software
  131. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  132. +
  133. +#include "bfd.h"
  134. +#include "sysdep.h"
  135. +#include "bfdlink.h"
  136. +#include "libbfd.h"
  137. +#include "elf-bfd.h"
  138. +#include "elf/avr32.h"
  139. +#include "elf32-avr32.h"
  140. +
  141. +#define xDEBUG
  142. +#define xRELAX_DEBUG
  143. +
  144. +#ifdef DEBUG
  145. +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
  146. +#else
  147. +# define pr_debug(fmt, args...) do { } while (0)
  148. +#endif
  149. +
  150. +#ifdef RELAX_DEBUG
  151. +# define RDBG(fmt, args...) fprintf(stderr, fmt, ##args)
  152. +#else
  153. +# define RDBG(fmt, args...) do { } while (0)
  154. +#endif
  155. +
  156. +/* When things go wrong, we want it to blow up, damnit! */
  157. +#undef BFD_ASSERT
  158. +#undef abort
  159. +#define BFD_ASSERT(expr) \
  160. + do \
  161. + { \
  162. + if (!(expr)) \
  163. + { \
  164. + bfd_assert(__FILE__, __LINE__); \
  165. + abort(); \
  166. + } \
  167. + } \
  168. + while (0)
  169. +
  170. +/* The name of the dynamic interpreter. This is put in the .interp section. */
  171. +#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1"
  172. +
  173. +#define AVR32_GOT_HEADER_SIZE 8
  174. +#define AVR32_FUNCTION_STUB_SIZE 8
  175. +
  176. +#define ELF_R_INFO(x, y) ELF32_R_INFO(x, y)
  177. +#define ELF_R_TYPE(x) ELF32_R_TYPE(x)
  178. +#define ELF_R_SYM(x) ELF32_R_SYM(x)
  179. +
  180. +#define NOP_OPCODE 0xd703
  181. +
  182. +
  183. +/* Mapping between BFD relocations and ELF relocations */
  184. +
  185. +static reloc_howto_type *
  186. +bfd_elf32_bfd_reloc_type_lookup(bfd *abfd, bfd_reloc_code_real_type code);
  187. +
  188. +static reloc_howto_type *
  189. +bfd_elf32_bfd_reloc_name_lookup(bfd *abfd, const char *r_name);
  190. +
  191. +static void
  192. +avr32_info_to_howto (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst);
  193. +
  194. +/* Generic HOWTO */
  195. +#define GENH(name, align, size, bitsize, pcrel, bitpos, complain, mask) \
  196. + HOWTO(name, align, size, bitsize, pcrel, bitpos, \
  197. + complain_overflow_##complain, bfd_elf_generic_reloc, #name, \
  198. + FALSE, 0, mask, pcrel)
  199. +
  200. +static reloc_howto_type elf_avr32_howto_table[] = {
  201. + /* NAME ALN SZ BSZ PCREL BP COMPLAIN MASK */
  202. + GENH(R_AVR32_NONE, 0, 0, 0, FALSE, 0, dont, 0x00000000),
  203. +
  204. + GENH(R_AVR32_32, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
  205. + GENH(R_AVR32_16, 0, 1, 16, FALSE, 0, bitfield, 0x0000ffff),
  206. + GENH(R_AVR32_8, 0, 0, 8, FALSE, 0, bitfield, 0x000000ff),
  207. + GENH(R_AVR32_32_PCREL, 0, 2, 32, TRUE, 0, signed, 0xffffffff),
  208. + GENH(R_AVR32_16_PCREL, 0, 1, 16, TRUE, 0, signed, 0x0000ffff),
  209. + GENH(R_AVR32_8_PCREL, 0, 0, 8, TRUE, 0, signed, 0x000000ff),
  210. +
  211. + /* Difference between two symbol (sym2 - sym1). The reloc encodes
  212. + the value of sym1. The field contains the difference before any
  213. + relaxing is done. */
  214. + GENH(R_AVR32_DIFF32, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
  215. + GENH(R_AVR32_DIFF16, 0, 1, 16, FALSE, 0, signed, 0x0000ffff),
  216. + GENH(R_AVR32_DIFF8, 0, 0, 8, FALSE, 0, signed, 0x000000ff),
  217. +
  218. + GENH(R_AVR32_GOT32, 0, 2, 32, FALSE, 0, signed, 0xffffffff),
  219. + GENH(R_AVR32_GOT16, 0, 1, 16, FALSE, 0, signed, 0x0000ffff),
  220. + GENH(R_AVR32_GOT8, 0, 0, 8, FALSE, 0, signed, 0x000000ff),
  221. +
  222. + GENH(R_AVR32_21S, 0, 2, 21, FALSE, 0, signed, 0x1e10ffff),
  223. + GENH(R_AVR32_16U, 0, 2, 16, FALSE, 0, unsigned, 0x0000ffff),
  224. + GENH(R_AVR32_16S, 0, 2, 16, FALSE, 0, signed, 0x0000ffff),
  225. + GENH(R_AVR32_8S, 0, 1, 8, FALSE, 4, signed, 0x00000ff0),
  226. + GENH(R_AVR32_8S_EXT, 0, 2, 8, FALSE, 0, signed, 0x000000ff),
  227. +
  228. + GENH(R_AVR32_22H_PCREL, 1, 2, 21, TRUE, 0, signed, 0x1e10ffff),
  229. + GENH(R_AVR32_18W_PCREL, 2, 2, 16, TRUE, 0, signed, 0x0000ffff),
  230. + GENH(R_AVR32_16B_PCREL, 0, 2, 16, TRUE, 0, signed, 0x0000ffff),
  231. + GENH(R_AVR32_16N_PCREL, 0, 2, 16, TRUE, 0, signed, 0x0000ffff),
  232. + GENH(R_AVR32_14UW_PCREL, 2, 2, 12, TRUE, 0, unsigned, 0x0000f0ff),
  233. + GENH(R_AVR32_11H_PCREL, 1, 1, 10, TRUE, 4, signed, 0x00000ff3),
  234. + GENH(R_AVR32_10UW_PCREL, 2, 2, 8, TRUE, 0, unsigned, 0x000000ff),
  235. + GENH(R_AVR32_9H_PCREL, 1, 1, 8, TRUE, 4, signed, 0x00000ff0),
  236. + GENH(R_AVR32_9UW_PCREL, 2, 1, 7, TRUE, 4, unsigned, 0x000007f0),
  237. +
  238. + GENH(R_AVR32_HI16, 16, 2, 16, FALSE, 0, dont, 0x0000ffff),
  239. + GENH(R_AVR32_LO16, 0, 2, 16, FALSE, 0, dont, 0x0000ffff),
  240. +
  241. + GENH(R_AVR32_GOTPC, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
  242. + GENH(R_AVR32_GOTCALL, 2, 2, 21, FALSE, 0, signed, 0x1e10ffff),
  243. + GENH(R_AVR32_LDA_GOT, 2, 2, 21, FALSE, 0, signed, 0x1e10ffff),
  244. + GENH(R_AVR32_GOT21S, 0, 2, 21, FALSE, 0, signed, 0x1e10ffff),
  245. + GENH(R_AVR32_GOT18SW, 2, 2, 16, FALSE, 0, signed, 0x0000ffff),
  246. + GENH(R_AVR32_GOT16S, 0, 2, 16, FALSE, 0, signed, 0x0000ffff),
  247. + GENH(R_AVR32_GOT7UW, 2, 1, 5, FALSE, 4, unsigned, 0x000001f0),
  248. +
  249. + GENH(R_AVR32_32_CPENT, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
  250. + GENH(R_AVR32_CPCALL, 2, 2, 16, TRUE, 0, signed, 0x0000ffff),
  251. + GENH(R_AVR32_16_CP, 0, 2, 16, TRUE, 0, signed, 0x0000ffff),
  252. + GENH(R_AVR32_9W_CP, 2, 1, 7, TRUE, 4, unsigned, 0x000007f0),
  253. +
  254. + GENH(R_AVR32_RELATIVE, 0, 2, 32, FALSE, 0, signed, 0xffffffff),
  255. + GENH(R_AVR32_GLOB_DAT, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
  256. + GENH(R_AVR32_JMP_SLOT, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
  257. +
  258. + GENH(R_AVR32_ALIGN, 0, 1, 0, FALSE, 0, unsigned, 0x00000000),
  259. +
  260. + GENH(R_AVR32_15S, 2, 2, 15, FALSE, 0, signed, 0x00007fff),
  261. +};
  262. +
  263. +struct elf_reloc_map
  264. +{
  265. + bfd_reloc_code_real_type bfd_reloc_val;
  266. + unsigned char elf_reloc_val;
  267. +};
  268. +
  269. +static const struct elf_reloc_map avr32_reloc_map[] =
  270. +{
  271. + { BFD_RELOC_NONE, R_AVR32_NONE },
  272. +
  273. + { BFD_RELOC_32, R_AVR32_32 },
  274. + { BFD_RELOC_16, R_AVR32_16 },
  275. + { BFD_RELOC_8, R_AVR32_8 },
  276. + { BFD_RELOC_32_PCREL, R_AVR32_32_PCREL },
  277. + { BFD_RELOC_16_PCREL, R_AVR32_16_PCREL },
  278. + { BFD_RELOC_8_PCREL, R_AVR32_8_PCREL },
  279. + { BFD_RELOC_AVR32_DIFF32, R_AVR32_DIFF32 },
  280. + { BFD_RELOC_AVR32_DIFF16, R_AVR32_DIFF16 },
  281. + { BFD_RELOC_AVR32_DIFF8, R_AVR32_DIFF8 },
  282. + { BFD_RELOC_AVR32_GOT32, R_AVR32_GOT32 },
  283. + { BFD_RELOC_AVR32_GOT16, R_AVR32_GOT16 },
  284. + { BFD_RELOC_AVR32_GOT8, R_AVR32_GOT8 },
  285. +
  286. + { BFD_RELOC_AVR32_21S, R_AVR32_21S },
  287. + { BFD_RELOC_AVR32_16U, R_AVR32_16U },
  288. + { BFD_RELOC_AVR32_16S, R_AVR32_16S },
  289. + { BFD_RELOC_AVR32_SUB5, R_AVR32_16S },
  290. + { BFD_RELOC_AVR32_8S_EXT, R_AVR32_8S_EXT },
  291. + { BFD_RELOC_AVR32_8S, R_AVR32_8S },
  292. +
  293. + { BFD_RELOC_AVR32_22H_PCREL, R_AVR32_22H_PCREL },
  294. + { BFD_RELOC_AVR32_18W_PCREL, R_AVR32_18W_PCREL },
  295. + { BFD_RELOC_AVR32_16B_PCREL, R_AVR32_16B_PCREL },
  296. + { BFD_RELOC_AVR32_16N_PCREL, R_AVR32_16N_PCREL },
  297. + { BFD_RELOC_AVR32_11H_PCREL, R_AVR32_11H_PCREL },
  298. + { BFD_RELOC_AVR32_10UW_PCREL, R_AVR32_10UW_PCREL },
  299. + { BFD_RELOC_AVR32_9H_PCREL, R_AVR32_9H_PCREL },
  300. + { BFD_RELOC_AVR32_9UW_PCREL, R_AVR32_9UW_PCREL },
  301. +
  302. + { BFD_RELOC_HI16, R_AVR32_HI16 },
  303. + { BFD_RELOC_LO16, R_AVR32_LO16 },
  304. +
  305. + { BFD_RELOC_AVR32_GOTPC, R_AVR32_GOTPC },
  306. + { BFD_RELOC_AVR32_GOTCALL, R_AVR32_GOTCALL },
  307. + { BFD_RELOC_AVR32_LDA_GOT, R_AVR32_LDA_GOT },
  308. + { BFD_RELOC_AVR32_GOT21S, R_AVR32_GOT21S },
  309. + { BFD_RELOC_AVR32_GOT18SW, R_AVR32_GOT18SW },
  310. + { BFD_RELOC_AVR32_GOT16S, R_AVR32_GOT16S },
  311. + /* GOT7UW should never be generated by the assembler */
  312. +
  313. + { BFD_RELOC_AVR32_32_CPENT, R_AVR32_32_CPENT },
  314. + { BFD_RELOC_AVR32_CPCALL, R_AVR32_CPCALL },
  315. + { BFD_RELOC_AVR32_16_CP, R_AVR32_16_CP },
  316. + { BFD_RELOC_AVR32_9W_CP, R_AVR32_9W_CP },
  317. +
  318. + { BFD_RELOC_AVR32_ALIGN, R_AVR32_ALIGN },
  319. +
  320. + { BFD_RELOC_AVR32_15S, R_AVR32_15S },
  321. +};
  322. +
  323. +static reloc_howto_type *
  324. +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
  325. + bfd_reloc_code_real_type code)
  326. +{
  327. + unsigned int i;
  328. +
  329. + for (i = 0; i < sizeof(avr32_reloc_map) / sizeof(struct elf_reloc_map); i++)
  330. + {
  331. + if (avr32_reloc_map[i].bfd_reloc_val == code)
  332. + return &elf_avr32_howto_table[avr32_reloc_map[i].elf_reloc_val];
  333. + }
  334. +
  335. + return NULL;
  336. +}
  337. +
  338. +static reloc_howto_type *
  339. +bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
  340. + const char *r_name)
  341. +{
  342. + unsigned int i;
  343. +
  344. + for (i = 0;
  345. + i < sizeof (elf_avr32_howto_table) / sizeof (elf_avr32_howto_table[0]);
  346. + i++)
  347. + if (elf_avr32_howto_table[i].name != NULL
  348. + && strcasecmp (elf_avr32_howto_table[i].name, r_name) == 0)
  349. + return &elf_avr32_howto_table[i];
  350. +
  351. + return NULL;
  352. +}
  353. +
  354. +/* Set the howto pointer for an AVR32 ELF reloc. */
  355. +static void
  356. +avr32_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
  357. + arelent *cache_ptr,
  358. + Elf_Internal_Rela *dst)
  359. +{
  360. + unsigned int r_type;
  361. +
  362. + r_type = ELF32_R_TYPE (dst->r_info);
  363. + BFD_ASSERT (r_type < (unsigned int) R_AVR32_max);
  364. + cache_ptr->howto = &elf_avr32_howto_table[r_type];
  365. +}
  366. +
  367. +
  368. +/* AVR32 ELF linker hash table and associated hash entries. */
  369. +
  370. +static struct bfd_hash_entry *
  371. +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
  372. + struct bfd_hash_table *table,
  373. + const char *string);
  374. +static void
  375. +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
  376. + struct elf_link_hash_entry *dir,
  377. + struct elf_link_hash_entry *ind);
  378. +static struct bfd_link_hash_table *
  379. +avr32_elf_link_hash_table_create(bfd *abfd);
  380. +
  381. +/*
  382. + Try to limit memory usage to something reasonable when sorting the
  383. + GOT. If just a couple of entries end up getting more references
  384. + than this, it won't affect performance at all, but if there are many
  385. + of them, we could end up with the wrong symbols being assigned the
  386. + first GOT entries.
  387. +*/
  388. +#define MAX_NR_GOT_HOLES 2048
  389. +
  390. +/*
  391. + AVR32 GOT entry. We need to keep track of refcounts and offsets
  392. + simultaneously, since we need the offsets during relaxation, and we
  393. + also want to be able to drop GOT entries during relaxation. In
  394. + addition to this, we want to keep the list of GOT entries sorted so
  395. + that we can keep the most-used entries at the lowest offsets.
  396. +*/
  397. +struct got_entry
  398. +{
  399. + struct got_entry *next;
  400. + struct got_entry **pprev;
  401. + int refcount;
  402. + bfd_signed_vma offset;
  403. +};
  404. +
  405. +struct elf_avr32_link_hash_entry
  406. +{
  407. + struct elf_link_hash_entry root;
  408. +
  409. + /* Number of runtime relocations against this symbol. */
  410. + unsigned int possibly_dynamic_relocs;
  411. +
  412. + /* If there are anything but R_AVR32_GOT18 relocations against this
  413. + symbol, it means that someone may be taking the address of the
  414. + function, and we should therefore not create a stub. */
  415. + bfd_boolean no_fn_stub;
  416. +
  417. + /* If there is a R_AVR32_32 relocation in a read-only section
  418. + against this symbol, we could be in trouble. If we're linking a
  419. + shared library or this symbol is defined in one, it means we must
  420. + emit a run-time reloc for it and that's not allowed in read-only
  421. + sections. */
  422. + asection *readonly_reloc_sec;
  423. + bfd_vma readonly_reloc_offset;
  424. +
  425. + /* Record which frag (if any) contains the symbol. This is used
  426. + during relaxation in order to avoid having to update all symbols
  427. + whenever we move something. For local symbols, this information
  428. + is in the local_sym_frag member of struct elf_obj_tdata. */
  429. + struct fragment *sym_frag;
  430. +};
  431. +#define avr32_elf_hash_entry(ent) ((struct elf_avr32_link_hash_entry *)(ent))
  432. +
  433. +struct elf_avr32_link_hash_table
  434. +{
  435. + struct elf_link_hash_table root;
  436. +
  437. + /* Shortcuts to get to dynamic linker sections. */
  438. + asection *sgot;
  439. + asection *srelgot;
  440. + asection *sstub;
  441. +
  442. + /* We use a variation of Pigeonhole Sort to sort the GOT. After the
  443. + initial refcounts have been determined, we initialize
  444. + nr_got_holes to the highest refcount ever seen and allocate an
  445. + array of nr_got_holes entries for got_hole. Each GOT entry is
  446. + then stored in this array at the index given by its refcount.
  447. +
  448. + When a GOT entry has its refcount decremented during relaxation,
  449. + it is moved to a lower index in the got_hole array.
  450. + */
  451. + struct got_entry **got_hole;
  452. + int nr_got_holes;
  453. +
  454. + /* Dynamic relocations to local symbols. Only used when linking a
  455. + shared library and -Bsymbolic is not given. */
  456. + unsigned int local_dynamic_relocs;
  457. +
  458. + bfd_boolean relocations_analyzed;
  459. + bfd_boolean symbols_adjusted;
  460. + bfd_boolean repeat_pass;
  461. + bfd_boolean direct_data_refs;
  462. + unsigned int relax_iteration;
  463. + unsigned int relax_pass;
  464. +};
  465. +#define avr32_elf_hash_table(p) \
  466. + ((struct elf_avr32_link_hash_table *)((p)->hash))
  467. +
  468. +static struct bfd_hash_entry *
  469. +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
  470. + struct bfd_hash_table *table,
  471. + const char *string)
  472. +{
  473. + struct elf_avr32_link_hash_entry *ret = avr32_elf_hash_entry(entry);
  474. +
  475. + /* Allocate the structure if it hasn't already been allocated by a
  476. + subclass */
  477. + if (ret == NULL)
  478. + ret = (struct elf_avr32_link_hash_entry *)
  479. + bfd_hash_allocate(table, sizeof(struct elf_avr32_link_hash_entry));
  480. +
  481. + if (ret == NULL)
  482. + return NULL;
  483. +
  484. + memset(ret, 0, sizeof(struct elf_avr32_link_hash_entry));
  485. +
  486. + /* Give the superclass a chance */
  487. + ret = (struct elf_avr32_link_hash_entry *)
  488. + _bfd_elf_link_hash_newfunc((struct bfd_hash_entry *)ret, table, string);
  489. +
  490. + return (struct bfd_hash_entry *)ret;
  491. +}
  492. +
  493. +/* Copy data from an indirect symbol to its direct symbol, hiding the
  494. + old indirect symbol. Process additional relocation information.
  495. + Also called for weakdefs, in which case we just let
  496. + _bfd_elf_link_hash_copy_indirect copy the flags for us. */
  497. +
  498. +static void
  499. +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
  500. + struct elf_link_hash_entry *dir,
  501. + struct elf_link_hash_entry *ind)
  502. +{
  503. + struct elf_avr32_link_hash_entry *edir, *eind;
  504. +
  505. + _bfd_elf_link_hash_copy_indirect (info, dir, ind);
  506. +
  507. + if (ind->root.type != bfd_link_hash_indirect)
  508. + return;
  509. +
  510. + edir = (struct elf_avr32_link_hash_entry *)dir;
  511. + eind = (struct elf_avr32_link_hash_entry *)ind;
  512. +
  513. + edir->possibly_dynamic_relocs += eind->possibly_dynamic_relocs;
  514. + edir->no_fn_stub = edir->no_fn_stub || eind->no_fn_stub;
  515. +}
  516. +
  517. +static struct bfd_link_hash_table *
  518. +avr32_elf_link_hash_table_create(bfd *abfd)
  519. +{
  520. + struct elf_avr32_link_hash_table *ret;
  521. +
  522. + ret = bfd_zmalloc(sizeof(*ret));
  523. + if (ret == NULL)
  524. + return NULL;
  525. +
  526. + if (! _bfd_elf_link_hash_table_init(&ret->root, abfd,
  527. + avr32_elf_link_hash_newfunc,
  528. + sizeof (struct elf_avr32_link_hash_entry)))
  529. + {
  530. + free(ret);
  531. + return NULL;
  532. + }
  533. +
  534. + /* Prevent the BFD core from creating bogus got_entry pointers */
  535. + ret->root.init_got_refcount.glist = NULL;
  536. + ret->root.init_plt_refcount.glist = NULL;
  537. + ret->root.init_got_offset.glist = NULL;
  538. + ret->root.init_plt_offset.glist = NULL;
  539. +
  540. + return &ret->root.root;
  541. +}
  542. +
  543. +
  544. +/* Initial analysis and creation of dynamic sections and symbols */
  545. +
  546. +static asection *
  547. +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
  548. + unsigned int align_power);
  549. +static struct elf_link_hash_entry *
  550. +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
  551. + const char *name, asection *sec,
  552. + bfd_vma offset);
  553. +static bfd_boolean
  554. +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info);
  555. +static bfd_boolean
  556. +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info);
  557. +static bfd_boolean
  558. +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
  559. + const Elf_Internal_Rela *relocs);
  560. +static bfd_boolean
  561. +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
  562. + struct elf_link_hash_entry *h);
  563. +
  564. +static asection *
  565. +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
  566. + unsigned int align_power)
  567. +{
  568. + asection *sec;
  569. +
  570. + sec = bfd_make_section(dynobj, name);
  571. + if (!sec
  572. + || !bfd_set_section_flags(dynobj, sec, flags)
  573. + || !bfd_set_section_alignment(dynobj, sec, align_power))
  574. + return NULL;
  575. +
  576. + return sec;
  577. +}
  578. +
  579. +static struct elf_link_hash_entry *
  580. +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
  581. + const char *name, asection *sec,
  582. + bfd_vma offset)
  583. +{
  584. + struct bfd_link_hash_entry *bh = NULL;
  585. + struct elf_link_hash_entry *h;
  586. + const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
  587. +
  588. + if (!(_bfd_generic_link_add_one_symbol
  589. + (info, dynobj, name, BSF_GLOBAL, sec, offset, NULL, FALSE,
  590. + bed->collect, &bh)))
  591. + return NULL;
  592. +
  593. + h = (struct elf_link_hash_entry *)bh;
  594. + h->def_regular = 1;
  595. + h->type = STT_OBJECT;
  596. + h->other = STV_HIDDEN;
  597. +
  598. + return h;
  599. +}
  600. +
  601. +static bfd_boolean
  602. +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info)
  603. +{
  604. + struct elf_avr32_link_hash_table *htab;
  605. + flagword flags;
  606. + const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
  607. +
  608. + htab = avr32_elf_hash_table(info);
  609. + flags = bed->dynamic_sec_flags;
  610. +
  611. + if (htab->sgot)
  612. + return TRUE;
  613. +
  614. + htab->sgot = create_dynamic_section(dynobj, ".got", flags, 2);
  615. + if (!htab->srelgot)
  616. + htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
  617. + flags | SEC_READONLY, 2);
  618. +
  619. + if (!htab->sgot || !htab->srelgot)
  620. + return FALSE;
  621. +
  622. + htab->root.hgot = create_dynamic_symbol(dynobj, info, "_GLOBAL_OFFSET_TABLE_",
  623. + htab->sgot, 0);
  624. + if (!htab->root.hgot)
  625. + return FALSE;
  626. +
  627. + /* Make room for the GOT header */
  628. + htab->sgot->size += bed->got_header_size;
  629. +
  630. + return TRUE;
  631. +}
  632. +
  633. +/* (1) Create all dynamic (i.e. linker generated) sections that we may
  634. + need during the link */
  635. +
  636. +static bfd_boolean
  637. +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
  638. +{
  639. + struct elf_avr32_link_hash_table *htab;
  640. + flagword flags;
  641. + const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
  642. +
  643. + pr_debug("(1) create dynamic sections\n");
  644. +
  645. + htab = avr32_elf_hash_table(info);
  646. + flags = bed->dynamic_sec_flags;
  647. +
  648. + if (!avr32_elf_create_got_section (dynobj, info))
  649. + return FALSE;
  650. +
  651. + if (!htab->sstub)
  652. + htab->sstub = create_dynamic_section(dynobj, ".stub",
  653. + flags | SEC_READONLY | SEC_CODE, 2);
  654. +
  655. + if (!htab->sstub)
  656. + return FALSE;
  657. +
  658. + return TRUE;
  659. +}
  660. +
  661. +/* (2) Go through all the relocs and count any potential GOT- or
  662. + PLT-references to each symbol */
  663. +
  664. +static bfd_boolean
  665. +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
  666. + const Elf_Internal_Rela *relocs)
  667. +{
  668. + Elf_Internal_Shdr *symtab_hdr;
  669. + struct elf_avr32_link_hash_table *htab;
  670. + struct elf_link_hash_entry **sym_hashes;
  671. + const Elf_Internal_Rela *rel, *rel_end;
  672. + struct got_entry **local_got_ents;
  673. + struct got_entry *got;
  674. + const struct elf_backend_data *bed = get_elf_backend_data (abfd);
  675. + asection *sgot;
  676. + bfd *dynobj;
  677. +
  678. + pr_debug("(2) check relocs for %s:<%s> (size 0x%lx)\n",
  679. + abfd->filename, sec->name, sec->size);
  680. +
  681. + if (info->relocatable)
  682. + return TRUE;
  683. +
  684. + dynobj = elf_hash_table(info)->dynobj;
  685. + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
  686. + sym_hashes = elf_sym_hashes(abfd);
  687. + htab = avr32_elf_hash_table(info);
  688. + local_got_ents = elf_local_got_ents(abfd);
  689. + sgot = htab->sgot;
  690. +
  691. + rel_end = relocs + sec->reloc_count;
  692. + for (rel = relocs; rel < rel_end; rel++)
  693. + {
  694. + unsigned long r_symndx, r_type;
  695. + struct elf_avr32_link_hash_entry *h;
  696. +
  697. + r_symndx = ELF32_R_SYM(rel->r_info);
  698. + r_type = ELF32_R_TYPE(rel->r_info);
  699. +
  700. + /* Local symbols use local_got_ents, while others store the same
  701. + information in the hash entry */
  702. + if (r_symndx < symtab_hdr->sh_info)
  703. + {
  704. + pr_debug(" (2a) processing local symbol %lu\n", r_symndx);
  705. + h = NULL;
  706. + }
  707. + else
  708. + {
  709. + h = (struct elf_avr32_link_hash_entry *)
  710. + sym_hashes[r_symndx - symtab_hdr->sh_info];
  711. + while (h->root.type == bfd_link_hash_indirect
  712. + || h->root.type == bfd_link_hash_warning)
  713. + h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
  714. + pr_debug(" (2a) processing symbol %s\n", h->root.root.root.string);
  715. + }
  716. +
  717. + /* Some relocs require special sections to be created. */
  718. + switch (r_type)
  719. + {
  720. + case R_AVR32_GOT32:
  721. + case R_AVR32_GOT16:
  722. + case R_AVR32_GOT8:
  723. + case R_AVR32_GOT21S:
  724. + case R_AVR32_GOT18SW:
  725. + case R_AVR32_GOT16S:
  726. + case R_AVR32_GOT7UW:
  727. + case R_AVR32_LDA_GOT:
  728. + case R_AVR32_GOTCALL:
  729. + if (rel->r_addend)
  730. + {
  731. + if (info->callbacks->reloc_dangerous
  732. + (info, _("Non-zero addend on GOT-relative relocation"),
  733. + abfd, sec, rel->r_offset) == FALSE)
  734. + return FALSE;
  735. + }
  736. + /* fall through */
  737. + case R_AVR32_GOTPC:
  738. + if (dynobj == NULL)
  739. + elf_hash_table(info)->dynobj = dynobj = abfd;
  740. + if (sgot == NULL && !avr32_elf_create_got_section(dynobj, info))
  741. + return FALSE;
  742. + break;
  743. + case R_AVR32_32:
  744. + /* We may need to create .rela.dyn later on. */
  745. + if (dynobj == NULL
  746. + && (info->shared || h != NULL)
  747. + && (sec->flags & SEC_ALLOC))
  748. + elf_hash_table(info)->dynobj = dynobj = abfd;
  749. + break;
  750. + }
  751. +
  752. + if (h != NULL && r_type != R_AVR32_GOT18SW)
  753. + h->no_fn_stub = TRUE;
  754. +
  755. + switch (r_type)
  756. + {
  757. + case R_AVR32_GOT32:
  758. + case R_AVR32_GOT16:
  759. + case R_AVR32_GOT8:
  760. + case R_AVR32_GOT21S:
  761. + case R_AVR32_GOT18SW:
  762. + case R_AVR32_GOT16S:
  763. + case R_AVR32_GOT7UW:
  764. + case R_AVR32_LDA_GOT:
  765. + case R_AVR32_GOTCALL:
  766. + if (h != NULL)
  767. + {
  768. + got = h->root.got.glist;
  769. + if (!got)
  770. + {
  771. + got = bfd_zalloc(abfd, sizeof(struct got_entry));
  772. + if (!got)
  773. + return FALSE;
  774. + h->root.got.glist = got;
  775. + }
  776. + }
  777. + else
  778. + {
  779. + if (!local_got_ents)
  780. + {
  781. + bfd_size_type size;
  782. + bfd_size_type i;
  783. + struct got_entry *tmp_entry;
  784. +
  785. + size = symtab_hdr->sh_info;
  786. + size *= sizeof(struct got_entry *) + sizeof(struct got_entry);
  787. + local_got_ents = bfd_zalloc(abfd, size);
  788. + if (!local_got_ents)
  789. + return FALSE;
  790. +
  791. + elf_local_got_ents(abfd) = local_got_ents;
  792. +
  793. + tmp_entry = (struct got_entry *)(local_got_ents
  794. + + symtab_hdr->sh_info);
  795. + for (i = 0; i < symtab_hdr->sh_info; i++)
  796. + local_got_ents[i] = &tmp_entry[i];
  797. + }
  798. +
  799. + got = local_got_ents[r_symndx];
  800. + }
  801. +
  802. + got->refcount++;
  803. + if (got->refcount > htab->nr_got_holes)
  804. + htab->nr_got_holes = got->refcount;
  805. + break;
  806. +
  807. + case R_AVR32_32:
  808. + if ((info->shared || h != NULL)
  809. + && (sec->flags & SEC_ALLOC))
  810. + {
  811. + if (htab->srelgot == NULL)
  812. + {
  813. + htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
  814. + bed->dynamic_sec_flags
  815. + | SEC_READONLY, 2);
  816. + if (htab->srelgot == NULL)
  817. + return FALSE;
  818. + }
  819. +
  820. + if (sec->flags & SEC_READONLY
  821. + && !h->readonly_reloc_sec)
  822. + {
  823. + h->readonly_reloc_sec = sec;
  824. + h->readonly_reloc_offset = rel->r_offset;
  825. + }
  826. +
  827. + if (h != NULL)
  828. + {
  829. + pr_debug("Non-GOT reference to symbol %s\n",
  830. + h->root.root.root.string);
  831. + h->possibly_dynamic_relocs++;
  832. + }
  833. + else
  834. + {
  835. + pr_debug("Non-GOT reference to local symbol %lu\n",
  836. + r_symndx);
  837. + htab->local_dynamic_relocs++;
  838. + }
  839. + }
  840. +
  841. + break;
  842. +
  843. + /* TODO: GNU_VTINHERIT and GNU_VTENTRY */
  844. + }
  845. + }
  846. +
  847. + return TRUE;
  848. +}
  849. +
  850. +/* (3) Adjust a symbol defined by a dynamic object and referenced by a
  851. + regular object. The current definition is in some section of the
  852. + dynamic object, but we're not including those sections. We have to
  853. + change the definition to something the rest of the link can
  854. + understand. */
  855. +
  856. +static bfd_boolean
  857. +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
  858. + struct elf_link_hash_entry *h)
  859. +{
  860. + struct elf_avr32_link_hash_table *htab;
  861. + struct elf_avr32_link_hash_entry *havr;
  862. + bfd *dynobj;
  863. +
  864. + pr_debug("(3) adjust dynamic symbol %s\n", h->root.root.string);
  865. +
  866. + htab = avr32_elf_hash_table(info);
  867. + havr = (struct elf_avr32_link_hash_entry *)h;
  868. + dynobj = elf_hash_table(info)->dynobj;
  869. +
  870. + /* Make sure we know what is going on here. */
  871. + BFD_ASSERT (dynobj != NULL
  872. + && (h->u.weakdef != NULL
  873. + || (h->def_dynamic
  874. + && h->ref_regular
  875. + && !h->def_regular)));
  876. +
  877. + /* We don't want dynamic relocations in read-only sections. */
  878. + if (havr->readonly_reloc_sec)
  879. + {
  880. + if (info->callbacks->reloc_dangerous
  881. + (info, _("dynamic relocation in read-only section"),
  882. + havr->readonly_reloc_sec->owner, havr->readonly_reloc_sec,
  883. + havr->readonly_reloc_offset) == FALSE)
  884. + return FALSE;
  885. + }
  886. +
  887. + /* If this is a function, create a stub if possible and set the
  888. + symbol to the stub location. */
  889. + if (0 && !havr->no_fn_stub)
  890. + {
  891. + if (!h->def_regular)
  892. + {
  893. + asection *s = htab->sstub;
  894. +
  895. + BFD_ASSERT(s != NULL);
  896. +
  897. + h->root.u.def.section = s;
  898. + h->root.u.def.value = s->size;
  899. + h->plt.offset = s->size;
  900. + s->size += AVR32_FUNCTION_STUB_SIZE;
  901. +
  902. + return TRUE;
  903. + }
  904. + }
  905. + else if (h->type == STT_FUNC)
  906. + {
  907. + /* This will set the entry for this symbol in the GOT to 0, and
  908. + the dynamic linker will take care of this. */
  909. + h->root.u.def.value = 0;
  910. + return TRUE;
  911. + }
  912. +
  913. + /* If this is a weak symbol, and there is a real definition, the
  914. + processor independent code will have arranged for us to see the
  915. + real definition first, and we can just use the same value. */
  916. + if (h->u.weakdef != NULL)
  917. + {
  918. + BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined
  919. + || h->u.weakdef->root.type == bfd_link_hash_defweak);
  920. + h->root.u.def.section = h->u.weakdef->root.u.def.section;
  921. + h->root.u.def.value = h->u.weakdef->root.u.def.value;
  922. + return TRUE;
  923. + }
  924. +
  925. + /* This is a reference to a symbol defined by a dynamic object which
  926. + is not a function. */
  927. +
  928. + return TRUE;
  929. +}
  930. +
  931. +
  932. +/* Garbage-collection of unused sections */
  933. +
  934. +static asection *
  935. +avr32_elf_gc_mark_hook(asection *sec,
  936. + struct bfd_link_info *info ATTRIBUTE_UNUSED,
  937. + Elf_Internal_Rela *rel,
  938. + struct elf_link_hash_entry *h,
  939. + Elf_Internal_Sym *sym)
  940. +{
  941. + if (h)
  942. + {
  943. + switch (ELF32_R_TYPE(rel->r_info))
  944. + {
  945. + /* TODO: VTINHERIT/VTENTRY */
  946. + default:
  947. + switch (h->root.type)
  948. + {
  949. + case bfd_link_hash_defined:
  950. + case bfd_link_hash_defweak:
  951. + return h->root.u.def.section;
  952. +
  953. + case bfd_link_hash_common:
  954. + return h->root.u.c.p->section;
  955. +
  956. + default:
  957. + break;
  958. + }
  959. + }
  960. + }
  961. + else
  962. + return bfd_section_from_elf_index(sec->owner, sym->st_shndx);
  963. +
  964. + return NULL;
  965. +}
  966. +
  967. +/* Update the GOT entry reference counts for the section being removed. */
  968. +static bfd_boolean
  969. +avr32_elf_gc_sweep_hook(bfd *abfd,
  970. + struct bfd_link_info *info ATTRIBUTE_UNUSED,
  971. + asection *sec,
  972. + const Elf_Internal_Rela *relocs)
  973. +{
  974. + Elf_Internal_Shdr *symtab_hdr;
  975. + struct elf_avr32_link_hash_entry **sym_hashes;
  976. + struct got_entry **local_got_ents;
  977. + const Elf_Internal_Rela *rel, *relend;
  978. +
  979. + if (!(sec->flags & SEC_ALLOC))
  980. + return TRUE;
  981. +
  982. + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
  983. + sym_hashes = (struct elf_avr32_link_hash_entry **)elf_sym_hashes(abfd);
  984. + local_got_ents = elf_local_got_ents(abfd);
  985. +
  986. + relend = relocs + sec->reloc_count;
  987. + for (rel = relocs; rel < relend; rel++)
  988. + {
  989. + unsigned long r_symndx;
  990. + unsigned int r_type;
  991. + struct elf_avr32_link_hash_entry *h = NULL;
  992. +
  993. + r_symndx = ELF32_R_SYM(rel->r_info);
  994. + if (r_symndx >= symtab_hdr->sh_info)
  995. + {
  996. + h = sym_hashes[r_symndx - symtab_hdr->sh_info];
  997. + while (h->root.root.type == bfd_link_hash_indirect
  998. + || h->root.root.type == bfd_link_hash_warning)
  999. + h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
  1000. + }
  1001. +
  1002. + r_type = ELF32_R_TYPE(rel->r_info);
  1003. +
  1004. + switch (r_type)
  1005. + {
  1006. + case R_AVR32_GOT32:
  1007. + case R_AVR32_GOT16:
  1008. + case R_AVR32_GOT8:
  1009. + case R_AVR32_GOT21S:
  1010. + case R_AVR32_GOT18SW:
  1011. + case R_AVR32_GOT16S:
  1012. + case R_AVR32_GOT7UW:
  1013. + case R_AVR32_LDA_GOT:
  1014. + case R_AVR32_GOTCALL:
  1015. + if (h)
  1016. + h->root.got.glist->refcount--;
  1017. + else
  1018. + local_got_ents[r_symndx]->refcount--;
  1019. + break;
  1020. +
  1021. + case R_AVR32_32:
  1022. + if (info->shared || h)
  1023. + {
  1024. + if (h)
  1025. + h->possibly_dynamic_relocs--;
  1026. + else
  1027. + avr32_elf_hash_table(info)->local_dynamic_relocs--;
  1028. + }
  1029. +
  1030. + default:
  1031. + break;
  1032. + }
  1033. + }
  1034. +
  1035. + return TRUE;
  1036. +}
  1037. +
  1038. +/* Sizing and refcounting of dynamic sections */
  1039. +
  1040. +static void
  1041. +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
  1042. +static void
  1043. +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
  1044. +static void
  1045. +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
  1046. +static bfd_boolean
  1047. +assign_got_offsets(struct elf_avr32_link_hash_table *htab);
  1048. +static bfd_boolean
  1049. +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info);
  1050. +static bfd_boolean
  1051. +avr32_elf_size_dynamic_sections (bfd *output_bfd,
  1052. + struct bfd_link_info *info);
  1053. +
  1054. +static void
  1055. +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
  1056. +{
  1057. + /* Any entries with got_refcount > htab->nr_got_holes end up in the
  1058. + * last pigeonhole without any sorting. We expect the number of such
  1059. + * entries to be small, so it is very unlikely to affect
  1060. + * performance. */
  1061. + int entry = got->refcount;
  1062. +
  1063. + if (entry > htab->nr_got_holes)
  1064. + entry = htab->nr_got_holes;
  1065. +
  1066. + got->pprev = &htab->got_hole[entry];
  1067. + got->next = htab->got_hole[entry];
  1068. +
  1069. + if (got->next)
  1070. + got->next->pprev = &got->next;
  1071. +
  1072. + htab->got_hole[entry] = got;
  1073. +}
  1074. +
  1075. +/* Decrement the refcount of a GOT entry and update its position in
  1076. + the pigeonhole array. */
  1077. +static void
  1078. +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
  1079. +{
  1080. + BFD_ASSERT(got->refcount > 0);
  1081. +
  1082. + if (got->next)
  1083. + got->next->pprev = got->pprev;
  1084. +
  1085. + *(got->pprev) = got->next;
  1086. + got->refcount--;
  1087. + insert_got_entry(htab, got);
  1088. +}
  1089. +
  1090. +static void
  1091. +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
  1092. +{
  1093. + if (got->next)
  1094. + got->next->pprev = got->pprev;
  1095. +
  1096. + *(got->pprev) = got->next;
  1097. + got->refcount++;
  1098. + insert_got_entry(htab, got);
  1099. +
  1100. + BFD_ASSERT(got->refcount > 0);
  1101. +}
  1102. +
  1103. +/* Assign offsets to all GOT entries we intend to keep. The entries
  1104. + that are referenced most often are placed at low offsets so that we
  1105. + can use compact instructions as much as possible.
  1106. +
  1107. + Returns TRUE if any offsets or the total size of the GOT changed. */
  1108. +
  1109. +static bfd_boolean
  1110. +assign_got_offsets(struct elf_avr32_link_hash_table *htab)
  1111. +{
  1112. + struct got_entry *got;
  1113. + bfd_size_type got_size = 0;
  1114. + bfd_boolean changed = FALSE;
  1115. + bfd_signed_vma offset;
  1116. + int i;
  1117. +
  1118. + /* The GOT header provides the address of the DYNAMIC segment, so
  1119. + we need that even if the GOT is otherwise empty. */
  1120. + if (htab->root.dynamic_sections_created)
  1121. + got_size = AVR32_GOT_HEADER_SIZE;
  1122. +
  1123. + for (i = htab->nr_got_holes; i > 0; i--)
  1124. + {
  1125. + got = htab->got_hole[i];
  1126. + while (got)
  1127. + {
  1128. + if (got->refcount > 0)
  1129. + {
  1130. + offset = got_size;
  1131. + if (got->offset != offset)
  1132. + {
  1133. + RDBG("GOT offset changed: %ld -> %ld\n",
  1134. + got->offset, offset);
  1135. + changed = TRUE;
  1136. + }
  1137. + got->offset = offset;
  1138. + got_size += 4;
  1139. + }
  1140. + got = got->next;
  1141. + }
  1142. + }
  1143. +
  1144. + if (htab->sgot->size != got_size)
  1145. + {
  1146. + RDBG("GOT size changed: %lu -> %lu\n", htab->sgot->size,
  1147. + got_size);
  1148. + changed = TRUE;
  1149. + }
  1150. + htab->sgot->size = got_size;
  1151. +
  1152. + RDBG("assign_got_offsets: total size %lu (%s)\n",
  1153. + got_size, changed ? "changed" : "no change");
  1154. +
  1155. + return changed;
  1156. +}
  1157. +
  1158. +static bfd_boolean
  1159. +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info)
  1160. +{
  1161. + struct bfd_link_info *info = _info;
  1162. + struct elf_avr32_link_hash_table *htab;
  1163. + struct elf_avr32_link_hash_entry *havr;
  1164. + struct got_entry *got;
  1165. +
  1166. + pr_debug(" (4b) allocate_dynrelocs: %s\n", h->root.root.string);
  1167. +
  1168. + if (h->root.type == bfd_link_hash_indirect)
  1169. + return TRUE;
  1170. +
  1171. + if (h->root.type == bfd_link_hash_warning)
  1172. + /* When warning symbols are created, they **replace** the "real"
  1173. + entry in the hash table, thus we never get to see the real
  1174. + symbol in a hash traversal. So look at it now. */
  1175. + h = (struct elf_link_hash_entry *) h->root.u.i.link;
  1176. +
  1177. + htab = avr32_elf_hash_table(info);
  1178. + havr = (struct elf_avr32_link_hash_entry *)h;
  1179. +
  1180. + got = h->got.glist;
  1181. +
  1182. + /* If got is NULL, the symbol is never referenced through the GOT */
  1183. + if (got && got->refcount > 0)
  1184. + {
  1185. + insert_got_entry(htab, got);
  1186. +
  1187. + /* Shared libraries need relocs for all GOT entries unless the
  1188. + symbol is forced local or -Bsymbolic is used. Others need
  1189. + relocs for everything that is not guaranteed to be defined in
  1190. + a regular object. */
  1191. + if ((info->shared
  1192. + && !info->symbolic
  1193. + && h->dynindx != -1)
  1194. + || (htab->root.dynamic_sections_created
  1195. + && h->def_dynamic
  1196. + && !h->def_regular))
  1197. + htab->srelgot->size += sizeof(Elf32_External_Rela);
  1198. + }
  1199. +
  1200. + if (havr->possibly_dynamic_relocs
  1201. + && (info->shared
  1202. + || (elf_hash_table(info)->dynamic_sections_created
  1203. + && h->def_dynamic
  1204. + && !h->def_regular)))
  1205. + {
  1206. + pr_debug("Allocating %d dynamic reloc against symbol %s...\n",
  1207. + havr->possibly_dynamic_relocs, h->root.root.string);
  1208. + htab->srelgot->size += (havr->possibly_dynamic_relocs
  1209. + * sizeof(Elf32_External_Rela));
  1210. + }
  1211. +
  1212. + return TRUE;
  1213. +}
  1214. +
  1215. +/* (4) Calculate the sizes of the linker-generated sections and
  1216. + allocate memory for them. */
  1217. +
  1218. +static bfd_boolean
  1219. +avr32_elf_size_dynamic_sections (bfd *output_bfd,
  1220. + struct bfd_link_info *info)
  1221. +{
  1222. + struct elf_avr32_link_hash_table *htab;
  1223. + bfd *dynobj;
  1224. + asection *s;
  1225. + bfd *ibfd;
  1226. + bfd_boolean relocs;
  1227. +
  1228. + pr_debug("(4) size dynamic sections\n");
  1229. +
  1230. + htab = avr32_elf_hash_table(info);
  1231. + dynobj = htab->root.dynobj;
  1232. + BFD_ASSERT(dynobj != NULL);
  1233. +
  1234. + if (htab->root.dynamic_sections_created)
  1235. + {
  1236. + /* Initialize the contents of the .interp section to the name of
  1237. + the dynamic loader */
  1238. + if (info->executable)
  1239. + {
  1240. + s = bfd_get_section_by_name(dynobj, ".interp");
  1241. + BFD_ASSERT(s != NULL);
  1242. + s->size = sizeof(ELF_DYNAMIC_INTERPRETER);
  1243. + s->contents = (unsigned char *)ELF_DYNAMIC_INTERPRETER;
  1244. + }
  1245. + }
  1246. +
  1247. + if (htab->nr_got_holes > 0)
  1248. + {
  1249. + /* Allocate holes for the pigeonhole sort algorithm */
  1250. + pr_debug("Highest GOT refcount: %d\n", htab->nr_got_holes);
  1251. +
  1252. + /* Limit the memory usage by clipping the number of pigeonholes
  1253. + * at a predefined maximum. All entries with a higher refcount
  1254. + * will end up in the last pigeonhole. */
  1255. + if (htab->nr_got_holes >= MAX_NR_GOT_HOLES)
  1256. + {
  1257. + htab->nr_got_holes = MAX_NR_GOT_HOLES - 1;
  1258. +
  1259. + pr_debug("Limiting maximum number of GOT pigeonholes to %u\n",
  1260. + htab->nr_got_holes);
  1261. + }
  1262. + htab->got_hole = bfd_zalloc(output_bfd,
  1263. + sizeof(struct got_entry *)
  1264. + * (htab->nr_got_holes + 1));
  1265. + if (!htab->got_hole)
  1266. + return FALSE;
  1267. +
  1268. + /* Set up .got offsets for local syms. */
  1269. + for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
  1270. + {
  1271. + struct got_entry **local_got;
  1272. + struct got_entry **end_local_got;
  1273. + Elf_Internal_Shdr *symtab_hdr;
  1274. + bfd_size_type locsymcount;
  1275. +
  1276. + pr_debug(" (4a) processing file %s...\n", ibfd->filename);
  1277. +
  1278. + BFD_ASSERT(bfd_get_flavour(ibfd) == bfd_target_elf_flavour);
  1279. +
  1280. + local_got = elf_local_got_ents(ibfd);
  1281. + if (!local_got)
  1282. + continue;
  1283. +
  1284. + symtab_hdr = &elf_tdata(ibfd)->symtab_hdr;
  1285. + locsymcount = symtab_hdr->sh_info;
  1286. + end_local_got = local_got + locsymcount;
  1287. +
  1288. + for (; local_got < end_local_got; ++local_got)
  1289. + insert_got_entry(htab, *local_got);
  1290. + }
  1291. + }
  1292. +
  1293. + /* Allocate global sym .got entries and space for global sym
  1294. + dynamic relocs */
  1295. + elf_link_hash_traverse(&htab->root, allocate_dynrelocs, info);
  1296. +
  1297. + /* Now that we have sorted the GOT entries, we are ready to
  1298. + assign offsets and determine the initial size of the GOT. */
  1299. + if (htab->sgot)
  1300. + assign_got_offsets(htab);
  1301. +
  1302. + /* Allocate space for local sym dynamic relocs */
  1303. + BFD_ASSERT(htab->local_dynamic_relocs == 0 || info->shared);
  1304. + if (htab->local_dynamic_relocs)
  1305. + htab->srelgot->size += (htab->local_dynamic_relocs
  1306. + * sizeof(Elf32_External_Rela));
  1307. +
  1308. + /* We now have determined the sizes of the various dynamic
  1309. + sections. Allocate memory for them. */
  1310. + relocs = FALSE;
  1311. + for (s = dynobj->sections; s; s = s->next)
  1312. + {
  1313. + if ((s->flags & SEC_LINKER_CREATED) == 0)
  1314. + continue;
  1315. +
  1316. + if (s == htab->sgot
  1317. + || s == htab->sstub)
  1318. + {
  1319. + /* Strip this section if we don't need it */
  1320. + }
  1321. + else if (strncmp (bfd_get_section_name(dynobj, s), ".rela", 5) == 0)
  1322. + {
  1323. + if (s->size != 0)
  1324. + relocs = TRUE;
  1325. +
  1326. + s->reloc_count = 0;
  1327. + }
  1328. + else
  1329. + {
  1330. + /* It's not one of our sections */
  1331. + continue;
  1332. + }
  1333. +
  1334. + if (s->size == 0)
  1335. + {
  1336. + /* Strip unneeded sections */
  1337. + pr_debug("Stripping section %s from output...\n", s->name);
  1338. + /* deleted function in 2.17
  1339. + _bfd_strip_section_from_output(info, s);
  1340. + */
  1341. + continue;
  1342. + }
  1343. +
  1344. + s->contents = bfd_zalloc(dynobj, s->size);
  1345. + if (s->contents == NULL)
  1346. + return FALSE;
  1347. + }
  1348. +
  1349. + if (htab->root.dynamic_sections_created)
  1350. + {
  1351. + /* Add some entries to the .dynamic section. We fill in the
  1352. + values later, in sh_elf_finish_dynamic_sections, but we
  1353. + must add the entries now so that we get the correct size for
  1354. + the .dynamic section. The DT_DEBUG entry is filled in by the
  1355. + dynamic linker and used by the debugger. */
  1356. +#define add_dynamic_entry(TAG, VAL) _bfd_elf_add_dynamic_entry(info, TAG, VAL)
  1357. +
  1358. + if (!add_dynamic_entry(DT_PLTGOT, 0))
  1359. + return FALSE;
  1360. + if (!add_dynamic_entry(DT_AVR32_GOTSZ, 0))
  1361. + return FALSE;
  1362. +
  1363. + if (info->executable)
  1364. + {
  1365. + if (!add_dynamic_entry(DT_DEBUG, 0))
  1366. + return FALSE;
  1367. + }
  1368. + if (relocs)
  1369. + {
  1370. + if (!add_dynamic_entry(DT_RELA, 0)
  1371. + || !add_dynamic_entry(DT_RELASZ, 0)
  1372. + || !add_dynamic_entry(DT_RELAENT,
  1373. + sizeof(Elf32_External_Rela)))
  1374. + return FALSE;
  1375. + }
  1376. + }
  1377. +#undef add_dynamic_entry
  1378. +
  1379. + return TRUE;
  1380. +}
  1381. +
  1382. +
  1383. +/* Access to internal relocations, section contents and symbols.
  1384. + (stolen from the xtensa port) */
  1385. +
  1386. +static Elf_Internal_Rela *
  1387. +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory);
  1388. +static void
  1389. +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
  1390. +static void
  1391. +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
  1392. +static bfd_byte *
  1393. +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory);
  1394. +/*
  1395. +static void
  1396. +pin_contents (asection *sec, bfd_byte *contents);
  1397. +*/
  1398. +static void
  1399. +release_contents (asection *sec, bfd_byte *contents);
  1400. +static Elf_Internal_Sym *
  1401. +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory);
  1402. +/*
  1403. +static void
  1404. +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
  1405. +*/
  1406. +static void
  1407. +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
  1408. +
  1409. +/* During relaxation, we need to modify relocations, section contents,
  1410. + and symbol definitions, and we need to keep the original values from
  1411. + being reloaded from the input files, i.e., we need to "pin" the
  1412. + modified values in memory. We also want to continue to observe the
  1413. + setting of the "keep-memory" flag. The following functions wrap the
  1414. + standard BFD functions to take care of this for us. */
  1415. +
  1416. +static Elf_Internal_Rela *
  1417. +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory)
  1418. +{
  1419. + /* _bfd_elf_link_read_relocs knows about caching, so no need for us
  1420. + to be clever here. */
  1421. + return _bfd_elf_link_read_relocs(abfd, sec, NULL, NULL, keep_memory);
  1422. +}
  1423. +
  1424. +static void
  1425. +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
  1426. +{
  1427. + elf_section_data (sec)->relocs = internal_relocs;
  1428. +}
  1429. +
  1430. +static void
  1431. +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
  1432. +{
  1433. + if (internal_relocs
  1434. + && elf_section_data (sec)->relocs != internal_relocs)
  1435. + free (internal_relocs);
  1436. +}
  1437. +
  1438. +static bfd_byte *
  1439. +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory)
  1440. +{
  1441. + bfd_byte *contents;
  1442. + bfd_size_type sec_size;
  1443. +
  1444. + sec_size = bfd_get_section_limit (abfd, sec);
  1445. + contents = elf_section_data (sec)->this_hdr.contents;
  1446. +
  1447. + if (contents == NULL && sec_size != 0)
  1448. + {
  1449. + if (!bfd_malloc_and_get_section (abfd, sec, &contents))
  1450. + {
  1451. + if (contents)
  1452. + free (contents);
  1453. + return NULL;
  1454. + }
  1455. + if (keep_memory)
  1456. + elf_section_data (sec)->this_hdr.contents = contents;
  1457. + }
  1458. + return contents;
  1459. +}
  1460. +
  1461. +/*
  1462. +static void
  1463. +pin_contents (asection *sec, bfd_byte *contents)
  1464. +{
  1465. + elf_section_data (sec)->this_hdr.contents = contents;
  1466. +}
  1467. +*/
  1468. +static void
  1469. +release_contents (asection *sec, bfd_byte *contents)
  1470. +{
  1471. + if (contents && elf_section_data (sec)->this_hdr.contents != contents)
  1472. + free (contents);
  1473. +}
  1474. +
  1475. +static Elf_Internal_Sym *
  1476. +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory)
  1477. +{
  1478. + Elf_Internal_Shdr *symtab_hdr;
  1479. + Elf_Internal_Sym *isymbuf;
  1480. + size_t locsymcount;
  1481. +
  1482. + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
  1483. + locsymcount = symtab_hdr->sh_info;
  1484. +
  1485. + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
  1486. + if (isymbuf == NULL && locsymcount != 0)
  1487. + {
  1488. + isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0,
  1489. + NULL, NULL, NULL);
  1490. + if (isymbuf && keep_memory)
  1491. + symtab_hdr->contents = (unsigned char *) isymbuf;
  1492. + }
  1493. +
  1494. + return isymbuf;
  1495. +}
  1496. +
  1497. +/*
  1498. +static void
  1499. +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
  1500. +{
  1501. + elf_tdata (input_bfd)->symtab_hdr.contents = (unsigned char *)isymbuf;
  1502. +}
  1503. +
  1504. +*/
  1505. +static void
  1506. +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
  1507. +{
  1508. + if (isymbuf && (elf_tdata (input_bfd)->symtab_hdr.contents
  1509. + != (unsigned char *)isymbuf))
  1510. + free (isymbuf);
  1511. +}
  1512. +
  1513. + /* Data structures used during relaxation. */
  1514. +
  1515. +enum relax_state_id {
  1516. + RS_ERROR = -1,
  1517. + RS_NONE = 0,
  1518. + RS_ALIGN,
  1519. + RS_CPENT,
  1520. + RS_PIC_CALL,
  1521. + RS_PIC_MCALL,
  1522. + RS_PIC_RCALL2,
  1523. + RS_PIC_RCALL1,
  1524. + RS_PIC_LDA,
  1525. + RS_PIC_LDW4,
  1526. + RS_PIC_LDW3,
  1527. + RS_PIC_SUB5,
  1528. + RS_NOPIC_MCALL,
  1529. + RS_NOPIC_RCALL2,
  1530. + RS_NOPIC_RCALL1,
  1531. + RS_NOPIC_LDW4,
  1532. + RS_NOPIC_LDDPC,
  1533. + RS_NOPIC_SUB5,
  1534. + RS_NOPIC_MOV2,
  1535. + RS_NOPIC_MOV1,
  1536. + RS_RCALL2,
  1537. + RS_RCALL1,
  1538. + RS_BRC2,
  1539. + RS_BRC1,
  1540. + RS_BRAL,
  1541. + RS_RJMP,
  1542. + RS_MAX,
  1543. +};
  1544. +
  1545. +enum reference_type {
  1546. + REF_ABSOLUTE,
  1547. + REF_PCREL,
  1548. + REF_CPOOL,
  1549. + REF_GOT,
  1550. +};
  1551. +
  1552. +struct relax_state
  1553. +{
  1554. + const char *name;
  1555. + enum relax_state_id id;
  1556. + enum relax_state_id direct;
  1557. + enum relax_state_id next;
  1558. + enum relax_state_id prev;
  1559. +
  1560. + enum reference_type reftype;
  1561. +
  1562. + unsigned int r_type;
  1563. +
  1564. + bfd_vma opcode;
  1565. + bfd_vma opcode_mask;
  1566. +
  1567. + bfd_signed_vma range_min;
  1568. + bfd_signed_vma range_max;
  1569. +
  1570. + bfd_size_type size;
  1571. +};
  1572. +
  1573. +/*
  1574. + * This is for relocs that
  1575. + * a) has an addend or is of type R_AVR32_DIFF32, and
  1576. + * b) references a different section than it's in, and
  1577. + * c) references a section that is relaxable
  1578. + *
  1579. + * as well as relocs that references the constant pool, in which case
  1580. + * the add_frag member points to the frag containing the constant pool
  1581. + * entry.
  1582. + *
  1583. + * Such relocs must be fixed up whenever we delete any code. Sections
  1584. + * that don't have any relocs with all of the above properties don't
  1585. + * have any additional reloc data, but sections that do will have
  1586. + * additional data for all its relocs.
  1587. + */
  1588. +struct avr32_reloc_data
  1589. +{
  1590. + struct fragment *add_frag;
  1591. + struct fragment *sub_frag;
  1592. +};
  1593. +
  1594. +/*
  1595. + * A 'fragment' is a relaxable entity, that is, code may be added or
  1596. + * deleted at the end of a fragment. When this happens, all subsequent
  1597. + * fragments in the list will have their offsets updated.
  1598. + */
  1599. +struct fragment
  1600. +{
  1601. + enum relax_state_id state;
  1602. + enum relax_state_id initial_state;
  1603. +
  1604. + Elf_Internal_Rela *rela;
  1605. + bfd_size_type size;
  1606. + bfd_vma offset;
  1607. + int size_adjust;
  1608. + int offset_adjust;
  1609. + bfd_boolean has_grown;
  1610. +
  1611. + /* Only used by constant pool entries. When this drops to zero, the
  1612. + frag is discarded (i.e. size_adjust is set to -4.) */
  1613. + int refcount;
  1614. +};
  1615. +
  1616. +struct avr32_relax_data
  1617. +{
  1618. + unsigned int frag_count;
  1619. + struct fragment *frag;
  1620. + struct avr32_reloc_data *reloc_data;
  1621. +
  1622. + /* TRUE if this section has one or more relaxable relocations */
  1623. + bfd_boolean is_relaxable;
  1624. + unsigned int iteration;
  1625. +};
  1626. +
  1627. +struct avr32_section_data
  1628. +{
  1629. + struct bfd_elf_section_data elf;
  1630. + struct avr32_relax_data relax_data;
  1631. +};
  1632. +
  1633. + /* Relax state definitions */
  1634. +
  1635. +#define PIC_MOV2_OPCODE 0xe0600000
  1636. +#define PIC_MOV2_MASK 0xe1e00000
  1637. +#define PIC_MOV2_RANGE_MIN (-1048576 * 4)
  1638. +#define PIC_MOV2_RANGE_MAX (1048575 * 4)
  1639. +#define PIC_MCALL_OPCODE 0xf0160000
  1640. +#define PIC_MCALL_MASK 0xffff0000
  1641. +#define PIC_MCALL_RANGE_MIN (-131072)
  1642. +#define PIC_MCALL_RANGE_MAX (131068)
  1643. +#define RCALL2_OPCODE 0xe0a00000
  1644. +#define RCALL2_MASK 0xe1ef0000
  1645. +#define RCALL2_RANGE_MIN (-2097152)
  1646. +#define RCALL2_RANGE_MAX (2097150)
  1647. +#define RCALL1_OPCODE 0xc00c0000
  1648. +#define RCALL1_MASK 0xf00c0000
  1649. +#define RCALL1_RANGE_MIN (-1024)
  1650. +#define RCALL1_RANGE_MAX (1022)
  1651. +#define PIC_LDW4_OPCODE 0xecf00000
  1652. +#define PIC_LDW4_MASK 0xfff00000
  1653. +#define PIC_LDW4_RANGE_MIN (-32768)
  1654. +#define PIC_LDW4_RANGE_MAX (32767)
  1655. +#define PIC_LDW3_OPCODE 0x6c000000
  1656. +#define PIC_LDW3_MASK 0xfe000000
  1657. +#define PIC_LDW3_RANGE_MIN (0)
  1658. +#define PIC_LDW3_RANGE_MAX (124)
  1659. +#define SUB5_PC_OPCODE 0xfec00000
  1660. +#define SUB5_PC_MASK 0xfff00000
  1661. +#define SUB5_PC_RANGE_MIN (-32768)
  1662. +#define SUB5_PC_RANGE_MAX (32767)
  1663. +#define NOPIC_MCALL_OPCODE 0xf01f0000
  1664. +#define NOPIC_MCALL_MASK 0xffff0000
  1665. +#define NOPIC_MCALL_RANGE_MIN PIC_MCALL_RANGE_MIN
  1666. +#define NOPIC_MCALL_RANGE_MAX PIC_MCALL_RANGE_MAX
  1667. +#define NOPIC_LDW4_OPCODE 0xfef00000
  1668. +#define NOPIC_LDW4_MASK 0xfff00000
  1669. +#define NOPIC_LDW4_RANGE_MIN PIC_LDW4_RANGE_MIN
  1670. +#define NOPIC_LDW4_RANGE_MAX PIC_LDW4_RANGE_MAX
  1671. +#define LDDPC_OPCODE 0x48000000
  1672. +#define LDDPC_MASK 0xf8000000
  1673. +#define LDDPC_RANGE_MIN 0
  1674. +#define LDDPC_RANGE_MAX 508
  1675. +
  1676. +#define NOPIC_MOV2_OPCODE 0xe0600000
  1677. +#define NOPIC_MOV2_MASK 0xe1e00000
  1678. +#define NOPIC_MOV2_RANGE_MIN (-1048576)
  1679. +#define NOPIC_MOV2_RANGE_MAX (1048575)
  1680. +#define NOPIC_MOV1_OPCODE 0x30000000
  1681. +#define NOPIC_MOV1_MASK 0xf0000000
  1682. +#define NOPIC_MOV1_RANGE_MIN (-128)
  1683. +#define NOPIC_MOV1_RANGE_MAX (127)
  1684. +
  1685. +/* Only brc2 variants with cond[3] == 0 is considered, since the
  1686. + others are not relaxable. bral is a special case and is handled
  1687. + separately. */
  1688. +#define BRC2_OPCODE 0xe0800000
  1689. +#define BRC2_MASK 0xe1e80000
  1690. +#define BRC2_RANGE_MIN (-2097152)
  1691. +#define BRC2_RANGE_MAX (2097150)
  1692. +#define BRC1_OPCODE 0xc0000000
  1693. +#define BRC1_MASK 0xf0080000
  1694. +#define BRC1_RANGE_MIN (-256)
  1695. +#define BRC1_RANGE_MAX (254)
  1696. +#define BRAL_OPCODE 0xe08f0000
  1697. +#define BRAL_MASK 0xe1ef0000
  1698. +#define BRAL_RANGE_MIN BRC2_RANGE_MIN
  1699. +#define BRAL_RANGE_MAX BRC2_RANGE_MAX
  1700. +#define RJMP_OPCODE 0xc0080000
  1701. +#define RJMP_MASK 0xf00c0000
  1702. +#define RJMP_RANGE_MIN (-1024)
  1703. +#define RJMP_RANGE_MAX (1022)
  1704. +
  1705. +/* Define a relax state using the GOT */
  1706. +#define RG(id, dir, next, prev, r_type, opc, size) \
  1707. + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_GOT, \
  1708. + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
  1709. + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
  1710. +/* Define a relax state using the Constant Pool */
  1711. +#define RC(id, dir, next, prev, r_type, opc, size) \
  1712. + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_CPOOL, \
  1713. + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
  1714. + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
  1715. +
  1716. +/* Define a relax state using pc-relative direct reference */
  1717. +#define RP(id, dir, next, prev, r_type, opc, size) \
  1718. + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_PCREL, \
  1719. + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
  1720. + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
  1721. +
  1722. +/* Define a relax state using non-pc-relative direct reference */
  1723. +#define RD(id, dir, next, prev, r_type, opc, size) \
  1724. + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_ABSOLUTE, \
  1725. + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
  1726. + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
  1727. +
  1728. +/* Define a relax state that will be handled specially */
  1729. +#define RS(id, r_type, size) \
  1730. + { "RS_"#id, RS_##id, RS_NONE, RS_NONE, RS_NONE, REF_ABSOLUTE, \
  1731. + R_AVR32_##r_type, 0, 0, 0, 0, size }
  1732. +
  1733. +const struct relax_state relax_state[RS_MAX] = {
  1734. + RS(NONE, NONE, 0),
  1735. + RS(ALIGN, ALIGN, 0),
  1736. + RS(CPENT, 32_CPENT, 4),
  1737. +
  1738. + RG(PIC_CALL, PIC_RCALL1, PIC_MCALL, NONE, GOTCALL, PIC_MOV2, 10),
  1739. + RG(PIC_MCALL, PIC_RCALL1, NONE, PIC_CALL, GOT18SW, PIC_MCALL, 4),
  1740. + RP(PIC_RCALL2, NONE, PIC_RCALL1, PIC_MCALL, 22H_PCREL, RCALL2, 4),
  1741. + RP(PIC_RCALL1, NONE, NONE, PIC_RCALL2, 11H_PCREL, RCALL1, 2),
  1742. +
  1743. + RG(PIC_LDA, PIC_SUB5, PIC_LDW4, NONE, LDA_GOT, PIC_MOV2, 8),
  1744. + RG(PIC_LDW4, PIC_SUB5, PIC_LDW3, PIC_LDA, GOT16S, PIC_LDW4, 4),
  1745. + RG(PIC_LDW3, PIC_SUB5, NONE, PIC_LDW4, GOT7UW, PIC_LDW3, 2),
  1746. + RP(PIC_SUB5, NONE, NONE, PIC_LDW3, 16N_PCREL, SUB5_PC, 4),
  1747. +
  1748. + RC(NOPIC_MCALL, NOPIC_RCALL1, NONE, NONE, CPCALL, NOPIC_MCALL, 4),
  1749. + RP(NOPIC_RCALL2, NONE, NOPIC_RCALL1, NOPIC_MCALL, 22H_PCREL, RCALL2, 4),
  1750. + RP(NOPIC_RCALL1, NONE, NONE, NOPIC_RCALL2, 11H_PCREL, RCALL1, 2),
  1751. +
  1752. + RC(NOPIC_LDW4, NOPIC_MOV1, NOPIC_LDDPC, NONE, 16_CP, NOPIC_LDW4, 4),
  1753. + RC(NOPIC_LDDPC, NOPIC_MOV1, NONE, NOPIC_LDW4, 9W_CP, LDDPC, 2),
  1754. + RP(NOPIC_SUB5, NOPIC_MOV1, NONE, NOPIC_LDDPC, 16N_PCREL, SUB5_PC, 4),
  1755. + RD(NOPIC_MOV2, NONE, NOPIC_MOV1, NOPIC_SUB5, 21S, NOPIC_MOV2, 4),
  1756. + RD(NOPIC_MOV1, NONE, NONE, NOPIC_MOV2, 8S, NOPIC_MOV1, 2),
  1757. +
  1758. + RP(RCALL2, NONE, RCALL1, NONE, 22H_PCREL, RCALL2, 4),
  1759. + RP(RCALL1, NONE, NONE, RCALL2, 11H_PCREL, RCALL1, 2),
  1760. + RP(BRC2, NONE, BRC1, NONE, 22H_PCREL, BRC2, 4),
  1761. + RP(BRC1, NONE, NONE, BRC2, 9H_PCREL, BRC1, 2),
  1762. + RP(BRAL, NONE, RJMP, NONE, 22H_PCREL, BRAL, 4),
  1763. + RP(RJMP, NONE, NONE, BRAL, 11H_PCREL, RJMP, 2),
  1764. +};
  1765. +
  1766. +static bfd_boolean
  1767. +avr32_elf_new_section_hook(bfd *abfd, asection *sec)
  1768. +{
  1769. + struct avr32_section_data *sdata;
  1770. +
  1771. + sdata = bfd_zalloc(abfd, sizeof(struct avr32_section_data));
  1772. + if (!sdata)
  1773. + return FALSE;
  1774. +
  1775. + sec->used_by_bfd = sdata;
  1776. + return _bfd_elf_new_section_hook(abfd, sec);
  1777. +}
  1778. +
  1779. +static struct avr32_relax_data *
  1780. +avr32_relax_data(asection *sec)
  1781. +{
  1782. + struct avr32_section_data *sdata;
  1783. +
  1784. + BFD_ASSERT(sec->used_by_bfd);
  1785. +
  1786. + sdata = (struct avr32_section_data *)elf_section_data(sec);
  1787. + return &sdata->relax_data;
  1788. +}
  1789. +
  1790. + /* Link-time relaxation */
  1791. +
  1792. +static bfd_boolean
  1793. +avr32_elf_relax_section(bfd *abfd, asection *sec,
  1794. + struct bfd_link_info *info, bfd_boolean *again);
  1795. +
  1796. +enum relax_pass_id {
  1797. + RELAX_PASS_SIZE_FRAGS,
  1798. + RELAX_PASS_MOVE_DATA,
  1799. +};
  1800. +
  1801. +/* Stolen from the xtensa port */
  1802. +static int
  1803. +internal_reloc_compare (const void *ap, const void *bp)
  1804. +{
  1805. + const Elf_Internal_Rela *a = (const Elf_Internal_Rela *) ap;
  1806. + const Elf_Internal_Rela *b = (const Elf_Internal_Rela *) bp;
  1807. +
  1808. + if (a->r_offset != b->r_offset)
  1809. + return (a->r_offset - b->r_offset);
  1810. +
  1811. + /* We don't need to sort on these criteria for correctness,
  1812. + but enforcing a more strict ordering prevents unstable qsort
  1813. + from behaving differently with different implementations.
  1814. + Without the code below we get correct but different results
  1815. + on Solaris 2.7 and 2.8. We would like to always produce the
  1816. + same results no matter the host. */
  1817. +
  1818. + if (a->r_info != b->r_info)
  1819. + return (a->r_info - b->r_info);
  1820. +
  1821. + return (a->r_addend - b->r_addend);
  1822. +}
  1823. +
  1824. +static enum relax_state_id
  1825. +get_pcrel22_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
  1826. + const Elf_Internal_Rela *rela)
  1827. +{
  1828. + bfd_byte *contents;
  1829. + bfd_vma insn;
  1830. + enum relax_state_id rs = RS_NONE;
  1831. +
  1832. + contents = retrieve_contents(abfd, sec, info->keep_memory);
  1833. + if (!contents)
  1834. + return RS_ERROR;
  1835. +
  1836. + insn = bfd_get_32(abfd, contents + rela->r_offset);
  1837. + if ((insn & RCALL2_MASK) == RCALL2_OPCODE)
  1838. + rs = RS_RCALL2;
  1839. + else if ((insn & BRAL_MASK) == BRAL_OPCODE)
  1840. + /* Optimizing bral -> rjmp gets us into all kinds of
  1841. + trouble with jump tables. Better not do it. */
  1842. + rs = RS_NONE;
  1843. + else if ((insn & BRC2_MASK) == BRC2_OPCODE)
  1844. + rs = RS_BRC2;
  1845. +
  1846. + release_contents(sec, contents);
  1847. +
  1848. + return rs;
  1849. +}
  1850. +
  1851. +static enum relax_state_id
  1852. +get_initial_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
  1853. + const Elf_Internal_Rela *rela)
  1854. +{
  1855. + switch (ELF_R_TYPE(rela->r_info))
  1856. + {
  1857. + case R_AVR32_GOTCALL:
  1858. + return RS_PIC_CALL;
  1859. + case R_AVR32_GOT18SW:
  1860. + return RS_PIC_MCALL;
  1861. + case R_AVR32_LDA_GOT:
  1862. + return RS_PIC_LDA;
  1863. + case R_AVR32_GOT16S:
  1864. + return RS_PIC_LDW4;
  1865. + case R_AVR32_CPCALL:
  1866. + return RS_NOPIC_MCALL;
  1867. + case R_AVR32_16_CP:
  1868. + return RS_NOPIC_LDW4;
  1869. + case R_AVR32_9W_CP:
  1870. + return RS_NOPIC_LDDPC;
  1871. + case R_AVR32_ALIGN:
  1872. + return RS_ALIGN;
  1873. + case R_AVR32_32_CPENT:
  1874. + return RS_CPENT;
  1875. + case R_AVR32_22H_PCREL:
  1876. + return get_pcrel22_relax_state(abfd, sec, info, rela);
  1877. + case R_AVR32_9H_PCREL:
  1878. + return RS_BRC1;
  1879. + default:
  1880. + return RS_NONE;
  1881. + }
  1882. +}
  1883. +
  1884. +static bfd_boolean
  1885. +reloc_is_cpool_ref(const Elf_Internal_Rela *rela)
  1886. +{
  1887. + switch (ELF_R_TYPE(rela->r_info))
  1888. + {
  1889. + case R_AVR32_CPCALL:
  1890. + case R_AVR32_16_CP:
  1891. + case R_AVR32_9W_CP:
  1892. + return TRUE;
  1893. + default:
  1894. + return FALSE;
  1895. + }
  1896. +}
  1897. +
  1898. +static struct fragment *
  1899. +new_frag(bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
  1900. + struct avr32_relax_data *rd, enum relax_state_id state,
  1901. + Elf_Internal_Rela *rela)
  1902. +{
  1903. + struct fragment *frag;
  1904. + bfd_size_type r_size;
  1905. + bfd_vma r_offset;
  1906. + unsigned int i = rd->frag_count;
  1907. +
  1908. + BFD_ASSERT(state >= RS_NONE && state < RS_MAX);
  1909. +
  1910. + rd->frag_count++;
  1911. + frag = bfd_realloc(rd->frag, sizeof(struct fragment) * rd->frag_count);
  1912. + if (!frag)
  1913. + return NULL;
  1914. + rd->frag = frag;
  1915. +
  1916. + frag += i;
  1917. + memset(frag, 0, sizeof(struct fragment));
  1918. +
  1919. + if (state == RS_ALIGN)
  1920. + r_size = (((rela->r_offset + (1 << rela->r_addend) - 1)
  1921. + & ~((1 << rela->r_addend) - 1)) - rela->r_offset);
  1922. + else
  1923. + r_size = relax_state[state].size;
  1924. +
  1925. + if (rela)
  1926. + r_offset = rela->r_offset;
  1927. + else
  1928. + r_offset = sec->size;
  1929. +
  1930. + if (i == 0)
  1931. + {
  1932. + frag->offset = 0;
  1933. + frag->size = r_offset + r_size;
  1934. + }
  1935. + else
  1936. + {
  1937. + frag->offset = rd->frag[i - 1].offset + rd->frag[i - 1].size;
  1938. + frag->size = r_offset + r_size - frag->offset;
  1939. + }
  1940. +
  1941. + if (state != RS_CPENT)
  1942. + /* Make sure we don't discard this frag */
  1943. + frag->refcount = 1;
  1944. +
  1945. + frag->initial_state = frag->state = state;
  1946. + frag->rela = rela;
  1947. +
  1948. + return frag;
  1949. +}
  1950. +
  1951. +static struct fragment *
  1952. +find_frag(asection *sec, bfd_vma offset)
  1953. +{
  1954. + struct fragment *first, *last;
  1955. + struct avr32_relax_data *rd = avr32_relax_data(sec);
  1956. +
  1957. + if (rd->frag_count == 0)
  1958. + return NULL;
  1959. +
  1960. + first = &rd->frag[0];
  1961. + last = &rd->frag[rd->frag_count - 1];
  1962. +
  1963. + /* This may be a reloc referencing the end of a section. The last
  1964. + frag will never have a reloc associated with it, so its size will
  1965. + never change, thus the offset adjustment of the last frag will
  1966. + always be the same as the offset adjustment of the end of the
  1967. + section. */
  1968. + if (offset == sec->size)
  1969. + {
  1970. + BFD_ASSERT(last->offset + last->size == sec->size);
  1971. + BFD_ASSERT(!last->rela);
  1972. + return last;
  1973. + }
  1974. +
  1975. + while (first <= last)
  1976. + {
  1977. + struct fragment *mid;
  1978. +
  1979. + mid = (last - first) / 2 + first;
  1980. + if ((mid->offset + mid->size) <= offset)
  1981. + first = mid + 1;
  1982. + else if (mid->offset > offset)
  1983. + last = mid - 1;
  1984. + else
  1985. + return mid;
  1986. + }
  1987. +
  1988. + return NULL;
  1989. +}
  1990. +
  1991. +/* Look through all relocs in a section and determine if any relocs
  1992. + may be affected by relaxation in other sections. If so, allocate
  1993. + an array of additional relocation data which links the affected
  1994. + relocations to the frag(s) where the relaxation may occur.
  1995. +
  1996. + This function also links cpool references to cpool entries and
  1997. + increments the refcount of the latter when this happens. */
  1998. +
  1999. +static bfd_boolean
  2000. +allocate_reloc_data(bfd *abfd, asection *sec, Elf_Internal_Rela *relocs,
  2001. + struct bfd_link_info *info)
  2002. +{
  2003. + Elf_Internal_Shdr *symtab_hdr;
  2004. + Elf_Internal_Sym *isymbuf = NULL;
  2005. + struct avr32_relax_data *rd;
  2006. + unsigned int i;
  2007. + bfd_boolean ret = FALSE;
  2008. +
  2009. + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
  2010. + rd = avr32_relax_data(sec);
  2011. +
  2012. + RDBG("%s<%s>: allocate_reloc_data\n", abfd->filename, sec->name);
  2013. +
  2014. + for (i = 0; i < sec->reloc_count; i++)
  2015. + {
  2016. + Elf_Internal_Rela *rel = &relocs[i];
  2017. + asection *sym_sec;
  2018. + unsigned long r_symndx;
  2019. + bfd_vma sym_value;
  2020. +
  2021. + if (!rel->r_addend && ELF_R_TYPE(rel->r_info) != R_AVR32_DIFF32
  2022. + && !reloc_is_cpool_ref(rel))
  2023. + continue;
  2024. +
  2025. + r_symndx = ELF_R_SYM(rel->r_info);
  2026. +
  2027. + if (r_symndx < symtab_hdr->sh_info)
  2028. + {
  2029. + Elf_Internal_Sym *isym;
  2030. +
  2031. + if (!isymbuf)
  2032. + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
  2033. + if (!isymbuf)
  2034. + return FALSE;
  2035. +
  2036. + isym = &isymbuf[r_symndx];
  2037. + sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
  2038. + sym_value = isym->st_value;
  2039. + }
  2040. + else
  2041. + {
  2042. + struct elf_link_hash_entry *h;
  2043. +
  2044. + h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
  2045. +
  2046. + while (h->root.type == bfd_link_hash_indirect
  2047. + || h->root.type == bfd_link_hash_warning)
  2048. + h = (struct elf_link_hash_entry *)h->root.u.i.link;
  2049. +
  2050. + if (h->root.type != bfd_link_hash_defined
  2051. + && h->root.type != bfd_link_hash_defweak)
  2052. + continue;
  2053. +
  2054. + sym_sec = h->root.u.def.section;
  2055. + sym_value = h->root.u.def.value;
  2056. + }
  2057. +
  2058. + if (sym_sec && avr32_relax_data(sym_sec)->is_relaxable)
  2059. + {
  2060. + bfd_size_type size;
  2061. + struct fragment *frag;
  2062. +
  2063. + if (!rd->reloc_data)
  2064. + {
  2065. + size = sizeof(struct avr32_reloc_data) * sec->reloc_count;
  2066. + rd->reloc_data = bfd_zalloc(abfd, size);
  2067. + if (!rd->reloc_data)
  2068. + goto out;
  2069. + }
  2070. +
  2071. + RDBG("[%3d] 0x%04lx: target: 0x%lx + 0x%lx",
  2072. + i, rel->r_offset, sym_value, rel->r_addend);
  2073. +
  2074. + frag = find_frag(sym_sec, sym_value + rel->r_addend);
  2075. + BFD_ASSERT(frag);
  2076. + rd->reloc_data[i].add_frag = frag;
  2077. +
  2078. + RDBG(" -> %s<%s>:%04lx\n", sym_sec->owner->filename, sym_sec->name,
  2079. + frag->rela ? frag->rela->r_offset : sym_sec->size);
  2080. +
  2081. + if (reloc_is_cpool_ref(rel))
  2082. + {
  2083. + BFD_ASSERT(ELF_R_TYPE(frag->rela->r_info) == R_AVR32_32_CPENT);
  2084. + frag->refcount++;
  2085. + }
  2086. +
  2087. + if (ELF_R_TYPE(rel->r_info) == R_AVR32_DIFF32)
  2088. + {
  2089. + bfd_byte *contents;
  2090. + bfd_signed_vma diff;
  2091. +
  2092. + contents = retrieve_contents(abfd, sec, info->keep_memory);
  2093. + if (!contents)
  2094. + goto out;
  2095. +
  2096. + diff = bfd_get_signed_32(abfd, contents + rel->r_offset);
  2097. + frag = find_frag(sym_sec, sym_value + rel->r_addend + diff);
  2098. + BFD_ASSERT(frag);
  2099. + rd->reloc_data[i].sub_frag = frag;
  2100. +
  2101. + release_contents(sec, contents);
  2102. + }
  2103. + }
  2104. + }
  2105. +
  2106. + ret = TRUE;
  2107. +
  2108. + out:
  2109. + release_local_syms(abfd, isymbuf);
  2110. + return ret;
  2111. +}
  2112. +
  2113. +static bfd_boolean
  2114. +global_sym_set_frag(struct elf_avr32_link_hash_entry *havr,
  2115. + struct bfd_link_info *info ATTRIBUTE_UNUSED)
  2116. +{
  2117. + struct fragment *frag;
  2118. + asection *sec;
  2119. +
  2120. + if (havr->root.root.type != bfd_link_hash_defined
  2121. + && havr->root.root.type != bfd_link_hash_defweak)
  2122. + return TRUE;
  2123. +
  2124. + sec = havr->root.root.u.def.section;
  2125. + if (bfd_is_const_section(sec)
  2126. + || !avr32_relax_data(sec)->is_relaxable)
  2127. + return TRUE;
  2128. +
  2129. + frag = find_frag(sec, havr->root.root.u.def.value);
  2130. + if (!frag)
  2131. + {
  2132. + unsigned int i;
  2133. + struct avr32_relax_data *rd = avr32_relax_data(sec);
  2134. +
  2135. + RDBG("In %s: No frag for %s <%s+%lu> (limit %lu)\n",
  2136. + sec->owner->filename, havr->root.root.root.string,
  2137. + sec->name, havr->root.root.u.def.value, sec->size);
  2138. + for (i = 0; i < rd->frag_count; i++)
  2139. + RDBG(" %8lu - %8lu\n", rd->frag[i].offset,
  2140. + rd->frag[i].offset + rd->frag[i].size);
  2141. + }
  2142. + BFD_ASSERT(frag);
  2143. +
  2144. + havr->sym_frag = frag;
  2145. + return TRUE;
  2146. +}
  2147. +
  2148. +static bfd_boolean
  2149. +analyze_relocations(struct bfd_link_info *info)
  2150. +{
  2151. + bfd *abfd;
  2152. + asection *sec;
  2153. +
  2154. + /* Divide all relaxable sections into fragments */
  2155. + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
  2156. + {
  2157. + if (!(elf_elfheader(abfd)->e_flags & EF_AVR32_LINKRELAX))
  2158. + {
  2159. + if (!(*info->callbacks->warning)
  2160. + (info, _("input is not relaxable"), NULL, abfd, NULL, 0))
  2161. + return FALSE;
  2162. + continue;
  2163. + }
  2164. +
  2165. + for (sec = abfd->sections; sec; sec = sec->next)
  2166. + {
  2167. + struct avr32_relax_data *rd;
  2168. + struct fragment *frag;
  2169. + Elf_Internal_Rela *relocs;
  2170. + unsigned int i;
  2171. + bfd_boolean ret = TRUE;
  2172. +
  2173. + if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
  2174. + continue;
  2175. +
  2176. + rd = avr32_relax_data(sec);
  2177. +
  2178. + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
  2179. + if (!relocs)
  2180. + return FALSE;
  2181. +
  2182. + qsort(relocs, sec->reloc_count, sizeof(Elf_Internal_Rela),
  2183. + internal_reloc_compare);
  2184. +
  2185. + for (i = 0; i < sec->reloc_count; i++)
  2186. + {
  2187. + enum relax_state_id state;
  2188. +
  2189. + ret = FALSE;
  2190. + state = get_initial_relax_state(abfd, sec, info, &relocs[i]);
  2191. + if (state == RS_ERROR)
  2192. + break;
  2193. +
  2194. + if (state)
  2195. + {
  2196. + frag = new_frag(abfd, sec, rd, state, &relocs[i]);
  2197. + if (!frag)
  2198. + break;
  2199. +
  2200. + pin_internal_relocs(sec, relocs);
  2201. + rd->is_relaxable = TRUE;
  2202. + }
  2203. +
  2204. + ret = TRUE;
  2205. + }
  2206. +
  2207. + release_internal_relocs(sec, relocs);
  2208. + if (!ret)
  2209. + return ret;
  2210. +
  2211. + if (rd->is_relaxable)
  2212. + {
  2213. + frag = new_frag(abfd, sec, rd, RS_NONE, NULL);
  2214. + if (!frag)
  2215. + return FALSE;
  2216. + }
  2217. + }
  2218. + }
  2219. +
  2220. + /* Link each global symbol to the fragment where it's defined. */
  2221. + elf_link_hash_traverse(elf_hash_table(info), global_sym_set_frag, info);
  2222. +
  2223. + /* Do the same for local symbols. */
  2224. + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
  2225. + {
  2226. + Elf_Internal_Sym *isymbuf, *isym;
  2227. + struct fragment **local_sym_frag;
  2228. + unsigned int i, sym_count;
  2229. +
  2230. + sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
  2231. + if (sym_count == 0)
  2232. + continue;
  2233. +
  2234. + local_sym_frag = bfd_zalloc(abfd, sym_count * sizeof(struct fragment *));
  2235. + if (!local_sym_frag)
  2236. + return FALSE;
  2237. + elf_tdata(abfd)->local_sym_frag = local_sym_frag;
  2238. +
  2239. + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
  2240. + if (!isymbuf)
  2241. + return FALSE;
  2242. +
  2243. + for (i = 0; i < sym_count; i++)
  2244. + {
  2245. + struct avr32_relax_data *rd;
  2246. + struct fragment *frag;
  2247. + asection *sec;
  2248. +
  2249. + isym = &isymbuf[i];
  2250. +
  2251. + sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
  2252. + if (!sec)
  2253. + continue;
  2254. +
  2255. + rd = avr32_relax_data(sec);
  2256. + if (!rd->is_relaxable)
  2257. + continue;
  2258. +
  2259. + frag = find_frag(sec, isym->st_value);
  2260. + BFD_ASSERT(frag);
  2261. +
  2262. + local_sym_frag[i] = frag;
  2263. + }
  2264. +
  2265. + release_local_syms(abfd, isymbuf);
  2266. + }
  2267. +
  2268. + /* And again for relocs with addends and constant pool references */
  2269. + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
  2270. + for (sec = abfd->sections; sec; sec = sec->next)
  2271. + {
  2272. + Elf_Internal_Rela *relocs;
  2273. + bfd_boolean ret;
  2274. +
  2275. + if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
  2276. + continue;
  2277. +
  2278. + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
  2279. + if (!relocs)
  2280. + return FALSE;
  2281. +
  2282. + ret = allocate_reloc_data(abfd, sec, relocs, info);
  2283. +
  2284. + release_internal_relocs(sec, relocs);
  2285. + if (ret == FALSE)
  2286. + return ret;
  2287. + }
  2288. +
  2289. + return TRUE;
  2290. +}
  2291. +
  2292. +static bfd_boolean
  2293. +rs_is_good_enough(const struct relax_state *rs, struct fragment *frag,
  2294. + bfd_vma symval, bfd_vma addr, struct got_entry *got,
  2295. + struct avr32_reloc_data *ind_data,
  2296. + bfd_signed_vma offset_adjust)
  2297. +{
  2298. + bfd_signed_vma target = 0;
  2299. +
  2300. + switch (rs->reftype)
  2301. + {
  2302. + case REF_ABSOLUTE:
  2303. + target = symval;
  2304. + break;
  2305. + case REF_PCREL:
  2306. + target = symval - addr;
  2307. + break;
  2308. + case REF_CPOOL:
  2309. + /* cpool frags are always in the same section and always after
  2310. + all frags referring to it. So it's always correct to add in
  2311. + offset_adjust here. */
  2312. + target = (ind_data->add_frag->offset + ind_data->add_frag->offset_adjust
  2313. + + offset_adjust - frag->offset - frag->offset_adjust);
  2314. + break;
  2315. + case REF_GOT:
  2316. + target = got->offset;
  2317. + break;
  2318. + default:
  2319. + abort();
  2320. + }
  2321. +
  2322. + if (target >= rs->range_min && target <= rs->range_max)
  2323. + return TRUE;
  2324. + else
  2325. + return FALSE;
  2326. +}
  2327. +
  2328. +static bfd_boolean
  2329. +avr32_size_frags(bfd *abfd, asection *sec, struct bfd_link_info *info)
  2330. +{
  2331. + struct elf_avr32_link_hash_table *htab;
  2332. + struct avr32_relax_data *rd;
  2333. + Elf_Internal_Shdr *symtab_hdr;
  2334. + Elf_Internal_Rela *relocs = NULL;
  2335. + Elf_Internal_Sym *isymbuf = NULL;
  2336. + struct got_entry **local_got_ents;
  2337. + struct fragment **local_sym_frag;
  2338. + bfd_boolean ret = FALSE;
  2339. + bfd_signed_vma delta = 0;
  2340. + unsigned int i;
  2341. +
  2342. + htab = avr32_elf_hash_table(info);
  2343. + rd = avr32_relax_data(sec);
  2344. +
  2345. + if (sec == htab->sgot)
  2346. + {
  2347. + RDBG("Relaxing GOT section (vma: 0x%lx)\n",
  2348. + sec->output_section->vma + sec->output_offset);
  2349. + if (assign_got_offsets(htab))
  2350. + htab->repeat_pass = TRUE;
  2351. + return TRUE;
  2352. + }
  2353. +
  2354. + if (!rd->is_relaxable)
  2355. + return TRUE;
  2356. +
  2357. + if (!sec->rawsize)
  2358. + sec->rawsize = sec->size;
  2359. +
  2360. + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
  2361. + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
  2362. + if (!relocs)
  2363. + goto out;
  2364. +
  2365. + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
  2366. + if (!isymbuf)
  2367. + goto out;
  2368. +
  2369. + local_got_ents = elf_local_got_ents(abfd);
  2370. + local_sym_frag = elf_tdata(abfd)->local_sym_frag;
  2371. +
  2372. + RDBG("size_frags: %s<%s>\n vma: 0x%08lx, size: 0x%08lx\n",
  2373. + abfd->filename, sec->name,
  2374. + sec->output_section->vma + sec->output_offset, sec->size);
  2375. +
  2376. + for (i = 0; i < rd->frag_count; i++)
  2377. + {
  2378. + struct fragment *frag = &rd->frag[i];
  2379. + struct avr32_reloc_data *r_data = NULL, *ind_data = NULL;
  2380. + const struct relax_state *state, *next_state;
  2381. + struct fragment *target_frag = NULL;
  2382. + asection *sym_sec = NULL;
  2383. + Elf_Internal_Rela *rela;
  2384. + struct got_entry *got;
  2385. + bfd_vma symval, r_offset, addend, addr;
  2386. + bfd_signed_vma size_adjust = 0, distance;
  2387. + unsigned long r_symndx;
  2388. + bfd_boolean defined = TRUE, dynamic = FALSE;
  2389. + unsigned char sym_type;
  2390. +
  2391. + frag->offset_adjust += delta;
  2392. + state = next_state = &relax_state[frag->state];
  2393. + rela = frag->rela;
  2394. +
  2395. + BFD_ASSERT(state->id == frag->state);
  2396. +
  2397. + RDBG(" 0x%04lx%c%d: %s [size %ld]", rela ? rela->r_offset : sec->rawsize,
  2398. + (frag->offset_adjust < 0)?'-':'+',
  2399. + abs(frag->offset_adjust), state->name, state->size);
  2400. +
  2401. + if (!rela)
  2402. + {
  2403. + RDBG(": no reloc, ignoring\n");
  2404. + continue;
  2405. + }
  2406. +
  2407. + BFD_ASSERT((unsigned int)(rela - relocs) < sec->reloc_count);
  2408. + BFD_ASSERT(state != RS_NONE);
  2409. +
  2410. + r_offset = rela->r_offset + frag->offset_adjust;
  2411. + addr = sec->output_section->vma + sec->output_offset + r_offset;
  2412. +
  2413. + switch (frag->state)
  2414. + {
  2415. + case RS_ALIGN:
  2416. + size_adjust = ((addr + (1 << rela->r_addend) - 1)
  2417. + & ~((1 << rela->r_addend) - 1));
  2418. + size_adjust -= (sec->output_section->vma + sec->output_offset
  2419. + + frag->offset + frag->offset_adjust
  2420. + + frag->size + frag->size_adjust);
  2421. +
  2422. + RDBG(": adjusting size %lu -> %lu\n", frag->size + frag->size_adjust,
  2423. + frag->size + frag->size_adjust + size_adjust);
  2424. + break;
  2425. +
  2426. + case RS_CPENT:
  2427. + if (frag->refcount == 0 && frag->size_adjust == 0)
  2428. + {
  2429. + RDBG(": discarding frag\n");
  2430. + size_adjust = -4;
  2431. + }
  2432. + else if (frag->refcount > 0 && frag->size_adjust < 0)
  2433. + {
  2434. + RDBG(": un-discarding frag\n");
  2435. + size_adjust = 4;
  2436. + }
  2437. + break;
  2438. +
  2439. + default:
  2440. + if (rd->reloc_data)
  2441. + r_data = &rd->reloc_data[frag->rela - relocs];
  2442. +
  2443. + /* If this is a cpool reference, we want the symbol that the
  2444. + cpool entry refers to, not the symbol for the cpool entry
  2445. + itself, as we already know what frag it's in. */
  2446. + if (relax_state[frag->initial_state].reftype == REF_CPOOL)
  2447. + {
  2448. + Elf_Internal_Rela *irela = r_data->add_frag->rela;
  2449. +
  2450. + r_symndx = ELF_R_SYM(irela->r_info);
  2451. + addend = irela->r_addend;
  2452. +
  2453. + /* The constant pool must be in the same section as the
  2454. + reloc referring to it. */
  2455. + BFD_ASSERT((unsigned long)(irela - relocs) < sec->reloc_count);
  2456. +
  2457. + ind_data = r_data;
  2458. + r_data = &rd->reloc_data[irela - relocs];
  2459. + }
  2460. + else
  2461. + {
  2462. + r_symndx = ELF_R_SYM(rela->r_info);
  2463. + addend = rela->r_addend;
  2464. + }
  2465. +
  2466. + /* Get the value of the symbol referred to by the reloc. */
  2467. + if (r_symndx < symtab_hdr->sh_info)
  2468. + {
  2469. + Elf_Internal_Sym *isym;
  2470. +
  2471. + isym = isymbuf + r_symndx;
  2472. + symval = 0;
  2473. +
  2474. + RDBG(" local sym %lu: ", r_symndx);
  2475. +
  2476. + if (isym->st_shndx == SHN_UNDEF)
  2477. + defined = FALSE;
  2478. + else if (isym->st_shndx == SHN_ABS)
  2479. + sym_sec = bfd_abs_section_ptr;
  2480. + else if (isym->st_shndx == SHN_COMMON)
  2481. + sym_sec = bfd_com_section_ptr;
  2482. + else
  2483. + sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
  2484. +
  2485. + symval = isym->st_value;
  2486. + sym_type = ELF_ST_TYPE(isym->st_info);
  2487. + target_frag = local_sym_frag[r_symndx];
  2488. +
  2489. + if (local_got_ents)
  2490. + got = local_got_ents[r_symndx];
  2491. + else
  2492. + got = NULL;
  2493. + }
  2494. + else
  2495. + {
  2496. + /* Global symbol */
  2497. + unsigned long index;
  2498. + struct elf_link_hash_entry *h;
  2499. + struct elf_avr32_link_hash_entry *havr;
  2500. +
  2501. + index = r_symndx - symtab_hdr->sh_info;
  2502. + h = elf_sym_hashes(abfd)[index];
  2503. + BFD_ASSERT(h != NULL);
  2504. +
  2505. + while (h->root.type == bfd_link_hash_indirect
  2506. + || h->root.type == bfd_link_hash_warning)
  2507. + h = (struct elf_link_hash_entry *)h->root.u.i.link;
  2508. +
  2509. + havr = (struct elf_avr32_link_hash_entry *)h;
  2510. + got = h->got.glist;
  2511. +
  2512. + symval = 0;
  2513. +
  2514. + RDBG(" %s: ", h->root.root.string);
  2515. +
  2516. + if (h->root.type != bfd_link_hash_defined
  2517. + && h->root.type != bfd_link_hash_defweak)
  2518. + {
  2519. + RDBG("(undef)");
  2520. + defined = FALSE;
  2521. + }
  2522. + else if ((info->shared && !info->symbolic && h->dynindx != -1)
  2523. + || (htab->root.dynamic_sections_created
  2524. + && h->def_dynamic && !h->def_regular))
  2525. + {
  2526. + RDBG("(dynamic)");
  2527. + dynamic = TRUE;
  2528. + sym_sec = h->root.u.def.section;
  2529. + }
  2530. + else
  2531. + {
  2532. + sym_sec = h->root.u.def.section;
  2533. + symval = h->root.u.def.value;
  2534. + target_frag = havr->sym_frag;
  2535. + }
  2536. +
  2537. + sym_type = h->type;
  2538. + }
  2539. +
  2540. + /* Thanks to elf32-ppc for this one. */
  2541. + if (sym_sec && sym_sec->sec_info_type == ELF_INFO_TYPE_MERGE)
  2542. + {
  2543. + /* At this stage in linking, no SEC_MERGE symbol has been
  2544. + adjusted, so all references to such symbols need to be
  2545. + passed through _bfd_merged_section_offset. (Later, in
  2546. + relocate_section, all SEC_MERGE symbols *except* for
  2547. + section symbols have been adjusted.)
  2548. +
  2549. + SEC_MERGE sections are not relaxed by us, as they
  2550. + shouldn't contain any code. */
  2551. +
  2552. + BFD_ASSERT(!target_frag && !(r_data && r_data->add_frag));
  2553. +
  2554. + /* gas may reduce relocations against symbols in SEC_MERGE
  2555. + sections to a relocation against the section symbol when
  2556. + the original addend was zero. When the reloc is against
  2557. + a section symbol we should include the addend in the
  2558. + offset passed to _bfd_merged_section_offset, since the
  2559. + location of interest is the original symbol. On the
  2560. + other hand, an access to "sym+addend" where "sym" is not
  2561. + a section symbol should not include the addend; Such an
  2562. + access is presumed to be an offset from "sym"; The
  2563. + location of interest is just "sym". */
  2564. + RDBG("\n MERGE: %s: 0x%lx+0x%lx+0x%lx -> ",
  2565. + (sym_type == STT_SECTION)?"section":"not section",
  2566. + sym_sec->output_section->vma + sym_sec->output_offset,
  2567. + symval, addend);
  2568. +
  2569. + if (sym_type == STT_SECTION)
  2570. + symval += addend;
  2571. +
  2572. + symval = (_bfd_merged_section_offset
  2573. + (abfd, &sym_sec,
  2574. + elf_section_data(sym_sec)->sec_info, symval));
  2575. +
  2576. + if (sym_type != STT_SECTION)
  2577. + symval += addend;
  2578. + }
  2579. + else
  2580. + symval += addend;
  2581. +
  2582. + if (defined && !dynamic)
  2583. + {
  2584. + RDBG("0x%lx+0x%lx",
  2585. + sym_sec->output_section->vma + sym_sec->output_offset,
  2586. + symval);
  2587. + symval += sym_sec->output_section->vma + sym_sec->output_offset;
  2588. + }
  2589. +
  2590. + if (r_data && r_data->add_frag)
  2591. + /* If the add_frag pointer is set, it means that this reloc
  2592. + has an addend that may be affected by relaxation. */
  2593. + target_frag = r_data->add_frag;
  2594. +
  2595. + if (target_frag)
  2596. + {
  2597. + symval += target_frag->offset_adjust;
  2598. +
  2599. + /* If target_frag comes after this frag in the same
  2600. + section, we should assume that it will be moved by
  2601. + the same amount we are. */
  2602. + if ((target_frag - rd->frag) < (int)rd->frag_count
  2603. + && target_frag > frag)
  2604. + symval += delta;
  2605. + }
  2606. +
  2607. + distance = symval - addr;
  2608. +
  2609. + /* First, try to make a direct reference. If the symbol is
  2610. + dynamic or undefined, we must take care not to change its
  2611. + reference type, that is, we can't make it direct.
  2612. +
  2613. + Also, it seems like some sections may actually be resized
  2614. + after the relaxation code is done, so we can't really
  2615. + trust that our "distance" is correct. There's really no
  2616. + easy solution to this problem, so we'll just disallow
  2617. + direct references to SEC_DATA sections.
  2618. +
  2619. + Oh, and .bss isn't actually SEC_DATA, so we disallow
  2620. + !SEC_HAS_CONTENTS as well. */
  2621. + if (!dynamic && defined
  2622. + && (htab->direct_data_refs
  2623. + || (!(sym_sec->flags & SEC_DATA)
  2624. + && (sym_sec->flags & SEC_HAS_CONTENTS)))
  2625. + && next_state->direct)
  2626. + {
  2627. + next_state = &relax_state[next_state->direct];
  2628. + RDBG(" D-> %s", next_state->name);
  2629. + }
  2630. +
  2631. + /* Iterate backwards until we find a state that fits. */
  2632. + while (next_state->prev
  2633. + && !rs_is_good_enough(next_state, frag, symval, addr,
  2634. + got, ind_data, delta))
  2635. + {
  2636. + next_state = &relax_state[next_state->prev];
  2637. + RDBG(" P-> %s", next_state->name);
  2638. + }
  2639. +
  2640. + /* Then try to find the best possible state. */
  2641. + while (next_state->next)
  2642. + {
  2643. + const struct relax_state *candidate;
  2644. +
  2645. + candidate = &relax_state[next_state->next];
  2646. + if (!rs_is_good_enough(candidate, frag, symval, addr, got,
  2647. + ind_data, delta))
  2648. + break;
  2649. +
  2650. + next_state = candidate;
  2651. + RDBG(" N-> %s", next_state->name);
  2652. + }
  2653. +
  2654. + RDBG(" [size %ld]\n", next_state->size);
  2655. +
  2656. + BFD_ASSERT(next_state->id);
  2657. + BFD_ASSERT(!dynamic || next_state->reftype == REF_GOT);
  2658. +
  2659. + size_adjust = next_state->size - state->size;
  2660. +
  2661. + /* There's a theoretical possibility that shrinking one frag
  2662. + may cause another to grow, which may cause the first one to
  2663. + grow as well, and we're back where we started. Avoid this
  2664. + scenario by disallowing a frag that has grown to ever
  2665. + shrink again. */
  2666. + if (state->reftype == REF_GOT && next_state->reftype != REF_GOT)
  2667. + {
  2668. + if (frag->has_grown)
  2669. + next_state = state;
  2670. + else
  2671. + unref_got_entry(htab, got);
  2672. + }
  2673. + else if (state->reftype != REF_GOT && next_state->reftype == REF_GOT)
  2674. + {
  2675. + ref_got_entry(htab, got);
  2676. + frag->has_grown = TRUE;
  2677. + }
  2678. + else if (state->reftype == REF_CPOOL
  2679. + && next_state->reftype != REF_CPOOL)
  2680. + {
  2681. + if (frag->has_grown)
  2682. + next_state = state;
  2683. + else
  2684. + ind_data->add_frag->refcount--;
  2685. + }
  2686. + else if (state->reftype != REF_CPOOL
  2687. + && next_state->reftype == REF_CPOOL)
  2688. + {
  2689. + ind_data->add_frag->refcount++;
  2690. + frag->has_grown = TRUE;
  2691. + }
  2692. + else
  2693. + {
  2694. + if (frag->has_grown && size_adjust < 0)
  2695. + next_state = state;
  2696. + else if (size_adjust > 0)
  2697. + frag->has_grown = TRUE;
  2698. + }
  2699. +
  2700. + size_adjust = next_state->size - state->size;
  2701. + frag->state = next_state->id;
  2702. +
  2703. + break;
  2704. + }
  2705. +
  2706. + if (size_adjust)
  2707. + htab->repeat_pass = TRUE;
  2708. +
  2709. + frag->size_adjust += size_adjust;
  2710. + sec->size += size_adjust;
  2711. + delta += size_adjust;
  2712. +
  2713. + BFD_ASSERT((frag->offset + frag->offset_adjust
  2714. + + frag->size + frag->size_adjust)
  2715. + == (frag[1].offset + frag[1].offset_adjust + delta));
  2716. + }
  2717. +
  2718. + ret = TRUE;
  2719. +
  2720. + out:
  2721. + release_local_syms(abfd, isymbuf);
  2722. + release_internal_relocs(sec, relocs);
  2723. + return ret;
  2724. +}
  2725. +
  2726. +static bfd_boolean
  2727. +adjust_global_symbol(struct elf_avr32_link_hash_entry *havr,
  2728. + struct bfd_link_info *info ATTRIBUTE_UNUSED)
  2729. +{
  2730. + struct elf_link_hash_entry *h = &havr->root;
  2731. +
  2732. + if (havr->sym_frag && (h->root.type == bfd_link_hash_defined
  2733. + || h->root.type == bfd_link_hash_defweak))
  2734. + {
  2735. + RDBG("adjust_global_symbol: %s 0x%08lx -> 0x%08lx\n",
  2736. + h->root.root.string, h->root.u.def.value,
  2737. + h->root.u.def.value + havr->sym_frag->offset_adjust);
  2738. + h->root.u.def.value += havr->sym_frag->offset_adjust;
  2739. + }
  2740. + return TRUE;
  2741. +}
  2742. +
  2743. +static bfd_boolean
  2744. +adjust_syms(struct bfd_link_info *info)
  2745. +{
  2746. + struct elf_avr32_link_hash_table *htab;
  2747. + bfd *abfd;
  2748. +
  2749. + htab = avr32_elf_hash_table(info);
  2750. + elf_link_hash_traverse(&htab->root, adjust_global_symbol, info);
  2751. +
  2752. + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
  2753. + {
  2754. + Elf_Internal_Sym *isymbuf;
  2755. + struct fragment **local_sym_frag, *frag;
  2756. + unsigned int i, sym_count;
  2757. +
  2758. + sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
  2759. + if (sym_count == 0)
  2760. + continue;
  2761. +
  2762. + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
  2763. + if (!isymbuf)
  2764. + return FALSE;
  2765. +
  2766. + local_sym_frag = elf_tdata(abfd)->local_sym_frag;
  2767. +
  2768. + for (i = 0; i < sym_count; i++)
  2769. + {
  2770. + frag = local_sym_frag[i];
  2771. + if (frag)
  2772. + {
  2773. + RDBG("adjust_local_symbol: %s[%u] 0x%08lx -> 0x%08lx\n",
  2774. + abfd->filename, i, isymbuf[i].st_value,
  2775. + isymbuf[i].st_value + frag->offset_adjust);
  2776. + isymbuf[i].st_value += frag->offset_adjust;
  2777. + }
  2778. + }
  2779. +
  2780. + release_local_syms(abfd, isymbuf);
  2781. + }
  2782. +
  2783. + htab->symbols_adjusted = TRUE;
  2784. + return TRUE;
  2785. +}
  2786. +
  2787. +static bfd_boolean
  2788. +adjust_relocs(bfd *abfd, asection *sec, struct bfd_link_info *info)
  2789. +{
  2790. + struct avr32_relax_data *rd;
  2791. + Elf_Internal_Rela *relocs;
  2792. + Elf_Internal_Shdr *symtab_hdr;
  2793. + unsigned int i;
  2794. + bfd_boolean ret = FALSE;
  2795. +
  2796. + rd = avr32_relax_data(sec);
  2797. + if (!rd->reloc_data)
  2798. + return TRUE;
  2799. +
  2800. + RDBG("adjust_relocs: %s<%s> (count: %u)\n", abfd->filename, sec->name,
  2801. + sec->reloc_count);
  2802. +
  2803. + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
  2804. + if (!relocs)
  2805. + return FALSE;
  2806. +
  2807. + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
  2808. +
  2809. + for (i = 0; i < sec->reloc_count; i++)
  2810. + {
  2811. + Elf_Internal_Rela *rela = &relocs[i];
  2812. + struct avr32_reloc_data *r_data = &rd->reloc_data[i];
  2813. + struct fragment *sym_frag;
  2814. + unsigned long r_symndx;
  2815. +
  2816. + if (r_data->add_frag)
  2817. + {
  2818. + r_symndx = ELF_R_SYM(rela->r_info);
  2819. +
  2820. + if (r_symndx < symtab_hdr->sh_info)
  2821. + sym_frag = elf_tdata(abfd)->local_sym_frag[r_symndx];
  2822. + else
  2823. + {
  2824. + struct elf_link_hash_entry *h;
  2825. +
  2826. + h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
  2827. +
  2828. + while (h->root.type == bfd_link_hash_indirect
  2829. + || h->root.type == bfd_link_hash_warning)
  2830. + h = (struct elf_link_hash_entry *)h->root.u.i.link;
  2831. +
  2832. + BFD_ASSERT(h->root.type == bfd_link_hash_defined
  2833. + || h->root.type == bfd_link_hash_defweak);
  2834. +
  2835. + sym_frag = ((struct elf_avr32_link_hash_entry *)h)->sym_frag;
  2836. + }
  2837. +
  2838. + RDBG(" addend: 0x%08lx -> 0x%08lx\n",
  2839. + rela->r_addend,
  2840. + rela->r_addend + r_data->add_frag->offset_adjust
  2841. + - (sym_frag ? sym_frag->offset_adjust : 0));
  2842. +
  2843. + /* If this is against a section symbol, we won't find any
  2844. + sym_frag, so we'll just adjust the addend. */
  2845. + rela->r_addend += r_data->add_frag->offset_adjust;
  2846. + if (sym_frag)
  2847. + rela->r_addend -= sym_frag->offset_adjust;
  2848. +
  2849. + if (r_data->sub_frag)
  2850. + {
  2851. + bfd_byte *contents;
  2852. + bfd_signed_vma diff;
  2853. +
  2854. + contents = retrieve_contents(abfd, sec, info->keep_memory);
  2855. + if (!contents)
  2856. + goto out;
  2857. +
  2858. + /* I realize now that sub_frag is misnamed. It's
  2859. + actually add_frag which is subtracted in this
  2860. + case... */
  2861. + diff = bfd_get_signed_32(abfd, contents + rela->r_offset);
  2862. + diff += (r_data->sub_frag->offset_adjust
  2863. + - r_data->add_frag->offset_adjust);
  2864. + bfd_put_32(abfd, diff, contents + rela->r_offset);
  2865. +
  2866. + RDBG(" 0x%lx: DIFF32 updated: 0x%lx\n", rela->r_offset, diff);
  2867. +
  2868. + release_contents(sec, contents);
  2869. + }
  2870. + }
  2871. + else
  2872. + BFD_ASSERT(!r_data->sub_frag);
  2873. + }
  2874. +
  2875. + ret = TRUE;
  2876. +
  2877. + out:
  2878. + release_internal_relocs(sec, relocs);
  2879. + return ret;
  2880. +}
  2881. +
  2882. +static bfd_boolean
  2883. +avr32_move_data(bfd *abfd, asection *sec, struct bfd_link_info *info)
  2884. +{
  2885. + struct elf_avr32_link_hash_table *htab;
  2886. + struct avr32_relax_data *rd;
  2887. + struct fragment *frag, *fragend;
  2888. + Elf_Internal_Rela *relocs = NULL;
  2889. + bfd_byte *contents = NULL;
  2890. + unsigned int i;
  2891. + bfd_boolean ret = FALSE;
  2892. +
  2893. + htab = avr32_elf_hash_table(info);
  2894. + rd = avr32_relax_data(sec);
  2895. +
  2896. + if (!htab->symbols_adjusted)
  2897. + if (!adjust_syms(info))
  2898. + return FALSE;
  2899. +
  2900. + if (rd->is_relaxable)
  2901. + {
  2902. + /* Resize the section first, so that we can be sure that enough
  2903. + memory is allocated in case the section has grown. */
  2904. + if (sec->size > sec->rawsize
  2905. + && elf_section_data(sec)->this_hdr.contents)
  2906. + {
  2907. + /* We must not use cached data if the section has grown. */
  2908. + free(elf_section_data(sec)->this_hdr.contents);
  2909. + elf_section_data(sec)->this_hdr.contents = NULL;
  2910. + }
  2911. +
  2912. + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
  2913. + if (!relocs)
  2914. + goto out;
  2915. + contents = retrieve_contents(abfd, sec, info->keep_memory);
  2916. + if (!contents)
  2917. + goto out;
  2918. +
  2919. + fragend = rd->frag + rd->frag_count;
  2920. +
  2921. + RDBG("move_data: %s<%s>: relocs=%p, contents=%p\n",
  2922. + abfd->filename, sec->name, relocs, contents);
  2923. +
  2924. + /* First, move the data into place. We must take care to move
  2925. + frags in the right order so that we don't accidentally
  2926. + overwrite parts of the next frag. */
  2927. + for (frag = rd->frag; frag < fragend; frag++)
  2928. + {
  2929. + RDBG(" 0x%08lx%c0x%x: size 0x%lx%c0x%x\n",
  2930. + frag->offset, frag->offset_adjust >= 0 ? '+' : '-',
  2931. + abs(frag->offset_adjust),
  2932. + frag->size, frag->size_adjust >= 0 ? '+' : '-',
  2933. + abs(frag->size_adjust));
  2934. + if (frag->offset_adjust > 0)
  2935. + {
  2936. + struct fragment *prev = frag - 1;
  2937. + struct fragment *last;
  2938. +
  2939. + for (last = frag; last < fragend && last->offset_adjust > 0;
  2940. + last++) ;
  2941. +
  2942. + if (last == fragend)
  2943. + last--;
  2944. +
  2945. + for (frag = last; frag != prev; frag--)
  2946. + {
  2947. + if (frag->offset_adjust
  2948. + && frag->size + frag->size_adjust > 0)
  2949. + {
  2950. + RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
  2951. + frag->offset, frag->offset + frag->offset_adjust,
  2952. + frag->size + frag->size_adjust);
  2953. + memmove(contents + frag->offset + frag->offset_adjust,
  2954. + contents + frag->offset,
  2955. + frag->size + frag->size_adjust);
  2956. + }
  2957. + }
  2958. + frag = last;
  2959. + }
  2960. + else if (frag->offset_adjust && frag->size + frag->size_adjust > 0)
  2961. + {
  2962. + RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
  2963. + frag->offset, frag->offset + frag->offset_adjust,
  2964. + frag->size + frag->size_adjust);
  2965. + memmove(contents + frag->offset + frag->offset_adjust,
  2966. + contents + frag->offset,
  2967. + frag->size + frag->size_adjust);
  2968. + }
  2969. + }
  2970. +
  2971. + i = 0;
  2972. +
  2973. + for (frag = rd->frag; frag < fragend; frag++)
  2974. + {
  2975. + const struct relax_state *state, *istate;
  2976. + struct avr32_reloc_data *r_data = NULL;
  2977. +
  2978. + istate = &relax_state[frag->initial_state];
  2979. + state = &relax_state[frag->state];
  2980. +
  2981. + if (rd->reloc_data)
  2982. + r_data = &rd->reloc_data[frag->rela - relocs];
  2983. +
  2984. + BFD_ASSERT((long)(frag->size + frag->size_adjust) >= 0);
  2985. + BFD_ASSERT(state->reftype != REF_CPOOL
  2986. + || r_data->add_frag->refcount > 0);
  2987. +
  2988. + if (istate->reftype == REF_CPOOL && state->reftype != REF_CPOOL)
  2989. + {
  2990. + struct fragment *ifrag;
  2991. +
  2992. + /* An indirect reference through the cpool has been
  2993. + converted to a direct reference. We must update the
  2994. + reloc to point to the symbol itself instead of the
  2995. + constant pool entry. The reloc type will be updated
  2996. + later. */
  2997. + ifrag = r_data->add_frag;
  2998. + frag->rela->r_info = ifrag->rela->r_info;
  2999. + frag->rela->r_addend = ifrag->rela->r_addend;
  3000. +
  3001. + /* Copy the reloc data so the addend will be adjusted
  3002. + correctly later. */
  3003. + *r_data = rd->reloc_data[ifrag->rela - relocs];
  3004. + }
  3005. +
  3006. + /* Move all relocs covered by this frag. */
  3007. + if (frag->rela)
  3008. + BFD_ASSERT(&relocs[i] <= frag->rela);
  3009. + else
  3010. + BFD_ASSERT((frag + 1) == fragend && frag->state == RS_NONE);
  3011. +
  3012. + if (frag == rd->frag)
  3013. + BFD_ASSERT(i == 0);
  3014. + else
  3015. + BFD_ASSERT(&relocs[i] > frag[-1].rela);
  3016. +
  3017. + /* If non-null, frag->rela is the last relocation in the
  3018. + fragment. frag->rela can only be null in the last
  3019. + fragment, so in that case, we'll just do the rest. */
  3020. + for (; (i < sec->reloc_count
  3021. + && (!frag->rela || &relocs[i] <= frag->rela)); i++)
  3022. + {
  3023. + RDBG("[%4u] r_offset 0x%08lx -> 0x%08lx\n", i, relocs[i].r_offset,
  3024. + relocs[i].r_offset + frag->offset_adjust);
  3025. + relocs[i].r_offset += frag->offset_adjust;
  3026. + }
  3027. +
  3028. + if (frag->refcount == 0)
  3029. + {
  3030. + /* If this frag is to be discarded, make sure we won't
  3031. + relocate it later on. */
  3032. + BFD_ASSERT(frag->state == RS_CPENT);
  3033. + frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
  3034. + R_AVR32_NONE);
  3035. + }
  3036. + else if (frag->state == RS_ALIGN)
  3037. + {
  3038. + bfd_vma addr, addr_end;
  3039. +
  3040. + addr = frag->rela->r_offset;
  3041. + addr_end = (frag->offset + frag->offset_adjust
  3042. + + frag->size + frag->size_adjust);
  3043. +
  3044. + /* If the section is executable, insert NOPs.
  3045. + Otherwise, insert zeroes. */
  3046. + if (sec->flags & SEC_CODE)
  3047. + {
  3048. + if (addr & 1)
  3049. + {
  3050. + bfd_put_8(abfd, 0, contents + addr);
  3051. + addr++;
  3052. + }
  3053. +
  3054. + BFD_ASSERT(!((addr_end - addr) & 1));
  3055. +
  3056. + while (addr < addr_end)
  3057. + {
  3058. + bfd_put_16(abfd, NOP_OPCODE, contents + addr);
  3059. + addr += 2;
  3060. + }
  3061. + }
  3062. + else
  3063. + memset(contents + addr, 0, addr_end - addr);
  3064. + }
  3065. + else if (state->opcode_mask)
  3066. + {
  3067. + bfd_vma insn;
  3068. +
  3069. + /* Update the opcode and the relocation type unless it's a
  3070. + "special" relax state (i.e. RS_NONE, RS_ALIGN or
  3071. + RS_CPENT.), in which case the opcode mask is zero. */
  3072. + insn = bfd_get_32(abfd, contents + frag->rela->r_offset);
  3073. + insn &= ~state->opcode_mask;
  3074. + insn |= state->opcode;
  3075. + RDBG(" 0x%lx: inserting insn %08lx\n",
  3076. + frag->rela->r_offset, insn);
  3077. + bfd_put_32(abfd, insn, contents + frag->rela->r_offset);
  3078. +
  3079. + frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
  3080. + state->r_type);
  3081. + }
  3082. +
  3083. + if ((frag + 1) == fragend)
  3084. + BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
  3085. + + frag->size_adjust) == sec->size);
  3086. + else
  3087. + BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
  3088. + + frag->size_adjust)
  3089. + == (frag[1].offset + frag[1].offset_adjust));
  3090. + }
  3091. + }
  3092. +
  3093. + /* Adjust reloc addends and DIFF32 differences */
  3094. + if (!adjust_relocs(abfd, sec, info))
  3095. + return FALSE;
  3096. +
  3097. + ret = TRUE;
  3098. +
  3099. + out:
  3100. + release_contents(sec, contents);
  3101. + release_internal_relocs(sec, relocs);
  3102. + return ret;
  3103. +}
  3104. +
  3105. +static bfd_boolean
  3106. +avr32_elf_relax_section(bfd *abfd, asection *sec,
  3107. + struct bfd_link_info *info, bfd_boolean *again)
  3108. +{
  3109. + struct elf_avr32_link_hash_table *htab;
  3110. + struct avr32_relax_data *rd;
  3111. +
  3112. + *again = FALSE;
  3113. + if (info->relocatable)
  3114. + return TRUE;
  3115. +
  3116. + htab = avr32_elf_hash_table(info);
  3117. + if ((!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
  3118. + && sec != htab->sgot)
  3119. + return TRUE;
  3120. +
  3121. + if (!htab->relocations_analyzed)
  3122. + {
  3123. + if (!analyze_relocations(info))
  3124. + return FALSE;
  3125. + htab->relocations_analyzed = TRUE;
  3126. + }
  3127. +
  3128. + rd = avr32_relax_data(sec);
  3129. +
  3130. + if (rd->iteration != htab->relax_iteration)
  3131. + {
  3132. + if (!htab->repeat_pass)
  3133. + htab->relax_pass++;
  3134. + htab->relax_iteration++;
  3135. + htab->repeat_pass = FALSE;
  3136. + }
  3137. +
  3138. + rd->iteration++;
  3139. +
  3140. + switch (htab->relax_pass)
  3141. + {
  3142. + case RELAX_PASS_SIZE_FRAGS:
  3143. + if (!avr32_size_frags(abfd, sec, info))
  3144. + return FALSE;
  3145. + *again = TRUE;
  3146. + break;
  3147. + case RELAX_PASS_MOVE_DATA:
  3148. + if (!avr32_move_data(abfd, sec, info))
  3149. + return FALSE;
  3150. + break;
  3151. + }
  3152. +
  3153. + return TRUE;
  3154. +}
  3155. +
  3156. +
  3157. +/* Relocation */
  3158. +
  3159. +static bfd_reloc_status_type
  3160. +avr32_check_reloc_value(asection *sec, Elf_Internal_Rela *rela,
  3161. + bfd_signed_vma relocation, reloc_howto_type *howto);
  3162. +static bfd_reloc_status_type
  3163. +avr32_final_link_relocate(reloc_howto_type *howto, bfd *input_bfd,
  3164. + asection *input_section, bfd_byte *contents,
  3165. + Elf_Internal_Rela *rel, bfd_vma value);
  3166. +static bfd_boolean
  3167. +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
  3168. + bfd *input_bfd, asection *input_section,
  3169. + bfd_byte *contents, Elf_Internal_Rela *relocs,
  3170. + Elf_Internal_Sym *local_syms,
  3171. + asection **local_sections);
  3172. +
  3173. +
  3174. +#define symbol_address(symbol) \
  3175. + symbol->value + symbol->section->output_section->vma \
  3176. + + symbol->section->output_offset
  3177. +
  3178. +#define avr32_elf_insert_field(size, field, abfd, reloc_entry, data) \
  3179. + do \
  3180. + { \
  3181. + unsigned long x; \
  3182. + x = bfd_get_##size (abfd, data + reloc_entry->address); \
  3183. + x &= ~reloc_entry->howto->dst_mask; \
  3184. + x |= field & reloc_entry->howto->dst_mask; \
  3185. + bfd_put_##size (abfd, (bfd_vma) x, data + reloc_entry->address); \
  3186. + } \
  3187. + while(0)
  3188. +
  3189. +static bfd_reloc_status_type
  3190. +avr32_check_reloc_value(asection *sec ATTRIBUTE_UNUSED,
  3191. + Elf_Internal_Rela *rela ATTRIBUTE_UNUSED,
  3192. + bfd_signed_vma relocation,
  3193. + reloc_howto_type *howto)
  3194. +{
  3195. + bfd_vma reloc_u;
  3196. +
  3197. + /* We take "complain_overflow_dont" to mean "don't complain on
  3198. + alignment either". This way, we don't have to special-case
  3199. + R_AVR32_HI16 */
  3200. + if (howto->complain_on_overflow == complain_overflow_dont)
  3201. + return bfd_reloc_ok;
  3202. +
  3203. + /* Check if the value is correctly aligned */
  3204. + if (relocation & ((1 << howto->rightshift) - 1))
  3205. + {
  3206. + RDBG("misaligned: %s<%s+%lx>: %s: 0x%lx (align %u)\n",
  3207. + sec->owner->filename, sec->name, rela->r_offset,
  3208. + howto->name, relocation, howto->rightshift);
  3209. + return bfd_reloc_overflow;
  3210. + }
  3211. +
  3212. + /* Now, get rid of the unnecessary bits */
  3213. + relocation >>= howto->rightshift;
  3214. + reloc_u = (bfd_vma)relocation;
  3215. +
  3216. + switch (howto->complain_on_overflow)
  3217. + {
  3218. + case complain_overflow_unsigned:
  3219. + case complain_overflow_bitfield:
  3220. + if (reloc_u > (unsigned long)((1 << howto->bitsize) - 1))
  3221. + {
  3222. + RDBG("unsigned overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
  3223. + sec->owner->filename, sec->name, rela->r_offset,
  3224. + howto->name, reloc_u, howto->bitsize);
  3225. + RDBG("reloc vma: 0x%lx\n",
  3226. + sec->output_section->vma + sec->output_offset + rela->r_offset);
  3227. +
  3228. + return bfd_reloc_overflow;
  3229. + }
  3230. + break;
  3231. + case complain_overflow_signed:
  3232. + if (relocation > (1 << (howto->bitsize - 1)) - 1)
  3233. + {
  3234. + RDBG("signed overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
  3235. + sec->owner->filename, sec->name, rela->r_offset,
  3236. + howto->name, reloc_u, howto->bitsize);
  3237. + RDBG("reloc vma: 0x%lx\n",
  3238. + sec->output_section->vma + sec->output_offset + rela->r_offset);
  3239. +
  3240. + return bfd_reloc_overflow;
  3241. + }
  3242. + if (relocation < -(1 << (howto->bitsize - 1)))
  3243. + {
  3244. + RDBG("signed overflow: %s<%s+%lx>: %s: -0x%lx (size %u)\n",
  3245. + sec->owner->filename, sec->name, rela->r_offset,
  3246. + howto->name, -relocation, howto->bitsize);
  3247. + RDBG("reloc vma: 0x%lx\n",
  3248. + sec->output_section->vma + sec->output_offset + rela->r_offset);
  3249. +
  3250. + return bfd_reloc_overflow;
  3251. + }
  3252. + break;
  3253. + default:
  3254. + abort();
  3255. + }
  3256. +
  3257. + return bfd_reloc_ok;
  3258. +}
  3259. +
  3260. +
  3261. +static bfd_reloc_status_type
  3262. +avr32_final_link_relocate(reloc_howto_type *howto,
  3263. + bfd *input_bfd,
  3264. + asection *input_section,
  3265. + bfd_byte *contents,
  3266. + Elf_Internal_Rela *rel,
  3267. + bfd_vma value)
  3268. +{
  3269. + bfd_vma field;
  3270. + bfd_vma relocation;
  3271. + bfd_reloc_status_type status;
  3272. + bfd_byte *p = contents + rel->r_offset;
  3273. + unsigned long x;
  3274. +
  3275. + pr_debug(" (6b) final link relocate\n");
  3276. +
  3277. + /* Sanity check the address */
  3278. + if (rel->r_offset > input_section->size)
  3279. + {
  3280. + (*_bfd_error_handler)
  3281. + ("%B: %A+0x%lx: offset out of range (section size: 0x%lx)",
  3282. + input_bfd, input_section, rel->r_offset, input_section->size);
  3283. + return bfd_reloc_outofrange;
  3284. + }
  3285. +
  3286. + relocation = value + rel->r_addend;
  3287. +
  3288. + if (howto->pc_relative)
  3289. + {
  3290. + bfd_vma addr;
  3291. +
  3292. + addr = input_section->output_section->vma
  3293. + + input_section->output_offset + rel->r_offset;
  3294. + addr &= ~0UL << howto->rightshift;
  3295. + relocation -= addr;
  3296. + }
  3297. +
  3298. + switch (ELF32_R_TYPE(rel->r_info))
  3299. + {
  3300. + case R_AVR32_16N_PCREL:
  3301. + /* sub reg, pc, . - (sym + addend) */
  3302. + relocation = -relocation;
  3303. + break;
  3304. + }
  3305. +
  3306. + status = avr32_check_reloc_value(input_section, rel, relocation, howto);
  3307. +
  3308. + relocation >>= howto->rightshift;
  3309. + if (howto->bitsize == 21)
  3310. + field = (relocation & 0xffff)
  3311. + | ((relocation & 0x10000) << 4)
  3312. + | ((relocation & 0x1e0000) << 8);
  3313. + else if (howto->bitsize == 12)
  3314. + field = (relocation & 0xff) | ((relocation & 0xf00) << 4);
  3315. + else if (howto->bitsize == 10)
  3316. + field = ((relocation & 0xff) << 4)
  3317. + | ((relocation & 0x300) >> 8);
  3318. + else
  3319. + field = relocation << howto->bitpos;
  3320. +
  3321. + switch (howto->size)
  3322. + {
  3323. + case 0:
  3324. + x = bfd_get_8 (input_bfd, p);
  3325. + x &= ~howto->dst_mask;
  3326. + x |= field & howto->dst_mask;
  3327. + bfd_put_8 (input_bfd, (bfd_vma) x, p);
  3328. + break;
  3329. + case 1:
  3330. + x = bfd_get_16 (input_bfd, p);
  3331. + x &= ~howto->dst_mask;
  3332. + x |= field & howto->dst_mask;
  3333. + bfd_put_16 (input_bfd, (bfd_vma) x, p);
  3334. + break;
  3335. + case 2:
  3336. + x = bfd_get_32 (input_bfd, p);
  3337. + x &= ~howto->dst_mask;
  3338. + x |= field & howto->dst_mask;
  3339. + bfd_put_32 (input_bfd, (bfd_vma) x, p);
  3340. + break;
  3341. + default:
  3342. + abort();
  3343. + }
  3344. +
  3345. + return status;
  3346. +}
  3347. +
  3348. +/* (6) Apply relocations to the normal (non-dynamic) sections */
  3349. +
  3350. +static bfd_boolean
  3351. +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
  3352. + bfd *input_bfd, asection *input_section,
  3353. + bfd_byte *contents, Elf_Internal_Rela *relocs,
  3354. + Elf_Internal_Sym *local_syms,
  3355. + asection **local_sections)
  3356. +{
  3357. + struct elf_avr32_link_hash_table *htab;
  3358. + Elf_Internal_Shdr *symtab_hdr;
  3359. + Elf_Internal_Rela *rel, *relend;
  3360. + struct elf_link_hash_entry **sym_hashes;
  3361. + struct got_entry **local_got_ents;
  3362. + asection *sgot;
  3363. + asection *srelgot;
  3364. +
  3365. + pr_debug("(6) relocate section %s:<%s> (size 0x%lx)\n",
  3366. + input_bfd->filename, input_section->name, input_section->size);
  3367. +
  3368. + /* If we're doing a partial link, we don't have to do anything since
  3369. + we're using RELA relocations */
  3370. + if (info->relocatable)
  3371. + return TRUE;
  3372. +
  3373. + htab = avr32_elf_hash_table(info);
  3374. + symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr;
  3375. + sym_hashes = elf_sym_hashes(input_bfd);
  3376. + local_got_ents = elf_local_got_ents(input_bfd);
  3377. + sgot = htab->sgot;
  3378. + srelgot = htab->srelgot;
  3379. +
  3380. + relend = relocs + input_section->reloc_count;
  3381. + for (rel = relocs; rel < relend; rel++)
  3382. + {
  3383. + unsigned long r_type, r_symndx;
  3384. + reloc_howto_type *howto;
  3385. + Elf_Internal_Sym *sym = NULL;
  3386. + struct elf_link_hash_entry *h = NULL;
  3387. + asection *sec = NULL;
  3388. + bfd_vma value;
  3389. + bfd_vma offset;
  3390. + bfd_reloc_status_type status;
  3391. +
  3392. + r_type = ELF32_R_TYPE(rel->r_info);
  3393. + r_symndx = ELF32_R_SYM(rel->r_info);
  3394. +
  3395. + if (r_type == R_AVR32_NONE
  3396. + || r_type == R_AVR32_ALIGN
  3397. + || r_type == R_AVR32_DIFF32
  3398. + || r_type == R_AVR32_DIFF16
  3399. + || r_type == R_AVR32_DIFF8)
  3400. + continue;
  3401. +
  3402. + /* Sanity check */
  3403. + if (r_type > R_AVR32_max)
  3404. + {
  3405. + bfd_set_error(bfd_error_bad_value);
  3406. + return FALSE;
  3407. + }
  3408. +
  3409. + howto = &elf_avr32_howto_table[r_type];
  3410. +
  3411. + if (r_symndx < symtab_hdr->sh_info)
  3412. + {
  3413. + sym = local_syms + r_symndx;
  3414. + sec = local_sections[r_symndx];
  3415. +
  3416. + pr_debug(" (6a) processing %s against local symbol %lu\n",
  3417. + howto->name, r_symndx);
  3418. +
  3419. + /* The following function changes rel->r_addend behind our back. */
  3420. + value = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel);
  3421. + pr_debug(" => value: %lx, addend: %lx\n", value, rel->r_addend);
  3422. + }
  3423. + else
  3424. + {
  3425. + if (sym_hashes == NULL)
  3426. + return FALSE;
  3427. +
  3428. + h = sym_hashes[r_symndx - symtab_hdr->sh_info];
  3429. + while (h->root.type == bfd_link_hash_indirect
  3430. + || h->root.type == bfd_link_hash_warning)
  3431. + h = (struct elf_link_hash_entry *)h->root.u.i.link;
  3432. +
  3433. + pr_debug(" (6a) processing %s against symbol %s\n",
  3434. + howto->name, h->root.root.string);
  3435. +
  3436. + if (h->root.type == bfd_link_hash_defined
  3437. + || h->root.type == bfd_link_hash_defweak)
  3438. + {
  3439. + bfd_boolean dyn;
  3440. +
  3441. + dyn = htab->root.dynamic_sections_created;
  3442. + sec = h->root.u.def.section;
  3443. +
  3444. + if (sec->output_section)
  3445. + value = (h->root.u.def.value
  3446. + + sec->output_section->vma
  3447. + + sec->output_offset);
  3448. + else
  3449. + value = h->root.u.def.value;
  3450. + }
  3451. + else if (h->root.type == bfd_link_hash_undefweak)
  3452. + value = 0;
  3453. + else if (info->unresolved_syms_in_objects == RM_IGNORE
  3454. + && ELF_ST_VISIBILITY(h->other) == STV_DEFAULT)
  3455. + value = 0;
  3456. + else
  3457. + {
  3458. + bfd_boolean err;
  3459. + err = (info->unresolved_syms_in_objects == RM_GENERATE_ERROR
  3460. + || ELF_ST_VISIBILITY(h->other) != STV_DEFAULT);
  3461. + if (!info->callbacks->undefined_symbol
  3462. + (info, h->root.root.string, input_bfd,
  3463. + input_section, rel->r_offset, err))
  3464. + return FALSE;
  3465. + value = 0;
  3466. + }
  3467. +
  3468. + pr_debug(" => value: %lx, addend: %lx\n", value, rel->r_addend);
  3469. + }
  3470. +
  3471. + switch (r_type)
  3472. + {
  3473. + case R_AVR32_GOT32:
  3474. + case R_AVR32_GOT16:
  3475. + case R_AVR32_GOT8:
  3476. + case R_AVR32_GOT21S:
  3477. + case R_AVR32_GOT18SW:
  3478. + case R_AVR32_GOT16S:
  3479. + case R_AVR32_GOT7UW:
  3480. + case R_AVR32_LDA_GOT:
  3481. + case R_AVR32_GOTCALL:
  3482. + BFD_ASSERT(sgot != NULL);
  3483. +
  3484. + if (h != NULL)
  3485. + {
  3486. + BFD_ASSERT(h->got.glist->refcount > 0);
  3487. + offset = h->got.glist->offset;
  3488. +
  3489. + BFD_ASSERT(offset < sgot->size);
  3490. + if (!elf_hash_table(info)->dynamic_sections_created
  3491. + || (h->def_regular
  3492. + && (!info->shared
  3493. + || info->symbolic
  3494. + || h->dynindx == -1)))
  3495. + {
  3496. + /* This is actually a static link, or it is a
  3497. + -Bsymbolic link and the symbol is defined
  3498. + locally, or the symbol was forced to be local. */
  3499. + bfd_put_32(output_bfd, value, sgot->contents + offset);
  3500. + }
  3501. + }
  3502. + else
  3503. + {
  3504. + BFD_ASSERT(local_got_ents &&
  3505. + local_got_ents[r_symndx]->refcount > 0);
  3506. + offset = local_got_ents[r_symndx]->offset;
  3507. +
  3508. + /* Local GOT entries don't have relocs. If this is a
  3509. + shared library, the dynamic linker will add the load
  3510. + address to the initial value at startup. */
  3511. + BFD_ASSERT(offset < sgot->size);
  3512. + pr_debug("Initializing GOT entry at offset %lu: 0x%lx\n",
  3513. + offset, value);
  3514. + bfd_put_32 (output_bfd, value, sgot->contents + offset);
  3515. + }
  3516. +
  3517. + value = sgot->output_offset + offset;
  3518. + pr_debug("GOT reference: New value %lx\n", value);
  3519. + break;
  3520. +
  3521. + case R_AVR32_GOTPC:
  3522. + /* This relocation type is for constant pool entries used in
  3523. + the calculation "Rd = PC - (PC - GOT)", where the
  3524. + constant pool supplies the constant (PC - GOT)
  3525. + offset. The symbol value + addend indicates where the
  3526. + value of PC is taken. */
  3527. + value -= sgot->output_section->vma;
  3528. + break;
  3529. +
  3530. + case R_AVR32_32_PCREL:
  3531. + /* We must adjust r_offset to account for discarded data in
  3532. + the .eh_frame section. This is probably not the right
  3533. + way to do this, since AFAICS all other architectures do
  3534. + it some other way. I just can't figure out how... */
  3535. + {
  3536. + bfd_vma r_offset;
  3537. +
  3538. + r_offset = _bfd_elf_section_offset(output_bfd, info,
  3539. + input_section,
  3540. + rel->r_offset);
  3541. + if (r_offset == (bfd_vma)-1
  3542. + || r_offset == (bfd_vma)-2)
  3543. + continue;
  3544. + rel->r_offset = r_offset;
  3545. + }
  3546. + break;
  3547. +
  3548. + case R_AVR32_32:
  3549. + /* We need to emit a run-time relocation in the following cases:
  3550. + - we're creating a shared library
  3551. + - the symbol is not defined in any regular objects
  3552. +
  3553. + Of course, sections that aren't going to be part of the
  3554. + run-time image will not get any relocs, and undefined
  3555. + symbols won't have any either (only weak undefined
  3556. + symbols should get this far). */
  3557. + if ((info->shared
  3558. + || (elf_hash_table(info)->dynamic_sections_created
  3559. + && h != NULL
  3560. + && h->def_dynamic
  3561. + && !h->def_regular))
  3562. + && r_symndx != 0
  3563. + && (input_section->flags & SEC_ALLOC))
  3564. + {
  3565. + Elf_Internal_Rela outrel;
  3566. + bfd_byte *loc;
  3567. + bfd_boolean skip, relocate;
  3568. + struct elf_avr32_link_hash_entry *avrh;
  3569. +
  3570. + pr_debug("Going to generate dynamic reloc...\n");
  3571. +
  3572. + skip = FALSE;
  3573. + relocate = FALSE;
  3574. +
  3575. + outrel.r_offset = _bfd_elf_section_offset(output_bfd, info,
  3576. + input_section,
  3577. + rel->r_offset);
  3578. + if (outrel.r_offset == (bfd_vma)-1)
  3579. + skip = TRUE;
  3580. + else if (outrel.r_offset == (bfd_vma)-2)
  3581. + skip = TRUE, relocate = TRUE;
  3582. +
  3583. + outrel.r_offset += (input_section->output_section->vma
  3584. + + input_section->output_offset);
  3585. +
  3586. + pr_debug(" ... offset %lx, dynindx %ld\n",
  3587. + outrel.r_offset, h ? h->dynindx : -1);
  3588. +
  3589. + if (skip)
  3590. + memset(&outrel, 0, sizeof(outrel));
  3591. + else
  3592. + {
  3593. + avrh = (struct elf_avr32_link_hash_entry *)h;
  3594. + /* h->dynindx may be -1 if this symbol was marked to
  3595. + become local. */
  3596. + if (h == NULL
  3597. + || ((info->symbolic || h->dynindx == -1)
  3598. + && h->def_regular))
  3599. + {
  3600. + relocate = TRUE;
  3601. + outrel.r_info = ELF32_R_INFO(0, R_AVR32_RELATIVE);
  3602. + outrel.r_addend = value + rel->r_addend;
  3603. + pr_debug(" ... R_AVR32_RELATIVE\n");
  3604. + }
  3605. + else
  3606. + {
  3607. + BFD_ASSERT(h->dynindx != -1);
  3608. + relocate = TRUE;
  3609. + outrel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
  3610. + outrel.r_addend = rel->r_addend;
  3611. + pr_debug(" ... R_AVR32_GLOB_DAT\n");
  3612. + }
  3613. + }
  3614. +
  3615. + pr_debug("srelgot reloc_count: %d, size %lu\n",
  3616. + srelgot->reloc_count, srelgot->size);
  3617. +
  3618. + loc = srelgot->contents;
  3619. + loc += srelgot->reloc_count++ * sizeof(Elf32_External_Rela);
  3620. + bfd_elf32_swap_reloca_out(output_bfd, &outrel, loc);
  3621. +
  3622. + BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
  3623. + <= srelgot->size);
  3624. +
  3625. + if (!relocate)
  3626. + continue;
  3627. + }
  3628. + break;
  3629. + }
  3630. +
  3631. + status = avr32_final_link_relocate(howto, input_bfd, input_section,
  3632. + contents, rel, value);
  3633. +
  3634. + switch (status)
  3635. + {
  3636. + case bfd_reloc_ok:
  3637. + break;
  3638. +
  3639. + case bfd_reloc_overflow:
  3640. + {
  3641. + const char *name;
  3642. +
  3643. + if (h != NULL)
  3644. + name = h->root.root.string;
  3645. + else
  3646. + {
  3647. + name = bfd_elf_string_from_elf_section(input_bfd,
  3648. + symtab_hdr->sh_link,
  3649. + sym->st_name);
  3650. + if (name == NULL)
  3651. + return FALSE;
  3652. + if (*name == '\0')
  3653. + name = bfd_section_name(input_bfd, sec);
  3654. + }
  3655. + if (!((*info->callbacks->reloc_overflow)
  3656. + (info, (h ? &h->root : NULL), name, howto->name,
  3657. + rel->r_addend, input_bfd, input_section, rel->r_offset)))
  3658. + return FALSE;
  3659. + }
  3660. + break;
  3661. +
  3662. + case bfd_reloc_outofrange:
  3663. + default:
  3664. + abort();
  3665. + }
  3666. + }
  3667. +
  3668. + return TRUE;
  3669. +}
  3670. +
  3671. +
  3672. +/* Additional processing of dynamic sections after relocation */
  3673. +
  3674. +static bfd_boolean
  3675. +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
  3676. + struct elf_link_hash_entry *h,
  3677. + Elf_Internal_Sym *sym);
  3678. +static bfd_boolean
  3679. +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info);
  3680. +
  3681. +
  3682. +/* (7) Initialize the contents of a dynamic symbol and/or emit
  3683. + relocations for it */
  3684. +
  3685. +static bfd_boolean
  3686. +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
  3687. + struct elf_link_hash_entry *h,
  3688. + Elf_Internal_Sym *sym)
  3689. +{
  3690. + struct elf_avr32_link_hash_table *htab;
  3691. + struct got_entry *got;
  3692. +
  3693. + pr_debug("(7) finish dynamic symbol: %s\n", h->root.root.string);
  3694. +
  3695. + htab = avr32_elf_hash_table(info);
  3696. + got = h->got.glist;
  3697. +
  3698. + if (got && got->refcount > 0)
  3699. + {
  3700. + asection *sgot;
  3701. + asection *srelgot;
  3702. + Elf_Internal_Rela rel;
  3703. + bfd_byte *loc;
  3704. +
  3705. + /* This symbol has an entry in the GOT. Set it up. */
  3706. + sgot = htab->sgot;
  3707. + srelgot = htab->srelgot;
  3708. + BFD_ASSERT(sgot && srelgot);
  3709. +
  3710. + rel.r_offset = (sgot->output_section->vma
  3711. + + sgot->output_offset
  3712. + + got->offset);
  3713. +
  3714. + /* If this is a static link, or it is a -Bsymbolic link and the
  3715. + symbol is defined locally or was forced to be local because
  3716. + of a version file, we just want to emit a RELATIVE reloc. The
  3717. + entry in the global offset table will already have been
  3718. + initialized in the relocate_section function. */
  3719. + if ((info->shared
  3720. + && !info->symbolic
  3721. + && h->dynindx != -1)
  3722. + || (htab->root.dynamic_sections_created
  3723. + && h->def_dynamic
  3724. + && !h->def_regular))
  3725. + {
  3726. + bfd_put_32(output_bfd, 0, sgot->contents + got->offset);
  3727. + rel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
  3728. + rel.r_addend = 0;
  3729. +
  3730. + pr_debug("GOT reloc R_AVR32_GLOB_DAT, dynindx: %ld\n", h->dynindx);
  3731. + pr_debug(" srelgot reloc_count: %d, size: %lu\n",
  3732. + srelgot->reloc_count, srelgot->size);
  3733. +
  3734. + loc = (srelgot->contents
  3735. + + srelgot->reloc_count++ * sizeof(Elf32_External_Rela));
  3736. + bfd_elf32_swap_reloca_out(output_bfd, &rel, loc);
  3737. +
  3738. + BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
  3739. + <= srelgot->size);
  3740. + }
  3741. + }
  3742. +
  3743. + /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute */
  3744. + if (strcmp(h->root.root.string, "_DYNAMIC") == 0
  3745. + || strcmp(h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
  3746. + sym->st_shndx = SHN_ABS;
  3747. +
  3748. + return TRUE;
  3749. +}
  3750. +
  3751. +/* (8) Do any remaining initialization of the dynamic sections */
  3752. +
  3753. +static bfd_boolean
  3754. +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info)
  3755. +{
  3756. + struct elf_avr32_link_hash_table *htab;
  3757. + asection *sgot, *sdyn;
  3758. +
  3759. + pr_debug("(8) finish dynamic sections\n");
  3760. +
  3761. + htab = avr32_elf_hash_table(info);
  3762. + sgot = htab->sgot;
  3763. + sdyn = bfd_get_section_by_name(htab->root.dynobj, ".dynamic");
  3764. +
  3765. + if (htab->root.dynamic_sections_created)
  3766. + {
  3767. + Elf32_External_Dyn *dyncon, *dynconend;
  3768. +
  3769. + BFD_ASSERT(sdyn && sgot && sgot->size >= AVR32_GOT_HEADER_SIZE);
  3770. +
  3771. + dyncon = (Elf32_External_Dyn *)sdyn->contents;
  3772. + dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size);
  3773. + for (; dyncon < dynconend; dyncon++)
  3774. + {
  3775. + Elf_Internal_Dyn dyn;
  3776. + asection *s;
  3777. +
  3778. + bfd_elf32_swap_dyn_in(htab->root.dynobj, dyncon, &dyn);
  3779. +
  3780. + switch (dyn.d_tag)
  3781. + {
  3782. + default:
  3783. + break;
  3784. +
  3785. + case DT_PLTGOT:
  3786. + s = sgot->output_section;
  3787. + BFD_ASSERT(s != NULL);
  3788. + dyn.d_un.d_ptr = s->vma;
  3789. + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
  3790. + break;
  3791. +
  3792. + case DT_AVR32_GOTSZ:
  3793. + s = sgot->output_section;
  3794. + BFD_ASSERT(s != NULL);
  3795. + dyn.d_un.d_val = s->size;
  3796. + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
  3797. + break;
  3798. + }
  3799. + }
  3800. +
  3801. + /* Fill in the first two entries in the global offset table */
  3802. + bfd_put_32(output_bfd,
  3803. + sdyn->output_section->vma + sdyn->output_offset,
  3804. + sgot->contents);
  3805. +
  3806. + /* The runtime linker will fill this one in with the address of
  3807. + the run-time link map */
  3808. + bfd_put_32(output_bfd, 0, sgot->contents + 4);
  3809. + }
  3810. +
  3811. + if (sgot)
  3812. + elf_section_data(sgot->output_section)->this_hdr.sh_entsize = 4;
  3813. +
  3814. + return TRUE;
  3815. +}
  3816. +
  3817. +
  3818. +/* AVR32-specific private ELF data */
  3819. +
  3820. +static bfd_boolean
  3821. +avr32_elf_set_private_flags(bfd *abfd, flagword flags);
  3822. +static bfd_boolean
  3823. +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd);
  3824. +static bfd_boolean
  3825. +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd);
  3826. +static bfd_boolean
  3827. +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr);
  3828. +
  3829. +static bfd_boolean
  3830. +avr32_elf_set_private_flags(bfd *abfd, flagword flags)
  3831. +{
  3832. + elf_elfheader(abfd)->e_flags = flags;
  3833. + elf_flags_init(abfd) = TRUE;
  3834. +
  3835. + return TRUE;
  3836. +}
  3837. +
  3838. +/* Copy backend specific data from one object module to another. */
  3839. +
  3840. +static bfd_boolean
  3841. +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd)
  3842. +{
  3843. + elf_elfheader(obfd)->e_flags = elf_elfheader(ibfd)->e_flags;
  3844. + return TRUE;
  3845. +}
  3846. +
  3847. +/* Merge backend specific data from an object file to the output
  3848. + object file when linking. */
  3849. +
  3850. +static bfd_boolean
  3851. +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd)
  3852. +{
  3853. + flagword out_flags, in_flags;
  3854. +
  3855. + pr_debug("(0) merge_private_bfd_data: %s -> %s\n",
  3856. + ibfd->filename, obfd->filename);
  3857. +
  3858. + in_flags = elf_elfheader(ibfd)->e_flags;
  3859. + out_flags = elf_elfheader(obfd)->e_flags;
  3860. +
  3861. + if (elf_flags_init(obfd))
  3862. + {
  3863. + /* If one of the inputs are non-PIC, the output must be
  3864. + considered non-PIC. The same applies to linkrelax. */
  3865. + if (!(in_flags & EF_AVR32_PIC))
  3866. + out_flags &= ~EF_AVR32_PIC;
  3867. + if (!(in_flags & EF_AVR32_LINKRELAX))
  3868. + out_flags &= ~EF_AVR32_LINKRELAX;
  3869. + }
  3870. + else
  3871. + {
  3872. + elf_flags_init(obfd) = TRUE;
  3873. + out_flags = in_flags;
  3874. + }
  3875. +
  3876. + elf_elfheader(obfd)->e_flags = out_flags;
  3877. +
  3878. + return TRUE;
  3879. +}
  3880. +
  3881. +static bfd_boolean
  3882. +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr)
  3883. +{
  3884. + FILE *file = (FILE *)ptr;
  3885. + unsigned long flags;
  3886. +
  3887. + BFD_ASSERT(abfd != NULL && ptr != NULL);
  3888. +
  3889. + _bfd_elf_print_private_bfd_data(abfd, ptr);
  3890. +
  3891. + flags = elf_elfheader(abfd)->e_flags;
  3892. +
  3893. + fprintf(file, _("private flags = %lx:"), elf_elfheader(abfd)->e_flags);
  3894. +
  3895. + if (flags & EF_AVR32_PIC)
  3896. + fprintf(file, " [PIC]");
  3897. + if (flags & EF_AVR32_LINKRELAX)
  3898. + fprintf(file, " [linker relaxable]");
  3899. +
  3900. + flags &= ~(EF_AVR32_PIC | EF_AVR32_LINKRELAX);
  3901. +
  3902. + if (flags)
  3903. + fprintf(file, _("<Unrecognized flag bits set>"));
  3904. +
  3905. + fputc('\n', file);
  3906. +
  3907. + return TRUE;
  3908. +}
  3909. +
  3910. +/* Set avr32-specific linker options. */
  3911. +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
  3912. + int direct_data_refs)
  3913. +{
  3914. + struct elf_avr32_link_hash_table *htab;
  3915. +
  3916. + htab = avr32_elf_hash_table (info);
  3917. + htab->direct_data_refs = !!direct_data_refs;
  3918. +}
  3919. +
  3920. +
  3921. +
  3922. +/* Understanding core dumps */
  3923. +
  3924. +static bfd_boolean
  3925. +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note);
  3926. +static bfd_boolean
  3927. +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note);
  3928. +
  3929. +static bfd_boolean
  3930. +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note)
  3931. +{
  3932. + /* Linux/AVR32B elf_prstatus */
  3933. + if (note->descsz != 148)
  3934. + return FALSE;
  3935. +
  3936. + /* pr_cursig */
  3937. + elf_tdata(abfd)->core_signal = bfd_get_16(abfd, note->descdata + 12);
  3938. +
  3939. + /* pr_pid */
  3940. + elf_tdata(abfd)->core_pid = bfd_get_32(abfd, note->descdata + 24);
  3941. +
  3942. + /* Make a ".reg/999" section for pr_reg. The size is for 16
  3943. + general-purpose registers, SR and r12_orig (18 * 4 = 72). */
  3944. + return _bfd_elfcore_make_pseudosection(abfd, ".reg", 72,
  3945. + note->descpos + 72);
  3946. +}
  3947. +
  3948. +static bfd_boolean
  3949. +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note)
  3950. +{
  3951. + /* Linux/AVR32B elf_prpsinfo */
  3952. + if (note->descsz != 128)
  3953. + return FALSE;
  3954. +
  3955. + elf_tdata(abfd)->core_program
  3956. + = _bfd_elfcore_strndup(abfd, note->descdata + 32, 16);
  3957. + elf_tdata(abfd)->core_command
  3958. + = _bfd_elfcore_strndup(abfd, note->descdata + 48, 80);
  3959. +
  3960. + /* Note that for some reason, a spurious space is tacked
  3961. + onto the end of the args in some (at least one anyway)
  3962. + implementations, so strip it off if it exists. */
  3963. +
  3964. + {
  3965. + char *command = elf_tdata (abfd)->core_command;
  3966. + int n = strlen (command);
  3967. +
  3968. + if (0 < n && command[n - 1] == ' ')
  3969. + command[n - 1] = '\0';
  3970. + }
  3971. +
  3972. + return TRUE;
  3973. +}
  3974. +
  3975. +
  3976. +#define ELF_ARCH bfd_arch_avr32
  3977. +#define ELF_MACHINE_CODE EM_AVR32
  3978. +#define ELF_MAXPAGESIZE 1024
  3979. +
  3980. +#define TARGET_BIG_SYM bfd_elf32_avr32_vec
  3981. +#define TARGET_BIG_NAME "elf32-avr32"
  3982. +
  3983. +#define elf_backend_grok_prstatus avr32_elf_grok_prstatus
  3984. +#define elf_backend_grok_psinfo avr32_elf_grok_psinfo
  3985. +
  3986. +/* Only RELA relocations are used */
  3987. +#define elf_backend_may_use_rel_p 0
  3988. +#define elf_backend_may_use_rela_p 1
  3989. +#define elf_backend_default_use_rela_p 1
  3990. +#define elf_backend_rela_normal 1
  3991. +#define elf_info_to_howto_rel NULL
  3992. +#define elf_info_to_howto avr32_info_to_howto
  3993. +
  3994. +#define bfd_elf32_bfd_copy_private_bfd_data avr32_elf_copy_private_bfd_data
  3995. +#define bfd_elf32_bfd_merge_private_bfd_data avr32_elf_merge_private_bfd_data
  3996. +#define bfd_elf32_bfd_set_private_flags avr32_elf_set_private_flags
  3997. +#define bfd_elf32_bfd_print_private_bfd_data avr32_elf_print_private_bfd_data
  3998. +#define bfd_elf32_new_section_hook avr32_elf_new_section_hook
  3999. +
  4000. +#define elf_backend_gc_mark_hook avr32_elf_gc_mark_hook
  4001. +#define elf_backend_gc_sweep_hook avr32_elf_gc_sweep_hook
  4002. +#define elf_backend_relocate_section avr32_elf_relocate_section
  4003. +#define elf_backend_copy_indirect_symbol avr32_elf_copy_indirect_symbol
  4004. +#define elf_backend_create_dynamic_sections avr32_elf_create_dynamic_sections
  4005. +#define bfd_elf32_bfd_link_hash_table_create avr32_elf_link_hash_table_create
  4006. +#define elf_backend_adjust_dynamic_symbol avr32_elf_adjust_dynamic_symbol
  4007. +#define elf_backend_size_dynamic_sections avr32_elf_size_dynamic_sections
  4008. +#define elf_backend_finish_dynamic_symbol avr32_elf_finish_dynamic_symbol
  4009. +#define elf_backend_finish_dynamic_sections avr32_elf_finish_dynamic_sections
  4010. +
  4011. +#define bfd_elf32_bfd_relax_section avr32_elf_relax_section
  4012. +
  4013. +/* Find out which symbols need an entry in .got. */
  4014. +#define elf_backend_check_relocs avr32_check_relocs
  4015. +#define elf_backend_can_refcount 1
  4016. +#define elf_backend_can_gc_sections 1
  4017. +#define elf_backend_plt_readonly 1
  4018. +#define elf_backend_plt_not_loaded 1
  4019. +#define elf_backend_want_plt_sym 0
  4020. +#define elf_backend_plt_alignment 2
  4021. +#define elf_backend_want_dynbss 0
  4022. +#define elf_backend_want_got_plt 0
  4023. +#define elf_backend_want_got_sym 1
  4024. +#define elf_backend_got_header_size AVR32_GOT_HEADER_SIZE
  4025. +
  4026. +#include "elf32-target.h"
  4027. --- /dev/null
  4028. +++ b/bfd/elf32-avr32.h
  4029. @@ -0,0 +1,23 @@
  4030. +/* AVR32-specific support for 32-bit ELF.
  4031. + Copyright 2007,2008,2009 Atmel Corporation.
  4032. +
  4033. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  4034. +
  4035. + This file is part of BFD, the Binary File Descriptor library.
  4036. +
  4037. + This program is free software; you can redistribute it and/or modify
  4038. + it under the terms of the GNU General Public License as published by
  4039. + the Free Software Foundation; either version 2 of the License, or
  4040. + (at your option) any later version.
  4041. +
  4042. + This program is distributed in the hope that it will be useful,
  4043. + but WITHOUT ANY WARRANTY; without even the implied warranty of
  4044. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  4045. + GNU General Public License for more details.
  4046. +
  4047. + You should have received a copy of the GNU General Public License
  4048. + along with this program; if not, write to the Free Software
  4049. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  4050. +
  4051. +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
  4052. + int direct_data_refs);
  4053. --- a/bfd/elf-bfd.h
  4054. +++ b/bfd/elf-bfd.h
  4055. @@ -1503,6 +1503,10 @@ struct elf_obj_tdata
  4056. find_nearest_line. */
  4057. struct mips_elf_find_line *find_line_info;
  4058. + /* Used by AVR32 ELF relaxation code. Contains an array of pointers
  4059. + for each local symbol to the fragment where it is defined. */
  4060. + struct fragment **local_sym_frag;
  4061. +
  4062. /* A place to stash dwarf1 info for this bfd. */
  4063. struct dwarf1_debug *dwarf1_find_line_info;
  4064. --- a/bfd/Makefile.am
  4065. +++ b/bfd/Makefile.am
  4066. @@ -73,6 +73,7 @@ ALL_MACHINES = \
  4067. cpu-arc.lo \
  4068. cpu-arm.lo \
  4069. cpu-avr.lo \
  4070. + cpu-avr32.lo \
  4071. cpu-bfin.lo \
  4072. cpu-cr16.lo \
  4073. cpu-cr16c.lo \
  4074. @@ -269,6 +270,7 @@ BFD32_BACKENDS = \
  4075. elf32-arc.lo \
  4076. elf32-arm.lo \
  4077. elf32-avr.lo \
  4078. + elf32-avr32.lo \
  4079. elf32-bfin.lo \
  4080. elf32-cr16.lo \
  4081. elf32-cr16c.lo \
  4082. --- a/bfd/reloc.c
  4083. +++ b/bfd/reloc.c
  4084. @@ -4052,6 +4052,131 @@ ENUMDOC
  4085. instructions
  4086. ENUM
  4087. + BFD_RELOC_AVR32_DIFF32
  4088. +ENUMX
  4089. + BFD_RELOC_AVR32_DIFF16
  4090. +ENUMX
  4091. + BFD_RELOC_AVR32_DIFF8
  4092. +ENUMDOC
  4093. + Difference between two labels: L2 - L1. The value of L1 is encoded
  4094. + as sym + addend, while the initial difference after assembly is
  4095. + inserted into the object file by the assembler.
  4096. +ENUM
  4097. + BFD_RELOC_AVR32_GOT32
  4098. +ENUMX
  4099. + BFD_RELOC_AVR32_GOT16
  4100. +ENUMX
  4101. + BFD_RELOC_AVR32_GOT8
  4102. +ENUMDOC
  4103. + Reference to a symbol through the Global Offset Table. The linker
  4104. + will allocate an entry for symbol in the GOT and insert the offset
  4105. + of this entry as the relocation value.
  4106. +ENUM
  4107. + BFD_RELOC_AVR32_21S
  4108. +ENUMX
  4109. + BFD_RELOC_AVR32_16U
  4110. +ENUMX
  4111. + BFD_RELOC_AVR32_16S
  4112. +ENUMX
  4113. + BFD_RELOC_AVR32_SUB5
  4114. +ENUMX
  4115. + BFD_RELOC_AVR32_8S_EXT
  4116. +ENUMX
  4117. + BFD_RELOC_AVR32_8S
  4118. +ENUMX
  4119. + BFD_RELOC_AVR32_15S
  4120. +ENUMDOC
  4121. + Normal (non-pc-relative) code relocations. Alignment and signedness
  4122. + is indicated by the suffixes. S means signed, U means unsigned. W
  4123. + means word-aligned, H means halfword-aligned, neither means
  4124. + byte-aligned (no alignment.) SUB5 is the same relocation as 16S.
  4125. +ENUM
  4126. + BFD_RELOC_AVR32_22H_PCREL
  4127. +ENUMX
  4128. + BFD_RELOC_AVR32_18W_PCREL
  4129. +ENUMX
  4130. + BFD_RELOC_AVR32_16B_PCREL
  4131. +ENUMX
  4132. + BFD_RELOC_AVR32_16N_PCREL
  4133. +ENUMX
  4134. + BFD_RELOC_AVR32_14UW_PCREL
  4135. +ENUMX
  4136. + BFD_RELOC_AVR32_11H_PCREL
  4137. +ENUMX
  4138. + BFD_RELOC_AVR32_10UW_PCREL
  4139. +ENUMX
  4140. + BFD_RELOC_AVR32_9H_PCREL
  4141. +ENUMX
  4142. + BFD_RELOC_AVR32_9UW_PCREL
  4143. +ENUMDOC
  4144. + PC-relative relocations are signed if neither 'U' nor 'S' is
  4145. + specified. However, we explicitly tack on a 'B' to indicate no
  4146. + alignment, to avoid confusion with data relocs. All of these resolve
  4147. + to sym + addend - offset, except the one with 'N' (negated) suffix.
  4148. + This particular one resolves to offset - sym - addend.
  4149. +ENUM
  4150. + BFD_RELOC_AVR32_GOTPC
  4151. +ENUMDOC
  4152. + Subtract the link-time address of the GOT from (symbol + addend)
  4153. + and insert the result.
  4154. +ENUM
  4155. + BFD_RELOC_AVR32_GOTCALL
  4156. +ENUMX
  4157. + BFD_RELOC_AVR32_LDA_GOT
  4158. +ENUMX
  4159. + BFD_RELOC_AVR32_GOT21S
  4160. +ENUMX
  4161. + BFD_RELOC_AVR32_GOT18SW
  4162. +ENUMX
  4163. + BFD_RELOC_AVR32_GOT16S
  4164. +ENUMDOC
  4165. + Reference to a symbol through the GOT. The linker will allocate an
  4166. + entry for symbol in the GOT and insert the offset of this entry as
  4167. + the relocation value. addend must be zero. As usual, 'S' means
  4168. + signed, 'W' means word-aligned, etc.
  4169. +ENUM
  4170. + BFD_RELOC_AVR32_32_CPENT
  4171. +ENUMDOC
  4172. + 32-bit constant pool entry. I don't think 8- and 16-bit entries make
  4173. + a whole lot of sense.
  4174. +ENUM
  4175. + BFD_RELOC_AVR32_CPCALL
  4176. +ENUMX
  4177. + BFD_RELOC_AVR32_16_CP
  4178. +ENUMX
  4179. + BFD_RELOC_AVR32_9W_CP
  4180. +ENUMDOC
  4181. + Constant pool references. Some of these relocations are signed,
  4182. + others are unsigned. It doesn't really matter, since the constant
  4183. + pool always comes after the code that references it.
  4184. +ENUM
  4185. + BFD_RELOC_AVR32_ALIGN
  4186. +ENUMDOC
  4187. + sym must be the absolute symbol. The addend specifies the alignment
  4188. + order, e.g. if addend is 2, the linker must add padding so that the
  4189. + next address is aligned to a 4-byte boundary.
  4190. +ENUM
  4191. + BFD_RELOC_AVR32_14UW
  4192. +ENUMX
  4193. + BFD_RELOC_AVR32_10UW
  4194. +ENUMX
  4195. + BFD_RELOC_AVR32_10SW
  4196. +ENUMX
  4197. + BFD_RELOC_AVR32_STHH_W
  4198. +ENUMX
  4199. + BFD_RELOC_AVR32_7UW
  4200. +ENUMX
  4201. + BFD_RELOC_AVR32_6S
  4202. +ENUMX
  4203. + BFD_RELOC_AVR32_6UW
  4204. +ENUMX
  4205. + BFD_RELOC_AVR32_4UH
  4206. +ENUMX
  4207. + BFD_RELOC_AVR32_3U
  4208. +ENUMDOC
  4209. + Code relocations that will never make it to the output file.
  4210. +
  4211. +ENUM
  4212. BFD_RELOC_390_12
  4213. ENUMDOC
  4214. Direct 12 bit.
  4215. --- a/bfd/targets.c
  4216. +++ b/bfd/targets.c
  4217. @@ -568,6 +568,7 @@ extern const bfd_target b_out_vec_big_ho
  4218. extern const bfd_target b_out_vec_little_host;
  4219. extern const bfd_target bfd_pei_ia64_vec;
  4220. extern const bfd_target bfd_elf32_avr_vec;
  4221. +extern const bfd_target bfd_elf32_avr32_vec;
  4222. extern const bfd_target bfd_elf32_bfin_vec;
  4223. extern const bfd_target bfd_elf32_bfinfdpic_vec;
  4224. extern const bfd_target bfd_elf32_big_generic_vec;
  4225. @@ -896,6 +897,7 @@ static const bfd_target * const _bfd_tar
  4226. &bfd_pei_ia64_vec,
  4227. #endif
  4228. &bfd_elf32_avr_vec,
  4229. + &bfd_elf32_avr32_vec,
  4230. &bfd_elf32_bfin_vec,
  4231. &bfd_elf32_bfinfdpic_vec,
  4232. --- a/binutils/doc/binutils.info
  4233. +++ b/binutils/doc/binutils.info
  4234. @@ -1665,6 +1665,10 @@ equivalent. At least one option from th
  4235. useful when attempting to disassemble thumb code produced by other
  4236. compilers.
  4237. + For the AVR32 architectures that support Floating point unit (FPU),
  4238. + specifying '-M decode-fpu' will enable disassembler to print the
  4239. + floating point instruction instead of 'cop' instructions.
  4240. +
  4241. For the x86, some of the options duplicate functions of the `-m'
  4242. switch, but allow finer grained control. Multiple selections from
  4243. the following may be specified as a comma separated string.
  4244. --- a/binutils/doc/binutils.texi
  4245. +++ b/binutils/doc/binutils.texi
  4246. @@ -1935,6 +1935,10 @@ using the switch @option{--disassembler-
  4247. useful when attempting to disassemble thumb code produced by other
  4248. compilers.
  4249. +For the AVR32 architectures that support Floating point unit (FPU),
  4250. +specifying @option{-M decode-fpu} will enable disassembler to print the
  4251. +floating point instructions instead of 'cop' instructions.
  4252. +
  4253. For the x86, some of the options duplicate functions of the @option{-m}
  4254. switch, but allow finer grained control. Multiple selections from the
  4255. following may be specified as a comma separated string.
  4256. --- a/binutils/doc/objdump.1
  4257. +++ b/binutils/doc/objdump.1
  4258. @@ -425,6 +425,10 @@ using the switch \fB\-\-disassembler\-op
  4259. useful when attempting to disassemble thumb code produced by other
  4260. compilers.
  4261. .Sp
  4262. +For the \s-1AVR32\s0 architectures that support Floating point unit (FPU),
  4263. +specifying \fB\-M decode\-fpu\fR will enable disassembler to print the
  4264. +floating point instructions instead of 'cop' instructions.
  4265. +.Sp
  4266. For the x86, some of the options duplicate functions of the \fB\-m\fR
  4267. switch, but allow finer grained control. Multiple selections from the
  4268. following may be specified as a comma separated string.
  4269. --- a/binutils/readelf.c
  4270. +++ b/binutils/readelf.c
  4271. @@ -94,6 +94,7 @@
  4272. #include "elf/arc.h"
  4273. #include "elf/arm.h"
  4274. #include "elf/avr.h"
  4275. +#include "elf/avr32.h"
  4276. #include "elf/bfin.h"
  4277. #include "elf/cr16.h"
  4278. #include "elf/cris.h"
  4279. @@ -570,6 +571,7 @@ guess_is_rela (unsigned int e_machine)
  4280. case EM_ALPHA:
  4281. case EM_ALTERA_NIOS2:
  4282. case EM_AVR:
  4283. + case EM_AVR32:
  4284. case EM_AVR_OLD:
  4285. case EM_BLACKFIN:
  4286. case EM_CR16:
  4287. @@ -1020,6 +1022,10 @@ dump_relocations (FILE * file,
  4288. rtype = elf_avr_reloc_type (type);
  4289. break;
  4290. + case EM_AVR32:
  4291. + rtype = elf_avr32_reloc_type (type);
  4292. + break;
  4293. +
  4294. case EM_OLD_SPARCV9:
  4295. case EM_SPARC32PLUS:
  4296. case EM_SPARCV9:
  4297. @@ -1853,6 +1859,7 @@ get_machine_name (unsigned e_machine)
  4298. case EM_VAX: return "Digital VAX";
  4299. case EM_AVR_OLD:
  4300. case EM_AVR: return "Atmel AVR 8-bit microcontroller";
  4301. + case EM_AVR32: return "Atmel AVR32 32-bit microprocessor";
  4302. case EM_CRIS: return "Axis Communications 32-bit embedded processor";
  4303. case EM_JAVELIN: return "Infineon Technologies 32-bit embedded cpu";
  4304. case EM_FIREPATH: return "Element 14 64-bit DSP processor";
  4305. --- a/gas/as.c
  4306. +++ b/gas/as.c
  4307. @@ -445,10 +445,10 @@ parse_args (int * pargc, char *** pargv)
  4308. the end of the preceeding line so that it is simpler to
  4309. selectively add and remove lines from this list. */
  4310. {"alternate", no_argument, NULL, OPTION_ALTERNATE}
  4311. - /* The entry for "a" is here to prevent getopt_long_only() from
  4312. - considering that -a is an abbreviation for --alternate. This is
  4313. - necessary because -a=<FILE> is a valid switch but getopt would
  4314. - normally reject it since --alternate does not take an argument. */
  4315. + /* The next two entries are here to prevent getopt_long_only() from
  4316. + considering that -a or -al is an abbreviation for --alternate.
  4317. + This is necessary because -a=<FILE> is a valid switch but getopt
  4318. + would normally reject it since --alternate does not take an argument. */
  4319. ,{"a", optional_argument, NULL, 'a'}
  4320. /* Handle -al=<FILE>. */
  4321. ,{"al", optional_argument, NULL, OPTION_AL}
  4322. @@ -811,8 +811,15 @@ This program has absolutely no warranty.
  4323. case 'a':
  4324. if (optarg)
  4325. {
  4326. - if (optarg != old_argv[optind] && optarg[-1] == '=')
  4327. + /* If optarg is part of the -a switch and not a separate argument
  4328. + in its own right, then scan backwards to the just after the -a.
  4329. + This means skipping over both '=' and 'l' which might have been
  4330. + taken to be part of the -a switch itself. */
  4331. + if (optarg != old_argv[optind])
  4332. + {
  4333. + while (optarg[-1] == '=' || optarg[-1] == 'l')
  4334. --optarg;
  4335. + }
  4336. if (md_parse_option (optc, optarg) != 0)
  4337. break;
  4338. @@ -1245,7 +1252,7 @@ main (int argc, char ** argv)
  4339. keep_it = 0;
  4340. if (!keep_it)
  4341. - unlink_if_ordinary (out_file_name);
  4342. + unlink (out_file_name);
  4343. input_scrub_end ();
  4344. --- a/gas/as.h
  4345. +++ b/gas/as.h
  4346. @@ -110,6 +110,7 @@ typedef int * va_list;
  4347. #endif
  4348. #define gas_assert(P) \
  4349. ((void) ((P) ? 0 : (as_assert (__FILE__, __LINE__, __PRETTY_FUNCTION__), 0)))
  4350. +#define assert(P) gas_assert(P)
  4351. #undef abort
  4352. #define abort() as_abort (__FILE__, __LINE__, __PRETTY_FUNCTION__)
  4353. --- a/gas/atof-generic.c
  4354. +++ b/gas/atof-generic.c
  4355. @@ -121,6 +121,21 @@ atof_generic (/* return pointer to just
  4356. switch (first_digit[0])
  4357. {
  4358. + case 's':
  4359. + case 'S':
  4360. + case 'q':
  4361. + case 'Q':
  4362. + if (!strncasecmp ("nan", first_digit+1, 3))
  4363. + {
  4364. + address_of_generic_floating_point_number->sign = 0;
  4365. + address_of_generic_floating_point_number->exponent = 0;
  4366. + address_of_generic_floating_point_number->leader =
  4367. + address_of_generic_floating_point_number->low;
  4368. + *address_of_string_pointer = first_digit + 4;
  4369. + return 0;
  4370. + }
  4371. + break;
  4372. +
  4373. case 'n':
  4374. case 'N':
  4375. if (!strncasecmp ("nan", first_digit, 3))
  4376. --- a/gas/config/atof-vax.c
  4377. +++ b/gas/config/atof-vax.c
  4378. @@ -268,9 +268,27 @@ flonum_gen2vax (int format_letter, /* On
  4379. int exponent_skippage;
  4380. LITTLENUM_TYPE word1;
  4381. - /* JF: Deal with new Nan, +Inf and -Inf codes. */
  4382. + /* JF: Deal with new +/-(q/Q/s/S)Nan, +Inf and -Inf codes. */
  4383. if (f->sign != '-' && f->sign != '+')
  4384. {
  4385. + if (f->sign == 0)
  4386. + {
  4387. + /* All NaNs are 0. */
  4388. + memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
  4389. + }
  4390. + else if (f->sign == 'P')
  4391. + {
  4392. + /* Positive Infinity. */
  4393. + memset (words, 0xff, sizeof (LITTLENUM_TYPE) * precision);
  4394. + words[0] &= 0x7fff;
  4395. + }
  4396. + else if (f->sign == 'N')
  4397. + {
  4398. + /* Negative Infinity. */
  4399. + memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
  4400. + words[0] = 0x0080;
  4401. + }
  4402. + else
  4403. make_invalid_floating_point_number (words);
  4404. return return_value;
  4405. }
  4406. --- /dev/null
  4407. +++ b/gas/config/tc-avr32.c
  4408. @@ -0,0 +1,4839 @@
  4409. +/* Assembler implementation for AVR32.
  4410. + Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation.
  4411. +
  4412. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  4413. +
  4414. + This file is part of GAS, the GNU Assembler.
  4415. +
  4416. + GAS is free software; you can redistribute it and/or modify it
  4417. + under the terms of the GNU General Public License as published by
  4418. + the Free Software Foundation; either version 2, or (at your option)
  4419. + any later version.
  4420. +
  4421. + GAS is distributed in the hope that it will be useful, but WITHOUT
  4422. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  4423. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  4424. + License for more details.
  4425. +
  4426. + You should have received a copy of the GNU General Public License
  4427. + along with GAS; see the file COPYING. If not, write to the Free
  4428. + Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  4429. + 02111-1307, USA. */
  4430. +
  4431. +#include <stdio.h>
  4432. +#include "as.h"
  4433. +#include "safe-ctype.h"
  4434. +#include "subsegs.h"
  4435. +#include "symcat.h"
  4436. +#include "opcodes/avr32-opc.h"
  4437. +#include "opcodes/avr32-asm.h"
  4438. +#include "elf/avr32.h"
  4439. +#include "dwarf2dbg.h"
  4440. +
  4441. +#define xDEBUG
  4442. +#define xOPC_CONSISTENCY_CHECK
  4443. +
  4444. +#ifdef DEBUG
  4445. +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
  4446. +#else
  4447. +# define pr_debug(fmt, args...)
  4448. +#endif
  4449. +
  4450. +/* 3 MSB of instruction word indicate group. Group 7 -> extended */
  4451. +#define AVR32_COMPACT_P(opcode) ((opcode[0] & 0xe0) != 0xe0)
  4452. +
  4453. +#define streq(a, b) (strcmp(a, b) == 0)
  4454. +#define skip_whitespace(str) do { while(*(str) == ' ') ++(str); } while(0)
  4455. +
  4456. +/* Flags given on the command line */
  4457. +static int avr32_pic = FALSE;
  4458. +int linkrelax = FALSE;
  4459. +int avr32_iarcompat = FALSE;
  4460. +
  4461. +/* This array holds the chars that always start a comment. */
  4462. +const char comment_chars[] = "#";
  4463. +
  4464. +/* This array holds the chars that only start a comment at the
  4465. + beginning of a line. We must include '#' here because the compiler
  4466. + may produce #APP and #NO_APP in its output. */
  4467. +const char line_comment_chars[] = "#";
  4468. +
  4469. +/* These may be used instead of newline (same as ';' in C). */
  4470. +const char line_separator_chars[] = ";";
  4471. +
  4472. +/* Chars that can be used to separate mantissa from exponent in
  4473. + floating point numbers. */
  4474. +const char EXP_CHARS[] = "eE";
  4475. +
  4476. +/* Chars that mean this number is a floating point constant. */
  4477. +const char FLT_CHARS[] = "dD";
  4478. +
  4479. +/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
  4480. +symbolS *GOT_symbol;
  4481. +
  4482. +static struct hash_control *avr32_mnemonic_htab;
  4483. +
  4484. +struct avr32_ifield_data
  4485. +{
  4486. + bfd_vma value;
  4487. + /* FIXME: Get rid of align_order and complain. complain is never
  4488. + used, align_order is used in one place. Try to use the relax
  4489. + table instead. */
  4490. + unsigned int align_order;
  4491. +};
  4492. +
  4493. +struct avr32_insn
  4494. +{
  4495. + const struct avr32_syntax *syntax;
  4496. + expressionS immediate;
  4497. + int pcrel;
  4498. + int force_extended;
  4499. + unsigned int next_slot;
  4500. + bfd_reloc_code_real_type r_type;
  4501. + struct avr32_ifield_data field_value[AVR32_MAX_FIELDS];
  4502. +};
  4503. +
  4504. +static struct avr32_insn current_insn;
  4505. +
  4506. +/* The target specific pseudo-ops we support. */
  4507. +static void s_rseg (int);
  4508. +static void s_cpool(int);
  4509. +
  4510. +const pseudo_typeS md_pseudo_table[] =
  4511. +{
  4512. + /* Make sure that .word is 32 bits */
  4513. + { "word", cons, 4 },
  4514. + { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
  4515. + { "loc", dwarf2_directive_loc, 0 },
  4516. +
  4517. + /* .lcomm requires an explicit alignment parameter */
  4518. + { "lcomm", s_lcomm, 1 },
  4519. +
  4520. + /* AVR32-specific pseudo-ops */
  4521. + { "cpool", s_cpool, 0},
  4522. +
  4523. + /* IAR compatible pseudo-ops */
  4524. + { "program", s_ignore, 0 },
  4525. + { "public", s_globl, 0 },
  4526. + { "extern", s_ignore, 0 },
  4527. + { "module", s_ignore, 0 },
  4528. + { "rseg", s_rseg, 0 },
  4529. + { "dc8", cons, 1 },
  4530. + { "dc16", cons, 2 },
  4531. + { "dc32", cons, 4 },
  4532. +
  4533. + { NULL, NULL, 0 }
  4534. +};
  4535. +
  4536. +/* Questionable stuff starts here */
  4537. +
  4538. +enum avr32_opinfo {
  4539. + AVR32_OPINFO_NONE = BFD_RELOC_NONE,
  4540. + AVR32_OPINFO_GOT,
  4541. + AVR32_OPINFO_TLSGD,
  4542. + AVR32_OPINFO_HI,
  4543. + AVR32_OPINFO_LO,
  4544. +};
  4545. +
  4546. +enum avr32_arch {
  4547. + ARCH_TYPE_AP,
  4548. + ARCH_TYPE_UCR1,
  4549. + ARCH_TYPE_UCR2,
  4550. + ARCH_TYPE_UCR3,
  4551. + ARCH_TYPE_UCR3FP
  4552. +};
  4553. +
  4554. +struct arch_type_s
  4555. +{
  4556. + /* Architecture name */
  4557. + char *name;
  4558. + /* Instruction Set Architecture Flags */
  4559. + unsigned long isa_flags;
  4560. +};
  4561. +
  4562. +struct part_type_s
  4563. +{
  4564. + /* Part name */
  4565. + char *name;
  4566. + /* Architecture type */
  4567. + unsigned int arch;
  4568. +};
  4569. +
  4570. +static struct arch_type_s arch_types[] =
  4571. +{
  4572. + {"ap", AVR32_V1 | AVR32_SIMD | AVR32_DSP | AVR32_PICO},
  4573. + {"ucr1", AVR32_V1 | AVR32_DSP | AVR32_RMW},
  4574. + {"ucr2", AVR32_V1 | AVR32_V2 | AVR32_DSP | AVR32_RMW},
  4575. + {"ucr3", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW},
  4576. + {"ucr3fp", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW | AVR32_V3FP},
  4577. + {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO},
  4578. + {NULL, 0}
  4579. +};
  4580. +
  4581. +static struct part_type_s part_types[] =
  4582. +{
  4583. + {"ap7000", ARCH_TYPE_AP},
  4584. + {"ap7001", ARCH_TYPE_AP},
  4585. + {"ap7002", ARCH_TYPE_AP},
  4586. + {"ap7200", ARCH_TYPE_AP},
  4587. + {"uc3a0128", ARCH_TYPE_UCR2},
  4588. + {"uc3a0256", ARCH_TYPE_UCR2},
  4589. + {"uc3a0512es", ARCH_TYPE_UCR1},
  4590. + {"uc3a0512", ARCH_TYPE_UCR2},
  4591. + {"uc3a1128", ARCH_TYPE_UCR2},
  4592. + {"uc3a1256es", ARCH_TYPE_UCR1},
  4593. + {"uc3a1256", ARCH_TYPE_UCR2},
  4594. + {"uc3a1512es", ARCH_TYPE_UCR1},
  4595. + {"uc3a1512", ARCH_TYPE_UCR2},
  4596. + {"uc3a364", ARCH_TYPE_UCR2},
  4597. + {"uc3a364s", ARCH_TYPE_UCR2},
  4598. + {"uc3a3128", ARCH_TYPE_UCR2},
  4599. + {"uc3a3128s", ARCH_TYPE_UCR2},
  4600. + {"uc3a3256", ARCH_TYPE_UCR2},
  4601. + {"uc3a3256s", ARCH_TYPE_UCR2},
  4602. + {"uc3b064", ARCH_TYPE_UCR1},
  4603. + {"uc3b0128", ARCH_TYPE_UCR1},
  4604. + {"uc3b0256es", ARCH_TYPE_UCR1},
  4605. + {"uc3b0256", ARCH_TYPE_UCR1},
  4606. + {"uc3b0512", ARCH_TYPE_UCR2},
  4607. + {"uc3b0512revc", ARCH_TYPE_UCR2},
  4608. + {"uc3b164", ARCH_TYPE_UCR1},
  4609. + {"uc3b1128", ARCH_TYPE_UCR1},
  4610. + {"uc3b1256", ARCH_TYPE_UCR1},
  4611. + {"uc3b1256es", ARCH_TYPE_UCR1},
  4612. + {"uc3b1512", ARCH_TYPE_UCR2},
  4613. + {"uc3b1512revc", ARCH_TYPE_UCR2},
  4614. + {"uc3c0512crevc", ARCH_TYPE_UCR3},
  4615. + {"uc3c1512crevc", ARCH_TYPE_UCR3},
  4616. + {"uc3c2512crevc", ARCH_TYPE_UCR3},
  4617. + {"atuc3l0256", ARCH_TYPE_UCR3},
  4618. + {"mxt768e", ARCH_TYPE_UCR3},
  4619. + {"uc3l064", ARCH_TYPE_UCR3},
  4620. + {"uc3l032", ARCH_TYPE_UCR3},
  4621. + {"uc3l016", ARCH_TYPE_UCR3},
  4622. + {"uc3l064revb", ARCH_TYPE_UCR3},
  4623. + {"uc3c064c", ARCH_TYPE_UCR3FP},
  4624. + {"uc3c0128c", ARCH_TYPE_UCR3FP},
  4625. + {"uc3c0256c", ARCH_TYPE_UCR3FP},
  4626. + {"uc3c0512c", ARCH_TYPE_UCR3FP},
  4627. + {"uc3c164c", ARCH_TYPE_UCR3FP},
  4628. + {"uc3c1128c", ARCH_TYPE_UCR3FP},
  4629. + {"uc3c1256c", ARCH_TYPE_UCR3FP},
  4630. + {"uc3c1512c", ARCH_TYPE_UCR3FP},
  4631. + {"uc3c264c", ARCH_TYPE_UCR3FP},
  4632. + {"uc3c2128c", ARCH_TYPE_UCR3FP},
  4633. + {"uc3c2256c", ARCH_TYPE_UCR3FP},
  4634. + {"uc3c2512c", ARCH_TYPE_UCR3FP},
  4635. + {NULL, 0}
  4636. +};
  4637. +
  4638. +/* Current architecture type. */
  4639. +static struct arch_type_s default_arch = {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO };
  4640. +static struct arch_type_s *avr32_arch = &default_arch;
  4641. +
  4642. +/* Display nicely formatted list of known part- and architecture names. */
  4643. +
  4644. +static void
  4645. +show_arch_list (FILE *stream)
  4646. +{
  4647. + int i, x;
  4648. +
  4649. + fprintf (stream, _("Architectures supported by the assembler:"));
  4650. + x = 1000;
  4651. +
  4652. + for (i = 0; arch_types[i].name; i++)
  4653. + {
  4654. + int len = strlen (arch_types[i].name);
  4655. +
  4656. + x += len + 1;
  4657. +
  4658. + if (x < 75)
  4659. + fprintf (stream, " %s", arch_types[i].name);
  4660. + else
  4661. + {
  4662. + fprintf (stream, "\n %s", arch_types[i].name);
  4663. + x = len + 2;
  4664. + }
  4665. + }
  4666. +
  4667. + fprintf (stream, "\n");
  4668. +}
  4669. +
  4670. +static void
  4671. +show_part_list (FILE *stream)
  4672. +{
  4673. + int i, x;
  4674. +
  4675. + fprintf (stream, _("Known part names:"));
  4676. + x = 1000;
  4677. +
  4678. + for (i = 0; part_types[i].name; i++)
  4679. + {
  4680. + int len = strlen(part_types[i].name);
  4681. +
  4682. + x += len + 1;
  4683. +
  4684. + if (x < 75)
  4685. + fprintf (stream, " %s", part_types[i].name);
  4686. + else
  4687. + {
  4688. + fprintf(stream, "\n %s", part_types[i].name);
  4689. + x = len + 2;
  4690. + }
  4691. + }
  4692. +
  4693. + fprintf (stream, "\n");
  4694. +}
  4695. +
  4696. +const char *md_shortopts = "";
  4697. +struct option md_longopts[] =
  4698. +{
  4699. +#define OPTION_ARCH (OPTION_MD_BASE)
  4700. +#define OPTION_PART (OPTION_ARCH + 1)
  4701. +#define OPTION_IAR (OPTION_PART + 1)
  4702. +#define OPTION_PIC (OPTION_IAR + 1)
  4703. +#define OPTION_NOPIC (OPTION_PIC + 1)
  4704. +#define OPTION_LINKRELAX (OPTION_NOPIC + 1)
  4705. +#define OPTION_NOLINKRELAX (OPTION_LINKRELAX + 1)
  4706. +#define OPTION_DIRECT_DATA_REFS (OPTION_NOLINKRELAX + 1)
  4707. + {"march", required_argument, NULL, OPTION_ARCH},
  4708. + {"mpart", required_argument, NULL, OPTION_PART},
  4709. + {"iar", no_argument, NULL, OPTION_IAR},
  4710. + {"pic", no_argument, NULL, OPTION_PIC},
  4711. + {"no-pic", no_argument, NULL, OPTION_NOPIC},
  4712. + {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
  4713. + {"no-linkrelax", no_argument, NULL, OPTION_NOLINKRELAX},
  4714. + /* deprecated alias for -mpart=xxx */
  4715. + {"mcpu", required_argument, NULL, OPTION_PART},
  4716. + {NULL, no_argument, NULL, 0}
  4717. +};
  4718. +
  4719. +size_t md_longopts_size = sizeof (md_longopts);
  4720. +
  4721. +void
  4722. +md_show_usage (FILE *stream)
  4723. +{
  4724. + fprintf (stream, _("\
  4725. +AVR32 options:\n\
  4726. + -march=[arch-name] Select cpu architecture. [Default `all-insn']\n\
  4727. + -mpart=[part-name] Select specific part. [Default `none']\n\
  4728. + --pic Produce Position-Independent Code\n\
  4729. + --no-pic Don't produce Position-Independent Code\n\
  4730. + --linkrelax Produce output suitable for linker relaxing\n\
  4731. + --no-linkrelax Don't produce output suitable for linker relaxing\n"));
  4732. + show_arch_list(stream);
  4733. +}
  4734. +
  4735. +int
  4736. +md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
  4737. +{
  4738. + switch (c)
  4739. + {
  4740. + case OPTION_ARCH:
  4741. + {
  4742. + int i;
  4743. + char *s = alloca (strlen (arg) + 1);
  4744. +
  4745. + {
  4746. + char *t = s;
  4747. + char *arg1 = arg;
  4748. +
  4749. + do
  4750. + *t = TOLOWER (*arg1++);
  4751. + while (*t++);
  4752. + }
  4753. +
  4754. + /* Add backward compability */
  4755. + if (strcmp ("uc", s)== 0)
  4756. + {
  4757. + as_warn("Deprecated arch `%s' specified. "
  4758. + "Please use '-march=ucr1' instead. "
  4759. + "Using to arch 'ucr1'\n",
  4760. + s);
  4761. + s="ucr1";
  4762. + }
  4763. +
  4764. + for (i = 0; arch_types[i].name; ++i)
  4765. + if (strcmp (arch_types[i].name, s) == 0)
  4766. + break;
  4767. +
  4768. + if (!arch_types[i].name)
  4769. + {
  4770. + show_arch_list (stderr);
  4771. + as_fatal (_("unknown architecture: %s\n"), arg);
  4772. + }
  4773. +
  4774. + avr32_arch = &arch_types[i];
  4775. + break;
  4776. + }
  4777. + case OPTION_PART:
  4778. + {
  4779. + int i;
  4780. + char *s = alloca (strlen (arg) + 1);
  4781. + char *t = s;
  4782. + char *p = arg;
  4783. +
  4784. + /* If arch type has already been set, don't bother.
  4785. + -march= always overrides -mpart= */
  4786. + if (avr32_arch != &default_arch)
  4787. + break;
  4788. +
  4789. + do
  4790. + *t = TOLOWER (*p++);
  4791. + while (*t++);
  4792. +
  4793. + for (i = 0; part_types[i].name; ++i)
  4794. + if (strcmp (part_types[i].name, s) == 0)
  4795. + break;
  4796. +
  4797. + if (!part_types[i].name)
  4798. + {
  4799. + show_part_list (stderr);
  4800. + as_fatal (_("unknown part: %s\n"), arg);
  4801. + }
  4802. +
  4803. + avr32_arch = &arch_types[part_types[i].arch];
  4804. + break;
  4805. + }
  4806. + case OPTION_IAR:
  4807. + avr32_iarcompat = 1;
  4808. + break;
  4809. + case OPTION_PIC:
  4810. + avr32_pic = 1;
  4811. + break;
  4812. + case OPTION_NOPIC:
  4813. + avr32_pic = 0;
  4814. + break;
  4815. + case OPTION_LINKRELAX:
  4816. + linkrelax = 1;
  4817. + break;
  4818. + case OPTION_NOLINKRELAX:
  4819. + linkrelax = 0;
  4820. + break;
  4821. + default:
  4822. + return 0;
  4823. + }
  4824. + return 1;
  4825. +}
  4826. +
  4827. +/* Can't use symbol_new here, so have to create a symbol and then at
  4828. + a later date assign it a value. Thats what these functions do.
  4829. +
  4830. + Shamelessly stolen from ARM. */
  4831. +
  4832. +static void
  4833. +symbol_locate (symbolS * symbolP,
  4834. + const char * name, /* It is copied, the caller can modify. */
  4835. + segT segment, /* Segment identifier (SEG_<something>). */
  4836. + valueT valu, /* Symbol value. */
  4837. + fragS * frag) /* Associated fragment. */
  4838. +{
  4839. + unsigned int name_length;
  4840. + char * preserved_copy_of_name;
  4841. +
  4842. + name_length = strlen (name) + 1; /* +1 for \0. */
  4843. + obstack_grow (&notes, name, name_length);
  4844. + preserved_copy_of_name = obstack_finish (&notes);
  4845. +#ifdef STRIP_UNDERSCORE
  4846. + if (preserved_copy_of_name[0] == '_')
  4847. + preserved_copy_of_name++;
  4848. +#endif
  4849. +
  4850. +#ifdef tc_canonicalize_symbol_name
  4851. + preserved_copy_of_name =
  4852. + tc_canonicalize_symbol_name (preserved_copy_of_name);
  4853. +#endif
  4854. +
  4855. + S_SET_NAME (symbolP, preserved_copy_of_name);
  4856. +
  4857. + S_SET_SEGMENT (symbolP, segment);
  4858. + S_SET_VALUE (symbolP, valu);
  4859. + symbol_clear_list_pointers (symbolP);
  4860. +
  4861. + symbol_set_frag (symbolP, frag);
  4862. +
  4863. + /* Link to end of symbol chain. */
  4864. + {
  4865. + extern int symbol_table_frozen;
  4866. +
  4867. + if (symbol_table_frozen)
  4868. + abort ();
  4869. + }
  4870. +
  4871. + symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
  4872. +
  4873. + obj_symbol_new_hook (symbolP);
  4874. +
  4875. +#ifdef tc_symbol_new_hook
  4876. + tc_symbol_new_hook (symbolP);
  4877. +#endif
  4878. +
  4879. +#ifdef DEBUG_SYMS
  4880. + verify_symbol_chain (symbol_rootP, symbol_lastP);
  4881. +#endif /* DEBUG_SYMS */
  4882. +}
  4883. +
  4884. +struct cpool_entry
  4885. +{
  4886. + int refcount;
  4887. + offsetT offset;
  4888. + expressionS exp;
  4889. +};
  4890. +
  4891. +struct cpool
  4892. +{
  4893. + struct cpool *next;
  4894. + int used;
  4895. + struct cpool_entry *literals;
  4896. + unsigned int padding;
  4897. + unsigned int next_free_entry;
  4898. + unsigned int id;
  4899. + symbolS *symbol;
  4900. + segT section;
  4901. + subsegT sub_section;
  4902. +};
  4903. +
  4904. +struct cpool *cpool_list = NULL;
  4905. +
  4906. +static struct cpool *
  4907. +find_cpool(segT section, subsegT sub_section)
  4908. +{
  4909. + struct cpool *pool;
  4910. +
  4911. + for (pool = cpool_list; pool != NULL; pool = pool->next)
  4912. + {
  4913. + if (!pool->used
  4914. + && pool->section == section
  4915. + && pool->sub_section == sub_section)
  4916. + break;
  4917. + }
  4918. +
  4919. + return pool;
  4920. +}
  4921. +
  4922. +static struct cpool *
  4923. +find_or_make_cpool(segT section, subsegT sub_section)
  4924. +{
  4925. + static unsigned int next_cpool_id = 0;
  4926. + struct cpool *pool;
  4927. +
  4928. + pool = find_cpool(section, sub_section);
  4929. +
  4930. + if (!pool)
  4931. + {
  4932. + pool = xmalloc(sizeof(*pool));
  4933. + if (!pool)
  4934. + return NULL;
  4935. +
  4936. + pool->used = 0;
  4937. + pool->literals = NULL;
  4938. + pool->padding = 0;
  4939. + pool->next_free_entry = 0;
  4940. + pool->section = section;
  4941. + pool->sub_section = sub_section;
  4942. + pool->next = cpool_list;
  4943. + pool->symbol = NULL;
  4944. +
  4945. + cpool_list = pool;
  4946. + }
  4947. +
  4948. + /* NULL symbol means that the pool is new or has just been emptied. */
  4949. + if (!pool->symbol)
  4950. + {
  4951. + pool->symbol = symbol_create(FAKE_LABEL_NAME, undefined_section,
  4952. + 0, &zero_address_frag);
  4953. + pool->id = next_cpool_id++;
  4954. + }
  4955. +
  4956. + return pool;
  4957. +}
  4958. +
  4959. +static struct cpool *
  4960. +add_to_cpool(expressionS *exp, unsigned int *index, int ref)
  4961. +{
  4962. + struct cpool *pool;
  4963. + unsigned int entry;
  4964. +
  4965. + pool = find_or_make_cpool(now_seg, now_subseg);
  4966. +
  4967. + /* Check if this constant is already in the pool. */
  4968. + for (entry = 0; entry < pool->next_free_entry; entry++)
  4969. + {
  4970. + if ((pool->literals[entry].exp.X_op == exp->X_op)
  4971. + && (exp->X_op == O_constant)
  4972. + && (pool->literals[entry].exp.X_add_number
  4973. + == exp->X_add_number)
  4974. + && (pool->literals[entry].exp.X_unsigned
  4975. + == exp->X_unsigned))
  4976. + break;
  4977. +
  4978. + if ((pool->literals[entry].exp.X_op == exp->X_op)
  4979. + && (exp->X_op == O_symbol)
  4980. + && (pool->literals[entry].exp.X_add_number
  4981. + == exp->X_add_number)
  4982. + && (pool->literals[entry].exp.X_add_symbol
  4983. + == exp->X_add_symbol)
  4984. + && (pool->literals[entry].exp.X_op_symbol
  4985. + == exp->X_op_symbol))
  4986. + break;
  4987. + }
  4988. +
  4989. + /* Create an entry if we didn't find a match */
  4990. + if (entry == pool->next_free_entry)
  4991. + {
  4992. + pool->literals = xrealloc(pool->literals,
  4993. + sizeof(struct cpool_entry) * (entry + 1));
  4994. + pool->literals[entry].exp = *exp;
  4995. + pool->literals[entry].refcount = 0;
  4996. + pool->next_free_entry++;
  4997. + }
  4998. +
  4999. + if (index)
  5000. + *index = entry;
  5001. + if (ref)
  5002. + pool->literals[entry].refcount++;
  5003. +
  5004. + return pool;
  5005. +}
  5006. +
  5007. +struct avr32_operand
  5008. +{
  5009. + int id;
  5010. + int is_signed;
  5011. + int is_pcrel;
  5012. + int align_order;
  5013. + int (*match)(char *str);
  5014. + void (*parse)(const struct avr32_operand *op, char *str, int opindex);
  5015. +};
  5016. +
  5017. +static int
  5018. +match_anything(char *str ATTRIBUTE_UNUSED)
  5019. +{
  5020. + return 1;
  5021. +}
  5022. +
  5023. +static int
  5024. +match_intreg(char *str)
  5025. +{
  5026. + int regid, ret = 1;
  5027. +
  5028. + regid = avr32_parse_intreg(str);
  5029. + if (regid < 0)
  5030. + ret = 0;
  5031. +
  5032. + pr_debug("match_intreg: `%s': %d\n", str, ret);
  5033. +
  5034. + return ret;
  5035. +}
  5036. +
  5037. +static int
  5038. +match_intreg_predec(char *str)
  5039. +{
  5040. + int regid;
  5041. +
  5042. + if (str[0] != '-' || str[1] != '-')
  5043. + return 0;
  5044. +
  5045. + regid = avr32_parse_intreg(str + 2);
  5046. + if (regid < 0)
  5047. + return 0;
  5048. +
  5049. + return 1;
  5050. +}
  5051. +
  5052. +static int
  5053. +match_intreg_postinc(char *str)
  5054. +{
  5055. + int regid, ret = 1;
  5056. + char *p, c;
  5057. +
  5058. + for (p = str; *p; p++)
  5059. + if (*p == '+')
  5060. + break;
  5061. +
  5062. + if (p[0] != '+' || p[1] != '+')
  5063. + return 0;
  5064. +
  5065. + c = *p, *p = 0;
  5066. + regid = avr32_parse_intreg(str);
  5067. + if (regid < 0)
  5068. + ret = 0;
  5069. +
  5070. + *p = c;
  5071. + return ret;
  5072. +}
  5073. +
  5074. +static int
  5075. +match_intreg_lsl(char *str)
  5076. +{
  5077. + int regid, ret = 1;
  5078. + char *p, c;
  5079. +
  5080. + for (p = str; *p; p++)
  5081. + if (*p == '<')
  5082. + break;
  5083. +
  5084. + if (p[0] && p[1] != '<')
  5085. + return 0;
  5086. +
  5087. + c = *p, *p = 0;
  5088. + regid = avr32_parse_intreg(str);
  5089. + if (regid < 0)
  5090. + ret = 0;
  5091. +
  5092. + *p = c;
  5093. + return ret;
  5094. +}
  5095. +
  5096. +static int
  5097. +match_intreg_lsr(char *str)
  5098. +{
  5099. + int regid, ret = 1;
  5100. + char *p, c;
  5101. +
  5102. + for (p = str; *p; p++)
  5103. + if (*p == '>')
  5104. + break;
  5105. +
  5106. + if (p[0] && p[1] != '>')
  5107. + return 0;
  5108. +
  5109. + c = *p, *p = 0;
  5110. +
  5111. + regid = avr32_parse_intreg(str);
  5112. + if (regid < 0)
  5113. + ret = 0;
  5114. +
  5115. + *p = c;
  5116. + return ret;
  5117. +}
  5118. +
  5119. +static int
  5120. +match_intreg_part(char *str)
  5121. +{
  5122. + int regid, ret = 1;
  5123. + char *p, c;
  5124. +
  5125. + for (p = str; *p; p++)
  5126. + if (*p == ':')
  5127. + break;
  5128. +
  5129. + if (p[0] != ':' || !ISPRINT(p[1]) || p[2] != '\0')
  5130. + return 0;
  5131. +
  5132. + c = *p, *p = 0;
  5133. + regid = avr32_parse_intreg(str);
  5134. + if (regid < 0)
  5135. + ret = 0;
  5136. +
  5137. + *p = c;
  5138. +
  5139. + return ret;
  5140. +}
  5141. +
  5142. +#define match_intreg_disp match_anything
  5143. +
  5144. +static int
  5145. +match_intreg_index(char *str)
  5146. +{
  5147. + int regid, ret = 1;
  5148. + char *p, *end, c;
  5149. +
  5150. + for (p = str; *p; p++)
  5151. + if (*p == '[')
  5152. + break;
  5153. +
  5154. + /* don't allow empty displacement here (it makes no sense) */
  5155. + if (p[0] != '[')
  5156. + return 0;
  5157. +
  5158. + for (end = p + 1; *end; end++) ;
  5159. + if (*(--end) != ']')
  5160. + return 0;
  5161. +
  5162. + c = *end, *end = 0;
  5163. + if (!match_intreg_lsl(p + 1))
  5164. + ret = 0;
  5165. + *end = c;
  5166. +
  5167. + if (ret)
  5168. + {
  5169. + c = *p, *p = 0;
  5170. + regid = avr32_parse_intreg(str);
  5171. + if (regid < 0)
  5172. + ret = 0;
  5173. + *p = c;
  5174. + }
  5175. +
  5176. + return ret;
  5177. +}
  5178. +
  5179. +static int
  5180. +match_intreg_xindex(char *str)
  5181. +{
  5182. + int regid, ret = 1;
  5183. + char *p, *end, c;
  5184. +
  5185. + for (p = str; *p; p++)
  5186. + if (*p == '[')
  5187. + break;
  5188. +
  5189. + /* empty displacement makes no sense here either */
  5190. + if (p[0] != '[')
  5191. + return 0;
  5192. +
  5193. + for (end = p + 1; *end; end++)
  5194. + if (*end == '<')
  5195. + break;
  5196. +
  5197. + if (!streq(end, "<<2]"))
  5198. + return 0;
  5199. +
  5200. + c = *end, *end = 0;
  5201. + if (!match_intreg_part(p + 1))
  5202. + ret = 0;
  5203. + *end = c;
  5204. +
  5205. + if (ret)
  5206. + {
  5207. + c = *p, *p = 0;
  5208. + regid = avr32_parse_intreg(str);
  5209. + if (regid < 0)
  5210. + ret = 0;
  5211. + *p = c;
  5212. + }
  5213. +
  5214. + return ret;
  5215. +}
  5216. +
  5217. +/* The PC_UDISP_W operator may show up as a label or as a pc[disp]
  5218. + expression. So there's no point in attempting to match this... */
  5219. +#define match_pc_disp match_anything
  5220. +
  5221. +static int
  5222. +match_sp(char *str)
  5223. +{
  5224. + /* SP in any form will do */
  5225. + return avr32_parse_intreg(str) == AVR32_REG_SP;
  5226. +}
  5227. +
  5228. +static int
  5229. +match_sp_disp(char *str)
  5230. +{
  5231. + int regid, ret = 1;
  5232. + char *p, c;
  5233. +
  5234. + for (p = str; *p; p++)
  5235. + if (*p == '[')
  5236. + break;
  5237. +
  5238. + /* allow empty displacement, meaning zero */
  5239. + if (p[0] == '[')
  5240. + {
  5241. + char *end;
  5242. + for (end = p + 1; *end; end++) ;
  5243. + if (end[-1] != ']')
  5244. + return 0;
  5245. + }
  5246. +
  5247. + c = *p, *p = 0;
  5248. + regid = avr32_parse_intreg(str);
  5249. + if (regid != AVR32_REG_SP)
  5250. + ret = 0;
  5251. +
  5252. + *p = c;
  5253. + return ret;
  5254. +}
  5255. +
  5256. +static int
  5257. +match_cpno(char *str)
  5258. +{
  5259. + if (strncasecmp(str, "cp", 2) != 0)
  5260. + return 0;
  5261. + return 1;
  5262. +}
  5263. +
  5264. +static int
  5265. +match_cpreg(char *str)
  5266. +{
  5267. + if (strncasecmp(str, "cr", 2) != 0)
  5268. + return 0;
  5269. + return 1;
  5270. +}
  5271. +
  5272. +/* We allow complex expressions, and register names may show up as
  5273. + symbols. Just make sure immediate expressions are always matched
  5274. + last. */
  5275. +#define match_const match_anything
  5276. +#define match_jmplabel match_anything
  5277. +#define match_number match_anything
  5278. +
  5279. +/* Mnemonics that take reglists never accept anything else */
  5280. +#define match_reglist8 match_anything
  5281. +#define match_reglist9 match_anything
  5282. +#define match_reglist16 match_anything
  5283. +#define match_reglist_ldm match_anything
  5284. +#define match_reglist_cp8 match_anything
  5285. +#define match_reglist_cpd8 match_anything
  5286. +
  5287. +/* Ditto for retval, jospinc and mcall */
  5288. +#define match_retval match_anything
  5289. +#define match_jospinc match_anything
  5290. +#define match_mcall match_anything
  5291. +
  5292. +/* COH is used to select between two different syntaxes */
  5293. +static int
  5294. +match_coh(char *str)
  5295. +{
  5296. + return strcasecmp(str, "coh") == 0;
  5297. +}
  5298. +#if 0
  5299. +static int
  5300. +match_fpreg(char *str)
  5301. +{
  5302. + unsigned long regid;
  5303. + char *endptr;
  5304. +
  5305. + if ((str[0] != 'f' && str[0] != 'F')
  5306. + || (str[1] != 'r' && str[1] != 'R'))
  5307. + return 0;
  5308. +
  5309. + str += 2;
  5310. + regid = strtoul(str, &endptr, 10);
  5311. + if (!*str || *endptr)
  5312. + return 0;
  5313. +
  5314. + return 1;
  5315. +}
  5316. +#endif
  5317. +
  5318. +static int
  5319. +match_picoreg(char *str)
  5320. +{
  5321. + int regid;
  5322. +
  5323. + regid = avr32_parse_picoreg(str);
  5324. + if (regid < 0)
  5325. + return 0;
  5326. + return 1;
  5327. +}
  5328. +
  5329. +#define match_pico_reglist_w match_anything
  5330. +#define match_pico_reglist_d match_anything
  5331. +
  5332. +static int
  5333. +match_pico_in(char *str)
  5334. +{
  5335. + unsigned long regid;
  5336. + char *end;
  5337. +
  5338. + if (strncasecmp(str, "in", 2) != 0)
  5339. + return 0;
  5340. +
  5341. + str += 2;
  5342. + regid = strtoul(str, &end, 10);
  5343. + if (!*str || *end)
  5344. + return 0;
  5345. +
  5346. + return 1;
  5347. +}
  5348. +
  5349. +static int
  5350. +match_pico_out0(char *str)
  5351. +{
  5352. + if (strcasecmp(str, "out0") != 0)
  5353. + return 0;
  5354. + return 1;
  5355. +}
  5356. +
  5357. +static int
  5358. +match_pico_out1(char *str)
  5359. +{
  5360. + if (strcasecmp(str, "out1") != 0)
  5361. + return 0;
  5362. + return 1;
  5363. +}
  5364. +
  5365. +static int
  5366. +match_pico_out2(char *str)
  5367. +{
  5368. + if (strcasecmp(str, "out2") != 0)
  5369. + return 0;
  5370. + return 1;
  5371. +}
  5372. +
  5373. +static int
  5374. +match_pico_out3(char *str)
  5375. +{
  5376. + if (strcasecmp(str, "out3") != 0)
  5377. + return 0;
  5378. + return 1;
  5379. +}
  5380. +
  5381. +static void parse_nothing(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  5382. + char *str ATTRIBUTE_UNUSED,
  5383. + int opindex ATTRIBUTE_UNUSED)
  5384. +{
  5385. + /* Do nothing (this is used for "match-only" operands like COH) */
  5386. +}
  5387. +
  5388. +static void
  5389. +parse_const(const struct avr32_operand *op, char *str,
  5390. + int opindex ATTRIBUTE_UNUSED)
  5391. +{
  5392. + expressionS *exp = &current_insn.immediate;
  5393. + expressionS *sym_exp;
  5394. + int slot;
  5395. + char *save;
  5396. +
  5397. + pr_debug("parse_const: `%s' (signed: %d, pcrel: %d, align: %d)\n",
  5398. + str, op->is_signed, op->is_pcrel, op->align_order);
  5399. +
  5400. + save = input_line_pointer;
  5401. + input_line_pointer = str;
  5402. +
  5403. + expression(exp);
  5404. +
  5405. + slot = current_insn.next_slot++;
  5406. + current_insn.field_value[slot].align_order = op->align_order;
  5407. + current_insn.pcrel = op->is_pcrel;
  5408. +
  5409. + switch (exp->X_op)
  5410. + {
  5411. + case O_illegal:
  5412. + as_bad(_("illegal operand"));
  5413. + break;
  5414. + case O_absent:
  5415. + as_bad(_("missing operand"));
  5416. + break;
  5417. + case O_constant:
  5418. + pr_debug(" -> constant: %ld\n", (long)exp->X_add_number);
  5419. + current_insn.field_value[slot].value = exp->X_add_number;
  5420. + break;
  5421. + case O_uminus:
  5422. + pr_debug(" -> uminus\n");
  5423. + sym_exp = symbol_get_value_expression(exp->X_add_symbol);
  5424. + switch (sym_exp->X_op) {
  5425. + case O_subtract:
  5426. + pr_debug(" -> subtract: switching operands\n");
  5427. + exp->X_op_symbol = sym_exp->X_add_symbol;
  5428. + exp->X_add_symbol = sym_exp->X_op_symbol;
  5429. + exp->X_op = O_subtract;
  5430. + /* TODO: Remove the old X_add_symbol */
  5431. + break;
  5432. + default:
  5433. + as_bad(_("Expression too complex\n"));
  5434. + break;
  5435. + }
  5436. + break;
  5437. +#if 0
  5438. + case O_subtract:
  5439. + /* Any expression subtracting a symbol from the current section
  5440. + can be made PC-relative by adding the right offset. */
  5441. + if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
  5442. + current_insn.pcrel = TRUE;
  5443. + pr_debug(" -> subtract: pcrel? %s\n",
  5444. + current_insn.pcrel ? "yes" : "no");
  5445. + /* fall through */
  5446. +#endif
  5447. + default:
  5448. + pr_debug(" -> (%p <%d> %p + %d)\n",
  5449. + exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
  5450. + exp->X_add_number);
  5451. + current_insn.field_value[slot].value = 0;
  5452. + break;
  5453. + }
  5454. +
  5455. + input_line_pointer = save;
  5456. +}
  5457. +
  5458. +static void
  5459. +parse_jmplabel(const struct avr32_operand *op, char *str,
  5460. + int opindex ATTRIBUTE_UNUSED)
  5461. +{
  5462. + expressionS *exp = &current_insn.immediate;
  5463. + int slot;
  5464. + char *save;
  5465. +
  5466. + pr_debug("parse_jmplabel: `%s' (signed: %d, pcrel: %d, align: %d)\n",
  5467. + str, op->is_signed, op->is_pcrel, op->align_order);
  5468. +
  5469. + save = input_line_pointer;
  5470. + input_line_pointer = str;
  5471. +
  5472. + expression(exp);
  5473. +
  5474. + slot = current_insn.next_slot++;
  5475. + current_insn.field_value[slot].align_order = op->align_order;
  5476. + current_insn.pcrel = TRUE;
  5477. +
  5478. + switch (exp->X_op)
  5479. + {
  5480. + case O_illegal:
  5481. + as_bad(_("illegal operand"));
  5482. + break;
  5483. + case O_absent:
  5484. + as_bad(_("missing operand"));
  5485. + break;
  5486. + case O_constant:
  5487. + pr_debug(" -> constant: %ld\n", (long)exp->X_add_number);
  5488. + current_insn.field_value[slot].value = exp->X_add_number;
  5489. + current_insn.pcrel = 0;
  5490. + break;
  5491. + default:
  5492. + pr_debug(" -> (%p <%d> %p + %d)\n",
  5493. + exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
  5494. + exp->X_add_number);
  5495. + current_insn.field_value[slot].value = 0;
  5496. + break;
  5497. + }
  5498. +
  5499. + input_line_pointer = save;
  5500. +}
  5501. +
  5502. +static void
  5503. +parse_intreg(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  5504. + char *str, int opindex ATTRIBUTE_UNUSED)
  5505. +{
  5506. + int regid, slot;
  5507. +
  5508. + pr_debug("parse_intreg: `%s'\n", str);
  5509. +
  5510. + regid = avr32_parse_intreg(str);
  5511. + assert(regid >= 0);
  5512. +
  5513. + slot = current_insn.next_slot++;
  5514. + current_insn.field_value[slot].value = regid;
  5515. + current_insn.field_value[slot].align_order = op->align_order;
  5516. +}
  5517. +
  5518. +static void
  5519. +parse_intreg_predec(const struct avr32_operand *op, char *str, int opindex)
  5520. +{
  5521. + parse_intreg(op, str + 2, opindex);
  5522. +}
  5523. +
  5524. +static void
  5525. +parse_intreg_postinc(const struct avr32_operand *op, char *str, int opindex)
  5526. +{
  5527. + char *p, c;
  5528. +
  5529. + pr_debug("parse_intreg_postinc: `%s'\n", str);
  5530. +
  5531. + for (p = str; *p != '+'; p++) ;
  5532. +
  5533. + c = *p, *p = 0;
  5534. + parse_intreg(op, str, opindex);
  5535. + *p = c;
  5536. +}
  5537. +
  5538. +static void
  5539. +parse_intreg_shift(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  5540. + char *str, int opindex ATTRIBUTE_UNUSED)
  5541. +{
  5542. + int regid, slot, shift = 0;
  5543. + char *p, c;
  5544. + char shiftop;
  5545. +
  5546. + pr_debug("parse Ry<<sa: `%s'\n", str);
  5547. +
  5548. + for (p = str; *p; p++)
  5549. + if (*p == '<' || *p == '>')
  5550. + break;
  5551. +
  5552. + shiftop = *p;
  5553. +
  5554. + c = *p, *p = 0;
  5555. + regid = avr32_parse_intreg(str);
  5556. + assert(regid >= 0);
  5557. + *p = c;
  5558. +
  5559. + if (c)
  5560. + {
  5561. + if (p[0] != shiftop || p[1] != shiftop)
  5562. + as_bad(_("expected shift operator in `%s'"), p);
  5563. + else
  5564. + {
  5565. + expressionS exp;
  5566. + char *saved;
  5567. +
  5568. + saved = input_line_pointer;
  5569. + input_line_pointer = p + 2;
  5570. + expression(&exp);
  5571. + input_line_pointer = saved;
  5572. +
  5573. + if (exp.X_op != O_constant)
  5574. + as_bad(_("shift amount must be a numeric constant"));
  5575. + else
  5576. + shift = exp.X_add_number;
  5577. + }
  5578. + }
  5579. +
  5580. + slot = current_insn.next_slot++;
  5581. + current_insn.field_value[slot].value = regid;
  5582. + slot = current_insn.next_slot++;
  5583. + current_insn.field_value[slot].value = shift;
  5584. +}
  5585. +
  5586. +/* The match() function selected the right opcode, so it doesn't
  5587. + matter which way we shift any more. */
  5588. +#define parse_intreg_lsl parse_intreg_shift
  5589. +#define parse_intreg_lsr parse_intreg_shift
  5590. +
  5591. +static void
  5592. +parse_intreg_part(const struct avr32_operand *op, char *str,
  5593. + int opindex ATTRIBUTE_UNUSED)
  5594. +{
  5595. + static const char bparts[] = { 'b', 'l', 'u', 't' };
  5596. + static const char hparts[] = { 'b', 't' };
  5597. + unsigned int slot, sel;
  5598. + int regid;
  5599. + char *p, c;
  5600. +
  5601. + pr_debug("parse reg:part `%s'\n", str);
  5602. +
  5603. + for (p = str; *p; p++)
  5604. + if (*p == ':')
  5605. + break;
  5606. +
  5607. + c = *p, *p = 0;
  5608. + regid = avr32_parse_intreg(str);
  5609. + assert(regid >= 0);
  5610. + *p = c;
  5611. +
  5612. + assert(c == ':');
  5613. +
  5614. + if (op->align_order)
  5615. + {
  5616. + for (sel = 0; sel < sizeof(hparts); sel++)
  5617. + if (TOLOWER(p[1]) == hparts[sel])
  5618. + break;
  5619. +
  5620. + if (sel >= sizeof(hparts))
  5621. + {
  5622. + as_bad(_("invalid halfword selector `%c' (must be either b or t)"),
  5623. + p[1]);
  5624. + sel = 0;
  5625. + }
  5626. + }
  5627. + else
  5628. + {
  5629. + for (sel = 0; sel < sizeof(bparts); sel++)
  5630. + if (TOLOWER(p[1]) == bparts[sel])
  5631. + break;
  5632. +
  5633. + if (sel >= sizeof(bparts))
  5634. + {
  5635. + as_bad(_("invalid byte selector `%c' (must be one of b,l,u,t)"),
  5636. + p[1]);
  5637. + sel = 0;
  5638. + }
  5639. + }
  5640. +
  5641. + slot = current_insn.next_slot++;
  5642. + current_insn.field_value[slot].value = regid;
  5643. + slot = current_insn.next_slot++;
  5644. + current_insn.field_value[slot].value = sel;
  5645. +}
  5646. +
  5647. +/* This is the parser for "Rp[displacement]" expressions. In addition
  5648. + to the "official" syntax, we accept a label as a replacement for
  5649. + the register expression. This syntax implies Rp=PC and the
  5650. + displacement is the pc-relative distance to the label. */
  5651. +static void
  5652. +parse_intreg_disp(const struct avr32_operand *op, char *str, int opindex)
  5653. +{
  5654. + expressionS *exp = &current_insn.immediate;
  5655. + int slot, regid;
  5656. + char *save, *p, c;
  5657. +
  5658. + pr_debug("parse_intreg_disp: `%s' (signed: %d, pcrel: %d, align: %d)\n",
  5659. + str, op->is_signed, op->is_pcrel, op->align_order);
  5660. +
  5661. + for (p = str; *p; p++)
  5662. + if (*p == '[')
  5663. + break;
  5664. +
  5665. + slot = current_insn.next_slot++;
  5666. +
  5667. + /* First, check if we have a valid register either before '[' or as
  5668. + the sole expression. If so, we use the Rp[disp] syntax. */
  5669. + c = *p, *p = 0;
  5670. + regid = avr32_parse_intreg(str);
  5671. + *p = c;
  5672. +
  5673. + if (regid >= 0)
  5674. + {
  5675. + current_insn.field_value[slot].value = regid;
  5676. +
  5677. + slot = current_insn.next_slot++;
  5678. + current_insn.field_value[slot].align_order = op->align_order;
  5679. +
  5680. + if (c == '[')
  5681. + {
  5682. + save = input_line_pointer;
  5683. + input_line_pointer = p + 1;
  5684. +
  5685. + expression(exp);
  5686. +
  5687. + if (*input_line_pointer != ']')
  5688. + as_bad(_("junk after displacement expression"));
  5689. +
  5690. + input_line_pointer = save;
  5691. +
  5692. + switch (exp->X_op)
  5693. + {
  5694. + case O_illegal:
  5695. + as_bad(_("illegal displacement expression"));
  5696. + break;
  5697. + case O_absent:
  5698. + as_bad(_("missing displacement expression"));
  5699. + break;
  5700. + case O_constant:
  5701. + pr_debug(" -> constant: %ld\n", exp->X_add_number);
  5702. + current_insn.field_value[slot].value = exp->X_add_number;
  5703. + break;
  5704. +#if 0
  5705. + case O_subtract:
  5706. + if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
  5707. + current_insn.pcrel = TRUE;
  5708. + pr_debug(" -> subtract: pcrel? %s\n",
  5709. + current_insn.pcrel ? "yes" : "no");
  5710. + /* fall through */
  5711. +#endif
  5712. + default:
  5713. + pr_debug(" -> (%p <%d> %p + %d)\n",
  5714. + exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
  5715. + exp->X_add_number);
  5716. + current_insn.field_value[slot].value = 0;
  5717. + }
  5718. + }
  5719. + else
  5720. + {
  5721. + exp->X_op = O_constant;
  5722. + exp->X_add_number = 0;
  5723. + current_insn.field_value[slot].value = 0;
  5724. + }
  5725. + }
  5726. + else
  5727. + {
  5728. + /* Didn't find a valid register. Try parsing it as a label. */
  5729. + current_insn.field_value[slot].value = AVR32_REG_PC;
  5730. + parse_jmplabel(op, str, opindex);
  5731. + }
  5732. +}
  5733. +
  5734. +static void
  5735. +parse_intreg_index(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  5736. + char *str, int opindex ATTRIBUTE_UNUSED)
  5737. +{
  5738. + int slot, regid;
  5739. + char *p, *end, c;
  5740. +
  5741. + for (p = str; *p; p++)
  5742. + if (*p == '[')
  5743. + break;
  5744. +
  5745. + assert(*p);
  5746. +
  5747. + c = *p, *p = 0;
  5748. + regid = avr32_parse_intreg(str);
  5749. + assert(regid >= 0);
  5750. + *p = c;
  5751. +
  5752. + slot = current_insn.next_slot++;
  5753. + current_insn.field_value[slot].value = regid;
  5754. +
  5755. + p++;
  5756. + for (end = p; *end; end++)
  5757. + if (*end == ']' || *end == '<')
  5758. + break;
  5759. +
  5760. + assert(*end);
  5761. +
  5762. + c = *end, *end = 0;
  5763. + regid = avr32_parse_intreg(p);
  5764. + assert(regid >= 0);
  5765. + *end = c;
  5766. +
  5767. + slot = current_insn.next_slot++;
  5768. + current_insn.field_value[slot].value = regid;
  5769. +
  5770. + slot = current_insn.next_slot++;
  5771. + current_insn.field_value[slot].value = 0;
  5772. +
  5773. + if (*end == '<')
  5774. + {
  5775. + expressionS exp;
  5776. + char *save;
  5777. +
  5778. + p = end + 2;
  5779. + for (end = p; *end; end++)
  5780. + if (*end == ']')
  5781. + break;
  5782. +
  5783. + assert(*end == ']');
  5784. +
  5785. + c = *end, *end = 0;
  5786. + save = input_line_pointer;
  5787. + input_line_pointer = p;
  5788. + expression(&exp);
  5789. +
  5790. + if (*input_line_pointer)
  5791. + as_bad(_("junk after shift expression"));
  5792. +
  5793. + *end = c;
  5794. + input_line_pointer = save;
  5795. +
  5796. + if (exp.X_op == O_constant)
  5797. + current_insn.field_value[slot].value = exp.X_add_number;
  5798. + else
  5799. + as_bad(_("shift expression too complex"));
  5800. + }
  5801. +}
  5802. +
  5803. +static void
  5804. +parse_intreg_xindex(const struct avr32_operand *op, char *str, int opindex)
  5805. +{
  5806. + int slot, regid;
  5807. + char *p, *end, c;
  5808. +
  5809. + for (p = str; *p; p++)
  5810. + if (*p == '[')
  5811. + break;
  5812. +
  5813. + assert(*p);
  5814. +
  5815. + c = *p, *p = 0;
  5816. + regid = avr32_parse_intreg(str);
  5817. + assert(regid >= 0);
  5818. + *p = c;
  5819. +
  5820. + slot = current_insn.next_slot++;
  5821. + current_insn.field_value[slot].value = regid;
  5822. +
  5823. + p++;
  5824. + for (end = p; *end; end++)
  5825. + if (*end == '<')
  5826. + break;
  5827. +
  5828. + assert(*end);
  5829. +
  5830. + c = *end, *end = 0;
  5831. + parse_intreg_part(op, p, opindex);
  5832. + *end = c;
  5833. +}
  5834. +
  5835. +static void
  5836. +parse_pc_disp(const struct avr32_operand *op, char *str, int opindex)
  5837. +{
  5838. + char *p, c;
  5839. +
  5840. + for (p = str; *p; p++)
  5841. + if (*p == '[')
  5842. + break;
  5843. +
  5844. + /* The lddpc instruction comes in two different syntax variants:
  5845. + lddpc reg, expression
  5846. + lddpc reg, pc[disp]
  5847. + If the operand contains a '[', we use the second form. */
  5848. + if (*p)
  5849. + {
  5850. + int regid;
  5851. +
  5852. + c = *p, *p = 0;
  5853. + regid = avr32_parse_intreg(str);
  5854. + *p = c;
  5855. + if (regid == AVR32_REG_PC)
  5856. + {
  5857. + char *end;
  5858. +
  5859. + for (end = ++p; *end; end++) ;
  5860. + if (*(--end) != ']')
  5861. + as_bad(_("unrecognized form of instruction: `%s'"), str);
  5862. + else
  5863. + {
  5864. + c = *end, *end = 0;
  5865. + parse_const(op, p, opindex);
  5866. + *end = c;
  5867. + current_insn.pcrel = 0;
  5868. + }
  5869. + }
  5870. + else
  5871. + as_bad(_("unrecognized form of instruction: `%s'"), str);
  5872. + }
  5873. + else
  5874. + {
  5875. + parse_jmplabel(op, str, opindex);
  5876. + }
  5877. +}
  5878. +
  5879. +static void parse_sp(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  5880. + char *str ATTRIBUTE_UNUSED,
  5881. + int opindex ATTRIBUTE_UNUSED)
  5882. +{
  5883. + int slot;
  5884. +
  5885. + slot = current_insn.next_slot++;
  5886. + current_insn.field_value[slot].value = AVR32_REG_SP;
  5887. +}
  5888. +
  5889. +static void
  5890. +parse_sp_disp(const struct avr32_operand *op, char *str, int opindex)
  5891. +{
  5892. + char *p, c;
  5893. +
  5894. + for (; *str; str++)
  5895. + if (*str == '[')
  5896. + break;
  5897. +
  5898. + assert(*str);
  5899. +
  5900. + for (p = ++str; *p; p++)
  5901. + if (*p == ']')
  5902. + break;
  5903. +
  5904. + c = *p, *p = 0;
  5905. + parse_const(op, str, opindex);
  5906. + *p = c;
  5907. +}
  5908. +
  5909. +static void
  5910. +parse_cpno(const struct avr32_operand *op ATTRIBUTE_UNUSED, char *str,
  5911. + int opindex ATTRIBUTE_UNUSED)
  5912. +{
  5913. + int slot;
  5914. +
  5915. + str += 2;
  5916. + if (*str == '#')
  5917. + str++;
  5918. + if (*str < '0' || *str > '7' || str[1])
  5919. + as_bad(_("invalid coprocessor `%s'"), str);
  5920. +
  5921. + slot = current_insn.next_slot++;
  5922. + current_insn.field_value[slot].value = *str - '0';
  5923. +}
  5924. +
  5925. +static void
  5926. +parse_cpreg(const struct avr32_operand *op, char *str,
  5927. + int opindex ATTRIBUTE_UNUSED)
  5928. +{
  5929. + unsigned int crid;
  5930. + int slot;
  5931. + char *endptr;
  5932. +
  5933. + str += 2;
  5934. + crid = strtoul(str, &endptr, 10);
  5935. + if (*endptr || crid > 15 || crid & ((1 << op->align_order) - 1))
  5936. + as_bad(_("invalid coprocessor register `%s'"), str);
  5937. +
  5938. + crid >>= op->align_order;
  5939. +
  5940. + slot = current_insn.next_slot++;
  5941. + current_insn.field_value[slot].value = crid;
  5942. +}
  5943. +
  5944. +static void
  5945. +parse_number(const struct avr32_operand *op, char *str,
  5946. + int opindex ATTRIBUTE_UNUSED)
  5947. +{
  5948. + expressionS exp;
  5949. + int slot;
  5950. + char *save;
  5951. +
  5952. + save = input_line_pointer;
  5953. + input_line_pointer = str;
  5954. + expression(&exp);
  5955. + input_line_pointer = save;
  5956. +
  5957. + slot = current_insn.next_slot++;
  5958. + current_insn.field_value[slot].align_order = op->align_order;
  5959. +
  5960. + if (exp.X_op == O_constant)
  5961. + current_insn.field_value[slot].value = exp.X_add_number;
  5962. + else
  5963. + as_bad(_("invalid numeric expression `%s'"), str);
  5964. +}
  5965. +
  5966. +static void
  5967. +parse_reglist8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  5968. + char *str, int opindex ATTRIBUTE_UNUSED)
  5969. +{
  5970. + unsigned long regmask;
  5971. + unsigned long value = 0;
  5972. + int slot;
  5973. + char *tail;
  5974. +
  5975. + regmask = avr32_parse_reglist(str, &tail);
  5976. + if (*tail)
  5977. + as_bad(_("invalid register list `%s'"), str);
  5978. + else
  5979. + {
  5980. + if (avr32_make_regmask8(regmask, &value))
  5981. + as_bad(_("register list `%s' doesn't fit"), str);
  5982. + }
  5983. +
  5984. + slot = current_insn.next_slot++;
  5985. + current_insn.field_value[slot].value = value;
  5986. +}
  5987. +
  5988. +static int
  5989. +parse_reglist_tail(char *str, unsigned long regmask)
  5990. +{
  5991. + expressionS exp;
  5992. + char *save, *p, c;
  5993. + int regid;
  5994. +
  5995. + for (p = str + 1; *p; p++)
  5996. + if (*p == '=')
  5997. + break;
  5998. +
  5999. + if (!*p)
  6000. + {
  6001. + as_bad(_("invalid register list `%s'"), str);
  6002. + return -2;
  6003. + }
  6004. +
  6005. + c = *p, *p = 0;
  6006. + regid = avr32_parse_intreg(str);
  6007. + *p = c;
  6008. +
  6009. + if (regid != 12)
  6010. + {
  6011. + as_bad(_("invalid register list `%s'"), str);
  6012. + return -2;
  6013. + }
  6014. +
  6015. + /* If we have an assignment, we must pop PC and we must _not_
  6016. + pop LR or R12 */
  6017. + if (!(regmask & (1 << AVR32_REG_PC)))
  6018. + {
  6019. + as_bad(_("return value specified for non-return instruction"));
  6020. + return -2;
  6021. + }
  6022. + else if (regmask & ((1 << AVR32_REG_R12) | (1 << AVR32_REG_LR)))
  6023. + {
  6024. + as_bad(_("can't pop LR or R12 when specifying return value"));
  6025. + return -2;
  6026. + }
  6027. +
  6028. + save = input_line_pointer;
  6029. + input_line_pointer = p + 1;
  6030. + expression(&exp);
  6031. + input_line_pointer = save;
  6032. +
  6033. + if (exp.X_op != O_constant
  6034. + || exp.X_add_number < -1
  6035. + || exp.X_add_number > 1)
  6036. + {
  6037. + as_bad(_("invalid return value `%s'"), str);
  6038. + return -2;
  6039. + }
  6040. +
  6041. + return exp.X_add_number;
  6042. +}
  6043. +
  6044. +static void
  6045. +parse_reglist9(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6046. + char *str, int opindex ATTRIBUTE_UNUSED)
  6047. +{
  6048. + unsigned long regmask;
  6049. + unsigned long value = 0, kbit = 0;
  6050. + int slot;
  6051. + char *tail;
  6052. +
  6053. + regmask = avr32_parse_reglist(str, &tail);
  6054. + /* printf("parsed reglist16: %04lx, tail: `%s'\n", regmask, tail); */
  6055. + if (*tail)
  6056. + {
  6057. + int retval;
  6058. +
  6059. + retval = parse_reglist_tail(tail, regmask);
  6060. +
  6061. + switch (retval)
  6062. + {
  6063. + case -1:
  6064. + regmask |= 1 << AVR32_REG_LR;
  6065. + break;
  6066. + case 0:
  6067. + break;
  6068. + case 1:
  6069. + regmask |= 1 << AVR32_REG_R12;
  6070. + break;
  6071. + default:
  6072. + break;
  6073. + }
  6074. +
  6075. + kbit = 1;
  6076. + }
  6077. +
  6078. + if (avr32_make_regmask8(regmask, &value))
  6079. + as_bad(_("register list `%s' doesn't fit"), str);
  6080. +
  6081. +
  6082. + slot = current_insn.next_slot++;
  6083. + current_insn.field_value[slot].value = (value << 1) | kbit;
  6084. +}
  6085. +
  6086. +static void
  6087. +parse_reglist16(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6088. + char *str, int opindex ATTRIBUTE_UNUSED)
  6089. +{
  6090. + unsigned long regmask;
  6091. + int slot;
  6092. + char *tail;
  6093. +
  6094. + regmask = avr32_parse_reglist(str, &tail);
  6095. + if (*tail)
  6096. + as_bad(_("invalid register list `%s'"), str);
  6097. +
  6098. + slot = current_insn.next_slot++;
  6099. + current_insn.field_value[slot].value = regmask;
  6100. +}
  6101. +
  6102. +static void
  6103. +parse_reglist_ldm(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6104. + char *str, int opindex ATTRIBUTE_UNUSED)
  6105. +{
  6106. + unsigned long regmask;
  6107. + int slot, rp, w_bit = 0;
  6108. + char *tail, *p, c;
  6109. +
  6110. + for (p = str; *p && *p != ','; p++)
  6111. + if (*p == '+')
  6112. + break;
  6113. +
  6114. + c = *p, *p = 0;
  6115. + rp = avr32_parse_intreg(str);
  6116. + *p = c;
  6117. + if (rp < 0)
  6118. + {
  6119. + as_bad(_("invalid destination register in `%s'"), str);
  6120. + return;
  6121. + }
  6122. +
  6123. + if (p[0] == '+' && p[1] == '+')
  6124. + {
  6125. + w_bit = 1;
  6126. + p += 2;
  6127. + }
  6128. +
  6129. + if (*p != ',')
  6130. + {
  6131. + as_bad(_("expected `,' after destination register in `%s'"), str);
  6132. + return;
  6133. + }
  6134. +
  6135. + str = p + 1;
  6136. + regmask = avr32_parse_reglist(str, &tail);
  6137. + if (*tail)
  6138. + {
  6139. + int retval;
  6140. +
  6141. + if (rp != AVR32_REG_SP)
  6142. + {
  6143. + as_bad(_("junk at end of line: `%s'"), tail);
  6144. + return;
  6145. + }
  6146. +
  6147. + rp = AVR32_REG_PC;
  6148. +
  6149. + retval = parse_reglist_tail(tail, regmask);
  6150. +
  6151. + switch (retval)
  6152. + {
  6153. + case -1:
  6154. + regmask |= 1 << AVR32_REG_LR;
  6155. + break;
  6156. + case 0:
  6157. + break;
  6158. + case 1:
  6159. + regmask |= 1 << AVR32_REG_R12;
  6160. + break;
  6161. + default:
  6162. + return;
  6163. + }
  6164. + }
  6165. +
  6166. + slot = current_insn.next_slot++;
  6167. + current_insn.field_value[slot].value = rp;
  6168. + slot = current_insn.next_slot++;
  6169. + current_insn.field_value[slot].value = w_bit;
  6170. + slot = current_insn.next_slot++;
  6171. + current_insn.field_value[slot].value = regmask;
  6172. +}
  6173. +
  6174. +static void
  6175. +parse_reglist_cp8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6176. + char *str, int opindex ATTRIBUTE_UNUSED)
  6177. +{
  6178. + unsigned long regmask;
  6179. + int slot, h_bit = 0;
  6180. + char *tail;
  6181. +
  6182. + regmask = avr32_parse_cpreglist(str, &tail);
  6183. + if (*tail)
  6184. + as_bad(_("junk at end of line: `%s'"), tail);
  6185. + else if (regmask & 0xffUL)
  6186. + {
  6187. + if (regmask & 0xff00UL)
  6188. + as_bad(_("register list `%s' doesn't fit"), str);
  6189. + regmask &= 0xff;
  6190. + }
  6191. + else if (regmask & 0xff00UL)
  6192. + {
  6193. + regmask >>= 8;
  6194. + h_bit = 1;
  6195. + }
  6196. + else
  6197. + as_warn(_("register list is empty"));
  6198. +
  6199. + slot = current_insn.next_slot++;
  6200. + current_insn.field_value[slot].value = regmask;
  6201. + slot = current_insn.next_slot++;
  6202. + current_insn.field_value[slot].value = h_bit;
  6203. +}
  6204. +
  6205. +static void
  6206. +parse_reglist_cpd8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6207. + char *str, int opindex ATTRIBUTE_UNUSED)
  6208. +{
  6209. + unsigned long regmask, regmask_d = 0;
  6210. + int slot, i;
  6211. + char *tail;
  6212. +
  6213. + regmask = avr32_parse_cpreglist(str, &tail);
  6214. + if (*tail)
  6215. + as_bad(_("junk at end of line: `%s'"), tail);
  6216. +
  6217. + for (i = 0; i < 8; i++)
  6218. + {
  6219. + if (regmask & 1)
  6220. + {
  6221. + if (!(regmask & 2))
  6222. + {
  6223. + as_bad(_("register list `%s' doesn't fit"), str);
  6224. + break;
  6225. + }
  6226. + regmask_d |= 1 << i;
  6227. + }
  6228. + else if (regmask & 2)
  6229. + {
  6230. + as_bad(_("register list `%s' doesn't fit"), str);
  6231. + break;
  6232. + }
  6233. +
  6234. + regmask >>= 2;
  6235. + }
  6236. +
  6237. + slot = current_insn.next_slot++;
  6238. + current_insn.field_value[slot].value = regmask_d;
  6239. +}
  6240. +
  6241. +static void
  6242. +parse_retval(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6243. + char *str, int opindex ATTRIBUTE_UNUSED)
  6244. +{
  6245. + int regid, slot;
  6246. +
  6247. + regid = avr32_parse_intreg(str);
  6248. + if (regid < 0)
  6249. + {
  6250. + expressionS exp;
  6251. + char *save;
  6252. +
  6253. + regid = 0;
  6254. +
  6255. + save = input_line_pointer;
  6256. + input_line_pointer = str;
  6257. + expression(&exp);
  6258. + input_line_pointer = save;
  6259. +
  6260. + if (exp.X_op != O_constant)
  6261. + as_bad(_("invalid return value `%s'"), str);
  6262. + else
  6263. + switch (exp.X_add_number)
  6264. + {
  6265. + case -1:
  6266. + regid = AVR32_REG_LR;
  6267. + break;
  6268. + case 0:
  6269. + regid = AVR32_REG_SP;
  6270. + break;
  6271. + case 1:
  6272. + regid = AVR32_REG_PC;
  6273. + break;
  6274. + default:
  6275. + as_bad(_("invalid return value `%s'"), str);
  6276. + break;
  6277. + }
  6278. + }
  6279. +
  6280. + slot = current_insn.next_slot++;
  6281. + current_insn.field_value[slot].value = regid;
  6282. +}
  6283. +
  6284. +#define parse_mcall parse_intreg_disp
  6285. +
  6286. +static void
  6287. +parse_jospinc(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6288. + char *str, int opindex ATTRIBUTE_UNUSED)
  6289. +{
  6290. + expressionS exp;
  6291. + int slot;
  6292. + char *save;
  6293. +
  6294. + save = input_line_pointer;
  6295. + input_line_pointer = str;
  6296. + expression(&exp);
  6297. + input_line_pointer = save;
  6298. +
  6299. + slot = current_insn.next_slot++;
  6300. +
  6301. + if (exp.X_op == O_constant)
  6302. + {
  6303. + if (exp.X_add_number > 0)
  6304. + exp.X_add_number--;
  6305. + current_insn.field_value[slot].value = exp.X_add_number;
  6306. + }
  6307. + else
  6308. + as_bad(_("invalid numeric expression `%s'"), str);
  6309. +}
  6310. +
  6311. +#define parse_coh parse_nothing
  6312. +#if 0
  6313. +static void
  6314. +parse_fpreg(const struct avr32_operand *op,
  6315. + char *str, int opindex ATTRIBUTE_UNUSED)
  6316. +{
  6317. + unsigned long regid;
  6318. + int slot;
  6319. +
  6320. + regid = strtoul(str + 2, NULL, 10);
  6321. +
  6322. + if ((regid >= 16) || (regid & ((1 << op->align_order) - 1)))
  6323. + as_bad(_("invalid floating-point register `%s'"), str);
  6324. +
  6325. + slot = current_insn.next_slot++;
  6326. + current_insn.field_value[slot].value = regid;
  6327. + current_insn.field_value[slot].align_order = op->align_order;
  6328. +}
  6329. +#endif
  6330. +
  6331. +static void
  6332. +parse_picoreg(const struct avr32_operand *op,
  6333. + char *str, int opindex ATTRIBUTE_UNUSED)
  6334. +{
  6335. + unsigned long regid;
  6336. + int slot;
  6337. +
  6338. + regid = avr32_parse_picoreg(str);
  6339. + if (regid & ((1 << op->align_order) - 1))
  6340. + as_bad(_("invalid double-word PiCo register `%s'"), str);
  6341. +
  6342. + slot = current_insn.next_slot++;
  6343. + current_insn.field_value[slot].value = regid;
  6344. + current_insn.field_value[slot].align_order = op->align_order;
  6345. +}
  6346. +
  6347. +static void
  6348. +parse_pico_reglist_w(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6349. + char *str, int opindex ATTRIBUTE_UNUSED)
  6350. +{
  6351. + unsigned long regmask;
  6352. + int slot, h_bit = 0;
  6353. + char *tail;
  6354. +
  6355. + regmask = avr32_parse_pico_reglist(str, &tail);
  6356. + if (*tail)
  6357. + as_bad(_("junk at end of line: `%s'"), tail);
  6358. +
  6359. + if (regmask & 0x00ffUL)
  6360. + {
  6361. + if (regmask & 0xff00UL)
  6362. + as_bad(_("register list `%s' doesn't fit"), str);
  6363. + regmask &= 0x00ffUL;
  6364. + }
  6365. + else if (regmask & 0xff00UL)
  6366. + {
  6367. + regmask >>= 8;
  6368. + h_bit = 1;
  6369. + }
  6370. + else
  6371. + as_warn(_("register list is empty"));
  6372. +
  6373. + slot = current_insn.next_slot++;
  6374. + current_insn.field_value[slot].value = regmask;
  6375. + slot = current_insn.next_slot++;
  6376. + current_insn.field_value[slot].value = h_bit;
  6377. +}
  6378. +
  6379. +static void
  6380. +parse_pico_reglist_d(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6381. + char *str, int opindex ATTRIBUTE_UNUSED)
  6382. +{
  6383. + unsigned long regmask, regmask_d = 0;
  6384. + int slot, i;
  6385. + char *tail;
  6386. +
  6387. + regmask = avr32_parse_pico_reglist(str, &tail);
  6388. + if (*tail)
  6389. + as_bad(_("junk at end of line: `%s'"), tail);
  6390. +
  6391. + for (i = 0; i < 8; i++)
  6392. + {
  6393. + if (regmask & 1)
  6394. + {
  6395. + if (!(regmask & 2))
  6396. + {
  6397. + as_bad(_("register list `%s' doesn't fit"), str);
  6398. + break;
  6399. + }
  6400. + regmask_d |= 1 << i;
  6401. + }
  6402. + else if (regmask & 2)
  6403. + {
  6404. + as_bad(_("register list `%s' doesn't fit"), str);
  6405. + break;
  6406. + }
  6407. +
  6408. + regmask >>= 2;
  6409. + }
  6410. +
  6411. + slot = current_insn.next_slot++;
  6412. + current_insn.field_value[slot].value = regmask_d;
  6413. +}
  6414. +
  6415. +static void
  6416. +parse_pico_in(const struct avr32_operand *op ATTRIBUTE_UNUSED,
  6417. + char *str, int opindex ATTRIBUTE_UNUSED)
  6418. +{
  6419. + unsigned long regid;
  6420. + int slot;
  6421. +
  6422. + regid = strtoul(str + 2, NULL, 10);
  6423. +
  6424. + if (regid >= 12)
  6425. + as_bad(_("invalid PiCo IN register `%s'"), str);
  6426. +
  6427. + slot = current_insn.next_slot++;
  6428. + current_insn.field_value[slot].value = regid;
  6429. + current_insn.field_value[slot].align_order = 0;
  6430. +}
  6431. +
  6432. +#define parse_pico_out0 parse_nothing
  6433. +#define parse_pico_out1 parse_nothing
  6434. +#define parse_pico_out2 parse_nothing
  6435. +#define parse_pico_out3 parse_nothing
  6436. +
  6437. +#define OP(name, sgn, pcrel, align, func) \
  6438. + { AVR32_OPERAND_##name, sgn, pcrel, align, match_##func, parse_##func }
  6439. +
  6440. +struct avr32_operand avr32_operand_table[] = {
  6441. + OP(INTREG, 0, 0, 0, intreg),
  6442. + OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
  6443. + OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
  6444. + OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
  6445. + OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
  6446. + OP(INTREG_BSEL, 0, 0, 0, intreg_part),
  6447. + OP(INTREG_HSEL, 0, 0, 1, intreg_part),
  6448. + OP(INTREG_SDISP, 1, 0, 0, intreg_disp),
  6449. + OP(INTREG_SDISP_H, 1, 0, 1, intreg_disp),
  6450. + OP(INTREG_SDISP_W, 1, 0, 2, intreg_disp),
  6451. + OP(INTREG_UDISP, 0, 0, 0, intreg_disp),
  6452. + OP(INTREG_UDISP_H, 0, 0, 1, intreg_disp),
  6453. + OP(INTREG_UDISP_W, 0, 0, 2, intreg_disp),
  6454. + OP(INTREG_INDEX, 0, 0, 0, intreg_index),
  6455. + OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
  6456. + OP(DWREG, 0, 0, 1, intreg),
  6457. + OP(PC_UDISP_W, 0, 1, 2, pc_disp),
  6458. + OP(SP, 0, 0, 0, sp),
  6459. + OP(SP_UDISP_W, 0, 0, 2, sp_disp),
  6460. + OP(CPNO, 0, 0, 0, cpno),
  6461. + OP(CPREG, 0, 0, 0, cpreg),
  6462. + OP(CPREG_D, 0, 0, 1, cpreg),
  6463. + OP(UNSIGNED_CONST, 0, 0, 0, const),
  6464. + OP(UNSIGNED_CONST_W, 0, 0, 2, const),
  6465. + OP(SIGNED_CONST, 1, 0, 0, const),
  6466. + OP(SIGNED_CONST_W, 1, 0, 2, const),
  6467. + OP(JMPLABEL, 1, 1, 1, jmplabel),
  6468. + OP(UNSIGNED_NUMBER, 0, 0, 0, number),
  6469. + OP(UNSIGNED_NUMBER_W, 0, 0, 2, number),
  6470. + OP(REGLIST8, 0, 0, 0, reglist8),
  6471. + OP(REGLIST9, 0, 0, 0, reglist9),
  6472. + OP(REGLIST16, 0, 0, 0, reglist16),
  6473. + OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
  6474. + OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
  6475. + OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
  6476. + OP(RETVAL, 0, 0, 0, retval),
  6477. + OP(MCALL, 1, 0, 2, mcall),
  6478. + OP(JOSPINC, 0, 0, 0, jospinc),
  6479. + OP(COH, 0, 0, 0, coh),
  6480. + OP(PICO_REG_W, 0, 0, 0, picoreg),
  6481. + OP(PICO_REG_D, 0, 0, 1, picoreg),
  6482. + OP(PICO_REGLIST_W, 0, 0, 0, pico_reglist_w),
  6483. + OP(PICO_REGLIST_D, 0, 0, 0, pico_reglist_d),
  6484. + OP(PICO_IN, 0, 0, 0, pico_in),
  6485. + OP(PICO_OUT0, 0, 0, 0, pico_out0),
  6486. + OP(PICO_OUT1, 0, 0, 0, pico_out1),
  6487. + OP(PICO_OUT2, 0, 0, 0, pico_out2),
  6488. + OP(PICO_OUT3, 0, 0, 0, pico_out3),
  6489. +};
  6490. +
  6491. +symbolS *
  6492. +md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
  6493. +{
  6494. + pr_debug("md_undefined_symbol: %s\n", name);
  6495. + return 0;
  6496. +}
  6497. +
  6498. +struct avr32_relax_type
  6499. +{
  6500. + long lower_bound;
  6501. + long upper_bound;
  6502. + unsigned char align;
  6503. + unsigned char length;
  6504. + signed short next;
  6505. +};
  6506. +
  6507. +#define EMPTY { 0, 0, 0, 0, -1 }
  6508. +#define C(lower, upper, align, next) \
  6509. + { (lower), (upper), (align), 2, AVR32_OPC_##next }
  6510. +#define E(lower, upper, align) \
  6511. + { (lower), (upper), (align), 4, -1 }
  6512. +
  6513. +static const struct avr32_relax_type avr32_relax_table[] =
  6514. + {
  6515. + /* 0 */
  6516. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6517. + EMPTY, EMPTY, EMPTY,
  6518. + E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0),
  6519. + EMPTY,
  6520. + /* 16 */
  6521. + EMPTY, EMPTY, EMPTY, EMPTY,
  6522. +
  6523. + C(-256, 254, 1, BREQ2), C(-256, 254, 1, BRNE2),
  6524. + C(-256, 254, 1, BRCC2), C(-256, 254, 1, BRCS2),
  6525. + C(-256, 254, 1, BRGE2), C(-256, 254, 1, BRLT2),
  6526. + C(-256, 254, 1, BRMI2), C(-256, 254, 1, BRPL2),
  6527. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6528. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6529. + /* 32 */
  6530. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6531. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6532. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6533. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6534. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6535. + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
  6536. +
  6537. + EMPTY, EMPTY, EMPTY, EMPTY,
  6538. + /* 48 */
  6539. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6540. + EMPTY, EMPTY, EMPTY,
  6541. +
  6542. + C(-32, 31, 0, CP_W3), E(-1048576, 1048575, 0),
  6543. +
  6544. + EMPTY, EMPTY, EMPTY,
  6545. + /* 64: csrfcz */
  6546. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6547. + E(0, 65535, 0), E(0, 65535, 0),
  6548. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6549. + E(-32768, 32767, 0),
  6550. + /* 80: LD_SB2 */
  6551. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6552. +
  6553. + C(0, 7, 0, LD_UB4), E(-32768, 32767, 0),
  6554. +
  6555. + EMPTY,
  6556. + EMPTY, EMPTY,
  6557. +
  6558. + C(0, 14, 1, LD_SH4), E(-32768, 32767, 0),
  6559. +
  6560. + EMPTY, EMPTY, EMPTY,
  6561. +
  6562. + C(0, 14, 1, LD_UH4),
  6563. +
  6564. + /* 96: LD_UH4 */
  6565. + E(-32768, 32767, 0),
  6566. +
  6567. + EMPTY, EMPTY, EMPTY, EMPTY,
  6568. +
  6569. + C(0, 124, 2, LD_W4), E(-32768, 32767, 0),
  6570. +
  6571. + E(0, 1020, 2), /* LDC_D1 */
  6572. + EMPTY, EMPTY,
  6573. + E(0, 1020, 2), /* LDC_W1 */
  6574. + EMPTY, EMPTY,
  6575. + E(0, 16380, 2), /* LDC0_D */
  6576. + E(0, 16380, 2), /* LDC0_W */
  6577. + EMPTY,
  6578. +
  6579. + /* 112: LDCM_D_PU */
  6580. + EMPTY, EMPTY, EMPTY,
  6581. +
  6582. + C(0, 508, 2, LDDPC_EXT), E(-32768, 32767, 0),
  6583. +
  6584. + EMPTY,EMPTY, EMPTY,
  6585. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6586. +
  6587. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6588. + /* 134: MACHH_W */
  6589. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6590. + E(-131072, 131068, 2), /* MCALL */
  6591. + E(0, 1020, 2), /* MFDR */
  6592. + E(0, 1020, 2), /* MFSR */
  6593. + EMPTY, EMPTY,
  6594. +
  6595. + C(-128, 127, 0, MOV2), E(-1048576, 1048575, 0),
  6596. +
  6597. + EMPTY, EMPTY, EMPTY,
  6598. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6599. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6600. +
  6601. + E(-128, 127, 0), /* MOVEQ2 */
  6602. + E(-128, 127, 0), /* MOVNE2 */
  6603. + E(-128, 127, 0), /* MOVCC2 */
  6604. + E(-128, 127, 0), /* 166: MOVCS2 */
  6605. + E(-128, 127, 0), /* MOVGE2 */
  6606. + E(-128, 127, 0), /* MOVLT2 */
  6607. + E(-128, 127, 0), /* MOVMI2 */
  6608. + E(-128, 127, 0), /* MOVPL2 */
  6609. + E(-128, 127, 0), /* MOVLS2 */
  6610. + E(-128, 127, 0), /* MOVGT2 */
  6611. + E(-128, 127, 0), /* MOVLE2 */
  6612. + E(-128, 127, 0), /* MOVHI2 */
  6613. + E(-128, 127, 0), /* MOVVS2 */
  6614. + E(-128, 127, 0), /* MOVVC2 */
  6615. + E(-128, 127, 0), /* MOVQS2 */
  6616. + E(-128, 127, 0), /* MOVAL2 */
  6617. +
  6618. + E(0, 1020, 2), /* MTDR */
  6619. + E(0, 1020, 2), /* MTSR */
  6620. + EMPTY,
  6621. + EMPTY,
  6622. + E(-128, 127, 0), /* MUL3 */
  6623. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6624. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6625. + /* 198: MVCR_W */
  6626. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6627. + E(0, 65535, 0), E(0, 65535, 0),
  6628. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6629. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6630. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6631. + /* 230: PASR_H */
  6632. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6633. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6634. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6635. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6636. + /* 262: PUNPCKSB_H */
  6637. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6638. +
  6639. + C(-1024, 1022, 1, RCALL2), E(-2097152, 2097150, 1),
  6640. +
  6641. + EMPTY,
  6642. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6643. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6644. + EMPTY, EMPTY, EMPTY,
  6645. +
  6646. + C(-1024, 1022, 1, BRAL),
  6647. +
  6648. + EMPTY, EMPTY, EMPTY,
  6649. + E(-128, 127, 0), /* RSUB2 */
  6650. + /* 294: SATADD_H */
  6651. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6652. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6653. + E(0, 255, 0), /* SLEEP */
  6654. + EMPTY, EMPTY,
  6655. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6656. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6657. + /* 326: ST_B2 */
  6658. + EMPTY, EMPTY,
  6659. + C(0, 7, 0, ST_B4), E(-32768, 32767, 0),
  6660. + EMPTY, EMPTY, EMPTY, EMPTY,
  6661. + E(-32768, 32767, 0),
  6662. + EMPTY, EMPTY, EMPTY,
  6663. + C(0, 14, 1, ST_H4), E(-32768, 32767, 0),
  6664. + EMPTY, EMPTY,
  6665. + EMPTY,
  6666. + C(0, 60, 2, ST_W4), E(-32768, 32767, 0),
  6667. + E(0, 1020, 2), /* STC_D1 */
  6668. + EMPTY, EMPTY,
  6669. + E(0, 1020, 2), /* STC_W1 */
  6670. + EMPTY, EMPTY,
  6671. + E(0, 16380, 2), /* STC0_D */
  6672. + E(0, 16380, 2), /* STC0_W */
  6673. +
  6674. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6675. + /* 358: STDSP */
  6676. + EMPTY, EMPTY,
  6677. + E(0, 1020, 2), /* STHH_W1 */
  6678. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6679. + EMPTY, EMPTY, EMPTY,
  6680. + E(-32768, 32767, 0),
  6681. + C(-512, 508, 2, SUB4),
  6682. + C(-128, 127, 0, SUB4), E(-1048576, 1048576, 0),
  6683. + /* SUB{cond} */
  6684. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6685. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6686. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6687. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6688. + /* SUBF{cond} */
  6689. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6690. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6691. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6692. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6693. + EMPTY,
  6694. +
  6695. + /* 406: SWAP_B */
  6696. + EMPTY, EMPTY, EMPTY,
  6697. + E(0, 255, 0), /* SYNC */
  6698. + EMPTY, EMPTY, EMPTY, EMPTY,
  6699. + /* 414: TST */
  6700. + EMPTY, EMPTY, E(-65536, 65535, 2), E(-65536, 65535, 2), E(-65536, 65535, 2), EMPTY, EMPTY, EMPTY,
  6701. + /* 422: RSUB{cond} */
  6702. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6703. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6704. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6705. + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
  6706. + /* 436: ADD{cond} */
  6707. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6708. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6709. + /* 454: SUB{cond} */
  6710. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6711. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6712. + /* 472: AND{cond} */
  6713. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6714. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6715. + /* 486: OR{cond} */
  6716. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6717. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6718. + /* 502: EOR{cond} */
  6719. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6720. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6721. + /* 518: LD.w{cond} */
  6722. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6723. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6724. + /* 534: LD.sh{cond} */
  6725. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6726. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6727. + /* 550: LD.uh{cond} */
  6728. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6729. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6730. + /* 566: LD.sb{cond} */
  6731. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6732. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6733. + /* 582: LD.ub{cond} */
  6734. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6735. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6736. + /* 596: ST.w{cond} */
  6737. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6738. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6739. + /* 614: ST.h{cond} */
  6740. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6741. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6742. + /* 630: ST.b{cond} */
  6743. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6744. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6745. + /* 646: movh */
  6746. + E(0, 65535, 0), EMPTY, EMPTY,
  6747. + /* 649: fmac.s */
  6748. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6749. + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
  6750. + };
  6751. +
  6752. +#undef E
  6753. +#undef C
  6754. +#undef EMPTY
  6755. +
  6756. +#define AVR32_RS_NONE (-1)
  6757. +
  6758. +#define avr32_rs_size(state) (avr32_relax_table[(state)].length)
  6759. +#define avr32_rs_align(state) (avr32_relax_table[(state)].align)
  6760. +#define relax_more(state) (avr32_relax_table[(state)].next)
  6761. +
  6762. +#define opc_initial_substate(opc) ((opc)->id)
  6763. +
  6764. +static int need_relax(int subtype, offsetT distance)
  6765. +{
  6766. + offsetT upper_bound, lower_bound;
  6767. +
  6768. + upper_bound = avr32_relax_table[subtype].upper_bound;
  6769. + lower_bound = avr32_relax_table[subtype].lower_bound;
  6770. +
  6771. + if (distance & ((1 << avr32_rs_align(subtype)) - 1))
  6772. + return 1;
  6773. + if ((distance > upper_bound) || (distance < lower_bound))
  6774. + return 1;
  6775. +
  6776. + return 0;
  6777. +}
  6778. +
  6779. +enum {
  6780. + LDA_SUBTYPE_MOV1,
  6781. + LDA_SUBTYPE_MOV2,
  6782. + LDA_SUBTYPE_SUB,
  6783. + LDA_SUBTYPE_LDDPC,
  6784. + LDA_SUBTYPE_LDW,
  6785. + LDA_SUBTYPE_GOTLOAD,
  6786. + LDA_SUBTYPE_GOTLOAD_LARGE,
  6787. +};
  6788. +
  6789. +enum {
  6790. + CALL_SUBTYPE_RCALL1,
  6791. + CALL_SUBTYPE_RCALL2,
  6792. + CALL_SUBTYPE_MCALL_CP,
  6793. + CALL_SUBTYPE_MCALL_GOT,
  6794. + CALL_SUBTYPE_MCALL_LARGE,
  6795. +};
  6796. +
  6797. +#define LDA_INITIAL_SIZE (avr32_pic ? 4 : 2)
  6798. +#define CALL_INITIAL_SIZE 2
  6799. +
  6800. +#define need_reloc(sym, seg, pcrel) \
  6801. + (!(S_IS_DEFINED(sym) \
  6802. + && ((pcrel && S_GET_SEGMENT(sym) == seg) \
  6803. + || (!pcrel && S_GET_SEGMENT(sym) == absolute_section))) \
  6804. + || S_FORCE_RELOC(sym, 1))
  6805. +
  6806. +/* Return an initial guess of the length by which a fragment must grow to
  6807. + hold a branch to reach its destination.
  6808. + Also updates fr_type/fr_subtype as necessary.
  6809. +
  6810. + Called just before doing relaxation.
  6811. + Any symbol that is now undefined will not become defined.
  6812. + The guess for fr_var is ACTUALLY the growth beyond fr_fix.
  6813. + Whatever we do to grow fr_fix or fr_var contributes to our returned value.
  6814. + Although it may not be explicit in the frag, pretend fr_var starts with a
  6815. + 0 value. */
  6816. +
  6817. +static int
  6818. +avr32_default_estimate_size_before_relax (fragS *fragP, segT segment)
  6819. +{
  6820. + int growth = 0;
  6821. +
  6822. + assert(fragP);
  6823. + assert(fragP->fr_symbol);
  6824. +
  6825. + if (fragP->tc_frag_data.force_extended
  6826. + || need_reloc(fragP->fr_symbol, segment, fragP->tc_frag_data.pcrel))
  6827. + {
  6828. + int largest_state = fragP->fr_subtype;
  6829. + while (relax_more(largest_state) != AVR32_RS_NONE)
  6830. + largest_state = relax_more(largest_state);
  6831. + growth = avr32_rs_size(largest_state) - fragP->fr_var;
  6832. + }
  6833. + else
  6834. + {
  6835. + growth = avr32_rs_size(fragP->fr_subtype) - fragP->fr_var;
  6836. + }
  6837. +
  6838. + pr_debug("%s:%d: md_estimate_size_before_relax: %d\n",
  6839. + fragP->fr_file, fragP->fr_line, growth);
  6840. +
  6841. + return growth;
  6842. +}
  6843. +
  6844. +static int
  6845. +avr32_lda_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
  6846. +{
  6847. + return fragP->fr_var - LDA_INITIAL_SIZE;
  6848. +}
  6849. +
  6850. +static int
  6851. +avr32_call_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
  6852. +{
  6853. + return fragP->fr_var - CALL_INITIAL_SIZE;
  6854. +}
  6855. +
  6856. +static int
  6857. +avr32_cpool_estimate_size_before_relax(fragS *fragP,
  6858. + segT segment ATTRIBUTE_UNUSED)
  6859. +{
  6860. + return fragP->fr_var;
  6861. +}
  6862. +
  6863. +/* This macro may be defined to relax a frag. GAS will call this with the
  6864. + * segment, the frag, and the change in size of all previous frags;
  6865. + * md_relax_frag should return the change in size of the frag. */
  6866. +static long
  6867. +avr32_default_relax_frag (segT segment, fragS *fragP, long stretch)
  6868. +{
  6869. + int state, next_state;
  6870. + symbolS *symbolP; /* The target symbol */
  6871. + long growth = 0;
  6872. +
  6873. + state = next_state = fragP->fr_subtype;
  6874. +
  6875. + symbolP = fragP->fr_symbol;
  6876. +
  6877. + if (fragP->tc_frag_data.force_extended
  6878. + || need_reloc(symbolP, segment, fragP->tc_frag_data.pcrel))
  6879. + {
  6880. + /* Symbol must be resolved by the linker. Emit the largest
  6881. + possible opcode. */
  6882. + while (relax_more(next_state) != AVR32_RS_NONE)
  6883. + next_state = relax_more(next_state);
  6884. + }
  6885. + else
  6886. + {
  6887. + addressT address; /* The address of fragP */
  6888. + addressT target; /* The address of the target symbol */
  6889. + offsetT distance; /* The distance between the insn and the symbol */
  6890. + fragS *sym_frag;
  6891. +
  6892. + address = fragP->fr_address;
  6893. + target = fragP->fr_offset;
  6894. + symbolP = fragP->fr_symbol;
  6895. + sym_frag = symbol_get_frag(symbolP);
  6896. +
  6897. + address += fragP->fr_fix - fragP->fr_var;
  6898. + target += S_GET_VALUE(symbolP);
  6899. +
  6900. + if (stretch != 0
  6901. + && sym_frag->relax_marker != fragP->relax_marker
  6902. + && S_GET_SEGMENT(symbolP) == segment)
  6903. + /* if it was correctly aligned before, make sure it stays aligned */
  6904. + target += stretch & (~0UL << avr32_rs_align(state));
  6905. +
  6906. + if (fragP->tc_frag_data.pcrel)
  6907. + distance = target - (address & (~0UL << avr32_rs_align(state)));
  6908. + else
  6909. + distance = target;
  6910. +
  6911. + pr_debug("%s:%d: relax more? 0x%x - 0x%x = 0x%x (%d), align %d\n",
  6912. + fragP->fr_file, fragP->fr_line, target, address,
  6913. + distance, distance, avr32_rs_align(state));
  6914. +
  6915. + if (need_relax(state, distance))
  6916. + {
  6917. + if (relax_more(state) != AVR32_RS_NONE)
  6918. + next_state = relax_more(state);
  6919. + pr_debug("%s:%d: relax more %d -> %d (%d - %d, align %d)\n",
  6920. + fragP->fr_file, fragP->fr_line, state, next_state,
  6921. + target, address, avr32_rs_align(state));
  6922. + }
  6923. + }
  6924. +
  6925. + growth = avr32_rs_size(next_state) - avr32_rs_size(state);
  6926. + fragP->fr_subtype = next_state;
  6927. +
  6928. + pr_debug("%s:%d: md_relax_frag: growth=%d, subtype=%d, opc=0x%08lx\n",
  6929. + fragP->fr_file, fragP->fr_line, growth, fragP->fr_subtype,
  6930. + avr32_opc_table[next_state].value);
  6931. +
  6932. + return growth;
  6933. +}
  6934. +
  6935. +static long
  6936. +avr32_lda_relax_frag(segT segment, fragS *fragP, long stretch)
  6937. +{
  6938. + struct cpool *pool= NULL;
  6939. + unsigned int entry = 0;
  6940. + addressT address, target;
  6941. + offsetT distance;
  6942. + symbolS *symbolP;
  6943. + fragS *sym_frag;
  6944. + long old_size, new_size;
  6945. +
  6946. + symbolP = fragP->fr_symbol;
  6947. + old_size = fragP->fr_var;
  6948. + if (!avr32_pic)
  6949. + {
  6950. + pool = fragP->tc_frag_data.pool;
  6951. + entry = fragP->tc_frag_data.pool_entry;
  6952. + }
  6953. +
  6954. + address = fragP->fr_address;
  6955. + address += fragP->fr_fix - LDA_INITIAL_SIZE;
  6956. +
  6957. + if (!S_IS_DEFINED(symbolP) || S_FORCE_RELOC(symbolP, 1))
  6958. + goto relax_max;
  6959. +
  6960. + target = fragP->fr_offset;
  6961. + sym_frag = symbol_get_frag(symbolP);
  6962. + target += S_GET_VALUE(symbolP);
  6963. +
  6964. + if (sym_frag->relax_marker != fragP->relax_marker
  6965. + && S_GET_SEGMENT(symbolP) == segment)
  6966. + target += stretch;
  6967. +
  6968. + distance = target - address;
  6969. +
  6970. + pr_debug("lda_relax_frag: target: %d, address: %d, var: %d\n",
  6971. + target, address, fragP->fr_var);
  6972. +
  6973. + if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
  6974. + && target <= 127 && (offsetT)target >= -128)
  6975. + {
  6976. + if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
  6977. + || fragP->fr_subtype == LDA_SUBTYPE_LDW)
  6978. + pool->literals[entry].refcount--;
  6979. + new_size = 2;
  6980. + fragP->fr_subtype = LDA_SUBTYPE_MOV1;
  6981. + }
  6982. + else if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
  6983. + && target <= 1048575 && (offsetT)target >= -1048576)
  6984. + {
  6985. + if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
  6986. + || fragP->fr_subtype == LDA_SUBTYPE_LDW)
  6987. + pool->literals[entry].refcount--;
  6988. + new_size = 4;
  6989. + fragP->fr_subtype = LDA_SUBTYPE_MOV2;
  6990. + }
  6991. + else if (!linkrelax && S_GET_SEGMENT(symbolP) == segment
  6992. + /* the field will be negated, so this is really -(-32768)
  6993. + and -(32767) */
  6994. + && distance <= 32768 && distance >= -32767)
  6995. + {
  6996. + if (!avr32_pic
  6997. + && (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
  6998. + || fragP->fr_subtype == LDA_SUBTYPE_LDW))
  6999. + pool->literals[entry].refcount--;
  7000. + new_size = 4;
  7001. + fragP->fr_subtype = LDA_SUBTYPE_SUB;
  7002. + }
  7003. + else
  7004. + {
  7005. + relax_max:
  7006. + if (avr32_pic)
  7007. + {
  7008. + if (linkrelax)
  7009. + {
  7010. + new_size = 8;
  7011. + fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD_LARGE;
  7012. + }
  7013. + else
  7014. + {
  7015. + new_size = 4;
  7016. + fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD;
  7017. + }
  7018. + }
  7019. + else
  7020. + {
  7021. + if (fragP->fr_subtype != LDA_SUBTYPE_LDDPC
  7022. + && fragP->fr_subtype != LDA_SUBTYPE_LDW)
  7023. + pool->literals[entry].refcount++;
  7024. +
  7025. + sym_frag = symbol_get_frag(pool->symbol);
  7026. + target = (sym_frag->fr_address + sym_frag->fr_fix
  7027. + + pool->padding + pool->literals[entry].offset);
  7028. +
  7029. + pr_debug("cpool sym address: 0x%lx\n",
  7030. + sym_frag->fr_address + sym_frag->fr_fix);
  7031. +
  7032. + know(pool->section == segment);
  7033. +
  7034. + if (sym_frag->relax_marker != fragP->relax_marker)
  7035. + target += stretch;
  7036. +
  7037. + distance = target - address;
  7038. + if (distance <= 508 && distance >= 0)
  7039. + {
  7040. + new_size = 2;
  7041. + fragP->fr_subtype = LDA_SUBTYPE_LDDPC;
  7042. + }
  7043. + else
  7044. + {
  7045. + new_size = 4;
  7046. + fragP->fr_subtype = LDA_SUBTYPE_LDW;
  7047. + }
  7048. +
  7049. + pr_debug("lda_relax_frag (cpool): target=0x%lx, address=0x%lx, refcount=%d\n",
  7050. + target, address, pool->literals[entry].refcount);
  7051. + }
  7052. + }
  7053. +
  7054. + fragP->fr_var = new_size;
  7055. +
  7056. + pr_debug("%s:%d: lda: relax pass done. subtype: %d, growth: %ld\n",
  7057. + fragP->fr_file, fragP->fr_line,
  7058. + fragP->fr_subtype, new_size - old_size);
  7059. +
  7060. + return new_size - old_size;
  7061. +}
  7062. +
  7063. +static long
  7064. +avr32_call_relax_frag(segT segment, fragS *fragP, long stretch)
  7065. +{
  7066. + struct cpool *pool = NULL;
  7067. + unsigned int entry = 0;
  7068. + addressT address, target;
  7069. + offsetT distance;
  7070. + symbolS *symbolP;
  7071. + fragS *sym_frag;
  7072. + long old_size, new_size;
  7073. +
  7074. + symbolP = fragP->fr_symbol;
  7075. + old_size = fragP->fr_var;
  7076. + if (!avr32_pic)
  7077. + {
  7078. + pool = fragP->tc_frag_data.pool;
  7079. + entry = fragP->tc_frag_data.pool_entry;
  7080. + }
  7081. +
  7082. + address = fragP->fr_address;
  7083. + address += fragP->fr_fix - CALL_INITIAL_SIZE;
  7084. +
  7085. + if (need_reloc(symbolP, segment, 1))
  7086. + {
  7087. + pr_debug("call: must emit reloc\n");
  7088. + goto relax_max;
  7089. + }
  7090. +
  7091. + target = fragP->fr_offset;
  7092. + sym_frag = symbol_get_frag(symbolP);
  7093. + target += S_GET_VALUE(symbolP);
  7094. +
  7095. + if (sym_frag->relax_marker != fragP->relax_marker
  7096. + && S_GET_SEGMENT(symbolP) == segment)
  7097. + target += stretch;
  7098. +
  7099. + distance = target - address;
  7100. +
  7101. + if (distance <= 1022 && distance >= -1024)
  7102. + {
  7103. + pr_debug("call: distance is %d, emitting short rcall\n", distance);
  7104. + if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
  7105. + pool->literals[entry].refcount--;
  7106. + new_size = 2;
  7107. + fragP->fr_subtype = CALL_SUBTYPE_RCALL1;
  7108. + }
  7109. + else if (distance <= 2097150 && distance >= -2097152)
  7110. + {
  7111. + pr_debug("call: distance is %d, emitting long rcall\n", distance);
  7112. + if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
  7113. + pool->literals[entry].refcount--;
  7114. + new_size = 4;
  7115. + fragP->fr_subtype = CALL_SUBTYPE_RCALL2;
  7116. + }
  7117. + else
  7118. + {
  7119. + pr_debug("call: distance %d too far, emitting something big\n", distance);
  7120. +
  7121. + relax_max:
  7122. + if (avr32_pic)
  7123. + {
  7124. + if (linkrelax)
  7125. + {
  7126. + new_size = 10;
  7127. + fragP->fr_subtype = CALL_SUBTYPE_MCALL_LARGE;
  7128. + }
  7129. + else
  7130. + {
  7131. + new_size = 4;
  7132. + fragP->fr_subtype = CALL_SUBTYPE_MCALL_GOT;
  7133. + }
  7134. + }
  7135. + else
  7136. + {
  7137. + if (fragP->fr_subtype != CALL_SUBTYPE_MCALL_CP)
  7138. + pool->literals[entry].refcount++;
  7139. +
  7140. + new_size = 4;
  7141. + fragP->fr_subtype = CALL_SUBTYPE_MCALL_CP;
  7142. + }
  7143. + }
  7144. +
  7145. + fragP->fr_var = new_size;
  7146. +
  7147. + pr_debug("%s:%d: call: relax pass done, growth: %d, fr_var: %d\n",
  7148. + fragP->fr_file, fragP->fr_line,
  7149. + new_size - old_size, fragP->fr_var);
  7150. +
  7151. + return new_size - old_size;
  7152. +}
  7153. +
  7154. +static long
  7155. +avr32_cpool_relax_frag(segT segment ATTRIBUTE_UNUSED,
  7156. + fragS *fragP,
  7157. + long stretch ATTRIBUTE_UNUSED)
  7158. +{
  7159. + struct cpool *pool;
  7160. + addressT address;
  7161. + long old_size, new_size;
  7162. + unsigned int entry;
  7163. +
  7164. + pool = fragP->tc_frag_data.pool;
  7165. + address = fragP->fr_address + fragP->fr_fix;
  7166. + old_size = fragP->fr_var;
  7167. + new_size = 0;
  7168. +
  7169. + for (entry = 0; entry < pool->next_free_entry; entry++)
  7170. + {
  7171. + if (pool->literals[entry].refcount > 0)
  7172. + {
  7173. + pool->literals[entry].offset = new_size;
  7174. + new_size += 4;
  7175. + }
  7176. + }
  7177. +
  7178. + fragP->fr_var = new_size;
  7179. +
  7180. + return new_size - old_size;
  7181. +}
  7182. +
  7183. +/* *fragP has been relaxed to its final size, and now needs to have
  7184. + the bytes inside it modified to conform to the new size.
  7185. +
  7186. + Called after relaxation is finished.
  7187. + fragP->fr_type == rs_machine_dependent.
  7188. + fragP->fr_subtype is the subtype of what the address relaxed to. */
  7189. +
  7190. +static void
  7191. +avr32_default_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
  7192. + segT segment ATTRIBUTE_UNUSED,
  7193. + fragS *fragP)
  7194. +{
  7195. + const struct avr32_opcode *opc;
  7196. + const struct avr32_ifield *ifield;
  7197. + bfd_reloc_code_real_type r_type;
  7198. + symbolS *symbolP;
  7199. + fixS *fixP;
  7200. + bfd_vma value;
  7201. + int subtype;
  7202. +
  7203. + opc = &avr32_opc_table[fragP->fr_subtype];
  7204. + ifield = opc->fields[opc->var_field];
  7205. + symbolP = fragP->fr_symbol;
  7206. + subtype = fragP->fr_subtype;
  7207. + r_type = opc->reloc_type;
  7208. +
  7209. + /* Clear the opcode bits and the bits belonging to the relaxed
  7210. + field. We assume all other fields stay the same. */
  7211. + value = bfd_getb32(fragP->fr_opcode);
  7212. + value &= ~(opc->mask | ifield->mask);
  7213. +
  7214. + /* Insert the new opcode */
  7215. + value |= opc->value;
  7216. + bfd_putb32(value, fragP->fr_opcode);
  7217. +
  7218. + fragP->fr_fix += opc->size - fragP->fr_var;
  7219. +
  7220. + if (fragP->tc_frag_data.reloc_info != AVR32_OPINFO_NONE)
  7221. + {
  7222. + switch (fragP->tc_frag_data.reloc_info)
  7223. + {
  7224. + case AVR32_OPINFO_HI:
  7225. + r_type = BFD_RELOC_HI16;
  7226. + break;
  7227. + case AVR32_OPINFO_LO:
  7228. + r_type = BFD_RELOC_LO16;
  7229. + break;
  7230. + case AVR32_OPINFO_GOT:
  7231. + switch (r_type)
  7232. + {
  7233. + case BFD_RELOC_AVR32_18W_PCREL:
  7234. + r_type = BFD_RELOC_AVR32_GOT18SW;
  7235. + break;
  7236. + case BFD_RELOC_AVR32_16S:
  7237. + r_type = BFD_RELOC_AVR32_GOT16S;
  7238. + break;
  7239. + default:
  7240. + BAD_CASE(r_type);
  7241. + break;
  7242. + }
  7243. + break;
  7244. + default:
  7245. + BAD_CASE(fragP->tc_frag_data.reloc_info);
  7246. + break;
  7247. + }
  7248. + }
  7249. +
  7250. + pr_debug("%s:%d: convert_frag: new %s fixup\n",
  7251. + fragP->fr_file, fragP->fr_line,
  7252. + bfd_get_reloc_code_name(r_type));
  7253. +
  7254. +#if 1
  7255. + fixP = fix_new_exp(fragP, fragP->fr_fix - opc->size, opc->size,
  7256. + &fragP->tc_frag_data.exp,
  7257. + fragP->tc_frag_data.pcrel, r_type);
  7258. +#else
  7259. + fixP = fix_new(fragP, fragP->fr_fix - opc->size, opc->size, symbolP,
  7260. + fragP->fr_offset, fragP->tc_frag_data.pcrel, r_type);
  7261. +#endif
  7262. +
  7263. + /* Revert fix_new brain damage. "dot_value" is the value of PC at
  7264. + the point of the fixup, relative to the frag address. fix_new()
  7265. + and friends think they are only being called during the assembly
  7266. + pass, not during relaxation or similar, so fx_dot_value, fx_file
  7267. + and fx_line are all initialized to the wrong value. But we don't
  7268. + know the size of the fixup until now, so we really can't live up
  7269. + to the assumptions these functions make about the target. What
  7270. + do these functions think the "where" and "frag" argument mean
  7271. + anyway? */
  7272. + fixP->fx_dot_value = fragP->fr_fix - opc->size;
  7273. + fixP->fx_file = fragP->fr_file;
  7274. + fixP->fx_line = fragP->fr_line;
  7275. +
  7276. + fixP->tc_fix_data.ifield = ifield;
  7277. + fixP->tc_fix_data.align = avr32_rs_align(subtype);
  7278. + fixP->tc_fix_data.min = avr32_relax_table[subtype].lower_bound;
  7279. + fixP->tc_fix_data.max = avr32_relax_table[subtype].upper_bound;
  7280. +}
  7281. +
  7282. +static void
  7283. +avr32_lda_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
  7284. + segT segment ATTRIBUTE_UNUSED,
  7285. + fragS *fragP)
  7286. +{
  7287. + const struct avr32_opcode *opc;
  7288. + const struct avr32_ifield *ifield;
  7289. + bfd_reloc_code_real_type r_type;
  7290. + expressionS exp;
  7291. + struct cpool *pool;
  7292. + fixS *fixP;
  7293. + bfd_vma value;
  7294. + int regid, pcrel = 0, align = 0;
  7295. + char *p;
  7296. +
  7297. + r_type = BFD_RELOC_NONE;
  7298. + regid = fragP->tc_frag_data.reloc_info;
  7299. + p = fragP->fr_opcode;
  7300. + exp.X_add_symbol = fragP->fr_symbol;
  7301. + exp.X_add_number = fragP->fr_offset;
  7302. + exp.X_op = O_symbol;
  7303. +
  7304. + pr_debug("%s:%d: lda_convert_frag, subtype: %d, fix: %d, var: %d, regid: %d\n",
  7305. + fragP->fr_file, fragP->fr_line,
  7306. + fragP->fr_subtype, fragP->fr_fix, fragP->fr_var, regid);
  7307. +
  7308. + switch (fragP->fr_subtype)
  7309. + {
  7310. + case LDA_SUBTYPE_MOV1:
  7311. + opc = &avr32_opc_table[AVR32_OPC_MOV1];
  7312. + opc->fields[0]->insert(opc->fields[0], p, regid);
  7313. + ifield = opc->fields[1];
  7314. + r_type = opc->reloc_type;
  7315. + break;
  7316. + case LDA_SUBTYPE_MOV2:
  7317. + opc = &avr32_opc_table[AVR32_OPC_MOV2];
  7318. + opc->fields[0]->insert(opc->fields[0], p, regid);
  7319. + ifield = opc->fields[1];
  7320. + r_type = opc->reloc_type;
  7321. + break;
  7322. + case LDA_SUBTYPE_SUB:
  7323. + opc = &avr32_opc_table[AVR32_OPC_SUB5];
  7324. + opc->fields[0]->insert(opc->fields[0], p, regid);
  7325. + opc->fields[1]->insert(opc->fields[1], p, AVR32_REG_PC);
  7326. + ifield = opc->fields[2];
  7327. + r_type = BFD_RELOC_AVR32_16N_PCREL;
  7328. +
  7329. + /* Pretend that SUB5 isn't a "negated" pcrel expression for now.
  7330. + We'll have to fix it up later when we know whether to
  7331. + generate a reloc for it (in which case the linker will negate
  7332. + it, so we shouldn't). */
  7333. + pcrel = 1;
  7334. + break;
  7335. + case LDA_SUBTYPE_LDDPC:
  7336. + opc = &avr32_opc_table[AVR32_OPC_LDDPC];
  7337. + align = 2;
  7338. + r_type = BFD_RELOC_AVR32_9W_CP;
  7339. + goto cpool_common;
  7340. + case LDA_SUBTYPE_LDW:
  7341. + opc = &avr32_opc_table[AVR32_OPC_LDDPC_EXT];
  7342. + r_type = BFD_RELOC_AVR32_16_CP;
  7343. + cpool_common:
  7344. + opc->fields[0]->insert(opc->fields[0], p, regid);
  7345. + ifield = opc->fields[1];
  7346. + pool = fragP->tc_frag_data.pool;
  7347. + exp.X_add_symbol = pool->symbol;
  7348. + exp.X_add_number = pool->literals[fragP->tc_frag_data.pool_entry].offset;
  7349. + pcrel = 1;
  7350. + break;
  7351. + case LDA_SUBTYPE_GOTLOAD_LARGE:
  7352. + /* ld.w Rd, r6[Rd << 2] (last) */
  7353. + opc = &avr32_opc_table[AVR32_OPC_LD_W5];
  7354. + bfd_putb32(opc->value, p + 4);
  7355. + opc->fields[0]->insert(opc->fields[0], p + 4, regid);
  7356. + opc->fields[1]->insert(opc->fields[1], p + 4, 6);
  7357. + opc->fields[2]->insert(opc->fields[2], p + 4, regid);
  7358. + opc->fields[3]->insert(opc->fields[3], p + 4, 2);
  7359. +
  7360. + /* mov Rd, (got_offset / 4) */
  7361. + opc = &avr32_opc_table[AVR32_OPC_MOV2];
  7362. + opc->fields[0]->insert(opc->fields[0], p, regid);
  7363. + ifield = opc->fields[1];
  7364. + r_type = BFD_RELOC_AVR32_LDA_GOT;
  7365. + break;
  7366. + case LDA_SUBTYPE_GOTLOAD:
  7367. + opc = &avr32_opc_table[AVR32_OPC_LD_W4];
  7368. + opc->fields[0]->insert(opc->fields[0], p, regid);
  7369. + opc->fields[1]->insert(opc->fields[1], p, 6);
  7370. + ifield = opc->fields[2];
  7371. + if (r_type == BFD_RELOC_NONE)
  7372. + r_type = BFD_RELOC_AVR32_GOT16S;
  7373. + break;
  7374. + default:
  7375. + BAD_CASE(fragP->fr_subtype);
  7376. + }
  7377. +
  7378. + value = bfd_getb32(p);
  7379. + value &= ~(opc->mask | ifield->mask);
  7380. + value |= opc->value;
  7381. + bfd_putb32(value, p);
  7382. +
  7383. + fragP->fr_fix += fragP->fr_var - LDA_INITIAL_SIZE;
  7384. +
  7385. + if (fragP->fr_next
  7386. + && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
  7387. + != fragP->fr_fix))
  7388. + {
  7389. + fprintf(stderr, "LDA frag: fr_fix is wrong! fragP->fr_var = %ld, r_type = %s\n",
  7390. + fragP->fr_var, bfd_get_reloc_code_name(r_type));
  7391. + abort();
  7392. + }
  7393. +
  7394. + fixP = fix_new_exp(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
  7395. + &exp, pcrel, r_type);
  7396. +
  7397. + /* Revert fix_new brain damage. "dot_value" is the value of PC at
  7398. + the point of the fixup, relative to the frag address. fix_new()
  7399. + and friends think they are only being called during the assembly
  7400. + pass, not during relaxation or similar, so fx_dot_value, fx_file
  7401. + and fx_line are all initialized to the wrong value. But we don't
  7402. + know the size of the fixup until now, so we really can't live up
  7403. + to the assumptions these functions make about the target. What
  7404. + do these functions think the "where" and "frag" argument mean
  7405. + anyway? */
  7406. + fixP->fx_dot_value = fragP->fr_fix - opc->size;
  7407. + fixP->fx_file = fragP->fr_file;
  7408. + fixP->fx_line = fragP->fr_line;
  7409. +
  7410. + fixP->tc_fix_data.ifield = ifield;
  7411. + fixP->tc_fix_data.align = align;
  7412. + /* these are only used if the fixup can actually be resolved */
  7413. + fixP->tc_fix_data.min = -32768;
  7414. + fixP->tc_fix_data.max = 32767;
  7415. +}
  7416. +
  7417. +static void
  7418. +avr32_call_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
  7419. + segT segment ATTRIBUTE_UNUSED,
  7420. + fragS *fragP)
  7421. +{
  7422. + const struct avr32_opcode *opc = NULL;
  7423. + const struct avr32_ifield *ifield;
  7424. + bfd_reloc_code_real_type r_type;
  7425. + symbolS *symbol;
  7426. + offsetT offset;
  7427. + fixS *fixP;
  7428. + bfd_vma value;
  7429. + int pcrel = 0, align = 0;
  7430. + char *p;
  7431. +
  7432. + symbol = fragP->fr_symbol;
  7433. + offset = fragP->fr_offset;
  7434. + r_type = BFD_RELOC_NONE;
  7435. + p = fragP->fr_opcode;
  7436. +
  7437. + pr_debug("%s:%d: call_convert_frag, subtype: %d, fix: %d, var: %d\n",
  7438. + fragP->fr_file, fragP->fr_line,
  7439. + fragP->fr_subtype, fragP->fr_fix, fragP->fr_var);
  7440. +
  7441. + switch (fragP->fr_subtype)
  7442. + {
  7443. + case CALL_SUBTYPE_RCALL1:
  7444. + opc = &avr32_opc_table[AVR32_OPC_RCALL1];
  7445. + /* fall through */
  7446. + case CALL_SUBTYPE_RCALL2:
  7447. + if (!opc)
  7448. + opc = &avr32_opc_table[AVR32_OPC_RCALL2];
  7449. + ifield = opc->fields[0];
  7450. + r_type = opc->reloc_type;
  7451. + pcrel = 1;
  7452. + align = 1;
  7453. + break;
  7454. + case CALL_SUBTYPE_MCALL_CP:
  7455. + opc = &avr32_opc_table[AVR32_OPC_MCALL];
  7456. + opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_PC);
  7457. + ifield = opc->fields[1];
  7458. + r_type = BFD_RELOC_AVR32_CPCALL;
  7459. + symbol = fragP->tc_frag_data.pool->symbol;
  7460. + offset = fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].offset;
  7461. + assert(fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].refcount > 0);
  7462. + pcrel = 1;
  7463. + align = 2;
  7464. + break;
  7465. + case CALL_SUBTYPE_MCALL_GOT:
  7466. + opc = &avr32_opc_table[AVR32_OPC_MCALL];
  7467. + opc->fields[0]->insert(opc->fields[0], p, 6);
  7468. + ifield = opc->fields[1];
  7469. + r_type = BFD_RELOC_AVR32_GOT18SW;
  7470. + break;
  7471. + case CALL_SUBTYPE_MCALL_LARGE:
  7472. + assert(fragP->fr_var == 10);
  7473. + /* ld.w lr, r6[lr << 2] */
  7474. + opc = &avr32_opc_table[AVR32_OPC_LD_W5];
  7475. + bfd_putb32(opc->value, p + 4);
  7476. + opc->fields[0]->insert(opc->fields[0], p + 4, AVR32_REG_LR);
  7477. + opc->fields[1]->insert(opc->fields[1], p + 4, 6);
  7478. + opc->fields[2]->insert(opc->fields[2], p + 4, AVR32_REG_LR);
  7479. + opc->fields[3]->insert(opc->fields[3], p + 4, 2);
  7480. +
  7481. + /* icall lr */
  7482. + opc = &avr32_opc_table[AVR32_OPC_ICALL];
  7483. + bfd_putb16(opc->value >> 16, p + 8);
  7484. + opc->fields[0]->insert(opc->fields[0], p + 8, AVR32_REG_LR);
  7485. +
  7486. + /* mov lr, (got_offset / 4) */
  7487. + opc = &avr32_opc_table[AVR32_OPC_MOV2];
  7488. + opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_LR);
  7489. + ifield = opc->fields[1];
  7490. + r_type = BFD_RELOC_AVR32_GOTCALL;
  7491. + break;
  7492. + default:
  7493. + BAD_CASE(fragP->fr_subtype);
  7494. + }
  7495. +
  7496. + /* Insert the opcode and clear the variable ifield */
  7497. + value = bfd_getb32(p);
  7498. + value &= ~(opc->mask | ifield->mask);
  7499. + value |= opc->value;
  7500. + bfd_putb32(value, p);
  7501. +
  7502. + fragP->fr_fix += fragP->fr_var - CALL_INITIAL_SIZE;
  7503. +
  7504. + if (fragP->fr_next
  7505. + && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
  7506. + != fragP->fr_fix))
  7507. + {
  7508. + fprintf(stderr, "%s:%d: fr_fix %lu is wrong! fr_var=%lu, r_type=%s\n",
  7509. + fragP->fr_file, fragP->fr_line,
  7510. + fragP->fr_fix, fragP->fr_var, bfd_get_reloc_code_name(r_type));
  7511. + fprintf(stderr, "fr_fix should be %ld. next frag is %s:%d\n",
  7512. + (offsetT)(fragP->fr_next->fr_address - fragP->fr_address),
  7513. + fragP->fr_next->fr_file, fragP->fr_next->fr_line);
  7514. + }
  7515. +
  7516. + fixP = fix_new(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
  7517. + symbol, offset, pcrel, r_type);
  7518. +
  7519. + /* Revert fix_new brain damage. "dot_value" is the value of PC at
  7520. + the point of the fixup, relative to the frag address. fix_new()
  7521. + and friends think they are only being called during the assembly
  7522. + pass, not during relaxation or similar, so fx_dot_value, fx_file
  7523. + and fx_line are all initialized to the wrong value. But we don't
  7524. + know the size of the fixup until now, so we really can't live up
  7525. + to the assumptions these functions make about the target. What
  7526. + do these functions think the "where" and "frag" argument mean
  7527. + anyway? */
  7528. + fixP->fx_dot_value = fragP->fr_fix - opc->size;
  7529. + fixP->fx_file = fragP->fr_file;
  7530. + fixP->fx_line = fragP->fr_line;
  7531. +
  7532. + fixP->tc_fix_data.ifield = ifield;
  7533. + fixP->tc_fix_data.align = align;
  7534. + /* these are only used if the fixup can actually be resolved */
  7535. + fixP->tc_fix_data.min = -2097152;
  7536. + fixP->tc_fix_data.max = 2097150;
  7537. +}
  7538. +
  7539. +static void
  7540. +avr32_cpool_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
  7541. + segT segment ATTRIBUTE_UNUSED,
  7542. + fragS *fragP)
  7543. +{
  7544. + struct cpool *pool;
  7545. + addressT address;
  7546. + unsigned int entry;
  7547. + char *p;
  7548. + char sym_name[20];
  7549. +
  7550. + /* Did we get rid of the frag altogether? */
  7551. + if (!fragP->fr_var)
  7552. + return;
  7553. +
  7554. + pool = fragP->tc_frag_data.pool;
  7555. + address = fragP->fr_address + fragP->fr_fix;
  7556. + p = fragP->fr_literal + fragP->fr_fix;
  7557. +
  7558. + sprintf(sym_name, "$$cp_\002%x", pool->id);
  7559. + symbol_locate(pool->symbol, sym_name, pool->section, fragP->fr_fix, fragP);
  7560. + symbol_table_insert(pool->symbol);
  7561. +
  7562. + for (entry = 0; entry < pool->next_free_entry; entry++)
  7563. + {
  7564. + if (pool->literals[entry].refcount > 0)
  7565. + {
  7566. + fix_new_exp(fragP, fragP->fr_fix, 4, &pool->literals[entry].exp,
  7567. + FALSE, BFD_RELOC_AVR32_32_CPENT);
  7568. + fragP->fr_fix += 4;
  7569. + }
  7570. + }
  7571. +}
  7572. +
  7573. +static struct avr32_relaxer avr32_default_relaxer = {
  7574. + .estimate_size = avr32_default_estimate_size_before_relax,
  7575. + .relax_frag = avr32_default_relax_frag,
  7576. + .convert_frag = avr32_default_convert_frag,
  7577. +};
  7578. +static struct avr32_relaxer avr32_lda_relaxer = {
  7579. + .estimate_size = avr32_lda_estimate_size_before_relax,
  7580. + .relax_frag = avr32_lda_relax_frag,
  7581. + .convert_frag = avr32_lda_convert_frag,
  7582. +};
  7583. +static struct avr32_relaxer avr32_call_relaxer = {
  7584. + .estimate_size = avr32_call_estimate_size_before_relax,
  7585. + .relax_frag = avr32_call_relax_frag,
  7586. + .convert_frag = avr32_call_convert_frag,
  7587. +};
  7588. +static struct avr32_relaxer avr32_cpool_relaxer = {
  7589. + .estimate_size = avr32_cpool_estimate_size_before_relax,
  7590. + .relax_frag = avr32_cpool_relax_frag,
  7591. + .convert_frag = avr32_cpool_convert_frag,
  7592. +};
  7593. +
  7594. +static void s_cpool(int arg ATTRIBUTE_UNUSED)
  7595. +{
  7596. + struct cpool *pool;
  7597. + unsigned int max_size;
  7598. + char *buf;
  7599. +
  7600. + pool = find_cpool(now_seg, now_subseg);
  7601. + if (!pool || !pool->symbol || pool->next_free_entry == 0)
  7602. + return;
  7603. +
  7604. + /* Make sure the constant pool is properly aligned */
  7605. + frag_align_code(2, 0);
  7606. + if (bfd_get_section_alignment(stdoutput, pool->section) < 2)
  7607. + bfd_set_section_alignment(stdoutput, pool->section, 2);
  7608. +
  7609. + /* Assume none of the entries are discarded, and that we need the
  7610. + maximum amount of alignment. But we're not going to allocate
  7611. + anything up front. */
  7612. + max_size = pool->next_free_entry * 4 + 2;
  7613. + frag_grow(max_size);
  7614. + buf = frag_more(0);
  7615. +
  7616. + frag_now->tc_frag_data.relaxer = &avr32_cpool_relaxer;
  7617. + frag_now->tc_frag_data.pool = pool;
  7618. +
  7619. + symbol_set_frag(pool->symbol, frag_now);
  7620. +
  7621. + /* Assume zero initial size, allowing other relaxers to be
  7622. + optimistic about things. */
  7623. + frag_var(rs_machine_dependent, max_size, 0,
  7624. + 0, pool->symbol, 0, NULL);
  7625. +
  7626. + /* Mark the pool as empty. */
  7627. + pool->used = 1;
  7628. +}
  7629. +
  7630. +/* The location from which a PC relative jump should be calculated,
  7631. + given a PC relative reloc. */
  7632. +
  7633. +long
  7634. +md_pcrel_from_section (fixS *fixP, segT sec)
  7635. +{
  7636. + pr_debug("pcrel_from_section, fx_offset = %d\n", fixP->fx_offset);
  7637. +
  7638. + if (fixP->fx_addsy != NULL
  7639. + && (! S_IS_DEFINED (fixP->fx_addsy)
  7640. + || S_GET_SEGMENT (fixP->fx_addsy) != sec
  7641. + || S_FORCE_RELOC(fixP->fx_addsy, 1)))
  7642. + {
  7643. + pr_debug("Unknown pcrel symbol: %s\n", S_GET_NAME(fixP->fx_addsy));
  7644. +
  7645. + /* The symbol is undefined (or is defined but not in this section).
  7646. + Let the linker figure it out. */
  7647. + return 0;
  7648. + }
  7649. +
  7650. + pr_debug("pcrel from %x + %x, symbol: %s (%x)\n",
  7651. + fixP->fx_frag->fr_address, fixP->fx_where,
  7652. + fixP->fx_addsy?S_GET_NAME(fixP->fx_addsy):"(null)",
  7653. + fixP->fx_addsy?S_GET_VALUE(fixP->fx_addsy):0);
  7654. +
  7655. + return ((fixP->fx_frag->fr_address + fixP->fx_where)
  7656. + & (~0UL << fixP->tc_fix_data.align));
  7657. +}
  7658. +
  7659. +valueT
  7660. +md_section_align (segT segment, valueT size)
  7661. +{
  7662. + int align = bfd_get_section_alignment (stdoutput, segment);
  7663. + return ((size + (1 << align) - 1) & (-1 << align));
  7664. +}
  7665. +
  7666. +static int syntax_matches(const struct avr32_syntax *syntax,
  7667. + char *str)
  7668. +{
  7669. + int i;
  7670. +
  7671. + pr_debug("syntax %d matches `%s'?\n", syntax->id, str);
  7672. +
  7673. + if (syntax->nr_operands < 0)
  7674. + {
  7675. + struct avr32_operand *op;
  7676. + int optype;
  7677. +
  7678. + for (i = 0; i < (-syntax->nr_operands - 1); i++)
  7679. + {
  7680. + char *p;
  7681. + char c;
  7682. +
  7683. + optype = syntax->operand[i];
  7684. + assert(optype < AVR32_NR_OPERANDS);
  7685. + op = &avr32_operand_table[optype];
  7686. +
  7687. + for (p = str; *p; p++)
  7688. + if (*p == ',')
  7689. + break;
  7690. +
  7691. + if (p == str)
  7692. + return 0;
  7693. +
  7694. + c = *p;
  7695. + *p = 0;
  7696. +
  7697. + if (!op->match(str))
  7698. + {
  7699. + *p = c;
  7700. + return 0;
  7701. + }
  7702. +
  7703. + str = p;
  7704. + *p = c;
  7705. + if (c)
  7706. + str++;
  7707. + }
  7708. +
  7709. + optype = syntax->operand[i];
  7710. + assert(optype < AVR32_NR_OPERANDS);
  7711. + op = &avr32_operand_table[optype];
  7712. +
  7713. + if (!op->match(str))
  7714. + return 0;
  7715. + return 1;
  7716. + }
  7717. +
  7718. + for (i = 0; i < syntax->nr_operands; i++)
  7719. + {
  7720. + struct avr32_operand *op;
  7721. + int optype = syntax->operand[i];
  7722. + char *p;
  7723. + char c;
  7724. +
  7725. + assert(optype < AVR32_NR_OPERANDS);
  7726. + op = &avr32_operand_table[optype];
  7727. +
  7728. + for (p = str; *p; p++)
  7729. + if (*p == ',')
  7730. + break;
  7731. +
  7732. + if (p == str)
  7733. + return 0;
  7734. +
  7735. + c = *p;
  7736. + *p = 0;
  7737. +
  7738. + if (!op->match(str))
  7739. + {
  7740. + *p = c;
  7741. + return 0;
  7742. + }
  7743. +
  7744. + str = p;
  7745. + *p = c;
  7746. + if (c)
  7747. + str++;
  7748. + }
  7749. +
  7750. + if (*str == '\0')
  7751. + return 1;
  7752. +
  7753. + if ((*str == 'e' || *str == 'E') && !str[1])
  7754. + return 1;
  7755. +
  7756. + return 0;
  7757. +}
  7758. +
  7759. +static int parse_operands(char *str)
  7760. +{
  7761. + int i;
  7762. +
  7763. + if (current_insn.syntax->nr_operands < 0)
  7764. + {
  7765. + int optype;
  7766. + struct avr32_operand *op;
  7767. +
  7768. + for (i = 0; i < (-current_insn.syntax->nr_operands - 1); i++)
  7769. + {
  7770. + char *p;
  7771. + char c;
  7772. +
  7773. + optype = current_insn.syntax->operand[i];
  7774. + op = &avr32_operand_table[optype];
  7775. +
  7776. + for (p = str; *p; p++)
  7777. + if (*p == ',')
  7778. + break;
  7779. +
  7780. + assert(p != str);
  7781. +
  7782. + c = *p, *p = 0;
  7783. + op->parse(op, str, i);
  7784. + *p = c;
  7785. +
  7786. + str = p;
  7787. + if (c) str++;
  7788. + }
  7789. +
  7790. + /* give the rest of the line to the last operand */
  7791. + optype = current_insn.syntax->operand[i];
  7792. + op = &avr32_operand_table[optype];
  7793. + op->parse(op, str, i);
  7794. + }
  7795. + else
  7796. + {
  7797. + for (i = 0; i < current_insn.syntax->nr_operands; i++)
  7798. + {
  7799. + int optype = current_insn.syntax->operand[i];
  7800. + struct avr32_operand *op = &avr32_operand_table[optype];
  7801. + char *p;
  7802. + char c;
  7803. +
  7804. + skip_whitespace(str);
  7805. +
  7806. + for (p = str; *p; p++)
  7807. + if (*p == ',')
  7808. + break;
  7809. +
  7810. + assert(p != str);
  7811. +
  7812. + c = *p, *p = 0;
  7813. + op->parse(op, str, i);
  7814. + *p = c;
  7815. +
  7816. + str = p;
  7817. + if (c) str++;
  7818. + }
  7819. +
  7820. + if (*str == 'E' || *str == 'e')
  7821. + current_insn.force_extended = 1;
  7822. + }
  7823. +
  7824. + return 0;
  7825. +}
  7826. +
  7827. +static const char *
  7828. +finish_insn(const struct avr32_opcode *opc)
  7829. +{
  7830. + expressionS *exp = &current_insn.immediate;
  7831. + unsigned int i;
  7832. + int will_relax = 0;
  7833. + char *buf;
  7834. +
  7835. + assert(current_insn.next_slot == opc->nr_fields);
  7836. +
  7837. + pr_debug("%s:%d: finish_insn: trying opcode %d\n",
  7838. + frag_now->fr_file, frag_now->fr_line, opc->id);
  7839. +
  7840. + /* Go through the relaxation stage for all instructions that can
  7841. + possibly take a symbolic immediate. The relax code will take
  7842. + care of range checking and alignment. */
  7843. + if (opc->var_field != -1)
  7844. + {
  7845. + int substate, largest_substate;
  7846. + symbolS *sym;
  7847. + offsetT off;
  7848. +
  7849. + will_relax = 1;
  7850. + substate = largest_substate = opc_initial_substate(opc);
  7851. +
  7852. + while (relax_more(largest_substate) != AVR32_RS_NONE)
  7853. + largest_substate = relax_more(largest_substate);
  7854. +
  7855. + pr_debug("will relax. initial substate: %d (size %d), largest substate: %d (size %d)\n",
  7856. + substate, avr32_rs_size(substate),
  7857. + largest_substate, avr32_rs_size(largest_substate));
  7858. +
  7859. + /* make sure we have enough room for the largest possible opcode */
  7860. + frag_grow(avr32_rs_size(largest_substate));
  7861. + buf = frag_more(opc->size);
  7862. +
  7863. + dwarf2_emit_insn(opc->size);
  7864. +
  7865. + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_NONE;
  7866. + frag_now->tc_frag_data.pcrel = current_insn.pcrel;
  7867. + frag_now->tc_frag_data.force_extended = current_insn.force_extended;
  7868. + frag_now->tc_frag_data.relaxer = &avr32_default_relaxer;
  7869. +
  7870. + if (exp->X_op == O_hi)
  7871. + {
  7872. + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_HI;
  7873. + exp->X_op = exp->X_md;
  7874. + }
  7875. + else if (exp->X_op == O_lo)
  7876. + {
  7877. + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_LO;
  7878. + exp->X_op = exp->X_md;
  7879. + }
  7880. + else if (exp->X_op == O_got)
  7881. + {
  7882. + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_GOT;
  7883. + exp->X_op = O_symbol;
  7884. + }
  7885. +
  7886. +#if 0
  7887. + if ((opc->reloc_type == BFD_RELOC_AVR32_SUB5)
  7888. + && exp->X_op == O_subtract)
  7889. + {
  7890. + symbolS *tmp;
  7891. + tmp = exp->X_add_symbol;
  7892. + exp->X_add_symbol = exp->X_op_symbol;
  7893. + exp->X_op_symbol = tmp;
  7894. + }
  7895. +#endif
  7896. +
  7897. + frag_now->tc_frag_data.exp = current_insn.immediate;
  7898. +
  7899. + sym = exp->X_add_symbol;
  7900. + off = exp->X_add_number;
  7901. + if (exp->X_op != O_symbol)
  7902. + {
  7903. + sym = make_expr_symbol(exp);
  7904. + off = 0;
  7905. + }
  7906. +
  7907. + frag_var(rs_machine_dependent,
  7908. + avr32_rs_size(largest_substate) - opc->size,
  7909. + opc->size,
  7910. + substate, sym, off, buf);
  7911. + }
  7912. + else
  7913. + {
  7914. + assert(avr32_rs_size(opc_initial_substate(opc)) == 0);
  7915. +
  7916. + /* Make sure we always have room for another whole word, as the ifield
  7917. + inserters can only write words. */
  7918. + frag_grow(4);
  7919. + buf = frag_more(opc->size);
  7920. + dwarf2_emit_insn(opc->size);
  7921. + }
  7922. +
  7923. + assert(!(opc->value & ~opc->mask));
  7924. +
  7925. + pr_debug("inserting opcode: 0x%lx\n", opc->value);
  7926. + bfd_putb32(opc->value, buf);
  7927. +
  7928. + for (i = 0; i < opc->nr_fields; i++)
  7929. + {
  7930. + const struct avr32_ifield *f = opc->fields[i];
  7931. + const struct avr32_ifield_data *fd = &current_insn.field_value[i];
  7932. +
  7933. + pr_debug("inserting field: 0x%lx & 0x%lx\n",
  7934. + fd->value >> fd->align_order, f->mask);
  7935. +
  7936. + f->insert(f, buf, fd->value >> fd->align_order);
  7937. + }
  7938. +
  7939. + assert(will_relax || !current_insn.immediate.X_add_symbol);
  7940. + return NULL;
  7941. +}
  7942. +
  7943. +static const char *
  7944. +finish_alias(const struct avr32_alias *alias)
  7945. +{
  7946. + const struct avr32_opcode *opc;
  7947. + struct {
  7948. + unsigned long value;
  7949. + unsigned long align;
  7950. + } mapped_operand[AVR32_MAX_OPERANDS];
  7951. + unsigned int i;
  7952. +
  7953. + opc = alias->opc;
  7954. +
  7955. + /* Remap the operands from the alias to the real opcode */
  7956. + for (i = 0; i < opc->nr_fields; i++)
  7957. + {
  7958. + if (alias->operand_map[i].is_opindex)
  7959. + {
  7960. + struct avr32_ifield_data *fd;
  7961. + fd = &current_insn.field_value[alias->operand_map[i].value];
  7962. + mapped_operand[i].value = fd->value;
  7963. + mapped_operand[i].align = fd->align_order;
  7964. + }
  7965. + else
  7966. + {
  7967. + mapped_operand[i].value = alias->operand_map[i].value;
  7968. + mapped_operand[i].align = 0;
  7969. + }
  7970. + }
  7971. +
  7972. + for (i = 0; i < opc->nr_fields; i++)
  7973. + {
  7974. + current_insn.field_value[i].value = mapped_operand[i].value;
  7975. + if (opc->id == AVR32_OPC_COP)
  7976. + current_insn.field_value[i].align_order = 0;
  7977. + else
  7978. + current_insn.field_value[i].align_order
  7979. + = mapped_operand[i].align;
  7980. + }
  7981. +
  7982. + current_insn.next_slot = opc->nr_fields;
  7983. +
  7984. + return finish_insn(opc);
  7985. +}
  7986. +
  7987. +static const char *
  7988. +finish_lda(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
  7989. +{
  7990. + expressionS *exp = &current_insn.immediate;
  7991. + relax_substateT initial_subtype;
  7992. + symbolS *sym;
  7993. + offsetT off;
  7994. + int initial_size, max_size;
  7995. + char *buf;
  7996. +
  7997. + initial_size = LDA_INITIAL_SIZE;
  7998. +
  7999. + if (avr32_pic)
  8000. + {
  8001. + initial_subtype = LDA_SUBTYPE_SUB;
  8002. + if (linkrelax)
  8003. + max_size = 8;
  8004. + else
  8005. + max_size = 4;
  8006. + }
  8007. + else
  8008. + {
  8009. + initial_subtype = LDA_SUBTYPE_MOV1;
  8010. + max_size = 4;
  8011. + }
  8012. +
  8013. + frag_grow(max_size);
  8014. + buf = frag_more(initial_size);
  8015. + dwarf2_emit_insn(initial_size);
  8016. +
  8017. + if (exp->X_op == O_symbol)
  8018. + {
  8019. + sym = exp->X_add_symbol;
  8020. + off = exp->X_add_number;
  8021. + }
  8022. + else
  8023. + {
  8024. + sym = make_expr_symbol(exp);
  8025. + off = 0;
  8026. + }
  8027. +
  8028. + frag_now->tc_frag_data.reloc_info = current_insn.field_value[0].value;
  8029. + frag_now->tc_frag_data.relaxer = &avr32_lda_relaxer;
  8030. +
  8031. + if (!avr32_pic)
  8032. + {
  8033. + /* The relaxer will bump the refcount if necessary */
  8034. + frag_now->tc_frag_data.pool
  8035. + = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
  8036. + }
  8037. +
  8038. + frag_var(rs_machine_dependent, max_size - initial_size,
  8039. + initial_size, initial_subtype, sym, off, buf);
  8040. +
  8041. + return NULL;
  8042. +}
  8043. +
  8044. +static const char *
  8045. +finish_call(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
  8046. +{
  8047. + expressionS *exp = &current_insn.immediate;
  8048. + symbolS *sym;
  8049. + offsetT off;
  8050. + int initial_size, max_size;
  8051. + char *buf;
  8052. +
  8053. + initial_size = CALL_INITIAL_SIZE;
  8054. +
  8055. + if (avr32_pic)
  8056. + {
  8057. + if (linkrelax)
  8058. + max_size = 10;
  8059. + else
  8060. + max_size = 4;
  8061. + }
  8062. + else
  8063. + max_size = 4;
  8064. +
  8065. + frag_grow(max_size);
  8066. + buf = frag_more(initial_size);
  8067. + dwarf2_emit_insn(initial_size);
  8068. +
  8069. + frag_now->tc_frag_data.relaxer = &avr32_call_relaxer;
  8070. +
  8071. + if (exp->X_op == O_symbol)
  8072. + {
  8073. + sym = exp->X_add_symbol;
  8074. + off = exp->X_add_number;
  8075. + }
  8076. + else
  8077. + {
  8078. + sym = make_expr_symbol(exp);
  8079. + off = 0;
  8080. + }
  8081. +
  8082. + if (!avr32_pic)
  8083. + {
  8084. + /* The relaxer will bump the refcount if necessary */
  8085. + frag_now->tc_frag_data.pool
  8086. + = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
  8087. + }
  8088. +
  8089. + frag_var(rs_machine_dependent, max_size - initial_size,
  8090. + initial_size, CALL_SUBTYPE_RCALL1, sym, off, buf);
  8091. +
  8092. + return NULL;
  8093. +}
  8094. +
  8095. +void
  8096. +md_begin (void)
  8097. +{
  8098. + unsigned long flags = 0;
  8099. + int i;
  8100. +
  8101. + avr32_mnemonic_htab = hash_new();
  8102. +
  8103. + if (!avr32_mnemonic_htab)
  8104. + as_fatal(_("virtual memory exhausted"));
  8105. +
  8106. + for (i = 0; i < AVR32_NR_MNEMONICS; i++)
  8107. + {
  8108. + hash_insert(avr32_mnemonic_htab, avr32_mnemonic_table[i].name,
  8109. + (void *)&avr32_mnemonic_table[i]);
  8110. + }
  8111. +
  8112. + if (linkrelax)
  8113. + flags |= EF_AVR32_LINKRELAX;
  8114. + if (avr32_pic)
  8115. + flags |= EF_AVR32_PIC;
  8116. +
  8117. + bfd_set_private_flags(stdoutput, flags);
  8118. +
  8119. +#ifdef OPC_CONSISTENCY_CHECK
  8120. + if (sizeof(avr32_operand_table)/sizeof(avr32_operand_table[0])
  8121. + < AVR32_NR_OPERANDS)
  8122. + as_fatal(_("operand table is incomplete"));
  8123. +
  8124. + for (i = 0; i < AVR32_NR_OPERANDS; i++)
  8125. + if (avr32_operand_table[i].id != i)
  8126. + as_fatal(_("operand table inconsistency found at index %d\n"), i);
  8127. + pr_debug("%d operands verified\n", AVR32_NR_OPERANDS);
  8128. +
  8129. + for (i = 0; i < AVR32_NR_IFIELDS; i++)
  8130. + if (avr32_ifield_table[i].id != i)
  8131. + as_fatal(_("ifield table inconsistency found at index %d\n"), i);
  8132. + pr_debug("%d instruction fields verified\n", AVR32_NR_IFIELDS);
  8133. +
  8134. + for (i = 0; i < AVR32_NR_OPCODES; i++)
  8135. + {
  8136. + if (avr32_opc_table[i].id != i)
  8137. + as_fatal(_("opcode table inconsistency found at index %d\n"), i);
  8138. + if ((avr32_opc_table[i].var_field == -1
  8139. + && avr32_relax_table[i].length != 0)
  8140. + || (avr32_opc_table[i].var_field != -1
  8141. + && avr32_relax_table[i].length == 0))
  8142. + as_fatal(_("relax table inconsistency found at index %d\n"), i);
  8143. + }
  8144. + pr_debug("%d opcodes verified\n", AVR32_NR_OPCODES);
  8145. +
  8146. + for (i = 0; i < AVR32_NR_SYNTAX; i++)
  8147. + if (avr32_syntax_table[i].id != i)
  8148. + as_fatal(_("syntax table inconsistency found at index %d\n"), i);
  8149. + pr_debug("%d syntax variants verified\n", AVR32_NR_SYNTAX);
  8150. +
  8151. + for (i = 0; i < AVR32_NR_ALIAS; i++)
  8152. + if (avr32_alias_table[i].id != i)
  8153. + as_fatal(_("alias table inconsistency found at index %d\n"), i);
  8154. + pr_debug("%d aliases verified\n", AVR32_NR_ALIAS);
  8155. +
  8156. + for (i = 0; i < AVR32_NR_MNEMONICS; i++)
  8157. + if (avr32_mnemonic_table[i].id != i)
  8158. + as_fatal(_("mnemonic table inconsistency found at index %d\n"), i);
  8159. + pr_debug("%d mnemonics verified\n", AVR32_NR_MNEMONICS);
  8160. +#endif
  8161. +}
  8162. +
  8163. +void
  8164. +md_assemble (char *str)
  8165. +{
  8166. + struct avr32_mnemonic *mnemonic;
  8167. + char *p, c;
  8168. +
  8169. + memset(&current_insn, 0, sizeof(current_insn));
  8170. + current_insn.immediate.X_op = O_constant;
  8171. +
  8172. + skip_whitespace(str);
  8173. + for (p = str; *p; p++)
  8174. + if (*p == ' ')
  8175. + break;
  8176. + c = *p;
  8177. + *p = 0;
  8178. +
  8179. + mnemonic = hash_find(avr32_mnemonic_htab, str);
  8180. + *p = c;
  8181. + if (c) p++;
  8182. +
  8183. + if (mnemonic)
  8184. + {
  8185. + const struct avr32_syntax *syntax;
  8186. +
  8187. + for (syntax = mnemonic->syntax; syntax; syntax = syntax->next)
  8188. + {
  8189. + const char *errmsg = NULL;
  8190. +
  8191. + if (syntax_matches(syntax, p))
  8192. + {
  8193. + if (!(syntax->isa_flags & avr32_arch->isa_flags))
  8194. + {
  8195. + as_bad(_("Selected architecture `%s' does not support `%s'"),
  8196. + avr32_arch->name, str);
  8197. + return;
  8198. + }
  8199. +
  8200. + current_insn.syntax = syntax;
  8201. + parse_operands(p);
  8202. +
  8203. + switch (syntax->type)
  8204. + {
  8205. + case AVR32_PARSER_NORMAL:
  8206. + errmsg = finish_insn(syntax->u.opc);
  8207. + break;
  8208. + case AVR32_PARSER_ALIAS:
  8209. + errmsg = finish_alias(syntax->u.alias);
  8210. + break;
  8211. + case AVR32_PARSER_LDA:
  8212. + errmsg = finish_lda(syntax);
  8213. + break;
  8214. + case AVR32_PARSER_CALL:
  8215. + errmsg = finish_call(syntax);
  8216. + break;
  8217. + default:
  8218. + BAD_CASE(syntax->type);
  8219. + break;
  8220. + }
  8221. +
  8222. + if (errmsg)
  8223. + as_bad("%s in `%s'", errmsg, str);
  8224. +
  8225. + return;
  8226. + }
  8227. + }
  8228. +
  8229. + as_bad(_("unrecognized form of instruction: `%s'"), str);
  8230. + }
  8231. + else
  8232. + as_bad(_("unrecognized instruction `%s'"), str);
  8233. +}
  8234. +
  8235. +void avr32_cleanup(void)
  8236. +{
  8237. + struct cpool *pool;
  8238. +
  8239. + /* Emit any constant pools that haven't been explicitly flushed with
  8240. + a .cpool directive. */
  8241. + for (pool = cpool_list; pool; pool = pool->next)
  8242. + {
  8243. + subseg_set(pool->section, pool->sub_section);
  8244. + s_cpool(0);
  8245. + }
  8246. +}
  8247. +
  8248. +/* Handle any PIC-related operands in data allocation pseudo-ops */
  8249. +void
  8250. +avr32_cons_fix_new (fragS *frag, int off, int size, expressionS *exp)
  8251. +{
  8252. + bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
  8253. + int pcrel = 0;
  8254. +
  8255. + pr_debug("%s:%u: cons_fix_new, add_sym: %s, op_sym: %s, op: %d, add_num: %d\n",
  8256. + frag->fr_file, frag->fr_line,
  8257. + exp->X_add_symbol?S_GET_NAME(exp->X_add_symbol):"(none)",
  8258. + exp->X_op_symbol?S_GET_NAME(exp->X_op_symbol):"(none)",
  8259. + exp->X_op, exp->X_add_number);
  8260. +
  8261. + if (exp->X_op == O_subtract && exp->X_op_symbol)
  8262. + {
  8263. + if (exp->X_op_symbol == GOT_symbol)
  8264. + {
  8265. + if (size != 4)
  8266. + goto bad_size;
  8267. + r_type = BFD_RELOC_AVR32_GOTPC;
  8268. + exp->X_op = O_symbol;
  8269. + exp->X_op_symbol = NULL;
  8270. + }
  8271. + }
  8272. + else if (exp->X_op == O_got)
  8273. + {
  8274. + switch (size)
  8275. + {
  8276. + case 1:
  8277. + r_type = BFD_RELOC_AVR32_GOT8;
  8278. + break;
  8279. + case 2:
  8280. + r_type = BFD_RELOC_AVR32_GOT16;
  8281. + break;
  8282. + case 4:
  8283. + r_type = BFD_RELOC_AVR32_GOT32;
  8284. + break;
  8285. + default:
  8286. + goto bad_size;
  8287. + }
  8288. +
  8289. + exp->X_op = O_symbol;
  8290. + }
  8291. +
  8292. + if (r_type == BFD_RELOC_UNUSED)
  8293. + switch (size)
  8294. + {
  8295. + case 1:
  8296. + r_type = BFD_RELOC_8;
  8297. + break;
  8298. + case 2:
  8299. + r_type = BFD_RELOC_16;
  8300. + break;
  8301. + case 4:
  8302. + r_type = BFD_RELOC_32;
  8303. + break;
  8304. + default:
  8305. + goto bad_size;
  8306. + }
  8307. + else if (size != 4)
  8308. + {
  8309. + bad_size:
  8310. + as_bad(_("unsupported BFD relocation size %u"), size);
  8311. + r_type = BFD_RELOC_UNUSED;
  8312. + }
  8313. +
  8314. + fix_new_exp (frag, off, size, exp, pcrel, r_type);
  8315. +}
  8316. +
  8317. +static void
  8318. +avr32_frob_section(bfd *abfd ATTRIBUTE_UNUSED, segT sec,
  8319. + void *ignore ATTRIBUTE_UNUSED)
  8320. +{
  8321. + segment_info_type *seginfo;
  8322. + fixS *fix;
  8323. +
  8324. + seginfo = seg_info(sec);
  8325. + if (!seginfo)
  8326. + return;
  8327. +
  8328. + for (fix = seginfo->fix_root; fix; fix = fix->fx_next)
  8329. + {
  8330. + if (fix->fx_done)
  8331. + continue;
  8332. +
  8333. + if (fix->fx_r_type == BFD_RELOC_AVR32_SUB5
  8334. + && fix->fx_addsy && fix->fx_subsy)
  8335. + {
  8336. + if (S_GET_SEGMENT(fix->fx_addsy) != S_GET_SEGMENT(fix->fx_subsy)
  8337. + || linkrelax)
  8338. + {
  8339. + symbolS *tmp;
  8340. +#ifdef DEBUG
  8341. + fprintf(stderr, "Swapping symbols in fixup:\n");
  8342. + print_fixup(fix);
  8343. +#endif
  8344. + tmp = fix->fx_addsy;
  8345. + fix->fx_addsy = fix->fx_subsy;
  8346. + fix->fx_subsy = tmp;
  8347. + fix->fx_offset = -fix->fx_offset;
  8348. + }
  8349. + }
  8350. + }
  8351. +}
  8352. +
  8353. +/* We need to look for SUB5 instructions with expressions that will be
  8354. + made PC-relative and switch fx_addsy with fx_subsy. This has to be
  8355. + done before adjustment or the wrong symbol might be adjusted.
  8356. +
  8357. + This applies to fixups that are a result of expressions like -(sym
  8358. + - .) and that will make it all the way to md_apply_fix3(). LDA
  8359. + does the right thing in convert_frag, so we must not convert
  8360. + those. */
  8361. +void
  8362. +avr32_frob_file(void)
  8363. +{
  8364. + /* if (1 || !linkrelax)
  8365. + return; */
  8366. +
  8367. + bfd_map_over_sections(stdoutput, avr32_frob_section, NULL);
  8368. +}
  8369. +
  8370. +static bfd_boolean
  8371. +convert_to_diff_reloc(fixS *fixP)
  8372. +{
  8373. + switch (fixP->fx_r_type)
  8374. + {
  8375. + case BFD_RELOC_32:
  8376. + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
  8377. + break;
  8378. + case BFD_RELOC_16:
  8379. + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF16;
  8380. + break;
  8381. + case BFD_RELOC_8:
  8382. + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF8;
  8383. + break;
  8384. + default:
  8385. + return FALSE;
  8386. + }
  8387. +
  8388. + return TRUE;
  8389. +}
  8390. +
  8391. +/* Simplify a fixup. If possible, the fixup is reduced to a single
  8392. + constant which is written to the output file. Otherwise, a
  8393. + relocation is generated so that the linker can take care of the
  8394. + rest.
  8395. +
  8396. + ELF relocations have certain constraints: They can only take a
  8397. + single symbol and a single addend. This means that for difference
  8398. + expressions, we _must_ get rid of the fx_subsy symbol somehow.
  8399. +
  8400. + The difference between two labels in the same section can be
  8401. + calculated directly unless 'linkrelax' is set, or a relocation is
  8402. + forced. If so, we must emit a R_AVR32_DIFFxx relocation. If there
  8403. + are addends involved at this point, we must be especially careful
  8404. + as the relocation must point exactly to the symbol being
  8405. + subtracted.
  8406. +
  8407. + When subtracting a symbol defined in the same section as the fixup,
  8408. + we might be able to convert it to a PC-relative expression, unless
  8409. + linkrelax is set. If this is the case, there's no way we can make
  8410. + sure that the difference between the fixup and fx_subsy stays
  8411. + constant. So for now, we're just going to disallow that.
  8412. + */
  8413. +void
  8414. +avr32_process_fixup(fixS *fixP, segT this_segment)
  8415. +{
  8416. + segT add_symbol_segment = absolute_section;
  8417. + segT sub_symbol_segment = absolute_section;
  8418. + symbolS *fx_addsy, *fx_subsy;
  8419. + offsetT value = 0, fx_offset;
  8420. + bfd_boolean apply = FALSE;
  8421. +
  8422. + assert(this_segment != absolute_section);
  8423. +
  8424. + if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
  8425. + {
  8426. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8427. + _("Bad relocation type %d\n"), fixP->fx_r_type);
  8428. + return;
  8429. + }
  8430. +
  8431. + /* BFD_RELOC_AVR32_SUB5 fixups have been swapped by avr32_frob_section() */
  8432. + fx_addsy = fixP->fx_addsy;
  8433. + fx_subsy = fixP->fx_subsy;
  8434. + fx_offset = fixP->fx_offset;
  8435. +
  8436. + if (fx_addsy)
  8437. + add_symbol_segment = S_GET_SEGMENT(fx_addsy);
  8438. +
  8439. + if (fx_subsy)
  8440. + {
  8441. + resolve_symbol_value(fx_subsy);
  8442. + sub_symbol_segment = S_GET_SEGMENT(fx_subsy);
  8443. +
  8444. + if (sub_symbol_segment == this_segment
  8445. + && (!linkrelax
  8446. + || S_GET_VALUE(fx_subsy) == (fixP->fx_frag->fr_address
  8447. + + fixP->fx_where)))
  8448. + {
  8449. + fixP->fx_pcrel = TRUE;
  8450. + fx_offset += (fixP->fx_frag->fr_address + fixP->fx_where
  8451. + - S_GET_VALUE(fx_subsy));
  8452. + fx_subsy = NULL;
  8453. + }
  8454. + else if (sub_symbol_segment == absolute_section)
  8455. + {
  8456. + /* The symbol is really a constant. */
  8457. + fx_offset -= S_GET_VALUE(fx_subsy);
  8458. + fx_subsy = NULL;
  8459. + }
  8460. + else if (SEG_NORMAL(add_symbol_segment)
  8461. + && sub_symbol_segment == add_symbol_segment
  8462. + && (!linkrelax || convert_to_diff_reloc(fixP)))
  8463. + {
  8464. + /* Difference between two labels in the same section. */
  8465. + if (linkrelax)
  8466. + {
  8467. + /* convert_to_diff() has ensured that the reloc type is
  8468. + either DIFF32, DIFF16 or DIFF8. */
  8469. + value = (S_GET_VALUE(fx_addsy) + fixP->fx_offset
  8470. + - S_GET_VALUE(fx_subsy));
  8471. +
  8472. + /* Try to convert it to a section symbol if possible */
  8473. + if (!S_FORCE_RELOC(fx_addsy, 1)
  8474. + && !(sub_symbol_segment->flags & SEC_THREAD_LOCAL))
  8475. + {
  8476. + fx_offset = S_GET_VALUE(fx_subsy);
  8477. + fx_addsy = section_symbol(sub_symbol_segment);
  8478. + }
  8479. + else
  8480. + {
  8481. + fx_addsy = fx_subsy;
  8482. + fx_offset = 0;
  8483. + }
  8484. +
  8485. + fx_subsy = NULL;
  8486. + apply = TRUE;
  8487. + }
  8488. + else
  8489. + {
  8490. + fx_offset += S_GET_VALUE(fx_addsy);
  8491. + fx_offset -= S_GET_VALUE(fx_subsy);
  8492. + fx_addsy = NULL;
  8493. + fx_subsy = NULL;
  8494. + }
  8495. + }
  8496. + else
  8497. + {
  8498. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8499. + _("can't resolve `%s' {%s section} - `%s' {%s section}"),
  8500. + fx_addsy ? S_GET_NAME (fx_addsy) : "0",
  8501. + segment_name (add_symbol_segment),
  8502. + S_GET_NAME (fx_subsy),
  8503. + segment_name (sub_symbol_segment));
  8504. + return;
  8505. + }
  8506. + }
  8507. +
  8508. + if (fx_addsy && !TC_FORCE_RELOCATION(fixP))
  8509. + {
  8510. + if (add_symbol_segment == this_segment
  8511. + && fixP->fx_pcrel)
  8512. + {
  8513. + value += S_GET_VALUE(fx_addsy);
  8514. + value -= md_pcrel_from_section(fixP, this_segment);
  8515. + fx_addsy = NULL;
  8516. + fixP->fx_pcrel = FALSE;
  8517. + }
  8518. + else if (add_symbol_segment == absolute_section)
  8519. + {
  8520. + fx_offset += S_GET_VALUE(fixP->fx_addsy);
  8521. + fx_addsy = NULL;
  8522. + }
  8523. + }
  8524. +
  8525. + if (!fx_addsy)
  8526. + fixP->fx_done = TRUE;
  8527. +
  8528. + if (fixP->fx_pcrel)
  8529. + {
  8530. + if (fx_addsy != NULL
  8531. + && S_IS_DEFINED(fx_addsy)
  8532. + && S_GET_SEGMENT(fx_addsy) != this_segment)
  8533. + value += md_pcrel_from_section(fixP, this_segment);
  8534. +
  8535. + switch (fixP->fx_r_type)
  8536. + {
  8537. + case BFD_RELOC_32:
  8538. + fixP->fx_r_type = BFD_RELOC_32_PCREL;
  8539. + break;
  8540. + case BFD_RELOC_16:
  8541. + fixP->fx_r_type = BFD_RELOC_16_PCREL;
  8542. + break;
  8543. + case BFD_RELOC_8:
  8544. + fixP->fx_r_type = BFD_RELOC_8_PCREL;
  8545. + break;
  8546. + case BFD_RELOC_AVR32_SUB5:
  8547. + fixP->fx_r_type = BFD_RELOC_AVR32_16N_PCREL;
  8548. + break;
  8549. + case BFD_RELOC_AVR32_16S:
  8550. + fixP->fx_r_type = BFD_RELOC_AVR32_16B_PCREL;
  8551. + break;
  8552. + case BFD_RELOC_AVR32_14UW:
  8553. + fixP->fx_r_type = BFD_RELOC_AVR32_14UW_PCREL;
  8554. + break;
  8555. + case BFD_RELOC_AVR32_10UW:
  8556. + fixP->fx_r_type = BFD_RELOC_AVR32_10UW_PCREL;
  8557. + break;
  8558. + default:
  8559. + /* Should have been taken care of already */
  8560. + break;
  8561. + }
  8562. + }
  8563. +
  8564. + if (fixP->fx_done || apply)
  8565. + {
  8566. + const struct avr32_ifield *ifield;
  8567. + char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
  8568. +
  8569. + if (fixP->fx_done)
  8570. + value += fx_offset;
  8571. +
  8572. + /* For hosts with longs bigger than 32-bits make sure that the top
  8573. + bits of a 32-bit negative value read in by the parser are set,
  8574. + so that the correct comparisons are made. */
  8575. + if (value & 0x80000000)
  8576. + value |= (-1L << 31);
  8577. +
  8578. + switch (fixP->fx_r_type)
  8579. + {
  8580. + case BFD_RELOC_32:
  8581. + case BFD_RELOC_16:
  8582. + case BFD_RELOC_8:
  8583. + case BFD_RELOC_AVR32_DIFF32:
  8584. + case BFD_RELOC_AVR32_DIFF16:
  8585. + case BFD_RELOC_AVR32_DIFF8:
  8586. + md_number_to_chars(buf, value, fixP->fx_size);
  8587. + break;
  8588. + case BFD_RELOC_HI16:
  8589. + value >>= 16;
  8590. + case BFD_RELOC_LO16:
  8591. + value &= 0xffff;
  8592. + md_number_to_chars(buf + 2, value, 2);
  8593. + break;
  8594. + case BFD_RELOC_AVR32_16N_PCREL:
  8595. + value = -value;
  8596. + /* fall through */
  8597. + case BFD_RELOC_AVR32_22H_PCREL:
  8598. + case BFD_RELOC_AVR32_18W_PCREL:
  8599. + case BFD_RELOC_AVR32_16B_PCREL:
  8600. + case BFD_RELOC_AVR32_11H_PCREL:
  8601. + case BFD_RELOC_AVR32_9H_PCREL:
  8602. + case BFD_RELOC_AVR32_9UW_PCREL:
  8603. + case BFD_RELOC_AVR32_3U:
  8604. + case BFD_RELOC_AVR32_4UH:
  8605. + case BFD_RELOC_AVR32_6UW:
  8606. + case BFD_RELOC_AVR32_6S:
  8607. + case BFD_RELOC_AVR32_7UW:
  8608. + case BFD_RELOC_AVR32_8S_EXT:
  8609. + case BFD_RELOC_AVR32_8S:
  8610. + case BFD_RELOC_AVR32_10UW:
  8611. + case BFD_RELOC_AVR32_10SW:
  8612. + case BFD_RELOC_AVR32_STHH_W:
  8613. + case BFD_RELOC_AVR32_14UW:
  8614. + case BFD_RELOC_AVR32_16S:
  8615. + case BFD_RELOC_AVR32_16U:
  8616. + case BFD_RELOC_AVR32_21S:
  8617. + case BFD_RELOC_AVR32_SUB5:
  8618. + case BFD_RELOC_AVR32_CPCALL:
  8619. + case BFD_RELOC_AVR32_16_CP:
  8620. + case BFD_RELOC_AVR32_9W_CP:
  8621. + case BFD_RELOC_AVR32_15S:
  8622. + ifield = fixP->tc_fix_data.ifield;
  8623. + pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
  8624. + fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
  8625. + fixP->tc_fix_data.align);
  8626. + if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
  8627. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8628. + _("operand out of range (%ld not between %ld and %ld)"),
  8629. + value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
  8630. + if (value & ((1 << fixP->tc_fix_data.align) - 1))
  8631. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8632. + _("misaligned operand (required alignment: %d)"),
  8633. + 1 << fixP->tc_fix_data.align);
  8634. + ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
  8635. + break;
  8636. + case BFD_RELOC_AVR32_ALIGN:
  8637. + /* Nothing to do */
  8638. + fixP->fx_done = FALSE;
  8639. + break;
  8640. + default:
  8641. + as_fatal("reloc type %s not handled\n",
  8642. + bfd_get_reloc_code_name(fixP->fx_r_type));
  8643. + }
  8644. + }
  8645. +
  8646. + fixP->fx_addsy = fx_addsy;
  8647. + fixP->fx_subsy = fx_subsy;
  8648. + fixP->fx_offset = fx_offset;
  8649. +
  8650. + if (!fixP->fx_done)
  8651. + {
  8652. + if (!fixP->fx_addsy)
  8653. + fixP->fx_addsy = abs_section_sym;
  8654. +
  8655. + symbol_mark_used_in_reloc(fixP->fx_addsy);
  8656. + if (fixP->fx_subsy)
  8657. + abort();
  8658. + }
  8659. +}
  8660. +
  8661. +#if 0
  8662. +void
  8663. +md_apply_fix3 (fixS *fixP, valueT *valP, segT seg)
  8664. +{
  8665. + const struct avr32_ifield *ifield;
  8666. + offsetT value = *valP;
  8667. + char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
  8668. + bfd_boolean apply;
  8669. +
  8670. + pr_debug("%s:%u: apply_fix3: r_type=%d value=%lx offset=%lx\n",
  8671. + fixP->fx_file, fixP->fx_line, fixP->fx_r_type, *valP,
  8672. + fixP->fx_offset);
  8673. +
  8674. + if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
  8675. + {
  8676. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8677. + _("Bad relocation type %d\n"), fixP->fx_r_type);
  8678. + return;
  8679. + }
  8680. +
  8681. + if (!fixP->fx_addsy && !fixP->fx_subsy)
  8682. + fixP->fx_done = 1;
  8683. +
  8684. + if (fixP->fx_pcrel)
  8685. + {
  8686. + if (fixP->fx_addsy != NULL
  8687. + && S_IS_DEFINED(fixP->fx_addsy)
  8688. + && S_GET_SEGMENT(fixP->fx_addsy) != seg)
  8689. + value += md_pcrel_from_section(fixP, seg);
  8690. +
  8691. + switch (fixP->fx_r_type)
  8692. + {
  8693. + case BFD_RELOC_32:
  8694. + fixP->fx_r_type = BFD_RELOC_32_PCREL;
  8695. + break;
  8696. + case BFD_RELOC_16:
  8697. + case BFD_RELOC_8:
  8698. + as_bad_where (fixP->fx_file, fixP->fx_line,
  8699. + _("8- and 16-bit PC-relative relocations not supported"));
  8700. + break;
  8701. + case BFD_RELOC_AVR32_SUB5:
  8702. + fixP->fx_r_type = BFD_RELOC_AVR32_PCREL_SUB5;
  8703. + break;
  8704. + case BFD_RELOC_AVR32_16S:
  8705. + fixP->fx_r_type = BFD_RELOC_AVR32_16_PCREL;
  8706. + break;
  8707. + default:
  8708. + /* Should have been taken care of already */
  8709. + break;
  8710. + }
  8711. + }
  8712. +
  8713. + if (fixP->fx_r_type == BFD_RELOC_32
  8714. + && fixP->fx_subsy)
  8715. + {
  8716. + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
  8717. +
  8718. + /* Offsets are only allowed if it's a result of adjusting a
  8719. + local symbol into a section-relative offset.
  8720. + tc_fix_adjustable() should prevent any adjustment if there
  8721. + was an offset involved before. */
  8722. + if (fixP->fx_offset && !symbol_section_p(fixP->fx_addsy))
  8723. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8724. + _("cannot represent symbol difference with an offset"));
  8725. +
  8726. + value = (S_GET_VALUE(fixP->fx_addsy) + fixP->fx_offset
  8727. + - S_GET_VALUE(fixP->fx_subsy));
  8728. +
  8729. + /* The difference before any relaxing takes place is written
  8730. + out, and the DIFF32 reloc identifies the address of the first
  8731. + symbol (i.e. the on that's subtracted.) */
  8732. + *valP = value;
  8733. + fixP->fx_offset -= value;
  8734. + fixP->fx_subsy = NULL;
  8735. +
  8736. + md_number_to_chars(buf, value, fixP->fx_size);
  8737. + }
  8738. +
  8739. + if (fixP->fx_done)
  8740. + {
  8741. + switch (fixP->fx_r_type)
  8742. + {
  8743. + case BFD_RELOC_8:
  8744. + case BFD_RELOC_16:
  8745. + case BFD_RELOC_32:
  8746. + md_number_to_chars(buf, value, fixP->fx_size);
  8747. + break;
  8748. + case BFD_RELOC_HI16:
  8749. + value >>= 16;
  8750. + case BFD_RELOC_LO16:
  8751. + value &= 0xffff;
  8752. + *valP = value;
  8753. + md_number_to_chars(buf + 2, value, 2);
  8754. + break;
  8755. + case BFD_RELOC_AVR32_PCREL_SUB5:
  8756. + value = -value;
  8757. + /* fall through */
  8758. + case BFD_RELOC_AVR32_9_PCREL:
  8759. + case BFD_RELOC_AVR32_11_PCREL:
  8760. + case BFD_RELOC_AVR32_16_PCREL:
  8761. + case BFD_RELOC_AVR32_18_PCREL:
  8762. + case BFD_RELOC_AVR32_22_PCREL:
  8763. + case BFD_RELOC_AVR32_3U:
  8764. + case BFD_RELOC_AVR32_4UH:
  8765. + case BFD_RELOC_AVR32_6UW:
  8766. + case BFD_RELOC_AVR32_6S:
  8767. + case BFD_RELOC_AVR32_7UW:
  8768. + case BFD_RELOC_AVR32_8S:
  8769. + case BFD_RELOC_AVR32_10UW:
  8770. + case BFD_RELOC_AVR32_10SW:
  8771. + case BFD_RELOC_AVR32_14UW:
  8772. + case BFD_RELOC_AVR32_16S:
  8773. + case BFD_RELOC_AVR32_16U:
  8774. + case BFD_RELOC_AVR32_21S:
  8775. + case BFD_RELOC_AVR32_BRC1:
  8776. + case BFD_RELOC_AVR32_SUB5:
  8777. + case BFD_RELOC_AVR32_CPCALL:
  8778. + case BFD_RELOC_AVR32_16_CP:
  8779. + case BFD_RELOC_AVR32_9_CP:
  8780. + case BFD_RELOC_AVR32_15S:
  8781. + ifield = fixP->tc_fix_data.ifield;
  8782. + pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
  8783. + fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
  8784. + fixP->tc_fix_data.align);
  8785. + if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
  8786. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8787. + _("operand out of range (%ld not between %ld and %ld)"),
  8788. + value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
  8789. + if (value & ((1 << fixP->tc_fix_data.align) - 1))
  8790. + as_bad_where(fixP->fx_file, fixP->fx_line,
  8791. + _("misaligned operand (required alignment: %d)"),
  8792. + 1 << fixP->tc_fix_data.align);
  8793. + ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
  8794. + break;
  8795. + case BFD_RELOC_AVR32_ALIGN:
  8796. + /* Nothing to do */
  8797. + fixP->fx_done = FALSE;
  8798. + break;
  8799. + default:
  8800. + as_fatal("reloc type %s not handled\n",
  8801. + bfd_get_reloc_code_name(fixP->fx_r_type));
  8802. + }
  8803. + }
  8804. +}
  8805. +#endif
  8806. +
  8807. +arelent *
  8808. +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
  8809. + fixS *fixp)
  8810. +{
  8811. + arelent *reloc;
  8812. + bfd_reloc_code_real_type code;
  8813. +
  8814. + reloc = xmalloc (sizeof (arelent));
  8815. +
  8816. + reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
  8817. + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
  8818. + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
  8819. + reloc->addend = fixp->fx_offset;
  8820. + code = fixp->fx_r_type;
  8821. +
  8822. + reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
  8823. +
  8824. + if (reloc->howto == NULL)
  8825. + {
  8826. + as_bad_where (fixp->fx_file, fixp->fx_line,
  8827. + _("cannot represent relocation %s in this object file format"),
  8828. + bfd_get_reloc_code_name (code));
  8829. + return NULL;
  8830. + }
  8831. +
  8832. + return reloc;
  8833. +}
  8834. +
  8835. +bfd_boolean
  8836. +avr32_force_reloc(fixS *fixP)
  8837. +{
  8838. + if (linkrelax && fixP->fx_addsy
  8839. + && !(S_GET_SEGMENT(fixP->fx_addsy)->flags & SEC_DEBUGGING)
  8840. + && S_GET_SEGMENT(fixP->fx_addsy) != absolute_section)
  8841. + {
  8842. + pr_debug(stderr, "force reloc: addsy=%p, r_type=%d, sec=%s\n",
  8843. + fixP->fx_addsy, fixP->fx_r_type, S_GET_SEGMENT(fixP->fx_addsy)->name);
  8844. + return 1;
  8845. + }
  8846. +
  8847. + return generic_force_reloc(fixP);
  8848. +}
  8849. +
  8850. +bfd_boolean
  8851. +avr32_fix_adjustable(fixS *fixP)
  8852. +{
  8853. + switch (fixP->fx_r_type)
  8854. + {
  8855. + /* GOT relocations can't have addends since BFD treats all
  8856. + references to a given symbol the same. This means that we
  8857. + must avoid section-relative references to local symbols when
  8858. + dealing with these kinds of relocs */
  8859. + case BFD_RELOC_AVR32_GOT32:
  8860. + case BFD_RELOC_AVR32_GOT16:
  8861. + case BFD_RELOC_AVR32_GOT8:
  8862. + case BFD_RELOC_AVR32_GOT21S:
  8863. + case BFD_RELOC_AVR32_GOT18SW:
  8864. + case BFD_RELOC_AVR32_GOT16S:
  8865. + case BFD_RELOC_AVR32_LDA_GOT:
  8866. + case BFD_RELOC_AVR32_GOTCALL:
  8867. + pr_debug("fix not adjustable\n");
  8868. + return 0;
  8869. +
  8870. + default:
  8871. + break;
  8872. + }
  8873. +
  8874. + return 1;
  8875. +}
  8876. +
  8877. +/* When we want the linker to be able to relax the code, we need to
  8878. + output a reloc for every .align directive requesting an alignment
  8879. + to a four byte boundary or larger. If we don't do this, the linker
  8880. + can't guarantee that the alignment is actually maintained in the
  8881. + linker output.
  8882. +
  8883. + TODO: Might as well insert proper NOPs while we're at it... */
  8884. +void
  8885. +avr32_handle_align(fragS *frag)
  8886. +{
  8887. + if (linkrelax
  8888. + && frag->fr_type == rs_align_code
  8889. + && frag->fr_address + frag->fr_fix > 0
  8890. + && frag->fr_offset > 0)
  8891. + {
  8892. + /* The alignment order (fr_offset) is stored in the addend. */
  8893. + fix_new(frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset,
  8894. + FALSE, BFD_RELOC_AVR32_ALIGN);
  8895. + }
  8896. +}
  8897. +
  8898. +/* Relax_align. Advance location counter to next address that has 'alignment'
  8899. + lowest order bits all 0s, return size of adjustment made. */
  8900. +relax_addressT
  8901. +avr32_relax_align(segT segment ATTRIBUTE_UNUSED,
  8902. + fragS *fragP,
  8903. + relax_addressT address)
  8904. +{
  8905. + relax_addressT mask;
  8906. + relax_addressT new_address;
  8907. + int alignment;
  8908. +
  8909. + alignment = fragP->fr_offset;
  8910. + mask = ~((~0) << alignment);
  8911. + new_address = (address + mask) & (~mask);
  8912. +
  8913. + return new_address - address;
  8914. +}
  8915. +
  8916. +/* Turn a string in input_line_pointer into a floating point constant
  8917. + of type type, and store the appropriate bytes in *litP. The number
  8918. + of LITTLENUMS emitted is stored in *sizeP . An error message is
  8919. + returned, or NULL on OK. */
  8920. +
  8921. +/* Equal to MAX_PRECISION in atof-ieee.c */
  8922. +#define MAX_LITTLENUMS 6
  8923. +
  8924. +char *
  8925. +md_atof (type, litP, sizeP)
  8926. +char type;
  8927. +char * litP;
  8928. +int * sizeP;
  8929. +{
  8930. + int i;
  8931. + int prec;
  8932. + LITTLENUM_TYPE words [MAX_LITTLENUMS];
  8933. + char * t;
  8934. +
  8935. + switch (type)
  8936. + {
  8937. + case 'f':
  8938. + case 'F':
  8939. + case 's':
  8940. + case 'S':
  8941. + prec = 2;
  8942. + break;
  8943. +
  8944. + case 'd':
  8945. + case 'D':
  8946. + case 'r':
  8947. + case 'R':
  8948. + prec = 4;
  8949. + break;
  8950. +
  8951. + /* FIXME: Some targets allow other format chars for bigger sizes here. */
  8952. +
  8953. + default:
  8954. + * sizeP = 0;
  8955. + return _("Bad call to md_atof()");
  8956. + }
  8957. +
  8958. + t = atof_ieee (input_line_pointer, type, words);
  8959. + if (t)
  8960. + input_line_pointer = t;
  8961. + * sizeP = prec * sizeof (LITTLENUM_TYPE);
  8962. +
  8963. + for (i = 0; i < prec; i++)
  8964. + {
  8965. + md_number_to_chars (litP, (valueT) words[i],
  8966. + sizeof (LITTLENUM_TYPE));
  8967. + litP += sizeof (LITTLENUM_TYPE);
  8968. + }
  8969. +
  8970. + return 0;
  8971. +}
  8972. +
  8973. +static char *avr32_end_of_match(char *cont, char *what)
  8974. +{
  8975. + int len = strlen (what);
  8976. +
  8977. + if (! is_part_of_name (cont[len])
  8978. + && strncasecmp (cont, what, len) == 0)
  8979. + return cont + len;
  8980. +
  8981. + return NULL;
  8982. +}
  8983. +
  8984. +int
  8985. +avr32_parse_name (char const *name, expressionS *exp, char *nextchar)
  8986. +{
  8987. + char *next = input_line_pointer;
  8988. + char *next_end;
  8989. +
  8990. + pr_debug("parse_name: %s, nextchar=%c (%02x)\n", name, *nextchar, *nextchar);
  8991. +
  8992. + if (*nextchar == '(')
  8993. + {
  8994. + if (strcasecmp(name, "hi") == 0)
  8995. + {
  8996. + *next = *nextchar;
  8997. +
  8998. + expression(exp);
  8999. +
  9000. + if (exp->X_op == O_constant)
  9001. + {
  9002. + pr_debug(" -> constant hi(0x%08lx) -> 0x%04lx\n",
  9003. + exp->X_add_number, exp->X_add_number >> 16);
  9004. + exp->X_add_number = (exp->X_add_number >> 16) & 0xffff;
  9005. + }
  9006. + else
  9007. + {
  9008. + exp->X_md = exp->X_op;
  9009. + exp->X_op = O_hi;
  9010. + }
  9011. +
  9012. + return 1;
  9013. + }
  9014. + else if (strcasecmp(name, "lo") == 0)
  9015. + {
  9016. + *next = *nextchar;
  9017. +
  9018. + expression(exp);
  9019. +
  9020. + if (exp->X_op == O_constant)
  9021. + exp->X_add_number &= 0xffff;
  9022. + else
  9023. + {
  9024. + exp->X_md = exp->X_op;
  9025. + exp->X_op = O_lo;
  9026. + }
  9027. +
  9028. + return 1;
  9029. + }
  9030. + }
  9031. + else if (*nextchar == '@')
  9032. + {
  9033. + exp->X_md = exp->X_op;
  9034. +
  9035. + if ((next_end = avr32_end_of_match (next + 1, "got")))
  9036. + exp->X_op = O_got;
  9037. + else if ((next_end = avr32_end_of_match (next + 1, "tlsgd")))
  9038. + exp->X_op = O_tlsgd;
  9039. + /* Add more as needed */
  9040. + else
  9041. + {
  9042. + char c;
  9043. + input_line_pointer++;
  9044. + c = get_symbol_end();
  9045. + as_bad (_("unknown relocation override `%s'"), next + 1);
  9046. + *input_line_pointer = c;
  9047. + input_line_pointer = next;
  9048. + return 0;
  9049. + }
  9050. +
  9051. + exp->X_op_symbol = NULL;
  9052. + exp->X_add_symbol = symbol_find_or_make (name);
  9053. + exp->X_add_number = 0;
  9054. +
  9055. + *input_line_pointer = *nextchar;
  9056. + input_line_pointer = next_end;
  9057. + *nextchar = *input_line_pointer;
  9058. + *input_line_pointer = '\0';
  9059. + return 1;
  9060. + }
  9061. + else if (strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0)
  9062. + {
  9063. + if (!GOT_symbol)
  9064. + GOT_symbol = symbol_find_or_make(name);
  9065. +
  9066. + exp->X_add_symbol = GOT_symbol;
  9067. + exp->X_op = O_symbol;
  9068. + exp->X_add_number = 0;
  9069. + return 1;
  9070. + }
  9071. +
  9072. + return 0;
  9073. +}
  9074. +
  9075. +static void
  9076. +s_rseg (int value ATTRIBUTE_UNUSED)
  9077. +{
  9078. + /* Syntax: RSEG segment_name [:type] [NOROOT|ROOT] [(align)]
  9079. + * Defaults:
  9080. + * - type: undocumented ("typically CODE or DATA")
  9081. + * - ROOT
  9082. + * - align: 1 for code, 0 for others
  9083. + *
  9084. + * TODO: NOROOT is ignored. If gas supports discardable segments, it should
  9085. + * be implemented.
  9086. + */
  9087. + char *name, *end;
  9088. + int length, type, attr;
  9089. + int align = 0;
  9090. +
  9091. + SKIP_WHITESPACE();
  9092. +
  9093. + end = input_line_pointer;
  9094. + while (0 == strchr ("\n\t;:( ", *end))
  9095. + end++;
  9096. + if (end == input_line_pointer)
  9097. + {
  9098. + as_warn (_("missing name"));
  9099. + ignore_rest_of_line();
  9100. + return;
  9101. + }
  9102. +
  9103. + name = xmalloc (end - input_line_pointer + 1);
  9104. + memcpy (name, input_line_pointer, end - input_line_pointer);
  9105. + name[end - input_line_pointer] = '\0';
  9106. + input_line_pointer = end;
  9107. +
  9108. + SKIP_WHITESPACE();
  9109. +
  9110. + type = SHT_NULL;
  9111. + attr = 0;
  9112. +
  9113. + if (*input_line_pointer == ':')
  9114. + {
  9115. + /* Skip the colon */
  9116. + ++input_line_pointer;
  9117. + SKIP_WHITESPACE();
  9118. +
  9119. + /* Possible options at this point:
  9120. + * - flag (ROOT or NOROOT)
  9121. + * - a segment type
  9122. + */
  9123. + end = input_line_pointer;
  9124. + while (0 == strchr ("\n\t;:( ", *end))
  9125. + end++;
  9126. + length = end - input_line_pointer;
  9127. + if (((length == 4) && (0 == strncasecmp( input_line_pointer, "ROOT", 4))) ||
  9128. + ((length == 6) && (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
  9129. + {
  9130. + /* Ignore ROOT/NOROOT */
  9131. + input_line_pointer = end;
  9132. + }
  9133. + else
  9134. + {
  9135. + /* Must be a segment type */
  9136. + switch (*input_line_pointer)
  9137. + {
  9138. + case 'C':
  9139. + case 'c':
  9140. + if ((length == 4) &&
  9141. + (0 == strncasecmp (input_line_pointer, "CODE", 4)))
  9142. + {
  9143. + attr |= SHF_ALLOC | SHF_EXECINSTR;
  9144. + type = SHT_PROGBITS;
  9145. + align = 1;
  9146. + break;
  9147. + }
  9148. + if ((length == 5) &&
  9149. + (0 == strncasecmp (input_line_pointer, "CONST", 5)))
  9150. + {
  9151. + attr |= SHF_ALLOC;
  9152. + type = SHT_PROGBITS;
  9153. + break;
  9154. + }
  9155. + goto de_fault;
  9156. +
  9157. + case 'D':
  9158. + case 'd':
  9159. + if ((length == 4) &&
  9160. + (0 == strncasecmp (input_line_pointer, "DATA", 4)))
  9161. + {
  9162. + attr |= SHF_ALLOC | SHF_WRITE;
  9163. + type = SHT_PROGBITS;
  9164. + break;
  9165. + }
  9166. + goto de_fault;
  9167. +
  9168. + /* TODO: Add FAR*, HUGE*, IDATA and NEAR* if necessary */
  9169. +
  9170. + case 'U':
  9171. + case 'u':
  9172. + if ((length == 7) &&
  9173. + (0 == strncasecmp (input_line_pointer, "UNTYPED", 7)))
  9174. + break;
  9175. + goto de_fault;
  9176. +
  9177. + /* TODO: Add XDATA and ZPAGE if necessary */
  9178. +
  9179. + de_fault:
  9180. + default:
  9181. + as_warn (_("unrecognized segment type"));
  9182. + }
  9183. +
  9184. + input_line_pointer = end;
  9185. + SKIP_WHITESPACE();
  9186. +
  9187. + if (*input_line_pointer == ':')
  9188. + {
  9189. + /* ROOT/NOROOT */
  9190. + ++input_line_pointer;
  9191. + SKIP_WHITESPACE();
  9192. +
  9193. + end = input_line_pointer;
  9194. + while (0 == strchr ("\n\t;:( ", *end))
  9195. + end++;
  9196. + length = end - input_line_pointer;
  9197. + if (! ((length == 4) &&
  9198. + (0 == strncasecmp( input_line_pointer, "ROOT", 4))) &&
  9199. + ! ((length == 6) &&
  9200. + (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
  9201. + {
  9202. + as_warn (_("unrecognized segment flag"));
  9203. + }
  9204. +
  9205. + input_line_pointer = end;
  9206. + SKIP_WHITESPACE();
  9207. + }
  9208. + }
  9209. + }
  9210. +
  9211. + if (*input_line_pointer == '(')
  9212. + {
  9213. + align = get_absolute_expression ();
  9214. + }
  9215. +
  9216. + demand_empty_rest_of_line();
  9217. +
  9218. + obj_elf_change_section (name, type, attr, 0, NULL, 0, 0);
  9219. +#ifdef AVR32_DEBUG
  9220. + fprintf( stderr, "RSEG: Changed section to %s, type: 0x%x, attr: 0x%x\n",
  9221. + name, type, attr );
  9222. + fprintf( stderr, "RSEG: Aligning to 2**%d\n", align );
  9223. +#endif
  9224. +
  9225. + if (align > 15)
  9226. + {
  9227. + align = 15;
  9228. + as_warn (_("alignment too large: %u assumed"), align);
  9229. + }
  9230. +
  9231. + /* Hope not, that is */
  9232. + assert (now_seg != absolute_section);
  9233. +
  9234. + /* Only make a frag if we HAVE to... */
  9235. + if (align != 0 && !need_pass_2)
  9236. + {
  9237. + if (subseg_text_p (now_seg))
  9238. + frag_align_code (align, 0);
  9239. + else
  9240. + frag_align (align, 0, 0);
  9241. + }
  9242. +
  9243. + record_alignment (now_seg, align - OCTETS_PER_BYTE_POWER);
  9244. +}
  9245. +
  9246. +/* vim: syntax=c sw=2
  9247. + */
  9248. --- /dev/null
  9249. +++ b/gas/config/tc-avr32.h
  9250. @@ -0,0 +1,325 @@
  9251. +/* Assembler definitions for AVR32.
  9252. + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  9253. +
  9254. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  9255. +
  9256. + This file is part of GAS, the GNU Assembler.
  9257. +
  9258. + GAS is free software; you can redistribute it and/or modify it
  9259. + under the terms of the GNU General Public License as published by
  9260. + the Free Software Foundation; either version 2, or (at your option)
  9261. + any later version.
  9262. +
  9263. + GAS is distributed in the hope that it will be useful, but WITHOUT
  9264. + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  9265. + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  9266. + License for more details.
  9267. +
  9268. + You should have received a copy of the GNU General Public License
  9269. + along with GAS; see the file COPYING. If not, write to the Free
  9270. + Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  9271. + 02111-1307, USA. */
  9272. +
  9273. +#if 0
  9274. +#define DEBUG
  9275. +#define DEBUG1
  9276. +#define DEBUG2
  9277. +#define DEBUG3
  9278. +#define DEBUG4
  9279. +#define DEBUG5
  9280. +#endif
  9281. +
  9282. +/* Are we trying to be compatible with the IAR assembler? (--iar) */
  9283. +extern int avr32_iarcompat;
  9284. +
  9285. +/* By convention, you should define this macro in the `.h' file. For
  9286. + example, `tc-m68k.h' defines `TC_M68K'. You might have to use this
  9287. + if it is necessary to add CPU specific code to the object format
  9288. + file. */
  9289. +#define TC_AVR32
  9290. +
  9291. +/* This macro is the BFD target name to use when creating the output
  9292. + file. This will normally depend upon the `OBJ_FMT' macro. */
  9293. +#define TARGET_FORMAT "elf32-avr32"
  9294. +
  9295. +/* This macro is the BFD architecture to pass to `bfd_set_arch_mach'. */
  9296. +#define TARGET_ARCH bfd_arch_avr32
  9297. +
  9298. +/* This macro is the BFD machine number to pass to
  9299. + `bfd_set_arch_mach'. If it is not defined, GAS will use 0. */
  9300. +#define TARGET_MACH 0
  9301. +
  9302. +/* UNDOCUMENTED: Allow //-style comments */
  9303. +#define DOUBLESLASH_LINE_COMMENTS
  9304. +
  9305. +/* You should define this macro to be non-zero if the target is big
  9306. + endian, and zero if the target is little endian. */
  9307. +#define TARGET_BYTES_BIG_ENDIAN 1
  9308. +
  9309. +/* FIXME: It seems that GAS only expects a one-byte opcode...
  9310. + #define NOP_OPCODE 0xd703 */
  9311. +
  9312. +/* If you define this macro, GAS will warn about the use of
  9313. + nonstandard escape sequences in a string. */
  9314. +#undef ONLY_STANDARD_ESCAPES
  9315. +
  9316. +#define DWARF2_FORMAT(SEC) dwarf2_format_32bit
  9317. +
  9318. +/* Instructions are either 2 or 4 bytes long */
  9319. +/* #define DWARF2_LINE_MIN_INSN_LENGTH 2 */
  9320. +
  9321. +/* GAS will call this function for any expression that can not be
  9322. + recognized. When the function is called, `input_line_pointer'
  9323. + will point to the start of the expression. */
  9324. +#define md_operand(x)
  9325. +
  9326. +#define md_parse_name(name, expr, mode, c) avr32_parse_name(name, expr, c)
  9327. +extern int avr32_parse_name(const char *, struct expressionS *, char *);
  9328. +
  9329. +/* You may define this macro to generate a fixup for a data
  9330. + allocation pseudo-op. */
  9331. +#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
  9332. + avr32_cons_fix_new(FRAG, OFF, LEN, EXP)
  9333. +void avr32_cons_fix_new (fragS *, int, int, expressionS *);
  9334. +
  9335. +/* `extsym - .' expressions can be emitted using PC-relative relocs */
  9336. +#define DIFF_EXPR_OK
  9337. +
  9338. +/* This is used to construct expressions out of @gotoff, etc. The
  9339. + relocation type is stored in X_md */
  9340. +#define O_got O_md1
  9341. +#define O_hi O_md2
  9342. +#define O_lo O_md3
  9343. +#define O_tlsgd O_md4
  9344. +
  9345. +/* You may define this macro to parse an expression used in a data
  9346. + allocation pseudo-op such as `.word'. You can use this to
  9347. + recognize relocation directives that may appear in such directives. */
  9348. +/* #define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR,N)
  9349. + void avr_parse_cons_expression (expressionS *exp, int nbytes); */
  9350. +
  9351. +/* This should just call either `number_to_chars_bigendian' or
  9352. + `number_to_chars_littleendian', whichever is appropriate. On
  9353. + targets like the MIPS which support options to change the
  9354. + endianness, which function to call is a runtime decision. On
  9355. + other targets, `md_number_to_chars' can be a simple macro. */
  9356. +#define md_number_to_chars number_to_chars_bigendian
  9357. +
  9358. +/* `md_short_jump_size'
  9359. + `md_long_jump_size'
  9360. + `md_create_short_jump'
  9361. + `md_create_long_jump'
  9362. + If `WORKING_DOT_WORD' is defined, GAS will not do broken word
  9363. + processing (*note Broken words::.). Otherwise, you should set
  9364. + `md_short_jump_size' to the size of a short jump (a jump that is
  9365. + just long enough to jump around a long jmp) and
  9366. + `md_long_jump_size' to the size of a long jump (a jump that can go
  9367. + anywhere in the function), You should define
  9368. + `md_create_short_jump' to create a short jump around a long jump,
  9369. + and define `md_create_long_jump' to create a long jump. */
  9370. +#define WORKING_DOT_WORD
  9371. +
  9372. +/* If you define this macro, it means that `tc_gen_reloc' may return
  9373. + multiple relocation entries for a single fixup. In this case, the
  9374. + return value of `tc_gen_reloc' is a pointer to a null terminated
  9375. + array. */
  9376. +#undef RELOC_EXPANSION_POSSIBLE
  9377. +
  9378. +/* If you define this macro, GAS will not require pseudo-ops to start with a .
  9379. + character. */
  9380. +#define NO_PSEUDO_DOT (avr32_iarcompat)
  9381. +
  9382. +/* The IAR assembler uses $ as the location counter. Unfortunately, we
  9383. + can't make this dependent on avr32_iarcompat... */
  9384. +#define DOLLAR_DOT
  9385. +
  9386. +/* Values passed to md_apply_fix3 don't include the symbol value. */
  9387. +#define MD_APPLY_SYM_VALUE(FIX) 0
  9388. +
  9389. +/* The number of bytes to put into a word in a listing. This affects
  9390. + the way the bytes are clumped together in the listing. For
  9391. + example, a value of 2 might print `1234 5678' where a value of 1
  9392. + would print `12 34 56 78'. The default value is 4. */
  9393. +#define LISTING_WORD_SIZE 4
  9394. +
  9395. +/* extern const struct relax_type md_relax_table[];
  9396. +#define TC_GENERIC_RELAX_TABLE md_relax_table */
  9397. +
  9398. +/*
  9399. + An `.lcomm' directive with no explicit alignment parameter will use
  9400. + this macro to set P2VAR to the alignment that a request for SIZE
  9401. + bytes will have. The alignment is expressed as a power of two. If
  9402. + no alignment should take place, the macro definition should do
  9403. + nothing. Some targets define a `.bss' directive that is also
  9404. + affected by this macro. The default definition will set P2VAR to
  9405. + the truncated power of two of sizes up to eight bytes.
  9406. +
  9407. + We want doublewords to be word-aligned, so we're going to modify the
  9408. + default definition a tiny bit.
  9409. +*/
  9410. +#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) \
  9411. + do \
  9412. + { \
  9413. + if ((SIZE) >= 4) \
  9414. + (P2VAR) = 2; \
  9415. + else if ((SIZE) >= 2) \
  9416. + (P2VAR) = 1; \
  9417. + else \
  9418. + (P2VAR) = 0; \
  9419. + } \
  9420. + while (0)
  9421. +
  9422. +/* When relaxing, we need to generate relocations for alignment
  9423. + directives. */
  9424. +#define HANDLE_ALIGN(frag) avr32_handle_align(frag)
  9425. +extern void avr32_handle_align(fragS *);
  9426. +
  9427. +/* See internals doc for explanation. Oh wait...
  9428. + Now, can you guess where "alignment" comes from? ;-) */
  9429. +#define MAX_MEM_FOR_RS_ALIGN_CODE ((1 << alignment) - 1)
  9430. +
  9431. +/* We need to stop gas from reducing certain expressions (e.g. GOT
  9432. + references) */
  9433. +#define tc_fix_adjustable(fix) avr32_fix_adjustable(fix)
  9434. +extern bfd_boolean avr32_fix_adjustable(struct fix *);
  9435. +
  9436. +/* The linker needs to be passed a little more information when relaxing. */
  9437. +#define TC_FORCE_RELOCATION(fix) avr32_force_reloc(fix)
  9438. +extern bfd_boolean avr32_force_reloc(struct fix *);
  9439. +
  9440. +/* I'm tired of working around all the madness in fixup_segment().
  9441. + This hook will do basically the same things as the generic code,
  9442. + and then it will "goto" right past it. */
  9443. +#define TC_VALIDATE_FIX(FIX, SEG, SKIP) \
  9444. + do \
  9445. + { \
  9446. + avr32_process_fixup(FIX, SEG); \
  9447. + if (!(FIX)->fx_done) \
  9448. + ++seg_reloc_count; \
  9449. + goto SKIP; \
  9450. + } \
  9451. + while (0)
  9452. +extern void avr32_process_fixup(struct fix *fixP, segT this_segment);
  9453. +
  9454. +/* Positive values of TC_FX_SIZE_SLACK allow a target to define
  9455. + fixups that far past the end of a frag. Having such fixups
  9456. + is of course most most likely a bug in setting fx_size correctly.
  9457. + A negative value disables the fixup check entirely, which is
  9458. + appropriate for something like the Renesas / SuperH SH_COUNT
  9459. + reloc. */
  9460. +/* This target is buggy, and sets fix size too large. */
  9461. +#define TC_FX_SIZE_SLACK(FIX) -1
  9462. +
  9463. +/* We don't want the gas core to make any assumptions about our way of
  9464. + doing linkrelaxing. */
  9465. +#define TC_LINKRELAX_FIXUP(SEG) 0
  9466. +
  9467. +/* ... but we do want it to insert lots of padding. */
  9468. +#define LINKER_RELAXING_SHRINKS_ONLY
  9469. +
  9470. +/* Better do it ourselves, really... */
  9471. +#define TC_RELAX_ALIGN(SEG, FRAG, ADDR) avr32_relax_align(SEG, FRAG, ADDR)
  9472. +extern relax_addressT
  9473. +avr32_relax_align(segT segment, fragS *fragP, relax_addressT address);
  9474. +
  9475. +/* Use line number format that is amenable to linker relaxation. */
  9476. +#define DWARF2_USE_FIXED_ADVANCE_PC (linkrelax != 0)
  9477. +
  9478. +/* This is called by write_object_file() just before symbols are
  9479. + attempted converted into section symbols. */
  9480. +#define tc_frob_file_before_adjust() avr32_frob_file()
  9481. +extern void avr32_frob_file(void);
  9482. +
  9483. +/* If you define this macro, GAS will call it at the end of each input
  9484. + file. */
  9485. +#define md_cleanup() avr32_cleanup()
  9486. +extern void avr32_cleanup(void);
  9487. +
  9488. +/* There's an AVR32-specific hack in operand() which creates O_md
  9489. + expressions when encountering HWRD or LWRD. We need to generate
  9490. + proper relocs for them */
  9491. +/* #define md_cgen_record_fixup_exp avr32_cgen_record_fixup_exp */
  9492. +
  9493. +/* I needed to add an extra hook in gas_cgen_finish_insn() for
  9494. + conversion of O_md* operands because md_cgen_record_fixup_exp()
  9495. + isn't called for relaxable insns */
  9496. +/* #define md_cgen_convert_expr(exp, opinfo) avr32_cgen_convert_expr(exp, opinfo)
  9497. + int avr32_cgen_convert_expr(expressionS *, int); */
  9498. +
  9499. +/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
  9500. +
  9501. +/* If you define this macro, it should return the position from which
  9502. + the PC relative adjustment for a PC relative fixup should be
  9503. + made. On many processors, the base of a PC relative instruction is
  9504. + the next instruction, so this macro would return the length of an
  9505. + instruction, plus the address of the PC relative fixup. The latter
  9506. + can be calculated as fixp->fx_where + fixp->fx_frag->fr_address. */
  9507. +extern long md_pcrel_from_section (struct fix *, segT);
  9508. +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
  9509. +
  9510. +#define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L'))
  9511. +#define LOCAL_LABELS_FB 1
  9512. +
  9513. +struct avr32_relaxer
  9514. +{
  9515. + int (*estimate_size)(fragS *, segT);
  9516. + long (*relax_frag)(segT, fragS *, long);
  9517. + void (*convert_frag)(bfd *, segT, fragS *);
  9518. +};
  9519. +
  9520. +/* AVR32 has quite complex instruction coding, which means we need
  9521. + * lots of information in order to do the right thing during relaxing
  9522. + * (basically, we need to be able to reconstruct a whole new opcode if
  9523. + * necessary) */
  9524. +#define TC_FRAG_TYPE struct avr32_frag_data
  9525. +
  9526. +struct cpool;
  9527. +
  9528. +struct avr32_frag_data
  9529. +{
  9530. + /* TODO: Maybe add an expression object here so that we can use
  9531. + fix_new_exp() in md_convert_frag? We may have to decide
  9532. + pcrel-ness in md_estimate_size_before_relax() as well...or we
  9533. + might do it when parsing. Doing it while parsing may fail
  9534. + because the sub_symbol is undefined then... */
  9535. + int pcrel;
  9536. + int force_extended;
  9537. + int reloc_info;
  9538. + struct avr32_relaxer *relaxer;
  9539. + expressionS exp;
  9540. +
  9541. + /* Points to associated constant pool, for use by LDA and CALL in
  9542. + non-pic mode, and when relaxing the .cpool directive */
  9543. + struct cpool *pool;
  9544. + unsigned int pool_entry;
  9545. +};
  9546. +
  9547. +/* We will have to initialize the fields explicitly when needed */
  9548. +#define TC_FRAG_INIT(fragP)
  9549. +
  9550. +#define md_estimate_size_before_relax(fragP, segT) \
  9551. + ((fragP)->tc_frag_data.relaxer->estimate_size(fragP, segT))
  9552. +#define md_relax_frag(segment, fragP, stretch) \
  9553. + ((fragP)->tc_frag_data.relaxer->relax_frag(segment, fragP, stretch))
  9554. +#define md_convert_frag(abfd, segment, fragP) \
  9555. + ((fragP)->tc_frag_data.relaxer->convert_frag(abfd, segment, fragP))
  9556. +
  9557. +#define TC_FIX_TYPE struct avr32_fix_data
  9558. +
  9559. +struct avr32_fix_data
  9560. +{
  9561. + const struct avr32_ifield *ifield;
  9562. + unsigned int align;
  9563. + long min;
  9564. + long max;
  9565. +};
  9566. +
  9567. +#define TC_INIT_FIX_DATA(fixP) \
  9568. + do \
  9569. + { \
  9570. + (fixP)->tc_fix_data.ifield = NULL; \
  9571. + (fixP)->tc_fix_data.align = 0; \
  9572. + (fixP)->tc_fix_data.min = 0; \
  9573. + (fixP)->tc_fix_data.max = 0; \
  9574. + } \
  9575. + while (0)
  9576. --- a/gas/configure.tgt
  9577. +++ b/gas/configure.tgt
  9578. @@ -33,6 +33,7 @@ case ${cpu} in
  9579. am33_2.0) cpu_type=mn10300 endian=little ;;
  9580. arm*be|arm*b) cpu_type=arm endian=big ;;
  9581. arm*) cpu_type=arm endian=little ;;
  9582. + avr32*) cpu_type=avr32 endian=big ;;
  9583. bfin*) cpu_type=bfin endian=little ;;
  9584. c4x*) cpu_type=tic4x ;;
  9585. cr16*) cpu_type=cr16 endian=little ;;
  9586. @@ -136,6 +137,9 @@ case ${generic_target} in
  9587. cr16-*-elf*) fmt=elf ;;
  9588. + avr32-*-linux*) fmt=elf em=linux bfd_gas=yes ;;
  9589. + avr32*) fmt=elf bfd_gas=yes ;;
  9590. +
  9591. cris-*-linux-* | crisv32-*-linux-*)
  9592. fmt=multi em=linux ;;
  9593. cris-*-* | crisv32-*-*) fmt=multi ;;
  9594. --- a/gas/doc/all.texi
  9595. +++ b/gas/doc/all.texi
  9596. @@ -30,6 +30,7 @@
  9597. @set ARC
  9598. @set ARM
  9599. @set AVR
  9600. +@set AVR32
  9601. @set Blackfin
  9602. @set CR16
  9603. @set CRIS
  9604. --- a/gas/doc/asconfig.texi
  9605. +++ b/gas/doc/asconfig.texi
  9606. @@ -30,6 +30,7 @@
  9607. @set ARC
  9608. @set ARM
  9609. @set AVR
  9610. +@set AVR32
  9611. @set Blackfin
  9612. @set CR16
  9613. @set CRIS
  9614. --- a/gas/doc/as.texinfo
  9615. +++ b/gas/doc/as.texinfo
  9616. @@ -6731,6 +6731,9 @@ subject, see the hardware manufacturer's
  9617. @ifset AVR
  9618. * AVR-Dependent:: AVR Dependent Features
  9619. @end ifset
  9620. +@ifset AVR32
  9621. +* AVR32-Dependent:: AVR32 Dependent Features
  9622. +@end ifset
  9623. @ifset Blackfin
  9624. * Blackfin-Dependent:: Blackfin Dependent Features
  9625. @end ifset
  9626. @@ -6866,6 +6869,10 @@ subject, see the hardware manufacturer's
  9627. @include c-avr.texi
  9628. @end ifset
  9629. +@ifset AVR32
  9630. +@include c-avr32.texi
  9631. +@end ifset
  9632. +
  9633. @ifset Blackfin
  9634. @include c-bfin.texi
  9635. @end ifset
  9636. --- /dev/null
  9637. +++ b/gas/doc/c-avr32.texi
  9638. @@ -0,0 +1,244 @@
  9639. +@c Copyright 2005, 2006, 2007, 2008, 2009
  9640. +@c Atmel Corporation
  9641. +@c This is part of the GAS manual.
  9642. +@c For copying conditions, see the file as.texinfo.
  9643. +
  9644. +@ifset GENERIC
  9645. +@page
  9646. +@node AVR32-Dependent
  9647. +@chapter AVR32 Dependent Features
  9648. +@end ifset
  9649. +
  9650. +@ifclear GENERIC
  9651. +@node Machine Dependencies
  9652. +@chapter AVR32 Dependent Features
  9653. +@end ifclear
  9654. +
  9655. +@cindex AVR32 support
  9656. +@menu
  9657. +* AVR32 Options:: Options
  9658. +* AVR32 Syntax:: Syntax
  9659. +* AVR32 Directives:: Directives
  9660. +* AVR32 Opcodes:: Opcodes
  9661. +@end menu
  9662. +
  9663. +@node AVR32 Options
  9664. +@section Options
  9665. +@cindex AVR32 options
  9666. +@cindex options for AVR32
  9667. +
  9668. +@table @code
  9669. +
  9670. +@cindex @code{--pic} command line option, AVR32
  9671. +@cindex PIC code generation for AVR32
  9672. +@item --pic
  9673. +This option specifies that the output of the assembler should be marked
  9674. +as position-independent code (PIC). It will also ensure that
  9675. +pseudo-instructions that deal with address calculation are output as
  9676. +PIC, and that all absolute address references in the code are marked as
  9677. +such.
  9678. +
  9679. +@cindex @code{--linkrelax} command line option, AVR32
  9680. +@item --linkrelax
  9681. +This option specifies that the output of the assembler should be marked
  9682. +as linker-relaxable. It will also ensure that all PC-relative operands
  9683. +that may change during linker relaxation get appropriate relocations.
  9684. +
  9685. +@end table
  9686. +
  9687. +
  9688. +@node AVR32 Syntax
  9689. +@section Syntax
  9690. +@menu
  9691. +* AVR32-Chars:: Special Characters
  9692. +* AVR32-Symrefs:: Symbol references
  9693. +@end menu
  9694. +
  9695. +@node AVR32-Chars
  9696. +@subsection Special Characters
  9697. +
  9698. +@cindex line comment character, AVR32
  9699. +@cindex AVR32 line comment character
  9700. +The presence of a @samp{//} on a line indicates the start of a comment
  9701. +that extends to the end of the current line. If a @samp{#} appears as
  9702. +the first character of a line, the whole line is treated as a comment.
  9703. +
  9704. +@cindex line separator, AVR32
  9705. +@cindex statement separator, AVR32
  9706. +@cindex AVR32 line separator
  9707. +The @samp{;} character can be used instead of a newline to separate
  9708. +statements.
  9709. +
  9710. +@node AVR32-Symrefs
  9711. +@subsection Symbol references
  9712. +
  9713. +The absolute value of a symbol can be obtained by simply naming the
  9714. +symbol. However, as AVR32 symbols have 32-bit values, most symbols have
  9715. +values that are outside the range of any instructions.
  9716. +
  9717. +Instructions that take a PC-relative offset, e.g. @code{lddpc} or
  9718. +@code{rcall}, can also reference a symbol by simply naming the symbol
  9719. +(no explicit calculations necessary). In this case, the assembler or
  9720. +linker subtracts the address of the instruction from the symbol's value
  9721. +and inserts the result into the instruction. Note that even though an
  9722. +overflow is less likely to happen for a relative reference than for an
  9723. +absolute reference, the assembler or linker will generate an error if
  9724. +the referenced symbol is too far away from the current location.
  9725. +
  9726. +Relative references can be used for data as well. For example:
  9727. +
  9728. +@smallexample
  9729. + lddpc r0, 2f
  9730. +1: add r0, pc
  9731. + ...
  9732. + .align 2
  9733. +2: .int @var{some_symbol} - 1b
  9734. +@end smallexample
  9735. +
  9736. +Here, r0 will end up with the run-time address of @var{some_symbol} even
  9737. +if the program was loaded at a different address than it was linked
  9738. +(position-independent code).
  9739. +
  9740. +@subsubsection Symbol modifiers
  9741. +
  9742. +@table @code
  9743. +
  9744. +@item @code{hi(@var{symbol})}
  9745. +Evaluates to the value of the symbol shifted right 16 bits. This will
  9746. +work even if @var{symbol} is defined in a different module.
  9747. +
  9748. +@item @code{lo(@var{symbol})}
  9749. +Evaluates to the low 16 bits of the symbol's value. This will work even
  9750. +if @var{symbol} is defined in a different module.
  9751. +
  9752. +@item @code{@var{symbol}@@got}
  9753. +Create a GOT entry for @var{symbol} and return the offset of that entry
  9754. +relative to the GOT base.
  9755. +
  9756. +@end table
  9757. +
  9758. +
  9759. +@node AVR32 Directives
  9760. +@section Directives
  9761. +@cindex machine directives, AVR32
  9762. +@cindex AVR32 directives
  9763. +
  9764. +@table @code
  9765. +
  9766. +@cindex @code{.cpool} directive, AVR32
  9767. +@item .cpool
  9768. +This directive causes the current contents of the constant pool to be
  9769. +dumped into the current section at the current location (aligned to a
  9770. +word boundary). @code{GAS} maintains a separate constant pool for each
  9771. +section and each sub-section. The @code{.cpool} directive will only
  9772. +affect the constant pool of the current section and sub-section. At the
  9773. +end of assembly, all remaining, non-empty constant pools will
  9774. +automatically be dumped.
  9775. +
  9776. +@end table
  9777. +
  9778. +
  9779. +@node AVR32 Opcodes
  9780. +@section Opcodes
  9781. +@cindex AVR32 opcodes
  9782. +@cindex opcodes for AVR32
  9783. +
  9784. +@code{@value{AS}} implements all the standard AVR32 opcodes. It also
  9785. +implements several pseudo-opcodes, which are recommended to use wherever
  9786. +possible because they give the tool chain better freedom to generate
  9787. +optimal code.
  9788. +
  9789. +@table @code
  9790. +
  9791. +@cindex @code{LDA.W reg, symbol} pseudo op, AVR32
  9792. +@item LDA.W
  9793. +@smallexample
  9794. + lda.w @var{reg}, @var{symbol}
  9795. +@end smallexample
  9796. +
  9797. +This instruction will load the address of @var{symbol} into
  9798. +@var{reg}. The instruction will evaluate to one of the following,
  9799. +depending on the relative distance to the symbol, the relative distance
  9800. +to the constant pool and whether the @code{--pic} option has been
  9801. +specified. If the @code{--pic} option has not been specified, the
  9802. +alternatives are as follows:
  9803. +@smallexample
  9804. + /* @var{symbol} evaluates to a small enough value */
  9805. + mov @var{reg}, @var{symbol}
  9806. +
  9807. + /* (. - @var{symbol}) evaluates to a small enough value */
  9808. + sub @var{reg}, pc, . - @var{symbol}
  9809. +
  9810. + /* Constant pool is close enough */
  9811. + lddpc @var{reg}, @var{cpent}
  9812. + ...
  9813. +@var{cpent}:
  9814. + .long @var{symbol}
  9815. +
  9816. + /* Otherwise (not implemented yet, probably not necessary) */
  9817. + mov @var{reg}, lo(@var{symbol})
  9818. + orh @var{reg}, hi(@var{symbol})
  9819. +@end smallexample
  9820. +
  9821. +If the @code{--pic} option has been specified, the alternatives are as
  9822. +follows:
  9823. +@smallexample
  9824. + /* (. - @var{symbol}) evaluates to a small enough value */
  9825. + sub @var{reg}, pc, . - @var{symbol}
  9826. +
  9827. + /* If @code{--linkrelax} not specified */
  9828. + ld.w @var{reg}, r6[@var{symbol}@@got]
  9829. +
  9830. + /* Otherwise */
  9831. + mov @var{reg}, @var{symbol}@@got / 4
  9832. + ld.w @var{reg}, r6[@var{reg} << 2]
  9833. +@end smallexample
  9834. +
  9835. +If @var{symbol} is not defined in the same file and section as the
  9836. +@code{LDA.W} instruction, the most pessimistic alternative of the
  9837. +above is selected. The linker may convert it back into the most
  9838. +optimal alternative when the final value of all symbols is known.
  9839. +
  9840. +@cindex @code{CALL symbol} pseudo op, AVR32
  9841. +@item CALL
  9842. +@smallexample
  9843. + call @var{symbol}
  9844. +@end smallexample
  9845. +
  9846. +This instruction will insert code to call the subroutine identified by
  9847. +@var{symbol}. It will evaluate to one of the following, depending on
  9848. +the relative distance to the symbol as well as the @code{--linkrelax}
  9849. +and @code{--pic} command-line options.
  9850. +
  9851. +If @var{symbol} is defined in the same section and input file, and the
  9852. +distance is small enough, an @code{rcall} instruction is inserted:
  9853. +@smallexample
  9854. + rcall @var{symbol}
  9855. +@end smallexample
  9856. +
  9857. +Otherwise, if the @code{--pic} option has not been specified:
  9858. +@smallexample
  9859. + mcall @var{cpent}
  9860. + ...
  9861. +@var{cpent}:
  9862. + .long @var{symbol}
  9863. +@end smallexample
  9864. +
  9865. +Finally, if nothing else fits and the @code{--pic} option has been
  9866. +specified, the assembler will indirect the call through the Global
  9867. +Offset Table:
  9868. +@smallexample
  9869. + /* If @code{--linkrelax} not specified */
  9870. + mcall r6[@var{symbol}@@got]
  9871. +
  9872. + /* If @code{--linkrelax} specified */
  9873. + mov lr, @var{symbol}@@got / 4
  9874. + ld.w lr, r6[lr << 2]
  9875. + icall lr
  9876. +@end smallexample
  9877. +
  9878. +The linker, after determining the final value of @var{symbol}, may
  9879. +convert any of these into more optimal alternatives. This includes
  9880. +deleting any superfluous constant pool- and GOT-entries.
  9881. +
  9882. +@end table
  9883. --- a/gas/doc/Makefile.am
  9884. +++ b/gas/doc/Makefile.am
  9885. @@ -33,6 +33,7 @@ CPU_DOCS = \
  9886. c-arc.texi \
  9887. c-arm.texi \
  9888. c-avr.texi \
  9889. + c-avr32.texi \
  9890. c-bfin.texi \
  9891. c-cr16.texi \
  9892. c-d10v.texi \
  9893. --- a/gas/Makefile.am
  9894. +++ b/gas/Makefile.am
  9895. @@ -43,6 +43,7 @@ CPU_TYPES = \
  9896. arc \
  9897. arm \
  9898. avr \
  9899. + avr32 \
  9900. bfin \
  9901. cr16 \
  9902. cris \
  9903. @@ -244,6 +245,7 @@ TARGET_CPU_CFILES = \
  9904. config/tc-arc.c \
  9905. config/tc-arm.c \
  9906. config/tc-avr.c \
  9907. + config/tc-avr32.c \
  9908. config/tc-bfin.c \
  9909. config/tc-cr16.c \
  9910. config/tc-cris.c \
  9911. @@ -307,6 +309,7 @@ TARGET_CPU_HFILES = \
  9912. config/tc-arc.h \
  9913. config/tc-arm.h \
  9914. config/tc-avr.h \
  9915. + config/tc-avr32.h \
  9916. config/tc-bfin.h \
  9917. config/tc-cr16.h \
  9918. config/tc-cris.h \
  9919. --- /dev/null
  9920. +++ b/gas/testsuite/gas/avr32/aliases.d
  9921. @@ -0,0 +1,19 @@
  9922. +#as:
  9923. +#objdump: -dr
  9924. +#name: aliases
  9925. +
  9926. +.*: +file format .*
  9927. +
  9928. +Disassembly of section \.text:
  9929. +
  9930. +00000000 <ld_nodisp>:
  9931. + 0: 19 80 [ \t]+ld\.ub r0,r12\[0x0\]
  9932. + 2: f9 20 00 00[ \t]+ld\.sb r0,r12\[0\]
  9933. + 6: 98 80 [ \t]+ld\.uh r0,r12\[0x0\]
  9934. + 8: 98 00 [ \t]+ld\.sh r0,r12\[0x0\]
  9935. + a: 78 00 [ \t]+ld\.w r0,r12\[0x0\]
  9936. +
  9937. +0000000c <st_nodisp>:
  9938. + c: b8 80 [ \t]+st\.b r12\[0x0\],r0
  9939. + e: b8 00 [ \t]+st\.h r12\[0x0\],r0
  9940. + 10: 99 00 [ \t]+st\.w r12\[0x0\],r0
  9941. --- /dev/null
  9942. +++ b/gas/testsuite/gas/avr32/aliases.s
  9943. @@ -0,0 +1,14 @@
  9944. + .text
  9945. + .global ld_nodisp
  9946. +ld_nodisp:
  9947. + ld.ub r0, r12
  9948. + ld.sb r0, r12
  9949. + ld.uh r0, r12
  9950. + ld.sh r0, r12
  9951. + ld.w r0, r12
  9952. +
  9953. + .global st_nodisp
  9954. +st_nodisp:
  9955. + st.b r12, r0
  9956. + st.h r12, r0
  9957. + st.w r12, r0
  9958. --- /dev/null
  9959. +++ b/gas/testsuite/gas/avr32/allinsn.d
  9960. @@ -0,0 +1,2987 @@
  9961. +#as:
  9962. +#objdump: -dr
  9963. +#name: allinsn
  9964. +
  9965. +.*: +file format .*
  9966. +
  9967. +Disassembly of section \.text:
  9968. +
  9969. +[0-9a-f]* <ld_d5>:
  9970. + *[0-9a-f]*: fe 0f 02 3e ld\.d lr,pc\[pc<<0x3\]
  9971. + *[0-9a-f]*: e0 00 02 00 ld\.d r0,r0\[r0\]
  9972. + *[0-9a-f]*: ea 05 02 26 ld\.d r6,r5\[r5<<0x2\]
  9973. + *[0-9a-f]*: e8 04 02 14 ld\.d r4,r4\[r4<<0x1\]
  9974. + *[0-9a-f]*: fc 0e 02 1e ld\.d lr,lr\[lr<<0x1\]
  9975. + *[0-9a-f]*: e6 0d 02 2a ld\.d r10,r3\[sp<<0x2\]
  9976. + *[0-9a-f]*: f4 06 02 28 ld\.d r8,r10\[r6<<0x2\]
  9977. + *[0-9a-f]*: ee 09 02 02 ld\.d r2,r7\[r9\]
  9978. +
  9979. +[0-9a-f]* <ld_w5>:
  9980. + *[0-9a-f]*: fe 0f 03 0f ld\.w pc,pc\[pc\]
  9981. + *[0-9a-f]*: f8 0c 03 3c ld\.w r12,r12\[r12<<0x3\]
  9982. + *[0-9a-f]*: ea 05 03 25 ld\.w r5,r5\[r5<<0x2\]
  9983. + *[0-9a-f]*: e8 04 03 14 ld\.w r4,r4\[r4<<0x1\]
  9984. + *[0-9a-f]*: fc 0e 03 1e ld\.w lr,lr\[lr<<0x1\]
  9985. + *[0-9a-f]*: f2 09 03 02 ld\.w r2,r9\[r9\]
  9986. + *[0-9a-f]*: e4 06 03 0b ld\.w r11,r2\[r6\]
  9987. + *[0-9a-f]*: e4 0d 03 30 ld\.w r0,r2\[sp<<0x3\]
  9988. +
  9989. +[0-9a-f]* <ld_sh5>:
  9990. + *[0-9a-f]*: fe 0f 04 0f ld\.sh pc,pc\[pc\]
  9991. + *[0-9a-f]*: f8 0c 04 3c ld\.sh r12,r12\[r12<<0x3\]
  9992. + *[0-9a-f]*: ea 05 04 25 ld\.sh r5,r5\[r5<<0x2\]
  9993. + *[0-9a-f]*: e8 04 04 14 ld\.sh r4,r4\[r4<<0x1\]
  9994. + *[0-9a-f]*: fc 0e 04 1e ld\.sh lr,lr\[lr<<0x1\]
  9995. + *[0-9a-f]*: e0 0f 04 2b ld\.sh r11,r0\[pc<<0x2\]
  9996. + *[0-9a-f]*: fa 06 04 2a ld\.sh r10,sp\[r6<<0x2\]
  9997. + *[0-9a-f]*: e4 02 04 0c ld\.sh r12,r2\[r2\]
  9998. +
  9999. +[0-9a-f]* <ld_uh5>:
  10000. + *[0-9a-f]*: fe 0f 05 0f ld\.uh pc,pc\[pc\]
  10001. + *[0-9a-f]*: f8 0c 05 3c ld\.uh r12,r12\[r12<<0x3\]
  10002. + *[0-9a-f]*: ea 05 05 25 ld\.uh r5,r5\[r5<<0x2\]
  10003. + *[0-9a-f]*: e8 04 05 14 ld\.uh r4,r4\[r4<<0x1\]
  10004. + *[0-9a-f]*: fc 0e 05 1e ld\.uh lr,lr\[lr<<0x1\]
  10005. + *[0-9a-f]*: fe 0e 05 38 ld\.uh r8,pc\[lr<<0x3\]
  10006. + *[0-9a-f]*: e2 0f 05 16 ld\.uh r6,r1\[pc<<0x1\]
  10007. + *[0-9a-f]*: fc 0d 05 16 ld\.uh r6,lr\[sp<<0x1\]
  10008. +
  10009. +[0-9a-f]* <ld_sb2>:
  10010. + *[0-9a-f]*: fe 0f 06 0f ld\.sb pc,pc\[pc\]
  10011. + *[0-9a-f]*: f8 0c 06 3c ld\.sb r12,r12\[r12<<0x3\]
  10012. + *[0-9a-f]*: ea 05 06 25 ld\.sb r5,r5\[r5<<0x2\]
  10013. + *[0-9a-f]*: e8 04 06 14 ld\.sb r4,r4\[r4<<0x1\]
  10014. + *[0-9a-f]*: fc 0e 06 1e ld\.sb lr,lr\[lr<<0x1\]
  10015. + *[0-9a-f]*: e2 0f 06 39 ld\.sb r9,r1\[pc<<0x3\]
  10016. + *[0-9a-f]*: e6 0b 06 10 ld\.sb r0,r3\[r11<<0x1\]
  10017. + *[0-9a-f]*: ea 05 06 1a ld\.sb r10,r5\[r5<<0x1\]
  10018. +
  10019. +[0-9a-f]* <ld_ub5>:
  10020. + *[0-9a-f]*: fe 0f 07 0f ld\.ub pc,pc\[pc\]
  10021. + *[0-9a-f]*: f8 0c 07 3c ld\.ub r12,r12\[r12<<0x3\]
  10022. + *[0-9a-f]*: ea 05 07 25 ld\.ub r5,r5\[r5<<0x2\]
  10023. + *[0-9a-f]*: e8 04 07 14 ld\.ub r4,r4\[r4<<0x1\]
  10024. + *[0-9a-f]*: fc 0e 07 1e ld\.ub lr,lr\[lr<<0x1\]
  10025. + *[0-9a-f]*: f8 07 07 36 ld\.ub r6,r12\[r7<<0x3\]
  10026. + *[0-9a-f]*: ec 0c 07 02 ld\.ub r2,r6\[r12\]
  10027. + *[0-9a-f]*: ee 0b 07 10 ld\.ub r0,r7\[r11<<0x1\]
  10028. +
  10029. +[0-9a-f]* <st_d5>:
  10030. + *[0-9a-f]*: fe 0f 08 0e st\.d pc\[pc\],lr
  10031. + *[0-9a-f]*: f8 0c 08 3c st\.d r12\[r12<<0x3\],r12
  10032. + *[0-9a-f]*: ea 05 08 26 st\.d r5\[r5<<0x2\],r6
  10033. + *[0-9a-f]*: e8 04 08 14 st\.d r4\[r4<<0x1\],r4
  10034. + *[0-9a-f]*: fc 0e 08 1e st\.d lr\[lr<<0x1\],lr
  10035. + *[0-9a-f]*: e2 09 08 14 st\.d r1\[r9<<0x1\],r4
  10036. + *[0-9a-f]*: f4 02 08 14 st\.d r10\[r2<<0x1\],r4
  10037. + *[0-9a-f]*: f8 06 08 0e st\.d r12\[r6\],lr
  10038. +
  10039. +[0-9a-f]* <st_w5>:
  10040. + *[0-9a-f]*: fe 0f 09 0f st\.w pc\[pc\],pc
  10041. + *[0-9a-f]*: f8 0c 09 3c st\.w r12\[r12<<0x3\],r12
  10042. + *[0-9a-f]*: ea 05 09 25 st\.w r5\[r5<<0x2\],r5
  10043. + *[0-9a-f]*: e8 04 09 14 st\.w r4\[r4<<0x1\],r4
  10044. + *[0-9a-f]*: fc 0e 09 1e st\.w lr\[lr<<0x1\],lr
  10045. + *[0-9a-f]*: e2 0a 09 03 st\.w r1\[r10\],r3
  10046. + *[0-9a-f]*: e0 0a 09 19 st\.w r0\[r10<<0x1\],r9
  10047. + *[0-9a-f]*: e8 05 09 3f st\.w r4\[r5<<0x3\],pc
  10048. +
  10049. +[0-9a-f]* <st_h5>:
  10050. + *[0-9a-f]*: fe 0f 0a 0f st\.h pc\[pc\],pc
  10051. + *[0-9a-f]*: f8 0c 0a 3c st\.h r12\[r12<<0x3\],r12
  10052. + *[0-9a-f]*: ea 05 0a 25 st\.h r5\[r5<<0x2\],r5
  10053. + *[0-9a-f]*: e8 04 0a 14 st\.h r4\[r4<<0x1\],r4
  10054. + *[0-9a-f]*: fc 0e 0a 1e st\.h lr\[lr<<0x1\],lr
  10055. + *[0-9a-f]*: e4 09 0a 0b st\.h r2\[r9\],r11
  10056. + *[0-9a-f]*: ea 01 0a 2c st\.h r5\[r1<<0x2\],r12
  10057. + *[0-9a-f]*: fe 08 0a 23 st\.h pc\[r8<<0x2\],r3
  10058. +
  10059. +[0-9a-f]* <st_b5>:
  10060. + *[0-9a-f]*: fe 0f 0b 0f st\.b pc\[pc\],pc
  10061. + *[0-9a-f]*: f8 0c 0b 3c st\.b r12\[r12<<0x3\],r12
  10062. + *[0-9a-f]*: ea 05 0b 25 st\.b r5\[r5<<0x2\],r5
  10063. + *[0-9a-f]*: e8 04 0b 14 st\.b r4\[r4<<0x1\],r4
  10064. + *[0-9a-f]*: fc 0e 0b 1e st\.b lr\[lr<<0x1\],lr
  10065. + *[0-9a-f]*: e2 08 0b 16 st\.b r1\[r8<<0x1\],r6
  10066. + *[0-9a-f]*: fc 0e 0b 31 st\.b lr\[lr<<0x3\],r1
  10067. + *[0-9a-f]*: ea 00 0b 2f st\.b r5\[r0<<0x2\],pc
  10068. +
  10069. +[0-9a-f]* <divs>:
  10070. + *[0-9a-f]*: fe 0f 0c 0f divs pc,pc,pc
  10071. + *[0-9a-f]*: f8 0c 0c 0c divs r12,r12,r12
  10072. + *[0-9a-f]*: ea 05 0c 05 divs r5,r5,r5
  10073. + *[0-9a-f]*: e8 04 0c 04 divs r4,r4,r4
  10074. + *[0-9a-f]*: fc 0e 0c 0e divs lr,lr,lr
  10075. + *[0-9a-f]*: fe 0f 0c 03 divs r3,pc,pc
  10076. + *[0-9a-f]*: f8 02 0c 09 divs r9,r12,r2
  10077. + *[0-9a-f]*: e8 01 0c 07 divs r7,r4,r1
  10078. +
  10079. +[0-9a-f]* <add1>:
  10080. + *[0-9a-f]*: 1e 0f add pc,pc
  10081. + *[0-9a-f]*: 18 0c add r12,r12
  10082. + *[0-9a-f]*: 0a 05 add r5,r5
  10083. + *[0-9a-f]*: 08 04 add r4,r4
  10084. + *[0-9a-f]*: 1c 0e add lr,lr
  10085. + *[0-9a-f]*: 12 0c add r12,r9
  10086. + *[0-9a-f]*: 06 06 add r6,r3
  10087. + *[0-9a-f]*: 18 0a add r10,r12
  10088. +
  10089. +[0-9a-f]* <sub1>:
  10090. + *[0-9a-f]*: 1e 1f sub pc,pc
  10091. + *[0-9a-f]*: 18 1c sub r12,r12
  10092. + *[0-9a-f]*: 0a 15 sub r5,r5
  10093. + *[0-9a-f]*: 08 14 sub r4,r4
  10094. + *[0-9a-f]*: 1c 1e sub lr,lr
  10095. + *[0-9a-f]*: 0c 1e sub lr,r6
  10096. + *[0-9a-f]*: 1a 10 sub r0,sp
  10097. + *[0-9a-f]*: 18 16 sub r6,r12
  10098. +
  10099. +[0-9a-f]* <rsub1>:
  10100. + *[0-9a-f]*: 1e 2f rsub pc,pc
  10101. + *[0-9a-f]*: 18 2c rsub r12,r12
  10102. + *[0-9a-f]*: 0a 25 rsub r5,r5
  10103. + *[0-9a-f]*: 08 24 rsub r4,r4
  10104. + *[0-9a-f]*: 1c 2e rsub lr,lr
  10105. + *[0-9a-f]*: 1a 2b rsub r11,sp
  10106. + *[0-9a-f]*: 08 27 rsub r7,r4
  10107. + *[0-9a-f]*: 02 29 rsub r9,r1
  10108. +
  10109. +[0-9a-f]* <cp1>:
  10110. + *[0-9a-f]*: 1e 3f cp\.w pc,pc
  10111. + *[0-9a-f]*: 18 3c cp\.w r12,r12
  10112. + *[0-9a-f]*: 0a 35 cp\.w r5,r5
  10113. + *[0-9a-f]*: 08 34 cp\.w r4,r4
  10114. + *[0-9a-f]*: 1c 3e cp\.w lr,lr
  10115. + *[0-9a-f]*: 04 36 cp\.w r6,r2
  10116. + *[0-9a-f]*: 12 30 cp\.w r0,r9
  10117. + *[0-9a-f]*: 1a 33 cp\.w r3,sp
  10118. +
  10119. +[0-9a-f]* <or1>:
  10120. + *[0-9a-f]*: 1e 4f or pc,pc
  10121. + *[0-9a-f]*: 18 4c or r12,r12
  10122. + *[0-9a-f]*: 0a 45 or r5,r5
  10123. + *[0-9a-f]*: 08 44 or r4,r4
  10124. + *[0-9a-f]*: 1c 4e or lr,lr
  10125. + *[0-9a-f]*: 12 44 or r4,r9
  10126. + *[0-9a-f]*: 08 4b or r11,r4
  10127. + *[0-9a-f]*: 00 44 or r4,r0
  10128. +
  10129. +[0-9a-f]* <eor1>:
  10130. + *[0-9a-f]*: 1e 5f eor pc,pc
  10131. + *[0-9a-f]*: 18 5c eor r12,r12
  10132. + *[0-9a-f]*: 0a 55 eor r5,r5
  10133. + *[0-9a-f]*: 08 54 eor r4,r4
  10134. + *[0-9a-f]*: 1c 5e eor lr,lr
  10135. + *[0-9a-f]*: 16 5c eor r12,r11
  10136. + *[0-9a-f]*: 02 50 eor r0,r1
  10137. + *[0-9a-f]*: 1e 55 eor r5,pc
  10138. +
  10139. +[0-9a-f]* <and1>:
  10140. + *[0-9a-f]*: 1e 6f and pc,pc
  10141. + *[0-9a-f]*: 18 6c and r12,r12
  10142. + *[0-9a-f]*: 0a 65 and r5,r5
  10143. + *[0-9a-f]*: 08 64 and r4,r4
  10144. + *[0-9a-f]*: 1c 6e and lr,lr
  10145. + *[0-9a-f]*: 02 68 and r8,r1
  10146. + *[0-9a-f]*: 1a 60 and r0,sp
  10147. + *[0-9a-f]*: 0a 6a and r10,r5
  10148. +
  10149. +[0-9a-f]* <tst>:
  10150. + *[0-9a-f]*: 1e 7f tst pc,pc
  10151. + *[0-9a-f]*: 18 7c tst r12,r12
  10152. + *[0-9a-f]*: 0a 75 tst r5,r5
  10153. + *[0-9a-f]*: 08 74 tst r4,r4
  10154. + *[0-9a-f]*: 1c 7e tst lr,lr
  10155. + *[0-9a-f]*: 18 70 tst r0,r12
  10156. + *[0-9a-f]*: 0c 7a tst r10,r6
  10157. + *[0-9a-f]*: 08 7d tst sp,r4
  10158. +
  10159. +[0-9a-f]* <andn>:
  10160. + *[0-9a-f]*: 1e 8f andn pc,pc
  10161. + *[0-9a-f]*: 18 8c andn r12,r12
  10162. + *[0-9a-f]*: 0a 85 andn r5,r5
  10163. + *[0-9a-f]*: 08 84 andn r4,r4
  10164. + *[0-9a-f]*: 1c 8e andn lr,lr
  10165. + *[0-9a-f]*: 18 89 andn r9,r12
  10166. + *[0-9a-f]*: 1a 8b andn r11,sp
  10167. + *[0-9a-f]*: 0a 8c andn r12,r5
  10168. +
  10169. +[0-9a-f]* <mov3>:
  10170. + *[0-9a-f]*: 1e 9f mov pc,pc
  10171. + *[0-9a-f]*: 18 9c mov r12,r12
  10172. + *[0-9a-f]*: 0a 95 mov r5,r5
  10173. + *[0-9a-f]*: 08 94 mov r4,r4
  10174. + *[0-9a-f]*: 1c 9e mov lr,lr
  10175. + *[0-9a-f]*: 12 95 mov r5,r9
  10176. + *[0-9a-f]*: 16 9b mov r11,r11
  10177. + *[0-9a-f]*: 1c 92 mov r2,lr
  10178. +
  10179. +[0-9a-f]* <st_w1>:
  10180. + *[0-9a-f]*: 1e af st\.w pc\+\+,pc
  10181. + *[0-9a-f]*: 18 ac st\.w r12\+\+,r12
  10182. + *[0-9a-f]*: 0a a5 st\.w r5\+\+,r5
  10183. + *[0-9a-f]*: 08 a4 st\.w r4\+\+,r4
  10184. + *[0-9a-f]*: 1c ae st\.w lr\+\+,lr
  10185. + *[0-9a-f]*: 02 ab st\.w r1\+\+,r11
  10186. + *[0-9a-f]*: 1a a0 st\.w sp\+\+,r0
  10187. + *[0-9a-f]*: 1a a1 st\.w sp\+\+,r1
  10188. +
  10189. +[0-9a-f]* <st_h1>:
  10190. + *[0-9a-f]*: 1e bf st\.h pc\+\+,pc
  10191. + *[0-9a-f]*: 18 bc st\.h r12\+\+,r12
  10192. + *[0-9a-f]*: 0a b5 st\.h r5\+\+,r5
  10193. + *[0-9a-f]*: 08 b4 st\.h r4\+\+,r4
  10194. + *[0-9a-f]*: 1c be st\.h lr\+\+,lr
  10195. + *[0-9a-f]*: 18 bd st\.h r12\+\+,sp
  10196. + *[0-9a-f]*: 0e be st\.h r7\+\+,lr
  10197. + *[0-9a-f]*: 0e b4 st\.h r7\+\+,r4
  10198. +
  10199. +[0-9a-f]* <st_b1>:
  10200. + *[0-9a-f]*: 1e cf st\.b pc\+\+,pc
  10201. + *[0-9a-f]*: 18 cc st\.b r12\+\+,r12
  10202. + *[0-9a-f]*: 0a c5 st\.b r5\+\+,r5
  10203. + *[0-9a-f]*: 08 c4 st\.b r4\+\+,r4
  10204. + *[0-9a-f]*: 1c ce st\.b lr\+\+,lr
  10205. + *[0-9a-f]*: 12 cd st\.b r9\+\+,sp
  10206. + *[0-9a-f]*: 02 cd st\.b r1\+\+,sp
  10207. + *[0-9a-f]*: 00 c4 st\.b r0\+\+,r4
  10208. +
  10209. +[0-9a-f]* <st_w2>:
  10210. + *[0-9a-f]*: 1e df st\.w --pc,pc
  10211. + *[0-9a-f]*: 18 dc st\.w --r12,r12
  10212. + *[0-9a-f]*: 0a d5 st\.w --r5,r5
  10213. + *[0-9a-f]*: 08 d4 st\.w --r4,r4
  10214. + *[0-9a-f]*: 1c de st\.w --lr,lr
  10215. + *[0-9a-f]*: 02 d7 st\.w --r1,r7
  10216. + *[0-9a-f]*: 06 d9 st\.w --r3,r9
  10217. + *[0-9a-f]*: 0a d5 st\.w --r5,r5
  10218. +
  10219. +[0-9a-f]* <st_h2>:
  10220. + *[0-9a-f]*: 1e ef st\.h --pc,pc
  10221. + *[0-9a-f]*: 18 ec st\.h --r12,r12
  10222. + *[0-9a-f]*: 0a e5 st\.h --r5,r5
  10223. + *[0-9a-f]*: 08 e4 st\.h --r4,r4
  10224. + *[0-9a-f]*: 1c ee st\.h --lr,lr
  10225. + *[0-9a-f]*: 0a e7 st\.h --r5,r7
  10226. + *[0-9a-f]*: 10 e8 st\.h --r8,r8
  10227. + *[0-9a-f]*: 0e e2 st\.h --r7,r2
  10228. +
  10229. +[0-9a-f]* <st_b2>:
  10230. + *[0-9a-f]*: 1e ff st\.b --pc,pc
  10231. + *[0-9a-f]*: 18 fc st\.b --r12,r12
  10232. + *[0-9a-f]*: 0a f5 st\.b --r5,r5
  10233. + *[0-9a-f]*: 08 f4 st\.b --r4,r4
  10234. + *[0-9a-f]*: 1c fe st\.b --lr,lr
  10235. + *[0-9a-f]*: 1a fd st\.b --sp,sp
  10236. + *[0-9a-f]*: 1a fb st\.b --sp,r11
  10237. + *[0-9a-f]*: 08 f5 st\.b --r4,r5
  10238. +
  10239. +[0-9a-f]* <ld_w1>:
  10240. + *[0-9a-f]*: 1f 0f ld\.w pc,pc\+\+
  10241. + *[0-9a-f]*: 19 0c ld\.w r12,r12\+\+
  10242. + *[0-9a-f]*: 0b 05 ld\.w r5,r5\+\+
  10243. + *[0-9a-f]*: 09 04 ld\.w r4,r4\+\+
  10244. + *[0-9a-f]*: 1d 0e ld\.w lr,lr\+\+
  10245. + *[0-9a-f]*: 0f 03 ld\.w r3,r7\+\+
  10246. + *[0-9a-f]*: 1d 03 ld\.w r3,lr\+\+
  10247. + *[0-9a-f]*: 0b 0c ld\.w r12,r5\+\+
  10248. +
  10249. +[0-9a-f]* <ld_sh1>:
  10250. + *[0-9a-f]*: 1f 1f ld\.sh pc,pc\+\+
  10251. + *[0-9a-f]*: 19 1c ld\.sh r12,r12\+\+
  10252. + *[0-9a-f]*: 0b 15 ld\.sh r5,r5\+\+
  10253. + *[0-9a-f]*: 09 14 ld\.sh r4,r4\+\+
  10254. + *[0-9a-f]*: 1d 1e ld\.sh lr,lr\+\+
  10255. + *[0-9a-f]*: 05 1b ld\.sh r11,r2\+\+
  10256. + *[0-9a-f]*: 11 12 ld\.sh r2,r8\+\+
  10257. + *[0-9a-f]*: 0d 17 ld\.sh r7,r6\+\+
  10258. +
  10259. +[0-9a-f]* <ld_uh1>:
  10260. + *[0-9a-f]*: 1f 2f ld\.uh pc,pc\+\+
  10261. + *[0-9a-f]*: 19 2c ld\.uh r12,r12\+\+
  10262. + *[0-9a-f]*: 0b 25 ld\.uh r5,r5\+\+
  10263. + *[0-9a-f]*: 09 24 ld\.uh r4,r4\+\+
  10264. + *[0-9a-f]*: 1d 2e ld\.uh lr,lr\+\+
  10265. + *[0-9a-f]*: 0f 26 ld\.uh r6,r7\+\+
  10266. + *[0-9a-f]*: 17 2a ld\.uh r10,r11\+\+
  10267. + *[0-9a-f]*: 09 2e ld\.uh lr,r4\+\+
  10268. +
  10269. +[0-9a-f]* <ld_ub1>:
  10270. + *[0-9a-f]*: 1f 3f ld\.ub pc,pc\+\+
  10271. + *[0-9a-f]*: 19 3c ld\.ub r12,r12\+\+
  10272. + *[0-9a-f]*: 0b 35 ld\.ub r5,r5\+\+
  10273. + *[0-9a-f]*: 09 34 ld\.ub r4,r4\+\+
  10274. + *[0-9a-f]*: 1d 3e ld\.ub lr,lr\+\+
  10275. + *[0-9a-f]*: 1d 38 ld\.ub r8,lr\+\+
  10276. + *[0-9a-f]*: 19 3c ld\.ub r12,r12\+\+
  10277. + *[0-9a-f]*: 15 3b ld\.ub r11,r10\+\+
  10278. +
  10279. +[0-9a-f]* <ld_w2>:
  10280. + *[0-9a-f]*: 1f 4f ld\.w pc,--pc
  10281. + *[0-9a-f]*: 19 4c ld\.w r12,--r12
  10282. + *[0-9a-f]*: 0b 45 ld\.w r5,--r5
  10283. + *[0-9a-f]*: 09 44 ld\.w r4,--r4
  10284. + *[0-9a-f]*: 1d 4e ld\.w lr,--lr
  10285. + *[0-9a-f]*: 1d 4a ld\.w r10,--lr
  10286. + *[0-9a-f]*: 13 4c ld\.w r12,--r9
  10287. + *[0-9a-f]*: 0b 46 ld\.w r6,--r5
  10288. +
  10289. +[0-9a-f]* <ld_sh2>:
  10290. + *[0-9a-f]*: 1f 5f ld\.sh pc,--pc
  10291. + *[0-9a-f]*: 19 5c ld\.sh r12,--r12
  10292. + *[0-9a-f]*: 0b 55 ld\.sh r5,--r5
  10293. + *[0-9a-f]*: 09 54 ld\.sh r4,--r4
  10294. + *[0-9a-f]*: 1d 5e ld\.sh lr,--lr
  10295. + *[0-9a-f]*: 15 5f ld\.sh pc,--r10
  10296. + *[0-9a-f]*: 07 56 ld\.sh r6,--r3
  10297. + *[0-9a-f]*: 0d 54 ld\.sh r4,--r6
  10298. +
  10299. +[0-9a-f]* <ld_uh2>:
  10300. + *[0-9a-f]*: 1f 6f ld\.uh pc,--pc
  10301. + *[0-9a-f]*: 19 6c ld\.uh r12,--r12
  10302. + *[0-9a-f]*: 0b 65 ld\.uh r5,--r5
  10303. + *[0-9a-f]*: 09 64 ld\.uh r4,--r4
  10304. + *[0-9a-f]*: 1d 6e ld\.uh lr,--lr
  10305. + *[0-9a-f]*: 05 63 ld\.uh r3,--r2
  10306. + *[0-9a-f]*: 01 61 ld\.uh r1,--r0
  10307. + *[0-9a-f]*: 13 62 ld\.uh r2,--r9
  10308. +
  10309. +[0-9a-f]* <ld_ub2>:
  10310. + *[0-9a-f]*: 1f 7f ld\.ub pc,--pc
  10311. + *[0-9a-f]*: 19 7c ld\.ub r12,--r12
  10312. + *[0-9a-f]*: 0b 75 ld\.ub r5,--r5
  10313. + *[0-9a-f]*: 09 74 ld\.ub r4,--r4
  10314. + *[0-9a-f]*: 1d 7e ld\.ub lr,--lr
  10315. + *[0-9a-f]*: 03 71 ld\.ub r1,--r1
  10316. + *[0-9a-f]*: 0d 70 ld\.ub r0,--r6
  10317. + *[0-9a-f]*: 0f 72 ld\.ub r2,--r7
  10318. +
  10319. +[0-9a-f]* <ld_ub3>:
  10320. + *[0-9a-f]*: 1f 8f ld\.ub pc,pc\[0x0\]
  10321. + *[0-9a-f]*: 19 fc ld\.ub r12,r12\[0x7\]
  10322. + *[0-9a-f]*: 0b c5 ld\.ub r5,r5\[0x4\]
  10323. + *[0-9a-f]*: 09 b4 ld\.ub r4,r4\[0x3\]
  10324. + *[0-9a-f]*: 1d 9e ld\.ub lr,lr\[0x1\]
  10325. + *[0-9a-f]*: 13 e6 ld\.ub r6,r9\[0x6\]
  10326. + *[0-9a-f]*: 1d c2 ld\.ub r2,lr\[0x4\]
  10327. + *[0-9a-f]*: 11 81 ld\.ub r1,r8\[0x0\]
  10328. +
  10329. +[0-9a-f]* <sub3_sp>:
  10330. + *[0-9a-f]*: 20 0d sub sp,0
  10331. + *[0-9a-f]*: 2f fd sub sp,-4
  10332. + *[0-9a-f]*: 28 0d sub sp,-512
  10333. + *[0-9a-f]*: 27 fd sub sp,508
  10334. + *[0-9a-f]*: 20 1d sub sp,4
  10335. + *[0-9a-f]*: 20 bd sub sp,44
  10336. + *[0-9a-f]*: 20 2d sub sp,8
  10337. + *[0-9a-f]*: 25 7d sub sp,348
  10338. +
  10339. +[0-9a-f]* <sub3>:
  10340. + *[0-9a-f]*: 20 0f sub pc,0
  10341. + *[0-9a-f]*: 2f fc sub r12,-1
  10342. + *[0-9a-f]*: 28 05 sub r5,-128
  10343. + *[0-9a-f]*: 27 f4 sub r4,127
  10344. + *[0-9a-f]*: 20 1e sub lr,1
  10345. + *[0-9a-f]*: 2d 76 sub r6,-41
  10346. + *[0-9a-f]*: 22 54 sub r4,37
  10347. + *[0-9a-f]*: 23 8c sub r12,56
  10348. +
  10349. +[0-9a-f]* <mov1>:
  10350. + *[0-9a-f]*: 30 0f mov pc,0
  10351. + *[0-9a-f]*: 3f fc mov r12,-1
  10352. + *[0-9a-f]*: 38 05 mov r5,-128
  10353. + *[0-9a-f]*: 37 f4 mov r4,127
  10354. + *[0-9a-f]*: 30 1e mov lr,1
  10355. + *[0-9a-f]*: 30 ef mov pc,14
  10356. + *[0-9a-f]*: 39 c6 mov r6,-100
  10357. + *[0-9a-f]*: 38 6e mov lr,-122
  10358. +
  10359. +[0-9a-f]* <lddsp>:
  10360. + *[0-9a-f]*: 40 0f lddsp pc,sp\[0x0\]
  10361. + *[0-9a-f]*: 47 fc lddsp r12,sp\[0x1fc\]
  10362. + *[0-9a-f]*: 44 05 lddsp r5,sp\[0x100\]
  10363. + *[0-9a-f]*: 43 f4 lddsp r4,sp\[0xfc\]
  10364. + *[0-9a-f]*: 40 1e lddsp lr,sp\[0x4\]
  10365. + *[0-9a-f]*: 44 0e lddsp lr,sp\[0x100\]
  10366. + *[0-9a-f]*: 40 5c lddsp r12,sp\[0x14\]
  10367. + *[0-9a-f]*: 47 69 lddsp r9,sp\[0x1d8\]
  10368. +
  10369. +[0-9a-f]* <lddpc>:
  10370. + *[0-9a-f]*: 48 0f lddpc pc,[0-9a-f]* <.*>
  10371. + *[0-9a-f]*: 4f f0 lddpc r0,[0-9a-f]* <.*>
  10372. + *[0-9a-f]*: 4c 08 lddpc r8,[0-9a-f]* <.*>
  10373. + *[0-9a-f]*: 4b f7 lddpc r7,[0-9a-f]* <.*>
  10374. + *[0-9a-f]*: 48 1e lddpc lr,[0-9a-f]* <.*>
  10375. + *[0-9a-f]*: 4f 6d lddpc sp,[0-9a-f]* <.*>
  10376. + *[0-9a-f]*: 49 e6 lddpc r6,[0-9a-f]* <.*>
  10377. + *[0-9a-f]*: 48 7b lddpc r11,[0-9a-f]* <.*>
  10378. +
  10379. +[0-9a-f]* <stdsp>:
  10380. + *[0-9a-f]*: 50 0f stdsp sp\[0x0\],pc
  10381. + *[0-9a-f]*: 57 fc stdsp sp\[0x1fc\],r12
  10382. + *[0-9a-f]*: 54 05 stdsp sp\[0x100\],r5
  10383. + *[0-9a-f]*: 53 f4 stdsp sp\[0xfc\],r4
  10384. + *[0-9a-f]*: 50 1e stdsp sp\[0x4\],lr
  10385. + *[0-9a-f]*: 54 cf stdsp sp\[0x130\],pc
  10386. + *[0-9a-f]*: 54 00 stdsp sp\[0x100\],r0
  10387. + *[0-9a-f]*: 55 45 stdsp sp\[0x150\],r5
  10388. +
  10389. +[0-9a-f]* <cp2>:
  10390. + *[0-9a-f]*: 58 0f cp.w pc,0
  10391. + *[0-9a-f]*: 5b fc cp.w r12,-1
  10392. + *[0-9a-f]*: 5a 05 cp.w r5,-32
  10393. + *[0-9a-f]*: 59 f4 cp.w r4,31
  10394. + *[0-9a-f]*: 58 1e cp.w lr,1
  10395. + *[0-9a-f]*: 58 38 cp.w r8,3
  10396. + *[0-9a-f]*: 59 0e cp.w lr,16
  10397. + *[0-9a-f]*: 5a 67 cp.w r7,-26
  10398. +
  10399. +[0-9a-f]* <acr>:
  10400. + *[0-9a-f]*: 5c 0f acr pc
  10401. + *[0-9a-f]*: 5c 0c acr r12
  10402. + *[0-9a-f]*: 5c 05 acr r5
  10403. + *[0-9a-f]*: 5c 04 acr r4
  10404. + *[0-9a-f]*: 5c 0e acr lr
  10405. + *[0-9a-f]*: 5c 02 acr r2
  10406. + *[0-9a-f]*: 5c 0c acr r12
  10407. + *[0-9a-f]*: 5c 0f acr pc
  10408. +
  10409. +[0-9a-f]* <scr>:
  10410. + *[0-9a-f]*: 5c 1f scr pc
  10411. + *[0-9a-f]*: 5c 1c scr r12
  10412. + *[0-9a-f]*: 5c 15 scr r5
  10413. + *[0-9a-f]*: 5c 14 scr r4
  10414. + *[0-9a-f]*: 5c 1e scr lr
  10415. + *[0-9a-f]*: 5c 1f scr pc
  10416. + *[0-9a-f]*: 5c 16 scr r6
  10417. + *[0-9a-f]*: 5c 11 scr r1
  10418. +
  10419. +[0-9a-f]* <cpc0>:
  10420. + *[0-9a-f]*: 5c 2f cpc pc
  10421. + *[0-9a-f]*: 5c 2c cpc r12
  10422. + *[0-9a-f]*: 5c 25 cpc r5
  10423. + *[0-9a-f]*: 5c 24 cpc r4
  10424. + *[0-9a-f]*: 5c 2e cpc lr
  10425. + *[0-9a-f]*: 5c 2f cpc pc
  10426. + *[0-9a-f]*: 5c 24 cpc r4
  10427. + *[0-9a-f]*: 5c 29 cpc r9
  10428. +
  10429. +[0-9a-f]* <neg>:
  10430. + *[0-9a-f]*: 5c 3f neg pc
  10431. + *[0-9a-f]*: 5c 3c neg r12
  10432. + *[0-9a-f]*: 5c 35 neg r5
  10433. + *[0-9a-f]*: 5c 34 neg r4
  10434. + *[0-9a-f]*: 5c 3e neg lr
  10435. + *[0-9a-f]*: 5c 37 neg r7
  10436. + *[0-9a-f]*: 5c 31 neg r1
  10437. + *[0-9a-f]*: 5c 39 neg r9
  10438. +
  10439. +[0-9a-f]* <abs>:
  10440. + *[0-9a-f]*: 5c 4f abs pc
  10441. + *[0-9a-f]*: 5c 4c abs r12
  10442. + *[0-9a-f]*: 5c 45 abs r5
  10443. + *[0-9a-f]*: 5c 44 abs r4
  10444. + *[0-9a-f]*: 5c 4e abs lr
  10445. + *[0-9a-f]*: 5c 46 abs r6
  10446. + *[0-9a-f]*: 5c 46 abs r6
  10447. + *[0-9a-f]*: 5c 44 abs r4
  10448. +
  10449. +[0-9a-f]* <castu_b>:
  10450. + *[0-9a-f]*: 5c 5f castu\.b pc
  10451. + *[0-9a-f]*: 5c 5c castu\.b r12
  10452. + *[0-9a-f]*: 5c 55 castu\.b r5
  10453. + *[0-9a-f]*: 5c 54 castu\.b r4
  10454. + *[0-9a-f]*: 5c 5e castu\.b lr
  10455. + *[0-9a-f]*: 5c 57 castu\.b r7
  10456. + *[0-9a-f]*: 5c 5d castu\.b sp
  10457. + *[0-9a-f]*: 5c 59 castu\.b r9
  10458. +
  10459. +[0-9a-f]* <casts_b>:
  10460. + *[0-9a-f]*: 5c 6f casts\.b pc
  10461. + *[0-9a-f]*: 5c 6c casts\.b r12
  10462. + *[0-9a-f]*: 5c 65 casts\.b r5
  10463. + *[0-9a-f]*: 5c 64 casts\.b r4
  10464. + *[0-9a-f]*: 5c 6e casts\.b lr
  10465. + *[0-9a-f]*: 5c 6b casts\.b r11
  10466. + *[0-9a-f]*: 5c 61 casts\.b r1
  10467. + *[0-9a-f]*: 5c 6a casts\.b r10
  10468. +
  10469. +[0-9a-f]* <castu_h>:
  10470. + *[0-9a-f]*: 5c 7f castu\.h pc
  10471. + *[0-9a-f]*: 5c 7c castu\.h r12
  10472. + *[0-9a-f]*: 5c 75 castu\.h r5
  10473. + *[0-9a-f]*: 5c 74 castu\.h r4
  10474. + *[0-9a-f]*: 5c 7e castu\.h lr
  10475. + *[0-9a-f]*: 5c 7a castu\.h r10
  10476. + *[0-9a-f]*: 5c 7b castu\.h r11
  10477. + *[0-9a-f]*: 5c 71 castu\.h r1
  10478. +
  10479. +[0-9a-f]* <casts_h>:
  10480. + *[0-9a-f]*: 5c 8f casts\.h pc
  10481. + *[0-9a-f]*: 5c 8c casts\.h r12
  10482. + *[0-9a-f]*: 5c 85 casts\.h r5
  10483. + *[0-9a-f]*: 5c 84 casts\.h r4
  10484. + *[0-9a-f]*: 5c 8e casts\.h lr
  10485. + *[0-9a-f]*: 5c 80 casts\.h r0
  10486. + *[0-9a-f]*: 5c 85 casts\.h r5
  10487. + *[0-9a-f]*: 5c 89 casts\.h r9
  10488. +
  10489. +[0-9a-f]* <brev>:
  10490. + *[0-9a-f]*: 5c 9f brev pc
  10491. + *[0-9a-f]*: 5c 9c brev r12
  10492. + *[0-9a-f]*: 5c 95 brev r5
  10493. + *[0-9a-f]*: 5c 94 brev r4
  10494. + *[0-9a-f]*: 5c 9e brev lr
  10495. + *[0-9a-f]*: 5c 95 brev r5
  10496. + *[0-9a-f]*: 5c 9a brev r10
  10497. + *[0-9a-f]*: 5c 98 brev r8
  10498. +
  10499. +[0-9a-f]* <swap_h>:
  10500. + *[0-9a-f]*: 5c af swap\.h pc
  10501. + *[0-9a-f]*: 5c ac swap\.h r12
  10502. + *[0-9a-f]*: 5c a5 swap\.h r5
  10503. + *[0-9a-f]*: 5c a4 swap\.h r4
  10504. + *[0-9a-f]*: 5c ae swap\.h lr
  10505. + *[0-9a-f]*: 5c a7 swap\.h r7
  10506. + *[0-9a-f]*: 5c a0 swap\.h r0
  10507. + *[0-9a-f]*: 5c a8 swap\.h r8
  10508. +
  10509. +[0-9a-f]* <swap_b>:
  10510. + *[0-9a-f]*: 5c bf swap\.b pc
  10511. + *[0-9a-f]*: 5c bc swap\.b r12
  10512. + *[0-9a-f]*: 5c b5 swap\.b r5
  10513. + *[0-9a-f]*: 5c b4 swap\.b r4
  10514. + *[0-9a-f]*: 5c be swap\.b lr
  10515. + *[0-9a-f]*: 5c ba swap\.b r10
  10516. + *[0-9a-f]*: 5c bc swap\.b r12
  10517. + *[0-9a-f]*: 5c b1 swap\.b r1
  10518. +
  10519. +[0-9a-f]* <swap_bh>:
  10520. + *[0-9a-f]*: 5c cf swap\.bh pc
  10521. + *[0-9a-f]*: 5c cc swap\.bh r12
  10522. + *[0-9a-f]*: 5c c5 swap\.bh r5
  10523. + *[0-9a-f]*: 5c c4 swap\.bh r4
  10524. + *[0-9a-f]*: 5c ce swap\.bh lr
  10525. + *[0-9a-f]*: 5c c9 swap\.bh r9
  10526. + *[0-9a-f]*: 5c c4 swap\.bh r4
  10527. + *[0-9a-f]*: 5c c1 swap\.bh r1
  10528. +
  10529. +[0-9a-f]* <One_s_compliment>:
  10530. + *[0-9a-f]*: 5c df com pc
  10531. + *[0-9a-f]*: 5c dc com r12
  10532. + *[0-9a-f]*: 5c d5 com r5
  10533. + *[0-9a-f]*: 5c d4 com r4
  10534. + *[0-9a-f]*: 5c de com lr
  10535. + *[0-9a-f]*: 5c d2 com r2
  10536. + *[0-9a-f]*: 5c d2 com r2
  10537. + *[0-9a-f]*: 5c d7 com r7
  10538. +
  10539. +[0-9a-f]* <tnbz>:
  10540. + *[0-9a-f]*: 5c ef tnbz pc
  10541. + *[0-9a-f]*: 5c ec tnbz r12
  10542. + *[0-9a-f]*: 5c e5 tnbz r5
  10543. + *[0-9a-f]*: 5c e4 tnbz r4
  10544. + *[0-9a-f]*: 5c ee tnbz lr
  10545. + *[0-9a-f]*: 5c e8 tnbz r8
  10546. + *[0-9a-f]*: 5c ec tnbz r12
  10547. + *[0-9a-f]*: 5c ef tnbz pc
  10548. +
  10549. +[0-9a-f]* <rol>:
  10550. + *[0-9a-f]*: 5c ff rol pc
  10551. + *[0-9a-f]*: 5c fc rol r12
  10552. + *[0-9a-f]*: 5c f5 rol r5
  10553. + *[0-9a-f]*: 5c f4 rol r4
  10554. + *[0-9a-f]*: 5c fe rol lr
  10555. + *[0-9a-f]*: 5c fa rol r10
  10556. + *[0-9a-f]*: 5c f9 rol r9
  10557. + *[0-9a-f]*: 5c f5 rol r5
  10558. +
  10559. +[0-9a-f]* <ror>:
  10560. + *[0-9a-f]*: 5d 0f ror pc
  10561. + *[0-9a-f]*: 5d 0c ror r12
  10562. + *[0-9a-f]*: 5d 05 ror r5
  10563. + *[0-9a-f]*: 5d 04 ror r4
  10564. + *[0-9a-f]*: 5d 0e ror lr
  10565. + *[0-9a-f]*: 5d 08 ror r8
  10566. + *[0-9a-f]*: 5d 04 ror r4
  10567. + *[0-9a-f]*: 5d 07 ror r7
  10568. +
  10569. +[0-9a-f]* <icall>:
  10570. + *[0-9a-f]*: 5d 1f icall pc
  10571. + *[0-9a-f]*: 5d 1c icall r12
  10572. + *[0-9a-f]*: 5d 15 icall r5
  10573. + *[0-9a-f]*: 5d 14 icall r4
  10574. + *[0-9a-f]*: 5d 1e icall lr
  10575. + *[0-9a-f]*: 5d 13 icall r3
  10576. + *[0-9a-f]*: 5d 11 icall r1
  10577. + *[0-9a-f]*: 5d 13 icall r3
  10578. +
  10579. +[0-9a-f]* <mustr>:
  10580. + *[0-9a-f]*: 5d 2f mustr pc
  10581. + *[0-9a-f]*: 5d 2c mustr r12
  10582. + *[0-9a-f]*: 5d 25 mustr r5
  10583. + *[0-9a-f]*: 5d 24 mustr r4
  10584. + *[0-9a-f]*: 5d 2e mustr lr
  10585. + *[0-9a-f]*: 5d 21 mustr r1
  10586. + *[0-9a-f]*: 5d 24 mustr r4
  10587. + *[0-9a-f]*: 5d 2c mustr r12
  10588. +
  10589. +[0-9a-f]* <musfr>:
  10590. + *[0-9a-f]*: 5d 3f musfr pc
  10591. + *[0-9a-f]*: 5d 3c musfr r12
  10592. + *[0-9a-f]*: 5d 35 musfr r5
  10593. + *[0-9a-f]*: 5d 34 musfr r4
  10594. + *[0-9a-f]*: 5d 3e musfr lr
  10595. + *[0-9a-f]*: 5d 3b musfr r11
  10596. + *[0-9a-f]*: 5d 3c musfr r12
  10597. + *[0-9a-f]*: 5d 32 musfr r2
  10598. +
  10599. +[0-9a-f]* <ret_cond>:
  10600. + *[0-9a-f]*: 5e 0f reteq 1
  10601. + *[0-9a-f]*: 5e fc retal r12
  10602. + *[0-9a-f]*: 5e 85 retls r5
  10603. + *[0-9a-f]*: 5e 74 retpl r4
  10604. + *[0-9a-f]*: 5e 1e retne -1
  10605. + *[0-9a-f]*: 5e 90 retgt r0
  10606. + *[0-9a-f]*: 5e 9c retgt r12
  10607. + *[0-9a-f]*: 5e 4a retge r10
  10608. +
  10609. +[0-9a-f]* <sr_cond>:
  10610. + *[0-9a-f]*: 5f 0f sreq pc
  10611. + *[0-9a-f]*: 5f fc sral r12
  10612. + *[0-9a-f]*: 5f 85 srls r5
  10613. + *[0-9a-f]*: 5f 74 srpl r4
  10614. + *[0-9a-f]*: 5f 1e srne lr
  10615. + *[0-9a-f]*: 5f 50 srlt r0
  10616. + *[0-9a-f]*: 5f fd sral sp
  10617. + *[0-9a-f]*: 5f 49 srge r9
  10618. +
  10619. +[0-9a-f]* <ld_w3>:
  10620. + *[0-9a-f]*: 7e 0f ld\.w pc,pc\[0x0\]
  10621. + *[0-9a-f]*: 79 fc ld\.w r12,r12\[0x7c\]
  10622. + *[0-9a-f]*: 6b 05 ld\.w r5,r5\[0x40\]
  10623. + *[0-9a-f]*: 68 f4 ld\.w r4,r4\[0x3c\]
  10624. + *[0-9a-f]*: 7c 1e ld\.w lr,lr\[0x4\]
  10625. + *[0-9a-f]*: 64 dd ld\.w sp,r2\[0x34\]
  10626. + *[0-9a-f]*: 62 29 ld\.w r9,r1\[0x8\]
  10627. + *[0-9a-f]*: 7a f5 ld\.w r5,sp\[0x3c\]
  10628. +
  10629. +[0-9a-f]* <ld_sh3>:
  10630. + *[0-9a-f]*: 9e 0f ld\.sh pc,pc\[0x0\]
  10631. + *[0-9a-f]*: 98 7c ld\.sh r12,r12\[0xe\]
  10632. + *[0-9a-f]*: 8a 45 ld\.sh r5,r5\[0x8\]
  10633. + *[0-9a-f]*: 88 34 ld\.sh r4,r4\[0x6\]
  10634. + *[0-9a-f]*: 9c 1e ld\.sh lr,lr\[0x2\]
  10635. + *[0-9a-f]*: 84 44 ld\.sh r4,r2\[0x8\]
  10636. + *[0-9a-f]*: 9c 5d ld\.sh sp,lr\[0xa\]
  10637. + *[0-9a-f]*: 96 12 ld\.sh r2,r11\[0x2\]
  10638. +
  10639. +[0-9a-f]* <ld_uh3>:
  10640. + *[0-9a-f]*: 9e 8f ld\.uh pc,pc\[0x0\]
  10641. + *[0-9a-f]*: 98 fc ld\.uh r12,r12\[0xe\]
  10642. + *[0-9a-f]*: 8a c5 ld\.uh r5,r5\[0x8\]
  10643. + *[0-9a-f]*: 88 b4 ld\.uh r4,r4\[0x6\]
  10644. + *[0-9a-f]*: 9c 9e ld\.uh lr,lr\[0x2\]
  10645. + *[0-9a-f]*: 80 da ld\.uh r10,r0\[0xa\]
  10646. + *[0-9a-f]*: 96 c8 ld\.uh r8,r11\[0x8\]
  10647. + *[0-9a-f]*: 84 ea ld\.uh r10,r2\[0xc\]
  10648. +
  10649. +[0-9a-f]* <st_w3>:
  10650. + *[0-9a-f]*: 9f 0f st\.w pc\[0x0\],pc
  10651. + *[0-9a-f]*: 99 fc st\.w r12\[0x3c\],r12
  10652. + *[0-9a-f]*: 8b 85 st\.w r5\[0x20\],r5
  10653. + *[0-9a-f]*: 89 74 st\.w r4\[0x1c\],r4
  10654. + *[0-9a-f]*: 9d 1e st\.w lr\[0x4\],lr
  10655. + *[0-9a-f]*: 8f bb st\.w r7\[0x2c\],r11
  10656. + *[0-9a-f]*: 85 66 st\.w r2\[0x18\],r6
  10657. + *[0-9a-f]*: 89 39 st\.w r4\[0xc\],r9
  10658. +
  10659. +[0-9a-f]* <st_h3>:
  10660. + *[0-9a-f]*: be 0f st\.h pc\[0x0\],pc
  10661. + *[0-9a-f]*: b8 7c st\.h r12\[0xe\],r12
  10662. + *[0-9a-f]*: aa 45 st\.h r5\[0x8\],r5
  10663. + *[0-9a-f]*: a8 34 st\.h r4\[0x6\],r4
  10664. + *[0-9a-f]*: bc 1e st\.h lr\[0x2\],lr
  10665. + *[0-9a-f]*: bc 5c st\.h lr\[0xa\],r12
  10666. + *[0-9a-f]*: ac 20 st\.h r6\[0x4\],r0
  10667. + *[0-9a-f]*: aa 6d st\.h r5\[0xc\],sp
  10668. +
  10669. +[0-9a-f]* <st_b3>:
  10670. + *[0-9a-f]*: be 8f st\.b pc\[0x0\],pc
  10671. + *[0-9a-f]*: b8 fc st\.b r12\[0x7\],r12
  10672. + *[0-9a-f]*: aa c5 st\.b r5\[0x4\],r5
  10673. + *[0-9a-f]*: a8 b4 st\.b r4\[0x3\],r4
  10674. + *[0-9a-f]*: bc 9e st\.b lr\[0x1\],lr
  10675. + *[0-9a-f]*: b8 e9 st\.b r12\[0x6\],r9
  10676. + *[0-9a-f]*: a4 be st\.b r2\[0x3\],lr
  10677. + *[0-9a-f]*: a2 bb st\.b r1\[0x3\],r11
  10678. +
  10679. +[0-9a-f]* <ldd>:
  10680. + *[0-9a-f]*: bf 00 ld\.d r0,pc
  10681. + *[0-9a-f]*: b9 0e ld\.d lr,r12
  10682. + *[0-9a-f]*: ab 08 ld\.d r8,r5
  10683. + *[0-9a-f]*: a9 06 ld\.d r6,r4
  10684. + *[0-9a-f]*: bd 02 ld\.d r2,lr
  10685. + *[0-9a-f]*: af 0e ld\.d lr,r7
  10686. + *[0-9a-f]*: a9 04 ld\.d r4,r4
  10687. + *[0-9a-f]*: bf 0e ld\.d lr,pc
  10688. +
  10689. +[0-9a-f]* <ldd_postinc>:
  10690. + *[0-9a-f]*: bf 01 ld\.d r0,pc\+\+
  10691. + *[0-9a-f]*: b9 0f ld\.d lr,r12\+\+
  10692. + *[0-9a-f]*: ab 09 ld\.d r8,r5\+\+
  10693. + *[0-9a-f]*: a9 07 ld\.d r6,r4\+\+
  10694. + *[0-9a-f]*: bd 03 ld\.d r2,lr\+\+
  10695. + *[0-9a-f]*: ab 0f ld\.d lr,r5\+\+
  10696. + *[0-9a-f]*: b7 0d ld\.d r12,r11\+\+
  10697. + *[0-9a-f]*: b9 03 ld\.d r2,r12\+\+
  10698. +
  10699. +[0-9a-f]* <ldd_predec>:
  10700. + *[0-9a-f]*: bf 10 ld\.d r0,--pc
  10701. + *[0-9a-f]*: b9 1e ld\.d lr,--r12
  10702. + *[0-9a-f]*: ab 18 ld\.d r8,--r5
  10703. + *[0-9a-f]*: a9 16 ld\.d r6,--r4
  10704. + *[0-9a-f]*: bd 12 ld\.d r2,--lr
  10705. + *[0-9a-f]*: a1 18 ld\.d r8,--r0
  10706. + *[0-9a-f]*: bf 1a ld\.d r10,--pc
  10707. + *[0-9a-f]*: a9 12 ld\.d r2,--r4
  10708. +
  10709. +[0-9a-f]* <std>:
  10710. + *[0-9a-f]*: bf 11 st\.d pc,r0
  10711. + *[0-9a-f]*: b9 1f st\.d r12,lr
  10712. + *[0-9a-f]*: ab 19 st\.d r5,r8
  10713. + *[0-9a-f]*: a9 17 st\.d r4,r6
  10714. + *[0-9a-f]*: bd 13 st\.d lr,r2
  10715. + *[0-9a-f]*: a1 1d st\.d r0,r12
  10716. + *[0-9a-f]*: bb 15 st\.d sp,r4
  10717. + *[0-9a-f]*: b9 1d st\.d r12,r12
  10718. +
  10719. +[0-9a-f]* <std_postinc>:
  10720. + *[0-9a-f]*: bf 20 st\.d pc\+\+,r0
  10721. + *[0-9a-f]*: b9 2e st\.d r12\+\+,lr
  10722. + *[0-9a-f]*: ab 28 st\.d r5\+\+,r8
  10723. + *[0-9a-f]*: a9 26 st\.d r4\+\+,r6
  10724. + *[0-9a-f]*: bd 22 st\.d lr\+\+,r2
  10725. + *[0-9a-f]*: bb 26 st\.d sp\+\+,r6
  10726. + *[0-9a-f]*: b5 26 st\.d r10\+\+,r6
  10727. + *[0-9a-f]*: af 22 st\.d r7\+\+,r2
  10728. +
  10729. +[0-9a-f]* <std_predec>:
  10730. + *[0-9a-f]*: bf 21 st\.d --pc,r0
  10731. + *[0-9a-f]*: b9 2f st\.d --r12,lr
  10732. + *[0-9a-f]*: ab 29 st\.d --r5,r8
  10733. + *[0-9a-f]*: a9 27 st\.d --r4,r6
  10734. + *[0-9a-f]*: bd 23 st\.d --lr,r2
  10735. + *[0-9a-f]*: a7 27 st\.d --r3,r6
  10736. + *[0-9a-f]*: bd 23 st\.d --lr,r2
  10737. + *[0-9a-f]*: a1 25 st\.d --r0,r4
  10738. +
  10739. +[0-9a-f]* <mul>:
  10740. + *[0-9a-f]*: bf 3f mul pc,pc
  10741. + *[0-9a-f]*: b9 3c mul r12,r12
  10742. + *[0-9a-f]*: ab 35 mul r5,r5
  10743. + *[0-9a-f]*: a9 34 mul r4,r4
  10744. + *[0-9a-f]*: bd 3e mul lr,lr
  10745. + *[0-9a-f]*: bd 3a mul r10,lr
  10746. + *[0-9a-f]*: b1 30 mul r0,r8
  10747. + *[0-9a-f]*: ab 38 mul r8,r5
  10748. +
  10749. +[0-9a-f]* <asr_imm5>:
  10750. + *[0-9a-f]*: a1 4f asr pc,0x0
  10751. + *[0-9a-f]*: bf 5c asr r12,0x1f
  10752. + *[0-9a-f]*: b1 45 asr r5,0x10
  10753. + *[0-9a-f]*: af 54 asr r4,0xf
  10754. + *[0-9a-f]*: a1 5e asr lr,0x1
  10755. + *[0-9a-f]*: b7 56 asr r6,0x17
  10756. + *[0-9a-f]*: b3 46 asr r6,0x12
  10757. + *[0-9a-f]*: a9 45 asr r5,0x8
  10758. +
  10759. +[0-9a-f]* <lsl_imm5>:
  10760. + *[0-9a-f]*: a1 6f lsl pc,0x0
  10761. + *[0-9a-f]*: bf 7c lsl r12,0x1f
  10762. + *[0-9a-f]*: b1 65 lsl r5,0x10
  10763. + *[0-9a-f]*: af 74 lsl r4,0xf
  10764. + *[0-9a-f]*: a1 7e lsl lr,0x1
  10765. + *[0-9a-f]*: ad 7c lsl r12,0xd
  10766. + *[0-9a-f]*: b1 66 lsl r6,0x10
  10767. + *[0-9a-f]*: b9 71 lsl r1,0x19
  10768. +
  10769. +[0-9a-f]* <lsr_imm5>:
  10770. + *[0-9a-f]*: a1 8f lsr pc,0x0
  10771. + *[0-9a-f]*: bf 9c lsr r12,0x1f
  10772. + *[0-9a-f]*: b1 85 lsr r5,0x10
  10773. + *[0-9a-f]*: af 94 lsr r4,0xf
  10774. + *[0-9a-f]*: a1 9e lsr lr,0x1
  10775. + *[0-9a-f]*: a1 90 lsr r0,0x1
  10776. + *[0-9a-f]*: ab 88 lsr r8,0xa
  10777. + *[0-9a-f]*: bb 87 lsr r7,0x1a
  10778. +
  10779. +[0-9a-f]* <sbr>:
  10780. + *[0-9a-f]*: a1 af sbr pc,0x0
  10781. + *[0-9a-f]*: bf bc sbr r12,0x1f
  10782. + *[0-9a-f]*: b1 a5 sbr r5,0x10
  10783. + *[0-9a-f]*: af b4 sbr r4,0xf
  10784. + *[0-9a-f]*: a1 be sbr lr,0x1
  10785. + *[0-9a-f]*: bf b8 sbr r8,0x1f
  10786. + *[0-9a-f]*: b7 a6 sbr r6,0x16
  10787. + *[0-9a-f]*: b7 b1 sbr r1,0x17
  10788. +
  10789. +[0-9a-f]* <cbr>:
  10790. + *[0-9a-f]*: a1 cf cbr pc,0x0
  10791. + *[0-9a-f]*: bf dc cbr r12,0x1f
  10792. + *[0-9a-f]*: b1 c5 cbr r5,0x10
  10793. + *[0-9a-f]*: af d4 cbr r4,0xf
  10794. + *[0-9a-f]*: a1 de cbr lr,0x1
  10795. + *[0-9a-f]*: ab cc cbr r12,0xa
  10796. + *[0-9a-f]*: b7 c7 cbr r7,0x16
  10797. + *[0-9a-f]*: a9 d8 cbr r8,0x9
  10798. +
  10799. +[0-9a-f]* <brc1>:
  10800. + *[0-9a-f]*: c0 00 breq [0-9a-f]* <.*>
  10801. + *[0-9a-f]*: cf f7 brpl [0-9a-f]* <.*>
  10802. + *[0-9a-f]*: c8 04 brge [0-9a-f]* <.*>
  10803. + *[0-9a-f]*: c7 f3 brcs [0-9a-f]* <.*>
  10804. + *[0-9a-f]*: c0 11 brne [0-9a-f]* <.*>
  10805. + *[0-9a-f]*: c7 33 brcs [0-9a-f]* <.*>
  10806. + *[0-9a-f]*: cf 70 breq [0-9a-f]* <.*>
  10807. + *[0-9a-f]*: c0 60 breq [0-9a-f]* <.*>
  10808. +
  10809. +[0-9a-f]* <rjmp>:
  10810. + *[0-9a-f]*: c0 08 rjmp [0-9a-f]* <.*>
  10811. + *[0-9a-f]*: cf fb rjmp [0-9a-f]* <.*>
  10812. + *[0-9a-f]*: c0 0a rjmp [0-9a-f]* <.*>
  10813. + *[0-9a-f]*: cf f9 rjmp [0-9a-f]* <.*>
  10814. + *[0-9a-f]*: c0 18 rjmp [0-9a-f]* <.*>
  10815. + *[0-9a-f]*: c1 fa rjmp [0-9a-f]* <.*>
  10816. + *[0-9a-f]*: c0 78 rjmp [0-9a-f]* <.*>
  10817. + *[0-9a-f]*: cf ea rjmp [0-9a-f]* <.*>
  10818. +
  10819. +[0-9a-f]* <rcall1>:
  10820. + *[0-9a-f]*: c0 0c rcall [0-9a-f]* <.*>
  10821. + *[0-9a-f]*: cf ff rcall [0-9a-f]* <.*>
  10822. + *[0-9a-f]*: c0 0e rcall [0-9a-f]* <.*>
  10823. + *[0-9a-f]*: cf fd rcall [0-9a-f]* <.*>
  10824. + *[0-9a-f]*: c0 1c rcall [0-9a-f]* <.*>
  10825. + *[0-9a-f]*: c6 cc rcall [0-9a-f]* <.*>
  10826. + *[0-9a-f]*: cf 7e rcall [0-9a-f]* <.*>
  10827. + *[0-9a-f]*: c1 ae rcall [0-9a-f]* <.*>
  10828. +
  10829. +[0-9a-f]* <acall>:
  10830. + *[0-9a-f]*: d0 00 acall 0x0
  10831. + *[0-9a-f]*: df f0 acall 0x3fc
  10832. + *[0-9a-f]*: d8 00 acall 0x200
  10833. + *[0-9a-f]*: d7 f0 acall 0x1fc
  10834. + *[0-9a-f]*: d0 10 acall 0x4
  10835. + *[0-9a-f]*: d5 90 acall 0x164
  10836. + *[0-9a-f]*: d4 c0 acall 0x130
  10837. + *[0-9a-f]*: d2 b0 acall 0xac
  10838. +
  10839. +[0-9a-f]* <scall>:
  10840. + *[0-9a-f]*: d7 33 scall
  10841. + *[0-9a-f]*: d7 33 scall
  10842. + *[0-9a-f]*: d7 33 scall
  10843. + *[0-9a-f]*: d7 33 scall
  10844. + *[0-9a-f]*: d7 33 scall
  10845. + *[0-9a-f]*: d7 33 scall
  10846. + *[0-9a-f]*: d7 33 scall
  10847. + *[0-9a-f]*: d7 33 scall
  10848. +
  10849. +[0-9a-f]* <popm>:
  10850. + *[0-9a-f]*: d8 02 popm pc
  10851. + *[0-9a-f]*: dd fa popm r0-r11,pc,r12=-1
  10852. + *[0-9a-f]*: d4 02 popm lr
  10853. + *[0-9a-f]*: db fa popm r0-r11,pc,r12=1
  10854. + *[0-9a-f]*: d0 12 popm r0-r3
  10855. + *[0-9a-f]*: d8 e2 popm r4-r10,pc
  10856. + *[0-9a-f]*: d9 1a popm r0-r3,r11,pc,r12=0
  10857. + *[0-9a-f]*: d7 b2 popm r0-r7,r10-r12,lr
  10858. +
  10859. +[0-9a-f]* <pushm>:
  10860. + *[0-9a-f]*: d8 01 pushm pc
  10861. + *[0-9a-f]*: df f1 pushm r0-r12,lr-pc
  10862. + *[0-9a-f]*: d8 01 pushm pc
  10863. + *[0-9a-f]*: d7 f1 pushm r0-r12,lr
  10864. + *[0-9a-f]*: d0 11 pushm r0-r3
  10865. + *[0-9a-f]*: dc c1 pushm r8-r10,lr-pc
  10866. + *[0-9a-f]*: d0 91 pushm r0-r3,r10
  10867. + *[0-9a-f]*: d2 41 pushm r8-r9,r12
  10868. +
  10869. +[0-9a-f]* <popm_n>:
  10870. +.*
  10871. +.*
  10872. +.*
  10873. +.*
  10874. +.*
  10875. +.*
  10876. +.*
  10877. +.*
  10878. +
  10879. +[0-9a-f]* <pushm_n>:
  10880. +.*
  10881. +.*
  10882. +.*
  10883. +.*
  10884. +.*
  10885. +.*
  10886. +.*
  10887. +.*
  10888. +
  10889. +[0-9a-f]* <csrfcz>:
  10890. + *[0-9a-f]*: d0 03 csrfcz 0x0
  10891. + *[0-9a-f]*: d1 f3 csrfcz 0x1f
  10892. + *[0-9a-f]*: d1 03 csrfcz 0x10
  10893. + *[0-9a-f]*: d0 f3 csrfcz 0xf
  10894. + *[0-9a-f]*: d0 13 csrfcz 0x1
  10895. + *[0-9a-f]*: d0 53 csrfcz 0x5
  10896. + *[0-9a-f]*: d0 d3 csrfcz 0xd
  10897. + *[0-9a-f]*: d1 73 csrfcz 0x17
  10898. +
  10899. +[0-9a-f]* <ssrf>:
  10900. + *[0-9a-f]*: d2 03 ssrf 0x0
  10901. + *[0-9a-f]*: d3 f3 ssrf 0x1f
  10902. + *[0-9a-f]*: d3 03 ssrf 0x10
  10903. + *[0-9a-f]*: d2 f3 ssrf 0xf
  10904. + *[0-9a-f]*: d2 13 ssrf 0x1
  10905. + *[0-9a-f]*: d3 d3 ssrf 0x1d
  10906. + *[0-9a-f]*: d2 d3 ssrf 0xd
  10907. + *[0-9a-f]*: d2 d3 ssrf 0xd
  10908. +
  10909. +[0-9a-f]* <csrf>:
  10910. + *[0-9a-f]*: d4 03 csrf 0x0
  10911. + *[0-9a-f]*: d5 f3 csrf 0x1f
  10912. + *[0-9a-f]*: d5 03 csrf 0x10
  10913. + *[0-9a-f]*: d4 f3 csrf 0xf
  10914. + *[0-9a-f]*: d4 13 csrf 0x1
  10915. + *[0-9a-f]*: d4 a3 csrf 0xa
  10916. + *[0-9a-f]*: d4 f3 csrf 0xf
  10917. + *[0-9a-f]*: d4 b3 csrf 0xb
  10918. +
  10919. +[0-9a-f]* <rete>:
  10920. + *[0-9a-f]*: d6 03 rete
  10921. +
  10922. +[0-9a-f]* <rets>:
  10923. + *[0-9a-f]*: d6 13 rets
  10924. +
  10925. +[0-9a-f]* <retd>:
  10926. + *[0-9a-f]*: d6 23 retd
  10927. +
  10928. +[0-9a-f]* <retj>:
  10929. + *[0-9a-f]*: d6 33 retj
  10930. +
  10931. +[0-9a-f]* <tlbr>:
  10932. + *[0-9a-f]*: d6 43 tlbr
  10933. +
  10934. +[0-9a-f]* <tlbs>:
  10935. + *[0-9a-f]*: d6 53 tlbs
  10936. +
  10937. +[0-9a-f]* <tlbw>:
  10938. + *[0-9a-f]*: d6 63 tlbw
  10939. +
  10940. +[0-9a-f]* <breakpoint>:
  10941. + *[0-9a-f]*: d6 73 breakpoint
  10942. +
  10943. +[0-9a-f]* <incjosp>:
  10944. + *[0-9a-f]*: d6 83 incjosp 1
  10945. + *[0-9a-f]*: d6 93 incjosp 2
  10946. + *[0-9a-f]*: d6 a3 incjosp 3
  10947. + *[0-9a-f]*: d6 b3 incjosp 4
  10948. + *[0-9a-f]*: d6 c3 incjosp -4
  10949. + *[0-9a-f]*: d6 d3 incjosp -3
  10950. + *[0-9a-f]*: d6 e3 incjosp -2
  10951. + *[0-9a-f]*: d6 f3 incjosp -1
  10952. +
  10953. +[0-9a-f]* <nop>:
  10954. + *[0-9a-f]*: d7 03 nop
  10955. +
  10956. +[0-9a-f]* <popjc>:
  10957. + *[0-9a-f]*: d7 13 popjc
  10958. +
  10959. +[0-9a-f]* <pushjc>:
  10960. + *[0-9a-f]*: d7 23 pushjc
  10961. +
  10962. +[0-9a-f]* <add2>:
  10963. + *[0-9a-f]*: fe 0f 00 0f add pc,pc,pc
  10964. + *[0-9a-f]*: f8 0c 00 3c add r12,r12,r12<<0x3
  10965. + *[0-9a-f]*: ea 05 00 25 add r5,r5,r5<<0x2
  10966. + *[0-9a-f]*: e8 04 00 14 add r4,r4,r4<<0x1
  10967. + *[0-9a-f]*: fc 0e 00 1e add lr,lr,lr<<0x1
  10968. + *[0-9a-f]*: f8 00 00 10 add r0,r12,r0<<0x1
  10969. + *[0-9a-f]*: f8 04 00 09 add r9,r12,r4
  10970. + *[0-9a-f]*: f8 07 00 2c add r12,r12,r7<<0x2
  10971. +
  10972. +[0-9a-f]* <sub2>:
  10973. + *[0-9a-f]*: fe 0f 01 0f sub pc,pc,pc
  10974. + *[0-9a-f]*: f8 0c 01 3c sub r12,r12,r12<<0x3
  10975. + *[0-9a-f]*: ea 05 01 25 sub r5,r5,r5<<0x2
  10976. + *[0-9a-f]*: e8 04 01 14 sub r4,r4,r4<<0x1
  10977. + *[0-9a-f]*: fc 0e 01 1e sub lr,lr,lr<<0x1
  10978. + *[0-9a-f]*: e6 04 01 0d sub sp,r3,r4
  10979. + *[0-9a-f]*: ee 03 01 03 sub r3,r7,r3
  10980. + *[0-9a-f]*: f4 0d 01 1d sub sp,r10,sp<<0x1
  10981. +
  10982. +[0-9a-f]* <divu>:
  10983. + *[0-9a-f]*: fe 0f 0d 0f divu pc,pc,pc
  10984. + *[0-9a-f]*: f8 0c 0d 0c divu r12,r12,r12
  10985. + *[0-9a-f]*: ea 05 0d 05 divu r5,r5,r5
  10986. + *[0-9a-f]*: e8 04 0d 04 divu r4,r4,r4
  10987. + *[0-9a-f]*: fc 0e 0d 0e divu lr,lr,lr
  10988. + *[0-9a-f]*: e8 0f 0d 0d divu sp,r4,pc
  10989. + *[0-9a-f]*: ea 0d 0d 05 divu r5,r5,sp
  10990. + *[0-9a-f]*: fa 00 0d 0a divu r10,sp,r0
  10991. +
  10992. +[0-9a-f]* <addhh_w>:
  10993. + *[0-9a-f]*: fe 0f 0e 0f addhh\.w pc,pc:b,pc:b
  10994. + *[0-9a-f]*: f8 0c 0e 3c addhh\.w r12,r12:t,r12:t
  10995. + *[0-9a-f]*: ea 05 0e 35 addhh\.w r5,r5:t,r5:t
  10996. + *[0-9a-f]*: e8 04 0e 04 addhh\.w r4,r4:b,r4:b
  10997. + *[0-9a-f]*: fc 0e 0e 3e addhh\.w lr,lr:t,lr:t
  10998. + *[0-9a-f]*: e0 03 0e 00 addhh\.w r0,r0:b,r3:b
  10999. + *[0-9a-f]*: f8 07 0e 2e addhh\.w lr,r12:t,r7:b
  11000. + *[0-9a-f]*: f4 02 0e 23 addhh\.w r3,r10:t,r2:b
  11001. +
  11002. +[0-9a-f]* <subhh_w>:
  11003. + *[0-9a-f]*: fe 0f 0f 0f subhh\.w pc,pc:b,pc:b
  11004. + *[0-9a-f]*: f8 0c 0f 3c subhh\.w r12,r12:t,r12:t
  11005. + *[0-9a-f]*: ea 05 0f 35 subhh\.w r5,r5:t,r5:t
  11006. + *[0-9a-f]*: e8 04 0f 04 subhh\.w r4,r4:b,r4:b
  11007. + *[0-9a-f]*: fc 0e 0f 3e subhh\.w lr,lr:t,lr:t
  11008. + *[0-9a-f]*: e2 07 0f 2a subhh\.w r10,r1:t,r7:b
  11009. + *[0-9a-f]*: f4 0e 0f 3f subhh\.w pc,r10:t,lr:t
  11010. + *[0-9a-f]*: e0 0c 0f 23 subhh\.w r3,r0:t,r12:b
  11011. +
  11012. +[0-9a-f]* <adc>:
  11013. + *[0-9a-f]*: fe 0f 00 4f adc pc,pc,pc
  11014. + *[0-9a-f]*: f8 0c 00 4c adc r12,r12,r12
  11015. + *[0-9a-f]*: ea 05 00 45 adc r5,r5,r5
  11016. + *[0-9a-f]*: e8 04 00 44 adc r4,r4,r4
  11017. + *[0-9a-f]*: fc 0e 00 4e adc lr,lr,lr
  11018. + *[0-9a-f]*: e0 07 00 44 adc r4,r0,r7
  11019. + *[0-9a-f]*: e8 03 00 4d adc sp,r4,r3
  11020. + *[0-9a-f]*: f8 00 00 42 adc r2,r12,r0
  11021. +
  11022. +[0-9a-f]* <sbc>:
  11023. + *[0-9a-f]*: fe 0f 01 4f sbc pc,pc,pc
  11024. + *[0-9a-f]*: f8 0c 01 4c sbc r12,r12,r12
  11025. + *[0-9a-f]*: ea 05 01 45 sbc r5,r5,r5
  11026. + *[0-9a-f]*: e8 04 01 44 sbc r4,r4,r4
  11027. + *[0-9a-f]*: fc 0e 01 4e sbc lr,lr,lr
  11028. + *[0-9a-f]*: ee 09 01 46 sbc r6,r7,r9
  11029. + *[0-9a-f]*: f0 05 01 40 sbc r0,r8,r5
  11030. + *[0-9a-f]*: e0 04 01 41 sbc r1,r0,r4
  11031. +
  11032. +[0-9a-f]* <mul_2>:
  11033. + *[0-9a-f]*: fe 0f 02 4f mul pc,pc,pc
  11034. + *[0-9a-f]*: f8 0c 02 4c mul r12,r12,r12
  11035. + *[0-9a-f]*: ea 05 02 45 mul r5,r5,r5
  11036. + *[0-9a-f]*: e8 04 02 44 mul r4,r4,r4
  11037. + *[0-9a-f]*: fc 0e 02 4e mul lr,lr,lr
  11038. + *[0-9a-f]*: e0 00 02 4f mul pc,r0,r0
  11039. + *[0-9a-f]*: fe 0e 02 48 mul r8,pc,lr
  11040. + *[0-9a-f]*: f8 0f 02 44 mul r4,r12,pc
  11041. +
  11042. +[0-9a-f]* <mac>:
  11043. + *[0-9a-f]*: fe 0f 03 4f mac pc,pc,pc
  11044. + *[0-9a-f]*: f8 0c 03 4c mac r12,r12,r12
  11045. + *[0-9a-f]*: ea 05 03 45 mac r5,r5,r5
  11046. + *[0-9a-f]*: e8 04 03 44 mac r4,r4,r4
  11047. + *[0-9a-f]*: fc 0e 03 4e mac lr,lr,lr
  11048. + *[0-9a-f]*: e8 00 03 4a mac r10,r4,r0
  11049. + *[0-9a-f]*: fc 00 03 47 mac r7,lr,r0
  11050. + *[0-9a-f]*: f2 0c 03 42 mac r2,r9,r12
  11051. +
  11052. +[0-9a-f]* <mulsd>:
  11053. + *[0-9a-f]*: fe 0f 04 4f muls\.d pc,pc,pc
  11054. + *[0-9a-f]*: f8 0c 04 4c muls\.d r12,r12,r12
  11055. + *[0-9a-f]*: ea 05 04 45 muls\.d r5,r5,r5
  11056. + *[0-9a-f]*: e8 04 04 44 muls\.d r4,r4,r4
  11057. + *[0-9a-f]*: fc 0e 04 4e muls\.d lr,lr,lr
  11058. + *[0-9a-f]*: f0 0e 04 42 muls\.d r2,r8,lr
  11059. + *[0-9a-f]*: e0 0b 04 44 muls\.d r4,r0,r11
  11060. + *[0-9a-f]*: fc 06 04 45 muls\.d r5,lr,r6
  11061. +
  11062. +[0-9a-f]* <macsd>:
  11063. + *[0-9a-f]*: fe 0f 05 40 macs\.d r0,pc,pc
  11064. + *[0-9a-f]*: f8 0c 05 4e macs\.d lr,r12,r12
  11065. + *[0-9a-f]*: ea 05 05 48 macs\.d r8,r5,r5
  11066. + *[0-9a-f]*: e8 04 05 46 macs\.d r6,r4,r4
  11067. + *[0-9a-f]*: fc 0e 05 42 macs\.d r2,lr,lr
  11068. + *[0-9a-f]*: e2 09 05 48 macs\.d r8,r1,r9
  11069. + *[0-9a-f]*: f0 08 05 4e macs\.d lr,r8,r8
  11070. + *[0-9a-f]*: e6 0c 05 44 macs\.d r4,r3,r12
  11071. +
  11072. +[0-9a-f]* <mulud>:
  11073. + *[0-9a-f]*: fe 0f 06 40 mulu\.d r0,pc,pc
  11074. + *[0-9a-f]*: f8 0c 06 4e mulu\.d lr,r12,r12
  11075. + *[0-9a-f]*: ea 05 06 48 mulu\.d r8,r5,r5
  11076. + *[0-9a-f]*: e8 04 06 46 mulu\.d r6,r4,r4
  11077. + *[0-9a-f]*: fc 0e 06 42 mulu\.d r2,lr,lr
  11078. + *[0-9a-f]*: ea 00 06 46 mulu\.d r6,r5,r0
  11079. + *[0-9a-f]*: ec 01 06 44 mulu\.d r4,r6,r1
  11080. + *[0-9a-f]*: f0 02 06 48 mulu\.d r8,r8,r2
  11081. +
  11082. +[0-9a-f]* <macud>:
  11083. + *[0-9a-f]*: fe 0f 07 40 macu\.d r0,pc,pc
  11084. + *[0-9a-f]*: f8 0c 07 4e macu\.d lr,r12,r12
  11085. + *[0-9a-f]*: ea 05 07 48 macu\.d r8,r5,r5
  11086. + *[0-9a-f]*: e8 04 07 46 macu\.d r6,r4,r4
  11087. + *[0-9a-f]*: fc 0e 07 42 macu\.d r2,lr,lr
  11088. + *[0-9a-f]*: fa 0b 07 46 macu\.d r6,sp,r11
  11089. + *[0-9a-f]*: e8 08 07 42 macu\.d r2,r4,r8
  11090. + *[0-9a-f]*: f4 09 07 46 macu\.d r6,r10,r9
  11091. +
  11092. +[0-9a-f]* <asr_1>:
  11093. + *[0-9a-f]*: fe 0f 08 4f asr pc,pc,pc
  11094. + *[0-9a-f]*: f8 0c 08 4c asr r12,r12,r12
  11095. + *[0-9a-f]*: ea 05 08 45 asr r5,r5,r5
  11096. + *[0-9a-f]*: e8 04 08 44 asr r4,r4,r4
  11097. + *[0-9a-f]*: fc 0e 08 4e asr lr,lr,lr
  11098. + *[0-9a-f]*: ec 0f 08 4f asr pc,r6,pc
  11099. + *[0-9a-f]*: ec 0c 08 40 asr r0,r6,r12
  11100. + *[0-9a-f]*: fa 00 08 44 asr r4,sp,r0
  11101. +
  11102. +[0-9a-f]* <lsl_1>:
  11103. + *[0-9a-f]*: fe 0f 09 4f lsl pc,pc,pc
  11104. + *[0-9a-f]*: f8 0c 09 4c lsl r12,r12,r12
  11105. + *[0-9a-f]*: ea 05 09 45 lsl r5,r5,r5
  11106. + *[0-9a-f]*: e8 04 09 44 lsl r4,r4,r4
  11107. + *[0-9a-f]*: fc 0e 09 4e lsl lr,lr,lr
  11108. + *[0-9a-f]*: ea 0e 09 4e lsl lr,r5,lr
  11109. + *[0-9a-f]*: fe 03 09 45 lsl r5,pc,r3
  11110. + *[0-9a-f]*: fe 09 09 41 lsl r1,pc,r9
  11111. +
  11112. +[0-9a-f]* <lsr_1>:
  11113. + *[0-9a-f]*: fe 0f 0a 4f lsr pc,pc,pc
  11114. + *[0-9a-f]*: f8 0c 0a 4c lsr r12,r12,r12
  11115. + *[0-9a-f]*: ea 05 0a 45 lsr r5,r5,r5
  11116. + *[0-9a-f]*: e8 04 0a 44 lsr r4,r4,r4
  11117. + *[0-9a-f]*: fc 0e 0a 4e lsr lr,lr,lr
  11118. + *[0-9a-f]*: e8 01 0a 42 lsr r2,r4,r1
  11119. + *[0-9a-f]*: e2 06 0a 45 lsr r5,r1,r6
  11120. + *[0-9a-f]*: ec 07 0a 4d lsr sp,r6,r7
  11121. +
  11122. +[0-9a-f]* <xchg>:
  11123. + *[0-9a-f]*: fe 0f 0b 4f xchg pc,pc,pc
  11124. + *[0-9a-f]*: f8 0c 0b 4c xchg r12,r12,r12
  11125. + *[0-9a-f]*: ea 05 0b 45 xchg r5,r5,r5
  11126. + *[0-9a-f]*: e8 04 0b 44 xchg r4,r4,r4
  11127. + *[0-9a-f]*: fc 0e 0b 4e xchg lr,lr,lr
  11128. + *[0-9a-f]*: e8 0d 0b 4e xchg lr,r4,sp
  11129. + *[0-9a-f]*: ea 0c 0b 41 xchg r1,r5,r12
  11130. + *[0-9a-f]*: f8 00 0b 4e xchg lr,r12,r0
  11131. +
  11132. +[0-9a-f]* <max>:
  11133. + *[0-9a-f]*: fe 0f 0c 4f max pc,pc,pc
  11134. + *[0-9a-f]*: f8 0c 0c 4c max r12,r12,r12
  11135. + *[0-9a-f]*: ea 05 0c 45 max r5,r5,r5
  11136. + *[0-9a-f]*: e8 04 0c 44 max r4,r4,r4
  11137. + *[0-9a-f]*: fc 0e 0c 4e max lr,lr,lr
  11138. + *[0-9a-f]*: e4 0d 0c 4e max lr,r2,sp
  11139. + *[0-9a-f]*: f4 09 0c 44 max r4,r10,r9
  11140. + *[0-9a-f]*: f2 0e 0c 4e max lr,r9,lr
  11141. +
  11142. +[0-9a-f]* <min>:
  11143. + *[0-9a-f]*: fe 0f 0d 4f min pc,pc,pc
  11144. + *[0-9a-f]*: f8 0c 0d 4c min r12,r12,r12
  11145. + *[0-9a-f]*: ea 05 0d 45 min r5,r5,r5
  11146. + *[0-9a-f]*: e8 04 0d 44 min r4,r4,r4
  11147. + *[0-9a-f]*: fc 0e 0d 4e min lr,lr,lr
  11148. + *[0-9a-f]*: ee 08 0d 49 min r9,r7,r8
  11149. + *[0-9a-f]*: ea 05 0d 4d min sp,r5,r5
  11150. + *[0-9a-f]*: e2 04 0d 44 min r4,r1,r4
  11151. +
  11152. +[0-9a-f]* <addabs>:
  11153. + *[0-9a-f]*: fe 0f 0e 4f addabs pc,pc,pc
  11154. + *[0-9a-f]*: f8 0c 0e 4c addabs r12,r12,r12
  11155. + *[0-9a-f]*: ea 05 0e 45 addabs r5,r5,r5
  11156. + *[0-9a-f]*: e8 04 0e 44 addabs r4,r4,r4
  11157. + *[0-9a-f]*: fc 0e 0e 4e addabs lr,lr,lr
  11158. + *[0-9a-f]*: f4 00 0e 47 addabs r7,r10,r0
  11159. + *[0-9a-f]*: f2 07 0e 49 addabs r9,r9,r7
  11160. + *[0-9a-f]*: f0 0c 0e 42 addabs r2,r8,r12
  11161. +
  11162. +[0-9a-f]* <mulnhh_w>:
  11163. + *[0-9a-f]*: fe 0f 01 8f mulnhh\.w pc,pc:b,pc:b
  11164. + *[0-9a-f]*: f8 0c 01 bc mulnhh\.w r12,r12:t,r12:t
  11165. + *[0-9a-f]*: ea 05 01 b5 mulnhh\.w r5,r5:t,r5:t
  11166. + *[0-9a-f]*: e8 04 01 84 mulnhh\.w r4,r4:b,r4:b
  11167. + *[0-9a-f]*: fc 0e 01 be mulnhh\.w lr,lr:t,lr:t
  11168. + *[0-9a-f]*: fa 09 01 ab mulnhh\.w r11,sp:t,r9:b
  11169. + *[0-9a-f]*: e8 0e 01 9d mulnhh\.w sp,r4:b,lr:t
  11170. + *[0-9a-f]*: e4 0b 01 ac mulnhh\.w r12,r2:t,r11:b
  11171. +
  11172. +[0-9a-f]* <mulnwh_d>:
  11173. + *[0-9a-f]*: fe 0f 02 80 mulnwh\.d r0,pc,pc:b
  11174. + *[0-9a-f]*: f8 0c 02 9e mulnwh\.d lr,r12,r12:t
  11175. + *[0-9a-f]*: ea 05 02 98 mulnwh\.d r8,r5,r5:t
  11176. + *[0-9a-f]*: e8 04 02 86 mulnwh\.d r6,r4,r4:b
  11177. + *[0-9a-f]*: fc 0e 02 92 mulnwh\.d r2,lr,lr:t
  11178. + *[0-9a-f]*: e6 02 02 9e mulnwh\.d lr,r3,r2:t
  11179. + *[0-9a-f]*: ea 09 02 84 mulnwh\.d r4,r5,r9:b
  11180. + *[0-9a-f]*: e8 04 02 9c mulnwh\.d r12,r4,r4:t
  11181. +
  11182. +[0-9a-f]* <machh_w>:
  11183. + *[0-9a-f]*: fe 0f 04 8f machh\.w pc,pc:b,pc:b
  11184. + *[0-9a-f]*: f8 0c 04 bc machh\.w r12,r12:t,r12:t
  11185. + *[0-9a-f]*: ea 05 04 b5 machh\.w r5,r5:t,r5:t
  11186. + *[0-9a-f]*: e8 04 04 84 machh\.w r4,r4:b,r4:b
  11187. + *[0-9a-f]*: fc 0e 04 be machh\.w lr,lr:t,lr:t
  11188. + *[0-9a-f]*: ea 01 04 9e machh\.w lr,r5:b,r1:t
  11189. + *[0-9a-f]*: ec 07 04 89 machh\.w r9,r6:b,r7:b
  11190. + *[0-9a-f]*: fc 0c 04 a5 machh\.w r5,lr:t,r12:b
  11191. +
  11192. +[0-9a-f]* <machh_d>:
  11193. + *[0-9a-f]*: fe 0f 05 80 machh\.d r0,pc:b,pc:b
  11194. + *[0-9a-f]*: f8 0c 05 be machh\.d lr,r12:t,r12:t
  11195. + *[0-9a-f]*: ea 05 05 b8 machh\.d r8,r5:t,r5:t
  11196. + *[0-9a-f]*: e8 04 05 86 machh\.d r6,r4:b,r4:b
  11197. + *[0-9a-f]*: fc 0e 05 b2 machh\.d r2,lr:t,lr:t
  11198. + *[0-9a-f]*: e0 08 05 8a machh\.d r10,r0:b,r8:b
  11199. + *[0-9a-f]*: e8 05 05 9e machh\.d lr,r4:b,r5:t
  11200. + *[0-9a-f]*: e0 04 05 98 machh\.d r8,r0:b,r4:t
  11201. +
  11202. +[0-9a-f]* <macsathh_w>:
  11203. + *[0-9a-f]*: fe 0f 06 8f macsathh\.w pc,pc:b,pc:b
  11204. + *[0-9a-f]*: f8 0c 06 bc macsathh\.w r12,r12:t,r12:t
  11205. + *[0-9a-f]*: ea 05 06 b5 macsathh\.w r5,r5:t,r5:t
  11206. + *[0-9a-f]*: e8 04 06 84 macsathh\.w r4,r4:b,r4:b
  11207. + *[0-9a-f]*: fc 0e 06 be macsathh\.w lr,lr:t,lr:t
  11208. + *[0-9a-f]*: ee 0f 06 b7 macsathh\.w r7,r7:t,pc:t
  11209. + *[0-9a-f]*: e4 04 06 a4 macsathh\.w r4,r2:t,r4:b
  11210. + *[0-9a-f]*: f0 03 06 b4 macsathh\.w r4,r8:t,r3:t
  11211. +
  11212. +[0-9a-f]* <mulhh_w>:
  11213. + *[0-9a-f]*: fe 0f 07 8f mulhh\.w pc,pc:b,pc:b
  11214. + *[0-9a-f]*: f8 0c 07 bc mulhh\.w r12,r12:t,r12:t
  11215. + *[0-9a-f]*: ea 05 07 b5 mulhh\.w r5,r5:t,r5:t
  11216. + *[0-9a-f]*: e8 04 07 84 mulhh\.w r4,r4:b,r4:b
  11217. + *[0-9a-f]*: fc 0e 07 be mulhh\.w lr,lr:t,lr:t
  11218. + *[0-9a-f]*: e8 09 07 a7 mulhh\.w r7,r4:t,r9:b
  11219. + *[0-9a-f]*: e6 07 07 bf mulhh\.w pc,r3:t,r7:t
  11220. + *[0-9a-f]*: e8 09 07 9f mulhh\.w pc,r4:b,r9:t
  11221. +
  11222. +[0-9a-f]* <mulsathh_h>:
  11223. + *[0-9a-f]*: fe 0f 08 8f mulsathh\.h pc,pc:b,pc:b
  11224. + *[0-9a-f]*: f8 0c 08 bc mulsathh\.h r12,r12:t,r12:t
  11225. + *[0-9a-f]*: ea 05 08 b5 mulsathh\.h r5,r5:t,r5:t
  11226. + *[0-9a-f]*: e8 04 08 84 mulsathh\.h r4,r4:b,r4:b
  11227. + *[0-9a-f]*: fc 0e 08 be mulsathh\.h lr,lr:t,lr:t
  11228. + *[0-9a-f]*: e2 0d 08 83 mulsathh\.h r3,r1:b,sp:b
  11229. + *[0-9a-f]*: fc 0b 08 ab mulsathh\.h r11,lr:t,r11:b
  11230. + *[0-9a-f]*: f0 0b 08 98 mulsathh\.h r8,r8:b,r11:t
  11231. +
  11232. +[0-9a-f]* <mulsathh_w>:
  11233. + *[0-9a-f]*: fe 0f 09 8f mulsathh\.w pc,pc:b,pc:b
  11234. + *[0-9a-f]*: f8 0c 09 bc mulsathh\.w r12,r12:t,r12:t
  11235. + *[0-9a-f]*: ea 05 09 b5 mulsathh\.w r5,r5:t,r5:t
  11236. + *[0-9a-f]*: e8 04 09 84 mulsathh\.w r4,r4:b,r4:b
  11237. + *[0-9a-f]*: fc 0e 09 be mulsathh\.w lr,lr:t,lr:t
  11238. + *[0-9a-f]*: f6 06 09 ae mulsathh\.w lr,r11:t,r6:b
  11239. + *[0-9a-f]*: ec 07 09 96 mulsathh\.w r6,r6:b,r7:t
  11240. + *[0-9a-f]*: e4 03 09 8a mulsathh\.w r10,r2:b,r3:b
  11241. +
  11242. +[0-9a-f]* <mulsatrndhh_h>:
  11243. + *[0-9a-f]*: fe 0f 0a 8f mulsatrndhh\.h pc,pc:b,pc:b
  11244. + *[0-9a-f]*: f8 0c 0a bc mulsatrndhh\.h r12,r12:t,r12:t
  11245. + *[0-9a-f]*: ea 05 0a b5 mulsatrndhh\.h r5,r5:t,r5:t
  11246. + *[0-9a-f]*: e8 04 0a 84 mulsatrndhh\.h r4,r4:b,r4:b
  11247. + *[0-9a-f]*: fc 0e 0a be mulsatrndhh\.h lr,lr:t,lr:t
  11248. + *[0-9a-f]*: ec 09 0a 8b mulsatrndhh\.h r11,r6:b,r9:b
  11249. + *[0-9a-f]*: e6 08 0a 9b mulsatrndhh\.h r11,r3:b,r8:t
  11250. + *[0-9a-f]*: fa 07 0a b5 mulsatrndhh\.h r5,sp:t,r7:t
  11251. +
  11252. +[0-9a-f]* <mulsatrndwh_w>:
  11253. + *[0-9a-f]*: fe 0f 0b 8f mulsatrndwh\.w pc,pc,pc:b
  11254. + *[0-9a-f]*: f8 0c 0b 9c mulsatrndwh\.w r12,r12,r12:t
  11255. + *[0-9a-f]*: ea 05 0b 95 mulsatrndwh\.w r5,r5,r5:t
  11256. + *[0-9a-f]*: e8 04 0b 84 mulsatrndwh\.w r4,r4,r4:b
  11257. + *[0-9a-f]*: fc 0e 0b 9e mulsatrndwh\.w lr,lr,lr:t
  11258. + *[0-9a-f]*: f8 00 0b 85 mulsatrndwh\.w r5,r12,r0:b
  11259. + *[0-9a-f]*: f4 0f 0b 87 mulsatrndwh\.w r7,r10,pc:b
  11260. + *[0-9a-f]*: f0 05 0b 9a mulsatrndwh\.w r10,r8,r5:t
  11261. +
  11262. +[0-9a-f]* <macwh_d>:
  11263. + *[0-9a-f]*: fe 0f 0c 80 macwh\.d r0,pc,pc:b
  11264. + *[0-9a-f]*: f8 0c 0c 9e macwh\.d lr,r12,r12:t
  11265. + *[0-9a-f]*: ea 05 0c 98 macwh\.d r8,r5,r5:t
  11266. + *[0-9a-f]*: e8 04 0c 86 macwh\.d r6,r4,r4:b
  11267. + *[0-9a-f]*: fc 0e 0c 92 macwh\.d r2,lr,lr:t
  11268. + *[0-9a-f]*: f4 0c 0c 94 macwh\.d r4,r10,r12:t
  11269. + *[0-9a-f]*: ee 0d 0c 84 macwh\.d r4,r7,sp:b
  11270. + *[0-9a-f]*: f2 0b 0c 8e macwh\.d lr,r9,r11:b
  11271. +
  11272. +[0-9a-f]* <mulwh_d>:
  11273. + *[0-9a-f]*: fe 0f 0d 80 mulwh\.d r0,pc,pc:b
  11274. + *[0-9a-f]*: f8 0c 0d 9e mulwh\.d lr,r12,r12:t
  11275. + *[0-9a-f]*: ea 05 0d 98 mulwh\.d r8,r5,r5:t
  11276. + *[0-9a-f]*: e8 04 0d 86 mulwh\.d r6,r4,r4:b
  11277. + *[0-9a-f]*: fc 0e 0d 92 mulwh\.d r2,lr,lr:t
  11278. + *[0-9a-f]*: ea 01 0d 8c mulwh\.d r12,r5,r1:b
  11279. + *[0-9a-f]*: e2 03 0d 90 mulwh\.d r0,r1,r3:t
  11280. + *[0-9a-f]*: f2 02 0d 80 mulwh\.d r0,r9,r2:b
  11281. +
  11282. +[0-9a-f]* <mulsatwh_w>:
  11283. + *[0-9a-f]*: fe 0f 0e 8f mulsatwh\.w pc,pc,pc:b
  11284. + *[0-9a-f]*: f8 0c 0e 9c mulsatwh\.w r12,r12,r12:t
  11285. + *[0-9a-f]*: ea 05 0e 95 mulsatwh\.w r5,r5,r5:t
  11286. + *[0-9a-f]*: e8 04 0e 84 mulsatwh\.w r4,r4,r4:b
  11287. + *[0-9a-f]*: fc 0e 0e 9e mulsatwh\.w lr,lr,lr:t
  11288. + *[0-9a-f]*: fe 0a 0e 9b mulsatwh\.w r11,pc,r10:t
  11289. + *[0-9a-f]*: f8 09 0e 9d mulsatwh\.w sp,r12,r9:t
  11290. + *[0-9a-f]*: e6 02 0e 90 mulsatwh\.w r0,r3,r2:t
  11291. +
  11292. +[0-9a-f]* <ldw7>:
  11293. + *[0-9a-f]*: fe 0f 0f 8f ld\.w pc,pc\[pc:b<<2\]
  11294. + *[0-9a-f]*: f8 0c 0f bc ld\.w r12,r12\[r12:t<<2\]
  11295. + *[0-9a-f]*: ea 05 0f a5 ld\.w r5,r5\[r5:u<<2\]
  11296. + *[0-9a-f]*: e8 04 0f 94 ld\.w r4,r4\[r4:l<<2\]
  11297. + *[0-9a-f]*: fc 0e 0f 9e ld\.w lr,lr\[lr:l<<2\]
  11298. + *[0-9a-f]*: f4 06 0f 99 ld\.w r9,r10\[r6:l<<2\]
  11299. + *[0-9a-f]*: f4 0a 0f 82 ld\.w r2,r10\[r10:b<<2\]
  11300. + *[0-9a-f]*: ea 0f 0f 8b ld\.w r11,r5\[pc:b<<2\]
  11301. +
  11302. +[0-9a-f]* <satadd_w>:
  11303. + *[0-9a-f]*: fe 0f 00 cf satadd\.w pc,pc,pc
  11304. + *[0-9a-f]*: f8 0c 00 cc satadd\.w r12,r12,r12
  11305. + *[0-9a-f]*: ea 05 00 c5 satadd\.w r5,r5,r5
  11306. + *[0-9a-f]*: e8 04 00 c4 satadd\.w r4,r4,r4
  11307. + *[0-9a-f]*: fc 0e 00 ce satadd\.w lr,lr,lr
  11308. + *[0-9a-f]*: f0 0b 00 c4 satadd\.w r4,r8,r11
  11309. + *[0-9a-f]*: f8 06 00 c3 satadd\.w r3,r12,r6
  11310. + *[0-9a-f]*: fc 09 00 c3 satadd\.w r3,lr,r9
  11311. +
  11312. +[0-9a-f]* <satsub_w1>:
  11313. + *[0-9a-f]*: fe 0f 01 cf satsub\.w pc,pc,pc
  11314. + *[0-9a-f]*: f8 0c 01 cc satsub\.w r12,r12,r12
  11315. + *[0-9a-f]*: ea 05 01 c5 satsub\.w r5,r5,r5
  11316. + *[0-9a-f]*: e8 04 01 c4 satsub\.w r4,r4,r4
  11317. + *[0-9a-f]*: fc 0e 01 ce satsub\.w lr,lr,lr
  11318. + *[0-9a-f]*: fa 00 01 c8 satsub\.w r8,sp,r0
  11319. + *[0-9a-f]*: f0 04 01 c9 satsub\.w r9,r8,r4
  11320. + *[0-9a-f]*: fc 02 01 cf satsub\.w pc,lr,r2
  11321. +
  11322. +[0-9a-f]* <satadd_h>:
  11323. + *[0-9a-f]*: fe 0f 02 cf satadd\.h pc,pc,pc
  11324. + *[0-9a-f]*: f8 0c 02 cc satadd\.h r12,r12,r12
  11325. + *[0-9a-f]*: ea 05 02 c5 satadd\.h r5,r5,r5
  11326. + *[0-9a-f]*: e8 04 02 c4 satadd\.h r4,r4,r4
  11327. + *[0-9a-f]*: fc 0e 02 ce satadd\.h lr,lr,lr
  11328. + *[0-9a-f]*: e6 09 02 c7 satadd\.h r7,r3,r9
  11329. + *[0-9a-f]*: e0 02 02 c1 satadd\.h r1,r0,r2
  11330. + *[0-9a-f]*: e8 0e 02 c1 satadd\.h r1,r4,lr
  11331. +
  11332. +[0-9a-f]* <satsub_h>:
  11333. + *[0-9a-f]*: fe 0f 03 cf satsub\.h pc,pc,pc
  11334. + *[0-9a-f]*: f8 0c 03 cc satsub\.h r12,r12,r12
  11335. + *[0-9a-f]*: ea 05 03 c5 satsub\.h r5,r5,r5
  11336. + *[0-9a-f]*: e8 04 03 c4 satsub\.h r4,r4,r4
  11337. + *[0-9a-f]*: fc 0e 03 ce satsub\.h lr,lr,lr
  11338. + *[0-9a-f]*: fc 03 03 ce satsub\.h lr,lr,r3
  11339. + *[0-9a-f]*: ec 05 03 cb satsub\.h r11,r6,r5
  11340. + *[0-9a-f]*: fa 00 03 c3 satsub\.h r3,sp,r0
  11341. +
  11342. +[0-9a-f]* <mul3>:
  11343. + *[0-9a-f]*: fe 0f 10 00 mul pc,pc,0
  11344. + *[0-9a-f]*: f8 0c 10 ff mul r12,r12,-1
  11345. + *[0-9a-f]*: ea 05 10 80 mul r5,r5,-128
  11346. + *[0-9a-f]*: e8 04 10 7f mul r4,r4,127
  11347. + *[0-9a-f]*: fc 0e 10 01 mul lr,lr,1
  11348. + *[0-9a-f]*: e4 0c 10 f9 mul r12,r2,-7
  11349. + *[0-9a-f]*: fe 01 10 5f mul r1,pc,95
  11350. + *[0-9a-f]*: ec 04 10 13 mul r4,r6,19
  11351. +
  11352. +[0-9a-f]* <rsub2>:
  11353. + *[0-9a-f]*: fe 0f 11 00 rsub pc,pc,0
  11354. + *[0-9a-f]*: f8 0c 11 ff rsub r12,r12,-1
  11355. + *[0-9a-f]*: ea 05 11 80 rsub r5,r5,-128
  11356. + *[0-9a-f]*: e8 04 11 7f rsub r4,r4,127
  11357. + *[0-9a-f]*: fc 0e 11 01 rsub lr,lr,1
  11358. + *[0-9a-f]*: fc 09 11 60 rsub r9,lr,96
  11359. + *[0-9a-f]*: e2 0b 11 38 rsub r11,r1,56
  11360. + *[0-9a-f]*: ee 00 11 a9 rsub r0,r7,-87
  11361. +
  11362. +[0-9a-f]* <clz>:
  11363. + *[0-9a-f]*: fe 0f 12 00 clz pc,pc
  11364. + *[0-9a-f]*: f8 0c 12 00 clz r12,r12
  11365. + *[0-9a-f]*: ea 05 12 00 clz r5,r5
  11366. + *[0-9a-f]*: e8 04 12 00 clz r4,r4
  11367. + *[0-9a-f]*: fc 0e 12 00 clz lr,lr
  11368. + *[0-9a-f]*: e6 02 12 00 clz r2,r3
  11369. + *[0-9a-f]*: f6 05 12 00 clz r5,r11
  11370. + *[0-9a-f]*: e6 0f 12 00 clz pc,r3
  11371. +
  11372. +[0-9a-f]* <cpc1>:
  11373. + *[0-9a-f]*: fe 0f 13 00 cpc pc,pc
  11374. + *[0-9a-f]*: f8 0c 13 00 cpc r12,r12
  11375. + *[0-9a-f]*: ea 05 13 00 cpc r5,r5
  11376. + *[0-9a-f]*: e8 04 13 00 cpc r4,r4
  11377. + *[0-9a-f]*: fc 0e 13 00 cpc lr,lr
  11378. + *[0-9a-f]*: e8 0f 13 00 cpc pc,r4
  11379. + *[0-9a-f]*: f2 05 13 00 cpc r5,r9
  11380. + *[0-9a-f]*: ee 06 13 00 cpc r6,r7
  11381. +
  11382. +[0-9a-f]* <asr3>:
  11383. + *[0-9a-f]*: fe 0f 14 00 asr pc,pc,0x0
  11384. + *[0-9a-f]*: f8 0c 14 1f asr r12,r12,0x1f
  11385. + *[0-9a-f]*: ea 05 14 10 asr r5,r5,0x10
  11386. + *[0-9a-f]*: e8 04 14 0f asr r4,r4,0xf
  11387. + *[0-9a-f]*: fc 0e 14 01 asr lr,lr,0x1
  11388. + *[0-9a-f]*: f6 04 14 13 asr r4,r11,0x13
  11389. + *[0-9a-f]*: fe 0d 14 1a asr sp,pc,0x1a
  11390. + *[0-9a-f]*: fa 0b 14 08 asr r11,sp,0x8
  11391. +
  11392. +[0-9a-f]* <lsl3>:
  11393. + *[0-9a-f]*: fe 0f 15 00 lsl pc,pc,0x0
  11394. + *[0-9a-f]*: f8 0c 15 1f lsl r12,r12,0x1f
  11395. + *[0-9a-f]*: ea 05 15 10 lsl r5,r5,0x10
  11396. + *[0-9a-f]*: e8 04 15 0f lsl r4,r4,0xf
  11397. + *[0-9a-f]*: fc 0e 15 01 lsl lr,lr,0x1
  11398. + *[0-9a-f]*: f4 08 15 11 lsl r8,r10,0x11
  11399. + *[0-9a-f]*: fc 02 15 03 lsl r2,lr,0x3
  11400. + *[0-9a-f]*: f6 0e 15 0e lsl lr,r11,0xe
  11401. +
  11402. +[0-9a-f]* <lsr3>:
  11403. + *[0-9a-f]*: fe 0f 16 00 lsr pc,pc,0x0
  11404. + *[0-9a-f]*: f8 0c 16 1f lsr r12,r12,0x1f
  11405. + *[0-9a-f]*: ea 05 16 10 lsr r5,r5,0x10
  11406. + *[0-9a-f]*: e8 04 16 0f lsr r4,r4,0xf
  11407. + *[0-9a-f]*: fc 0e 16 01 lsr lr,lr,0x1
  11408. + *[0-9a-f]*: e6 04 16 1f lsr r4,r3,0x1f
  11409. + *[0-9a-f]*: f2 0f 16 0e lsr pc,r9,0xe
  11410. + *[0-9a-f]*: e0 03 16 06 lsr r3,r0,0x6
  11411. +
  11412. +[0-9a-f]* <movc1>:
  11413. + *[0-9a-f]*: fe 0f 17 00 moveq pc,pc
  11414. + *[0-9a-f]*: f8 0c 17 f0 moval r12,r12
  11415. + *[0-9a-f]*: ea 05 17 80 movls r5,r5
  11416. + *[0-9a-f]*: e8 04 17 70 movpl r4,r4
  11417. + *[0-9a-f]*: fc 0e 17 10 movne lr,lr
  11418. + *[0-9a-f]*: f6 0f 17 10 movne pc,r11
  11419. + *[0-9a-f]*: e4 0a 17 60 movmi r10,r2
  11420. + *[0-9a-f]*: f8 08 17 80 movls r8,r12
  11421. +
  11422. +[0-9a-f]* <padd_h>:
  11423. + *[0-9a-f]*: fe 0f 20 0f padd\.h pc,pc,pc
  11424. + *[0-9a-f]*: f8 0c 20 0c padd\.h r12,r12,r12
  11425. + *[0-9a-f]*: ea 05 20 05 padd\.h r5,r5,r5
  11426. + *[0-9a-f]*: e8 04 20 04 padd\.h r4,r4,r4
  11427. + *[0-9a-f]*: fc 0e 20 0e padd\.h lr,lr,lr
  11428. + *[0-9a-f]*: e4 07 20 08 padd\.h r8,r2,r7
  11429. + *[0-9a-f]*: e0 03 20 00 padd\.h r0,r0,r3
  11430. + *[0-9a-f]*: f6 06 20 0d padd\.h sp,r11,r6
  11431. +
  11432. +[0-9a-f]* <psub_h>:
  11433. + *[0-9a-f]*: fe 0f 20 1f psub\.h pc,pc,pc
  11434. + *[0-9a-f]*: f8 0c 20 1c psub\.h r12,r12,r12
  11435. + *[0-9a-f]*: ea 05 20 15 psub\.h r5,r5,r5
  11436. + *[0-9a-f]*: e8 04 20 14 psub\.h r4,r4,r4
  11437. + *[0-9a-f]*: fc 0e 20 1e psub\.h lr,lr,lr
  11438. + *[0-9a-f]*: ec 08 20 1e psub\.h lr,r6,r8
  11439. + *[0-9a-f]*: e2 0d 20 10 psub\.h r0,r1,sp
  11440. + *[0-9a-f]*: fe 0d 20 1f psub\.h pc,pc,sp
  11441. +
  11442. +[0-9a-f]* <paddx_h>:
  11443. + *[0-9a-f]*: fe 0f 20 2f paddx\.h pc,pc,pc
  11444. + *[0-9a-f]*: f8 0c 20 2c paddx\.h r12,r12,r12
  11445. + *[0-9a-f]*: ea 05 20 25 paddx\.h r5,r5,r5
  11446. + *[0-9a-f]*: e8 04 20 24 paddx\.h r4,r4,r4
  11447. + *[0-9a-f]*: fc 0e 20 2e paddx\.h lr,lr,lr
  11448. + *[0-9a-f]*: fe 01 20 2f paddx\.h pc,pc,r1
  11449. + *[0-9a-f]*: e8 05 20 2a paddx\.h r10,r4,r5
  11450. + *[0-9a-f]*: fe 02 20 25 paddx\.h r5,pc,r2
  11451. +
  11452. +[0-9a-f]* <psubx_h>:
  11453. + *[0-9a-f]*: fe 0f 20 3f psubx\.h pc,pc,pc
  11454. + *[0-9a-f]*: f8 0c 20 3c psubx\.h r12,r12,r12
  11455. + *[0-9a-f]*: ea 05 20 35 psubx\.h r5,r5,r5
  11456. + *[0-9a-f]*: e8 04 20 34 psubx\.h r4,r4,r4
  11457. + *[0-9a-f]*: fc 0e 20 3e psubx\.h lr,lr,lr
  11458. + *[0-9a-f]*: f8 05 20 35 psubx\.h r5,r12,r5
  11459. + *[0-9a-f]*: f0 03 20 33 psubx\.h r3,r8,r3
  11460. + *[0-9a-f]*: e4 03 20 35 psubx\.h r5,r2,r3
  11461. +
  11462. +[0-9a-f]* <padds_sh>:
  11463. + *[0-9a-f]*: fe 0f 20 4f padds\.sh pc,pc,pc
  11464. + *[0-9a-f]*: f8 0c 20 4c padds\.sh r12,r12,r12
  11465. + *[0-9a-f]*: ea 05 20 45 padds\.sh r5,r5,r5
  11466. + *[0-9a-f]*: e8 04 20 44 padds\.sh r4,r4,r4
  11467. + *[0-9a-f]*: fc 0e 20 4e padds\.sh lr,lr,lr
  11468. + *[0-9a-f]*: fc 02 20 49 padds\.sh r9,lr,r2
  11469. + *[0-9a-f]*: f0 01 20 46 padds\.sh r6,r8,r1
  11470. + *[0-9a-f]*: e8 0a 20 46 padds\.sh r6,r4,r10
  11471. +
  11472. +[0-9a-f]* <psubs_sh>:
  11473. + *[0-9a-f]*: fe 0f 20 5f psubs\.sh pc,pc,pc
  11474. + *[0-9a-f]*: f8 0c 20 5c psubs\.sh r12,r12,r12
  11475. + *[0-9a-f]*: ea 05 20 55 psubs\.sh r5,r5,r5
  11476. + *[0-9a-f]*: e8 04 20 54 psubs\.sh r4,r4,r4
  11477. + *[0-9a-f]*: fc 0e 20 5e psubs\.sh lr,lr,lr
  11478. + *[0-9a-f]*: fc 0b 20 56 psubs\.sh r6,lr,r11
  11479. + *[0-9a-f]*: f8 04 20 52 psubs\.sh r2,r12,r4
  11480. + *[0-9a-f]*: f2 00 20 50 psubs\.sh r0,r9,r0
  11481. +
  11482. +[0-9a-f]* <paddxs_sh>:
  11483. + *[0-9a-f]*: fe 0f 20 6f paddxs\.sh pc,pc,pc
  11484. + *[0-9a-f]*: f8 0c 20 6c paddxs\.sh r12,r12,r12
  11485. + *[0-9a-f]*: ea 05 20 65 paddxs\.sh r5,r5,r5
  11486. + *[0-9a-f]*: e8 04 20 64 paddxs\.sh r4,r4,r4
  11487. + *[0-9a-f]*: fc 0e 20 6e paddxs\.sh lr,lr,lr
  11488. + *[0-9a-f]*: e6 09 20 60 paddxs\.sh r0,r3,r9
  11489. + *[0-9a-f]*: f4 0b 20 6f paddxs\.sh pc,r10,r11
  11490. + *[0-9a-f]*: f4 0f 20 6f paddxs\.sh pc,r10,pc
  11491. +
  11492. +[0-9a-f]* <psubxs_sh>:
  11493. + *[0-9a-f]*: fe 0f 20 7f psubxs\.sh pc,pc,pc
  11494. + *[0-9a-f]*: f8 0c 20 7c psubxs\.sh r12,r12,r12
  11495. + *[0-9a-f]*: ea 05 20 75 psubxs\.sh r5,r5,r5
  11496. + *[0-9a-f]*: e8 04 20 74 psubxs\.sh r4,r4,r4
  11497. + *[0-9a-f]*: fc 0e 20 7e psubxs\.sh lr,lr,lr
  11498. + *[0-9a-f]*: e8 04 20 77 psubxs\.sh r7,r4,r4
  11499. + *[0-9a-f]*: f0 03 20 77 psubxs\.sh r7,r8,r3
  11500. + *[0-9a-f]*: ec 05 20 7f psubxs\.sh pc,r6,r5
  11501. +
  11502. +[0-9a-f]* <padds_uh>:
  11503. + *[0-9a-f]*: fe 0f 20 8f padds\.uh pc,pc,pc
  11504. + *[0-9a-f]*: f8 0c 20 8c padds\.uh r12,r12,r12
  11505. + *[0-9a-f]*: ea 05 20 85 padds\.uh r5,r5,r5
  11506. + *[0-9a-f]*: e8 04 20 84 padds\.uh r4,r4,r4
  11507. + *[0-9a-f]*: fc 0e 20 8e padds\.uh lr,lr,lr
  11508. + *[0-9a-f]*: f6 07 20 8c padds\.uh r12,r11,r7
  11509. + *[0-9a-f]*: f0 0e 20 87 padds\.uh r7,r8,lr
  11510. + *[0-9a-f]*: f2 07 20 86 padds\.uh r6,r9,r7
  11511. +
  11512. +[0-9a-f]* <psubs_uh>:
  11513. + *[0-9a-f]*: fe 0f 20 9f psubs\.uh pc,pc,pc
  11514. + *[0-9a-f]*: f8 0c 20 9c psubs\.uh r12,r12,r12
  11515. + *[0-9a-f]*: ea 05 20 95 psubs\.uh r5,r5,r5
  11516. + *[0-9a-f]*: e8 04 20 94 psubs\.uh r4,r4,r4
  11517. + *[0-9a-f]*: fc 0e 20 9e psubs\.uh lr,lr,lr
  11518. + *[0-9a-f]*: f4 06 20 9e psubs\.uh lr,r10,r6
  11519. + *[0-9a-f]*: e4 0f 20 9d psubs\.uh sp,r2,pc
  11520. + *[0-9a-f]*: f2 02 20 92 psubs\.uh r2,r9,r2
  11521. +
  11522. +[0-9a-f]* <paddxs_uh>:
  11523. + *[0-9a-f]*: fe 0f 20 af paddxs\.uh pc,pc,pc
  11524. + *[0-9a-f]*: f8 0c 20 ac paddxs\.uh r12,r12,r12
  11525. + *[0-9a-f]*: ea 05 20 a5 paddxs\.uh r5,r5,r5
  11526. + *[0-9a-f]*: e8 04 20 a4 paddxs\.uh r4,r4,r4
  11527. + *[0-9a-f]*: fc 0e 20 ae paddxs\.uh lr,lr,lr
  11528. + *[0-9a-f]*: f2 05 20 a7 paddxs\.uh r7,r9,r5
  11529. + *[0-9a-f]*: e2 04 20 a9 paddxs\.uh r9,r1,r4
  11530. + *[0-9a-f]*: e4 03 20 a5 paddxs\.uh r5,r2,r3
  11531. +
  11532. +[0-9a-f]* <psubxs_uh>:
  11533. + *[0-9a-f]*: fe 0f 20 bf psubxs\.uh pc,pc,pc
  11534. + *[0-9a-f]*: f8 0c 20 bc psubxs\.uh r12,r12,r12
  11535. + *[0-9a-f]*: ea 05 20 b5 psubxs\.uh r5,r5,r5
  11536. + *[0-9a-f]*: e8 04 20 b4 psubxs\.uh r4,r4,r4
  11537. + *[0-9a-f]*: fc 0e 20 be psubxs\.uh lr,lr,lr
  11538. + *[0-9a-f]*: ea 0d 20 bd psubxs\.uh sp,r5,sp
  11539. + *[0-9a-f]*: ec 06 20 bd psubxs\.uh sp,r6,r6
  11540. + *[0-9a-f]*: f6 08 20 b3 psubxs\.uh r3,r11,r8
  11541. +
  11542. +[0-9a-f]* <paddh_sh>:
  11543. + *[0-9a-f]*: fe 0f 20 cf paddh\.sh pc,pc,pc
  11544. + *[0-9a-f]*: f8 0c 20 cc paddh\.sh r12,r12,r12
  11545. + *[0-9a-f]*: ea 05 20 c5 paddh\.sh r5,r5,r5
  11546. + *[0-9a-f]*: e8 04 20 c4 paddh\.sh r4,r4,r4
  11547. + *[0-9a-f]*: fc 0e 20 ce paddh\.sh lr,lr,lr
  11548. + *[0-9a-f]*: fa 03 20 cc paddh\.sh r12,sp,r3
  11549. + *[0-9a-f]*: ea 03 20 cf paddh\.sh pc,r5,r3
  11550. + *[0-9a-f]*: f0 0d 20 c8 paddh\.sh r8,r8,sp
  11551. +
  11552. +[0-9a-f]* <psubh_sh>:
  11553. + *[0-9a-f]*: fe 0f 20 df psubh\.sh pc,pc,pc
  11554. + *[0-9a-f]*: f8 0c 20 dc psubh\.sh r12,r12,r12
  11555. + *[0-9a-f]*: ea 05 20 d5 psubh\.sh r5,r5,r5
  11556. + *[0-9a-f]*: e8 04 20 d4 psubh\.sh r4,r4,r4
  11557. + *[0-9a-f]*: fc 0e 20 de psubh\.sh lr,lr,lr
  11558. + *[0-9a-f]*: ea 08 20 d1 psubh\.sh r1,r5,r8
  11559. + *[0-9a-f]*: e6 06 20 d7 psubh\.sh r7,r3,r6
  11560. + *[0-9a-f]*: e6 03 20 d4 psubh\.sh r4,r3,r3
  11561. +
  11562. +[0-9a-f]* <paddxh_sh>:
  11563. + *[0-9a-f]*: fe 0f 20 ef paddxh\.sh pc,pc,pc
  11564. + *[0-9a-f]*: f8 0c 20 ec paddxh\.sh r12,r12,r12
  11565. + *[0-9a-f]*: ea 05 20 e5 paddxh\.sh r5,r5,r5
  11566. + *[0-9a-f]*: e8 04 20 e4 paddxh\.sh r4,r4,r4
  11567. + *[0-9a-f]*: fc 0e 20 ee paddxh\.sh lr,lr,lr
  11568. + *[0-9a-f]*: e0 04 20 e6 paddxh\.sh r6,r0,r4
  11569. + *[0-9a-f]*: f0 09 20 e9 paddxh\.sh r9,r8,r9
  11570. + *[0-9a-f]*: e0 0d 20 e3 paddxh\.sh r3,r0,sp
  11571. +
  11572. +[0-9a-f]* <psubxh_sh>:
  11573. + *[0-9a-f]*: fe 0f 20 ff psubxh\.sh pc,pc,pc
  11574. + *[0-9a-f]*: f8 0c 20 fc psubxh\.sh r12,r12,r12
  11575. + *[0-9a-f]*: ea 05 20 f5 psubxh\.sh r5,r5,r5
  11576. + *[0-9a-f]*: e8 04 20 f4 psubxh\.sh r4,r4,r4
  11577. + *[0-9a-f]*: fc 0e 20 fe psubxh\.sh lr,lr,lr
  11578. + *[0-9a-f]*: fe 0c 20 f4 psubxh\.sh r4,pc,r12
  11579. + *[0-9a-f]*: e8 06 20 f8 psubxh\.sh r8,r4,r6
  11580. + *[0-9a-f]*: f2 04 20 fc psubxh\.sh r12,r9,r4
  11581. +
  11582. +[0-9a-f]* <paddsub_h>:
  11583. + *[0-9a-f]*: fe 0f 21 0f paddsub\.h pc,pc:b,pc:b
  11584. + *[0-9a-f]*: f8 0c 21 3c paddsub\.h r12,r12:t,r12:t
  11585. + *[0-9a-f]*: ea 05 21 35 paddsub\.h r5,r5:t,r5:t
  11586. + *[0-9a-f]*: e8 04 21 04 paddsub\.h r4,r4:b,r4:b
  11587. + *[0-9a-f]*: fc 0e 21 3e paddsub\.h lr,lr:t,lr:t
  11588. + *[0-9a-f]*: e4 0e 21 25 paddsub\.h r5,r2:t,lr:b
  11589. + *[0-9a-f]*: e2 08 21 07 paddsub\.h r7,r1:b,r8:b
  11590. + *[0-9a-f]*: f4 05 21 36 paddsub\.h r6,r10:t,r5:t
  11591. +
  11592. +[0-9a-f]* <psubadd_h>:
  11593. + *[0-9a-f]*: fe 0f 21 4f psubadd\.h pc,pc:b,pc:b
  11594. + *[0-9a-f]*: f8 0c 21 7c psubadd\.h r12,r12:t,r12:t
  11595. + *[0-9a-f]*: ea 05 21 75 psubadd\.h r5,r5:t,r5:t
  11596. + *[0-9a-f]*: e8 04 21 44 psubadd\.h r4,r4:b,r4:b
  11597. + *[0-9a-f]*: fc 0e 21 7e psubadd\.h lr,lr:t,lr:t
  11598. + *[0-9a-f]*: f6 08 21 79 psubadd\.h r9,r11:t,r8:t
  11599. + *[0-9a-f]*: ee 0e 21 7a psubadd\.h r10,r7:t,lr:t
  11600. + *[0-9a-f]*: fe 0f 21 66 psubadd\.h r6,pc:t,pc:b
  11601. +
  11602. +[0-9a-f]* <paddsubs_sh>:
  11603. + *[0-9a-f]*: fe 0f 21 8f paddsubs\.sh pc,pc:b,pc:b
  11604. + *[0-9a-f]*: f8 0c 21 bc paddsubs\.sh r12,r12:t,r12:t
  11605. + *[0-9a-f]*: ea 05 21 b5 paddsubs\.sh r5,r5:t,r5:t
  11606. + *[0-9a-f]*: e8 04 21 84 paddsubs\.sh r4,r4:b,r4:b
  11607. + *[0-9a-f]*: fc 0e 21 be paddsubs\.sh lr,lr:t,lr:t
  11608. + *[0-9a-f]*: fc 00 21 a0 paddsubs\.sh r0,lr:t,r0:b
  11609. + *[0-9a-f]*: e4 04 21 b9 paddsubs\.sh r9,r2:t,r4:t
  11610. + *[0-9a-f]*: f2 0d 21 bc paddsubs\.sh r12,r9:t,sp:t
  11611. +
  11612. +[0-9a-f]* <psubadds_sh>:
  11613. + *[0-9a-f]*: fe 0f 21 cf psubadds\.sh pc,pc:b,pc:b
  11614. + *[0-9a-f]*: f8 0c 21 fc psubadds\.sh r12,r12:t,r12:t
  11615. + *[0-9a-f]*: ea 05 21 f5 psubadds\.sh r5,r5:t,r5:t
  11616. + *[0-9a-f]*: e8 04 21 c4 psubadds\.sh r4,r4:b,r4:b
  11617. + *[0-9a-f]*: fc 0e 21 fe psubadds\.sh lr,lr:t,lr:t
  11618. + *[0-9a-f]*: fc 01 21 df psubadds\.sh pc,lr:b,r1:t
  11619. + *[0-9a-f]*: e6 0c 21 cb psubadds\.sh r11,r3:b,r12:b
  11620. + *[0-9a-f]*: e4 08 21 fa psubadds\.sh r10,r2:t,r8:t
  11621. +
  11622. +[0-9a-f]* <paddsubs_uh>:
  11623. + *[0-9a-f]*: fe 0f 22 0f paddsubs\.uh pc,pc:b,pc:b
  11624. + *[0-9a-f]*: f8 0c 22 3c paddsubs\.uh r12,r12:t,r12:t
  11625. + *[0-9a-f]*: ea 05 22 35 paddsubs\.uh r5,r5:t,r5:t
  11626. + *[0-9a-f]*: e8 04 22 04 paddsubs\.uh r4,r4:b,r4:b
  11627. + *[0-9a-f]*: fc 0e 22 3e paddsubs\.uh lr,lr:t,lr:t
  11628. + *[0-9a-f]*: e4 03 22 09 paddsubs\.uh r9,r2:b,r3:b
  11629. + *[0-9a-f]*: fa 07 22 1d paddsubs\.uh sp,sp:b,r7:t
  11630. + *[0-9a-f]*: e0 0a 22 1e paddsubs\.uh lr,r0:b,r10:t
  11631. +
  11632. +[0-9a-f]* <psubadds_uh>:
  11633. + *[0-9a-f]*: fe 0f 22 4f psubadds\.uh pc,pc:b,pc:b
  11634. + *[0-9a-f]*: f8 0c 22 7c psubadds\.uh r12,r12:t,r12:t
  11635. + *[0-9a-f]*: ea 05 22 75 psubadds\.uh r5,r5:t,r5:t
  11636. + *[0-9a-f]*: e8 04 22 44 psubadds\.uh r4,r4:b,r4:b
  11637. + *[0-9a-f]*: fc 0e 22 7e psubadds\.uh lr,lr:t,lr:t
  11638. + *[0-9a-f]*: f2 0f 22 7c psubadds\.uh r12,r9:t,pc:t
  11639. + *[0-9a-f]*: ec 08 22 48 psubadds\.uh r8,r6:b,r8:b
  11640. + *[0-9a-f]*: f0 04 22 48 psubadds\.uh r8,r8:b,r4:b
  11641. +
  11642. +[0-9a-f]* <paddsubh_sh>:
  11643. + *[0-9a-f]*: fe 0f 22 8f paddsubh\.sh pc,pc:b,pc:b
  11644. + *[0-9a-f]*: f8 0c 22 bc paddsubh\.sh r12,r12:t,r12:t
  11645. + *[0-9a-f]*: ea 05 22 b5 paddsubh\.sh r5,r5:t,r5:t
  11646. + *[0-9a-f]*: e8 04 22 84 paddsubh\.sh r4,r4:b,r4:b
  11647. + *[0-9a-f]*: fc 0e 22 be paddsubh\.sh lr,lr:t,lr:t
  11648. + *[0-9a-f]*: f2 09 22 a8 paddsubh\.sh r8,r9:t,r9:b
  11649. + *[0-9a-f]*: fa 01 22 b0 paddsubh\.sh r0,sp:t,r1:t
  11650. + *[0-9a-f]*: e2 00 22 93 paddsubh\.sh r3,r1:b,r0:t
  11651. +
  11652. +[0-9a-f]* <psubaddh_sh>:
  11653. + *[0-9a-f]*: fe 0f 22 cf psubaddh\.sh pc,pc:b,pc:b
  11654. + *[0-9a-f]*: f8 0c 22 fc psubaddh\.sh r12,r12:t,r12:t
  11655. + *[0-9a-f]*: ea 05 22 f5 psubaddh\.sh r5,r5:t,r5:t
  11656. + *[0-9a-f]*: e8 04 22 c4 psubaddh\.sh r4,r4:b,r4:b
  11657. + *[0-9a-f]*: fc 0e 22 fe psubaddh\.sh lr,lr:t,lr:t
  11658. + *[0-9a-f]*: e6 0a 22 e7 psubaddh\.sh r7,r3:t,r10:b
  11659. + *[0-9a-f]*: e4 01 22 f7 psubaddh\.sh r7,r2:t,r1:t
  11660. + *[0-9a-f]*: e6 06 22 cb psubaddh\.sh r11,r3:b,r6:b
  11661. +
  11662. +[0-9a-f]* <padd_b>:
  11663. + *[0-9a-f]*: fe 0f 23 0f padd\.b pc,pc,pc
  11664. + *[0-9a-f]*: f8 0c 23 0c padd\.b r12,r12,r12
  11665. + *[0-9a-f]*: ea 05 23 05 padd\.b r5,r5,r5
  11666. + *[0-9a-f]*: e8 04 23 04 padd\.b r4,r4,r4
  11667. + *[0-9a-f]*: fc 0e 23 0e padd\.b lr,lr,lr
  11668. + *[0-9a-f]*: ec 0f 23 02 padd\.b r2,r6,pc
  11669. + *[0-9a-f]*: f2 0c 23 08 padd\.b r8,r9,r12
  11670. + *[0-9a-f]*: f8 03 23 05 padd\.b r5,r12,r3
  11671. +
  11672. +[0-9a-f]* <psub_b>:
  11673. + *[0-9a-f]*: fe 0f 23 1f psub\.b pc,pc,pc
  11674. + *[0-9a-f]*: f8 0c 23 1c psub\.b r12,r12,r12
  11675. + *[0-9a-f]*: ea 05 23 15 psub\.b r5,r5,r5
  11676. + *[0-9a-f]*: e8 04 23 14 psub\.b r4,r4,r4
  11677. + *[0-9a-f]*: fc 0e 23 1e psub\.b lr,lr,lr
  11678. + *[0-9a-f]*: f8 0f 23 10 psub\.b r0,r12,pc
  11679. + *[0-9a-f]*: fa 0a 23 17 psub\.b r7,sp,r10
  11680. + *[0-9a-f]*: fa 0c 23 15 psub\.b r5,sp,r12
  11681. +
  11682. +[0-9a-f]* <padds_sb>:
  11683. + *[0-9a-f]*: fe 0f 23 2f padds\.sb pc,pc,pc
  11684. + *[0-9a-f]*: f8 0c 23 2c padds\.sb r12,r12,r12
  11685. + *[0-9a-f]*: ea 05 23 25 padds\.sb r5,r5,r5
  11686. + *[0-9a-f]*: e8 04 23 24 padds\.sb r4,r4,r4
  11687. + *[0-9a-f]*: fc 0e 23 2e padds\.sb lr,lr,lr
  11688. + *[0-9a-f]*: f6 04 23 2d padds\.sb sp,r11,r4
  11689. + *[0-9a-f]*: f4 0b 23 2b padds\.sb r11,r10,r11
  11690. + *[0-9a-f]*: f8 06 23 25 padds\.sb r5,r12,r6
  11691. +
  11692. +[0-9a-f]* <psubs_sb>:
  11693. + *[0-9a-f]*: fe 0f 23 3f psubs\.sb pc,pc,pc
  11694. + *[0-9a-f]*: f8 0c 23 3c psubs\.sb r12,r12,r12
  11695. + *[0-9a-f]*: ea 05 23 35 psubs\.sb r5,r5,r5
  11696. + *[0-9a-f]*: e8 04 23 34 psubs\.sb r4,r4,r4
  11697. + *[0-9a-f]*: fc 0e 23 3e psubs\.sb lr,lr,lr
  11698. + *[0-9a-f]*: ec 08 23 37 psubs\.sb r7,r6,r8
  11699. + *[0-9a-f]*: f4 09 23 3c psubs\.sb r12,r10,r9
  11700. + *[0-9a-f]*: f6 00 23 3f psubs\.sb pc,r11,r0
  11701. +
  11702. +[0-9a-f]* <padds_ub>:
  11703. + *[0-9a-f]*: fe 0f 23 4f padds\.ub pc,pc,pc
  11704. + *[0-9a-f]*: f8 0c 23 4c padds\.ub r12,r12,r12
  11705. + *[0-9a-f]*: ea 05 23 45 padds\.ub r5,r5,r5
  11706. + *[0-9a-f]*: e8 04 23 44 padds\.ub r4,r4,r4
  11707. + *[0-9a-f]*: fc 0e 23 4e padds\.ub lr,lr,lr
  11708. + *[0-9a-f]*: e4 0b 23 43 padds\.ub r3,r2,r11
  11709. + *[0-9a-f]*: f0 01 23 4a padds\.ub r10,r8,r1
  11710. + *[0-9a-f]*: f0 0a 23 4b padds\.ub r11,r8,r10
  11711. +
  11712. +[0-9a-f]* <psubs_ub>:
  11713. + *[0-9a-f]*: fe 0f 23 5f psubs\.ub pc,pc,pc
  11714. + *[0-9a-f]*: f8 0c 23 5c psubs\.ub r12,r12,r12
  11715. + *[0-9a-f]*: ea 05 23 55 psubs\.ub r5,r5,r5
  11716. + *[0-9a-f]*: e8 04 23 54 psubs\.ub r4,r4,r4
  11717. + *[0-9a-f]*: fc 0e 23 5e psubs\.ub lr,lr,lr
  11718. + *[0-9a-f]*: e4 07 23 50 psubs\.ub r0,r2,r7
  11719. + *[0-9a-f]*: ea 03 23 5e psubs\.ub lr,r5,r3
  11720. + *[0-9a-f]*: ee 09 23 56 psubs\.ub r6,r7,r9
  11721. +
  11722. +[0-9a-f]* <paddh_ub>:
  11723. + *[0-9a-f]*: fe 0f 23 6f paddh\.ub pc,pc,pc
  11724. + *[0-9a-f]*: f8 0c 23 6c paddh\.ub r12,r12,r12
  11725. + *[0-9a-f]*: ea 05 23 65 paddh\.ub r5,r5,r5
  11726. + *[0-9a-f]*: e8 04 23 64 paddh\.ub r4,r4,r4
  11727. + *[0-9a-f]*: fc 0e 23 6e paddh\.ub lr,lr,lr
  11728. + *[0-9a-f]*: e2 00 23 6e paddh\.ub lr,r1,r0
  11729. + *[0-9a-f]*: ee 07 23 62 paddh\.ub r2,r7,r7
  11730. + *[0-9a-f]*: e2 02 23 62 paddh\.ub r2,r1,r2
  11731. +
  11732. +[0-9a-f]* <psubh_ub>:
  11733. + *[0-9a-f]*: fe 0f 23 7f psubh\.ub pc,pc,pc
  11734. + *[0-9a-f]*: f8 0c 23 7c psubh\.ub r12,r12,r12
  11735. + *[0-9a-f]*: ea 05 23 75 psubh\.ub r5,r5,r5
  11736. + *[0-9a-f]*: e8 04 23 74 psubh\.ub r4,r4,r4
  11737. + *[0-9a-f]*: fc 0e 23 7e psubh\.ub lr,lr,lr
  11738. + *[0-9a-f]*: e2 06 23 70 psubh\.ub r0,r1,r6
  11739. + *[0-9a-f]*: fc 0a 23 74 psubh\.ub r4,lr,r10
  11740. + *[0-9a-f]*: f0 01 23 79 psubh\.ub r9,r8,r1
  11741. +
  11742. +[0-9a-f]* <pmax_ub>:
  11743. + *[0-9a-f]*: fe 0f 23 8f pmax\.ub pc,pc,pc
  11744. + *[0-9a-f]*: f8 0c 23 8c pmax\.ub r12,r12,r12
  11745. + *[0-9a-f]*: ea 05 23 85 pmax\.ub r5,r5,r5
  11746. + *[0-9a-f]*: e8 04 23 84 pmax\.ub r4,r4,r4
  11747. + *[0-9a-f]*: fc 0e 23 8e pmax\.ub lr,lr,lr
  11748. + *[0-9a-f]*: e4 0b 23 8f pmax\.ub pc,r2,r11
  11749. + *[0-9a-f]*: e2 01 23 8c pmax\.ub r12,r1,r1
  11750. + *[0-9a-f]*: e4 00 23 85 pmax\.ub r5,r2,r0
  11751. +
  11752. +[0-9a-f]* <pmax_sh>:
  11753. + *[0-9a-f]*: fe 0f 23 9f pmax\.sh pc,pc,pc
  11754. + *[0-9a-f]*: f8 0c 23 9c pmax\.sh r12,r12,r12
  11755. + *[0-9a-f]*: ea 05 23 95 pmax\.sh r5,r5,r5
  11756. + *[0-9a-f]*: e8 04 23 94 pmax\.sh r4,r4,r4
  11757. + *[0-9a-f]*: fc 0e 23 9e pmax\.sh lr,lr,lr
  11758. + *[0-9a-f]*: ec 0c 23 9e pmax\.sh lr,r6,r12
  11759. + *[0-9a-f]*: fe 05 23 92 pmax\.sh r2,pc,r5
  11760. + *[0-9a-f]*: e4 07 23 9f pmax\.sh pc,r2,r7
  11761. +
  11762. +[0-9a-f]* <pmin_ub>:
  11763. + *[0-9a-f]*: fe 0f 23 af pmin\.ub pc,pc,pc
  11764. + *[0-9a-f]*: f8 0c 23 ac pmin\.ub r12,r12,r12
  11765. + *[0-9a-f]*: ea 05 23 a5 pmin\.ub r5,r5,r5
  11766. + *[0-9a-f]*: e8 04 23 a4 pmin\.ub r4,r4,r4
  11767. + *[0-9a-f]*: fc 0e 23 ae pmin\.ub lr,lr,lr
  11768. + *[0-9a-f]*: e2 05 23 a8 pmin\.ub r8,r1,r5
  11769. + *[0-9a-f]*: f0 03 23 a1 pmin\.ub r1,r8,r3
  11770. + *[0-9a-f]*: e4 07 23 a0 pmin\.ub r0,r2,r7
  11771. +
  11772. +[0-9a-f]* <pmin_sh>:
  11773. + *[0-9a-f]*: fe 0f 23 bf pmin\.sh pc,pc,pc
  11774. + *[0-9a-f]*: f8 0c 23 bc pmin\.sh r12,r12,r12
  11775. + *[0-9a-f]*: ea 05 23 b5 pmin\.sh r5,r5,r5
  11776. + *[0-9a-f]*: e8 04 23 b4 pmin\.sh r4,r4,r4
  11777. + *[0-9a-f]*: fc 0e 23 be pmin\.sh lr,lr,lr
  11778. + *[0-9a-f]*: e8 0a 23 b8 pmin\.sh r8,r4,r10
  11779. + *[0-9a-f]*: f4 0c 23 be pmin\.sh lr,r10,r12
  11780. + *[0-9a-f]*: ec 02 23 b2 pmin\.sh r2,r6,r2
  11781. +
  11782. +[0-9a-f]* <pavg_ub>:
  11783. + *[0-9a-f]*: fe 0f 23 cf pavg\.ub pc,pc,pc
  11784. + *[0-9a-f]*: f8 0c 23 cc pavg\.ub r12,r12,r12
  11785. + *[0-9a-f]*: ea 05 23 c5 pavg\.ub r5,r5,r5
  11786. + *[0-9a-f]*: e8 04 23 c4 pavg\.ub r4,r4,r4
  11787. + *[0-9a-f]*: fc 0e 23 ce pavg\.ub lr,lr,lr
  11788. + *[0-9a-f]*: e2 06 23 c0 pavg\.ub r0,r1,r6
  11789. + *[0-9a-f]*: e6 06 23 c8 pavg\.ub r8,r3,r6
  11790. + *[0-9a-f]*: f8 0a 23 cf pavg\.ub pc,r12,r10
  11791. +
  11792. +[0-9a-f]* <pavg_sh>:
  11793. + *[0-9a-f]*: fe 0f 23 df pavg\.sh pc,pc,pc
  11794. + *[0-9a-f]*: f8 0c 23 dc pavg\.sh r12,r12,r12
  11795. + *[0-9a-f]*: ea 05 23 d5 pavg\.sh r5,r5,r5
  11796. + *[0-9a-f]*: e8 04 23 d4 pavg\.sh r4,r4,r4
  11797. + *[0-9a-f]*: fc 0e 23 de pavg\.sh lr,lr,lr
  11798. + *[0-9a-f]*: fe 0d 23 d9 pavg\.sh r9,pc,sp
  11799. + *[0-9a-f]*: fa 03 23 df pavg\.sh pc,sp,r3
  11800. + *[0-9a-f]*: e2 09 23 d6 pavg\.sh r6,r1,r9
  11801. +
  11802. +[0-9a-f]* <pabs_sb>:
  11803. + *[0-9a-f]*: e0 0f 23 ef pabs\.sb pc,pc
  11804. + *[0-9a-f]*: e0 0c 23 ec pabs\.sb r12,r12
  11805. + *[0-9a-f]*: e0 05 23 e5 pabs\.sb r5,r5
  11806. + *[0-9a-f]*: e0 04 23 e4 pabs\.sb r4,r4
  11807. + *[0-9a-f]*: e0 0e 23 ee pabs\.sb lr,lr
  11808. + *[0-9a-f]*: e0 06 23 eb pabs\.sb r11,r6
  11809. + *[0-9a-f]*: e0 09 23 ee pabs\.sb lr,r9
  11810. + *[0-9a-f]*: e0 07 23 ed pabs\.sb sp,r7
  11811. +
  11812. +[0-9a-f]* <pabs_sh>:
  11813. + *[0-9a-f]*: e0 0f 23 ff pabs\.sh pc,pc
  11814. + *[0-9a-f]*: e0 0c 23 fc pabs\.sh r12,r12
  11815. + *[0-9a-f]*: e0 05 23 f5 pabs\.sh r5,r5
  11816. + *[0-9a-f]*: e0 04 23 f4 pabs\.sh r4,r4
  11817. + *[0-9a-f]*: e0 0e 23 fe pabs\.sh lr,lr
  11818. + *[0-9a-f]*: e0 03 23 ff pabs\.sh pc,r3
  11819. + *[0-9a-f]*: e0 07 23 f5 pabs\.sh r5,r7
  11820. + *[0-9a-f]*: e0 00 23 f4 pabs\.sh r4,r0
  11821. +
  11822. +[0-9a-f]* <psad>:
  11823. + *[0-9a-f]*: fe 0f 24 0f psad pc,pc,pc
  11824. + *[0-9a-f]*: f8 0c 24 0c psad r12,r12,r12
  11825. + *[0-9a-f]*: ea 05 24 05 psad r5,r5,r5
  11826. + *[0-9a-f]*: e8 04 24 04 psad r4,r4,r4
  11827. + *[0-9a-f]*: fc 0e 24 0e psad lr,lr,lr
  11828. + *[0-9a-f]*: f6 0b 24 09 psad r9,r11,r11
  11829. + *[0-9a-f]*: e8 0d 24 0e psad lr,r4,sp
  11830. + *[0-9a-f]*: e8 05 24 0e psad lr,r4,r5
  11831. +
  11832. +[0-9a-f]* <pasr_b>:
  11833. + *[0-9a-f]*: fe 00 24 1f pasr\.b pc,pc,0x0
  11834. + *[0-9a-f]*: f8 07 24 1c pasr\.b r12,r12,0x7
  11835. + *[0-9a-f]*: ea 04 24 15 pasr\.b r5,r5,0x4
  11836. + *[0-9a-f]*: e8 03 24 14 pasr\.b r4,r4,0x3
  11837. + *[0-9a-f]*: fc 01 24 1e pasr\.b lr,lr,0x1
  11838. + *[0-9a-f]*: ee 01 24 1f pasr\.b pc,r7,0x1
  11839. + *[0-9a-f]*: fc 06 24 1d pasr\.b sp,lr,0x6
  11840. + *[0-9a-f]*: e6 02 24 1d pasr\.b sp,r3,0x2
  11841. +
  11842. +[0-9a-f]* <plsl_b>:
  11843. + *[0-9a-f]*: fe 00 24 2f plsl\.b pc,pc,0x0
  11844. + *[0-9a-f]*: f8 07 24 2c plsl\.b r12,r12,0x7
  11845. + *[0-9a-f]*: ea 04 24 25 plsl\.b r5,r5,0x4
  11846. + *[0-9a-f]*: e8 03 24 24 plsl\.b r4,r4,0x3
  11847. + *[0-9a-f]*: fc 01 24 2e plsl\.b lr,lr,0x1
  11848. + *[0-9a-f]*: f6 04 24 22 plsl\.b r2,r11,0x4
  11849. + *[0-9a-f]*: ea 07 24 28 plsl\.b r8,r5,0x7
  11850. + *[0-9a-f]*: e0 02 24 2f plsl\.b pc,r0,0x2
  11851. +
  11852. +[0-9a-f]* <plsr_b>:
  11853. + *[0-9a-f]*: fe 00 24 3f plsr\.b pc,pc,0x0
  11854. + *[0-9a-f]*: f8 07 24 3c plsr\.b r12,r12,0x7
  11855. + *[0-9a-f]*: ea 04 24 35 plsr\.b r5,r5,0x4
  11856. + *[0-9a-f]*: e8 03 24 34 plsr\.b r4,r4,0x3
  11857. + *[0-9a-f]*: fc 01 24 3e plsr\.b lr,lr,0x1
  11858. + *[0-9a-f]*: e2 02 24 3c plsr\.b r12,r1,0x2
  11859. + *[0-9a-f]*: fe 07 24 36 plsr\.b r6,pc,0x7
  11860. + *[0-9a-f]*: f6 02 24 3c plsr\.b r12,r11,0x2
  11861. +
  11862. +[0-9a-f]* <pasr_h>:
  11863. + *[0-9a-f]*: fe 00 24 4f pasr\.h pc,pc,0x0
  11864. + *[0-9a-f]*: f8 0f 24 4c pasr\.h r12,r12,0xf
  11865. + *[0-9a-f]*: ea 08 24 45 pasr\.h r5,r5,0x8
  11866. + *[0-9a-f]*: e8 07 24 44 pasr\.h r4,r4,0x7
  11867. + *[0-9a-f]*: fc 01 24 4e pasr\.h lr,lr,0x1
  11868. + *[0-9a-f]*: f6 0a 24 40 pasr\.h r0,r11,0xa
  11869. + *[0-9a-f]*: ec 08 24 44 pasr\.h r4,r6,0x8
  11870. + *[0-9a-f]*: e4 04 24 46 pasr\.h r6,r2,0x4
  11871. +
  11872. +[0-9a-f]* <plsl_h>:
  11873. + *[0-9a-f]*: fe 00 24 5f plsl\.h pc,pc,0x0
  11874. + *[0-9a-f]*: f8 0f 24 5c plsl\.h r12,r12,0xf
  11875. + *[0-9a-f]*: ea 08 24 55 plsl\.h r5,r5,0x8
  11876. + *[0-9a-f]*: e8 07 24 54 plsl\.h r4,r4,0x7
  11877. + *[0-9a-f]*: fc 01 24 5e plsl\.h lr,lr,0x1
  11878. + *[0-9a-f]*: f4 09 24 55 plsl\.h r5,r10,0x9
  11879. + *[0-9a-f]*: fc 08 24 5d plsl\.h sp,lr,0x8
  11880. + *[0-9a-f]*: fc 07 24 50 plsl\.h r0,lr,0x7
  11881. +
  11882. +[0-9a-f]* <plsr_h>:
  11883. + *[0-9a-f]*: fe 00 24 6f plsr\.h pc,pc,0x0
  11884. + *[0-9a-f]*: f8 0f 24 6c plsr\.h r12,r12,0xf
  11885. + *[0-9a-f]*: ea 08 24 65 plsr\.h r5,r5,0x8
  11886. + *[0-9a-f]*: e8 07 24 64 plsr\.h r4,r4,0x7
  11887. + *[0-9a-f]*: fc 01 24 6e plsr\.h lr,lr,0x1
  11888. + *[0-9a-f]*: e0 0f 24 6b plsr\.h r11,r0,0xf
  11889. + *[0-9a-f]*: e6 03 24 6e plsr\.h lr,r3,0x3
  11890. + *[0-9a-f]*: fc 0a 24 68 plsr\.h r8,lr,0xa
  11891. +
  11892. +[0-9a-f]* <packw_sh>:
  11893. + *[0-9a-f]*: fe 0f 24 7f packw\.sh pc,pc,pc
  11894. + *[0-9a-f]*: f8 0c 24 7c packw\.sh r12,r12,r12
  11895. + *[0-9a-f]*: ea 05 24 75 packw\.sh r5,r5,r5
  11896. + *[0-9a-f]*: e8 04 24 74 packw\.sh r4,r4,r4
  11897. + *[0-9a-f]*: fc 0e 24 7e packw\.sh lr,lr,lr
  11898. + *[0-9a-f]*: f6 0a 24 7d packw\.sh sp,r11,r10
  11899. + *[0-9a-f]*: e4 0c 24 78 packw\.sh r8,r2,r12
  11900. + *[0-9a-f]*: e2 05 24 78 packw\.sh r8,r1,r5
  11901. +
  11902. +[0-9a-f]* <punpckub_h>:
  11903. + *[0-9a-f]*: fe 00 24 8f punpckub\.h pc,pc:b
  11904. + *[0-9a-f]*: f8 00 24 9c punpckub\.h r12,r12:t
  11905. + *[0-9a-f]*: ea 00 24 95 punpckub\.h r5,r5:t
  11906. + *[0-9a-f]*: e8 00 24 84 punpckub\.h r4,r4:b
  11907. + *[0-9a-f]*: fc 00 24 9e punpckub\.h lr,lr:t
  11908. + *[0-9a-f]*: e2 00 24 96 punpckub\.h r6,r1:t
  11909. + *[0-9a-f]*: ea 00 24 8e punpckub\.h lr,r5:b
  11910. + *[0-9a-f]*: e4 00 24 9e punpckub\.h lr,r2:t
  11911. +
  11912. +[0-9a-f]* <punpcksb_h>:
  11913. + *[0-9a-f]*: fe 00 24 af punpcksb\.h pc,pc:b
  11914. + *[0-9a-f]*: f8 00 24 bc punpcksb\.h r12,r12:t
  11915. + *[0-9a-f]*: ea 00 24 b5 punpcksb\.h r5,r5:t
  11916. + *[0-9a-f]*: e8 00 24 a4 punpcksb\.h r4,r4:b
  11917. + *[0-9a-f]*: fc 00 24 be punpcksb\.h lr,lr:t
  11918. + *[0-9a-f]*: ee 00 24 b4 punpcksb\.h r4,r7:t
  11919. + *[0-9a-f]*: fc 00 24 a6 punpcksb\.h r6,lr:b
  11920. + *[0-9a-f]*: f8 00 24 bc punpcksb\.h r12,r12:t
  11921. +
  11922. +[0-9a-f]* <packsh_ub>:
  11923. + *[0-9a-f]*: fe 0f 24 cf packsh\.ub pc,pc,pc
  11924. + *[0-9a-f]*: f8 0c 24 cc packsh\.ub r12,r12,r12
  11925. + *[0-9a-f]*: ea 05 24 c5 packsh\.ub r5,r5,r5
  11926. + *[0-9a-f]*: e8 04 24 c4 packsh\.ub r4,r4,r4
  11927. + *[0-9a-f]*: fc 0e 24 ce packsh\.ub lr,lr,lr
  11928. + *[0-9a-f]*: ec 03 24 c3 packsh\.ub r3,r6,r3
  11929. + *[0-9a-f]*: e0 03 24 c8 packsh\.ub r8,r0,r3
  11930. + *[0-9a-f]*: e6 0e 24 c9 packsh\.ub r9,r3,lr
  11931. +
  11932. +[0-9a-f]* <packsh_sb>:
  11933. + *[0-9a-f]*: fe 0f 24 df packsh\.sb pc,pc,pc
  11934. + *[0-9a-f]*: f8 0c 24 dc packsh\.sb r12,r12,r12
  11935. + *[0-9a-f]*: ea 05 24 d5 packsh\.sb r5,r5,r5
  11936. + *[0-9a-f]*: e8 04 24 d4 packsh\.sb r4,r4,r4
  11937. + *[0-9a-f]*: fc 0e 24 de packsh\.sb lr,lr,lr
  11938. + *[0-9a-f]*: f0 01 24 d6 packsh\.sb r6,r8,r1
  11939. + *[0-9a-f]*: f2 08 24 de packsh\.sb lr,r9,r8
  11940. + *[0-9a-f]*: ec 06 24 dd packsh\.sb sp,r6,r6
  11941. +
  11942. +[0-9a-f]* <andl>:
  11943. + *[0-9a-f]*: e0 1f 00 00 andl pc,0x0
  11944. + *[0-9a-f]*: e0 1c ff ff andl r12,0xffff
  11945. + *[0-9a-f]*: e0 15 80 00 andl r5,0x8000
  11946. + *[0-9a-f]*: e0 14 7f ff andl r4,0x7fff
  11947. + *[0-9a-f]*: e0 1e 00 01 andl lr,0x1
  11948. + *[0-9a-f]*: e0 1f 5a 58 andl pc,0x5a58
  11949. + *[0-9a-f]*: e0 18 b8 9e andl r8,0xb89e
  11950. + *[0-9a-f]*: e0 17 35 97 andl r7,0x3597
  11951. +
  11952. +[0-9a-f]* <andl_coh>:
  11953. + *[0-9a-f]*: e2 1f 00 00 andl pc,0x0,COH
  11954. + *[0-9a-f]*: e2 1c ff ff andl r12,0xffff,COH
  11955. + *[0-9a-f]*: e2 15 80 00 andl r5,0x8000,COH
  11956. + *[0-9a-f]*: e2 14 7f ff andl r4,0x7fff,COH
  11957. + *[0-9a-f]*: e2 1e 00 01 andl lr,0x1,COH
  11958. + *[0-9a-f]*: e2 16 58 e1 andl r6,0x58e1,COH
  11959. + *[0-9a-f]*: e2 10 9e cd andl r0,0x9ecd,COH
  11960. + *[0-9a-f]*: e2 14 bd c4 andl r4,0xbdc4,COH
  11961. +
  11962. +[0-9a-f]* <andh>:
  11963. + *[0-9a-f]*: e4 1f 00 00 andh pc,0x0
  11964. + *[0-9a-f]*: e4 1c ff ff andh r12,0xffff
  11965. + *[0-9a-f]*: e4 15 80 00 andh r5,0x8000
  11966. + *[0-9a-f]*: e4 14 7f ff andh r4,0x7fff
  11967. + *[0-9a-f]*: e4 1e 00 01 andh lr,0x1
  11968. + *[0-9a-f]*: e4 1c cc 58 andh r12,0xcc58
  11969. + *[0-9a-f]*: e4 13 21 e3 andh r3,0x21e3
  11970. + *[0-9a-f]*: e4 12 a7 eb andh r2,0xa7eb
  11971. +
  11972. +[0-9a-f]* <andh_coh>:
  11973. + *[0-9a-f]*: e6 1f 00 00 andh pc,0x0,COH
  11974. + *[0-9a-f]*: e6 1c ff ff andh r12,0xffff,COH
  11975. + *[0-9a-f]*: e6 15 80 00 andh r5,0x8000,COH
  11976. + *[0-9a-f]*: e6 14 7f ff andh r4,0x7fff,COH
  11977. + *[0-9a-f]*: e6 1e 00 01 andh lr,0x1,COH
  11978. + *[0-9a-f]*: e6 1b 86 0d andh r11,0x860d,COH
  11979. + *[0-9a-f]*: e6 18 ce f6 andh r8,0xcef6,COH
  11980. + *[0-9a-f]*: e6 1a 5c 83 andh r10,0x5c83,COH
  11981. +
  11982. +[0-9a-f]* <orl>:
  11983. + *[0-9a-f]*: e8 1f 00 00 orl pc,0x0
  11984. + *[0-9a-f]*: e8 1c ff ff orl r12,0xffff
  11985. + *[0-9a-f]*: e8 15 80 00 orl r5,0x8000
  11986. + *[0-9a-f]*: e8 14 7f ff orl r4,0x7fff
  11987. + *[0-9a-f]*: e8 1e 00 01 orl lr,0x1
  11988. + *[0-9a-f]*: e8 1d 41 7e orl sp,0x417e
  11989. + *[0-9a-f]*: e8 10 52 bd orl r0,0x52bd
  11990. + *[0-9a-f]*: e8 1f ac 47 orl pc,0xac47
  11991. +
  11992. +[0-9a-f]* <orh>:
  11993. + *[0-9a-f]*: ea 1f 00 00 orh pc,0x0
  11994. + *[0-9a-f]*: ea 1c ff ff orh r12,0xffff
  11995. + *[0-9a-f]*: ea 15 80 00 orh r5,0x8000
  11996. + *[0-9a-f]*: ea 14 7f ff orh r4,0x7fff
  11997. + *[0-9a-f]*: ea 1e 00 01 orh lr,0x1
  11998. + *[0-9a-f]*: ea 18 6e 7d orh r8,0x6e7d
  11999. + *[0-9a-f]*: ea 1c 77 1c orh r12,0x771c
  12000. + *[0-9a-f]*: ea 11 ea 1a orh r1,0xea1a
  12001. +
  12002. +[0-9a-f]* <eorl>:
  12003. + *[0-9a-f]*: ec 1f 00 00 eorl pc,0x0
  12004. + *[0-9a-f]*: ec 1c ff ff eorl r12,0xffff
  12005. + *[0-9a-f]*: ec 15 80 00 eorl r5,0x8000
  12006. + *[0-9a-f]*: ec 14 7f ff eorl r4,0x7fff
  12007. + *[0-9a-f]*: ec 1e 00 01 eorl lr,0x1
  12008. + *[0-9a-f]*: ec 14 c7 b9 eorl r4,0xc7b9
  12009. + *[0-9a-f]*: ec 16 fb dd eorl r6,0xfbdd
  12010. + *[0-9a-f]*: ec 11 51 b1 eorl r1,0x51b1
  12011. +
  12012. +[0-9a-f]* <eorh>:
  12013. + *[0-9a-f]*: ee 1f 00 00 eorh pc,0x0
  12014. + *[0-9a-f]*: ee 1c ff ff eorh r12,0xffff
  12015. + *[0-9a-f]*: ee 15 80 00 eorh r5,0x8000
  12016. + *[0-9a-f]*: ee 14 7f ff eorh r4,0x7fff
  12017. + *[0-9a-f]*: ee 1e 00 01 eorh lr,0x1
  12018. + *[0-9a-f]*: ee 10 2d d4 eorh r0,0x2dd4
  12019. + *[0-9a-f]*: ee 1a 94 b5 eorh r10,0x94b5
  12020. + *[0-9a-f]*: ee 19 df 2a eorh r9,0xdf2a
  12021. +
  12022. +[0-9a-f]* <mcall>:
  12023. + *[0-9a-f]*: f0 1f 00 00 mcall [0-9a-f]* <.*>
  12024. + *[0-9a-f]*: f0 1c ff ff mcall r12\[-4\]
  12025. + *[0-9a-f]*: f0 15 80 00 mcall r5\[-131072\]
  12026. + *[0-9a-f]*: f0 14 7f ff mcall r4\[131068\]
  12027. + *[0-9a-f]*: f0 1e 00 01 mcall lr\[4\]
  12028. + *[0-9a-f]*: f0 1d 3b bf mcall sp\[61180\]
  12029. + *[0-9a-f]*: f0 14 dd d2 mcall r4\[-35000\]
  12030. + *[0-9a-f]*: f0 10 09 b1 mcall r0\[9924\]
  12031. +
  12032. +[0-9a-f]* <pref>:
  12033. + *[0-9a-f]*: f2 1f 00 00 pref pc\[0\]
  12034. + *[0-9a-f]*: f2 1c ff ff pref r12\[-1\]
  12035. + *[0-9a-f]*: f2 15 80 00 pref r5\[-32768\]
  12036. + *[0-9a-f]*: f2 14 7f ff pref r4\[32767\]
  12037. + *[0-9a-f]*: f2 1e 00 01 pref lr\[1\]
  12038. + *[0-9a-f]*: f2 17 1e 44 pref r7\[7748\]
  12039. + *[0-9a-f]*: f2 17 e1 ed pref r7\[-7699\]
  12040. + *[0-9a-f]*: f2 12 9a dc pref r2\[-25892\]
  12041. +
  12042. +[0-9a-f]* <cache>:
  12043. + *[0-9a-f]*: f4 1f 00 00 cache pc\[0\],0x0
  12044. + *[0-9a-f]*: f4 1c ff ff cache r12\[-1\],0x1f
  12045. + *[0-9a-f]*: f4 15 84 00 cache r5\[-1024\],0x10
  12046. + *[0-9a-f]*: f4 14 7b ff cache r4\[1023\],0xf
  12047. + *[0-9a-f]*: f4 1e 08 01 cache lr\[1\],0x1
  12048. + *[0-9a-f]*: f4 13 8c 3c cache r3\[-964\],0x11
  12049. + *[0-9a-f]*: f4 14 b6 89 cache r4\[-375\],0x16
  12050. + *[0-9a-f]*: f4 13 8c 88 cache r3\[-888\],0x11
  12051. +
  12052. +[0-9a-f]* <sub4>:
  12053. + *[0-9a-f]*: 20 0f sub pc,0
  12054. + *[0-9a-f]*: 2f fc sub r12,-1
  12055. + *[0-9a-f]*: f0 25 00 00 sub r5,-1048576
  12056. + *[0-9a-f]*: ee 34 ff ff sub r4,1048575
  12057. + *[0-9a-f]*: 20 1e sub lr,1
  12058. + *[0-9a-f]*: f6 22 8d 6c sub r2,-619156
  12059. + *[0-9a-f]*: e6 3e 0a cd sub lr,461517
  12060. + *[0-9a-f]*: fc 38 2d 25 sub r8,-185051
  12061. +
  12062. +[0-9a-f]* <cp3>:
  12063. + *[0-9a-f]*: 58 0f cp.w pc,0
  12064. + *[0-9a-f]*: 5b fc cp.w r12,-1
  12065. + *[0-9a-f]*: f0 45 00 00 cp.w r5,-1048576
  12066. + *[0-9a-f]*: ee 54 ff ff cp.w r4,1048575
  12067. + *[0-9a-f]*: 58 1e cp.w lr,1
  12068. + *[0-9a-f]*: e0 51 e4 ae cp.w r1,124078
  12069. + *[0-9a-f]*: fa 40 37 e3 cp.w r0,-378909
  12070. + *[0-9a-f]*: fc 44 4a 14 cp.w r4,-243180
  12071. +
  12072. +[0-9a-f]* <mov2>:
  12073. + *[0-9a-f]*: 30 0f mov pc,0
  12074. + *[0-9a-f]*: 3f fc mov r12,-1
  12075. + *[0-9a-f]*: f0 65 00 00 mov r5,-1048576
  12076. + *[0-9a-f]*: ee 74 ff ff mov r4,1048575
  12077. + *[0-9a-f]*: 30 1e mov lr,1
  12078. + *[0-9a-f]*: fa 75 29 a3 mov r5,-317021
  12079. + *[0-9a-f]*: f4 6d 91 94 mov sp,-749164
  12080. + *[0-9a-f]*: ee 65 58 93 mov r5,940179
  12081. +
  12082. +[0-9a-f]* <brc2>:
  12083. + *[0-9a-f]*: c0 00 breq [0-9a-f]* <.*>
  12084. + *[0-9a-f]*: fe 9f ff ff bral [0-9a-f]* <.*>
  12085. + *[0-9a-f]*: f0 88 00 00 brls [0-9a-f]* <.*>
  12086. + *[0-9a-f]*: ee 97 ff ff brpl [0-9a-f]* <.*>
  12087. + *[0-9a-f]*: c0 11 brne [0-9a-f]* <.*>
  12088. + *[0-9a-f]*: f2 8b 4a 4d brhi [0-9a-f]* <.*>
  12089. + *[0-9a-f]*: ea 8e 14 cc brqs [0-9a-f]* <.*>
  12090. + *[0-9a-f]*: fa 98 98 33 brls [0-9a-f]* <.*>
  12091. +
  12092. +[0-9a-f]* <rcall2>:
  12093. + *[0-9a-f]*: c0 0c rcall [0-9a-f]* <.*>
  12094. + *[0-9a-f]*: cf ff rcall [0-9a-f]* <.*>
  12095. + *[0-9a-f]*: f0 a0 00 00 rcall [0-9a-f]* <.*>
  12096. + *[0-9a-f]*: ee b0 ff ff rcall [0-9a-f]* <.*>
  12097. + *[0-9a-f]*: c0 1c rcall [0-9a-f]* <.*>
  12098. + *[0-9a-f]*: e2 b0 ca 5a rcall [0-9a-f]* <.*>
  12099. + *[0-9a-f]*: e8 a0 47 52 rcall [0-9a-f]* <.*>
  12100. + *[0-9a-f]*: fe b0 fd ef rcall [0-9a-f]* <.*>
  12101. +
  12102. +[0-9a-f]* <sub5>:
  12103. + *[0-9a-f]*: fe cf 00 00 sub pc,pc,0
  12104. + *[0-9a-f]*: f8 cc ff ff sub r12,r12,-1
  12105. + *[0-9a-f]*: ea c5 80 00 sub r5,r5,-32768
  12106. + *[0-9a-f]*: e8 c4 7f ff sub r4,r4,32767
  12107. + *[0-9a-f]*: fc ce 00 01 sub lr,lr,1
  12108. + *[0-9a-f]*: fe cf ce 38 sub pc,pc,-12744
  12109. + *[0-9a-f]*: ee c7 95 1b sub r7,r7,-27365
  12110. + *[0-9a-f]*: f2 c2 bc 32 sub r2,r9,-17358
  12111. +
  12112. +[0-9a-f]* <satsub_w2>:
  12113. + *[0-9a-f]*: fe df 00 00 satsub\.w pc,pc,0
  12114. + *[0-9a-f]*: f8 dc ff ff satsub\.w r12,r12,-1
  12115. + *[0-9a-f]*: ea d5 80 00 satsub\.w r5,r5,-32768
  12116. + *[0-9a-f]*: e8 d4 7f ff satsub\.w r4,r4,32767
  12117. + *[0-9a-f]*: fc de 00 01 satsub\.w lr,lr,1
  12118. + *[0-9a-f]*: fc d2 f8 29 satsub\.w r2,lr,-2007
  12119. + *[0-9a-f]*: f8 d7 fc f0 satsub\.w r7,r12,-784
  12120. + *[0-9a-f]*: ee d4 5a 8c satsub\.w r4,r7,23180
  12121. +
  12122. +[0-9a-f]* <ld_d4>:
  12123. + *[0-9a-f]*: fe e0 00 00 ld\.d r0,pc\[0\]
  12124. + *[0-9a-f]*: f8 ee ff ff ld\.d lr,r12\[-1\]
  12125. + *[0-9a-f]*: ea e8 80 00 ld\.d r8,r5\[-32768\]
  12126. + *[0-9a-f]*: e8 e6 7f ff ld\.d r6,r4\[32767\]
  12127. + *[0-9a-f]*: fc e2 00 01 ld\.d r2,lr\[1\]
  12128. + *[0-9a-f]*: f6 ee 39 c0 ld\.d lr,r11\[14784\]
  12129. + *[0-9a-f]*: f2 e6 b6 27 ld\.d r6,r9\[-18905\]
  12130. + *[0-9a-f]*: e6 e2 e7 2d ld\.d r2,r3\[-6355\]
  12131. +
  12132. +[0-9a-f]* <ld_w4>:
  12133. + *[0-9a-f]*: 7e 0f ld\.w pc,pc\[0x0\]
  12134. + *[0-9a-f]*: f8 fc ff ff ld\.w r12,r12\[-1\]
  12135. + *[0-9a-f]*: ea f5 80 00 ld\.w r5,r5\[-32768\]
  12136. + *[0-9a-f]*: e8 f4 7f ff ld\.w r4,r4\[32767\]
  12137. + *[0-9a-f]*: fc fe 00 01 ld\.w lr,lr\[1\]
  12138. + *[0-9a-f]*: f8 f0 a9 8b ld\.w r0,r12\[-22133\]
  12139. + *[0-9a-f]*: fe fd af d7 ld\.w sp,pc\[-20521\]
  12140. + *[0-9a-f]*: d7 03 nop
  12141. +
  12142. +[0-9a-f]* <ld_sh4>:
  12143. + *[0-9a-f]*: 9e 0f ld\.sh pc,pc\[0x0\]
  12144. + *[0-9a-f]*: f9 0c ff ff ld\.sh r12,r12\[-1\]
  12145. + *[0-9a-f]*: eb 05 80 00 ld\.sh r5,r5\[-32768\]
  12146. + *[0-9a-f]*: e9 04 7f ff ld\.sh r4,r4\[32767\]
  12147. + *[0-9a-f]*: fd 0e 00 01 ld\.sh lr,lr\[1\]
  12148. + *[0-9a-f]*: f5 06 78 d2 ld\.sh r6,r10\[30930\]
  12149. + *[0-9a-f]*: f5 06 55 d5 ld\.sh r6,r10\[21973\]
  12150. + *[0-9a-f]*: d7 03 nop
  12151. +
  12152. +[0-9a-f]* <ld_uh4>:
  12153. + *[0-9a-f]*: 9e 8f ld\.uh pc,pc\[0x0\]
  12154. + *[0-9a-f]*: f9 1c ff ff ld\.uh r12,r12\[-1\]
  12155. + *[0-9a-f]*: eb 15 80 00 ld\.uh r5,r5\[-32768\]
  12156. + *[0-9a-f]*: e9 14 7f ff ld\.uh r4,r4\[32767\]
  12157. + *[0-9a-f]*: fd 1e 00 01 ld\.uh lr,lr\[1\]
  12158. + *[0-9a-f]*: f3 11 cb d6 ld\.uh r1,r9\[-13354\]
  12159. + *[0-9a-f]*: f7 1e 53 59 ld\.uh lr,r11\[21337\]
  12160. + *[0-9a-f]*: d7 03 nop
  12161. +
  12162. +[0-9a-f]* <ld_sb1>:
  12163. + *[0-9a-f]*: ff 2f 00 00 ld\.sb pc,pc\[0\]
  12164. + *[0-9a-f]*: f9 2c ff ff ld\.sb r12,r12\[-1\]
  12165. + *[0-9a-f]*: eb 25 80 00 ld\.sb r5,r5\[-32768\]
  12166. + *[0-9a-f]*: e9 24 7f ff ld\.sb r4,r4\[32767\]
  12167. + *[0-9a-f]*: fd 2e 00 01 ld\.sb lr,lr\[1\]
  12168. + *[0-9a-f]*: fb 27 90 09 ld\.sb r7,sp\[-28663\]
  12169. + *[0-9a-f]*: e3 22 e9 09 ld\.sb r2,r1\[-5879\]
  12170. + *[0-9a-f]*: e7 2c 49 2e ld\.sb r12,r3\[18734\]
  12171. +
  12172. +[0-9a-f]* <ld_ub4>:
  12173. + *[0-9a-f]*: 1f 8f ld\.ub pc,pc\[0x0\]
  12174. + *[0-9a-f]*: f9 3c ff ff ld\.ub r12,r12\[-1\]
  12175. + *[0-9a-f]*: eb 35 80 00 ld\.ub r5,r5\[-32768\]
  12176. + *[0-9a-f]*: e9 34 7f ff ld\.ub r4,r4\[32767\]
  12177. + *[0-9a-f]*: 1d 9e ld\.ub lr,lr\[0x1\]
  12178. + *[0-9a-f]*: e9 3f 20 55 ld\.ub pc,r4\[8277\]
  12179. + *[0-9a-f]*: f9 35 4a e4 ld\.ub r5,r12\[19172\]
  12180. + *[0-9a-f]*: fd 3a 66 eb ld\.ub r10,lr\[26347\]
  12181. +
  12182. +[0-9a-f]* <st_d4>:
  12183. + *[0-9a-f]*: fe e1 00 00 st\.d pc\[0\],r0
  12184. + *[0-9a-f]*: f8 ef ff ff st\.d r12\[-1\],lr
  12185. + *[0-9a-f]*: ea e9 80 00 st\.d r5\[-32768\],r8
  12186. + *[0-9a-f]*: e8 e7 7f ff st\.d r4\[32767\],r6
  12187. + *[0-9a-f]*: fc e3 00 01 st\.d lr\[1\],r2
  12188. + *[0-9a-f]*: ea eb 33 90 st\.d r5\[13200\],r10
  12189. + *[0-9a-f]*: ea eb 24 88 st\.d r5\[9352\],r10
  12190. + *[0-9a-f]*: ea e5 7e 75 st\.d r5\[32373\],r4
  12191. +
  12192. +[0-9a-f]* <st_w4>:
  12193. + *[0-9a-f]*: 9f 0f st\.w pc\[0x0\],pc
  12194. + *[0-9a-f]*: f9 4c ff ff st\.w r12\[-1\],r12
  12195. + *[0-9a-f]*: eb 45 80 00 st\.w r5\[-32768\],r5
  12196. + *[0-9a-f]*: e9 44 7f ff st\.w r4\[32767\],r4
  12197. + *[0-9a-f]*: fd 4e 00 01 st\.w lr\[1\],lr
  12198. + *[0-9a-f]*: fb 47 17 f8 st\.w sp\[6136\],r7
  12199. + *[0-9a-f]*: ed 4c 69 cf st\.w r6\[27087\],r12
  12200. + *[0-9a-f]*: d7 03 nop
  12201. +
  12202. +[0-9a-f]* <st_h4>:
  12203. + *[0-9a-f]*: be 0f st\.h pc\[0x0\],pc
  12204. + *[0-9a-f]*: f9 5c ff ff st\.h r12\[-1\],r12
  12205. + *[0-9a-f]*: eb 55 80 00 st\.h r5\[-32768\],r5
  12206. + *[0-9a-f]*: e9 54 7f ff st\.h r4\[32767\],r4
  12207. + *[0-9a-f]*: fd 5e 00 01 st\.h lr\[1\],lr
  12208. + *[0-9a-f]*: e9 57 d9 16 st\.h r4\[-9962\],r7
  12209. + *[0-9a-f]*: f3 53 c0 86 st\.h r9\[-16250\],r3
  12210. + *[0-9a-f]*: d7 03 nop
  12211. +
  12212. +[0-9a-f]* <st_b4>:
  12213. + *[0-9a-f]*: be 8f st\.b pc\[0x0\],pc
  12214. + *[0-9a-f]*: f9 6c ff ff st\.b r12\[-1\],r12
  12215. + *[0-9a-f]*: eb 65 80 00 st\.b r5\[-32768\],r5
  12216. + *[0-9a-f]*: e9 64 7f ff st\.b r4\[32767\],r4
  12217. + *[0-9a-f]*: bc 9e st\.b lr\[0x1\],lr
  12218. + *[0-9a-f]*: f9 66 75 96 st\.b r12\[30102\],r6
  12219. + *[0-9a-f]*: eb 61 71 31 st\.b r5\[28977\],r1
  12220. + *[0-9a-f]*: e1 61 15 5e st\.b r0\[5470\],r1
  12221. +
  12222. +[0-9a-f]* <mfsr>:
  12223. + *[0-9a-f]*: e1 bf 00 00 mfsr pc,0x0
  12224. + *[0-9a-f]*: e1 bc 00 ff mfsr r12,0x3fc
  12225. + *[0-9a-f]*: e1 b5 00 80 mfsr r5,0x200
  12226. + *[0-9a-f]*: e1 b4 00 7f mfsr r4,0x1fc
  12227. + *[0-9a-f]*: e1 be 00 01 mfsr lr,0x4
  12228. + *[0-9a-f]*: e1 b2 00 ae mfsr r2,0x2b8
  12229. + *[0-9a-f]*: e1 b4 00 41 mfsr r4,0x104
  12230. + *[0-9a-f]*: e1 ba 00 fe mfsr r10,0x3f8
  12231. +
  12232. +[0-9a-f]* <mtsr>:
  12233. + *[0-9a-f]*: e3 bf 00 00 mtsr 0x0,pc
  12234. + *[0-9a-f]*: e3 bc 00 ff mtsr 0x3fc,r12
  12235. + *[0-9a-f]*: e3 b5 00 80 mtsr 0x200,r5
  12236. + *[0-9a-f]*: e3 b4 00 7f mtsr 0x1fc,r4
  12237. + *[0-9a-f]*: e3 be 00 01 mtsr 0x4,lr
  12238. + *[0-9a-f]*: e3 ba 00 38 mtsr 0xe0,r10
  12239. + *[0-9a-f]*: e3 bc 00 d1 mtsr 0x344,r12
  12240. + *[0-9a-f]*: e3 b9 00 4c mtsr 0x130,r9
  12241. +
  12242. +[0-9a-f]* <mfdr>:
  12243. + *[0-9a-f]*: e5 bf 00 00 mfdr pc,0x0
  12244. + *[0-9a-f]*: e5 bc 00 ff mfdr r12,0x3fc
  12245. + *[0-9a-f]*: e5 b5 00 80 mfdr r5,0x200
  12246. + *[0-9a-f]*: e5 b4 00 7f mfdr r4,0x1fc
  12247. + *[0-9a-f]*: e5 be 00 01 mfdr lr,0x4
  12248. + *[0-9a-f]*: e5 b6 00 e9 mfdr r6,0x3a4
  12249. + *[0-9a-f]*: e5 b5 00 09 mfdr r5,0x24
  12250. + *[0-9a-f]*: e5 b9 00 4b mfdr r9,0x12c
  12251. +
  12252. +[0-9a-f]* <mtdr>:
  12253. + *[0-9a-f]*: e7 bf 00 00 mtdr 0x0,pc
  12254. + *[0-9a-f]*: e7 bc 00 ff mtdr 0x3fc,r12
  12255. + *[0-9a-f]*: e7 b5 00 80 mtdr 0x200,r5
  12256. + *[0-9a-f]*: e7 b4 00 7f mtdr 0x1fc,r4
  12257. + *[0-9a-f]*: e7 be 00 01 mtdr 0x4,lr
  12258. + *[0-9a-f]*: e7 b8 00 2d mtdr 0xb4,r8
  12259. + *[0-9a-f]*: e7 ba 00 b4 mtdr 0x2d0,r10
  12260. + *[0-9a-f]*: e7 be 00 66 mtdr 0x198,lr
  12261. +
  12262. +[0-9a-f]* <sleep>:
  12263. + *[0-9a-f]*: e9 b0 00 00 sleep 0x0
  12264. + *[0-9a-f]*: e9 b0 00 ff sleep 0xff
  12265. + *[0-9a-f]*: e9 b0 00 80 sleep 0x80
  12266. + *[0-9a-f]*: e9 b0 00 7f sleep 0x7f
  12267. + *[0-9a-f]*: e9 b0 00 01 sleep 0x1
  12268. + *[0-9a-f]*: e9 b0 00 fe sleep 0xfe
  12269. + *[0-9a-f]*: e9 b0 00 0f sleep 0xf
  12270. + *[0-9a-f]*: e9 b0 00 2b sleep 0x2b
  12271. +
  12272. +[0-9a-f]* <sync>:
  12273. + *[0-9a-f]*: eb b0 00 00 sync 0x0
  12274. + *[0-9a-f]*: eb b0 00 ff sync 0xff
  12275. + *[0-9a-f]*: eb b0 00 80 sync 0x80
  12276. + *[0-9a-f]*: eb b0 00 7f sync 0x7f
  12277. + *[0-9a-f]*: eb b0 00 01 sync 0x1
  12278. + *[0-9a-f]*: eb b0 00 a6 sync 0xa6
  12279. + *[0-9a-f]*: eb b0 00 e6 sync 0xe6
  12280. + *[0-9a-f]*: eb b0 00 b4 sync 0xb4
  12281. +
  12282. +[0-9a-f]* <bld>:
  12283. + *[0-9a-f]*: ed bf 00 00 bld pc,0x0
  12284. + *[0-9a-f]*: ed bc 00 1f bld r12,0x1f
  12285. + *[0-9a-f]*: ed b5 00 10 bld r5,0x10
  12286. + *[0-9a-f]*: ed b4 00 0f bld r4,0xf
  12287. + *[0-9a-f]*: ed be 00 01 bld lr,0x1
  12288. + *[0-9a-f]*: ed b9 00 0f bld r9,0xf
  12289. + *[0-9a-f]*: ed b0 00 04 bld r0,0x4
  12290. + *[0-9a-f]*: ed be 00 1a bld lr,0x1a
  12291. +
  12292. +[0-9a-f]* <bst>:
  12293. + *[0-9a-f]*: ef bf 00 00 bst pc,0x0
  12294. + *[0-9a-f]*: ef bc 00 1f bst r12,0x1f
  12295. + *[0-9a-f]*: ef b5 00 10 bst r5,0x10
  12296. + *[0-9a-f]*: ef b4 00 0f bst r4,0xf
  12297. + *[0-9a-f]*: ef be 00 01 bst lr,0x1
  12298. + *[0-9a-f]*: ef ba 00 1c bst r10,0x1c
  12299. + *[0-9a-f]*: ef b0 00 03 bst r0,0x3
  12300. + *[0-9a-f]*: ef bd 00 02 bst sp,0x2
  12301. +
  12302. +[0-9a-f]* <sats>:
  12303. + *[0-9a-f]*: f1 bf 00 00 sats pc,0x0
  12304. + *[0-9a-f]*: f1 bc 03 ff sats r12>>0x1f,0x1f
  12305. + *[0-9a-f]*: f1 b5 02 10 sats r5>>0x10,0x10
  12306. + *[0-9a-f]*: f1 b4 01 ef sats r4>>0xf,0xf
  12307. + *[0-9a-f]*: f1 be 00 21 sats lr>>0x1,0x1
  12308. + *[0-9a-f]*: f1 ba 02 63 sats r10>>0x3,0x13
  12309. + *[0-9a-f]*: f1 ba 03 42 sats r10>>0x2,0x1a
  12310. + *[0-9a-f]*: f1 b1 00 34 sats r1>>0x14,0x1
  12311. +
  12312. +[0-9a-f]* <satu>:
  12313. + *[0-9a-f]*: f1 bf 04 00 satu pc,0x0
  12314. + *[0-9a-f]*: f1 bc 07 ff satu r12>>0x1f,0x1f
  12315. + *[0-9a-f]*: f1 b5 06 10 satu r5>>0x10,0x10
  12316. + *[0-9a-f]*: f1 b4 05 ef satu r4>>0xf,0xf
  12317. + *[0-9a-f]*: f1 be 04 21 satu lr>>0x1,0x1
  12318. + *[0-9a-f]*: f1 bf 04 e5 satu pc>>0x5,0x7
  12319. + *[0-9a-f]*: f1 b7 04 a5 satu r7>>0x5,0x5
  12320. + *[0-9a-f]*: f1 b2 06 7a satu r2>>0x1a,0x13
  12321. +
  12322. +[0-9a-f]* <satrnds>:
  12323. + *[0-9a-f]*: f3 bf 00 00 satrnds pc,0x0
  12324. + *[0-9a-f]*: f3 bc 03 ff satrnds r12>>0x1f,0x1f
  12325. + *[0-9a-f]*: f3 b5 02 10 satrnds r5>>0x10,0x10
  12326. + *[0-9a-f]*: f3 b4 01 ef satrnds r4>>0xf,0xf
  12327. + *[0-9a-f]*: f3 be 00 21 satrnds lr>>0x1,0x1
  12328. + *[0-9a-f]*: f3 b0 02 75 satrnds r0>>0x15,0x13
  12329. + *[0-9a-f]*: f3 bd 00 40 satrnds sp,0x2
  12330. + *[0-9a-f]*: f3 b7 03 a6 satrnds r7>>0x6,0x1d
  12331. +
  12332. +[0-9a-f]* <satrndu>:
  12333. + *[0-9a-f]*: f3 bf 04 00 satrndu pc,0x0
  12334. + *[0-9a-f]*: f3 bc 07 ff satrndu r12>>0x1f,0x1f
  12335. + *[0-9a-f]*: f3 b5 06 10 satrndu r5>>0x10,0x10
  12336. + *[0-9a-f]*: f3 b4 05 ef satrndu r4>>0xf,0xf
  12337. + *[0-9a-f]*: f3 be 04 21 satrndu lr>>0x1,0x1
  12338. + *[0-9a-f]*: f3 bc 07 40 satrndu r12,0x1a
  12339. + *[0-9a-f]*: f3 b4 04 75 satrndu r4>>0x15,0x3
  12340. + *[0-9a-f]*: f3 ba 06 03 satrndu r10>>0x3,0x10
  12341. +
  12342. +[0-9a-f]* <subfc>:
  12343. + *[0-9a-f]*: f5 bf 00 00 subfeq pc,0
  12344. + *[0-9a-f]*: f5 bc 0f ff subfal r12,-1
  12345. + *[0-9a-f]*: f5 b5 08 80 subfls r5,-128
  12346. + *[0-9a-f]*: f5 b4 07 7f subfpl r4,127
  12347. + *[0-9a-f]*: f5 be 01 01 subfne lr,1
  12348. + *[0-9a-f]*: f5 ba 08 08 subfls r10,8
  12349. + *[0-9a-f]*: f5 bb 0d 63 subfvc r11,99
  12350. + *[0-9a-f]*: f5 b2 0c 49 subfvs r2,73
  12351. +
  12352. +[0-9a-f]* <subc>:
  12353. + *[0-9a-f]*: f7 bf 00 00 subeq pc,0
  12354. + *[0-9a-f]*: f7 bc 0f ff subal r12,-1
  12355. + *[0-9a-f]*: f7 b5 08 80 subls r5,-128
  12356. + *[0-9a-f]*: f7 b4 07 7f subpl r4,127
  12357. + *[0-9a-f]*: f7 be 01 01 subne lr,1
  12358. + *[0-9a-f]*: f7 bc 08 76 subls r12,118
  12359. + *[0-9a-f]*: f7 be 0d f4 subvc lr,-12
  12360. + *[0-9a-f]*: f7 b4 06 f3 submi r4,-13
  12361. +
  12362. +[0-9a-f]* <movc2>:
  12363. + *[0-9a-f]*: f9 bf 00 00 moveq pc,0
  12364. + *[0-9a-f]*: f9 bc 0f ff moval r12,-1
  12365. + *[0-9a-f]*: f9 b5 08 80 movls r5,-128
  12366. + *[0-9a-f]*: f9 b4 07 7f movpl r4,127
  12367. + *[0-9a-f]*: f9 be 01 01 movne lr,1
  12368. + *[0-9a-f]*: f9 b3 05 86 movlt r3,-122
  12369. + *[0-9a-f]*: f9 b8 0d 02 movvc r8,2
  12370. + *[0-9a-f]*: f9 b7 01 91 movne r7,-111
  12371. +
  12372. +[0-9a-f]* <cp_b>:
  12373. + *[0-9a-f]*: e0 0f 18 00 cp\.b pc,r0
  12374. + *[0-9a-f]*: fe 00 18 00 cp\.b r0,pc
  12375. + *[0-9a-f]*: f0 07 18 00 cp\.b r7,r8
  12376. + *[0-9a-f]*: ee 08 18 00 cp\.b r8,r7
  12377. +
  12378. +[0-9a-f]* <cp_h>:
  12379. + *[0-9a-f]*: e0 0f 19 00 cp\.h pc,r0
  12380. + *[0-9a-f]*: fe 00 19 00 cp\.h r0,pc
  12381. + *[0-9a-f]*: f0 07 19 00 cp\.h r7,r8
  12382. + *[0-9a-f]*: ee 08 19 00 cp\.h r8,r7
  12383. +
  12384. +[0-9a-f]* <ldm>:
  12385. + *[0-9a-f]*: e1 cf 00 7e ldm pc,r1-r6
  12386. + *[0-9a-f]*: e1 cc ff ff ldm r12,r0-pc
  12387. + *[0-9a-f]*: e1 c5 80 00 ldm r5,pc
  12388. + *[0-9a-f]*: e1 c4 7f ff ldm r4,r0-lr
  12389. + *[0-9a-f]*: e1 ce 00 01 ldm lr,r0
  12390. + *[0-9a-f]*: e1 c9 40 22 ldm r9,r1,r5,lr
  12391. + *[0-9a-f]*: e1 cb 81 ec ldm r11,r2-r3,r5-r8,pc
  12392. + *[0-9a-f]*: e1 c6 a2 09 ldm r6,r0,r3,r9,sp,pc
  12393. +
  12394. +[0-9a-f]* <ldm_pu>:
  12395. + *[0-9a-f]*: e3 cf 03 c0 ldm pc\+\+,r6-r9
  12396. + *[0-9a-f]*: e3 cc ff ff ldm r12\+\+,r0-pc
  12397. + *[0-9a-f]*: e3 c5 80 00 ldm r5\+\+,pc
  12398. + *[0-9a-f]*: e3 c4 7f ff ldm r4\+\+,r0-lr
  12399. + *[0-9a-f]*: e3 ce 00 01 ldm lr\+\+,r0
  12400. + *[0-9a-f]*: e3 cc d5 38 ldm r12\+\+,r3-r5,r8,r10,r12,lr-pc
  12401. + *[0-9a-f]*: e3 ca c0 74 ldm r10\+\+,r2,r4-r6,lr-pc
  12402. + *[0-9a-f]*: e3 c6 7e 1a ldm r6\+\+,r1,r3-r4,r9-lr
  12403. +
  12404. +[0-9a-f]* <ldmts>:
  12405. + *[0-9a-f]*: e5 cf 01 80 ldmts pc,r7-r8
  12406. + *[0-9a-f]*: e5 cc ff ff ldmts r12,r0-pc
  12407. + *[0-9a-f]*: e5 c5 80 00 ldmts r5,pc
  12408. + *[0-9a-f]*: e5 c4 7f ff ldmts r4,r0-lr
  12409. + *[0-9a-f]*: e5 ce 00 01 ldmts lr,r0
  12410. + *[0-9a-f]*: e5 c0 18 06 ldmts r0,r1-r2,r11-r12
  12411. + *[0-9a-f]*: e5 ce 61 97 ldmts lr,r0-r2,r4,r7-r8,sp-lr
  12412. + *[0-9a-f]*: e5 cc c2 3b ldmts r12,r0-r1,r3-r5,r9,lr-pc
  12413. +
  12414. +[0-9a-f]* <ldmts_pu>:
  12415. + *[0-9a-f]*: e7 cf 02 00 ldmts pc\+\+,r9
  12416. + *[0-9a-f]*: e7 cc ff ff ldmts r12\+\+,r0-pc
  12417. + *[0-9a-f]*: e7 c5 80 00 ldmts r5\+\+,pc
  12418. + *[0-9a-f]*: e7 c4 7f ff ldmts r4\+\+,r0-lr
  12419. + *[0-9a-f]*: e7 ce 00 01 ldmts lr\+\+,r0
  12420. + *[0-9a-f]*: e7 cd 0a bd ldmts sp\+\+,r0,r2-r5,r7,r9,r11
  12421. + *[0-9a-f]*: e7 c5 0c 8e ldmts r5\+\+,r1-r3,r7,r10-r11
  12422. + *[0-9a-f]*: e7 c8 a1 9c ldmts r8\+\+,r2-r4,r7-r8,sp,pc
  12423. +
  12424. +[0-9a-f]* <stm>:
  12425. + *[0-9a-f]*: e9 cf 00 80 stm pc,r7
  12426. + *[0-9a-f]*: e9 cc ff ff stm r12,r0-pc
  12427. + *[0-9a-f]*: e9 c5 80 00 stm r5,pc
  12428. + *[0-9a-f]*: e9 c4 7f ff stm r4,r0-lr
  12429. + *[0-9a-f]*: e9 ce 00 01 stm lr,r0
  12430. + *[0-9a-f]*: e9 cd 49 2c stm sp,r2-r3,r5,r8,r11,lr
  12431. + *[0-9a-f]*: e9 c4 4c 5f stm r4,r0-r4,r6,r10-r11,lr
  12432. + *[0-9a-f]*: e9 c9 f2 22 stm r9,r1,r5,r9,r12-pc
  12433. +
  12434. +[0-9a-f]* <stm_pu>:
  12435. + *[0-9a-f]*: eb cf 00 70 stm --pc,r4-r6
  12436. + *[0-9a-f]*: eb cc ff ff stm --r12,r0-pc
  12437. + *[0-9a-f]*: eb c5 80 00 stm --r5,pc
  12438. + *[0-9a-f]*: eb c4 7f ff stm --r4,r0-lr
  12439. + *[0-9a-f]*: eb ce 00 01 stm --lr,r0
  12440. + *[0-9a-f]*: eb cb fb f1 stm --r11,r0,r4-r9,r11-pc
  12441. + *[0-9a-f]*: eb cb 56 09 stm --r11,r0,r3,r9-r10,r12,lr
  12442. + *[0-9a-f]*: eb c6 63 04 stm --r6,r2,r8-r9,sp-lr
  12443. +
  12444. +[0-9a-f]* <stmts>:
  12445. + *[0-9a-f]*: ed cf 01 00 stmts pc,r8
  12446. + *[0-9a-f]*: ed cc ff ff stmts r12,r0-pc
  12447. + *[0-9a-f]*: ed c5 80 00 stmts r5,pc
  12448. + *[0-9a-f]*: ed c4 7f ff stmts r4,r0-lr
  12449. + *[0-9a-f]*: ed ce 00 01 stmts lr,r0
  12450. + *[0-9a-f]*: ed c1 c6 5b stmts r1,r0-r1,r3-r4,r6,r9-r10,lr-pc
  12451. + *[0-9a-f]*: ed c3 1d c1 stmts r3,r0,r6-r8,r10-r12
  12452. + *[0-9a-f]*: ed cb d6 d1 stmts r11,r0,r4,r6-r7,r9-r10,r12,lr-pc
  12453. +
  12454. +[0-9a-f]* <stmts_pu>:
  12455. + *[0-9a-f]*: ef cf 01 c0 stmts --pc,r6-r8
  12456. + *[0-9a-f]*: ef cc ff ff stmts --r12,r0-pc
  12457. + *[0-9a-f]*: ef c5 80 00 stmts --r5,pc
  12458. + *[0-9a-f]*: ef c4 7f ff stmts --r4,r0-lr
  12459. + *[0-9a-f]*: ef ce 00 01 stmts --lr,r0
  12460. + *[0-9a-f]*: ef c2 36 19 stmts --r2,r0,r3-r4,r9-r10,r12-sp
  12461. + *[0-9a-f]*: ef c3 c0 03 stmts --r3,r0-r1,lr-pc
  12462. + *[0-9a-f]*: ef c0 44 7d stmts --r0,r0,r2-r6,r10,lr
  12463. +
  12464. +[0-9a-f]* <ldins_h>:
  12465. + *[0-9a-f]*: ff df 00 00 ldins\.h pc:b,pc\[0\]
  12466. + *[0-9a-f]*: f9 dc 1f ff ldins\.h r12:t,r12\[-2\]
  12467. + *[0-9a-f]*: eb d5 18 00 ldins\.h r5:t,r5\[-4096\]
  12468. + *[0-9a-f]*: e9 d4 07 ff ldins\.h r4:b,r4\[4094\]
  12469. + *[0-9a-f]*: fd de 10 01 ldins\.h lr:t,lr\[2\]
  12470. + *[0-9a-f]*: fd d0 13 c5 ldins\.h r0:t,lr\[1930\]
  12471. + *[0-9a-f]*: ef d3 0e f5 ldins\.h r3:b,r7\[-534\]
  12472. + *[0-9a-f]*: f9 d2 0b 9a ldins\.h r2:b,r12\[-2252\]
  12473. +
  12474. +[0-9a-f]* <ldins_b>:
  12475. + *[0-9a-f]*: ff df 40 00 ldins\.b pc:b,pc\[0\]
  12476. + *[0-9a-f]*: f9 dc 7f ff ldins\.b r12:t,r12\[-1\]
  12477. + *[0-9a-f]*: eb d5 68 00 ldins\.b r5:u,r5\[-2048\]
  12478. + *[0-9a-f]*: e9 d4 57 ff ldins\.b r4:l,r4\[2047\]
  12479. + *[0-9a-f]*: fd de 50 01 ldins\.b lr:l,lr\[1\]
  12480. + *[0-9a-f]*: e9 d6 7d 6a ldins\.b r6:t,r4\[-662\]
  12481. + *[0-9a-f]*: e3 d5 4f 69 ldins\.b r5:b,r1\[-151\]
  12482. + *[0-9a-f]*: f7 da 78 7d ldins\.b r10:t,r11\[-1923\]
  12483. +
  12484. +[0-9a-f]* <ldswp_sh>:
  12485. + *[0-9a-f]*: ff df 20 00 ldswp\.sh pc,pc\[0\]
  12486. + *[0-9a-f]*: f9 dc 2f ff ldswp\.sh r12,r12\[-2\]
  12487. + *[0-9a-f]*: eb d5 28 00 ldswp\.sh r5,r5\[-4096\]
  12488. + *[0-9a-f]*: e9 d4 27 ff ldswp\.sh r4,r4\[4094\]
  12489. + *[0-9a-f]*: fd de 20 01 ldswp\.sh lr,lr\[2\]
  12490. + *[0-9a-f]*: f5 d9 27 84 ldswp\.sh r9,r10\[3848\]
  12491. + *[0-9a-f]*: f9 d4 2c 04 ldswp\.sh r4,r12\[-2040\]
  12492. + *[0-9a-f]*: e5 da 26 08 ldswp\.sh r10,r2\[3088\]
  12493. +
  12494. +[0-9a-f]* <ldswp_uh>:
  12495. + *[0-9a-f]*: ff df 30 00 ldswp\.uh pc,pc\[0\]
  12496. + *[0-9a-f]*: f9 dc 3f ff ldswp\.uh r12,r12\[-2\]
  12497. + *[0-9a-f]*: eb d5 38 00 ldswp\.uh r5,r5\[-4096\]
  12498. + *[0-9a-f]*: e9 d4 37 ff ldswp\.uh r4,r4\[4094\]
  12499. + *[0-9a-f]*: fd de 30 01 ldswp\.uh lr,lr\[2\]
  12500. + *[0-9a-f]*: f3 d4 37 46 ldswp\.uh r4,r9\[3724\]
  12501. + *[0-9a-f]*: fb de 3c bc ldswp\.uh lr,sp\[-1672\]
  12502. + *[0-9a-f]*: f9 d8 38 7d ldswp\.uh r8,r12\[-3846\]
  12503. +
  12504. +[0-9a-f]* <ldswp_w>:
  12505. + *[0-9a-f]*: ff df 80 00 ldswp\.w pc,pc\[0\]
  12506. + *[0-9a-f]*: f9 dc 8f ff ldswp\.w r12,r12\[-4\]
  12507. + *[0-9a-f]*: eb d5 88 00 ldswp\.w r5,r5\[-8192\]
  12508. + *[0-9a-f]*: e9 d4 87 ff ldswp\.w r4,r4\[8188\]
  12509. + *[0-9a-f]*: fd de 80 01 ldswp\.w lr,lr\[4\]
  12510. + *[0-9a-f]*: ef dd 81 d1 ldswp\.w sp,r7\[1860\]
  12511. + *[0-9a-f]*: eb df 8c c1 ldswp\.w pc,r5\[-3324\]
  12512. + *[0-9a-f]*: f5 dc 8c c8 ldswp\.w r12,r10\[-3296\]
  12513. +
  12514. +[0-9a-f]* <stswp_h>:
  12515. + *[0-9a-f]*: ff df 90 00 stswp\.h pc\[0\],pc
  12516. + *[0-9a-f]*: f9 dc 9f ff stswp\.h r12\[-2\],r12
  12517. + *[0-9a-f]*: eb d5 98 00 stswp\.h r5\[-4096\],r5
  12518. + *[0-9a-f]*: e9 d4 97 ff stswp\.h r4\[4094\],r4
  12519. + *[0-9a-f]*: fd de 90 01 stswp\.h lr\[2\],lr
  12520. + *[0-9a-f]*: ef da 90 20 stswp\.h r7\[64\],r10
  12521. + *[0-9a-f]*: f5 d2 95 e8 stswp\.h r10\[3024\],r2
  12522. + *[0-9a-f]*: e1 da 9b 74 stswp\.h r0\[-2328\],r10
  12523. +
  12524. +[0-9a-f]* <stswp_w>:
  12525. + *[0-9a-f]*: ff df a0 00 stswp\.w pc\[0\],pc
  12526. + *[0-9a-f]*: f9 dc af ff stswp\.w r12\[-4\],r12
  12527. + *[0-9a-f]*: eb d5 a8 00 stswp\.w r5\[-8192\],r5
  12528. + *[0-9a-f]*: e9 d4 a7 ff stswp\.w r4\[8188\],r4
  12529. + *[0-9a-f]*: fd de a0 01 stswp\.w lr\[4\],lr
  12530. + *[0-9a-f]*: ff d8 a1 21 stswp\.w pc\[1156\],r8
  12531. + *[0-9a-f]*: fb da a7 ce stswp\.w sp\[7992\],r10
  12532. + *[0-9a-f]*: f1 d5 ae db stswp\.w r8\[-1172\],r5
  12533. +
  12534. +[0-9a-f]* <and2>:
  12535. + *[0-9a-f]*: ff ef 00 0f and pc,pc,pc
  12536. + *[0-9a-f]*: f9 ec 01 fc and r12,r12,r12<<0x1f
  12537. + *[0-9a-f]*: eb e5 01 05 and r5,r5,r5<<0x10
  12538. + *[0-9a-f]*: e9 e4 00 f4 and r4,r4,r4<<0xf
  12539. + *[0-9a-f]*: fd ee 00 1e and lr,lr,lr<<0x1
  12540. + *[0-9a-f]*: e5 e1 00 1a and r10,r2,r1<<0x1
  12541. + *[0-9a-f]*: f1 eb 01 bc and r12,r8,r11<<0x1b
  12542. + *[0-9a-f]*: ef e0 00 3a and r10,r7,r0<<0x3
  12543. +
  12544. +[0-9a-f]* <and3>:
  12545. + *[0-9a-f]*: ff ef 02 0f and pc,pc,pc
  12546. + *[0-9a-f]*: f9 ec 03 fc and r12,r12,r12>>0x1f
  12547. + *[0-9a-f]*: eb e5 03 05 and r5,r5,r5>>0x10
  12548. + *[0-9a-f]*: e9 e4 02 f4 and r4,r4,r4>>0xf
  12549. + *[0-9a-f]*: fd ee 02 1e and lr,lr,lr>>0x1
  12550. + *[0-9a-f]*: f1 e7 03 1c and r12,r8,r7>>0x11
  12551. + *[0-9a-f]*: e9 e9 03 4f and pc,r4,r9>>0x14
  12552. + *[0-9a-f]*: f3 ea 02 ca and r10,r9,r10>>0xc
  12553. +
  12554. +[0-9a-f]* <or2>:
  12555. + *[0-9a-f]*: ff ef 10 0f or pc,pc,pc
  12556. + *[0-9a-f]*: f9 ec 11 fc or r12,r12,r12<<0x1f
  12557. + *[0-9a-f]*: eb e5 11 05 or r5,r5,r5<<0x10
  12558. + *[0-9a-f]*: e9 e4 10 f4 or r4,r4,r4<<0xf
  12559. + *[0-9a-f]*: fd ee 10 1e or lr,lr,lr<<0x1
  12560. + *[0-9a-f]*: fb eb 11 d8 or r8,sp,r11<<0x1d
  12561. + *[0-9a-f]*: f3 e2 11 cf or pc,r9,r2<<0x1c
  12562. + *[0-9a-f]*: e3 e2 10 35 or r5,r1,r2<<0x3
  12563. +
  12564. +[0-9a-f]* <or3>:
  12565. + *[0-9a-f]*: ff ef 12 0f or pc,pc,pc
  12566. + *[0-9a-f]*: f9 ec 13 fc or r12,r12,r12>>0x1f
  12567. + *[0-9a-f]*: eb e5 13 05 or r5,r5,r5>>0x10
  12568. + *[0-9a-f]*: e9 e4 12 f4 or r4,r4,r4>>0xf
  12569. + *[0-9a-f]*: fd ee 12 1e or lr,lr,lr>>0x1
  12570. + *[0-9a-f]*: fb ed 12 21 or r1,sp,sp>>0x2
  12571. + *[0-9a-f]*: e3 e1 13 d0 or r0,r1,r1>>0x1d
  12572. + *[0-9a-f]*: f9 e8 12 84 or r4,r12,r8>>0x8
  12573. +
  12574. +[0-9a-f]* <eor2>:
  12575. + *[0-9a-f]*: ff ef 20 0f eor pc,pc,pc
  12576. + *[0-9a-f]*: f9 ec 21 fc eor r12,r12,r12<<0x1f
  12577. + *[0-9a-f]*: eb e5 21 05 eor r5,r5,r5<<0x10
  12578. + *[0-9a-f]*: e9 e4 20 f4 eor r4,r4,r4<<0xf
  12579. + *[0-9a-f]*: fd ee 20 1e eor lr,lr,lr<<0x1
  12580. + *[0-9a-f]*: f3 e4 20 ba eor r10,r9,r4<<0xb
  12581. + *[0-9a-f]*: e1 e1 21 f4 eor r4,r0,r1<<0x1f
  12582. + *[0-9a-f]*: e5 ec 20 d6 eor r6,r2,r12<<0xd
  12583. +
  12584. +[0-9a-f]* <eor3>:
  12585. + *[0-9a-f]*: ff ef 22 0f eor pc,pc,pc
  12586. + *[0-9a-f]*: f9 ec 23 fc eor r12,r12,r12>>0x1f
  12587. + *[0-9a-f]*: eb e5 23 05 eor r5,r5,r5>>0x10
  12588. + *[0-9a-f]*: e9 e4 22 f4 eor r4,r4,r4>>0xf
  12589. + *[0-9a-f]*: fd ee 22 1e eor lr,lr,lr>>0x1
  12590. + *[0-9a-f]*: eb e5 23 65 eor r5,r5,r5>>0x16
  12591. + *[0-9a-f]*: e3 ee 22 3a eor r10,r1,lr>>0x3
  12592. + *[0-9a-f]*: fd ed 23 a7 eor r7,lr,sp>>0x1a
  12593. +
  12594. +[0-9a-f]* <sthh_w2>:
  12595. + *[0-9a-f]*: ff ef 8f 0f sthh\.w pc\[pc\],pc:b,pc:b
  12596. + *[0-9a-f]*: f9 ec bc 3c sthh\.w r12\[r12<<0x3\],r12:t,r12:t
  12597. + *[0-9a-f]*: eb e5 b5 25 sthh\.w r5\[r5<<0x2\],r5:t,r5:t
  12598. + *[0-9a-f]*: e9 e4 84 14 sthh\.w r4\[r4<<0x1\],r4:b,r4:b
  12599. + *[0-9a-f]*: fd ee be 1e sthh\.w lr\[lr<<0x1\],lr:t,lr:t
  12600. + *[0-9a-f]*: e3 ec b6 3d sthh\.w sp\[r6<<0x3\],r1:t,r12:t
  12601. + *[0-9a-f]*: f3 e9 b6 06 sthh\.w r6\[r6\],r9:t,r9:t
  12602. + *[0-9a-f]*: e1 eb 93 0a sthh\.w r10\[r3\],r0:b,r11:t
  12603. +
  12604. +[0-9a-f]* <sthh_w1>:
  12605. + *[0-9a-f]*: ff ef c0 0f sthh\.w pc\[0x0\],pc:b,pc:b
  12606. + *[0-9a-f]*: f9 ec ff fc sthh\.w r12\[0x3fc\],r12:t,r12:t
  12607. + *[0-9a-f]*: eb e5 f8 05 sthh\.w r5\[0x200\],r5:t,r5:t
  12608. + *[0-9a-f]*: e9 e4 c7 f4 sthh\.w r4\[0x1fc\],r4:b,r4:b
  12609. + *[0-9a-f]*: fd ee f0 1e sthh\.w lr\[0x4\],lr:t,lr:t
  12610. + *[0-9a-f]*: f3 e0 e6 54 sthh\.w r4\[0x194\],r9:t,r0:b
  12611. + *[0-9a-f]*: e5 ea e5 78 sthh\.w r8\[0x15c\],r2:t,r10:b
  12612. + *[0-9a-f]*: f3 e2 c2 bd sthh\.w sp\[0xac\],r9:b,r2:b
  12613. +
  12614. +[0-9a-f]* <cop>:
  12615. + *[0-9a-f]*: e1 a0 00 00 cop cp0,cr0,cr0,cr0,0x0
  12616. + *[0-9a-f]*: e7 af ff ff cop cp7,cr15,cr15,cr15,0x7f
  12617. + *[0-9a-f]*: e3 a8 75 55 cop cp3,cr5,cr5,cr5,0x31
  12618. + *[0-9a-f]*: e3 a8 44 44 cop cp2,cr4,cr4,cr4,0x30
  12619. + *[0-9a-f]*: e5 ad a8 37 cop cp5,cr8,cr3,cr7,0x5a
  12620. +
  12621. +[0-9a-f]* <ldc_w1>:
  12622. + *[0-9a-f]*: e9 a0 00 00 ldc\.w cp0,cr0,r0\[0x0\]
  12623. + *[0-9a-f]*: e9 af ef ff ldc\.w cp7,cr15,pc\[0x3fc\]
  12624. + *[0-9a-f]*: e9 a5 65 80 ldc\.w cp3,cr5,r5\[0x200\]
  12625. + *[0-9a-f]*: e9 a4 44 7f ldc\.w cp2,cr4,r4\[0x1fc\]
  12626. + *[0-9a-f]*: e9 ad 89 24 ldc\.w cp4,cr9,sp\[0x90\]
  12627. +
  12628. +[0-9a-f]* <ldc_w2>:
  12629. + *[0-9a-f]*: ef a0 00 40 ldc\.w cp0,cr0,--r0
  12630. + *[0-9a-f]*: ef af ef 40 ldc\.w cp7,cr15,--pc
  12631. + *[0-9a-f]*: ef a5 65 40 ldc\.w cp3,cr5,--r5
  12632. + *[0-9a-f]*: ef a4 44 40 ldc\.w cp2,cr4,--r4
  12633. + *[0-9a-f]*: ef ad 89 40 ldc\.w cp4,cr9,--sp
  12634. +
  12635. +[0-9a-f]* <ldc_w3>:
  12636. + *[0-9a-f]*: ef a0 10 00 ldc\.w cp0,cr0,r0\[r0\]
  12637. + *[0-9a-f]*: ef af ff 3f ldc\.w cp7,cr15,pc\[pc<<0x3\]
  12638. + *[0-9a-f]*: ef a5 75 24 ldc\.w cp3,cr5,r5\[r4<<0x2\]
  12639. + *[0-9a-f]*: ef a4 54 13 ldc\.w cp2,cr4,r4\[r3<<0x1\]
  12640. + *[0-9a-f]*: ef ad 99 0c ldc\.w cp4,cr9,sp\[r12\]
  12641. +
  12642. +[0-9a-f]* <ldc_d1>:
  12643. + *[0-9a-f]*: e9 a0 10 00 ldc\.d cp0,cr0,r0\[0x0\]
  12644. + *[0-9a-f]*: e9 af fe ff ldc\.d cp7,cr14,pc\[0x3fc\]
  12645. + *[0-9a-f]*: e9 a5 76 80 ldc\.d cp3,cr6,r5\[0x200\]
  12646. + *[0-9a-f]*: e9 a4 54 7f ldc\.d cp2,cr4,r4\[0x1fc\]
  12647. + *[0-9a-f]*: e9 ad 98 24 ldc\.d cp4,cr8,sp\[0x90\]
  12648. +
  12649. +[0-9a-f]* <ldc_d2>:
  12650. + *[0-9a-f]*: ef a0 00 50 ldc\.d cp0,cr0,--r0
  12651. + *[0-9a-f]*: ef af ee 50 ldc\.d cp7,cr14,--pc
  12652. + *[0-9a-f]*: ef a5 66 50 ldc\.d cp3,cr6,--r5
  12653. + *[0-9a-f]*: ef a4 44 50 ldc\.d cp2,cr4,--r4
  12654. + *[0-9a-f]*: ef ad 88 50 ldc\.d cp4,cr8,--sp
  12655. +
  12656. +[0-9a-f]* <ldc_d3>:
  12657. + *[0-9a-f]*: ef a0 10 40 ldc\.d cp0,cr0,r0\[r0\]
  12658. + *[0-9a-f]*: ef af fe 7f ldc\.d cp7,cr14,pc\[pc<<0x3\]
  12659. + *[0-9a-f]*: ef a5 76 64 ldc\.d cp3,cr6,r5\[r4<<0x2\]
  12660. + *[0-9a-f]*: ef a4 54 53 ldc\.d cp2,cr4,r4\[r3<<0x1\]
  12661. + *[0-9a-f]*: ef ad 98 4c ldc\.d cp4,cr8,sp\[r12\]
  12662. +
  12663. +[0-9a-f]* <stc_w1>:
  12664. + *[0-9a-f]*: eb a0 00 00 stc\.w cp0,r0\[0x0\],cr0
  12665. + *[0-9a-f]*: eb af ef ff stc\.w cp7,pc\[0x3fc\],cr15
  12666. + *[0-9a-f]*: eb a5 65 80 stc\.w cp3,r5\[0x200\],cr5
  12667. + *[0-9a-f]*: eb a4 44 7f stc\.w cp2,r4\[0x1fc\],cr4
  12668. + *[0-9a-f]*: eb ad 89 24 stc\.w cp4,sp\[0x90\],cr9
  12669. +
  12670. +[0-9a-f]* <stc_w2>:
  12671. + *[0-9a-f]*: ef a0 00 60 stc\.w cp0,r0\+\+,cr0
  12672. + *[0-9a-f]*: ef af ef 60 stc\.w cp7,pc\+\+,cr15
  12673. + *[0-9a-f]*: ef a5 65 60 stc\.w cp3,r5\+\+,cr5
  12674. + *[0-9a-f]*: ef a4 44 60 stc\.w cp2,r4\+\+,cr4
  12675. + *[0-9a-f]*: ef ad 89 60 stc\.w cp4,sp\+\+,cr9
  12676. +
  12677. +[0-9a-f]* <stc_w3>:
  12678. + *[0-9a-f]*: ef a0 10 80 stc\.w cp0,r0\[r0\],cr0
  12679. + *[0-9a-f]*: ef af ff bf stc\.w cp7,pc\[pc<<0x3\],cr15
  12680. + *[0-9a-f]*: ef a5 75 a4 stc\.w cp3,r5\[r4<<0x2\],cr5
  12681. + *[0-9a-f]*: ef a4 54 93 stc\.w cp2,r4\[r3<<0x1\],cr4
  12682. + *[0-9a-f]*: ef ad 99 8c stc\.w cp4,sp\[r12\],cr9
  12683. +
  12684. +[0-9a-f]* <stc_d1>:
  12685. + *[0-9a-f]*: eb a0 10 00 stc\.d cp0,r0\[0x0\],cr0
  12686. + *[0-9a-f]*: eb af fe ff stc\.d cp7,pc\[0x3fc\],cr14
  12687. + *[0-9a-f]*: eb a5 76 80 stc\.d cp3,r5\[0x200\],cr6
  12688. + *[0-9a-f]*: eb a4 54 7f stc\.d cp2,r4\[0x1fc\],cr4
  12689. + *[0-9a-f]*: eb ad 98 24 stc\.d cp4,sp\[0x90\],cr8
  12690. +
  12691. +[0-9a-f]* <stc_d2>:
  12692. + *[0-9a-f]*: ef a0 00 70 stc\.d cp0,r0\+\+,cr0
  12693. + *[0-9a-f]*: ef af ee 70 stc\.d cp7,pc\+\+,cr14
  12694. + *[0-9a-f]*: ef a5 66 70 stc\.d cp3,r5\+\+,cr6
  12695. + *[0-9a-f]*: ef a4 44 70 stc\.d cp2,r4\+\+,cr4
  12696. + *[0-9a-f]*: ef ad 88 70 stc\.d cp4,sp\+\+,cr8
  12697. +
  12698. +[0-9a-f]* <stc_d3>:
  12699. + *[0-9a-f]*: ef a0 10 c0 stc\.d cp0,r0\[r0\],cr0
  12700. + *[0-9a-f]*: ef af fe ff stc\.d cp7,pc\[pc<<0x3\],cr14
  12701. + *[0-9a-f]*: ef a5 76 e4 stc\.d cp3,r5\[r4<<0x2\],cr6
  12702. + *[0-9a-f]*: ef a4 54 d3 stc\.d cp2,r4\[r3<<0x1\],cr4
  12703. + *[0-9a-f]*: ef ad 98 cc stc\.d cp4,sp\[r12\],cr8
  12704. +
  12705. +[0-9a-f]* <ldc0_w>:
  12706. + *[0-9a-f]*: f1 a0 00 00 ldc0\.w cr0,r0\[0x0\]
  12707. + *[0-9a-f]*: f1 af ff ff ldc0\.w cr15,pc\[0x3ffc\]
  12708. + *[0-9a-f]*: f1 a5 85 00 ldc0\.w cr5,r5\[0x2000\]
  12709. + *[0-9a-f]*: f1 a4 74 ff ldc0\.w cr4,r4\[0x1ffc\]
  12710. + *[0-9a-f]*: f1 ad 09 93 ldc0\.w cr9,sp\[0x24c\]
  12711. +
  12712. +[0-9a-f]* <ldc0_d>:
  12713. + *[0-9a-f]*: f3 a0 00 00 ldc0\.d cr0,r0\[0x0\]
  12714. + *[0-9a-f]*: f3 af fe ff ldc0\.d cr14,pc\[0x3ffc\]
  12715. + *[0-9a-f]*: f3 a5 86 00 ldc0\.d cr6,r5\[0x2000\]
  12716. + *[0-9a-f]*: f3 a4 74 ff ldc0\.d cr4,r4\[0x1ffc\]
  12717. + *[0-9a-f]*: f3 ad 08 93 ldc0\.d cr8,sp\[0x24c\]
  12718. +
  12719. +[0-9a-f]* <stc0_w>:
  12720. + *[0-9a-f]*: f5 a0 00 00 stc0\.w r0\[0x0\],cr0
  12721. + *[0-9a-f]*: f5 af ff ff stc0\.w pc\[0x3ffc\],cr15
  12722. + *[0-9a-f]*: f5 a5 85 00 stc0\.w r5\[0x2000\],cr5
  12723. + *[0-9a-f]*: f5 a4 74 ff stc0\.w r4\[0x1ffc\],cr4
  12724. + *[0-9a-f]*: f5 ad 09 93 stc0\.w sp\[0x24c\],cr9
  12725. +
  12726. +[0-9a-f]* <stc0_d>:
  12727. + *[0-9a-f]*: f7 a0 00 00 stc0\.d r0\[0x0\],cr0
  12728. + *[0-9a-f]*: f7 af fe ff stc0\.d pc\[0x3ffc\],cr14
  12729. + *[0-9a-f]*: f7 a5 86 00 stc0\.d r5\[0x2000\],cr6
  12730. + *[0-9a-f]*: f7 a4 74 ff stc0\.d r4\[0x1ffc\],cr4
  12731. + *[0-9a-f]*: f7 ad 08 93 stc0\.d sp\[0x24c\],cr8
  12732. +
  12733. +[0-9a-f]* <memc>:
  12734. + *[0-9a-f]*: f6 10 00 00 memc 0,0x0
  12735. + *[0-9a-f]*: f6 1f ff ff memc -4,0x1f
  12736. + *[0-9a-f]*: f6 18 40 00 memc -65536,0x10
  12737. + *[0-9a-f]*: f6 17 bf ff memc 65532,0xf
  12738. +
  12739. +[0-9a-f]* <mems>:
  12740. + *[0-9a-f]*: f8 10 00 00 mems 0,0x0
  12741. + *[0-9a-f]*: f8 1f ff ff mems -4,0x1f
  12742. + *[0-9a-f]*: f8 18 40 00 mems -65536,0x10
  12743. + *[0-9a-f]*: f8 17 bf ff mems 65532,0xf
  12744. +
  12745. +[0-9a-f]* <memt>:
  12746. + *[0-9a-f]*: fa 10 00 00 memt 0,0x0
  12747. + *[0-9a-f]*: fa 1f ff ff memt -4,0x1f
  12748. + *[0-9a-f]*: fa 18 40 00 memt -65536,0x10
  12749. + *[0-9a-f]*: fa 17 bf ff memt 65532,0xf
  12750. +
  12751. +[0-9a-f]* <stcond>:
  12752. + *[0-9a-f]*: e1 70 00 00 stcond r0\[0\],r0
  12753. + *[0-9a-f]*: ff 7f ff ff stcond pc\[-1\],pc
  12754. + *[0-9a-f]*: f1 77 80 00 stcond r8\[-32768\],r7
  12755. + *[0-9a-f]*: ef 78 7f ff stcond r7\[32767\],r8
  12756. + *[0-9a-f]*: eb 7a 12 34 stcond r5\[4660\],r10
  12757. +
  12758. +[0-9a-f]* <ldcm_w>:
  12759. + *[0-9a-f]*: ed af 00 ff ldcm\.w cp0,pc,cr0-cr7
  12760. + *[0-9a-f]*: ed a0 e0 01 ldcm\.w cp7,r0,cr0
  12761. + *[0-9a-f]*: ed a4 90 7f ldcm\.w cp4,r4\+\+,cr0-cr6
  12762. + *[0-9a-f]*: ed a7 60 80 ldcm\.w cp3,r7,cr7
  12763. + *[0-9a-f]*: ed ac 30 72 ldcm\.w cp1,r12\+\+,cr1,cr4-cr6
  12764. + *[0-9a-f]*: ed af 01 ff ldcm\.w cp0,pc,cr8-cr15
  12765. + *[0-9a-f]*: ed a0 e1 01 ldcm\.w cp7,r0,cr8
  12766. + *[0-9a-f]*: ed a4 91 7f ldcm\.w cp4,r4\+\+,cr8-cr14
  12767. + *[0-9a-f]*: ed a7 61 80 ldcm\.w cp3,r7,cr15
  12768. + *[0-9a-f]*: ed ac 31 72 ldcm\.w cp1,r12\+\+,cr9,cr12-cr14
  12769. +
  12770. +[0-9a-f]* <ldcm_d>:
  12771. + *[0-9a-f]*: ed af 04 ff ldcm\.d cp0,pc,cr0-cr15
  12772. + *[0-9a-f]*: ed a0 e4 01 ldcm\.d cp7,r0,cr0-cr1
  12773. + *[0-9a-f]*: ed a4 94 7f ldcm\.d cp4,r4\+\+,cr0-cr13
  12774. + *[0-9a-f]*: ed a7 64 80 ldcm\.d cp3,r7,cr14-cr15
  12775. + *[0-9a-f]*: ed ac 54 93 ldcm\.d cp2,r12\+\+,cr0-cr3,cr8-cr9,cr14-cr15
  12776. +
  12777. +[0-9a-f]* <stcm_w>:
  12778. + *[0-9a-f]*: ed af 02 ff stcm\.w cp0,pc,cr0-cr7
  12779. + *[0-9a-f]*: ed a0 e2 01 stcm\.w cp7,r0,cr0
  12780. + *[0-9a-f]*: ed a4 92 7f stcm\.w cp4,--r4,cr0-cr6
  12781. + *[0-9a-f]*: ed a7 62 80 stcm\.w cp3,r7,cr7
  12782. + *[0-9a-f]*: ed ac 32 72 stcm\.w cp1,--r12,cr1,cr4-cr6
  12783. + *[0-9a-f]*: ed af 03 ff stcm\.w cp0,pc,cr8-cr15
  12784. + *[0-9a-f]*: ed a0 e3 01 stcm\.w cp7,r0,cr8
  12785. + *[0-9a-f]*: ed a4 93 7f stcm\.w cp4,--r4,cr8-cr14
  12786. + *[0-9a-f]*: ed a7 63 80 stcm\.w cp3,r7,cr15
  12787. + *[0-9a-f]*: ed ac 33 72 stcm\.w cp1,--r12,cr9,cr12-cr14
  12788. +
  12789. +[0-9a-f]* <stcm_d>:
  12790. + *[0-9a-f]*: ed af 05 ff stcm\.d cp0,pc,cr0-cr15
  12791. + *[0-9a-f]*: ed a0 e5 01 stcm\.d cp7,r0,cr0-cr1
  12792. + *[0-9a-f]*: ed a4 95 7f stcm\.d cp4,--r4,cr0-cr13
  12793. + *[0-9a-f]*: ed a7 65 80 stcm\.d cp3,r7,cr14-cr15
  12794. + *[0-9a-f]*: ed ac 55 93 stcm\.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
  12795. +
  12796. +[0-9a-f]* <mvcr_w>:
  12797. + *[0-9a-f]*: ef af ef 00 mvcr\.w cp7,pc,cr15
  12798. + *[0-9a-f]*: ef a0 00 00 mvcr\.w cp0,r0,cr0
  12799. + *[0-9a-f]*: ef af 0f 00 mvcr\.w cp0,pc,cr15
  12800. + *[0-9a-f]*: ef a0 ef 00 mvcr\.w cp7,r0,cr15
  12801. + *[0-9a-f]*: ef af e0 00 mvcr\.w cp7,pc,cr0
  12802. + *[0-9a-f]*: ef a7 88 00 mvcr\.w cp4,r7,cr8
  12803. + *[0-9a-f]*: ef a8 67 00 mvcr\.w cp3,r8,cr7
  12804. +
  12805. +[0-9a-f]* <mvcr_d>:
  12806. + *[0-9a-f]*: ef ae ee 10 mvcr\.d cp7,lr,cr14
  12807. + *[0-9a-f]*: ef a0 00 10 mvcr\.d cp0,r0,cr0
  12808. + *[0-9a-f]*: ef ae 0e 10 mvcr\.d cp0,lr,cr14
  12809. + *[0-9a-f]*: ef a0 ee 10 mvcr\.d cp7,r0,cr14
  12810. + *[0-9a-f]*: ef ae e0 10 mvcr\.d cp7,lr,cr0
  12811. + *[0-9a-f]*: ef a6 88 10 mvcr\.d cp4,r6,cr8
  12812. + *[0-9a-f]*: ef a8 66 10 mvcr\.d cp3,r8,cr6
  12813. +
  12814. +[0-9a-f]* <mvrc_w>:
  12815. + *[0-9a-f]*: ef af ef 20 mvrc\.w cp7,cr15,pc
  12816. + *[0-9a-f]*: ef a0 00 20 mvrc\.w cp0,cr0,r0
  12817. + *[0-9a-f]*: ef af 0f 20 mvrc\.w cp0,cr15,pc
  12818. + *[0-9a-f]*: ef a0 ef 20 mvrc\.w cp7,cr15,r0
  12819. + *[0-9a-f]*: ef af e0 20 mvrc\.w cp7,cr0,pc
  12820. + *[0-9a-f]*: ef a7 88 20 mvrc\.w cp4,cr8,r7
  12821. + *[0-9a-f]*: ef a8 67 20 mvrc\.w cp3,cr7,r8
  12822. +
  12823. +[0-9a-f]* <mvrc_d>:
  12824. + *[0-9a-f]*: ef ae ee 30 mvrc\.d cp7,cr14,lr
  12825. + *[0-9a-f]*: ef a0 00 30 mvrc\.d cp0,cr0,r0
  12826. + *[0-9a-f]*: ef ae 0e 30 mvrc\.d cp0,cr14,lr
  12827. + *[0-9a-f]*: ef a0 ee 30 mvrc\.d cp7,cr14,r0
  12828. + *[0-9a-f]*: ef ae e0 30 mvrc\.d cp7,cr0,lr
  12829. + *[0-9a-f]*: ef a6 88 30 mvrc\.d cp4,cr8,r6
  12830. + *[0-9a-f]*: ef a8 66 30 mvrc\.d cp3,cr6,r8
  12831. +
  12832. +[0-9a-f]* <bfexts>:
  12833. + *[0-9a-f]*: ff df b3 ff bfexts pc,pc,0x1f,0x1f
  12834. + *[0-9a-f]*: e1 d0 b0 00 bfexts r0,r0,0x0,0x0
  12835. + *[0-9a-f]*: e1 df b3 ff bfexts r0,pc,0x1f,0x1f
  12836. + *[0-9a-f]*: ff d0 b3 ff bfexts pc,r0,0x1f,0x1f
  12837. + *[0-9a-f]*: ff df b0 1f bfexts pc,pc,0x0,0x1f
  12838. + *[0-9a-f]*: ff df b3 e0 bfexts pc,pc,0x1f,0x0
  12839. + *[0-9a-f]*: ef d8 b1 f0 bfexts r7,r8,0xf,0x10
  12840. + *[0-9a-f]*: f1 d7 b2 0f bfexts r8,r7,0x10,0xf
  12841. +
  12842. +[0-9a-f]* <bfextu>:
  12843. + *[0-9a-f]*: ff df c3 ff bfextu pc,pc,0x1f,0x1f
  12844. + *[0-9a-f]*: e1 d0 c0 00 bfextu r0,r0,0x0,0x0
  12845. + *[0-9a-f]*: e1 df c3 ff bfextu r0,pc,0x1f,0x1f
  12846. + *[0-9a-f]*: ff d0 c3 ff bfextu pc,r0,0x1f,0x1f
  12847. + *[0-9a-f]*: ff df c0 1f bfextu pc,pc,0x0,0x1f
  12848. + *[0-9a-f]*: ff df c3 e0 bfextu pc,pc,0x1f,0x0
  12849. + *[0-9a-f]*: ef d8 c1 f0 bfextu r7,r8,0xf,0x10
  12850. + *[0-9a-f]*: f1 d7 c2 0f bfextu r8,r7,0x10,0xf
  12851. +
  12852. +[0-9a-f]* <bfins>:
  12853. + *[0-9a-f]*: ff df d3 ff bfins pc,pc,0x1f,0x1f
  12854. + *[0-9a-f]*: e1 d0 d0 00 bfins r0,r0,0x0,0x0
  12855. + *[0-9a-f]*: e1 df d3 ff bfins r0,pc,0x1f,0x1f
  12856. + *[0-9a-f]*: ff d0 d3 ff bfins pc,r0,0x1f,0x1f
  12857. + *[0-9a-f]*: ff df d0 1f bfins pc,pc,0x0,0x1f
  12858. + *[0-9a-f]*: ff df d3 e0 bfins pc,pc,0x1f,0x0
  12859. + *[0-9a-f]*: ef d8 d1 f0 bfins r7,r8,0xf,0x10
  12860. + *[0-9a-f]*: f1 d7 d2 0f bfins r8,r7,0x10,0xf
  12861. +
  12862. +[0-9a-f]* <rsubc>:
  12863. + *[0-9a-f]*: fb bf 00 00 rsubeq pc,0
  12864. + *[0-9a-f]*: fb bc 0f ff rsubal r12,-1
  12865. + *[0-9a-f]*: fb b5 08 80 rsubls r5,-128
  12866. + *[0-9a-f]*: fb b4 07 7f rsubpl r4,127
  12867. + *[0-9a-f]*: fb be 01 01 rsubne lr,1
  12868. + *[0-9a-f]*: fb bc 08 76 rsubls r12,118
  12869. + *[0-9a-f]*: fb be 0d f4 rsubvc lr,-12
  12870. + *[0-9a-f]*: fb b4 06 f3 rsubmi r4,-13
  12871. +
  12872. +[0-9a-f]* <addc>:
  12873. + *[0-9a-f]*: ff df e0 0f addeq pc,pc,pc
  12874. + *[0-9a-f]*: f9 dc ef 0c addal r12,r12,r12
  12875. + *[0-9a-f]*: eb d5 e8 05 addls r5,r5,r5
  12876. + *[0-9a-f]*: e9 d4 e7 04 addpl r4,r4,r4
  12877. + *[0-9a-f]*: fd de e1 0e addne lr,lr,lr
  12878. + *[0-9a-f]*: e5 d1 e8 0a addls r10,r2,r1
  12879. + *[0-9a-f]*: f1 db ed 0c addvc r12,r8,r11
  12880. + *[0-9a-f]*: ef d0 e6 0a addmi r10,r7,r0
  12881. +
  12882. +[0-9a-f]* <subc2>:
  12883. + *[0-9a-f]*: ff df e0 1f subeq pc,pc,pc
  12884. + *[0-9a-f]*: f9 dc ef 1c subal r12,r12,r12
  12885. + *[0-9a-f]*: eb d5 e8 15 subls r5,r5,r5
  12886. + *[0-9a-f]*: e9 d4 e7 14 subpl r4,r4,r4
  12887. + *[0-9a-f]*: fd de e1 1e subne lr,lr,lr
  12888. + *[0-9a-f]*: e5 d1 e8 1a subls r10,r2,r1
  12889. + *[0-9a-f]*: f1 db ed 1c subvc r12,r8,r11
  12890. + *[0-9a-f]*: ef d0 e6 1a submi r10,r7,r0
  12891. +
  12892. +[0-9a-f]* <andc>:
  12893. + *[0-9a-f]*: ff df e0 2f andeq pc,pc,pc
  12894. + *[0-9a-f]*: f9 dc ef 2c andal r12,r12,r12
  12895. + *[0-9a-f]*: eb d5 e8 25 andls r5,r5,r5
  12896. + *[0-9a-f]*: e9 d4 e7 24 andpl r4,r4,r4
  12897. + *[0-9a-f]*: fd de e1 2e andne lr,lr,lr
  12898. + *[0-9a-f]*: e5 d1 e8 2a andls r10,r2,r1
  12899. + *[0-9a-f]*: f1 db ed 2c andvc r12,r8,r11
  12900. + *[0-9a-f]*: ef d0 e6 2a andmi r10,r7,r0
  12901. +
  12902. +[0-9a-f]* <orc>:
  12903. + *[0-9a-f]*: ff df e0 3f oreq pc,pc,pc
  12904. + *[0-9a-f]*: f9 dc ef 3c oral r12,r12,r12
  12905. + *[0-9a-f]*: eb d5 e8 35 orls r5,r5,r5
  12906. + *[0-9a-f]*: e9 d4 e7 34 orpl r4,r4,r4
  12907. + *[0-9a-f]*: fd de e1 3e orne lr,lr,lr
  12908. + *[0-9a-f]*: e5 d1 e8 3a orls r10,r2,r1
  12909. + *[0-9a-f]*: f1 db ed 3c orvc r12,r8,r11
  12910. + *[0-9a-f]*: ef d0 e6 3a ormi r10,r7,r0
  12911. +
  12912. +[0-9a-f]* <eorc>:
  12913. + *[0-9a-f]*: ff df e0 4f eoreq pc,pc,pc
  12914. + *[0-9a-f]*: f9 dc ef 4c eoral r12,r12,r12
  12915. + *[0-9a-f]*: eb d5 e8 45 eorls r5,r5,r5
  12916. + *[0-9a-f]*: e9 d4 e7 44 eorpl r4,r4,r4
  12917. + *[0-9a-f]*: fd de e1 4e eorne lr,lr,lr
  12918. + *[0-9a-f]*: e5 d1 e8 4a eorls r10,r2,r1
  12919. + *[0-9a-f]*: f1 db ed 4c eorvc r12,r8,r11
  12920. + *[0-9a-f]*: ef d0 e6 4a eormi r10,r7,r0
  12921. +
  12922. +[0-9a-f]* <ldcond>:
  12923. + *[0-9a-f]*: ff ff 01 ff ld.weq pc,pc[0x7fc]
  12924. + *[0-9a-f]*: f9 fc f3 ff ld.shal r12,r12[0x3fe]
  12925. + *[0-9a-f]*: eb f5 84 00 ld.shls r5,r5[0x0]
  12926. + *[0-9a-f]*: e9 f4 79 ff ld.ubpl r4,r4[0x1ff]
  12927. + *[0-9a-f]*: fd fe 16 00 ld.sbne lr,lr[0x0]
  12928. + *[0-9a-f]*: e5 fa 80 00 ld.wls r10,r2[0x0]
  12929. + *[0-9a-f]*: f1 fc d3 ff ld.shvc r12,r8[0x3fe]
  12930. + *[0-9a-f]*: ef fa 68 01 ld.ubmi r10,r7[0x1]
  12931. +
  12932. +[0-9a-f]* <stcond2>:
  12933. + *[0-9a-f]*: ff ff 0b ff st.weq pc[0x7fc],pc
  12934. + *[0-9a-f]*: f9 fc fd ff st.hal r12[0x3fe],r12
  12935. + *[0-9a-f]*: eb f5 8c 00 st.hls r5[0x0],r5
  12936. + *[0-9a-f]*: e9 f4 7f ff st.bpl r4[0x1ff],r4
  12937. + *[0-9a-f]*: fd fe 1e 00 st.bne lr[0x0],lr
  12938. + *[0-9a-f]*: e5 fa 8a 00 st.wls r2[0x0],r10
  12939. + *[0-9a-f]*: f1 fc dd ff st.hvc r8[0x3fe],r12
  12940. + *[0-9a-f]*: ef fa 6e 01 st.bmi r7[0x1],r10
  12941. +
  12942. +[0-9a-f]* <movh>:
  12943. + *[0-9a-f]*: fc 1f ff ff movh pc,0xffff
  12944. + *[0-9a-f]*: fc 10 00 00 movh r0,0x0
  12945. + *[0-9a-f]*: fc 15 00 01 movh r5,0x1
  12946. + *[0-9a-f]*: fc 1c 7f ff movh r12,0x7fff
  12947. +
  12948. --- /dev/null
  12949. +++ b/gas/testsuite/gas/avr32/allinsn.exp
  12950. @@ -0,0 +1,5 @@
  12951. +# AVR32 assembler testsuite. -*- Tcl -*-
  12952. +
  12953. +if [istarget avr32-*-*] {
  12954. + run_dump_test "allinsn"
  12955. +}
  12956. --- /dev/null
  12957. +++ b/gas/testsuite/gas/avr32/allinsn.s
  12958. @@ -0,0 +1,3330 @@
  12959. + .data
  12960. +foodata: .word 42
  12961. + .text
  12962. +footext:
  12963. + .text
  12964. + .global ld_d5
  12965. +ld_d5:
  12966. + ld.d lr,pc[pc<<3]
  12967. + ld.d r0,r0[r0<<0]
  12968. + ld.d r6,r5[r5<<2]
  12969. + ld.d r4,r4[r4<<1]
  12970. + ld.d lr,lr[lr<<1]
  12971. + ld.d r10,r3[sp<<2]
  12972. + ld.d r8,r10[r6<<2]
  12973. + ld.d r2,r7[r9<<0]
  12974. + .text
  12975. + .global ld_w5
  12976. +ld_w5:
  12977. + ld.w pc,pc[pc<<0]
  12978. + ld.w r12,r12[r12<<3]
  12979. + ld.w r5,r5[r5<<2]
  12980. + ld.w r4,r4[r4<<1]
  12981. + ld.w lr,lr[lr<<1]
  12982. + ld.w r2,r9[r9<<0]
  12983. + ld.w r11,r2[r6<<0]
  12984. + ld.w r0,r2[sp<<3]
  12985. + .text
  12986. + .global ld_sh5
  12987. +ld_sh5:
  12988. + ld.sh pc,pc[pc<<0]
  12989. + ld.sh r12,r12[r12<<3]
  12990. + ld.sh r5,r5[r5<<2]
  12991. + ld.sh r4,r4[r4<<1]
  12992. + ld.sh lr,lr[lr<<1]
  12993. + ld.sh r11,r0[pc<<2]
  12994. + ld.sh r10,sp[r6<<2]
  12995. + ld.sh r12,r2[r2<<0]
  12996. + .text
  12997. + .global ld_uh5
  12998. +ld_uh5:
  12999. + ld.uh pc,pc[pc<<0]
  13000. + ld.uh r12,r12[r12<<3]
  13001. + ld.uh r5,r5[r5<<2]
  13002. + ld.uh r4,r4[r4<<1]
  13003. + ld.uh lr,lr[lr<<1]
  13004. + ld.uh r8,pc[lr<<3]
  13005. + ld.uh r6,r1[pc<<1]
  13006. + ld.uh r6,lr[sp<<1]
  13007. + .text
  13008. + .global ld_sb2
  13009. +ld_sb2:
  13010. + ld.sb pc,pc[pc<<0]
  13011. + ld.sb r12,r12[r12<<3]
  13012. + ld.sb r5,r5[r5<<2]
  13013. + ld.sb r4,r4[r4<<1]
  13014. + ld.sb lr,lr[lr<<1]
  13015. + ld.sb r9,r1[pc<<3]
  13016. + ld.sb r0,r3[r11<<1]
  13017. + ld.sb r10,r5[r5<<1]
  13018. + .text
  13019. + .global ld_ub5
  13020. +ld_ub5:
  13021. + ld.ub pc,pc[pc<<0]
  13022. + ld.ub r12,r12[r12<<3]
  13023. + ld.ub r5,r5[r5<<2]
  13024. + ld.ub r4,r4[r4<<1]
  13025. + ld.ub lr,lr[lr<<1]
  13026. + ld.ub r6,r12[r7<<3]
  13027. + ld.ub r2,r6[r12<<0]
  13028. + ld.ub r0,r7[r11<<1]
  13029. + .text
  13030. + .global st_d5
  13031. +st_d5:
  13032. + st.d pc[pc<<0],r14
  13033. + st.d r12[r12<<3],r12
  13034. + st.d r5[r5<<2],r6
  13035. + st.d r4[r4<<1],r4
  13036. + st.d lr[lr<<1],lr
  13037. + st.d r1[r9<<1],r4
  13038. + st.d r10[r2<<1],r4
  13039. + st.d r12[r6<<0],lr
  13040. + .text
  13041. + .global st_w5
  13042. +st_w5:
  13043. + st.w pc[pc<<0],pc
  13044. + st.w r12[r12<<3],r12
  13045. + st.w r5[r5<<2],r5
  13046. + st.w r4[r4<<1],r4
  13047. + st.w lr[lr<<1],lr
  13048. + st.w r1[r10<<0],r3
  13049. + st.w r0[r10<<1],r9
  13050. + st.w r4[r5<<3],pc
  13051. + .text
  13052. + .global st_h5
  13053. +st_h5:
  13054. + st.h pc[pc<<0],pc
  13055. + st.h r12[r12<<3],r12
  13056. + st.h r5[r5<<2],r5
  13057. + st.h r4[r4<<1],r4
  13058. + st.h lr[lr<<1],lr
  13059. + st.h r2[r9<<0],r11
  13060. + st.h r5[r1<<2],r12
  13061. + st.h pc[r8<<2],r3
  13062. + .text
  13063. + .global st_b5
  13064. +st_b5:
  13065. + st.b pc[pc<<0],pc
  13066. + st.b r12[r12<<3],r12
  13067. + st.b r5[r5<<2],r5
  13068. + st.b r4[r4<<1],r4
  13069. + st.b lr[lr<<1],lr
  13070. + st.b r1[r8<<1],r6
  13071. + st.b lr[lr<<3],r1
  13072. + st.b r5[r0<<2],pc
  13073. + .text
  13074. + .global divs
  13075. +divs:
  13076. + divs pc,pc,pc
  13077. + divs r12,r12,r12
  13078. + divs r5,r5,r5
  13079. + divs r4,r4,r4
  13080. + divs lr,lr,lr
  13081. + divs r3,pc,pc
  13082. + divs r9,r12,r2
  13083. + divs r7,r4,r1
  13084. + .text
  13085. + .global add1
  13086. +add1:
  13087. + add pc,pc
  13088. + add r12,r12
  13089. + add r5,r5
  13090. + add r4,r4
  13091. + add lr,lr
  13092. + add r12,r9
  13093. + add r6,r3
  13094. + add r10,r12
  13095. + .text
  13096. + .global sub1
  13097. +sub1:
  13098. + sub pc,pc
  13099. + sub r12,r12
  13100. + sub r5,r5
  13101. + sub r4,r4
  13102. + sub lr,lr
  13103. + sub lr,r6
  13104. + sub r0,sp
  13105. + sub r6,r12
  13106. + .text
  13107. + .global rsub1
  13108. +rsub1:
  13109. + rsub pc,pc
  13110. + rsub r12,r12
  13111. + rsub r5,r5
  13112. + rsub r4,r4
  13113. + rsub lr,lr
  13114. + rsub r11,sp
  13115. + rsub r7,r4
  13116. + rsub r9,r1
  13117. + .text
  13118. + .global cp1
  13119. +cp1:
  13120. + cp pc,pc
  13121. + cp r12,r12
  13122. + cp r5,r5
  13123. + cp r4,r4
  13124. + cp lr,lr
  13125. + cp r6,r2
  13126. + cp r0,r9
  13127. + cp r3,sp
  13128. + .text
  13129. + .global or1
  13130. +or1:
  13131. + or pc,pc
  13132. + or r12,r12
  13133. + or r5,r5
  13134. + or r4,r4
  13135. + or lr,lr
  13136. + or r4,r9
  13137. + or r11,r4
  13138. + or r4,r0
  13139. + .text
  13140. + .global eor1
  13141. +eor1:
  13142. + eor pc,pc
  13143. + eor r12,r12
  13144. + eor r5,r5
  13145. + eor r4,r4
  13146. + eor lr,lr
  13147. + eor r12,r11
  13148. + eor r0,r1
  13149. + eor r5,pc
  13150. + .text
  13151. + .global and1
  13152. +and1:
  13153. + and pc,pc
  13154. + and r12,r12
  13155. + and r5,r5
  13156. + and r4,r4
  13157. + and lr,lr
  13158. + and r8,r1
  13159. + and r0,sp
  13160. + and r10,r5
  13161. + .text
  13162. + .global tst
  13163. +tst:
  13164. + tst pc,pc
  13165. + tst r12,r12
  13166. + tst r5,r5
  13167. + tst r4,r4
  13168. + tst lr,lr
  13169. + tst r0,r12
  13170. + tst r10,r6
  13171. + tst sp,r4
  13172. + .text
  13173. + .global andn
  13174. +andn:
  13175. + andn pc,pc
  13176. + andn r12,r12
  13177. + andn r5,r5
  13178. + andn r4,r4
  13179. + andn lr,lr
  13180. + andn r9,r12
  13181. + andn r11,sp
  13182. + andn r12,r5
  13183. + .text
  13184. + .global mov3
  13185. +mov3:
  13186. + mov pc,pc
  13187. + mov r12,r12
  13188. + mov r5,r5
  13189. + mov r4,r4
  13190. + mov lr,lr
  13191. + mov r5,r9
  13192. + mov r11,r11
  13193. + mov r2,lr
  13194. + .text
  13195. + .global st_w1
  13196. +st_w1:
  13197. + st.w pc++,pc
  13198. + st.w r12++,r12
  13199. + st.w r5++,r5
  13200. + st.w r4++,r4
  13201. + st.w lr++,lr
  13202. + st.w r1++,r11
  13203. + st.w sp++,r0
  13204. + st.w sp++,r1
  13205. + .text
  13206. + .global st_h1
  13207. +st_h1:
  13208. + st.h pc++,pc
  13209. + st.h r12++,r12
  13210. + st.h r5++,r5
  13211. + st.h r4++,r4
  13212. + st.h lr++,lr
  13213. + st.h r12++,sp
  13214. + st.h r7++,lr
  13215. + st.h r7++,r4
  13216. + .text
  13217. + .global st_b1
  13218. +st_b1:
  13219. + st.b pc++,pc
  13220. + st.b r12++,r12
  13221. + st.b r5++,r5
  13222. + st.b r4++,r4
  13223. + st.b lr++,lr
  13224. + st.b r9++,sp
  13225. + st.b r1++,sp
  13226. + st.b r0++,r4
  13227. + .text
  13228. + .global st_w2
  13229. +st_w2:
  13230. + st.w --pc,pc
  13231. + st.w --r12,r12
  13232. + st.w --r5,r5
  13233. + st.w --r4,r4
  13234. + st.w --lr,lr
  13235. + st.w --r1,r7
  13236. + st.w --r3,r9
  13237. + st.w --r5,r5
  13238. + .text
  13239. + .global st_h2
  13240. +st_h2:
  13241. + st.h --pc,pc
  13242. + st.h --r12,r12
  13243. + st.h --r5,r5
  13244. + st.h --r4,r4
  13245. + st.h --lr,lr
  13246. + st.h --r5,r7
  13247. + st.h --r8,r8
  13248. + st.h --r7,r2
  13249. + .text
  13250. + .global st_b2
  13251. +st_b2:
  13252. + st.b --pc,pc
  13253. + st.b --r12,r12
  13254. + st.b --r5,r5
  13255. + st.b --r4,r4
  13256. + st.b --lr,lr
  13257. + st.b --sp,sp
  13258. + st.b --sp,r11
  13259. + st.b --r4,r5
  13260. + .text
  13261. + .global ld_w1
  13262. +ld_w1:
  13263. + ld.w pc,pc++
  13264. + ld.w r12,r12++
  13265. + ld.w r5,r5++
  13266. + ld.w r4,r4++
  13267. + ld.w lr,lr++
  13268. + ld.w r3,r7++
  13269. + ld.w r3,lr++
  13270. + ld.w r12,r5++
  13271. + .text
  13272. + .global ld_sh1
  13273. +ld_sh1:
  13274. + ld.sh pc,pc++
  13275. + ld.sh r12,r12++
  13276. + ld.sh r5,r5++
  13277. + ld.sh r4,r4++
  13278. + ld.sh lr,lr++
  13279. + ld.sh r11,r2++
  13280. + ld.sh r2,r8++
  13281. + ld.sh r7,r6++
  13282. + .text
  13283. + .global ld_uh1
  13284. +ld_uh1:
  13285. + ld.uh pc,pc++
  13286. + ld.uh r12,r12++
  13287. + ld.uh r5,r5++
  13288. + ld.uh r4,r4++
  13289. + ld.uh lr,lr++
  13290. + ld.uh r6,r7++
  13291. + ld.uh r10,r11++
  13292. + ld.uh lr,r4++
  13293. + .text
  13294. + .global ld_ub1
  13295. +ld_ub1:
  13296. + ld.ub pc,pc++
  13297. + ld.ub r12,r12++
  13298. + ld.ub r5,r5++
  13299. + ld.ub r4,r4++
  13300. + ld.ub lr,lr++
  13301. + ld.ub r8,lr++
  13302. + ld.ub r12,r12++
  13303. + ld.ub r11,r10++
  13304. + .text
  13305. + .global ld_w2
  13306. +ld_w2:
  13307. + ld.w pc,--pc
  13308. + ld.w r12,--r12
  13309. + ld.w r5,--r5
  13310. + ld.w r4,--r4
  13311. + ld.w lr,--lr
  13312. + ld.w r10,--lr
  13313. + ld.w r12,--r9
  13314. + ld.w r6,--r5
  13315. + .text
  13316. + .global ld_sh2
  13317. +ld_sh2:
  13318. + ld.sh pc,--pc
  13319. + ld.sh r12,--r12
  13320. + ld.sh r5,--r5
  13321. + ld.sh r4,--r4
  13322. + ld.sh lr,--lr
  13323. + ld.sh pc,--r10
  13324. + ld.sh r6,--r3
  13325. + ld.sh r4,--r6
  13326. + .text
  13327. + .global ld_uh2
  13328. +ld_uh2:
  13329. + ld.uh pc,--pc
  13330. + ld.uh r12,--r12
  13331. + ld.uh r5,--r5
  13332. + ld.uh r4,--r4
  13333. + ld.uh lr,--lr
  13334. + ld.uh r3,--r2
  13335. + ld.uh r1,--r0
  13336. + ld.uh r2,--r9
  13337. + .text
  13338. + .global ld_ub2
  13339. +ld_ub2:
  13340. + ld.ub pc,--pc
  13341. + ld.ub r12,--r12
  13342. + ld.ub r5,--r5
  13343. + ld.ub r4,--r4
  13344. + ld.ub lr,--lr
  13345. + ld.ub r1,--r1
  13346. + ld.ub r0,--r6
  13347. + ld.ub r2,--r7
  13348. + .text
  13349. + .global ld_ub3
  13350. +ld_ub3:
  13351. + ld.ub pc,pc[0]
  13352. + ld.ub r12,r12[7]
  13353. + ld.ub r5,r5[4]
  13354. + ld.ub r4,r4[3]
  13355. + ld.ub lr,lr[1]
  13356. + ld.ub r6,r9[6]
  13357. + ld.ub r2,lr[4]
  13358. + ld.ub r1,r8[0]
  13359. + .text
  13360. + .global sub3_sp
  13361. +sub3_sp:
  13362. + sub sp,0
  13363. + sub sp,-4
  13364. + sub sp,-512
  13365. + sub sp,508
  13366. + sub sp,4
  13367. + sub sp,44
  13368. + sub sp,8
  13369. + sub sp,348
  13370. + .text
  13371. + .global sub3
  13372. +sub3:
  13373. + sub pc,0
  13374. + sub r12,-1
  13375. + sub r5,-128
  13376. + sub r4,127
  13377. + sub lr,1
  13378. + sub r6,-41
  13379. + sub r4,37
  13380. + sub r12,56
  13381. + .text
  13382. + .global mov1
  13383. +mov1:
  13384. + mov pc,0
  13385. + mov r12,-1
  13386. + mov r5,-128
  13387. + mov r4,127
  13388. + mov lr,1
  13389. + mov pc,14
  13390. + mov r6,-100
  13391. + mov lr,-122
  13392. + .text
  13393. + .global lddsp
  13394. +lddsp:
  13395. + lddsp pc,sp[0]
  13396. + lddsp r12,sp[508]
  13397. + lddsp r5,sp[256]
  13398. + lddsp r4,sp[252]
  13399. + lddsp lr,sp[4]
  13400. + lddsp lr,sp[256]
  13401. + lddsp r12,sp[20]
  13402. + lddsp r9,sp[472]
  13403. + .text
  13404. + .global lddpc
  13405. +lddpc:
  13406. + lddpc pc,pc[0]
  13407. + lddpc r0,pc[508]
  13408. + lddpc r8,pc[256]
  13409. + lddpc r7,pc[252]
  13410. + lddpc lr,pc[4]
  13411. + lddpc sp,pc[472]
  13412. + lddpc r6,pc[120]
  13413. + lddpc r11,pc[28]
  13414. + .text
  13415. + .global stdsp
  13416. +stdsp:
  13417. + stdsp sp[0],pc
  13418. + stdsp sp[508],r12
  13419. + stdsp sp[256],r5
  13420. + stdsp sp[252],r4
  13421. + stdsp sp[4],lr
  13422. + stdsp sp[304],pc
  13423. + stdsp sp[256],r0
  13424. + stdsp sp[336],r5
  13425. + .text
  13426. + .global cp2
  13427. +cp2:
  13428. + cp pc,0
  13429. + cp r12,-1
  13430. + cp r5,-32
  13431. + cp r4,31
  13432. + cp lr,1
  13433. + cp r8,3
  13434. + cp lr,16
  13435. + cp r7,-26
  13436. + .text
  13437. + .global acr
  13438. +acr:
  13439. + acr pc
  13440. + acr r12
  13441. + acr r5
  13442. + acr r4
  13443. + acr lr
  13444. + acr r2
  13445. + acr r12
  13446. + acr pc
  13447. + .text
  13448. + .global scr
  13449. +scr:
  13450. + scr pc
  13451. + scr r12
  13452. + scr r5
  13453. + scr r4
  13454. + scr lr
  13455. + scr pc
  13456. + scr r6
  13457. + scr r1
  13458. + .text
  13459. + .global cpc0
  13460. +cpc0:
  13461. + cpc pc
  13462. + cpc r12
  13463. + cpc r5
  13464. + cpc r4
  13465. + cpc lr
  13466. + cpc pc
  13467. + cpc r4
  13468. + cpc r9
  13469. + .text
  13470. + .global neg
  13471. +neg:
  13472. + neg pc
  13473. + neg r12
  13474. + neg r5
  13475. + neg r4
  13476. + neg lr
  13477. + neg r7
  13478. + neg r1
  13479. + neg r9
  13480. + .text
  13481. + .global abs
  13482. +abs:
  13483. + abs pc
  13484. + abs r12
  13485. + abs r5
  13486. + abs r4
  13487. + abs lr
  13488. + abs r6
  13489. + abs r6
  13490. + abs r4
  13491. + .text
  13492. + .global castu_b
  13493. +castu_b:
  13494. + castu.b pc
  13495. + castu.b r12
  13496. + castu.b r5
  13497. + castu.b r4
  13498. + castu.b lr
  13499. + castu.b r7
  13500. + castu.b sp
  13501. + castu.b r9
  13502. + .text
  13503. + .global casts_b
  13504. +casts_b:
  13505. + casts.b pc
  13506. + casts.b r12
  13507. + casts.b r5
  13508. + casts.b r4
  13509. + casts.b lr
  13510. + casts.b r11
  13511. + casts.b r1
  13512. + casts.b r10
  13513. + .text
  13514. + .global castu_h
  13515. +castu_h:
  13516. + castu.h pc
  13517. + castu.h r12
  13518. + castu.h r5
  13519. + castu.h r4
  13520. + castu.h lr
  13521. + castu.h r10
  13522. + castu.h r11
  13523. + castu.h r1
  13524. + .text
  13525. + .global casts_h
  13526. +casts_h:
  13527. + casts.h pc
  13528. + casts.h r12
  13529. + casts.h r5
  13530. + casts.h r4
  13531. + casts.h lr
  13532. + casts.h r0
  13533. + casts.h r5
  13534. + casts.h r9
  13535. + .text
  13536. + .global brev
  13537. +brev:
  13538. + brev pc
  13539. + brev r12
  13540. + brev r5
  13541. + brev r4
  13542. + brev lr
  13543. + brev r5
  13544. + brev r10
  13545. + brev r8
  13546. + .text
  13547. + .global swap_h
  13548. +swap_h:
  13549. + swap.h pc
  13550. + swap.h r12
  13551. + swap.h r5
  13552. + swap.h r4
  13553. + swap.h lr
  13554. + swap.h r7
  13555. + swap.h r0
  13556. + swap.h r8
  13557. + .text
  13558. + .global swap_b
  13559. +swap_b:
  13560. + swap.b pc
  13561. + swap.b r12
  13562. + swap.b r5
  13563. + swap.b r4
  13564. + swap.b lr
  13565. + swap.b r10
  13566. + swap.b r12
  13567. + swap.b r1
  13568. + .text
  13569. + .global swap_bh
  13570. +swap_bh:
  13571. + swap.bh pc
  13572. + swap.bh r12
  13573. + swap.bh r5
  13574. + swap.bh r4
  13575. + swap.bh lr
  13576. + swap.bh r9
  13577. + swap.bh r4
  13578. + swap.bh r1
  13579. + .text
  13580. + .global One_s_compliment
  13581. +One_s_compliment:
  13582. + com pc
  13583. + com r12
  13584. + com r5
  13585. + com r4
  13586. + com lr
  13587. + com r2
  13588. + com r2
  13589. + com r7
  13590. + .text
  13591. + .global tnbz
  13592. +tnbz:
  13593. + tnbz pc
  13594. + tnbz r12
  13595. + tnbz r5
  13596. + tnbz r4
  13597. + tnbz lr
  13598. + tnbz r8
  13599. + tnbz r12
  13600. + tnbz pc
  13601. + .text
  13602. + .global rol
  13603. +rol:
  13604. + rol pc
  13605. + rol r12
  13606. + rol r5
  13607. + rol r4
  13608. + rol lr
  13609. + rol r10
  13610. + rol r9
  13611. + rol r5
  13612. + .text
  13613. + .global ror
  13614. +ror:
  13615. + ror pc
  13616. + ror r12
  13617. + ror r5
  13618. + ror r4
  13619. + ror lr
  13620. + ror r8
  13621. + ror r4
  13622. + ror r7
  13623. + .text
  13624. + .global icall
  13625. +icall:
  13626. + icall pc
  13627. + icall r12
  13628. + icall r5
  13629. + icall r4
  13630. + icall lr
  13631. + icall r3
  13632. + icall r1
  13633. + icall r3
  13634. + .text
  13635. + .global mustr
  13636. +mustr:
  13637. + mustr pc
  13638. + mustr r12
  13639. + mustr r5
  13640. + mustr r4
  13641. + mustr lr
  13642. + mustr r1
  13643. + mustr r4
  13644. + mustr r12
  13645. + .text
  13646. + .global musfr
  13647. +musfr:
  13648. + musfr pc
  13649. + musfr r12
  13650. + musfr r5
  13651. + musfr r4
  13652. + musfr lr
  13653. + musfr r11
  13654. + musfr r12
  13655. + musfr r2
  13656. + .text
  13657. + .global ret_cond
  13658. +ret_cond:
  13659. + reteq pc
  13660. + retal r12
  13661. + retls r5
  13662. + retpl r4
  13663. + retne lr
  13664. + retgt r0
  13665. + retgt r12
  13666. + retge r10
  13667. + .text
  13668. + .global sr_cond
  13669. +sr_cond:
  13670. + sreq pc
  13671. + sral r12
  13672. + srls r5
  13673. + srpl r4
  13674. + srne lr
  13675. + srlt r0
  13676. + sral sp
  13677. + srge r9
  13678. + .text
  13679. + .global ld_w3
  13680. +ld_w3:
  13681. + ld.w pc,pc[0]
  13682. + ld.w r12,r12[124]
  13683. + ld.w r5,r5[64]
  13684. + ld.w r4,r4[60]
  13685. + ld.w lr,lr[4]
  13686. + ld.w sp,r2[52]
  13687. + ld.w r9,r1[8]
  13688. + ld.w r5,sp[60]
  13689. + .text
  13690. + .global ld_sh3
  13691. +ld_sh3:
  13692. + ld.sh pc,pc[0]
  13693. + ld.sh r12,r12[14]
  13694. + ld.sh r5,r5[8]
  13695. + ld.sh r4,r4[6]
  13696. + ld.sh lr,lr[2]
  13697. + ld.sh r4,r2[8]
  13698. + ld.sh sp,lr[10]
  13699. + ld.sh r2,r11[2]
  13700. + .text
  13701. + .global ld_uh3
  13702. +ld_uh3:
  13703. + ld.uh pc,pc[0]
  13704. + ld.uh r12,r12[14]
  13705. + ld.uh r5,r5[8]
  13706. + ld.uh r4,r4[6]
  13707. + ld.uh lr,lr[2]
  13708. + ld.uh r10,r0[10]
  13709. + ld.uh r8,r11[8]
  13710. + ld.uh r10,r2[12]
  13711. + .text
  13712. + .global st_w3
  13713. +st_w3:
  13714. + st.w pc[0],pc
  13715. + st.w r12[60],r12
  13716. + st.w r5[32],r5
  13717. + st.w r4[28],r4
  13718. + st.w lr[4],lr
  13719. + st.w r7[44],r11
  13720. + st.w r2[24],r6
  13721. + st.w r4[12],r9
  13722. + .text
  13723. + .global st_h3
  13724. +st_h3:
  13725. + st.h pc[0],pc
  13726. + st.h r12[14],r12
  13727. + st.h r5[8],r5
  13728. + st.h r4[6],r4
  13729. + st.h lr[2],lr
  13730. + st.h lr[10],r12
  13731. + st.h r6[4],r0
  13732. + st.h r5[12],sp
  13733. + .text
  13734. + .global st_b3
  13735. +st_b3:
  13736. + st.b pc[0],pc
  13737. + st.b r12[7],r12
  13738. + st.b r5[4],r5
  13739. + st.b r4[3],r4
  13740. + st.b lr[1],lr
  13741. + st.b r12[6],r9
  13742. + st.b r2[3],lr
  13743. + st.b r1[3],r11
  13744. + .text
  13745. + .global ldd
  13746. +ldd:
  13747. + ld.d r0,pc
  13748. + ld.d r14,r12
  13749. + ld.d r8,r5
  13750. + ld.d r6,r4
  13751. + ld.d r2,lr
  13752. + ld.d r14,r7
  13753. + ld.d r4,r4
  13754. + ld.d r14,pc
  13755. + .text
  13756. + .global ldd_postinc
  13757. +ldd_postinc:
  13758. + ld.d r0,pc++
  13759. + ld.d r14,r12++
  13760. + ld.d r8,r5++
  13761. + ld.d r6,r4++
  13762. + ld.d r2,lr++
  13763. + ld.d r14,r5++
  13764. + ld.d r12,r11++
  13765. + ld.d r2,r12++
  13766. + .text
  13767. + .global ldd_predec
  13768. +ldd_predec:
  13769. + ld.d r0,--pc
  13770. + ld.d r14,--r12
  13771. + ld.d r8,--r5
  13772. + ld.d r6,--r4
  13773. + ld.d r2,--lr
  13774. + ld.d r8,--r0
  13775. + ld.d r10,--pc
  13776. + ld.d r2,--r4
  13777. + .text
  13778. + .global std
  13779. +std:
  13780. + st.d pc,r0
  13781. + st.d r12,r14
  13782. + st.d r5,r8
  13783. + st.d r4,r6
  13784. + st.d lr,r2
  13785. + st.d r0,r12
  13786. + st.d sp,r4
  13787. + st.d r12,r12
  13788. + .text
  13789. + .global std_postinc
  13790. +std_postinc:
  13791. + st.d pc++,r0
  13792. + st.d r12++,r14
  13793. + st.d r5++,r8
  13794. + st.d r4++,r6
  13795. + st.d lr++,r2
  13796. + st.d sp++,r6
  13797. + st.d r10++,r6
  13798. + st.d r7++,r2
  13799. + .text
  13800. + .global std_predec
  13801. +std_predec:
  13802. + st.d --pc,r0
  13803. + st.d --r12,r14
  13804. + st.d --r5,r8
  13805. + st.d --r4,r6
  13806. + st.d --lr,r2
  13807. + st.d --r3,r6
  13808. + st.d --lr,r2
  13809. + st.d --r0,r4
  13810. + .text
  13811. + .global mul
  13812. +mul:
  13813. + mul pc,pc
  13814. + mul r12,r12
  13815. + mul r5,r5
  13816. + mul r4,r4
  13817. + mul lr,lr
  13818. + mul r10,lr
  13819. + mul r0,r8
  13820. + mul r8,r5
  13821. + .text
  13822. + .global asr_imm5
  13823. +asr_imm5:
  13824. + asr pc,0
  13825. + asr r12,31
  13826. + asr r5,16
  13827. + asr r4,15
  13828. + asr lr,1
  13829. + asr r6,23
  13830. + asr r6,18
  13831. + asr r5,8
  13832. + .text
  13833. + .global lsl_imm5
  13834. +lsl_imm5:
  13835. + lsl pc,0
  13836. + lsl r12,31
  13837. + lsl r5,16
  13838. + lsl r4,15
  13839. + lsl lr,1
  13840. + lsl r12,13
  13841. + lsl r6,16
  13842. + lsl r1,25
  13843. + .text
  13844. + .global lsr_imm5
  13845. +lsr_imm5:
  13846. + lsr pc,0
  13847. + lsr r12,31
  13848. + lsr r5,16
  13849. + lsr r4,15
  13850. + lsr lr,1
  13851. + lsr r0,1
  13852. + lsr r8,10
  13853. + lsr r7,26
  13854. + .text
  13855. + .global sbr
  13856. +sbr:
  13857. + sbr pc,0
  13858. + sbr r12,31
  13859. + sbr r5,16
  13860. + sbr r4,15
  13861. + sbr lr,1
  13862. + sbr r8,31
  13863. + sbr r6,22
  13864. + sbr r1,23
  13865. + .text
  13866. + .global cbr
  13867. +cbr:
  13868. + cbr pc,0
  13869. + cbr r12,31
  13870. + cbr r5,16
  13871. + cbr r4,15
  13872. + cbr lr,1
  13873. + cbr r12,10
  13874. + cbr r7,22
  13875. + cbr r8,9
  13876. + .text
  13877. + .global brc1
  13878. +brc1:
  13879. + breq 0
  13880. + brpl -2
  13881. + brge -256
  13882. + brcs 254
  13883. + brne 2
  13884. + brcs 230
  13885. + breq -18
  13886. + breq 12
  13887. + .text
  13888. + .global rjmp
  13889. +rjmp:
  13890. + rjmp 0
  13891. + rjmp -2
  13892. + rjmp -1024
  13893. + rjmp 1022
  13894. + rjmp 2
  13895. + rjmp -962
  13896. + rjmp 14
  13897. + rjmp -516
  13898. + .text
  13899. + .global rcall1
  13900. +rcall1:
  13901. + rcall 0
  13902. + rcall -2
  13903. + rcall -1024
  13904. + rcall 1022
  13905. + rcall 2
  13906. + rcall 216
  13907. + rcall -530
  13908. + rcall -972
  13909. + .text
  13910. + .global acall
  13911. +acall:
  13912. + acall 0
  13913. + acall 1020
  13914. + acall 512
  13915. + acall 508
  13916. + acall 4
  13917. + acall 356
  13918. + acall 304
  13919. + acall 172
  13920. + .text
  13921. + .global scall
  13922. +scall:
  13923. + scall
  13924. + scall
  13925. + scall
  13926. + scall
  13927. + scall
  13928. + scall
  13929. + scall
  13930. + scall
  13931. + .text
  13932. + .global popm
  13933. +popm:
  13934. + /* popm with no argument fails currently */
  13935. + popm pc
  13936. + popm r0-r11,pc,r12=-1
  13937. + popm lr
  13938. + popm r0-r11,pc,r12=1
  13939. + popm r0-r3
  13940. + popm r4-r10,pc
  13941. + popm r0-r3,r11,pc,r12=0
  13942. + popm r0-r7,r10-r12,lr
  13943. + .text
  13944. + .global pushm
  13945. +pushm:
  13946. + pushm pc
  13947. + pushm r0-r12,lr,pc
  13948. + pushm pc
  13949. + pushm r0-r12,lr
  13950. + pushm r0-r3
  13951. + pushm r8-r10,lr,pc
  13952. + pushm r0-r3,r10
  13953. + pushm r8-r9,r12
  13954. + .text
  13955. + .global popm_n
  13956. +popm_n:
  13957. + popm pc
  13958. + popm r0-r11,pc,r12=-1
  13959. + popm lr
  13960. + popm r0-r11,pc,r12=1
  13961. + popm r0-r3
  13962. + popm r4-r10,pc
  13963. + popm r0-r3,r11,pc,r12=0
  13964. + popm r0-r7,r10-r12,lr
  13965. + .text
  13966. + .global pushm_n
  13967. +pushm_n:
  13968. + pushm pc
  13969. + pushm r0-r12,lr,pc
  13970. + pushm pc
  13971. + pushm r0-r12,lr
  13972. + pushm r0-r3
  13973. + pushm r8-r10,lr,pc
  13974. + pushm r0-r3,r10
  13975. + pushm r8-r9,r12
  13976. + .text
  13977. + .global csrfcz
  13978. +csrfcz:
  13979. + csrfcz 0
  13980. + csrfcz 31
  13981. + csrfcz 16
  13982. + csrfcz 15
  13983. + csrfcz 1
  13984. + csrfcz 5
  13985. + csrfcz 13
  13986. + csrfcz 23
  13987. + .text
  13988. + .global ssrf
  13989. +ssrf:
  13990. + ssrf 0
  13991. + ssrf 31
  13992. + ssrf 16
  13993. + ssrf 15
  13994. + ssrf 1
  13995. + ssrf 29
  13996. + ssrf 13
  13997. + ssrf 13
  13998. + .text
  13999. + .global csrf
  14000. +csrf:
  14001. + csrf 0
  14002. + csrf 31
  14003. + csrf 16
  14004. + csrf 15
  14005. + csrf 1
  14006. + csrf 10
  14007. + csrf 15
  14008. + csrf 11
  14009. + .text
  14010. + .global rete
  14011. +rete:
  14012. + rete
  14013. + .text
  14014. + .global rets
  14015. +rets:
  14016. + rets
  14017. + .text
  14018. + .global retd
  14019. +retd:
  14020. + retd
  14021. + .text
  14022. + .global retj
  14023. +retj:
  14024. + retj
  14025. + .text
  14026. + .global tlbr
  14027. +tlbr:
  14028. + tlbr
  14029. + .text
  14030. + .global tlbs
  14031. +tlbs:
  14032. + tlbs
  14033. + .text
  14034. + .global tlbw
  14035. +tlbw:
  14036. + tlbw
  14037. + .text
  14038. + .global breakpoint
  14039. +breakpoint:
  14040. + breakpoint
  14041. + .text
  14042. + .global incjosp
  14043. +incjosp:
  14044. + incjosp 1
  14045. + incjosp 2
  14046. + incjosp 3
  14047. + incjosp 4
  14048. + incjosp -4
  14049. + incjosp -3
  14050. + incjosp -2
  14051. + incjosp -1
  14052. + .text
  14053. + .global nop
  14054. +nop:
  14055. + nop
  14056. + .text
  14057. + .global popjc
  14058. +popjc:
  14059. + popjc
  14060. + .text
  14061. + .global pushjc
  14062. +pushjc:
  14063. + pushjc
  14064. + .text
  14065. + .global add2
  14066. +add2:
  14067. + add pc,pc,pc<<0
  14068. + add r12,r12,r12<<3
  14069. + add r5,r5,r5<<2
  14070. + add r4,r4,r4<<1
  14071. + add lr,lr,lr<<1
  14072. + add r0,r12,r0<<1
  14073. + add r9,r12,r4<<0
  14074. + add r12,r12,r7<<2
  14075. + .text
  14076. + .global sub2
  14077. +sub2:
  14078. + sub pc,pc,pc<<0
  14079. + sub r12,r12,r12<<3
  14080. + sub r5,r5,r5<<2
  14081. + sub r4,r4,r4<<1
  14082. + sub lr,lr,lr<<1
  14083. + sub sp,r3,r4<<0
  14084. + sub r3,r7,r3<<0
  14085. + sub sp,r10,sp<<1
  14086. + .text
  14087. + .global divu
  14088. +divu:
  14089. + divu pc,pc,pc
  14090. + divu r12,r12,r12
  14091. + divu r5,r5,r5
  14092. + divu r4,r4,r4
  14093. + divu lr,lr,lr
  14094. + divu sp,r4,pc
  14095. + divu r5,r5,sp
  14096. + divu r10,sp,r0
  14097. + .text
  14098. + .global addhh_w
  14099. +addhh_w:
  14100. + addhh.w pc,pc:b,pc:b
  14101. + addhh.w r12,r12:t,r12:t
  14102. + addhh.w r5,r5:t,r5:t
  14103. + addhh.w r4,r4:b,r4:b
  14104. + addhh.w lr,lr:t,lr:t
  14105. + addhh.w r0,r0:b,r3:b
  14106. + addhh.w lr,r12:t,r7:b
  14107. + addhh.w r3,r10:t,r2:b
  14108. + .text
  14109. + .global subhh_w
  14110. +subhh_w:
  14111. + subhh.w pc,pc:b,pc:b
  14112. + subhh.w r12,r12:t,r12:t
  14113. + subhh.w r5,r5:t,r5:t
  14114. + subhh.w r4,r4:b,r4:b
  14115. + subhh.w lr,lr:t,lr:t
  14116. + subhh.w r10,r1:t,r7:b
  14117. + subhh.w pc,r10:t,lr:t
  14118. + subhh.w r3,r0:t,r12:b
  14119. + .text
  14120. + .global adc
  14121. +adc:
  14122. + adc pc,pc,pc
  14123. + adc r12,r12,r12
  14124. + adc r5,r5,r5
  14125. + adc r4,r4,r4
  14126. + adc lr,lr,lr
  14127. + adc r4,r0,r7
  14128. + adc sp,r4,r3
  14129. + adc r2,r12,r0
  14130. + .text
  14131. + .global sbc
  14132. +sbc:
  14133. + sbc pc,pc,pc
  14134. + sbc r12,r12,r12
  14135. + sbc r5,r5,r5
  14136. + sbc r4,r4,r4
  14137. + sbc lr,lr,lr
  14138. + sbc r6,r7,r9
  14139. + sbc r0,r8,r5
  14140. + sbc r1,r0,r4
  14141. + .text
  14142. + .global mul_2
  14143. +mul_2:
  14144. + mul pc,pc,pc
  14145. + mul r12,r12,r12
  14146. + mul r5,r5,r5
  14147. + mul r4,r4,r4
  14148. + mul lr,lr,lr
  14149. + mul pc,r0,r0
  14150. + mul r8,pc,lr
  14151. + mul r4,r12,pc
  14152. + .text
  14153. + .global mac
  14154. +mac:
  14155. + mac pc,pc,pc
  14156. + mac r12,r12,r12
  14157. + mac r5,r5,r5
  14158. + mac r4,r4,r4
  14159. + mac lr,lr,lr
  14160. + mac r10,r4,r0
  14161. + mac r7,lr,r0
  14162. + mac r2,r9,r12
  14163. + .text
  14164. + .global mulsd
  14165. +mulsd:
  14166. + muls.d pc,pc,pc
  14167. + muls.d r12,r12,r12
  14168. + muls.d r5,r5,r5
  14169. + muls.d r4,r4,r4
  14170. + muls.d lr,lr,lr
  14171. + muls.d r2,r8,lr
  14172. + muls.d r4,r0,r11
  14173. + muls.d r5,lr,r6
  14174. + .text
  14175. + .global macsd
  14176. +macsd:
  14177. + macs.d r0,pc,pc
  14178. + macs.d r14,r12,r12
  14179. + macs.d r8,r5,r5
  14180. + macs.d r6,r4,r4
  14181. + macs.d r2,lr,lr
  14182. + macs.d r8,r1,r9
  14183. + macs.d r14,r8,r8
  14184. + macs.d r4,r3,r12
  14185. + .text
  14186. + .global mulud
  14187. +mulud:
  14188. + mulu.d r0,pc,pc
  14189. + mulu.d r14,r12,r12
  14190. + mulu.d r8,r5,r5
  14191. + mulu.d r6,r4,r4
  14192. + mulu.d r2,lr,lr
  14193. + mulu.d r6,r5,r0
  14194. + mulu.d r4,r6,r1
  14195. + mulu.d r8,r8,r2
  14196. + .text
  14197. + .global macud
  14198. +macud:
  14199. + macu.d r0,pc,pc
  14200. + macu.d r14,r12,r12
  14201. + macu.d r8,r5,r5
  14202. + macu.d r6,r4,r4
  14203. + macu.d r2,lr,lr
  14204. + macu.d r6,sp,r11
  14205. + macu.d r2,r4,r8
  14206. + macu.d r6,r10,r9
  14207. + .text
  14208. + .global asr_1
  14209. +asr_1:
  14210. + asr pc,pc,pc
  14211. + asr r12,r12,r12
  14212. + asr r5,r5,r5
  14213. + asr r4,r4,r4
  14214. + asr lr,lr,lr
  14215. + asr pc,r6,pc
  14216. + asr r0,r6,r12
  14217. + asr r4,sp,r0
  14218. + .text
  14219. + .global lsl_1
  14220. +lsl_1:
  14221. + lsl pc,pc,pc
  14222. + lsl r12,r12,r12
  14223. + lsl r5,r5,r5
  14224. + lsl r4,r4,r4
  14225. + lsl lr,lr,lr
  14226. + lsl lr,r5,lr
  14227. + lsl r5,pc,r3
  14228. + lsl r1,pc,r9
  14229. + .text
  14230. + .global lsr_1
  14231. +lsr_1:
  14232. + lsr pc,pc,pc
  14233. + lsr r12,r12,r12
  14234. + lsr r5,r5,r5
  14235. + lsr r4,r4,r4
  14236. + lsr lr,lr,lr
  14237. + lsr r2,r4,r1
  14238. + lsr r5,r1,r6
  14239. + lsr sp,r6,r7
  14240. + .text
  14241. + .global xchg
  14242. +xchg:
  14243. + xchg pc,pc,pc
  14244. + xchg r12,r12,r12
  14245. + xchg r5,r5,r5
  14246. + xchg r4,r4,r4
  14247. + xchg lr,lr,lr
  14248. + xchg lr,r4,sp
  14249. + xchg r1,r5,r12
  14250. + xchg lr,r12,r0
  14251. + .text
  14252. + .global max
  14253. +max:
  14254. + max pc,pc,pc
  14255. + max r12,r12,r12
  14256. + max r5,r5,r5
  14257. + max r4,r4,r4
  14258. + max lr,lr,lr
  14259. + max lr,r2,sp
  14260. + max r4,r10,r9
  14261. + max lr,r9,lr
  14262. + .text
  14263. + .global min
  14264. +min:
  14265. + min pc,pc,pc
  14266. + min r12,r12,r12
  14267. + min r5,r5,r5
  14268. + min r4,r4,r4
  14269. + min lr,lr,lr
  14270. + min r9,r7,r8
  14271. + min sp,r5,r5
  14272. + min r4,r1,r4
  14273. + .text
  14274. + .global addabs
  14275. +addabs:
  14276. + addabs pc,pc,pc
  14277. + addabs r12,r12,r12
  14278. + addabs r5,r5,r5
  14279. + addabs r4,r4,r4
  14280. + addabs lr,lr,lr
  14281. + addabs r7,r10,r0
  14282. + addabs r9,r9,r7
  14283. + addabs r2,r8,r12
  14284. + .text
  14285. + .global mulnhh_w
  14286. +mulnhh_w:
  14287. + mulnhh.w pc,pc:b,pc:b
  14288. + mulnhh.w r12,r12:t,r12:t
  14289. + mulnhh.w r5,r5:t,r5:t
  14290. + mulnhh.w r4,r4:b,r4:b
  14291. + mulnhh.w lr,lr:t,lr:t
  14292. + mulnhh.w r11,sp:t,r9:b
  14293. + mulnhh.w sp,r4:b,lr:t
  14294. + mulnhh.w r12,r2:t,r11:b
  14295. + .text
  14296. + .global mulnwh_d
  14297. +mulnwh_d:
  14298. + mulnwh.d r0,pc,pc:b
  14299. + mulnwh.d r14,r12,r12:t
  14300. + mulnwh.d r8,r5,r5:t
  14301. + mulnwh.d r6,r4,r4:b
  14302. + mulnwh.d r2,lr,lr:t
  14303. + mulnwh.d r14,r3,r2:t
  14304. + mulnwh.d r4,r5,r9:b
  14305. + mulnwh.d r12,r4,r4:t
  14306. + .text
  14307. + .global machh_w
  14308. +machh_w:
  14309. + machh.w pc,pc:b,pc:b
  14310. + machh.w r12,r12:t,r12:t
  14311. + machh.w r5,r5:t,r5:t
  14312. + machh.w r4,r4:b,r4:b
  14313. + machh.w lr,lr:t,lr:t
  14314. + machh.w lr,r5:b,r1:t
  14315. + machh.w r9,r6:b,r7:b
  14316. + machh.w r5,lr:t,r12:b
  14317. + .text
  14318. + .global machh_d
  14319. +machh_d:
  14320. + machh.d r0,pc:b,pc:b
  14321. + machh.d r14,r12:t,r12:t
  14322. + machh.d r8,r5:t,r5:t
  14323. + machh.d r6,r4:b,r4:b
  14324. + machh.d r2,lr:t,lr:t
  14325. + machh.d r10,r0:b,r8:b
  14326. + machh.d r14,r4:b,r5:t
  14327. + machh.d r8,r0:b,r4:t
  14328. + .text
  14329. + .global macsathh_w
  14330. +macsathh_w:
  14331. + macsathh.w pc,pc:b,pc:b
  14332. + macsathh.w r12,r12:t,r12:t
  14333. + macsathh.w r5,r5:t,r5:t
  14334. + macsathh.w r4,r4:b,r4:b
  14335. + macsathh.w lr,lr:t,lr:t
  14336. + macsathh.w r7,r7:t,pc:t
  14337. + macsathh.w r4,r2:t,r4:b
  14338. + macsathh.w r4,r8:t,r3:t
  14339. + .text
  14340. + .global mulhh_w
  14341. +mulhh_w:
  14342. + mulhh.w pc,pc:b,pc:b
  14343. + mulhh.w r12,r12:t,r12:t
  14344. + mulhh.w r5,r5:t,r5:t
  14345. + mulhh.w r4,r4:b,r4:b
  14346. + mulhh.w lr,lr:t,lr:t
  14347. + mulhh.w r7,r4:t,r9:b
  14348. + mulhh.w pc,r3:t,r7:t
  14349. + mulhh.w pc,r4:b,r9:t
  14350. + .text
  14351. + .global mulsathh_h
  14352. +mulsathh_h:
  14353. + mulsathh.h pc,pc:b,pc:b
  14354. + mulsathh.h r12,r12:t,r12:t
  14355. + mulsathh.h r5,r5:t,r5:t
  14356. + mulsathh.h r4,r4:b,r4:b
  14357. + mulsathh.h lr,lr:t,lr:t
  14358. + mulsathh.h r3,r1:b,sp:b
  14359. + mulsathh.h r11,lr:t,r11:b
  14360. + mulsathh.h r8,r8:b,r11:t
  14361. + .text
  14362. + .global mulsathh_w
  14363. +mulsathh_w:
  14364. + mulsathh.w pc,pc:b,pc:b
  14365. + mulsathh.w r12,r12:t,r12:t
  14366. + mulsathh.w r5,r5:t,r5:t
  14367. + mulsathh.w r4,r4:b,r4:b
  14368. + mulsathh.w lr,lr:t,lr:t
  14369. + mulsathh.w lr,r11:t,r6:b
  14370. + mulsathh.w r6,r6:b,r7:t
  14371. + mulsathh.w r10,r2:b,r3:b
  14372. + .text
  14373. + .global mulsatrndhh_h
  14374. +mulsatrndhh_h:
  14375. + mulsatrndhh.h pc,pc:b,pc:b
  14376. + mulsatrndhh.h r12,r12:t,r12:t
  14377. + mulsatrndhh.h r5,r5:t,r5:t
  14378. + mulsatrndhh.h r4,r4:b,r4:b
  14379. + mulsatrndhh.h lr,lr:t,lr:t
  14380. + mulsatrndhh.h r11,r6:b,r9:b
  14381. + mulsatrndhh.h r11,r3:b,r8:t
  14382. + mulsatrndhh.h r5,sp:t,r7:t
  14383. + .text
  14384. + .global mulsatrndwh_w
  14385. +mulsatrndwh_w:
  14386. + mulsatrndwh.w pc,pc,pc:b
  14387. + mulsatrndwh.w r12,r12,r12:t
  14388. + mulsatrndwh.w r5,r5,r5:t
  14389. + mulsatrndwh.w r4,r4,r4:b
  14390. + mulsatrndwh.w lr,lr,lr:t
  14391. + mulsatrndwh.w r5,r12,r0:b
  14392. + mulsatrndwh.w r7,r10,pc:b
  14393. + mulsatrndwh.w r10,r8,r5:t
  14394. + .text
  14395. + .global macwh_d
  14396. +macwh_d:
  14397. + macwh.d r0,pc,pc:b
  14398. + macwh.d r14,r12,r12:t
  14399. + macwh.d r8,r5,r5:t
  14400. + macwh.d r6,r4,r4:b
  14401. + macwh.d r2,lr,lr:t
  14402. + macwh.d r4,r10,r12:t
  14403. + macwh.d r4,r7,sp:b
  14404. + macwh.d r14,r9,r11:b
  14405. + .text
  14406. + .global mulwh_d
  14407. +mulwh_d:
  14408. + mulwh.d r0,pc,pc:b
  14409. + mulwh.d r14,r12,r12:t
  14410. + mulwh.d r8,r5,r5:t
  14411. + mulwh.d r6,r4,r4:b
  14412. + mulwh.d r2,lr,lr:t
  14413. + mulwh.d r12,r5,r1:b
  14414. + mulwh.d r0,r1,r3:t
  14415. + mulwh.d r0,r9,r2:b
  14416. + .text
  14417. + .global mulsatwh_w
  14418. +mulsatwh_w:
  14419. + mulsatwh.w pc,pc,pc:b
  14420. + mulsatwh.w r12,r12,r12:t
  14421. + mulsatwh.w r5,r5,r5:t
  14422. + mulsatwh.w r4,r4,r4:b
  14423. + mulsatwh.w lr,lr,lr:t
  14424. + mulsatwh.w r11,pc,r10:t
  14425. + mulsatwh.w sp,r12,r9:t
  14426. + mulsatwh.w r0,r3,r2:t
  14427. + .text
  14428. + .global ldw7
  14429. +ldw7:
  14430. + ld.w pc,pc[pc:b<<2]
  14431. + ld.w r12,r12[r12:t<<2]
  14432. + ld.w r5,r5[r5:u<<2]
  14433. + ld.w r4,r4[r4:l<<2]
  14434. + ld.w lr,lr[lr:l<<2]
  14435. + ld.w r9,r10[r6:l<<2]
  14436. + ld.w r2,r10[r10:b<<2]
  14437. + ld.w r11,r5[pc:b<<2]
  14438. + .text
  14439. + .global satadd_w
  14440. +satadd_w:
  14441. + satadd.w pc,pc,pc
  14442. + satadd.w r12,r12,r12
  14443. + satadd.w r5,r5,r5
  14444. + satadd.w r4,r4,r4
  14445. + satadd.w lr,lr,lr
  14446. + satadd.w r4,r8,r11
  14447. + satadd.w r3,r12,r6
  14448. + satadd.w r3,lr,r9
  14449. + .text
  14450. + .global satsub_w1
  14451. +satsub_w1:
  14452. + satsub.w pc,pc,pc
  14453. + satsub.w r12,r12,r12
  14454. + satsub.w r5,r5,r5
  14455. + satsub.w r4,r4,r4
  14456. + satsub.w lr,lr,lr
  14457. + satsub.w r8,sp,r0
  14458. + satsub.w r9,r8,r4
  14459. + satsub.w pc,lr,r2
  14460. + .text
  14461. + .global satadd_h
  14462. +satadd_h:
  14463. + satadd.h pc,pc,pc
  14464. + satadd.h r12,r12,r12
  14465. + satadd.h r5,r5,r5
  14466. + satadd.h r4,r4,r4
  14467. + satadd.h lr,lr,lr
  14468. + satadd.h r7,r3,r9
  14469. + satadd.h r1,r0,r2
  14470. + satadd.h r1,r4,lr
  14471. + .text
  14472. + .global satsub_h
  14473. +satsub_h:
  14474. + satsub.h pc,pc,pc
  14475. + satsub.h r12,r12,r12
  14476. + satsub.h r5,r5,r5
  14477. + satsub.h r4,r4,r4
  14478. + satsub.h lr,lr,lr
  14479. + satsub.h lr,lr,r3
  14480. + satsub.h r11,r6,r5
  14481. + satsub.h r3,sp,r0
  14482. + .text
  14483. + .global mul3
  14484. +mul3:
  14485. + mul pc,pc,0
  14486. + mul r12,r12,-1
  14487. + mul r5,r5,-128
  14488. + mul r4,r4,127
  14489. + mul lr,lr,1
  14490. + mul r12,r2,-7
  14491. + mul r1,pc,95
  14492. + mul r4,r6,19
  14493. + .text
  14494. + .global rsub2
  14495. +rsub2:
  14496. + rsub pc,pc,0
  14497. + rsub r12,r12,-1
  14498. + rsub r5,r5,-128
  14499. + rsub r4,r4,127
  14500. + rsub lr,lr,1
  14501. + rsub r9,lr,96
  14502. + rsub r11,r1,56
  14503. + rsub r0,r7,-87
  14504. + .text
  14505. + .global clz
  14506. +clz:
  14507. + clz pc,pc
  14508. + clz r12,r12
  14509. + clz r5,r5
  14510. + clz r4,r4
  14511. + clz lr,lr
  14512. + clz r2,r3
  14513. + clz r5,r11
  14514. + clz pc,r3
  14515. + .text
  14516. + .global cpc1
  14517. +cpc1:
  14518. + cpc pc,pc
  14519. + cpc r12,r12
  14520. + cpc r5,r5
  14521. + cpc r4,r4
  14522. + cpc lr,lr
  14523. + cpc pc,r4
  14524. + cpc r5,r9
  14525. + cpc r6,r7
  14526. + .text
  14527. + .global asr3
  14528. +asr3:
  14529. + asr pc,pc,0
  14530. + asr r12,r12,31
  14531. + asr r5,r5,16
  14532. + asr r4,r4,15
  14533. + asr lr,lr,1
  14534. + asr r4,r11,19
  14535. + asr sp,pc,26
  14536. + asr r11,sp,8
  14537. + .text
  14538. + .global lsl3
  14539. +lsl3:
  14540. + lsl pc,pc,0
  14541. + lsl r12,r12,31
  14542. + lsl r5,r5,16
  14543. + lsl r4,r4,15
  14544. + lsl lr,lr,1
  14545. + lsl r8,r10,17
  14546. + lsl r2,lr,3
  14547. + lsl lr,r11,14
  14548. + .text
  14549. + .global lsr3
  14550. +lsr3:
  14551. + lsr pc,pc,0
  14552. + lsr r12,r12,31
  14553. + lsr r5,r5,16
  14554. + lsr r4,r4,15
  14555. + lsr lr,lr,1
  14556. + lsr r4,r3,31
  14557. + lsr pc,r9,14
  14558. + lsr r3,r0,6
  14559. +/* .text
  14560. + .global extract_b
  14561. +extract_b:
  14562. + extract.b pc,pc:b
  14563. + extract.b r12,r12:t
  14564. + extract.b r5,r5:u
  14565. + extract.b r4,r4:l
  14566. + extract.b lr,lr:l
  14567. + extract.b r2,r5:l
  14568. + extract.b r12,r3:l
  14569. + extract.b sp,r3:l
  14570. + .text
  14571. + .global insert_b
  14572. +insert_b:
  14573. + insert.b pc:b,pc
  14574. + insert.b r12:t,r12
  14575. + insert.b r5:u,r5
  14576. + insert.b r4:l,r4
  14577. + insert.b lr:l,lr
  14578. + insert.b r12:u,r3
  14579. + insert.b r10:l,lr
  14580. + insert.b r11:l,r12
  14581. + .text
  14582. + .global extract_h
  14583. +extract_h:
  14584. + extract.h pc,pc:b
  14585. + extract.h r12,r12:t
  14586. + extract.h r5,r5:t
  14587. + extract.h r4,r4:b
  14588. + extract.h lr,lr:t
  14589. + extract.h r11,lr:b
  14590. + extract.h r10,r0:b
  14591. + extract.h r11,r12:b
  14592. + .text
  14593. + .global insert_h
  14594. +insert_h:
  14595. + insert.h pc:b,pc
  14596. + insert.h r12:t,r12
  14597. + insert.h r5:t,r5
  14598. + insert.h r4:b,r4
  14599. + insert.h lr:t,lr
  14600. + insert.h r12:t,r11
  14601. + insert.h r7:b,r6
  14602. + insert.h r1:t,r11 */
  14603. + .text
  14604. + .global movc1
  14605. +movc1:
  14606. + moveq pc,pc
  14607. + moval r12,r12
  14608. + movls r5,r5
  14609. + movpl r4,r4
  14610. + movne lr,lr
  14611. + movne pc,r11
  14612. + movmi r10,r2
  14613. + movls r8,r12
  14614. + .text
  14615. + .global padd_h
  14616. +padd_h:
  14617. + padd.h pc,pc,pc
  14618. + padd.h r12,r12,r12
  14619. + padd.h r5,r5,r5
  14620. + padd.h r4,r4,r4
  14621. + padd.h lr,lr,lr
  14622. + padd.h r8,r2,r7
  14623. + padd.h r0,r0,r3
  14624. + padd.h sp,r11,r6
  14625. + .text
  14626. + .global psub_h
  14627. +psub_h:
  14628. + psub.h pc,pc,pc
  14629. + psub.h r12,r12,r12
  14630. + psub.h r5,r5,r5
  14631. + psub.h r4,r4,r4
  14632. + psub.h lr,lr,lr
  14633. + psub.h lr,r6,r8
  14634. + psub.h r0,r1,sp
  14635. + psub.h pc,pc,sp
  14636. + .text
  14637. + .global paddx_h
  14638. +paddx_h:
  14639. + paddx.h pc,pc,pc
  14640. + paddx.h r12,r12,r12
  14641. + paddx.h r5,r5,r5
  14642. + paddx.h r4,r4,r4
  14643. + paddx.h lr,lr,lr
  14644. + paddx.h pc,pc,r1
  14645. + paddx.h r10,r4,r5
  14646. + paddx.h r5,pc,r2
  14647. + .text
  14648. + .global psubx_h
  14649. +psubx_h:
  14650. + psubx.h pc,pc,pc
  14651. + psubx.h r12,r12,r12
  14652. + psubx.h r5,r5,r5
  14653. + psubx.h r4,r4,r4
  14654. + psubx.h lr,lr,lr
  14655. + psubx.h r5,r12,r5
  14656. + psubx.h r3,r8,r3
  14657. + psubx.h r5,r2,r3
  14658. + .text
  14659. + .global padds_sh
  14660. +padds_sh:
  14661. + padds.sh pc,pc,pc
  14662. + padds.sh r12,r12,r12
  14663. + padds.sh r5,r5,r5
  14664. + padds.sh r4,r4,r4
  14665. + padds.sh lr,lr,lr
  14666. + padds.sh r9,lr,r2
  14667. + padds.sh r6,r8,r1
  14668. + padds.sh r6,r4,r10
  14669. + .text
  14670. + .global psubs_sh
  14671. +psubs_sh:
  14672. + psubs.sh pc,pc,pc
  14673. + psubs.sh r12,r12,r12
  14674. + psubs.sh r5,r5,r5
  14675. + psubs.sh r4,r4,r4
  14676. + psubs.sh lr,lr,lr
  14677. + psubs.sh r6,lr,r11
  14678. + psubs.sh r2,r12,r4
  14679. + psubs.sh r0,r9,r0
  14680. + .text
  14681. + .global paddxs_sh
  14682. +paddxs_sh:
  14683. + paddxs.sh pc,pc,pc
  14684. + paddxs.sh r12,r12,r12
  14685. + paddxs.sh r5,r5,r5
  14686. + paddxs.sh r4,r4,r4
  14687. + paddxs.sh lr,lr,lr
  14688. + paddxs.sh r0,r3,r9
  14689. + paddxs.sh pc,r10,r11
  14690. + paddxs.sh pc,r10,pc
  14691. + .text
  14692. + .global psubxs_sh
  14693. +psubxs_sh:
  14694. + psubxs.sh pc,pc,pc
  14695. + psubxs.sh r12,r12,r12
  14696. + psubxs.sh r5,r5,r5
  14697. + psubxs.sh r4,r4,r4
  14698. + psubxs.sh lr,lr,lr
  14699. + psubxs.sh r7,r4,r4
  14700. + psubxs.sh r7,r8,r3
  14701. + psubxs.sh pc,r6,r5
  14702. + .text
  14703. + .global padds_uh
  14704. +padds_uh:
  14705. + padds.uh pc,pc,pc
  14706. + padds.uh r12,r12,r12
  14707. + padds.uh r5,r5,r5
  14708. + padds.uh r4,r4,r4
  14709. + padds.uh lr,lr,lr
  14710. + padds.uh r12,r11,r7
  14711. + padds.uh r7,r8,lr
  14712. + padds.uh r6,r9,r7
  14713. + .text
  14714. + .global psubs_uh
  14715. +psubs_uh:
  14716. + psubs.uh pc,pc,pc
  14717. + psubs.uh r12,r12,r12
  14718. + psubs.uh r5,r5,r5
  14719. + psubs.uh r4,r4,r4
  14720. + psubs.uh lr,lr,lr
  14721. + psubs.uh lr,r10,r6
  14722. + psubs.uh sp,r2,pc
  14723. + psubs.uh r2,r9,r2
  14724. + .text
  14725. + .global paddxs_uh
  14726. +paddxs_uh:
  14727. + paddxs.uh pc,pc,pc
  14728. + paddxs.uh r12,r12,r12
  14729. + paddxs.uh r5,r5,r5
  14730. + paddxs.uh r4,r4,r4
  14731. + paddxs.uh lr,lr,lr
  14732. + paddxs.uh r7,r9,r5
  14733. + paddxs.uh r9,r1,r4
  14734. + paddxs.uh r5,r2,r3
  14735. + .text
  14736. + .global psubxs_uh
  14737. +psubxs_uh:
  14738. + psubxs.uh pc,pc,pc
  14739. + psubxs.uh r12,r12,r12
  14740. + psubxs.uh r5,r5,r5
  14741. + psubxs.uh r4,r4,r4
  14742. + psubxs.uh lr,lr,lr
  14743. + psubxs.uh sp,r5,sp
  14744. + psubxs.uh sp,r6,r6
  14745. + psubxs.uh r3,r11,r8
  14746. + .text
  14747. + .global paddh_sh
  14748. +paddh_sh:
  14749. + paddh.sh pc,pc,pc
  14750. + paddh.sh r12,r12,r12
  14751. + paddh.sh r5,r5,r5
  14752. + paddh.sh r4,r4,r4
  14753. + paddh.sh lr,lr,lr
  14754. + paddh.sh r12,sp,r3
  14755. + paddh.sh pc,r5,r3
  14756. + paddh.sh r8,r8,sp
  14757. + .text
  14758. + .global psubh_sh
  14759. +psubh_sh:
  14760. + psubh.sh pc,pc,pc
  14761. + psubh.sh r12,r12,r12
  14762. + psubh.sh r5,r5,r5
  14763. + psubh.sh r4,r4,r4
  14764. + psubh.sh lr,lr,lr
  14765. + psubh.sh r1,r5,r8
  14766. + psubh.sh r7,r3,r6
  14767. + psubh.sh r4,r3,r3
  14768. + .text
  14769. + .global paddxh_sh
  14770. +paddxh_sh:
  14771. + paddxh.sh pc,pc,pc
  14772. + paddxh.sh r12,r12,r12
  14773. + paddxh.sh r5,r5,r5
  14774. + paddxh.sh r4,r4,r4
  14775. + paddxh.sh lr,lr,lr
  14776. + paddxh.sh r6,r0,r4
  14777. + paddxh.sh r9,r8,r9
  14778. + paddxh.sh r3,r0,sp
  14779. + .text
  14780. + .global psubxh_sh
  14781. +psubxh_sh:
  14782. + psubxh.sh pc,pc,pc
  14783. + psubxh.sh r12,r12,r12
  14784. + psubxh.sh r5,r5,r5
  14785. + psubxh.sh r4,r4,r4
  14786. + psubxh.sh lr,lr,lr
  14787. + psubxh.sh r4,pc,r12
  14788. + psubxh.sh r8,r4,r6
  14789. + psubxh.sh r12,r9,r4
  14790. + .text
  14791. + .global paddsub_h
  14792. +paddsub_h:
  14793. + paddsub.h pc,pc:b,pc:b
  14794. + paddsub.h r12,r12:t,r12:t
  14795. + paddsub.h r5,r5:t,r5:t
  14796. + paddsub.h r4,r4:b,r4:b
  14797. + paddsub.h lr,lr:t,lr:t
  14798. + paddsub.h r5,r2:t,lr:b
  14799. + paddsub.h r7,r1:b,r8:b
  14800. + paddsub.h r6,r10:t,r5:t
  14801. + .text
  14802. + .global psubadd_h
  14803. +psubadd_h:
  14804. + psubadd.h pc,pc:b,pc:b
  14805. + psubadd.h r12,r12:t,r12:t
  14806. + psubadd.h r5,r5:t,r5:t
  14807. + psubadd.h r4,r4:b,r4:b
  14808. + psubadd.h lr,lr:t,lr:t
  14809. + psubadd.h r9,r11:t,r8:t
  14810. + psubadd.h r10,r7:t,lr:t
  14811. + psubadd.h r6,pc:t,pc:b
  14812. + .text
  14813. + .global paddsubs_sh
  14814. +paddsubs_sh:
  14815. + paddsubs.sh pc,pc:b,pc:b
  14816. + paddsubs.sh r12,r12:t,r12:t
  14817. + paddsubs.sh r5,r5:t,r5:t
  14818. + paddsubs.sh r4,r4:b,r4:b
  14819. + paddsubs.sh lr,lr:t,lr:t
  14820. + paddsubs.sh r0,lr:t,r0:b
  14821. + paddsubs.sh r9,r2:t,r4:t
  14822. + paddsubs.sh r12,r9:t,sp:t
  14823. + .text
  14824. + .global psubadds_sh
  14825. +psubadds_sh:
  14826. + psubadds.sh pc,pc:b,pc:b
  14827. + psubadds.sh r12,r12:t,r12:t
  14828. + psubadds.sh r5,r5:t,r5:t
  14829. + psubadds.sh r4,r4:b,r4:b
  14830. + psubadds.sh lr,lr:t,lr:t
  14831. + psubadds.sh pc,lr:b,r1:t
  14832. + psubadds.sh r11,r3:b,r12:b
  14833. + psubadds.sh r10,r2:t,r8:t
  14834. + .text
  14835. + .global paddsubs_uh
  14836. +paddsubs_uh:
  14837. + paddsubs.uh pc,pc:b,pc:b
  14838. + paddsubs.uh r12,r12:t,r12:t
  14839. + paddsubs.uh r5,r5:t,r5:t
  14840. + paddsubs.uh r4,r4:b,r4:b
  14841. + paddsubs.uh lr,lr:t,lr:t
  14842. + paddsubs.uh r9,r2:b,r3:b
  14843. + paddsubs.uh sp,sp:b,r7:t
  14844. + paddsubs.uh lr,r0:b,r10:t
  14845. + .text
  14846. + .global psubadds_uh
  14847. +psubadds_uh:
  14848. + psubadds.uh pc,pc:b,pc:b
  14849. + psubadds.uh r12,r12:t,r12:t
  14850. + psubadds.uh r5,r5:t,r5:t
  14851. + psubadds.uh r4,r4:b,r4:b
  14852. + psubadds.uh lr,lr:t,lr:t
  14853. + psubadds.uh r12,r9:t,pc:t
  14854. + psubadds.uh r8,r6:b,r8:b
  14855. + psubadds.uh r8,r8:b,r4:b
  14856. + .text
  14857. + .global paddsubh_sh
  14858. +paddsubh_sh:
  14859. + paddsubh.sh pc,pc:b,pc:b
  14860. + paddsubh.sh r12,r12:t,r12:t
  14861. + paddsubh.sh r5,r5:t,r5:t
  14862. + paddsubh.sh r4,r4:b,r4:b
  14863. + paddsubh.sh lr,lr:t,lr:t
  14864. + paddsubh.sh r8,r9:t,r9:b
  14865. + paddsubh.sh r0,sp:t,r1:t
  14866. + paddsubh.sh r3,r1:b,r0:t
  14867. + .text
  14868. + .global psubaddh_sh
  14869. +psubaddh_sh:
  14870. + psubaddh.sh pc,pc:b,pc:b
  14871. + psubaddh.sh r12,r12:t,r12:t
  14872. + psubaddh.sh r5,r5:t,r5:t
  14873. + psubaddh.sh r4,r4:b,r4:b
  14874. + psubaddh.sh lr,lr:t,lr:t
  14875. + psubaddh.sh r7,r3:t,r10:b
  14876. + psubaddh.sh r7,r2:t,r1:t
  14877. + psubaddh.sh r11,r3:b,r6:b
  14878. + .text
  14879. + .global padd_b
  14880. +padd_b:
  14881. + padd.b pc,pc,pc
  14882. + padd.b r12,r12,r12
  14883. + padd.b r5,r5,r5
  14884. + padd.b r4,r4,r4
  14885. + padd.b lr,lr,lr
  14886. + padd.b r2,r6,pc
  14887. + padd.b r8,r9,r12
  14888. + padd.b r5,r12,r3
  14889. + .text
  14890. + .global psub_b
  14891. +psub_b:
  14892. + psub.b pc,pc,pc
  14893. + psub.b r12,r12,r12
  14894. + psub.b r5,r5,r5
  14895. + psub.b r4,r4,r4
  14896. + psub.b lr,lr,lr
  14897. + psub.b r0,r12,pc
  14898. + psub.b r7,sp,r10
  14899. + psub.b r5,sp,r12
  14900. + .text
  14901. + .global padds_sb
  14902. +padds_sb:
  14903. + padds.sb pc,pc,pc
  14904. + padds.sb r12,r12,r12
  14905. + padds.sb r5,r5,r5
  14906. + padds.sb r4,r4,r4
  14907. + padds.sb lr,lr,lr
  14908. + padds.sb sp,r11,r4
  14909. + padds.sb r11,r10,r11
  14910. + padds.sb r5,r12,r6
  14911. + .text
  14912. + .global psubs_sb
  14913. +psubs_sb:
  14914. + psubs.sb pc,pc,pc
  14915. + psubs.sb r12,r12,r12
  14916. + psubs.sb r5,r5,r5
  14917. + psubs.sb r4,r4,r4
  14918. + psubs.sb lr,lr,lr
  14919. + psubs.sb r7,r6,r8
  14920. + psubs.sb r12,r10,r9
  14921. + psubs.sb pc,r11,r0
  14922. + .text
  14923. + .global padds_ub
  14924. +padds_ub:
  14925. + padds.ub pc,pc,pc
  14926. + padds.ub r12,r12,r12
  14927. + padds.ub r5,r5,r5
  14928. + padds.ub r4,r4,r4
  14929. + padds.ub lr,lr,lr
  14930. + padds.ub r3,r2,r11
  14931. + padds.ub r10,r8,r1
  14932. + padds.ub r11,r8,r10
  14933. + .text
  14934. + .global psubs_ub
  14935. +psubs_ub:
  14936. + psubs.ub pc,pc,pc
  14937. + psubs.ub r12,r12,r12
  14938. + psubs.ub r5,r5,r5
  14939. + psubs.ub r4,r4,r4
  14940. + psubs.ub lr,lr,lr
  14941. + psubs.ub r0,r2,r7
  14942. + psubs.ub lr,r5,r3
  14943. + psubs.ub r6,r7,r9
  14944. + .text
  14945. + .global paddh_ub
  14946. +paddh_ub:
  14947. + paddh.ub pc,pc,pc
  14948. + paddh.ub r12,r12,r12
  14949. + paddh.ub r5,r5,r5
  14950. + paddh.ub r4,r4,r4
  14951. + paddh.ub lr,lr,lr
  14952. + paddh.ub lr,r1,r0
  14953. + paddh.ub r2,r7,r7
  14954. + paddh.ub r2,r1,r2
  14955. + .text
  14956. + .global psubh_ub
  14957. +psubh_ub:
  14958. + psubh.ub pc,pc,pc
  14959. + psubh.ub r12,r12,r12
  14960. + psubh.ub r5,r5,r5
  14961. + psubh.ub r4,r4,r4
  14962. + psubh.ub lr,lr,lr
  14963. + psubh.ub r0,r1,r6
  14964. + psubh.ub r4,lr,r10
  14965. + psubh.ub r9,r8,r1
  14966. + .text
  14967. + .global pmax_ub
  14968. +pmax_ub:
  14969. + pmax.ub pc,pc,pc
  14970. + pmax.ub r12,r12,r12
  14971. + pmax.ub r5,r5,r5
  14972. + pmax.ub r4,r4,r4
  14973. + pmax.ub lr,lr,lr
  14974. + pmax.ub pc,r2,r11
  14975. + pmax.ub r12,r1,r1
  14976. + pmax.ub r5,r2,r0
  14977. + .text
  14978. + .global pmax_sh
  14979. +pmax_sh:
  14980. + pmax.sh pc,pc,pc
  14981. + pmax.sh r12,r12,r12
  14982. + pmax.sh r5,r5,r5
  14983. + pmax.sh r4,r4,r4
  14984. + pmax.sh lr,lr,lr
  14985. + pmax.sh lr,r6,r12
  14986. + pmax.sh r2,pc,r5
  14987. + pmax.sh pc,r2,r7
  14988. + .text
  14989. + .global pmin_ub
  14990. +pmin_ub:
  14991. + pmin.ub pc,pc,pc
  14992. + pmin.ub r12,r12,r12
  14993. + pmin.ub r5,r5,r5
  14994. + pmin.ub r4,r4,r4
  14995. + pmin.ub lr,lr,lr
  14996. + pmin.ub r8,r1,r5
  14997. + pmin.ub r1,r8,r3
  14998. + pmin.ub r0,r2,r7
  14999. + .text
  15000. + .global pmin_sh
  15001. +pmin_sh:
  15002. + pmin.sh pc,pc,pc
  15003. + pmin.sh r12,r12,r12
  15004. + pmin.sh r5,r5,r5
  15005. + pmin.sh r4,r4,r4
  15006. + pmin.sh lr,lr,lr
  15007. + pmin.sh r8,r4,r10
  15008. + pmin.sh lr,r10,r12
  15009. + pmin.sh r2,r6,r2
  15010. + .text
  15011. + .global pavg_ub
  15012. +pavg_ub:
  15013. + pavg.ub pc,pc,pc
  15014. + pavg.ub r12,r12,r12
  15015. + pavg.ub r5,r5,r5
  15016. + pavg.ub r4,r4,r4
  15017. + pavg.ub lr,lr,lr
  15018. + pavg.ub r0,r1,r6
  15019. + pavg.ub r8,r3,r6
  15020. + pavg.ub pc,r12,r10
  15021. + .text
  15022. + .global pavg_sh
  15023. +pavg_sh:
  15024. + pavg.sh pc,pc,pc
  15025. + pavg.sh r12,r12,r12
  15026. + pavg.sh r5,r5,r5
  15027. + pavg.sh r4,r4,r4
  15028. + pavg.sh lr,lr,lr
  15029. + pavg.sh r9,pc,sp
  15030. + pavg.sh pc,sp,r3
  15031. + pavg.sh r6,r1,r9
  15032. + .text
  15033. + .global pabs_sb
  15034. +pabs_sb:
  15035. + pabs.sb pc,pc
  15036. + pabs.sb r12,r12
  15037. + pabs.sb r5,r5
  15038. + pabs.sb r4,r4
  15039. + pabs.sb lr,lr
  15040. + pabs.sb r11,r6
  15041. + pabs.sb lr,r9
  15042. + pabs.sb sp,r7
  15043. + .text
  15044. + .global pabs_sh
  15045. +pabs_sh:
  15046. + pabs.sh pc,pc
  15047. + pabs.sh r12,r12
  15048. + pabs.sh r5,r5
  15049. + pabs.sh r4,r4
  15050. + pabs.sh lr,lr
  15051. + pabs.sh pc,r3
  15052. + pabs.sh r5,r7
  15053. + pabs.sh r4,r0
  15054. + .text
  15055. + .global psad
  15056. +psad:
  15057. + psad pc,pc,pc
  15058. + psad r12,r12,r12
  15059. + psad r5,r5,r5
  15060. + psad r4,r4,r4
  15061. + psad lr,lr,lr
  15062. + psad r9,r11,r11
  15063. + psad lr,r4,sp
  15064. + psad lr,r4,r5
  15065. + .text
  15066. + .global pasr_b
  15067. +pasr_b:
  15068. + pasr.b pc,pc,0
  15069. + pasr.b r12,r12,7
  15070. + pasr.b r5,r5,4
  15071. + pasr.b r4,r4,3
  15072. + pasr.b lr,lr,1
  15073. + pasr.b pc,r7,1
  15074. + pasr.b sp,lr,6
  15075. + pasr.b sp,r3,2
  15076. + .text
  15077. + .global plsl_b
  15078. +plsl_b:
  15079. + plsl.b pc,pc,0
  15080. + plsl.b r12,r12,7
  15081. + plsl.b r5,r5,4
  15082. + plsl.b r4,r4,3
  15083. + plsl.b lr,lr,1
  15084. + plsl.b r2,r11,4
  15085. + plsl.b r8,r5,7
  15086. + plsl.b pc,r0,2
  15087. + .text
  15088. + .global plsr_b
  15089. +plsr_b:
  15090. + plsr.b pc,pc,0
  15091. + plsr.b r12,r12,7
  15092. + plsr.b r5,r5,4
  15093. + plsr.b r4,r4,3
  15094. + plsr.b lr,lr,1
  15095. + plsr.b r12,r1,2
  15096. + plsr.b r6,pc,7
  15097. + plsr.b r12,r11,2
  15098. + .text
  15099. + .global pasr_h
  15100. +pasr_h:
  15101. + pasr.h pc,pc,0
  15102. + pasr.h r12,r12,15
  15103. + pasr.h r5,r5,8
  15104. + pasr.h r4,r4,7
  15105. + pasr.h lr,lr,1
  15106. + pasr.h r0,r11,10
  15107. + pasr.h r4,r6,8
  15108. + pasr.h r6,r2,4
  15109. + .text
  15110. + .global plsl_h
  15111. +plsl_h:
  15112. + plsl.h pc,pc,0
  15113. + plsl.h r12,r12,15
  15114. + plsl.h r5,r5,8
  15115. + plsl.h r4,r4,7
  15116. + plsl.h lr,lr,1
  15117. + plsl.h r5,r10,9
  15118. + plsl.h sp,lr,8
  15119. + plsl.h r0,lr,7
  15120. + .text
  15121. + .global plsr_h
  15122. +plsr_h:
  15123. + plsr.h pc,pc,0
  15124. + plsr.h r12,r12,15
  15125. + plsr.h r5,r5,8
  15126. + plsr.h r4,r4,7
  15127. + plsr.h lr,lr,1
  15128. + plsr.h r11,r0,15
  15129. + plsr.h lr,r3,3
  15130. + plsr.h r8,lr,10
  15131. + .text
  15132. + .global packw_sh
  15133. +packw_sh:
  15134. + packw.sh pc,pc,pc
  15135. + packw.sh r12,r12,r12
  15136. + packw.sh r5,r5,r5
  15137. + packw.sh r4,r4,r4
  15138. + packw.sh lr,lr,lr
  15139. + packw.sh sp,r11,r10
  15140. + packw.sh r8,r2,r12
  15141. + packw.sh r8,r1,r5
  15142. + .text
  15143. + .global punpckub_h
  15144. +punpckub_h:
  15145. + punpckub.h pc,pc:b
  15146. + punpckub.h r12,r12:t
  15147. + punpckub.h r5,r5:t
  15148. + punpckub.h r4,r4:b
  15149. + punpckub.h lr,lr:t
  15150. + punpckub.h r6,r1:t
  15151. + punpckub.h lr,r5:b
  15152. + punpckub.h lr,r2:t
  15153. + .text
  15154. + .global punpcksb_h
  15155. +punpcksb_h:
  15156. + punpcksb.h pc,pc:b
  15157. + punpcksb.h r12,r12:t
  15158. + punpcksb.h r5,r5:t
  15159. + punpcksb.h r4,r4:b
  15160. + punpcksb.h lr,lr:t
  15161. + punpcksb.h r4,r7:t
  15162. + punpcksb.h r6,lr:b
  15163. + punpcksb.h r12,r12:t
  15164. + .text
  15165. + .global packsh_ub
  15166. +packsh_ub:
  15167. + packsh.ub pc,pc,pc
  15168. + packsh.ub r12,r12,r12
  15169. + packsh.ub r5,r5,r5
  15170. + packsh.ub r4,r4,r4
  15171. + packsh.ub lr,lr,lr
  15172. + packsh.ub r3,r6,r3
  15173. + packsh.ub r8,r0,r3
  15174. + packsh.ub r9,r3,lr
  15175. + .text
  15176. + .global packsh_sb
  15177. +packsh_sb:
  15178. + packsh.sb pc,pc,pc
  15179. + packsh.sb r12,r12,r12
  15180. + packsh.sb r5,r5,r5
  15181. + packsh.sb r4,r4,r4
  15182. + packsh.sb lr,lr,lr
  15183. + packsh.sb r6,r8,r1
  15184. + packsh.sb lr,r9,r8
  15185. + packsh.sb sp,r6,r6
  15186. + .text
  15187. + .global andl
  15188. +andl:
  15189. + andl pc,0
  15190. + andl r12,65535
  15191. + andl r5,32768
  15192. + andl r4,32767
  15193. + andl lr,1
  15194. + andl pc,23128
  15195. + andl r8,47262
  15196. + andl r7,13719
  15197. + .text
  15198. + .global andl_coh
  15199. +andl_coh:
  15200. + andl pc,0,COH
  15201. + andl r12,65535,COH
  15202. + andl r5,32768,COH
  15203. + andl r4,32767,COH
  15204. + andl lr,1,COH
  15205. + andl r6,22753,COH
  15206. + andl r0,40653,COH
  15207. + andl r4,48580,COH
  15208. + .text
  15209. + .global andh
  15210. +andh:
  15211. + andh pc,0
  15212. + andh r12,65535
  15213. + andh r5,32768
  15214. + andh r4,32767
  15215. + andh lr,1
  15216. + andh r12,52312
  15217. + andh r3,8675
  15218. + andh r2,42987
  15219. + .text
  15220. + .global andh_coh
  15221. +andh_coh:
  15222. + andh pc,0,COH
  15223. + andh r12,65535,COH
  15224. + andh r5,32768,COH
  15225. + andh r4,32767,COH
  15226. + andh lr,1,COH
  15227. + andh r11,34317,COH
  15228. + andh r8,52982,COH
  15229. + andh r10,23683,COH
  15230. + .text
  15231. + .global orl
  15232. +orl:
  15233. + orl pc,0
  15234. + orl r12,65535
  15235. + orl r5,32768
  15236. + orl r4,32767
  15237. + orl lr,1
  15238. + orl sp,16766
  15239. + orl r0,21181
  15240. + orl pc,44103
  15241. + .text
  15242. + .global orh
  15243. +orh:
  15244. + orh pc,0
  15245. + orh r12,65535
  15246. + orh r5,32768
  15247. + orh r4,32767
  15248. + orh lr,1
  15249. + orh r8,28285
  15250. + orh r12,30492
  15251. + orh r1,59930
  15252. + .text
  15253. + .global eorl
  15254. +eorl:
  15255. + eorl pc,0
  15256. + eorl r12,65535
  15257. + eorl r5,32768
  15258. + eorl r4,32767
  15259. + eorl lr,1
  15260. + eorl r4,51129
  15261. + eorl r6,64477
  15262. + eorl r1,20913
  15263. + .text
  15264. + .global eorh
  15265. +eorh:
  15266. + eorh pc,0
  15267. + eorh r12,65535
  15268. + eorh r5,32768
  15269. + eorh r4,32767
  15270. + eorh lr,1
  15271. + eorh r0,11732
  15272. + eorh r10,38069
  15273. + eorh r9,57130
  15274. + .text
  15275. + .global mcall
  15276. +mcall:
  15277. + mcall pc[0]
  15278. + mcall r12[-4]
  15279. + mcall r5[-131072]
  15280. + mcall r4[131068]
  15281. + mcall lr[4]
  15282. + mcall sp[61180]
  15283. + mcall r4[-35000]
  15284. + mcall r0[9924]
  15285. + .text
  15286. + .global pref
  15287. +pref:
  15288. + pref pc[0]
  15289. + pref r12[-1]
  15290. + pref r5[-32768]
  15291. + pref r4[32767]
  15292. + pref lr[1]
  15293. + pref r7[7748]
  15294. + pref r7[-7699]
  15295. + pref r2[-25892]
  15296. + .text
  15297. + .global cache
  15298. +cache:
  15299. + cache pc[0],0
  15300. + cache r12[-1],31
  15301. + cache r5[-1024],16
  15302. + cache r4[1023],15
  15303. + cache lr[1],1
  15304. + cache r3[-964],17
  15305. + cache r4[-375],22
  15306. + cache r3[-888],17
  15307. + .text
  15308. + .global sub4
  15309. +sub4:
  15310. + sub pc,0
  15311. + sub r12,-1
  15312. + sub r5,-1048576
  15313. + sub r4,1048575
  15314. + sub lr,1
  15315. + sub r2,-619156
  15316. + sub lr,461517
  15317. + sub r8,-185051
  15318. + .text
  15319. + .global cp3
  15320. +cp3:
  15321. + cp pc,0
  15322. + cp r12,-1
  15323. + cp r5,-1048576
  15324. + cp r4,1048575
  15325. + cp lr,1
  15326. + cp r1,124078
  15327. + cp r0,-378909
  15328. + cp r4,-243180
  15329. + .text
  15330. + .global mov2
  15331. +mov2:
  15332. + mov pc,0
  15333. + mov r12,-1
  15334. + mov r5,-1048576
  15335. + mov r4,1048575
  15336. + mov lr,1
  15337. + mov r5,-317021
  15338. + mov sp,-749164
  15339. + mov r5,940179
  15340. + .text
  15341. + .global brc2
  15342. +brc2:
  15343. + breq 0
  15344. + bral -2
  15345. + brls -2097152
  15346. + brpl 2097150
  15347. + brne 2
  15348. + brhi -1796966
  15349. + brqs 1321368
  15350. + brls -577434
  15351. + .text
  15352. + .global rcall2
  15353. +rcall2:
  15354. + rcall 0
  15355. + rcall -2
  15356. + rcall -2097152
  15357. + rcall 2097150
  15358. + rcall 2
  15359. + rcall 496820
  15360. + rcall 1085092
  15361. + rcall -1058
  15362. + .text
  15363. + .global sub5
  15364. +sub5:
  15365. + sub pc,pc,0
  15366. + sub r12,r12,-1
  15367. + sub r5,r5,-32768
  15368. + sub r4,r4,32767
  15369. + sub lr,lr,1
  15370. + sub pc,pc,-12744
  15371. + sub r7,r7,-27365
  15372. + sub r2,r9,-17358
  15373. + .text
  15374. + .global satsub_w2
  15375. +satsub_w2:
  15376. + satsub.w pc,pc,0
  15377. + satsub.w r12,r12,-1
  15378. + satsub.w r5,r5,-32768
  15379. + satsub.w r4,r4,32767
  15380. + satsub.w lr,lr,1
  15381. + satsub.w r2,lr,-2007
  15382. + satsub.w r7,r12,-784
  15383. + satsub.w r4,r7,23180
  15384. + .text
  15385. + .global ld_d4
  15386. +ld_d4:
  15387. + ld.d r0,pc[0]
  15388. + ld.d r14,r12[-1]
  15389. + ld.d r8,r5[-32768]
  15390. + ld.d r6,r4[32767]
  15391. + ld.d r2,lr[1]
  15392. + ld.d r14,r11[14784]
  15393. + ld.d r6,r9[-18905]
  15394. + ld.d r2,r3[-6355]
  15395. + .text
  15396. + .global ld_w4
  15397. +ld_w4:
  15398. + ld.w pc,pc[0]
  15399. + ld.w r12,r12[-1]
  15400. + ld.w r5,r5[-32768]
  15401. + ld.w r4,r4[32767]
  15402. + ld.w lr,lr[1]
  15403. + ld.w r0,r12[-22133]
  15404. + ld.w sp,pc[-20521]
  15405. + /* ld.w r3,r5[29035] */
  15406. + nop
  15407. + .text
  15408. + .global ld_sh4
  15409. +ld_sh4:
  15410. + ld.sh pc,pc[0]
  15411. + ld.sh r12,r12[-1]
  15412. + ld.sh r5,r5[-32768]
  15413. + ld.sh r4,r4[32767]
  15414. + ld.sh lr,lr[1]
  15415. + ld.sh r6,r10[30930]
  15416. + ld.sh r6,r10[21973]
  15417. + /* ld.sh r11,r10[-2058] */
  15418. + nop
  15419. + .text
  15420. + .global ld_uh4
  15421. +ld_uh4:
  15422. + ld.uh pc,pc[0]
  15423. + ld.uh r12,r12[-1]
  15424. + ld.uh r5,r5[-32768]
  15425. + ld.uh r4,r4[32767]
  15426. + ld.uh lr,lr[1]
  15427. + ld.uh r1,r9[-13354]
  15428. + ld.uh lr,r11[21337]
  15429. + /* ld.uh r2,lr[-25370] */
  15430. + nop
  15431. + .text
  15432. + .global ld_sb1
  15433. +ld_sb1:
  15434. + ld.sb pc,pc[0]
  15435. + ld.sb r12,r12[-1]
  15436. + ld.sb r5,r5[-32768]
  15437. + ld.sb r4,r4[32767]
  15438. + ld.sb lr,lr[1]
  15439. + ld.sb r7,sp[-28663]
  15440. + ld.sb r2,r1[-5879]
  15441. + ld.sb r12,r3[18734]
  15442. + .text
  15443. + .global ld_ub4
  15444. +ld_ub4:
  15445. + ld.ub pc,pc[0]
  15446. + ld.ub r12,r12[-1]
  15447. + ld.ub r5,r5[-32768]
  15448. + ld.ub r4,r4[32767]
  15449. + ld.ub lr,lr[1]
  15450. + ld.ub pc,r4[8277]
  15451. + ld.ub r5,r12[19172]
  15452. + ld.ub r10,lr[26347]
  15453. + .text
  15454. + .global st_d4
  15455. +st_d4:
  15456. + st.d pc[0],r0
  15457. + st.d r12[-1],r14
  15458. + st.d r5[-32768],r8
  15459. + st.d r4[32767],r6
  15460. + st.d lr[1],r2
  15461. + st.d r5[13200],r10
  15462. + st.d r5[9352],r10
  15463. + st.d r5[32373],r4
  15464. + .text
  15465. + .global st_w4
  15466. +st_w4:
  15467. + st.w pc[0],pc
  15468. + st.w r12[-1],r12
  15469. + st.w r5[-32768],r5
  15470. + st.w r4[32767],r4
  15471. + st.w lr[1],lr
  15472. + st.w sp[6136],r7
  15473. + st.w r6[27087],r12
  15474. + /* st.w r3[20143],r7 */
  15475. + nop
  15476. + .text
  15477. + .global st_h4
  15478. +st_h4:
  15479. + st.h pc[0],pc
  15480. + st.h r12[-1],r12
  15481. + st.h r5[-32768],r5
  15482. + st.h r4[32767],r4
  15483. + st.h lr[1],lr
  15484. + st.h r4[-9962],r7
  15485. + st.h r9[-16250],r3
  15486. + /* st.h r8[-28810],r7 */
  15487. + nop
  15488. + .text
  15489. + .global st_b4
  15490. +st_b4:
  15491. + st.b pc[0],pc
  15492. + st.b r12[-1],r12
  15493. + st.b r5[-32768],r5
  15494. + st.b r4[32767],r4
  15495. + st.b lr[1],lr
  15496. + st.b r12[30102],r6
  15497. + st.b r5[28977],r1
  15498. + st.b r0[5470],r1
  15499. + .text
  15500. + .global mfsr
  15501. +mfsr:
  15502. + mfsr pc,0
  15503. + mfsr r12,1020
  15504. + mfsr r5,512
  15505. + mfsr r4,508
  15506. + mfsr lr,4
  15507. + mfsr r2,696
  15508. + mfsr r4,260
  15509. + mfsr r10,1016
  15510. + .text
  15511. + .global mtsr
  15512. +mtsr:
  15513. + mtsr 0,pc
  15514. + mtsr 1020,r12
  15515. + mtsr 512,r5
  15516. + mtsr 508,r4
  15517. + mtsr 4,lr
  15518. + mtsr 224,r10
  15519. + mtsr 836,r12
  15520. + mtsr 304,r9
  15521. + .text
  15522. + .global mfdr
  15523. +mfdr:
  15524. + mfdr pc,0
  15525. + mfdr r12,1020
  15526. + mfdr r5,512
  15527. + mfdr r4,508
  15528. + mfdr lr,4
  15529. + mfdr r6,932
  15530. + mfdr r5,36
  15531. + mfdr r9,300
  15532. + .text
  15533. + .global mtdr
  15534. +mtdr:
  15535. + mtdr 0,pc
  15536. + mtdr 1020,r12
  15537. + mtdr 512,r5
  15538. + mtdr 508,r4
  15539. + mtdr 4,lr
  15540. + mtdr 180,r8
  15541. + mtdr 720,r10
  15542. + mtdr 408,lr
  15543. + .text
  15544. + .global sleep
  15545. +sleep:
  15546. + sleep 0
  15547. + sleep 255
  15548. + sleep 128
  15549. + sleep 127
  15550. + sleep 1
  15551. + sleep 254
  15552. + sleep 15
  15553. + sleep 43
  15554. + .text
  15555. + .global sync
  15556. +sync:
  15557. + sync 0
  15558. + sync 255
  15559. + sync 128
  15560. + sync 127
  15561. + sync 1
  15562. + sync 166
  15563. + sync 230
  15564. + sync 180
  15565. + .text
  15566. + .global bld
  15567. +bld:
  15568. + bld pc,0
  15569. + bld r12,31
  15570. + bld r5,16
  15571. + bld r4,15
  15572. + bld lr,1
  15573. + bld r9,15
  15574. + bld r0,4
  15575. + bld lr,26
  15576. + .text
  15577. + .global bst
  15578. +bst:
  15579. + bst pc,0
  15580. + bst r12,31
  15581. + bst r5,16
  15582. + bst r4,15
  15583. + bst lr,1
  15584. + bst r10,28
  15585. + bst r0,3
  15586. + bst sp,2
  15587. + .text
  15588. + .global sats
  15589. +sats:
  15590. + sats pc>>0,0
  15591. + sats r12>>31,31
  15592. + sats r5>>16,16
  15593. + sats r4>>15,15
  15594. + sats lr>>1,1
  15595. + sats r10>>3,19
  15596. + sats r10>>2,26
  15597. + sats r1>>20,1
  15598. + .text
  15599. + .global satu
  15600. +satu:
  15601. + satu pc>>0,0
  15602. + satu r12>>31,31
  15603. + satu r5>>16,16
  15604. + satu r4>>15,15
  15605. + satu lr>>1,1
  15606. + satu pc>>5,7
  15607. + satu r7>>5,5
  15608. + satu r2>>26,19
  15609. + .text
  15610. + .global satrnds
  15611. +satrnds:
  15612. + satrnds pc>>0,0
  15613. + satrnds r12>>31,31
  15614. + satrnds r5>>16,16
  15615. + satrnds r4>>15,15
  15616. + satrnds lr>>1,1
  15617. + satrnds r0>>21,19
  15618. + satrnds sp>>0,2
  15619. + satrnds r7>>6,29
  15620. + .text
  15621. + .global satrndu
  15622. +satrndu:
  15623. + satrndu pc>>0,0
  15624. + satrndu r12>>31,31
  15625. + satrndu r5>>16,16
  15626. + satrndu r4>>15,15
  15627. + satrndu lr>>1,1
  15628. + satrndu r12>>0,26
  15629. + satrndu r4>>21,3
  15630. + satrndu r10>>3,16
  15631. + .text
  15632. + .global subfc
  15633. +subfc:
  15634. + subfeq pc,0
  15635. + subfal r12,-1
  15636. + subfls r5,-128
  15637. + subfpl r4,127
  15638. + subfne lr,1
  15639. + subfls r10,8
  15640. + subfvc r11,99
  15641. + subfvs r2,73
  15642. + .text
  15643. + .global subc
  15644. +subc:
  15645. + subeq pc,0
  15646. + subal r12,-1
  15647. + subls r5,-128
  15648. + subpl r4,127
  15649. + subne lr,1
  15650. + subls r12,118
  15651. + subvc lr,-12
  15652. + submi r4,-13
  15653. + .text
  15654. + .global movc2
  15655. +movc2:
  15656. + moveq pc,0
  15657. + moval r12,-1
  15658. + movls r5,-128
  15659. + movpl r4,127
  15660. + movne lr,1
  15661. + movlt r3,-122
  15662. + movvc r8,2
  15663. + movne r7,-111
  15664. + .text
  15665. + .global cp_b
  15666. +cp_b:
  15667. + cp.b pc,r0
  15668. + cp.b r0,pc
  15669. + cp.b r7,r8
  15670. + cp.b r8,r7
  15671. + .text
  15672. + .global cp_h
  15673. +cp_h:
  15674. + cp.h pc,r0
  15675. + cp.h r0,pc
  15676. + cp.h r7,r8
  15677. + cp.h r8,r7
  15678. + .text
  15679. + .global ldm
  15680. +ldm:
  15681. + ldm pc,r1-r6
  15682. + ldm r12,r0-r15
  15683. + ldm r5,r15
  15684. + ldm r4,r0-r14
  15685. + ldm lr,r0
  15686. + ldm r9,r1,r5,r14
  15687. + ldm r11,r2-r3,r5-r8,r15
  15688. + ldm r6,r0,r3,r9,r13,r15
  15689. + .text
  15690. + .global ldm_pu
  15691. +ldm_pu:
  15692. + ldm pc++,r6-r9
  15693. + ldm r12++,r0-r15
  15694. + ldm r5++,r15
  15695. + ldm r4++,r0-r14
  15696. + ldm lr++,r0
  15697. + ldm r12++,r3-r5,r8,r10,r12,r14-r15
  15698. + ldm r10++,r2,r4-r6,r14-r15
  15699. + ldm r6++,r1,r3-r4,r9-r14
  15700. + .text
  15701. + .global ldmts
  15702. +ldmts:
  15703. + ldmts pc,r7-r8
  15704. + ldmts r12,r0-r15
  15705. + ldmts r5,r15
  15706. + ldmts r4,r0-r14
  15707. + ldmts lr,r0
  15708. + ldmts r0,r1-r2,r11-r12
  15709. + ldmts lr,r0-r2,r4,r7-r8,r13-r14
  15710. + ldmts r12,r0-r1,r3-r5,r9,r14-r15
  15711. + .text
  15712. + .global ldmts_pu
  15713. +ldmts_pu:
  15714. + ldmts pc++,r9
  15715. + ldmts r12++,r0-r15
  15716. + ldmts r5++,r15
  15717. + ldmts r4++,r0-r14
  15718. + ldmts lr++,r0
  15719. + ldmts sp++,r0,r2-r5,r7,r9,r11
  15720. + ldmts r5++,r1-r3,r7,r10-r11
  15721. + ldmts r8++,r2-r4,r7-r8,r13,r15
  15722. + .text
  15723. + .global stm
  15724. +stm:
  15725. + stm pc,r7
  15726. + stm r12,r0-r15
  15727. + stm r5,r15
  15728. + stm r4,r0-r14
  15729. + stm lr,r0
  15730. + stm sp,r2-r3,r5,r8,r11,r14
  15731. + stm r4,r0-r4,r6,r10-r11,r14
  15732. + stm r9,r1,r5,r9,r12-r15
  15733. + .text
  15734. + .global stm_pu
  15735. +stm_pu:
  15736. + stm --pc,r4-r6
  15737. + stm --r12,r0-r15
  15738. + stm --r5,r15
  15739. + stm --r4,r0-r14
  15740. + stm --lr,r0
  15741. + stm --r11,r0,r4-r9,r11-r15
  15742. + stm --r11,r0,r3,r9-r10,r12,r14
  15743. + stm --r6,r2,r8-r9,r13-r14
  15744. + .text
  15745. + .global stmts
  15746. +stmts:
  15747. + stmts pc,r8
  15748. + stmts r12,r0-r15
  15749. + stmts r5,r15
  15750. + stmts r4,r0-r14
  15751. + stmts lr,r0
  15752. + stmts r1,r0-r1,r3-r4,r6,r9-r10,r14-r15
  15753. + stmts r3,r0,r6-r8,r10-r12
  15754. + stmts r11,r0,r4,r6-r7,r9-r10,r12,r14-r15
  15755. + .text
  15756. + .global stmts_pu
  15757. +stmts_pu:
  15758. + stmts --pc,r6-r8
  15759. + stmts --r12,r0-r15
  15760. + stmts --r5,r15
  15761. + stmts --r4,r0-r14
  15762. + stmts --lr,r0
  15763. + stmts --r2,r0,r3-r4,r9-r10,r12-r13
  15764. + stmts --r3,r0-r1,r14-r15
  15765. + stmts --r0,r0,r2-r6,r10,r14
  15766. + .text
  15767. + .global ldins_h
  15768. +ldins_h:
  15769. + ldins.h pc:b,pc[0]
  15770. + ldins.h r12:t,r12[-2]
  15771. + ldins.h r5:t,r5[-4096]
  15772. + ldins.h r4:b,r4[4094]
  15773. + ldins.h lr:t,lr[2]
  15774. + ldins.h r0:t,lr[1930]
  15775. + ldins.h r3:b,r7[-534]
  15776. + ldins.h r2:b,r12[-2252]
  15777. + .text
  15778. + .global ldins_b
  15779. +ldins_b:
  15780. + ldins.b pc:b,pc[0]
  15781. + ldins.b r12:t,r12[-1]
  15782. + ldins.b r5:u,r5[-2048]
  15783. + ldins.b r4:l,r4[2047]
  15784. + ldins.b lr:l,lr[1]
  15785. + ldins.b r6:t,r4[-662]
  15786. + ldins.b r5:b,r1[-151]
  15787. + ldins.b r10:t,r11[-1923]
  15788. + .text
  15789. + .global ldswp_sh
  15790. +ldswp_sh:
  15791. + ldswp.sh pc,pc[0]
  15792. + ldswp.sh r12,r12[-2]
  15793. + ldswp.sh r5,r5[-4096]
  15794. + ldswp.sh r4,r4[4094]
  15795. + ldswp.sh lr,lr[2]
  15796. + ldswp.sh r9,r10[3848]
  15797. + ldswp.sh r4,r12[-2040]
  15798. + ldswp.sh r10,r2[3088]
  15799. + .text
  15800. + .global ldswp_uh
  15801. +ldswp_uh:
  15802. + ldswp.uh pc,pc[0]
  15803. + ldswp.uh r12,r12[-2]
  15804. + ldswp.uh r5,r5[-4096]
  15805. + ldswp.uh r4,r4[4094]
  15806. + ldswp.uh lr,lr[2]
  15807. + ldswp.uh r4,r9[3724]
  15808. + ldswp.uh lr,sp[-1672]
  15809. + ldswp.uh r8,r12[-3846]
  15810. + .text
  15811. + .global ldswp_w
  15812. +ldswp_w:
  15813. + ldswp.w pc,pc[0]
  15814. + ldswp.w r12,r12[-4]
  15815. + ldswp.w r5,r5[-8192]
  15816. + ldswp.w r4,r4[8188]
  15817. + ldswp.w lr,lr[4]
  15818. + ldswp.w sp,r7[1860]
  15819. + ldswp.w pc,r5[-3324]
  15820. + ldswp.w r12,r10[-3296]
  15821. + .text
  15822. + .global stswp_h
  15823. +stswp_h:
  15824. + stswp.h pc[0],pc
  15825. + stswp.h r12[-2],r12
  15826. + stswp.h r5[-4096],r5
  15827. + stswp.h r4[4094],r4
  15828. + stswp.h lr[2],lr
  15829. + stswp.h r7[64],r10
  15830. + stswp.h r10[3024],r2
  15831. + stswp.h r0[-2328],r10
  15832. + .text
  15833. + .global stswp_w
  15834. +stswp_w:
  15835. + stswp.w pc[0],pc
  15836. + stswp.w r12[-4],r12
  15837. + stswp.w r5[-8192],r5
  15838. + stswp.w r4[8188],r4
  15839. + stswp.w lr[4],lr
  15840. + stswp.w pc[1156],r8
  15841. + stswp.w sp[7992],r10
  15842. + stswp.w r8[-1172],r5
  15843. + .text
  15844. + .global and2
  15845. +and2:
  15846. + and pc,pc,pc<<0
  15847. + and r12,r12,r12<<31
  15848. + and r5,r5,r5<<16
  15849. + and r4,r4,r4<<15
  15850. + and lr,lr,lr<<1
  15851. + and r10,r2,r1<<1
  15852. + and r12,r8,r11<<27
  15853. + and r10,r7,r0<<3
  15854. + .text
  15855. + .global and3
  15856. +and3:
  15857. + and pc,pc,pc>>0
  15858. + and r12,r12,r12>>31
  15859. + and r5,r5,r5>>16
  15860. + and r4,r4,r4>>15
  15861. + and lr,lr,lr>>1
  15862. + and r12,r8,r7>>17
  15863. + and pc,r4,r9>>20
  15864. + and r10,r9,r10>>12
  15865. + .text
  15866. + .global or2
  15867. +or2:
  15868. + or pc,pc,pc<<0
  15869. + or r12,r12,r12<<31
  15870. + or r5,r5,r5<<16
  15871. + or r4,r4,r4<<15
  15872. + or lr,lr,lr<<1
  15873. + or r8,sp,r11<<29
  15874. + or pc,r9,r2<<28
  15875. + or r5,r1,r2<<3
  15876. + .text
  15877. + .global or3
  15878. +or3:
  15879. + or pc,pc,pc>>0
  15880. + or r12,r12,r12>>31
  15881. + or r5,r5,r5>>16
  15882. + or r4,r4,r4>>15
  15883. + or lr,lr,lr>>1
  15884. + or r1,sp,sp>>2
  15885. + or r0,r1,r1>>29
  15886. + or r4,r12,r8>>8
  15887. + .text
  15888. + .global eor2
  15889. +eor2:
  15890. + eor pc,pc,pc<<0
  15891. + eor r12,r12,r12<<31
  15892. + eor r5,r5,r5<<16
  15893. + eor r4,r4,r4<<15
  15894. + eor lr,lr,lr<<1
  15895. + eor r10,r9,r4<<11
  15896. + eor r4,r0,r1<<31
  15897. + eor r6,r2,r12<<13
  15898. + .text
  15899. + .global eor3
  15900. +eor3:
  15901. + eor pc,pc,pc>>0
  15902. + eor r12,r12,r12>>31
  15903. + eor r5,r5,r5>>16
  15904. + eor r4,r4,r4>>15
  15905. + eor lr,lr,lr>>1
  15906. + eor r5,r5,r5>>22
  15907. + eor r10,r1,lr>>3
  15908. + eor r7,lr,sp>>26
  15909. + .text
  15910. + .global sthh_w2
  15911. +sthh_w2:
  15912. + sthh.w pc[pc<<0],pc:b,pc:b
  15913. + sthh.w r12[r12<<3],r12:t,r12:t
  15914. + sthh.w r5[r5<<2],r5:t,r5:t
  15915. + sthh.w r4[r4<<1],r4:b,r4:b
  15916. + sthh.w lr[lr<<1],lr:t,lr:t
  15917. + sthh.w sp[r6<<3],r1:t,r12:t
  15918. + sthh.w r6[r6<<0],r9:t,r9:t
  15919. + sthh.w r10[r3<<0],r0:b,r11:t
  15920. + .text
  15921. + .global sthh_w1
  15922. +sthh_w1:
  15923. + sthh.w pc[0],pc:b,pc:b
  15924. + sthh.w r12[1020],r12:t,r12:t
  15925. + sthh.w r5[512],r5:t,r5:t
  15926. + sthh.w r4[508],r4:b,r4:b
  15927. + sthh.w lr[4],lr:t,lr:t
  15928. + sthh.w r4[404],r9:t,r0:b
  15929. + sthh.w r8[348],r2:t,r10:b
  15930. + sthh.w sp[172],r9:b,r2:b
  15931. + .text
  15932. + .global cop
  15933. +cop:
  15934. + cop cp0,cr0,cr0,cr0,0
  15935. + cop cp7,cr15,cr15,cr15,0x7f
  15936. + cop cp3,cr5,cr5,cr5,0x31
  15937. + cop cp2,cr4,cr4,cr4,0x30
  15938. + cop cp5,cr8,cr3,cr7,0x5a
  15939. + .text
  15940. + .global ldc_w1
  15941. +ldc_w1:
  15942. + ldc.w cp0,cr0,r0[0]
  15943. + ldc.w cp7,cr15,pc[255<<2]
  15944. + ldc.w cp3,cr5,r5[128<<2]
  15945. + ldc.w cp2,cr4,r4[127<<2]
  15946. + ldc.w cp4,cr9,r13[36<<2]
  15947. + .text
  15948. + .global ldc_w2
  15949. +ldc_w2:
  15950. + ldc.w cp0,cr0,--r0
  15951. + ldc.w cp7,cr15,--pc
  15952. + ldc.w cp3,cr5,--r5
  15953. + ldc.w cp2,cr4,--r4
  15954. + ldc.w cp4,cr9,--r13
  15955. + .text
  15956. + .global ldc_w3
  15957. +ldc_w3:
  15958. + ldc.w cp0,cr0,r0[r0]
  15959. + ldc.w cp7,cr15,pc[pc<<3]
  15960. + ldc.w cp3,cr5,r5[r4<<2]
  15961. + ldc.w cp2,cr4,r4[r3<<1]
  15962. + ldc.w cp4,cr9,r13[r12<<0]
  15963. + .text
  15964. + .global ldc_d1
  15965. +ldc_d1:
  15966. + ldc.d cp0,cr0,r0[0]
  15967. + ldc.d cp7,cr14,pc[255<<2]
  15968. + ldc.d cp3,cr6,r5[128<<2]
  15969. + ldc.d cp2,cr4,r4[127<<2]
  15970. + ldc.d cp4,cr8,r13[36<<2]
  15971. + .text
  15972. + .global ldc_d2
  15973. +ldc_d2:
  15974. + ldc.d cp0,cr0,--r0
  15975. + ldc.d cp7,cr14,--pc
  15976. + ldc.d cp3,cr6,--r5
  15977. + ldc.d cp2,cr4,--r4
  15978. + ldc.d cp4,cr8,--r13
  15979. + .text
  15980. + .global ldc_d3
  15981. +ldc_d3:
  15982. + ldc.d cp0,cr0,r0[r0]
  15983. + ldc.d cp7,cr14,pc[pc<<3]
  15984. + ldc.d cp3,cr6,r5[r4<<2]
  15985. + ldc.d cp2,cr4,r4[r3<<1]
  15986. + ldc.d cp4,cr8,r13[r12<<0]
  15987. + .text
  15988. + .global stc_w1
  15989. +stc_w1:
  15990. + stc.w cp0,r0[0],cr0
  15991. + stc.w cp7,pc[255<<2],cr15
  15992. + stc.w cp3,r5[128<<2],cr5
  15993. + stc.w cp2,r4[127<<2],cr4
  15994. + stc.w cp4,r13[36<<2],cr9
  15995. + .text
  15996. + .global stc_w2
  15997. +stc_w2:
  15998. + stc.w cp0,r0++,cr0
  15999. + stc.w cp7,pc++,cr15
  16000. + stc.w cp3,r5++,cr5
  16001. + stc.w cp2,r4++,cr4
  16002. + stc.w cp4,r13++,cr9
  16003. + .text
  16004. + .global stc_w3
  16005. +stc_w3:
  16006. + stc.w cp0,r0[r0],cr0
  16007. + stc.w cp7,pc[pc<<3],cr15
  16008. + stc.w cp3,r5[r4<<2],cr5
  16009. + stc.w cp2,r4[r3<<1],cr4
  16010. + stc.w cp4,r13[r12<<0],cr9
  16011. + .text
  16012. + .global stc_d1
  16013. +stc_d1:
  16014. + stc.d cp0,r0[0],cr0
  16015. + stc.d cp7,pc[255<<2],cr14
  16016. + stc.d cp3,r5[128<<2],cr6
  16017. + stc.d cp2,r4[127<<2],cr4
  16018. + stc.d cp4,r13[36<<2],cr8
  16019. + .text
  16020. + .global stc_d2
  16021. +stc_d2:
  16022. + stc.d cp0,r0++,cr0
  16023. + stc.d cp7,pc++,cr14
  16024. + stc.d cp3,r5++,cr6
  16025. + stc.d cp2,r4++,cr4
  16026. + stc.d cp4,r13++,cr8
  16027. + .text
  16028. + .global stc_d3
  16029. +stc_d3:
  16030. + stc.d cp0,r0[r0],cr0
  16031. + stc.d cp7,pc[pc<<3],cr14
  16032. + stc.d cp3,r5[r4<<2],cr6
  16033. + stc.d cp2,r4[r3<<1],cr4
  16034. + stc.d cp4,r13[r12<<0],cr8
  16035. + .text
  16036. + .global ldc0_w
  16037. +ldc0_w:
  16038. + ldc0.w cr0,r0[0]
  16039. + ldc0.w cr15,pc[4095<<2]
  16040. + ldc0.w cr5,r5[2048<<2]
  16041. + ldc0.w cr4,r4[2047<<2]
  16042. + ldc0.w cr9,r13[147<<2]
  16043. + .text
  16044. + .global ldc0_d
  16045. +ldc0_d:
  16046. + ldc0.d cr0,r0[0]
  16047. + ldc0.d cr14,pc[4095<<2]
  16048. + ldc0.d cr6,r5[2048<<2]
  16049. + ldc0.d cr4,r4[2047<<2]
  16050. + ldc0.d cr8,r13[147<<2]
  16051. + .text
  16052. + .global stc0_w
  16053. +stc0_w:
  16054. + stc0.w r0[0],cr0
  16055. + stc0.w pc[4095<<2],cr15
  16056. + stc0.w r5[2048<<2],cr5
  16057. + stc0.w r4[2047<<2],cr4
  16058. + stc0.w r13[147<<2],cr9
  16059. + .text
  16060. + .global stc0_d
  16061. +stc0_d:
  16062. + stc0.d r0[0],cr0
  16063. + stc0.d pc[4095<<2],cr14
  16064. + stc0.d r5[2048<<2],cr6
  16065. + stc0.d r4[2047<<2],cr4
  16066. + stc0.d r13[147<<2],cr8
  16067. + .text
  16068. + .global memc
  16069. +memc:
  16070. + memc 0, 0
  16071. + memc -4, 31
  16072. + memc -65536, 16
  16073. + memc 65532, 15
  16074. + .text
  16075. + .global mems
  16076. +mems:
  16077. + mems 0, 0
  16078. + mems -4, 31
  16079. + mems -65536, 16
  16080. + mems 65532, 15
  16081. + .text
  16082. + .global memt
  16083. +memt:
  16084. + memt 0, 0
  16085. + memt -4, 31
  16086. + memt -65536, 16
  16087. + memt 65532, 15
  16088. +
  16089. + .text
  16090. + .global stcond
  16091. +stcond:
  16092. + stcond r0[0], r0
  16093. + stcond pc[-1], pc
  16094. + stcond r8[-32768], r7
  16095. + stcond r7[32767], r8
  16096. + stcond r5[0x1234], r10
  16097. +
  16098. +ldcm_w:
  16099. + ldcm.w cp0,pc,cr0-cr7
  16100. + ldcm.w cp7,r0,cr0
  16101. + ldcm.w cp4,r4++,cr0-cr6
  16102. + ldcm.w cp3,r7,cr7
  16103. + ldcm.w cp1,r12++,cr1,cr4-cr6
  16104. + ldcm.w cp0,pc,cr8-cr15
  16105. + ldcm.w cp7,r0,cr8
  16106. + ldcm.w cp4,r4++,cr8-cr14
  16107. + ldcm.w cp3,r7,cr15
  16108. + ldcm.w cp1,r12++,cr9,cr12-cr14
  16109. +
  16110. +ldcm_d:
  16111. + ldcm.d cp0,pc,cr0-cr15
  16112. + ldcm.d cp7,r0,cr0,cr1
  16113. + ldcm.d cp4,r4++,cr0-cr13
  16114. + ldcm.d cp3,r7,cr14-cr15
  16115. + ldcm.d cp2,r12++,cr0-cr3,cr8-cr9,cr14-cr15
  16116. +
  16117. +stcm_w:
  16118. + stcm.w cp0,pc,cr0-cr7
  16119. + stcm.w cp7,r0,cr0
  16120. + stcm.w cp4,--r4,cr0-cr6
  16121. + stcm.w cp3,r7,cr7
  16122. + stcm.w cp1,--r12,cr1,cr4-cr6
  16123. + stcm.w cp0,pc,cr8-cr15
  16124. + stcm.w cp7,r0,cr8
  16125. + stcm.w cp4,--r4,cr8-cr14
  16126. + stcm.w cp3,r7,cr15
  16127. + stcm.w cp1,--r12,cr9,cr12-cr14
  16128. +
  16129. +stcm_d:
  16130. + stcm.d cp0,pc,cr0-cr15
  16131. + stcm.d cp7,r0,cr0,cr1
  16132. + stcm.d cp4,--r4,cr0-cr13
  16133. + stcm.d cp3,r7,cr14-cr15
  16134. + stcm.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
  16135. +
  16136. +mvcr_w:
  16137. + mvcr.w cp7,pc,cr15
  16138. + mvcr.w cp0,r0,cr0
  16139. + mvcr.w cp0,pc,cr15
  16140. + mvcr.w cp7,r0,cr15
  16141. + mvcr.w cp7,pc,cr0
  16142. + mvcr.w cp4,r7,cr8
  16143. + mvcr.w cp3,r8,cr7
  16144. +
  16145. +mvcr_d:
  16146. + mvcr.d cp7,lr,cr14
  16147. + mvcr.d cp0,r0,cr0
  16148. + mvcr.d cp0,lr,cr14
  16149. + mvcr.d cp7,r0,cr14
  16150. + mvcr.d cp7,lr,cr0
  16151. + mvcr.d cp4,r6,cr8
  16152. + mvcr.d cp3,r8,cr6
  16153. +
  16154. +mvrc_w:
  16155. + mvrc.w cp7,cr15,pc
  16156. + mvrc.w cp0,cr0,r0
  16157. + mvrc.w cp0,cr15,pc
  16158. + mvrc.w cp7,cr15,r0
  16159. + mvrc.w cp7,cr0,pc
  16160. + mvrc.w cp4,cr8,r7
  16161. + mvrc.w cp3,cr7,r8
  16162. +
  16163. +mvrc_d:
  16164. + mvrc.d cp7,cr14,lr
  16165. + mvrc.d cp0,cr0,r0
  16166. + mvrc.d cp0,cr14,lr
  16167. + mvrc.d cp7,cr14,r0
  16168. + mvrc.d cp7,cr0,lr
  16169. + mvrc.d cp4,cr8,r6
  16170. + mvrc.d cp3,cr6,r8
  16171. +
  16172. +bfexts:
  16173. + bfexts pc,pc,31,31
  16174. + bfexts r0,r0,0,0
  16175. + bfexts r0,pc,31,31
  16176. + bfexts pc,r0,31,31
  16177. + bfexts pc,pc,0,31
  16178. + bfexts pc,pc,31,0
  16179. + bfexts r7,r8,15,16
  16180. + bfexts r8,r7,16,15
  16181. +
  16182. +bfextu:
  16183. + bfextu pc,pc,31,31
  16184. + bfextu r0,r0,0,0
  16185. + bfextu r0,pc,31,31
  16186. + bfextu pc,r0,31,31
  16187. + bfextu pc,pc,0,31
  16188. + bfextu pc,pc,31,0
  16189. + bfextu r7,r8,15,16
  16190. + bfextu r8,r7,16,15
  16191. +
  16192. +bfins:
  16193. + bfins pc,pc,31,31
  16194. + bfins r0,r0,0,0
  16195. + bfins r0,pc,31,31
  16196. + bfins pc,r0,31,31
  16197. + bfins pc,pc,0,31
  16198. + bfins pc,pc,31,0
  16199. + bfins r7,r8,15,16
  16200. + bfins r8,r7,16,15
  16201. +
  16202. +rsubc:
  16203. + rsubeq pc,0
  16204. + rsubal r12,-1
  16205. + rsubls r5,-128
  16206. + rsubpl r4,127
  16207. + rsubne lr,1
  16208. + rsubls r12,118
  16209. + rsubvc lr,-12
  16210. + rsubmi r4,-13
  16211. +
  16212. +addc:
  16213. + addeq pc,pc,pc
  16214. + addal r12,r12,r12
  16215. + addls r5,r5,r5
  16216. + addpl r4,r4,r4
  16217. + addne lr,lr,lr
  16218. + addls r10,r2,r1
  16219. + addvc r12,r8,r11
  16220. + addmi r10,r7,r0
  16221. +
  16222. +subc2:
  16223. + subeq pc,pc,pc
  16224. + subal r12,r12,r12
  16225. + subls r5,r5,r5
  16226. + subpl r4,r4,r4
  16227. + subne lr,lr,lr
  16228. + subls r10,r2,r1
  16229. + subvc r12,r8,r11
  16230. + submi r10,r7,r0
  16231. +
  16232. +andc:
  16233. + andeq pc,pc,pc
  16234. + andal r12,r12,r12
  16235. + andls r5,r5,r5
  16236. + andpl r4,r4,r4
  16237. + andne lr,lr,lr
  16238. + andls r10,r2,r1
  16239. + andvc r12,r8,r11
  16240. + andmi r10,r7,r0
  16241. +
  16242. +orc:
  16243. + oreq pc,pc,pc
  16244. + oral r12,r12,r12
  16245. + orls r5,r5,r5
  16246. + orpl r4,r4,r4
  16247. + orne lr,lr,lr
  16248. + orls r10,r2,r1
  16249. + orvc r12,r8,r11
  16250. + ormi r10,r7,r0
  16251. +
  16252. +eorc:
  16253. + eoreq pc,pc,pc
  16254. + eoral r12,r12,r12
  16255. + eorls r5,r5,r5
  16256. + eorpl r4,r4,r4
  16257. + eorne lr,lr,lr
  16258. + eorls r10,r2,r1
  16259. + eorvc r12,r8,r11
  16260. + eormi r10,r7,r0
  16261. +
  16262. +ldcond:
  16263. + ld.weq pc,pc[2044]
  16264. + ld.shal r12,r12[1022]
  16265. + ld.uhls r5,r5[0]
  16266. + ld.ubpl r4,r4[511]
  16267. + ld.sbne lr,lr[0]
  16268. + ld.wls r10,r2[0]
  16269. + ld.shvc r12,r8[0x3fe]
  16270. + ld.ubmi r10,r7[1]
  16271. +
  16272. +stcond2:
  16273. + st.weq pc[2044],pc
  16274. + st.hal r12[1022],r12
  16275. + st.hls r5[0],r5
  16276. + st.bpl r4[511],r4
  16277. + st.bne lr[0],lr
  16278. + st.wls r2[0],r10
  16279. + st.hvc r8[0x3fe],r12
  16280. + st.bmi r7[1],r10
  16281. +
  16282. +movh:
  16283. + movh pc, 65535
  16284. + movh r0, 0
  16285. + movh r5, 1
  16286. + movh r12, 32767
  16287. +
  16288. +
  16289. --- /dev/null
  16290. +++ b/gas/testsuite/gas/avr32/avr32.exp
  16291. @@ -0,0 +1,23 @@
  16292. +# AVR32 assembler testsuite. -*- Tcl -*-
  16293. +
  16294. +if [istarget avr32-*-*] {
  16295. + run_dump_test "hwrd-lwrd"
  16296. + run_dump_test "pcrel"
  16297. + run_dump_test "aliases"
  16298. + run_dump_test "dwarf2"
  16299. + run_dump_test "pic_reloc"
  16300. + run_dump_test "fpinsn"
  16301. + run_dump_test "pico"
  16302. + run_dump_test "lda_pic"
  16303. + run_dump_test "lda_pic_linkrelax"
  16304. + run_dump_test "lda_nopic"
  16305. + run_dump_test "lda_nopic_linkrelax"
  16306. + run_dump_test "call_pic"
  16307. + run_dump_test "call_pic_linkrelax"
  16308. + run_dump_test "call_nopic"
  16309. + run_dump_test "call_nopic_linkrelax"
  16310. + run_dump_test "jmptable"
  16311. + run_dump_test "jmptable_linkrelax"
  16312. + run_dump_test "symdiff"
  16313. + run_dump_test "symdiff_linkrelax"
  16314. +}
  16315. --- /dev/null
  16316. +++ b/gas/testsuite/gas/avr32/call_nopic.d
  16317. @@ -0,0 +1,36 @@
  16318. +#source: call.s
  16319. +#as:
  16320. +#objdump: -dr
  16321. +#name: call_nopic
  16322. +
  16323. +.*: +file format .*
  16324. +
  16325. +Disassembly of section \.text:
  16326. +
  16327. +00000000 <call_test>:
  16328. + 0: d7 03 nop
  16329. +
  16330. +00000002 <toofar_negative>:
  16331. + \.\.\.
  16332. + 1ffffe: 00 00 add r0,r0
  16333. + 200000: f0 a0 00 00 rcall 0 <call_test>
  16334. + 200004: f0 1f 00 0c mcall 200034 <toofar_negative\+0x200032>
  16335. + 200008: f0 1f 00 0c mcall 200038 <toofar_negative\+0x200036>
  16336. + 20000c: f0 1f 00 0c mcall 20003c <toofar_negative\+0x20003a>
  16337. + 200010: f0 1f 00 0c mcall 200040 <toofar_negative\+0x20003e>
  16338. + \.\.\.
  16339. + 200030: ee b0 ff ff rcall 40002e <far_positive>
  16340. + \.\.\.
  16341. + 200034: R_AVR32_32_CPENT \.text\+0x2
  16342. + 200038: R_AVR32_32_CPENT \.text\.init
  16343. + 20003c: R_AVR32_32_CPENT undefined
  16344. + 200040: R_AVR32_32_CPENT \.text\+0x40002c
  16345. +
  16346. +0040002c <toofar_positive>:
  16347. + 40002c: d7 03 nop
  16348. +0040002e <far_positive>:
  16349. + 40002e: d7 03 nop
  16350. +Disassembly of section \.text\.init:
  16351. +
  16352. +00000000 <different_section>:
  16353. + 0: e2 c0 00 00 sub r0,r1,0
  16354. --- /dev/null
  16355. +++ b/gas/testsuite/gas/avr32/call_nopic_linkrelax.d
  16356. @@ -0,0 +1,43 @@
  16357. +#source: call.s
  16358. +#as: --linkrelax
  16359. +#objdump: -dr
  16360. +#name: call_nopic_linkrelax
  16361. +
  16362. +.*: +file format .*
  16363. +
  16364. +Disassembly of section \.text:
  16365. +
  16366. +00000000 <call_test>:
  16367. + 0: d7 03 nop
  16368. +
  16369. +00000002 <toofar_negative>:
  16370. + \.\.\.
  16371. + 1ffffe: 00 00 add r0,r0
  16372. + 200000: e0 a0 00 00 rcall 200000 <toofar_negative\+0x1ffffe>
  16373. + 200000: R_AVR32_22H_PCREL \.text
  16374. + 200004: f0 1f 00 00 mcall 200004 <toofar_negative\+0x200002>
  16375. + 200004: R_AVR32_CPCALL \.text\+0x200034
  16376. + 200008: f0 1f 00 00 mcall 200008 <toofar_negative\+0x200006>
  16377. + 200008: R_AVR32_CPCALL \.text\+0x200038
  16378. + 20000c: f0 1f 00 00 mcall 20000c <toofar_negative\+0x20000a>
  16379. + 20000c: R_AVR32_CPCALL \.text\+0x20003c
  16380. + 200010: f0 1f 00 00 mcall 200010 <toofar_negative\+0x20000e>
  16381. + 200010: R_AVR32_CPCALL \.text\+0x200040
  16382. + \.\.\.
  16383. + 200030: e0 a0 00 00 rcall 200030 <toofar_negative\+0x20002e>
  16384. + 200030: R_AVR32_22H_PCREL \.text\+0x40002e
  16385. + \.\.\.
  16386. + 200034: R_AVR32_ALIGN \*ABS\*\+0x2
  16387. + 200034: R_AVR32_32_CPENT \.text\+0x2
  16388. + 200038: R_AVR32_32_CPENT \.text\.init
  16389. + 20003c: R_AVR32_32_CPENT undefined
  16390. + 200040: R_AVR32_32_CPENT \.text\+0x40002c
  16391. +
  16392. +0040002c <toofar_positive>:
  16393. + 40002c: d7 03 nop
  16394. +0040002e <far_positive>:
  16395. + 40002e: d7 03 nop
  16396. +Disassembly of section \.text\.init:
  16397. +
  16398. +00000000 <different_section>:
  16399. + 0: e2 c0 00 00 sub r0,r1,0
  16400. --- /dev/null
  16401. +++ b/gas/testsuite/gas/avr32/call_pic.d
  16402. @@ -0,0 +1,36 @@
  16403. +#source: call.s
  16404. +#as: --pic
  16405. +#objdump: -dr
  16406. +#name: call_pic
  16407. +
  16408. +.*: +file format .*
  16409. +
  16410. +Disassembly of section \.text:
  16411. +
  16412. +00000000 <call_test>:
  16413. + 0: d7 03 nop
  16414. +
  16415. +00000002 <toofar_negative>:
  16416. + \.\.\.
  16417. + 1ffffe: 00 00 add r0,r0
  16418. + 200000: f0 a0 00 00 rcall 0 <call_test>
  16419. + 200004: f0 16 00 00 mcall r6\[0\]
  16420. + 200004: R_AVR32_GOT18SW toofar_negative
  16421. + 200008: f0 16 00 00 mcall r6\[0\]
  16422. + 200008: R_AVR32_GOT18SW different_section
  16423. + 20000c: f0 16 00 00 mcall r6\[0\]
  16424. + 20000c: R_AVR32_GOT18SW undefined
  16425. + 200010: f0 16 00 00 mcall r6\[0\]
  16426. + 200010: R_AVR32_GOT18SW toofar_positive
  16427. + \.\.\.
  16428. + 200030: ee b0 ff ff rcall 40002e <far_positive>
  16429. + \.\.\.
  16430. +
  16431. +0040002c <toofar_positive>:
  16432. + 40002c: d7 03 nop
  16433. +0040002e <far_positive>:
  16434. + 40002e: d7 03 nop
  16435. +Disassembly of section \.text\.init:
  16436. +
  16437. +00000000 <different_section>:
  16438. + 0: e2 c0 00 00 sub r0,r1,0
  16439. --- /dev/null
  16440. +++ b/gas/testsuite/gas/avr32/call_pic_linkrelax.d
  16441. @@ -0,0 +1,47 @@
  16442. +#source: call.s
  16443. +#as: --pic --linkrelax
  16444. +#objdump: -dr
  16445. +#name: call_pic_linkrelax
  16446. +
  16447. +.*: +file format .*
  16448. +
  16449. +Disassembly of section \.text:
  16450. +
  16451. +00000000 <call_test>:
  16452. + 0: d7 03 nop
  16453. +
  16454. +00000002 <toofar_negative>:
  16455. + \.\.\.
  16456. + 1ffffe: 00 00 add r0,r0
  16457. + 200000: e0 a0 00 00 rcall 200000 <toofar_negative\+0x1ffffe>
  16458. + 200000: R_AVR32_22H_PCREL \.text
  16459. + 200004: e0 6e 00 00 mov lr,0
  16460. + 200004: R_AVR32_GOTCALL toofar_negative
  16461. + 200008: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
  16462. + 20000c: 5d 1e icall lr
  16463. + 20000e: e0 6e 00 00 mov lr,0
  16464. + 20000e: R_AVR32_GOTCALL different_section
  16465. + 200012: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
  16466. + 200016: 5d 1e icall lr
  16467. + 200018: e0 6e 00 00 mov lr,0
  16468. + 200018: R_AVR32_GOTCALL undefined
  16469. + 20001c: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
  16470. + 200020: 5d 1e icall lr
  16471. + 200022: e0 6e 00 00 mov lr,0
  16472. + 200022: R_AVR32_GOTCALL toofar_positive
  16473. + 200026: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
  16474. + 20002a: 5d 1e icall lr
  16475. + 20002c: 00 00 add r0,r0
  16476. + 20002e: 00 00 add r0,r0
  16477. + 200030: e0 a0 00 00 rcall 200030 <toofar_negative\+0x20002e>
  16478. + 200030: R_AVR32_22H_PCREL \.text\+0x40002e
  16479. + \.\.\.
  16480. +
  16481. +0040002c <toofar_positive>:
  16482. + 40002c: d7 03 nop
  16483. +0040002e <far_positive>:
  16484. + 40002e: d7 03 nop
  16485. +Disassembly of section \.text\.init:
  16486. +
  16487. +00000000 <different_section>:
  16488. + 0: e2 c0 00 00 sub r0,r1,0
  16489. --- /dev/null
  16490. +++ b/gas/testsuite/gas/avr32/call.s
  16491. @@ -0,0 +1,30 @@
  16492. +
  16493. + .text
  16494. + .global call_test
  16495. +call_test:
  16496. +far_negative:
  16497. + nop
  16498. +toofar_negative:
  16499. +
  16500. + .org 0x200000
  16501. +
  16502. + call far_negative
  16503. + call toofar_negative
  16504. + call different_section
  16505. + call undefined
  16506. + call toofar_positive
  16507. + .org 0x200030
  16508. + call far_positive
  16509. +
  16510. + .cpool
  16511. +
  16512. + .org 0x40002c
  16513. +
  16514. +toofar_positive:
  16515. + nop
  16516. +far_positive:
  16517. + nop
  16518. +
  16519. + .section .text.init,"ax",@progbits
  16520. +different_section:
  16521. + sub r0, r1, 0
  16522. --- /dev/null
  16523. +++ b/gas/testsuite/gas/avr32/dwarf2.d
  16524. @@ -0,0 +1,42 @@
  16525. +#readelf: -wl
  16526. +#name: dwarf2
  16527. +#source: dwarf2.s
  16528. +
  16529. +Dump of debug contents of section \.debug_line:
  16530. +
  16531. + Length: 53
  16532. + DWARF Version: 2
  16533. + Prologue Length: 26
  16534. + Minimum Instruction Length: 1
  16535. + Initial value of 'is_stmt': 1
  16536. + Line Base: -5
  16537. + Line Range: 14
  16538. + Opcode Base: 10
  16539. + \(Pointer size: 4\)
  16540. +
  16541. + Opcodes:
  16542. + Opcode 1 has 0 args
  16543. + Opcode 2 has 1 args
  16544. + Opcode 3 has 1 args
  16545. + Opcode 4 has 1 args
  16546. + Opcode 5 has 1 args
  16547. + Opcode 6 has 0 args
  16548. + Opcode 7 has 0 args
  16549. + Opcode 8 has 0 args
  16550. + Opcode 9 has 1 args
  16551. +
  16552. + The Directory Table is empty\.
  16553. +
  16554. + The File Name Table:
  16555. + Entry Dir Time Size Name
  16556. + 1 0 0 0 main\.c
  16557. +
  16558. + Line Number Statements:
  16559. + Extended opcode 2: set Address to 0x0
  16560. + Advance Line by 87 to 88
  16561. + Copy
  16562. + Advance Line by 23 to 111
  16563. + Special opcode .*: advance Address by 4 to 0x4 and Line by 0 to 111
  16564. + Special opcode .*: advance Address by 10 to 0xe and Line by 1 to 112
  16565. + Advance PC by 530 to 220
  16566. + Extended opcode 1: End of Sequence
  16567. --- /dev/null
  16568. +++ b/gas/testsuite/gas/avr32/dwarf2.s
  16569. @@ -0,0 +1,67 @@
  16570. +# Source file used to test DWARF2 information for AVR32.
  16571. +
  16572. + .file "main.c"
  16573. +
  16574. + .section .debug_abbrev,"",@progbits
  16575. +.Ldebug_abbrev0:
  16576. + .section .debug_info,"",@progbits
  16577. +.Ldebug_info0:
  16578. + .section .debug_line,"",@progbits
  16579. +.Ldebug_line0:
  16580. +
  16581. + .text
  16582. + .align 1
  16583. + .globl main
  16584. + .type main, @function
  16585. +.Ltext0:
  16586. +main:
  16587. + .file 1 "main.c"
  16588. + .loc 1 88 0
  16589. + pushm r0-r7,lr
  16590. + sub sp, 4
  16591. + .loc 1 111 0
  16592. + lddpc r12, .LC1
  16593. + lddpc r7, .LC1
  16594. + icall r7
  16595. + .loc 1 112 0
  16596. + lddpc r6, .LC4
  16597. +
  16598. + .align 2
  16599. +.LC4: .int 0
  16600. +
  16601. + .fill 256, 2, 0
  16602. +
  16603. + .align 2
  16604. +.LC1:
  16605. + .int 0
  16606. +.LC2:
  16607. + .int 0
  16608. +.LC3:
  16609. + .int 0
  16610. + .size main, . - main
  16611. +
  16612. +.Letext0:
  16613. +
  16614. + .section .debug_info
  16615. + .int .Ledebug_info0 - .Ldebug_info0 // size
  16616. + .short 2 // version
  16617. + .int .Ldebug_abbrev0 // abbrev offset
  16618. + .byte 4 // bytes per addr
  16619. +
  16620. + .uleb128 1 // abbrev 1
  16621. + .int .Ldebug_line0 // DW_AT_stmt_list
  16622. + .int .Letext0 // DW_AT_high_pc
  16623. + .int .Ltext0 // DW_AT_low_pc
  16624. +
  16625. +.Ledebug_info0:
  16626. +
  16627. + .section .debug_abbrev
  16628. + .uleb128 0x01
  16629. + .uleb128 0x11 // DW_TAG_compile_unit
  16630. + .byte 0 // DW_CHILDREN_no
  16631. + .uleb128 0x10, 0x6 // DW_AT_stmt_list
  16632. + .uleb128 0x12, 0x1 // DW_AT_high_pc
  16633. + .uleb128 0x11, 0x1 // DW_AT_low_pc
  16634. + .uleb128 0, 0
  16635. +
  16636. + .byte 0
  16637. --- /dev/null
  16638. +++ b/gas/testsuite/gas/avr32/fpinsn.d
  16639. @@ -0,0 +1,271 @@
  16640. +#as:
  16641. +#objdump: -dr
  16642. +#name: fpinsn
  16643. +
  16644. +.*: +file format .*
  16645. +
  16646. +Disassembly of section \.text:
  16647. +
  16648. +[0-9a-f]* <fadd_s>:
  16649. + *[0-9a-f]*: e1 a2 0f ff cop cp0,cr15,cr15,cr15,0x4
  16650. + *[0-9a-f]*: e1 a2 00 00 cop cp0,cr0,cr0,cr0,0x4
  16651. + *[0-9a-f]*: e1 a2 00 ff cop cp0,cr0,cr15,cr15,0x4
  16652. + *[0-9a-f]*: e1 a2 0f 0f cop cp0,cr15,cr0,cr15,0x4
  16653. + *[0-9a-f]*: e1 a2 0f f0 cop cp0,cr15,cr15,cr0,0x4
  16654. + *[0-9a-f]*: e1 a2 07 88 cop cp0,cr7,cr8,cr8,0x4
  16655. + *[0-9a-f]*: e1 a2 08 78 cop cp0,cr8,cr7,cr8,0x4
  16656. + *[0-9a-f]*: e1 a2 08 87 cop cp0,cr8,cr8,cr7,0x4
  16657. +
  16658. +[0-9a-f]* <fsub_s>:
  16659. + *[0-9a-f]*: e1 a2 1f ff cop cp0,cr15,cr15,cr15,0x5
  16660. + *[0-9a-f]*: e1 a2 10 00 cop cp0,cr0,cr0,cr0,0x5
  16661. + *[0-9a-f]*: e1 a2 10 ff cop cp0,cr0,cr15,cr15,0x5
  16662. + *[0-9a-f]*: e1 a2 1f 0f cop cp0,cr15,cr0,cr15,0x5
  16663. + *[0-9a-f]*: e1 a2 1f f0 cop cp0,cr15,cr15,cr0,0x5
  16664. + *[0-9a-f]*: e1 a2 17 88 cop cp0,cr7,cr8,cr8,0x5
  16665. + *[0-9a-f]*: e1 a2 18 78 cop cp0,cr8,cr7,cr8,0x5
  16666. + *[0-9a-f]*: e1 a2 18 87 cop cp0,cr8,cr8,cr7,0x5
  16667. +
  16668. +[0-9a-f]* <fmac_s>:
  16669. + *[0-9a-f]*: e1 a0 0f ff cop cp0,cr15,cr15,cr15,0x0
  16670. + *[0-9a-f]*: e1 a0 00 00 cop cp0,cr0,cr0,cr0,0x0
  16671. + *[0-9a-f]*: e1 a0 00 ff cop cp0,cr0,cr15,cr15,0x0
  16672. + *[0-9a-f]*: e1 a0 0f 0f cop cp0,cr15,cr0,cr15,0x0
  16673. + *[0-9a-f]*: e1 a0 0f f0 cop cp0,cr15,cr15,cr0,0x0
  16674. + *[0-9a-f]*: e1 a0 07 88 cop cp0,cr7,cr8,cr8,0x0
  16675. + *[0-9a-f]*: e1 a0 08 78 cop cp0,cr8,cr7,cr8,0x0
  16676. + *[0-9a-f]*: e1 a0 08 87 cop cp0,cr8,cr8,cr7,0x0
  16677. +
  16678. +[0-9a-f]* <fnmac_s>:
  16679. + *[0-9a-f]*: e1 a0 1f ff cop cp0,cr15,cr15,cr15,0x1
  16680. + *[0-9a-f]*: e1 a0 10 00 cop cp0,cr0,cr0,cr0,0x1
  16681. + *[0-9a-f]*: e1 a0 10 ff cop cp0,cr0,cr15,cr15,0x1
  16682. + *[0-9a-f]*: e1 a0 1f 0f cop cp0,cr15,cr0,cr15,0x1
  16683. + *[0-9a-f]*: e1 a0 1f f0 cop cp0,cr15,cr15,cr0,0x1
  16684. + *[0-9a-f]*: e1 a0 17 88 cop cp0,cr7,cr8,cr8,0x1
  16685. + *[0-9a-f]*: e1 a0 18 78 cop cp0,cr8,cr7,cr8,0x1
  16686. + *[0-9a-f]*: e1 a0 18 87 cop cp0,cr8,cr8,cr7,0x1
  16687. +
  16688. +[0-9a-f]* <fmsc_s>:
  16689. + *[0-9a-f]*: e1 a1 0f ff cop cp0,cr15,cr15,cr15,0x2
  16690. + *[0-9a-f]*: e1 a1 00 00 cop cp0,cr0,cr0,cr0,0x2
  16691. + *[0-9a-f]*: e1 a1 00 ff cop cp0,cr0,cr15,cr15,0x2
  16692. + *[0-9a-f]*: e1 a1 0f 0f cop cp0,cr15,cr0,cr15,0x2
  16693. + *[0-9a-f]*: e1 a1 0f f0 cop cp0,cr15,cr15,cr0,0x2
  16694. + *[0-9a-f]*: e1 a1 07 88 cop cp0,cr7,cr8,cr8,0x2
  16695. + *[0-9a-f]*: e1 a1 08 78 cop cp0,cr8,cr7,cr8,0x2
  16696. + *[0-9a-f]*: e1 a1 08 87 cop cp0,cr8,cr8,cr7,0x2
  16697. +
  16698. +[0-9a-f]* <fnmsc_s>:
  16699. + *[0-9a-f]*: e1 a1 1f ff cop cp0,cr15,cr15,cr15,0x3
  16700. + *[0-9a-f]*: e1 a1 10 00 cop cp0,cr0,cr0,cr0,0x3
  16701. + *[0-9a-f]*: e1 a1 10 ff cop cp0,cr0,cr15,cr15,0x3
  16702. + *[0-9a-f]*: e1 a1 1f 0f cop cp0,cr15,cr0,cr15,0x3
  16703. + *[0-9a-f]*: e1 a1 1f f0 cop cp0,cr15,cr15,cr0,0x3
  16704. + *[0-9a-f]*: e1 a1 17 88 cop cp0,cr7,cr8,cr8,0x3
  16705. + *[0-9a-f]*: e1 a1 18 78 cop cp0,cr8,cr7,cr8,0x3
  16706. + *[0-9a-f]*: e1 a1 18 87 cop cp0,cr8,cr8,cr7,0x3
  16707. +
  16708. +[0-9a-f]* <fmul_s>:
  16709. + *[0-9a-f]*: e1 a3 0f ff cop cp0,cr15,cr15,cr15,0x6
  16710. + *[0-9a-f]*: e1 a3 00 00 cop cp0,cr0,cr0,cr0,0x6
  16711. + *[0-9a-f]*: e1 a3 00 ff cop cp0,cr0,cr15,cr15,0x6
  16712. + *[0-9a-f]*: e1 a3 0f 0f cop cp0,cr15,cr0,cr15,0x6
  16713. + *[0-9a-f]*: e1 a3 0f f0 cop cp0,cr15,cr15,cr0,0x6
  16714. + *[0-9a-f]*: e1 a3 07 88 cop cp0,cr7,cr8,cr8,0x6
  16715. + *[0-9a-f]*: e1 a3 08 78 cop cp0,cr8,cr7,cr8,0x6
  16716. + *[0-9a-f]*: e1 a3 08 87 cop cp0,cr8,cr8,cr7,0x6
  16717. +
  16718. +[0-9a-f]* <fnmul_s>:
  16719. + *[0-9a-f]*: e1 a3 1f ff cop cp0,cr15,cr15,cr15,0x7
  16720. + *[0-9a-f]*: e1 a3 10 00 cop cp0,cr0,cr0,cr0,0x7
  16721. + *[0-9a-f]*: e1 a3 10 ff cop cp0,cr0,cr15,cr15,0x7
  16722. + *[0-9a-f]*: e1 a3 1f 0f cop cp0,cr15,cr0,cr15,0x7
  16723. + *[0-9a-f]*: e1 a3 1f f0 cop cp0,cr15,cr15,cr0,0x7
  16724. + *[0-9a-f]*: e1 a3 17 88 cop cp0,cr7,cr8,cr8,0x7
  16725. + *[0-9a-f]*: e1 a3 18 78 cop cp0,cr8,cr7,cr8,0x7
  16726. + *[0-9a-f]*: e1 a3 18 87 cop cp0,cr8,cr8,cr7,0x7
  16727. +
  16728. +[0-9a-f]* <fneg_s>:
  16729. + *[0-9a-f]*: e1 a4 0f f0 cop cp0,cr15,cr15,cr0,0x8
  16730. + *[0-9a-f]*: e1 a4 00 00 cop cp0,cr0,cr0,cr0,0x8
  16731. + *[0-9a-f]*: e1 a4 00 f0 cop cp0,cr0,cr15,cr0,0x8
  16732. + *[0-9a-f]*: e1 a4 0f 00 cop cp0,cr15,cr0,cr0,0x8
  16733. + *[0-9a-f]*: e1 a4 07 80 cop cp0,cr7,cr8,cr0,0x8
  16734. + *[0-9a-f]*: e1 a4 08 70 cop cp0,cr8,cr7,cr0,0x8
  16735. +
  16736. +[0-9a-f]* <fabs_s>:
  16737. + *[0-9a-f]*: e1 a4 1f f0 cop cp0,cr15,cr15,cr0,0x9
  16738. + *[0-9a-f]*: e1 a4 10 00 cop cp0,cr0,cr0,cr0,0x9
  16739. + *[0-9a-f]*: e1 a4 10 f0 cop cp0,cr0,cr15,cr0,0x9
  16740. + *[0-9a-f]*: e1 a4 1f 00 cop cp0,cr15,cr0,cr0,0x9
  16741. + *[0-9a-f]*: e1 a4 17 80 cop cp0,cr7,cr8,cr0,0x9
  16742. + *[0-9a-f]*: e1 a4 18 70 cop cp0,cr8,cr7,cr0,0x9
  16743. +
  16744. +[0-9a-f]* <fcmp_s>:
  16745. + *[0-9a-f]*: e1 a6 10 ff cop cp0,cr0,cr15,cr15,0xd
  16746. + *[0-9a-f]*: e1 a6 10 00 cop cp0,cr0,cr0,cr0,0xd
  16747. + *[0-9a-f]*: e1 a6 10 0f cop cp0,cr0,cr0,cr15,0xd
  16748. + *[0-9a-f]*: e1 a6 10 f0 cop cp0,cr0,cr15,cr0,0xd
  16749. + *[0-9a-f]*: e1 a6 10 78 cop cp0,cr0,cr7,cr8,0xd
  16750. + *[0-9a-f]*: e1 a6 10 87 cop cp0,cr0,cr8,cr7,0xd
  16751. +
  16752. +[0-9a-f]* <fadd_d>:
  16753. + *[0-9a-f]*: e5 a2 0e ee cop cp0,cr14,cr14,cr14,0x44
  16754. + *[0-9a-f]*: e5 a2 00 00 cop cp0,cr0,cr0,cr0,0x44
  16755. + *[0-9a-f]*: e5 a2 00 ee cop cp0,cr0,cr14,cr14,0x44
  16756. + *[0-9a-f]*: e5 a2 0e 0e cop cp0,cr14,cr0,cr14,0x44
  16757. + *[0-9a-f]*: e5 a2 0e e0 cop cp0,cr14,cr14,cr0,0x44
  16758. + *[0-9a-f]*: e5 a2 06 88 cop cp0,cr6,cr8,cr8,0x44
  16759. + *[0-9a-f]*: e5 a2 08 68 cop cp0,cr8,cr6,cr8,0x44
  16760. + *[0-9a-f]*: e5 a2 08 86 cop cp0,cr8,cr8,cr6,0x44
  16761. +
  16762. +[0-9a-f]* <fsub_d>:
  16763. + *[0-9a-f]*: e5 a2 1e ee cop cp0,cr14,cr14,cr14,0x45
  16764. + *[0-9a-f]*: e5 a2 10 00 cop cp0,cr0,cr0,cr0,0x45
  16765. + *[0-9a-f]*: e5 a2 10 ee cop cp0,cr0,cr14,cr14,0x45
  16766. + *[0-9a-f]*: e5 a2 1e 0e cop cp0,cr14,cr0,cr14,0x45
  16767. + *[0-9a-f]*: e5 a2 1e e0 cop cp0,cr14,cr14,cr0,0x45
  16768. + *[0-9a-f]*: e5 a2 16 88 cop cp0,cr6,cr8,cr8,0x45
  16769. + *[0-9a-f]*: e5 a2 18 68 cop cp0,cr8,cr6,cr8,0x45
  16770. + *[0-9a-f]*: e5 a2 18 86 cop cp0,cr8,cr8,cr6,0x45
  16771. +
  16772. +[0-9a-f]* <fmac_d>:
  16773. + *[0-9a-f]*: e5 a0 0e ee cop cp0,cr14,cr14,cr14,0x40
  16774. + *[0-9a-f]*: e5 a0 00 00 cop cp0,cr0,cr0,cr0,0x40
  16775. + *[0-9a-f]*: e5 a0 00 ee cop cp0,cr0,cr14,cr14,0x40
  16776. + *[0-9a-f]*: e5 a0 0e 0e cop cp0,cr14,cr0,cr14,0x40
  16777. + *[0-9a-f]*: e5 a0 0e e0 cop cp0,cr14,cr14,cr0,0x40
  16778. + *[0-9a-f]*: e5 a0 06 88 cop cp0,cr6,cr8,cr8,0x40
  16779. + *[0-9a-f]*: e5 a0 08 68 cop cp0,cr8,cr6,cr8,0x40
  16780. + *[0-9a-f]*: e5 a0 08 86 cop cp0,cr8,cr8,cr6,0x40
  16781. +
  16782. +[0-9a-f]* <fnmac_d>:
  16783. + *[0-9a-f]*: e5 a0 1e ee cop cp0,cr14,cr14,cr14,0x41
  16784. + *[0-9a-f]*: e5 a0 10 00 cop cp0,cr0,cr0,cr0,0x41
  16785. + *[0-9a-f]*: e5 a0 10 ee cop cp0,cr0,cr14,cr14,0x41
  16786. + *[0-9a-f]*: e5 a0 1e 0e cop cp0,cr14,cr0,cr14,0x41
  16787. + *[0-9a-f]*: e5 a0 1e e0 cop cp0,cr14,cr14,cr0,0x41
  16788. + *[0-9a-f]*: e5 a0 16 88 cop cp0,cr6,cr8,cr8,0x41
  16789. + *[0-9a-f]*: e5 a0 18 68 cop cp0,cr8,cr6,cr8,0x41
  16790. + *[0-9a-f]*: e5 a0 18 86 cop cp0,cr8,cr8,cr6,0x41
  16791. +
  16792. +[0-9a-f]* <fmsc_d>:
  16793. + *[0-9a-f]*: e5 a1 0e ee cop cp0,cr14,cr14,cr14,0x42
  16794. + *[0-9a-f]*: e5 a1 00 00 cop cp0,cr0,cr0,cr0,0x42
  16795. + *[0-9a-f]*: e5 a1 00 ee cop cp0,cr0,cr14,cr14,0x42
  16796. + *[0-9a-f]*: e5 a1 0e 0e cop cp0,cr14,cr0,cr14,0x42
  16797. + *[0-9a-f]*: e5 a1 0e e0 cop cp0,cr14,cr14,cr0,0x42
  16798. + *[0-9a-f]*: e5 a1 06 88 cop cp0,cr6,cr8,cr8,0x42
  16799. + *[0-9a-f]*: e5 a1 08 68 cop cp0,cr8,cr6,cr8,0x42
  16800. + *[0-9a-f]*: e5 a1 08 86 cop cp0,cr8,cr8,cr6,0x42
  16801. +
  16802. +[0-9a-f]* <fnmsc_d>:
  16803. + *[0-9a-f]*: e5 a1 1e ee cop cp0,cr14,cr14,cr14,0x43
  16804. + *[0-9a-f]*: e5 a1 10 00 cop cp0,cr0,cr0,cr0,0x43
  16805. + *[0-9a-f]*: e5 a1 10 ee cop cp0,cr0,cr14,cr14,0x43
  16806. + *[0-9a-f]*: e5 a1 1e 0e cop cp0,cr14,cr0,cr14,0x43
  16807. + *[0-9a-f]*: e5 a1 1e e0 cop cp0,cr14,cr14,cr0,0x43
  16808. + *[0-9a-f]*: e5 a1 16 88 cop cp0,cr6,cr8,cr8,0x43
  16809. + *[0-9a-f]*: e5 a1 18 68 cop cp0,cr8,cr6,cr8,0x43
  16810. + *[0-9a-f]*: e5 a1 18 86 cop cp0,cr8,cr8,cr6,0x43
  16811. +
  16812. +[0-9a-f]* <fmul_d>:
  16813. + *[0-9a-f]*: e5 a3 0e ee cop cp0,cr14,cr14,cr14,0x46
  16814. + *[0-9a-f]*: e5 a3 00 00 cop cp0,cr0,cr0,cr0,0x46
  16815. + *[0-9a-f]*: e5 a3 00 ee cop cp0,cr0,cr14,cr14,0x46
  16816. + *[0-9a-f]*: e5 a3 0e 0e cop cp0,cr14,cr0,cr14,0x46
  16817. + *[0-9a-f]*: e5 a3 0e e0 cop cp0,cr14,cr14,cr0,0x46
  16818. + *[0-9a-f]*: e5 a3 06 88 cop cp0,cr6,cr8,cr8,0x46
  16819. + *[0-9a-f]*: e5 a3 08 68 cop cp0,cr8,cr6,cr8,0x46
  16820. + *[0-9a-f]*: e5 a3 08 86 cop cp0,cr8,cr8,cr6,0x46
  16821. +
  16822. +[0-9a-f]* <fnmul_d>:
  16823. + *[0-9a-f]*: e5 a3 1e ee cop cp0,cr14,cr14,cr14,0x47
  16824. + *[0-9a-f]*: e5 a3 10 00 cop cp0,cr0,cr0,cr0,0x47
  16825. + *[0-9a-f]*: e5 a3 10 ee cop cp0,cr0,cr14,cr14,0x47
  16826. + *[0-9a-f]*: e5 a3 1e 0e cop cp0,cr14,cr0,cr14,0x47
  16827. + *[0-9a-f]*: e5 a3 1e e0 cop cp0,cr14,cr14,cr0,0x47
  16828. + *[0-9a-f]*: e5 a3 16 88 cop cp0,cr6,cr8,cr8,0x47
  16829. + *[0-9a-f]*: e5 a3 18 68 cop cp0,cr8,cr6,cr8,0x47
  16830. + *[0-9a-f]*: e5 a3 18 86 cop cp0,cr8,cr8,cr6,0x47
  16831. +
  16832. +[0-9a-f]* <fneg_d>:
  16833. + *[0-9a-f]*: e5 a4 0e e0 cop cp0,cr14,cr14,cr0,0x48
  16834. + *[0-9a-f]*: e5 a4 00 00 cop cp0,cr0,cr0,cr0,0x48
  16835. + *[0-9a-f]*: e5 a4 00 e0 cop cp0,cr0,cr14,cr0,0x48
  16836. + *[0-9a-f]*: e5 a4 0e 00 cop cp0,cr14,cr0,cr0,0x48
  16837. + *[0-9a-f]*: e5 a4 06 80 cop cp0,cr6,cr8,cr0,0x48
  16838. + *[0-9a-f]*: e5 a4 08 60 cop cp0,cr8,cr6,cr0,0x48
  16839. +
  16840. +[0-9a-f]* <fabs_d>:
  16841. + *[0-9a-f]*: e5 a4 1e e0 cop cp0,cr14,cr14,cr0,0x49
  16842. + *[0-9a-f]*: e5 a4 10 00 cop cp0,cr0,cr0,cr0,0x49
  16843. + *[0-9a-f]*: e5 a4 10 e0 cop cp0,cr0,cr14,cr0,0x49
  16844. + *[0-9a-f]*: e5 a4 1e 00 cop cp0,cr14,cr0,cr0,0x49
  16845. + *[0-9a-f]*: e5 a4 16 80 cop cp0,cr6,cr8,cr0,0x49
  16846. + *[0-9a-f]*: e5 a4 18 60 cop cp0,cr8,cr6,cr0,0x49
  16847. +
  16848. +[0-9a-f]* <fcmp_d>:
  16849. + *[0-9a-f]*: e5 a6 10 ee cop cp0,cr0,cr14,cr14,0x4d
  16850. + *[0-9a-f]*: e5 a6 10 00 cop cp0,cr0,cr0,cr0,0x4d
  16851. + *[0-9a-f]*: e5 a6 10 0e cop cp0,cr0,cr0,cr14,0x4d
  16852. + *[0-9a-f]*: e5 a6 10 e0 cop cp0,cr0,cr14,cr0,0x4d
  16853. + *[0-9a-f]*: e5 a6 10 68 cop cp0,cr0,cr6,cr8,0x4d
  16854. + *[0-9a-f]*: e5 a6 10 86 cop cp0,cr0,cr8,cr6,0x4d
  16855. +
  16856. +[0-9a-f]* <fmov_s>:
  16857. + *[0-9a-f]*: e1 a5 0f f0 cop cp0,cr15,cr15,cr0,0xa
  16858. + *[0-9a-f]*: e1 a5 00 00 cop cp0,cr0,cr0,cr0,0xa
  16859. + *[0-9a-f]*: e1 a5 0f 00 cop cp0,cr15,cr0,cr0,0xa
  16860. + *[0-9a-f]*: e1 a5 00 f0 cop cp0,cr0,cr15,cr0,0xa
  16861. + *[0-9a-f]*: e1 a5 08 70 cop cp0,cr8,cr7,cr0,0xa
  16862. + *[0-9a-f]*: e1 a5 07 80 cop cp0,cr7,cr8,cr0,0xa
  16863. + *[0-9a-f]*: ef af 0f 00 mvcr.w cp0,pc,cr15
  16864. + *[0-9a-f]*: ef a0 00 00 mvcr.w cp0,r0,cr0
  16865. + *[0-9a-f]*: ef af 00 00 mvcr.w cp0,pc,cr0
  16866. + *[0-9a-f]*: ef a0 0f 00 mvcr.w cp0,r0,cr15
  16867. + *[0-9a-f]*: ef a8 07 00 mvcr.w cp0,r8,cr7
  16868. + *[0-9a-f]*: ef a7 08 00 mvcr.w cp0,r7,cr8
  16869. + *[0-9a-f]*: ef af 0f 20 mvrc.w cp0,cr15,pc
  16870. + *[0-9a-f]*: ef a0 00 20 mvrc.w cp0,cr0,r0
  16871. + *[0-9a-f]*: ef a0 0f 20 mvrc.w cp0,cr15,r0
  16872. + *[0-9a-f]*: ef af 00 20 mvrc.w cp0,cr0,pc
  16873. + *[0-9a-f]*: ef a7 08 20 mvrc.w cp0,cr8,r7
  16874. + *[0-9a-f]*: ef a8 07 20 mvrc.w cp0,cr7,r8
  16875. +
  16876. +[0-9a-f]* <fmov_d>:
  16877. + *[0-9a-f]*: e5 a5 0e e0 cop cp0,cr14,cr14,cr0,0x4a
  16878. + *[0-9a-f]*: e5 a5 00 00 cop cp0,cr0,cr0,cr0,0x4a
  16879. + *[0-9a-f]*: e5 a5 0e 00 cop cp0,cr14,cr0,cr0,0x4a
  16880. + *[0-9a-f]*: e5 a5 00 e0 cop cp0,cr0,cr14,cr0,0x4a
  16881. + *[0-9a-f]*: e5 a5 08 60 cop cp0,cr8,cr6,cr0,0x4a
  16882. + *[0-9a-f]*: e5 a5 06 80 cop cp0,cr6,cr8,cr0,0x4a
  16883. + *[0-9a-f]*: ef ae 0e 10 mvcr.d cp0,lr,cr14
  16884. + *[0-9a-f]*: ef a0 00 10 mvcr.d cp0,r0,cr0
  16885. + *[0-9a-f]*: ef ae 00 10 mvcr.d cp0,lr,cr0
  16886. + *[0-9a-f]*: ef a0 0e 10 mvcr.d cp0,r0,cr14
  16887. + *[0-9a-f]*: ef a8 06 10 mvcr.d cp0,r8,cr6
  16888. + *[0-9a-f]*: ef a6 08 10 mvcr.d cp0,r6,cr8
  16889. + *[0-9a-f]*: ef ae 0e 30 mvrc.d cp0,cr14,lr
  16890. + *[0-9a-f]*: ef a0 00 30 mvrc.d cp0,cr0,r0
  16891. + *[0-9a-f]*: ef a0 0e 30 mvrc.d cp0,cr14,r0
  16892. + *[0-9a-f]*: ef ae 00 30 mvrc.d cp0,cr0,lr
  16893. + *[0-9a-f]*: ef a6 08 30 mvrc.d cp0,cr8,r6
  16894. + *[0-9a-f]*: ef a8 06 30 mvrc.d cp0,cr6,r8
  16895. +
  16896. +[0-9a-f]* <fcasts_d>:
  16897. + *[0-9a-f]*: e1 a7 1f e0 cop cp0,cr15,cr14,cr0,0xf
  16898. + *[0-9a-f]*: e1 a7 10 00 cop cp0,cr0,cr0,cr0,0xf
  16899. + *[0-9a-f]*: e1 a7 1f 00 cop cp0,cr15,cr0,cr0,0xf
  16900. + *[0-9a-f]*: e1 a7 10 e0 cop cp0,cr0,cr14,cr0,0xf
  16901. + *[0-9a-f]*: e1 a7 18 60 cop cp0,cr8,cr6,cr0,0xf
  16902. + *[0-9a-f]*: e1 a7 17 80 cop cp0,cr7,cr8,cr0,0xf
  16903. +
  16904. +[0-9a-f]* <fcastd_s>:
  16905. + *[0-9a-f]*: e1 a8 0e f0 cop cp0,cr14,cr15,cr0,0x10
  16906. + *[0-9a-f]*: e1 a8 00 00 cop cp0,cr0,cr0,cr0,0x10
  16907. + *[0-9a-f]*: e1 a8 0e 00 cop cp0,cr14,cr0,cr0,0x10
  16908. + *[0-9a-f]*: e1 a8 00 f0 cop cp0,cr0,cr15,cr0,0x10
  16909. + *[0-9a-f]*: e1 a8 08 70 cop cp0,cr8,cr7,cr0,0x10
  16910. + *[0-9a-f]*: e1 a8 06 80 cop cp0,cr6,cr8,cr0,0x10
  16911. --- /dev/null
  16912. +++ b/gas/testsuite/gas/avr32/fpinsn.s
  16913. @@ -0,0 +1,266 @@
  16914. +
  16915. + .text
  16916. + .global fadd_s
  16917. +fadd_s:
  16918. + fadd.s fr15, fr15, fr15
  16919. + fadd.s fr0, fr0, fr0
  16920. + fadd.s fr0, fr15, fr15
  16921. + fadd.s fr15, fr0, fr15
  16922. + fadd.s fr15, fr15, fr0
  16923. + fadd.s fr7, fr8, fr8
  16924. + fadd.s fr8, fr7, fr8
  16925. + fadd.s fr8, fr8, fr7
  16926. + .global fsub_s
  16927. +fsub_s:
  16928. + fsub.s fr15, fr15, fr15
  16929. + fsub.s fr0, fr0, fr0
  16930. + fsub.s fr0, fr15, fr15
  16931. + fsub.s fr15, fr0, fr15
  16932. + fsub.s fr15, fr15, fr0
  16933. + fsub.s fr7, fr8, fr8
  16934. + fsub.s fr8, fr7, fr8
  16935. + fsub.s fr8, fr8, fr7
  16936. + .global fmac_s
  16937. +fmac_s:
  16938. + fmac.s fr15, fr15, fr15
  16939. + fmac.s fr0, fr0, fr0
  16940. + fmac.s fr0, fr15, fr15
  16941. + fmac.s fr15, fr0, fr15
  16942. + fmac.s fr15, fr15, fr0
  16943. + fmac.s fr7, fr8, fr8
  16944. + fmac.s fr8, fr7, fr8
  16945. + fmac.s fr8, fr8, fr7
  16946. + .global fnmac_s
  16947. +fnmac_s:
  16948. + fnmac.s fr15, fr15, fr15
  16949. + fnmac.s fr0, fr0, fr0
  16950. + fnmac.s fr0, fr15, fr15
  16951. + fnmac.s fr15, fr0, fr15
  16952. + fnmac.s fr15, fr15, fr0
  16953. + fnmac.s fr7, fr8, fr8
  16954. + fnmac.s fr8, fr7, fr8
  16955. + fnmac.s fr8, fr8, fr7
  16956. + .global fmsc_s
  16957. +fmsc_s:
  16958. + fmsc.s fr15, fr15, fr15
  16959. + fmsc.s fr0, fr0, fr0
  16960. + fmsc.s fr0, fr15, fr15
  16961. + fmsc.s fr15, fr0, fr15
  16962. + fmsc.s fr15, fr15, fr0
  16963. + fmsc.s fr7, fr8, fr8
  16964. + fmsc.s fr8, fr7, fr8
  16965. + fmsc.s fr8, fr8, fr7
  16966. + .global fnmsc_s
  16967. +fnmsc_s:
  16968. + fnmsc.s fr15, fr15, fr15
  16969. + fnmsc.s fr0, fr0, fr0
  16970. + fnmsc.s fr0, fr15, fr15
  16971. + fnmsc.s fr15, fr0, fr15
  16972. + fnmsc.s fr15, fr15, fr0
  16973. + fnmsc.s fr7, fr8, fr8
  16974. + fnmsc.s fr8, fr7, fr8
  16975. + fnmsc.s fr8, fr8, fr7
  16976. + .global fmul_s
  16977. +fmul_s:
  16978. + fmul.s fr15, fr15, fr15
  16979. + fmul.s fr0, fr0, fr0
  16980. + fmul.s fr0, fr15, fr15
  16981. + fmul.s fr15, fr0, fr15
  16982. + fmul.s fr15, fr15, fr0
  16983. + fmul.s fr7, fr8, fr8
  16984. + fmul.s fr8, fr7, fr8
  16985. + fmul.s fr8, fr8, fr7
  16986. + .global fnmul_s
  16987. +fnmul_s:
  16988. + fnmul.s fr15, fr15, fr15
  16989. + fnmul.s fr0, fr0, fr0
  16990. + fnmul.s fr0, fr15, fr15
  16991. + fnmul.s fr15, fr0, fr15
  16992. + fnmul.s fr15, fr15, fr0
  16993. + fnmul.s fr7, fr8, fr8
  16994. + fnmul.s fr8, fr7, fr8
  16995. + fnmul.s fr8, fr8, fr7
  16996. + .global fneg_s
  16997. +fneg_s:
  16998. + fneg.s fr15, fr15
  16999. + fneg.s fr0, fr0
  17000. + fneg.s fr0, fr15
  17001. + fneg.s fr15, fr0
  17002. + fneg.s fr7, fr8
  17003. + fneg.s fr8, fr7
  17004. + .global fabs_s
  17005. +fabs_s:
  17006. + fabs.s fr15, fr15
  17007. + fabs.s fr0, fr0
  17008. + fabs.s fr0, fr15
  17009. + fabs.s fr15, fr0
  17010. + fabs.s fr7, fr8
  17011. + fabs.s fr8, fr7
  17012. + .global fcmp_s
  17013. +fcmp_s:
  17014. + fcmp.s fr15, fr15
  17015. + fcmp.s fr0, fr0
  17016. + fcmp.s fr0, fr15
  17017. + fcmp.s fr15, fr0
  17018. + fcmp.s fr7, fr8
  17019. + fcmp.s fr8, fr7
  17020. + .global fadd_d
  17021. +fadd_d:
  17022. + fadd.d fr14, fr14, fr14
  17023. + fadd.d fr0, fr0, fr0
  17024. + fadd.d fr0, fr14, fr14
  17025. + fadd.d fr14, fr0, fr14
  17026. + fadd.d fr14, fr14, fr0
  17027. + fadd.d fr6, fr8, fr8
  17028. + fadd.d fr8, fr6, fr8
  17029. + fadd.d fr8, fr8, fr6
  17030. + .global fsub_d
  17031. +fsub_d:
  17032. + fsub.d fr14, fr14, fr14
  17033. + fsub.d fr0, fr0, fr0
  17034. + fsub.d fr0, fr14, fr14
  17035. + fsub.d fr14, fr0, fr14
  17036. + fsub.d fr14, fr14, fr0
  17037. + fsub.d fr6, fr8, fr8
  17038. + fsub.d fr8, fr6, fr8
  17039. + fsub.d fr8, fr8, fr6
  17040. + .global fmac_d
  17041. +fmac_d:
  17042. + fmac.d fr14, fr14, fr14
  17043. + fmac.d fr0, fr0, fr0
  17044. + fmac.d fr0, fr14, fr14
  17045. + fmac.d fr14, fr0, fr14
  17046. + fmac.d fr14, fr14, fr0
  17047. + fmac.d fr6, fr8, fr8
  17048. + fmac.d fr8, fr6, fr8
  17049. + fmac.d fr8, fr8, fr6
  17050. + .global fnmac_d
  17051. +fnmac_d:
  17052. + fnmac.d fr14, fr14, fr14
  17053. + fnmac.d fr0, fr0, fr0
  17054. + fnmac.d fr0, fr14, fr14
  17055. + fnmac.d fr14, fr0, fr14
  17056. + fnmac.d fr14, fr14, fr0
  17057. + fnmac.d fr6, fr8, fr8
  17058. + fnmac.d fr8, fr6, fr8
  17059. + fnmac.d fr8, fr8, fr6
  17060. + .global fmsc_d
  17061. +fmsc_d:
  17062. + fmsc.d fr14, fr14, fr14
  17063. + fmsc.d fr0, fr0, fr0
  17064. + fmsc.d fr0, fr14, fr14
  17065. + fmsc.d fr14, fr0, fr14
  17066. + fmsc.d fr14, fr14, fr0
  17067. + fmsc.d fr6, fr8, fr8
  17068. + fmsc.d fr8, fr6, fr8
  17069. + fmsc.d fr8, fr8, fr6
  17070. + .global fnmsc_d
  17071. +fnmsc_d:
  17072. + fnmsc.d fr14, fr14, fr14
  17073. + fnmsc.d fr0, fr0, fr0
  17074. + fnmsc.d fr0, fr14, fr14
  17075. + fnmsc.d fr14, fr0, fr14
  17076. + fnmsc.d fr14, fr14, fr0
  17077. + fnmsc.d fr6, fr8, fr8
  17078. + fnmsc.d fr8, fr6, fr8
  17079. + fnmsc.d fr8, fr8, fr6
  17080. + .global fmul_d
  17081. +fmul_d:
  17082. + fmul.d fr14, fr14, fr14
  17083. + fmul.d fr0, fr0, fr0
  17084. + fmul.d fr0, fr14, fr14
  17085. + fmul.d fr14, fr0, fr14
  17086. + fmul.d fr14, fr14, fr0
  17087. + fmul.d fr6, fr8, fr8
  17088. + fmul.d fr8, fr6, fr8
  17089. + fmul.d fr8, fr8, fr6
  17090. + .global fnmul_d
  17091. +fnmul_d:
  17092. + fnmul.d fr14, fr14, fr14
  17093. + fnmul.d fr0, fr0, fr0
  17094. + fnmul.d fr0, fr14, fr14
  17095. + fnmul.d fr14, fr0, fr14
  17096. + fnmul.d fr14, fr14, fr0
  17097. + fnmul.d fr6, fr8, fr8
  17098. + fnmul.d fr8, fr6, fr8
  17099. + fnmul.d fr8, fr8, fr6
  17100. + .global fneg_d
  17101. +fneg_d:
  17102. + fneg.d fr14, fr14
  17103. + fneg.d fr0, fr0
  17104. + fneg.d fr0, fr14
  17105. + fneg.d fr14, fr0
  17106. + fneg.d fr6, fr8
  17107. + fneg.d fr8, fr6
  17108. + .global fabs_d
  17109. +fabs_d:
  17110. + fabs.d fr14, fr14
  17111. + fabs.d fr0, fr0
  17112. + fabs.d fr0, fr14
  17113. + fabs.d fr14, fr0
  17114. + fabs.d fr6, fr8
  17115. + fabs.d fr8, fr6
  17116. + .global fcmp_d
  17117. +fcmp_d:
  17118. + fcmp.d fr14, fr14
  17119. + fcmp.d fr0, fr0
  17120. + fcmp.d fr0, fr14
  17121. + fcmp.d fr14, fr0
  17122. + fcmp.d fr6, fr8
  17123. + fcmp.d fr8, fr6
  17124. + .global fmov_s
  17125. +fmov_s:
  17126. + fmov.s fr15, fr15
  17127. + fmov.s fr0, fr0
  17128. + fmov.s fr15, fr0
  17129. + fmov.s fr0, fr15
  17130. + fmov.s fr8, fr7
  17131. + fmov.s fr7, fr8
  17132. + fmov.s pc, fr15
  17133. + fmov.s r0, fr0
  17134. + fmov.s pc, fr0
  17135. + fmov.s r0, fr15
  17136. + fmov.s r8, fr7
  17137. + fmov.s r7, fr8
  17138. + fmov.s fr15, pc
  17139. + fmov.s fr0, r0
  17140. + fmov.s fr15, r0
  17141. + fmov.s fr0, pc
  17142. + fmov.s fr8, r7
  17143. + fmov.s fr7, r8
  17144. + .global fmov_d
  17145. +fmov_d:
  17146. + fmov.d fr14, fr14
  17147. + fmov.d fr0, fr0
  17148. + fmov.d fr14, fr0
  17149. + fmov.d fr0, fr14
  17150. + fmov.d fr8, fr6
  17151. + fmov.d fr6, fr8
  17152. + fmov.d lr, fr14
  17153. + fmov.d r0, fr0
  17154. + fmov.d lr, fr0
  17155. + fmov.d r0, fr14
  17156. + fmov.d r8, fr6
  17157. + fmov.d r6, fr8
  17158. + fmov.d fr14, lr
  17159. + fmov.d fr0, r0
  17160. + fmov.d fr14, r0
  17161. + fmov.d fr0, lr
  17162. + fmov.d fr8, r6
  17163. + fmov.d fr6, r8
  17164. + .global fcasts_d
  17165. +fcasts_d:
  17166. + fcasts.d fr15, fr14
  17167. + fcasts.d fr0, fr0
  17168. + fcasts.d fr15, fr0
  17169. + fcasts.d fr0, fr14
  17170. + fcasts.d fr8, fr6
  17171. + fcasts.d fr7, fr8
  17172. + .global fcastd_s
  17173. +fcastd_s:
  17174. + fcastd.s fr14, fr15
  17175. + fcastd.s fr0, fr0
  17176. + fcastd.s fr14, fr0
  17177. + fcastd.s fr0, fr15
  17178. + fcastd.s fr8, fr7
  17179. + fcastd.s fr6, fr8
  17180. --- /dev/null
  17181. +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.d
  17182. @@ -0,0 +1,47 @@
  17183. +#as:
  17184. +#objdump: -dr
  17185. +#name: hwrd-lwrd
  17186. +
  17187. +.*: +file format .*
  17188. +
  17189. +Disassembly of section \.text:
  17190. +
  17191. +00000000 <test_hwrd>:
  17192. + 0: e0 60 87 65 mov r0,34661
  17193. + 4: e0 60 12 34 mov r0,4660
  17194. + 8: e0 60 00 00 mov r0,0
  17195. + 8: R_AVR32_HI16 \.text\+0x60
  17196. + c: e0 60 00 00 mov r0,0
  17197. + c: R_AVR32_HI16 extsym1
  17198. + 10: ea 10 87 65 orh r0,0x8765
  17199. + 14: ea 10 12 34 orh r0,0x1234
  17200. + 18: ea 10 00 00 orh r0,0x0
  17201. + 18: R_AVR32_HI16 \.text\+0x60
  17202. + 1c: ea 10 00 00 orh r0,0x0
  17203. + 1c: R_AVR32_HI16 extsym1
  17204. + 20: e4 10 87 65 andh r0,0x8765
  17205. + 24: e4 10 12 34 andh r0,0x1234
  17206. + 28: e4 10 00 00 andh r0,0x0
  17207. + 28: R_AVR32_HI16 \.text\+0x60
  17208. + 2c: e4 10 00 00 andh r0,0x0
  17209. + 2c: R_AVR32_HI16 extsym1
  17210. +
  17211. +00000030 <test_lwrd>:
  17212. + 30: e0 60 43 21 mov r0,17185
  17213. + 34: e0 60 56 78 mov r0,22136
  17214. + 38: e0 60 00 00 mov r0,0
  17215. + 38: R_AVR32_LO16 \.text\+0x60
  17216. + 3c: e0 60 00 00 mov r0,0
  17217. + 3c: R_AVR32_LO16 extsym1
  17218. + 40: e8 10 43 21 orl r0,0x4321
  17219. + 44: e8 10 56 78 orl r0,0x5678
  17220. + 48: e8 10 00 00 orl r0,0x0
  17221. + 48: R_AVR32_LO16 \.text\+0x60
  17222. + 4c: e8 10 00 00 orl r0,0x0
  17223. + 4c: R_AVR32_LO16 extsym1
  17224. + 50: e0 10 43 21 andl r0,0x4321
  17225. + 54: e0 10 56 78 andl r0,0x5678
  17226. + 58: e0 10 00 00 andl r0,0x0
  17227. + 58: R_AVR32_LO16 \.text\+0x60
  17228. + 5c: e0 10 00 00 andl r0,0x0
  17229. + 5c: R_AVR32_LO16 extsym1
  17230. --- /dev/null
  17231. +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.s
  17232. @@ -0,0 +1,39 @@
  17233. +
  17234. + .equ sym1, 0x12345678
  17235. +
  17236. + .text
  17237. + .global test_hwrd
  17238. +test_hwrd:
  17239. + mov r0, hi(0x87654321)
  17240. + mov r0, hi(sym1)
  17241. + mov r0, hi(sym2)
  17242. + mov r0, hi(extsym1)
  17243. +
  17244. + orh r0, hi(0x87654321)
  17245. + orh r0, hi(sym1)
  17246. + orh r0, hi(sym2)
  17247. + orh r0, hi(extsym1)
  17248. +
  17249. + andh r0, hi(0x87654321)
  17250. + andh r0, hi(sym1)
  17251. + andh r0, hi(sym2)
  17252. + andh r0, hi(extsym1)
  17253. +
  17254. + .global test_lwrd
  17255. +test_lwrd:
  17256. + mov r0, lo(0x87654321)
  17257. + mov r0, lo(sym1)
  17258. + mov r0, lo(sym2)
  17259. + mov r0, lo(extsym1)
  17260. +
  17261. + orl r0, lo(0x87654321)
  17262. + orl r0, lo(sym1)
  17263. + orl r0, lo(sym2)
  17264. + orl r0, lo(extsym1)
  17265. +
  17266. + andl r0, lo(0x87654321)
  17267. + andl r0, lo(sym1)
  17268. + andl r0, lo(sym2)
  17269. + andl r0, lo(extsym1)
  17270. +
  17271. +sym2:
  17272. --- /dev/null
  17273. +++ b/gas/testsuite/gas/avr32/jmptable.d
  17274. @@ -0,0 +1,20 @@
  17275. +#source: jmptable.s
  17276. +#as:
  17277. +#objdump: -dr
  17278. +#name: jmptable
  17279. +
  17280. +.*: +file format .*
  17281. +
  17282. +Disassembly of section \.text:
  17283. +
  17284. +00000000 <jmptable_test>:
  17285. + 0: fe c8 ff f4 sub r8,pc,-12
  17286. + 4: f0 00 00 2f add pc,r8,r0<<0x2
  17287. + 8: d7 03 nop
  17288. + a: 00 00 add r0,r0
  17289. + c: c0 38 rjmp 12 <jmptable_test\+0x12>
  17290. + e: c0 38 rjmp 14 <jmptable_test\+0x14>
  17291. + 10: c0 38 rjmp 16 <jmptable_test\+0x16>
  17292. + 12: d7 03 nop
  17293. + 14: d7 03 nop
  17294. + 16: d7 03 nop
  17295. --- /dev/null
  17296. +++ b/gas/testsuite/gas/avr32/jmptable_linkrelax.d
  17297. @@ -0,0 +1,25 @@
  17298. +#source: jmptable.s
  17299. +#as: --linkrelax
  17300. +#objdump: -dr
  17301. +#name: jmptable_linkrelax
  17302. +
  17303. +.*: +file format .*
  17304. +
  17305. +Disassembly of section \.text:
  17306. +
  17307. +00000000 <jmptable_test>:
  17308. + 0: fe c8 00 00 sub r8,pc,0
  17309. + 0: R_AVR32_16N_PCREL \.text\+0xc
  17310. + 4: f0 00 00 2f add pc,r8,r0<<0x2
  17311. + 8: d7 03 nop
  17312. + a: 00 00 add r0,r0
  17313. + a: R_AVR32_ALIGN \*ABS\*\+0x2
  17314. + c: c0 08 rjmp c <jmptable_test\+0xc>
  17315. + c: R_AVR32_11H_PCREL \.text\+0x12
  17316. + e: c0 08 rjmp e <jmptable_test\+0xe>
  17317. + e: R_AVR32_11H_PCREL \.text\+0x14
  17318. + 10: c0 08 rjmp 10 <jmptable_test\+0x10>
  17319. + 10: R_AVR32_11H_PCREL \.text\+0x16
  17320. + 12: d7 03 nop
  17321. + 14: d7 03 nop
  17322. + 16: d7 03 nop
  17323. --- /dev/null
  17324. +++ b/gas/testsuite/gas/avr32/jmptable.s
  17325. @@ -0,0 +1,14 @@
  17326. +
  17327. + .text
  17328. + .global jmptable_test
  17329. +jmptable_test:
  17330. + sub r8, pc, -(.L1 - .)
  17331. + add pc, r8, r0 << 2
  17332. + nop
  17333. + .align 2
  17334. +.L1: rjmp 1f
  17335. + rjmp 2f
  17336. + rjmp 3f
  17337. +1: nop
  17338. +2: nop
  17339. +3: nop
  17340. --- /dev/null
  17341. +++ b/gas/testsuite/gas/avr32/lda_nopic.d
  17342. @@ -0,0 +1,32 @@
  17343. +#source: lda.s
  17344. +#as:
  17345. +#objdump: -dr
  17346. +#name: lda_nopic
  17347. +
  17348. +.*: +file format .*
  17349. +
  17350. +Disassembly of section \.text:
  17351. +
  17352. +00000000 <lda_test>:
  17353. + 0: f2 c8 00 00 sub r8,r9,0
  17354. +
  17355. +00000004 <far_negative>:
  17356. + 4: f6 ca 00 00 sub r10,r11,0
  17357. + ...
  17358. + 8000: fe c0 7f fc sub r0,pc,32764
  17359. + 8004: 48 31 lddpc r1,8010 <far_negative\+0x800c>
  17360. + 8006: 48 42 lddpc r2,8014 <far_negative\+0x8010>
  17361. + 8008: 48 43 lddpc r3,8018 <far_negative\+0x8014>
  17362. + 800a: 48 54 lddpc r4,801c <far_negative\+0x8018>
  17363. + 800c: fe c5 80 04 sub r5,pc,-32764
  17364. + ...
  17365. + 8010: R_AVR32_32_CPENT \.text
  17366. + 8014: R_AVR32_32_CPENT \.data
  17367. + 8018: R_AVR32_32_CPENT undefined
  17368. + 801c: R_AVR32_32_CPENT \.text\+0x1001c
  17369. +
  17370. +00010008 <far_positive>:
  17371. + 10008: fa cc 00 00 sub r12,sp,0
  17372. + ...
  17373. +0001001c <toofar_positive>:
  17374. + 1001c: fe ce 00 00 sub lr,pc,0
  17375. --- /dev/null
  17376. +++ b/gas/testsuite/gas/avr32/lda_nopic_linkrelax.d
  17377. @@ -0,0 +1,41 @@
  17378. +#source: lda.s
  17379. +#as: --linkrelax
  17380. +#objdump: -dr
  17381. +#name: lda_nopic_linkrelax
  17382. +
  17383. +.*: +file format .*
  17384. +
  17385. +Disassembly of section \.text:
  17386. +
  17387. +00000000 <lda_test>:
  17388. + 0: f2 c8 00 00 sub r8,r9,0
  17389. +
  17390. +00000004 <far_negative>:
  17391. + 4: f6 ca 00 00 sub r10,r11,0
  17392. + \.\.\.
  17393. + 8000: 48 00 lddpc r0,8000 <far_negative\+0x7ffc>
  17394. + 8000: R_AVR32_9W_CP \.text\+0x800c
  17395. + 8002: 48 01 lddpc r1,8000 <far_negative\+0x7ffc>
  17396. + 8002: R_AVR32_9W_CP \.text\+0x8010
  17397. + 8004: 48 02 lddpc r2,8004 <far_negative\+0x8000>
  17398. + 8004: R_AVR32_9W_CP \.text\+0x8014
  17399. + 8006: 48 03 lddpc r3,8004 <far_negative\+0x8000>
  17400. + 8006: R_AVR32_9W_CP \.text\+0x8018
  17401. + 8008: 48 04 lddpc r4,8008 <far_negative\+0x8004>
  17402. + 8008: R_AVR32_9W_CP \.text\+0x801c
  17403. + 800a: 48 05 lddpc r5,8008 <far_negative\+0x8004>
  17404. + 800a: R_AVR32_9W_CP \.text\+0x8020
  17405. + \.\.\.
  17406. + 800c: R_AVR32_ALIGN \*ABS\*\+0x2
  17407. + 800c: R_AVR32_32_CPENT \.text\+0x4
  17408. + 8010: R_AVR32_32_CPENT \.text
  17409. + 8014: R_AVR32_32_CPENT \.data
  17410. + 8018: R_AVR32_32_CPENT undefined
  17411. + 801c: R_AVR32_32_CPENT \.text\+0x10020
  17412. + 8020: R_AVR32_32_CPENT \.text\+0x1000c
  17413. +
  17414. +0001000c <far_positive>:
  17415. + 1000c: fa cc 00 00 sub r12,sp,0
  17416. + \.\.\.
  17417. +00010020 <toofar_positive>:
  17418. + 10020: fe ce 00 00 sub lr,pc,0
  17419. --- /dev/null
  17420. +++ b/gas/testsuite/gas/avr32/lda_pic.d
  17421. @@ -0,0 +1,32 @@
  17422. +#source: lda.s
  17423. +#as: --pic
  17424. +#objdump: -dr
  17425. +#name: lda_pic
  17426. +
  17427. +.*: +file format .*
  17428. +
  17429. +Disassembly of section \.text:
  17430. +
  17431. +00000000 <lda_test>:
  17432. + 0: f2 c8 00 00 sub r8,r9,0
  17433. +
  17434. +00000004 <far_negative>:
  17435. + 4: f6 ca 00 00 sub r10,r11,0
  17436. + ...
  17437. + 8000: fe c0 7f fc sub r0,pc,32764
  17438. + 8004: ec f1 00 00 ld.w r1,r6\[0\]
  17439. + 8004: R_AVR32_GOT16S toofar_negative
  17440. + 8008: ec f2 00 00 ld.w r2,r6\[0\]
  17441. + 8008: R_AVR32_GOT16S different_section
  17442. + 800c: ec f3 00 00 ld.w r3,r6\[0\]
  17443. + 800c: R_AVR32_GOT16S undefined
  17444. + 8010: ec f4 00 00 ld.w r4,r6\[0\]
  17445. + 8010: R_AVR32_GOT16S toofar_positive
  17446. + 8014: fe c5 80 14 sub r5,pc,-32748
  17447. + ...
  17448. +
  17449. +00010000 <far_positive>:
  17450. + 10000: fa cc 00 00 sub r12,sp,0
  17451. + ...
  17452. +00010014 <toofar_positive>:
  17453. + 10014: fe ce 00 00 sub lr,pc,0
  17454. --- /dev/null
  17455. +++ b/gas/testsuite/gas/avr32/lda_pic_linkrelax.d
  17456. @@ -0,0 +1,40 @@
  17457. +#source: lda.s
  17458. +#as: --pic --linkrelax
  17459. +#objdump: -dr
  17460. +#name: lda_pic_linkrelax
  17461. +
  17462. +.*: +file format .*
  17463. +
  17464. +Disassembly of section \.text:
  17465. +
  17466. +00000000 <lda_test>:
  17467. + 0: f2 c8 00 00 sub r8,r9,0
  17468. +
  17469. +00000004 <far_negative>:
  17470. + 4: f6 ca 00 00 sub r10,r11,0
  17471. + ...
  17472. + 8000: e0 60 00 00 mov r0,0
  17473. + 8000: R_AVR32_LDA_GOT far_negative
  17474. + 8004: ec 00 03 20 ld\.w r0,r6\[r0<<0x2\]
  17475. + 8008: e0 61 00 00 mov r1,0
  17476. + 8008: R_AVR32_LDA_GOT toofar_negative
  17477. + 800c: ec 01 03 21 ld\.w r1,r6\[r1<<0x2\]
  17478. + 8010: e0 62 00 00 mov r2,0
  17479. + 8010: R_AVR32_LDA_GOT different_section
  17480. + 8014: ec 02 03 22 ld\.w r2,r6\[r2<<0x2\]
  17481. + 8018: e0 63 00 00 mov r3,0
  17482. + 8018: R_AVR32_LDA_GOT undefined
  17483. + 801c: ec 03 03 23 ld\.w r3,r6\[r3<<0x2\]
  17484. + 8020: e0 64 00 00 mov r4,0
  17485. + 8020: R_AVR32_LDA_GOT toofar_positive
  17486. + 8024: ec 04 03 24 ld\.w r4,r6\[r4<<0x2\]
  17487. + 8028: e0 65 00 00 mov r5,0
  17488. + 8028: R_AVR32_LDA_GOT far_positive
  17489. + 802c: ec 05 03 25 ld\.w r5,r6\[r5<<0x2\]
  17490. + ...
  17491. +
  17492. +00010018 <far_positive>:
  17493. + 10018: fa cc 00 00 sub r12,sp,0
  17494. + ...
  17495. +0001002c <toofar_positive>:
  17496. + 1002c: fe ce 00 00 sub lr,pc,0
  17497. --- /dev/null
  17498. +++ b/gas/testsuite/gas/avr32/lda.s
  17499. @@ -0,0 +1,30 @@
  17500. +
  17501. + .text
  17502. + .global lda_test
  17503. +lda_test:
  17504. +toofar_negative:
  17505. + sub r8, r9, 0
  17506. +far_negative:
  17507. + sub r10, r11, 0
  17508. +
  17509. + .fill 32760, 1, 0x00
  17510. +
  17511. + lda.w r0, far_negative
  17512. + lda.w r1, toofar_negative
  17513. + lda.w r2, different_section
  17514. + lda.w r3, undefined
  17515. + lda.w r4, toofar_positive
  17516. + lda.w r5, far_positive
  17517. +
  17518. + .cpool
  17519. +
  17520. + .fill 32744, 1, 0x00
  17521. +far_positive:
  17522. + sub r12, sp, 0
  17523. + .fill 16, 1, 0x00
  17524. +toofar_positive:
  17525. + sub lr, pc, 0
  17526. +
  17527. + .data
  17528. +different_section:
  17529. + .long 0x12345678
  17530. --- /dev/null
  17531. +++ b/gas/testsuite/gas/avr32/pcrel.d
  17532. @@ -0,0 +1,64 @@
  17533. +#as:
  17534. +#objdump: -dr
  17535. +#name: pcrel
  17536. +
  17537. +.*: +file format .*
  17538. +
  17539. +Disassembly of section \.text:
  17540. +
  17541. +00000000 <test_rjmp>:
  17542. + 0: d7 03 nop
  17543. + 2: c0 28 rjmp 6 <test_rjmp\+0x6>
  17544. + 4: d7 03 nop
  17545. + 6: e0 8f 00 00 bral 6 <test_rjmp\+0x6>
  17546. + 6: R_AVR32_22H_PCREL extsym10
  17547. +
  17548. +0000000a <test_rcall>:
  17549. + a: d7 03 nop
  17550. +0000000c <test_rcall2>:
  17551. + c: c0 2c rcall 10 <test_rcall2\+0x4>
  17552. + e: d7 03 nop
  17553. + 10: e0 a0 00 00 rcall 10 <test_rcall2\+0x4>
  17554. + 10: R_AVR32_22H_PCREL extsym21
  17555. +
  17556. +00000014 <test_branch>:
  17557. + 14: c0 31 brne 1a <test_branch\+0x6>
  17558. + 16: e0 8f 00 00 bral 16 <test_branch\+0x2>
  17559. + 16: R_AVR32_22H_PCREL test_branch
  17560. + 1a: e0 80 00 00 breq 1a <test_branch\+0x6>
  17561. + 1a: R_AVR32_22H_PCREL extsym21
  17562. +
  17563. +0000001e <test_lddpc>:
  17564. + 1e: 48 30 lddpc r0,28 <sym1>
  17565. + 20: 48 20 lddpc r0,28 <sym1>
  17566. + 22: fe f0 00 00 ld.w r0,pc\[0\]
  17567. + 22: R_AVR32_16B_PCREL extsym16
  17568. + \.\.\.
  17569. +
  17570. +00000028 <sym1>:
  17571. + 28: d7 03 nop
  17572. + 2a: d7 03 nop
  17573. +
  17574. +0000002c <test_local>:
  17575. + 2c: 48 20 lddpc r0,34 <test_local\+0x8>
  17576. + 2e: 48 30 lddpc r0,38 <test_local\+0xc>
  17577. + 30: 48 20 lddpc r0,38 <test_local\+0xc>
  17578. + 32: 00 00 add r0,r0
  17579. + 34: d7 03 nop
  17580. + 36: d7 03 nop
  17581. + 38: d7 03 nop
  17582. + 3a: d7 03 nop
  17583. +
  17584. +Disassembly of section \.text\.init:
  17585. +
  17586. +00000000 <test_inter_section>:
  17587. + 0: e0 a0 .. .. rcall [0-9a-f]+ <.*>
  17588. + 0: R_AVR32_22H_PCREL test_rcall
  17589. + 4: d7 03 nop
  17590. + 6: e0 a0 .. .. rcall [0-9a-f]+ <.*>
  17591. + 6: R_AVR32_22H_PCREL test_rcall
  17592. + a: e0 a0 .. .. rcall [0-9a-z]+ <.*>
  17593. + a: R_AVR32_22H_PCREL \.text\+0xc
  17594. + e: d7 03 nop
  17595. + 10: e0 a0 .. .. rcall [0-9a-f]+ <.*>
  17596. + 10: R_AVR32_22H_PCREL \.text\+0xc
  17597. --- /dev/null
  17598. +++ b/gas/testsuite/gas/avr32/pcrel.s
  17599. @@ -0,0 +1,57 @@
  17600. +
  17601. + .text
  17602. + .global test_rjmp
  17603. +test_rjmp:
  17604. + nop
  17605. + rjmp 0f
  17606. + nop
  17607. +0: rjmp extsym10
  17608. +
  17609. + .global test_rcall
  17610. +test_rcall:
  17611. + nop
  17612. +test_rcall2:
  17613. + rcall 0f
  17614. + nop
  17615. +0: rcall extsym21
  17616. +
  17617. + .global test_branch
  17618. +test_branch:
  17619. + brne 0f
  17620. + /* This will generate a reloc since test_branch is global */
  17621. + bral test_branch
  17622. +0: breq extsym21
  17623. +
  17624. + .global test_lddpc
  17625. +test_lddpc:
  17626. + lddpc r0,sym1
  17627. + lddpc r0,sym1
  17628. + lddpc r0,extsym16
  17629. +
  17630. + .align 2
  17631. +sym1: nop
  17632. + nop
  17633. +
  17634. + .global test_local
  17635. +test_local:
  17636. + lddpc r0, .LC1
  17637. + lddpc r0, .LC2
  17638. + lddpc r0, .LC1 + 0x4
  17639. +
  17640. + .align 2
  17641. +.LC1:
  17642. + nop
  17643. + nop
  17644. +.LC2:
  17645. + nop
  17646. + nop
  17647. +
  17648. + .section .text.init,"ax"
  17649. + .global test_inter_section
  17650. +test_inter_section:
  17651. + rcall test_rcall
  17652. + nop
  17653. + rcall test_rcall
  17654. + rcall test_rcall2
  17655. + nop
  17656. + rcall test_rcall2
  17657. --- /dev/null
  17658. +++ b/gas/testsuite/gas/avr32/pico.d
  17659. @@ -0,0 +1,149 @@
  17660. +#as:
  17661. +#objdump: -dr
  17662. +#name: pico
  17663. +
  17664. +.*: +file format .*
  17665. +
  17666. +Disassembly of section \.text:
  17667. +
  17668. +[0-9a-f]* <picosvmac>:
  17669. + *[0-9a-f]*: e1 a6 20 00 cop cp1,cr0,cr0,cr0,0xc
  17670. + *[0-9a-f]*: e1 a7 2b bb cop cp1,cr11,cr11,cr11,0xe
  17671. + *[0-9a-f]*: e1 a6 3a 05 cop cp1,cr10,cr0,cr5,0xd
  17672. + *[0-9a-f]*: e1 a7 36 90 cop cp1,cr6,cr9,cr0,0xf
  17673. +
  17674. +[0-9a-f]* <picosvmul>:
  17675. + *[0-9a-f]*: e1 a4 20 00 cop cp1,cr0,cr0,cr0,0x8
  17676. + *[0-9a-f]*: e1 a5 2b bb cop cp1,cr11,cr11,cr11,0xa
  17677. + *[0-9a-f]*: e1 a4 3a 05 cop cp1,cr10,cr0,cr5,0x9
  17678. + *[0-9a-f]*: e1 a5 36 90 cop cp1,cr6,cr9,cr0,0xb
  17679. +
  17680. +[0-9a-f]* <picovmac>:
  17681. + *[0-9a-f]*: e1 a2 20 00 cop cp1,cr0,cr0,cr0,0x4
  17682. + *[0-9a-f]*: e1 a3 2b bb cop cp1,cr11,cr11,cr11,0x6
  17683. + *[0-9a-f]*: e1 a2 3a 05 cop cp1,cr10,cr0,cr5,0x5
  17684. + *[0-9a-f]*: e1 a3 36 90 cop cp1,cr6,cr9,cr0,0x7
  17685. +
  17686. +[0-9a-f]* <picovmul>:
  17687. + *[0-9a-f]*: e1 a0 20 00 cop cp1,cr0,cr0,cr0,0x0
  17688. + *[0-9a-f]*: e1 a1 2b bb cop cp1,cr11,cr11,cr11,0x2
  17689. + *[0-9a-f]*: e1 a0 3a 05 cop cp1,cr10,cr0,cr5,0x1
  17690. + *[0-9a-f]*: e1 a1 36 90 cop cp1,cr6,cr9,cr0,0x3
  17691. +
  17692. +[0-9a-f]* <picold_d>:
  17693. + *[0-9a-f]*: e9 af 3e ff ldc\.d cp1,cr14,pc\[0x3fc\]
  17694. + *[0-9a-f]*: e9 a0 30 ff ldc\.d cp1,cr0,r0\[0x3fc\]
  17695. + *[0-9a-f]*: e9 a0 30 00 ldc\.d cp1,cr0,r0\[0x0\]
  17696. + *[0-9a-f]*: ef a8 26 50 ldc\.d cp1,cr6,--r8
  17697. + *[0-9a-f]*: ef a7 28 50 ldc\.d cp1,cr8,--r7
  17698. + *[0-9a-f]*: ef aa 32 65 ldc\.d cp1,cr2,r10\[r5<<0x2\]
  17699. + *[0-9a-f]*: ef a3 3c 46 ldc\.d cp1,cr12,r3\[r6\]
  17700. +
  17701. +[0-9a-f]* <picold_w>:
  17702. + *[0-9a-f]*: e9 af 2f ff ldc\.w cp1,cr15,pc\[0x3fc\]
  17703. + *[0-9a-f]*: e9 a0 20 ff ldc\.w cp1,cr0,r0\[0x3fc\]
  17704. + *[0-9a-f]*: e9 a0 20 00 ldc\.w cp1,cr0,r0\[0x0\]
  17705. + *[0-9a-f]*: ef a8 27 40 ldc\.w cp1,cr7,--r8
  17706. + *[0-9a-f]*: ef a7 28 40 ldc\.w cp1,cr8,--r7
  17707. + *[0-9a-f]*: ef aa 31 25 ldc\.w cp1,cr1,r10\[r5<<0x2\]
  17708. + *[0-9a-f]*: ef a3 3d 06 ldc\.w cp1,cr13,r3\[r6\]
  17709. +
  17710. +[0-9a-f]* <picoldm_d>:
  17711. + *[0-9a-f]*: ed af 24 ff ldcm\.d cp1,pc,cr0-cr15
  17712. + *[0-9a-f]*: ed a0 24 01 ldcm\.d cp1,r0,cr0-cr1
  17713. + *[0-9a-f]*: ed a7 24 80 ldcm\.d cp1,r7,cr14-cr15
  17714. + *[0-9a-f]*: ed a8 24 7f ldcm\.d cp1,r8,cr0-cr13
  17715. +
  17716. +[0-9a-f]* <picoldm_d_pu>:
  17717. + *[0-9a-f]*: ed af 34 ff ldcm\.d cp1,pc\+\+,cr0-cr15
  17718. + *[0-9a-f]*: ed a0 34 01 ldcm\.d cp1,r0\+\+,cr0-cr1
  17719. + *[0-9a-f]*: ed a7 34 80 ldcm\.d cp1,r7\+\+,cr14-cr15
  17720. + *[0-9a-f]*: ed a8 34 7f ldcm\.d cp1,r8\+\+,cr0-cr13
  17721. +
  17722. +[0-9a-f]* <picoldm_w>:
  17723. + *[0-9a-f]*: ed af 20 ff ldcm\.w cp1,pc,cr0-cr7
  17724. + *[0-9a-f]*: ed a0 20 01 ldcm\.w cp1,r0,cr0
  17725. + *[0-9a-f]*: ed a7 20 80 ldcm\.w cp1,r7,cr7
  17726. + *[0-9a-f]*: ed a8 20 7f ldcm\.w cp1,r8,cr0-cr6
  17727. + *[0-9a-f]*: ed af 21 ff ldcm\.w cp1,pc,cr8-cr15
  17728. + *[0-9a-f]*: ed a0 21 01 ldcm\.w cp1,r0,cr8
  17729. + *[0-9a-f]*: ed a7 21 80 ldcm\.w cp1,r7,cr15
  17730. + *[0-9a-f]*: ed a8 21 7f ldcm\.w cp1,r8,cr8-cr14
  17731. +
  17732. +[0-9a-f]* <picoldm_w_pu>:
  17733. + *[0-9a-f]*: ed af 30 ff ldcm\.w cp1,pc\+\+,cr0-cr7
  17734. + *[0-9a-f]*: ed a0 30 01 ldcm\.w cp1,r0\+\+,cr0
  17735. + *[0-9a-f]*: ed a7 30 80 ldcm\.w cp1,r7\+\+,cr7
  17736. + *[0-9a-f]*: ed a8 30 7f ldcm\.w cp1,r8\+\+,cr0-cr6
  17737. + *[0-9a-f]*: ed af 31 ff ldcm\.w cp1,pc\+\+,cr8-cr15
  17738. + *[0-9a-f]*: ed a0 31 01 ldcm\.w cp1,r0\+\+,cr8
  17739. + *[0-9a-f]*: ed a7 31 80 ldcm\.w cp1,r7\+\+,cr15
  17740. + *[0-9a-f]*: ed a8 31 7f ldcm\.w cp1,r8\+\+,cr8-cr14
  17741. +
  17742. +[0-9a-f]* <picomv_d>:
  17743. + *[0-9a-f]*: ef ae 2e 30 mvrc\.d cp1,cr14,lr
  17744. + *[0-9a-f]*: ef a0 20 30 mvrc\.d cp1,cr0,r0
  17745. + *[0-9a-f]*: ef a8 26 30 mvrc\.d cp1,cr6,r8
  17746. + *[0-9a-f]*: ef a6 28 30 mvrc\.d cp1,cr8,r6
  17747. + *[0-9a-f]*: ef ae 2e 10 mvcr\.d cp1,lr,cr14
  17748. + *[0-9a-f]*: ef a0 20 10 mvcr\.d cp1,r0,cr0
  17749. + *[0-9a-f]*: ef a8 26 10 mvcr\.d cp1,r8,cr6
  17750. + *[0-9a-f]*: ef a6 28 10 mvcr\.d cp1,r6,cr8
  17751. +
  17752. +[0-9a-f]* <picomv_w>:
  17753. + *[0-9a-f]*: ef af 2f 20 mvrc\.w cp1,cr15,pc
  17754. + *[0-9a-f]*: ef a0 20 20 mvrc\.w cp1,cr0,r0
  17755. + *[0-9a-f]*: ef a8 27 20 mvrc\.w cp1,cr7,r8
  17756. + *[0-9a-f]*: ef a7 28 20 mvrc\.w cp1,cr8,r7
  17757. + *[0-9a-f]*: ef af 2f 00 mvcr\.w cp1,pc,cr15
  17758. + *[0-9a-f]*: ef a0 20 00 mvcr\.w cp1,r0,cr0
  17759. + *[0-9a-f]*: ef a8 27 00 mvcr\.w cp1,r8,cr7
  17760. + *[0-9a-f]*: ef a7 28 00 mvcr\.w cp1,r7,cr8
  17761. +
  17762. +[0-9a-f]* <picost_d>:
  17763. + *[0-9a-f]*: eb af 3e ff stc\.d cp1,pc\[0x3fc\],cr14
  17764. + *[0-9a-f]*: eb a0 30 00 stc\.d cp1,r0\[0x0\],cr0
  17765. + *[0-9a-f]*: ef a8 26 70 stc\.d cp1,r8\+\+,cr6
  17766. + *[0-9a-f]*: ef a7 28 70 stc\.d cp1,r7\+\+,cr8
  17767. + *[0-9a-f]*: ef aa 32 e5 stc\.d cp1,r10\[r5<<0x2\],cr2
  17768. + *[0-9a-f]*: ef a3 3c c6 stc\.d cp1,r3\[r6\],cr12
  17769. +
  17770. +[0-9a-f]* <picost_w>:
  17771. + *[0-9a-f]*: eb af 2f ff stc\.w cp1,pc\[0x3fc\],cr15
  17772. + *[0-9a-f]*: eb a0 20 00 stc\.w cp1,r0\[0x0\],cr0
  17773. + *[0-9a-f]*: ef a8 27 60 stc\.w cp1,r8\+\+,cr7
  17774. + *[0-9a-f]*: ef a7 28 60 stc\.w cp1,r7\+\+,cr8
  17775. + *[0-9a-f]*: ef aa 31 a5 stc\.w cp1,r10\[r5<<0x2\],cr1
  17776. + *[0-9a-f]*: ef a3 3d 86 stc\.w cp1,r3\[r6\],cr13
  17777. +
  17778. +[0-9a-f]* <picostm_d>:
  17779. + *[0-9a-f]*: ed af 25 ff stcm\.d cp1,pc,cr0-cr15
  17780. + *[0-9a-f]*: ed a0 25 01 stcm\.d cp1,r0,cr0-cr1
  17781. + *[0-9a-f]*: ed a7 25 80 stcm\.d cp1,r7,cr14-cr15
  17782. + *[0-9a-f]*: ed a8 25 7f stcm\.d cp1,r8,cr0-cr13
  17783. +
  17784. +[0-9a-f]* <picostm_d_pu>:
  17785. + *[0-9a-f]*: ed af 35 ff stcm\.d cp1,--pc,cr0-cr15
  17786. + *[0-9a-f]*: ed a0 35 01 stcm\.d cp1,--r0,cr0-cr1
  17787. + *[0-9a-f]*: ed a7 35 80 stcm\.d cp1,--r7,cr14-cr15
  17788. + *[0-9a-f]*: ed a8 35 7f stcm\.d cp1,--r8,cr0-cr13
  17789. +
  17790. +[0-9a-f]* <picostm_w>:
  17791. + *[0-9a-f]*: ed af 22 ff stcm\.w cp1,pc,cr0-cr7
  17792. + *[0-9a-f]*: ed a0 22 01 stcm\.w cp1,r0,cr0
  17793. + *[0-9a-f]*: ed a7 22 80 stcm\.w cp1,r7,cr7
  17794. + *[0-9a-f]*: ed a8 22 7f stcm\.w cp1,r8,cr0-cr6
  17795. + *[0-9a-f]*: ed af 23 ff stcm\.w cp1,pc,cr8-cr15
  17796. + *[0-9a-f]*: ed a0 23 01 stcm\.w cp1,r0,cr8
  17797. + *[0-9a-f]*: ed a7 23 80 stcm\.w cp1,r7,cr15
  17798. + *[0-9a-f]*: ed a8 23 7f stcm\.w cp1,r8,cr8-cr14
  17799. +
  17800. +[0-9a-f]* <picostm_w_pu>:
  17801. + *[0-9a-f]*: ed af 32 ff stcm\.w cp1,--pc,cr0-cr7
  17802. + *[0-9a-f]*: ed a0 32 01 stcm\.w cp1,--r0,cr0
  17803. + *[0-9a-f]*: ed a7 32 80 stcm\.w cp1,--r7,cr7
  17804. + *[0-9a-f]*: ed a8 32 7f stcm\.w cp1,--r8,cr0-cr6
  17805. + *[0-9a-f]*: ed af 33 ff stcm\.w cp1,--pc,cr8-cr15
  17806. + *[0-9a-f]*: ed a0 33 01 stcm\.w cp1,--r0,cr8
  17807. + *[0-9a-f]*: ed a7 33 80 stcm\.w cp1,--r7,cr15
  17808. + *[0-9a-f]*: ed a8 33 7f stcm\.w cp1,--r8,cr8-cr14
  17809. --- /dev/null
  17810. +++ b/gas/testsuite/gas/avr32/pico.s
  17811. @@ -0,0 +1,144 @@
  17812. +
  17813. + .text
  17814. + .global picosvmac
  17815. +picosvmac:
  17816. + picosvmac out0, in0, in0, in0
  17817. + picosvmac out2, in11, in11, in11
  17818. + picosvmac out1, in10, in0, in5
  17819. + picosvmac out3, in6, in9, in0
  17820. + .global picosvmul
  17821. +picosvmul:
  17822. + picosvmul out0, in0, in0, in0
  17823. + picosvmul out2, in11, in11, in11
  17824. + picosvmul out1, in10, in0, in5
  17825. + picosvmul out3, in6, in9, in0
  17826. + .global picovmac
  17827. +picovmac:
  17828. + picovmac out0, in0, in0, in0
  17829. + picovmac out2, in11, in11, in11
  17830. + picovmac out1, in10, in0, in5
  17831. + picovmac out3, in6, in9, in0
  17832. + .global picovmul
  17833. +picovmul:
  17834. + picovmul out0, in0, in0, in0
  17835. + picovmul out2, in11, in11, in11
  17836. + picovmul out1, in10, in0, in5
  17837. + picovmul out3, in6, in9, in0
  17838. + .global picold_d
  17839. +picold_d:
  17840. + picold.d vmu2_out, pc[1020]
  17841. + picold.d inpix2, r0[1020]
  17842. + picold.d inpix2, r0[0]
  17843. + picold.d coeff0_a, --r8
  17844. + picold.d coeff1_a, --r7
  17845. + picold.d inpix0, r10[r5 << 2]
  17846. + picold.d vmu0_out, r3[r6 << 0]
  17847. + .global picold_w
  17848. +picold_w:
  17849. + picold.w config, pc[1020]
  17850. + picold.w inpix2, r0[1020]
  17851. + picold.w inpix2, r0[0]
  17852. + picold.w coeff0_b, --r8
  17853. + picold.w coeff1_a, --r7
  17854. + picold.w inpix1, r10[r5 << 2]
  17855. + picold.w vmu1_out, r3[r6 << 0]
  17856. + .global picoldm_d
  17857. +picoldm_d:
  17858. + picoldm.d pc, inpix2-config
  17859. + picoldm.d r0, inpix2, inpix1
  17860. + picoldm.d r7, vmu2_out, config
  17861. + picoldm.d r8, inpix2-vmu1_out
  17862. + .global picoldm_d_pu
  17863. +picoldm_d_pu:
  17864. + picoldm.d pc++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
  17865. + picoldm.d r0++, inpix2, inpix1
  17866. + picoldm.d r7++, vmu2_out, config
  17867. + picoldm.d r8++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
  17868. + .global picoldm_w
  17869. +picoldm_w:
  17870. + picoldm.w pc, inpix2-coeff0_b
  17871. + picoldm.w r0, inpix2
  17872. + picoldm.w r7, coeff0_b
  17873. + picoldm.w r8, inpix2-coeff0_a
  17874. + picoldm.w pc, coeff1_a-config
  17875. + picoldm.w r0, coeff1_a
  17876. + picoldm.w r7, config
  17877. + picoldm.w r8, coeff1_a-vmu2_out
  17878. + .global picoldm_w_pu
  17879. +picoldm_w_pu:
  17880. + picoldm.w pc++, inpix2-coeff0_b
  17881. + picoldm.w r0++, inpix2
  17882. + picoldm.w r7++, coeff0_b
  17883. + picoldm.w r8++, inpix2-coeff0_a
  17884. + picoldm.w pc++, coeff1_a-config
  17885. + picoldm.w r0++, coeff1_a
  17886. + picoldm.w r7++, config
  17887. + picoldm.w r8++, coeff1_a-vmu2_out
  17888. + .global picomv_d
  17889. +picomv_d:
  17890. + picomv.d vmu2_out, lr
  17891. + picomv.d inpix2, r0
  17892. + picomv.d coeff0_a, r8
  17893. + picomv.d coeff1_a, r6
  17894. + picomv.d pc, vmu2_out
  17895. + picomv.d r0, inpix2
  17896. + picomv.d r8, coeff0_a
  17897. + picomv.d r6, coeff1_a
  17898. + .global picomv_w
  17899. +picomv_w:
  17900. + picomv.w config, pc
  17901. + picomv.w inpix2, r0
  17902. + picomv.w coeff0_b, r8
  17903. + picomv.w coeff1_a, r7
  17904. + picomv.w pc, config
  17905. + picomv.w r0, inpix2
  17906. + picomv.w r8, coeff0_b
  17907. + picomv.w r7, coeff1_a
  17908. + .global picost_d
  17909. +picost_d:
  17910. + picost.d pc[1020], vmu2_out
  17911. + picost.d r0[0], inpix2
  17912. + picost.d r8++, coeff0_a
  17913. + picost.d r7++, coeff1_a
  17914. + picost.d r10[r5 << 2], inpix0
  17915. + picost.d r3[r6 << 0], vmu0_out
  17916. + .global picost_w
  17917. +picost_w:
  17918. + picost.w pc[1020], config
  17919. + picost.w r0[0], inpix2
  17920. + picost.w r8++, coeff0_b
  17921. + picost.w r7++, coeff1_a
  17922. + picost.w r10[r5 << 2], inpix1
  17923. + picost.w r3[r6 << 0], vmu1_out
  17924. + .global picostm_d
  17925. +picostm_d:
  17926. + picostm.d pc, inpix2-config
  17927. + picostm.d r0, inpix2, inpix1
  17928. + picostm.d r7, vmu2_out, config
  17929. + picostm.d r8, inpix2-vmu1_out
  17930. + .global picostm_d_pu
  17931. +picostm_d_pu:
  17932. + picostm.d --pc, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
  17933. + picostm.d --r0, inpix2, inpix1
  17934. + picostm.d --r7, vmu2_out, config
  17935. + picostm.d --r8, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
  17936. + .global picostm_w
  17937. +picostm_w:
  17938. + picostm.w pc, inpix2-coeff0_b
  17939. + picostm.w r0, inpix2
  17940. + picostm.w r7, coeff0_b
  17941. + picostm.w r8, inpix2-coeff0_a
  17942. + picostm.w pc, coeff1_a-config
  17943. + picostm.w r0, coeff1_a
  17944. + picostm.w r7, config
  17945. + picostm.w r8, coeff1_a-vmu2_out
  17946. + .global picostm_w_pu
  17947. +picostm_w_pu:
  17948. + picostm.w --pc, inpix2-coeff0_b
  17949. + picostm.w --r0, inpix2
  17950. + picostm.w --r7, coeff0_b
  17951. + picostm.w --r8, inpix2-coeff0_a
  17952. + picostm.w --pc, coeff1_a-config
  17953. + picostm.w --r0, coeff1_a
  17954. + picostm.w --r7, config
  17955. + picostm.w --r8, coeff1_a-vmu2_out
  17956. --- /dev/null
  17957. +++ b/gas/testsuite/gas/avr32/pic_reloc.d
  17958. @@ -0,0 +1,27 @@
  17959. +#as:
  17960. +#objdump: -dr
  17961. +#name: pic_reloc
  17962. +
  17963. +.*: +file format .*
  17964. +
  17965. +Disassembly of section \.text:
  17966. +
  17967. +00000000 <mcall_got>:
  17968. + 0: f0 16 00 00 mcall r6\[0\]
  17969. + 0: R_AVR32_GOT18SW extfunc
  17970. + 4: f0 16 00 00 mcall r6\[0\]
  17971. + 4: R_AVR32_GOT18SW \.L1
  17972. + 8: f0 16 00 00 mcall r6\[0\]
  17973. + 8: R_AVR32_GOT18SW \.L2
  17974. + c: f0 16 00 00 mcall r6\[0\]
  17975. + c: R_AVR32_GOT18SW mcall_got
  17976. +
  17977. +00000010 <ldw_got>:
  17978. + 10: ec f0 00 00 ld.w r0,r6\[0\]
  17979. + 10: R_AVR32_GOT16S extvar
  17980. + 14: ec f0 00 00 ld.w r0,r6\[0\]
  17981. + 14: R_AVR32_GOT16S \.L3
  17982. + 18: ec f0 00 00 ld.w r0,r6\[0\]
  17983. + 18: R_AVR32_GOT16S \.L4
  17984. + 1c: ec f0 00 00 ld.w r0,r6\[0\]
  17985. + 1c: R_AVR32_GOT16S ldw_got
  17986. --- /dev/null
  17987. +++ b/gas/testsuite/gas/avr32/pic_reloc.s
  17988. @@ -0,0 +1,18 @@
  17989. +
  17990. + .text
  17991. + .global mcall_got
  17992. +mcall_got:
  17993. +.L1:
  17994. + mcall r6[extfunc@got]
  17995. + mcall r6[.L1@got]
  17996. + mcall r6[.L2@got]
  17997. + mcall r6[mcall_got@got]
  17998. +.L2:
  17999. +
  18000. + .global ldw_got
  18001. +ldw_got:
  18002. +.L3: ld.w r0,r6[extvar@got]
  18003. + ld.w r0,r6[.L3@got]
  18004. + ld.w r0,r6[.L4@got]
  18005. + ld.w r0,r6[ldw_got@got]
  18006. +.L4:
  18007. --- /dev/null
  18008. +++ b/gas/testsuite/gas/avr32/symdiff.d
  18009. @@ -0,0 +1,24 @@
  18010. +#source: symdiff.s
  18011. +#as:
  18012. +#objdump: -dr
  18013. +#name: symdiff
  18014. +
  18015. +.*: +file format .*
  18016. +
  18017. +Disassembly of section \.text:
  18018. +
  18019. +00000000 <diff32>:
  18020. + 0: 00 00 add r0,r0
  18021. + 2: 00 04 add r4,r0
  18022. +
  18023. +00000004 <diff16>:
  18024. + 4: 00 04 add r4,r0
  18025. +
  18026. +00000006 <diff8>:
  18027. + 6: 04 00 add r0,r2
  18028. +
  18029. +00000008 <symdiff_test>:
  18030. + 8: d7 03 nop
  18031. + a: d7 03 nop
  18032. + c: d7 03 nop
  18033. + e: d7 03 nop
  18034. --- /dev/null
  18035. +++ b/gas/testsuite/gas/avr32/symdiff_linkrelax.d
  18036. @@ -0,0 +1,28 @@
  18037. +#source: symdiff.s
  18038. +#as: --linkrelax
  18039. +#objdump: -dr
  18040. +#name: symdiff_linkrelax
  18041. +
  18042. +.*: +file format .*
  18043. +
  18044. +Disassembly of section \.text:
  18045. +
  18046. +00000000 <diff32>:
  18047. + 0: 00 00 add r0,r0
  18048. + 0: R_AVR32_DIFF32 \.text\+0xa
  18049. + 2: 00 04 add r4,r0
  18050. +
  18051. +00000004 <diff16>:
  18052. + 4: 00 04 add r4,r0
  18053. + 4: R_AVR32_DIFF16 \.text\+0xa
  18054. +
  18055. +00000006 <diff8>:
  18056. + 6: 04 00 add r0,r2
  18057. + 6: R_AVR32_DIFF8 \.text\+0xa
  18058. + 7: R_AVR32_ALIGN \*ABS\*\+0x1
  18059. +
  18060. +00000008 <symdiff_test>:
  18061. + 8: d7 03 nop
  18062. + a: d7 03 nop
  18063. + c: d7 03 nop
  18064. + e: d7 03 nop
  18065. --- /dev/null
  18066. +++ b/gas/testsuite/gas/avr32/symdiff.s
  18067. @@ -0,0 +1,19 @@
  18068. +
  18069. + .text
  18070. + .global diff32
  18071. +diff32:
  18072. + .long .L2 - .L1
  18073. + .global diff16
  18074. +diff16:
  18075. + .short .L2 - .L1
  18076. + .global diff8
  18077. +diff8:
  18078. + .byte .L2 - .L1
  18079. +
  18080. + .global symdiff_test
  18081. + .align 1
  18082. +symdiff_test:
  18083. + nop
  18084. +.L1: nop
  18085. + nop
  18086. +.L2: nop
  18087. --- a/gas/write.c
  18088. +++ b/gas/write.c
  18089. @@ -2011,6 +2011,10 @@ relax_frag (segT segment, fragS *fragP,
  18090. #endif /* defined (TC_GENERIC_RELAX_TABLE) */
  18091. +#ifdef TC_RELAX_ALIGN
  18092. +#define RELAX_ALIGN(SEG, FRAG, ADDR) TC_RELAX_ALIGN(SEG, FRAG, ADDR)
  18093. +#else
  18094. +#define RELAX_ALIGN(SEG, FRAG, ADDR) relax_align(ADDR, (FRAG)->fr_offset)
  18095. /* Relax_align. Advance location counter to next address that has 'alignment'
  18096. lowest order bits all 0s, return size of adjustment made. */
  18097. static relax_addressT
  18098. @@ -2030,6 +2034,7 @@ relax_align (register relax_addressT add
  18099. #endif
  18100. return (new_address - address);
  18101. }
  18102. +#endif
  18103. /* Now we have a segment, not a crowd of sub-segments, we can make
  18104. fr_address values.
  18105. @@ -2073,7 +2078,7 @@ relax_segment (struct frag *segment_frag
  18106. case rs_align_code:
  18107. case rs_align_test:
  18108. {
  18109. - addressT offset = relax_align (address, (int) fragP->fr_offset);
  18110. + addressT offset = RELAX_ALIGN(segment, fragP, address);
  18111. if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype)
  18112. offset = 0;
  18113. @@ -2280,10 +2285,10 @@ relax_segment (struct frag *segment_frag
  18114. {
  18115. addressT oldoff, newoff;
  18116. - oldoff = relax_align (was_address + fragP->fr_fix,
  18117. - (int) offset);
  18118. - newoff = relax_align (address + fragP->fr_fix,
  18119. - (int) offset);
  18120. + oldoff = RELAX_ALIGN (segment, fragP,
  18121. + was_address + fragP->fr_fix);
  18122. + newoff = RELAX_ALIGN (segment, fragP,
  18123. + address + fragP->fr_fix);
  18124. if (fragP->fr_subtype != 0)
  18125. {
  18126. --- a/include/dis-asm.h
  18127. +++ b/include/dis-asm.h
  18128. @@ -222,6 +222,7 @@ typedef int (*disassembler_ftype) (bfd_v
  18129. extern int print_insn_alpha (bfd_vma, disassemble_info *);
  18130. extern int print_insn_avr (bfd_vma, disassemble_info *);
  18131. +extern int print_insn_avr32 (bfd_vma, disassemble_info *);
  18132. extern int print_insn_bfin (bfd_vma, disassemble_info *);
  18133. extern int print_insn_big_arm (bfd_vma, disassemble_info *);
  18134. extern int print_insn_big_mips (bfd_vma, disassemble_info *);
  18135. @@ -304,7 +305,9 @@ extern void print_i386_disassembler_opti
  18136. extern void print_mips_disassembler_options (FILE *);
  18137. extern void print_ppc_disassembler_options (FILE *);
  18138. extern void print_arm_disassembler_options (FILE *);
  18139. +extern void print_avr32_disassembler_options (FILE *);
  18140. extern void parse_arm_disassembler_option (char *);
  18141. +extern void parse_avr32_disassembler_option (char *);
  18142. extern void print_s390_disassembler_options (FILE *);
  18143. extern int get_arm_regname_num_options (void);
  18144. extern int set_arm_regname_option (int);
  18145. --- /dev/null
  18146. +++ b/include/elf/avr32.h
  18147. @@ -0,0 +1,98 @@
  18148. +/* AVR32 ELF support for BFD.
  18149. + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  18150. +
  18151. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  18152. +
  18153. + This file is part of BFD, the Binary File Descriptor library.
  18154. +
  18155. + This program is free software; you can redistribute it and/or
  18156. + modify it under the terms of the GNU General Public License as
  18157. + published by the Free Software Foundation; either version 2 of the
  18158. + License, or (at your option) any later version.
  18159. +
  18160. + This program is distributed in the hope that it will be useful, but
  18161. + WITHOUT ANY WARRANTY; without even the implied warranty of
  18162. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18163. + General Public License for more details.
  18164. +
  18165. + You should have received a copy of the GNU General Public License
  18166. + along with this program; if not, write to the Free Software
  18167. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  18168. + 02111-1307, USA. */
  18169. +
  18170. +#include "elf/reloc-macros.h"
  18171. +
  18172. +/* CPU-specific flags for the ELF header e_flags field */
  18173. +#define EF_AVR32_LINKRELAX 0x01
  18174. +#define EF_AVR32_PIC 0x02
  18175. +
  18176. +START_RELOC_NUMBERS (elf_avr32_reloc_type)
  18177. + RELOC_NUMBER (R_AVR32_NONE, 0)
  18178. +
  18179. + /* Data Relocations */
  18180. + RELOC_NUMBER (R_AVR32_32, 1)
  18181. + RELOC_NUMBER (R_AVR32_16, 2)
  18182. + RELOC_NUMBER (R_AVR32_8, 3)
  18183. + RELOC_NUMBER (R_AVR32_32_PCREL, 4)
  18184. + RELOC_NUMBER (R_AVR32_16_PCREL, 5)
  18185. + RELOC_NUMBER (R_AVR32_8_PCREL, 6)
  18186. + RELOC_NUMBER (R_AVR32_DIFF32, 7)
  18187. + RELOC_NUMBER (R_AVR32_DIFF16, 8)
  18188. + RELOC_NUMBER (R_AVR32_DIFF8, 9)
  18189. + RELOC_NUMBER (R_AVR32_GOT32, 10)
  18190. + RELOC_NUMBER (R_AVR32_GOT16, 11)
  18191. + RELOC_NUMBER (R_AVR32_GOT8, 12)
  18192. +
  18193. + /* Normal Code Relocations */
  18194. + RELOC_NUMBER (R_AVR32_21S, 13)
  18195. + RELOC_NUMBER (R_AVR32_16U, 14)
  18196. + RELOC_NUMBER (R_AVR32_16S, 15)
  18197. + RELOC_NUMBER (R_AVR32_8S, 16)
  18198. + RELOC_NUMBER (R_AVR32_8S_EXT, 17)
  18199. +
  18200. + /* PC-Relative Code Relocations */
  18201. + RELOC_NUMBER (R_AVR32_22H_PCREL, 18)
  18202. + RELOC_NUMBER (R_AVR32_18W_PCREL, 19)
  18203. + RELOC_NUMBER (R_AVR32_16B_PCREL, 20)
  18204. + RELOC_NUMBER (R_AVR32_16N_PCREL, 21)
  18205. + RELOC_NUMBER (R_AVR32_14UW_PCREL, 22)
  18206. + RELOC_NUMBER (R_AVR32_11H_PCREL, 23)
  18207. + RELOC_NUMBER (R_AVR32_10UW_PCREL, 24)
  18208. + RELOC_NUMBER (R_AVR32_9H_PCREL, 25)
  18209. + RELOC_NUMBER (R_AVR32_9UW_PCREL, 26)
  18210. +
  18211. + /* Special Code Relocations */
  18212. + RELOC_NUMBER (R_AVR32_HI16, 27)
  18213. + RELOC_NUMBER (R_AVR32_LO16, 28)
  18214. +
  18215. + /* PIC Relocations */
  18216. + RELOC_NUMBER (R_AVR32_GOTPC, 29)
  18217. + RELOC_NUMBER (R_AVR32_GOTCALL, 30)
  18218. + RELOC_NUMBER (R_AVR32_LDA_GOT, 31)
  18219. + RELOC_NUMBER (R_AVR32_GOT21S, 32)
  18220. + RELOC_NUMBER (R_AVR32_GOT18SW, 33)
  18221. + RELOC_NUMBER (R_AVR32_GOT16S, 34)
  18222. + RELOC_NUMBER (R_AVR32_GOT7UW, 35)
  18223. +
  18224. + /* Constant Pool Relocations */
  18225. + RELOC_NUMBER (R_AVR32_32_CPENT, 36)
  18226. + RELOC_NUMBER (R_AVR32_CPCALL, 37)
  18227. + RELOC_NUMBER (R_AVR32_16_CP, 38)
  18228. + RELOC_NUMBER (R_AVR32_9W_CP, 39)
  18229. +
  18230. + /* Dynamic Relocations */
  18231. + RELOC_NUMBER (R_AVR32_RELATIVE, 40)
  18232. + RELOC_NUMBER (R_AVR32_GLOB_DAT, 41)
  18233. + RELOC_NUMBER (R_AVR32_JMP_SLOT, 42)
  18234. +
  18235. + /* Linkrelax Information */
  18236. + RELOC_NUMBER (R_AVR32_ALIGN, 43)
  18237. +
  18238. + RELOC_NUMBER (R_AVR32_15S, 44)
  18239. +
  18240. +END_RELOC_NUMBERS (R_AVR32_max)
  18241. +
  18242. +/* Processor specific dynamic array tags. */
  18243. +
  18244. +/* The total size in bytes of the Global Offset Table */
  18245. +#define DT_AVR32_GOTSZ 0x70000001
  18246. --- a/include/elf/common.h
  18247. +++ b/include/elf/common.h
  18248. @@ -286,7 +286,7 @@
  18249. #define EM_INTEL182 182 /* Reserved by Intel */
  18250. #define EM_res183 183 /* Reserved by ARM */
  18251. #define EM_res184 184 /* Reserved by ARM */
  18252. -#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family */
  18253. +#define EM_AVR32_OLD 185 /* Atmel Corporation 32-bit microprocessor family */
  18254. #define EM_STM8 186 /* STMicroeletronics STM8 8-bit microcontroller */
  18255. #define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */
  18256. #define EM_TILEPRO 188 /* Tilera TILEPro multicore architecture family */
  18257. @@ -365,6 +365,9 @@
  18258. /* V850 backend magic number. Written in the absense of an ABI. */
  18259. #define EM_CYGNUS_V850 0x9080
  18260. +/* AVR32 magic number, picked by IAR Systems. */
  18261. +#define EM_AVR32 0x18ad
  18262. +
  18263. /* old S/390 backend magic number. Written in the absence of an ABI. */
  18264. #define EM_S390_OLD 0xa390
  18265. --- a/ld/configdoc.texi
  18266. +++ b/ld/configdoc.texi
  18267. @@ -7,6 +7,7 @@
  18268. @set H8300
  18269. @set HPPA
  18270. @set I960
  18271. +@set AVR32
  18272. @set M68HC11
  18273. @set M68K
  18274. @set MMIX
  18275. --- a/ld/configure.tgt
  18276. +++ b/ld/configure.tgt
  18277. @@ -112,6 +112,9 @@ xscale-*-elf) targ_emul=armelf
  18278. avr-*-*) targ_emul=avr2
  18279. targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6"
  18280. ;;
  18281. +avr32-*-none) targ_emul=avr32elf_ap7000
  18282. + targ_extra_emuls="avr32elf_ap7001 avr32elf_ap7002 avr32elf_ap7200 avr32elf_uc3a0128 avr32elf_uc3a0256 avr32elf_uc3a0512 avr32elf_uc3a0512es avr32elf_uc3a1128 avr32elf_uc3a1256 avr32elf_uc3a1512es avr32elf_uc3a1512 avr32elf_uc3a364 avr32elf_uc3a364s avr32elf_uc3a3128 avr32elf_uc3a3128s avr32elf_uc3a3256 avr32elf_uc3a3256s avr32elf_uc3b064 avr32elf_uc3b0128 avr32elf_uc3b0256es avr32elf_uc3b0256 avr32elf_uc3b0512 avr32elf_uc3b0512revc avr32elf_uc3b164 avr32elf_uc3b1128 avr32elf_uc3b1256es avr32elf_uc3b1256 avr32elf_uc3b1512 avr32elf_uc3b1512revc avr32elf_uc3c0512crevc avr32elf_uc3c1512crevc avr32elf_uc3c2512crevc avr32elf_atuc3l0256 avr32elf_mxt768e avr32elf_uc3l064 avr32elf_uc3l032 avr32elf_uc3l016 avr32elf_uc3l064revb avr32elf_uc3c064c avr32elf_uc3c0128c avr32elf_uc3c0256c avr32elf_uc3c0512c avr32elf_uc3c164c avr32elf_uc3c1128c avr32elf_uc3c1256c avr32elf_uc3c1512c avr32elf_uc3c264c avr32elf_uc3c2128c avr32elf_uc3c2256c avr32elf_uc3c2512c" ;;
  18283. +avr32-*-linux*) targ_emul=avr32linux ;;
  18284. bfin-*-elf) targ_emul=elf32bfin;
  18285. targ_extra_emuls="elf32bfinfd"
  18286. targ_extra_libpath=$targ_extra_emuls
  18287. --- /dev/null
  18288. +++ b/ld/emulparams/avr32elf.sh
  18289. @@ -0,0 +1,402 @@
  18290. +# This script is called from ld/genscript.sh
  18291. +# There is a difference on how 'bash' and POSIX handles
  18292. +# the '.' (source) command in a script.
  18293. +# genscript.sh calls this script with argument ${EMULATION_NAME}
  18294. +# but that will fail on POSIX compilant shells like 'sh' or 'dash'
  18295. +# therefor I use the variable directly instead of $1
  18296. +EMULATION=${EMULATION_NAME}
  18297. +SCRIPT_NAME=avr32
  18298. +TEMPLATE_NAME=elf32
  18299. +EXTRA_EM_FILE=avr32elf
  18300. +OUTPUT_FORMAT="elf32-avr32"
  18301. +ARCH=avr32
  18302. +MAXPAGESIZE=4096
  18303. +ENTRY=_start
  18304. +EMBEDDED=yes
  18305. +NO_SMALL_DATA=yes
  18306. +NOP=0xd703d703
  18307. +
  18308. +DATA_SEGMENT_ALIGN=8
  18309. +BSS_ALIGNMENT=8
  18310. +
  18311. +RO_LMA_REGION="FLASH"
  18312. +RO_VMA_REGION="FLASH"
  18313. +RW_LMA_REGION="FLASH"
  18314. +RW_VMA_REGION="CPUSRAM"
  18315. +
  18316. +STACK_SIZE=_stack_size
  18317. +STACK_ADDR="ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - ${STACK_SIZE}"
  18318. +
  18319. +DATA_SEGMENT_END="
  18320. + __heap_start__ = ALIGN(8);
  18321. + . = ${STACK_ADDR};
  18322. + __heap_end__ = .;
  18323. +"
  18324. +
  18325. +case "$EMULATION" in
  18326. +avr32elf_ap*)
  18327. + MACHINE=ap
  18328. + INITIAL_READONLY_SECTIONS="
  18329. + .reset : { *(.reset) } >FLASH AT>FLASH
  18330. + . = . & 0x9fffffff;
  18331. +"
  18332. + TEXT_START_ADDR=0xa0000000
  18333. + case "$EMULATION" in
  18334. + avr32elf_ap700[0-2])
  18335. + MEMORY="
  18336. +MEMORY
  18337. +{
  18338. + FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
  18339. + CPUSRAM (rwxa) : ORIGIN = 0x24000000, LENGTH = 32K
  18340. +}
  18341. +"
  18342. + ;;
  18343. + avr32elf_ap7200)
  18344. + MEMORY="
  18345. +MEMORY
  18346. +{
  18347. + FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
  18348. + CPUSRAM (rwxa) : ORIGIN = 0x08000000, LENGTH = 64K
  18349. +}
  18350. +"
  18351. + ;;
  18352. + esac
  18353. + ;;
  18354. +
  18355. +avr32elf_mxt768e)
  18356. + MACHINE=uc
  18357. + INITIAL_READONLY_SECTIONS=".reset : { *(.reset) } >FLASH AT>FLASH"
  18358. + TEXT_START_ADDR=0x80000000
  18359. + OTHER_SECTIONS="
  18360. + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE
  18361. + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE
  18362. +"
  18363. + MEMORY="
  18364. +MEMORY
  18365. +{
  18366. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
  18367. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
  18368. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18369. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18370. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18371. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18372. +}
  18373. +"
  18374. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18375. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18376. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18377. +"
  18378. + ;;
  18379. +
  18380. +avr32elf_atuc3*)
  18381. + MACHINE=uc
  18382. + INITIAL_READONLY_SECTIONS=".reset : { *(.reset) } >FLASH AT>FLASH"
  18383. + TEXT_START_ADDR=0x80000000
  18384. + OTHER_SECTIONS="
  18385. + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE
  18386. + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE
  18387. +"
  18388. + case "$EMULATION" in
  18389. + avr32elf_atuc3l0256)
  18390. + MEMORY="
  18391. +MEMORY
  18392. +{
  18393. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
  18394. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
  18395. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18396. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18397. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18398. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18399. +}
  18400. +"
  18401. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18402. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18403. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18404. +"
  18405. + ;;
  18406. + esac
  18407. + ;;
  18408. +
  18409. +avr32elf_uc3*)
  18410. + MACHINE=uc
  18411. + INITIAL_READONLY_SECTIONS=".reset : { *(.reset) } >FLASH AT>FLASH"
  18412. + TEXT_START_ADDR=0x80000000
  18413. + OTHER_SECTIONS="
  18414. + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE
  18415. + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE
  18416. +"
  18417. +
  18418. + case "$EMULATION" in
  18419. + avr32elf_uc3c[012]512c)
  18420. + MEMORY="
  18421. +MEMORY
  18422. +{
  18423. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
  18424. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
  18425. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18426. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18427. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18428. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18429. +}
  18430. +"
  18431. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18432. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18433. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18434. +"
  18435. + ;;
  18436. +
  18437. + avr32elf_uc3c[012]256c)
  18438. + MEMORY="
  18439. +MEMORY
  18440. +{
  18441. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
  18442. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
  18443. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18444. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18445. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18446. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18447. +}
  18448. +"
  18449. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18450. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18451. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18452. +"
  18453. + ;;
  18454. +
  18455. + avr32elf_uc3c[012]128c)
  18456. + MEMORY="
  18457. +MEMORY
  18458. +{
  18459. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
  18460. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
  18461. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18462. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18463. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18464. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18465. +}
  18466. +"
  18467. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18468. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18469. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18470. +"
  18471. + ;;
  18472. +
  18473. + avr32elf_uc3c[012]64c)
  18474. + MEMORY="
  18475. +MEMORY
  18476. +{
  18477. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
  18478. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
  18479. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18480. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18481. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18482. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18483. +}
  18484. +"
  18485. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18486. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18487. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18488. +"
  18489. + ;;
  18490. +
  18491. + avr32elf_uc3[ac][012]512*)
  18492. + MEMORY="
  18493. +MEMORY
  18494. +{
  18495. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
  18496. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
  18497. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18498. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18499. +}
  18500. +"
  18501. + ;;
  18502. +
  18503. + avr32elf_uc3a[012]256*)
  18504. + MEMORY="
  18505. +MEMORY
  18506. +{
  18507. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
  18508. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
  18509. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18510. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18511. +}
  18512. +"
  18513. + ;;
  18514. +
  18515. + avr32elf_uc3b[01]512revc)
  18516. + MEMORY="
  18517. +MEMORY
  18518. +{
  18519. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
  18520. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
  18521. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18522. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18523. +}
  18524. +"
  18525. + PADDING="
  18526. + .padding : {
  18527. + QUAD(0)
  18528. + QUAD(0)
  18529. + QUAD(0)
  18530. + QUAD(0)
  18531. + } >FLASH AT>FLASH
  18532. +"
  18533. + ;;
  18534. +
  18535. + avr32elf_uc3b[01]512)
  18536. + MEMORY="
  18537. +MEMORY
  18538. +{
  18539. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
  18540. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
  18541. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18542. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18543. +}
  18544. +"
  18545. + ;;
  18546. +
  18547. + avr32elf_uc3b[01]256*)
  18548. + MEMORY="
  18549. +MEMORY
  18550. +{
  18551. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
  18552. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
  18553. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18554. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18555. +}
  18556. +"
  18557. + ;;
  18558. +
  18559. + avr32elf_uc3[ab][012]128*)
  18560. + MEMORY="
  18561. +MEMORY
  18562. +{
  18563. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
  18564. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
  18565. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18566. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18567. +}
  18568. +"
  18569. + ;;
  18570. +
  18571. + avr32elf_uc3b[0123]64*)
  18572. + MEMORY="
  18573. +MEMORY
  18574. +{
  18575. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
  18576. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
  18577. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18578. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18579. +}
  18580. +"
  18581. + ;;
  18582. +
  18583. + avr32elf_uc3a3256*)
  18584. + MEMORY="
  18585. +MEMORY
  18586. +{
  18587. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
  18588. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
  18589. + HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
  18590. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18591. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18592. +}
  18593. +"
  18594. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18595. + .hsbsram : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
  18596. +"
  18597. +
  18598. + ;;
  18599. +
  18600. + avr32elf_uc3a3128*)
  18601. + MEMORY="
  18602. +MEMORY
  18603. +{
  18604. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
  18605. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
  18606. + HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
  18607. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18608. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18609. +}
  18610. +"
  18611. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18612. + .hsbsram : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
  18613. +"
  18614. + ;;
  18615. +
  18616. + avr32elf_uc3a364*)
  18617. + MEMORY="
  18618. +MEMORY
  18619. +{
  18620. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
  18621. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
  18622. + HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
  18623. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18624. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18625. +}
  18626. +"
  18627. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18628. + .hsbsram : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
  18629. +"
  18630. + ;;
  18631. +
  18632. +
  18633. + avr32elf_uc3l[0123]64*)
  18634. + MEMORY="
  18635. +MEMORY
  18636. +{
  18637. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
  18638. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
  18639. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18640. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18641. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18642. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18643. +}
  18644. +"
  18645. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18646. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18647. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18648. +"
  18649. + ;;
  18650. +
  18651. + avr32elf_uc3l[0123]32*)
  18652. + MEMORY="
  18653. +MEMORY
  18654. +{
  18655. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 32K
  18656. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
  18657. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18658. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18659. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18660. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18661. +}
  18662. +"
  18663. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18664. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18665. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18666. +"
  18667. + ;;
  18668. +
  18669. + avr32elf_uc3l[0123]16*)
  18670. + MEMORY="
  18671. +MEMORY
  18672. +{
  18673. + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16K
  18674. + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x1FFC
  18675. + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
  18676. + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
  18677. + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
  18678. + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
  18679. +}
  18680. +"
  18681. + OTHER_SECTIONS="${OTHER_SECTIONS}
  18682. + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
  18683. + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
  18684. +"
  18685. + ;;
  18686. +
  18687. +
  18688. + esac
  18689. + ;;
  18690. +
  18691. +esac
  18692. --- /dev/null
  18693. +++ b/ld/emulparams/avr32linux.sh
  18694. @@ -0,0 +1,14 @@
  18695. +ARCH=avr32
  18696. +SCRIPT_NAME=elf
  18697. +TEMPLATE_NAME=elf32
  18698. +EXTRA_EM_FILE=avr32elf
  18699. +OUTPUT_FORMAT="elf32-avr32"
  18700. +GENERATE_SHLIB_SCRIPT=yes
  18701. +MAXPAGESIZE=0x1000
  18702. +TEXT_START_ADDR=0x00001000
  18703. +NOP=0xd703d703
  18704. +
  18705. +# This appears to place the GOT before the data section, which is
  18706. +# essential for uClinux. We don't use those .s* sections on AVR32
  18707. +# anyway, so it shouldn't hurt for regular Linux either...
  18708. +NO_SMALL_DATA=yes
  18709. --- /dev/null
  18710. +++ b/ld/emultempl/avr32elf.em
  18711. @@ -0,0 +1,162 @@
  18712. +# This shell script emits a C file. -*- C -*-
  18713. +# Copyright (C) 2007,2008,2009 Atmel Corporation
  18714. +#
  18715. +# This file is part of GLD, the Gnu Linker.
  18716. +#
  18717. +# This program is free software; you can redistribute it and/or modify
  18718. +# it under the terms of the GNU General Public License as published by
  18719. +# the Free Software Foundation; either version 2 of the License, or
  18720. +# (at your option) any later version.
  18721. +#
  18722. +# This program is distributed in the hope that it will be useful,
  18723. +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  18724. +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18725. +# GNU General Public License for more details.
  18726. +#
  18727. +# You should have received a copy of the GNU General Public License
  18728. +# along with this program; if not, write to the Free Software
  18729. +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  18730. +#
  18731. +
  18732. +# This file is sourced from elf32.em, and defines extra avr32-elf
  18733. +# specific routines.
  18734. +#
  18735. +
  18736. +# Generate linker script for writable rodata
  18737. +LD_FLAG=rodata-writable
  18738. +DATA_ALIGNMENT=${DATA_ALIGNMENT_}
  18739. +RELOCATING=" "
  18740. +WRITABLE_RODATA=" "
  18741. +( echo "/* Linker script for writable rodata */"
  18742. + . ${CUSTOMIZER_SCRIPT} ${EMULATION_NAME}
  18743. + . ${srcdir}/scripttempl/${SCRIPT_NAME}.sc
  18744. +) | sed -e '/^ *$/d;s/[ ]*$//' > ldscripts/${EMULATION_NAME}.xwr
  18745. +
  18746. +
  18747. +cat >> e${EMULATION_NAME}.c <<EOF
  18748. +
  18749. +#include "libbfd.h"
  18750. +#include "elf32-avr32.h"
  18751. +
  18752. +/* Whether to allow direct references (sub or mov) to SEC_DATA and
  18753. + !SEC_CONTENTS sections when optimizing. Not enabled by default
  18754. + since it might cause link errors. */
  18755. +static int direct_data_refs = 0;
  18756. +
  18757. +static void avr32_elf_after_open (void)
  18758. +{
  18759. + bfd_elf32_avr32_set_options (&link_info, direct_data_refs);
  18760. + gld${EMULATION_NAME}_after_open ();
  18761. +}
  18762. +
  18763. +static int rodata_writable = 0;
  18764. +
  18765. +static int stack_size = 0x1000;
  18766. +
  18767. +static void avr32_elf_set_symbols (void)
  18768. +{
  18769. + /* Glue the assignments into the abs section. */
  18770. + lang_statement_list_type *save = stat_ptr;
  18771. +
  18772. +
  18773. + stat_ptr = &(abs_output_section->children);
  18774. +
  18775. + lang_add_assignment (exp_assop ('=', "_stack_size",
  18776. + exp_intop (stack_size)));
  18777. +
  18778. + stat_ptr = save;
  18779. +}
  18780. +
  18781. +static char * gld${EMULATION_NAME}_get_script (int *isfile);
  18782. +
  18783. +static char * avr32_elf_get_script (int *isfile)
  18784. +{
  18785. + if ( rodata_writable )
  18786. + {
  18787. +EOF
  18788. +if test -n "$COMPILE_IN"
  18789. +then
  18790. +# Scripts compiled in.
  18791. +
  18792. +# sed commands to quote an ld script as a C string.
  18793. +sc="-f stringify.sed"
  18794. +
  18795. +cat >>e${EMULATION_NAME}.c <<EOF
  18796. + *isfile = 0;
  18797. + return
  18798. +EOF
  18799. +sed $sc ldscripts/${EMULATION_NAME}.xwr >> e${EMULATION_NAME}.c
  18800. +echo ';' >> e${EMULATION_NAME}.c
  18801. +else
  18802. +# Scripts read from the filesystem.
  18803. +
  18804. +cat >>e${EMULATION_NAME}.c <<EOF
  18805. + *isfile = 1;
  18806. + return "ldscripts/${EMULATION_NAME}.xwr";
  18807. +EOF
  18808. +fi
  18809. +
  18810. +cat >>e${EMULATION_NAME}.c <<EOF
  18811. + }
  18812. + return gld${EMULATION_NAME}_get_script (isfile);
  18813. +}
  18814. +
  18815. +
  18816. +EOF
  18817. +
  18818. +# Define some shell vars to insert bits of code into the standard elf
  18819. +# parse_args and list_options functions.
  18820. +#
  18821. +PARSE_AND_LIST_PROLOGUE='
  18822. +#define OPTION_DIRECT_DATA 300
  18823. +#define OPTION_NO_DIRECT_DATA 301
  18824. +#define OPTION_RODATA_WRITABLE 302
  18825. +#define OPTION_NO_RODATA_WRITABLE 303
  18826. +#define OPTION_STACK 304
  18827. +'
  18828. +
  18829. +PARSE_AND_LIST_LONGOPTS='
  18830. + { "direct-data", no_argument, NULL, OPTION_DIRECT_DATA },
  18831. + { "no-direct-data", no_argument, NULL, OPTION_NO_DIRECT_DATA },
  18832. + { "rodata-writable", no_argument, NULL, OPTION_RODATA_WRITABLE },
  18833. + { "no-rodata-writable", no_argument, NULL, OPTION_NO_RODATA_WRITABLE },
  18834. + { "stack", required_argument, NULL, OPTION_STACK },
  18835. +'
  18836. +
  18837. +PARSE_AND_LIST_OPTIONS='
  18838. + fprintf (file, _(" --direct-data\t\tAllow direct data references when optimizing\n"));
  18839. + fprintf (file, _(" --no-direct-data\tDo not allow direct data references when optimizing\n"));
  18840. + fprintf (file, _(" --rodata-writable\tPut read-only data in writable data section\n"));
  18841. + fprintf (file, _(" --no-rodata-writable\tDo not put read-only data in writable data section\n"));
  18842. + fprintf (file, _(" --stack <size>\tSet the initial size of the stack\n"));
  18843. +'
  18844. +
  18845. +PARSE_AND_LIST_ARGS_CASES='
  18846. + case OPTION_DIRECT_DATA:
  18847. + direct_data_refs = 1;
  18848. + break;
  18849. + case OPTION_NO_DIRECT_DATA:
  18850. + direct_data_refs = 0;
  18851. + break;
  18852. + case OPTION_RODATA_WRITABLE:
  18853. + rodata_writable = 1;
  18854. + break;
  18855. + case OPTION_NO_RODATA_WRITABLE:
  18856. + rodata_writable = 0;
  18857. + break;
  18858. + case OPTION_STACK:
  18859. + {
  18860. + char *end;
  18861. + stack_size = strtoul (optarg, &end, 0);
  18862. + if (end == optarg)
  18863. + einfo (_("%P%F: invalid hex number for parameter '%s'\n"), optarg);
  18864. + optarg = end;
  18865. + break;
  18866. + }
  18867. +'
  18868. +
  18869. +# Replace some of the standard ELF functions with our own versions.
  18870. +#
  18871. +LDEMUL_AFTER_OPEN=avr32_elf_after_open
  18872. +LDEMUL_GET_SCRIPT=avr32_elf_get_script
  18873. +LDEMUL_SET_SYMBOLS=avr32_elf_set_symbols
  18874. --- a/ld/Makefile.am
  18875. +++ b/ld/Makefile.am
  18876. @@ -148,6 +148,58 @@ ALL_EMULATIONS = \
  18877. eavr5.o \
  18878. eavr51.o \
  18879. eavr6.o \
  18880. + eavr32elf_ap7000.o \
  18881. + eavr32elf_ap7001.o \
  18882. + eavr32elf_ap7002.o \
  18883. + eavr32elf_ap7200.o \
  18884. + eavr32elf_uc3a0128.o \
  18885. + eavr32elf_uc3a0256.o \
  18886. + eavr32elf_uc3a0512.o \
  18887. + eavr32elf_uc3a0512es.o \
  18888. + eavr32elf_uc3a1128.o \
  18889. + eavr32elf_uc3a1256.o \
  18890. + eavr32elf_uc3a1512es.o \
  18891. + eavr32elf_uc3a1512.o \
  18892. + eavr32elf_uc3a364.o \
  18893. + eavr32elf_uc3a364s.o \
  18894. + eavr32elf_uc3a3128.o \
  18895. + eavr32elf_uc3a3128s.o \
  18896. + eavr32elf_uc3a3256.o \
  18897. + eavr32elf_uc3a3256s.o \
  18898. + eavr32elf_uc3b064.o \
  18899. + eavr32elf_uc3b0128.o \
  18900. + eavr32elf_uc3b0256es.o \
  18901. + eavr32elf_uc3b0256.o \
  18902. + eavr32elf_uc3b0512.o \
  18903. + eavr32elf_uc3b0512revc.o \
  18904. + eavr32elf_uc3b164.o \
  18905. + eavr32elf_uc3b1128.o \
  18906. + eavr32elf_uc3b1256es.o \
  18907. + eavr32elf_uc3b1256.o \
  18908. + eavr32elf_uc3b1512.o \
  18909. + eavr32elf_uc3b1512revc.o \
  18910. + eavr32elf_uc3c0512crevc.o \
  18911. + eavr32elf_uc3c1512crevc.o \
  18912. + eavr32elf_uc3c2512crevc.o \
  18913. + eavr32elf_atuc3l0256.o \
  18914. + eavr32elf_mxt768e.o \
  18915. + eavr32elf_uc3l064.o \
  18916. + eavr32elf_uc3l032.o \
  18917. + eavr32elf_uc3l016.o \
  18918. + eavr32elf_uc3l064revb.o \
  18919. + eavr32elf_uc3c064c.o \
  18920. + eavr32elf_uc3c0128c.o \
  18921. + eavr32elf_uc3c0256c.o \
  18922. + eavr32elf_uc3c0512c.o \
  18923. + eavr32elf_uc3c164c.o \
  18924. + eavr32elf_uc3c1128c.o \
  18925. + eavr32elf_uc3c1256c.o \
  18926. + eavr32elf_uc3c1512c.o \
  18927. + eavr32elf_uc3c264c.o \
  18928. + eavr32elf_uc3c2128c.o \
  18929. + eavr32elf_uc3c2256c.o \
  18930. + eavr32elf_uc3c2512c.o \
  18931. + eavr32linux.o \
  18932. ecoff_i860.o \
  18933. ecoff_sparc.o \
  18934. eelf32_spu.o \
  18935. @@ -727,6 +779,214 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
  18936. $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
  18937. ${GEN_DEPENDS}
  18938. ${GENSCRIPTS} avr6 "$(tdir_avr2)"
  18939. +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
  18940. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18941. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18942. + ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
  18943. +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
  18944. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18945. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18946. + ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
  18947. +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
  18948. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18949. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18950. + ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
  18951. +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
  18952. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18953. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18954. + ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
  18955. +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
  18956. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18957. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18958. + ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
  18959. +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
  18960. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18961. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18962. + ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
  18963. +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
  18964. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18965. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18966. + ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
  18967. +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
  18968. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18969. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18970. + ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
  18971. +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
  18972. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18973. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18974. + ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
  18975. +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
  18976. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18977. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18978. + ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
  18979. +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
  18980. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18981. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18982. + ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
  18983. +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
  18984. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18985. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18986. + ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
  18987. +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
  18988. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18989. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18990. + ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
  18991. +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
  18992. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18993. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18994. + ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
  18995. +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
  18996. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  18997. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  18998. + ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
  18999. +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
  19000. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19001. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19002. + ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
  19003. +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
  19004. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19005. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19006. + ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
  19007. +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
  19008. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19009. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19010. + ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
  19011. +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
  19012. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19013. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19014. + ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
  19015. +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
  19016. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19017. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19018. + ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
  19019. +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
  19020. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19021. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19022. + ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
  19023. +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
  19024. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19025. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19026. + ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
  19027. +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
  19028. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19029. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19030. + ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
  19031. +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
  19032. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19033. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19034. + ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
  19035. +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
  19036. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19037. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19038. + ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
  19039. +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
  19040. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19041. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19042. + ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
  19043. +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
  19044. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19045. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19046. + ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
  19047. +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
  19048. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19049. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19050. + ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
  19051. +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
  19052. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19053. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19054. + ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
  19055. +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
  19056. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19057. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19058. + ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
  19059. +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
  19060. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19061. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19062. + ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
  19063. +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
  19064. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19065. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19066. + ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
  19067. +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
  19068. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19069. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19070. + ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
  19071. +eavr32elf_atuc3l0256.c: $(srcdir)/emulparams/avr32elf.sh \
  19072. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19073. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19074. + ${GENSCRIPTS} avr32elf_atuc3l0256 "$(tdir_avr32)" avr32elf
  19075. +eavr32elf_mxt768e.c: $(srcdir)/emulparams/avr32elf.sh \
  19076. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19077. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19078. + ${GENSCRIPTS} avr32elf_mxt768e "$(tdir_avr32)" avr32elf
  19079. +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
  19080. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19081. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19082. + ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
  19083. +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
  19084. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19085. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19086. + ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
  19087. +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
  19088. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19089. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19090. + ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
  19091. +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
  19092. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19093. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19094. + ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
  19095. +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
  19096. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19097. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19098. + ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
  19099. +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
  19100. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19101. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19102. + ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
  19103. +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
  19104. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19105. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19106. + ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
  19107. +eavr32elf_uc3c0512c.c: $(srcdir)/emulparams/avr32elf.sh \
  19108. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19109. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19110. + ${GENSCRIPTS} avr32elf_uc3c0512c "$(tdir_avr32)" avr32elf
  19111. +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
  19112. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19113. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19114. + ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
  19115. +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
  19116. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19117. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19118. + ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
  19119. +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
  19120. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19121. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19122. + ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
  19123. +eavr32elf_uc3c1512c.c: $(srcdir)/emulparams/avr32elf.sh \
  19124. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19125. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19126. + ${GENSCRIPTS} avr32elf_uc3c1512c "$(tdir_avr32)" avr32elf
  19127. +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
  19128. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19129. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19130. + ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
  19131. +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
  19132. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19133. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19134. + ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
  19135. +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
  19136. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19137. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19138. + ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
  19139. +eavr32elf_uc3c2512c.c: $(srcdir)/emulparams/avr32elf.sh \
  19140. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19141. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  19142. + ${GENSCRIPTS} avr32elf_uc3c2512c "$(tdir_avr32)" avr32elf
  19143. +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
  19144. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  19145. + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
  19146. + ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
  19147. ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
  19148. $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
  19149. ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
  19150. @@ -1964,7 +2224,9 @@ install-exec-local: ld-new$(EXEEXT)
  19151. || $(LIBTOOL) --mode=install $(INSTALL_PROGRAM) ld-new$(EXEEXT) $(DESTDIR)$(tooldir)/bin/ld$(EXEEXT); \
  19152. fi
  19153. -install-data-local:
  19154. +# We want install to imply install-info as per GNU standards, despite the
  19155. +# cygnus option.
  19156. +install-data-local: install-info
  19157. $(mkinstalldirs) $(DESTDIR)$(scriptdir)/ldscripts
  19158. for f in ldscripts/*; do \
  19159. $(INSTALL_DATA) $$f $(DESTDIR)$(scriptdir)/$$f ; \
  19160. --- /dev/null
  19161. +++ b/ld/scripttempl/avr32.sc
  19162. @@ -0,0 +1,459 @@
  19163. +#
  19164. +# Unusual variables checked by this code:
  19165. +# NOP - four byte opcode for no-op (defaults to 0)
  19166. +# NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
  19167. +# empty.
  19168. +# SMALL_DATA_CTOR - .ctors contains small data.
  19169. +# SMALL_DATA_DTOR - .dtors contains small data.
  19170. +# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
  19171. +# INITIAL_READONLY_SECTIONS - at start of text segment
  19172. +# OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
  19173. +# (e.g., .PARISC.milli)
  19174. +# OTHER_TEXT_SECTIONS - these get put in .text when relocating
  19175. +# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
  19176. +# (e.g., .PARISC.global)
  19177. +# OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
  19178. +# (e.g. PPC32 .fixup, .got[12])
  19179. +# OTHER_BSS_SECTIONS - other than .bss .sbss ...
  19180. +# OTHER_SECTIONS - at the end
  19181. +# EXECUTABLE_SYMBOLS - symbols that must be defined for an
  19182. +# executable (e.g., _DYNAMIC_LINK)
  19183. +# TEXT_START_ADDR - the first byte of the text segment, after any
  19184. +# headers.
  19185. +# TEXT_BASE_ADDRESS - the first byte of the text segment.
  19186. +# TEXT_START_SYMBOLS - symbols that appear at the start of the
  19187. +# .text section.
  19188. +# DATA_START_SYMBOLS - symbols that appear at the start of the
  19189. +# .data section.
  19190. +# OTHER_GOT_SYMBOLS - symbols defined just before .got.
  19191. +# OTHER_GOT_SECTIONS - sections just after .got.
  19192. +# OTHER_SDATA_SECTIONS - sections just after .sdata.
  19193. +# OTHER_BSS_SYMBOLS - symbols that appear at the start of the
  19194. +# .bss section besides __bss_start.
  19195. +# DATA_PLT - .plt should be in data segment, not text segment.
  19196. +# PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement.
  19197. +# BSS_PLT - .plt should be in bss segment
  19198. +# TEXT_DYNAMIC - .dynamic in text segment, not data segment.
  19199. +# EMBEDDED - whether this is for an embedded system.
  19200. +# SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
  19201. +# start address of shared library.
  19202. +# INPUT_FILES - INPUT command of files to always include
  19203. +# WRITABLE_RODATA - if set, the .rodata section should be writable
  19204. +# INIT_START, INIT_END - statements just before and just after
  19205. +# combination of .init sections.
  19206. +# FINI_START, FINI_END - statements just before and just after
  19207. +# combination of .fini sections.
  19208. +# STACK_ADDR - start of a .stack section.
  19209. +# OTHER_END_SYMBOLS - symbols to place right at the end of the script.
  19210. +# SEPARATE_GOTPLT - if set, .got.plt should be separate output section,
  19211. +# so that .got can be in the RELRO area. It should be set to
  19212. +# the number of bytes in the beginning of .got.plt which can be
  19213. +# in the RELRO area as well.
  19214. +#
  19215. +# When adding sections, do note that the names of some sections are used
  19216. +# when specifying the start address of the next.
  19217. +#
  19218. +
  19219. +# Many sections come in three flavours. There is the 'real' section,
  19220. +# like ".data". Then there are the per-procedure or per-variable
  19221. +# sections, generated by -ffunction-sections and -fdata-sections in GCC,
  19222. +# and useful for --gc-sections, which for a variable "foo" might be
  19223. +# ".data.foo". Then there are the linkonce sections, for which the linker
  19224. +# eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
  19225. +# The exact correspondences are:
  19226. +#
  19227. +# Section Linkonce section
  19228. +# .text .gnu.linkonce.t.foo
  19229. +# .rodata .gnu.linkonce.r.foo
  19230. +# .data .gnu.linkonce.d.foo
  19231. +# .bss .gnu.linkonce.b.foo
  19232. +# .sdata .gnu.linkonce.s.foo
  19233. +# .sbss .gnu.linkonce.sb.foo
  19234. +# .sdata2 .gnu.linkonce.s2.foo
  19235. +# .sbss2 .gnu.linkonce.sb2.foo
  19236. +# .debug_info .gnu.linkonce.wi.foo
  19237. +# .tdata .gnu.linkonce.td.foo
  19238. +# .tbss .gnu.linkonce.tb.foo
  19239. +#
  19240. +# Each of these can also have corresponding .rel.* and .rela.* sections.
  19241. +
  19242. +test -z "$ENTRY" && ENTRY=_start
  19243. +test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
  19244. +test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
  19245. +if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
  19246. +test -z "${ELFSIZE}" && ELFSIZE=32
  19247. +test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
  19248. +test "$LD_FLAG" = "N" && DATA_ADDR=.
  19249. +test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
  19250. +test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
  19251. +test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT
  19252. +if test -n "$RELOCATING"; then
  19253. + RO_REGION="${RO_VMA_REGION+ >}${RO_VMA_REGION}${RO_LMA_REGION+ AT>}${RO_LMA_REGION}"
  19254. + RW_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}${RW_LMA_REGION+ AT>}${RW_LMA_REGION}"
  19255. + RW_BSS_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}"
  19256. +else
  19257. + RO_REGION=""
  19258. + RW_REGION=""
  19259. + RW_BSS_REGION=""
  19260. +fi
  19261. +INTERP=".interp ${RELOCATING-0} : { *(.interp) }${RO_REGION}"
  19262. +PLT=".plt ${RELOCATING-0} : { *(.plt) }"
  19263. +if test -z "$GOT"; then
  19264. + if test -z "$SEPARATE_GOTPLT"; then
  19265. + GOT=".got ${RELOCATING-0} : { *(.got.plt) *(.got) }"
  19266. + else
  19267. + GOT=".got ${RELOCATING-0} : { *(.got) }"
  19268. + GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}}
  19269. + .got.plt ${RELOCATING-0} : { *(.got.plt) }"
  19270. + fi
  19271. +fi
  19272. +DALIGN=".dalign : { . = ALIGN(${DATA_SEGMENT_ALIGN}); PROVIDE(_data_lma = .); }${RO_REGION}"
  19273. +BALIGN=".balign : { . = ALIGN(${BSS_ALIGNMENT}); _edata = .; }${RW_REGION}"
  19274. +DYNAMIC=".dynamic ${RELOCATING-0} : { *(.dynamic) }"
  19275. +RODATA=".rodata ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
  19276. +DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }${RW_REGION}"
  19277. +STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
  19278. +if test -z "${NO_SMALL_DATA}"; then
  19279. + SBSS=".sbss ${RELOCATING-0} :
  19280. + {
  19281. + ${RELOCATING+PROVIDE (__sbss_start = .);}
  19282. + ${RELOCATING+PROVIDE (___sbss_start = .);}
  19283. + ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)}
  19284. + *(.dynsbss)
  19285. + *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
  19286. + *(.scommon)
  19287. + ${RELOCATING+PROVIDE (__sbss_end = .);}
  19288. + ${RELOCATING+PROVIDE (___sbss_end = .);}
  19289. + }${RW_BSS_REGION}"
  19290. + SBSS2=".sbss2 ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }${RW_REGION}"
  19291. + SDATA="/* We want the small data sections together, so single-instruction offsets
  19292. + can access them all, and initialized data all before uninitialized, so
  19293. + we can shorten the on-disk segment size. */
  19294. + .sdata ${RELOCATING-0} :
  19295. + {
  19296. + ${RELOCATING+${SDATA_START_SYMBOLS}}
  19297. + ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)}
  19298. + *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
  19299. + }${RW_REGION}"
  19300. + SDATA2=".sdata2 ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }${RW_REGION}"
  19301. + REL_SDATA=".rel.sdata ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }${RO_REGION}
  19302. + .rela.sdata ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
  19303. + REL_SBSS=".rel.sbss ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }${RO_REGION}
  19304. + .rela.sbss ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }${RO_REGION}"
  19305. + REL_SDATA2=".rel.sdata2 ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }${RO_REGION}
  19306. + .rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }${RO_REGION}"
  19307. + REL_SBSS2=".rel.sbss2 ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }${RO_REGION}
  19308. + .rela.sbss2 ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }${RO_REGION}"
  19309. +else
  19310. + NO_SMALL_DATA=" "
  19311. +fi
  19312. +test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" "
  19313. +CTOR=".ctors ${CONSTRUCTING-0} :
  19314. + {
  19315. + ${CONSTRUCTING+${CTOR_START}}
  19316. + /* gcc uses crtbegin.o to find the start of
  19317. + the constructors, so we make sure it is
  19318. + first. Because this is a wildcard, it
  19319. + doesn't matter if the user does not
  19320. + actually link against crtbegin.o; the
  19321. + linker won't look for a file to match a
  19322. + wildcard. The wildcard also means that it
  19323. + doesn't matter which directory crtbegin.o
  19324. + is in. */
  19325. +
  19326. + KEEP (*crtbegin*.o(.ctors))
  19327. +
  19328. + /* We don't want to include the .ctor section from
  19329. + from the crtend.o file until after the sorted ctors.
  19330. + The .ctor section from the crtend file contains the
  19331. + end of ctors marker and it must be last */
  19332. +
  19333. + KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
  19334. + KEEP (*(SORT(.ctors.*)))
  19335. + KEEP (*(.ctors))
  19336. + ${CONSTRUCTING+${CTOR_END}}
  19337. + }"
  19338. +DTOR=".dtors ${CONSTRUCTING-0} :
  19339. + {
  19340. + ${CONSTRUCTING+${DTOR_START}}
  19341. + KEEP (*crtbegin*.o(.dtors))
  19342. + KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
  19343. + KEEP (*(SORT(.dtors.*)))
  19344. + KEEP (*(.dtors))
  19345. + ${CONSTRUCTING+${DTOR_END}}
  19346. + }"
  19347. +STACK=".stack ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
  19348. + {
  19349. + ${RELOCATING+_stack = .;}
  19350. + *(.stack)
  19351. + ${RELOCATING+${STACK_SIZE+. = ${STACK_SIZE};}}
  19352. + ${RELOCATING+_estack = .;}
  19353. + }${RW_BSS_REGION}"
  19354. +
  19355. +# if this is for an embedded system, don't add SIZEOF_HEADERS.
  19356. +if [ -z "$EMBEDDED" ]; then
  19357. + test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
  19358. +else
  19359. + test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
  19360. +fi
  19361. +
  19362. +cat <<EOF
  19363. +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
  19364. + "${LITTLE_OUTPUT_FORMAT}")
  19365. +OUTPUT_ARCH(${OUTPUT_ARCH})
  19366. +ENTRY(${ENTRY})
  19367. +
  19368. +${RELOCATING+${LIB_SEARCH_DIRS}}
  19369. +${RELOCATING+/* Do we need any of these for elf?
  19370. + __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}} */}
  19371. +${RELOCATING+${EXECUTABLE_SYMBOLS}}
  19372. +${RELOCATING+${INPUT_FILES}}
  19373. +${RELOCATING- /* For some reason, the Solaris linker makes bad executables
  19374. + if gld -r is used and the intermediate file has sections starting
  19375. + at non-zero addresses. Could be a Solaris ld bug, could be a GNU ld
  19376. + bug. But for now assigning the zero vmas works. */}
  19377. +
  19378. +${RELOCATING+${MEMORY}}
  19379. +
  19380. +SECTIONS
  19381. +{
  19382. + /* Read-only sections, merged into text segment: */
  19383. + ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
  19384. + ${PADDING}
  19385. + ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
  19386. + ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
  19387. + ${CREATE_SHLIB-${INTERP}}
  19388. + ${INITIAL_READONLY_SECTIONS}
  19389. + ${TEXT_DYNAMIC+${DYNAMIC}${RO_REGION}}
  19390. + .hash ${RELOCATING-0} : { *(.hash) }${RO_REGION}
  19391. + .dynsym ${RELOCATING-0} : { *(.dynsym) }${RO_REGION}
  19392. + .dynstr ${RELOCATING-0} : { *(.dynstr) }${RO_REGION}
  19393. + .gnu.version ${RELOCATING-0} : { *(.gnu.version) }${RO_REGION}
  19394. + .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }${RO_REGION}
  19395. + .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }${RO_REGION}
  19396. +
  19397. +EOF
  19398. +if [ "x$COMBRELOC" = x ]; then
  19399. + COMBRELOCCAT=cat
  19400. +else
  19401. + COMBRELOCCAT="cat > $COMBRELOC"
  19402. +fi
  19403. +eval $COMBRELOCCAT <<EOF
  19404. + .rel.init ${RELOCATING-0} : { *(.rel.init) }${RO_REGION}
  19405. + .rela.init ${RELOCATING-0} : { *(.rela.init) }${RO_REGION}
  19406. + .rel.text ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }${RO_REGION}
  19407. + .rela.text ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }${RO_REGION}
  19408. + .rel.fini ${RELOCATING-0} : { *(.rel.fini) }${RO_REGION}
  19409. + .rela.fini ${RELOCATING-0} : { *(.rela.fini) }${RO_REGION}
  19410. + .rel.rodata ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }${RO_REGION}
  19411. + .rela.rodata ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }${RO_REGION}
  19412. + ${OTHER_READONLY_RELOC_SECTIONS}
  19413. + .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
  19414. + .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
  19415. + .rel.data ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }${RO_REGION}
  19416. + .rela.data ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }${RO_REGION}
  19417. + .rel.tdata ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }${RO_REGION}
  19418. + .rela.tdata ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }${RO_REGION}
  19419. + .rel.tbss ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }${RO_REGION}
  19420. + .rela.tbss ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }${RO_REGION}
  19421. + .rel.ctors ${RELOCATING-0} : { *(.rel.ctors) }${RO_REGION}
  19422. + .rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }${RO_REGION}
  19423. + .rel.dtors ${RELOCATING-0} : { *(.rel.dtors) }${RO_REGION}
  19424. + .rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }${RO_REGION}
  19425. + .rel.got ${RELOCATING-0} : { *(.rel.got) }${RO_REGION}
  19426. + .rela.got ${RELOCATING-0} : { *(.rela.got) }${RO_REGION}
  19427. + ${OTHER_GOT_RELOC_SECTIONS}
  19428. + ${REL_SDATA}
  19429. + ${REL_SBSS}
  19430. + ${REL_SDATA2}
  19431. + ${REL_SBSS2}
  19432. + .rel.bss ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }${RO_REGION}
  19433. + .rela.bss ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }${RO_REGION}
  19434. +EOF
  19435. +if [ -n "$COMBRELOC" ]; then
  19436. +cat <<EOF
  19437. + .rel.dyn ${RELOCATING-0} :
  19438. + {
  19439. +EOF
  19440. +sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/ \1/' $COMBRELOC
  19441. +cat <<EOF
  19442. + }${RO_REGION}
  19443. + .rela.dyn ${RELOCATING-0} :
  19444. + {
  19445. +EOF
  19446. +sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/ \1/' $COMBRELOC
  19447. +cat <<EOF
  19448. + }${RO_REGION}
  19449. +EOF
  19450. +fi
  19451. +cat <<EOF
  19452. + .rel.plt ${RELOCATING-0} : { *(.rel.plt) }${RO_REGION}
  19453. + .rela.plt ${RELOCATING-0} : { *(.rela.plt) }${RO_REGION}
  19454. + ${OTHER_PLT_RELOC_SECTIONS}
  19455. +
  19456. + .init ${RELOCATING-0} :
  19457. + {
  19458. + ${RELOCATING+${INIT_START}}
  19459. + KEEP (*(.init))
  19460. + ${RELOCATING+${INIT_END}}
  19461. + }${RO_REGION} =${NOP-0}
  19462. +
  19463. + ${DATA_PLT-${BSS_PLT-${PLT}${RO_REGION}}}
  19464. + .text ${RELOCATING-0} :
  19465. + {
  19466. + ${RELOCATING+${TEXT_START_SYMBOLS}}
  19467. + *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
  19468. + KEEP (*(.text.*personality*))
  19469. + /* .gnu.warning sections are handled specially by elf32.em. */
  19470. + *(.gnu.warning)
  19471. + ${RELOCATING+${OTHER_TEXT_SECTIONS}}
  19472. + }${RO_REGION} =${NOP-0}
  19473. + .fini ${RELOCATING-0} :
  19474. + {
  19475. + ${RELOCATING+${FINI_START}}
  19476. + KEEP (*(.fini))
  19477. + ${RELOCATING+${FINI_END}}
  19478. + }${RO_REGION} =${NOP-0}
  19479. + ${RELOCATING+PROVIDE (__etext = .);}
  19480. + ${RELOCATING+PROVIDE (_etext = .);}
  19481. + ${RELOCATING+PROVIDE (etext = .);}
  19482. + ${WRITABLE_RODATA-${RODATA}${RO_REGION}}
  19483. + .rodata1 ${RELOCATING-0} : { *(.rodata1) }${RO_REGION}
  19484. + ${CREATE_SHLIB-${SDATA2}}
  19485. + ${CREATE_SHLIB-${SBSS2}}
  19486. + ${OTHER_READONLY_SECTIONS}
  19487. + .eh_frame_hdr : { *(.eh_frame_hdr) }${RO_REGION}
  19488. + .eh_frame ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }${RO_REGION}
  19489. + .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RO_REGION}
  19490. +
  19491. + ${RELOCATING+${DALIGN}}
  19492. + ${RELOCATING+PROVIDE (_data = ORIGIN(${RW_VMA_REGION}));}
  19493. + . = ORIGIN(${RW_VMA_REGION});
  19494. + /* Exception handling */
  19495. + .eh_frame ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }${RW_REGION}
  19496. + .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RW_REGION}
  19497. +
  19498. + /* Thread Local Storage sections */
  19499. + .tdata ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }${RW_REGION}
  19500. + .tbss ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }${RW_BSS_REGION}
  19501. +
  19502. + /* Ensure the __preinit_array_start label is properly aligned. We
  19503. + could instead move the label definition inside the section, but
  19504. + the linker would then create the section even if it turns out to
  19505. + be empty, which isn't pretty. */
  19506. + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = ALIGN(${ALIGNMENT}));}}
  19507. + .preinit_array ${RELOCATING-0} : { KEEP (*(.preinit_array)) }${RW_REGION}
  19508. + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
  19509. +
  19510. + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
  19511. + .init_array ${RELOCATING-0} : { KEEP (*(.init_array)) }${RW_REGION}
  19512. + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
  19513. +
  19514. + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
  19515. + .fini_array ${RELOCATING-0} : { KEEP (*(.fini_array)) }${RW_REGION}
  19516. + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
  19517. +
  19518. + ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}${RW_REGION}}}
  19519. + ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}${RW_REGION}}}
  19520. + .jcr ${RELOCATING-0} : { KEEP (*(.jcr)) }${RW_REGION}
  19521. +
  19522. + ${RELOCATING+${DATARELRO}}
  19523. + ${OTHER_RELRO_SECTIONS}
  19524. + ${TEXT_DYNAMIC-${DYNAMIC}${RW_REGION}}
  19525. + ${NO_SMALL_DATA+${RELRO_NOW+${GOT}${RW_REGION}}}
  19526. + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}${RW_REGION}}}}
  19527. + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}${RW_REGION}}}}
  19528. + ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
  19529. + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}${RW_REGION}}}}
  19530. +
  19531. + ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}${RW_REGION}}}
  19532. +
  19533. + .data ${RELOCATING-0} :
  19534. + {
  19535. + ${RELOCATING+${DATA_START_SYMBOLS}}
  19536. + *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
  19537. + KEEP (*(.gnu.linkonce.d.*personality*))
  19538. + ${CONSTRUCTING+SORT(CONSTRUCTORS)}
  19539. + }${RW_REGION}
  19540. + .data1 ${RELOCATING-0} : { *(.data1) }${RW_REGION}
  19541. + ${WRITABLE_RODATA+${RODATA}${RW_REGION}}
  19542. + ${OTHER_READWRITE_SECTIONS}
  19543. + ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}${RW_REGION}}}
  19544. + ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}${RW_REGION}}}
  19545. + ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}${RW_REGION}}}
  19546. + ${RELOCATING+${OTHER_GOT_SYMBOLS}}
  19547. + ${NO_SMALL_DATA-${GOT}${RW_REGION}}
  19548. + ${OTHER_GOT_SECTIONS}
  19549. + ${SDATA}
  19550. + ${OTHER_SDATA_SECTIONS}
  19551. + ${RELOCATING+${BALIGN}}
  19552. + ${RELOCATING+_edata = .;}
  19553. + ${RELOCATING+PROVIDE (edata = .);}
  19554. + ${RELOCATING+__bss_start = .;}
  19555. + ${RELOCATING+${OTHER_BSS_SYMBOLS}}
  19556. + ${SBSS}
  19557. + ${BSS_PLT+${PLT}${RW_REGION}}
  19558. + .bss ${RELOCATING-0} :
  19559. + {
  19560. + *(.dynbss)
  19561. + *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
  19562. + *(COMMON)
  19563. + /* Align here to ensure that the .bss section occupies space up to
  19564. + _end. Align after .bss to ensure correct alignment even if the
  19565. + .bss section disappears because there are no input sections. */
  19566. + ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
  19567. + }${RW_BSS_REGION}
  19568. + ${OTHER_BSS_SECTIONS}
  19569. + ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
  19570. + ${RELOCATING+_end = .;}
  19571. + ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
  19572. + ${RELOCATING+PROVIDE (end = .);}
  19573. + ${RELOCATING+${DATA_SEGMENT_END}}
  19574. +
  19575. + /* Stabs debugging sections. */
  19576. + .stab 0 : { *(.stab) }
  19577. + .stabstr 0 : { *(.stabstr) }
  19578. + .stab.excl 0 : { *(.stab.excl) }
  19579. + .stab.exclstr 0 : { *(.stab.exclstr) }
  19580. + .stab.index 0 : { *(.stab.index) }
  19581. + .stab.indexstr 0 : { *(.stab.indexstr) }
  19582. +
  19583. + .comment 0 : { *(.comment) }
  19584. +
  19585. + /* DWARF debug sections.
  19586. + Symbols in the DWARF debugging sections are relative to the beginning
  19587. + of the section so we begin them at 0. */
  19588. +
  19589. + /* DWARF 1 */
  19590. + .debug 0 : { *(.debug) }
  19591. + .line 0 : { *(.line) }
  19592. +
  19593. + /* GNU DWARF 1 extensions */
  19594. + .debug_srcinfo 0 : { *(.debug_srcinfo) }
  19595. + .debug_sfnames 0 : { *(.debug_sfnames) }
  19596. +
  19597. + /* DWARF 1.1 and DWARF 2 */
  19598. + .debug_aranges 0 : { *(.debug_aranges) }
  19599. + .debug_pubnames 0 : { *(.debug_pubnames) }
  19600. +
  19601. + /* DWARF 2 */
  19602. + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
  19603. + .debug_abbrev 0 : { *(.debug_abbrev) }
  19604. + .debug_line 0 : { *(.debug_line) }
  19605. + .debug_frame 0 : { *(.debug_frame) }
  19606. + .debug_str 0 : { *(.debug_str) }
  19607. + .debug_loc 0 : { *(.debug_loc) }
  19608. + .debug_macinfo 0 : { *(.debug_macinfo) }
  19609. +
  19610. + /* SGI/MIPS DWARF 2 extensions */
  19611. + .debug_weaknames 0 : { *(.debug_weaknames) }
  19612. + .debug_funcnames 0 : { *(.debug_funcnames) }
  19613. + .debug_typenames 0 : { *(.debug_typenames) }
  19614. + .debug_varnames 0 : { *(.debug_varnames) }
  19615. +
  19616. + ${STACK_ADDR+${STACK}}
  19617. + ${OTHER_SECTIONS}
  19618. + ${RELOCATING+${OTHER_END_SYMBOLS}}
  19619. + ${RELOCATING+${STACKNOTE}}
  19620. +}
  19621. +EOF
  19622. --- /dev/null
  19623. +++ b/ld/testsuite/ld-avr32/avr32.exp
  19624. @@ -0,0 +1,25 @@
  19625. +# Expect script for AVR32 ELF linker tests.
  19626. +# Copyright 2004-2006 Atmel Corporation.
  19627. +#
  19628. +# This file is free software; you can redistribute it and/or modify
  19629. +# it under the terms of the GNU General Public License as published by
  19630. +# the Free Software Foundation; either version 2 of the License, or
  19631. +# (at your option) any later version.
  19632. +#
  19633. +# This program is distributed in the hope that it will be useful,
  19634. +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  19635. +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19636. +# GNU General Public License for more details.
  19637. +#
  19638. +# You should have received a copy of the GNU General Public License
  19639. +# along with this program; if not, write to the Free Software
  19640. +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19641. +#
  19642. +# Written by Haavard Skinnemoen (hskinnemoen@atmel.com)
  19643. +#
  19644. +
  19645. +if ![istarget avr32-*-*] {
  19646. + return
  19647. +}
  19648. +
  19649. +run_dump_test "pcrel"
  19650. --- /dev/null
  19651. +++ b/ld/testsuite/ld-avr32/pcrel.d
  19652. @@ -0,0 +1,74 @@
  19653. +#name: AVR32 ELF PC-relative external relocs
  19654. +#source: symbols.s
  19655. +#source: ../../../gas/testsuite/gas/avr32/pcrel.s
  19656. +#ld: -T $srcdir/$subdir/pcrel.ld
  19657. +#objdump: -d
  19658. +
  19659. +.*: file format elf.*avr32.*
  19660. +
  19661. +Disassembly of section .text:
  19662. +
  19663. +a0000000 <_start>:
  19664. +a0000000: d7 03 nop
  19665. +a0000002: d7 03 nop
  19666. +
  19667. +a0000004 <test_rjmp>:
  19668. +a0000004: d7 03 nop
  19669. +a0000006: c0 28 rjmp a000000a <test_rjmp\+0x6>
  19670. +a0000008: d7 03 nop
  19671. +a000000a: e0 8f 01 fb bral a0000400 <extsym10>
  19672. +
  19673. +a000000e <test_rcall>:
  19674. +a000000e: d7 03 nop
  19675. +a0000010 <test_rcall2>:
  19676. +a0000010: c0 2c rcall a0000014 <test_rcall2\+0x4>
  19677. +a0000012: d7 03 nop
  19678. +a0000014: ee b0 ff f6 rcall a0200000 <extsym21>
  19679. +
  19680. +a0000018 <test_branch>:
  19681. +a0000018: c0 31 brne a000001e <test_branch\+0x6>
  19682. +a000001a: fe 9f ff ff bral a0000018 <test_branch>
  19683. +a000001e: ee 90 ff f1 breq a0200000 <extsym21>
  19684. +
  19685. +a0000022 <test_lddpc>:
  19686. +a0000022: 48 30 lddpc r0,a000002c <sym1>
  19687. +a0000024: 48 20 lddpc r0,a000002c <sym1>
  19688. +a0000026: fe f0 7f da ld.w r0,pc\[32730\]
  19689. + ...
  19690. +
  19691. +a000002c <sym1>:
  19692. +a000002c: d7 03 nop
  19693. +a000002e: d7 03 nop
  19694. +
  19695. +a0000030 <test_local>:
  19696. +a0000030: 48 20 lddpc r0,a0000038 <test_local\+0x8>
  19697. +a0000032: 48 30 lddpc r0,a000003c <test_local\+0xc>
  19698. +a0000034: 48 20 lddpc r0,a000003c <test_local\+0xc>
  19699. +a0000036: 00 00 add r0,r0
  19700. +a0000038: d7 03 nop
  19701. +a000003a: d7 03 nop
  19702. +a000003c: d7 03 nop
  19703. +a000003e: d7 03 nop
  19704. +
  19705. +Disassembly of section \.text\.init:
  19706. +a0000040 <test_inter_section>:
  19707. +a0000040: fe b0 ff e7 rcall a000000e <test_rcall>
  19708. +a0000044: d7 03 nop
  19709. +a0000046: fe b0 ff e4 rcall a000000e <test_rcall>
  19710. +a000004a: fe b0 ff e3 rcall a0000010 <test_rcall2>
  19711. +a000004e: d7 03 nop
  19712. +a0000050: fe b0 ff e0 rcall a0000010 <test_rcall2>
  19713. +
  19714. +Disassembly of section \.text\.pcrel10:
  19715. +
  19716. +a0000400 <extsym10>:
  19717. +a0000400: d7 03 nop
  19718. +
  19719. +Disassembly of section \.text\.pcrel16:
  19720. +
  19721. +a0008000 <extsym16>:
  19722. +a0008000: d7 03 nop
  19723. +
  19724. +Disassembly of section \.text\.pcrel21:
  19725. +a0200000 <extsym21>:
  19726. +a0200000: d7 03 nop
  19727. --- /dev/null
  19728. +++ b/ld/testsuite/ld-avr32/pcrel.ld
  19729. @@ -0,0 +1,23 @@
  19730. +ENTRY(_start)
  19731. +SECTIONS
  19732. +{
  19733. + .text 0xa0000000:
  19734. + {
  19735. + *(.text)
  19736. + }
  19737. +
  19738. + .text.pcrel10 0xa0000400:
  19739. + {
  19740. + *(.text.pcrel10)
  19741. + }
  19742. +
  19743. + .text.pcrel16 0xa0008000:
  19744. + {
  19745. + *(.text.pcrel16)
  19746. + }
  19747. +
  19748. + .text.pcrel21 0xa0200000:
  19749. + {
  19750. + *(.text.pcrel21)
  19751. + }
  19752. +}
  19753. --- /dev/null
  19754. +++ b/ld/testsuite/ld-avr32/symbols.s
  19755. @@ -0,0 +1,20 @@
  19756. + .text
  19757. + .global _start
  19758. +_start:
  19759. + nop
  19760. + nop
  19761. +
  19762. + .section .text.pcrel10,"ax"
  19763. + .global extsym10
  19764. +extsym10:
  19765. + nop
  19766. +
  19767. + .section .text.pcrel16,"ax"
  19768. + .global extsym16
  19769. +extsym16:
  19770. + nop
  19771. +
  19772. + .section .text.pcrel21,"ax"
  19773. + .global extsym21
  19774. +extsym21:
  19775. + nop
  19776. --- /dev/null
  19777. +++ b/opcodes/avr32-asm.c
  19778. @@ -0,0 +1,244 @@
  19779. +/* Assembler interface for AVR32.
  19780. + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
  19781. +
  19782. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  19783. +
  19784. + This file is part of libopcodes.
  19785. +
  19786. + This program is free software; you can redistribute it and/or
  19787. + modify it under the terms of the GNU General Public License as
  19788. + published by the Free Software Foundation; either version 2 of the
  19789. + License, or (at your option) any later version.
  19790. +
  19791. + This program is distributed in the hope that it will be useful, but
  19792. + WITHOUT ANY WARRANTY; without even the implied warranty of
  19793. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19794. + General Public License for more details.
  19795. +
  19796. + You should have received a copy of the GNU General Public License
  19797. + along with this program; if not, write to the Free Software
  19798. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  19799. + 02111-1307, USA. */
  19800. +
  19801. +#include <string.h>
  19802. +
  19803. +#include "avr32-opc.h"
  19804. +#include "avr32-asm.h"
  19805. +
  19806. +/* Structure for a register hash table entry. */
  19807. +struct reg_entry
  19808. +{
  19809. + const char *name;
  19810. + int number;
  19811. +};
  19812. +
  19813. +/* Integer Registers. */
  19814. +static const struct reg_entry reg_table[] =
  19815. + {
  19816. + /* Primary names (used by the disassembler) */
  19817. + { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 },
  19818. + { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 },
  19819. + { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 },
  19820. + { "r12", 12 }, { "sp", 13 }, { "lr", 14 }, { "pc", 15 },
  19821. + /* Alternatives to sp, lr and pc. */
  19822. + { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
  19823. + };
  19824. +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
  19825. +
  19826. +/* Coprocessor Registers. */
  19827. +static const struct reg_entry cr_table[] =
  19828. + {
  19829. + { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 },
  19830. + { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 }, { "cr7", 7 },
  19831. + { "cr8", 8 }, { "cr9", 9 }, { "cr10", 10 }, { "cr11", 11 },
  19832. + { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
  19833. + };
  19834. +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
  19835. +
  19836. +#define AVR32_NR_FPREGS (sizeof(fr_table)/sizeof(fr_table[0]))
  19837. +
  19838. +/* PiCo Registers. */
  19839. +static const struct reg_entry pico_table[] =
  19840. + {
  19841. + { "inpix2", 0 }, { "inpix1", 1 }, { "inpix0", 2 },
  19842. + { "outpix2", 3 }, { "outpix1", 4 }, { "outpix0", 5 },
  19843. + { "coeff0_a", 6 }, { "coeff0_b", 7 }, { "coeff1_a", 8 },
  19844. + { "coeff1_b", 9 }, { "coeff2_a", 10 }, { "coeff2_b", 11 },
  19845. + { "vmu0_out", 12 }, { "vmu1_out", 13 }, { "vmu2_out", 14 },
  19846. + { "config", 15 },
  19847. + };
  19848. +#define AVR32_NR_PICOREGS (sizeof(pico_table)/sizeof(pico_table[0]))
  19849. +
  19850. +int
  19851. +avr32_parse_intreg(const char *str)
  19852. +{
  19853. + unsigned int i;
  19854. +
  19855. + for (i = 0; i < AVR32_NR_INTREGS; i++)
  19856. + {
  19857. + if (strcasecmp(reg_table[i].name, str) == 0)
  19858. + return reg_table[i].number;
  19859. + }
  19860. +
  19861. + return -1;
  19862. +}
  19863. +
  19864. +int
  19865. +avr32_parse_cpreg(const char *str)
  19866. +{
  19867. + unsigned int i;
  19868. +
  19869. + for (i = 0; i < AVR32_NR_CPREGS; i++)
  19870. + {
  19871. + if (strcasecmp(cr_table[i].name, str) == 0)
  19872. + return cr_table[i].number;
  19873. + }
  19874. +
  19875. + return -1;
  19876. +}
  19877. +
  19878. +
  19879. +int avr32_parse_picoreg(const char *str)
  19880. +{
  19881. + unsigned int i;
  19882. +
  19883. + for (i = 0; i < AVR32_NR_PICOREGS; i++)
  19884. + {
  19885. + if (strcasecmp(pico_table[i].name, str) == 0)
  19886. + return pico_table[i].number;
  19887. + }
  19888. +
  19889. + return -1;
  19890. +}
  19891. +
  19892. +static unsigned long
  19893. +parse_reglist(char *str, char **endptr, int (*parse_reg)(const char *))
  19894. +{
  19895. + int reg_from, reg_to;
  19896. + unsigned long result = 0;
  19897. + char *p1, *p2, c;
  19898. +
  19899. + while (*str)
  19900. + {
  19901. + for (p1 = str; *p1; p1++)
  19902. + if (*p1 == ',' || *p1 == '-')
  19903. + break;
  19904. +
  19905. + c = *p1, *p1 = 0;
  19906. + reg_from = parse_reg(str);
  19907. + *p1 = c;
  19908. +
  19909. + if (reg_from < 0)
  19910. + break;
  19911. +
  19912. + if (*p1 == '-')
  19913. + {
  19914. + for (p2 = ++p1; *p2; p2++)
  19915. + if (*p2 == ',')
  19916. + break;
  19917. +
  19918. + c = *p2, *p2 = 0;
  19919. + /* printf("going to parse reg_to from `%s'\n", p1); */
  19920. + reg_to = parse_reg(p1);
  19921. + *p2 = c;
  19922. +
  19923. + if (reg_to < 0)
  19924. + break;
  19925. +
  19926. + while (reg_from <= reg_to)
  19927. + result |= (1 << reg_from++);
  19928. + p1 = p2;
  19929. + }
  19930. + else
  19931. + result |= (1 << reg_from);
  19932. +
  19933. + str = p1;
  19934. + if (*str) ++str;
  19935. + }
  19936. +
  19937. + if (endptr)
  19938. + *endptr = str;
  19939. +
  19940. + return result;
  19941. +}
  19942. +
  19943. +unsigned long
  19944. +avr32_parse_reglist(char *str, char **endptr)
  19945. +{
  19946. + return parse_reglist(str, endptr, avr32_parse_intreg);
  19947. +}
  19948. +
  19949. +unsigned long
  19950. +avr32_parse_cpreglist(char *str, char **endptr)
  19951. +{
  19952. + return parse_reglist(str, endptr, avr32_parse_cpreg);
  19953. +}
  19954. +
  19955. +unsigned long
  19956. +avr32_parse_pico_reglist(char *str, char **endptr)
  19957. +{
  19958. + return parse_reglist(str, endptr, avr32_parse_picoreg);
  19959. +}
  19960. +
  19961. +int
  19962. +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8)
  19963. +{
  19964. + unsigned long result = 0;
  19965. +
  19966. + /* printf("convert regmask16 0x%04lx\n", regmask16); */
  19967. +
  19968. + if (regmask16 & 0xf)
  19969. + {
  19970. + if ((regmask16 & 0xf) == 0xf)
  19971. + result |= 1 << 0;
  19972. + else
  19973. + return -1;
  19974. + }
  19975. + if (regmask16 & 0xf0)
  19976. + {
  19977. + if ((regmask16 & 0xf0) == 0xf0)
  19978. + result |= 1 << 1;
  19979. + else
  19980. + return -1;
  19981. + }
  19982. + if (regmask16 & 0x300)
  19983. + {
  19984. + if ((regmask16 & 0x300) == 0x300)
  19985. + result |= 1 << 2;
  19986. + else
  19987. + return -1;
  19988. + }
  19989. + if (regmask16 & (1 << 13))
  19990. + return -1;
  19991. +
  19992. + if (regmask16 & (1 << 10))
  19993. + result |= 1 << 3;
  19994. + if (regmask16 & (1 << 11))
  19995. + result |= 1 << 4;
  19996. + if (regmask16 & (1 << 12))
  19997. + result |= 1 << 5;
  19998. + if (regmask16 & (1 << 14))
  19999. + result |= 1 << 6;
  20000. + if (regmask16 & (1 << 15))
  20001. + result |= 1 << 7;
  20002. +
  20003. + *regmask8 = result;
  20004. +
  20005. + return 0;
  20006. +}
  20007. +
  20008. +#if 0
  20009. +struct reg_map
  20010. +{
  20011. + const struct reg_entry *names;
  20012. + int nr_regs;
  20013. + struct hash_control *htab;
  20014. + const char *errmsg;
  20015. +};
  20016. +
  20017. +struct reg_map all_reg_maps[] =
  20018. + {
  20019. + { reg_table, AVR32_NR_INTREGS, NULL, N_("integral register expected") },
  20020. + { cr_table, AVR32_NR_CPREGS, NULL, N_("coprocessor register expected") },
  20021. + };
  20022. +#endif
  20023. --- /dev/null
  20024. +++ b/opcodes/avr32-asm.h
  20025. @@ -0,0 +1,40 @@
  20026. +/* Assembler interface for AVR32.
  20027. + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
  20028. +
  20029. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  20030. +
  20031. + This file is part of libopcodes.
  20032. +
  20033. + This program is free software; you can redistribute it and/or
  20034. + modify it under the terms of the GNU General Public License as
  20035. + published by the Free Software Foundation; either version 2 of the
  20036. + License, or (at your option) any later version.
  20037. +
  20038. + This program is distributed in the hope that it will be useful, but
  20039. + WITHOUT ANY WARRANTY; without even the implied warranty of
  20040. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  20041. + General Public License for more details.
  20042. +
  20043. + You should have received a copy of the GNU General Public License
  20044. + along with this program; if not, write to the Free Software
  20045. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  20046. + 02111-1307, USA. */
  20047. +#ifndef __OPCODES_AVR32_ASM_H
  20048. +#define __OPCODES_AVR32_ASM_H
  20049. +
  20050. +extern int
  20051. +avr32_parse_intreg(const char *str);
  20052. +extern int
  20053. +avr32_parse_cpreg(const char *str);
  20054. +extern int
  20055. +avr32_parse_picoreg(const char *str);
  20056. +extern unsigned long
  20057. +avr32_parse_reglist(char *str, char **endptr);
  20058. +extern unsigned long
  20059. +avr32_parse_cpreglist(char *str, char **endptr);
  20060. +extern unsigned long
  20061. +avr32_parse_pico_reglist(char *str, char **endptr);
  20062. +extern int
  20063. +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8);
  20064. +
  20065. +#endif /* __OPCODES_AVR32_ASM_H */
  20066. --- /dev/null
  20067. +++ b/opcodes/avr32-dis.c
  20068. @@ -0,0 +1,916 @@
  20069. +/* Print AVR32 instructions for GDB and objdump.
  20070. + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
  20071. +
  20072. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  20073. +
  20074. + This file is part of libopcodes.
  20075. +
  20076. + This program is free software; you can redistribute it and/or
  20077. + modify it under the terms of the GNU General Public License as
  20078. + published by the Free Software Foundation; either version 2 of the
  20079. + License, or (at your option) any later version.
  20080. +
  20081. + This program is distributed in the hope that it will be useful, but
  20082. + WITHOUT ANY WARRANTY; without even the implied warranty of
  20083. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  20084. + General Public License for more details.
  20085. +
  20086. + You should have received a copy of the GNU General Public License
  20087. + along with this program; if not, write to the Free Software
  20088. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  20089. + 02111-1307, USA. */
  20090. +
  20091. +#include "sysdep.h"
  20092. +#include "dis-asm.h"
  20093. +#include "avr32-opc.h"
  20094. +#include "opintl.h"
  20095. +#include "safe-ctype.h"
  20096. +
  20097. +/* TODO: Share this with -asm */
  20098. +
  20099. +/* Structure for a register hash table entry. */
  20100. +struct reg_entry
  20101. +{
  20102. + const char *name;
  20103. + int number;
  20104. +};
  20105. +
  20106. +#ifndef strneq
  20107. +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
  20108. +#endif
  20109. +
  20110. +static char avr32_opt_decode_fpu = 0;
  20111. +
  20112. +static const struct reg_entry reg_table[] =
  20113. + {
  20114. + /* Primary names (used by the disassembler) */
  20115. + { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 },
  20116. + { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 },
  20117. + { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 },
  20118. + { "r12", 12 }, { "sp", 13 }, { "lr", 14 }, { "pc", 15 },
  20119. + /* Alternatives to sp, lr and pc. */
  20120. + { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
  20121. + };
  20122. +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
  20123. +
  20124. +/* Coprocessor Registers. */
  20125. +static const struct reg_entry cr_table[] =
  20126. + {
  20127. + { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 },
  20128. + { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 }, { "cr7", 7 },
  20129. + { "cr8", 8 }, { "cr9", 9 }, { "cr10", 10 }, { "cr11", 11 },
  20130. + { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
  20131. + };
  20132. +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
  20133. +
  20134. +static const char bparts[4] = { 'b', 'l', 'u', 't' };
  20135. +static bfd_vma current_pc;
  20136. +
  20137. +struct avr32_field_value
  20138. +{
  20139. + const struct avr32_ifield *ifield;
  20140. + unsigned long value;
  20141. +};
  20142. +
  20143. +struct avr32_operand
  20144. +{
  20145. + int id;
  20146. + int is_pcrel;
  20147. + int align_order;
  20148. + int (*print)(struct avr32_operand *op, struct disassemble_info *info,
  20149. + struct avr32_field_value *ifields);
  20150. +};
  20151. +
  20152. +static signed long
  20153. +get_signed_value(const struct avr32_field_value *fv)
  20154. +{
  20155. + signed long value = fv->value;
  20156. +
  20157. + if (fv->value & (1 << (fv->ifield->bitsize - 1)))
  20158. + value |= (~0UL << fv->ifield->bitsize);
  20159. +
  20160. + return value;
  20161. +}
  20162. +
  20163. +static void
  20164. +print_reglist_range(unsigned int first, unsigned int last,
  20165. + const struct reg_entry *reg_names,
  20166. + int need_comma,
  20167. + struct disassemble_info *info)
  20168. +{
  20169. + if (need_comma)
  20170. + info->fprintf_func(info->stream, ",");
  20171. +
  20172. + if (first == last)
  20173. + info->fprintf_func(info->stream, "%s",
  20174. + reg_names[first].name);
  20175. + else
  20176. + info->fprintf_func(info->stream, "%s-%s",
  20177. + reg_names[first].name, reg_names[last].name);
  20178. +}
  20179. +
  20180. +static int
  20181. +print_intreg(struct avr32_operand *op,
  20182. + struct disassemble_info *info,
  20183. + struct avr32_field_value *ifields)
  20184. +{
  20185. + unsigned long regid = ifields[0].value << op->align_order;
  20186. +
  20187. + info->fprintf_func(info->stream, "%s",
  20188. + reg_table[regid].name);
  20189. + return 1;
  20190. +}
  20191. +
  20192. +static int
  20193. +print_intreg_predec(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20194. + struct disassemble_info *info,
  20195. + struct avr32_field_value *ifields)
  20196. +{
  20197. + info->fprintf_func(info->stream, "--%s",
  20198. + reg_table[ifields[0].value].name);
  20199. + return 1;
  20200. +}
  20201. +
  20202. +static int
  20203. +print_intreg_postinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20204. + struct disassemble_info *info,
  20205. + struct avr32_field_value *ifields)
  20206. +{
  20207. + info->fprintf_func(info->stream, "%s++",
  20208. + reg_table[ifields[0].value].name);
  20209. + return 1;
  20210. +}
  20211. +
  20212. +static int
  20213. +print_intreg_lsl(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20214. + struct disassemble_info *info,
  20215. + struct avr32_field_value *ifields)
  20216. +{
  20217. + const char *rp = reg_table[ifields[0].value].name;
  20218. + unsigned long sa = ifields[1].value;
  20219. +
  20220. + if (sa)
  20221. + info->fprintf_func(info->stream, "%s<<0x%lx", rp, sa);
  20222. + else
  20223. + info->fprintf_func(info->stream, "%s", rp);
  20224. +
  20225. + return 2;
  20226. +}
  20227. +
  20228. +static int
  20229. +print_intreg_lsr(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20230. + struct disassemble_info *info,
  20231. + struct avr32_field_value *ifields)
  20232. +{
  20233. + const char *rp = reg_table[ifields[0].value].name;
  20234. + unsigned long sa = ifields[1].value;
  20235. +
  20236. + if (sa)
  20237. + info->fprintf_func(info->stream, "%s>>0x%lx", rp, sa);
  20238. + else
  20239. + info->fprintf_func(info->stream, "%s", rp);
  20240. +
  20241. + return 2;
  20242. +}
  20243. +
  20244. +static int
  20245. +print_intreg_bpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20246. + struct disassemble_info *info,
  20247. + struct avr32_field_value *ifields)
  20248. +{
  20249. + info->fprintf_func(info->stream, "%s:%c",
  20250. + reg_table[ifields[0].value].name,
  20251. + bparts[ifields[1].value]);
  20252. + return 2;
  20253. +}
  20254. +
  20255. +static int
  20256. +print_intreg_hpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20257. + struct disassemble_info *info,
  20258. + struct avr32_field_value *ifields)
  20259. +{
  20260. + info->fprintf_func(info->stream, "%s:%c",
  20261. + reg_table[ifields[0].value].name,
  20262. + ifields[1].value ? 't' : 'b');
  20263. + return 2;
  20264. +}
  20265. +
  20266. +static int
  20267. +print_intreg_sdisp(struct avr32_operand *op,
  20268. + struct disassemble_info *info,
  20269. + struct avr32_field_value *ifields)
  20270. +{
  20271. + signed long disp;
  20272. +
  20273. + disp = get_signed_value(&ifields[1]) << op->align_order;
  20274. +
  20275. + info->fprintf_func(info->stream, "%s[%ld]",
  20276. + reg_table[ifields[0].value].name, disp);
  20277. + return 2;
  20278. +}
  20279. +
  20280. +static int
  20281. +print_intreg_udisp(struct avr32_operand *op,
  20282. + struct disassemble_info *info,
  20283. + struct avr32_field_value *ifields)
  20284. +{
  20285. + info->fprintf_func(info->stream, "%s[0x%lx]",
  20286. + reg_table[ifields[0].value].name,
  20287. + ifields[1].value << op->align_order);
  20288. + return 2;
  20289. +}
  20290. +
  20291. +static int
  20292. +print_intreg_index(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20293. + struct disassemble_info *info,
  20294. + struct avr32_field_value *ifields)
  20295. +{
  20296. + const char *rb, *ri;
  20297. + unsigned long sa = ifields[2].value;
  20298. +
  20299. + rb = reg_table[ifields[0].value].name;
  20300. + ri = reg_table[ifields[1].value].name;
  20301. +
  20302. + if (sa)
  20303. + info->fprintf_func(info->stream, "%s[%s<<0x%lx]", rb, ri, sa);
  20304. + else
  20305. + info->fprintf_func(info->stream, "%s[%s]", rb, ri);
  20306. +
  20307. + return 3;
  20308. +}
  20309. +
  20310. +static int
  20311. +print_intreg_xindex(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20312. + struct disassemble_info *info,
  20313. + struct avr32_field_value *ifields)
  20314. +{
  20315. + info->fprintf_func(info->stream, "%s[%s:%c<<2]",
  20316. + reg_table[ifields[0].value].name,
  20317. + reg_table[ifields[1].value].name,
  20318. + bparts[ifields[2].value]);
  20319. + return 3;
  20320. +}
  20321. +
  20322. +static int
  20323. +print_jmplabel(struct avr32_operand *op,
  20324. + struct disassemble_info *info,
  20325. + struct avr32_field_value *ifields)
  20326. +{
  20327. + bfd_vma address, offset;
  20328. +
  20329. + offset = get_signed_value(ifields) << op->align_order;
  20330. + address = (current_pc & (~0UL << op->align_order)) + offset;
  20331. +
  20332. + info->print_address_func(address, info);
  20333. +
  20334. + return 1;
  20335. +}
  20336. +
  20337. +static int
  20338. +print_pc_disp(struct avr32_operand *op,
  20339. + struct disassemble_info *info,
  20340. + struct avr32_field_value *ifields)
  20341. +{
  20342. + bfd_vma address, offset;
  20343. +
  20344. + offset = ifields[0].value << op->align_order;
  20345. + address = (current_pc & (~0UL << op->align_order)) + offset;
  20346. +
  20347. + info->print_address_func(address, info);
  20348. +
  20349. + return 1;
  20350. +}
  20351. +
  20352. +static int
  20353. +print_sp(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20354. + struct disassemble_info *info,
  20355. + struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
  20356. +{
  20357. + info->fprintf_func(info->stream, "sp");
  20358. + return 1;
  20359. +}
  20360. +
  20361. +static int
  20362. +print_sp_disp(struct avr32_operand *op,
  20363. + struct disassemble_info *info,
  20364. + struct avr32_field_value *ifields)
  20365. +{
  20366. + info->fprintf_func(info->stream, "sp[0x%lx]",
  20367. + ifields[0].value << op->align_order);
  20368. + return 1;
  20369. +}
  20370. +
  20371. +static int
  20372. +print_cpno(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20373. + struct disassemble_info *info,
  20374. + struct avr32_field_value *ifields)
  20375. +{
  20376. + info->fprintf_func(info->stream, "cp%lu", ifields[0].value);
  20377. + return 1;
  20378. +}
  20379. +
  20380. +static int
  20381. +print_cpreg(struct avr32_operand *op,
  20382. + struct disassemble_info *info,
  20383. + struct avr32_field_value *ifields)
  20384. +{
  20385. + info->fprintf_func(info->stream, "cr%lu",
  20386. + ifields[0].value << op->align_order);
  20387. + return 1;
  20388. +}
  20389. +
  20390. +static int
  20391. +print_uconst(struct avr32_operand *op,
  20392. + struct disassemble_info *info,
  20393. + struct avr32_field_value *ifields)
  20394. +{
  20395. + info->fprintf_func(info->stream, "0x%lx",
  20396. + ifields[0].value << op->align_order);
  20397. + return 1;
  20398. +}
  20399. +
  20400. +static int
  20401. +print_sconst(struct avr32_operand *op,
  20402. + struct disassemble_info *info,
  20403. + struct avr32_field_value *ifields)
  20404. +{
  20405. + info->fprintf_func(info->stream, "%ld",
  20406. + get_signed_value(ifields) << op->align_order);
  20407. + return 1;
  20408. +}
  20409. +
  20410. +static int
  20411. +print_reglist8_head(unsigned long regmask, int *commap,
  20412. + struct disassemble_info *info)
  20413. +{
  20414. + int first = -1, last, i = 0;
  20415. + int need_comma = 0;
  20416. +
  20417. + while (i < 12)
  20418. + {
  20419. + if (first == -1 && (regmask & 1))
  20420. + {
  20421. + first = i;
  20422. + }
  20423. + else if (first != -1 && !(regmask & 1))
  20424. + {
  20425. + last = i - 1;
  20426. +
  20427. + print_reglist_range(first, last, reg_table, need_comma, info);
  20428. + need_comma = 1;
  20429. + first = -1;
  20430. + }
  20431. +
  20432. + if (i < 8)
  20433. + i += 4;
  20434. + else if (i < 10)
  20435. + i += 2;
  20436. + else
  20437. + i++;
  20438. + regmask >>= 1;
  20439. + }
  20440. +
  20441. + *commap = need_comma;
  20442. + return first;
  20443. +}
  20444. +
  20445. +static void
  20446. +print_reglist8_tail(unsigned long regmask, int first, int need_comma,
  20447. + struct disassemble_info *info)
  20448. +{
  20449. + int last = 11;
  20450. +
  20451. + if (regmask & 0x20)
  20452. + {
  20453. + if (first == -1)
  20454. + first = 12;
  20455. + last = 12;
  20456. + }
  20457. +
  20458. + if (first != -1)
  20459. + {
  20460. + print_reglist_range(first, last, reg_table, need_comma, info);
  20461. + need_comma = 1;
  20462. + first = -1;
  20463. + }
  20464. +
  20465. + if (regmask & 0x40)
  20466. + {
  20467. + if (first == -1)
  20468. + first = 14;
  20469. + last = 14;
  20470. + }
  20471. +
  20472. + if (regmask & 0x80)
  20473. + {
  20474. + if (first == -1)
  20475. + first = 15;
  20476. + last = 15;
  20477. + }
  20478. +
  20479. + if (first != -1)
  20480. + print_reglist_range(first, last, reg_table, need_comma, info);
  20481. +}
  20482. +
  20483. +static int
  20484. +print_reglist8(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20485. + struct disassemble_info *info,
  20486. + struct avr32_field_value *ifields)
  20487. +{
  20488. + unsigned long regmask = ifields[0].value;
  20489. + int first, need_comma;
  20490. +
  20491. + first = print_reglist8_head(regmask, &need_comma, info);
  20492. + print_reglist8_tail(regmask, first, need_comma, info);
  20493. +
  20494. + return 1;
  20495. +}
  20496. +
  20497. +static int
  20498. +print_reglist9(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20499. + struct disassemble_info *info,
  20500. + struct avr32_field_value *ifields)
  20501. +{
  20502. + unsigned long regmask = ifields[0].value >> 1;
  20503. + int first, last, need_comma;
  20504. +
  20505. + first = print_reglist8_head(regmask, &need_comma, info);
  20506. +
  20507. + if ((ifields[0].value & 0x101) == 0x101)
  20508. + {
  20509. + if (first != -1)
  20510. + {
  20511. + last = 11;
  20512. +
  20513. + print_reglist_range(first, last, reg_table, need_comma, info);
  20514. + need_comma = 1;
  20515. + first = -1;
  20516. + }
  20517. +
  20518. + print_reglist_range(15, 15, reg_table, need_comma, info);
  20519. +
  20520. + regmask >>= 5;
  20521. +
  20522. + if ((regmask & 3) == 0)
  20523. + info->fprintf_func(info->stream, ",r12=0");
  20524. + else if ((regmask & 3) == 1)
  20525. + info->fprintf_func(info->stream, ",r12=1");
  20526. + else
  20527. + info->fprintf_func(info->stream, ",r12=-1");
  20528. + }
  20529. + else
  20530. + print_reglist8_tail(regmask, first, need_comma, info);
  20531. +
  20532. + return 1;
  20533. +}
  20534. +
  20535. +static int
  20536. +print_reglist16(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20537. + struct disassemble_info *info,
  20538. + struct avr32_field_value *ifields)
  20539. +{
  20540. + unsigned long regmask = ifields[0].value;
  20541. + unsigned int i = 0, first, last;
  20542. + int need_comma = 0;
  20543. +
  20544. + while (i < 16)
  20545. + {
  20546. + if (regmask & 1)
  20547. + {
  20548. + first = i;
  20549. + while (i < 16)
  20550. + {
  20551. + i++;
  20552. + regmask >>= 1;
  20553. + if (!(regmask & 1))
  20554. + break;
  20555. + }
  20556. + last = i - 1;
  20557. + print_reglist_range(first, last, reg_table, need_comma, info);
  20558. + need_comma = 1;
  20559. + }
  20560. + else
  20561. + {
  20562. + i++;
  20563. + regmask >>= 1;
  20564. + }
  20565. + }
  20566. +
  20567. + return 1;
  20568. +}
  20569. +
  20570. +static int
  20571. +print_reglist_ldm(struct avr32_operand *op,
  20572. + struct disassemble_info *info,
  20573. + struct avr32_field_value *ifields)
  20574. +{
  20575. + int rp, w_bit;
  20576. + int i, first, last;
  20577. + unsigned long regmask;
  20578. +
  20579. + rp = ifields[0].value;
  20580. + w_bit = ifields[1].value;
  20581. + regmask = ifields[2].value;
  20582. +
  20583. + if (regmask & (1 << AVR32_REG_PC) && rp == AVR32_REG_PC)
  20584. + {
  20585. + if (w_bit)
  20586. + info->fprintf_func(info->stream, "sp++");
  20587. + else
  20588. + info->fprintf_func(info->stream, "sp");
  20589. +
  20590. + for (i = 0; i < 12; )
  20591. + {
  20592. + if (regmask & (1 << i))
  20593. + {
  20594. + first = i;
  20595. + while (i < 12)
  20596. + {
  20597. + i++;
  20598. + if (!(regmask & (1 << i)))
  20599. + break;
  20600. + }
  20601. + last = i - 1;
  20602. + print_reglist_range(first, last, reg_table, 1, info);
  20603. + }
  20604. + else
  20605. + i++;
  20606. + }
  20607. +
  20608. + info->fprintf_func(info->stream, ",pc");
  20609. + if (regmask & (1 << AVR32_REG_LR))
  20610. + info->fprintf_func(info->stream, ",r12=-1");
  20611. + else if (regmask & (1 << AVR32_REG_R12))
  20612. + info->fprintf_func(info->stream, ",r12=1");
  20613. + else
  20614. + info->fprintf_func(info->stream, ",r12=0");
  20615. + }
  20616. + else
  20617. + {
  20618. + if (w_bit)
  20619. + info->fprintf_func(info->stream, "%s++,", reg_table[rp].name);
  20620. + else
  20621. + info->fprintf_func(info->stream, "%s,", reg_table[rp].name);
  20622. +
  20623. + print_reglist16(op, info, ifields + 2);
  20624. + }
  20625. +
  20626. + return 3;
  20627. +}
  20628. +
  20629. +static int
  20630. +print_reglist_cp8(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20631. + struct disassemble_info *info,
  20632. + struct avr32_field_value *ifields)
  20633. +{
  20634. + unsigned long regmask = ifields[0].value;
  20635. + unsigned int i = 0, first, last, offset = 0;
  20636. + int need_comma = 0;
  20637. +
  20638. + if (ifields[1].value)
  20639. + offset = 8;
  20640. +
  20641. + while (i < 8)
  20642. + {
  20643. + if (regmask & 1)
  20644. + {
  20645. + first = i;
  20646. + while (i < 8)
  20647. + {
  20648. + i++;
  20649. + regmask >>= 1;
  20650. + if (!(regmask & 1))
  20651. + break;
  20652. + }
  20653. + last = i - 1;
  20654. + print_reglist_range(offset + first, offset + last,
  20655. + cr_table, need_comma, info);
  20656. + need_comma = 1;
  20657. + }
  20658. + else
  20659. + {
  20660. + i++;
  20661. + regmask >>= 1;
  20662. + }
  20663. + }
  20664. +
  20665. + return 2;
  20666. +}
  20667. +
  20668. +static int
  20669. +print_reglist_cpd8(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20670. + struct disassemble_info *info,
  20671. + struct avr32_field_value *ifields)
  20672. +{
  20673. + unsigned long regmask = ifields[0].value;
  20674. + unsigned int i = 0, first, last;
  20675. + int need_comma = 0;
  20676. +
  20677. + while (i < 8)
  20678. + {
  20679. + if (regmask & 1)
  20680. + {
  20681. + first = 2 * i;
  20682. + while (i < 8)
  20683. + {
  20684. + i++;
  20685. + regmask >>= 1;
  20686. + if (!(regmask & 1))
  20687. + break;
  20688. + }
  20689. + last = 2 * (i - 1) + 1;
  20690. + print_reglist_range(first, last, cr_table, need_comma, info);
  20691. + need_comma = 1;
  20692. + }
  20693. + else
  20694. + {
  20695. + i++;
  20696. + regmask >>= 1;
  20697. + }
  20698. + }
  20699. +
  20700. + return 1;
  20701. +}
  20702. +
  20703. +static int
  20704. +print_retval(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20705. + struct disassemble_info *info,
  20706. + struct avr32_field_value *ifields)
  20707. +{
  20708. + unsigned long regid = ifields[0].value;
  20709. + const char *retval;
  20710. +
  20711. + if (regid < AVR32_REG_SP)
  20712. + retval = reg_table[regid].name;
  20713. + else if (regid == AVR32_REG_SP)
  20714. + retval = "0";
  20715. + else if (regid == AVR32_REG_LR)
  20716. + retval = "-1";
  20717. + else
  20718. + retval = "1";
  20719. +
  20720. + info->fprintf_func(info->stream, "%s", retval);
  20721. +
  20722. + return 1;
  20723. +}
  20724. +
  20725. +static int
  20726. +print_mcall(struct avr32_operand *op,
  20727. + struct disassemble_info *info,
  20728. + struct avr32_field_value *ifields)
  20729. +{
  20730. + unsigned long regid = ifields[0].value;
  20731. +
  20732. + if (regid == AVR32_REG_PC)
  20733. + print_jmplabel(op, info, ifields + 1);
  20734. + else
  20735. + print_intreg_sdisp(op, info, ifields);
  20736. +
  20737. + return 2;
  20738. +}
  20739. +
  20740. +static int
  20741. +print_jospinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20742. + struct disassemble_info *info,
  20743. + struct avr32_field_value *ifields)
  20744. +{
  20745. + signed long value = ifields[0].value;
  20746. +
  20747. + if (value >= 4)
  20748. + value -= 8;
  20749. + else
  20750. + value += 1;
  20751. +
  20752. + info->fprintf_func(info->stream, "%ld", value);
  20753. +
  20754. + return 1;
  20755. +}
  20756. +
  20757. +static int
  20758. +print_coh(struct avr32_operand *op ATTRIBUTE_UNUSED,
  20759. + struct disassemble_info *info,
  20760. + struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
  20761. +{
  20762. + info->fprintf_func(info->stream, "COH");
  20763. + return 0;
  20764. +}
  20765. +
  20766. +#define OP(name, sgn, pcrel, align, func) \
  20767. + { AVR32_OPERAND_##name, pcrel, align, print_##func }
  20768. +
  20769. +struct avr32_operand operand[AVR32_NR_OPERANDS] =
  20770. + {
  20771. + OP(INTREG, 0, 0, 0, intreg),
  20772. + OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
  20773. + OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
  20774. + OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
  20775. + OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
  20776. + OP(INTREG_BSEL, 0, 0, 0, intreg_bpart),
  20777. + OP(INTREG_HSEL, 0, 0, 1, intreg_hpart),
  20778. + OP(INTREG_SDISP, 1, 0, 0, intreg_sdisp),
  20779. + OP(INTREG_SDISP_H, 1, 0, 1, intreg_sdisp),
  20780. + OP(INTREG_SDISP_W, 1, 0, 2, intreg_sdisp),
  20781. + OP(INTREG_UDISP, 0, 0, 0, intreg_udisp),
  20782. + OP(INTREG_UDISP_H, 0, 0, 1, intreg_udisp),
  20783. + OP(INTREG_UDISP_W, 0, 0, 2, intreg_udisp),
  20784. + OP(INTREG_INDEX, 0, 0, 0, intreg_index),
  20785. + OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
  20786. + OP(DWREG, 0, 0, 1, intreg),
  20787. + OP(PC_UDISP_W, 0, 1, 2, pc_disp),
  20788. + OP(SP, 0, 0, 0, sp),
  20789. + OP(SP_UDISP_W, 0, 0, 2, sp_disp),
  20790. + OP(CPNO, 0, 0, 0, cpno),
  20791. + OP(CPREG, 0, 0, 0, cpreg),
  20792. + OP(CPREG_D, 0, 0, 1, cpreg),
  20793. + OP(UNSIGNED_CONST, 0, 0, 0, uconst),
  20794. + OP(UNSIGNED_CONST_W, 0, 0, 2, uconst),
  20795. + OP(SIGNED_CONST, 1, 0, 0, sconst),
  20796. + OP(SIGNED_CONST_W, 1, 0, 2, sconst),
  20797. + OP(JMPLABEL, 1, 1, 1, jmplabel),
  20798. + OP(UNSIGNED_NUMBER, 0, 0, 0, uconst),
  20799. + OP(UNSIGNED_NUMBER_W, 0, 0, 2, uconst),
  20800. + OP(REGLIST8, 0, 0, 0, reglist8),
  20801. + OP(REGLIST9, 0, 0, 0, reglist9),
  20802. + OP(REGLIST16, 0, 0, 0, reglist16),
  20803. + OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
  20804. + OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
  20805. + OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
  20806. + OP(RETVAL, 0, 0, 0, retval),
  20807. + OP(MCALL, 1, 0, 2, mcall),
  20808. + OP(JOSPINC, 0, 0, 0, jospinc),
  20809. + OP(COH, 0, 0, 0, coh),
  20810. + };
  20811. +
  20812. +static void
  20813. +print_opcode(bfd_vma insn_word, const struct avr32_opcode *opc,
  20814. + bfd_vma pc, struct disassemble_info *info)
  20815. +{
  20816. + const struct avr32_syntax *syntax = opc->syntax;
  20817. + struct avr32_field_value fields[AVR32_MAX_FIELDS];
  20818. + unsigned int i, next_field = 0, nr_operands;
  20819. +
  20820. + for (i = 0; i < opc->nr_fields; i++)
  20821. + {
  20822. + opc->fields[i]->extract(opc->fields[i], &insn_word, &fields[i].value);
  20823. + fields[i].ifield = opc->fields[i];
  20824. + }
  20825. +
  20826. + current_pc = pc;
  20827. + info->fprintf_func(info->stream, "%s", syntax->mnemonic->name);
  20828. +
  20829. + if (syntax->nr_operands < 0)
  20830. + nr_operands = (unsigned int) -syntax->nr_operands;
  20831. + else
  20832. + nr_operands = (unsigned int) syntax->nr_operands;
  20833. +
  20834. + for (i = 0; i < nr_operands; i++)
  20835. + {
  20836. + struct avr32_operand *op = &operand[syntax->operand[i]];
  20837. +
  20838. + if (i)
  20839. + info->fprintf_func(info->stream, ",");
  20840. + else
  20841. + info->fprintf_func(info->stream, "\t");
  20842. + next_field += op->print(op, info, &fields[next_field]);
  20843. + }
  20844. +}
  20845. +
  20846. +#define is_fpu_insn(iw) ((iw&0xf9f0e000)==0xe1a00000)
  20847. +
  20848. +static const struct avr32_opcode *
  20849. +find_opcode(bfd_vma insn_word)
  20850. +{
  20851. + int i;
  20852. +
  20853. + for (i = 0; i < AVR32_NR_OPCODES; i++)
  20854. + {
  20855. + const struct avr32_opcode *opc = &avr32_opc_table[i];
  20856. +
  20857. + if ((insn_word & opc->mask) == opc->value)
  20858. + {
  20859. + if (avr32_opt_decode_fpu)
  20860. + {
  20861. + if (is_fpu_insn(insn_word))
  20862. + {
  20863. + if (opc->id != AVR32_OPC_COP)
  20864. + return opc;
  20865. + }
  20866. + else
  20867. + return opc;
  20868. + }
  20869. + else
  20870. + return opc;
  20871. + }
  20872. + }
  20873. +
  20874. + return NULL;
  20875. +}
  20876. +
  20877. +static int
  20878. +read_insn_word(bfd_vma pc, bfd_vma *valuep,
  20879. + struct disassemble_info *info)
  20880. +{
  20881. + bfd_byte b[4];
  20882. + int status;
  20883. +
  20884. + status = info->read_memory_func(pc, b, 4, info);
  20885. + if (status)
  20886. + {
  20887. + status = info->read_memory_func(pc, b, 2, info);
  20888. + if (status)
  20889. + {
  20890. + info->memory_error_func(status, pc, info);
  20891. + return -1;
  20892. + }
  20893. + b[3] = b[2] = 0;
  20894. + }
  20895. +
  20896. + *valuep = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
  20897. + return 0;
  20898. +}
  20899. +
  20900. +/* Parse an individual disassembler option. */
  20901. +
  20902. +void
  20903. +parse_avr32_disassembler_option (option)
  20904. + char * option;
  20905. +{
  20906. + if (option == NULL)
  20907. + return;
  20908. +
  20909. + if (!strcmp(option,"decode-fpu"))
  20910. + {
  20911. + avr32_opt_decode_fpu = 1;
  20912. + return;
  20913. + }
  20914. +
  20915. + printf("\n%s--",option);
  20916. + /* XXX - should break 'option' at following delimiter. */
  20917. + fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
  20918. +
  20919. + return;
  20920. +}
  20921. +
  20922. +/* Parse the string of disassembler options, spliting it at whitespaces
  20923. + or commas. (Whitespace separators supported for backwards compatibility). */
  20924. +
  20925. +static void
  20926. +parse_disassembler_options (char *options)
  20927. +{
  20928. + if (options == NULL)
  20929. + return;
  20930. +
  20931. + while (*options)
  20932. + {
  20933. + parse_avr32_disassembler_option (options);
  20934. +
  20935. + /* Skip forward to next seperator. */
  20936. + while ((*options) && (! ISSPACE (*options)) && (*options != ','))
  20937. + ++ options;
  20938. + /* Skip forward past seperators. */
  20939. + while (ISSPACE (*options) || (*options == ','))
  20940. + ++ options;
  20941. + }
  20942. +}
  20943. +
  20944. +int
  20945. +print_insn_avr32(bfd_vma pc, struct disassemble_info *info)
  20946. +{
  20947. + bfd_vma insn_word;
  20948. + const struct avr32_opcode *opc;
  20949. +
  20950. + if (info->disassembler_options)
  20951. + {
  20952. + parse_disassembler_options (info->disassembler_options);
  20953. +
  20954. + /* To avoid repeated parsing of these options, we remove them here. */
  20955. + info->disassembler_options = NULL;
  20956. + }
  20957. +
  20958. + info->bytes_per_chunk = 1;
  20959. + info->display_endian = BFD_ENDIAN_BIG;
  20960. +
  20961. + if (read_insn_word(pc, &insn_word, info))
  20962. + return -1;
  20963. +
  20964. + opc = find_opcode(insn_word);
  20965. + if (opc)
  20966. + {
  20967. + print_opcode(insn_word, opc, pc, info);
  20968. + return opc->size;
  20969. + }
  20970. + else
  20971. + {
  20972. + info->fprintf_func(info->stream, _("*unknown*"));
  20973. + return 2;
  20974. + }
  20975. +
  20976. +}
  20977. +
  20978. +void
  20979. +print_avr32_disassembler_options (FILE *stream ATTRIBUTE_UNUSED)
  20980. +{
  20981. + fprintf(stream, "\n AVR32 Specific Disassembler Options:\n");
  20982. + fprintf(stream, " -M decode-fpu Print FPU instructions instead of 'cop' \n");
  20983. +}
  20984. +
  20985. --- /dev/null
  20986. +++ b/opcodes/avr32-opc.c
  20987. @@ -0,0 +1,6906 @@
  20988. +/* Opcode tables for AVR32.
  20989. + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
  20990. +
  20991. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  20992. +
  20993. + This file is part of libopcodes.
  20994. +
  20995. + This program is free software; you can redistribute it and/or
  20996. + modify it under the terms of the GNU General Public License as
  20997. + published by the Free Software Foundation; either version 2 of the
  20998. + License, or (at your option) any later version.
  20999. +
  21000. + This program is distributed in the hope that it will be useful, but
  21001. + WITHOUT ANY WARRANTY; without even the implied warranty of
  21002. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  21003. + General Public License for more details.
  21004. +
  21005. + You should have received a copy of the GNU General Public License
  21006. + along with this program; if not, write to the Free Software
  21007. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  21008. + 02111-1307, USA. */
  21009. +
  21010. +#include <stdlib.h>
  21011. +#include <assert.h>
  21012. +
  21013. +#include "avr32-opc.h"
  21014. +
  21015. +#define PICO_CPNO 1
  21016. +
  21017. +void
  21018. +avr32_insert_simple(const struct avr32_ifield *field,
  21019. + void *buf, unsigned long value)
  21020. +{
  21021. + bfd_vma word;
  21022. +
  21023. + word = bfd_getb32(buf);
  21024. + word &= ~field->mask;
  21025. + word |= (value << field->shift) & field->mask;
  21026. + bfd_putb32(word, buf);
  21027. +}
  21028. +
  21029. +void
  21030. +avr32_insert_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
  21031. + void *buf, unsigned long value)
  21032. +{
  21033. + char *opcode = buf;
  21034. +
  21035. + opcode[0] = (opcode[0] & 0xe1) | (value & 0x1e);
  21036. + opcode[1] = (opcode[1] & 0xef) | ((value & 1) << 4);
  21037. +}
  21038. +
  21039. +void
  21040. +avr32_insert_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
  21041. + void *buf, unsigned long value)
  21042. +{
  21043. + char *opcode = buf;
  21044. +
  21045. + opcode[0] = (opcode[0] & 0xf0) | ((value & 0xf0) >> 4);
  21046. + opcode[1] = ((opcode[1] & 0x0c) | ((value & 0x0f) << 4)
  21047. + | ((value & 0x300) >> 8));
  21048. +}
  21049. +
  21050. +
  21051. +void
  21052. +avr32_insert_k21(const struct avr32_ifield *field,
  21053. + void *buf, unsigned long value)
  21054. +{
  21055. + bfd_vma word;
  21056. + bfd_vma k21;
  21057. +
  21058. + word = bfd_getb32(buf);
  21059. + word &= ~field->mask;
  21060. + k21 = ((value & 0xffff) | ((value & 0x10000) << 4)
  21061. + | ((value & 0x1e0000) << 8));
  21062. + assert(!(k21 & ~field->mask));
  21063. + word |= k21;
  21064. + bfd_putb32(word, buf);
  21065. +}
  21066. +
  21067. +void
  21068. +avr32_insert_cpop(const struct avr32_ifield *field,
  21069. + void *buf, unsigned long value)
  21070. +{
  21071. + bfd_vma word;
  21072. +
  21073. + word = bfd_getb32(buf);
  21074. + word &= ~field->mask;
  21075. + word |= (((value & 0x1e) << 15) | ((value & 0x60) << 20)
  21076. + | ((value & 0x01) << 12));
  21077. + bfd_putb32(word, buf);
  21078. +}
  21079. +
  21080. +void
  21081. +avr32_insert_k12cp(const struct avr32_ifield *field,
  21082. + void *buf, unsigned long value)
  21083. +{
  21084. + bfd_vma word;
  21085. +
  21086. + word = bfd_getb32(buf);
  21087. + word &= ~field->mask;
  21088. + word |= ((value & 0xf00) << 4) | (value & 0xff);
  21089. + bfd_putb32(word, buf);
  21090. +}
  21091. +
  21092. +void avr32_extract_simple(const struct avr32_ifield *field,
  21093. + void *buf, unsigned long *value)
  21094. +{
  21095. + /* XXX: The disassembler has done any necessary byteswapping already */
  21096. + bfd_vma word = *(bfd_vma *)buf;
  21097. +
  21098. + *value = (word & field->mask) >> field->shift;
  21099. +}
  21100. +
  21101. +void avr32_extract_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
  21102. + void *buf, unsigned long *value)
  21103. +{
  21104. + bfd_vma word = *(bfd_vma *)buf;
  21105. +
  21106. + *value = ((word >> 20) & 1) | ((word >> 24) & 0x1e);
  21107. +}
  21108. +
  21109. +void avr32_extract_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
  21110. + void *buf, unsigned long *value)
  21111. +{
  21112. + bfd_vma word = *(bfd_vma *)buf;
  21113. +
  21114. + *value = ((word >> 8) & 0x300) | ((word >> 20) & 0xff);
  21115. +}
  21116. +
  21117. +void avr32_extract_k21(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
  21118. + void *buf, unsigned long *value)
  21119. +{
  21120. + bfd_vma word = *(bfd_vma *)buf;
  21121. +
  21122. + *value = ((word & 0xffff) | ((word >> 4) & 0x10000)
  21123. + | ((word >> 8) & 0x1e0000));
  21124. +}
  21125. +
  21126. +void avr32_extract_cpop(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
  21127. + void *buf, unsigned long *value)
  21128. +{
  21129. + bfd_vma word = *(bfd_vma *)buf;
  21130. +
  21131. + *value = (((word >> 12) & 1) | ((word >> 15) & 0x1e)
  21132. + | ((word >> 20) & 0x60));
  21133. +}
  21134. +
  21135. +void avr32_extract_k12cp(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
  21136. + void *buf, unsigned long *value)
  21137. +{
  21138. + bfd_vma word = *(bfd_vma *)buf;
  21139. +
  21140. + *value = ((word >> 4) & 0xf00) | (word & 0xff);
  21141. +}
  21142. +
  21143. +
  21144. +#define IFLD(id, bitsz, shift, mask, func) \
  21145. + { AVR32_IFIELD_##id, bitsz, shift, mask, \
  21146. + avr32_insert_##func, avr32_extract_##func }
  21147. +
  21148. +const struct avr32_ifield avr32_ifield_table[] =
  21149. + {
  21150. + IFLD(RX, 4, 25, 0x1e000000, simple),
  21151. + IFLD(RY, 4, 16, 0x000f0000, simple),
  21152. + IFLD(COND4C, 4, 20, 0x00f00000, simple),
  21153. + IFLD(K8C, 8, 20, 0x0ff00000, simple),
  21154. + IFLD(K7C, 7, 20, 0x07f00000, simple),
  21155. + IFLD(K5C, 5, 20, 0x01f00000, simple),
  21156. + IFLD(K3, 3, 20, 0x00700000, simple),
  21157. + IFLD(RY_DW, 3, 17, 0x000e0000, simple),
  21158. + IFLD(COND4E, 4, 8, 0x00000f00, simple),
  21159. + IFLD(K8E, 8, 0, 0x000000ff, simple),
  21160. + IFLD(BIT5C, 5, 20, 0x1e100000, bit5c),
  21161. + IFLD(COND3, 3, 16, 0x00070000, simple),
  21162. + IFLD(K10, 10, 16, 0x0ff30000, k10),
  21163. + IFLD(POPM, 9, 19, 0x0ff80000, simple),
  21164. + IFLD(K2, 2, 4, 0x00000030, simple),
  21165. + IFLD(RD_E, 4, 0, 0x0000000f, simple),
  21166. + IFLD(RD_DW, 3, 1, 0x0000000e, simple),
  21167. + IFLD(X, 1, 5, 0x00000020, simple),
  21168. + IFLD(Y, 1, 4, 0x00000010, simple),
  21169. + IFLD(X2, 1, 13, 0x00002000, simple),
  21170. + IFLD(Y2, 1, 12, 0x00001000, simple),
  21171. + IFLD(K5E, 5, 0, 0x0000001f, simple),
  21172. + IFLD(PART2, 2, 0, 0x00000003, simple),
  21173. + IFLD(PART1, 1, 0, 0x00000001, simple),
  21174. + IFLD(K16, 16, 0, 0x0000ffff, simple),
  21175. + IFLD(CACHEOP, 5, 11, 0x0000f800, simple),
  21176. + IFLD(K11, 11, 0, 0x000007ff, simple),
  21177. + IFLD(K21, 21, 0, 0x1e10ffff, k21),
  21178. + IFLD(CPOP, 7, 12, 0x060f1000, cpop),
  21179. + IFLD(CPNO, 3, 13, 0x0000e000, simple),
  21180. + IFLD(CRD_RI, 4, 8, 0x00000f00, simple),
  21181. + IFLD(CRX, 4, 4, 0x000000f0, simple),
  21182. + IFLD(CRY, 4, 0, 0x0000000f, simple),
  21183. + IFLD(K7E, 7, 0, 0x0000007f, simple),
  21184. + IFLD(CRD_DW, 3, 9, 0x00000e00, simple),
  21185. + IFLD(PART1_K12, 1, 12, 0x00001000, simple),
  21186. + IFLD(PART2_K12, 2, 12, 0x00003000, simple),
  21187. + IFLD(K12, 12, 0, 0x00000fff, simple),
  21188. + IFLD(S5, 5, 5, 0x000003e0, simple),
  21189. + IFLD(K5E2, 5, 4, 0x000001f0, simple),
  21190. + IFLD(K4, 4, 20, 0x00f00000, simple),
  21191. + IFLD(COND4E2, 4, 4, 0x000000f0, simple),
  21192. + IFLD(K8E2, 8, 4, 0x00000ff0, simple),
  21193. + IFLD(K6, 6, 20, 0x03f00000, simple),
  21194. + IFLD(MEM15, 15, 0, 0x00007fff, simple),
  21195. + IFLD(MEMB5, 5, 15, 0x000f8000, simple),
  21196. + IFLD(W, 1, 25, 0x02000000, simple),
  21197. + /* Coprocessor Multiple High/Low */
  21198. + IFLD(CM_HL, 1, 8, 0x00000100, simple),
  21199. + IFLD(K12CP, 12 ,0, 0x0000f0ff, k12cp),
  21200. + IFLD(K9E, 9 ,0, 0x000001ff, simple),
  21201. + IFLD (FP_RX, 4, 4, 0x000000F0, simple),
  21202. + IFLD (FP_RY, 4, 0, 0x0000000F, simple),
  21203. + IFLD (FP_RD, 4, 8, 0x00000F00, simple),
  21204. + IFLD (FP_RA, 4, 16, 0x000F0000, simple)
  21205. + };
  21206. +#undef IFLD
  21207. +
  21208. +
  21209. +struct avr32_opcode avr32_opc_table[] =
  21210. + {
  21211. + {
  21212. + AVR32_OPC_ABS, 2, 0x5c400000, 0xfff00000,
  21213. + &avr32_syntax_table[AVR32_SYNTAX_ABS],
  21214. + BFD_RELOC_UNUSED, 1, -1,
  21215. + {
  21216. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21217. + }
  21218. + },
  21219. + {
  21220. + AVR32_OPC_ACALL, 2, 0xd0000000, 0xf00f0000,
  21221. + &avr32_syntax_table[AVR32_SYNTAX_ACALL],
  21222. + BFD_RELOC_UNUSED, 1, -1,
  21223. + {
  21224. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21225. + },
  21226. + },
  21227. + {
  21228. + AVR32_OPC_ACR, 2, 0x5c000000, 0xfff00000,
  21229. + &avr32_syntax_table[AVR32_SYNTAX_ACR],
  21230. + BFD_RELOC_UNUSED, 1, -1,
  21231. + {
  21232. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21233. + },
  21234. + },
  21235. + {
  21236. + AVR32_OPC_ADC, 4, 0xe0000040, 0xe1f0fff0,
  21237. + &avr32_syntax_table[AVR32_SYNTAX_ADC],
  21238. + BFD_RELOC_UNUSED, 3, -1,
  21239. + {
  21240. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21241. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21242. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21243. + },
  21244. + },
  21245. + {
  21246. + AVR32_OPC_ADD1, 2, 0x00000000, 0xe1f00000,
  21247. + &avr32_syntax_table[AVR32_SYNTAX_ADD1],
  21248. + BFD_RELOC_UNUSED, 2, -1,
  21249. + {
  21250. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21251. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21252. + },
  21253. + },
  21254. + {
  21255. + AVR32_OPC_ADD2, 4, 0xe0000000, 0xe1f0ffc0,
  21256. + &avr32_syntax_table[AVR32_SYNTAX_ADD2],
  21257. + BFD_RELOC_UNUSED, 4, -1,
  21258. + {
  21259. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21260. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21261. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21262. + &avr32_ifield_table[AVR32_IFIELD_K2],
  21263. + },
  21264. + },
  21265. + {
  21266. + AVR32_OPC_ADDABS, 4, 0xe0000e40, 0xe1f0fff0,
  21267. + &avr32_syntax_table[AVR32_SYNTAX_ADDABS],
  21268. + BFD_RELOC_UNUSED, 3, -1,
  21269. + {
  21270. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21271. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21272. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21273. + },
  21274. + },
  21275. + {
  21276. + AVR32_OPC_ADDHH_W, 4, 0xe0000e00, 0xe1f0ffc0,
  21277. + &avr32_syntax_table[AVR32_SYNTAX_ADDHH_W],
  21278. + BFD_RELOC_UNUSED, 5, -1,
  21279. + {
  21280. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21281. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21282. + &avr32_ifield_table[AVR32_IFIELD_X],
  21283. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21284. + &avr32_ifield_table[AVR32_IFIELD_Y],
  21285. + },
  21286. + },
  21287. + {
  21288. + AVR32_OPC_AND1, 2, 0x00600000, 0xe1f00000,
  21289. + &avr32_syntax_table[AVR32_SYNTAX_AND1],
  21290. + BFD_RELOC_UNUSED, 2, -1,
  21291. + {
  21292. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21293. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21294. + },
  21295. + },
  21296. + {
  21297. + AVR32_OPC_AND2, 4, 0xe1e00000, 0xe1f0fe00,
  21298. + &avr32_syntax_table[AVR32_SYNTAX_AND2],
  21299. + BFD_RELOC_UNUSED, 4, -1,
  21300. + {
  21301. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21302. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21303. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21304. + &avr32_ifield_table[AVR32_IFIELD_K5E2],
  21305. + },
  21306. + },
  21307. + {
  21308. + AVR32_OPC_AND3, 4, 0xe1e00200, 0xe1f0fe00,
  21309. + &avr32_syntax_table[AVR32_SYNTAX_AND3],
  21310. + BFD_RELOC_UNUSED, 4, -1,
  21311. + {
  21312. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21313. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21314. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21315. + &avr32_ifield_table[AVR32_IFIELD_K5E2],
  21316. + },
  21317. + },
  21318. + {
  21319. + AVR32_OPC_ANDH, 4, 0xe4100000, 0xfff00000,
  21320. + &avr32_syntax_table[AVR32_SYNTAX_ANDH],
  21321. + BFD_RELOC_AVR32_16U, 2, 1,
  21322. + {
  21323. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21324. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21325. + },
  21326. + },
  21327. + {
  21328. + AVR32_OPC_ANDH_COH, 4, 0xe6100000, 0xfff00000,
  21329. + &avr32_syntax_table[AVR32_SYNTAX_ANDH_COH],
  21330. + BFD_RELOC_AVR32_16U, 2, 1,
  21331. + {
  21332. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21333. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21334. + },
  21335. + },
  21336. + {
  21337. + AVR32_OPC_ANDL, 4, 0xe0100000, 0xfff00000,
  21338. + &avr32_syntax_table[AVR32_SYNTAX_ANDL],
  21339. + BFD_RELOC_AVR32_16U, 2, 1,
  21340. + {
  21341. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21342. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21343. + },
  21344. + },
  21345. + {
  21346. + AVR32_OPC_ANDL_COH, 4, 0xe2100000, 0xfff00000,
  21347. + &avr32_syntax_table[AVR32_SYNTAX_ANDL_COH],
  21348. + BFD_RELOC_AVR32_16U, 2, 1,
  21349. + {
  21350. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21351. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21352. + },
  21353. + },
  21354. + {
  21355. + AVR32_OPC_ANDN, 2, 0x00800000, 0xe1f00000,
  21356. + &avr32_syntax_table[AVR32_SYNTAX_ANDN],
  21357. + BFD_RELOC_UNUSED, 2, -1,
  21358. + {
  21359. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21360. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21361. + },
  21362. + },
  21363. + {
  21364. + AVR32_OPC_ASR1, 4, 0xe0000840, 0xe1f0fff0,
  21365. + &avr32_syntax_table[AVR32_SYNTAX_ASR1],
  21366. + BFD_RELOC_UNUSED, 3, -1,
  21367. + {
  21368. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21369. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21370. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21371. + },
  21372. + },
  21373. + {
  21374. + AVR32_OPC_ASR3, 4, 0xe0001400, 0xe1f0ffe0,
  21375. + &avr32_syntax_table[AVR32_SYNTAX_ASR3],
  21376. + BFD_RELOC_UNUSED, 3, -1,
  21377. + {
  21378. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21379. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21380. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  21381. + },
  21382. + },
  21383. + {
  21384. + AVR32_OPC_ASR2, 2, 0xa1400000, 0xe1e00000,
  21385. + &avr32_syntax_table[AVR32_SYNTAX_ASR2],
  21386. + BFD_RELOC_UNUSED, 2, -1,
  21387. + {
  21388. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21389. + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
  21390. + },
  21391. + },
  21392. + {
  21393. + AVR32_OPC_BLD, 4, 0xedb00000, 0xfff0ffe0,
  21394. + &avr32_syntax_table[AVR32_SYNTAX_BLD],
  21395. + BFD_RELOC_UNUSED, 2, -1,
  21396. + {
  21397. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21398. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  21399. + },
  21400. + },
  21401. + {
  21402. + AVR32_OPC_BREQ1, 2, 0xc0000000, 0xf00f0000,
  21403. + &avr32_syntax_table[AVR32_SYNTAX_BREQ1],
  21404. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21405. + {
  21406. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21407. + },
  21408. + },
  21409. + {
  21410. + AVR32_OPC_BRNE1, 2, 0xc0010000, 0xf00f0000,
  21411. + &avr32_syntax_table[AVR32_SYNTAX_BRNE1],
  21412. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21413. + {
  21414. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21415. + },
  21416. + },
  21417. + {
  21418. + AVR32_OPC_BRCC1, 2, 0xc0020000, 0xf00f0000,
  21419. + &avr32_syntax_table[AVR32_SYNTAX_BRCC1],
  21420. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21421. + {
  21422. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21423. + },
  21424. + },
  21425. + {
  21426. + AVR32_OPC_BRCS1, 2, 0xc0030000, 0xf00f0000,
  21427. + &avr32_syntax_table[AVR32_SYNTAX_BRCS1],
  21428. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21429. + {
  21430. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21431. + },
  21432. + },
  21433. + {
  21434. + AVR32_OPC_BRGE1, 2, 0xc0040000, 0xf00f0000,
  21435. + &avr32_syntax_table[AVR32_SYNTAX_BRGE1],
  21436. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21437. + {
  21438. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21439. + },
  21440. + },
  21441. + {
  21442. + AVR32_OPC_BRLT1, 2, 0xc0050000, 0xf00f0000,
  21443. + &avr32_syntax_table[AVR32_SYNTAX_BRLT1],
  21444. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21445. + {
  21446. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21447. + },
  21448. + },
  21449. + {
  21450. + AVR32_OPC_BRMI1, 2, 0xc0060000, 0xf00f0000,
  21451. + &avr32_syntax_table[AVR32_SYNTAX_BRMI1],
  21452. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21453. + {
  21454. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21455. + },
  21456. + },
  21457. + {
  21458. + AVR32_OPC_BRPL1, 2, 0xc0070000, 0xf00f0000,
  21459. + &avr32_syntax_table[AVR32_SYNTAX_BRPL1],
  21460. + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
  21461. + {
  21462. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  21463. + },
  21464. + },
  21465. + {
  21466. + AVR32_OPC_BREQ2, 4, 0xe0800000, 0xe1ef0000,
  21467. + &avr32_syntax_table[AVR32_SYNTAX_BREQ2],
  21468. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21469. + {
  21470. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21471. + },
  21472. + },
  21473. + {
  21474. + AVR32_OPC_BRNE2, 4, 0xe0810000, 0xe1ef0000,
  21475. + &avr32_syntax_table[AVR32_SYNTAX_BRNE2],
  21476. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21477. + {
  21478. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21479. + },
  21480. + },
  21481. + {
  21482. + AVR32_OPC_BRCC2, 4, 0xe0820000, 0xe1ef0000,
  21483. + &avr32_syntax_table[AVR32_SYNTAX_BRHS2],
  21484. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21485. + {
  21486. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21487. + },
  21488. + },
  21489. + {
  21490. + AVR32_OPC_BRCS2, 4, 0xe0830000, 0xe1ef0000,
  21491. + &avr32_syntax_table[AVR32_SYNTAX_BRLO2],
  21492. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21493. + {
  21494. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21495. + },
  21496. + },
  21497. + {
  21498. + AVR32_OPC_BRGE2, 4, 0xe0840000, 0xe1ef0000,
  21499. + &avr32_syntax_table[AVR32_SYNTAX_BRGE2],
  21500. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21501. + {
  21502. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21503. + },
  21504. + },
  21505. + {
  21506. + AVR32_OPC_BRLT2, 4, 0xe0850000, 0xe1ef0000,
  21507. + &avr32_syntax_table[AVR32_SYNTAX_BRLT2],
  21508. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21509. + {
  21510. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21511. + },
  21512. + },
  21513. + {
  21514. + AVR32_OPC_BRMI2, 4, 0xe0860000, 0xe1ef0000,
  21515. + &avr32_syntax_table[AVR32_SYNTAX_BRMI2],
  21516. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21517. + {
  21518. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21519. + },
  21520. + },
  21521. + {
  21522. + AVR32_OPC_BRPL2, 4, 0xe0870000, 0xe1ef0000,
  21523. + &avr32_syntax_table[AVR32_SYNTAX_BRPL2],
  21524. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21525. + {
  21526. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21527. + },
  21528. + },
  21529. + {
  21530. + AVR32_OPC_BRLS, 4, 0xe0880000, 0xe1ef0000,
  21531. + &avr32_syntax_table[AVR32_SYNTAX_BRLS],
  21532. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21533. + {
  21534. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21535. + },
  21536. + },
  21537. + {
  21538. + AVR32_OPC_BRGT, 4, 0xe0890000, 0xe1ef0000,
  21539. + &avr32_syntax_table[AVR32_SYNTAX_BRGT],
  21540. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21541. + {
  21542. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21543. + },
  21544. + },
  21545. + {
  21546. + AVR32_OPC_BRLE, 4, 0xe08a0000, 0xe1ef0000,
  21547. + &avr32_syntax_table[AVR32_SYNTAX_BRLE],
  21548. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21549. + {
  21550. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21551. + },
  21552. + },
  21553. + {
  21554. + AVR32_OPC_BRHI, 4, 0xe08b0000, 0xe1ef0000,
  21555. + &avr32_syntax_table[AVR32_SYNTAX_BRHI],
  21556. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21557. + {
  21558. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21559. + },
  21560. + },
  21561. + {
  21562. + AVR32_OPC_BRVS, 4, 0xe08c0000, 0xe1ef0000,
  21563. + &avr32_syntax_table[AVR32_SYNTAX_BRVS],
  21564. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21565. + {
  21566. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21567. + },
  21568. + },
  21569. + {
  21570. + AVR32_OPC_BRVC, 4, 0xe08d0000, 0xe1ef0000,
  21571. + &avr32_syntax_table[AVR32_SYNTAX_BRVC],
  21572. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21573. + {
  21574. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21575. + },
  21576. + },
  21577. + {
  21578. + AVR32_OPC_BRQS, 4, 0xe08e0000, 0xe1ef0000,
  21579. + &avr32_syntax_table[AVR32_SYNTAX_BRQS],
  21580. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21581. + {
  21582. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21583. + },
  21584. + },
  21585. + {
  21586. + AVR32_OPC_BRAL, 4, 0xe08f0000, 0xe1ef0000,
  21587. + &avr32_syntax_table[AVR32_SYNTAX_BRAL],
  21588. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  21589. + {
  21590. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21591. + },
  21592. + },
  21593. + {
  21594. + AVR32_OPC_BREAKPOINT, 2, 0xd6730000, 0xffff0000,
  21595. + &avr32_syntax_table[AVR32_SYNTAX_BREAKPOINT],
  21596. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  21597. + },
  21598. + {
  21599. + AVR32_OPC_BREV, 2, 0x5c900000, 0xfff00000,
  21600. + &avr32_syntax_table[AVR32_SYNTAX_BREV],
  21601. + BFD_RELOC_UNUSED, 1, -1,
  21602. + {
  21603. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21604. + },
  21605. + },
  21606. + {
  21607. + AVR32_OPC_BST, 4, 0xefb00000, 0xfff0ffe0,
  21608. + &avr32_syntax_table[AVR32_SYNTAX_BST],
  21609. + BFD_RELOC_UNUSED, 2, -1,
  21610. + {
  21611. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21612. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  21613. + },
  21614. + },
  21615. + {
  21616. + AVR32_OPC_CACHE, 4, 0xf4100000, 0xfff00000,
  21617. + &avr32_syntax_table[AVR32_SYNTAX_CACHE],
  21618. + BFD_RELOC_UNUSED, 3, -1,
  21619. + {
  21620. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21621. + &avr32_ifield_table[AVR32_IFIELD_K11],
  21622. + &avr32_ifield_table[AVR32_IFIELD_CACHEOP],
  21623. + },
  21624. + },
  21625. + {
  21626. + AVR32_OPC_CASTS_B, 2, 0x5c600000, 0xfff00000,
  21627. + &avr32_syntax_table[AVR32_SYNTAX_CASTS_B],
  21628. + BFD_RELOC_UNUSED, 1, -1,
  21629. + {
  21630. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21631. + },
  21632. + },
  21633. + {
  21634. + AVR32_OPC_CASTS_H, 2, 0x5c800000, 0xfff00000,
  21635. + &avr32_syntax_table[AVR32_SYNTAX_CASTS_H],
  21636. + BFD_RELOC_UNUSED, 1, -1,
  21637. + {
  21638. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21639. + },
  21640. + },
  21641. + {
  21642. + AVR32_OPC_CASTU_B, 2, 0x5c500000, 0xfff00000,
  21643. + &avr32_syntax_table[AVR32_SYNTAX_CASTU_B],
  21644. + BFD_RELOC_UNUSED, 1, -1,
  21645. + {
  21646. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21647. + },
  21648. + },
  21649. + {
  21650. + AVR32_OPC_CASTU_H, 2, 0x5c700000, 0xfff00000,
  21651. + &avr32_syntax_table[AVR32_SYNTAX_CASTU_H],
  21652. + BFD_RELOC_UNUSED, 1, -1,
  21653. + {
  21654. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21655. + },
  21656. + },
  21657. + {
  21658. + AVR32_OPC_CBR, 2, 0xa1c00000, 0xe1e00000,
  21659. + &avr32_syntax_table[AVR32_SYNTAX_CBR],
  21660. + BFD_RELOC_UNUSED, 2, -1,
  21661. + {
  21662. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21663. + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
  21664. + },
  21665. + },
  21666. + {
  21667. + AVR32_OPC_CLZ, 4, 0xe0001200, 0xe1f0ffff,
  21668. + &avr32_syntax_table[AVR32_SYNTAX_CLZ],
  21669. + BFD_RELOC_UNUSED, 2, -1,
  21670. + {
  21671. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21672. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21673. + },
  21674. + },
  21675. + {
  21676. + AVR32_OPC_COM, 2, 0x5cd00000, 0xfff00000,
  21677. + &avr32_syntax_table[AVR32_SYNTAX_COM],
  21678. + BFD_RELOC_UNUSED, 1, -1,
  21679. + {
  21680. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21681. + },
  21682. + },
  21683. + {
  21684. + AVR32_OPC_COP, 4, 0xe1a00000, 0xf9f00000,
  21685. + &avr32_syntax_table[AVR32_SYNTAX_COP],
  21686. + BFD_RELOC_UNUSED, 5, -1,
  21687. + {
  21688. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  21689. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  21690. + &avr32_ifield_table[AVR32_IFIELD_CRX],
  21691. + &avr32_ifield_table[AVR32_IFIELD_CRY],
  21692. + &avr32_ifield_table[AVR32_IFIELD_CPOP],
  21693. + },
  21694. + },
  21695. + {
  21696. + AVR32_OPC_CP_B, 4, 0xe0001800, 0xe1f0ffff,
  21697. + &avr32_syntax_table[AVR32_SYNTAX_CP_B],
  21698. + BFD_RELOC_UNUSED, 2, -1,
  21699. + {
  21700. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21701. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21702. + },
  21703. + },
  21704. + {
  21705. + AVR32_OPC_CP_H, 4, 0xe0001900, 0xe1f0ffff,
  21706. + &avr32_syntax_table[AVR32_SYNTAX_CP_H],
  21707. + BFD_RELOC_UNUSED, 2, -1,
  21708. + {
  21709. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21710. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21711. + },
  21712. + },
  21713. + {
  21714. + AVR32_OPC_CP_W1, 2, 0x00300000, 0xe1f00000,
  21715. + &avr32_syntax_table[AVR32_SYNTAX_CP_W1],
  21716. + BFD_RELOC_UNUSED, 2, -1,
  21717. + {
  21718. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21719. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21720. + },
  21721. + },
  21722. + {
  21723. + AVR32_OPC_CP_W2, 2, 0x58000000, 0xfc000000,
  21724. + &avr32_syntax_table[AVR32_SYNTAX_CP_W2],
  21725. + BFD_RELOC_AVR32_6S, 2, 1,
  21726. + {
  21727. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21728. + &avr32_ifield_table[AVR32_IFIELD_K6],
  21729. + },
  21730. + },
  21731. + {
  21732. + AVR32_OPC_CP_W3, 4, 0xe0400000, 0xe1e00000,
  21733. + &avr32_syntax_table[AVR32_SYNTAX_CP_W3],
  21734. + BFD_RELOC_AVR32_21S, 2, 1,
  21735. + {
  21736. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21737. + &avr32_ifield_table[AVR32_IFIELD_K21],
  21738. + },
  21739. + },
  21740. + {
  21741. + AVR32_OPC_CPC1, 4, 0xe0001300, 0xe1f0ffff,
  21742. + &avr32_syntax_table[AVR32_SYNTAX_CPC1],
  21743. + BFD_RELOC_UNUSED, 2, -1,
  21744. + {
  21745. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21746. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21747. + },
  21748. + },
  21749. + {
  21750. + AVR32_OPC_CPC2, 2, 0x5c200000, 0xfff00000,
  21751. + &avr32_syntax_table[AVR32_SYNTAX_CPC2],
  21752. + BFD_RELOC_UNUSED, 1, -1,
  21753. + {
  21754. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21755. + },
  21756. + },
  21757. + {
  21758. + AVR32_OPC_CSRF, 2, 0xd4030000, 0xfe0f0000,
  21759. + &avr32_syntax_table[AVR32_SYNTAX_CSRF],
  21760. + BFD_RELOC_UNUSED, 1, -1,
  21761. + {
  21762. + &avr32_ifield_table[AVR32_IFIELD_K5C],
  21763. + },
  21764. + },
  21765. + {
  21766. + AVR32_OPC_CSRFCZ, 2, 0xd0030000, 0xfe0f0000,
  21767. + &avr32_syntax_table[AVR32_SYNTAX_CSRFCZ],
  21768. + BFD_RELOC_UNUSED, 1, -1,
  21769. + {
  21770. + &avr32_ifield_table[AVR32_IFIELD_K5C],
  21771. + },
  21772. + },
  21773. + {
  21774. + AVR32_OPC_DIVS, 4, 0xe0000c00, 0xe1f0ffc0,
  21775. + &avr32_syntax_table[AVR32_SYNTAX_DIVS],
  21776. + BFD_RELOC_UNUSED, 3, -1,
  21777. + {
  21778. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21779. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21780. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21781. + },
  21782. + },
  21783. + {
  21784. + AVR32_OPC_DIVU, 4, 0xe0000d00, 0xe1f0ffc0,
  21785. + &avr32_syntax_table[AVR32_SYNTAX_DIVU],
  21786. + BFD_RELOC_UNUSED, 3, -1,
  21787. + {
  21788. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21789. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21790. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21791. + },
  21792. + },
  21793. + {
  21794. + AVR32_OPC_EOR1, 2, 0x00500000, 0xe1f00000,
  21795. + &avr32_syntax_table[AVR32_SYNTAX_EOR1],
  21796. + BFD_RELOC_UNUSED, 2, -1,
  21797. + {
  21798. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21799. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21800. + },
  21801. + },
  21802. + {
  21803. + AVR32_OPC_EOR2, 4, 0xe1e02000, 0xe1f0fe00,
  21804. + &avr32_syntax_table[AVR32_SYNTAX_EOR2],
  21805. + BFD_RELOC_UNUSED, 4, -1,
  21806. + {
  21807. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21808. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21809. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21810. + &avr32_ifield_table[AVR32_IFIELD_K5E2],
  21811. + }
  21812. + },
  21813. + {
  21814. + AVR32_OPC_EOR3, 4, 0xe1e02200, 0xe1f0fe00,
  21815. + &avr32_syntax_table[AVR32_SYNTAX_EOR3],
  21816. + BFD_RELOC_UNUSED, 4, -1,
  21817. + {
  21818. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21819. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21820. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21821. + &avr32_ifield_table[AVR32_IFIELD_K5E2],
  21822. + }
  21823. + },
  21824. + {
  21825. + AVR32_OPC_EORL, 4, 0xec100000, 0xfff00000,
  21826. + &avr32_syntax_table[AVR32_SYNTAX_EORL],
  21827. + BFD_RELOC_AVR32_16U, 2, 1,
  21828. + {
  21829. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21830. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21831. + },
  21832. + },
  21833. + {
  21834. + AVR32_OPC_EORH, 4, 0xee100000, 0xfff00000,
  21835. + &avr32_syntax_table[AVR32_SYNTAX_EORH],
  21836. + BFD_RELOC_AVR32_16U, 2, 1,
  21837. + {
  21838. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21839. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21840. + },
  21841. + },
  21842. + {
  21843. + AVR32_OPC_FRS, 2, 0xd7430000, 0xffff0000,
  21844. + &avr32_syntax_table[AVR32_SYNTAX_FRS],
  21845. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  21846. + },
  21847. + {
  21848. + AVR32_OPC_ICALL, 2, 0x5d100000, 0xfff00000,
  21849. + &avr32_syntax_table[AVR32_SYNTAX_ICALL],
  21850. + BFD_RELOC_UNUSED, 1, -1,
  21851. + {
  21852. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21853. + },
  21854. + },
  21855. + {
  21856. + AVR32_OPC_INCJOSP, 2, 0xd6830000, 0xff8f0000,
  21857. + &avr32_syntax_table[AVR32_SYNTAX_INCJOSP],
  21858. + BFD_RELOC_UNUSED, 1, -1,
  21859. + {
  21860. + &avr32_ifield_table[AVR32_IFIELD_K3],
  21861. + },
  21862. + },
  21863. + {
  21864. + AVR32_OPC_LD_D1, 2, 0xa1010000, 0xe1f10000,
  21865. + &avr32_syntax_table[AVR32_SYNTAX_LD_D1],
  21866. + BFD_RELOC_UNUSED, 2, -1,
  21867. + {
  21868. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  21869. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21870. + },
  21871. + },
  21872. + {
  21873. + AVR32_OPC_LD_D2, 2, 0xa1100000, 0xe1f10000,
  21874. + &avr32_syntax_table[AVR32_SYNTAX_LD_D2],
  21875. + BFD_RELOC_UNUSED, 2, -1,
  21876. + {
  21877. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  21878. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21879. + },
  21880. + },
  21881. + {
  21882. + AVR32_OPC_LD_D3, 2, 0xa1000000, 0xe1f10000,
  21883. + &avr32_syntax_table[AVR32_SYNTAX_LD_D3],
  21884. + BFD_RELOC_UNUSED, 2, -1,
  21885. + {
  21886. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  21887. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21888. + },
  21889. + },
  21890. + {
  21891. + AVR32_OPC_LD_D5, 4, 0xe0000200, 0xe1f0ffc1,
  21892. + &avr32_syntax_table[AVR32_SYNTAX_LD_D5],
  21893. + BFD_RELOC_UNUSED, 4, -1,
  21894. + {
  21895. + &avr32_ifield_table[AVR32_IFIELD_RD_DW],
  21896. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21897. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21898. + &avr32_ifield_table[AVR32_IFIELD_K2],
  21899. + },
  21900. + },
  21901. + {
  21902. + AVR32_OPC_LD_D4, 4, 0xe0e00000, 0xe1f10000,
  21903. + &avr32_syntax_table[AVR32_SYNTAX_LD_D4],
  21904. + BFD_RELOC_AVR32_16S, 3, 2,
  21905. + {
  21906. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  21907. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21908. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21909. + },
  21910. + },
  21911. + {
  21912. + AVR32_OPC_LD_SB2, 4, 0xe0000600, 0xe1f0ffc0,
  21913. + &avr32_syntax_table[AVR32_SYNTAX_LD_SB2],
  21914. + BFD_RELOC_UNUSED, 4, -1,
  21915. + {
  21916. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21917. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21918. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21919. + &avr32_ifield_table[AVR32_IFIELD_K2],
  21920. + },
  21921. + },
  21922. + {
  21923. + AVR32_OPC_LD_SB1, 4, 0xe1200000, 0xe1f00000,
  21924. + &avr32_syntax_table[AVR32_SYNTAX_LD_SB1],
  21925. + BFD_RELOC_AVR32_16S, 3, -1,
  21926. + {
  21927. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21928. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21929. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21930. + },
  21931. + },
  21932. + {
  21933. + AVR32_OPC_LD_UB1, 2, 0x01300000, 0xe1f00000,
  21934. + &avr32_syntax_table[AVR32_SYNTAX_LD_UB1],
  21935. + BFD_RELOC_UNUSED, 2, -1,
  21936. + {
  21937. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21938. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21939. + },
  21940. + },
  21941. + {
  21942. + AVR32_OPC_LD_UB2, 2, 0x01700000, 0xe1f00000,
  21943. + &avr32_syntax_table[AVR32_SYNTAX_LD_UB2],
  21944. + BFD_RELOC_UNUSED, 2, -1,
  21945. + {
  21946. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21947. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21948. + },
  21949. + },
  21950. + {
  21951. + AVR32_OPC_LD_UB5, 4, 0xe0000700, 0xe1f0ffc0,
  21952. + &avr32_syntax_table[AVR32_SYNTAX_LD_UB5],
  21953. + BFD_RELOC_UNUSED, 4, -1,
  21954. + {
  21955. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  21956. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21957. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21958. + &avr32_ifield_table[AVR32_IFIELD_K2],
  21959. + },
  21960. + },
  21961. + {
  21962. + AVR32_OPC_LD_UB3, 2, 0x01800000, 0xe1800000,
  21963. + &avr32_syntax_table[AVR32_SYNTAX_LD_UB3],
  21964. + BFD_RELOC_AVR32_3U, 3, 2,
  21965. + {
  21966. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21967. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21968. + &avr32_ifield_table[AVR32_IFIELD_K3],
  21969. + },
  21970. + },
  21971. + {
  21972. + AVR32_OPC_LD_UB4, 4, 0xe1300000, 0xe1f00000,
  21973. + &avr32_syntax_table[AVR32_SYNTAX_LD_UB4],
  21974. + BFD_RELOC_AVR32_16S, 3, 2,
  21975. + {
  21976. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21977. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21978. + &avr32_ifield_table[AVR32_IFIELD_K16],
  21979. + },
  21980. + },
  21981. + {
  21982. + AVR32_OPC_LD_SH1, 2, 0x01100000, 0xe1f00000,
  21983. + &avr32_syntax_table[AVR32_SYNTAX_LD_SH1],
  21984. + BFD_RELOC_UNUSED, 2, -1,
  21985. + {
  21986. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21987. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21988. + },
  21989. + },
  21990. + {
  21991. + AVR32_OPC_LD_SH2, 2, 0x01500000, 0xe1f00000,
  21992. + &avr32_syntax_table[AVR32_SYNTAX_LD_SH2],
  21993. + BFD_RELOC_UNUSED, 2, -1,
  21994. + {
  21995. + &avr32_ifield_table[AVR32_IFIELD_RY],
  21996. + &avr32_ifield_table[AVR32_IFIELD_RX],
  21997. + },
  21998. + },
  21999. + {
  22000. + AVR32_OPC_LD_SH5, 4, 0xe0000400, 0xe1f0ffc0,
  22001. + &avr32_syntax_table[AVR32_SYNTAX_LD_SH5],
  22002. + BFD_RELOC_UNUSED, 4, -1,
  22003. + {
  22004. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22005. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22006. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22007. + &avr32_ifield_table[AVR32_IFIELD_K2],
  22008. + },
  22009. + },
  22010. + {
  22011. + AVR32_OPC_LD_SH3, 2, 0x80000000, 0xe1800000,
  22012. + &avr32_syntax_table[AVR32_SYNTAX_LD_SH3],
  22013. + BFD_RELOC_AVR32_4UH, 3, 2,
  22014. + {
  22015. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22016. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22017. + &avr32_ifield_table[AVR32_IFIELD_K3],
  22018. + },
  22019. + },
  22020. + {
  22021. + AVR32_OPC_LD_SH4, 4, 0xe1000000, 0xe1f00000,
  22022. + &avr32_syntax_table[AVR32_SYNTAX_LD_SH4],
  22023. + BFD_RELOC_AVR32_16S, 3, 2,
  22024. + {
  22025. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22026. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22027. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22028. + },
  22029. + },
  22030. + {
  22031. + AVR32_OPC_LD_UH1, 2, 0x01200000, 0xe1f00000,
  22032. + &avr32_syntax_table[AVR32_SYNTAX_LD_UH1],
  22033. + BFD_RELOC_UNUSED, 2, -1,
  22034. + {
  22035. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22036. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22037. + },
  22038. + },
  22039. + {
  22040. + AVR32_OPC_LD_UH2, 2, 0x01600000, 0xe1f00000,
  22041. + &avr32_syntax_table[AVR32_SYNTAX_LD_UH2],
  22042. + BFD_RELOC_UNUSED, 2, -1,
  22043. + {
  22044. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22045. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22046. + },
  22047. + },
  22048. + {
  22049. + AVR32_OPC_LD_UH5, 4, 0xe0000500, 0xe1f0ffc0,
  22050. + &avr32_syntax_table[AVR32_SYNTAX_LD_UH5],
  22051. + BFD_RELOC_UNUSED, 4, -1,
  22052. + {
  22053. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22054. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22055. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22056. + &avr32_ifield_table[AVR32_IFIELD_K2],
  22057. + },
  22058. + },
  22059. + {
  22060. + AVR32_OPC_LD_UH3, 2, 0x80800000, 0xe1800000,
  22061. + &avr32_syntax_table[AVR32_SYNTAX_LD_UH3],
  22062. + BFD_RELOC_AVR32_4UH, 3, 2,
  22063. + {
  22064. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22065. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22066. + &avr32_ifield_table[AVR32_IFIELD_K3],
  22067. + },
  22068. + },
  22069. + {
  22070. + AVR32_OPC_LD_UH4, 4, 0xe1100000, 0xe1f00000,
  22071. + &avr32_syntax_table[AVR32_SYNTAX_LD_UH4],
  22072. + BFD_RELOC_AVR32_16S, 3, 2,
  22073. + {
  22074. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22075. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22076. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22077. + },
  22078. + },
  22079. + {
  22080. + AVR32_OPC_LD_W1, 2, 0x01000000, 0xe1f00000,
  22081. + &avr32_syntax_table[AVR32_SYNTAX_LD_W1],
  22082. + BFD_RELOC_UNUSED, 2, -1,
  22083. + {
  22084. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22085. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22086. + },
  22087. + },
  22088. + {
  22089. + AVR32_OPC_LD_W2, 2, 0x01400000, 0xe1f00000,
  22090. + &avr32_syntax_table[AVR32_SYNTAX_LD_W2],
  22091. + BFD_RELOC_UNUSED, 2, -1,
  22092. + {
  22093. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22094. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22095. + },
  22096. + },
  22097. + {
  22098. + AVR32_OPC_LD_W5, 4, 0xe0000300, 0xe1f0ffc0,
  22099. + &avr32_syntax_table[AVR32_SYNTAX_LD_W5],
  22100. + BFD_RELOC_UNUSED, 4, -1,
  22101. + {
  22102. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22103. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22104. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22105. + &avr32_ifield_table[AVR32_IFIELD_K2],
  22106. + },
  22107. + },
  22108. + {
  22109. + AVR32_OPC_LD_W6, 4, 0xe0000f80, 0xe1f0ffc0,
  22110. + &avr32_syntax_table[AVR32_SYNTAX_LD_W6],
  22111. + BFD_RELOC_UNUSED, 4, -1,
  22112. + {
  22113. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22114. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22115. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22116. + &avr32_ifield_table[AVR32_IFIELD_K2],
  22117. + },
  22118. + },
  22119. + {
  22120. + AVR32_OPC_LD_W3, 2, 0x60000000, 0xe0000000,
  22121. + &avr32_syntax_table[AVR32_SYNTAX_LD_W3],
  22122. + BFD_RELOC_AVR32_7UW, 3, 2,
  22123. + {
  22124. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22125. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22126. + &avr32_ifield_table[AVR32_IFIELD_K5C],
  22127. + },
  22128. + },
  22129. + {
  22130. + AVR32_OPC_LD_W4, 4, 0xe0f00000, 0xe1f00000,
  22131. + &avr32_syntax_table[AVR32_SYNTAX_LD_W4],
  22132. + BFD_RELOC_AVR32_16S, 3, 2,
  22133. + {
  22134. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22135. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22136. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22137. + },
  22138. + },
  22139. + {
  22140. + AVR32_OPC_LDC_D1, 4, 0xe9a01000, 0xfff01100,
  22141. + &avr32_syntax_table[AVR32_SYNTAX_LDC_D1],
  22142. + BFD_RELOC_AVR32_10UW, 4, 3,
  22143. + {
  22144. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22145. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  22146. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22147. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22148. + },
  22149. + },
  22150. + {
  22151. + AVR32_OPC_LDC_D2, 4, 0xefa00050, 0xfff011ff,
  22152. + &avr32_syntax_table[AVR32_SYNTAX_LDC_D2],
  22153. + BFD_RELOC_UNUSED, 3, -1,
  22154. + {
  22155. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22156. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  22157. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22158. + },
  22159. + },
  22160. + {
  22161. + AVR32_OPC_LDC_D3, 4, 0xefa01040, 0xfff011c0,
  22162. + &avr32_syntax_table[AVR32_SYNTAX_LDC_D3],
  22163. + BFD_RELOC_UNUSED, 5, -1,
  22164. + {
  22165. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22166. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  22167. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22168. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22169. + &avr32_ifield_table[AVR32_IFIELD_K2],
  22170. + },
  22171. + },
  22172. + {
  22173. + AVR32_OPC_LDC_W1, 4, 0xe9a00000, 0xfff01000,
  22174. + &avr32_syntax_table[AVR32_SYNTAX_LDC_W1],
  22175. + BFD_RELOC_AVR32_10UW, 4, 3,
  22176. + {
  22177. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22178. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  22179. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22180. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22181. + },
  22182. + },
  22183. + {
  22184. + AVR32_OPC_LDC_W2, 4, 0xefa00040, 0xfff010ff,
  22185. + &avr32_syntax_table[AVR32_SYNTAX_LDC_W2],
  22186. + BFD_RELOC_UNUSED, 3, -1,
  22187. + {
  22188. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22189. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  22190. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22191. + },
  22192. + },
  22193. + {
  22194. + AVR32_OPC_LDC_W3, 4, 0xefa01000, 0xfff010c0,
  22195. + &avr32_syntax_table[AVR32_SYNTAX_LDC_W3],
  22196. + BFD_RELOC_UNUSED, 5, -1,
  22197. + {
  22198. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22199. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  22200. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22201. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22202. + &avr32_ifield_table[AVR32_IFIELD_K2],
  22203. + },
  22204. + },
  22205. + {
  22206. + AVR32_OPC_LDC0_D, 4, 0xf3a00000, 0xfff00100,
  22207. + &avr32_syntax_table[AVR32_SYNTAX_LDC0_D],
  22208. + BFD_RELOC_AVR32_14UW, 3, 2,
  22209. + {
  22210. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  22211. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22212. + &avr32_ifield_table[AVR32_IFIELD_K12CP],
  22213. + },
  22214. + },
  22215. + {
  22216. + AVR32_OPC_LDC0_W, 4, 0xf1a00000, 0xfff00000,
  22217. + &avr32_syntax_table[AVR32_SYNTAX_LDC0_W],
  22218. + BFD_RELOC_AVR32_14UW, 3, 2,
  22219. + {
  22220. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  22221. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22222. + &avr32_ifield_table[AVR32_IFIELD_K12CP],
  22223. + },
  22224. + },
  22225. + {
  22226. + AVR32_OPC_LDCM_D, 4, 0xeda00400, 0xfff01f00,
  22227. + &avr32_syntax_table[AVR32_SYNTAX_LDCM_D],
  22228. + BFD_RELOC_UNUSED, 3, -1,
  22229. + {
  22230. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22231. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22232. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22233. + },
  22234. + },
  22235. + {
  22236. + AVR32_OPC_LDCM_D_PU, 4, 0xeda01400, 0xfff01f00,
  22237. + &avr32_syntax_table[AVR32_SYNTAX_LDCM_D_PU],
  22238. + BFD_RELOC_UNUSED, 3, -1,
  22239. + {
  22240. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22241. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22242. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22243. + },
  22244. + },
  22245. + {
  22246. + AVR32_OPC_LDCM_W, 4, 0xeda00000, 0xfff01e00,
  22247. + &avr32_syntax_table[AVR32_SYNTAX_LDCM_W],
  22248. + BFD_RELOC_UNUSED, 4, -1,
  22249. + {
  22250. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22251. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22252. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22253. + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
  22254. + },
  22255. + },
  22256. + {
  22257. + AVR32_OPC_LDCM_W_PU, 4, 0xeda01000, 0xfff01e00,
  22258. + &avr32_syntax_table[AVR32_SYNTAX_LDCM_W_PU],
  22259. + BFD_RELOC_UNUSED, 4, -1,
  22260. + {
  22261. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  22262. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22263. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22264. + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
  22265. + },
  22266. + },
  22267. + {
  22268. + AVR32_OPC_LDDPC, 2, 0x48000000, 0xf8000000,
  22269. + &avr32_syntax_table[AVR32_SYNTAX_LDDPC],
  22270. + BFD_RELOC_AVR32_9UW_PCREL, 2, 1,
  22271. + {
  22272. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22273. + &avr32_ifield_table[AVR32_IFIELD_K7C],
  22274. + },
  22275. + },
  22276. + {
  22277. + AVR32_OPC_LDDPC_EXT, 4, 0xfef00000, 0xfff00000,
  22278. + &avr32_syntax_table[AVR32_SYNTAX_LDDPC_EXT],
  22279. + BFD_RELOC_AVR32_16B_PCREL, 2, 1,
  22280. + {
  22281. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22282. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22283. + },
  22284. + },
  22285. + {
  22286. + AVR32_OPC_LDDSP, 2, 0x40000000, 0xf8000000,
  22287. + &avr32_syntax_table[AVR32_SYNTAX_LDDSP],
  22288. + BFD_RELOC_UNUSED, 2, -1,
  22289. + {
  22290. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22291. + &avr32_ifield_table[AVR32_IFIELD_K7C],
  22292. + },
  22293. + },
  22294. + {
  22295. + AVR32_OPC_LDINS_B, 4, 0xe1d04000, 0xe1f0c000,
  22296. + &avr32_syntax_table[AVR32_SYNTAX_LDINS_B],
  22297. + BFD_RELOC_UNUSED, 4, -1,
  22298. + {
  22299. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22300. + &avr32_ifield_table[AVR32_IFIELD_PART2_K12],
  22301. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22302. + &avr32_ifield_table[AVR32_IFIELD_K12],
  22303. + },
  22304. + },
  22305. + {
  22306. + AVR32_OPC_LDINS_H, 4, 0xe1d00000, 0xe1f0e000,
  22307. + &avr32_syntax_table[AVR32_SYNTAX_LDINS_H],
  22308. + BFD_RELOC_UNUSED, 4, -1,
  22309. + {
  22310. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22311. + &avr32_ifield_table[AVR32_IFIELD_PART1_K12],
  22312. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22313. + &avr32_ifield_table[AVR32_IFIELD_K12],
  22314. + },
  22315. + },
  22316. + {
  22317. + AVR32_OPC_LDM, 4, 0xe1c00000, 0xfdf00000,
  22318. + &avr32_syntax_table[AVR32_SYNTAX_LDM],
  22319. + BFD_RELOC_UNUSED, 3, -1,
  22320. + {
  22321. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22322. + &avr32_ifield_table[AVR32_IFIELD_W],
  22323. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22324. + },
  22325. + },
  22326. + {
  22327. + AVR32_OPC_LDMTS, 4, 0xe5c00000, 0xfff00000,
  22328. + &avr32_syntax_table[AVR32_SYNTAX_LDMTS],
  22329. + BFD_RELOC_UNUSED, 2, -1,
  22330. + {
  22331. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22332. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22333. + },
  22334. + },
  22335. + {
  22336. + AVR32_OPC_LDMTS_PU, 4, 0xe7c00000, 0xfff00000,
  22337. + &avr32_syntax_table[AVR32_SYNTAX_LDMTS_PU],
  22338. + BFD_RELOC_UNUSED, 2, -1,
  22339. + {
  22340. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22341. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22342. + },
  22343. + },
  22344. + {
  22345. + AVR32_OPC_LDSWP_SH, 4, 0xe1d02000, 0xe1f0f000,
  22346. + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_SH],
  22347. + BFD_RELOC_UNUSED, 3, -1,
  22348. + {
  22349. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22350. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22351. + &avr32_ifield_table[AVR32_IFIELD_K12],
  22352. + },
  22353. + },
  22354. + {
  22355. + AVR32_OPC_LDSWP_UH, 4, 0xe1d03000, 0xe1f0f000,
  22356. + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_UH],
  22357. + BFD_RELOC_UNUSED, 3, -1,
  22358. + {
  22359. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22360. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22361. + &avr32_ifield_table[AVR32_IFIELD_K12],
  22362. + },
  22363. + },
  22364. + {
  22365. + AVR32_OPC_LDSWP_W, 4, 0xe1d08000, 0xe1f0f000,
  22366. + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_W],
  22367. + BFD_RELOC_UNUSED, 3, -1,
  22368. + {
  22369. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22370. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22371. + &avr32_ifield_table[AVR32_IFIELD_K12],
  22372. + },
  22373. + },
  22374. + {
  22375. + AVR32_OPC_LSL1, 4, 0xe0000940, 0xe1f0fff0,
  22376. + &avr32_syntax_table[AVR32_SYNTAX_LSL1],
  22377. + BFD_RELOC_UNUSED, 3, -1,
  22378. + {
  22379. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22380. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22381. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22382. + },
  22383. + },
  22384. + {
  22385. + AVR32_OPC_LSL3, 4, 0xe0001500, 0xe1f0ffe0,
  22386. + &avr32_syntax_table[AVR32_SYNTAX_LSL3],
  22387. + BFD_RELOC_UNUSED, 3, -1,
  22388. + {
  22389. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22390. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22391. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  22392. + },
  22393. + },
  22394. + {
  22395. + AVR32_OPC_LSL2, 2, 0xa1600000, 0xe1e00000,
  22396. + &avr32_syntax_table[AVR32_SYNTAX_LSL2],
  22397. + BFD_RELOC_UNUSED, 2, -1,
  22398. + {
  22399. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22400. + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
  22401. + },
  22402. + },
  22403. + {
  22404. + AVR32_OPC_LSR1, 4, 0xe0000a40, 0xe1f0fff0,
  22405. + &avr32_syntax_table[AVR32_SYNTAX_LSR1],
  22406. + BFD_RELOC_UNUSED, 3, -1,
  22407. + {
  22408. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22409. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22410. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22411. + },
  22412. + },
  22413. + {
  22414. + AVR32_OPC_LSR3, 4, 0xe0001600, 0xe1f0ffe0,
  22415. + &avr32_syntax_table[AVR32_SYNTAX_LSR3],
  22416. + BFD_RELOC_UNUSED, 3, -1,
  22417. + {
  22418. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22419. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22420. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  22421. + },
  22422. + },
  22423. + {
  22424. + AVR32_OPC_LSR2, 2, 0xa1800000, 0xe1e00000,
  22425. + &avr32_syntax_table[AVR32_SYNTAX_LSR2],
  22426. + BFD_RELOC_UNUSED, 2, -1,
  22427. + {
  22428. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22429. + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
  22430. + },
  22431. + },
  22432. + {
  22433. + AVR32_OPC_MAC, 4, 0xe0000340, 0xe1f0fff0,
  22434. + &avr32_syntax_table[AVR32_SYNTAX_MAC],
  22435. + BFD_RELOC_UNUSED, 3, -1,
  22436. + {
  22437. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22438. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22439. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22440. + },
  22441. + },
  22442. + {
  22443. + AVR32_OPC_MACHH_D, 4, 0xe0000580, 0xe1f0ffc1,
  22444. + &avr32_syntax_table[AVR32_SYNTAX_MACHH_D],
  22445. + BFD_RELOC_UNUSED, 5, -1,
  22446. + {
  22447. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22448. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22449. + &avr32_ifield_table[AVR32_IFIELD_X],
  22450. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22451. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22452. + },
  22453. + },
  22454. + {
  22455. + AVR32_OPC_MACHH_W, 4, 0xe0000480, 0xe1f0ffc0,
  22456. + &avr32_syntax_table[AVR32_SYNTAX_MACHH_W],
  22457. + BFD_RELOC_UNUSED, 5, -1,
  22458. + {
  22459. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22460. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22461. + &avr32_ifield_table[AVR32_IFIELD_X],
  22462. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22463. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22464. + },
  22465. + },
  22466. + {
  22467. + AVR32_OPC_MACS_D, 4, 0xe0000540, 0xe1f0fff1,
  22468. + &avr32_syntax_table[AVR32_SYNTAX_MACS_D],
  22469. + BFD_RELOC_UNUSED, 3, -1,
  22470. + {
  22471. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22472. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22473. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22474. + },
  22475. + },
  22476. + {
  22477. + AVR32_OPC_MACSATHH_W, 4, 0xe0000680, 0xe1f0ffc0,
  22478. + &avr32_syntax_table[AVR32_SYNTAX_MACSATHH_W],
  22479. + BFD_RELOC_UNUSED, 5, -1,
  22480. + {
  22481. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22482. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22483. + &avr32_ifield_table[AVR32_IFIELD_X],
  22484. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22485. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22486. + },
  22487. + },
  22488. + {
  22489. + AVR32_OPC_MACUD, 4, 0xe0000740, 0xe1f0fff1,
  22490. + &avr32_syntax_table[AVR32_SYNTAX_MACUD],
  22491. + BFD_RELOC_UNUSED, 3, -1,
  22492. + {
  22493. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22494. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22495. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22496. + },
  22497. + },
  22498. + {
  22499. + AVR32_OPC_MACWH_D, 4, 0xe0000c80, 0xe1f0ffe1,
  22500. + &avr32_syntax_table[AVR32_SYNTAX_MACWH_D],
  22501. + BFD_RELOC_UNUSED, 4, -1,
  22502. + {
  22503. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22504. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22505. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22506. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22507. + },
  22508. + },
  22509. + {
  22510. + AVR32_OPC_MAX, 4, 0xe0000c40, 0xe1f0fff0,
  22511. + &avr32_syntax_table[AVR32_SYNTAX_MAX],
  22512. + BFD_RELOC_UNUSED, 3, -1,
  22513. + {
  22514. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22515. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22516. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22517. + },
  22518. + },
  22519. + {
  22520. + AVR32_OPC_MCALL, 4, 0xf0100000, 0xfff00000,
  22521. + &avr32_syntax_table[AVR32_SYNTAX_MCALL],
  22522. + BFD_RELOC_AVR32_18W_PCREL, 2, 1,
  22523. + {
  22524. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22525. + &avr32_ifield_table[AVR32_IFIELD_K16],
  22526. + },
  22527. + },
  22528. + {
  22529. + AVR32_OPC_MFDR, 4, 0xe5b00000, 0xfff0ff00,
  22530. + &avr32_syntax_table[AVR32_SYNTAX_MFDR],
  22531. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22532. + {
  22533. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22534. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22535. + },
  22536. + },
  22537. + {
  22538. + AVR32_OPC_MFSR, 4, 0xe1b00000, 0xfff0ff00,
  22539. + &avr32_syntax_table[AVR32_SYNTAX_MFSR],
  22540. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22541. + {
  22542. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22543. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22544. + },
  22545. + },
  22546. + {
  22547. + AVR32_OPC_MIN, 4, 0xe0000d40, 0xe1f0fff0,
  22548. + &avr32_syntax_table[AVR32_SYNTAX_MIN],
  22549. + BFD_RELOC_UNUSED, 3, -1,
  22550. + {
  22551. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22552. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22553. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22554. + },
  22555. + },
  22556. + {
  22557. + AVR32_OPC_MOV3, 2, 0x00900000, 0xe1f00000,
  22558. + &avr32_syntax_table[AVR32_SYNTAX_MOV3],
  22559. + BFD_RELOC_NONE, 2, -1,
  22560. + {
  22561. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22562. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22563. + },
  22564. + },
  22565. + {
  22566. + AVR32_OPC_MOV1, 2, 0x30000000, 0xf0000000,
  22567. + &avr32_syntax_table[AVR32_SYNTAX_MOV1],
  22568. + BFD_RELOC_AVR32_8S, 2, 1,
  22569. + {
  22570. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22571. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  22572. + },
  22573. + },
  22574. + {
  22575. + AVR32_OPC_MOV2, 4, 0xe0600000, 0xe1e00000,
  22576. + &avr32_syntax_table[AVR32_SYNTAX_MOV2],
  22577. + BFD_RELOC_AVR32_21S, 2, 1,
  22578. + {
  22579. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22580. + &avr32_ifield_table[AVR32_IFIELD_K21],
  22581. + },
  22582. + },
  22583. + {
  22584. + AVR32_OPC_MOVEQ1, 4, 0xe0001700, 0xe1f0ffff,
  22585. + &avr32_syntax_table[AVR32_SYNTAX_MOVEQ1],
  22586. + BFD_RELOC_UNUSED, 2, -1,
  22587. + {
  22588. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22589. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22590. + },
  22591. + },
  22592. + {
  22593. + AVR32_OPC_MOVNE1, 4, 0xe0001710, 0xe1f0ffff,
  22594. + &avr32_syntax_table[AVR32_SYNTAX_MOVNE1],
  22595. + BFD_RELOC_UNUSED, 2, -1,
  22596. + {
  22597. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22598. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22599. + },
  22600. + },
  22601. + {
  22602. + AVR32_OPC_MOVCC1, 4, 0xe0001720, 0xe1f0ffff,
  22603. + &avr32_syntax_table[AVR32_SYNTAX_MOVHS1],
  22604. + BFD_RELOC_UNUSED, 2, -1,
  22605. + {
  22606. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22607. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22608. + },
  22609. + },
  22610. + {
  22611. + AVR32_OPC_MOVCS1, 4, 0xe0001730, 0xe1f0ffff,
  22612. + &avr32_syntax_table[AVR32_SYNTAX_MOVLO1],
  22613. + BFD_RELOC_UNUSED, 2, -1,
  22614. + {
  22615. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22616. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22617. + },
  22618. + },
  22619. + {
  22620. + AVR32_OPC_MOVGE1, 4, 0xe0001740, 0xe1f0ffff,
  22621. + &avr32_syntax_table[AVR32_SYNTAX_MOVGE1],
  22622. + BFD_RELOC_UNUSED, 2, -1,
  22623. + {
  22624. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22625. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22626. + },
  22627. + },
  22628. + {
  22629. + AVR32_OPC_MOVLT1, 4, 0xe0001750, 0xe1f0ffff,
  22630. + &avr32_syntax_table[AVR32_SYNTAX_MOVLT1],
  22631. + BFD_RELOC_UNUSED, 2, -1,
  22632. + {
  22633. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22634. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22635. + },
  22636. + },
  22637. + {
  22638. + AVR32_OPC_MOVMI1, 4, 0xe0001760, 0xe1f0ffff,
  22639. + &avr32_syntax_table[AVR32_SYNTAX_MOVMI1],
  22640. + BFD_RELOC_UNUSED, 2, -1,
  22641. + {
  22642. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22643. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22644. + },
  22645. + },
  22646. + {
  22647. + AVR32_OPC_MOVPL1, 4, 0xe0001770, 0xe1f0ffff,
  22648. + &avr32_syntax_table[AVR32_SYNTAX_MOVPL1],
  22649. + BFD_RELOC_UNUSED, 2, -1,
  22650. + {
  22651. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22652. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22653. + },
  22654. + },
  22655. + {
  22656. + AVR32_OPC_MOVLS1, 4, 0xe0001780, 0xe1f0ffff,
  22657. + &avr32_syntax_table[AVR32_SYNTAX_MOVLS1],
  22658. + BFD_RELOC_UNUSED, 2, -1,
  22659. + {
  22660. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22661. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22662. + },
  22663. + },
  22664. + {
  22665. + AVR32_OPC_MOVGT1, 4, 0xe0001790, 0xe1f0ffff,
  22666. + &avr32_syntax_table[AVR32_SYNTAX_MOVGT1],
  22667. + BFD_RELOC_UNUSED, 2, -1,
  22668. + {
  22669. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22670. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22671. + },
  22672. + },
  22673. + {
  22674. + AVR32_OPC_MOVLE1, 4, 0xe00017a0, 0xe1f0ffff,
  22675. + &avr32_syntax_table[AVR32_SYNTAX_MOVLE1],
  22676. + BFD_RELOC_UNUSED, 2, -1,
  22677. + {
  22678. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22679. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22680. + },
  22681. + },
  22682. + {
  22683. + AVR32_OPC_MOVHI1, 4, 0xe00017b0, 0xe1f0ffff,
  22684. + &avr32_syntax_table[AVR32_SYNTAX_MOVHI1],
  22685. + BFD_RELOC_UNUSED, 2, -1,
  22686. + {
  22687. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22688. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22689. + },
  22690. + },
  22691. + {
  22692. + AVR32_OPC_MOVVS1, 4, 0xe00017c0, 0xe1f0ffff,
  22693. + &avr32_syntax_table[AVR32_SYNTAX_MOVVS1],
  22694. + BFD_RELOC_UNUSED, 2, -1,
  22695. + {
  22696. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22697. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22698. + },
  22699. + },
  22700. + {
  22701. + AVR32_OPC_MOVVC1, 4, 0xe00017d0, 0xe1f0ffff,
  22702. + &avr32_syntax_table[AVR32_SYNTAX_MOVVC1],
  22703. + BFD_RELOC_UNUSED, 2, -1,
  22704. + {
  22705. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22706. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22707. + },
  22708. + },
  22709. + {
  22710. + AVR32_OPC_MOVQS1, 4, 0xe00017e0, 0xe1f0ffff,
  22711. + &avr32_syntax_table[AVR32_SYNTAX_MOVQS1],
  22712. + BFD_RELOC_UNUSED, 2, -1,
  22713. + {
  22714. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22715. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22716. + },
  22717. + },
  22718. + {
  22719. + AVR32_OPC_MOVAL1, 4, 0xe00017f0, 0xe1f0ffff,
  22720. + &avr32_syntax_table[AVR32_SYNTAX_MOVAL1],
  22721. + BFD_RELOC_UNUSED, 2, -1,
  22722. + {
  22723. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22724. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22725. + },
  22726. + },
  22727. + {
  22728. + AVR32_OPC_MOVEQ2, 4, 0xf9b00000, 0xfff0ff00,
  22729. + &avr32_syntax_table[AVR32_SYNTAX_MOVEQ2],
  22730. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22731. + {
  22732. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22733. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22734. + },
  22735. + },
  22736. + {
  22737. + AVR32_OPC_MOVNE2, 4, 0xf9b00100, 0xfff0ff00,
  22738. + &avr32_syntax_table[AVR32_SYNTAX_MOVNE2],
  22739. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22740. + {
  22741. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22742. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22743. + },
  22744. + },
  22745. + {
  22746. + AVR32_OPC_MOVCC2, 4, 0xf9b00200, 0xfff0ff00,
  22747. + &avr32_syntax_table[AVR32_SYNTAX_MOVHS2],
  22748. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22749. + {
  22750. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22751. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22752. + },
  22753. + },
  22754. + {
  22755. + AVR32_OPC_MOVCS2, 4, 0xf9b00300, 0xfff0ff00,
  22756. + &avr32_syntax_table[AVR32_SYNTAX_MOVLO2],
  22757. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22758. + {
  22759. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22760. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22761. + },
  22762. + },
  22763. + {
  22764. + AVR32_OPC_MOVGE2, 4, 0xf9b00400, 0xfff0ff00,
  22765. + &avr32_syntax_table[AVR32_SYNTAX_MOVGE2],
  22766. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22767. + {
  22768. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22769. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22770. + },
  22771. + },
  22772. + {
  22773. + AVR32_OPC_MOVLT2, 4, 0xf9b00500, 0xfff0ff00,
  22774. + &avr32_syntax_table[AVR32_SYNTAX_MOVLT2],
  22775. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22776. + {
  22777. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22778. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22779. + },
  22780. + },
  22781. + {
  22782. + AVR32_OPC_MOVMI2, 4, 0xf9b00600, 0xfff0ff00,
  22783. + &avr32_syntax_table[AVR32_SYNTAX_MOVMI2],
  22784. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22785. + {
  22786. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22787. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22788. + },
  22789. + },
  22790. + {
  22791. + AVR32_OPC_MOVPL2, 4, 0xf9b00700, 0xfff0ff00,
  22792. + &avr32_syntax_table[AVR32_SYNTAX_MOVPL2],
  22793. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22794. + {
  22795. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22796. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22797. + },
  22798. + },
  22799. + {
  22800. + AVR32_OPC_MOVLS2, 4, 0xf9b00800, 0xfff0ff00,
  22801. + &avr32_syntax_table[AVR32_SYNTAX_MOVLS2],
  22802. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22803. + {
  22804. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22805. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22806. + },
  22807. + },
  22808. + {
  22809. + AVR32_OPC_MOVGT2, 4, 0xf9b00900, 0xfff0ff00,
  22810. + &avr32_syntax_table[AVR32_SYNTAX_MOVGT2],
  22811. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22812. + {
  22813. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22814. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22815. + },
  22816. + },
  22817. + {
  22818. + AVR32_OPC_MOVLE2, 4, 0xf9b00a00, 0xfff0ff00,
  22819. + &avr32_syntax_table[AVR32_SYNTAX_MOVLE2],
  22820. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22821. + {
  22822. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22823. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22824. + },
  22825. + },
  22826. + {
  22827. + AVR32_OPC_MOVHI2, 4, 0xf9b00b00, 0xfff0ff00,
  22828. + &avr32_syntax_table[AVR32_SYNTAX_MOVHI2],
  22829. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22830. + {
  22831. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22832. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22833. + },
  22834. + },
  22835. + {
  22836. + AVR32_OPC_MOVVS2, 4, 0xf9b00c00, 0xfff0ff00,
  22837. + &avr32_syntax_table[AVR32_SYNTAX_MOVVS2],
  22838. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22839. + {
  22840. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22841. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22842. + },
  22843. + },
  22844. + {
  22845. + AVR32_OPC_MOVVC2, 4, 0xf9b00d00, 0xfff0ff00,
  22846. + &avr32_syntax_table[AVR32_SYNTAX_MOVVC2],
  22847. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22848. + {
  22849. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22850. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22851. + },
  22852. + },
  22853. + {
  22854. + AVR32_OPC_MOVQS2, 4, 0xf9b00e00, 0xfff0ff00,
  22855. + &avr32_syntax_table[AVR32_SYNTAX_MOVQS2],
  22856. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22857. + {
  22858. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22859. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22860. + },
  22861. + },
  22862. + {
  22863. + AVR32_OPC_MOVAL2, 4, 0xf9b00f00, 0xfff0ff00,
  22864. + &avr32_syntax_table[AVR32_SYNTAX_MOVAL2],
  22865. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  22866. + {
  22867. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22868. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22869. + },
  22870. + },
  22871. + {
  22872. + AVR32_OPC_MTDR, 4, 0xe7b00000, 0xfff0ff00,
  22873. + &avr32_syntax_table[AVR32_SYNTAX_MTDR],
  22874. + BFD_RELOC_AVR32_8S_EXT, 2, 0,
  22875. + {
  22876. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22877. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22878. + },
  22879. + },
  22880. + {
  22881. + AVR32_OPC_MTSR, 4, 0xe3b00000, 0xfff0ff00,
  22882. + &avr32_syntax_table[AVR32_SYNTAX_MTSR],
  22883. + BFD_RELOC_AVR32_8S_EXT, 2, 0,
  22884. + {
  22885. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22886. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22887. + },
  22888. + },
  22889. + {
  22890. + AVR32_OPC_MUL1, 2, 0xa1300000, 0xe1f00000,
  22891. + &avr32_syntax_table[AVR32_SYNTAX_MUL1],
  22892. + BFD_RELOC_UNUSED, 2, -1,
  22893. + {
  22894. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22895. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22896. + },
  22897. + },
  22898. + {
  22899. + AVR32_OPC_MUL2, 4, 0xe0000240, 0xe1f0fff0,
  22900. + &avr32_syntax_table[AVR32_SYNTAX_MUL2],
  22901. + BFD_RELOC_UNUSED, 3, -1,
  22902. + {
  22903. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22904. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22905. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22906. + },
  22907. + },
  22908. + {
  22909. + AVR32_OPC_MUL3, 4, 0xe0001000, 0xe1f0ff00,
  22910. + &avr32_syntax_table[AVR32_SYNTAX_MUL3],
  22911. + BFD_RELOC_AVR32_8S_EXT, 3, 2,
  22912. + {
  22913. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22914. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22915. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  22916. + },
  22917. + },
  22918. + {
  22919. + AVR32_OPC_MULHH_W, 4, 0xe0000780, 0xe1f0ffc0,
  22920. + &avr32_syntax_table[AVR32_SYNTAX_MULHH_W],
  22921. + BFD_RELOC_UNUSED, 5, -1,
  22922. + {
  22923. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22924. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22925. + &avr32_ifield_table[AVR32_IFIELD_X],
  22926. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22927. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22928. + },
  22929. + },
  22930. + {
  22931. + AVR32_OPC_MULNHH_W, 4, 0xe0000180, 0xe1f0ffc0,
  22932. + &avr32_syntax_table[AVR32_SYNTAX_MULNHH_W],
  22933. + BFD_RELOC_UNUSED, 5, -1,
  22934. + {
  22935. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22936. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22937. + &avr32_ifield_table[AVR32_IFIELD_X],
  22938. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22939. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22940. + },
  22941. + },
  22942. + {
  22943. + AVR32_OPC_MULNWH_D, 4, 0xe0000280, 0xe1f0ffe1,
  22944. + &avr32_syntax_table[AVR32_SYNTAX_MULNWH_D],
  22945. + BFD_RELOC_UNUSED, 4, -1,
  22946. + {
  22947. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22948. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22949. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22950. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22951. + },
  22952. + },
  22953. + {
  22954. + AVR32_OPC_MULSD, 4, 0xe0000440, 0xe1f0fff0,
  22955. + &avr32_syntax_table[AVR32_SYNTAX_MULSD],
  22956. + BFD_RELOC_UNUSED, 3, -1,
  22957. + {
  22958. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22959. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22960. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22961. + },
  22962. + },
  22963. + {
  22964. + AVR32_OPC_MULSATHH_H, 4, 0xe0000880, 0xe1f0ffc0,
  22965. + &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_H],
  22966. + BFD_RELOC_UNUSED, 5, -1,
  22967. + {
  22968. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22969. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22970. + &avr32_ifield_table[AVR32_IFIELD_X],
  22971. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22972. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22973. + },
  22974. + },
  22975. + {
  22976. + AVR32_OPC_MULSATHH_W, 4, 0xe0000980, 0xe1f0ffc0,
  22977. + &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_W],
  22978. + BFD_RELOC_UNUSED, 5, -1,
  22979. + {
  22980. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22981. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22982. + &avr32_ifield_table[AVR32_IFIELD_X],
  22983. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22984. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22985. + },
  22986. + },
  22987. + {
  22988. + AVR32_OPC_MULSATRNDHH_H, 4, 0xe0000a80, 0xe1f0ffc0,
  22989. + &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDHH_H],
  22990. + BFD_RELOC_UNUSED, 5, -1,
  22991. + {
  22992. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  22993. + &avr32_ifield_table[AVR32_IFIELD_RX],
  22994. + &avr32_ifield_table[AVR32_IFIELD_X],
  22995. + &avr32_ifield_table[AVR32_IFIELD_RY],
  22996. + &avr32_ifield_table[AVR32_IFIELD_Y],
  22997. + },
  22998. + },
  22999. + {
  23000. + AVR32_OPC_MULSATRNDWH_W, 4, 0xe0000b80, 0xe1f0ffe0,
  23001. + &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDWH_W],
  23002. + BFD_RELOC_UNUSED, 4, -1,
  23003. + {
  23004. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23005. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23006. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23007. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23008. + },
  23009. + },
  23010. + {
  23011. + AVR32_OPC_MULSATWH_W, 4, 0xe0000e80, 0xe1f0ffe0,
  23012. + &avr32_syntax_table[AVR32_SYNTAX_MULSATWH_W],
  23013. + BFD_RELOC_UNUSED, 4, -1,
  23014. + {
  23015. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23016. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23017. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23018. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23019. + },
  23020. + },
  23021. + {
  23022. + AVR32_OPC_MULU_D, 4, 0xe0000640, 0xe1f0fff1,
  23023. + &avr32_syntax_table[AVR32_SYNTAX_MULU_D],
  23024. + BFD_RELOC_UNUSED, 3, -1,
  23025. + {
  23026. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23027. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23028. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23029. + },
  23030. + },
  23031. + {
  23032. + AVR32_OPC_MULWH_D, 4, 0xe0000d80, 0xe1f0ffe1,
  23033. + &avr32_syntax_table[AVR32_SYNTAX_MULWH_D],
  23034. + BFD_RELOC_UNUSED, 4, -1,
  23035. + {
  23036. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23037. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23038. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23039. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23040. + },
  23041. + },
  23042. + {
  23043. + AVR32_OPC_MUSFR, 2, 0x5d300000, 0xfff00000,
  23044. + &avr32_syntax_table[AVR32_SYNTAX_MUSFR],
  23045. + BFD_RELOC_UNUSED, 1, -1,
  23046. + {
  23047. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23048. + }
  23049. + },
  23050. + {
  23051. + AVR32_OPC_MUSTR, 2, 0x5d200000, 0xfff00000,
  23052. + &avr32_syntax_table[AVR32_SYNTAX_MUSTR],
  23053. + BFD_RELOC_UNUSED, 1, -1,
  23054. + {
  23055. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23056. + }
  23057. + },
  23058. + {
  23059. + AVR32_OPC_MVCR_D, 4, 0xefa00010, 0xfff111ff,
  23060. + &avr32_syntax_table[AVR32_SYNTAX_MVCR_D],
  23061. + BFD_RELOC_UNUSED, 3, -1,
  23062. + {
  23063. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  23064. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  23065. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  23066. + },
  23067. + },
  23068. + {
  23069. + AVR32_OPC_MVCR_W, 4, 0xefa00000, 0xfff010ff,
  23070. + &avr32_syntax_table[AVR32_SYNTAX_MVCR_W],
  23071. + BFD_RELOC_UNUSED, 3, -1,
  23072. + {
  23073. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  23074. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23075. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  23076. + },
  23077. + },
  23078. + {
  23079. + AVR32_OPC_MVRC_D, 4, 0xefa00030, 0xfff111ff,
  23080. + &avr32_syntax_table[AVR32_SYNTAX_MVRC_D],
  23081. + BFD_RELOC_UNUSED, 3, -1,
  23082. + {
  23083. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  23084. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  23085. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  23086. + },
  23087. + },
  23088. + {
  23089. + AVR32_OPC_MVRC_W, 4, 0xefa00020, 0xfff010ff,
  23090. + &avr32_syntax_table[AVR32_SYNTAX_MVRC_W],
  23091. + BFD_RELOC_UNUSED, 3, -1,
  23092. + {
  23093. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  23094. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  23095. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23096. + },
  23097. + },
  23098. + {
  23099. + AVR32_OPC_NEG, 2, 0x5c300000, 0xfff00000,
  23100. + &avr32_syntax_table[AVR32_SYNTAX_NEG],
  23101. + BFD_RELOC_UNUSED, 1, -1,
  23102. + {
  23103. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23104. + }
  23105. + },
  23106. + {
  23107. + AVR32_OPC_NOP, 2, 0xd7030000, 0xffff0000,
  23108. + &avr32_syntax_table[AVR32_SYNTAX_NOP],
  23109. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  23110. + },
  23111. + {
  23112. + AVR32_OPC_OR1, 2, 0x00400000, 0xe1f00000,
  23113. + &avr32_syntax_table[AVR32_SYNTAX_OR1],
  23114. + BFD_RELOC_UNUSED, 2, -1,
  23115. + {
  23116. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23117. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23118. + },
  23119. + },
  23120. + {
  23121. + AVR32_OPC_OR2, 4, 0xe1e01000, 0xe1f0fe00,
  23122. + &avr32_syntax_table[AVR32_SYNTAX_OR2],
  23123. + BFD_RELOC_UNUSED, 4, -1,
  23124. + {
  23125. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23126. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23127. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23128. + &avr32_ifield_table[AVR32_IFIELD_K5E2],
  23129. + },
  23130. + },
  23131. + {
  23132. + AVR32_OPC_OR3, 4, 0xe1e01200, 0xe1f0fe00,
  23133. + &avr32_syntax_table[AVR32_SYNTAX_OR3],
  23134. + BFD_RELOC_UNUSED, 4, -1,
  23135. + {
  23136. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23137. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23138. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23139. + &avr32_ifield_table[AVR32_IFIELD_K5E2],
  23140. + },
  23141. + },
  23142. + {
  23143. + AVR32_OPC_ORH, 4, 0xea100000, 0xfff00000,
  23144. + &avr32_syntax_table[AVR32_SYNTAX_ORH],
  23145. + BFD_RELOC_AVR32_16U, 2, 1,
  23146. + {
  23147. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23148. + &avr32_ifield_table[AVR32_IFIELD_K16],
  23149. + },
  23150. + },
  23151. + {
  23152. + AVR32_OPC_ORL, 4, 0xe8100000, 0xfff00000,
  23153. + &avr32_syntax_table[AVR32_SYNTAX_ORL],
  23154. + BFD_RELOC_AVR32_16U, 2, 1,
  23155. + {
  23156. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23157. + &avr32_ifield_table[AVR32_IFIELD_K16],
  23158. + },
  23159. + },
  23160. + {
  23161. + AVR32_OPC_PABS_SB, 4, 0xe00023e0, 0xfff0fff0,
  23162. + &avr32_syntax_table[AVR32_SYNTAX_PABS_SB],
  23163. + BFD_RELOC_UNUSED, 2, -1,
  23164. + {
  23165. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23166. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23167. + },
  23168. + },
  23169. + {
  23170. + AVR32_OPC_PABS_SH, 4, 0xe00023f0, 0xfff0fff0,
  23171. + &avr32_syntax_table[AVR32_SYNTAX_PABS_SH],
  23172. + BFD_RELOC_UNUSED, 2, -1,
  23173. + {
  23174. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23175. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23176. + },
  23177. + },
  23178. + {
  23179. + AVR32_OPC_PACKSH_SB, 4, 0xe00024d0, 0xe1f0fff0,
  23180. + &avr32_syntax_table[AVR32_SYNTAX_PACKSH_SB],
  23181. + BFD_RELOC_UNUSED, 3, -1,
  23182. + {
  23183. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23184. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23185. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23186. + },
  23187. + },
  23188. + {
  23189. + AVR32_OPC_PACKSH_UB, 4, 0xe00024c0, 0xe1f0fff0,
  23190. + &avr32_syntax_table[AVR32_SYNTAX_PACKSH_UB],
  23191. + BFD_RELOC_UNUSED, 3, -1,
  23192. + {
  23193. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23194. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23195. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23196. + },
  23197. + },
  23198. + {
  23199. + AVR32_OPC_PACKW_SH, 4, 0xe0002470, 0xe1f0fff0,
  23200. + &avr32_syntax_table[AVR32_SYNTAX_PACKW_SH],
  23201. + BFD_RELOC_UNUSED, 3, -1,
  23202. + {
  23203. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23204. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23205. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23206. + },
  23207. + },
  23208. + {
  23209. + AVR32_OPC_PADD_B, 4, 0xe0002300, 0xe1f0fff0,
  23210. + &avr32_syntax_table[AVR32_SYNTAX_PADD_B],
  23211. + BFD_RELOC_UNUSED, 3, -1,
  23212. + {
  23213. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23214. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23215. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23216. + },
  23217. + },
  23218. + {
  23219. + AVR32_OPC_PADD_H, 4, 0xe0002000, 0xe1f0fff0,
  23220. + &avr32_syntax_table[AVR32_SYNTAX_PADD_H],
  23221. + BFD_RELOC_UNUSED, 3, -1,
  23222. + {
  23223. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23224. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23225. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23226. + },
  23227. + },
  23228. + {
  23229. + AVR32_OPC_PADDH_SH, 4, 0xe00020c0, 0xe1f0fff0,
  23230. + &avr32_syntax_table[AVR32_SYNTAX_PADDH_SH],
  23231. + BFD_RELOC_UNUSED, 3, -1,
  23232. + {
  23233. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23234. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23235. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23236. + },
  23237. + },
  23238. + {
  23239. + AVR32_OPC_PADDH_UB, 4, 0xe0002360, 0xe1f0fff0,
  23240. + &avr32_syntax_table[AVR32_SYNTAX_PADDH_UB],
  23241. + BFD_RELOC_UNUSED, 3, -1,
  23242. + {
  23243. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23244. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23245. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23246. + },
  23247. + },
  23248. + {
  23249. + AVR32_OPC_PADDS_SB, 4, 0xe0002320, 0xe1f0fff0,
  23250. + &avr32_syntax_table[AVR32_SYNTAX_PADDS_SB],
  23251. + BFD_RELOC_UNUSED, 3, -1,
  23252. + {
  23253. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23254. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23255. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23256. + },
  23257. + },
  23258. + {
  23259. + AVR32_OPC_PADDS_SH, 4, 0xe0002040, 0xe1f0fff0,
  23260. + &avr32_syntax_table[AVR32_SYNTAX_PADDS_SH],
  23261. + BFD_RELOC_UNUSED, 3, -1,
  23262. + {
  23263. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23264. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23265. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23266. + },
  23267. + },
  23268. + {
  23269. + AVR32_OPC_PADDS_UB, 4, 0xe0002340, 0xe1f0fff0,
  23270. + &avr32_syntax_table[AVR32_SYNTAX_PADDS_UB],
  23271. + BFD_RELOC_UNUSED, 3, -1,
  23272. + {
  23273. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23274. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23275. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23276. + },
  23277. + },
  23278. + {
  23279. + AVR32_OPC_PADDS_UH, 4, 0xe0002080, 0xe1f0fff0,
  23280. + &avr32_syntax_table[AVR32_SYNTAX_PADDS_UH],
  23281. + BFD_RELOC_UNUSED, 3, -1,
  23282. + {
  23283. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23284. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23285. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23286. + },
  23287. + },
  23288. + {
  23289. + AVR32_OPC_PADDSUB_H, 4, 0xe0002100, 0xe1f0ffc0,
  23290. + &avr32_syntax_table[AVR32_SYNTAX_PADDSUB_H],
  23291. + BFD_RELOC_UNUSED, 5, -1,
  23292. + {
  23293. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23294. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23295. + &avr32_ifield_table[AVR32_IFIELD_X],
  23296. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23297. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23298. + },
  23299. + },
  23300. + {
  23301. + AVR32_OPC_PADDSUBH_SH, 4, 0xe0002280, 0xe1f0ffc0,
  23302. + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBH_SH],
  23303. + BFD_RELOC_UNUSED, 5, -1,
  23304. + {
  23305. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23306. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23307. + &avr32_ifield_table[AVR32_IFIELD_X],
  23308. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23309. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23310. + },
  23311. + },
  23312. + {
  23313. + AVR32_OPC_PADDSUBS_SH, 4, 0xe0002180, 0xe1f0ffc0,
  23314. + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_SH],
  23315. + BFD_RELOC_UNUSED, 5, -1,
  23316. + {
  23317. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23318. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23319. + &avr32_ifield_table[AVR32_IFIELD_X],
  23320. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23321. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23322. + },
  23323. + },
  23324. + {
  23325. + AVR32_OPC_PADDSUBS_UH, 4, 0xe0002200, 0xe1f0ffc0,
  23326. + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_UH],
  23327. + BFD_RELOC_UNUSED, 5, -1,
  23328. + {
  23329. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23330. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23331. + &avr32_ifield_table[AVR32_IFIELD_X],
  23332. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23333. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23334. + },
  23335. + },
  23336. + {
  23337. + AVR32_OPC_PADDX_H, 4, 0xe0002020, 0xe1f0fff0,
  23338. + &avr32_syntax_table[AVR32_SYNTAX_PADDX_H],
  23339. + BFD_RELOC_UNUSED, 3, -1,
  23340. + {
  23341. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23342. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23343. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23344. + },
  23345. + },
  23346. + {
  23347. + AVR32_OPC_PADDXH_SH, 4, 0xe00020e0, 0xe1f0fff0,
  23348. + &avr32_syntax_table[AVR32_SYNTAX_PADDXH_SH],
  23349. + BFD_RELOC_UNUSED, 3, -1,
  23350. + {
  23351. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23352. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23353. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23354. + },
  23355. + },
  23356. + {
  23357. + AVR32_OPC_PADDXS_SH, 4, 0xe0002060, 0xe1f0fff0,
  23358. + &avr32_syntax_table[AVR32_SYNTAX_PADDXS_SH],
  23359. + BFD_RELOC_UNUSED, 3, -1,
  23360. + {
  23361. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23362. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23363. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23364. + },
  23365. + },
  23366. + {
  23367. + AVR32_OPC_PADDXS_UH, 4, 0xe00020a0, 0xe1f0fff0,
  23368. + &avr32_syntax_table[AVR32_SYNTAX_PADDXS_UH],
  23369. + BFD_RELOC_UNUSED, 3, -1,
  23370. + {
  23371. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23372. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23373. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23374. + },
  23375. + },
  23376. + {
  23377. + AVR32_OPC_PASR_B, 4, 0xe0002410, 0xe1f8fff0,
  23378. + &avr32_syntax_table[AVR32_SYNTAX_PASR_B],
  23379. + BFD_RELOC_UNUSED, 3, -1,
  23380. + {
  23381. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23382. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23383. + &avr32_ifield_table[AVR32_IFIELD_COND3],
  23384. + },
  23385. + },
  23386. + {
  23387. + AVR32_OPC_PASR_H, 4, 0xe0002440, 0xe1f0fff0,
  23388. + &avr32_syntax_table[AVR32_SYNTAX_PASR_H],
  23389. + BFD_RELOC_UNUSED, 3, -1,
  23390. + {
  23391. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23392. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23393. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23394. + },
  23395. + },
  23396. + {
  23397. + AVR32_OPC_PAVG_SH, 4, 0xe00023d0, 0xe1f0fff0,
  23398. + &avr32_syntax_table[AVR32_SYNTAX_PAVG_SH],
  23399. + BFD_RELOC_UNUSED, 3, -1,
  23400. + {
  23401. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23402. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23403. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23404. + },
  23405. + },
  23406. + {
  23407. + AVR32_OPC_PAVG_UB, 4, 0xe00023c0, 0xe1f0fff0,
  23408. + &avr32_syntax_table[AVR32_SYNTAX_PAVG_UB],
  23409. + BFD_RELOC_UNUSED, 3, -1,
  23410. + {
  23411. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23412. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23413. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23414. + },
  23415. + },
  23416. + {
  23417. + AVR32_OPC_PLSL_B, 4, 0xe0002420, 0xe1f8fff0,
  23418. + &avr32_syntax_table[AVR32_SYNTAX_PLSL_B],
  23419. + BFD_RELOC_UNUSED, 3, -1,
  23420. + {
  23421. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23422. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23423. + &avr32_ifield_table[AVR32_IFIELD_COND3],
  23424. + },
  23425. + },
  23426. + {
  23427. + AVR32_OPC_PLSL_H, 4, 0xe0002450, 0xe1f0fff0,
  23428. + &avr32_syntax_table[AVR32_SYNTAX_PLSL_H],
  23429. + BFD_RELOC_UNUSED, 3, -1,
  23430. + {
  23431. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23432. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23433. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23434. + },
  23435. + },
  23436. + {
  23437. + AVR32_OPC_PLSR_B, 4, 0xe0002430, 0xe1f8fff0,
  23438. + &avr32_syntax_table[AVR32_SYNTAX_PLSR_B],
  23439. + BFD_RELOC_UNUSED, 3, -1,
  23440. + {
  23441. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23442. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23443. + &avr32_ifield_table[AVR32_IFIELD_COND3],
  23444. + },
  23445. + },
  23446. + {
  23447. + AVR32_OPC_PLSR_H, 4, 0xe0002460, 0xe1f0fff0,
  23448. + &avr32_syntax_table[AVR32_SYNTAX_PLSR_H],
  23449. + BFD_RELOC_UNUSED, 3, -1,
  23450. + {
  23451. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23452. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23453. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23454. + },
  23455. + },
  23456. + {
  23457. + AVR32_OPC_PMAX_SH, 4, 0xe0002390, 0xe1f0fff0,
  23458. + &avr32_syntax_table[AVR32_SYNTAX_PMAX_SH],
  23459. + BFD_RELOC_UNUSED, 3, -1,
  23460. + {
  23461. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23462. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23463. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23464. + },
  23465. + },
  23466. + {
  23467. + AVR32_OPC_PMAX_UB, 4, 0xe0002380, 0xe1f0fff0,
  23468. + &avr32_syntax_table[AVR32_SYNTAX_PMAX_UB],
  23469. + BFD_RELOC_UNUSED, 3, -1,
  23470. + {
  23471. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23472. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23473. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23474. + },
  23475. + },
  23476. + {
  23477. + AVR32_OPC_PMIN_SH, 4, 0xe00023b0, 0xe1f0fff0,
  23478. + &avr32_syntax_table[AVR32_SYNTAX_PMIN_SH],
  23479. + BFD_RELOC_UNUSED, 3, -1,
  23480. + {
  23481. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23482. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23483. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23484. + },
  23485. + },
  23486. + {
  23487. + AVR32_OPC_PMIN_UB, 4, 0xe00023a0, 0xe1f0fff0,
  23488. + &avr32_syntax_table[AVR32_SYNTAX_PMIN_UB],
  23489. + BFD_RELOC_UNUSED, 3, -1,
  23490. + {
  23491. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23492. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23493. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23494. + },
  23495. + },
  23496. + {
  23497. + AVR32_OPC_POPJC, 2, 0xd7130000, 0xffff0000,
  23498. + &avr32_syntax_table[AVR32_SYNTAX_POPJC],
  23499. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  23500. + },
  23501. + {
  23502. + AVR32_OPC_POPM, 2, 0xd0020000, 0xf0070000,
  23503. + &avr32_syntax_table[AVR32_SYNTAX_POPM],
  23504. + BFD_RELOC_UNUSED, 1, -1,
  23505. + {
  23506. + &avr32_ifield_table[AVR32_IFIELD_POPM],
  23507. + },
  23508. + },
  23509. + {
  23510. + AVR32_OPC_POPM_E, 4, 0xe3cd0000, 0xffff0000,
  23511. + &avr32_syntax_table[AVR32_SYNTAX_POPM_E],
  23512. + BFD_RELOC_UNUSED, 1, -1,
  23513. + {
  23514. + &avr32_ifield_table[AVR32_IFIELD_K16],
  23515. + },
  23516. + },
  23517. + {
  23518. + AVR32_OPC_PREF, 4, 0xf2100000, 0xfff00000,
  23519. + &avr32_syntax_table[AVR32_SYNTAX_PREF],
  23520. + BFD_RELOC_AVR32_16S, 2, -1,
  23521. + {
  23522. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23523. + &avr32_ifield_table[AVR32_IFIELD_K16],
  23524. + },
  23525. + },
  23526. + {
  23527. + AVR32_OPC_PSAD, 4, 0xe0002400, 0xe1f0fff0,
  23528. + &avr32_syntax_table[AVR32_SYNTAX_PSAD],
  23529. + BFD_RELOC_UNUSED, 3, -1,
  23530. + {
  23531. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23532. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23533. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23534. + },
  23535. + },
  23536. + {
  23537. + AVR32_OPC_PSUB_B, 4, 0xe0002310, 0xe1f0fff0,
  23538. + &avr32_syntax_table[AVR32_SYNTAX_PSUB_B],
  23539. + BFD_RELOC_UNUSED, 3, -1,
  23540. + {
  23541. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23542. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23543. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23544. + },
  23545. + },
  23546. + {
  23547. + AVR32_OPC_PSUB_H, 4, 0xe0002010, 0xe1f0fff0,
  23548. + &avr32_syntax_table[AVR32_SYNTAX_PSUB_H],
  23549. + BFD_RELOC_UNUSED, 3, -1,
  23550. + {
  23551. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23552. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23553. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23554. + },
  23555. + },
  23556. + {
  23557. + AVR32_OPC_PSUBADD_H, 4, 0xe0002140, 0xe1f0ffc0,
  23558. + &avr32_syntax_table[AVR32_SYNTAX_PSUBADD_H],
  23559. + BFD_RELOC_UNUSED, 5, -1,
  23560. + {
  23561. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23562. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23563. + &avr32_ifield_table[AVR32_IFIELD_X],
  23564. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23565. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23566. + },
  23567. + },
  23568. + {
  23569. + AVR32_OPC_PSUBADDH_SH, 4, 0xe00022c0, 0xe1f0ffc0,
  23570. + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDH_SH],
  23571. + BFD_RELOC_UNUSED, 5, -1,
  23572. + {
  23573. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23574. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23575. + &avr32_ifield_table[AVR32_IFIELD_X],
  23576. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23577. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23578. + },
  23579. + },
  23580. + {
  23581. + AVR32_OPC_PSUBADDS_SH, 4, 0xe00021c0, 0xe1f0ffc0,
  23582. + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_SH],
  23583. + BFD_RELOC_UNUSED, 5, -1,
  23584. + {
  23585. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23586. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23587. + &avr32_ifield_table[AVR32_IFIELD_X],
  23588. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23589. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23590. + },
  23591. + },
  23592. + {
  23593. + AVR32_OPC_PSUBADDS_UH, 4, 0xe0002240, 0xe1f0ffc0,
  23594. + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_UH],
  23595. + BFD_RELOC_UNUSED, 5, -1,
  23596. + {
  23597. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23598. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23599. + &avr32_ifield_table[AVR32_IFIELD_X],
  23600. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23601. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23602. + },
  23603. + },
  23604. + {
  23605. + AVR32_OPC_PSUBH_SH, 4, 0xe00020d0, 0xe1f0fff0,
  23606. + &avr32_syntax_table[AVR32_SYNTAX_PSUBH_SH],
  23607. + BFD_RELOC_UNUSED, 3, -1,
  23608. + {
  23609. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23610. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23611. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23612. + },
  23613. + },
  23614. + {
  23615. + AVR32_OPC_PSUBH_UB, 4, 0xe0002370, 0xe1f0fff0,
  23616. + &avr32_syntax_table[AVR32_SYNTAX_PSUBH_UB],
  23617. + BFD_RELOC_UNUSED, 3, -1,
  23618. + {
  23619. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23620. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23621. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23622. + },
  23623. + },
  23624. + {
  23625. + AVR32_OPC_PSUBS_SB, 4, 0xe0002330, 0xe1f0fff0,
  23626. + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SB],
  23627. + BFD_RELOC_UNUSED, 3, -1,
  23628. + {
  23629. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23630. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23631. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23632. + },
  23633. + },
  23634. + {
  23635. + AVR32_OPC_PSUBS_SH, 4, 0xe0002050, 0xe1f0fff0,
  23636. + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SH],
  23637. + BFD_RELOC_UNUSED, 3, -1,
  23638. + {
  23639. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23640. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23641. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23642. + },
  23643. + },
  23644. + {
  23645. + AVR32_OPC_PSUBS_UB, 4, 0xe0002350, 0xe1f0fff0,
  23646. + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UB],
  23647. + BFD_RELOC_UNUSED, 3, -1,
  23648. + {
  23649. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23650. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23651. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23652. + },
  23653. + },
  23654. + {
  23655. + AVR32_OPC_PSUBS_UH, 4, 0xe0002090, 0xe1f0fff0,
  23656. + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UH],
  23657. + BFD_RELOC_UNUSED, 3, -1,
  23658. + {
  23659. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23660. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23661. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23662. + },
  23663. + },
  23664. + {
  23665. + AVR32_OPC_PSUBX_H, 4, 0xe0002030, 0xe1f0fff0,
  23666. + &avr32_syntax_table[AVR32_SYNTAX_PSUBX_H],
  23667. + BFD_RELOC_UNUSED, 3, -1,
  23668. + {
  23669. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23670. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23671. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23672. + },
  23673. + },
  23674. + {
  23675. + AVR32_OPC_PSUBXH_SH, 4, 0xe00020f0, 0xe1f0fff0,
  23676. + &avr32_syntax_table[AVR32_SYNTAX_PSUBXH_SH],
  23677. + BFD_RELOC_UNUSED, 3, -1,
  23678. + {
  23679. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23680. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23681. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23682. + },
  23683. + },
  23684. + {
  23685. + AVR32_OPC_PSUBXS_SH, 4, 0xe0002070, 0xe1f0fff0,
  23686. + &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_SH],
  23687. + BFD_RELOC_UNUSED, 3, -1,
  23688. + {
  23689. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23690. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23691. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23692. + },
  23693. + },
  23694. + {
  23695. + AVR32_OPC_PSUBXS_UH, 4, 0xe00020b0, 0xe1f0fff0,
  23696. + &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_UH],
  23697. + BFD_RELOC_UNUSED, 3, -1,
  23698. + {
  23699. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23700. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23701. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23702. + },
  23703. + },
  23704. + {
  23705. + AVR32_OPC_PUNPCKSB_H, 4, 0xe00024a0, 0xe1ffffe0,
  23706. + &avr32_syntax_table[AVR32_SYNTAX_PUNPCKSB_H],
  23707. + BFD_RELOC_UNUSED, 3, -1,
  23708. + {
  23709. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23710. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23711. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23712. + },
  23713. + },
  23714. + {
  23715. + AVR32_OPC_PUNPCKUB_H, 4, 0xe0002480, 0xe1ffffe0,
  23716. + &avr32_syntax_table[AVR32_SYNTAX_PUNPCKUB_H],
  23717. + BFD_RELOC_UNUSED, 3, -1,
  23718. + {
  23719. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23720. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23721. + &avr32_ifield_table[AVR32_IFIELD_Y],
  23722. + },
  23723. + },
  23724. + {
  23725. + AVR32_OPC_PUSHJC, 2, 0xd7230000, 0xffff0000,
  23726. + &avr32_syntax_table[AVR32_SYNTAX_PUSHJC],
  23727. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  23728. + },
  23729. + {
  23730. + AVR32_OPC_PUSHM, 2, 0xd0010000, 0xf00f0000,
  23731. + &avr32_syntax_table[AVR32_SYNTAX_PUSHM],
  23732. + BFD_RELOC_UNUSED, 1, -1,
  23733. + {
  23734. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  23735. + },
  23736. + },
  23737. + {
  23738. + AVR32_OPC_PUSHM_E, 4, 0xebcd0000, 0xffff0000,
  23739. + &avr32_syntax_table[AVR32_SYNTAX_PUSHM_E],
  23740. + BFD_RELOC_UNUSED, 1, -1,
  23741. + {
  23742. + &avr32_ifield_table[AVR32_IFIELD_K16],
  23743. + },
  23744. + },
  23745. + {
  23746. + AVR32_OPC_RCALL1, 2, 0xc00c0000, 0xf00c0000,
  23747. + &avr32_syntax_table[AVR32_SYNTAX_RCALL1],
  23748. + BFD_RELOC_AVR32_11H_PCREL, 1, 0,
  23749. + {
  23750. + &avr32_ifield_table[AVR32_IFIELD_K10],
  23751. + },
  23752. + },
  23753. + {
  23754. + AVR32_OPC_RCALL2, 4, 0xe0a00000, 0xe1ef0000,
  23755. + &avr32_syntax_table[AVR32_SYNTAX_RCALL2],
  23756. + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
  23757. + {
  23758. + &avr32_ifield_table[AVR32_IFIELD_K21],
  23759. + },
  23760. + },
  23761. + {
  23762. + AVR32_OPC_RETEQ, 2, 0x5e000000, 0xfff00000,
  23763. + &avr32_syntax_table[AVR32_SYNTAX_RETEQ],
  23764. + BFD_RELOC_NONE, 1, -1,
  23765. + {
  23766. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23767. + },
  23768. + },
  23769. + {
  23770. + AVR32_OPC_RETNE, 2, 0x5e100000, 0xfff00000,
  23771. + &avr32_syntax_table[AVR32_SYNTAX_RETNE],
  23772. + BFD_RELOC_NONE, 1, -1,
  23773. + {
  23774. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23775. + },
  23776. + },
  23777. + {
  23778. + AVR32_OPC_RETCC, 2, 0x5e200000, 0xfff00000,
  23779. + &avr32_syntax_table[AVR32_SYNTAX_RETHS],
  23780. + BFD_RELOC_NONE, 1, -1,
  23781. + {
  23782. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23783. + },
  23784. + },
  23785. + {
  23786. + AVR32_OPC_RETCS, 2, 0x5e300000, 0xfff00000,
  23787. + &avr32_syntax_table[AVR32_SYNTAX_RETLO],
  23788. + BFD_RELOC_NONE, 1, -1,
  23789. + {
  23790. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23791. + },
  23792. + },
  23793. + {
  23794. + AVR32_OPC_RETGE, 2, 0x5e400000, 0xfff00000,
  23795. + &avr32_syntax_table[AVR32_SYNTAX_RETGE],
  23796. + BFD_RELOC_NONE, 1, -1,
  23797. + {
  23798. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23799. + },
  23800. + },
  23801. + {
  23802. + AVR32_OPC_RETLT, 2, 0x5e500000, 0xfff00000,
  23803. + &avr32_syntax_table[AVR32_SYNTAX_RETLT],
  23804. + BFD_RELOC_NONE, 1, -1,
  23805. + {
  23806. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23807. + },
  23808. + },
  23809. + {
  23810. + AVR32_OPC_RETMI, 2, 0x5e600000, 0xfff00000,
  23811. + &avr32_syntax_table[AVR32_SYNTAX_RETMI],
  23812. + BFD_RELOC_NONE, 1, -1,
  23813. + {
  23814. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23815. + },
  23816. + },
  23817. + {
  23818. + AVR32_OPC_RETPL, 2, 0x5e700000, 0xfff00000,
  23819. + &avr32_syntax_table[AVR32_SYNTAX_RETPL],
  23820. + BFD_RELOC_NONE, 1, -1,
  23821. + {
  23822. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23823. + },
  23824. + },
  23825. + {
  23826. + AVR32_OPC_RETLS, 2, 0x5e800000, 0xfff00000,
  23827. + &avr32_syntax_table[AVR32_SYNTAX_RETLS],
  23828. + BFD_RELOC_NONE, 1, -1,
  23829. + {
  23830. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23831. + },
  23832. + },
  23833. + {
  23834. + AVR32_OPC_RETGT, 2, 0x5e900000, 0xfff00000,
  23835. + &avr32_syntax_table[AVR32_SYNTAX_RETGT],
  23836. + BFD_RELOC_NONE, 1, -1,
  23837. + {
  23838. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23839. + },
  23840. + },
  23841. + {
  23842. + AVR32_OPC_RETLE, 2, 0x5ea00000, 0xfff00000,
  23843. + &avr32_syntax_table[AVR32_SYNTAX_RETLE],
  23844. + BFD_RELOC_NONE, 1, -1,
  23845. + {
  23846. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23847. + },
  23848. + },
  23849. + {
  23850. + AVR32_OPC_RETHI, 2, 0x5eb00000, 0xfff00000,
  23851. + &avr32_syntax_table[AVR32_SYNTAX_RETHI],
  23852. + BFD_RELOC_NONE, 1, -1,
  23853. + {
  23854. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23855. + },
  23856. + },
  23857. + {
  23858. + AVR32_OPC_RETVS, 2, 0x5ec00000, 0xfff00000,
  23859. + &avr32_syntax_table[AVR32_SYNTAX_RETVS],
  23860. + BFD_RELOC_NONE, 1, -1,
  23861. + {
  23862. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23863. + },
  23864. + },
  23865. + {
  23866. + AVR32_OPC_RETVC, 2, 0x5ed00000, 0xfff00000,
  23867. + &avr32_syntax_table[AVR32_SYNTAX_RETVC],
  23868. + BFD_RELOC_NONE, 1, -1,
  23869. + {
  23870. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23871. + },
  23872. + },
  23873. + {
  23874. + AVR32_OPC_RETQS, 2, 0x5ee00000, 0xfff00000,
  23875. + &avr32_syntax_table[AVR32_SYNTAX_RETQS],
  23876. + BFD_RELOC_NONE, 1, -1,
  23877. + {
  23878. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23879. + },
  23880. + },
  23881. + {
  23882. + AVR32_OPC_RETAL, 2, 0x5ef00000, 0xfff00000,
  23883. + &avr32_syntax_table[AVR32_SYNTAX_RETAL],
  23884. + BFD_RELOC_NONE, 1, -1,
  23885. + {
  23886. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23887. + },
  23888. + },
  23889. + {
  23890. + AVR32_OPC_RETD, 2, 0xd6230000, 0xffff0000,
  23891. + &avr32_syntax_table[AVR32_SYNTAX_RETD],
  23892. + BFD_RELOC_NONE, 0, -1, { NULL },
  23893. + },
  23894. + {
  23895. + AVR32_OPC_RETE, 2, 0xd6030000, 0xffff0000,
  23896. + &avr32_syntax_table[AVR32_SYNTAX_RETE],
  23897. + BFD_RELOC_NONE, 0, -1, { NULL },
  23898. + },
  23899. + {
  23900. + AVR32_OPC_RETJ, 2, 0xd6330000, 0xffff0000,
  23901. + &avr32_syntax_table[AVR32_SYNTAX_RETJ],
  23902. + BFD_RELOC_NONE, 0, -1, { NULL },
  23903. + },
  23904. + {
  23905. + AVR32_OPC_RETS, 2, 0xd6130000, 0xffff0000,
  23906. + &avr32_syntax_table[AVR32_SYNTAX_RETS],
  23907. + BFD_RELOC_NONE, 0, -1, { NULL },
  23908. + },
  23909. + {
  23910. + AVR32_OPC_RJMP, 2, 0xc0080000, 0xf00c0000,
  23911. + &avr32_syntax_table[AVR32_SYNTAX_RJMP],
  23912. + BFD_RELOC_AVR32_11H_PCREL, 1, 0,
  23913. + {
  23914. + &avr32_ifield_table[AVR32_IFIELD_K10],
  23915. + },
  23916. + },
  23917. + {
  23918. + AVR32_OPC_ROL, 2, 0x5cf00000, 0xfff00000,
  23919. + &avr32_syntax_table[AVR32_SYNTAX_ROL],
  23920. + BFD_RELOC_UNUSED, 1, -1,
  23921. + {
  23922. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23923. + }
  23924. + },
  23925. + {
  23926. + AVR32_OPC_ROR, 2, 0x5d000000, 0xfff00000,
  23927. + &avr32_syntax_table[AVR32_SYNTAX_ROR],
  23928. + BFD_RELOC_UNUSED, 1, -1,
  23929. + {
  23930. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23931. + }
  23932. + },
  23933. + {
  23934. + AVR32_OPC_RSUB1, 2, 0x00200000, 0xe1f00000,
  23935. + &avr32_syntax_table[AVR32_SYNTAX_RSUB1],
  23936. + BFD_RELOC_UNUSED, 2, -1,
  23937. + {
  23938. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23939. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23940. + },
  23941. + },
  23942. + {
  23943. + AVR32_OPC_RSUB2, 4, 0xe0001100, 0xe1f0ff00,
  23944. + &avr32_syntax_table[AVR32_SYNTAX_RSUB2],
  23945. + BFD_RELOC_AVR32_8S_EXT, 3, 2,
  23946. + {
  23947. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23948. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23949. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  23950. + },
  23951. + },
  23952. + {
  23953. + AVR32_OPC_SATADD_H, 4, 0xe00002c0, 0xe1f0fff0,
  23954. + &avr32_syntax_table[AVR32_SYNTAX_SATADD_H],
  23955. + BFD_RELOC_UNUSED, 3, -1,
  23956. + {
  23957. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23958. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23959. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23960. + },
  23961. + },
  23962. + {
  23963. + AVR32_OPC_SATADD_W, 4, 0xe00000c0, 0xe1f0fff0,
  23964. + &avr32_syntax_table[AVR32_SYNTAX_SATADD_W],
  23965. + BFD_RELOC_UNUSED, 3, -1,
  23966. + {
  23967. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  23968. + &avr32_ifield_table[AVR32_IFIELD_RX],
  23969. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23970. + },
  23971. + },
  23972. + {
  23973. + AVR32_OPC_SATRNDS, 4, 0xf3b00000, 0xfff0fc00,
  23974. + &avr32_syntax_table[AVR32_SYNTAX_SATRNDS],
  23975. + BFD_RELOC_UNUSED, 3, -1,
  23976. + {
  23977. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23978. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  23979. + &avr32_ifield_table[AVR32_IFIELD_S5],
  23980. + },
  23981. + },
  23982. + {
  23983. + AVR32_OPC_SATRNDU, 4, 0xf3b00400, 0xfff0fc00,
  23984. + &avr32_syntax_table[AVR32_SYNTAX_SATRNDU],
  23985. + BFD_RELOC_UNUSED, 3, -1,
  23986. + {
  23987. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23988. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  23989. + &avr32_ifield_table[AVR32_IFIELD_S5],
  23990. + },
  23991. + },
  23992. + {
  23993. + AVR32_OPC_SATS, 4, 0xf1b00000, 0xfff0fc00,
  23994. + &avr32_syntax_table[AVR32_SYNTAX_SATS],
  23995. + BFD_RELOC_UNUSED, 3, -1,
  23996. + {
  23997. + &avr32_ifield_table[AVR32_IFIELD_RY],
  23998. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  23999. + &avr32_ifield_table[AVR32_IFIELD_S5],
  24000. + },
  24001. + },
  24002. + {
  24003. + AVR32_OPC_SATSUB_H, 4, 0xe00003c0, 0xe1f0fff0,
  24004. + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_H],
  24005. + BFD_RELOC_UNUSED, 3, -1,
  24006. + {
  24007. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24008. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24009. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24010. + },
  24011. + },
  24012. + {
  24013. + AVR32_OPC_SATSUB_W1, 4, 0xe00001c0, 0xe1f0fff0,
  24014. + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W1],
  24015. + BFD_RELOC_UNUSED, 3, -1,
  24016. + {
  24017. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24018. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24019. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24020. + },
  24021. + },
  24022. + {
  24023. + AVR32_OPC_SATSUB_W2, 4, 0xe0d00000, 0xe1f00000,
  24024. + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W2],
  24025. + BFD_RELOC_UNUSED, 3, -1,
  24026. + {
  24027. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24028. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24029. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24030. + },
  24031. + },
  24032. + {
  24033. + AVR32_OPC_SATU, 4, 0xf1b00400, 0xfff0fc00,
  24034. + &avr32_syntax_table[AVR32_SYNTAX_SATU],
  24035. + BFD_RELOC_UNUSED, 3, -1,
  24036. + {
  24037. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24038. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  24039. + &avr32_ifield_table[AVR32_IFIELD_S5],
  24040. + },
  24041. + },
  24042. + {
  24043. + AVR32_OPC_SBC, 4, 0xe0000140, 0xe1f0fff0,
  24044. + &avr32_syntax_table[AVR32_SYNTAX_SBC],
  24045. + BFD_RELOC_UNUSED, 3, -1,
  24046. + {
  24047. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24048. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24049. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24050. + },
  24051. + },
  24052. + {
  24053. + AVR32_OPC_SBR, 2, 0xa1a00000, 0xe1e00000,
  24054. + &avr32_syntax_table[AVR32_SYNTAX_SBR],
  24055. + BFD_RELOC_UNUSED, 2, -1,
  24056. + {
  24057. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24058. + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
  24059. + },
  24060. + },
  24061. + {
  24062. + AVR32_OPC_SCALL, 2, 0xd7330000, 0xffff0000,
  24063. + &avr32_syntax_table[AVR32_SYNTAX_SCALL],
  24064. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  24065. + },
  24066. + {
  24067. + AVR32_OPC_SCR, 2, 0x5c100000, 0xfff00000,
  24068. + &avr32_syntax_table[AVR32_SYNTAX_SCR],
  24069. + BFD_RELOC_UNUSED, 1, -1,
  24070. + {
  24071. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24072. + },
  24073. + },
  24074. + {
  24075. + AVR32_OPC_SLEEP, 4, 0xe9b00000, 0xffffff00,
  24076. + &avr32_syntax_table[AVR32_SYNTAX_SLEEP],
  24077. + BFD_RELOC_AVR32_8S_EXT, 1, 0,
  24078. + {
  24079. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24080. + },
  24081. + },
  24082. + {
  24083. + AVR32_OPC_SREQ, 2, 0x5f000000, 0xfff00000,
  24084. + &avr32_syntax_table[AVR32_SYNTAX_SREQ],
  24085. + BFD_RELOC_UNUSED, 1, -1,
  24086. + {
  24087. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24088. + },
  24089. + },
  24090. + {
  24091. + AVR32_OPC_SRNE, 2, 0x5f100000, 0xfff00000,
  24092. + &avr32_syntax_table[AVR32_SYNTAX_SRNE],
  24093. + BFD_RELOC_UNUSED, 1, -1,
  24094. + {
  24095. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24096. + },
  24097. + },
  24098. + {
  24099. + AVR32_OPC_SRCC, 2, 0x5f200000, 0xfff00000,
  24100. + &avr32_syntax_table[AVR32_SYNTAX_SRHS],
  24101. + BFD_RELOC_UNUSED, 1, -1,
  24102. + {
  24103. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24104. + },
  24105. + },
  24106. + {
  24107. + AVR32_OPC_SRCS, 2, 0x5f300000, 0xfff00000,
  24108. + &avr32_syntax_table[AVR32_SYNTAX_SRLO],
  24109. + BFD_RELOC_UNUSED, 1, -1,
  24110. + {
  24111. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24112. + },
  24113. + },
  24114. + {
  24115. + AVR32_OPC_SRGE, 2, 0x5f400000, 0xfff00000,
  24116. + &avr32_syntax_table[AVR32_SYNTAX_SRGE],
  24117. + BFD_RELOC_UNUSED, 1, -1,
  24118. + {
  24119. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24120. + },
  24121. + },
  24122. + {
  24123. + AVR32_OPC_SRLT, 2, 0x5f500000, 0xfff00000,
  24124. + &avr32_syntax_table[AVR32_SYNTAX_SRLT],
  24125. + BFD_RELOC_UNUSED, 1, -1,
  24126. + {
  24127. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24128. + },
  24129. + },
  24130. + {
  24131. + AVR32_OPC_SRMI, 2, 0x5f600000, 0xfff00000,
  24132. + &avr32_syntax_table[AVR32_SYNTAX_SRMI],
  24133. + BFD_RELOC_UNUSED, 1, -1,
  24134. + {
  24135. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24136. + },
  24137. + },
  24138. + {
  24139. + AVR32_OPC_SRPL, 2, 0x5f700000, 0xfff00000,
  24140. + &avr32_syntax_table[AVR32_SYNTAX_SRPL],
  24141. + BFD_RELOC_UNUSED, 1, -1,
  24142. + {
  24143. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24144. + },
  24145. + },
  24146. + {
  24147. + AVR32_OPC_SRLS, 2, 0x5f800000, 0xfff00000,
  24148. + &avr32_syntax_table[AVR32_SYNTAX_SRLS],
  24149. + BFD_RELOC_UNUSED, 1, -1,
  24150. + {
  24151. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24152. + },
  24153. + },
  24154. + {
  24155. + AVR32_OPC_SRGT, 2, 0x5f900000, 0xfff00000,
  24156. + &avr32_syntax_table[AVR32_SYNTAX_SRGT],
  24157. + BFD_RELOC_UNUSED, 1, -1,
  24158. + {
  24159. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24160. + },
  24161. + },
  24162. + {
  24163. + AVR32_OPC_SRLE, 2, 0x5fa00000, 0xfff00000,
  24164. + &avr32_syntax_table[AVR32_SYNTAX_SRLE],
  24165. + BFD_RELOC_UNUSED, 1, -1,
  24166. + {
  24167. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24168. + },
  24169. + },
  24170. + {
  24171. + AVR32_OPC_SRHI, 2, 0x5fb00000, 0xfff00000,
  24172. + &avr32_syntax_table[AVR32_SYNTAX_SRHI],
  24173. + BFD_RELOC_UNUSED, 1, -1,
  24174. + {
  24175. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24176. + },
  24177. + },
  24178. + {
  24179. + AVR32_OPC_SRVS, 2, 0x5fc00000, 0xfff00000,
  24180. + &avr32_syntax_table[AVR32_SYNTAX_SRVS],
  24181. + BFD_RELOC_UNUSED, 1, -1,
  24182. + {
  24183. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24184. + },
  24185. + },
  24186. + {
  24187. + AVR32_OPC_SRVC, 2, 0x5fd00000, 0xfff00000,
  24188. + &avr32_syntax_table[AVR32_SYNTAX_SRVC],
  24189. + BFD_RELOC_UNUSED, 1, -1,
  24190. + {
  24191. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24192. + },
  24193. + },
  24194. + {
  24195. + AVR32_OPC_SRQS, 2, 0x5fe00000, 0xfff00000,
  24196. + &avr32_syntax_table[AVR32_SYNTAX_SRQS],
  24197. + BFD_RELOC_UNUSED, 1, -1,
  24198. + {
  24199. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24200. + },
  24201. + },
  24202. + {
  24203. + AVR32_OPC_SRAL, 2, 0x5ff00000, 0xfff00000,
  24204. + &avr32_syntax_table[AVR32_SYNTAX_SRAL],
  24205. + BFD_RELOC_UNUSED, 1, -1,
  24206. + {
  24207. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24208. + },
  24209. + },
  24210. + {
  24211. + AVR32_OPC_SSRF, 2, 0xd2030000, 0xfe0f0000,
  24212. + &avr32_syntax_table[AVR32_SYNTAX_SSRF],
  24213. + BFD_RELOC_UNUSED, 1, -1,
  24214. + {
  24215. + &avr32_ifield_table[AVR32_IFIELD_K5C],
  24216. + },
  24217. + },
  24218. + {
  24219. + AVR32_OPC_ST_B1, 2, 0x00c00000, 0xe1f00000,
  24220. + &avr32_syntax_table[AVR32_SYNTAX_ST_B1],
  24221. + BFD_RELOC_UNUSED, 2, -1,
  24222. + {
  24223. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24224. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24225. + },
  24226. + },
  24227. + {
  24228. + AVR32_OPC_ST_B2, 2, 0x00f00000, 0xe1f00000,
  24229. + &avr32_syntax_table[AVR32_SYNTAX_ST_B2],
  24230. + BFD_RELOC_UNUSED, 2, -1,
  24231. + {
  24232. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24233. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24234. + },
  24235. + },
  24236. + {
  24237. + AVR32_OPC_ST_B5, 4, 0xe0000b00, 0xe1f0ffc0,
  24238. + &avr32_syntax_table[AVR32_SYNTAX_ST_B5],
  24239. + BFD_RELOC_UNUSED, 4, -1,
  24240. + {
  24241. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24242. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24243. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24244. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24245. + },
  24246. + },
  24247. + {
  24248. + AVR32_OPC_ST_B3, 2, 0xa0800000, 0xe1800000,
  24249. + &avr32_syntax_table[AVR32_SYNTAX_ST_B3],
  24250. + BFD_RELOC_AVR32_3U, 3, 1,
  24251. + {
  24252. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24253. + &avr32_ifield_table[AVR32_IFIELD_K3],
  24254. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24255. + },
  24256. + },
  24257. + {
  24258. + AVR32_OPC_ST_B4, 4, 0xe1600000, 0xe1f00000,
  24259. + &avr32_syntax_table[AVR32_SYNTAX_ST_B4],
  24260. + BFD_RELOC_AVR32_16S, 3, 1,
  24261. + {
  24262. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24263. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24264. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24265. + },
  24266. + },
  24267. + {
  24268. + AVR32_OPC_ST_D1, 2, 0xa1200000, 0xe1f10000,
  24269. + &avr32_syntax_table[AVR32_SYNTAX_ST_D1],
  24270. + BFD_RELOC_UNUSED, 2, -1,
  24271. + {
  24272. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24273. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  24274. + },
  24275. + },
  24276. + {
  24277. + AVR32_OPC_ST_D2, 2, 0xa1210000, 0xe1f10000,
  24278. + &avr32_syntax_table[AVR32_SYNTAX_ST_D2],
  24279. + BFD_RELOC_UNUSED, 2, -1,
  24280. + {
  24281. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24282. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  24283. + },
  24284. + },
  24285. + {
  24286. + AVR32_OPC_ST_D3, 2, 0xa1110000, 0xe1f10000,
  24287. + &avr32_syntax_table[AVR32_SYNTAX_ST_D3],
  24288. + BFD_RELOC_UNUSED, 2, -1,
  24289. + {
  24290. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24291. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  24292. + },
  24293. + },
  24294. + {
  24295. + AVR32_OPC_ST_D5, 4, 0xe0000800, 0xe1f0ffc1,
  24296. + &avr32_syntax_table[AVR32_SYNTAX_ST_D5],
  24297. + BFD_RELOC_UNUSED, 4, -1,
  24298. + {
  24299. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24300. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24301. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24302. + &avr32_ifield_table[AVR32_IFIELD_RD_DW],
  24303. + },
  24304. + },
  24305. + {
  24306. + AVR32_OPC_ST_D4, 4, 0xe0e10000, 0xe1f10000,
  24307. + &avr32_syntax_table[AVR32_SYNTAX_ST_D4],
  24308. + BFD_RELOC_AVR32_16S, 3, 1,
  24309. + {
  24310. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24311. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24312. + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
  24313. + },
  24314. + },
  24315. + {
  24316. + AVR32_OPC_ST_H1, 2, 0x00b00000, 0xe1f00000,
  24317. + &avr32_syntax_table[AVR32_SYNTAX_ST_H1],
  24318. + BFD_RELOC_UNUSED, 2, -1,
  24319. + {
  24320. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24321. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24322. + },
  24323. + },
  24324. + {
  24325. + AVR32_OPC_ST_H2, 2, 0x00e00000, 0xe1f00000,
  24326. + &avr32_syntax_table[AVR32_SYNTAX_ST_H2],
  24327. + BFD_RELOC_UNUSED, 2, -1,
  24328. + {
  24329. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24330. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24331. + },
  24332. + },
  24333. + {
  24334. + AVR32_OPC_ST_H5, 4, 0xe0000a00, 0xe1f0ffc0,
  24335. + &avr32_syntax_table[AVR32_SYNTAX_ST_H5],
  24336. + BFD_RELOC_UNUSED, 4, -1,
  24337. + {
  24338. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24339. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24340. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24341. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24342. + },
  24343. + },
  24344. + {
  24345. + AVR32_OPC_ST_H3, 2, 0xa0000000, 0xe1800000,
  24346. + &avr32_syntax_table[AVR32_SYNTAX_ST_H3],
  24347. + BFD_RELOC_AVR32_4UH, 3, 1,
  24348. + {
  24349. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24350. + &avr32_ifield_table[AVR32_IFIELD_K3],
  24351. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24352. + },
  24353. + },
  24354. + {
  24355. + AVR32_OPC_ST_H4, 4, 0xe1500000, 0xe1f00000,
  24356. + &avr32_syntax_table[AVR32_SYNTAX_ST_H4],
  24357. + BFD_RELOC_AVR32_16S, 3, 1,
  24358. + {
  24359. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24360. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24361. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24362. + },
  24363. + },
  24364. + {
  24365. + AVR32_OPC_ST_W1, 2, 0x00a00000, 0xe1f00000,
  24366. + &avr32_syntax_table[AVR32_SYNTAX_ST_W1],
  24367. + BFD_RELOC_UNUSED, 2, -1,
  24368. + {
  24369. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24370. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24371. + },
  24372. + },
  24373. + {
  24374. + AVR32_OPC_ST_W2, 2, 0x00d00000, 0xe1f00000,
  24375. + &avr32_syntax_table[AVR32_SYNTAX_ST_W2],
  24376. + BFD_RELOC_UNUSED, 2, -1,
  24377. + {
  24378. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24379. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24380. + },
  24381. + },
  24382. + {
  24383. + AVR32_OPC_ST_W5, 4, 0xe0000900, 0xe1f0ffc0,
  24384. + &avr32_syntax_table[AVR32_SYNTAX_ST_W5],
  24385. + BFD_RELOC_UNUSED, 4, -1,
  24386. + {
  24387. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24388. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24389. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24390. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24391. + },
  24392. + },
  24393. + {
  24394. + AVR32_OPC_ST_W3, 2, 0x81000000, 0xe1000000,
  24395. + &avr32_syntax_table[AVR32_SYNTAX_ST_W3],
  24396. + BFD_RELOC_AVR32_6UW, 3, 1,
  24397. + {
  24398. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24399. + &avr32_ifield_table[AVR32_IFIELD_K4],
  24400. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24401. + },
  24402. + },
  24403. + {
  24404. + AVR32_OPC_ST_W4, 4, 0xe1400000, 0xe1f00000,
  24405. + &avr32_syntax_table[AVR32_SYNTAX_ST_W4],
  24406. + BFD_RELOC_AVR32_16S, 3, 1,
  24407. + {
  24408. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24409. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24410. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24411. + },
  24412. + },
  24413. + {
  24414. + AVR32_OPC_STC_D1, 4, 0xeba01000, 0xfff01100,
  24415. + &avr32_syntax_table[AVR32_SYNTAX_STC_D1],
  24416. + BFD_RELOC_AVR32_10UW, 4, 2,
  24417. + {
  24418. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24419. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24420. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24421. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  24422. + },
  24423. + },
  24424. + {
  24425. + AVR32_OPC_STC_D2, 4, 0xefa00070, 0xfff011f0,
  24426. + &avr32_syntax_table[AVR32_SYNTAX_STC_D2],
  24427. + BFD_RELOC_UNUSED, 3, -1,
  24428. + {
  24429. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24430. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24431. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  24432. + },
  24433. + },
  24434. + {
  24435. + AVR32_OPC_STC_D3, 4, 0xefa010c0, 0xfff011c0,
  24436. + &avr32_syntax_table[AVR32_SYNTAX_STC_D3],
  24437. + BFD_RELOC_UNUSED, 5, -1,
  24438. + {
  24439. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24440. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24441. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24442. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24443. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  24444. + },
  24445. + },
  24446. + {
  24447. + AVR32_OPC_STC_W1, 4, 0xeba00000, 0xfff01000,
  24448. + &avr32_syntax_table[AVR32_SYNTAX_STC_W1],
  24449. + BFD_RELOC_AVR32_10UW, 4, 2,
  24450. + {
  24451. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24452. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24453. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24454. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  24455. + },
  24456. + },
  24457. + {
  24458. + AVR32_OPC_STC_W2, 4, 0xefa00060, 0xfff010ff,
  24459. + &avr32_syntax_table[AVR32_SYNTAX_STC_W2],
  24460. + BFD_RELOC_UNUSED, 3, -1,
  24461. + {
  24462. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24463. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24464. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  24465. + },
  24466. + },
  24467. + {
  24468. + AVR32_OPC_STC_W3, 4, 0xefa01080, 0xfff010c0,
  24469. + &avr32_syntax_table[AVR32_SYNTAX_STC_W3],
  24470. + BFD_RELOC_UNUSED, 5, -1,
  24471. + {
  24472. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24473. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24474. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24475. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24476. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  24477. + },
  24478. + },
  24479. + {
  24480. + AVR32_OPC_STC0_D, 4, 0xf7a00000, 0xfff00100,
  24481. + &avr32_syntax_table[AVR32_SYNTAX_STC0_D],
  24482. + BFD_RELOC_AVR32_14UW, 3, 1,
  24483. + {
  24484. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24485. + &avr32_ifield_table[AVR32_IFIELD_K12CP],
  24486. + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
  24487. + },
  24488. + },
  24489. + {
  24490. + AVR32_OPC_STC0_W, 4, 0xf5a00000, 0xfff00000,
  24491. + &avr32_syntax_table[AVR32_SYNTAX_STC0_W],
  24492. + BFD_RELOC_AVR32_14UW, 3, 1,
  24493. + {
  24494. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24495. + &avr32_ifield_table[AVR32_IFIELD_K12CP],
  24496. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  24497. + },
  24498. + },
  24499. + {
  24500. + AVR32_OPC_STCM_D, 4, 0xeda00500, 0xfff01f00,
  24501. + &avr32_syntax_table[AVR32_SYNTAX_STCM_D],
  24502. + BFD_RELOC_UNUSED, 3, -1,
  24503. + {
  24504. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24505. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24506. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24507. + },
  24508. + },
  24509. + {
  24510. + AVR32_OPC_STCM_D_PU, 4, 0xeda01500, 0xfff01f00,
  24511. + &avr32_syntax_table[AVR32_SYNTAX_STCM_D_PU],
  24512. + BFD_RELOC_UNUSED, 3, -1,
  24513. + {
  24514. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24515. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24516. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24517. + },
  24518. + },
  24519. + {
  24520. + AVR32_OPC_STCM_W, 4, 0xeda00200, 0xfff01e00,
  24521. + &avr32_syntax_table[AVR32_SYNTAX_STCM_W],
  24522. + BFD_RELOC_UNUSED, 4, -1,
  24523. + {
  24524. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24525. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24526. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24527. + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
  24528. + },
  24529. + },
  24530. + {
  24531. + AVR32_OPC_STCM_W_PU, 4, 0xeda01200, 0xfff01e00,
  24532. + &avr32_syntax_table[AVR32_SYNTAX_STCM_W_PU],
  24533. + BFD_RELOC_UNUSED, 4, -1,
  24534. + {
  24535. + &avr32_ifield_table[AVR32_IFIELD_CPNO],
  24536. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24537. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24538. + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
  24539. + },
  24540. + },
  24541. + {
  24542. + AVR32_OPC_STCOND, 4, 0xe1700000, 0xe1f00000,
  24543. + &avr32_syntax_table[AVR32_SYNTAX_STCOND],
  24544. + BFD_RELOC_UNUSED, 3, -1,
  24545. + {
  24546. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24547. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24548. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24549. + },
  24550. + },
  24551. + {
  24552. + AVR32_OPC_STDSP, 2, 0x50000000, 0xf8000000,
  24553. + &avr32_syntax_table[AVR32_SYNTAX_STDSP],
  24554. + BFD_RELOC_UNUSED, 2, -1,
  24555. + {
  24556. + &avr32_ifield_table[AVR32_IFIELD_K7C],
  24557. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24558. + },
  24559. + },
  24560. + {
  24561. + AVR32_OPC_STHH_W2, 4, 0xe1e08000, 0xe1f0c0c0,
  24562. + &avr32_syntax_table[AVR32_SYNTAX_STHH_W2],
  24563. + BFD_RELOC_UNUSED, 7, -1,
  24564. + {
  24565. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24566. + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
  24567. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24568. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24569. + &avr32_ifield_table[AVR32_IFIELD_X2],
  24570. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24571. + &avr32_ifield_table[AVR32_IFIELD_Y2],
  24572. + },
  24573. + },
  24574. + {
  24575. + AVR32_OPC_STHH_W1, 4, 0xe1e0c000, 0xe1f0c000,
  24576. + &avr32_syntax_table[AVR32_SYNTAX_STHH_W1],
  24577. + BFD_RELOC_AVR32_STHH_W, 6, 1,
  24578. + {
  24579. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24580. + &avr32_ifield_table[AVR32_IFIELD_K8E2],
  24581. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24582. + &avr32_ifield_table[AVR32_IFIELD_X2],
  24583. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24584. + &avr32_ifield_table[AVR32_IFIELD_Y2],
  24585. + },
  24586. + },
  24587. + {
  24588. + AVR32_OPC_STM, 4, 0xe9c00000, 0xfff00000,
  24589. + &avr32_syntax_table[AVR32_SYNTAX_STM],
  24590. + BFD_RELOC_UNUSED, 2, -1,
  24591. + {
  24592. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24593. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24594. + },
  24595. + },
  24596. + {
  24597. + AVR32_OPC_STM_PU, 4, 0xebc00000, 0xfff00000,
  24598. + &avr32_syntax_table[AVR32_SYNTAX_STM_PU],
  24599. + BFD_RELOC_UNUSED, 2, -1,
  24600. + {
  24601. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24602. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24603. + },
  24604. + },
  24605. + {
  24606. + AVR32_OPC_STMTS, 4, 0xedc00000, 0xfff00000,
  24607. + &avr32_syntax_table[AVR32_SYNTAX_STMTS],
  24608. + BFD_RELOC_UNUSED, 2, -1,
  24609. + {
  24610. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24611. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24612. + },
  24613. + },
  24614. + {
  24615. + AVR32_OPC_STMTS_PU, 4, 0xefc00000, 0xfff00000,
  24616. + &avr32_syntax_table[AVR32_SYNTAX_STMTS_PU],
  24617. + BFD_RELOC_UNUSED, 2, -1,
  24618. + {
  24619. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24620. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24621. + },
  24622. + },
  24623. + {
  24624. + AVR32_OPC_STSWP_H, 4, 0xe1d09000, 0xe1f0f000,
  24625. + &avr32_syntax_table[AVR32_SYNTAX_STSWP_H],
  24626. + BFD_RELOC_UNUSED, 3, -1,
  24627. + {
  24628. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24629. + &avr32_ifield_table[AVR32_IFIELD_K12],
  24630. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24631. + },
  24632. + },
  24633. + {
  24634. + AVR32_OPC_STSWP_W, 4, 0xe1d0a000, 0xe1f0f000,
  24635. + &avr32_syntax_table[AVR32_SYNTAX_STSWP_W],
  24636. + BFD_RELOC_UNUSED, 3, -1,
  24637. + {
  24638. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24639. + &avr32_ifield_table[AVR32_IFIELD_K12],
  24640. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24641. + },
  24642. + },
  24643. + {
  24644. + AVR32_OPC_SUB1, 2, 0x00100000, 0xe1f00000,
  24645. + &avr32_syntax_table[AVR32_SYNTAX_SUB1],
  24646. + BFD_RELOC_UNUSED, 2, -1,
  24647. + {
  24648. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24649. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24650. + },
  24651. + },
  24652. + {
  24653. + AVR32_OPC_SUB2, 4, 0xe0000100, 0xe1f0ffc0,
  24654. + &avr32_syntax_table[AVR32_SYNTAX_SUB2],
  24655. + BFD_RELOC_UNUSED, 4, -1,
  24656. + {
  24657. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24658. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24659. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24660. + &avr32_ifield_table[AVR32_IFIELD_K2],
  24661. + },
  24662. + },
  24663. + {
  24664. + AVR32_OPC_SUB5, 4, 0xe0c00000, 0xe1f00000,
  24665. + &avr32_syntax_table[AVR32_SYNTAX_SUB5],
  24666. + BFD_RELOC_AVR32_SUB5, 3, 2,
  24667. + {
  24668. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24669. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24670. + &avr32_ifield_table[AVR32_IFIELD_K16],
  24671. + },
  24672. + },
  24673. + {
  24674. + AVR32_OPC_SUB3_SP, 2, 0x200d0000, 0xf00f0000,
  24675. + &avr32_syntax_table[AVR32_SYNTAX_SUB3_SP],
  24676. + BFD_RELOC_AVR32_10SW, 2, 1,
  24677. + {
  24678. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24679. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  24680. + },
  24681. + },
  24682. + {
  24683. + AVR32_OPC_SUB3, 2, 0x20000000, 0xf0000000,
  24684. + &avr32_syntax_table[AVR32_SYNTAX_SUB3],
  24685. + BFD_RELOC_AVR32_8S, 2, 1,
  24686. + {
  24687. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24688. + &avr32_ifield_table[AVR32_IFIELD_K8C],
  24689. + },
  24690. + },
  24691. + {
  24692. + AVR32_OPC_SUB4, 4, 0xe0200000, 0xe1e00000,
  24693. + &avr32_syntax_table[AVR32_SYNTAX_SUB4],
  24694. + BFD_RELOC_AVR32_21S, 2, 1,
  24695. + {
  24696. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24697. + &avr32_ifield_table[AVR32_IFIELD_K21],
  24698. + },
  24699. + },
  24700. + {
  24701. + AVR32_OPC_SUBEQ, 4, 0xf7b00000, 0xfff0ff00,
  24702. + &avr32_syntax_table[AVR32_SYNTAX_SUBEQ],
  24703. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24704. + {
  24705. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24706. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24707. + },
  24708. + },
  24709. + {
  24710. + AVR32_OPC_SUBNE, 4, 0xf7b00100, 0xfff0ff00,
  24711. + &avr32_syntax_table[AVR32_SYNTAX_SUBNE],
  24712. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24713. + {
  24714. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24715. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24716. + },
  24717. + },
  24718. + {
  24719. + AVR32_OPC_SUBCC, 4, 0xf7b00200, 0xfff0ff00,
  24720. + &avr32_syntax_table[AVR32_SYNTAX_SUBHS],
  24721. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24722. + {
  24723. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24724. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24725. + },
  24726. + },
  24727. + {
  24728. + AVR32_OPC_SUBCS, 4, 0xf7b00300, 0xfff0ff00,
  24729. + &avr32_syntax_table[AVR32_SYNTAX_SUBLO],
  24730. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24731. + {
  24732. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24733. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24734. + },
  24735. + },
  24736. + {
  24737. + AVR32_OPC_SUBGE, 4, 0xf7b00400, 0xfff0ff00,
  24738. + &avr32_syntax_table[AVR32_SYNTAX_SUBGE],
  24739. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24740. + {
  24741. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24742. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24743. + },
  24744. + },
  24745. + {
  24746. + AVR32_OPC_SUBLT, 4, 0xf7b00500, 0xfff0ff00,
  24747. + &avr32_syntax_table[AVR32_SYNTAX_SUBLT],
  24748. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24749. + {
  24750. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24751. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24752. + },
  24753. + },
  24754. + {
  24755. + AVR32_OPC_SUBMI, 4, 0xf7b00600, 0xfff0ff00,
  24756. + &avr32_syntax_table[AVR32_SYNTAX_SUBMI],
  24757. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24758. + {
  24759. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24760. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24761. + },
  24762. + },
  24763. + {
  24764. + AVR32_OPC_SUBPL, 4, 0xf7b00700, 0xfff0ff00,
  24765. + &avr32_syntax_table[AVR32_SYNTAX_SUBPL],
  24766. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24767. + {
  24768. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24769. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24770. + },
  24771. + },
  24772. + {
  24773. + AVR32_OPC_SUBLS, 4, 0xf7b00800, 0xfff0ff00,
  24774. + &avr32_syntax_table[AVR32_SYNTAX_SUBLS],
  24775. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24776. + {
  24777. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24778. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24779. + },
  24780. + },
  24781. + {
  24782. + AVR32_OPC_SUBGT, 4, 0xf7b00900, 0xfff0ff00,
  24783. + &avr32_syntax_table[AVR32_SYNTAX_SUBGT],
  24784. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24785. + {
  24786. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24787. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24788. + },
  24789. + },
  24790. + {
  24791. + AVR32_OPC_SUBLE, 4, 0xf7b00a00, 0xfff0ff00,
  24792. + &avr32_syntax_table[AVR32_SYNTAX_SUBLE],
  24793. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24794. + {
  24795. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24796. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24797. + },
  24798. + },
  24799. + {
  24800. + AVR32_OPC_SUBHI, 4, 0xf7b00b00, 0xfff0ff00,
  24801. + &avr32_syntax_table[AVR32_SYNTAX_SUBHI],
  24802. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24803. + {
  24804. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24805. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24806. + },
  24807. + },
  24808. + {
  24809. + AVR32_OPC_SUBVS, 4, 0xf7b00c00, 0xfff0ff00,
  24810. + &avr32_syntax_table[AVR32_SYNTAX_SUBVS],
  24811. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24812. + {
  24813. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24814. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24815. + },
  24816. + },
  24817. + {
  24818. + AVR32_OPC_SUBVC, 4, 0xf7b00d00, 0xfff0ff00,
  24819. + &avr32_syntax_table[AVR32_SYNTAX_SUBVC],
  24820. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24821. + {
  24822. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24823. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24824. + },
  24825. + },
  24826. + {
  24827. + AVR32_OPC_SUBQS, 4, 0xf7b00e00, 0xfff0ff00,
  24828. + &avr32_syntax_table[AVR32_SYNTAX_SUBQS],
  24829. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24830. + {
  24831. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24832. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24833. + },
  24834. + },
  24835. + {
  24836. + AVR32_OPC_SUBAL, 4, 0xf7b00f00, 0xfff0ff00,
  24837. + &avr32_syntax_table[AVR32_SYNTAX_SUBAL],
  24838. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24839. + {
  24840. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24841. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24842. + },
  24843. + },
  24844. + {
  24845. + AVR32_OPC_SUBFEQ, 4, 0xf5b00000, 0xfff0ff00,
  24846. + &avr32_syntax_table[AVR32_SYNTAX_SUBFEQ],
  24847. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24848. + {
  24849. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24850. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24851. + },
  24852. + },
  24853. + {
  24854. + AVR32_OPC_SUBFNE, 4, 0xf5b00100, 0xfff0ff00,
  24855. + &avr32_syntax_table[AVR32_SYNTAX_SUBFNE],
  24856. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24857. + {
  24858. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24859. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24860. + },
  24861. + },
  24862. + {
  24863. + AVR32_OPC_SUBFCC, 4, 0xf5b00200, 0xfff0ff00,
  24864. + &avr32_syntax_table[AVR32_SYNTAX_SUBFHS],
  24865. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24866. + {
  24867. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24868. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24869. + },
  24870. + },
  24871. + {
  24872. + AVR32_OPC_SUBFCS, 4, 0xf5b00300, 0xfff0ff00,
  24873. + &avr32_syntax_table[AVR32_SYNTAX_SUBFLO],
  24874. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24875. + {
  24876. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24877. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24878. + },
  24879. + },
  24880. + {
  24881. + AVR32_OPC_SUBFGE, 4, 0xf5b00400, 0xfff0ff00,
  24882. + &avr32_syntax_table[AVR32_SYNTAX_SUBFGE],
  24883. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24884. + {
  24885. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24886. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24887. + },
  24888. + },
  24889. + {
  24890. + AVR32_OPC_SUBFLT, 4, 0xf5b00500, 0xfff0ff00,
  24891. + &avr32_syntax_table[AVR32_SYNTAX_SUBFLT],
  24892. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24893. + {
  24894. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24895. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24896. + },
  24897. + },
  24898. + {
  24899. + AVR32_OPC_SUBFMI, 4, 0xf5b00600, 0xfff0ff00,
  24900. + &avr32_syntax_table[AVR32_SYNTAX_SUBFMI],
  24901. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24902. + {
  24903. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24904. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24905. + },
  24906. + },
  24907. + {
  24908. + AVR32_OPC_SUBFPL, 4, 0xf5b00700, 0xfff0ff00,
  24909. + &avr32_syntax_table[AVR32_SYNTAX_SUBFPL],
  24910. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24911. + {
  24912. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24913. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24914. + },
  24915. + },
  24916. + {
  24917. + AVR32_OPC_SUBFLS, 4, 0xf5b00800, 0xfff0ff00,
  24918. + &avr32_syntax_table[AVR32_SYNTAX_SUBFLS],
  24919. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24920. + {
  24921. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24922. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24923. + },
  24924. + },
  24925. + {
  24926. + AVR32_OPC_SUBFGT, 4, 0xf5b00900, 0xfff0ff00,
  24927. + &avr32_syntax_table[AVR32_SYNTAX_SUBFGT],
  24928. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24929. + {
  24930. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24931. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24932. + },
  24933. + },
  24934. + {
  24935. + AVR32_OPC_SUBFLE, 4, 0xf5b00a00, 0xfff0ff00,
  24936. + &avr32_syntax_table[AVR32_SYNTAX_SUBFLE],
  24937. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24938. + {
  24939. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24940. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24941. + },
  24942. + },
  24943. + {
  24944. + AVR32_OPC_SUBFHI, 4, 0xf5b00b00, 0xfff0ff00,
  24945. + &avr32_syntax_table[AVR32_SYNTAX_SUBFHI],
  24946. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24947. + {
  24948. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24949. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24950. + },
  24951. + },
  24952. + {
  24953. + AVR32_OPC_SUBFVS, 4, 0xf5b00c00, 0xfff0ff00,
  24954. + &avr32_syntax_table[AVR32_SYNTAX_SUBFVS],
  24955. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24956. + {
  24957. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24958. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24959. + },
  24960. + },
  24961. + {
  24962. + AVR32_OPC_SUBFVC, 4, 0xf5b00d00, 0xfff0ff00,
  24963. + &avr32_syntax_table[AVR32_SYNTAX_SUBFVC],
  24964. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24965. + {
  24966. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24967. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24968. + },
  24969. + },
  24970. + {
  24971. + AVR32_OPC_SUBFQS, 4, 0xf5b00e00, 0xfff0ff00,
  24972. + &avr32_syntax_table[AVR32_SYNTAX_SUBFQS],
  24973. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24974. + {
  24975. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24976. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24977. + },
  24978. + },
  24979. + {
  24980. + AVR32_OPC_SUBFAL, 4, 0xf5b00f00, 0xfff0ff00,
  24981. + &avr32_syntax_table[AVR32_SYNTAX_SUBFAL],
  24982. + BFD_RELOC_AVR32_8S_EXT, 2, 1,
  24983. + {
  24984. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24985. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  24986. + },
  24987. + },
  24988. + {
  24989. + AVR32_OPC_SUBHH_W, 4, 0xe0000f00, 0xe1f0ffc0,
  24990. + &avr32_syntax_table[AVR32_SYNTAX_SUBHH_W],
  24991. + BFD_RELOC_UNUSED, 5, -1,
  24992. + {
  24993. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  24994. + &avr32_ifield_table[AVR32_IFIELD_RX],
  24995. + &avr32_ifield_table[AVR32_IFIELD_X],
  24996. + &avr32_ifield_table[AVR32_IFIELD_RY],
  24997. + &avr32_ifield_table[AVR32_IFIELD_Y],
  24998. + },
  24999. + },
  25000. + {
  25001. + AVR32_OPC_SWAP_B, 2, 0x5cb00000, 0xfff00000,
  25002. + &avr32_syntax_table[AVR32_SYNTAX_SWAP_B],
  25003. + BFD_RELOC_UNUSED, 1, -1,
  25004. + {
  25005. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25006. + }
  25007. + },
  25008. + {
  25009. + AVR32_OPC_SWAP_BH, 2, 0x5cc00000, 0xfff00000,
  25010. + &avr32_syntax_table[AVR32_SYNTAX_SWAP_BH],
  25011. + BFD_RELOC_UNUSED, 1, -1,
  25012. + {
  25013. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25014. + }
  25015. + },
  25016. + {
  25017. + AVR32_OPC_SWAP_H, 2, 0x5ca00000, 0xfff00000,
  25018. + &avr32_syntax_table[AVR32_SYNTAX_SWAP_H],
  25019. + BFD_RELOC_UNUSED, 1, -1,
  25020. + {
  25021. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25022. + }
  25023. + },
  25024. + {
  25025. + AVR32_OPC_SYNC, 4, 0xebb00000, 0xffffff00,
  25026. + &avr32_syntax_table[AVR32_SYNTAX_SYNC],
  25027. + BFD_RELOC_AVR32_8S_EXT, 1, 0,
  25028. + {
  25029. + &avr32_ifield_table[AVR32_IFIELD_K8E],
  25030. + }
  25031. + },
  25032. + {
  25033. + AVR32_OPC_TLBR, 2, 0xd6430000, 0xffff0000,
  25034. + &avr32_syntax_table[AVR32_SYNTAX_TLBR],
  25035. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  25036. + },
  25037. + {
  25038. + AVR32_OPC_TLBS, 2, 0xd6530000, 0xffff0000,
  25039. + &avr32_syntax_table[AVR32_SYNTAX_TLBS],
  25040. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  25041. + },
  25042. + {
  25043. + AVR32_OPC_TLBW, 2, 0xd6630000, 0xffff0000,
  25044. + &avr32_syntax_table[AVR32_SYNTAX_TLBW],
  25045. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  25046. + },
  25047. + {
  25048. + AVR32_OPC_TNBZ, 2, 0x5ce00000, 0xfff00000,
  25049. + &avr32_syntax_table[AVR32_SYNTAX_TNBZ],
  25050. + BFD_RELOC_UNUSED, 1, -1,
  25051. + {
  25052. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25053. + }
  25054. + },
  25055. + {
  25056. + AVR32_OPC_TST, 2, 0x00700000, 0xe1f00000,
  25057. + &avr32_syntax_table[AVR32_SYNTAX_TST],
  25058. + BFD_RELOC_UNUSED, 2, -1,
  25059. + {
  25060. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25061. + &avr32_ifield_table[AVR32_IFIELD_RX],
  25062. + },
  25063. + },
  25064. + {
  25065. + AVR32_OPC_XCHG, 4, 0xe0000b40, 0xe1f0fff0,
  25066. + &avr32_syntax_table[AVR32_SYNTAX_XCHG],
  25067. + BFD_RELOC_UNUSED, 3, -1,
  25068. + {
  25069. + &avr32_ifield_table[AVR32_IFIELD_RD_E],
  25070. + &avr32_ifield_table[AVR32_IFIELD_RX],
  25071. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25072. + },
  25073. + },
  25074. + {
  25075. + AVR32_OPC_MEMC, 4, 0xf6100000, 0xfff00000,
  25076. + &avr32_syntax_table[AVR32_SYNTAX_MEMC],
  25077. + BFD_RELOC_AVR32_15S, 2, 0,
  25078. + {
  25079. + &avr32_ifield_table[AVR32_IFIELD_MEM15],
  25080. + &avr32_ifield_table[AVR32_IFIELD_MEMB5],
  25081. + },
  25082. + },
  25083. + {
  25084. + AVR32_OPC_MEMS, 4, 0xf8100000, 0xfff00000,
  25085. + &avr32_syntax_table[AVR32_SYNTAX_MEMS],
  25086. + BFD_RELOC_AVR32_15S, 2, 0,
  25087. + {
  25088. + &avr32_ifield_table[AVR32_IFIELD_MEM15],
  25089. + &avr32_ifield_table[AVR32_IFIELD_MEMB5],
  25090. + },
  25091. + },
  25092. + {
  25093. + AVR32_OPC_MEMT, 4, 0xfa100000, 0xfff00000,
  25094. + &avr32_syntax_table[AVR32_SYNTAX_MEMT],
  25095. + BFD_RELOC_AVR32_15S, 2, 0,
  25096. + {
  25097. + &avr32_ifield_table[AVR32_IFIELD_MEM15],
  25098. + &avr32_ifield_table[AVR32_IFIELD_MEMB5],
  25099. + },
  25100. + },
  25101. + {
  25102. + AVR32_OPC_BFEXTS, 4, 0xe1d0b000, 0xe1f0fc00,
  25103. + &avr32_syntax_table[AVR32_SYNTAX_BFEXTS],
  25104. + BFD_RELOC_UNUSED, 4, -1,
  25105. + {
  25106. + &avr32_ifield_table[AVR32_IFIELD_RX],
  25107. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25108. + &avr32_ifield_table[AVR32_IFIELD_S5],
  25109. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  25110. + },
  25111. + },
  25112. + {
  25113. + AVR32_OPC_BFEXTU, 4, 0xe1d0c000, 0xe1f0fc00,
  25114. + &avr32_syntax_table[AVR32_SYNTAX_BFEXTU],
  25115. + BFD_RELOC_UNUSED, 4, -1,
  25116. + {
  25117. + &avr32_ifield_table[AVR32_IFIELD_RX],
  25118. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25119. + &avr32_ifield_table[AVR32_IFIELD_S5],
  25120. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  25121. + },
  25122. + },
  25123. + {
  25124. + AVR32_OPC_BFINS, 4, 0xe1d0d000, 0xe1f0fc00,
  25125. + &avr32_syntax_table[AVR32_SYNTAX_BFINS],
  25126. + BFD_RELOC_UNUSED, 4, -1,
  25127. + {
  25128. + &avr32_ifield_table[AVR32_IFIELD_RX],
  25129. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25130. + &avr32_ifield_table[AVR32_IFIELD_S5],
  25131. + &avr32_ifield_table[AVR32_IFIELD_K5E],
  25132. + },
  25133. + },
  25134. +#define AVR32_OPCODE_RSUBCOND(cond_name, cond_field) \
  25135. + { \
  25136. + AVR32_OPC_RSUB ## cond_name , 4, \
  25137. + 0xfbb00000 | (cond_field << 8), 0xfff0ff00, \
  25138. + &avr32_syntax_table[AVR32_SYNTAX_RSUB ## cond_name ], \
  25139. + BFD_RELOC_AVR32_8S_EXT, 2, 1, \
  25140. + { \
  25141. + &avr32_ifield_table[AVR32_IFIELD_RY], \
  25142. + &avr32_ifield_table[AVR32_IFIELD_K8E], \
  25143. + }, \
  25144. + },
  25145. +
  25146. + AVR32_OPCODE_RSUBCOND (EQ, 0)
  25147. + AVR32_OPCODE_RSUBCOND (NE, 1)
  25148. + AVR32_OPCODE_RSUBCOND (CC, 2)
  25149. + AVR32_OPCODE_RSUBCOND (CS, 3)
  25150. + AVR32_OPCODE_RSUBCOND (GE, 4)
  25151. + AVR32_OPCODE_RSUBCOND (LT, 5)
  25152. + AVR32_OPCODE_RSUBCOND (MI, 6)
  25153. + AVR32_OPCODE_RSUBCOND (PL, 7)
  25154. + AVR32_OPCODE_RSUBCOND (LS, 8)
  25155. + AVR32_OPCODE_RSUBCOND (GT, 9)
  25156. + AVR32_OPCODE_RSUBCOND (LE, 10)
  25157. + AVR32_OPCODE_RSUBCOND (HI, 11)
  25158. + AVR32_OPCODE_RSUBCOND (VS, 12)
  25159. + AVR32_OPCODE_RSUBCOND (VC, 13)
  25160. + AVR32_OPCODE_RSUBCOND (QS, 14)
  25161. + AVR32_OPCODE_RSUBCOND (AL, 15)
  25162. +
  25163. +#define AVR32_OPCODE_OP3_COND(op_name, op_field, cond_name, cond_field) \
  25164. + { \
  25165. + AVR32_OPC_ ## op_name ## cond_name , 4, \
  25166. + 0xe1d0e000 | (cond_field << 8) | (op_field << 4), 0xe1f0fff0, \
  25167. + &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ], \
  25168. + BFD_RELOC_UNUSED, 3, -1, \
  25169. + { \
  25170. + &avr32_ifield_table[AVR32_IFIELD_RD_E], \
  25171. + &avr32_ifield_table[AVR32_IFIELD_RX], \
  25172. + &avr32_ifield_table[AVR32_IFIELD_RY], \
  25173. + }, \
  25174. + },
  25175. +
  25176. + AVR32_OPCODE_OP3_COND (ADD, 0, EQ, 0)
  25177. + AVR32_OPCODE_OP3_COND (ADD, 0, NE, 1)
  25178. + AVR32_OPCODE_OP3_COND (ADD, 0, CC, 2)
  25179. + AVR32_OPCODE_OP3_COND (ADD, 0, CS, 3)
  25180. + AVR32_OPCODE_OP3_COND (ADD, 0, GE, 4)
  25181. + AVR32_OPCODE_OP3_COND (ADD, 0, LT, 5)
  25182. + AVR32_OPCODE_OP3_COND (ADD, 0, MI, 6)
  25183. + AVR32_OPCODE_OP3_COND (ADD, 0, PL, 7)
  25184. + AVR32_OPCODE_OP3_COND (ADD, 0, LS, 8)
  25185. + AVR32_OPCODE_OP3_COND (ADD, 0, GT, 9)
  25186. + AVR32_OPCODE_OP3_COND (ADD, 0, LE, 10)
  25187. + AVR32_OPCODE_OP3_COND (ADD, 0, HI, 11)
  25188. + AVR32_OPCODE_OP3_COND (ADD, 0, VS, 12)
  25189. + AVR32_OPCODE_OP3_COND (ADD, 0, VC, 13)
  25190. + AVR32_OPCODE_OP3_COND (ADD, 0, QS, 14)
  25191. + AVR32_OPCODE_OP3_COND (ADD, 0, AL, 15)
  25192. +
  25193. + AVR32_OPCODE_OP3_COND (SUB2, 1, EQ, 0)
  25194. + AVR32_OPCODE_OP3_COND (SUB2, 1, NE, 1)
  25195. + AVR32_OPCODE_OP3_COND (SUB2, 1, CC, 2)
  25196. + AVR32_OPCODE_OP3_COND (SUB2, 1, CS, 3)
  25197. + AVR32_OPCODE_OP3_COND (SUB2, 1, GE, 4)
  25198. + AVR32_OPCODE_OP3_COND (SUB2, 1, LT, 5)
  25199. + AVR32_OPCODE_OP3_COND (SUB2, 1, MI, 6)
  25200. + AVR32_OPCODE_OP3_COND (SUB2, 1, PL, 7)
  25201. + AVR32_OPCODE_OP3_COND (SUB2, 1, LS, 8)
  25202. + AVR32_OPCODE_OP3_COND (SUB2, 1, GT, 9)
  25203. + AVR32_OPCODE_OP3_COND (SUB2, 1, LE, 10)
  25204. + AVR32_OPCODE_OP3_COND (SUB2, 1, HI, 11)
  25205. + AVR32_OPCODE_OP3_COND (SUB2, 1, VS, 12)
  25206. + AVR32_OPCODE_OP3_COND (SUB2, 1, VC, 13)
  25207. + AVR32_OPCODE_OP3_COND (SUB2, 1, QS, 14)
  25208. + AVR32_OPCODE_OP3_COND (SUB2, 1, AL, 15)
  25209. +
  25210. + AVR32_OPCODE_OP3_COND (AND, 2, EQ, 0)
  25211. + AVR32_OPCODE_OP3_COND (AND, 2, NE, 1)
  25212. + AVR32_OPCODE_OP3_COND (AND, 2, CC, 2)
  25213. + AVR32_OPCODE_OP3_COND (AND, 2, CS, 3)
  25214. + AVR32_OPCODE_OP3_COND (AND, 2, GE, 4)
  25215. + AVR32_OPCODE_OP3_COND (AND, 2, LT, 5)
  25216. + AVR32_OPCODE_OP3_COND (AND, 2, MI, 6)
  25217. + AVR32_OPCODE_OP3_COND (AND, 2, PL, 7)
  25218. + AVR32_OPCODE_OP3_COND (AND, 2, LS, 8)
  25219. + AVR32_OPCODE_OP3_COND (AND, 2, GT, 9)
  25220. + AVR32_OPCODE_OP3_COND (AND, 2, LE, 10)
  25221. + AVR32_OPCODE_OP3_COND (AND, 2, HI, 11)
  25222. + AVR32_OPCODE_OP3_COND (AND, 2, VS, 12)
  25223. + AVR32_OPCODE_OP3_COND (AND, 2, VC, 13)
  25224. + AVR32_OPCODE_OP3_COND (AND, 2, QS, 14)
  25225. + AVR32_OPCODE_OP3_COND (AND, 2, AL, 15)
  25226. +
  25227. + AVR32_OPCODE_OP3_COND (OR, 3, EQ, 0)
  25228. + AVR32_OPCODE_OP3_COND (OR, 3, NE, 1)
  25229. + AVR32_OPCODE_OP3_COND (OR, 3, CC, 2)
  25230. + AVR32_OPCODE_OP3_COND (OR, 3, CS, 3)
  25231. + AVR32_OPCODE_OP3_COND (OR, 3, GE, 4)
  25232. + AVR32_OPCODE_OP3_COND (OR, 3, LT, 5)
  25233. + AVR32_OPCODE_OP3_COND (OR, 3, MI, 6)
  25234. + AVR32_OPCODE_OP3_COND (OR, 3, PL, 7)
  25235. + AVR32_OPCODE_OP3_COND (OR, 3, LS, 8)
  25236. + AVR32_OPCODE_OP3_COND (OR, 3, GT, 9)
  25237. + AVR32_OPCODE_OP3_COND (OR, 3, LE, 10)
  25238. + AVR32_OPCODE_OP3_COND (OR, 3, HI, 11)
  25239. + AVR32_OPCODE_OP3_COND (OR, 3, VS, 12)
  25240. + AVR32_OPCODE_OP3_COND (OR, 3, VC, 13)
  25241. + AVR32_OPCODE_OP3_COND (OR, 3, QS, 14)
  25242. + AVR32_OPCODE_OP3_COND (OR, 3, AL, 15)
  25243. +
  25244. + AVR32_OPCODE_OP3_COND (EOR, 4, EQ, 0)
  25245. + AVR32_OPCODE_OP3_COND (EOR, 4, NE, 1)
  25246. + AVR32_OPCODE_OP3_COND (EOR, 4, CC, 2)
  25247. + AVR32_OPCODE_OP3_COND (EOR, 4, CS, 3)
  25248. + AVR32_OPCODE_OP3_COND (EOR, 4, GE, 4)
  25249. + AVR32_OPCODE_OP3_COND (EOR, 4, LT, 5)
  25250. + AVR32_OPCODE_OP3_COND (EOR, 4, MI, 6)
  25251. + AVR32_OPCODE_OP3_COND (EOR, 4, PL, 7)
  25252. + AVR32_OPCODE_OP3_COND (EOR, 4, LS, 8)
  25253. + AVR32_OPCODE_OP3_COND (EOR, 4, GT, 9)
  25254. + AVR32_OPCODE_OP3_COND (EOR, 4, LE, 10)
  25255. + AVR32_OPCODE_OP3_COND (EOR, 4, HI, 11)
  25256. + AVR32_OPCODE_OP3_COND (EOR, 4, VS, 12)
  25257. + AVR32_OPCODE_OP3_COND (EOR, 4, VC, 13)
  25258. + AVR32_OPCODE_OP3_COND (EOR, 4, QS, 14)
  25259. + AVR32_OPCODE_OP3_COND (EOR, 4, AL, 15)
  25260. +
  25261. +#define AVR32_OPCODE_LD_COND(op_name, op_field, cond_name, cond_field) \
  25262. + { \
  25263. + AVR32_OPC_ ## op_name ## cond_name , 4, \
  25264. + 0xe1f00000 | (cond_field << 12) | (op_field << 9), 0xe1f0fe00, \
  25265. + &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ], \
  25266. + BFD_RELOC_UNUSED, 3, -1, \
  25267. + { \
  25268. + &avr32_ifield_table[AVR32_IFIELD_RY], \
  25269. + &avr32_ifield_table[AVR32_IFIELD_RX], \
  25270. + &avr32_ifield_table[AVR32_IFIELD_K9E], \
  25271. + }, \
  25272. + },
  25273. +
  25274. +#define AVR32_OPCODE_ST_COND(op_name, op_field, cond_name, cond_field) \
  25275. + { \
  25276. + AVR32_OPC_ ## op_name ## cond_name , 4, \
  25277. + 0xe1f00000 | (cond_field << 12) | (op_field << 9), 0xe1f0fe00, \
  25278. + &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ], \
  25279. + BFD_RELOC_UNUSED, 3, -1, \
  25280. + { \
  25281. + &avr32_ifield_table[AVR32_IFIELD_RX], \
  25282. + &avr32_ifield_table[AVR32_IFIELD_K9E], \
  25283. + &avr32_ifield_table[AVR32_IFIELD_RY], \
  25284. + }, \
  25285. + },
  25286. +
  25287. + AVR32_OPCODE_LD_COND (LD_W, 0, EQ, 0)
  25288. + AVR32_OPCODE_LD_COND (LD_W, 0, NE, 1)
  25289. + AVR32_OPCODE_LD_COND (LD_W, 0, CC, 2)
  25290. + AVR32_OPCODE_LD_COND (LD_W, 0, CS, 3)
  25291. + AVR32_OPCODE_LD_COND (LD_W, 0, GE, 4)
  25292. + AVR32_OPCODE_LD_COND (LD_W, 0, LT, 5)
  25293. + AVR32_OPCODE_LD_COND (LD_W, 0, MI, 6)
  25294. + AVR32_OPCODE_LD_COND (LD_W, 0, PL, 7)
  25295. + AVR32_OPCODE_LD_COND (LD_W, 0, LS, 8)
  25296. + AVR32_OPCODE_LD_COND (LD_W, 0, GT, 9)
  25297. + AVR32_OPCODE_LD_COND (LD_W, 0, LE, 10)
  25298. + AVR32_OPCODE_LD_COND (LD_W, 0, HI, 11)
  25299. + AVR32_OPCODE_LD_COND (LD_W, 0, VS, 12)
  25300. + AVR32_OPCODE_LD_COND (LD_W, 0, VC, 13)
  25301. + AVR32_OPCODE_LD_COND (LD_W, 0, QS, 14)
  25302. + AVR32_OPCODE_LD_COND (LD_W, 0, AL, 15)
  25303. +
  25304. + AVR32_OPCODE_LD_COND (LD_SH, 1, EQ, 0)
  25305. + AVR32_OPCODE_LD_COND (LD_SH, 1, NE, 1)
  25306. + AVR32_OPCODE_LD_COND (LD_SH, 1, CC, 2)
  25307. + AVR32_OPCODE_LD_COND (LD_SH, 1, CS, 3)
  25308. + AVR32_OPCODE_LD_COND (LD_SH, 1, GE, 4)
  25309. + AVR32_OPCODE_LD_COND (LD_SH, 1, LT, 5)
  25310. + AVR32_OPCODE_LD_COND (LD_SH, 1, MI, 6)
  25311. + AVR32_OPCODE_LD_COND (LD_SH, 1, PL, 7)
  25312. + AVR32_OPCODE_LD_COND (LD_SH, 1, LS, 8)
  25313. + AVR32_OPCODE_LD_COND (LD_SH, 1, GT, 9)
  25314. + AVR32_OPCODE_LD_COND (LD_SH, 1, LE, 10)
  25315. + AVR32_OPCODE_LD_COND (LD_SH, 1, HI, 11)
  25316. + AVR32_OPCODE_LD_COND (LD_SH, 1, VS, 12)
  25317. + AVR32_OPCODE_LD_COND (LD_SH, 1, VC, 13)
  25318. + AVR32_OPCODE_LD_COND (LD_SH, 1, QS, 14)
  25319. + AVR32_OPCODE_LD_COND (LD_SH, 1, AL, 15)
  25320. +
  25321. + AVR32_OPCODE_LD_COND (LD_UH, 2, EQ, 0)
  25322. + AVR32_OPCODE_LD_COND (LD_UH, 2, NE, 1)
  25323. + AVR32_OPCODE_LD_COND (LD_UH, 2, CC, 2)
  25324. + AVR32_OPCODE_LD_COND (LD_UH, 2, CS, 3)
  25325. + AVR32_OPCODE_LD_COND (LD_UH, 2, GE, 4)
  25326. + AVR32_OPCODE_LD_COND (LD_UH, 2, LT, 5)
  25327. + AVR32_OPCODE_LD_COND (LD_UH, 2, MI, 6)
  25328. + AVR32_OPCODE_LD_COND (LD_UH, 2, PL, 7)
  25329. + AVR32_OPCODE_LD_COND (LD_SH, 2, LS, 8)
  25330. + AVR32_OPCODE_LD_COND (LD_SH, 2, GT, 9)
  25331. + AVR32_OPCODE_LD_COND (LD_SH, 2, LE, 10)
  25332. + AVR32_OPCODE_LD_COND (LD_SH, 2, HI, 11)
  25333. + AVR32_OPCODE_LD_COND (LD_SH, 2, VS, 12)
  25334. + AVR32_OPCODE_LD_COND (LD_SH, 2, VC, 13)
  25335. + AVR32_OPCODE_LD_COND (LD_SH, 2, QS, 14)
  25336. + AVR32_OPCODE_LD_COND (LD_SH, 2, AL, 15)
  25337. +
  25338. + AVR32_OPCODE_LD_COND (LD_SB, 3, EQ, 0)
  25339. + AVR32_OPCODE_LD_COND (LD_SB, 3, NE, 1)
  25340. + AVR32_OPCODE_LD_COND (LD_SB, 3, CC, 2)
  25341. + AVR32_OPCODE_LD_COND (LD_SB, 3, CS, 3)
  25342. + AVR32_OPCODE_LD_COND (LD_SB, 3, GE, 4)
  25343. + AVR32_OPCODE_LD_COND (LD_SB, 3, LT, 5)
  25344. + AVR32_OPCODE_LD_COND (LD_SB, 3, MI, 6)
  25345. + AVR32_OPCODE_LD_COND (LD_SB, 3, PL, 7)
  25346. + AVR32_OPCODE_LD_COND (LD_SB, 3, LS, 8)
  25347. + AVR32_OPCODE_LD_COND (LD_SB, 3, GT, 9)
  25348. + AVR32_OPCODE_LD_COND (LD_SB, 3, LE, 10)
  25349. + AVR32_OPCODE_LD_COND (LD_SB, 3, HI, 11)
  25350. + AVR32_OPCODE_LD_COND (LD_SB, 3, VS, 12)
  25351. + AVR32_OPCODE_LD_COND (LD_SB, 3, VC, 13)
  25352. + AVR32_OPCODE_LD_COND (LD_SB, 3, QS, 14)
  25353. + AVR32_OPCODE_LD_COND (LD_SB, 3, AL, 15)
  25354. +
  25355. + AVR32_OPCODE_LD_COND (LD_UB, 4, EQ, 0)
  25356. + AVR32_OPCODE_LD_COND (LD_UB, 4, NE, 1)
  25357. + AVR32_OPCODE_LD_COND (LD_UB, 4, CC, 2)
  25358. + AVR32_OPCODE_LD_COND (LD_UB, 4, CS, 3)
  25359. + AVR32_OPCODE_LD_COND (LD_UB, 4, GE, 4)
  25360. + AVR32_OPCODE_LD_COND (LD_UB, 4, LT, 5)
  25361. + AVR32_OPCODE_LD_COND (LD_UB, 4, MI, 6)
  25362. + AVR32_OPCODE_LD_COND (LD_UB, 4, PL, 7)
  25363. + AVR32_OPCODE_LD_COND (LD_UB, 4, LS, 8)
  25364. + AVR32_OPCODE_LD_COND (LD_UB, 4, GT, 9)
  25365. + AVR32_OPCODE_LD_COND (LD_UB, 4, LE, 10)
  25366. + AVR32_OPCODE_LD_COND (LD_UB, 4, HI, 11)
  25367. + AVR32_OPCODE_LD_COND (LD_UB, 4, VS, 12)
  25368. + AVR32_OPCODE_LD_COND (LD_UB, 4, VC, 13)
  25369. + AVR32_OPCODE_LD_COND (LD_UB, 4, QS, 14)
  25370. + AVR32_OPCODE_LD_COND (LD_UB, 4, AL, 15)
  25371. +
  25372. + AVR32_OPCODE_ST_COND (ST_W, 5, EQ, 0)
  25373. + AVR32_OPCODE_ST_COND (ST_W, 5, NE, 1)
  25374. + AVR32_OPCODE_ST_COND (ST_W, 5, CC, 2)
  25375. + AVR32_OPCODE_ST_COND (ST_W, 5, CS, 3)
  25376. + AVR32_OPCODE_ST_COND (ST_W, 5, GE, 4)
  25377. + AVR32_OPCODE_ST_COND (ST_W, 5, LT, 5)
  25378. + AVR32_OPCODE_ST_COND (ST_W, 5, MI, 6)
  25379. + AVR32_OPCODE_ST_COND (ST_W, 5, PL, 7)
  25380. + AVR32_OPCODE_ST_COND (ST_W, 5, LS, 8)
  25381. + AVR32_OPCODE_ST_COND (ST_W, 5, GT, 9)
  25382. + AVR32_OPCODE_ST_COND (ST_W, 5, LE, 10)
  25383. + AVR32_OPCODE_ST_COND (ST_W, 5, HI, 11)
  25384. + AVR32_OPCODE_ST_COND (ST_W, 5, VS, 12)
  25385. + AVR32_OPCODE_ST_COND (ST_W, 5, VC, 13)
  25386. + AVR32_OPCODE_ST_COND (ST_W, 5, QS, 14)
  25387. + AVR32_OPCODE_ST_COND (ST_W, 5, AL, 15)
  25388. +
  25389. + AVR32_OPCODE_ST_COND (ST_H, 6, EQ, 0)
  25390. + AVR32_OPCODE_ST_COND (ST_H, 6, NE, 1)
  25391. + AVR32_OPCODE_ST_COND (ST_H, 6, CC, 2)
  25392. + AVR32_OPCODE_ST_COND (ST_H, 6, CS, 3)
  25393. + AVR32_OPCODE_ST_COND (ST_H, 6, GE, 4)
  25394. + AVR32_OPCODE_ST_COND (ST_H, 6, LT, 5)
  25395. + AVR32_OPCODE_ST_COND (ST_H, 6, MI, 6)
  25396. + AVR32_OPCODE_ST_COND (ST_H, 6, PL, 7)
  25397. + AVR32_OPCODE_ST_COND (ST_H, 6, LS, 8)
  25398. + AVR32_OPCODE_ST_COND (ST_H, 6, GT, 9)
  25399. + AVR32_OPCODE_ST_COND (ST_H, 6, LE, 10)
  25400. + AVR32_OPCODE_ST_COND (ST_H, 6, HI, 11)
  25401. + AVR32_OPCODE_ST_COND (ST_H, 6, VS, 12)
  25402. + AVR32_OPCODE_ST_COND (ST_H, 6, VC, 13)
  25403. + AVR32_OPCODE_ST_COND (ST_H, 6, QS, 14)
  25404. + AVR32_OPCODE_ST_COND (ST_H, 6, AL, 15)
  25405. +
  25406. + AVR32_OPCODE_ST_COND (ST_B, 7, EQ, 0)
  25407. + AVR32_OPCODE_ST_COND (ST_B, 7, NE, 1)
  25408. + AVR32_OPCODE_ST_COND (ST_B, 7, CC, 2)
  25409. + AVR32_OPCODE_ST_COND (ST_B, 7, CS, 3)
  25410. + AVR32_OPCODE_ST_COND (ST_B, 7, GE, 4)
  25411. + AVR32_OPCODE_ST_COND (ST_B, 7, LT, 5)
  25412. + AVR32_OPCODE_ST_COND (ST_B, 7, MI, 6)
  25413. + AVR32_OPCODE_ST_COND (ST_B, 7, PL, 7)
  25414. + AVR32_OPCODE_ST_COND (ST_B, 7, LS, 8)
  25415. + AVR32_OPCODE_ST_COND (ST_B, 7, GT, 9)
  25416. + AVR32_OPCODE_ST_COND (ST_B, 7, LE, 10)
  25417. + AVR32_OPCODE_ST_COND (ST_B, 7, HI, 11)
  25418. + AVR32_OPCODE_ST_COND (ST_B, 7, VS, 12)
  25419. + AVR32_OPCODE_ST_COND (ST_B, 7, VC, 13)
  25420. + AVR32_OPCODE_ST_COND (ST_B, 7, QS, 14)
  25421. + AVR32_OPCODE_ST_COND (ST_B, 7, AL, 15)
  25422. +
  25423. + {
  25424. + AVR32_OPC_MOVH, 4, 0xfc100000, 0xfff00000,
  25425. + &avr32_syntax_table[AVR32_SYNTAX_MOVH],
  25426. + BFD_RELOC_AVR32_16U, 2, 1,
  25427. + {
  25428. + &avr32_ifield_table[AVR32_IFIELD_RY],
  25429. + &avr32_ifield_table[AVR32_IFIELD_K16],
  25430. + },
  25431. + },
  25432. + {
  25433. + AVR32_OPC_SSCALL, 2, 0xd7530000, 0xffff0000,
  25434. + &avr32_syntax_table[AVR32_SYNTAX_SSCALL],
  25435. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  25436. + },
  25437. + {
  25438. + AVR32_OPC_RETSS, 2, 0xd7630000, 0xffff0000,
  25439. + &avr32_syntax_table[AVR32_SYNTAX_RETSS],
  25440. + BFD_RELOC_UNUSED, 0, -1, { NULL },
  25441. + },
  25442. +
  25443. + {
  25444. + AVR32_OPC_FMAC_S, 4, 0xE1A00000, 0xFFF0F000,
  25445. + &avr32_syntax_table[AVR32_SYNTAX_FMAC_S],
  25446. + BFD_RELOC_UNUSED, 4, -1,
  25447. + {
  25448. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25449. + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
  25450. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25451. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25452. + }
  25453. + },
  25454. + {
  25455. + AVR32_OPC_FNMAC_S, 4, 0xE1A01000, 0xFFF0F000,
  25456. + &avr32_syntax_table[AVR32_SYNTAX_FNMAC_S],
  25457. + BFD_RELOC_UNUSED, 4, -1,
  25458. + {
  25459. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25460. + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
  25461. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25462. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25463. + }
  25464. + },
  25465. + {
  25466. + AVR32_OPC_FMSC_S, 4, 0xE3A00000, 0xFFF0F000,
  25467. + &avr32_syntax_table[AVR32_SYNTAX_FMSC_S],
  25468. + BFD_RELOC_UNUSED, 4, -1,
  25469. + {
  25470. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25471. + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
  25472. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25473. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25474. + }
  25475. + },
  25476. + {
  25477. + AVR32_OPC_FNMSC_S, 4, 0xE3A01000, 0xFFF0F000,
  25478. + &avr32_syntax_table[AVR32_SYNTAX_FNMSC_S],
  25479. + BFD_RELOC_UNUSED, 4, -1,
  25480. + {
  25481. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25482. + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
  25483. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25484. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25485. + }
  25486. + },
  25487. + {
  25488. + AVR32_OPC_FMUL_S, 4, 0xE5A20000, 0xFFFFF000,
  25489. + &avr32_syntax_table[AVR32_SYNTAX_FMUL_S],
  25490. + BFD_RELOC_UNUSED, 3, -1,
  25491. + {
  25492. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25493. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25494. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25495. + }
  25496. + },
  25497. + {
  25498. + AVR32_OPC_FNMUL_S, 4, 0xE5A30000, 0xFFFFF000,
  25499. + &avr32_syntax_table[AVR32_SYNTAX_FNMUL_S],
  25500. + BFD_RELOC_UNUSED, 3, -1,
  25501. + {
  25502. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25503. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25504. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25505. + }
  25506. + },
  25507. + {
  25508. + AVR32_OPC_FADD_S, 4, 0xE5A00000, 0xFFFFF000,
  25509. + &avr32_syntax_table[AVR32_SYNTAX_FADD_S],
  25510. + BFD_RELOC_UNUSED, 3, -1,
  25511. + {
  25512. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25513. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25514. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25515. + }
  25516. + },
  25517. + {
  25518. + AVR32_OPC_FSUB_S, 4, 0xE5A10000, 0xFFFFF000,
  25519. + &avr32_syntax_table[AVR32_SYNTAX_FSUB_S],
  25520. + BFD_RELOC_UNUSED, 3, -1,
  25521. + {
  25522. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25523. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25524. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25525. + }
  25526. + },
  25527. + {
  25528. + AVR32_OPC_FCASTRS_SW, 4, 0xE5AB0000, 0xFFFFF0F0,
  25529. + &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_SW],
  25530. + BFD_RELOC_UNUSED, 2, -1,
  25531. + {
  25532. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25533. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25534. + }
  25535. + },
  25536. + {
  25537. + AVR32_OPC_FCASTRS_UW, 4, 0xE5A90000, 0xFFFFF0F0,
  25538. + &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_UW],
  25539. + BFD_RELOC_UNUSED, 2, -1,
  25540. + {
  25541. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25542. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25543. + }
  25544. + },
  25545. + {
  25546. + AVR32_OPC_FCASTSW_S, 4, 0xE5A60000, 0xFFFFF0F0,
  25547. + &avr32_syntax_table[AVR32_SYNTAX_FCASTSW_S],
  25548. + BFD_RELOC_UNUSED, 2, -1,
  25549. + {
  25550. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25551. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25552. + }
  25553. + },
  25554. + {
  25555. + AVR32_OPC_FCASTUW_S, 4, 0xE5A40000, 0xFFFFF0F0,
  25556. + &avr32_syntax_table[AVR32_SYNTAX_FCASTUW_S],
  25557. + BFD_RELOC_UNUSED, 2, -1,
  25558. + {
  25559. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25560. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25561. + }
  25562. + },
  25563. + {
  25564. + AVR32_OPC_FCMP_S, 4, 0xE5AC0000, 0xFFFFFF00,
  25565. + &avr32_syntax_table[AVR32_SYNTAX_FCMP_S],
  25566. + BFD_RELOC_UNUSED, 2, -1,
  25567. + {
  25568. + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
  25569. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25570. + }
  25571. + },
  25572. + {
  25573. + AVR32_OPC_FCHK_S, 4, 0xE5AD0000, 0xFFFFFFF0,
  25574. + &avr32_syntax_table[AVR32_SYNTAX_FCHK_S],
  25575. + BFD_RELOC_UNUSED, 1, -1,
  25576. + {
  25577. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25578. + }
  25579. + },
  25580. + {
  25581. + AVR32_OPC_FRCPA_S, 4, 0xE5AE0000, 0xFFFFF0F0,
  25582. + &avr32_syntax_table[AVR32_SYNTAX_FRCPA_S],
  25583. + BFD_RELOC_UNUSED, 2, -1,
  25584. + {
  25585. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25586. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25587. + }
  25588. + },
  25589. + {
  25590. + AVR32_OPC_FRSQRTA_S, 4, 0xE5AF0000, 0xFFFFF0F0,
  25591. + &avr32_syntax_table[AVR32_SYNTAX_FRSQRTA_S],
  25592. + BFD_RELOC_UNUSED, 2, -1,
  25593. + {
  25594. + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
  25595. + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
  25596. + }
  25597. + }
  25598. +
  25599. +};
  25600. +
  25601. +
  25602. +const struct avr32_alias avr32_alias_table[] =
  25603. + {
  25604. + {
  25605. + AVR32_ALIAS_PICOSVMAC0,
  25606. + &avr32_opc_table[AVR32_OPC_COP],
  25607. + {
  25608. + { 0, PICO_CPNO },
  25609. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25610. + { 0, 0x0c },
  25611. + },
  25612. + },
  25613. + {
  25614. + AVR32_ALIAS_PICOSVMAC1,
  25615. + &avr32_opc_table[AVR32_OPC_COP],
  25616. + {
  25617. + { 0, PICO_CPNO },
  25618. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25619. + { 0, 0x0d },
  25620. + },
  25621. + },
  25622. + {
  25623. + AVR32_ALIAS_PICOSVMAC2,
  25624. + &avr32_opc_table[AVR32_OPC_COP],
  25625. + {
  25626. + { 0, PICO_CPNO },
  25627. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25628. + { 0, 0x0e },
  25629. + },
  25630. + },
  25631. + {
  25632. + AVR32_ALIAS_PICOSVMAC3,
  25633. + &avr32_opc_table[AVR32_OPC_COP],
  25634. + {
  25635. + { 0, PICO_CPNO },
  25636. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25637. + { 0, 0x0f },
  25638. + },
  25639. + },
  25640. + {
  25641. + AVR32_ALIAS_PICOSVMUL0,
  25642. + &avr32_opc_table[AVR32_OPC_COP],
  25643. + {
  25644. + { 0, PICO_CPNO },
  25645. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25646. + { 0, 0x08 },
  25647. + },
  25648. + },
  25649. + {
  25650. + AVR32_ALIAS_PICOSVMUL1,
  25651. + &avr32_opc_table[AVR32_OPC_COP],
  25652. + {
  25653. + { 0, PICO_CPNO },
  25654. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25655. + { 0, 0x09 },
  25656. + },
  25657. + },
  25658. + {
  25659. + AVR32_ALIAS_PICOSVMUL2,
  25660. + &avr32_opc_table[AVR32_OPC_COP],
  25661. + {
  25662. + { 0, PICO_CPNO },
  25663. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25664. + { 0, 0x0a },
  25665. + },
  25666. + },
  25667. + {
  25668. + AVR32_ALIAS_PICOSVMUL3,
  25669. + &avr32_opc_table[AVR32_OPC_COP],
  25670. + {
  25671. + { 0, PICO_CPNO },
  25672. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25673. + { 0, 0x0b },
  25674. + },
  25675. + },
  25676. + {
  25677. + AVR32_ALIAS_PICOVMAC0,
  25678. + &avr32_opc_table[AVR32_OPC_COP],
  25679. + {
  25680. + { 0, PICO_CPNO },
  25681. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25682. + { 0, 0x04 },
  25683. + },
  25684. + },
  25685. + {
  25686. + AVR32_ALIAS_PICOVMAC1,
  25687. + &avr32_opc_table[AVR32_OPC_COP],
  25688. + {
  25689. + { 0, PICO_CPNO },
  25690. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25691. + { 0, 0x05 },
  25692. + },
  25693. + },
  25694. + {
  25695. + AVR32_ALIAS_PICOVMAC2,
  25696. + &avr32_opc_table[AVR32_OPC_COP],
  25697. + {
  25698. + { 0, PICO_CPNO },
  25699. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25700. + { 0, 0x06 },
  25701. + },
  25702. + },
  25703. + {
  25704. + AVR32_ALIAS_PICOVMAC3,
  25705. + &avr32_opc_table[AVR32_OPC_COP],
  25706. + {
  25707. + { 0, PICO_CPNO },
  25708. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25709. + { 0, 0x07 },
  25710. + },
  25711. + },
  25712. + {
  25713. + AVR32_ALIAS_PICOVMUL0,
  25714. + &avr32_opc_table[AVR32_OPC_COP],
  25715. + {
  25716. + { 0, PICO_CPNO },
  25717. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25718. + { 0, 0x00 },
  25719. + },
  25720. + },
  25721. + {
  25722. + AVR32_ALIAS_PICOVMUL1,
  25723. + &avr32_opc_table[AVR32_OPC_COP],
  25724. + {
  25725. + { 0, PICO_CPNO },
  25726. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25727. + { 0, 0x01 },
  25728. + },
  25729. + },
  25730. + {
  25731. + AVR32_ALIAS_PICOVMUL2,
  25732. + &avr32_opc_table[AVR32_OPC_COP],
  25733. + {
  25734. + { 0, PICO_CPNO },
  25735. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25736. + { 0, 0x02 },
  25737. + },
  25738. + },
  25739. + {
  25740. + AVR32_ALIAS_PICOVMUL3,
  25741. + &avr32_opc_table[AVR32_OPC_COP],
  25742. + {
  25743. + { 0, PICO_CPNO },
  25744. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25745. + { 0, 0x03 },
  25746. + },
  25747. + },
  25748. + {
  25749. + AVR32_ALIAS_PICOLD_D1,
  25750. + &avr32_opc_table[AVR32_OPC_LDC_D1],
  25751. + {
  25752. + { 0, PICO_CPNO },
  25753. + { 1, 0 }, { 1, 1 },
  25754. + },
  25755. + },
  25756. + {
  25757. + AVR32_ALIAS_PICOLD_D2,
  25758. + &avr32_opc_table[AVR32_OPC_LDC_D2],
  25759. + {
  25760. + { 0, PICO_CPNO },
  25761. + { 1, 0 }, { 1, 1 },
  25762. + },
  25763. + },
  25764. + {
  25765. + AVR32_ALIAS_PICOLD_D3,
  25766. + &avr32_opc_table[AVR32_OPC_LDC_D3],
  25767. + {
  25768. + { 0, PICO_CPNO },
  25769. + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
  25770. + },
  25771. + },
  25772. + {
  25773. + AVR32_ALIAS_PICOLD_W1,
  25774. + &avr32_opc_table[AVR32_OPC_LDC_W1],
  25775. + {
  25776. + { 0, PICO_CPNO },
  25777. + { 1, 0 }, { 1, 1 },
  25778. + },
  25779. + },
  25780. + {
  25781. + AVR32_ALIAS_PICOLD_W2,
  25782. + &avr32_opc_table[AVR32_OPC_LDC_W2],
  25783. + {
  25784. + { 0, PICO_CPNO },
  25785. + { 1, 0 }, { 1, 1 },
  25786. + },
  25787. + },
  25788. + {
  25789. + AVR32_ALIAS_PICOLD_W3,
  25790. + &avr32_opc_table[AVR32_OPC_LDC_W3],
  25791. + {
  25792. + { 0, PICO_CPNO },
  25793. + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
  25794. + },
  25795. + },
  25796. + {
  25797. + AVR32_ALIAS_PICOLDM_D,
  25798. + &avr32_opc_table[AVR32_OPC_LDCM_D],
  25799. + {
  25800. + { 0, PICO_CPNO },
  25801. + { 1, 0 }, { 1, 1 },
  25802. + },
  25803. + },
  25804. + {
  25805. + AVR32_ALIAS_PICOLDM_D_PU,
  25806. + &avr32_opc_table[AVR32_OPC_LDCM_D_PU],
  25807. + {
  25808. + { 0, PICO_CPNO },
  25809. + { 1, 0 }, { 1, 1 },
  25810. + },
  25811. + },
  25812. + {
  25813. + AVR32_ALIAS_PICOLDM_W,
  25814. + &avr32_opc_table[AVR32_OPC_LDCM_W],
  25815. + {
  25816. + { 0, PICO_CPNO },
  25817. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25818. + },
  25819. + },
  25820. + {
  25821. + AVR32_ALIAS_PICOLDM_W_PU,
  25822. + &avr32_opc_table[AVR32_OPC_LDCM_W_PU],
  25823. + {
  25824. + { 0, PICO_CPNO },
  25825. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25826. + },
  25827. + },
  25828. + {
  25829. + AVR32_ALIAS_PICOMV_D1,
  25830. + &avr32_opc_table[AVR32_OPC_MVCR_D],
  25831. + {
  25832. + { 0, PICO_CPNO },
  25833. + { 1, 0 }, { 1, 1 },
  25834. + },
  25835. + },
  25836. + {
  25837. + AVR32_ALIAS_PICOMV_D2,
  25838. + &avr32_opc_table[AVR32_OPC_MVRC_D],
  25839. + {
  25840. + { 0, PICO_CPNO },
  25841. + { 1, 0 }, { 1, 1 },
  25842. + },
  25843. + },
  25844. + {
  25845. + AVR32_ALIAS_PICOMV_W1,
  25846. + &avr32_opc_table[AVR32_OPC_MVCR_W],
  25847. + {
  25848. + { 0, PICO_CPNO },
  25849. + { 1, 0 }, { 1, 1 },
  25850. + },
  25851. + },
  25852. + {
  25853. + AVR32_ALIAS_PICOMV_W2,
  25854. + &avr32_opc_table[AVR32_OPC_MVRC_W],
  25855. + {
  25856. + { 0, PICO_CPNO },
  25857. + { 1, 0 }, { 1, 1 },
  25858. + },
  25859. + },
  25860. + {
  25861. + AVR32_ALIAS_PICOST_D1,
  25862. + &avr32_opc_table[AVR32_OPC_STC_D1],
  25863. + {
  25864. + { 0, PICO_CPNO },
  25865. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25866. + },
  25867. + },
  25868. + {
  25869. + AVR32_ALIAS_PICOST_D2,
  25870. + &avr32_opc_table[AVR32_OPC_STC_D2],
  25871. + {
  25872. + { 0, PICO_CPNO },
  25873. + { 1, 0 }, { 1, 1 },
  25874. + },
  25875. + },
  25876. + {
  25877. + AVR32_ALIAS_PICOST_D3,
  25878. + &avr32_opc_table[AVR32_OPC_STC_D3],
  25879. + {
  25880. + { 0, PICO_CPNO },
  25881. + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
  25882. + },
  25883. + },
  25884. + {
  25885. + AVR32_ALIAS_PICOST_W1,
  25886. + &avr32_opc_table[AVR32_OPC_STC_W1],
  25887. + {
  25888. + { 0, PICO_CPNO },
  25889. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25890. + },
  25891. + },
  25892. + {
  25893. + AVR32_ALIAS_PICOST_W2,
  25894. + &avr32_opc_table[AVR32_OPC_STC_W2],
  25895. + {
  25896. + { 0, PICO_CPNO },
  25897. + { 1, 0 }, { 1, 1 },
  25898. + },
  25899. + },
  25900. + {
  25901. + AVR32_ALIAS_PICOST_W3,
  25902. + &avr32_opc_table[AVR32_OPC_STC_W3],
  25903. + {
  25904. + { 0, PICO_CPNO },
  25905. + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
  25906. + },
  25907. + },
  25908. + {
  25909. + AVR32_ALIAS_PICOSTM_D,
  25910. + &avr32_opc_table[AVR32_OPC_STCM_D],
  25911. + {
  25912. + { 0, PICO_CPNO },
  25913. + { 1, 0 }, { 1, 1 },
  25914. + },
  25915. + },
  25916. + {
  25917. + AVR32_ALIAS_PICOSTM_D_PU,
  25918. + &avr32_opc_table[AVR32_OPC_STCM_D_PU],
  25919. + {
  25920. + { 0, PICO_CPNO },
  25921. + { 1, 0 }, { 1, 1 },
  25922. + },
  25923. + },
  25924. + {
  25925. + AVR32_ALIAS_PICOSTM_W,
  25926. + &avr32_opc_table[AVR32_OPC_STCM_W],
  25927. + {
  25928. + { 0, PICO_CPNO },
  25929. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25930. + },
  25931. + },
  25932. + {
  25933. + AVR32_ALIAS_PICOSTM_W_PU,
  25934. + &avr32_opc_table[AVR32_OPC_STCM_W_PU],
  25935. + {
  25936. + { 0, PICO_CPNO },
  25937. + { 1, 0 }, { 1, 1 }, { 1, 2 },
  25938. + },
  25939. + },
  25940. + };
  25941. +
  25942. +
  25943. +#define SYNTAX_NORMAL0(id, mne, opc, arch) \
  25944. + { \
  25945. + AVR32_SYNTAX_##id, arch, \
  25946. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  25947. + AVR32_PARSER_NORMAL, \
  25948. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  25949. + NULL, 0, { } \
  25950. + }
  25951. +#define SYNTAX_NORMAL1(id, mne, opc, op0, arch) \
  25952. + { \
  25953. + AVR32_SYNTAX_##id, arch, \
  25954. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  25955. + AVR32_PARSER_NORMAL, \
  25956. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  25957. + NULL, 1, \
  25958. + { \
  25959. + AVR32_OPERAND_##op0, \
  25960. + } \
  25961. + }
  25962. +#define SYNTAX_NORMALM1(id, mne, opc, op0, arch) \
  25963. + { \
  25964. + AVR32_SYNTAX_##id, arch, \
  25965. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  25966. + AVR32_PARSER_NORMAL, \
  25967. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  25968. + NULL, -1, \
  25969. + { \
  25970. + AVR32_OPERAND_##op0, \
  25971. + } \
  25972. + }
  25973. +#define SYNTAX_NORMAL2(id, mne, opc, op0, op1, arch) \
  25974. + { \
  25975. + AVR32_SYNTAX_##id, arch, \
  25976. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  25977. + AVR32_PARSER_NORMAL, \
  25978. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  25979. + NULL, 2, \
  25980. + { \
  25981. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  25982. + } \
  25983. + }
  25984. +#define SYNTAX_NORMALM2(id, mne, opc, op0, op1, arch) \
  25985. + { \
  25986. + AVR32_SYNTAX_##id, arch, \
  25987. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  25988. + AVR32_PARSER_NORMAL, \
  25989. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  25990. + NULL, -2, \
  25991. + { \
  25992. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  25993. + } \
  25994. + }
  25995. +#define SYNTAX_NORMAL3(id, mne, opc, op0, op1, op2, arch) \
  25996. + { \
  25997. + AVR32_SYNTAX_##id, arch, \
  25998. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  25999. + AVR32_PARSER_NORMAL, \
  26000. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26001. + NULL, 3, \
  26002. + { \
  26003. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26004. + AVR32_OPERAND_##op2, \
  26005. + } \
  26006. + }
  26007. +#define SYNTAX_NORMALM3(id, mne, opc, op0, op1, op2, arch) \
  26008. + { \
  26009. + AVR32_SYNTAX_##id, arch, \
  26010. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26011. + AVR32_PARSER_NORMAL, \
  26012. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26013. + NULL, -3, \
  26014. + { \
  26015. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26016. + AVR32_OPERAND_##op2, \
  26017. + } \
  26018. + }
  26019. +#define SYNTAX_NORMAL4(id, mne, opc, op0, op1, op2, op3, arch)\
  26020. + { \
  26021. + AVR32_SYNTAX_##id, arch, \
  26022. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26023. + AVR32_PARSER_NORMAL, \
  26024. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26025. + NULL, 4, \
  26026. + { \
  26027. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26028. + AVR32_OPERAND_##op2, AVR32_OPERAND_##op3, \
  26029. + } \
  26030. + }
  26031. +#define SYNTAX_NORMAL5(id, mne, opc, op0, op1, op2, op3, op4, arch) \
  26032. + { \
  26033. + AVR32_SYNTAX_##id, arch, \
  26034. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26035. + AVR32_PARSER_NORMAL, \
  26036. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26037. + NULL, 5, \
  26038. + { \
  26039. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26040. + AVR32_OPERAND_##op2, AVR32_OPERAND_##op3, \
  26041. + AVR32_OPERAND_##op4, \
  26042. + } \
  26043. + }
  26044. +
  26045. +#define SYNTAX_NORMAL_C1(id, mne, opc, nxt, op0, arch) \
  26046. + { \
  26047. + AVR32_SYNTAX_##id, arch, \
  26048. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26049. + AVR32_PARSER_NORMAL, \
  26050. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26051. + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 1, \
  26052. + { \
  26053. + AVR32_OPERAND_##op0, \
  26054. + } \
  26055. + }
  26056. +#define SYNTAX_NORMAL_CM1(id, mne, opc, nxt, op0, arch) \
  26057. + { \
  26058. + AVR32_SYNTAX_##id, arch, \
  26059. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26060. + AVR32_PARSER_NORMAL, \
  26061. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26062. + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -1, \
  26063. + { \
  26064. + AVR32_OPERAND_##op0, \
  26065. + } \
  26066. + }
  26067. +#define SYNTAX_NORMAL_C2(id, mne, opc, nxt, op0, op1, arch) \
  26068. + { \
  26069. + AVR32_SYNTAX_##id, arch, \
  26070. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26071. + AVR32_PARSER_NORMAL, \
  26072. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26073. + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 2, \
  26074. + { \
  26075. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26076. + } \
  26077. + }
  26078. +#define SYNTAX_NORMAL_CM2(id, mne, opc, nxt, op0, op1, arch) \
  26079. + { \
  26080. + AVR32_SYNTAX_##id, arch, \
  26081. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26082. + AVR32_PARSER_NORMAL, \
  26083. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26084. + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -2, \
  26085. + { \
  26086. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26087. + } \
  26088. + }
  26089. +#define SYNTAX_NORMAL_C3(id, mne, opc, nxt, op0, op1, op2, arch) \
  26090. + { \
  26091. + AVR32_SYNTAX_##id, arch, \
  26092. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26093. + AVR32_PARSER_NORMAL, \
  26094. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26095. + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 3, \
  26096. + { \
  26097. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26098. + AVR32_OPERAND_##op2, \
  26099. + } \
  26100. + }
  26101. +#define SYNTAX_NORMAL_CM3(id, mne, opc, nxt, op0, op1, op2, arch) \
  26102. + { \
  26103. + AVR32_SYNTAX_##id, arch, \
  26104. + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
  26105. + AVR32_PARSER_NORMAL, \
  26106. + { &avr32_opc_table[AVR32_OPC_##opc], }, \
  26107. + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -3, \
  26108. + { \
  26109. + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
  26110. + AVR32_OPERAND_##op2, \
  26111. + } \
  26112. + }
  26113. +
  26114. +
  26115. +const struct avr32_syntax avr32_syntax_table[] =
  26116. + {
  26117. + SYNTAX_NORMAL1(ABS, ABS, ABS, INTREG, AVR32_V1),
  26118. + SYNTAX_NORMAL1(ACALL, ACALL, ACALL, UNSIGNED_CONST_W, AVR32_V1),
  26119. + SYNTAX_NORMAL1(ACR, ACR, ACR, INTREG,AVR32_V1),
  26120. + SYNTAX_NORMAL3(ADC, ADC, ADC, INTREG, INTREG, INTREG, AVR32_V1),
  26121. + SYNTAX_NORMAL_C2(ADD1, ADD, ADD1, ADD2, INTREG, INTREG, AVR32_V1),
  26122. + SYNTAX_NORMAL3(ADD2, ADD, ADD2, INTREG, INTREG, INTREG_LSL, AVR32_V1),
  26123. + SYNTAX_NORMAL3(ADDABS, ADDABS, ADDABS, INTREG, INTREG, INTREG, AVR32_V1),
  26124. + SYNTAX_NORMAL3(ADDHH_W, ADDHH_W, ADDHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26125. + SYNTAX_NORMAL_C2(AND1, AND, AND1, AND2, INTREG, INTREG, AVR32_V1),
  26126. + SYNTAX_NORMAL_C3(AND2, AND, AND2, AND3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
  26127. + SYNTAX_NORMAL3(AND3, AND, AND3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
  26128. + SYNTAX_NORMAL_C2(ANDH, ANDH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
  26129. + SYNTAX_NORMAL3(ANDH_COH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
  26130. + SYNTAX_NORMAL_C2(ANDL, ANDL, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
  26131. + SYNTAX_NORMAL3(ANDL_COH, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
  26132. + SYNTAX_NORMAL2(ANDN, ANDN, ANDN, INTREG, INTREG, AVR32_V1),
  26133. + SYNTAX_NORMAL_C3(ASR1, ASR, ASR1, ASR3, INTREG, INTREG, INTREG, AVR32_V1),
  26134. + SYNTAX_NORMAL_C3(ASR3, ASR, ASR3, ASR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26135. + SYNTAX_NORMAL2(ASR2, ASR, ASR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26136. + SYNTAX_NORMAL4(BFEXTS, BFEXTS, BFEXTS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
  26137. + SYNTAX_NORMAL4(BFEXTU, BFEXTU, BFEXTU, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
  26138. + SYNTAX_NORMAL4(BFINS, BFINS, BFINS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
  26139. + SYNTAX_NORMAL2(BLD, BLD, BLD, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26140. + SYNTAX_NORMAL_C1(BREQ1, BREQ, BREQ1, BREQ2, JMPLABEL, AVR32_V1),
  26141. + SYNTAX_NORMAL_C1(BRNE1, BRNE, BRNE1, BRNE2, JMPLABEL, AVR32_V1),
  26142. + SYNTAX_NORMAL_C1(BRCC1, BRCC, BRCC1, BRCC2, JMPLABEL, AVR32_V1),
  26143. + SYNTAX_NORMAL_C1(BRCS1, BRCS, BRCS1, BRCS2, JMPLABEL, AVR32_V1),
  26144. + SYNTAX_NORMAL_C1(BRGE1, BRGE, BRGE1, BRGE2, JMPLABEL, AVR32_V1),
  26145. + SYNTAX_NORMAL_C1(BRLT1, BRLT, BRLT1, BRLT2, JMPLABEL, AVR32_V1),
  26146. + SYNTAX_NORMAL_C1(BRMI1, BRMI, BRMI1, BRMI2, JMPLABEL, AVR32_V1),
  26147. + SYNTAX_NORMAL_C1(BRPL1, BRPL, BRPL1, BRPL2, JMPLABEL, AVR32_V1),
  26148. + SYNTAX_NORMAL_C1(BRHS1, BRHS, BRCC1, BRHS2, JMPLABEL, AVR32_V1),
  26149. + SYNTAX_NORMAL_C1(BRLO1, BRLO, BRCS1, BRLO2, JMPLABEL, AVR32_V1),
  26150. + SYNTAX_NORMAL1(BREQ2, BREQ, BREQ2, JMPLABEL, AVR32_V1),
  26151. + SYNTAX_NORMAL1(BRNE2, BRNE, BRNE2, JMPLABEL, AVR32_V1),
  26152. + SYNTAX_NORMAL1(BRCC2, BRCC, BRCC2, JMPLABEL, AVR32_V1),
  26153. + SYNTAX_NORMAL1(BRCS2, BRCS, BRCS2, JMPLABEL, AVR32_V1),
  26154. + SYNTAX_NORMAL1(BRGE2, BRGE, BRGE2, JMPLABEL, AVR32_V1),
  26155. + SYNTAX_NORMAL1(BRLT2, BRLT, BRLT2, JMPLABEL, AVR32_V1),
  26156. + SYNTAX_NORMAL1(BRMI2, BRMI, BRMI2, JMPLABEL, AVR32_V1),
  26157. + SYNTAX_NORMAL1(BRPL2, BRPL, BRPL2, JMPLABEL, AVR32_V1),
  26158. + SYNTAX_NORMAL1(BRLS, BRLS, BRLS, JMPLABEL, AVR32_V1),
  26159. + SYNTAX_NORMAL1(BRGT, BRGT, BRGT, JMPLABEL, AVR32_V1),
  26160. + SYNTAX_NORMAL1(BRLE, BRLE, BRLE, JMPLABEL, AVR32_V1),
  26161. + SYNTAX_NORMAL1(BRHI, BRHI, BRHI, JMPLABEL, AVR32_V1),
  26162. + SYNTAX_NORMAL1(BRVS, BRVS, BRVS, JMPLABEL, AVR32_V1),
  26163. + SYNTAX_NORMAL1(BRVC, BRVC, BRVC, JMPLABEL, AVR32_V1),
  26164. + SYNTAX_NORMAL1(BRQS, BRQS, BRQS, JMPLABEL, AVR32_V1),
  26165. + SYNTAX_NORMAL1(BRAL, BRAL, BRAL, JMPLABEL, AVR32_V1),
  26166. + SYNTAX_NORMAL1(BRHS2, BRHS, BRCC2, JMPLABEL, AVR32_V1),
  26167. + SYNTAX_NORMAL1(BRLO2, BRLO, BRCS2, JMPLABEL, AVR32_V1),
  26168. + SYNTAX_NORMAL0(BREAKPOINT, BREAKPOINT, BREAKPOINT, AVR32_V1),
  26169. + SYNTAX_NORMAL1(BREV, BREV, BREV, INTREG, AVR32_V1),
  26170. + SYNTAX_NORMAL2(BST, BST, BST, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26171. + SYNTAX_NORMAL2(CACHE, CACHE, CACHE, INTREG_SDISP, UNSIGNED_NUMBER, AVR32_V1),
  26172. + SYNTAX_NORMAL1(CASTS_B, CASTS_B, CASTS_B, INTREG, AVR32_V1),
  26173. + SYNTAX_NORMAL1(CASTS_H, CASTS_H, CASTS_H, INTREG, AVR32_V1),
  26174. + SYNTAX_NORMAL1(CASTU_B, CASTU_B, CASTU_B, INTREG, AVR32_V1),
  26175. + SYNTAX_NORMAL1(CASTU_H, CASTU_H, CASTU_H, INTREG, AVR32_V1),
  26176. + SYNTAX_NORMAL2(CBR, CBR, CBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26177. + SYNTAX_NORMAL2(CLZ, CLZ, CLZ, INTREG, INTREG, AVR32_V1),
  26178. + SYNTAX_NORMAL1(COM, COM, COM, INTREG, AVR32_V1),
  26179. + SYNTAX_NORMAL5(COP, COP, COP, CPNO, CPREG, CPREG, CPREG, UNSIGNED_NUMBER, AVR32_V1),
  26180. + SYNTAX_NORMAL2(CP_B, CP_B, CP_B, INTREG, INTREG, AVR32_V1),
  26181. + SYNTAX_NORMAL2(CP_H, CP_H, CP_H, INTREG, INTREG, AVR32_V1),
  26182. + SYNTAX_NORMAL_C2(CP_W1, CP_W, CP_W1, CP_W2, INTREG, INTREG, AVR32_V1),
  26183. + SYNTAX_NORMAL_C2(CP_W2, CP_W, CP_W2, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
  26184. + SYNTAX_NORMAL2(CP_W3, CP_W, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
  26185. + SYNTAX_NORMAL_C2(CPC1, CPC, CPC1, CPC2, INTREG, INTREG, AVR32_V1),
  26186. + SYNTAX_NORMAL1(CPC2, CPC, CPC2, INTREG, AVR32_V1),
  26187. + SYNTAX_NORMAL1(CSRF, CSRF, CSRF, UNSIGNED_NUMBER, AVR32_V1),
  26188. + SYNTAX_NORMAL1(CSRFCZ, CSRFCZ, CSRFCZ, UNSIGNED_NUMBER, AVR32_V1),
  26189. + SYNTAX_NORMAL3(DIVS, DIVS, DIVS, INTREG, INTREG, INTREG, AVR32_V1),
  26190. + SYNTAX_NORMAL3(DIVU, DIVU, DIVU, INTREG, INTREG, INTREG, AVR32_V1),
  26191. + SYNTAX_NORMAL_C2(EOR1, EOR, EOR1, EOR2, INTREG, INTREG, AVR32_V1),
  26192. + SYNTAX_NORMAL_C3(EOR2, EOR, EOR2, EOR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
  26193. + SYNTAX_NORMAL3(EOR3, EOR, EOR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
  26194. + SYNTAX_NORMAL2(EORL, EORL, EORL, INTREG, UNSIGNED_CONST, AVR32_V1),
  26195. + SYNTAX_NORMAL2(EORH, EORH, EORH, INTREG, UNSIGNED_CONST, AVR32_V1),
  26196. + SYNTAX_NORMAL0(FRS, FRS, FRS, AVR32_V1),
  26197. + SYNTAX_NORMAL0(SSCALL, SSCALL, SSCALL, AVR32_V3),
  26198. + SYNTAX_NORMAL0(RETSS, RETSS, RETSS, AVR32_V3),
  26199. + SYNTAX_NORMAL1(ICALL, ICALL, ICALL, INTREG, AVR32_V1),
  26200. + SYNTAX_NORMAL1(INCJOSP, INCJOSP, INCJOSP, JOSPINC, AVR32_V1),
  26201. + SYNTAX_NORMAL_C2(LD_D1, LD_D, LD_D1, LD_D2, DWREG, INTREG_POSTINC, AVR32_V1),
  26202. + SYNTAX_NORMAL_C2(LD_D2, LD_D, LD_D2, LD_D3, DWREG, INTREG_PREDEC, AVR32_V1),
  26203. + SYNTAX_NORMAL_C2(LD_D3, LD_D, LD_D3, LD_D5, DWREG, INTREG, AVR32_V1),
  26204. + SYNTAX_NORMAL_C2(LD_D5, LD_D, LD_D5, LD_D4, DWREG, INTREG_INDEX, AVR32_V1),
  26205. + SYNTAX_NORMAL2(LD_D4, LD_D, LD_D4, DWREG, INTREG_SDISP, AVR32_V1),
  26206. + SYNTAX_NORMAL_C2(LD_SB2, LD_SB, LD_SB2, LD_SB1, INTREG, INTREG_INDEX, AVR32_V1),
  26207. + SYNTAX_NORMAL2(LD_SB1, LD_SB, LD_SB1, INTREG, INTREG_SDISP, AVR32_V1),
  26208. + SYNTAX_NORMAL_C2(LD_UB1, LD_UB, LD_UB1, LD_UB2, INTREG, INTREG_POSTINC, AVR32_V1),
  26209. + SYNTAX_NORMAL_C2(LD_UB2, LD_UB, LD_UB2, LD_UB5, INTREG, INTREG_PREDEC, AVR32_V1),
  26210. + SYNTAX_NORMAL_C2(LD_UB5, LD_UB, LD_UB5, LD_UB3, INTREG, INTREG_INDEX, AVR32_V1),
  26211. + SYNTAX_NORMAL_C2(LD_UB3, LD_UB, LD_UB3, LD_UB4, INTREG, INTREG_UDISP, AVR32_V1),
  26212. + SYNTAX_NORMAL2(LD_UB4, LD_UB, LD_UB4, INTREG, INTREG_SDISP, AVR32_V1),
  26213. + SYNTAX_NORMAL_C2(LD_SH1, LD_SH, LD_SH1, LD_SH2, INTREG, INTREG_POSTINC, AVR32_V1),
  26214. + SYNTAX_NORMAL_C2(LD_SH2, LD_SH, LD_SH2, LD_SH5, INTREG, INTREG_PREDEC, AVR32_V1),
  26215. + SYNTAX_NORMAL_C2(LD_SH5, LD_SH, LD_SH5, LD_SH3, INTREG, INTREG_INDEX, AVR32_V1),
  26216. + SYNTAX_NORMAL_C2(LD_SH3, LD_SH, LD_SH3, LD_SH4, INTREG, INTREG_UDISP_H, AVR32_V1),
  26217. + SYNTAX_NORMAL2(LD_SH4, LD_SH, LD_SH4, INTREG, INTREG_SDISP, AVR32_V1),
  26218. + SYNTAX_NORMAL_C2(LD_UH1, LD_UH, LD_UH1, LD_UH2, INTREG, INTREG_POSTINC, AVR32_V1),
  26219. + SYNTAX_NORMAL_C2(LD_UH2, LD_UH, LD_UH2, LD_UH5, INTREG, INTREG_PREDEC, AVR32_V1),
  26220. + SYNTAX_NORMAL_C2(LD_UH5, LD_UH, LD_UH5, LD_UH3, INTREG, INTREG_INDEX, AVR32_V1),
  26221. + SYNTAX_NORMAL_C2(LD_UH3, LD_UH, LD_UH3, LD_UH4, INTREG, INTREG_UDISP_H, AVR32_V1),
  26222. + SYNTAX_NORMAL2(LD_UH4, LD_UH, LD_UH4, INTREG, INTREG_SDISP, AVR32_V1),
  26223. + SYNTAX_NORMAL_C2(LD_W1, LD_W, LD_W1, LD_W2, INTREG, INTREG_POSTINC, AVR32_V1),
  26224. + SYNTAX_NORMAL_C2(LD_W2, LD_W, LD_W2, LD_W5, INTREG, INTREG_PREDEC, AVR32_V1),
  26225. + SYNTAX_NORMAL_C2(LD_W5, LD_W, LD_W5, LD_W6, INTREG, INTREG_INDEX, AVR32_V1),
  26226. + SYNTAX_NORMAL_C2(LD_W6, LD_W, LD_W6, LD_W3, INTREG, INTREG_XINDEX, AVR32_V1),
  26227. + SYNTAX_NORMAL_C2(LD_W3, LD_W, LD_W3, LD_W4, INTREG, INTREG_UDISP_W, AVR32_V1),
  26228. + SYNTAX_NORMAL2(LD_W4, LD_W, LD_W4, INTREG, INTREG_SDISP, AVR32_V1),
  26229. + SYNTAX_NORMAL3(LDC_D1, LDC_D, LDC_D1, CPNO, CPREG_D, INTREG_UDISP_W, AVR32_V1),
  26230. + SYNTAX_NORMAL_C3(LDC_D2, LDC_D, LDC_D2, LDC_D1, CPNO, CPREG_D, INTREG_PREDEC, AVR32_V1),
  26231. + SYNTAX_NORMAL_C3(LDC_D3, LDC_D, LDC_D3, LDC_D2, CPNO, CPREG_D, INTREG_INDEX, AVR32_V1),
  26232. + SYNTAX_NORMAL3(LDC_W1, LDC_W, LDC_W1, CPNO, CPREG, INTREG_UDISP_W, AVR32_V1),
  26233. + SYNTAX_NORMAL_C3(LDC_W2, LDC_W, LDC_W2, LDC_W1, CPNO, CPREG, INTREG_PREDEC, AVR32_V1),
  26234. + SYNTAX_NORMAL_C3(LDC_W3, LDC_W, LDC_W3, LDC_W2, CPNO, CPREG, INTREG_INDEX, AVR32_V1),
  26235. + SYNTAX_NORMAL2(LDC0_D, LDC0_D, LDC0_D, CPREG_D, INTREG_UDISP_W, AVR32_V1),
  26236. + SYNTAX_NORMAL2(LDC0_W, LDC0_W, LDC0_W, CPREG, INTREG_UDISP_W, AVR32_V1),
  26237. + SYNTAX_NORMAL_CM3(LDCM_D, LDCM_D, LDCM_D, LDCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
  26238. + SYNTAX_NORMALM3(LDCM_D_PU, LDCM_D, LDCM_D_PU, CPNO, INTREG_POSTINC, REGLIST_CPD8, AVR32_V1),
  26239. + SYNTAX_NORMAL_CM3(LDCM_W, LDCM_W, LDCM_W, LDCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
  26240. + SYNTAX_NORMALM3(LDCM_W_PU, LDCM_W, LDCM_W_PU, CPNO, INTREG_POSTINC, REGLIST_CP8, AVR32_V1),
  26241. + SYNTAX_NORMAL2(LDDPC, LDDPC, LDDPC, INTREG, PC_UDISP_W, AVR32_V1),
  26242. + SYNTAX_NORMAL2(LDDPC_EXT, LDDPC, LDDPC_EXT, INTREG, SIGNED_CONST, AVR32_V1),
  26243. + SYNTAX_NORMAL2(LDDSP, LDDSP, LDDSP, INTREG, SP_UDISP_W, AVR32_V1),
  26244. + SYNTAX_NORMAL2(LDINS_B, LDINS_B, LDINS_B, INTREG_BSEL, INTREG_SDISP, AVR32_V1),
  26245. + SYNTAX_NORMAL2(LDINS_H, LDINS_H, LDINS_H, INTREG_HSEL, INTREG_SDISP_H, AVR32_V1),
  26246. + SYNTAX_NORMALM1(LDM, LDM, LDM, REGLIST_LDM, AVR32_V1),
  26247. + SYNTAX_NORMAL_CM2(LDMTS, LDMTS, LDMTS, LDMTS_PU, INTREG, REGLIST16, AVR32_V1),
  26248. + SYNTAX_NORMALM2(LDMTS_PU, LDMTS, LDMTS_PU, INTREG_POSTINC, REGLIST16, AVR32_V1),
  26249. + SYNTAX_NORMAL2(LDSWP_SH, LDSWP_SH, LDSWP_SH, INTREG, INTREG_SDISP_H, AVR32_V1),
  26250. + SYNTAX_NORMAL2(LDSWP_UH, LDSWP_UH, LDSWP_UH, INTREG, INTREG_SDISP_H, AVR32_V1),
  26251. + SYNTAX_NORMAL2(LDSWP_W, LDSWP_W, LDSWP_W, INTREG, INTREG_SDISP_W, AVR32_V1),
  26252. + SYNTAX_NORMAL_C3(LSL1, LSL, LSL1, LSL3, INTREG, INTREG, INTREG, AVR32_V1),
  26253. + SYNTAX_NORMAL_C3(LSL3, LSL, LSL3, LSL2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26254. + SYNTAX_NORMAL2(LSL2, LSL, LSL2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26255. + SYNTAX_NORMAL_C3(LSR1, LSR, LSR1, LSR3, INTREG, INTREG, INTREG, AVR32_V1),
  26256. + SYNTAX_NORMAL_C3(LSR3, LSR, LSR3, LSR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26257. + SYNTAX_NORMAL2(LSR2, LSR, LSR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26258. + SYNTAX_NORMAL3(MAC, MAC, MAC, INTREG, INTREG, INTREG, AVR32_V1),
  26259. + SYNTAX_NORMAL3(MACHH_D, MACHH_D, MACHH_D, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26260. + SYNTAX_NORMAL3(MACHH_W, MACHH_W, MACHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26261. + SYNTAX_NORMAL3(MACS_D, MACS_D, MACS_D, INTREG, INTREG, INTREG, AVR32_V1),
  26262. + SYNTAX_NORMAL3(MACSATHH_W, MACSATHH_W, MACSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26263. + SYNTAX_NORMAL3(MACUD, MACU_D, MACUD, INTREG, INTREG, INTREG, AVR32_V1),
  26264. + SYNTAX_NORMAL3(MACWH_D, MACWH_D, MACWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
  26265. + SYNTAX_NORMAL3(MAX, MAX, MAX, INTREG, INTREG, INTREG, AVR32_V1),
  26266. + SYNTAX_NORMAL1(MCALL, MCALL, MCALL, MCALL, AVR32_V1),
  26267. + SYNTAX_NORMAL2(MFDR, MFDR, MFDR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
  26268. + SYNTAX_NORMAL2(MFSR, MFSR, MFSR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
  26269. + SYNTAX_NORMAL3(MIN, MIN, MIN, INTREG, INTREG, INTREG, AVR32_V1),
  26270. + SYNTAX_NORMAL_C2(MOV3, MOV, MOV3, MOV1, INTREG, INTREG, AVR32_V1),
  26271. + SYNTAX_NORMAL_C2(MOV1, MOV, MOV1, MOV2, INTREG, SIGNED_CONST, AVR32_V1),
  26272. + SYNTAX_NORMAL2(MOV2, MOV, MOV2,INTREG, SIGNED_CONST, AVR32_V1),
  26273. + SYNTAX_NORMAL_C2(MOVEQ1, MOVEQ, MOVEQ1, MOVEQ2, INTREG, INTREG, AVR32_V1),
  26274. + SYNTAX_NORMAL_C2(MOVNE1, MOVNE, MOVNE1, MOVNE2, INTREG, INTREG, AVR32_V1),
  26275. + SYNTAX_NORMAL_C2(MOVCC1, MOVCC, MOVCC1, MOVCC2, INTREG, INTREG, AVR32_V1),
  26276. + SYNTAX_NORMAL_C2(MOVCS1, MOVCS, MOVCS1, MOVCS2, INTREG, INTREG, AVR32_V1),
  26277. + SYNTAX_NORMAL_C2(MOVGE1, MOVGE, MOVGE1, MOVGE2, INTREG, INTREG, AVR32_V1),
  26278. + SYNTAX_NORMAL_C2(MOVLT1, MOVLT, MOVLT1, MOVLT2, INTREG, INTREG, AVR32_V1),
  26279. + SYNTAX_NORMAL_C2(MOVMI1, MOVMI, MOVMI1, MOVMI2, INTREG, INTREG, AVR32_V1),
  26280. + SYNTAX_NORMAL_C2(MOVPL1, MOVPL, MOVPL1, MOVPL2, INTREG, INTREG, AVR32_V1),
  26281. + SYNTAX_NORMAL_C2(MOVLS1, MOVLS, MOVLS1, MOVLS2, INTREG, INTREG, AVR32_V1),
  26282. + SYNTAX_NORMAL_C2(MOVGT1, MOVGT, MOVGT1, MOVGT2, INTREG, INTREG, AVR32_V1),
  26283. + SYNTAX_NORMAL_C2(MOVLE1, MOVLE, MOVLE1, MOVLE2, INTREG, INTREG, AVR32_V1),
  26284. + SYNTAX_NORMAL_C2(MOVHI1, MOVHI, MOVHI1, MOVHI2, INTREG, INTREG, AVR32_V1),
  26285. + SYNTAX_NORMAL_C2(MOVVS1, MOVVS, MOVVS1, MOVVS2, INTREG, INTREG, AVR32_V1),
  26286. + SYNTAX_NORMAL_C2(MOVVC1, MOVVC, MOVVC1, MOVVC2, INTREG, INTREG, AVR32_V1),
  26287. + SYNTAX_NORMAL_C2(MOVQS1, MOVQS, MOVQS1, MOVQS2, INTREG, INTREG, AVR32_V1),
  26288. + SYNTAX_NORMAL_C2(MOVAL1, MOVAL, MOVAL1, MOVAL2, INTREG, INTREG, AVR32_V1),
  26289. + SYNTAX_NORMAL_C2(MOVHS1, MOVHS, MOVCC1, MOVHS2, INTREG, INTREG, AVR32_V1),
  26290. + SYNTAX_NORMAL_C2(MOVLO1, MOVLO, MOVCS1, MOVLO2, INTREG, INTREG, AVR32_V1),
  26291. + SYNTAX_NORMAL2(MOVEQ2, MOVEQ, MOVEQ2, INTREG, SIGNED_CONST, AVR32_V1),
  26292. + SYNTAX_NORMAL2(MOVNE2, MOVNE, MOVNE2, INTREG, SIGNED_CONST, AVR32_V1),
  26293. + SYNTAX_NORMAL2(MOVCC2, MOVCC, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
  26294. + SYNTAX_NORMAL2(MOVCS2, MOVCS, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
  26295. + SYNTAX_NORMAL2(MOVGE2, MOVGE, MOVGE2, INTREG, SIGNED_CONST, AVR32_V1),
  26296. + SYNTAX_NORMAL2(MOVLT2, MOVLT, MOVLT2, INTREG, SIGNED_CONST, AVR32_V1),
  26297. + SYNTAX_NORMAL2(MOVMI2, MOVMI, MOVMI2, INTREG, SIGNED_CONST, AVR32_V1),
  26298. + SYNTAX_NORMAL2(MOVPL2, MOVPL, MOVPL2, INTREG, SIGNED_CONST, AVR32_V1),
  26299. + SYNTAX_NORMAL2(MOVLS2, MOVLS, MOVLS2, INTREG, SIGNED_CONST, AVR32_V1),
  26300. + SYNTAX_NORMAL2(MOVGT2, MOVGT, MOVGT2, INTREG, SIGNED_CONST, AVR32_V1),
  26301. + SYNTAX_NORMAL2(MOVLE2, MOVLE, MOVLE2, INTREG, SIGNED_CONST, AVR32_V1),
  26302. + SYNTAX_NORMAL2(MOVHI2, MOVHI, MOVHI2, INTREG, SIGNED_CONST, AVR32_V1),
  26303. + SYNTAX_NORMAL2(MOVVS2, MOVVS, MOVVS2, INTREG, SIGNED_CONST, AVR32_V1),
  26304. + SYNTAX_NORMAL2(MOVVC2, MOVVC, MOVVC2, INTREG, SIGNED_CONST, AVR32_V1),
  26305. + SYNTAX_NORMAL2(MOVQS2, MOVQS, MOVQS2, INTREG, SIGNED_CONST, AVR32_V1),
  26306. + SYNTAX_NORMAL2(MOVAL2, MOVAL, MOVAL2, INTREG, SIGNED_CONST, AVR32_V1),
  26307. + SYNTAX_NORMAL2(MOVHS2, MOVHS, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
  26308. + SYNTAX_NORMAL2(MOVLO2, MOVLO, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
  26309. + SYNTAX_NORMAL2(MTDR, MTDR, MTDR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
  26310. + SYNTAX_NORMAL2(MTSR, MTSR, MTSR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
  26311. + SYNTAX_NORMAL_C2(MUL1, MUL, MUL1, MUL2, INTREG, INTREG, AVR32_V1),
  26312. + SYNTAX_NORMAL_C3(MUL2, MUL, MUL2, MUL3, INTREG, INTREG, INTREG, AVR32_V1),
  26313. + SYNTAX_NORMAL3(MUL3, MUL, MUL3, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
  26314. + SYNTAX_NORMAL3(MULHH_W, MULHH_W, MULHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26315. + SYNTAX_NORMAL3(MULNHH_W, MULNHH_W, MULNHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26316. + SYNTAX_NORMAL3(MULNWH_D, MULNWH_D, MULNWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
  26317. + SYNTAX_NORMAL3(MULSD, MULS_D, MULSD, INTREG, INTREG, INTREG, AVR32_V1),
  26318. + SYNTAX_NORMAL3(MULSATHH_H, MULSATHH_H, MULSATHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26319. + SYNTAX_NORMAL3(MULSATHH_W, MULSATHH_W, MULSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26320. + SYNTAX_NORMAL3(MULSATRNDHH_H, MULSATRNDHH_H, MULSATRNDHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26321. + SYNTAX_NORMAL3(MULSATRNDWH_W, MULSATRNDWH_W, MULSATRNDWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
  26322. + SYNTAX_NORMAL3(MULSATWH_W, MULSATWH_W, MULSATWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
  26323. + SYNTAX_NORMAL3(MULU_D, MULU_D, MULU_D, INTREG, INTREG, INTREG, AVR32_V1),
  26324. + SYNTAX_NORMAL3(MULWH_D, MULWH_D, MULWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
  26325. + SYNTAX_NORMAL1(MUSFR, MUSFR, MUSFR, INTREG, AVR32_V1),
  26326. + SYNTAX_NORMAL1(MUSTR, MUSTR, MUSTR, INTREG, AVR32_V1),
  26327. + SYNTAX_NORMAL3(MVCR_D, MVCR_D, MVCR_D, CPNO, DWREG, CPREG_D, AVR32_V1),
  26328. + SYNTAX_NORMAL3(MVCR_W, MVCR_W, MVCR_W, CPNO, INTREG, CPREG, AVR32_V1),
  26329. + SYNTAX_NORMAL3(MVRC_D, MVRC_D, MVRC_D, CPNO, CPREG_D, DWREG, AVR32_V1),
  26330. + SYNTAX_NORMAL3(MVRC_W, MVRC_W, MVRC_W, CPNO, CPREG, INTREG, AVR32_V1),
  26331. + SYNTAX_NORMAL1(NEG, NEG, NEG, INTREG, AVR32_V1),
  26332. + SYNTAX_NORMAL0(NOP, NOP, NOP, AVR32_V1),
  26333. + SYNTAX_NORMAL_C2(OR1, OR, OR1, OR2, INTREG, INTREG, AVR32_V1),
  26334. + SYNTAX_NORMAL_C3(OR2, OR, OR2, OR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
  26335. + SYNTAX_NORMAL3(OR3, OR, OR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
  26336. + SYNTAX_NORMAL2(ORH, ORH, ORH, INTREG, UNSIGNED_CONST, AVR32_V1),
  26337. + SYNTAX_NORMAL2(ORL, ORL, ORL, INTREG, UNSIGNED_CONST, AVR32_V1),
  26338. + SYNTAX_NORMAL2(PABS_SB, PABS_SB, PABS_SB, INTREG, INTREG, AVR32_SIMD),
  26339. + SYNTAX_NORMAL2(PABS_SH, PABS_SH, PABS_SH, INTREG, INTREG, AVR32_SIMD),
  26340. + SYNTAX_NORMAL3(PACKSH_SB, PACKSH_SB, PACKSH_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26341. + SYNTAX_NORMAL3(PACKSH_UB, PACKSH_UB, PACKSH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26342. + SYNTAX_NORMAL3(PACKW_SH, PACKW_SH, PACKW_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26343. + SYNTAX_NORMAL3(PADD_B, PADD_B, PADD_B, INTREG, INTREG, INTREG, AVR32_SIMD),
  26344. + SYNTAX_NORMAL3(PADD_H, PADD_H, PADD_H, INTREG, INTREG, INTREG, AVR32_SIMD),
  26345. + SYNTAX_NORMAL3(PADDH_SH, PADDH_SH, PADDH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26346. + SYNTAX_NORMAL3(PADDH_UB, PADDH_UB, PADDH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26347. + SYNTAX_NORMAL3(PADDS_SB, PADDS_SB, PADDS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26348. + SYNTAX_NORMAL3(PADDS_SH, PADDS_SH, PADDS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26349. + SYNTAX_NORMAL3(PADDS_UB, PADDS_UB, PADDS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26350. + SYNTAX_NORMAL3(PADDS_UH, PADDS_UH, PADDS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26351. + SYNTAX_NORMAL3(PADDSUB_H, PADDSUB_H, PADDSUB_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26352. + SYNTAX_NORMAL3(PADDSUBH_SH, PADDSUBH_SH, PADDSUBH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26353. + SYNTAX_NORMAL3(PADDSUBS_SH, PADDSUBS_SH, PADDSUBS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26354. + SYNTAX_NORMAL3(PADDSUBS_UH, PADDSUBS_UH, PADDSUBS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26355. + SYNTAX_NORMAL3(PADDX_H, PADDX_H, PADDX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
  26356. + SYNTAX_NORMAL3(PADDXH_SH, PADDXH_SH, PADDXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26357. + SYNTAX_NORMAL3(PADDXS_SH, PADDXS_SH, PADDXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26358. + SYNTAX_NORMAL3(PADDXS_UH, PADDXS_UH, PADDXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26359. + SYNTAX_NORMAL3(PASR_B, PASR_B, PASR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
  26360. + SYNTAX_NORMAL3(PASR_H, PASR_H, PASR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
  26361. + SYNTAX_NORMAL3(PAVG_SH, PAVG_SH, PAVG_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26362. + SYNTAX_NORMAL3(PAVG_UB, PAVG_UB, PAVG_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26363. + SYNTAX_NORMAL3(PLSL_B, PLSL_B, PLSL_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
  26364. + SYNTAX_NORMAL3(PLSL_H, PLSL_H, PLSL_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
  26365. + SYNTAX_NORMAL3(PLSR_B, PLSR_B, PLSR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
  26366. + SYNTAX_NORMAL3(PLSR_H, PLSR_H, PLSR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
  26367. + SYNTAX_NORMAL3(PMAX_SH, PMAX_SH, PMAX_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26368. + SYNTAX_NORMAL3(PMAX_UB, PMAX_UB, PMAX_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26369. + SYNTAX_NORMAL3(PMIN_SH, PMIN_SH, PMIN_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26370. + SYNTAX_NORMAL3(PMIN_UB, PMIN_UB, PMIN_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26371. + SYNTAX_NORMAL0(POPJC, POPJC, POPJC, AVR32_V1),
  26372. + SYNTAX_NORMAL_CM1(POPM, POPM, POPM, POPM_E, REGLIST9, AVR32_V1),
  26373. + SYNTAX_NORMALM1(POPM_E, POPM, POPM_E, REGLIST16, AVR32_V1),
  26374. + SYNTAX_NORMAL1(PREF, PREF, PREF, INTREG_SDISP, AVR32_V1),
  26375. + SYNTAX_NORMAL3(PSAD, PSAD, PSAD, INTREG, INTREG, INTREG, AVR32_SIMD),
  26376. + SYNTAX_NORMAL3(PSUB_B, PSUB_B, PSUB_B, INTREG, INTREG, INTREG, AVR32_SIMD),
  26377. + SYNTAX_NORMAL3(PSUB_H, PSUB_H, PSUB_H, INTREG, INTREG, INTREG, AVR32_SIMD),
  26378. + SYNTAX_NORMAL3(PSUBADD_H, PSUBADD_H, PSUBADD_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26379. + SYNTAX_NORMAL3(PSUBADDH_SH, PSUBADDH_SH, PSUBADDH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26380. + SYNTAX_NORMAL3(PSUBADDS_SH, PSUBADDS_SH, PSUBADDS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26381. + SYNTAX_NORMAL3(PSUBADDS_UH, PSUBADDS_UH, PSUBADDS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
  26382. + SYNTAX_NORMAL3(PSUBH_SH, PSUBH_SH, PSUBH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26383. + SYNTAX_NORMAL3(PSUBH_UB, PSUBH_UB, PSUBH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26384. + SYNTAX_NORMAL3(PSUBS_SB, PSUBS_SB, PSUBS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26385. + SYNTAX_NORMAL3(PSUBS_SH, PSUBS_SH, PSUBS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26386. + SYNTAX_NORMAL3(PSUBS_UB, PSUBS_UB, PSUBS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
  26387. + SYNTAX_NORMAL3(PSUBS_UH, PSUBS_UH, PSUBS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26388. + SYNTAX_NORMAL3(PSUBX_H, PSUBX_H, PSUBX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
  26389. + SYNTAX_NORMAL3(PSUBXH_SH, PSUBXH_SH, PSUBXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26390. + SYNTAX_NORMAL3(PSUBXS_SH, PSUBXS_SH, PSUBXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26391. + SYNTAX_NORMAL3(PSUBXS_UH, PSUBXS_UH, PSUBXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
  26392. + SYNTAX_NORMAL2(PUNPCKSB_H, PUNPCKSB_H, PUNPCKSB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
  26393. + SYNTAX_NORMAL2(PUNPCKUB_H, PUNPCKUB_H, PUNPCKUB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
  26394. + SYNTAX_NORMAL0(PUSHJC, PUSHJC, PUSHJC, AVR32_V1),
  26395. + SYNTAX_NORMAL_CM1(PUSHM, PUSHM, PUSHM, PUSHM_E, REGLIST8, AVR32_V1),
  26396. + SYNTAX_NORMALM1(PUSHM_E, PUSHM, PUSHM_E, REGLIST16, AVR32_V1),
  26397. + SYNTAX_NORMAL_C1(RCALL1, RCALL, RCALL1, RCALL2, JMPLABEL, AVR32_V1),
  26398. + SYNTAX_NORMAL1(RCALL2, RCALL, RCALL2, JMPLABEL, AVR32_V1),
  26399. + SYNTAX_NORMAL1(RETEQ, RETEQ, RETEQ, RETVAL, AVR32_V1),
  26400. + SYNTAX_NORMAL1(RETNE, RETNE, RETNE, RETVAL, AVR32_V1),
  26401. + SYNTAX_NORMAL1(RETCC, RETCC, RETCC, RETVAL, AVR32_V1),
  26402. + SYNTAX_NORMAL1(RETCS, RETCS, RETCS, RETVAL, AVR32_V1),
  26403. + SYNTAX_NORMAL1(RETGE, RETGE, RETGE, RETVAL, AVR32_V1),
  26404. + SYNTAX_NORMAL1(RETLT, RETLT, RETLT, RETVAL, AVR32_V1),
  26405. + SYNTAX_NORMAL1(RETMI, RETMI, RETMI, RETVAL, AVR32_V1),
  26406. + SYNTAX_NORMAL1(RETPL, RETPL, RETPL, RETVAL, AVR32_V1),
  26407. + SYNTAX_NORMAL1(RETLS, RETLS, RETLS, RETVAL, AVR32_V1),
  26408. + SYNTAX_NORMAL1(RETGT, RETGT, RETGT, RETVAL, AVR32_V1),
  26409. + SYNTAX_NORMAL1(RETLE, RETLE, RETLE, RETVAL, AVR32_V1),
  26410. + SYNTAX_NORMAL1(RETHI, RETHI, RETHI, RETVAL, AVR32_V1),
  26411. + SYNTAX_NORMAL1(RETVS, RETVS, RETVS, RETVAL, AVR32_V1),
  26412. + SYNTAX_NORMAL1(RETVC, RETVC, RETVC, RETVAL, AVR32_V1),
  26413. + SYNTAX_NORMAL1(RETQS, RETQS, RETQS, RETVAL, AVR32_V1),
  26414. + SYNTAX_NORMAL1(RETAL, RETAL, RETAL, RETVAL, AVR32_V1),
  26415. + SYNTAX_NORMAL1(RETHS, RETHS, RETCC, RETVAL, AVR32_V1),
  26416. + SYNTAX_NORMAL1(RETLO, RETLO, RETCS, RETVAL, AVR32_V1),
  26417. + SYNTAX_NORMAL0(RETD, RETD, RETD, AVR32_V1),
  26418. + SYNTAX_NORMAL0(RETE, RETE, RETE, AVR32_V1),
  26419. + SYNTAX_NORMAL0(RETJ, RETJ, RETJ, AVR32_V1),
  26420. + SYNTAX_NORMAL0(RETS, RETS, RETS, AVR32_V1),
  26421. + SYNTAX_NORMAL1(RJMP, RJMP, RJMP, JMPLABEL, AVR32_V1),
  26422. + SYNTAX_NORMAL1(ROL, ROL, ROL, INTREG, AVR32_V1),
  26423. + SYNTAX_NORMAL1(ROR, ROR, ROR, INTREG, AVR32_V1),
  26424. + SYNTAX_NORMAL_C2(RSUB1, RSUB, RSUB1, RSUB2, INTREG, INTREG, AVR32_V1),
  26425. + SYNTAX_NORMAL3(RSUB2, RSUB, RSUB2, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
  26426. + SYNTAX_NORMAL3(SATADD_H, SATADD_H, SATADD_H, INTREG, INTREG, INTREG, AVR32_DSP),
  26427. + SYNTAX_NORMAL3(SATADD_W, SATADD_W, SATADD_W, INTREG, INTREG, INTREG, AVR32_DSP),
  26428. + SYNTAX_NORMAL2(SATRNDS, SATRNDS, SATRNDS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
  26429. + SYNTAX_NORMAL2(SATRNDU, SATRNDU, SATRNDU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
  26430. + SYNTAX_NORMAL2(SATS, SATS, SATS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
  26431. + SYNTAX_NORMAL3(SATSUB_H, SATSUB_H, SATSUB_H, INTREG, INTREG, INTREG, AVR32_DSP),
  26432. + SYNTAX_NORMAL_C3(SATSUB_W1, SATSUB_W, SATSUB_W1, SATSUB_W2, INTREG, INTREG, INTREG, AVR32_DSP),
  26433. + SYNTAX_NORMAL3(SATSUB_W2, SATSUB_W, SATSUB_W2, INTREG, INTREG, SIGNED_CONST, AVR32_DSP),
  26434. + SYNTAX_NORMAL2(SATU, SATU, SATU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_V1),
  26435. + SYNTAX_NORMAL3(SBC, SBC, SBC, INTREG, INTREG, INTREG, AVR32_V1),
  26436. + SYNTAX_NORMAL2(SBR, SBR, SBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
  26437. + SYNTAX_NORMAL0(SCALL, SCALL, SCALL, AVR32_V1),
  26438. + SYNTAX_NORMAL1(SCR, SCR, SCR, INTREG, AVR32_V1),
  26439. + SYNTAX_NORMAL1(SLEEP, SLEEP, SLEEP, UNSIGNED_CONST, AVR32_V1),
  26440. + SYNTAX_NORMAL1(SREQ, SREQ, SREQ, INTREG, AVR32_V1),
  26441. + SYNTAX_NORMAL1(SRNE, SRNE, SRNE, INTREG, AVR32_V1),
  26442. + SYNTAX_NORMAL1(SRCC, SRCC, SRCC, INTREG, AVR32_V1),
  26443. + SYNTAX_NORMAL1(SRCS, SRCS, SRCS, INTREG, AVR32_V1),
  26444. + SYNTAX_NORMAL1(SRGE, SRGE, SRGE, INTREG, AVR32_V1),
  26445. + SYNTAX_NORMAL1(SRLT, SRLT, SRLT, INTREG, AVR32_V1),
  26446. + SYNTAX_NORMAL1(SRMI, SRMI, SRMI, INTREG, AVR32_V1),
  26447. + SYNTAX_NORMAL1(SRPL, SRPL, SRPL, INTREG, AVR32_V1),
  26448. + SYNTAX_NORMAL1(SRLS, SRLS, SRLS, INTREG, AVR32_V1),
  26449. + SYNTAX_NORMAL1(SRGT, SRGT, SRGT, INTREG, AVR32_V1),
  26450. + SYNTAX_NORMAL1(SRLE, SRLE, SRLE, INTREG, AVR32_V1),
  26451. + SYNTAX_NORMAL1(SRHI, SRHI, SRHI, INTREG, AVR32_V1),
  26452. + SYNTAX_NORMAL1(SRVS, SRVS, SRVS, INTREG, AVR32_V1),
  26453. + SYNTAX_NORMAL1(SRVC, SRVC, SRVC, INTREG, AVR32_V1),
  26454. + SYNTAX_NORMAL1(SRQS, SRQS, SRQS, INTREG, AVR32_V1),
  26455. + SYNTAX_NORMAL1(SRAL, SRAL, SRAL, INTREG, AVR32_V1),
  26456. + SYNTAX_NORMAL1(SRHS, SRHS, SRCC, INTREG, AVR32_V1),
  26457. + SYNTAX_NORMAL1(SRLO, SRLO, SRCS, INTREG, AVR32_V1),
  26458. + SYNTAX_NORMAL1(SSRF, SSRF, SSRF, UNSIGNED_NUMBER, AVR32_V1),
  26459. + SYNTAX_NORMAL_C2(ST_B1, ST_B, ST_B1, ST_B2, INTREG_POSTINC, INTREG, AVR32_V1),
  26460. + SYNTAX_NORMAL_C2(ST_B2, ST_B, ST_B2, ST_B5, INTREG_PREDEC, INTREG, AVR32_V1),
  26461. + SYNTAX_NORMAL_C2(ST_B5, ST_B, ST_B5, ST_B3, INTREG_INDEX, INTREG, AVR32_V1),
  26462. + SYNTAX_NORMAL_C2(ST_B3, ST_B, ST_B3, ST_B4, INTREG_UDISP, INTREG, AVR32_V1),
  26463. + SYNTAX_NORMAL2(ST_B4, ST_B, ST_B4, INTREG_SDISP, INTREG, AVR32_V1),
  26464. + SYNTAX_NORMAL_C2(ST_D1, ST_D, ST_D1, ST_D2, INTREG_POSTINC, DWREG, AVR32_V1),
  26465. + SYNTAX_NORMAL_C2(ST_D2, ST_D, ST_D2, ST_D3, INTREG_PREDEC, DWREG, AVR32_V1),
  26466. + SYNTAX_NORMAL_C2(ST_D3, ST_D, ST_D3, ST_D5, INTREG, DWREG, AVR32_V1),
  26467. + SYNTAX_NORMAL_C2(ST_D5, ST_D, ST_D5, ST_D4, INTREG_INDEX, DWREG, AVR32_V1),
  26468. + SYNTAX_NORMAL2(ST_D4, ST_D, ST_D4, INTREG_SDISP, DWREG, AVR32_V1),
  26469. + SYNTAX_NORMAL_C2(ST_H1, ST_H, ST_H1, ST_H2, INTREG_POSTINC, INTREG, AVR32_V1),
  26470. + SYNTAX_NORMAL_C2(ST_H2, ST_H, ST_H2, ST_H5, INTREG_PREDEC, INTREG, AVR32_V1),
  26471. + SYNTAX_NORMAL_C2(ST_H5, ST_H, ST_H5, ST_H3, INTREG_INDEX, INTREG, AVR32_V1),
  26472. + SYNTAX_NORMAL_C2(ST_H3, ST_H, ST_H3, ST_H4, INTREG_UDISP_H, INTREG, AVR32_V1),
  26473. + SYNTAX_NORMAL2(ST_H4, ST_H, ST_H4, INTREG_SDISP, INTREG, AVR32_V1),
  26474. + SYNTAX_NORMAL_C2(ST_W1, ST_W, ST_W1, ST_W2, INTREG_POSTINC, INTREG, AVR32_V1),
  26475. + SYNTAX_NORMAL_C2(ST_W2, ST_W, ST_W2, ST_W5, INTREG_PREDEC, INTREG, AVR32_V1),
  26476. + SYNTAX_NORMAL_C2(ST_W5, ST_W, ST_W5, ST_W3, INTREG_INDEX, INTREG, AVR32_V1),
  26477. + SYNTAX_NORMAL_C2(ST_W3, ST_W, ST_W3, ST_W4, INTREG_UDISP_W, INTREG, AVR32_V1),
  26478. + SYNTAX_NORMAL2(ST_W4, ST_W, ST_W4, INTREG_SDISP, INTREG, AVR32_V1),
  26479. + SYNTAX_NORMAL3(STC_D1, STC_D, STC_D1, CPNO, INTREG_UDISP_W, CPREG_D, AVR32_V1),
  26480. + SYNTAX_NORMAL_C3(STC_D2, STC_D, STC_D2, STC_D1, CPNO, INTREG_POSTINC, CPREG_D, AVR32_V1),
  26481. + SYNTAX_NORMAL_C3(STC_D3, STC_D, STC_D3, STC_D2, CPNO, INTREG_INDEX, CPREG_D, AVR32_V1),
  26482. + SYNTAX_NORMAL3(STC_W1, STC_W, STC_W1, CPNO, INTREG_UDISP_W, CPREG, AVR32_V1),
  26483. + SYNTAX_NORMAL_C3(STC_W2, STC_W, STC_W2, STC_W1, CPNO, INTREG_POSTINC, CPREG, AVR32_V1),
  26484. + SYNTAX_NORMAL_C3(STC_W3, STC_W, STC_W3, STC_W2, CPNO, INTREG_INDEX, CPREG, AVR32_V1),
  26485. + SYNTAX_NORMAL2(STC0_D, STC0_D, STC0_D, INTREG_UDISP_W, CPREG_D, AVR32_V1),
  26486. + SYNTAX_NORMAL2(STC0_W, STC0_W, STC0_W, INTREG_UDISP_W, CPREG, AVR32_V1),
  26487. + SYNTAX_NORMAL_CM3(STCM_D, STCM_D, STCM_D, STCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
  26488. + SYNTAX_NORMALM3(STCM_D_PU, STCM_D, STCM_D_PU, CPNO, INTREG_PREDEC, REGLIST_CPD8, AVR32_V1),
  26489. + SYNTAX_NORMAL_CM3(STCM_W, STCM_W, STCM_W, STCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
  26490. + SYNTAX_NORMALM3(STCM_W_PU, STCM_W, STCM_W_PU, CPNO, INTREG_PREDEC, REGLIST_CP8, AVR32_V1),
  26491. + SYNTAX_NORMAL2(STCOND, STCOND, STCOND, INTREG_SDISP, INTREG, AVR32_V1),
  26492. + SYNTAX_NORMAL2(STDSP, STDSP, STDSP, SP_UDISP_W, INTREG, AVR32_V1),
  26493. + SYNTAX_NORMAL_C3(STHH_W2, STHH_W, STHH_W2, STHH_W1, INTREG_INDEX, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
  26494. + SYNTAX_NORMAL3(STHH_W1, STHH_W, STHH_W1, INTREG_UDISP_W, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
  26495. + SYNTAX_NORMAL_CM2(STM, STM, STM, STM_PU, INTREG, REGLIST16, AVR32_V1),
  26496. + SYNTAX_NORMALM2(STM_PU, STM, STM_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
  26497. + SYNTAX_NORMAL_CM2(STMTS, STMTS, STMTS, STMTS_PU, INTREG, REGLIST16, AVR32_V1),
  26498. + SYNTAX_NORMALM2(STMTS_PU, STMTS, STMTS_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
  26499. + SYNTAX_NORMAL2(STSWP_H, STSWP_H, STSWP_H, INTREG_SDISP_H, INTREG, AVR32_V1),
  26500. + SYNTAX_NORMAL2(STSWP_W, STSWP_W, STSWP_W, INTREG_SDISP_W, INTREG, AVR32_V1),
  26501. + SYNTAX_NORMAL_C2(SUB1, SUB, SUB1, SUB2, INTREG, INTREG, AVR32_V1),
  26502. + SYNTAX_NORMAL_C3(SUB2, SUB, SUB2, SUB5, INTREG, INTREG, INTREG_LSL, AVR32_V1),
  26503. + SYNTAX_NORMAL_C3(SUB5, SUB, SUB5, SUB3_SP, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
  26504. + SYNTAX_NORMAL_C2(SUB3_SP, SUB, SUB3_SP, SUB3, SP, SIGNED_CONST_W, AVR32_V1),
  26505. + SYNTAX_NORMAL_C2(SUB3, SUB, SUB3, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
  26506. + SYNTAX_NORMAL2(SUB4, SUB, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
  26507. + SYNTAX_NORMAL_C2(SUBEQ, SUBEQ, SUBEQ, SUB2EQ, INTREG, SIGNED_CONST, AVR32_V1),
  26508. + SYNTAX_NORMAL_C2(SUBNE, SUBNE, SUBNE, SUB2NE, INTREG, SIGNED_CONST, AVR32_V1),
  26509. + SYNTAX_NORMAL_C2(SUBCC, SUBCC, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
  26510. + SYNTAX_NORMAL_C2(SUBCS, SUBCS, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
  26511. + SYNTAX_NORMAL_C2(SUBGE, SUBGE, SUBGE, SUB2GE, INTREG, SIGNED_CONST, AVR32_V1),
  26512. + SYNTAX_NORMAL_C2(SUBLT, SUBLT, SUBLT, SUB2LT, INTREG, SIGNED_CONST, AVR32_V1),
  26513. + SYNTAX_NORMAL_C2(SUBMI, SUBMI, SUBMI, SUB2MI, INTREG, SIGNED_CONST, AVR32_V1),
  26514. + SYNTAX_NORMAL_C2(SUBPL, SUBPL, SUBPL, SUB2PL, INTREG, SIGNED_CONST, AVR32_V1),
  26515. + SYNTAX_NORMAL_C2(SUBLS, SUBLS, SUBLS, SUB2LS, INTREG, SIGNED_CONST, AVR32_V1),
  26516. + SYNTAX_NORMAL_C2(SUBGT, SUBGT, SUBGT, SUB2GT, INTREG, SIGNED_CONST, AVR32_V1),
  26517. + SYNTAX_NORMAL_C2(SUBLE, SUBLE, SUBLE, SUB2LE, INTREG, SIGNED_CONST, AVR32_V1),
  26518. + SYNTAX_NORMAL_C2(SUBHI, SUBHI, SUBHI, SUB2HI, INTREG, SIGNED_CONST, AVR32_V1),
  26519. + SYNTAX_NORMAL_C2(SUBVS, SUBVS, SUBVS, SUB2VS, INTREG, SIGNED_CONST, AVR32_V1),
  26520. + SYNTAX_NORMAL_C2(SUBVC, SUBVC, SUBVC, SUB2VC, INTREG, SIGNED_CONST, AVR32_V1),
  26521. + SYNTAX_NORMAL_C2(SUBQS, SUBQS, SUBQS, SUB2QS, INTREG, SIGNED_CONST, AVR32_V1),
  26522. + SYNTAX_NORMAL_C2(SUBAL, SUBAL, SUBAL, SUB2AL, INTREG, SIGNED_CONST, AVR32_V1),
  26523. + SYNTAX_NORMAL_C2(SUBHS, SUBHS, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
  26524. + SYNTAX_NORMAL_C2(SUBLO, SUBLO, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
  26525. + SYNTAX_NORMAL2(SUBFEQ, SUBFEQ, SUBFEQ, INTREG, SIGNED_CONST, AVR32_V1),
  26526. + SYNTAX_NORMAL2(SUBFNE, SUBFNE, SUBFNE, INTREG, SIGNED_CONST, AVR32_V1),
  26527. + SYNTAX_NORMAL2(SUBFCC, SUBFCC, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
  26528. + SYNTAX_NORMAL2(SUBFCS, SUBFCS, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
  26529. + SYNTAX_NORMAL2(SUBFGE, SUBFGE, SUBFGE, INTREG, SIGNED_CONST, AVR32_V1),
  26530. + SYNTAX_NORMAL2(SUBFLT, SUBFLT, SUBFLT, INTREG, SIGNED_CONST, AVR32_V1),
  26531. + SYNTAX_NORMAL2(SUBFMI, SUBFMI, SUBFMI, INTREG, SIGNED_CONST, AVR32_V1),
  26532. + SYNTAX_NORMAL2(SUBFPL, SUBFPL, SUBFPL, INTREG, SIGNED_CONST, AVR32_V1),
  26533. + SYNTAX_NORMAL2(SUBFLS, SUBFLS, SUBFLS, INTREG, SIGNED_CONST, AVR32_V1),
  26534. + SYNTAX_NORMAL2(SUBFGT, SUBFGT, SUBFGT, INTREG, SIGNED_CONST, AVR32_V1),
  26535. + SYNTAX_NORMAL2(SUBFLE, SUBFLE, SUBFLE, INTREG, SIGNED_CONST, AVR32_V1),
  26536. + SYNTAX_NORMAL2(SUBFHI, SUBFHI, SUBFHI, INTREG, SIGNED_CONST, AVR32_V1),
  26537. + SYNTAX_NORMAL2(SUBFVS, SUBFVS, SUBFVS, INTREG, SIGNED_CONST, AVR32_V1),
  26538. + SYNTAX_NORMAL2(SUBFVC, SUBFVC, SUBFVC, INTREG, SIGNED_CONST, AVR32_V1),
  26539. + SYNTAX_NORMAL2(SUBFQS, SUBFQS, SUBFQS, INTREG, SIGNED_CONST, AVR32_V1),
  26540. + SYNTAX_NORMAL2(SUBFAL, SUBFAL, SUBFAL, INTREG, SIGNED_CONST, AVR32_V1),
  26541. + SYNTAX_NORMAL2(SUBFHS, SUBFHS, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
  26542. + SYNTAX_NORMAL2(SUBFLO, SUBFLO, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
  26543. + SYNTAX_NORMAL3(SUBHH_W, SUBHH_W, SUBHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
  26544. + SYNTAX_NORMAL1(SWAP_B, SWAP_B, SWAP_B, INTREG, AVR32_V1),
  26545. + SYNTAX_NORMAL1(SWAP_BH, SWAP_BH, SWAP_BH, INTREG, AVR32_V1),
  26546. + SYNTAX_NORMAL1(SWAP_H, SWAP_H, SWAP_H, INTREG, AVR32_V1),
  26547. + SYNTAX_NORMAL1(SYNC, SYNC, SYNC, UNSIGNED_CONST, AVR32_V1),
  26548. + SYNTAX_NORMAL0(TLBR, TLBR, TLBR, AVR32_V1),
  26549. + SYNTAX_NORMAL0(TLBS, TLBS, TLBS, AVR32_V1),
  26550. + SYNTAX_NORMAL0(TLBW, TLBW, TLBW, AVR32_V1),
  26551. + SYNTAX_NORMAL1(TNBZ, TNBZ, TNBZ, INTREG, AVR32_V1),
  26552. + SYNTAX_NORMAL2(TST, TST, TST, INTREG, INTREG, AVR32_V1),
  26553. + SYNTAX_NORMAL3(XCHG, XCHG, XCHG, INTREG, INTREG, INTREG, AVR32_V1),
  26554. + SYNTAX_NORMAL2(MEMC, MEMC, MEMC, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
  26555. + SYNTAX_NORMAL2(MEMS, MEMS, MEMS, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
  26556. + SYNTAX_NORMAL2(MEMT, MEMT, MEMT, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
  26557. + SYNTAX_NORMAL4 (FMAC_S, FMAC_S, FMAC_S, INTREG, INTREG, INTREG, INTREG,
  26558. + AVR32_V3FP),
  26559. + SYNTAX_NORMAL4 (FNMAC_S, FNMAC_S, FNMAC_S, INTREG, INTREG, INTREG, INTREG,
  26560. + AVR32_V3FP),
  26561. + SYNTAX_NORMAL4 (FMSC_S, FMSC_S, FMSC_S, INTREG, INTREG, INTREG, INTREG,
  26562. + AVR32_V3FP),
  26563. + SYNTAX_NORMAL4 (FNMSC_S, FNMSC_S, FNMSC_S, INTREG, INTREG, INTREG, INTREG,
  26564. + AVR32_V3FP),
  26565. + SYNTAX_NORMAL3 (FMUL_S, FMUL_S, FMUL_S, INTREG, INTREG, INTREG, AVR32_V3FP),
  26566. + SYNTAX_NORMAL3 (FNMUL_S, FNMUL_S, FNMUL_S, INTREG, INTREG, INTREG, AVR32_V3FP),
  26567. + SYNTAX_NORMAL3 (FADD_S, FADD_S, FADD_S, INTREG, INTREG, INTREG, AVR32_V3FP),
  26568. + SYNTAX_NORMAL3 (FSUB_S, FSUB_S, FSUB_S, INTREG, INTREG, INTREG, AVR32_V3FP),
  26569. + SYNTAX_NORMAL2 (FCASTRS_SW, FCASTRS_SW, FCASTRS_SW, INTREG, INTREG, AVR32_V3FP),
  26570. + SYNTAX_NORMAL2 (FCASTRS_UW, FCASTRS_UW, FCASTRS_UW, INTREG, INTREG, AVR32_V3FP),
  26571. + SYNTAX_NORMAL2 (FCASTSW_S, FCASTSW_S, FCASTSW_S, INTREG, INTREG, AVR32_V3FP),
  26572. + SYNTAX_NORMAL2 (FCASTUW_S, FCASTUW_S, FCASTUW_S, INTREG, INTREG, AVR32_V3FP),
  26573. + SYNTAX_NORMAL2 (FCMP_S, FCMP_S, FCMP_S, INTREG, INTREG, AVR32_V3FP),
  26574. + SYNTAX_NORMAL1 (FCHK_S, FCHK_S, FCHK_S, INTREG, AVR32_V3FP),
  26575. + SYNTAX_NORMAL2 (FRCPA_S, FRCPA_S, FRCPA_S, INTREG, INTREG, AVR32_V3FP),
  26576. + SYNTAX_NORMAL2 (FRSQRTA_S, FRSQRTA_S, FRSQRTA_S, INTREG, INTREG, AVR32_V3FP),
  26577. + {
  26578. + AVR32_SYNTAX_LDA_W,
  26579. + AVR32_V1, NULL, AVR32_PARSER_LDA,
  26580. + { NULL }, NULL,
  26581. + 2,
  26582. + {
  26583. + AVR32_OPERAND_INTREG,
  26584. + AVR32_OPERAND_SIGNED_CONST,
  26585. + },
  26586. + },
  26587. + {
  26588. + AVR32_SYNTAX_CALL,
  26589. + AVR32_V1, NULL, AVR32_PARSER_CALL,
  26590. + { NULL }, NULL,
  26591. + 1,
  26592. + {
  26593. + AVR32_OPERAND_JMPLABEL,
  26594. + },
  26595. + },
  26596. + {
  26597. + AVR32_SYNTAX_PICOSVMAC0,
  26598. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
  26599. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC0] },
  26600. + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC1], 4,
  26601. + {
  26602. + AVR32_OPERAND_PICO_OUT0,
  26603. + AVR32_OPERAND_PICO_IN,
  26604. + AVR32_OPERAND_PICO_IN,
  26605. + AVR32_OPERAND_PICO_IN,
  26606. + },
  26607. + },
  26608. + {
  26609. + AVR32_SYNTAX_PICOSVMAC1,
  26610. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
  26611. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC1] },
  26612. + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC2], 4,
  26613. + {
  26614. + AVR32_OPERAND_PICO_OUT1,
  26615. + AVR32_OPERAND_PICO_IN,
  26616. + AVR32_OPERAND_PICO_IN,
  26617. + AVR32_OPERAND_PICO_IN,
  26618. + },
  26619. + },
  26620. + {
  26621. + AVR32_SYNTAX_PICOSVMAC2,
  26622. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
  26623. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC2] },
  26624. + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC3], 4,
  26625. + {
  26626. + AVR32_OPERAND_PICO_OUT2,
  26627. + AVR32_OPERAND_PICO_IN,
  26628. + AVR32_OPERAND_PICO_IN,
  26629. + AVR32_OPERAND_PICO_IN,
  26630. + },
  26631. + },
  26632. + {
  26633. + AVR32_SYNTAX_PICOSVMAC3,
  26634. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
  26635. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC3] },
  26636. + NULL, 4,
  26637. + {
  26638. + AVR32_OPERAND_PICO_OUT3,
  26639. + AVR32_OPERAND_PICO_IN,
  26640. + AVR32_OPERAND_PICO_IN,
  26641. + AVR32_OPERAND_PICO_IN,
  26642. + },
  26643. + },
  26644. + {
  26645. + AVR32_SYNTAX_PICOSVMUL0,
  26646. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
  26647. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL0] },
  26648. + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL1], 4,
  26649. + {
  26650. + AVR32_OPERAND_PICO_OUT0,
  26651. + AVR32_OPERAND_PICO_IN,
  26652. + AVR32_OPERAND_PICO_IN,
  26653. + AVR32_OPERAND_PICO_IN,
  26654. + },
  26655. + },
  26656. + {
  26657. + AVR32_SYNTAX_PICOSVMUL1,
  26658. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
  26659. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL1] },
  26660. + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL2], 4,
  26661. + {
  26662. + AVR32_OPERAND_PICO_OUT1,
  26663. + AVR32_OPERAND_PICO_IN,
  26664. + AVR32_OPERAND_PICO_IN,
  26665. + AVR32_OPERAND_PICO_IN,
  26666. + },
  26667. + },
  26668. + {
  26669. + AVR32_SYNTAX_PICOSVMUL2,
  26670. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
  26671. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL2] },
  26672. + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL3], 4,
  26673. + {
  26674. + AVR32_OPERAND_PICO_OUT2,
  26675. + AVR32_OPERAND_PICO_IN,
  26676. + AVR32_OPERAND_PICO_IN,
  26677. + AVR32_OPERAND_PICO_IN,
  26678. + },
  26679. + },
  26680. + {
  26681. + AVR32_SYNTAX_PICOSVMUL3,
  26682. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
  26683. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL3] },
  26684. + NULL, 4,
  26685. + {
  26686. + AVR32_OPERAND_PICO_OUT3,
  26687. + AVR32_OPERAND_PICO_IN,
  26688. + AVR32_OPERAND_PICO_IN,
  26689. + AVR32_OPERAND_PICO_IN,
  26690. + },
  26691. + },
  26692. + {
  26693. + AVR32_SYNTAX_PICOVMAC0,
  26694. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
  26695. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC0] },
  26696. + &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC1], 4,
  26697. + {
  26698. + AVR32_OPERAND_PICO_OUT0,
  26699. + AVR32_OPERAND_PICO_IN,
  26700. + AVR32_OPERAND_PICO_IN,
  26701. + AVR32_OPERAND_PICO_IN,
  26702. + },
  26703. + },
  26704. + {
  26705. + AVR32_SYNTAX_PICOVMAC1,
  26706. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
  26707. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC1] },
  26708. + &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC2], 4,
  26709. + {
  26710. + AVR32_OPERAND_PICO_OUT1,
  26711. + AVR32_OPERAND_PICO_IN,
  26712. + AVR32_OPERAND_PICO_IN,
  26713. + AVR32_OPERAND_PICO_IN,
  26714. + },
  26715. + },
  26716. + {
  26717. + AVR32_SYNTAX_PICOVMAC2,
  26718. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
  26719. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC2] },
  26720. + &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC3], 4,
  26721. + {
  26722. + AVR32_OPERAND_PICO_OUT2,
  26723. + AVR32_OPERAND_PICO_IN,
  26724. + AVR32_OPERAND_PICO_IN,
  26725. + AVR32_OPERAND_PICO_IN,
  26726. + },
  26727. + },
  26728. + {
  26729. + AVR32_SYNTAX_PICOVMAC3,
  26730. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
  26731. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC3] },
  26732. + NULL, 4,
  26733. + {
  26734. + AVR32_OPERAND_PICO_OUT3,
  26735. + AVR32_OPERAND_PICO_IN,
  26736. + AVR32_OPERAND_PICO_IN,
  26737. + AVR32_OPERAND_PICO_IN,
  26738. + },
  26739. + },
  26740. + {
  26741. + AVR32_SYNTAX_PICOVMUL0,
  26742. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
  26743. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL0] },
  26744. + &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL1], 4,
  26745. + {
  26746. + AVR32_OPERAND_PICO_OUT0,
  26747. + AVR32_OPERAND_PICO_IN,
  26748. + AVR32_OPERAND_PICO_IN,
  26749. + AVR32_OPERAND_PICO_IN,
  26750. + },
  26751. + },
  26752. + {
  26753. + AVR32_SYNTAX_PICOVMUL1,
  26754. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
  26755. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL1] },
  26756. + &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL2], 4,
  26757. + {
  26758. + AVR32_OPERAND_PICO_OUT1,
  26759. + AVR32_OPERAND_PICO_IN,
  26760. + AVR32_OPERAND_PICO_IN,
  26761. + AVR32_OPERAND_PICO_IN,
  26762. + },
  26763. + },
  26764. + {
  26765. + AVR32_SYNTAX_PICOVMUL2,
  26766. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
  26767. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL2] },
  26768. + &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL3], 4,
  26769. + {
  26770. + AVR32_OPERAND_PICO_OUT2,
  26771. + AVR32_OPERAND_PICO_IN,
  26772. + AVR32_OPERAND_PICO_IN,
  26773. + AVR32_OPERAND_PICO_IN,
  26774. + },
  26775. + },
  26776. + {
  26777. + AVR32_SYNTAX_PICOVMUL3,
  26778. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
  26779. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL3] },
  26780. + NULL, 4,
  26781. + {
  26782. + AVR32_OPERAND_PICO_OUT3,
  26783. + AVR32_OPERAND_PICO_IN,
  26784. + AVR32_OPERAND_PICO_IN,
  26785. + AVR32_OPERAND_PICO_IN,
  26786. + },
  26787. + },
  26788. + {
  26789. + AVR32_SYNTAX_PICOLD_D2,
  26790. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
  26791. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D2] },
  26792. + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D3], 2,
  26793. + {
  26794. + AVR32_OPERAND_PICO_REG_D,
  26795. + AVR32_OPERAND_INTREG_PREDEC,
  26796. + },
  26797. + },
  26798. + {
  26799. + AVR32_SYNTAX_PICOLD_D3,
  26800. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
  26801. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D3] },
  26802. + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D1], 2,
  26803. + {
  26804. + AVR32_OPERAND_PICO_REG_D,
  26805. + AVR32_OPERAND_INTREG_INDEX,
  26806. + },
  26807. + },
  26808. + {
  26809. + AVR32_SYNTAX_PICOLD_D1,
  26810. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
  26811. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D1] },
  26812. + NULL, 2,
  26813. + {
  26814. + AVR32_OPERAND_PICO_REG_D,
  26815. + AVR32_OPERAND_INTREG_UDISP_W,
  26816. + },
  26817. + },
  26818. + {
  26819. + AVR32_SYNTAX_PICOLD_W2,
  26820. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
  26821. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W2] },
  26822. + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W3], 2,
  26823. + {
  26824. + AVR32_OPERAND_PICO_REG_W,
  26825. + AVR32_OPERAND_INTREG_PREDEC,
  26826. + },
  26827. + },
  26828. + {
  26829. + AVR32_SYNTAX_PICOLD_W3,
  26830. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
  26831. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W3] },
  26832. + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W1], 2,
  26833. + {
  26834. + AVR32_OPERAND_PICO_REG_W,
  26835. + AVR32_OPERAND_INTREG_INDEX,
  26836. + },
  26837. + },
  26838. + {
  26839. + AVR32_SYNTAX_PICOLD_W1,
  26840. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
  26841. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W1] },
  26842. + NULL, 2,
  26843. + {
  26844. + AVR32_OPERAND_PICO_REG_W,
  26845. + AVR32_OPERAND_INTREG_UDISP_W,
  26846. + },
  26847. + },
  26848. + {
  26849. + AVR32_SYNTAX_PICOLDM_D,
  26850. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
  26851. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D] },
  26852. + &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_D_PU], -2,
  26853. + {
  26854. + AVR32_OPERAND_INTREG,
  26855. + AVR32_OPERAND_PICO_REGLIST_D,
  26856. + },
  26857. + },
  26858. + {
  26859. + AVR32_SYNTAX_PICOLDM_D_PU,
  26860. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
  26861. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D_PU] },
  26862. + NULL, -2,
  26863. + {
  26864. + AVR32_OPERAND_INTREG_POSTINC,
  26865. + AVR32_OPERAND_PICO_REGLIST_D,
  26866. + },
  26867. + },
  26868. + {
  26869. + AVR32_SYNTAX_PICOLDM_W,
  26870. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
  26871. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W] },
  26872. + &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_W_PU], -2,
  26873. + {
  26874. + AVR32_OPERAND_INTREG,
  26875. + AVR32_OPERAND_PICO_REGLIST_W,
  26876. + },
  26877. + },
  26878. + {
  26879. + AVR32_SYNTAX_PICOLDM_W_PU,
  26880. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
  26881. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W_PU] },
  26882. + NULL, -2,
  26883. + {
  26884. + AVR32_OPERAND_INTREG_POSTINC,
  26885. + AVR32_OPERAND_PICO_REGLIST_W,
  26886. + },
  26887. + },
  26888. + {
  26889. + AVR32_SYNTAX_PICOMV_D1,
  26890. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
  26891. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D1] },
  26892. + &avr32_syntax_table[AVR32_SYNTAX_PICOMV_D2], 2,
  26893. + {
  26894. + AVR32_OPERAND_DWREG,
  26895. + AVR32_OPERAND_PICO_REG_D,
  26896. + },
  26897. + },
  26898. + {
  26899. + AVR32_SYNTAX_PICOMV_D2,
  26900. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
  26901. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D2] },
  26902. + NULL, 2,
  26903. + {
  26904. + AVR32_OPERAND_PICO_REG_D,
  26905. + AVR32_OPERAND_DWREG,
  26906. + },
  26907. + },
  26908. + {
  26909. + AVR32_SYNTAX_PICOMV_W1,
  26910. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
  26911. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W1] },
  26912. + &avr32_syntax_table[AVR32_SYNTAX_PICOMV_W2], 2,
  26913. + {
  26914. + AVR32_OPERAND_INTREG,
  26915. + AVR32_OPERAND_PICO_REG_W,
  26916. + },
  26917. + },
  26918. + {
  26919. + AVR32_SYNTAX_PICOMV_W2,
  26920. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
  26921. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W2] },
  26922. + NULL, 2,
  26923. + {
  26924. + AVR32_OPERAND_PICO_REG_W,
  26925. + AVR32_OPERAND_INTREG,
  26926. + },
  26927. + },
  26928. + {
  26929. + AVR32_SYNTAX_PICOST_D2,
  26930. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
  26931. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D2] },
  26932. + &avr32_syntax_table[AVR32_SYNTAX_PICOST_D3], 2,
  26933. + {
  26934. + AVR32_OPERAND_INTREG_POSTINC,
  26935. + AVR32_OPERAND_PICO_REG_D,
  26936. + },
  26937. + },
  26938. + {
  26939. + AVR32_SYNTAX_PICOST_D3,
  26940. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
  26941. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D3] },
  26942. + &avr32_syntax_table[AVR32_SYNTAX_PICOST_D1], 2,
  26943. + {
  26944. + AVR32_OPERAND_INTREG_INDEX,
  26945. + AVR32_OPERAND_PICO_REG_D,
  26946. + },
  26947. + },
  26948. + {
  26949. + AVR32_SYNTAX_PICOST_D1,
  26950. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
  26951. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D1] },
  26952. + NULL, 2,
  26953. + {
  26954. + AVR32_OPERAND_INTREG_UDISP_W,
  26955. + AVR32_OPERAND_PICO_REG_D,
  26956. + },
  26957. + },
  26958. + {
  26959. + AVR32_SYNTAX_PICOST_W2,
  26960. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
  26961. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W2] },
  26962. + &avr32_syntax_table[AVR32_SYNTAX_PICOST_W3], 2,
  26963. + {
  26964. + AVR32_OPERAND_INTREG_POSTINC,
  26965. + AVR32_OPERAND_PICO_REG_W,
  26966. + },
  26967. + },
  26968. + {
  26969. + AVR32_SYNTAX_PICOST_W3,
  26970. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
  26971. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W3] },
  26972. + &avr32_syntax_table[AVR32_SYNTAX_PICOST_W1], 2,
  26973. + {
  26974. + AVR32_OPERAND_INTREG_INDEX,
  26975. + AVR32_OPERAND_PICO_REG_W,
  26976. + },
  26977. + },
  26978. + {
  26979. + AVR32_SYNTAX_PICOST_W1,
  26980. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
  26981. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W1] },
  26982. + NULL, 2,
  26983. + {
  26984. + AVR32_OPERAND_INTREG_UDISP_W,
  26985. + AVR32_OPERAND_PICO_REG_W,
  26986. + },
  26987. + },
  26988. + {
  26989. + AVR32_SYNTAX_PICOSTM_D,
  26990. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
  26991. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D] },
  26992. + &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_D_PU], -2,
  26993. + {
  26994. + AVR32_OPERAND_INTREG,
  26995. + AVR32_OPERAND_PICO_REGLIST_D,
  26996. + },
  26997. + },
  26998. + {
  26999. + AVR32_SYNTAX_PICOSTM_D_PU,
  27000. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
  27001. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D_PU] },
  27002. + NULL, -2,
  27003. + {
  27004. + AVR32_OPERAND_INTREG_PREDEC,
  27005. + AVR32_OPERAND_PICO_REGLIST_D,
  27006. + },
  27007. + },
  27008. + {
  27009. + AVR32_SYNTAX_PICOSTM_W,
  27010. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
  27011. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W] },
  27012. + &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_W_PU], -2,
  27013. + {
  27014. + AVR32_OPERAND_INTREG,
  27015. + AVR32_OPERAND_PICO_REGLIST_W,
  27016. + },
  27017. + },
  27018. + {
  27019. + AVR32_SYNTAX_PICOSTM_W_PU,
  27020. + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
  27021. + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W_PU] },
  27022. + NULL, -2,
  27023. + {
  27024. + AVR32_OPERAND_INTREG_PREDEC,
  27025. + AVR32_OPERAND_PICO_REGLIST_W,
  27026. + },
  27027. + },
  27028. + SYNTAX_NORMAL2(RSUBEQ, RSUBEQ, RSUBEQ, INTREG, SIGNED_CONST, AVR32_V1),
  27029. + SYNTAX_NORMAL2(RSUBNE, RSUBNE, RSUBNE, INTREG, SIGNED_CONST, AVR32_V2),
  27030. + SYNTAX_NORMAL2(RSUBCC, RSUBCC, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
  27031. + SYNTAX_NORMAL2(RSUBCS, RSUBCS, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
  27032. + SYNTAX_NORMAL2(RSUBGE, RSUBGE, RSUBGE, INTREG, SIGNED_CONST, AVR32_V2),
  27033. + SYNTAX_NORMAL2(RSUBLT, RSUBLT, RSUBLT, INTREG, SIGNED_CONST, AVR32_V2),
  27034. + SYNTAX_NORMAL2(RSUBMI, RSUBMI, RSUBMI, INTREG, SIGNED_CONST, AVR32_V2),
  27035. + SYNTAX_NORMAL2(RSUBPL, RSUBPL, RSUBPL, INTREG, SIGNED_CONST, AVR32_V2),
  27036. + SYNTAX_NORMAL2(RSUBLS, RSUBLS, RSUBLS, INTREG, SIGNED_CONST, AVR32_V2),
  27037. + SYNTAX_NORMAL2(RSUBGT, RSUBGT, RSUBGT, INTREG, SIGNED_CONST, AVR32_V2),
  27038. + SYNTAX_NORMAL2(RSUBLE, RSUBLE, RSUBLE, INTREG, SIGNED_CONST, AVR32_V2),
  27039. + SYNTAX_NORMAL2(RSUBHI, RSUBHI, RSUBHI, INTREG, SIGNED_CONST, AVR32_V2),
  27040. + SYNTAX_NORMAL2(RSUBVS, RSUBVS, RSUBVS, INTREG, SIGNED_CONST, AVR32_V2),
  27041. + SYNTAX_NORMAL2(RSUBVC, RSUBVC, RSUBVC, INTREG, SIGNED_CONST, AVR32_V2),
  27042. + SYNTAX_NORMAL2(RSUBQS, RSUBQS, RSUBQS, INTREG, SIGNED_CONST, AVR32_V2),
  27043. + SYNTAX_NORMAL2(RSUBAL, RSUBAL, RSUBAL, INTREG, SIGNED_CONST, AVR32_V2),
  27044. + SYNTAX_NORMAL2(RSUBHS, RSUBHS, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
  27045. + SYNTAX_NORMAL2(RSUBLO, RSUBLO, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
  27046. + SYNTAX_NORMAL3(ADDEQ, ADDEQ, ADDEQ, INTREG, INTREG, INTREG, AVR32_V2),
  27047. + SYNTAX_NORMAL3(ADDNE, ADDNE, ADDNE, INTREG, INTREG, INTREG, AVR32_V2),
  27048. + SYNTAX_NORMAL3(ADDCC, ADDCC, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
  27049. + SYNTAX_NORMAL3(ADDCS, ADDCS, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
  27050. + SYNTAX_NORMAL3(ADDGE, ADDGE, ADDGE, INTREG, INTREG, INTREG, AVR32_V2),
  27051. + SYNTAX_NORMAL3(ADDLT, ADDLT, ADDLT, INTREG, INTREG, INTREG, AVR32_V2),
  27052. + SYNTAX_NORMAL3(ADDMI, ADDMI, ADDMI, INTREG, INTREG, INTREG, AVR32_V2),
  27053. + SYNTAX_NORMAL3(ADDPL, ADDPL, ADDPL, INTREG, INTREG, INTREG, AVR32_V2),
  27054. + SYNTAX_NORMAL3(ADDLS, ADDLS, ADDLS, INTREG, INTREG, INTREG, AVR32_V2),
  27055. + SYNTAX_NORMAL3(ADDGT, ADDGT, ADDGT, INTREG, INTREG, INTREG, AVR32_V2),
  27056. + SYNTAX_NORMAL3(ADDLE, ADDLE, ADDLE, INTREG, INTREG, INTREG, AVR32_V2),
  27057. + SYNTAX_NORMAL3(ADDHI, ADDHI, ADDHI, INTREG, INTREG, INTREG, AVR32_V2),
  27058. + SYNTAX_NORMAL3(ADDVS, ADDVS, ADDVS, INTREG, INTREG, INTREG, AVR32_V2),
  27059. + SYNTAX_NORMAL3(ADDVC, ADDVC, ADDVC, INTREG, INTREG, INTREG, AVR32_V2),
  27060. + SYNTAX_NORMAL3(ADDQS, ADDQS, ADDQS, INTREG, INTREG, INTREG, AVR32_V2),
  27061. + SYNTAX_NORMAL3(ADDAL, ADDAL, ADDAL, INTREG, INTREG, INTREG, AVR32_V2),
  27062. + SYNTAX_NORMAL3(ADDHS, ADDHS, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
  27063. + SYNTAX_NORMAL3(ADDLO, ADDLO, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
  27064. + SYNTAX_NORMAL3(SUB2EQ, SUBEQ, SUB2EQ, INTREG, INTREG, INTREG, AVR32_V2),
  27065. + SYNTAX_NORMAL3(SUB2NE, SUBNE, SUB2NE, INTREG, INTREG, INTREG, AVR32_V2),
  27066. + SYNTAX_NORMAL3(SUB2CC, SUBCC, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
  27067. + SYNTAX_NORMAL3(SUB2CS, SUBCS, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
  27068. + SYNTAX_NORMAL3(SUB2GE, SUBGE, SUB2GE, INTREG, INTREG, INTREG, AVR32_V2),
  27069. + SYNTAX_NORMAL3(SUB2LT, SUBLT, SUB2LT, INTREG, INTREG, INTREG, AVR32_V2),
  27070. + SYNTAX_NORMAL3(SUB2MI, SUBMI, SUB2MI, INTREG, INTREG, INTREG, AVR32_V2),
  27071. + SYNTAX_NORMAL3(SUB2PL, SUBPL, SUB2PL, INTREG, INTREG, INTREG, AVR32_V2),
  27072. + SYNTAX_NORMAL3(SUB2LS, SUBLS, SUB2LS, INTREG, INTREG, INTREG, AVR32_V2),
  27073. + SYNTAX_NORMAL3(SUB2GT, SUBGT, SUB2GT, INTREG, INTREG, INTREG, AVR32_V2),
  27074. + SYNTAX_NORMAL3(SUB2LE, SUBLE, SUB2LE, INTREG, INTREG, INTREG, AVR32_V2),
  27075. + SYNTAX_NORMAL3(SUB2HI, SUBHI, SUB2HI, INTREG, INTREG, INTREG, AVR32_V2),
  27076. + SYNTAX_NORMAL3(SUB2VS, SUBVS, SUB2VS, INTREG, INTREG, INTREG, AVR32_V2),
  27077. + SYNTAX_NORMAL3(SUB2VC, SUBVC, SUB2VC, INTREG, INTREG, INTREG, AVR32_V2),
  27078. + SYNTAX_NORMAL3(SUB2QS, SUBQS, SUB2QS, INTREG, INTREG, INTREG, AVR32_V2),
  27079. + SYNTAX_NORMAL3(SUB2AL, SUBAL, SUB2AL, INTREG, INTREG, INTREG, AVR32_V2),
  27080. + SYNTAX_NORMAL3(SUB2HS, SUBHS, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
  27081. + SYNTAX_NORMAL3(SUB2LO, SUBLO, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
  27082. + SYNTAX_NORMAL3(ANDEQ, ANDEQ, ANDEQ, INTREG, INTREG, INTREG, AVR32_V2),
  27083. + SYNTAX_NORMAL3(ANDNE, ANDNE, ANDNE, INTREG, INTREG, INTREG, AVR32_V2),
  27084. + SYNTAX_NORMAL3(ANDCC, ANDCC, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
  27085. + SYNTAX_NORMAL3(ANDCS, ANDCS, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
  27086. + SYNTAX_NORMAL3(ANDGE, ANDGE, ANDGE, INTREG, INTREG, INTREG, AVR32_V2),
  27087. + SYNTAX_NORMAL3(ANDLT, ANDLT, ANDLT, INTREG, INTREG, INTREG, AVR32_V2),
  27088. + SYNTAX_NORMAL3(ANDMI, ANDMI, ANDMI, INTREG, INTREG, INTREG, AVR32_V2),
  27089. + SYNTAX_NORMAL3(ANDPL, ANDPL, ANDPL, INTREG, INTREG, INTREG, AVR32_V2),
  27090. + SYNTAX_NORMAL3(ANDLS, ANDLS, ANDLS, INTREG, INTREG, INTREG, AVR32_V2),
  27091. + SYNTAX_NORMAL3(ANDGT, ANDGT, ANDGT, INTREG, INTREG, INTREG, AVR32_V2),
  27092. + SYNTAX_NORMAL3(ANDLE, ANDLE, ANDLE, INTREG, INTREG, INTREG, AVR32_V2),
  27093. + SYNTAX_NORMAL3(ANDHI, ANDHI, ANDHI, INTREG, INTREG, INTREG, AVR32_V2),
  27094. + SYNTAX_NORMAL3(ANDVS, ANDVS, ANDVS, INTREG, INTREG, INTREG, AVR32_V2),
  27095. + SYNTAX_NORMAL3(ANDVC, ANDVC, ANDVC, INTREG, INTREG, INTREG, AVR32_V2),
  27096. + SYNTAX_NORMAL3(ANDQS, ANDQS, ANDQS, INTREG, INTREG, INTREG, AVR32_V2),
  27097. + SYNTAX_NORMAL3(ANDAL, ANDAL, ANDAL, INTREG, INTREG, INTREG, AVR32_V2),
  27098. + SYNTAX_NORMAL3(ANDHS, ANDHS, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
  27099. + SYNTAX_NORMAL3(ANDLO, ANDLO, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
  27100. + SYNTAX_NORMAL3(OREQ, OREQ, OREQ, INTREG, INTREG, INTREG, AVR32_V2),
  27101. + SYNTAX_NORMAL3(ORNE, ORNE, ORNE, INTREG, INTREG, INTREG, AVR32_V2),
  27102. + SYNTAX_NORMAL3(ORCC, ORCC, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
  27103. + SYNTAX_NORMAL3(ORCS, ORCS, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
  27104. + SYNTAX_NORMAL3(ORGE, ORGE, ORGE, INTREG, INTREG, INTREG, AVR32_V2),
  27105. + SYNTAX_NORMAL3(ORLT, ORLT, ORLT, INTREG, INTREG, INTREG, AVR32_V2),
  27106. + SYNTAX_NORMAL3(ORMI, ORMI, ORMI, INTREG, INTREG, INTREG, AVR32_V2),
  27107. + SYNTAX_NORMAL3(ORPL, ORPL, ORPL, INTREG, INTREG, INTREG, AVR32_V2),
  27108. + SYNTAX_NORMAL3(ORLS, ORLS, ORLS, INTREG, INTREG, INTREG, AVR32_V2),
  27109. + SYNTAX_NORMAL3(ORGT, ORGT, ORGT, INTREG, INTREG, INTREG, AVR32_V2),
  27110. + SYNTAX_NORMAL3(ORLE, ORLE, ORLE, INTREG, INTREG, INTREG, AVR32_V2),
  27111. + SYNTAX_NORMAL3(ORHI, ORHI, ORHI, INTREG, INTREG, INTREG, AVR32_V2),
  27112. + SYNTAX_NORMAL3(ORVS, ORVS, ORVS, INTREG, INTREG, INTREG, AVR32_V2),
  27113. + SYNTAX_NORMAL3(ORVC, ORVC, ORVC, INTREG, INTREG, INTREG, AVR32_V2),
  27114. + SYNTAX_NORMAL3(ORQS, ORQS, ORQS, INTREG, INTREG, INTREG, AVR32_V2),
  27115. + SYNTAX_NORMAL3(ORAL, ORAL, ORAL, INTREG, INTREG, INTREG, AVR32_V2),
  27116. + SYNTAX_NORMAL3(ORHS, ORHS, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
  27117. + SYNTAX_NORMAL3(ORLO, ORLO, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
  27118. + SYNTAX_NORMAL3(EOREQ, EOREQ, EOREQ, INTREG, INTREG, INTREG, AVR32_V2),
  27119. + SYNTAX_NORMAL3(EORNE, EORNE, EORNE, INTREG, INTREG, INTREG, AVR32_V2),
  27120. + SYNTAX_NORMAL3(EORCC, EORCC, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
  27121. + SYNTAX_NORMAL3(EORCS, EORCS, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
  27122. + SYNTAX_NORMAL3(EORGE, EORGE, EORGE, INTREG, INTREG, INTREG, AVR32_V2),
  27123. + SYNTAX_NORMAL3(EORLT, EORLT, EORLT, INTREG, INTREG, INTREG, AVR32_V2),
  27124. + SYNTAX_NORMAL3(EORMI, EORMI, EORMI, INTREG, INTREG, INTREG, AVR32_V2),
  27125. + SYNTAX_NORMAL3(EORPL, EORPL, EORPL, INTREG, INTREG, INTREG, AVR32_V2),
  27126. + SYNTAX_NORMAL3(EORLS, EORLS, EORLS, INTREG, INTREG, INTREG, AVR32_V2),
  27127. + SYNTAX_NORMAL3(EORGT, EORGT, EORGT, INTREG, INTREG, INTREG, AVR32_V2),
  27128. + SYNTAX_NORMAL3(EORLE, EORLE, EORLE, INTREG, INTREG, INTREG, AVR32_V2),
  27129. + SYNTAX_NORMAL3(EORHI, EORHI, EORHI, INTREG, INTREG, INTREG, AVR32_V2),
  27130. + SYNTAX_NORMAL3(EORVS, EORVS, EORVS, INTREG, INTREG, INTREG, AVR32_V2),
  27131. + SYNTAX_NORMAL3(EORVC, EORVC, EORVC, INTREG, INTREG, INTREG, AVR32_V2),
  27132. + SYNTAX_NORMAL3(EORQS, EORQS, EORQS, INTREG, INTREG, INTREG, AVR32_V2),
  27133. + SYNTAX_NORMAL3(EORAL, EORAL, EORAL, INTREG, INTREG, INTREG, AVR32_V2),
  27134. + SYNTAX_NORMAL3(EORHS, EORHS, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
  27135. + SYNTAX_NORMAL3(EORLO, EORLO, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
  27136. + SYNTAX_NORMAL2(LD_WEQ, LD_WEQ, LD_WEQ, INTREG, INTREG_UDISP_W, AVR32_V2),
  27137. + SYNTAX_NORMAL2(LD_WNE, LD_WNE, LD_WNE, INTREG, INTREG_UDISP_W, AVR32_V2),
  27138. + SYNTAX_NORMAL2(LD_WCC, LD_WCC, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
  27139. + SYNTAX_NORMAL2(LD_WCS, LD_WCS, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
  27140. + SYNTAX_NORMAL2(LD_WGE, LD_WGE, LD_WGE, INTREG, INTREG_UDISP_W, AVR32_V2),
  27141. + SYNTAX_NORMAL2(LD_WLT, LD_WLT, LD_WLT, INTREG, INTREG_UDISP_W, AVR32_V2),
  27142. + SYNTAX_NORMAL2(LD_WMI, LD_WMI, LD_WMI, INTREG, INTREG_UDISP_W, AVR32_V2),
  27143. + SYNTAX_NORMAL2(LD_WPL, LD_WPL, LD_WPL, INTREG, INTREG_UDISP_W, AVR32_V2),
  27144. + SYNTAX_NORMAL2(LD_WLS, LD_WLS, LD_WLS, INTREG, INTREG_UDISP_W, AVR32_V2),
  27145. + SYNTAX_NORMAL2(LD_WGT, LD_WGT, LD_WGT, INTREG, INTREG_UDISP_W, AVR32_V2),
  27146. + SYNTAX_NORMAL2(LD_WLE, LD_WLE, LD_WLE, INTREG, INTREG_UDISP_W, AVR32_V2),
  27147. + SYNTAX_NORMAL2(LD_WHI, LD_WHI, LD_WHI, INTREG, INTREG_UDISP_W, AVR32_V2),
  27148. + SYNTAX_NORMAL2(LD_WVS, LD_WVS, LD_WVS, INTREG, INTREG_UDISP_W, AVR32_V2),
  27149. + SYNTAX_NORMAL2(LD_WVC, LD_WVC, LD_WVC, INTREG, INTREG_UDISP_W, AVR32_V2),
  27150. + SYNTAX_NORMAL2(LD_WQS, LD_WQS, LD_WQS, INTREG, INTREG_UDISP_W, AVR32_V2),
  27151. + SYNTAX_NORMAL2(LD_WAL, LD_WAL, LD_WAL, INTREG, INTREG_UDISP_W, AVR32_V2),
  27152. + SYNTAX_NORMAL2(LD_WHS, LD_WHS, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
  27153. + SYNTAX_NORMAL2(LD_WLO, LD_WLO, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
  27154. + SYNTAX_NORMAL2(LD_SHEQ, LD_SHEQ, LD_SHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
  27155. + SYNTAX_NORMAL2(LD_SHNE, LD_SHNE, LD_SHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
  27156. + SYNTAX_NORMAL2(LD_SHCC, LD_SHCC, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
  27157. + SYNTAX_NORMAL2(LD_SHCS, LD_SHCS, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27158. + SYNTAX_NORMAL2(LD_SHGE, LD_SHGE, LD_SHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
  27159. + SYNTAX_NORMAL2(LD_SHLT, LD_SHLT, LD_SHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
  27160. + SYNTAX_NORMAL2(LD_SHMI, LD_SHMI, LD_SHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
  27161. + SYNTAX_NORMAL2(LD_SHPL, LD_SHPL, LD_SHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
  27162. + SYNTAX_NORMAL2(LD_SHLS, LD_SHLS, LD_SHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27163. + SYNTAX_NORMAL2(LD_SHGT, LD_SHGT, LD_SHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
  27164. + SYNTAX_NORMAL2(LD_SHLE, LD_SHLE, LD_SHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
  27165. + SYNTAX_NORMAL2(LD_SHHI, LD_SHHI, LD_SHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
  27166. + SYNTAX_NORMAL2(LD_SHVS, LD_SHVS, LD_SHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27167. + SYNTAX_NORMAL2(LD_SHVC, LD_SHVC, LD_SHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
  27168. + SYNTAX_NORMAL2(LD_SHQS, LD_SHQS, LD_SHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27169. + SYNTAX_NORMAL2(LD_SHAL, LD_SHAL, LD_SHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
  27170. + SYNTAX_NORMAL2(LD_SHHS, LD_SHHS, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
  27171. + SYNTAX_NORMAL2(LD_SHLO, LD_SHLO, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27172. + SYNTAX_NORMAL2(LD_UHEQ, LD_UHEQ, LD_UHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
  27173. + SYNTAX_NORMAL2(LD_UHNE, LD_UHNE, LD_UHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
  27174. + SYNTAX_NORMAL2(LD_UHCC, LD_UHCC, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
  27175. + SYNTAX_NORMAL2(LD_UHCS, LD_UHCS, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27176. + SYNTAX_NORMAL2(LD_UHGE, LD_UHGE, LD_UHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
  27177. + SYNTAX_NORMAL2(LD_UHLT, LD_UHLT, LD_UHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
  27178. + SYNTAX_NORMAL2(LD_UHMI, LD_UHMI, LD_UHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
  27179. + SYNTAX_NORMAL2(LD_UHPL, LD_UHPL, LD_UHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
  27180. + SYNTAX_NORMAL2(LD_UHLS, LD_UHLS, LD_UHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27181. + SYNTAX_NORMAL2(LD_UHGT, LD_UHGT, LD_UHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
  27182. + SYNTAX_NORMAL2(LD_UHLE, LD_UHLE, LD_UHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
  27183. + SYNTAX_NORMAL2(LD_UHHI, LD_UHHI, LD_UHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
  27184. + SYNTAX_NORMAL2(LD_UHVS, LD_UHVS, LD_UHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27185. + SYNTAX_NORMAL2(LD_UHVC, LD_UHVC, LD_UHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
  27186. + SYNTAX_NORMAL2(LD_UHQS, LD_UHQS, LD_UHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27187. + SYNTAX_NORMAL2(LD_UHAL, LD_UHAL, LD_UHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
  27188. + SYNTAX_NORMAL2(LD_UHHS, LD_UHHS, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
  27189. + SYNTAX_NORMAL2(LD_UHLO, LD_UHLO, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
  27190. + SYNTAX_NORMAL2(LD_SBEQ, LD_SBEQ, LD_SBEQ, INTREG, INTREG_UDISP, AVR32_V2),
  27191. + SYNTAX_NORMAL2(LD_SBNE, LD_SBNE, LD_SBNE, INTREG, INTREG_UDISP, AVR32_V2),
  27192. + SYNTAX_NORMAL2(LD_SBCC, LD_SBCC, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
  27193. + SYNTAX_NORMAL2(LD_SBCS, LD_SBCS, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
  27194. + SYNTAX_NORMAL2(LD_SBGE, LD_SBGE, LD_SBGE, INTREG, INTREG_UDISP, AVR32_V2),
  27195. + SYNTAX_NORMAL2(LD_SBLT, LD_SBLT, LD_SBLT, INTREG, INTREG_UDISP, AVR32_V2),
  27196. + SYNTAX_NORMAL2(LD_SBMI, LD_SBMI, LD_SBMI, INTREG, INTREG_UDISP, AVR32_V2),
  27197. + SYNTAX_NORMAL2(LD_SBPL, LD_SBPL, LD_SBPL, INTREG, INTREG_UDISP, AVR32_V2),
  27198. + SYNTAX_NORMAL2(LD_SBLS, LD_SBLS, LD_SBLS, INTREG, INTREG_UDISP, AVR32_V2),
  27199. + SYNTAX_NORMAL2(LD_SBGT, LD_SBGT, LD_SBGT, INTREG, INTREG_UDISP, AVR32_V2),
  27200. + SYNTAX_NORMAL2(LD_SBLE, LD_SBLE, LD_SBLE, INTREG, INTREG_UDISP, AVR32_V2),
  27201. + SYNTAX_NORMAL2(LD_SBHI, LD_SBHI, LD_SBHI, INTREG, INTREG_UDISP, AVR32_V2),
  27202. + SYNTAX_NORMAL2(LD_SBVS, LD_SBVS, LD_SBVS, INTREG, INTREG_UDISP, AVR32_V2),
  27203. + SYNTAX_NORMAL2(LD_SBVC, LD_SBVC, LD_SBVC, INTREG, INTREG_UDISP, AVR32_V2),
  27204. + SYNTAX_NORMAL2(LD_SBQS, LD_SBQS, LD_SBQS, INTREG, INTREG_UDISP, AVR32_V2),
  27205. + SYNTAX_NORMAL2(LD_SBAL, LD_SBAL, LD_SBAL, INTREG, INTREG_UDISP, AVR32_V2),
  27206. + SYNTAX_NORMAL2(LD_SBHS, LD_SBHS, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
  27207. + SYNTAX_NORMAL2(LD_SBLO, LD_SBLO, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
  27208. + SYNTAX_NORMAL2(LD_UBEQ, LD_UBEQ, LD_UBEQ, INTREG, INTREG_UDISP, AVR32_V2),
  27209. + SYNTAX_NORMAL2(LD_UBNE, LD_UBNE, LD_UBNE, INTREG, INTREG_UDISP, AVR32_V2),
  27210. + SYNTAX_NORMAL2(LD_UBCC, LD_UBCC, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
  27211. + SYNTAX_NORMAL2(LD_UBCS, LD_UBCS, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
  27212. + SYNTAX_NORMAL2(LD_UBGE, LD_UBGE, LD_UBGE, INTREG, INTREG_UDISP, AVR32_V2),
  27213. + SYNTAX_NORMAL2(LD_UBLT, LD_UBLT, LD_UBLT, INTREG, INTREG_UDISP, AVR32_V2),
  27214. + SYNTAX_NORMAL2(LD_UBMI, LD_UBMI, LD_UBMI, INTREG, INTREG_UDISP, AVR32_V2),
  27215. + SYNTAX_NORMAL2(LD_UBPL, LD_UBPL, LD_UBPL, INTREG, INTREG_UDISP, AVR32_V2),
  27216. + SYNTAX_NORMAL2(LD_UBLS, LD_UBLS, LD_UBLS, INTREG, INTREG_UDISP, AVR32_V2),
  27217. + SYNTAX_NORMAL2(LD_UBGT, LD_UBGT, LD_UBGT, INTREG, INTREG_UDISP, AVR32_V2),
  27218. + SYNTAX_NORMAL2(LD_UBLE, LD_UBLE, LD_UBLE, INTREG, INTREG_UDISP, AVR32_V2),
  27219. + SYNTAX_NORMAL2(LD_UBHI, LD_UBHI, LD_UBHI, INTREG, INTREG_UDISP, AVR32_V2),
  27220. + SYNTAX_NORMAL2(LD_UBVS, LD_UBVS, LD_UBVS, INTREG, INTREG_UDISP, AVR32_V2),
  27221. + SYNTAX_NORMAL2(LD_UBVC, LD_UBVC, LD_UBVC, INTREG, INTREG_UDISP, AVR32_V2),
  27222. + SYNTAX_NORMAL2(LD_UBQS, LD_UBQS, LD_UBQS, INTREG, INTREG_UDISP, AVR32_V2),
  27223. + SYNTAX_NORMAL2(LD_UBAL, LD_UBAL, LD_UBAL, INTREG, INTREG_UDISP, AVR32_V2),
  27224. + SYNTAX_NORMAL2(LD_UBHS, LD_UBHS, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
  27225. + SYNTAX_NORMAL2(LD_UBLO, LD_UBLO, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
  27226. + SYNTAX_NORMAL2(ST_WEQ, ST_WEQ, ST_WEQ, INTREG_UDISP_W, INTREG, AVR32_V2),
  27227. + SYNTAX_NORMAL2(ST_WNE, ST_WNE, ST_WNE, INTREG_UDISP_W, INTREG, AVR32_V2),
  27228. + SYNTAX_NORMAL2(ST_WCC, ST_WCC, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
  27229. + SYNTAX_NORMAL2(ST_WCS, ST_WCS, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
  27230. + SYNTAX_NORMAL2(ST_WGE, ST_WGE, ST_WGE, INTREG_UDISP_W, INTREG, AVR32_V2),
  27231. + SYNTAX_NORMAL2(ST_WLT, ST_WLT, ST_WLT, INTREG_UDISP_W, INTREG, AVR32_V2),
  27232. + SYNTAX_NORMAL2(ST_WMI, ST_WMI, ST_WMI, INTREG_UDISP_W, INTREG, AVR32_V2),
  27233. + SYNTAX_NORMAL2(ST_WPL, ST_WPL, ST_WPL, INTREG_UDISP_W, INTREG, AVR32_V2),
  27234. + SYNTAX_NORMAL2(ST_WLS, ST_WLS, ST_WLS, INTREG_UDISP_W, INTREG, AVR32_V2),
  27235. + SYNTAX_NORMAL2(ST_WGT, ST_WGT, ST_WGT, INTREG_UDISP_W, INTREG, AVR32_V2),
  27236. + SYNTAX_NORMAL2(ST_WLE, ST_WLE, ST_WLE, INTREG_UDISP_W, INTREG, AVR32_V2),
  27237. + SYNTAX_NORMAL2(ST_WHI, ST_WHI, ST_WHI, INTREG_UDISP_W, INTREG, AVR32_V2),
  27238. + SYNTAX_NORMAL2(ST_WVS, ST_WVS, ST_WVS, INTREG_UDISP_W, INTREG, AVR32_V2),
  27239. + SYNTAX_NORMAL2(ST_WVC, ST_WVC, ST_WVC, INTREG_UDISP_W, INTREG, AVR32_V2),
  27240. + SYNTAX_NORMAL2(ST_WQS, ST_WQS, ST_WQS, INTREG_UDISP_W, INTREG, AVR32_V2),
  27241. + SYNTAX_NORMAL2(ST_WAL, ST_WAL, ST_WAL, INTREG_UDISP_W, INTREG, AVR32_V2),
  27242. + SYNTAX_NORMAL2(ST_WHS, ST_WHS, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
  27243. + SYNTAX_NORMAL2(ST_WLO, ST_WLO, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
  27244. + SYNTAX_NORMAL2(ST_HEQ, ST_HEQ, ST_HEQ, INTREG_UDISP_H, INTREG, AVR32_V2),
  27245. + SYNTAX_NORMAL2(ST_HNE, ST_HNE, ST_HNE, INTREG_UDISP_H, INTREG, AVR32_V2),
  27246. + SYNTAX_NORMAL2(ST_HCC, ST_HCC, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
  27247. + SYNTAX_NORMAL2(ST_HCS, ST_HCS, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
  27248. + SYNTAX_NORMAL2(ST_HGE, ST_HGE, ST_HGE, INTREG_UDISP_H, INTREG, AVR32_V2),
  27249. + SYNTAX_NORMAL2(ST_HLT, ST_HLT, ST_HLT, INTREG_UDISP_H, INTREG, AVR32_V2),
  27250. + SYNTAX_NORMAL2(ST_HMI, ST_HMI, ST_HMI, INTREG_UDISP_H, INTREG, AVR32_V2),
  27251. + SYNTAX_NORMAL2(ST_HPL, ST_HPL, ST_HPL, INTREG_UDISP_H, INTREG, AVR32_V2),
  27252. + SYNTAX_NORMAL2(ST_HLS, ST_HLS, ST_HLS, INTREG_UDISP_H, INTREG, AVR32_V2),
  27253. + SYNTAX_NORMAL2(ST_HGT, ST_HGT, ST_HGT, INTREG_UDISP_H, INTREG, AVR32_V2),
  27254. + SYNTAX_NORMAL2(ST_HLE, ST_HLE, ST_HLE, INTREG_UDISP_H, INTREG, AVR32_V2),
  27255. + SYNTAX_NORMAL2(ST_HHI, ST_HHI, ST_HHI, INTREG_UDISP_H, INTREG, AVR32_V2),
  27256. + SYNTAX_NORMAL2(ST_HVS, ST_HVS, ST_HVS, INTREG_UDISP_H, INTREG, AVR32_V2),
  27257. + SYNTAX_NORMAL2(ST_HVC, ST_HVC, ST_HVC, INTREG_UDISP_H, INTREG, AVR32_V2),
  27258. + SYNTAX_NORMAL2(ST_HQS, ST_HQS, ST_HQS, INTREG_UDISP_H, INTREG, AVR32_V2),
  27259. + SYNTAX_NORMAL2(ST_HAL, ST_HAL, ST_HAL, INTREG_UDISP_H, INTREG, AVR32_V2),
  27260. + SYNTAX_NORMAL2(ST_HHS, ST_HHS, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
  27261. + SYNTAX_NORMAL2(ST_HLO, ST_HLO, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
  27262. + SYNTAX_NORMAL2(ST_BEQ, ST_BEQ, ST_BEQ, INTREG_UDISP, INTREG, AVR32_V2),
  27263. + SYNTAX_NORMAL2(ST_BNE, ST_BNE, ST_BNE, INTREG_UDISP, INTREG, AVR32_V2),
  27264. + SYNTAX_NORMAL2(ST_BCC, ST_BCC, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
  27265. + SYNTAX_NORMAL2(ST_BCS, ST_BCS, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
  27266. + SYNTAX_NORMAL2(ST_BGE, ST_BGE, ST_BGE, INTREG_UDISP, INTREG, AVR32_V2),
  27267. + SYNTAX_NORMAL2(ST_BLT, ST_BLT, ST_BLT, INTREG_UDISP, INTREG, AVR32_V2),
  27268. + SYNTAX_NORMAL2(ST_BMI, ST_BMI, ST_BMI, INTREG_UDISP, INTREG, AVR32_V2),
  27269. + SYNTAX_NORMAL2(ST_BPL, ST_BPL, ST_BPL, INTREG_UDISP, INTREG, AVR32_V2),
  27270. + SYNTAX_NORMAL2(ST_BLS, ST_BLS, ST_BLS, INTREG_UDISP, INTREG, AVR32_V2),
  27271. + SYNTAX_NORMAL2(ST_BGT, ST_BGT, ST_BGT, INTREG_UDISP, INTREG, AVR32_V2),
  27272. + SYNTAX_NORMAL2(ST_BLE, ST_BLE, ST_BLE, INTREG_UDISP, INTREG, AVR32_V2),
  27273. + SYNTAX_NORMAL2(ST_BHI, ST_BHI, ST_BHI, INTREG_UDISP, INTREG, AVR32_V2),
  27274. + SYNTAX_NORMAL2(ST_BVS, ST_BVS, ST_BVS, INTREG_UDISP, INTREG, AVR32_V2),
  27275. + SYNTAX_NORMAL2(ST_BVC, ST_BVC, ST_BVC, INTREG_UDISP, INTREG, AVR32_V2),
  27276. + SYNTAX_NORMAL2(ST_BQS, ST_BQS, ST_BQS, INTREG_UDISP, INTREG, AVR32_V2),
  27277. + SYNTAX_NORMAL2(ST_BAL, ST_BAL, ST_BAL, INTREG_UDISP, INTREG, AVR32_V2),
  27278. + SYNTAX_NORMAL2(ST_BHS, ST_BHS, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
  27279. + SYNTAX_NORMAL2(ST_BLO, ST_BLO, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
  27280. + SYNTAX_NORMAL2(MOVH, MOVH, MOVH, INTREG, UNSIGNED_CONST, AVR32_V2),
  27281. +
  27282. + };
  27283. +
  27284. +#define NORMAL_MNEMONIC(name, syntax, str) \
  27285. + { \
  27286. + AVR32_MNEMONIC_##name, str, \
  27287. + &avr32_syntax_table[AVR32_SYNTAX_##syntax], \
  27288. + }
  27289. +#define FP_MNEMONIC(name, syntax, str) \
  27290. + NORMAL_MNEMONIC(name##_S, syntax##_S, str ".s"), \
  27291. + NORMAL_MNEMONIC(name##_D, syntax##_D, str ".d")
  27292. +
  27293. +const struct avr32_mnemonic avr32_mnemonic_table[] =
  27294. + {
  27295. + NORMAL_MNEMONIC(ABS, ABS, "abs"),
  27296. + NORMAL_MNEMONIC(ACALL, ACALL, "acall"),
  27297. + NORMAL_MNEMONIC(ACR, ACR, "acr"),
  27298. + NORMAL_MNEMONIC(ADC, ADC, "adc"),
  27299. + NORMAL_MNEMONIC(ADD, ADD1, "add"),
  27300. + NORMAL_MNEMONIC(ADDABS, ADDABS, "addabs"),
  27301. + NORMAL_MNEMONIC(ADDHH_W, ADDHH_W, "addhh.w"),
  27302. + NORMAL_MNEMONIC(AND, AND1, "and"),
  27303. + NORMAL_MNEMONIC(ANDH, ANDH, "andh"),
  27304. + NORMAL_MNEMONIC(ANDL, ANDL, "andl"),
  27305. + NORMAL_MNEMONIC(ANDN, ANDN, "andn"),
  27306. + NORMAL_MNEMONIC(ASR, ASR1, "asr"),
  27307. + NORMAL_MNEMONIC(BFEXTS, BFEXTS, "bfexts"),
  27308. + NORMAL_MNEMONIC(BFEXTU, BFEXTU, "bfextu"),
  27309. + NORMAL_MNEMONIC(BFINS, BFINS, "bfins"),
  27310. + NORMAL_MNEMONIC(BLD, BLD, "bld"),
  27311. + NORMAL_MNEMONIC(BREQ, BREQ1, "breq"),
  27312. + NORMAL_MNEMONIC(BRNE, BRNE1, "brne"),
  27313. + NORMAL_MNEMONIC(BRCC, BRCC1, "brcc"),
  27314. + NORMAL_MNEMONIC(BRCS, BRCS1, "brcs"),
  27315. + NORMAL_MNEMONIC(BRGE, BRGE1, "brge"),
  27316. + NORMAL_MNEMONIC(BRLT, BRLT1, "brlt"),
  27317. + NORMAL_MNEMONIC(BRMI, BRMI1, "brmi"),
  27318. + NORMAL_MNEMONIC(BRPL, BRPL1, "brpl"),
  27319. + NORMAL_MNEMONIC(BRHS, BRHS1, "brhs"),
  27320. + NORMAL_MNEMONIC(BRLO, BRLO1, "brlo"),
  27321. + NORMAL_MNEMONIC(BRLS, BRLS, "brls"),
  27322. + NORMAL_MNEMONIC(BRGT, BRGT, "brgt"),
  27323. + NORMAL_MNEMONIC(BRLE, BRLE, "brle"),
  27324. + NORMAL_MNEMONIC(BRHI, BRHI, "brhi"),
  27325. + NORMAL_MNEMONIC(BRVS, BRVS, "brvs"),
  27326. + NORMAL_MNEMONIC(BRVC, BRVC, "brvc"),
  27327. + NORMAL_MNEMONIC(BRQS, BRQS, "brqs"),
  27328. + NORMAL_MNEMONIC(BRAL, BRAL, "bral"),
  27329. + NORMAL_MNEMONIC(BREAKPOINT, BREAKPOINT, "breakpoint"),
  27330. + NORMAL_MNEMONIC(BREV, BREV, "brev"),
  27331. + NORMAL_MNEMONIC(BST, BST, "bst"),
  27332. + NORMAL_MNEMONIC(CACHE, CACHE, "cache"),
  27333. + NORMAL_MNEMONIC(CASTS_B, CASTS_B, "casts.b"),
  27334. + NORMAL_MNEMONIC(CASTS_H, CASTS_H, "casts.h"),
  27335. + NORMAL_MNEMONIC(CASTU_B, CASTU_B, "castu.b"),
  27336. + NORMAL_MNEMONIC(CASTU_H, CASTU_H, "castu.h"),
  27337. + NORMAL_MNEMONIC(CBR, CBR, "cbr"),
  27338. + NORMAL_MNEMONIC(CLZ, CLZ, "clz"),
  27339. + NORMAL_MNEMONIC(COM, COM, "com"),
  27340. + NORMAL_MNEMONIC(COP, COP, "cop"),
  27341. + NORMAL_MNEMONIC(CP_B, CP_B, "cp.b"),
  27342. + NORMAL_MNEMONIC(CP_H, CP_H, "cp.h"),
  27343. + NORMAL_MNEMONIC(CP_W, CP_W1, "cp.w"),
  27344. + NORMAL_MNEMONIC(CP, CP_W1, "cp"),
  27345. + NORMAL_MNEMONIC(CPC, CPC1, "cpc"),
  27346. + NORMAL_MNEMONIC(CSRF, CSRF, "csrf"),
  27347. + NORMAL_MNEMONIC(CSRFCZ, CSRFCZ, "csrfcz"),
  27348. + NORMAL_MNEMONIC(DIVS, DIVS, "divs"),
  27349. + NORMAL_MNEMONIC(DIVU, DIVU, "divu"),
  27350. + NORMAL_MNEMONIC(EOR, EOR1, "eor"),
  27351. + NORMAL_MNEMONIC(EORL, EORL, "eorl"),
  27352. + NORMAL_MNEMONIC(EORH, EORH, "eorh"),
  27353. + NORMAL_MNEMONIC(FRS, FRS, "frs"),
  27354. + NORMAL_MNEMONIC(SSCALL, SSCALL, "sscall"),
  27355. + NORMAL_MNEMONIC(RETSS, RETSS, "retss"),
  27356. + NORMAL_MNEMONIC(ICALL, ICALL, "icall"),
  27357. + NORMAL_MNEMONIC(INCJOSP, INCJOSP, "incjosp"),
  27358. + NORMAL_MNEMONIC(LD_D, LD_D1, "ld.d"),
  27359. + NORMAL_MNEMONIC(LD_SB, LD_SB2, "ld.sb"),
  27360. + NORMAL_MNEMONIC(LD_UB, LD_UB1, "ld.ub"),
  27361. + NORMAL_MNEMONIC(LD_SH, LD_SH1, "ld.sh"),
  27362. + NORMAL_MNEMONIC(LD_UH, LD_UH1, "ld.uh"),
  27363. + NORMAL_MNEMONIC(LD_W, LD_W1, "ld.w"),
  27364. + NORMAL_MNEMONIC(LDC_D, LDC_D3, "ldc.d"),
  27365. + NORMAL_MNEMONIC(LDC_W, LDC_W3, "ldc.w"),
  27366. + NORMAL_MNEMONIC(LDC0_D, LDC0_D, "ldc0.d"),
  27367. + NORMAL_MNEMONIC(LDC0_W, LDC0_W, "ldc0.w"),
  27368. + NORMAL_MNEMONIC(LDCM_D, LDCM_D, "ldcm.d"),
  27369. + NORMAL_MNEMONIC(LDCM_W, LDCM_W, "ldcm.w"),
  27370. + NORMAL_MNEMONIC(LDDPC, LDDPC, "lddpc"),
  27371. + NORMAL_MNEMONIC(LDDSP, LDDSP, "lddsp"),
  27372. + NORMAL_MNEMONIC(LDINS_B, LDINS_B, "ldins.b"),
  27373. + NORMAL_MNEMONIC(LDINS_H, LDINS_H, "ldins.h"),
  27374. + NORMAL_MNEMONIC(LDM, LDM, "ldm"),
  27375. + NORMAL_MNEMONIC(LDMTS, LDMTS, "ldmts"),
  27376. + NORMAL_MNEMONIC(LDSWP_SH, LDSWP_SH, "ldswp.sh"),
  27377. + NORMAL_MNEMONIC(LDSWP_UH, LDSWP_UH, "ldswp.uh"),
  27378. + NORMAL_MNEMONIC(LDSWP_W, LDSWP_W, "ldswp.w"),
  27379. + NORMAL_MNEMONIC(LSL, LSL1, "lsl"),
  27380. + NORMAL_MNEMONIC(LSR, LSR1, "lsr"),
  27381. + NORMAL_MNEMONIC(MAC, MAC, "mac"),
  27382. + NORMAL_MNEMONIC(MACHH_D, MACHH_D, "machh.d"),
  27383. + NORMAL_MNEMONIC(MACHH_W, MACHH_W, "machh.w"),
  27384. + NORMAL_MNEMONIC(MACS_D, MACS_D, "macs.d"),
  27385. + NORMAL_MNEMONIC(MACSATHH_W, MACSATHH_W, "macsathh.w"),
  27386. + NORMAL_MNEMONIC(MACU_D, MACUD, "macu.d"),
  27387. + NORMAL_MNEMONIC(MACWH_D, MACWH_D, "macwh.d"),
  27388. + NORMAL_MNEMONIC(MAX, MAX, "max"),
  27389. + NORMAL_MNEMONIC(MCALL, MCALL, "mcall"),
  27390. + NORMAL_MNEMONIC(MFDR, MFDR, "mfdr"),
  27391. + NORMAL_MNEMONIC(MFSR, MFSR, "mfsr"),
  27392. + NORMAL_MNEMONIC(MIN, MIN, "min"),
  27393. + NORMAL_MNEMONIC(MOV, MOV3, "mov"),
  27394. + NORMAL_MNEMONIC(MOVEQ, MOVEQ1, "moveq"),
  27395. + NORMAL_MNEMONIC(MOVNE, MOVNE1, "movne"),
  27396. + NORMAL_MNEMONIC(MOVCC, MOVCC1, "movcc"),
  27397. + NORMAL_MNEMONIC(MOVCS, MOVCS1, "movcs"),
  27398. + NORMAL_MNEMONIC(MOVGE, MOVGE1, "movge"),
  27399. + NORMAL_MNEMONIC(MOVLT, MOVLT1, "movlt"),
  27400. + NORMAL_MNEMONIC(MOVMI, MOVMI1, "movmi"),
  27401. + NORMAL_MNEMONIC(MOVPL, MOVPL1, "movpl"),
  27402. + NORMAL_MNEMONIC(MOVLS, MOVLS1, "movls"),
  27403. + NORMAL_MNEMONIC(MOVGT, MOVGT1, "movgt"),
  27404. + NORMAL_MNEMONIC(MOVLE, MOVLE1, "movle"),
  27405. + NORMAL_MNEMONIC(MOVHI, MOVHI1, "movhi"),
  27406. + NORMAL_MNEMONIC(MOVVS, MOVVS1, "movvs"),
  27407. + NORMAL_MNEMONIC(MOVVC, MOVVC1, "movvc"),
  27408. + NORMAL_MNEMONIC(MOVQS, MOVQS1, "movqs"),
  27409. + NORMAL_MNEMONIC(MOVAL, MOVAL1, "moval"),
  27410. + NORMAL_MNEMONIC(MOVHS, MOVHS1, "movhs"),
  27411. + NORMAL_MNEMONIC(MOVLO, MOVLO1, "movlo"),
  27412. + NORMAL_MNEMONIC(MTDR, MTDR, "mtdr"),
  27413. + NORMAL_MNEMONIC(MTSR, MTSR, "mtsr"),
  27414. + NORMAL_MNEMONIC(MUL, MUL1, "mul"),
  27415. + NORMAL_MNEMONIC(MULHH_W, MULHH_W, "mulhh.w"),
  27416. + NORMAL_MNEMONIC(MULNHH_W, MULNHH_W, "mulnhh.w"),
  27417. + NORMAL_MNEMONIC(MULNWH_D, MULNWH_D, "mulnwh.d"),
  27418. + NORMAL_MNEMONIC(MULS_D, MULSD, "muls.d"),
  27419. + NORMAL_MNEMONIC(MULSATHH_H, MULSATHH_H, "mulsathh.h"),
  27420. + NORMAL_MNEMONIC(MULSATHH_W, MULSATHH_W, "mulsathh.w"),
  27421. + NORMAL_MNEMONIC(MULSATRNDHH_H, MULSATRNDHH_H, "mulsatrndhh.h"),
  27422. + NORMAL_MNEMONIC(MULSATRNDWH_W, MULSATRNDWH_W, "mulsatrndwh.w"),
  27423. + NORMAL_MNEMONIC(MULSATWH_W, MULSATWH_W, "mulsatwh.w"),
  27424. + NORMAL_MNEMONIC(MULU_D, MULU_D, "mulu.d"),
  27425. + NORMAL_MNEMONIC(MULWH_D, MULWH_D, "mulwh.d"),
  27426. + NORMAL_MNEMONIC(MUSFR, MUSFR, "musfr"),
  27427. + NORMAL_MNEMONIC(MUSTR, MUSTR, "mustr"),
  27428. + NORMAL_MNEMONIC(MVCR_D, MVCR_D, "mvcr.d"),
  27429. + NORMAL_MNEMONIC(MVCR_W, MVCR_W, "mvcr.w"),
  27430. + NORMAL_MNEMONIC(MVRC_D, MVRC_D, "mvrc.d"),
  27431. + NORMAL_MNEMONIC(MVRC_W, MVRC_W, "mvrc.w"),
  27432. + NORMAL_MNEMONIC(NEG, NEG, "neg"),
  27433. + NORMAL_MNEMONIC(NOP, NOP, "nop"),
  27434. + NORMAL_MNEMONIC(OR, OR1, "or"),
  27435. + NORMAL_MNEMONIC(ORH, ORH, "orh"),
  27436. + NORMAL_MNEMONIC(ORL, ORL, "orl"),
  27437. + NORMAL_MNEMONIC(PABS_SB, PABS_SB, "pabs.sb"),
  27438. + NORMAL_MNEMONIC(PABS_SH, PABS_SH, "pabs.sh"),
  27439. + NORMAL_MNEMONIC(PACKSH_SB, PACKSH_SB, "packsh.sb"),
  27440. + NORMAL_MNEMONIC(PACKSH_UB, PACKSH_UB, "packsh.ub"),
  27441. + NORMAL_MNEMONIC(PACKW_SH, PACKW_SH, "packw.sh"),
  27442. + NORMAL_MNEMONIC(PADD_B, PADD_B, "padd.b"),
  27443. + NORMAL_MNEMONIC(PADD_H, PADD_H, "padd.h"),
  27444. + NORMAL_MNEMONIC(PADDH_SH, PADDH_SH, "paddh.sh"),
  27445. + NORMAL_MNEMONIC(PADDH_UB, PADDH_UB, "paddh.ub"),
  27446. + NORMAL_MNEMONIC(PADDS_SB, PADDS_SB, "padds.sb"),
  27447. + NORMAL_MNEMONIC(PADDS_SH, PADDS_SH, "padds.sh"),
  27448. + NORMAL_MNEMONIC(PADDS_UB, PADDS_UB, "padds.ub"),
  27449. + NORMAL_MNEMONIC(PADDS_UH, PADDS_UH, "padds.uh"),
  27450. + NORMAL_MNEMONIC(PADDSUB_H, PADDSUB_H, "paddsub.h"),
  27451. + NORMAL_MNEMONIC(PADDSUBH_SH, PADDSUBH_SH, "paddsubh.sh"),
  27452. + NORMAL_MNEMONIC(PADDSUBS_SH, PADDSUBS_SH, "paddsubs.sh"),
  27453. + NORMAL_MNEMONIC(PADDSUBS_UH, PADDSUBS_UH, "paddsubs.uh"),
  27454. + NORMAL_MNEMONIC(PADDX_H, PADDX_H, "paddx.h"),
  27455. + NORMAL_MNEMONIC(PADDXH_SH, PADDXH_SH, "paddxh.sh"),
  27456. + NORMAL_MNEMONIC(PADDXS_SH, PADDXS_SH, "paddxs.sh"),
  27457. + NORMAL_MNEMONIC(PADDXS_UH, PADDXS_UH, "paddxs.uh"),
  27458. + NORMAL_MNEMONIC(PASR_B, PASR_B, "pasr.b"),
  27459. + NORMAL_MNEMONIC(PASR_H, PASR_H, "pasr.h"),
  27460. + NORMAL_MNEMONIC(PAVG_SH, PAVG_SH, "pavg.sh"),
  27461. + NORMAL_MNEMONIC(PAVG_UB, PAVG_UB, "pavg.ub"),
  27462. + NORMAL_MNEMONIC(PLSL_B, PLSL_B, "plsl.b"),
  27463. + NORMAL_MNEMONIC(PLSL_H, PLSL_H, "plsl.h"),
  27464. + NORMAL_MNEMONIC(PLSR_B, PLSR_B, "plsr.b"),
  27465. + NORMAL_MNEMONIC(PLSR_H, PLSR_H, "plsr.h"),
  27466. + NORMAL_MNEMONIC(PMAX_SH, PMAX_SH, "pmax.sh"),
  27467. + NORMAL_MNEMONIC(PMAX_UB, PMAX_UB, "pmax.ub"),
  27468. + NORMAL_MNEMONIC(PMIN_SH, PMIN_SH, "pmin.sh"),
  27469. + NORMAL_MNEMONIC(PMIN_UB, PMIN_UB, "pmin.ub"),
  27470. + NORMAL_MNEMONIC(POPJC, POPJC, "popjc"),
  27471. + NORMAL_MNEMONIC(POPM, POPM, "popm"),
  27472. + NORMAL_MNEMONIC(PREF, PREF, "pref"),
  27473. + NORMAL_MNEMONIC(PSAD, PSAD, "psad"),
  27474. + NORMAL_MNEMONIC(PSUB_B, PSUB_B, "psub.b"),
  27475. + NORMAL_MNEMONIC(PSUB_H, PSUB_H, "psub.h"),
  27476. + NORMAL_MNEMONIC(PSUBADD_H, PSUBADD_H, "psubadd.h"),
  27477. + NORMAL_MNEMONIC(PSUBADDH_SH, PSUBADDH_SH, "psubaddh.sh"),
  27478. + NORMAL_MNEMONIC(PSUBADDS_SH, PSUBADDS_SH, "psubadds.sh"),
  27479. + NORMAL_MNEMONIC(PSUBADDS_UH, PSUBADDS_UH, "psubadds.uh"),
  27480. + NORMAL_MNEMONIC(PSUBH_SH, PSUBH_SH, "psubh.sh"),
  27481. + NORMAL_MNEMONIC(PSUBH_UB, PSUBH_UB, "psubh.ub"),
  27482. + NORMAL_MNEMONIC(PSUBS_SB, PSUBS_SB, "psubs.sb"),
  27483. + NORMAL_MNEMONIC(PSUBS_SH, PSUBS_SH, "psubs.sh"),
  27484. + NORMAL_MNEMONIC(PSUBS_UB, PSUBS_UB, "psubs.ub"),
  27485. + NORMAL_MNEMONIC(PSUBS_UH, PSUBS_UH, "psubs.uh"),
  27486. + NORMAL_MNEMONIC(PSUBX_H, PSUBX_H, "psubx.h"),
  27487. + NORMAL_MNEMONIC(PSUBXH_SH, PSUBXH_SH, "psubxh.sh"),
  27488. + NORMAL_MNEMONIC(PSUBXS_SH, PSUBXS_SH, "psubxs.sh"),
  27489. + NORMAL_MNEMONIC(PSUBXS_UH, PSUBXS_UH, "psubxs.uh"),
  27490. + NORMAL_MNEMONIC(PUNPCKSB_H, PUNPCKSB_H, "punpcksb.h"),
  27491. + NORMAL_MNEMONIC(PUNPCKUB_H, PUNPCKUB_H, "punpckub.h"),
  27492. + NORMAL_MNEMONIC(PUSHJC, PUSHJC, "pushjc"),
  27493. + NORMAL_MNEMONIC(PUSHM, PUSHM, "pushm"),
  27494. + NORMAL_MNEMONIC(RCALL, RCALL1, "rcall"),
  27495. + NORMAL_MNEMONIC(RETEQ, RETEQ, "reteq"),
  27496. + NORMAL_MNEMONIC(RETNE, RETNE, "retne"),
  27497. + NORMAL_MNEMONIC(RETCC, RETCC, "retcc"),
  27498. + NORMAL_MNEMONIC(RETCS, RETCS, "retcs"),
  27499. + NORMAL_MNEMONIC(RETGE, RETGE, "retge"),
  27500. + NORMAL_MNEMONIC(RETLT, RETLT, "retlt"),
  27501. + NORMAL_MNEMONIC(RETMI, RETMI, "retmi"),
  27502. + NORMAL_MNEMONIC(RETPL, RETPL, "retpl"),
  27503. + NORMAL_MNEMONIC(RETLS, RETLS, "retls"),
  27504. + NORMAL_MNEMONIC(RETGT, RETGT, "retgt"),
  27505. + NORMAL_MNEMONIC(RETLE, RETLE, "retle"),
  27506. + NORMAL_MNEMONIC(RETHI, RETHI, "rethi"),
  27507. + NORMAL_MNEMONIC(RETVS, RETVS, "retvs"),
  27508. + NORMAL_MNEMONIC(RETVC, RETVC, "retvc"),
  27509. + NORMAL_MNEMONIC(RETQS, RETQS, "retqs"),
  27510. + NORMAL_MNEMONIC(RETAL, RETAL, "retal"),
  27511. + NORMAL_MNEMONIC(RETHS, RETHS, "reths"),
  27512. + NORMAL_MNEMONIC(RETLO, RETLO, "retlo"),
  27513. + NORMAL_MNEMONIC(RET, RETAL, "ret"),
  27514. + NORMAL_MNEMONIC(RETD, RETD, "retd"),
  27515. + NORMAL_MNEMONIC(RETE, RETE, "rete"),
  27516. + NORMAL_MNEMONIC(RETJ, RETJ, "retj"),
  27517. + NORMAL_MNEMONIC(RETS, RETS, "rets"),
  27518. + NORMAL_MNEMONIC(RJMP, RJMP, "rjmp"),
  27519. + NORMAL_MNEMONIC(ROL, ROL, "rol"),
  27520. + NORMAL_MNEMONIC(ROR, ROR, "ror"),
  27521. + NORMAL_MNEMONIC(RSUB, RSUB1, "rsub"),
  27522. + NORMAL_MNEMONIC(SATADD_H, SATADD_H, "satadd.h"),
  27523. + NORMAL_MNEMONIC(SATADD_W, SATADD_W, "satadd.w"),
  27524. + NORMAL_MNEMONIC(SATRNDS, SATRNDS, "satrnds"),
  27525. + NORMAL_MNEMONIC(SATRNDU, SATRNDU, "satrndu"),
  27526. + NORMAL_MNEMONIC(SATS, SATS, "sats"),
  27527. + NORMAL_MNEMONIC(SATSUB_H, SATSUB_H, "satsub.h"),
  27528. + NORMAL_MNEMONIC(SATSUB_W, SATSUB_W1, "satsub.w"),
  27529. + NORMAL_MNEMONIC(SATU, SATU, "satu"),
  27530. + NORMAL_MNEMONIC(SBC, SBC, "sbc"),
  27531. + NORMAL_MNEMONIC(SBR, SBR, "sbr"),
  27532. + NORMAL_MNEMONIC(SCALL, SCALL, "scall"),
  27533. + NORMAL_MNEMONIC(SCR, SCR, "scr"),
  27534. + NORMAL_MNEMONIC(SLEEP, SLEEP, "sleep"),
  27535. + NORMAL_MNEMONIC(SREQ, SREQ, "sreq"),
  27536. + NORMAL_MNEMONIC(SRNE, SRNE, "srne"),
  27537. + NORMAL_MNEMONIC(SRCC, SRCC, "srcc"),
  27538. + NORMAL_MNEMONIC(SRCS, SRCS, "srcs"),
  27539. + NORMAL_MNEMONIC(SRGE, SRGE, "srge"),
  27540. + NORMAL_MNEMONIC(SRLT, SRLT, "srlt"),
  27541. + NORMAL_MNEMONIC(SRMI, SRMI, "srmi"),
  27542. + NORMAL_MNEMONIC(SRPL, SRPL, "srpl"),
  27543. + NORMAL_MNEMONIC(SRLS, SRLS, "srls"),
  27544. + NORMAL_MNEMONIC(SRGT, SRGT, "srgt"),
  27545. + NORMAL_MNEMONIC(SRLE, SRLE, "srle"),
  27546. + NORMAL_MNEMONIC(SRHI, SRHI, "srhi"),
  27547. + NORMAL_MNEMONIC(SRVS, SRVS, "srvs"),
  27548. + NORMAL_MNEMONIC(SRVC, SRVC, "srvc"),
  27549. + NORMAL_MNEMONIC(SRQS, SRQS, "srqs"),
  27550. + NORMAL_MNEMONIC(SRAL, SRAL, "sral"),
  27551. + NORMAL_MNEMONIC(SRHS, SRHS, "srhs"),
  27552. + NORMAL_MNEMONIC(SRLO, SRLO, "srlo"),
  27553. + NORMAL_MNEMONIC(SSRF, SSRF, "ssrf"),
  27554. + NORMAL_MNEMONIC(ST_B, ST_B1, "st.b"),
  27555. + NORMAL_MNEMONIC(ST_D, ST_D1, "st.d"),
  27556. + NORMAL_MNEMONIC(ST_H, ST_H1, "st.h"),
  27557. + NORMAL_MNEMONIC(ST_W, ST_W1, "st.w"),
  27558. + NORMAL_MNEMONIC(STC_D, STC_D3, "stc.d"),
  27559. + NORMAL_MNEMONIC(STC_W, STC_W3, "stc.w"),
  27560. + NORMAL_MNEMONIC(STC0_D, STC0_D, "stc0.d"),
  27561. + NORMAL_MNEMONIC(STC0_W, STC0_W, "stc0.w"),
  27562. + NORMAL_MNEMONIC(STCM_D, STCM_D, "stcm.d"),
  27563. + NORMAL_MNEMONIC(STCM_W, STCM_W, "stcm.w"),
  27564. + NORMAL_MNEMONIC(STCOND, STCOND, "stcond"),
  27565. + NORMAL_MNEMONIC(STDSP, STDSP, "stdsp"),
  27566. + NORMAL_MNEMONIC(STHH_W, STHH_W2, "sthh.w"),
  27567. + NORMAL_MNEMONIC(STM, STM, "stm"),
  27568. + NORMAL_MNEMONIC(STMTS, STMTS, "stmts"),
  27569. + NORMAL_MNEMONIC(STSWP_H, STSWP_H, "stswp.h"),
  27570. + NORMAL_MNEMONIC(STSWP_W, STSWP_W, "stswp.w"),
  27571. + NORMAL_MNEMONIC(SUB, SUB1, "sub"),
  27572. + NORMAL_MNEMONIC(SUBEQ, SUBEQ, "subeq"),
  27573. + NORMAL_MNEMONIC(SUBNE, SUBNE, "subne"),
  27574. + NORMAL_MNEMONIC(SUBCC, SUBCC, "subcc"),
  27575. + NORMAL_MNEMONIC(SUBCS, SUBCS, "subcs"),
  27576. + NORMAL_MNEMONIC(SUBGE, SUBGE, "subge"),
  27577. + NORMAL_MNEMONIC(SUBLT, SUBLT, "sublt"),
  27578. + NORMAL_MNEMONIC(SUBMI, SUBMI, "submi"),
  27579. + NORMAL_MNEMONIC(SUBPL, SUBPL, "subpl"),
  27580. + NORMAL_MNEMONIC(SUBLS, SUBLS, "subls"),
  27581. + NORMAL_MNEMONIC(SUBGT, SUBGT, "subgt"),
  27582. + NORMAL_MNEMONIC(SUBLE, SUBLE, "suble"),
  27583. + NORMAL_MNEMONIC(SUBHI, SUBHI, "subhi"),
  27584. + NORMAL_MNEMONIC(SUBVS, SUBVS, "subvs"),
  27585. + NORMAL_MNEMONIC(SUBVC, SUBVC, "subvc"),
  27586. + NORMAL_MNEMONIC(SUBQS, SUBQS, "subqs"),
  27587. + NORMAL_MNEMONIC(SUBAL, SUBAL, "subal"),
  27588. + NORMAL_MNEMONIC(SUBHS, SUBHS, "subhs"),
  27589. + NORMAL_MNEMONIC(SUBLO, SUBLO, "sublo"),
  27590. + NORMAL_MNEMONIC(SUBFEQ, SUBFEQ, "subfeq"),
  27591. + NORMAL_MNEMONIC(SUBFNE, SUBFNE, "subfne"),
  27592. + NORMAL_MNEMONIC(SUBFCC, SUBFCC, "subfcc"),
  27593. + NORMAL_MNEMONIC(SUBFCS, SUBFCS, "subfcs"),
  27594. + NORMAL_MNEMONIC(SUBFGE, SUBFGE, "subfge"),
  27595. + NORMAL_MNEMONIC(SUBFLT, SUBFLT, "subflt"),
  27596. + NORMAL_MNEMONIC(SUBFMI, SUBFMI, "subfmi"),
  27597. + NORMAL_MNEMONIC(SUBFPL, SUBFPL, "subfpl"),
  27598. + NORMAL_MNEMONIC(SUBFLS, SUBFLS, "subfls"),
  27599. + NORMAL_MNEMONIC(SUBFGT, SUBFGT, "subfgt"),
  27600. + NORMAL_MNEMONIC(SUBFLE, SUBFLE, "subfle"),
  27601. + NORMAL_MNEMONIC(SUBFHI, SUBFHI, "subfhi"),
  27602. + NORMAL_MNEMONIC(SUBFVS, SUBFVS, "subfvs"),
  27603. + NORMAL_MNEMONIC(SUBFVC, SUBFVC, "subfvc"),
  27604. + NORMAL_MNEMONIC(SUBFQS, SUBFQS, "subfqs"),
  27605. + NORMAL_MNEMONIC(SUBFAL, SUBFAL, "subfal"),
  27606. + NORMAL_MNEMONIC(SUBFHS, SUBFHS, "subfhs"),
  27607. + NORMAL_MNEMONIC(SUBFLO, SUBFLO, "subflo"),
  27608. + NORMAL_MNEMONIC(SUBHH_W, SUBHH_W, "subhh.w"),
  27609. + NORMAL_MNEMONIC(SWAP_B, SWAP_B, "swap.b"),
  27610. + NORMAL_MNEMONIC(SWAP_BH, SWAP_BH, "swap.bh"),
  27611. + NORMAL_MNEMONIC(SWAP_H, SWAP_H, "swap.h"),
  27612. + NORMAL_MNEMONIC(SYNC, SYNC, "sync"),
  27613. + NORMAL_MNEMONIC(TLBR, TLBR, "tlbr"),
  27614. + NORMAL_MNEMONIC(TLBS, TLBS, "tlbs"),
  27615. + NORMAL_MNEMONIC(TLBW, TLBW, "tlbw"),
  27616. + NORMAL_MNEMONIC(TNBZ, TNBZ, "tnbz"),
  27617. + NORMAL_MNEMONIC(TST, TST, "tst"),
  27618. + NORMAL_MNEMONIC(XCHG, XCHG, "xchg"),
  27619. + NORMAL_MNEMONIC(MEMC, MEMC, "memc"),
  27620. + NORMAL_MNEMONIC(MEMS, MEMS, "mems"),
  27621. + NORMAL_MNEMONIC(MEMT, MEMT, "memt"),
  27622. + NORMAL_MNEMONIC (FMAC_S, FMAC_S, "fmac.s"),
  27623. + NORMAL_MNEMONIC (FNMAC_S, FNMAC_S, "fnmac.s"),
  27624. + NORMAL_MNEMONIC (FMSC_S, FMSC_S, "fmsc.s"),
  27625. + NORMAL_MNEMONIC (FNMSC_S, FNMSC_S, "fnmsc.s"),
  27626. + NORMAL_MNEMONIC (FMUL_S, FMUL_S, "fmul.s"),
  27627. + NORMAL_MNEMONIC (FNMUL_S, FNMUL_S, "fnmul.s"),
  27628. + NORMAL_MNEMONIC (FADD_S, FADD_S, "fadd.s"),
  27629. + NORMAL_MNEMONIC (FSUB_S, FSUB_S, "fsub.s"),
  27630. + NORMAL_MNEMONIC (FCASTRS_SW, FCASTRS_SW, "fcastrs.sw"),
  27631. + NORMAL_MNEMONIC (FCASTRS_UW, FCASTRS_UW, "fcastrs.uw"),
  27632. + NORMAL_MNEMONIC (FCASTSW_S, FCASTSW_S, "fcastsw.s"),
  27633. + NORMAL_MNEMONIC (FCASTUW_S, FCASTUW_S, "fcastuw.s"),
  27634. + NORMAL_MNEMONIC (FCMP_S, FCMP_S, "fcmp.s"),
  27635. + NORMAL_MNEMONIC (FCHK_S, FCHK_S, "fchk.s"),
  27636. + NORMAL_MNEMONIC (FRCPA_S, FRCPA_S, "frcpa.s"),
  27637. + NORMAL_MNEMONIC (FRSQRTA_S, FRSQRTA_S, "frsqrta.s"),
  27638. + NORMAL_MNEMONIC(LDA_W, LDA_W, "lda.w"),
  27639. + NORMAL_MNEMONIC(CALL, CALL, "call"),
  27640. + NORMAL_MNEMONIC(PICOSVMAC, PICOSVMAC0, "picosvmac"),
  27641. + NORMAL_MNEMONIC(PICOSVMUL, PICOSVMUL0, "picosvmul"),
  27642. + NORMAL_MNEMONIC(PICOVMAC, PICOVMAC0, "picovmac"),
  27643. + NORMAL_MNEMONIC(PICOVMUL, PICOVMUL0, "picovmul"),
  27644. + NORMAL_MNEMONIC(PICOLD_D, PICOLD_D2, "picold.d"),
  27645. + NORMAL_MNEMONIC(PICOLD_W, PICOLD_W2, "picold.w"),
  27646. + NORMAL_MNEMONIC(PICOLDM_D, PICOLDM_D, "picoldm.d"),
  27647. + NORMAL_MNEMONIC(PICOLDM_W, PICOLDM_W, "picoldm.w"),
  27648. + NORMAL_MNEMONIC(PICOMV_D, PICOMV_D1, "picomv.d"),
  27649. + NORMAL_MNEMONIC(PICOMV_W, PICOMV_W1, "picomv.w"),
  27650. + NORMAL_MNEMONIC(PICOST_D, PICOST_D2, "picost.d"),
  27651. + NORMAL_MNEMONIC(PICOST_W, PICOST_W2, "picost.w"),
  27652. + NORMAL_MNEMONIC(PICOSTM_D, PICOSTM_D, "picostm.d"),
  27653. + NORMAL_MNEMONIC(PICOSTM_W, PICOSTM_W, "picostm.w"),
  27654. + NORMAL_MNEMONIC(RSUBEQ, RSUBEQ, "rsubeq"),
  27655. + NORMAL_MNEMONIC(RSUBNE, RSUBNE, "rsubne"),
  27656. + NORMAL_MNEMONIC(RSUBCC, RSUBCC, "rsubcc"),
  27657. + NORMAL_MNEMONIC(RSUBCS, RSUBCS, "rsubcs"),
  27658. + NORMAL_MNEMONIC(RSUBGE, RSUBGE, "rsubge"),
  27659. + NORMAL_MNEMONIC(RSUBLT, RSUBLT, "rsublt"),
  27660. + NORMAL_MNEMONIC(RSUBMI, RSUBMI, "rsubmi"),
  27661. + NORMAL_MNEMONIC(RSUBPL, RSUBPL, "rsubpl"),
  27662. + NORMAL_MNEMONIC(RSUBLS, RSUBLS, "rsubls"),
  27663. + NORMAL_MNEMONIC(RSUBGT, RSUBGT, "rsubgt"),
  27664. + NORMAL_MNEMONIC(RSUBLE, RSUBLE, "rsuble"),
  27665. + NORMAL_MNEMONIC(RSUBHI, RSUBHI, "rsubhi"),
  27666. + NORMAL_MNEMONIC(RSUBVS, RSUBVS, "rsubvs"),
  27667. + NORMAL_MNEMONIC(RSUBVC, RSUBVC, "rsubvc"),
  27668. + NORMAL_MNEMONIC(RSUBQS, RSUBQS, "rsubqs"),
  27669. + NORMAL_MNEMONIC(RSUBAL, RSUBAL, "rsubal"),
  27670. + NORMAL_MNEMONIC(RSUBHS, RSUBHS, "rsubhs"),
  27671. + NORMAL_MNEMONIC(RSUBLO, RSUBLO, "rsublo"),
  27672. + NORMAL_MNEMONIC(ADDEQ, ADDEQ, "addeq"),
  27673. + NORMAL_MNEMONIC(ADDNE, ADDNE, "addne"),
  27674. + NORMAL_MNEMONIC(ADDCC, ADDCC, "addcc"),
  27675. + NORMAL_MNEMONIC(ADDCS, ADDCS, "addcs"),
  27676. + NORMAL_MNEMONIC(ADDGE, ADDGE, "addge"),
  27677. + NORMAL_MNEMONIC(ADDLT, ADDLT, "addlt"),
  27678. + NORMAL_MNEMONIC(ADDMI, ADDMI, "addmi"),
  27679. + NORMAL_MNEMONIC(ADDPL, ADDPL, "addpl"),
  27680. + NORMAL_MNEMONIC(ADDLS, ADDLS, "addls"),
  27681. + NORMAL_MNEMONIC(ADDGT, ADDGT, "addgt"),
  27682. + NORMAL_MNEMONIC(ADDLE, ADDLE, "addle"),
  27683. + NORMAL_MNEMONIC(ADDHI, ADDHI, "addhi"),
  27684. + NORMAL_MNEMONIC(ADDVS, ADDVS, "addvs"),
  27685. + NORMAL_MNEMONIC(ADDVC, ADDVC, "addvc"),
  27686. + NORMAL_MNEMONIC(ADDQS, ADDQS, "addqs"),
  27687. + NORMAL_MNEMONIC(ADDAL, ADDAL, "addal"),
  27688. + NORMAL_MNEMONIC(ADDHS, ADDHS, "addhs"),
  27689. + NORMAL_MNEMONIC(ADDLO, ADDLO, "addlo"),
  27690. + NORMAL_MNEMONIC(ANDEQ, ANDEQ, "andeq"),
  27691. + NORMAL_MNEMONIC(ANDNE, ANDNE, "andne"),
  27692. + NORMAL_MNEMONIC(ANDCC, ANDCC, "andcc"),
  27693. + NORMAL_MNEMONIC(ANDCS, ANDCS, "andcs"),
  27694. + NORMAL_MNEMONIC(ANDGE, ANDGE, "andge"),
  27695. + NORMAL_MNEMONIC(ANDLT, ANDLT, "andlt"),
  27696. + NORMAL_MNEMONIC(ANDMI, ANDMI, "andmi"),
  27697. + NORMAL_MNEMONIC(ANDPL, ANDPL, "andpl"),
  27698. + NORMAL_MNEMONIC(ANDLS, ANDLS, "andls"),
  27699. + NORMAL_MNEMONIC(ANDGT, ANDGT, "andgt"),
  27700. + NORMAL_MNEMONIC(ANDLE, ANDLE, "andle"),
  27701. + NORMAL_MNEMONIC(ANDHI, ANDHI, "andhi"),
  27702. + NORMAL_MNEMONIC(ANDVS, ANDVS, "andvs"),
  27703. + NORMAL_MNEMONIC(ANDVC, ANDVC, "andvc"),
  27704. + NORMAL_MNEMONIC(ANDQS, ANDQS, "andqs"),
  27705. + NORMAL_MNEMONIC(ANDAL, ANDAL, "andal"),
  27706. + NORMAL_MNEMONIC(ANDHS, ANDHS, "andhs"),
  27707. + NORMAL_MNEMONIC(ANDLO, ANDLO, "andlo"),
  27708. + NORMAL_MNEMONIC(OREQ, OREQ, "oreq"),
  27709. + NORMAL_MNEMONIC(ORNE, ORNE, "orne"),
  27710. + NORMAL_MNEMONIC(ORCC, ORCC, "orcc"),
  27711. + NORMAL_MNEMONIC(ORCS, ORCS, "orcs"),
  27712. + NORMAL_MNEMONIC(ORGE, ORGE, "orge"),
  27713. + NORMAL_MNEMONIC(ORLT, ORLT, "orlt"),
  27714. + NORMAL_MNEMONIC(ORMI, ORMI, "ormi"),
  27715. + NORMAL_MNEMONIC(ORPL, ORPL, "orpl"),
  27716. + NORMAL_MNEMONIC(ORLS, ORLS, "orls"),
  27717. + NORMAL_MNEMONIC(ORGT, ORGT, "orgt"),
  27718. + NORMAL_MNEMONIC(ORLE, ORLE, "orle"),
  27719. + NORMAL_MNEMONIC(ORHI, ORHI, "orhi"),
  27720. + NORMAL_MNEMONIC(ORVS, ORVS, "orvs"),
  27721. + NORMAL_MNEMONIC(ORVC, ORVC, "orvc"),
  27722. + NORMAL_MNEMONIC(ORQS, ORQS, "orqs"),
  27723. + NORMAL_MNEMONIC(ORAL, ORAL, "oral"),
  27724. + NORMAL_MNEMONIC(ORHS, ORHS, "orhs"),
  27725. + NORMAL_MNEMONIC(ORLO, ORLO, "orlo"),
  27726. + NORMAL_MNEMONIC(EOREQ, EOREQ, "eoreq"),
  27727. + NORMAL_MNEMONIC(EORNE, EORNE, "eorne"),
  27728. + NORMAL_MNEMONIC(EORCC, EORCC, "eorcc"),
  27729. + NORMAL_MNEMONIC(EORCS, EORCS, "eorcs"),
  27730. + NORMAL_MNEMONIC(EORGE, EORGE, "eorge"),
  27731. + NORMAL_MNEMONIC(EORLT, EORLT, "eorlt"),
  27732. + NORMAL_MNEMONIC(EORMI, EORMI, "eormi"),
  27733. + NORMAL_MNEMONIC(EORPL, EORPL, "eorpl"),
  27734. + NORMAL_MNEMONIC(EORLS, EORLS, "eorls"),
  27735. + NORMAL_MNEMONIC(EORGT, EORGT, "eorgt"),
  27736. + NORMAL_MNEMONIC(EORLE, EORLE, "eorle"),
  27737. + NORMAL_MNEMONIC(EORHI, EORHI, "eorhi"),
  27738. + NORMAL_MNEMONIC(EORVS, EORVS, "eorvs"),
  27739. + NORMAL_MNEMONIC(EORVC, EORVC, "eorvc"),
  27740. + NORMAL_MNEMONIC(EORQS, EORQS, "eorqs"),
  27741. + NORMAL_MNEMONIC(EORAL, EORAL, "eoral"),
  27742. + NORMAL_MNEMONIC(EORHS, EORHS, "eorhs"),
  27743. + NORMAL_MNEMONIC(EORLO, EORLO, "eorlo"),
  27744. + NORMAL_MNEMONIC(LD_WEQ, LD_WEQ, "ld.weq"),
  27745. + NORMAL_MNEMONIC(LD_WNE, LD_WNE, "ld.wne"),
  27746. + NORMAL_MNEMONIC(LD_WCC, LD_WCC, "ld.wcc"),
  27747. + NORMAL_MNEMONIC(LD_WCS, LD_WCS, "ld.wcs"),
  27748. + NORMAL_MNEMONIC(LD_WGE, LD_WGE, "ld.wge"),
  27749. + NORMAL_MNEMONIC(LD_WLT, LD_WLT, "ld.wlt"),
  27750. + NORMAL_MNEMONIC(LD_WMI, LD_WMI, "ld.wmi"),
  27751. + NORMAL_MNEMONIC(LD_WPL, LD_WPL, "ld.wpl"),
  27752. + NORMAL_MNEMONIC(LD_WLS, LD_WLS, "ld.wls"),
  27753. + NORMAL_MNEMONIC(LD_WGT, LD_WGT, "ld.wgt"),
  27754. + NORMAL_MNEMONIC(LD_WLE, LD_WLE, "ld.wle"),
  27755. + NORMAL_MNEMONIC(LD_WHI, LD_WHI, "ld.whi"),
  27756. + NORMAL_MNEMONIC(LD_WVS, LD_WVS, "ld.wvs"),
  27757. + NORMAL_MNEMONIC(LD_WVC, LD_WVC, "ld.wvc"),
  27758. + NORMAL_MNEMONIC(LD_WQS, LD_WQS, "ld.wqs"),
  27759. + NORMAL_MNEMONIC(LD_WAL, LD_WAL, "ld.wal"),
  27760. + NORMAL_MNEMONIC(LD_WHS, LD_WHS, "ld.whs"),
  27761. + NORMAL_MNEMONIC(LD_WLO, LD_WLO, "ld.wlo"),
  27762. + NORMAL_MNEMONIC(LD_SHEQ, LD_SHEQ, "ld.sheq"),
  27763. + NORMAL_MNEMONIC(LD_SHNE, LD_SHNE, "ld.shne"),
  27764. + NORMAL_MNEMONIC(LD_SHCC, LD_SHCC, "ld.shcc"),
  27765. + NORMAL_MNEMONIC(LD_SHCS, LD_SHCS, "ld.shcs"),
  27766. + NORMAL_MNEMONIC(LD_SHGE, LD_SHGE, "ld.shge"),
  27767. + NORMAL_MNEMONIC(LD_SHLT, LD_SHLT, "ld.shlt"),
  27768. + NORMAL_MNEMONIC(LD_SHMI, LD_SHMI, "ld.shmi"),
  27769. + NORMAL_MNEMONIC(LD_SHPL, LD_SHPL, "ld.shpl"),
  27770. + NORMAL_MNEMONIC(LD_SHLS, LD_SHLS, "ld.shls"),
  27771. + NORMAL_MNEMONIC(LD_SHGT, LD_SHGT, "ld.shgt"),
  27772. + NORMAL_MNEMONIC(LD_SHLE, LD_SHLE, "ld.shle"),
  27773. + NORMAL_MNEMONIC(LD_SHHI, LD_SHHI, "ld.shhi"),
  27774. + NORMAL_MNEMONIC(LD_SHVS, LD_SHVS, "ld.shvs"),
  27775. + NORMAL_MNEMONIC(LD_SHVC, LD_SHVC, "ld.shvc"),
  27776. + NORMAL_MNEMONIC(LD_SHQS, LD_SHQS, "ld.shqs"),
  27777. + NORMAL_MNEMONIC(LD_SHAL, LD_SHAL, "ld.shal"),
  27778. + NORMAL_MNEMONIC(LD_SHHS, LD_SHHS, "ld.shhs"),
  27779. + NORMAL_MNEMONIC(LD_SHLO, LD_SHLO, "ld.shlo"),
  27780. + NORMAL_MNEMONIC(LD_UHEQ, LD_UHEQ, "ld.uheq"),
  27781. + NORMAL_MNEMONIC(LD_UHNE, LD_UHNE, "ld.uhne"),
  27782. + NORMAL_MNEMONIC(LD_UHCC, LD_UHCC, "ld.uhcc"),
  27783. + NORMAL_MNEMONIC(LD_UHCS, LD_UHCS, "ld.uhcs"),
  27784. + NORMAL_MNEMONIC(LD_UHGE, LD_UHGE, "ld.uhge"),
  27785. + NORMAL_MNEMONIC(LD_UHLT, LD_UHLT, "ld.uhlt"),
  27786. + NORMAL_MNEMONIC(LD_UHMI, LD_UHMI, "ld.uhmi"),
  27787. + NORMAL_MNEMONIC(LD_UHPL, LD_UHPL, "ld.uhpl"),
  27788. + NORMAL_MNEMONIC(LD_UHLS, LD_UHLS, "ld.uhls"),
  27789. + NORMAL_MNEMONIC(LD_UHGT, LD_UHGT, "ld.uhgt"),
  27790. + NORMAL_MNEMONIC(LD_UHLE, LD_UHLE, "ld.uhle"),
  27791. + NORMAL_MNEMONIC(LD_UHHI, LD_UHHI, "ld.uhhi"),
  27792. + NORMAL_MNEMONIC(LD_UHVS, LD_UHVS, "ld.uhvs"),
  27793. + NORMAL_MNEMONIC(LD_UHVC, LD_UHVC, "ld.uhvc"),
  27794. + NORMAL_MNEMONIC(LD_UHQS, LD_UHQS, "ld.uhqs"),
  27795. + NORMAL_MNEMONIC(LD_UHAL, LD_UHAL, "ld.uhal"),
  27796. + NORMAL_MNEMONIC(LD_UHHS, LD_UHHS, "ld.uhhs"),
  27797. + NORMAL_MNEMONIC(LD_UHLO, LD_UHLO, "ld.uhlo"),
  27798. + NORMAL_MNEMONIC(LD_SBEQ, LD_SBEQ, "ld.sbeq"),
  27799. + NORMAL_MNEMONIC(LD_SBNE, LD_SBNE, "ld.sbne"),
  27800. + NORMAL_MNEMONIC(LD_SBCC, LD_SBCC, "ld.sbcc"),
  27801. + NORMAL_MNEMONIC(LD_SBCS, LD_SBCS, "ld.sbcs"),
  27802. + NORMAL_MNEMONIC(LD_SBGE, LD_SBGE, "ld.sbge"),
  27803. + NORMAL_MNEMONIC(LD_SBLT, LD_SBLT, "ld.sblt"),
  27804. + NORMAL_MNEMONIC(LD_SBMI, LD_SBMI, "ld.sbmi"),
  27805. + NORMAL_MNEMONIC(LD_SBPL, LD_SBPL, "ld.sbpl"),
  27806. + NORMAL_MNEMONIC(LD_SBLS, LD_SBLS, "ld.sbls"),
  27807. + NORMAL_MNEMONIC(LD_SBGT, LD_SBGT, "ld.sbgt"),
  27808. + NORMAL_MNEMONIC(LD_SBLE, LD_SBLE, "ld.sble"),
  27809. + NORMAL_MNEMONIC(LD_SBHI, LD_SBHI, "ld.sbhi"),
  27810. + NORMAL_MNEMONIC(LD_SBVS, LD_SBVS, "ld.sbvs"),
  27811. + NORMAL_MNEMONIC(LD_SBVC, LD_SBVC, "ld.sbvc"),
  27812. + NORMAL_MNEMONIC(LD_SBQS, LD_SBQS, "ld.sbqs"),
  27813. + NORMAL_MNEMONIC(LD_SBAL, LD_SBAL, "ld.sbal"),
  27814. + NORMAL_MNEMONIC(LD_SBHS, LD_SBHS, "ld.sbhs"),
  27815. + NORMAL_MNEMONIC(LD_SBLO, LD_SBLO, "ld.sblo"),
  27816. + NORMAL_MNEMONIC(LD_UBEQ, LD_UBEQ, "ld.ubeq"),
  27817. + NORMAL_MNEMONIC(LD_UBNE, LD_UBNE, "ld.ubne"),
  27818. + NORMAL_MNEMONIC(LD_UBCC, LD_UBCC, "ld.ubcc"),
  27819. + NORMAL_MNEMONIC(LD_UBCS, LD_UBCS, "ld.ubcs"),
  27820. + NORMAL_MNEMONIC(LD_UBGE, LD_UBGE, "ld.ubge"),
  27821. + NORMAL_MNEMONIC(LD_UBLT, LD_UBLT, "ld.ublt"),
  27822. + NORMAL_MNEMONIC(LD_UBMI, LD_UBMI, "ld.ubmi"),
  27823. + NORMAL_MNEMONIC(LD_UBPL, LD_UBPL, "ld.ubpl"),
  27824. + NORMAL_MNEMONIC(LD_UBLS, LD_UBLS, "ld.ubls"),
  27825. + NORMAL_MNEMONIC(LD_UBGT, LD_UBGT, "ld.ubgt"),
  27826. + NORMAL_MNEMONIC(LD_UBLE, LD_UBLE, "ld.uble"),
  27827. + NORMAL_MNEMONIC(LD_UBHI, LD_UBHI, "ld.ubhi"),
  27828. + NORMAL_MNEMONIC(LD_UBVS, LD_UBVS, "ld.ubvs"),
  27829. + NORMAL_MNEMONIC(LD_UBVC, LD_UBVC, "ld.ubvc"),
  27830. + NORMAL_MNEMONIC(LD_UBQS, LD_UBQS, "ld.ubqs"),
  27831. + NORMAL_MNEMONIC(LD_UBAL, LD_UBAL, "ld.ubal"),
  27832. + NORMAL_MNEMONIC(LD_UBHS, LD_UBHS, "ld.ubhs"),
  27833. + NORMAL_MNEMONIC(LD_UBLO, LD_UBLO, "ld.ublo"),
  27834. + NORMAL_MNEMONIC(ST_WEQ, ST_WEQ, "st.weq"),
  27835. + NORMAL_MNEMONIC(ST_WNE, ST_WNE, "st.wne"),
  27836. + NORMAL_MNEMONIC(ST_WCC, ST_WCC, "st.wcc"),
  27837. + NORMAL_MNEMONIC(ST_WCS, ST_WCS, "st.wcs"),
  27838. + NORMAL_MNEMONIC(ST_WGE, ST_WGE, "st.wge"),
  27839. + NORMAL_MNEMONIC(ST_WLT, ST_WLT, "st.wlt"),
  27840. + NORMAL_MNEMONIC(ST_WMI, ST_WMI, "st.wmi"),
  27841. + NORMAL_MNEMONIC(ST_WPL, ST_WPL, "st.wpl"),
  27842. + NORMAL_MNEMONIC(ST_WLS, ST_WLS, "st.wls"),
  27843. + NORMAL_MNEMONIC(ST_WGT, ST_WGT, "st.wgt"),
  27844. + NORMAL_MNEMONIC(ST_WLE, ST_WLE, "st.wle"),
  27845. + NORMAL_MNEMONIC(ST_WHI, ST_WHI, "st.whi"),
  27846. + NORMAL_MNEMONIC(ST_WVS, ST_WVS, "st.wvs"),
  27847. + NORMAL_MNEMONIC(ST_WVC, ST_WVC, "st.wvc"),
  27848. + NORMAL_MNEMONIC(ST_WQS, ST_WQS, "st.wqs"),
  27849. + NORMAL_MNEMONIC(ST_WAL, ST_WAL, "st.wal"),
  27850. + NORMAL_MNEMONIC(ST_WHS, ST_WHS, "st.whs"),
  27851. + NORMAL_MNEMONIC(ST_WLO, ST_WLO, "st.wlo"),
  27852. + NORMAL_MNEMONIC(ST_HEQ, ST_HEQ, "st.heq"),
  27853. + NORMAL_MNEMONIC(ST_HNE, ST_HNE, "st.hne"),
  27854. + NORMAL_MNEMONIC(ST_HCC, ST_HCC, "st.hcc"),
  27855. + NORMAL_MNEMONIC(ST_HCS, ST_HCS, "st.hcs"),
  27856. + NORMAL_MNEMONIC(ST_HGE, ST_HGE, "st.hge"),
  27857. + NORMAL_MNEMONIC(ST_HLT, ST_HLT, "st.hlt"),
  27858. + NORMAL_MNEMONIC(ST_HMI, ST_HMI, "st.hmi"),
  27859. + NORMAL_MNEMONIC(ST_HPL, ST_HPL, "st.hpl"),
  27860. + NORMAL_MNEMONIC(ST_HLS, ST_HLS, "st.hls"),
  27861. + NORMAL_MNEMONIC(ST_HGT, ST_HGT, "st.hgt"),
  27862. + NORMAL_MNEMONIC(ST_HLE, ST_HLE, "st.hle"),
  27863. + NORMAL_MNEMONIC(ST_HHI, ST_HHI, "st.hhi"),
  27864. + NORMAL_MNEMONIC(ST_HVS, ST_HVS, "st.hvs"),
  27865. + NORMAL_MNEMONIC(ST_HVC, ST_HVC, "st.hvc"),
  27866. + NORMAL_MNEMONIC(ST_HQS, ST_HQS, "st.hqs"),
  27867. + NORMAL_MNEMONIC(ST_HAL, ST_HAL, "st.hal"),
  27868. + NORMAL_MNEMONIC(ST_HHS, ST_HHS, "st.hhs"),
  27869. + NORMAL_MNEMONIC(ST_HLO, ST_HLO, "st.hlo"),
  27870. + NORMAL_MNEMONIC(ST_BEQ, ST_BEQ, "st.beq"),
  27871. + NORMAL_MNEMONIC(ST_BNE, ST_BNE, "st.bne"),
  27872. + NORMAL_MNEMONIC(ST_BCC, ST_BCC, "st.bcc"),
  27873. + NORMAL_MNEMONIC(ST_BCS, ST_BCS, "st.bcs"),
  27874. + NORMAL_MNEMONIC(ST_BGE, ST_BGE, "st.bge"),
  27875. + NORMAL_MNEMONIC(ST_BLT, ST_BLT, "st.blt"),
  27876. + NORMAL_MNEMONIC(ST_BMI, ST_BMI, "st.bmi"),
  27877. + NORMAL_MNEMONIC(ST_BPL, ST_BPL, "st.bpl"),
  27878. + NORMAL_MNEMONIC(ST_BLS, ST_BLS, "st.bls"),
  27879. + NORMAL_MNEMONIC(ST_BGT, ST_BGT, "st.bgt"),
  27880. + NORMAL_MNEMONIC(ST_BLE, ST_BLE, "st.ble"),
  27881. + NORMAL_MNEMONIC(ST_BHI, ST_BHI, "st.bhi"),
  27882. + NORMAL_MNEMONIC(ST_BVS, ST_BVS, "st.bvs"),
  27883. + NORMAL_MNEMONIC(ST_BVC, ST_BVC, "st.bvc"),
  27884. + NORMAL_MNEMONIC(ST_BQS, ST_BQS, "st.bqs"),
  27885. + NORMAL_MNEMONIC(ST_BAL, ST_BAL, "st.bal"),
  27886. + NORMAL_MNEMONIC(ST_BHS, ST_BHS, "st.bhs"),
  27887. + NORMAL_MNEMONIC(ST_BLO, ST_BLO, "st.blo"),
  27888. + NORMAL_MNEMONIC(MOVH, MOVH, "movh"),
  27889. +
  27890. + };
  27891. +#undef NORMAL_MNEMONIC
  27892. +#undef ALIAS_MNEMONIC
  27893. +#undef FP_MNEMONIC
  27894. --- /dev/null
  27895. +++ b/opcodes/avr32-opc.h
  27896. @@ -0,0 +1,2341 @@
  27897. +/* Opcode tables for AVR32.
  27898. + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
  27899. +
  27900. + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  27901. +
  27902. + This file is part of libopcodes.
  27903. +
  27904. + This program is free software; you can redistribute it and/or
  27905. + modify it under the terms of the GNU General Public License as
  27906. + published by the Free Software Foundation; either version 2 of the
  27907. + License, or (at your option) any later version.
  27908. +
  27909. + This program is distributed in the hope that it will be useful, but
  27910. + WITHOUT ANY WARRANTY; without even the implied warranty of
  27911. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  27912. + General Public License for more details.
  27913. +
  27914. + You should have received a copy of the GNU General Public License
  27915. + along with this program; if not, write to the Free Software
  27916. + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  27917. + 02111-1307, USA. */
  27918. +
  27919. +#include "bfd.h"
  27920. +
  27921. +#define AVR32_MAX_OPERANDS 8
  27922. +#define AVR32_MAX_FIELDS 8
  27923. +
  27924. +#define AVR32_V1 (1 << 1)
  27925. +#define AVR32_SIMD (1 << 2)
  27926. +#define AVR32_DSP (1 << 3)
  27927. +#define AVR32_RMW (1 << 4)
  27928. +#define AVR32_V2 (1 << 5)
  27929. +#define AVR32_V3 (1 << 6)
  27930. +#define AVR32_V3FP (1 << 7)
  27931. +#define AVR32_PICO (1 << 17)
  27932. +
  27933. +/* Registers we commonly refer to */
  27934. +#define AVR32_REG_R12 12
  27935. +#define AVR32_REG_SP 13
  27936. +#define AVR32_REG_LR 14
  27937. +#define AVR32_REG_PC 15
  27938. +
  27939. +struct avr32_ifield
  27940. +{
  27941. + int id;
  27942. + unsigned short bitsize;
  27943. + unsigned short shift;
  27944. + unsigned long mask;
  27945. +
  27946. + /* If the value doesn't fit, it will be truncated with no warning */
  27947. + void (*insert)(const struct avr32_ifield *, void *, unsigned long);
  27948. + void (*extract)(const struct avr32_ifield *, void *, unsigned long *);
  27949. +};
  27950. +
  27951. +struct avr32_opcode
  27952. +{
  27953. + int id;
  27954. + int size;
  27955. + unsigned long value;
  27956. + unsigned long mask;
  27957. + const struct avr32_syntax *syntax;
  27958. + bfd_reloc_code_real_type reloc_type;
  27959. + unsigned int nr_fields;
  27960. + /* if relaxable, which field is variable, otherwise -1 */
  27961. + int var_field;
  27962. + const struct avr32_ifield *fields[AVR32_MAX_FIELDS];
  27963. +};
  27964. +
  27965. +struct avr32_alias
  27966. +{
  27967. + int id;
  27968. + const struct avr32_opcode *opc;
  27969. + struct {
  27970. + int is_opindex;
  27971. + unsigned long value;
  27972. + } operand_map[AVR32_MAX_OPERANDS];
  27973. +};
  27974. +
  27975. +struct avr32_syntax
  27976. +{
  27977. + int id;
  27978. + unsigned long isa_flags;
  27979. + const struct avr32_mnemonic *mnemonic;
  27980. + int type;
  27981. + union {
  27982. + const struct avr32_opcode *opc;
  27983. + const struct avr32_alias *alias;
  27984. + } u;
  27985. + const struct avr32_syntax *next;
  27986. + /* negative means "vararg" */
  27987. + int nr_operands;
  27988. + int operand[AVR32_MAX_OPERANDS];
  27989. +};
  27990. +
  27991. +#if 0
  27992. +#define AVR32_ALIAS_MAKE_CONST(val) ((val) | 0x80000000UL)
  27993. +#define AVR32_ALIAS_IS_CONST(mapval) (((mapval) & 0x80000000UL) != 0)
  27994. +#define AVR32_ALIAS_GET_CONST(mapval) ((mapval) & ~0x80000000UL)
  27995. +#endif
  27996. +
  27997. +struct avr32_mnemonic
  27998. +{
  27999. + int id;
  28000. + const char *name;
  28001. + const struct avr32_syntax *syntax;
  28002. +};
  28003. +
  28004. +extern const struct avr32_ifield avr32_ifield_table[];
  28005. +extern struct avr32_opcode avr32_opc_table[];
  28006. +extern const struct avr32_syntax avr32_syntax_table[];
  28007. +extern const struct avr32_alias avr32_alias_table[];
  28008. +extern const struct avr32_mnemonic avr32_mnemonic_table[];
  28009. +
  28010. +extern void avr32_insert_simple(const struct avr32_ifield *field,
  28011. + void *buf, unsigned long value);
  28012. +extern void avr32_insert_bit5c(const struct avr32_ifield *field,
  28013. + void *buf, unsigned long value);
  28014. +extern void avr32_insert_k10(const struct avr32_ifield *field,
  28015. + void *buf, unsigned long value);
  28016. +extern void avr32_insert_k21(const struct avr32_ifield *field,
  28017. + void *buf, unsigned long value);
  28018. +extern void avr32_insert_cpop(const struct avr32_ifield *field,
  28019. + void *buf, unsigned long value);
  28020. +extern void avr32_insert_k12cp(const struct avr32_ifield *field,
  28021. + void *buf, unsigned long value);
  28022. +
  28023. +extern void avr32_extract_simple(const struct avr32_ifield *field,
  28024. + void *buf, unsigned long *value);
  28025. +extern void avr32_extract_bit5c(const struct avr32_ifield *field,
  28026. + void *buf, unsigned long *value);
  28027. +extern void avr32_extract_k10(const struct avr32_ifield *field,
  28028. + void *buf, unsigned long *value);
  28029. +extern void avr32_extract_k21(const struct avr32_ifield *field,
  28030. + void *buf, unsigned long *value);
  28031. +extern void avr32_extract_cpop(const struct avr32_ifield *field,
  28032. + void *buf, unsigned long *value);
  28033. +extern void avr32_extract_k12cp(const struct avr32_ifield *field,
  28034. + void *buf, unsigned long *value);
  28035. +
  28036. +enum avr32_operand_type
  28037. +{
  28038. + AVR32_OPERAND_INTREG, /* just a register */
  28039. + AVR32_OPERAND_INTREG_PREDEC, /* register with pre-decrement */
  28040. + AVR32_OPERAND_INTREG_POSTINC, /* register with post-increment */
  28041. + AVR32_OPERAND_INTREG_LSL, /* register with left shift */
  28042. + AVR32_OPERAND_INTREG_LSR, /* register with right shift */
  28043. + AVR32_OPERAND_INTREG_BSEL, /* register with byte selector */
  28044. + AVR32_OPERAND_INTREG_HSEL, /* register with halfword selector */
  28045. + AVR32_OPERAND_INTREG_SDISP, /* Rp[signed disp] */
  28046. + AVR32_OPERAND_INTREG_SDISP_H, /* Rp[signed hword-aligned disp] */
  28047. + AVR32_OPERAND_INTREG_SDISP_W, /* Rp[signed word-aligned disp] */
  28048. + AVR32_OPERAND_INTREG_UDISP, /* Rp[unsigned disp] */
  28049. + AVR32_OPERAND_INTREG_UDISP_H, /* Rp[unsigned hword-aligned disp] */
  28050. + AVR32_OPERAND_INTREG_UDISP_W, /* Rp[unsigned word-aligned disp] */
  28051. + AVR32_OPERAND_INTREG_INDEX, /* Rp[Ri << sa] */
  28052. + AVR32_OPERAND_INTREG_XINDEX, /* Rp[Ri:bytesel << 2] */
  28053. + AVR32_OPERAND_DWREG, /* Even-numbered register */
  28054. + AVR32_OPERAND_PC_UDISP_W, /* PC[unsigned word-aligned disp] or label */
  28055. + AVR32_OPERAND_SP, /* Just SP */
  28056. + AVR32_OPERAND_SP_UDISP_W, /* SP[unsigned word-aligned disp] */
  28057. + AVR32_OPERAND_CPNO,
  28058. + AVR32_OPERAND_CPREG,
  28059. + AVR32_OPERAND_CPREG_D,
  28060. + AVR32_OPERAND_UNSIGNED_CONST,
  28061. + AVR32_OPERAND_UNSIGNED_CONST_W,
  28062. + AVR32_OPERAND_SIGNED_CONST,
  28063. + AVR32_OPERAND_SIGNED_CONST_W,
  28064. + AVR32_OPERAND_JMPLABEL,
  28065. + AVR32_OPERAND_UNSIGNED_NUMBER,
  28066. + AVR32_OPERAND_UNSIGNED_NUMBER_W,
  28067. + AVR32_OPERAND_REGLIST8,
  28068. + AVR32_OPERAND_REGLIST9,
  28069. + AVR32_OPERAND_REGLIST16,
  28070. + AVR32_OPERAND_REGLIST_LDM,
  28071. + AVR32_OPERAND_REGLIST_CP8,
  28072. + AVR32_OPERAND_REGLIST_CPD8,
  28073. + AVR32_OPERAND_RETVAL,
  28074. + AVR32_OPERAND_MCALL,
  28075. + AVR32_OPERAND_JOSPINC,
  28076. + AVR32_OPERAND_COH,
  28077. + AVR32_OPERAND_PICO_REG_W,
  28078. + AVR32_OPERAND_PICO_REG_D,
  28079. + AVR32_OPERAND_PICO_REGLIST_W,
  28080. + AVR32_OPERAND_PICO_REGLIST_D,
  28081. + AVR32_OPERAND_PICO_IN,
  28082. + AVR32_OPERAND_PICO_OUT0,
  28083. + AVR32_OPERAND_PICO_OUT1,
  28084. + AVR32_OPERAND_PICO_OUT2,
  28085. + AVR32_OPERAND_PICO_OUT3,
  28086. + AVR32_OPERAND__END_
  28087. +};
  28088. +#define AVR32_OPERAND_UNKNOWN AVR32_OPERAND__END_
  28089. +#define AVR32_NR_OPERANDS AVR32_OPERAND__END_
  28090. +
  28091. +enum avr32_ifield_type
  28092. +{
  28093. + AVR32_IFIELD_RX,
  28094. + AVR32_IFIELD_RY,
  28095. + AVR32_IFIELD_COND4C,
  28096. + AVR32_IFIELD_K8C,
  28097. + AVR32_IFIELD_K7C,
  28098. + AVR32_IFIELD_K5C,
  28099. + AVR32_IFIELD_K3,
  28100. + AVR32_IFIELD_RY_DW,
  28101. + AVR32_IFIELD_COND4E,
  28102. + AVR32_IFIELD_K8E,
  28103. + AVR32_IFIELD_BIT5C,
  28104. + AVR32_IFIELD_COND3,
  28105. + AVR32_IFIELD_K10,
  28106. + AVR32_IFIELD_POPM,
  28107. + AVR32_IFIELD_K2,
  28108. + AVR32_IFIELD_RD_E,
  28109. + AVR32_IFIELD_RD_DW,
  28110. + AVR32_IFIELD_X,
  28111. + AVR32_IFIELD_Y,
  28112. + AVR32_IFIELD_X2,
  28113. + AVR32_IFIELD_Y2,
  28114. + AVR32_IFIELD_K5E,
  28115. + AVR32_IFIELD_PART2,
  28116. + AVR32_IFIELD_PART1,
  28117. + AVR32_IFIELD_K16,
  28118. + AVR32_IFIELD_CACHEOP,
  28119. + AVR32_IFIELD_K11,
  28120. + AVR32_IFIELD_K21,
  28121. + AVR32_IFIELD_CPOP,
  28122. + AVR32_IFIELD_CPNO,
  28123. + AVR32_IFIELD_CRD_RI,
  28124. + AVR32_IFIELD_CRX,
  28125. + AVR32_IFIELD_CRY,
  28126. + AVR32_IFIELD_K7E,
  28127. + AVR32_IFIELD_CRD_DW,
  28128. + AVR32_IFIELD_PART1_K12,
  28129. + AVR32_IFIELD_PART2_K12,
  28130. + AVR32_IFIELD_K12,
  28131. + AVR32_IFIELD_S5,
  28132. + AVR32_IFIELD_K5E2,
  28133. + AVR32_IFIELD_K4,
  28134. + AVR32_IFIELD_COND4E2,
  28135. + AVR32_IFIELD_K8E2,
  28136. + AVR32_IFIELD_K6,
  28137. + AVR32_IFIELD_MEM15,
  28138. + AVR32_IFIELD_MEMB5,
  28139. + AVR32_IFIELD_W,
  28140. + AVR32_IFIELD_CM_HL,
  28141. + AVR32_IFIELD_K12CP,
  28142. + AVR32_IFIELD_K9E,
  28143. + AVR32_IFIELD_FP_RX,
  28144. + AVR32_IFIELD_FP_RY,
  28145. + AVR32_IFIELD_FP_RD,
  28146. + AVR32_IFIELD_FP_RA,
  28147. + AVR32_IFIELD__END_,
  28148. +};
  28149. +#define AVR32_NR_IFIELDS AVR32_IFIELD__END_
  28150. +
  28151. +enum avr32_opc_type
  28152. +{
  28153. + AVR32_OPC_ABS,
  28154. + AVR32_OPC_ACALL,
  28155. + AVR32_OPC_ACR,
  28156. + AVR32_OPC_ADC,
  28157. + AVR32_OPC_ADD1,
  28158. + AVR32_OPC_ADD2,
  28159. + AVR32_OPC_ADDABS,
  28160. + AVR32_OPC_ADDHH_W,
  28161. + AVR32_OPC_AND1,
  28162. + AVR32_OPC_AND2,
  28163. + AVR32_OPC_AND3,
  28164. + AVR32_OPC_ANDH,
  28165. + AVR32_OPC_ANDH_COH,
  28166. + AVR32_OPC_ANDL,
  28167. + AVR32_OPC_ANDL_COH,
  28168. + AVR32_OPC_ANDN,
  28169. + AVR32_OPC_ASR1,
  28170. + AVR32_OPC_ASR3,
  28171. + AVR32_OPC_ASR2,
  28172. + AVR32_OPC_BLD,
  28173. + AVR32_OPC_BREQ1,
  28174. + AVR32_OPC_BRNE1,
  28175. + AVR32_OPC_BRCC1,
  28176. + AVR32_OPC_BRCS1,
  28177. + AVR32_OPC_BRGE1,
  28178. + AVR32_OPC_BRLT1,
  28179. + AVR32_OPC_BRMI1,
  28180. + AVR32_OPC_BRPL1,
  28181. + AVR32_OPC_BREQ2,
  28182. + AVR32_OPC_BRNE2,
  28183. + AVR32_OPC_BRCC2,
  28184. + AVR32_OPC_BRCS2,
  28185. + AVR32_OPC_BRGE2,
  28186. + AVR32_OPC_BRLT2,
  28187. + AVR32_OPC_BRMI2,
  28188. + AVR32_OPC_BRPL2,
  28189. + AVR32_OPC_BRLS,
  28190. + AVR32_OPC_BRGT,
  28191. + AVR32_OPC_BRLE,
  28192. + AVR32_OPC_BRHI,
  28193. + AVR32_OPC_BRVS,
  28194. + AVR32_OPC_BRVC,
  28195. + AVR32_OPC_BRQS,
  28196. + AVR32_OPC_BRAL,
  28197. + AVR32_OPC_BREAKPOINT,
  28198. + AVR32_OPC_BREV,
  28199. + AVR32_OPC_BST,
  28200. + AVR32_OPC_CACHE,
  28201. + AVR32_OPC_CASTS_B,
  28202. + AVR32_OPC_CASTS_H,
  28203. + AVR32_OPC_CASTU_B,
  28204. + AVR32_OPC_CASTU_H,
  28205. + AVR32_OPC_CBR,
  28206. + AVR32_OPC_CLZ,
  28207. + AVR32_OPC_COM,
  28208. + AVR32_OPC_COP,
  28209. + AVR32_OPC_CP_B,
  28210. + AVR32_OPC_CP_H,
  28211. + AVR32_OPC_CP_W1,
  28212. + AVR32_OPC_CP_W2,
  28213. + AVR32_OPC_CP_W3,
  28214. + AVR32_OPC_CPC1,
  28215. + AVR32_OPC_CPC2,
  28216. + AVR32_OPC_CSRF,
  28217. + AVR32_OPC_CSRFCZ,
  28218. + AVR32_OPC_DIVS,
  28219. + AVR32_OPC_DIVU,
  28220. + AVR32_OPC_EOR1,
  28221. + AVR32_OPC_EOR2,
  28222. + AVR32_OPC_EOR3,
  28223. + AVR32_OPC_EORL,
  28224. + AVR32_OPC_EORH,
  28225. + AVR32_OPC_FRS,
  28226. + AVR32_OPC_ICALL,
  28227. + AVR32_OPC_INCJOSP,
  28228. + AVR32_OPC_LD_D1,
  28229. + AVR32_OPC_LD_D2,
  28230. + AVR32_OPC_LD_D3,
  28231. + AVR32_OPC_LD_D5,
  28232. + AVR32_OPC_LD_D4,
  28233. + AVR32_OPC_LD_SB2,
  28234. + AVR32_OPC_LD_SB1,
  28235. + AVR32_OPC_LD_UB1,
  28236. + AVR32_OPC_LD_UB2,
  28237. + AVR32_OPC_LD_UB5,
  28238. + AVR32_OPC_LD_UB3,
  28239. + AVR32_OPC_LD_UB4,
  28240. + AVR32_OPC_LD_SH1,
  28241. + AVR32_OPC_LD_SH2,
  28242. + AVR32_OPC_LD_SH5,
  28243. + AVR32_OPC_LD_SH3,
  28244. + AVR32_OPC_LD_SH4,
  28245. + AVR32_OPC_LD_UH1,
  28246. + AVR32_OPC_LD_UH2,
  28247. + AVR32_OPC_LD_UH5,
  28248. + AVR32_OPC_LD_UH3,
  28249. + AVR32_OPC_LD_UH4,
  28250. + AVR32_OPC_LD_W1,
  28251. + AVR32_OPC_LD_W2,
  28252. + AVR32_OPC_LD_W5,
  28253. + AVR32_OPC_LD_W6,
  28254. + AVR32_OPC_LD_W3,
  28255. + AVR32_OPC_LD_W4,
  28256. + AVR32_OPC_LDC_D1,
  28257. + AVR32_OPC_LDC_D2,
  28258. + AVR32_OPC_LDC_D3,
  28259. + AVR32_OPC_LDC_W1,
  28260. + AVR32_OPC_LDC_W2,
  28261. + AVR32_OPC_LDC_W3,
  28262. + AVR32_OPC_LDC0_D,
  28263. + AVR32_OPC_LDC0_W,
  28264. + AVR32_OPC_LDCM_D,
  28265. + AVR32_OPC_LDCM_D_PU,
  28266. + AVR32_OPC_LDCM_W,
  28267. + AVR32_OPC_LDCM_W_PU,
  28268. + AVR32_OPC_LDDPC,
  28269. + AVR32_OPC_LDDPC_EXT,
  28270. + AVR32_OPC_LDDSP,
  28271. + AVR32_OPC_LDINS_B,
  28272. + AVR32_OPC_LDINS_H,
  28273. + AVR32_OPC_LDM,
  28274. + AVR32_OPC_LDMTS,
  28275. + AVR32_OPC_LDMTS_PU,
  28276. + AVR32_OPC_LDSWP_SH,
  28277. + AVR32_OPC_LDSWP_UH,
  28278. + AVR32_OPC_LDSWP_W,
  28279. + AVR32_OPC_LSL1,
  28280. + AVR32_OPC_LSL3,
  28281. + AVR32_OPC_LSL2,
  28282. + AVR32_OPC_LSR1,
  28283. + AVR32_OPC_LSR3,
  28284. + AVR32_OPC_LSR2,
  28285. + AVR32_OPC_MAC,
  28286. + AVR32_OPC_MACHH_D,
  28287. + AVR32_OPC_MACHH_W,
  28288. + AVR32_OPC_MACS_D,
  28289. + AVR32_OPC_MACSATHH_W,
  28290. + AVR32_OPC_MACUD,
  28291. + AVR32_OPC_MACWH_D,
  28292. + AVR32_OPC_MAX,
  28293. + AVR32_OPC_MCALL,
  28294. + AVR32_OPC_MFDR,
  28295. + AVR32_OPC_MFSR,
  28296. + AVR32_OPC_MIN,
  28297. + AVR32_OPC_MOV3,
  28298. + AVR32_OPC_MOV1,
  28299. + AVR32_OPC_MOV2,
  28300. + AVR32_OPC_MOVEQ1,
  28301. + AVR32_OPC_MOVNE1,
  28302. + AVR32_OPC_MOVCC1,
  28303. + AVR32_OPC_MOVCS1,
  28304. + AVR32_OPC_MOVGE1,
  28305. + AVR32_OPC_MOVLT1,
  28306. + AVR32_OPC_MOVMI1,
  28307. + AVR32_OPC_MOVPL1,
  28308. + AVR32_OPC_MOVLS1,
  28309. + AVR32_OPC_MOVGT1,
  28310. + AVR32_OPC_MOVLE1,
  28311. + AVR32_OPC_MOVHI1,
  28312. + AVR32_OPC_MOVVS1,
  28313. + AVR32_OPC_MOVVC1,
  28314. + AVR32_OPC_MOVQS1,
  28315. + AVR32_OPC_MOVAL1,
  28316. + AVR32_OPC_MOVEQ2,
  28317. + AVR32_OPC_MOVNE2,
  28318. + AVR32_OPC_MOVCC2,
  28319. + AVR32_OPC_MOVCS2,
  28320. + AVR32_OPC_MOVGE2,
  28321. + AVR32_OPC_MOVLT2,
  28322. + AVR32_OPC_MOVMI2,
  28323. + AVR32_OPC_MOVPL2,
  28324. + AVR32_OPC_MOVLS2,
  28325. + AVR32_OPC_MOVGT2,
  28326. + AVR32_OPC_MOVLE2,
  28327. + AVR32_OPC_MOVHI2,
  28328. + AVR32_OPC_MOVVS2,
  28329. + AVR32_OPC_MOVVC2,
  28330. + AVR32_OPC_MOVQS2,
  28331. + AVR32_OPC_MOVAL2,
  28332. + AVR32_OPC_MTDR,
  28333. + AVR32_OPC_MTSR,
  28334. + AVR32_OPC_MUL1,
  28335. + AVR32_OPC_MUL2,
  28336. + AVR32_OPC_MUL3,
  28337. + AVR32_OPC_MULHH_W,
  28338. + AVR32_OPC_MULNHH_W,
  28339. + AVR32_OPC_MULNWH_D,
  28340. + AVR32_OPC_MULSD,
  28341. + AVR32_OPC_MULSATHH_H,
  28342. + AVR32_OPC_MULSATHH_W,
  28343. + AVR32_OPC_MULSATRNDHH_H,
  28344. + AVR32_OPC_MULSATRNDWH_W,
  28345. + AVR32_OPC_MULSATWH_W,
  28346. + AVR32_OPC_MULU_D,
  28347. + AVR32_OPC_MULWH_D,
  28348. + AVR32_OPC_MUSFR,
  28349. + AVR32_OPC_MUSTR,
  28350. + AVR32_OPC_MVCR_D,
  28351. + AVR32_OPC_MVCR_W,
  28352. + AVR32_OPC_MVRC_D,
  28353. + AVR32_OPC_MVRC_W,
  28354. + AVR32_OPC_NEG,
  28355. + AVR32_OPC_NOP,
  28356. + AVR32_OPC_OR1,
  28357. + AVR32_OPC_OR2,
  28358. + AVR32_OPC_OR3,
  28359. + AVR32_OPC_ORH,
  28360. + AVR32_OPC_ORL,
  28361. + AVR32_OPC_PABS_SB,
  28362. + AVR32_OPC_PABS_SH,
  28363. + AVR32_OPC_PACKSH_SB,
  28364. + AVR32_OPC_PACKSH_UB,
  28365. + AVR32_OPC_PACKW_SH,
  28366. + AVR32_OPC_PADD_B,
  28367. + AVR32_OPC_PADD_H,
  28368. + AVR32_OPC_PADDH_SH,
  28369. + AVR32_OPC_PADDH_UB,
  28370. + AVR32_OPC_PADDS_SB,
  28371. + AVR32_OPC_PADDS_SH,
  28372. + AVR32_OPC_PADDS_UB,
  28373. + AVR32_OPC_PADDS_UH,
  28374. + AVR32_OPC_PADDSUB_H,
  28375. + AVR32_OPC_PADDSUBH_SH,
  28376. + AVR32_OPC_PADDSUBS_SH,
  28377. + AVR32_OPC_PADDSUBS_UH,
  28378. + AVR32_OPC_PADDX_H,
  28379. + AVR32_OPC_PADDXH_SH,
  28380. + AVR32_OPC_PADDXS_SH,
  28381. + AVR32_OPC_PADDXS_UH,
  28382. + AVR32_OPC_PASR_B,
  28383. + AVR32_OPC_PASR_H,
  28384. + AVR32_OPC_PAVG_SH,
  28385. + AVR32_OPC_PAVG_UB,
  28386. + AVR32_OPC_PLSL_B,
  28387. + AVR32_OPC_PLSL_H,
  28388. + AVR32_OPC_PLSR_B,
  28389. + AVR32_OPC_PLSR_H,
  28390. + AVR32_OPC_PMAX_SH,
  28391. + AVR32_OPC_PMAX_UB,
  28392. + AVR32_OPC_PMIN_SH,
  28393. + AVR32_OPC_PMIN_UB,
  28394. + AVR32_OPC_POPJC,
  28395. + AVR32_OPC_POPM,
  28396. + AVR32_OPC_POPM_E,
  28397. + AVR32_OPC_PREF,
  28398. + AVR32_OPC_PSAD,
  28399. + AVR32_OPC_PSUB_B,
  28400. + AVR32_OPC_PSUB_H,
  28401. + AVR32_OPC_PSUBADD_H,
  28402. + AVR32_OPC_PSUBADDH_SH,
  28403. + AVR32_OPC_PSUBADDS_SH,
  28404. + AVR32_OPC_PSUBADDS_UH,
  28405. + AVR32_OPC_PSUBH_SH,
  28406. + AVR32_OPC_PSUBH_UB,
  28407. + AVR32_OPC_PSUBS_SB,
  28408. + AVR32_OPC_PSUBS_SH,
  28409. + AVR32_OPC_PSUBS_UB,
  28410. + AVR32_OPC_PSUBS_UH,
  28411. + AVR32_OPC_PSUBX_H,
  28412. + AVR32_OPC_PSUBXH_SH,
  28413. + AVR32_OPC_PSUBXS_SH,
  28414. + AVR32_OPC_PSUBXS_UH,
  28415. + AVR32_OPC_PUNPCKSB_H,
  28416. + AVR32_OPC_PUNPCKUB_H,
  28417. + AVR32_OPC_PUSHJC,
  28418. + AVR32_OPC_PUSHM,
  28419. + AVR32_OPC_PUSHM_E,
  28420. + AVR32_OPC_RCALL1,
  28421. + AVR32_OPC_RCALL2,
  28422. + AVR32_OPC_RETEQ,
  28423. + AVR32_OPC_RETNE,
  28424. + AVR32_OPC_RETCC,
  28425. + AVR32_OPC_RETCS,
  28426. + AVR32_OPC_RETGE,
  28427. + AVR32_OPC_RETLT,
  28428. + AVR32_OPC_RETMI,
  28429. + AVR32_OPC_RETPL,
  28430. + AVR32_OPC_RETLS,
  28431. + AVR32_OPC_RETGT,
  28432. + AVR32_OPC_RETLE,
  28433. + AVR32_OPC_RETHI,
  28434. + AVR32_OPC_RETVS,
  28435. + AVR32_OPC_RETVC,
  28436. + AVR32_OPC_RETQS,
  28437. + AVR32_OPC_RETAL,
  28438. + AVR32_OPC_RETD,
  28439. + AVR32_OPC_RETE,
  28440. + AVR32_OPC_RETJ,
  28441. + AVR32_OPC_RETS,
  28442. + AVR32_OPC_RJMP,
  28443. + AVR32_OPC_ROL,
  28444. + AVR32_OPC_ROR,
  28445. + AVR32_OPC_RSUB1,
  28446. + AVR32_OPC_RSUB2,
  28447. + AVR32_OPC_SATADD_H,
  28448. + AVR32_OPC_SATADD_W,
  28449. + AVR32_OPC_SATRNDS,
  28450. + AVR32_OPC_SATRNDU,
  28451. + AVR32_OPC_SATS,
  28452. + AVR32_OPC_SATSUB_H,
  28453. + AVR32_OPC_SATSUB_W1,
  28454. + AVR32_OPC_SATSUB_W2,
  28455. + AVR32_OPC_SATU,
  28456. + AVR32_OPC_SBC,
  28457. + AVR32_OPC_SBR,
  28458. + AVR32_OPC_SCALL,
  28459. + AVR32_OPC_SCR,
  28460. + AVR32_OPC_SLEEP,
  28461. + AVR32_OPC_SREQ,
  28462. + AVR32_OPC_SRNE,
  28463. + AVR32_OPC_SRCC,
  28464. + AVR32_OPC_SRCS,
  28465. + AVR32_OPC_SRGE,
  28466. + AVR32_OPC_SRLT,
  28467. + AVR32_OPC_SRMI,
  28468. + AVR32_OPC_SRPL,
  28469. + AVR32_OPC_SRLS,
  28470. + AVR32_OPC_SRGT,
  28471. + AVR32_OPC_SRLE,
  28472. + AVR32_OPC_SRHI,
  28473. + AVR32_OPC_SRVS,
  28474. + AVR32_OPC_SRVC,
  28475. + AVR32_OPC_SRQS,
  28476. + AVR32_OPC_SRAL,
  28477. + AVR32_OPC_SSRF,
  28478. + AVR32_OPC_ST_B1,
  28479. + AVR32_OPC_ST_B2,
  28480. + AVR32_OPC_ST_B5,
  28481. + AVR32_OPC_ST_B3,
  28482. + AVR32_OPC_ST_B4,
  28483. + AVR32_OPC_ST_D1,
  28484. + AVR32_OPC_ST_D2,
  28485. + AVR32_OPC_ST_D3,
  28486. + AVR32_OPC_ST_D5,
  28487. + AVR32_OPC_ST_D4,
  28488. + AVR32_OPC_ST_H1,
  28489. + AVR32_OPC_ST_H2,
  28490. + AVR32_OPC_ST_H5,
  28491. + AVR32_OPC_ST_H3,
  28492. + AVR32_OPC_ST_H4,
  28493. + AVR32_OPC_ST_W1,
  28494. + AVR32_OPC_ST_W2,
  28495. + AVR32_OPC_ST_W5,
  28496. + AVR32_OPC_ST_W3,
  28497. + AVR32_OPC_ST_W4,
  28498. + AVR32_OPC_STC_D1,
  28499. + AVR32_OPC_STC_D2,
  28500. + AVR32_OPC_STC_D3,
  28501. + AVR32_OPC_STC_W1,
  28502. + AVR32_OPC_STC_W2,
  28503. + AVR32_OPC_STC_W3,
  28504. + AVR32_OPC_STC0_D,
  28505. + AVR32_OPC_STC0_W,
  28506. + AVR32_OPC_STCM_D,
  28507. + AVR32_OPC_STCM_D_PU,
  28508. + AVR32_OPC_STCM_W,
  28509. + AVR32_OPC_STCM_W_PU,
  28510. + AVR32_OPC_STCOND,
  28511. + AVR32_OPC_STDSP,
  28512. + AVR32_OPC_STHH_W2,
  28513. + AVR32_OPC_STHH_W1,
  28514. + AVR32_OPC_STM,
  28515. + AVR32_OPC_STM_PU,
  28516. + AVR32_OPC_STMTS,
  28517. + AVR32_OPC_STMTS_PU,
  28518. + AVR32_OPC_STSWP_H,
  28519. + AVR32_OPC_STSWP_W,
  28520. + AVR32_OPC_SUB1,
  28521. + AVR32_OPC_SUB2,
  28522. + AVR32_OPC_SUB5,
  28523. + AVR32_OPC_SUB3_SP,
  28524. + AVR32_OPC_SUB3,
  28525. + AVR32_OPC_SUB4,
  28526. + AVR32_OPC_SUBEQ,
  28527. + AVR32_OPC_SUBNE,
  28528. + AVR32_OPC_SUBCC,
  28529. + AVR32_OPC_SUBCS,
  28530. + AVR32_OPC_SUBGE,
  28531. + AVR32_OPC_SUBLT,
  28532. + AVR32_OPC_SUBMI,
  28533. + AVR32_OPC_SUBPL,
  28534. + AVR32_OPC_SUBLS,
  28535. + AVR32_OPC_SUBGT,
  28536. + AVR32_OPC_SUBLE,
  28537. + AVR32_OPC_SUBHI,
  28538. + AVR32_OPC_SUBVS,
  28539. + AVR32_OPC_SUBVC,
  28540. + AVR32_OPC_SUBQS,
  28541. + AVR32_OPC_SUBAL,
  28542. + AVR32_OPC_SUBFEQ,
  28543. + AVR32_OPC_SUBFNE,
  28544. + AVR32_OPC_SUBFCC,
  28545. + AVR32_OPC_SUBFCS,
  28546. + AVR32_OPC_SUBFGE,
  28547. + AVR32_OPC_SUBFLT,
  28548. + AVR32_OPC_SUBFMI,
  28549. + AVR32_OPC_SUBFPL,
  28550. + AVR32_OPC_SUBFLS,
  28551. + AVR32_OPC_SUBFGT,
  28552. + AVR32_OPC_SUBFLE,
  28553. + AVR32_OPC_SUBFHI,
  28554. + AVR32_OPC_SUBFVS,
  28555. + AVR32_OPC_SUBFVC,
  28556. + AVR32_OPC_SUBFQS,
  28557. + AVR32_OPC_SUBFAL,
  28558. + AVR32_OPC_SUBHH_W,
  28559. + AVR32_OPC_SWAP_B,
  28560. + AVR32_OPC_SWAP_BH,
  28561. + AVR32_OPC_SWAP_H,
  28562. + AVR32_OPC_SYNC,
  28563. + AVR32_OPC_TLBR,
  28564. + AVR32_OPC_TLBS,
  28565. + AVR32_OPC_TLBW,
  28566. + AVR32_OPC_TNBZ,
  28567. + AVR32_OPC_TST,
  28568. + AVR32_OPC_XCHG,
  28569. + AVR32_OPC_MEMC,
  28570. + AVR32_OPC_MEMS,
  28571. + AVR32_OPC_MEMT,
  28572. + AVR32_OPC_BFEXTS,
  28573. + AVR32_OPC_BFEXTU,
  28574. + AVR32_OPC_BFINS,
  28575. + AVR32_OPC_RSUBEQ,
  28576. + AVR32_OPC_RSUBNE,
  28577. + AVR32_OPC_RSUBCC,
  28578. + AVR32_OPC_RSUBCS,
  28579. + AVR32_OPC_RSUBGE,
  28580. + AVR32_OPC_RSUBLT,
  28581. + AVR32_OPC_RSUBMI,
  28582. + AVR32_OPC_RSUBPL,
  28583. + AVR32_OPC_RSUBLS,
  28584. + AVR32_OPC_RSUBGT,
  28585. + AVR32_OPC_RSUBLE,
  28586. + AVR32_OPC_RSUBHI,
  28587. + AVR32_OPC_RSUBVS,
  28588. + AVR32_OPC_RSUBVC,
  28589. + AVR32_OPC_RSUBQS,
  28590. + AVR32_OPC_RSUBAL,
  28591. + AVR32_OPC_ADDEQ,
  28592. + AVR32_OPC_ADDNE,
  28593. + AVR32_OPC_ADDCC,
  28594. + AVR32_OPC_ADDCS,
  28595. + AVR32_OPC_ADDGE,
  28596. + AVR32_OPC_ADDLT,
  28597. + AVR32_OPC_ADDMI,
  28598. + AVR32_OPC_ADDPL,
  28599. + AVR32_OPC_ADDLS,
  28600. + AVR32_OPC_ADDGT,
  28601. + AVR32_OPC_ADDLE,
  28602. + AVR32_OPC_ADDHI,
  28603. + AVR32_OPC_ADDVS,
  28604. + AVR32_OPC_ADDVC,
  28605. + AVR32_OPC_ADDQS,
  28606. + AVR32_OPC_ADDAL,
  28607. + AVR32_OPC_SUB2EQ,
  28608. + AVR32_OPC_SUB2NE,
  28609. + AVR32_OPC_SUB2CC,
  28610. + AVR32_OPC_SUB2CS,
  28611. + AVR32_OPC_SUB2GE,
  28612. + AVR32_OPC_SUB2LT,
  28613. + AVR32_OPC_SUB2MI,
  28614. + AVR32_OPC_SUB2PL,
  28615. + AVR32_OPC_SUB2LS,
  28616. + AVR32_OPC_SUB2GT,
  28617. + AVR32_OPC_SUB2LE,
  28618. + AVR32_OPC_SUB2HI,
  28619. + AVR32_OPC_SUB2VS,
  28620. + AVR32_OPC_SUB2VC,
  28621. + AVR32_OPC_SUB2QS,
  28622. + AVR32_OPC_SUB2AL,
  28623. + AVR32_OPC_ANDEQ,
  28624. + AVR32_OPC_ANDNE,
  28625. + AVR32_OPC_ANDCC,
  28626. + AVR32_OPC_ANDCS,
  28627. + AVR32_OPC_ANDGE,
  28628. + AVR32_OPC_ANDLT,
  28629. + AVR32_OPC_ANDMI,
  28630. + AVR32_OPC_ANDPL,
  28631. + AVR32_OPC_ANDLS,
  28632. + AVR32_OPC_ANDGT,
  28633. + AVR32_OPC_ANDLE,
  28634. + AVR32_OPC_ANDHI,
  28635. + AVR32_OPC_ANDVS,
  28636. + AVR32_OPC_ANDVC,
  28637. + AVR32_OPC_ANDQS,
  28638. + AVR32_OPC_ANDAL,
  28639. + AVR32_OPC_OREQ,
  28640. + AVR32_OPC_ORNE,
  28641. + AVR32_OPC_ORCC,
  28642. + AVR32_OPC_ORCS,
  28643. + AVR32_OPC_ORGE,
  28644. + AVR32_OPC_ORLT,
  28645. + AVR32_OPC_ORMI,
  28646. + AVR32_OPC_ORPL,
  28647. + AVR32_OPC_ORLS,
  28648. + AVR32_OPC_ORGT,
  28649. + AVR32_OPC_ORLE,
  28650. + AVR32_OPC_ORHI,
  28651. + AVR32_OPC_ORVS,
  28652. + AVR32_OPC_ORVC,
  28653. + AVR32_OPC_ORQS,
  28654. + AVR32_OPC_ORAL,
  28655. + AVR32_OPC_EOREQ,
  28656. + AVR32_OPC_EORNE,
  28657. + AVR32_OPC_EORCC,
  28658. + AVR32_OPC_EORCS,
  28659. + AVR32_OPC_EORGE,
  28660. + AVR32_OPC_EORLT,
  28661. + AVR32_OPC_EORMI,
  28662. + AVR32_OPC_EORPL,
  28663. + AVR32_OPC_EORLS,
  28664. + AVR32_OPC_EORGT,
  28665. + AVR32_OPC_EORLE,
  28666. + AVR32_OPC_EORHI,
  28667. + AVR32_OPC_EORVS,
  28668. + AVR32_OPC_EORVC,
  28669. + AVR32_OPC_EORQS,
  28670. + AVR32_OPC_EORAL,
  28671. + AVR32_OPC_LD_WEQ,
  28672. + AVR32_OPC_LD_WNE,
  28673. + AVR32_OPC_LD_WCC,
  28674. + AVR32_OPC_LD_WCS,
  28675. + AVR32_OPC_LD_WGE,
  28676. + AVR32_OPC_LD_WLT,
  28677. + AVR32_OPC_LD_WMI,
  28678. + AVR32_OPC_LD_WPL,
  28679. + AVR32_OPC_LD_WLS,
  28680. + AVR32_OPC_LD_WGT,
  28681. + AVR32_OPC_LD_WLE,
  28682. + AVR32_OPC_LD_WHI,
  28683. + AVR32_OPC_LD_WVS,
  28684. + AVR32_OPC_LD_WVC,
  28685. + AVR32_OPC_LD_WQS,
  28686. + AVR32_OPC_LD_WAL,
  28687. + AVR32_OPC_LD_SHEQ,
  28688. + AVR32_OPC_LD_SHNE,
  28689. + AVR32_OPC_LD_SHCC,
  28690. + AVR32_OPC_LD_SHCS,
  28691. + AVR32_OPC_LD_SHGE,
  28692. + AVR32_OPC_LD_SHLT,
  28693. + AVR32_OPC_LD_SHMI,
  28694. + AVR32_OPC_LD_SHPL,
  28695. + AVR32_OPC_LD_SHLS,
  28696. + AVR32_OPC_LD_SHGT,
  28697. + AVR32_OPC_LD_SHLE,
  28698. + AVR32_OPC_LD_SHHI,
  28699. + AVR32_OPC_LD_SHVS,
  28700. + AVR32_OPC_LD_SHVC,
  28701. + AVR32_OPC_LD_SHQS,
  28702. + AVR32_OPC_LD_SHAL,
  28703. + AVR32_OPC_LD_UHEQ,
  28704. + AVR32_OPC_LD_UHNE,
  28705. + AVR32_OPC_LD_UHCC,
  28706. + AVR32_OPC_LD_UHCS,
  28707. + AVR32_OPC_LD_UHGE,
  28708. + AVR32_OPC_LD_UHLT,
  28709. + AVR32_OPC_LD_UHMI,
  28710. + AVR32_OPC_LD_UHPL,
  28711. + AVR32_OPC_LD_UHLS,
  28712. + AVR32_OPC_LD_UHGT,
  28713. + AVR32_OPC_LD_UHLE,
  28714. + AVR32_OPC_LD_UHHI,
  28715. + AVR32_OPC_LD_UHVS,
  28716. + AVR32_OPC_LD_UHVC,
  28717. + AVR32_OPC_LD_UHQS,
  28718. + AVR32_OPC_LD_UHAL,
  28719. + AVR32_OPC_LD_SBEQ,
  28720. + AVR32_OPC_LD_SBNE,
  28721. + AVR32_OPC_LD_SBCC,
  28722. + AVR32_OPC_LD_SBCS,
  28723. + AVR32_OPC_LD_SBGE,
  28724. + AVR32_OPC_LD_SBLT,
  28725. + AVR32_OPC_LD_SBMI,
  28726. + AVR32_OPC_LD_SBPL,
  28727. + AVR32_OPC_LD_SBLS,
  28728. + AVR32_OPC_LD_SBGT,
  28729. + AVR32_OPC_LD_SBLE,
  28730. + AVR32_OPC_LD_SBHI,
  28731. + AVR32_OPC_LD_SBVS,
  28732. + AVR32_OPC_LD_SBVC,
  28733. + AVR32_OPC_LD_SBQS,
  28734. + AVR32_OPC_LD_SBAL,
  28735. + AVR32_OPC_LD_UBEQ,
  28736. + AVR32_OPC_LD_UBNE,
  28737. + AVR32_OPC_LD_UBCC,
  28738. + AVR32_OPC_LD_UBCS,
  28739. + AVR32_OPC_LD_UBGE,
  28740. + AVR32_OPC_LD_UBLT,
  28741. + AVR32_OPC_LD_UBMI,
  28742. + AVR32_OPC_LD_UBPL,
  28743. + AVR32_OPC_LD_UBLS,
  28744. + AVR32_OPC_LD_UBGT,
  28745. + AVR32_OPC_LD_UBLE,
  28746. + AVR32_OPC_LD_UBHI,
  28747. + AVR32_OPC_LD_UBVS,
  28748. + AVR32_OPC_LD_UBVC,
  28749. + AVR32_OPC_LD_UBQS,
  28750. + AVR32_OPC_LD_UBAL,
  28751. + AVR32_OPC_ST_WEQ,
  28752. + AVR32_OPC_ST_WNE,
  28753. + AVR32_OPC_ST_WCC,
  28754. + AVR32_OPC_ST_WCS,
  28755. + AVR32_OPC_ST_WGE,
  28756. + AVR32_OPC_ST_WLT,
  28757. + AVR32_OPC_ST_WMI,
  28758. + AVR32_OPC_ST_WPL,
  28759. + AVR32_OPC_ST_WLS,
  28760. + AVR32_OPC_ST_WGT,
  28761. + AVR32_OPC_ST_WLE,
  28762. + AVR32_OPC_ST_WHI,
  28763. + AVR32_OPC_ST_WVS,
  28764. + AVR32_OPC_ST_WVC,
  28765. + AVR32_OPC_ST_WQS,
  28766. + AVR32_OPC_ST_WAL,
  28767. + AVR32_OPC_ST_HEQ,
  28768. + AVR32_OPC_ST_HNE,
  28769. + AVR32_OPC_ST_HCC,
  28770. + AVR32_OPC_ST_HCS,
  28771. + AVR32_OPC_ST_HGE,
  28772. + AVR32_OPC_ST_HLT,
  28773. + AVR32_OPC_ST_HMI,
  28774. + AVR32_OPC_ST_HPL,
  28775. + AVR32_OPC_ST_HLS,
  28776. + AVR32_OPC_ST_HGT,
  28777. + AVR32_OPC_ST_HLE,
  28778. + AVR32_OPC_ST_HHI,
  28779. + AVR32_OPC_ST_HVS,
  28780. + AVR32_OPC_ST_HVC,
  28781. + AVR32_OPC_ST_HQS,
  28782. + AVR32_OPC_ST_HAL,
  28783. + AVR32_OPC_ST_BEQ,
  28784. + AVR32_OPC_ST_BNE,
  28785. + AVR32_OPC_ST_BCC,
  28786. + AVR32_OPC_ST_BCS,
  28787. + AVR32_OPC_ST_BGE,
  28788. + AVR32_OPC_ST_BLT,
  28789. + AVR32_OPC_ST_BMI,
  28790. + AVR32_OPC_ST_BPL,
  28791. + AVR32_OPC_ST_BLS,
  28792. + AVR32_OPC_ST_BGT,
  28793. + AVR32_OPC_ST_BLE,
  28794. + AVR32_OPC_ST_BHI,
  28795. + AVR32_OPC_ST_BVS,
  28796. + AVR32_OPC_ST_BVC,
  28797. + AVR32_OPC_ST_BQS,
  28798. + AVR32_OPC_ST_BAL,
  28799. + AVR32_OPC_MOVH,
  28800. + AVR32_OPC_SSCALL,
  28801. + AVR32_OPC_RETSS,
  28802. + AVR32_OPC_FMAC_S,
  28803. + AVR32_OPC_FNMAC_S,
  28804. + AVR32_OPC_FMSC_S,
  28805. + AVR32_OPC_FNMSC_S,
  28806. + AVR32_OPC_FMUL_S,
  28807. + AVR32_OPC_FNMUL_S,
  28808. + AVR32_OPC_FADD_S,
  28809. + AVR32_OPC_FSUB_S,
  28810. + AVR32_OPC_FCASTRS_SW,
  28811. + AVR32_OPC_FCASTRS_UW,
  28812. + AVR32_OPC_FCASTSW_S,
  28813. + AVR32_OPC_FCASTUW_S,
  28814. + AVR32_OPC_FCMP_S,
  28815. + AVR32_OPC_FCHK_S,
  28816. + AVR32_OPC_FRCPA_S,
  28817. + AVR32_OPC_FRSQRTA_S,
  28818. + AVR32_OPC__END_
  28819. +};
  28820. +#define AVR32_NR_OPCODES AVR32_OPC__END_
  28821. +
  28822. +enum avr32_syntax_type
  28823. +{
  28824. + AVR32_SYNTAX_ABS,
  28825. + AVR32_SYNTAX_ACALL,
  28826. + AVR32_SYNTAX_ACR,
  28827. + AVR32_SYNTAX_ADC,
  28828. + AVR32_SYNTAX_ADD1,
  28829. + AVR32_SYNTAX_ADD2,
  28830. + AVR32_SYNTAX_ADDABS,
  28831. + AVR32_SYNTAX_ADDHH_W,
  28832. + AVR32_SYNTAX_AND1,
  28833. + AVR32_SYNTAX_AND2,
  28834. + AVR32_SYNTAX_AND3,
  28835. + AVR32_SYNTAX_ANDH,
  28836. + AVR32_SYNTAX_ANDH_COH,
  28837. + AVR32_SYNTAX_ANDL,
  28838. + AVR32_SYNTAX_ANDL_COH,
  28839. + AVR32_SYNTAX_ANDN,
  28840. + AVR32_SYNTAX_ASR1,
  28841. + AVR32_SYNTAX_ASR3,
  28842. + AVR32_SYNTAX_ASR2,
  28843. + AVR32_SYNTAX_BFEXTS,
  28844. + AVR32_SYNTAX_BFEXTU,
  28845. + AVR32_SYNTAX_BFINS,
  28846. + AVR32_SYNTAX_BLD,
  28847. + AVR32_SYNTAX_BREQ1,
  28848. + AVR32_SYNTAX_BRNE1,
  28849. + AVR32_SYNTAX_BRCC1,
  28850. + AVR32_SYNTAX_BRCS1,
  28851. + AVR32_SYNTAX_BRGE1,
  28852. + AVR32_SYNTAX_BRLT1,
  28853. + AVR32_SYNTAX_BRMI1,
  28854. + AVR32_SYNTAX_BRPL1,
  28855. + AVR32_SYNTAX_BRHS1,
  28856. + AVR32_SYNTAX_BRLO1,
  28857. + AVR32_SYNTAX_BREQ2,
  28858. + AVR32_SYNTAX_BRNE2,
  28859. + AVR32_SYNTAX_BRCC2,
  28860. + AVR32_SYNTAX_BRCS2,
  28861. + AVR32_SYNTAX_BRGE2,
  28862. + AVR32_SYNTAX_BRLT2,
  28863. + AVR32_SYNTAX_BRMI2,
  28864. + AVR32_SYNTAX_BRPL2,
  28865. + AVR32_SYNTAX_BRLS,
  28866. + AVR32_SYNTAX_BRGT,
  28867. + AVR32_SYNTAX_BRLE,
  28868. + AVR32_SYNTAX_BRHI,
  28869. + AVR32_SYNTAX_BRVS,
  28870. + AVR32_SYNTAX_BRVC,
  28871. + AVR32_SYNTAX_BRQS,
  28872. + AVR32_SYNTAX_BRAL,
  28873. + AVR32_SYNTAX_BRHS2,
  28874. + AVR32_SYNTAX_BRLO2,
  28875. + AVR32_SYNTAX_BREAKPOINT,
  28876. + AVR32_SYNTAX_BREV,
  28877. + AVR32_SYNTAX_BST,
  28878. + AVR32_SYNTAX_CACHE,
  28879. + AVR32_SYNTAX_CASTS_B,
  28880. + AVR32_SYNTAX_CASTS_H,
  28881. + AVR32_SYNTAX_CASTU_B,
  28882. + AVR32_SYNTAX_CASTU_H,
  28883. + AVR32_SYNTAX_CBR,
  28884. + AVR32_SYNTAX_CLZ,
  28885. + AVR32_SYNTAX_COM,
  28886. + AVR32_SYNTAX_COP,
  28887. + AVR32_SYNTAX_CP_B,
  28888. + AVR32_SYNTAX_CP_H,
  28889. + AVR32_SYNTAX_CP_W1,
  28890. + AVR32_SYNTAX_CP_W2,
  28891. + AVR32_SYNTAX_CP_W3,
  28892. + AVR32_SYNTAX_CPC1,
  28893. + AVR32_SYNTAX_CPC2,
  28894. + AVR32_SYNTAX_CSRF,
  28895. + AVR32_SYNTAX_CSRFCZ,
  28896. + AVR32_SYNTAX_DIVS,
  28897. + AVR32_SYNTAX_DIVU,
  28898. + AVR32_SYNTAX_EOR1,
  28899. + AVR32_SYNTAX_EOR2,
  28900. + AVR32_SYNTAX_EOR3,
  28901. + AVR32_SYNTAX_EORL,
  28902. + AVR32_SYNTAX_EORH,
  28903. + AVR32_SYNTAX_FRS,
  28904. + AVR32_SYNTAX_SSCALL,
  28905. + AVR32_SYNTAX_RETSS,
  28906. + AVR32_SYNTAX_ICALL,
  28907. + AVR32_SYNTAX_INCJOSP,
  28908. + AVR32_SYNTAX_LD_D1,
  28909. + AVR32_SYNTAX_LD_D2,
  28910. + AVR32_SYNTAX_LD_D3,
  28911. + AVR32_SYNTAX_LD_D5,
  28912. + AVR32_SYNTAX_LD_D4,
  28913. + AVR32_SYNTAX_LD_SB2,
  28914. + AVR32_SYNTAX_LD_SB1,
  28915. + AVR32_SYNTAX_LD_UB1,
  28916. + AVR32_SYNTAX_LD_UB2,
  28917. + AVR32_SYNTAX_LD_UB5,
  28918. + AVR32_SYNTAX_LD_UB3,
  28919. + AVR32_SYNTAX_LD_UB4,
  28920. + AVR32_SYNTAX_LD_SH1,
  28921. + AVR32_SYNTAX_LD_SH2,
  28922. + AVR32_SYNTAX_LD_SH5,
  28923. + AVR32_SYNTAX_LD_SH3,
  28924. + AVR32_SYNTAX_LD_SH4,
  28925. + AVR32_SYNTAX_LD_UH1,
  28926. + AVR32_SYNTAX_LD_UH2,
  28927. + AVR32_SYNTAX_LD_UH5,
  28928. + AVR32_SYNTAX_LD_UH3,
  28929. + AVR32_SYNTAX_LD_UH4,
  28930. + AVR32_SYNTAX_LD_W1,
  28931. + AVR32_SYNTAX_LD_W2,
  28932. + AVR32_SYNTAX_LD_W5,
  28933. + AVR32_SYNTAX_LD_W6,
  28934. + AVR32_SYNTAX_LD_W3,
  28935. + AVR32_SYNTAX_LD_W4,
  28936. + AVR32_SYNTAX_LDC_D1,
  28937. + AVR32_SYNTAX_LDC_D2,
  28938. + AVR32_SYNTAX_LDC_D3,
  28939. + AVR32_SYNTAX_LDC_W1,
  28940. + AVR32_SYNTAX_LDC_W2,
  28941. + AVR32_SYNTAX_LDC_W3,
  28942. + AVR32_SYNTAX_LDC0_D,
  28943. + AVR32_SYNTAX_LDC0_W,
  28944. + AVR32_SYNTAX_LDCM_D,
  28945. + AVR32_SYNTAX_LDCM_D_PU,
  28946. + AVR32_SYNTAX_LDCM_W,
  28947. + AVR32_SYNTAX_LDCM_W_PU,
  28948. + AVR32_SYNTAX_LDDPC,
  28949. + AVR32_SYNTAX_LDDPC_EXT,
  28950. + AVR32_SYNTAX_LDDSP,
  28951. + AVR32_SYNTAX_LDINS_B,
  28952. + AVR32_SYNTAX_LDINS_H,
  28953. + AVR32_SYNTAX_LDM,
  28954. + AVR32_SYNTAX_LDMTS,
  28955. + AVR32_SYNTAX_LDMTS_PU,
  28956. + AVR32_SYNTAX_LDSWP_SH,
  28957. + AVR32_SYNTAX_LDSWP_UH,
  28958. + AVR32_SYNTAX_LDSWP_W,
  28959. + AVR32_SYNTAX_LSL1,
  28960. + AVR32_SYNTAX_LSL3,
  28961. + AVR32_SYNTAX_LSL2,
  28962. + AVR32_SYNTAX_LSR1,
  28963. + AVR32_SYNTAX_LSR3,
  28964. + AVR32_SYNTAX_LSR2,
  28965. + AVR32_SYNTAX_MAC,
  28966. + AVR32_SYNTAX_MACHH_D,
  28967. + AVR32_SYNTAX_MACHH_W,
  28968. + AVR32_SYNTAX_MACS_D,
  28969. + AVR32_SYNTAX_MACSATHH_W,
  28970. + AVR32_SYNTAX_MACUD,
  28971. + AVR32_SYNTAX_MACWH_D,
  28972. + AVR32_SYNTAX_MAX,
  28973. + AVR32_SYNTAX_MCALL,
  28974. + AVR32_SYNTAX_MFDR,
  28975. + AVR32_SYNTAX_MFSR,
  28976. + AVR32_SYNTAX_MIN,
  28977. + AVR32_SYNTAX_MOV3,
  28978. + AVR32_SYNTAX_MOV1,
  28979. + AVR32_SYNTAX_MOV2,
  28980. + AVR32_SYNTAX_MOVEQ1,
  28981. + AVR32_SYNTAX_MOVNE1,
  28982. + AVR32_SYNTAX_MOVCC1,
  28983. + AVR32_SYNTAX_MOVCS1,
  28984. + AVR32_SYNTAX_MOVGE1,
  28985. + AVR32_SYNTAX_MOVLT1,
  28986. + AVR32_SYNTAX_MOVMI1,
  28987. + AVR32_SYNTAX_MOVPL1,
  28988. + AVR32_SYNTAX_MOVLS1,
  28989. + AVR32_SYNTAX_MOVGT1,
  28990. + AVR32_SYNTAX_MOVLE1,
  28991. + AVR32_SYNTAX_MOVHI1,
  28992. + AVR32_SYNTAX_MOVVS1,
  28993. + AVR32_SYNTAX_MOVVC1,
  28994. + AVR32_SYNTAX_MOVQS1,
  28995. + AVR32_SYNTAX_MOVAL1,
  28996. + AVR32_SYNTAX_MOVHS1,
  28997. + AVR32_SYNTAX_MOVLO1,
  28998. + AVR32_SYNTAX_MOVEQ2,
  28999. + AVR32_SYNTAX_MOVNE2,
  29000. + AVR32_SYNTAX_MOVCC2,
  29001. + AVR32_SYNTAX_MOVCS2,
  29002. + AVR32_SYNTAX_MOVGE2,
  29003. + AVR32_SYNTAX_MOVLT2,
  29004. + AVR32_SYNTAX_MOVMI2,
  29005. + AVR32_SYNTAX_MOVPL2,
  29006. + AVR32_SYNTAX_MOVLS2,
  29007. + AVR32_SYNTAX_MOVGT2,
  29008. + AVR32_SYNTAX_MOVLE2,
  29009. + AVR32_SYNTAX_MOVHI2,
  29010. + AVR32_SYNTAX_MOVVS2,
  29011. + AVR32_SYNTAX_MOVVC2,
  29012. + AVR32_SYNTAX_MOVQS2,
  29013. + AVR32_SYNTAX_MOVAL2,
  29014. + AVR32_SYNTAX_MOVHS2,
  29015. + AVR32_SYNTAX_MOVLO2,
  29016. + AVR32_SYNTAX_MTDR,
  29017. + AVR32_SYNTAX_MTSR,
  29018. + AVR32_SYNTAX_MUL1,
  29019. + AVR32_SYNTAX_MUL2,
  29020. + AVR32_SYNTAX_MUL3,
  29021. + AVR32_SYNTAX_MULHH_W,
  29022. + AVR32_SYNTAX_MULNHH_W,
  29023. + AVR32_SYNTAX_MULNWH_D,
  29024. + AVR32_SYNTAX_MULSD,
  29025. + AVR32_SYNTAX_MULSATHH_H,
  29026. + AVR32_SYNTAX_MULSATHH_W,
  29027. + AVR32_SYNTAX_MULSATRNDHH_H,
  29028. + AVR32_SYNTAX_MULSATRNDWH_W,
  29029. + AVR32_SYNTAX_MULSATWH_W,
  29030. + AVR32_SYNTAX_MULU_D,
  29031. + AVR32_SYNTAX_MULWH_D,
  29032. + AVR32_SYNTAX_MUSFR,
  29033. + AVR32_SYNTAX_MUSTR,
  29034. + AVR32_SYNTAX_MVCR_D,
  29035. + AVR32_SYNTAX_MVCR_W,
  29036. + AVR32_SYNTAX_MVRC_D,
  29037. + AVR32_SYNTAX_MVRC_W,
  29038. + AVR32_SYNTAX_NEG,
  29039. + AVR32_SYNTAX_NOP,
  29040. + AVR32_SYNTAX_OR1,
  29041. + AVR32_SYNTAX_OR2,
  29042. + AVR32_SYNTAX_OR3,
  29043. + AVR32_SYNTAX_ORH,
  29044. + AVR32_SYNTAX_ORL,
  29045. + AVR32_SYNTAX_PABS_SB,
  29046. + AVR32_SYNTAX_PABS_SH,
  29047. + AVR32_SYNTAX_PACKSH_SB,
  29048. + AVR32_SYNTAX_PACKSH_UB,
  29049. + AVR32_SYNTAX_PACKW_SH,
  29050. + AVR32_SYNTAX_PADD_B,
  29051. + AVR32_SYNTAX_PADD_H,
  29052. + AVR32_SYNTAX_PADDH_SH,
  29053. + AVR32_SYNTAX_PADDH_UB,
  29054. + AVR32_SYNTAX_PADDS_SB,
  29055. + AVR32_SYNTAX_PADDS_SH,
  29056. + AVR32_SYNTAX_PADDS_UB,
  29057. + AVR32_SYNTAX_PADDS_UH,
  29058. + AVR32_SYNTAX_PADDSUB_H,
  29059. + AVR32_SYNTAX_PADDSUBH_SH,
  29060. + AVR32_SYNTAX_PADDSUBS_SH,
  29061. + AVR32_SYNTAX_PADDSUBS_UH,
  29062. + AVR32_SYNTAX_PADDX_H,
  29063. + AVR32_SYNTAX_PADDXH_SH,
  29064. + AVR32_SYNTAX_PADDXS_SH,
  29065. + AVR32_SYNTAX_PADDXS_UH,
  29066. + AVR32_SYNTAX_PASR_B,
  29067. + AVR32_SYNTAX_PASR_H,
  29068. + AVR32_SYNTAX_PAVG_SH,
  29069. + AVR32_SYNTAX_PAVG_UB,
  29070. + AVR32_SYNTAX_PLSL_B,
  29071. + AVR32_SYNTAX_PLSL_H,
  29072. + AVR32_SYNTAX_PLSR_B,
  29073. + AVR32_SYNTAX_PLSR_H,
  29074. + AVR32_SYNTAX_PMAX_SH,
  29075. + AVR32_SYNTAX_PMAX_UB,
  29076. + AVR32_SYNTAX_PMIN_SH,
  29077. + AVR32_SYNTAX_PMIN_UB,
  29078. + AVR32_SYNTAX_POPJC,
  29079. + AVR32_SYNTAX_POPM,
  29080. + AVR32_SYNTAX_POPM_E,
  29081. + AVR32_SYNTAX_PREF,
  29082. + AVR32_SYNTAX_PSAD,
  29083. + AVR32_SYNTAX_PSUB_B,
  29084. + AVR32_SYNTAX_PSUB_H,
  29085. + AVR32_SYNTAX_PSUBADD_H,
  29086. + AVR32_SYNTAX_PSUBADDH_SH,
  29087. + AVR32_SYNTAX_PSUBADDS_SH,
  29088. + AVR32_SYNTAX_PSUBADDS_UH,
  29089. + AVR32_SYNTAX_PSUBH_SH,
  29090. + AVR32_SYNTAX_PSUBH_UB,
  29091. + AVR32_SYNTAX_PSUBS_SB,
  29092. + AVR32_SYNTAX_PSUBS_SH,
  29093. + AVR32_SYNTAX_PSUBS_UB,
  29094. + AVR32_SYNTAX_PSUBS_UH,
  29095. + AVR32_SYNTAX_PSUBX_H,
  29096. + AVR32_SYNTAX_PSUBXH_SH,
  29097. + AVR32_SYNTAX_PSUBXS_SH,
  29098. + AVR32_SYNTAX_PSUBXS_UH,
  29099. + AVR32_SYNTAX_PUNPCKSB_H,
  29100. + AVR32_SYNTAX_PUNPCKUB_H,
  29101. + AVR32_SYNTAX_PUSHJC,
  29102. + AVR32_SYNTAX_PUSHM,
  29103. + AVR32_SYNTAX_PUSHM_E,
  29104. + AVR32_SYNTAX_RCALL1,
  29105. + AVR32_SYNTAX_RCALL2,
  29106. + AVR32_SYNTAX_RETEQ,
  29107. + AVR32_SYNTAX_RETNE,
  29108. + AVR32_SYNTAX_RETCC,
  29109. + AVR32_SYNTAX_RETCS,
  29110. + AVR32_SYNTAX_RETGE,
  29111. + AVR32_SYNTAX_RETLT,
  29112. + AVR32_SYNTAX_RETMI,
  29113. + AVR32_SYNTAX_RETPL,
  29114. + AVR32_SYNTAX_RETLS,
  29115. + AVR32_SYNTAX_RETGT,
  29116. + AVR32_SYNTAX_RETLE,
  29117. + AVR32_SYNTAX_RETHI,
  29118. + AVR32_SYNTAX_RETVS,
  29119. + AVR32_SYNTAX_RETVC,
  29120. + AVR32_SYNTAX_RETQS,
  29121. + AVR32_SYNTAX_RETAL,
  29122. + AVR32_SYNTAX_RETHS,
  29123. + AVR32_SYNTAX_RETLO,
  29124. + AVR32_SYNTAX_RETD,
  29125. + AVR32_SYNTAX_RETE,
  29126. + AVR32_SYNTAX_RETJ,
  29127. + AVR32_SYNTAX_RETS,
  29128. + AVR32_SYNTAX_RJMP,
  29129. + AVR32_SYNTAX_ROL,
  29130. + AVR32_SYNTAX_ROR,
  29131. + AVR32_SYNTAX_RSUB1,
  29132. + AVR32_SYNTAX_RSUB2,
  29133. + AVR32_SYNTAX_SATADD_H,
  29134. + AVR32_SYNTAX_SATADD_W,
  29135. + AVR32_SYNTAX_SATRNDS,
  29136. + AVR32_SYNTAX_SATRNDU,
  29137. + AVR32_SYNTAX_SATS,
  29138. + AVR32_SYNTAX_SATSUB_H,
  29139. + AVR32_SYNTAX_SATSUB_W1,
  29140. + AVR32_SYNTAX_SATSUB_W2,
  29141. + AVR32_SYNTAX_SATU,
  29142. + AVR32_SYNTAX_SBC,
  29143. + AVR32_SYNTAX_SBR,
  29144. + AVR32_SYNTAX_SCALL,
  29145. + AVR32_SYNTAX_SCR,
  29146. + AVR32_SYNTAX_SLEEP,
  29147. + AVR32_SYNTAX_SREQ,
  29148. + AVR32_SYNTAX_SRNE,
  29149. + AVR32_SYNTAX_SRCC,
  29150. + AVR32_SYNTAX_SRCS,
  29151. + AVR32_SYNTAX_SRGE,
  29152. + AVR32_SYNTAX_SRLT,
  29153. + AVR32_SYNTAX_SRMI,
  29154. + AVR32_SYNTAX_SRPL,
  29155. + AVR32_SYNTAX_SRLS,
  29156. + AVR32_SYNTAX_SRGT,
  29157. + AVR32_SYNTAX_SRLE,
  29158. + AVR32_SYNTAX_SRHI,
  29159. + AVR32_SYNTAX_SRVS,
  29160. + AVR32_SYNTAX_SRVC,
  29161. + AVR32_SYNTAX_SRQS,
  29162. + AVR32_SYNTAX_SRAL,
  29163. + AVR32_SYNTAX_SRHS,
  29164. + AVR32_SYNTAX_SRLO,
  29165. + AVR32_SYNTAX_SSRF,
  29166. + AVR32_SYNTAX_ST_B1,
  29167. + AVR32_SYNTAX_ST_B2,
  29168. + AVR32_SYNTAX_ST_B5,
  29169. + AVR32_SYNTAX_ST_B3,
  29170. + AVR32_SYNTAX_ST_B4,
  29171. + AVR32_SYNTAX_ST_D1,
  29172. + AVR32_SYNTAX_ST_D2,
  29173. + AVR32_SYNTAX_ST_D3,
  29174. + AVR32_SYNTAX_ST_D5,
  29175. + AVR32_SYNTAX_ST_D4,
  29176. + AVR32_SYNTAX_ST_H1,
  29177. + AVR32_SYNTAX_ST_H2,
  29178. + AVR32_SYNTAX_ST_H5,
  29179. + AVR32_SYNTAX_ST_H3,
  29180. + AVR32_SYNTAX_ST_H4,
  29181. + AVR32_SYNTAX_ST_W1,
  29182. + AVR32_SYNTAX_ST_W2,
  29183. + AVR32_SYNTAX_ST_W5,
  29184. + AVR32_SYNTAX_ST_W3,
  29185. + AVR32_SYNTAX_ST_W4,
  29186. + AVR32_SYNTAX_STC_D1,
  29187. + AVR32_SYNTAX_STC_D2,
  29188. + AVR32_SYNTAX_STC_D3,
  29189. + AVR32_SYNTAX_STC_W1,
  29190. + AVR32_SYNTAX_STC_W2,
  29191. + AVR32_SYNTAX_STC_W3,
  29192. + AVR32_SYNTAX_STC0_D,
  29193. + AVR32_SYNTAX_STC0_W,
  29194. + AVR32_SYNTAX_STCM_D,
  29195. + AVR32_SYNTAX_STCM_D_PU,
  29196. + AVR32_SYNTAX_STCM_W,
  29197. + AVR32_SYNTAX_STCM_W_PU,
  29198. + AVR32_SYNTAX_STCOND,
  29199. + AVR32_SYNTAX_STDSP,
  29200. + AVR32_SYNTAX_STHH_W2,
  29201. + AVR32_SYNTAX_STHH_W1,
  29202. + AVR32_SYNTAX_STM,
  29203. + AVR32_SYNTAX_STM_PU,
  29204. + AVR32_SYNTAX_STMTS,
  29205. + AVR32_SYNTAX_STMTS_PU,
  29206. + AVR32_SYNTAX_STSWP_H,
  29207. + AVR32_SYNTAX_STSWP_W,
  29208. + AVR32_SYNTAX_SUB1,
  29209. + AVR32_SYNTAX_SUB2,
  29210. + AVR32_SYNTAX_SUB5,
  29211. + AVR32_SYNTAX_SUB3_SP,
  29212. + AVR32_SYNTAX_SUB3,
  29213. + AVR32_SYNTAX_SUB4,
  29214. + AVR32_SYNTAX_SUBEQ,
  29215. + AVR32_SYNTAX_SUBNE,
  29216. + AVR32_SYNTAX_SUBCC,
  29217. + AVR32_SYNTAX_SUBCS,
  29218. + AVR32_SYNTAX_SUBGE,
  29219. + AVR32_SYNTAX_SUBLT,
  29220. + AVR32_SYNTAX_SUBMI,
  29221. + AVR32_SYNTAX_SUBPL,
  29222. + AVR32_SYNTAX_SUBLS,
  29223. + AVR32_SYNTAX_SUBGT,
  29224. + AVR32_SYNTAX_SUBLE,
  29225. + AVR32_SYNTAX_SUBHI,
  29226. + AVR32_SYNTAX_SUBVS,
  29227. + AVR32_SYNTAX_SUBVC,
  29228. + AVR32_SYNTAX_SUBQS,
  29229. + AVR32_SYNTAX_SUBAL,
  29230. + AVR32_SYNTAX_SUBHS,
  29231. + AVR32_SYNTAX_SUBLO,
  29232. + AVR32_SYNTAX_SUBFEQ,
  29233. + AVR32_SYNTAX_SUBFNE,
  29234. + AVR32_SYNTAX_SUBFCC,
  29235. + AVR32_SYNTAX_SUBFCS,
  29236. + AVR32_SYNTAX_SUBFGE,
  29237. + AVR32_SYNTAX_SUBFLT,
  29238. + AVR32_SYNTAX_SUBFMI,
  29239. + AVR32_SYNTAX_SUBFPL,
  29240. + AVR32_SYNTAX_SUBFLS,
  29241. + AVR32_SYNTAX_SUBFGT,
  29242. + AVR32_SYNTAX_SUBFLE,
  29243. + AVR32_SYNTAX_SUBFHI,
  29244. + AVR32_SYNTAX_SUBFVS,
  29245. + AVR32_SYNTAX_SUBFVC,
  29246. + AVR32_SYNTAX_SUBFQS,
  29247. + AVR32_SYNTAX_SUBFAL,
  29248. + AVR32_SYNTAX_SUBFHS,
  29249. + AVR32_SYNTAX_SUBFLO,
  29250. + AVR32_SYNTAX_SUBHH_W,
  29251. + AVR32_SYNTAX_SWAP_B,
  29252. + AVR32_SYNTAX_SWAP_BH,
  29253. + AVR32_SYNTAX_SWAP_H,
  29254. + AVR32_SYNTAX_SYNC,
  29255. + AVR32_SYNTAX_TLBR,
  29256. + AVR32_SYNTAX_TLBS,
  29257. + AVR32_SYNTAX_TLBW,
  29258. + AVR32_SYNTAX_TNBZ,
  29259. + AVR32_SYNTAX_TST,
  29260. + AVR32_SYNTAX_XCHG,
  29261. + AVR32_SYNTAX_MEMC,
  29262. + AVR32_SYNTAX_MEMS,
  29263. + AVR32_SYNTAX_MEMT,
  29264. + AVR32_SYNTAX_FMAC_S,
  29265. + AVR32_SYNTAX_FNMAC_S,
  29266. + AVR32_SYNTAX_FMSC_S,
  29267. + AVR32_SYNTAX_FNMSC_S,
  29268. + AVR32_SYNTAX_FMUL_S,
  29269. + AVR32_SYNTAX_FNMUL_S,
  29270. + AVR32_SYNTAX_FADD_S,
  29271. + AVR32_SYNTAX_FSUB_S,
  29272. + AVR32_SYNTAX_FCASTRS_SW,
  29273. + AVR32_SYNTAX_FCASTRS_UW,
  29274. + AVR32_SYNTAX_FCASTSW_S,
  29275. + AVR32_SYNTAX_FCASTUW_S,
  29276. + AVR32_SYNTAX_FCMP_S,
  29277. + AVR32_SYNTAX_FCHK_S,
  29278. + AVR32_SYNTAX_FRCPA_S,
  29279. + AVR32_SYNTAX_FRSQRTA_S,
  29280. + AVR32_SYNTAX_LDA_W,
  29281. + AVR32_SYNTAX_CALL,
  29282. + AVR32_SYNTAX_PICOSVMAC0,
  29283. + AVR32_SYNTAX_PICOSVMAC1,
  29284. + AVR32_SYNTAX_PICOSVMAC2,
  29285. + AVR32_SYNTAX_PICOSVMAC3,
  29286. + AVR32_SYNTAX_PICOSVMUL0,
  29287. + AVR32_SYNTAX_PICOSVMUL1,
  29288. + AVR32_SYNTAX_PICOSVMUL2,
  29289. + AVR32_SYNTAX_PICOSVMUL3,
  29290. + AVR32_SYNTAX_PICOVMAC0,
  29291. + AVR32_SYNTAX_PICOVMAC1,
  29292. + AVR32_SYNTAX_PICOVMAC2,
  29293. + AVR32_SYNTAX_PICOVMAC3,
  29294. + AVR32_SYNTAX_PICOVMUL0,
  29295. + AVR32_SYNTAX_PICOVMUL1,
  29296. + AVR32_SYNTAX_PICOVMUL2,
  29297. + AVR32_SYNTAX_PICOVMUL3,
  29298. + AVR32_SYNTAX_PICOLD_D2,
  29299. + AVR32_SYNTAX_PICOLD_D3,
  29300. + AVR32_SYNTAX_PICOLD_D1,
  29301. + AVR32_SYNTAX_PICOLD_W2,
  29302. + AVR32_SYNTAX_PICOLD_W3,
  29303. + AVR32_SYNTAX_PICOLD_W1,
  29304. + AVR32_SYNTAX_PICOLDM_D,
  29305. + AVR32_SYNTAX_PICOLDM_D_PU,
  29306. + AVR32_SYNTAX_PICOLDM_W,
  29307. + AVR32_SYNTAX_PICOLDM_W_PU,
  29308. + AVR32_SYNTAX_PICOMV_D1,
  29309. + AVR32_SYNTAX_PICOMV_D2,
  29310. + AVR32_SYNTAX_PICOMV_W1,
  29311. + AVR32_SYNTAX_PICOMV_W2,
  29312. + AVR32_SYNTAX_PICOST_D2,
  29313. + AVR32_SYNTAX_PICOST_D3,
  29314. + AVR32_SYNTAX_PICOST_D1,
  29315. + AVR32_SYNTAX_PICOST_W2,
  29316. + AVR32_SYNTAX_PICOST_W3,
  29317. + AVR32_SYNTAX_PICOST_W1,
  29318. + AVR32_SYNTAX_PICOSTM_D,
  29319. + AVR32_SYNTAX_PICOSTM_D_PU,
  29320. + AVR32_SYNTAX_PICOSTM_W,
  29321. + AVR32_SYNTAX_PICOSTM_W_PU,
  29322. + AVR32_SYNTAX_RSUBEQ,
  29323. + AVR32_SYNTAX_RSUBNE,
  29324. + AVR32_SYNTAX_RSUBCC,
  29325. + AVR32_SYNTAX_RSUBCS,
  29326. + AVR32_SYNTAX_RSUBGE,
  29327. + AVR32_SYNTAX_RSUBLT,
  29328. + AVR32_SYNTAX_RSUBMI,
  29329. + AVR32_SYNTAX_RSUBPL,
  29330. + AVR32_SYNTAX_RSUBLS,
  29331. + AVR32_SYNTAX_RSUBGT,
  29332. + AVR32_SYNTAX_RSUBLE,
  29333. + AVR32_SYNTAX_RSUBHI,
  29334. + AVR32_SYNTAX_RSUBVS,
  29335. + AVR32_SYNTAX_RSUBVC,
  29336. + AVR32_SYNTAX_RSUBQS,
  29337. + AVR32_SYNTAX_RSUBAL,
  29338. + AVR32_SYNTAX_RSUBHS,
  29339. + AVR32_SYNTAX_RSUBLO,
  29340. + AVR32_SYNTAX_ADDEQ,
  29341. + AVR32_SYNTAX_ADDNE,
  29342. + AVR32_SYNTAX_ADDCC,
  29343. + AVR32_SYNTAX_ADDCS,
  29344. + AVR32_SYNTAX_ADDGE,
  29345. + AVR32_SYNTAX_ADDLT,
  29346. + AVR32_SYNTAX_ADDMI,
  29347. + AVR32_SYNTAX_ADDPL,
  29348. + AVR32_SYNTAX_ADDLS,
  29349. + AVR32_SYNTAX_ADDGT,
  29350. + AVR32_SYNTAX_ADDLE,
  29351. + AVR32_SYNTAX_ADDHI,
  29352. + AVR32_SYNTAX_ADDVS,
  29353. + AVR32_SYNTAX_ADDVC,
  29354. + AVR32_SYNTAX_ADDQS,
  29355. + AVR32_SYNTAX_ADDAL,
  29356. + AVR32_SYNTAX_ADDHS,
  29357. + AVR32_SYNTAX_ADDLO,
  29358. + AVR32_SYNTAX_SUB2EQ,
  29359. + AVR32_SYNTAX_SUB2NE,
  29360. + AVR32_SYNTAX_SUB2CC,
  29361. + AVR32_SYNTAX_SUB2CS,
  29362. + AVR32_SYNTAX_SUB2GE,
  29363. + AVR32_SYNTAX_SUB2LT,
  29364. + AVR32_SYNTAX_SUB2MI,
  29365. + AVR32_SYNTAX_SUB2PL,
  29366. + AVR32_SYNTAX_SUB2LS,
  29367. + AVR32_SYNTAX_SUB2GT,
  29368. + AVR32_SYNTAX_SUB2LE,
  29369. + AVR32_SYNTAX_SUB2HI,
  29370. + AVR32_SYNTAX_SUB2VS,
  29371. + AVR32_SYNTAX_SUB2VC,
  29372. + AVR32_SYNTAX_SUB2QS,
  29373. + AVR32_SYNTAX_SUB2AL,
  29374. + AVR32_SYNTAX_SUB2HS,
  29375. + AVR32_SYNTAX_SUB2LO,
  29376. + AVR32_SYNTAX_ANDEQ,
  29377. + AVR32_SYNTAX_ANDNE,
  29378. + AVR32_SYNTAX_ANDCC,
  29379. + AVR32_SYNTAX_ANDCS,
  29380. + AVR32_SYNTAX_ANDGE,
  29381. + AVR32_SYNTAX_ANDLT,
  29382. + AVR32_SYNTAX_ANDMI,
  29383. + AVR32_SYNTAX_ANDPL,
  29384. + AVR32_SYNTAX_ANDLS,
  29385. + AVR32_SYNTAX_ANDGT,
  29386. + AVR32_SYNTAX_ANDLE,
  29387. + AVR32_SYNTAX_ANDHI,
  29388. + AVR32_SYNTAX_ANDVS,
  29389. + AVR32_SYNTAX_ANDVC,
  29390. + AVR32_SYNTAX_ANDQS,
  29391. + AVR32_SYNTAX_ANDAL,
  29392. + AVR32_SYNTAX_ANDHS,
  29393. + AVR32_SYNTAX_ANDLO,
  29394. + AVR32_SYNTAX_OREQ,
  29395. + AVR32_SYNTAX_ORNE,
  29396. + AVR32_SYNTAX_ORCC,
  29397. + AVR32_SYNTAX_ORCS,
  29398. + AVR32_SYNTAX_ORGE,
  29399. + AVR32_SYNTAX_ORLT,
  29400. + AVR32_SYNTAX_ORMI,
  29401. + AVR32_SYNTAX_ORPL,
  29402. + AVR32_SYNTAX_ORLS,
  29403. + AVR32_SYNTAX_ORGT,
  29404. + AVR32_SYNTAX_ORLE,
  29405. + AVR32_SYNTAX_ORHI,
  29406. + AVR32_SYNTAX_ORVS,
  29407. + AVR32_SYNTAX_ORVC,
  29408. + AVR32_SYNTAX_ORQS,
  29409. + AVR32_SYNTAX_ORAL,
  29410. + AVR32_SYNTAX_ORHS,
  29411. + AVR32_SYNTAX_ORLO,
  29412. + AVR32_SYNTAX_EOREQ,
  29413. + AVR32_SYNTAX_EORNE,
  29414. + AVR32_SYNTAX_EORCC,
  29415. + AVR32_SYNTAX_EORCS,
  29416. + AVR32_SYNTAX_EORGE,
  29417. + AVR32_SYNTAX_EORLT,
  29418. + AVR32_SYNTAX_EORMI,
  29419. + AVR32_SYNTAX_EORPL,
  29420. + AVR32_SYNTAX_EORLS,
  29421. + AVR32_SYNTAX_EORGT,
  29422. + AVR32_SYNTAX_EORLE,
  29423. + AVR32_SYNTAX_EORHI,
  29424. + AVR32_SYNTAX_EORVS,
  29425. + AVR32_SYNTAX_EORVC,
  29426. + AVR32_SYNTAX_EORQS,
  29427. + AVR32_SYNTAX_EORAL,
  29428. + AVR32_SYNTAX_EORHS,
  29429. + AVR32_SYNTAX_EORLO,
  29430. + AVR32_SYNTAX_LD_WEQ,
  29431. + AVR32_SYNTAX_LD_WNE,
  29432. + AVR32_SYNTAX_LD_WCC,
  29433. + AVR32_SYNTAX_LD_WCS,
  29434. + AVR32_SYNTAX_LD_WGE,
  29435. + AVR32_SYNTAX_LD_WLT,
  29436. + AVR32_SYNTAX_LD_WMI,
  29437. + AVR32_SYNTAX_LD_WPL,
  29438. + AVR32_SYNTAX_LD_WLS,
  29439. + AVR32_SYNTAX_LD_WGT,
  29440. + AVR32_SYNTAX_LD_WLE,
  29441. + AVR32_SYNTAX_LD_WHI,
  29442. + AVR32_SYNTAX_LD_WVS,
  29443. + AVR32_SYNTAX_LD_WVC,
  29444. + AVR32_SYNTAX_LD_WQS,
  29445. + AVR32_SYNTAX_LD_WAL,
  29446. + AVR32_SYNTAX_LD_WHS,
  29447. + AVR32_SYNTAX_LD_WLO,
  29448. + AVR32_SYNTAX_LD_SHEQ,
  29449. + AVR32_SYNTAX_LD_SHNE,
  29450. + AVR32_SYNTAX_LD_SHCC,
  29451. + AVR32_SYNTAX_LD_SHCS,
  29452. + AVR32_SYNTAX_LD_SHGE,
  29453. + AVR32_SYNTAX_LD_SHLT,
  29454. + AVR32_SYNTAX_LD_SHMI,
  29455. + AVR32_SYNTAX_LD_SHPL,
  29456. + AVR32_SYNTAX_LD_SHLS,
  29457. + AVR32_SYNTAX_LD_SHGT,
  29458. + AVR32_SYNTAX_LD_SHLE,
  29459. + AVR32_SYNTAX_LD_SHHI,
  29460. + AVR32_SYNTAX_LD_SHVS,
  29461. + AVR32_SYNTAX_LD_SHVC,
  29462. + AVR32_SYNTAX_LD_SHQS,
  29463. + AVR32_SYNTAX_LD_SHAL,
  29464. + AVR32_SYNTAX_LD_SHHS,
  29465. + AVR32_SYNTAX_LD_SHLO,
  29466. + AVR32_SYNTAX_LD_UHEQ,
  29467. + AVR32_SYNTAX_LD_UHNE,
  29468. + AVR32_SYNTAX_LD_UHCC,
  29469. + AVR32_SYNTAX_LD_UHCS,
  29470. + AVR32_SYNTAX_LD_UHGE,
  29471. + AVR32_SYNTAX_LD_UHLT,
  29472. + AVR32_SYNTAX_LD_UHMI,
  29473. + AVR32_SYNTAX_LD_UHPL,
  29474. + AVR32_SYNTAX_LD_UHLS,
  29475. + AVR32_SYNTAX_LD_UHGT,
  29476. + AVR32_SYNTAX_LD_UHLE,
  29477. + AVR32_SYNTAX_LD_UHHI,
  29478. + AVR32_SYNTAX_LD_UHVS,
  29479. + AVR32_SYNTAX_LD_UHVC,
  29480. + AVR32_SYNTAX_LD_UHQS,
  29481. + AVR32_SYNTAX_LD_UHAL,
  29482. + AVR32_SYNTAX_LD_UHHS,
  29483. + AVR32_SYNTAX_LD_UHLO,
  29484. + AVR32_SYNTAX_LD_SBEQ,
  29485. + AVR32_SYNTAX_LD_SBNE,
  29486. + AVR32_SYNTAX_LD_SBCC,
  29487. + AVR32_SYNTAX_LD_SBCS,
  29488. + AVR32_SYNTAX_LD_SBGE,
  29489. + AVR32_SYNTAX_LD_SBLT,
  29490. + AVR32_SYNTAX_LD_SBMI,
  29491. + AVR32_SYNTAX_LD_SBPL,
  29492. + AVR32_SYNTAX_LD_SBLS,
  29493. + AVR32_SYNTAX_LD_SBGT,
  29494. + AVR32_SYNTAX_LD_SBLE,
  29495. + AVR32_SYNTAX_LD_SBHI,
  29496. + AVR32_SYNTAX_LD_SBVS,
  29497. + AVR32_SYNTAX_LD_SBVC,
  29498. + AVR32_SYNTAX_LD_SBQS,
  29499. + AVR32_SYNTAX_LD_SBAL,
  29500. + AVR32_SYNTAX_LD_SBHS,
  29501. + AVR32_SYNTAX_LD_SBLO,
  29502. + AVR32_SYNTAX_LD_UBEQ,
  29503. + AVR32_SYNTAX_LD_UBNE,
  29504. + AVR32_SYNTAX_LD_UBCC,
  29505. + AVR32_SYNTAX_LD_UBCS,
  29506. + AVR32_SYNTAX_LD_UBGE,
  29507. + AVR32_SYNTAX_LD_UBLT,
  29508. + AVR32_SYNTAX_LD_UBMI,
  29509. + AVR32_SYNTAX_LD_UBPL,
  29510. + AVR32_SYNTAX_LD_UBLS,
  29511. + AVR32_SYNTAX_LD_UBGT,
  29512. + AVR32_SYNTAX_LD_UBLE,
  29513. + AVR32_SYNTAX_LD_UBHI,
  29514. + AVR32_SYNTAX_LD_UBVS,
  29515. + AVR32_SYNTAX_LD_UBVC,
  29516. + AVR32_SYNTAX_LD_UBQS,
  29517. + AVR32_SYNTAX_LD_UBAL,
  29518. + AVR32_SYNTAX_LD_UBHS,
  29519. + AVR32_SYNTAX_LD_UBLO,
  29520. + AVR32_SYNTAX_ST_WEQ,
  29521. + AVR32_SYNTAX_ST_WNE,
  29522. + AVR32_SYNTAX_ST_WCC,
  29523. + AVR32_SYNTAX_ST_WCS,
  29524. + AVR32_SYNTAX_ST_WGE,
  29525. + AVR32_SYNTAX_ST_WLT,
  29526. + AVR32_SYNTAX_ST_WMI,
  29527. + AVR32_SYNTAX_ST_WPL,
  29528. + AVR32_SYNTAX_ST_WLS,
  29529. + AVR32_SYNTAX_ST_WGT,
  29530. + AVR32_SYNTAX_ST_WLE,
  29531. + AVR32_SYNTAX_ST_WHI,
  29532. + AVR32_SYNTAX_ST_WVS,
  29533. + AVR32_SYNTAX_ST_WVC,
  29534. + AVR32_SYNTAX_ST_WQS,
  29535. + AVR32_SYNTAX_ST_WAL,
  29536. + AVR32_SYNTAX_ST_WHS,
  29537. + AVR32_SYNTAX_ST_WLO,
  29538. + AVR32_SYNTAX_ST_HEQ,
  29539. + AVR32_SYNTAX_ST_HNE,
  29540. + AVR32_SYNTAX_ST_HCC,
  29541. + AVR32_SYNTAX_ST_HCS,
  29542. + AVR32_SYNTAX_ST_HGE,
  29543. + AVR32_SYNTAX_ST_HLT,
  29544. + AVR32_SYNTAX_ST_HMI,
  29545. + AVR32_SYNTAX_ST_HPL,
  29546. + AVR32_SYNTAX_ST_HLS,
  29547. + AVR32_SYNTAX_ST_HGT,
  29548. + AVR32_SYNTAX_ST_HLE,
  29549. + AVR32_SYNTAX_ST_HHI,
  29550. + AVR32_SYNTAX_ST_HVS,
  29551. + AVR32_SYNTAX_ST_HVC,
  29552. + AVR32_SYNTAX_ST_HQS,
  29553. + AVR32_SYNTAX_ST_HAL,
  29554. + AVR32_SYNTAX_ST_HHS,
  29555. + AVR32_SYNTAX_ST_HLO,
  29556. + AVR32_SYNTAX_ST_BEQ,
  29557. + AVR32_SYNTAX_ST_BNE,
  29558. + AVR32_SYNTAX_ST_BCC,
  29559. + AVR32_SYNTAX_ST_BCS,
  29560. + AVR32_SYNTAX_ST_BGE,
  29561. + AVR32_SYNTAX_ST_BLT,
  29562. + AVR32_SYNTAX_ST_BMI,
  29563. + AVR32_SYNTAX_ST_BPL,
  29564. + AVR32_SYNTAX_ST_BLS,
  29565. + AVR32_SYNTAX_ST_BGT,
  29566. + AVR32_SYNTAX_ST_BLE,
  29567. + AVR32_SYNTAX_ST_BHI,
  29568. + AVR32_SYNTAX_ST_BVS,
  29569. + AVR32_SYNTAX_ST_BVC,
  29570. + AVR32_SYNTAX_ST_BQS,
  29571. + AVR32_SYNTAX_ST_BAL,
  29572. + AVR32_SYNTAX_ST_BHS,
  29573. + AVR32_SYNTAX_ST_BLO,
  29574. + AVR32_SYNTAX_MOVH,
  29575. + AVR32_SYNTAX__END_
  29576. +};
  29577. +#define AVR32_NR_SYNTAX AVR32_SYNTAX__END_
  29578. +
  29579. +enum avr32_alias_type
  29580. + {
  29581. + AVR32_ALIAS_PICOSVMAC0,
  29582. + AVR32_ALIAS_PICOSVMAC1,
  29583. + AVR32_ALIAS_PICOSVMAC2,
  29584. + AVR32_ALIAS_PICOSVMAC3,
  29585. + AVR32_ALIAS_PICOSVMUL0,
  29586. + AVR32_ALIAS_PICOSVMUL1,
  29587. + AVR32_ALIAS_PICOSVMUL2,
  29588. + AVR32_ALIAS_PICOSVMUL3,
  29589. + AVR32_ALIAS_PICOVMAC0,
  29590. + AVR32_ALIAS_PICOVMAC1,
  29591. + AVR32_ALIAS_PICOVMAC2,
  29592. + AVR32_ALIAS_PICOVMAC3,
  29593. + AVR32_ALIAS_PICOVMUL0,
  29594. + AVR32_ALIAS_PICOVMUL1,
  29595. + AVR32_ALIAS_PICOVMUL2,
  29596. + AVR32_ALIAS_PICOVMUL3,
  29597. + AVR32_ALIAS_PICOLD_D1,
  29598. + AVR32_ALIAS_PICOLD_D2,
  29599. + AVR32_ALIAS_PICOLD_D3,
  29600. + AVR32_ALIAS_PICOLD_W1,
  29601. + AVR32_ALIAS_PICOLD_W2,
  29602. + AVR32_ALIAS_PICOLD_W3,
  29603. + AVR32_ALIAS_PICOLDM_D,
  29604. + AVR32_ALIAS_PICOLDM_D_PU,
  29605. + AVR32_ALIAS_PICOLDM_W,
  29606. + AVR32_ALIAS_PICOLDM_W_PU,
  29607. + AVR32_ALIAS_PICOMV_D1,
  29608. + AVR32_ALIAS_PICOMV_D2,
  29609. + AVR32_ALIAS_PICOMV_W1,
  29610. + AVR32_ALIAS_PICOMV_W2,
  29611. + AVR32_ALIAS_PICOST_D1,
  29612. + AVR32_ALIAS_PICOST_D2,
  29613. + AVR32_ALIAS_PICOST_D3,
  29614. + AVR32_ALIAS_PICOST_W1,
  29615. + AVR32_ALIAS_PICOST_W2,
  29616. + AVR32_ALIAS_PICOST_W3,
  29617. + AVR32_ALIAS_PICOSTM_D,
  29618. + AVR32_ALIAS_PICOSTM_D_PU,
  29619. + AVR32_ALIAS_PICOSTM_W,
  29620. + AVR32_ALIAS_PICOSTM_W_PU,
  29621. + AVR32_ALIAS__END_
  29622. + };
  29623. +#define AVR32_NR_ALIAS AVR32_ALIAS__END_
  29624. +
  29625. +enum avr32_mnemonic_type
  29626. +{
  29627. + AVR32_MNEMONIC_ABS,
  29628. + AVR32_MNEMONIC_ACALL,
  29629. + AVR32_MNEMONIC_ACR,
  29630. + AVR32_MNEMONIC_ADC,
  29631. + AVR32_MNEMONIC_ADD,
  29632. + AVR32_MNEMONIC_ADDABS,
  29633. + AVR32_MNEMONIC_ADDHH_W,
  29634. + AVR32_MNEMONIC_AND,
  29635. + AVR32_MNEMONIC_ANDH,
  29636. + AVR32_MNEMONIC_ANDL,
  29637. + AVR32_MNEMONIC_ANDN,
  29638. + AVR32_MNEMONIC_ASR,
  29639. + AVR32_MNEMONIC_BFEXTS,
  29640. + AVR32_MNEMONIC_BFEXTU,
  29641. + AVR32_MNEMONIC_BFINS,
  29642. + AVR32_MNEMONIC_BLD,
  29643. + AVR32_MNEMONIC_BREQ,
  29644. + AVR32_MNEMONIC_BRNE,
  29645. + AVR32_MNEMONIC_BRCC,
  29646. + AVR32_MNEMONIC_BRCS,
  29647. + AVR32_MNEMONIC_BRGE,
  29648. + AVR32_MNEMONIC_BRLT,
  29649. + AVR32_MNEMONIC_BRMI,
  29650. + AVR32_MNEMONIC_BRPL,
  29651. + AVR32_MNEMONIC_BRHS,
  29652. + AVR32_MNEMONIC_BRLO,
  29653. + AVR32_MNEMONIC_BRLS,
  29654. + AVR32_MNEMONIC_BRGT,
  29655. + AVR32_MNEMONIC_BRLE,
  29656. + AVR32_MNEMONIC_BRHI,
  29657. + AVR32_MNEMONIC_BRVS,
  29658. + AVR32_MNEMONIC_BRVC,
  29659. + AVR32_MNEMONIC_BRQS,
  29660. + AVR32_MNEMONIC_BRAL,
  29661. + AVR32_MNEMONIC_BREAKPOINT,
  29662. + AVR32_MNEMONIC_BREV,
  29663. + AVR32_MNEMONIC_BST,
  29664. + AVR32_MNEMONIC_CACHE,
  29665. + AVR32_MNEMONIC_CASTS_B,
  29666. + AVR32_MNEMONIC_CASTS_H,
  29667. + AVR32_MNEMONIC_CASTU_B,
  29668. + AVR32_MNEMONIC_CASTU_H,
  29669. + AVR32_MNEMONIC_CBR,
  29670. + AVR32_MNEMONIC_CLZ,
  29671. + AVR32_MNEMONIC_COM,
  29672. + AVR32_MNEMONIC_COP,
  29673. + AVR32_MNEMONIC_CP_B,
  29674. + AVR32_MNEMONIC_CP_H,
  29675. + AVR32_MNEMONIC_CP_W,
  29676. + AVR32_MNEMONIC_CP,
  29677. + AVR32_MNEMONIC_CPC,
  29678. + AVR32_MNEMONIC_CSRF,
  29679. + AVR32_MNEMONIC_CSRFCZ,
  29680. + AVR32_MNEMONIC_DIVS,
  29681. + AVR32_MNEMONIC_DIVU,
  29682. + AVR32_MNEMONIC_EOR,
  29683. + AVR32_MNEMONIC_EORL,
  29684. + AVR32_MNEMONIC_EORH,
  29685. + AVR32_MNEMONIC_FRS,
  29686. + AVR32_MNEMONIC_SSCALL,
  29687. + AVR32_MNEMONIC_RETSS,
  29688. + AVR32_MNEMONIC_ICALL,
  29689. + AVR32_MNEMONIC_INCJOSP,
  29690. + AVR32_MNEMONIC_LD_D,
  29691. + AVR32_MNEMONIC_LD_SB,
  29692. + AVR32_MNEMONIC_LD_UB,
  29693. + AVR32_MNEMONIC_LD_SH,
  29694. + AVR32_MNEMONIC_LD_UH,
  29695. + AVR32_MNEMONIC_LD_W,
  29696. + AVR32_MNEMONIC_LDC_D,
  29697. + AVR32_MNEMONIC_LDC_W,
  29698. + AVR32_MNEMONIC_LDC0_D,
  29699. + AVR32_MNEMONIC_LDC0_W,
  29700. + AVR32_MNEMONIC_LDCM_D,
  29701. + AVR32_MNEMONIC_LDCM_W,
  29702. + AVR32_MNEMONIC_LDDPC,
  29703. + AVR32_MNEMONIC_LDDSP,
  29704. + AVR32_MNEMONIC_LDINS_B,
  29705. + AVR32_MNEMONIC_LDINS_H,
  29706. + AVR32_MNEMONIC_LDM,
  29707. + AVR32_MNEMONIC_LDMTS,
  29708. + AVR32_MNEMONIC_LDSWP_SH,
  29709. + AVR32_MNEMONIC_LDSWP_UH,
  29710. + AVR32_MNEMONIC_LDSWP_W,
  29711. + AVR32_MNEMONIC_LSL,
  29712. + AVR32_MNEMONIC_LSR,
  29713. + AVR32_MNEMONIC_MAC,
  29714. + AVR32_MNEMONIC_MACHH_D,
  29715. + AVR32_MNEMONIC_MACHH_W,
  29716. + AVR32_MNEMONIC_MACS_D,
  29717. + AVR32_MNEMONIC_MACSATHH_W,
  29718. + AVR32_MNEMONIC_MACU_D,
  29719. + AVR32_MNEMONIC_MACWH_D,
  29720. + AVR32_MNEMONIC_MAX,
  29721. + AVR32_MNEMONIC_MCALL,
  29722. + AVR32_MNEMONIC_MFDR,
  29723. + AVR32_MNEMONIC_MFSR,
  29724. + AVR32_MNEMONIC_MIN,
  29725. + AVR32_MNEMONIC_MOV,
  29726. + AVR32_MNEMONIC_MOVEQ,
  29727. + AVR32_MNEMONIC_MOVNE,
  29728. + AVR32_MNEMONIC_MOVCC,
  29729. + AVR32_MNEMONIC_MOVCS,
  29730. + AVR32_MNEMONIC_MOVGE,
  29731. + AVR32_MNEMONIC_MOVLT,
  29732. + AVR32_MNEMONIC_MOVMI,
  29733. + AVR32_MNEMONIC_MOVPL,
  29734. + AVR32_MNEMONIC_MOVLS,
  29735. + AVR32_MNEMONIC_MOVGT,
  29736. + AVR32_MNEMONIC_MOVLE,
  29737. + AVR32_MNEMONIC_MOVHI,
  29738. + AVR32_MNEMONIC_MOVVS,
  29739. + AVR32_MNEMONIC_MOVVC,
  29740. + AVR32_MNEMONIC_MOVQS,
  29741. + AVR32_MNEMONIC_MOVAL,
  29742. + AVR32_MNEMONIC_MOVHS,
  29743. + AVR32_MNEMONIC_MOVLO,
  29744. + AVR32_MNEMONIC_MTDR,
  29745. + AVR32_MNEMONIC_MTSR,
  29746. + AVR32_MNEMONIC_MUL,
  29747. + AVR32_MNEMONIC_MULHH_W,
  29748. + AVR32_MNEMONIC_MULNHH_W,
  29749. + AVR32_MNEMONIC_MULNWH_D,
  29750. + AVR32_MNEMONIC_MULS_D,
  29751. + AVR32_MNEMONIC_MULSATHH_H,
  29752. + AVR32_MNEMONIC_MULSATHH_W,
  29753. + AVR32_MNEMONIC_MULSATRNDHH_H,
  29754. + AVR32_MNEMONIC_MULSATRNDWH_W,
  29755. + AVR32_MNEMONIC_MULSATWH_W,
  29756. + AVR32_MNEMONIC_MULU_D,
  29757. + AVR32_MNEMONIC_MULWH_D,
  29758. + AVR32_MNEMONIC_MUSFR,
  29759. + AVR32_MNEMONIC_MUSTR,
  29760. + AVR32_MNEMONIC_MVCR_D,
  29761. + AVR32_MNEMONIC_MVCR_W,
  29762. + AVR32_MNEMONIC_MVRC_D,
  29763. + AVR32_MNEMONIC_MVRC_W,
  29764. + AVR32_MNEMONIC_NEG,
  29765. + AVR32_MNEMONIC_NOP,
  29766. + AVR32_MNEMONIC_OR,
  29767. + AVR32_MNEMONIC_ORH,
  29768. + AVR32_MNEMONIC_ORL,
  29769. + AVR32_MNEMONIC_PABS_SB,
  29770. + AVR32_MNEMONIC_PABS_SH,
  29771. + AVR32_MNEMONIC_PACKSH_SB,
  29772. + AVR32_MNEMONIC_PACKSH_UB,
  29773. + AVR32_MNEMONIC_PACKW_SH,
  29774. + AVR32_MNEMONIC_PADD_B,
  29775. + AVR32_MNEMONIC_PADD_H,
  29776. + AVR32_MNEMONIC_PADDH_SH,
  29777. + AVR32_MNEMONIC_PADDH_UB,
  29778. + AVR32_MNEMONIC_PADDS_SB,
  29779. + AVR32_MNEMONIC_PADDS_SH,
  29780. + AVR32_MNEMONIC_PADDS_UB,
  29781. + AVR32_MNEMONIC_PADDS_UH,
  29782. + AVR32_MNEMONIC_PADDSUB_H,
  29783. + AVR32_MNEMONIC_PADDSUBH_SH,
  29784. + AVR32_MNEMONIC_PADDSUBS_SH,
  29785. + AVR32_MNEMONIC_PADDSUBS_UH,
  29786. + AVR32_MNEMONIC_PADDX_H,
  29787. + AVR32_MNEMONIC_PADDXH_SH,
  29788. + AVR32_MNEMONIC_PADDXS_SH,
  29789. + AVR32_MNEMONIC_PADDXS_UH,
  29790. + AVR32_MNEMONIC_PASR_B,
  29791. + AVR32_MNEMONIC_PASR_H,
  29792. + AVR32_MNEMONIC_PAVG_SH,
  29793. + AVR32_MNEMONIC_PAVG_UB,
  29794. + AVR32_MNEMONIC_PLSL_B,
  29795. + AVR32_MNEMONIC_PLSL_H,
  29796. + AVR32_MNEMONIC_PLSR_B,
  29797. + AVR32_MNEMONIC_PLSR_H,
  29798. + AVR32_MNEMONIC_PMAX_SH,
  29799. + AVR32_MNEMONIC_PMAX_UB,
  29800. + AVR32_MNEMONIC_PMIN_SH,
  29801. + AVR32_MNEMONIC_PMIN_UB,
  29802. + AVR32_MNEMONIC_POPJC,
  29803. + AVR32_MNEMONIC_POPM,
  29804. + AVR32_MNEMONIC_PREF,
  29805. + AVR32_MNEMONIC_PSAD,
  29806. + AVR32_MNEMONIC_PSUB_B,
  29807. + AVR32_MNEMONIC_PSUB_H,
  29808. + AVR32_MNEMONIC_PSUBADD_H,
  29809. + AVR32_MNEMONIC_PSUBADDH_SH,
  29810. + AVR32_MNEMONIC_PSUBADDS_SH,
  29811. + AVR32_MNEMONIC_PSUBADDS_UH,
  29812. + AVR32_MNEMONIC_PSUBH_SH,
  29813. + AVR32_MNEMONIC_PSUBH_UB,
  29814. + AVR32_MNEMONIC_PSUBS_SB,
  29815. + AVR32_MNEMONIC_PSUBS_SH,
  29816. + AVR32_MNEMONIC_PSUBS_UB,
  29817. + AVR32_MNEMONIC_PSUBS_UH,
  29818. + AVR32_MNEMONIC_PSUBX_H,
  29819. + AVR32_MNEMONIC_PSUBXH_SH,
  29820. + AVR32_MNEMONIC_PSUBXS_SH,
  29821. + AVR32_MNEMONIC_PSUBXS_UH,
  29822. + AVR32_MNEMONIC_PUNPCKSB_H,
  29823. + AVR32_MNEMONIC_PUNPCKUB_H,
  29824. + AVR32_MNEMONIC_PUSHJC,
  29825. + AVR32_MNEMONIC_PUSHM,
  29826. + AVR32_MNEMONIC_RCALL,
  29827. + AVR32_MNEMONIC_RETEQ,
  29828. + AVR32_MNEMONIC_RETNE,
  29829. + AVR32_MNEMONIC_RETCC,
  29830. + AVR32_MNEMONIC_RETCS,
  29831. + AVR32_MNEMONIC_RETGE,
  29832. + AVR32_MNEMONIC_RETLT,
  29833. + AVR32_MNEMONIC_RETMI,
  29834. + AVR32_MNEMONIC_RETPL,
  29835. + AVR32_MNEMONIC_RETLS,
  29836. + AVR32_MNEMONIC_RETGT,
  29837. + AVR32_MNEMONIC_RETLE,
  29838. + AVR32_MNEMONIC_RETHI,
  29839. + AVR32_MNEMONIC_RETVS,
  29840. + AVR32_MNEMONIC_RETVC,
  29841. + AVR32_MNEMONIC_RETQS,
  29842. + AVR32_MNEMONIC_RETAL,
  29843. + AVR32_MNEMONIC_RETHS,
  29844. + AVR32_MNEMONIC_RETLO,
  29845. + AVR32_MNEMONIC_RET,
  29846. + AVR32_MNEMONIC_RETD,
  29847. + AVR32_MNEMONIC_RETE,
  29848. + AVR32_MNEMONIC_RETJ,
  29849. + AVR32_MNEMONIC_RETS,
  29850. + AVR32_MNEMONIC_RJMP,
  29851. + AVR32_MNEMONIC_ROL,
  29852. + AVR32_MNEMONIC_ROR,
  29853. + AVR32_MNEMONIC_RSUB,
  29854. + AVR32_MNEMONIC_SATADD_H,
  29855. + AVR32_MNEMONIC_SATADD_W,
  29856. + AVR32_MNEMONIC_SATRNDS,
  29857. + AVR32_MNEMONIC_SATRNDU,
  29858. + AVR32_MNEMONIC_SATS,
  29859. + AVR32_MNEMONIC_SATSUB_H,
  29860. + AVR32_MNEMONIC_SATSUB_W,
  29861. + AVR32_MNEMONIC_SATU,
  29862. + AVR32_MNEMONIC_SBC,
  29863. + AVR32_MNEMONIC_SBR,
  29864. + AVR32_MNEMONIC_SCALL,
  29865. + AVR32_MNEMONIC_SCR,
  29866. + AVR32_MNEMONIC_SLEEP,
  29867. + AVR32_MNEMONIC_SREQ,
  29868. + AVR32_MNEMONIC_SRNE,
  29869. + AVR32_MNEMONIC_SRCC,
  29870. + AVR32_MNEMONIC_SRCS,
  29871. + AVR32_MNEMONIC_SRGE,
  29872. + AVR32_MNEMONIC_SRLT,
  29873. + AVR32_MNEMONIC_SRMI,
  29874. + AVR32_MNEMONIC_SRPL,
  29875. + AVR32_MNEMONIC_SRLS,
  29876. + AVR32_MNEMONIC_SRGT,
  29877. + AVR32_MNEMONIC_SRLE,
  29878. + AVR32_MNEMONIC_SRHI,
  29879. + AVR32_MNEMONIC_SRVS,
  29880. + AVR32_MNEMONIC_SRVC,
  29881. + AVR32_MNEMONIC_SRQS,
  29882. + AVR32_MNEMONIC_SRAL,
  29883. + AVR32_MNEMONIC_SRHS,
  29884. + AVR32_MNEMONIC_SRLO,
  29885. + AVR32_MNEMONIC_SSRF,
  29886. + AVR32_MNEMONIC_ST_B,
  29887. + AVR32_MNEMONIC_ST_D,
  29888. + AVR32_MNEMONIC_ST_H,
  29889. + AVR32_MNEMONIC_ST_W,
  29890. + AVR32_MNEMONIC_STC_D,
  29891. + AVR32_MNEMONIC_STC_W,
  29892. + AVR32_MNEMONIC_STC0_D,
  29893. + AVR32_MNEMONIC_STC0_W,
  29894. + AVR32_MNEMONIC_STCM_D,
  29895. + AVR32_MNEMONIC_STCM_W,
  29896. + AVR32_MNEMONIC_STCOND,
  29897. + AVR32_MNEMONIC_STDSP,
  29898. + AVR32_MNEMONIC_STHH_W,
  29899. + AVR32_MNEMONIC_STM,
  29900. + AVR32_MNEMONIC_STMTS,
  29901. + AVR32_MNEMONIC_STSWP_H,
  29902. + AVR32_MNEMONIC_STSWP_W,
  29903. + AVR32_MNEMONIC_SUB,
  29904. + AVR32_MNEMONIC_SUBEQ,
  29905. + AVR32_MNEMONIC_SUBNE,
  29906. + AVR32_MNEMONIC_SUBCC,
  29907. + AVR32_MNEMONIC_SUBCS,
  29908. + AVR32_MNEMONIC_SUBGE,
  29909. + AVR32_MNEMONIC_SUBLT,
  29910. + AVR32_MNEMONIC_SUBMI,
  29911. + AVR32_MNEMONIC_SUBPL,
  29912. + AVR32_MNEMONIC_SUBLS,
  29913. + AVR32_MNEMONIC_SUBGT,
  29914. + AVR32_MNEMONIC_SUBLE,
  29915. + AVR32_MNEMONIC_SUBHI,
  29916. + AVR32_MNEMONIC_SUBVS,
  29917. + AVR32_MNEMONIC_SUBVC,
  29918. + AVR32_MNEMONIC_SUBQS,
  29919. + AVR32_MNEMONIC_SUBAL,
  29920. + AVR32_MNEMONIC_SUBHS,
  29921. + AVR32_MNEMONIC_SUBLO,
  29922. + AVR32_MNEMONIC_SUBFEQ,
  29923. + AVR32_MNEMONIC_SUBFNE,
  29924. + AVR32_MNEMONIC_SUBFCC,
  29925. + AVR32_MNEMONIC_SUBFCS,
  29926. + AVR32_MNEMONIC_SUBFGE,
  29927. + AVR32_MNEMONIC_SUBFLT,
  29928. + AVR32_MNEMONIC_SUBFMI,
  29929. + AVR32_MNEMONIC_SUBFPL,
  29930. + AVR32_MNEMONIC_SUBFLS,
  29931. + AVR32_MNEMONIC_SUBFGT,
  29932. + AVR32_MNEMONIC_SUBFLE,
  29933. + AVR32_MNEMONIC_SUBFHI,
  29934. + AVR32_MNEMONIC_SUBFVS,
  29935. + AVR32_MNEMONIC_SUBFVC,
  29936. + AVR32_MNEMONIC_SUBFQS,
  29937. + AVR32_MNEMONIC_SUBFAL,
  29938. + AVR32_MNEMONIC_SUBFHS,
  29939. + AVR32_MNEMONIC_SUBFLO,
  29940. + AVR32_MNEMONIC_SUBHH_W,
  29941. + AVR32_MNEMONIC_SWAP_B,
  29942. + AVR32_MNEMONIC_SWAP_BH,
  29943. + AVR32_MNEMONIC_SWAP_H,
  29944. + AVR32_MNEMONIC_SYNC,
  29945. + AVR32_MNEMONIC_TLBR,
  29946. + AVR32_MNEMONIC_TLBS,
  29947. + AVR32_MNEMONIC_TLBW,
  29948. + AVR32_MNEMONIC_TNBZ,
  29949. + AVR32_MNEMONIC_TST,
  29950. + AVR32_MNEMONIC_XCHG,
  29951. + AVR32_MNEMONIC_MEMC,
  29952. + AVR32_MNEMONIC_MEMS,
  29953. + AVR32_MNEMONIC_MEMT,
  29954. + AVR32_MNEMONIC_FMAC_S,
  29955. + AVR32_MNEMONIC_FNMAC_S,
  29956. + AVR32_MNEMONIC_FMSC_S,
  29957. + AVR32_MNEMONIC_FNMSC_S,
  29958. + AVR32_MNEMONIC_FMUL_S,
  29959. + AVR32_MNEMONIC_FNMUL_S,
  29960. + AVR32_MNEMONIC_FADD_S,
  29961. + AVR32_MNEMONIC_FSUB_S,
  29962. + AVR32_MNEMONIC_FCASTRS_SW,
  29963. + AVR32_MNEMONIC_FCASTRS_UW,
  29964. + AVR32_MNEMONIC_FCASTSW_S,
  29965. + AVR32_MNEMONIC_FCASTUW_S,
  29966. + AVR32_MNEMONIC_FCMP_S,
  29967. + AVR32_MNEMONIC_FCHK_S,
  29968. + AVR32_MNEMONIC_FRCPA_S,
  29969. + AVR32_MNEMONIC_FRSQRTA_S,
  29970. + /* AVR32_MNEMONIC_FLD_S,
  29971. + AVR32_MNEMONIC_FLD_D,
  29972. + AVR32_MNEMONIC_FST_S,
  29973. + AVR32_MNEMONIC_FST_D, */
  29974. + AVR32_MNEMONIC_LDA_W,
  29975. + AVR32_MNEMONIC_CALL,
  29976. + AVR32_MNEMONIC_PICOSVMAC,
  29977. + AVR32_MNEMONIC_PICOSVMUL,
  29978. + AVR32_MNEMONIC_PICOVMAC,
  29979. + AVR32_MNEMONIC_PICOVMUL,
  29980. + AVR32_MNEMONIC_PICOLD_D,
  29981. + AVR32_MNEMONIC_PICOLD_W,
  29982. + AVR32_MNEMONIC_PICOLDM_D,
  29983. + AVR32_MNEMONIC_PICOLDM_W,
  29984. + AVR32_MNEMONIC_PICOMV_D,
  29985. + AVR32_MNEMONIC_PICOMV_W,
  29986. + AVR32_MNEMONIC_PICOST_D,
  29987. + AVR32_MNEMONIC_PICOST_W,
  29988. + AVR32_MNEMONIC_PICOSTM_D,
  29989. + AVR32_MNEMONIC_PICOSTM_W,
  29990. + AVR32_MNEMONIC_RSUBEQ,
  29991. + AVR32_MNEMONIC_RSUBNE,
  29992. + AVR32_MNEMONIC_RSUBCC,
  29993. + AVR32_MNEMONIC_RSUBCS,
  29994. + AVR32_MNEMONIC_RSUBGE,
  29995. + AVR32_MNEMONIC_RSUBLT,
  29996. + AVR32_MNEMONIC_RSUBMI,
  29997. + AVR32_MNEMONIC_RSUBPL,
  29998. + AVR32_MNEMONIC_RSUBLS,
  29999. + AVR32_MNEMONIC_RSUBGT,
  30000. + AVR32_MNEMONIC_RSUBLE,
  30001. + AVR32_MNEMONIC_RSUBHI,
  30002. + AVR32_MNEMONIC_RSUBVS,
  30003. + AVR32_MNEMONIC_RSUBVC,
  30004. + AVR32_MNEMONIC_RSUBQS,
  30005. + AVR32_MNEMONIC_RSUBAL,
  30006. + AVR32_MNEMONIC_RSUBHS,
  30007. + AVR32_MNEMONIC_RSUBLO,
  30008. + AVR32_MNEMONIC_ADDEQ,
  30009. + AVR32_MNEMONIC_ADDNE,
  30010. + AVR32_MNEMONIC_ADDCC,
  30011. + AVR32_MNEMONIC_ADDCS,
  30012. + AVR32_MNEMONIC_ADDGE,
  30013. + AVR32_MNEMONIC_ADDLT,
  30014. + AVR32_MNEMONIC_ADDMI,
  30015. + AVR32_MNEMONIC_ADDPL,
  30016. + AVR32_MNEMONIC_ADDLS,
  30017. + AVR32_MNEMONIC_ADDGT,
  30018. + AVR32_MNEMONIC_ADDLE,
  30019. + AVR32_MNEMONIC_ADDHI,
  30020. + AVR32_MNEMONIC_ADDVS,
  30021. + AVR32_MNEMONIC_ADDVC,
  30022. + AVR32_MNEMONIC_ADDQS,
  30023. + AVR32_MNEMONIC_ADDAL,
  30024. + AVR32_MNEMONIC_ADDHS,
  30025. + AVR32_MNEMONIC_ADDLO,
  30026. + AVR32_MNEMONIC_ANDEQ,
  30027. + AVR32_MNEMONIC_ANDNE,
  30028. + AVR32_MNEMONIC_ANDCC,
  30029. + AVR32_MNEMONIC_ANDCS,
  30030. + AVR32_MNEMONIC_ANDGE,
  30031. + AVR32_MNEMONIC_ANDLT,
  30032. + AVR32_MNEMONIC_ANDMI,
  30033. + AVR32_MNEMONIC_ANDPL,
  30034. + AVR32_MNEMONIC_ANDLS,
  30035. + AVR32_MNEMONIC_ANDGT,
  30036. + AVR32_MNEMONIC_ANDLE,
  30037. + AVR32_MNEMONIC_ANDHI,
  30038. + AVR32_MNEMONIC_ANDVS,
  30039. + AVR32_MNEMONIC_ANDVC,
  30040. + AVR32_MNEMONIC_ANDQS,
  30041. + AVR32_MNEMONIC_ANDAL,
  30042. + AVR32_MNEMONIC_ANDHS,
  30043. + AVR32_MNEMONIC_ANDLO,
  30044. + AVR32_MNEMONIC_OREQ,
  30045. + AVR32_MNEMONIC_ORNE,
  30046. + AVR32_MNEMONIC_ORCC,
  30047. + AVR32_MNEMONIC_ORCS,
  30048. + AVR32_MNEMONIC_ORGE,
  30049. + AVR32_MNEMONIC_ORLT,
  30050. + AVR32_MNEMONIC_ORMI,
  30051. + AVR32_MNEMONIC_ORPL,
  30052. + AVR32_MNEMONIC_ORLS,
  30053. + AVR32_MNEMONIC_ORGT,
  30054. + AVR32_MNEMONIC_ORLE,
  30055. + AVR32_MNEMONIC_ORHI,
  30056. + AVR32_MNEMONIC_ORVS,
  30057. + AVR32_MNEMONIC_ORVC,
  30058. + AVR32_MNEMONIC_ORQS,
  30059. + AVR32_MNEMONIC_ORAL,
  30060. + AVR32_MNEMONIC_ORHS,
  30061. + AVR32_MNEMONIC_ORLO,
  30062. + AVR32_MNEMONIC_EOREQ,
  30063. + AVR32_MNEMONIC_EORNE,
  30064. + AVR32_MNEMONIC_EORCC,
  30065. + AVR32_MNEMONIC_EORCS,
  30066. + AVR32_MNEMONIC_EORGE,
  30067. + AVR32_MNEMONIC_EORLT,
  30068. + AVR32_MNEMONIC_EORMI,
  30069. + AVR32_MNEMONIC_EORPL,
  30070. + AVR32_MNEMONIC_EORLS,
  30071. + AVR32_MNEMONIC_EORGT,
  30072. + AVR32_MNEMONIC_EORLE,
  30073. + AVR32_MNEMONIC_EORHI,
  30074. + AVR32_MNEMONIC_EORVS,
  30075. + AVR32_MNEMONIC_EORVC,
  30076. + AVR32_MNEMONIC_EORQS,
  30077. + AVR32_MNEMONIC_EORAL,
  30078. + AVR32_MNEMONIC_EORHS,
  30079. + AVR32_MNEMONIC_EORLO,
  30080. + AVR32_MNEMONIC_LD_WEQ,
  30081. + AVR32_MNEMONIC_LD_WNE,
  30082. + AVR32_MNEMONIC_LD_WCC,
  30083. + AVR32_MNEMONIC_LD_WCS,
  30084. + AVR32_MNEMONIC_LD_WGE,
  30085. + AVR32_MNEMONIC_LD_WLT,
  30086. + AVR32_MNEMONIC_LD_WMI,
  30087. + AVR32_MNEMONIC_LD_WPL,
  30088. + AVR32_MNEMONIC_LD_WLS,
  30089. + AVR32_MNEMONIC_LD_WGT,
  30090. + AVR32_MNEMONIC_LD_WLE,
  30091. + AVR32_MNEMONIC_LD_WHI,
  30092. + AVR32_MNEMONIC_LD_WVS,
  30093. + AVR32_MNEMONIC_LD_WVC,
  30094. + AVR32_MNEMONIC_LD_WQS,
  30095. + AVR32_MNEMONIC_LD_WAL,
  30096. + AVR32_MNEMONIC_LD_WHS,
  30097. + AVR32_MNEMONIC_LD_WLO,
  30098. + AVR32_MNEMONIC_LD_SHEQ,
  30099. + AVR32_MNEMONIC_LD_SHNE,
  30100. + AVR32_MNEMONIC_LD_SHCC,
  30101. + AVR32_MNEMONIC_LD_SHCS,
  30102. + AVR32_MNEMONIC_LD_SHGE,
  30103. + AVR32_MNEMONIC_LD_SHLT,
  30104. + AVR32_MNEMONIC_LD_SHMI,
  30105. + AVR32_MNEMONIC_LD_SHPL,
  30106. + AVR32_MNEMONIC_LD_SHLS,
  30107. + AVR32_MNEMONIC_LD_SHGT,
  30108. + AVR32_MNEMONIC_LD_SHLE,
  30109. + AVR32_MNEMONIC_LD_SHHI,
  30110. + AVR32_MNEMONIC_LD_SHVS,
  30111. + AVR32_MNEMONIC_LD_SHVC,
  30112. + AVR32_MNEMONIC_LD_SHQS,
  30113. + AVR32_MNEMONIC_LD_SHAL,
  30114. + AVR32_MNEMONIC_LD_SHHS,
  30115. + AVR32_MNEMONIC_LD_SHLO,
  30116. + AVR32_MNEMONIC_LD_UHEQ,
  30117. + AVR32_MNEMONIC_LD_UHNE,
  30118. + AVR32_MNEMONIC_LD_UHCC,
  30119. + AVR32_MNEMONIC_LD_UHCS,
  30120. + AVR32_MNEMONIC_LD_UHGE,
  30121. + AVR32_MNEMONIC_LD_UHLT,
  30122. + AVR32_MNEMONIC_LD_UHMI,
  30123. + AVR32_MNEMONIC_LD_UHPL,
  30124. + AVR32_MNEMONIC_LD_UHLS,
  30125. + AVR32_MNEMONIC_LD_UHGT,
  30126. + AVR32_MNEMONIC_LD_UHLE,
  30127. + AVR32_MNEMONIC_LD_UHHI,
  30128. + AVR32_MNEMONIC_LD_UHVS,
  30129. + AVR32_MNEMONIC_LD_UHVC,
  30130. + AVR32_MNEMONIC_LD_UHQS,
  30131. + AVR32_MNEMONIC_LD_UHAL,
  30132. + AVR32_MNEMONIC_LD_UHHS,
  30133. + AVR32_MNEMONIC_LD_UHLO,
  30134. + AVR32_MNEMONIC_LD_SBEQ,
  30135. + AVR32_MNEMONIC_LD_SBNE,
  30136. + AVR32_MNEMONIC_LD_SBCC,
  30137. + AVR32_MNEMONIC_LD_SBCS,
  30138. + AVR32_MNEMONIC_LD_SBGE,
  30139. + AVR32_MNEMONIC_LD_SBLT,
  30140. + AVR32_MNEMONIC_LD_SBMI,
  30141. + AVR32_MNEMONIC_LD_SBPL,
  30142. + AVR32_MNEMONIC_LD_SBLS,
  30143. + AVR32_MNEMONIC_LD_SBGT,
  30144. + AVR32_MNEMONIC_LD_SBLE,
  30145. + AVR32_MNEMONIC_LD_SBHI,
  30146. + AVR32_MNEMONIC_LD_SBVS,
  30147. + AVR32_MNEMONIC_LD_SBVC,
  30148. + AVR32_MNEMONIC_LD_SBQS,
  30149. + AVR32_MNEMONIC_LD_SBAL,
  30150. + AVR32_MNEMONIC_LD_SBHS,
  30151. + AVR32_MNEMONIC_LD_SBLO,
  30152. + AVR32_MNEMONIC_LD_UBEQ,
  30153. + AVR32_MNEMONIC_LD_UBNE,
  30154. + AVR32_MNEMONIC_LD_UBCC,
  30155. + AVR32_MNEMONIC_LD_UBCS,
  30156. + AVR32_MNEMONIC_LD_UBGE,
  30157. + AVR32_MNEMONIC_LD_UBLT,
  30158. + AVR32_MNEMONIC_LD_UBMI,
  30159. + AVR32_MNEMONIC_LD_UBPL,
  30160. + AVR32_MNEMONIC_LD_UBLS,
  30161. + AVR32_MNEMONIC_LD_UBGT,
  30162. + AVR32_MNEMONIC_LD_UBLE,
  30163. + AVR32_MNEMONIC_LD_UBHI,
  30164. + AVR32_MNEMONIC_LD_UBVS,
  30165. + AVR32_MNEMONIC_LD_UBVC,
  30166. + AVR32_MNEMONIC_LD_UBQS,
  30167. + AVR32_MNEMONIC_LD_UBAL,
  30168. + AVR32_MNEMONIC_LD_UBHS,
  30169. + AVR32_MNEMONIC_LD_UBLO,
  30170. + AVR32_MNEMONIC_ST_WEQ,
  30171. + AVR32_MNEMONIC_ST_WNE,
  30172. + AVR32_MNEMONIC_ST_WCC,
  30173. + AVR32_MNEMONIC_ST_WCS,
  30174. + AVR32_MNEMONIC_ST_WGE,
  30175. + AVR32_MNEMONIC_ST_WLT,
  30176. + AVR32_MNEMONIC_ST_WMI,
  30177. + AVR32_MNEMONIC_ST_WPL,
  30178. + AVR32_MNEMONIC_ST_WLS,
  30179. + AVR32_MNEMONIC_ST_WGT,
  30180. + AVR32_MNEMONIC_ST_WLE,
  30181. + AVR32_MNEMONIC_ST_WHI,
  30182. + AVR32_MNEMONIC_ST_WVS,
  30183. + AVR32_MNEMONIC_ST_WVC,
  30184. + AVR32_MNEMONIC_ST_WQS,
  30185. + AVR32_MNEMONIC_ST_WAL,
  30186. + AVR32_MNEMONIC_ST_WHS,
  30187. + AVR32_MNEMONIC_ST_WLO,
  30188. + AVR32_MNEMONIC_ST_HEQ,
  30189. + AVR32_MNEMONIC_ST_HNE,
  30190. + AVR32_MNEMONIC_ST_HCC,
  30191. + AVR32_MNEMONIC_ST_HCS,
  30192. + AVR32_MNEMONIC_ST_HGE,
  30193. + AVR32_MNEMONIC_ST_HLT,
  30194. + AVR32_MNEMONIC_ST_HMI,
  30195. + AVR32_MNEMONIC_ST_HPL,
  30196. + AVR32_MNEMONIC_ST_HLS,
  30197. + AVR32_MNEMONIC_ST_HGT,
  30198. + AVR32_MNEMONIC_ST_HLE,
  30199. + AVR32_MNEMONIC_ST_HHI,
  30200. + AVR32_MNEMONIC_ST_HVS,
  30201. + AVR32_MNEMONIC_ST_HVC,
  30202. + AVR32_MNEMONIC_ST_HQS,
  30203. + AVR32_MNEMONIC_ST_HAL,
  30204. + AVR32_MNEMONIC_ST_HHS,
  30205. + AVR32_MNEMONIC_ST_HLO,
  30206. + AVR32_MNEMONIC_ST_BEQ,
  30207. + AVR32_MNEMONIC_ST_BNE,
  30208. + AVR32_MNEMONIC_ST_BCC,
  30209. + AVR32_MNEMONIC_ST_BCS,
  30210. + AVR32_MNEMONIC_ST_BGE,
  30211. + AVR32_MNEMONIC_ST_BLT,
  30212. + AVR32_MNEMONIC_ST_BMI,
  30213. + AVR32_MNEMONIC_ST_BPL,
  30214. + AVR32_MNEMONIC_ST_BLS,
  30215. + AVR32_MNEMONIC_ST_BGT,
  30216. + AVR32_MNEMONIC_ST_BLE,
  30217. + AVR32_MNEMONIC_ST_BHI,
  30218. + AVR32_MNEMONIC_ST_BVS,
  30219. + AVR32_MNEMONIC_ST_BVC,
  30220. + AVR32_MNEMONIC_ST_BQS,
  30221. + AVR32_MNEMONIC_ST_BAL,
  30222. + AVR32_MNEMONIC_ST_BHS,
  30223. + AVR32_MNEMONIC_ST_BLO,
  30224. + AVR32_MNEMONIC_MOVH,
  30225. + AVR32_MNEMONIC__END_
  30226. +};
  30227. +#define AVR32_NR_MNEMONICS AVR32_MNEMONIC__END_
  30228. +
  30229. +enum avr32_syntax_parser
  30230. + {
  30231. + AVR32_PARSER_NORMAL,
  30232. + AVR32_PARSER_ALIAS,
  30233. + AVR32_PARSER_LDA,
  30234. + AVR32_PARSER_CALL,
  30235. + AVR32_PARSER__END_
  30236. + };
  30237. +#define AVR32_NR_PARSERS AVR32_PARSER__END_
  30238. --- a/opcodes/configure.in
  30239. +++ b/opcodes/configure.in
  30240. @@ -223,6 +223,7 @@ if test x${all_targets} = xfalse ; then
  30241. bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
  30242. bfd_arm_arch) ta="$ta arm-dis.lo" ;;
  30243. bfd_avr_arch) ta="$ta avr-dis.lo" ;;
  30244. + bfd_avr32_arch) ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
  30245. bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
  30246. bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;;
  30247. bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
  30248. @@ -285,7 +286,7 @@ if test x${all_targets} = xfalse ; then
  30249. ta="$ta sh64-dis.lo sh64-opc.lo"
  30250. archdefs="$archdefs -DINCLUDE_SHMEDIA"
  30251. break;;
  30252. - esac;
  30253. + esac
  30254. done
  30255. ta="$ta sh-dis.lo cgen-bitset.lo" ;;
  30256. bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;;
  30257. --- a/opcodes/disassemble.c
  30258. +++ b/opcodes/disassemble.c
  30259. @@ -27,6 +27,7 @@
  30260. #define ARCH_arc
  30261. #define ARCH_arm
  30262. #define ARCH_avr
  30263. +#define ARCH_avr32
  30264. #define ARCH_bfin
  30265. #define ARCH_cr16
  30266. #define ARCH_cris
  30267. @@ -131,6 +132,11 @@ disassembler (abfd)
  30268. disassemble = print_insn_avr;
  30269. break;
  30270. #endif
  30271. +#ifdef ARCH_avr32
  30272. + case bfd_arch_avr32:
  30273. + disassemble = print_insn_avr32;
  30274. + break;
  30275. +#endif
  30276. #ifdef ARCH_bfin
  30277. case bfd_arch_bfin:
  30278. disassemble = print_insn_bfin;
  30279. @@ -485,6 +491,9 @@ disassembler_usage (stream)
  30280. #ifdef ARCH_i386
  30281. print_i386_disassembler_options (stream);
  30282. #endif
  30283. +#ifdef ARCH_avr32
  30284. + print_avr32_disassembler_options (stream);
  30285. +#endif
  30286. #ifdef ARCH_s390
  30287. print_s390_disassembler_options (stream);
  30288. #endif
  30289. --- a/bfd/configure
  30290. +++ b/bfd/configure
  30291. @@ -14787,6 +14787,7 @@ do
  30292. bfd_pei_ia64_vec) tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
  30293. bfd_elf32_am33lin_vec) tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
  30294. bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
  30295. + bfd_elf32_avr32_vec) tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
  30296. bfd_elf32_bfin_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
  30297. bfd_elf32_bfinfdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
  30298. bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
  30299. --- a/opcodes/configure
  30300. +++ b/opcodes/configure
  30301. @@ -12284,6 +12284,7 @@ if test x${all_targets} = xfalse ; then
  30302. bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
  30303. bfd_arm_arch) ta="$ta arm-dis.lo" ;;
  30304. bfd_avr_arch) ta="$ta avr-dis.lo" ;;
  30305. + bfd_avr32_arch) ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
  30306. bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
  30307. bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;;
  30308. bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
  30309. --- a/bfd/libbfd.h
  30310. +++ b/bfd/libbfd.h
  30311. @@ -1646,6 +1646,48 @@ static const char *const bfd_reloc_code_
  30312. "BFD_RELOC_AVR_LDI",
  30313. "BFD_RELOC_AVR_6",
  30314. "BFD_RELOC_AVR_6_ADIW",
  30315. + "BFD_RELOC_AVR32_DIFF32",
  30316. + "BFD_RELOC_AVR32_DIFF16",
  30317. + "BFD_RELOC_AVR32_DIFF8",
  30318. + "BFD_RELOC_AVR32_GOT32",
  30319. + "BFD_RELOC_AVR32_GOT16",
  30320. + "BFD_RELOC_AVR32_GOT8",
  30321. + "BFD_RELOC_AVR32_21S",
  30322. + "BFD_RELOC_AVR32_16U",
  30323. + "BFD_RELOC_AVR32_16S",
  30324. + "BFD_RELOC_AVR32_SUB5",
  30325. + "BFD_RELOC_AVR32_8S_EXT",
  30326. + "BFD_RELOC_AVR32_8S",
  30327. + "BFD_RELOC_AVR32_15S",
  30328. + "BFD_RELOC_AVR32_22H_PCREL",
  30329. + "BFD_RELOC_AVR32_18W_PCREL",
  30330. + "BFD_RELOC_AVR32_16B_PCREL",
  30331. + "BFD_RELOC_AVR32_16N_PCREL",
  30332. + "BFD_RELOC_AVR32_14UW_PCREL",
  30333. + "BFD_RELOC_AVR32_11H_PCREL",
  30334. + "BFD_RELOC_AVR32_10UW_PCREL",
  30335. + "BFD_RELOC_AVR32_9H_PCREL",
  30336. + "BFD_RELOC_AVR32_9UW_PCREL",
  30337. + "BFD_RELOC_AVR32_GOTPC",
  30338. + "BFD_RELOC_AVR32_GOTCALL",
  30339. + "BFD_RELOC_AVR32_LDA_GOT",
  30340. + "BFD_RELOC_AVR32_GOT21S",
  30341. + "BFD_RELOC_AVR32_GOT18SW",
  30342. + "BFD_RELOC_AVR32_GOT16S",
  30343. + "BFD_RELOC_AVR32_32_CPENT",
  30344. + "BFD_RELOC_AVR32_CPCALL",
  30345. + "BFD_RELOC_AVR32_16_CP",
  30346. + "BFD_RELOC_AVR32_9W_CP",
  30347. + "BFD_RELOC_AVR32_ALIGN",
  30348. + "BFD_RELOC_AVR32_14UW",
  30349. + "BFD_RELOC_AVR32_10UW",
  30350. + "BFD_RELOC_AVR32_10SW",
  30351. + "BFD_RELOC_AVR32_STHH_W",
  30352. + "BFD_RELOC_AVR32_7UW",
  30353. + "BFD_RELOC_AVR32_6S",
  30354. + "BFD_RELOC_AVR32_6UW",
  30355. + "BFD_RELOC_AVR32_4UH",
  30356. + "BFD_RELOC_AVR32_3U",
  30357. "BFD_RELOC_390_12",
  30358. "BFD_RELOC_390_GOT12",
  30359. "BFD_RELOC_390_PLT32",
  30360. --- a/ld/Makefile.in
  30361. +++ b/ld/Makefile.in
  30362. @@ -434,6 +434,53 @@ ALL_EMULATIONS = \
  30363. eavr5.o \
  30364. eavr51.o \
  30365. eavr6.o \
  30366. + eavr32elf_ap7000.o \
  30367. + eavr32elf_ap7001.o \
  30368. + eavr32elf_ap7002.o \
  30369. + eavr32elf_ap7200.o \
  30370. + eavr32elf_uc3a0128.o \
  30371. + eavr32elf_uc3a0256.o \
  30372. + eavr32elf_uc3a0512.o \
  30373. + eavr32elf_uc3a0512es.o \
  30374. + eavr32elf_uc3a1128.o \
  30375. + eavr32elf_uc3a1256.o \
  30376. + eavr32elf_uc3a1512es.o \
  30377. + eavr32elf_uc3a1512.o \
  30378. + eavr32elf_uc3a364.o \
  30379. + eavr32elf_uc3a364s.o \
  30380. + eavr32elf_uc3a3128.o \
  30381. + eavr32elf_uc3a3128s.o \
  30382. + eavr32elf_uc3a3256.o \
  30383. + eavr32elf_uc3a3256s.o \
  30384. + eavr32elf_uc3b064.o \
  30385. + eavr32elf_uc3b0128.o \
  30386. + eavr32elf_uc3b0256es.o \
  30387. + eavr32elf_uc3b0256.o \
  30388. + eavr32elf_uc3b0512.o \
  30389. + eavr32elf_uc3b0512revc.o \
  30390. + eavr32elf_uc3b164.o \
  30391. + eavr32elf_uc3b1128.o \
  30392. + eavr32elf_uc3b1256es.o \
  30393. + eavr32elf_uc3b1256.o \
  30394. + eavr32elf_uc3b1512.o \
  30395. + eavr32elf_uc3b1512revc.o \
  30396. + eavr32elf_uc3c064c.o \
  30397. + eavr32elf_uc3c0128c.o \
  30398. + eavr32elf_uc3c0256c.o \
  30399. + eavr32elf_uc3c0512crevc.o \
  30400. + eavr32elf_uc3c164c.o \
  30401. + eavr32elf_uc3c1128c.o \
  30402. + eavr32elf_uc3c1256c.o \
  30403. + eavr32elf_uc3c1512crevc.o \
  30404. + eavr32elf_uc3c264c.o \
  30405. + eavr32elf_uc3c2128c.o \
  30406. + eavr32elf_uc3c2256c.o \
  30407. + eavr32elf_uc3c2512crevc.o \
  30408. + eavr32elf_uc3l064.o \
  30409. + eavr32elf_uc3l032.o \
  30410. + eavr32elf_uc3l016.o \
  30411. + eavr32elf_uc3l064revb.o \
  30412. + eavr32linux.o \
  30413. ecoff_i860.o \
  30414. ecoff_sparc.o \
  30415. eelf32_spu.o \
  30416. @@ -2069,6 +2116,194 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
  30417. $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
  30418. ${GEN_DEPENDS}
  30419. ${GENSCRIPTS} avr6 "$(tdir_avr2)"
  30420. +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
  30421. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30422. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30423. + ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
  30424. +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
  30425. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30426. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30427. + ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
  30428. +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
  30429. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30430. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30431. + ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
  30432. +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
  30433. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30434. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30435. + ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
  30436. +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
  30437. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30438. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30439. + ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
  30440. +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
  30441. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30442. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30443. + ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
  30444. +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
  30445. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30446. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30447. + ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
  30448. +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
  30449. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30450. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30451. + ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
  30452. +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
  30453. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30454. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30455. + ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
  30456. +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
  30457. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30458. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30459. + ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
  30460. +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
  30461. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30462. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30463. + ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
  30464. +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
  30465. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30466. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30467. + ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
  30468. +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
  30469. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30470. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30471. + ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
  30472. +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
  30473. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30474. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30475. + ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
  30476. +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
  30477. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30478. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30479. + ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
  30480. +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
  30481. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30482. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30483. + ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
  30484. +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
  30485. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30486. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30487. + ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
  30488. +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
  30489. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30490. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30491. + ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
  30492. +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
  30493. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30494. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30495. + ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
  30496. +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
  30497. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30498. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30499. + ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
  30500. +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
  30501. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30502. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30503. + ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
  30504. +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
  30505. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30506. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30507. + ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
  30508. +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
  30509. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30510. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30511. + ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
  30512. +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
  30513. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30514. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30515. + ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
  30516. +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
  30517. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30518. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30519. + ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
  30520. +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
  30521. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30522. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30523. + ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
  30524. +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
  30525. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30526. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30527. + ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
  30528. +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
  30529. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30530. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30531. + ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
  30532. +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
  30533. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30534. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30535. + ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
  30536. +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
  30537. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30538. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30539. + ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
  30540. +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
  30541. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30542. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30543. + ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
  30544. +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
  30545. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30546. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30547. + ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
  30548. +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
  30549. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30550. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30551. + ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
  30552. +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
  30553. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30554. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30555. + ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
  30556. +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
  30557. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30558. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30559. + ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
  30560. +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
  30561. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30562. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30563. + ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
  30564. +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
  30565. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30566. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30567. + ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
  30568. +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
  30569. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30570. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30571. + ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
  30572. +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
  30573. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30574. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30575. + ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
  30576. +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
  30577. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30578. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30579. + ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
  30580. +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
  30581. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30582. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30583. + ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
  30584. +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
  30585. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30586. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30587. + ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
  30588. +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
  30589. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30590. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30591. + ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
  30592. +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
  30593. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30594. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30595. + ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
  30596. +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
  30597. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30598. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30599. + ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
  30600. +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
  30601. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30602. + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
  30603. + ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
  30604. +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
  30605. + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
  30606. + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
  30607. + ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
  30608. ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
  30609. $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
  30610. ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
  30611. --- a/gas/Makefile.in
  30612. +++ b/gas/Makefile.in
  30613. @@ -309,6 +309,7 @@ CPU_TYPES = \
  30614. arc \
  30615. arm \
  30616. avr \
  30617. + avr32 \
  30618. bfin \
  30619. cr16 \
  30620. cris \
  30621. @@ -508,6 +509,7 @@ TARGET_CPU_CFILES = \
  30622. config/tc-arc.c \
  30623. config/tc-arm.c \
  30624. config/tc-avr.c \
  30625. + config/tc-avr32.c \
  30626. config/tc-bfin.c \
  30627. config/tc-cr16.c \
  30628. config/tc-cris.c \
  30629. @@ -571,6 +573,7 @@ TARGET_CPU_HFILES = \
  30630. config/tc-arc.h \
  30631. config/tc-arm.h \
  30632. config/tc-avr.h \
  30633. + config/tc-avr32.h \
  30634. config/tc-bfin.h \
  30635. config/tc-cr16.h \
  30636. config/tc-cris.h \
  30637. @@ -949,6 +952,7 @@ distclean-compile:
  30638. @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arc.Po@am__quote@
  30639. @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arm.Po@am__quote@
  30640. @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr.Po@am__quote@
  30641. +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr32.Po@am__quote@
  30642. @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-bfin.Po@am__quote@
  30643. @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cr16.Po@am__quote@
  30644. @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cris.Po@am__quote@
  30645. @@ -1086,6 +1090,20 @@ tc-avr.obj: config/tc-avr.c
  30646. @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
  30647. @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr.obj `if test -f 'config/tc-avr.c'; then $(CYGPATH_W) 'config/tc-avr.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr.c'; fi`
  30648. +tc-avr32.o: config/tc-avr32.c
  30649. +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.o -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
  30650. +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
  30651. +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-avr32.c' object='tc-avr32.o' libtool=no @AMDEPBACKSLASH@
  30652. +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
  30653. +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
  30654. +
  30655. +tc-avr32.obj: config/tc-avr32.c
  30656. +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.obj -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
  30657. +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
  30658. +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-avr32.c' object='tc-avr32.obj' libtool=no @AMDEPBACKSLASH@
  30659. +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
  30660. +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
  30661. +
  30662. tc-bfin.o: config/tc-bfin.c
  30663. @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-bfin.o -MD -MP -MF $(DEPDIR)/tc-bfin.Tpo -c -o tc-bfin.o `test -f 'config/tc-bfin.c' || echo '$(srcdir)/'`config/tc-bfin.c
  30664. @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-bfin.Tpo $(DEPDIR)/tc-bfin.Po
  30665. --- a/bfd/bfd-in2.h
  30666. +++ b/bfd/bfd-in2.h
  30667. @@ -2042,6 +2042,12 @@ enum bfd_architecture
  30668. #define bfd_mach_avr5 5
  30669. #define bfd_mach_avr51 51
  30670. #define bfd_mach_avr6 6
  30671. + bfd_arch_avr32, /* Atmel AVR32 */
  30672. +#define bfd_mach_avr32_ap 7000
  30673. +#define bfd_mach_avr32_uc 3000
  30674. +#define bfd_mach_avr32_ucr1 3001
  30675. +#define bfd_mach_avr32_ucr2 3002
  30676. +#define bfd_mach_avr32_ucr3 3003
  30677. bfd_arch_bfin, /* ADI Blackfin */
  30678. #define bfd_mach_bfin 1
  30679. bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */
  30680. @@ -3851,6 +3857,88 @@ instructions */
  30681. instructions */
  30682. BFD_RELOC_AVR_6_ADIW,
  30683. +/* Difference between two labels: L2 - L1. The value of L1 is encoded
  30684. +as sym + addend, while the initial difference after assembly is
  30685. +inserted into the object file by the assembler. */
  30686. + BFD_RELOC_AVR32_DIFF32,
  30687. + BFD_RELOC_AVR32_DIFF16,
  30688. + BFD_RELOC_AVR32_DIFF8,
  30689. +
  30690. +/* Reference to a symbol through the Global Offset Table. The linker
  30691. +will allocate an entry for symbol in the GOT and insert the offset
  30692. +of this entry as the relocation value. */
  30693. + BFD_RELOC_AVR32_GOT32,
  30694. + BFD_RELOC_AVR32_GOT16,
  30695. + BFD_RELOC_AVR32_GOT8,
  30696. +
  30697. +/* Normal (non-pc-relative) code relocations. Alignment and signedness
  30698. +is indicated by the suffixes. S means signed, U means unsigned. W
  30699. +means word-aligned, H means halfword-aligned, neither means
  30700. +byte-aligned (no alignment.) SUB5 is the same relocation as 16S. */
  30701. + BFD_RELOC_AVR32_21S,
  30702. + BFD_RELOC_AVR32_16U,
  30703. + BFD_RELOC_AVR32_16S,
  30704. + BFD_RELOC_AVR32_SUB5,
  30705. + BFD_RELOC_AVR32_8S_EXT,
  30706. + BFD_RELOC_AVR32_8S,
  30707. + BFD_RELOC_AVR32_15S,
  30708. +
  30709. +/* PC-relative relocations are signed if neither 'U' nor 'S' is
  30710. +specified. However, we explicitly tack on a 'B' to indicate no
  30711. +alignment, to avoid confusion with data relocs. All of these resolve
  30712. +to sym + addend - offset, except the one with 'N' (negated) suffix.
  30713. +This particular one resolves to offset - sym - addend. */
  30714. + BFD_RELOC_AVR32_22H_PCREL,
  30715. + BFD_RELOC_AVR32_18W_PCREL,
  30716. + BFD_RELOC_AVR32_16B_PCREL,
  30717. + BFD_RELOC_AVR32_16N_PCREL,
  30718. + BFD_RELOC_AVR32_14UW_PCREL,
  30719. + BFD_RELOC_AVR32_11H_PCREL,
  30720. + BFD_RELOC_AVR32_10UW_PCREL,
  30721. + BFD_RELOC_AVR32_9H_PCREL,
  30722. + BFD_RELOC_AVR32_9UW_PCREL,
  30723. +
  30724. +/* Subtract the link-time address of the GOT from (symbol + addend)
  30725. +and insert the result. */
  30726. + BFD_RELOC_AVR32_GOTPC,
  30727. +
  30728. +/* Reference to a symbol through the GOT. The linker will allocate an
  30729. +entry for symbol in the GOT and insert the offset of this entry as
  30730. +the relocation value. addend must be zero. As usual, 'S' means
  30731. +signed, 'W' means word-aligned, etc. */
  30732. + BFD_RELOC_AVR32_GOTCALL,
  30733. + BFD_RELOC_AVR32_LDA_GOT,
  30734. + BFD_RELOC_AVR32_GOT21S,
  30735. + BFD_RELOC_AVR32_GOT18SW,
  30736. + BFD_RELOC_AVR32_GOT16S,
  30737. +
  30738. +/* 32-bit constant pool entry. I don't think 8- and 16-bit entries make
  30739. +a whole lot of sense. */
  30740. + BFD_RELOC_AVR32_32_CPENT,
  30741. +
  30742. +/* Constant pool references. Some of these relocations are signed,
  30743. +others are unsigned. It doesn't really matter, since the constant
  30744. +pool always comes after the code that references it. */
  30745. + BFD_RELOC_AVR32_CPCALL,
  30746. + BFD_RELOC_AVR32_16_CP,
  30747. + BFD_RELOC_AVR32_9W_CP,
  30748. +
  30749. +/* sym must be the absolute symbol. The addend specifies the alignment
  30750. +order, e.g. if addend is 2, the linker must add padding so that the
  30751. +next address is aligned to a 4-byte boundary. */
  30752. + BFD_RELOC_AVR32_ALIGN,
  30753. +
  30754. +/* Code relocations that will never make it to the output file. */
  30755. + BFD_RELOC_AVR32_14UW,
  30756. + BFD_RELOC_AVR32_10UW,
  30757. + BFD_RELOC_AVR32_10SW,
  30758. + BFD_RELOC_AVR32_STHH_W,
  30759. + BFD_RELOC_AVR32_7UW,
  30760. + BFD_RELOC_AVR32_6S,
  30761. + BFD_RELOC_AVR32_6UW,
  30762. + BFD_RELOC_AVR32_4UH,
  30763. + BFD_RELOC_AVR32_3U,
  30764. +
  30765. /* Direct 12 bit. */
  30766. BFD_RELOC_390_12,