1
0

s3adsp1800.dts 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287
  1. /dts-v1/;
  2. / {
  3. #address-cells = <0x1>;
  4. #size-cells = <0x1>;
  5. compatible = "xlnx,microblaze";
  6. model = "testing";
  7. memory@90000000 {
  8. device_type = "memory";
  9. reg = <0x90000000 0x8000000>;
  10. };
  11. chosen {
  12. bootargs = "console=ttyUL0,115200";
  13. linux,stdout-path = "/plb@0/serial@84000000";
  14. };
  15. cpus {
  16. #address-cells = <0x1>;
  17. #cpus = <0x1>;
  18. #size-cells = <0x0>;
  19. cpu@0 {
  20. clock-frequency = <0x3b9aca0>;
  21. compatible = "xlnx,microblaze-7.10.d";
  22. d-cache-baseaddr = <0x90000000>;
  23. d-cache-highaddr = <0x97ffffff>;
  24. d-cache-line-size = <0x10>;
  25. d-cache-size = <0x800>;
  26. device_type = "cpu";
  27. i-cache-baseaddr = <0x90000000>;
  28. i-cache-highaddr = <0x97ffffff>;
  29. i-cache-line-size = <0x10>;
  30. i-cache-size = <0x800>;
  31. model = "microblaze,7.10.d";
  32. reg = <0x0>;
  33. timebase-frequency = <0x3b9aca0>;
  34. xlnx,addr-tag-bits = <0x10>;
  35. xlnx,allow-dcache-wr = <0x1>;
  36. xlnx,allow-icache-wr = <0x1>;
  37. xlnx,area-optimized = <0x0>;
  38. xlnx,cache-byte-size = <0x800>;
  39. xlnx,d-lmb = <0x1>;
  40. xlnx,d-opb = <0x0>;
  41. xlnx,d-plb = <0x1>;
  42. xlnx,data-size = <0x20>;
  43. xlnx,dcache-addr-tag = <0x10>;
  44. xlnx,dcache-always-used = <0x0>;
  45. xlnx,dcache-byte-size = <0x800>;
  46. xlnx,dcache-line-len = <0x4>;
  47. xlnx,dcache-use-fsl = <0x1>;
  48. xlnx,debug-enabled = <0x1>;
  49. xlnx,div-zero-exception = <0x0>;
  50. xlnx,dopb-bus-exception = <0x0>;
  51. xlnx,dynamic-bus-sizing = <0x1>;
  52. xlnx,edge-is-positive = <0x1>;
  53. xlnx,family = "spartan3adsp";
  54. xlnx,fpu-exception = <0x0>;
  55. xlnx,fsl-data-size = <0x20>;
  56. xlnx,fsl-exception = <0x0>;
  57. xlnx,fsl-links = <0x0>;
  58. xlnx,i-lmb = <0x1>;
  59. xlnx,i-opb = <0x0>;
  60. xlnx,i-plb = <0x1>;
  61. xlnx,icache-always-used = <0x0>;
  62. xlnx,icache-line-len = <0x4>;
  63. xlnx,icache-use-fsl = <0x1>;
  64. xlnx,ill-opcode-exception = <0x0>;
  65. xlnx,instance = "microblaze_0";
  66. xlnx,interconnect = <0x1>;
  67. xlnx,interrupt-is-edge = <0x0>;
  68. xlnx,iopb-bus-exception = <0x0>;
  69. xlnx,mmu-dtlb-size = <0x4>;
  70. xlnx,mmu-itlb-size = <0x2>;
  71. xlnx,mmu-tlb-access = <0x3>;
  72. xlnx,mmu-zones = <0x10>;
  73. xlnx,number-of-pc-brk = <0x3>;
  74. xlnx,number-of-rd-addr-brk = <0x2>;
  75. xlnx,number-of-wr-addr-brk = <0x2>;
  76. xlnx,opcode-0x0-illegal = <0x0>;
  77. xlnx,pvr = <0x1>;
  78. xlnx,pvr-user1 = <0x0>;
  79. xlnx,pvr-user2 = <0x0>;
  80. xlnx,reset-msr = <0x0>;
  81. xlnx,sco = <0x0>;
  82. xlnx,unaligned-exceptions = <0x1>;
  83. xlnx,use-barrel = <0x1>;
  84. xlnx,use-dcache = <0x1>;
  85. xlnx,use-div = <0x0>;
  86. xlnx,use-ext-brk = <0x1>;
  87. xlnx,use-ext-nm-brk = <0x1>;
  88. xlnx,use-extended-fsl-instr = <0x0>;
  89. xlnx,use-fpu = <0x0>;
  90. xlnx,use-hw-mul = <0x1>;
  91. xlnx,use-icache = <0x1>;
  92. xlnx,use-interrupt = <0x1>;
  93. xlnx,use-mmu = <0x3>;
  94. xlnx,use-msr-instr = <0x1>;
  95. xlnx,use-pcmp-instr = <0x1>;
  96. };
  97. };
  98. plb@0 {
  99. #address-cells = <0x1>;
  100. #size-cells = <0x1>;
  101. compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
  102. ranges;
  103. ethernet@81000000 {
  104. compatible = "xlnx,xps-ethernetlite-2.00.b";
  105. device_type = "network";
  106. interrupt-parent = <0x1>;
  107. interrupts = <0x1 0x0>;
  108. local-mac-address = [02 00 00 00 00 00];
  109. reg = <0x81000000 0x10000>;
  110. xlnx,duplex = <0x1>;
  111. xlnx,family = "spartan3adsp";
  112. xlnx,rx-ping-pong = <0x0>;
  113. xlnx,tx-ping-pong = <0x0>;
  114. };
  115. flash@a0000000 {
  116. #address-cells = <1>;
  117. #size-cells = <1>;
  118. bank-width = <0x1>;
  119. compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
  120. reg = <0xa0000000 0x1000000>;
  121. xlnx,family = "spartan3adsp";
  122. xlnx,include-datawidth-matching-0 = <0x1>;
  123. xlnx,include-datawidth-matching-1 = <0x0>;
  124. xlnx,include-datawidth-matching-2 = <0x0>;
  125. xlnx,include-datawidth-matching-3 = <0x0>;
  126. xlnx,include-negedge-ioregs = <0x0>;
  127. xlnx,include-plb-ipif = <0x1>;
  128. xlnx,include-wrbuf = <0x1>;
  129. xlnx,max-mem-width = <0x8>;
  130. xlnx,mch-native-dwidth = <0x20>;
  131. xlnx,mch-plb-clk-period-ps = <0x3e80>;
  132. xlnx,mch-splb-awidth = <0x20>;
  133. xlnx,mch0-accessbuf-depth = <0x10>;
  134. xlnx,mch0-protocol = <0x0>;
  135. xlnx,mch0-rddatabuf-depth = <0x10>;
  136. xlnx,mch1-accessbuf-depth = <0x10>;
  137. xlnx,mch1-protocol = <0x0>;
  138. xlnx,mch1-rddatabuf-depth = <0x10>;
  139. xlnx,mch2-accessbuf-depth = <0x10>;
  140. xlnx,mch2-protocol = <0x0>;
  141. xlnx,mch2-rddatabuf-depth = <0x10>;
  142. xlnx,mch3-accessbuf-depth = <0x10>;
  143. xlnx,mch3-protocol = <0x0>;
  144. xlnx,mch3-rddatabuf-depth = <0x10>;
  145. xlnx,mem0-width = <0x8>;
  146. xlnx,mem1-width = <0x20>;
  147. xlnx,mem2-width = <0x20>;
  148. xlnx,mem3-width = <0x20>;
  149. xlnx,num-banks-mem = <0x1>;
  150. xlnx,num-channels = <0x0>;
  151. xlnx,priority-mode = <0x0>;
  152. xlnx,synch-mem-0 = <0x0>;
  153. xlnx,synch-mem-1 = <0x0>;
  154. xlnx,synch-mem-2 = <0x0>;
  155. xlnx,synch-mem-3 = <0x0>;
  156. xlnx,synch-pipedelay-0 = <0x2>;
  157. xlnx,synch-pipedelay-1 = <0x2>;
  158. xlnx,synch-pipedelay-2 = <0x2>;
  159. xlnx,synch-pipedelay-3 = <0x2>;
  160. xlnx,tavdv-ps-mem-0 = <0x11170>;
  161. xlnx,tavdv-ps-mem-1 = <0x3a98>;
  162. xlnx,tavdv-ps-mem-2 = <0x3a98>;
  163. xlnx,tavdv-ps-mem-3 = <0x3a98>;
  164. xlnx,tcedv-ps-mem-0 = <0x11170>;
  165. xlnx,tcedv-ps-mem-1 = <0x3a98>;
  166. xlnx,tcedv-ps-mem-2 = <0x3a98>;
  167. xlnx,tcedv-ps-mem-3 = <0x3a98>;
  168. xlnx,thzce-ps-mem-0 = <0x61a8>;
  169. xlnx,thzce-ps-mem-1 = <0x1b58>;
  170. xlnx,thzce-ps-mem-2 = <0x1b58>;
  171. xlnx,thzce-ps-mem-3 = <0x1b58>;
  172. xlnx,thzoe-ps-mem-0 = <0x61a8>;
  173. xlnx,thzoe-ps-mem-1 = <0x1b58>;
  174. xlnx,thzoe-ps-mem-2 = <0x1b58>;
  175. xlnx,thzoe-ps-mem-3 = <0x1b58>;
  176. xlnx,tlzwe-ps-mem-0 = <0x1388>;
  177. xlnx,tlzwe-ps-mem-1 = <0x0>;
  178. xlnx,tlzwe-ps-mem-2 = <0x0>;
  179. xlnx,tlzwe-ps-mem-3 = <0x0>;
  180. xlnx,twc-ps-mem-0 = <0x11170>;
  181. xlnx,twc-ps-mem-1 = <0x3a98>;
  182. xlnx,twc-ps-mem-2 = <0x3a98>;
  183. xlnx,twc-ps-mem-3 = <0x3a98>;
  184. xlnx,twp-ps-mem-0 = <0xafc8>;
  185. xlnx,twp-ps-mem-1 = <0x2ee0>;
  186. xlnx,twp-ps-mem-2 = <0x2ee0>;
  187. xlnx,twp-ps-mem-3 = <0x2ee0>;
  188. xlnx,xcl0-linesize = <0x4>;
  189. xlnx,xcl0-writexfer = <0x1>;
  190. xlnx,xcl1-linesize = <0x4>;
  191. xlnx,xcl1-writexfer = <0x1>;
  192. xlnx,xcl2-linesize = <0x4>;
  193. xlnx,xcl2-writexfer = <0x1>;
  194. xlnx,xcl3-linesize = <0x4>;
  195. xlnx,xcl3-writexfer = <0x1>;
  196. partition@0x00000000 {
  197. label = "rootfs";
  198. reg = <0x00000000 0x01000000>;
  199. };
  200. };
  201. gpio@81400000 {
  202. compatible = "xlnx,xps-gpio-1.00.a";
  203. interrupt-parent = <0x1>;
  204. interrupts = <0x2 0x2>;
  205. reg = <0x81400000 0x10000>;
  206. xlnx,all-inputs = <0x0>;
  207. xlnx,all-inputs-2 = <0x0>;
  208. xlnx,dout-default = <0x0>;
  209. xlnx,dout-default-2 = <0x0>;
  210. xlnx,family = "spartan3adsp";
  211. xlnx,gpio-width = <0x8>;
  212. xlnx,interrupt-present = <0x1>;
  213. xlnx,is-bidir = <0x0>;
  214. xlnx,is-bidir-2 = <0x1>;
  215. xlnx,is-dual = <0x0>;
  216. xlnx,tri-default = <0xffffffff>;
  217. xlnx,tri-default-2 = <0xffffffff>;
  218. };
  219. serial@84000000 {
  220. clock-frequency = <0x3b9aca0>;
  221. compatible = "xlnx,xps-uartlite-1.00.a";
  222. current-speed = <0x1c200>;
  223. device_type = "serial";
  224. interrupt-parent = <0x1>;
  225. interrupts = <0x3 0x0>;
  226. port-number = <0x0>;
  227. reg = <0x84000000 0x10000>;
  228. xlnx,baudrate = <0x1c200>;
  229. xlnx,data-bits = <0x8>;
  230. xlnx,family = "spartan3adsp";
  231. xlnx,odd-parity = <0x0>;
  232. xlnx,use-parity = <0x0>;
  233. };
  234. debug@84400000 {
  235. compatible = "xlnx,mdm-1.00.d";
  236. reg = <0x84400000 0x10000>;
  237. xlnx,family = "spartan3adsp";
  238. xlnx,interconnect = <0x1>;
  239. xlnx,jtag-chain = <0x2>;
  240. xlnx,mb-dbg-ports = <0x1>;
  241. xlnx,uart-width = <0x8>;
  242. xlnx,use-uart = <0x1>;
  243. xlnx,write-fsl-ports = <0x0>;
  244. };
  245. mpmc@90000000 {
  246. #address-cells = <0x1>;
  247. #size-cells = <0x1>;
  248. compatible = "xlnx,mpmc-4.03.a";
  249. };
  250. interrupt-controller@81800000 {
  251. #interrupt-cells = <0x2>;
  252. compatible = "xlnx,xps-intc-1.00.a";
  253. interrupt-controller;
  254. reg = <0x81800000 0x10000>;
  255. xlnx,kind-of-intr = <0xa>;
  256. xlnx,num-intr-inputs = <0x4>;
  257. linux,phandle = <0x1>;
  258. };
  259. timer@83c00000 {
  260. compatible = "xlnx,xps-timer-1.00.a";
  261. interrupt-parent = <0x1>;
  262. interrupts = <0x0 0x2>;
  263. reg = <0x83c00000 0x10000>;
  264. xlnx,count-width = <0x20>;
  265. xlnx,family = "spartan3adsp";
  266. xlnx,gen0-assert = <0x1>;
  267. xlnx,gen1-assert = <0x1>;
  268. xlnx,one-timer-only = <0x0>;
  269. xlnx,trig0-assert = <0x1>;
  270. xlnx,trig1-assert = <0x1>;
  271. };
  272. };
  273. };