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@@ -0,0 +1,114 @@
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+From ef8fe0487b236c70ee33856ca1a97b1df3043217 Mon Sep 17 00:00:00 2001
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+From: Damien Le Moal <damien.lemoal@wdc.com>
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+Date: Wed, 9 Sep 2020 17:31:33 +0900
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+Subject: [PATCH] elf2flt: add riscv 64-bits support
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+
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+Add support for riscv 64bits ISA by defining the relocation types
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+R_RISCV_32_PCREL, R_RISCV_ADD32, R_RISCV_SUB32, R_RISCV_32 and
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+R_RISCV_64. riscv64 support also needs the __global_pointer$ symbol to
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+be defined right after the relocation tables in the data section. To
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+define this symbol, the "RISCV_GP" line prefix is added. The "RISCV_GP"
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+string is removed if the target CPU type is riscv64 and the definition
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+line is dropped for other CPU types.
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+
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+With these changes, buildroot and busybox build and run on riscv NOMMU
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+systems with Linux kernel including patch 6045ab5fea4c
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+("binfmt_flat: do not stop relocating GOT entries prematurely on riscv")
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+fixing the binfmt_flat loader. Tested on QEMU and Canaan Kendryte K210
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+boards.
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+
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+This patch is based on earlier work by Christoph Hellwig <hch@lst.de>.
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+
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+Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
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+Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
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+---
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+ elf2flt.c | 26 ++++++++++++++++++++++++++
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+ elf2flt.ld.in | 1 +
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+ ld-elf2flt.c | 8 ++++++++
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+ 3 files changed, 35 insertions(+)
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+
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+diff --git a/elf2flt.c b/elf2flt.c
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+index 3c9f4d0..dfdced4 100644
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+--- a/elf2flt.c
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+@@ -81,6 +81,8 @@ const char *elf2flt_progname;
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+ #include <elf/v850.h>
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+ #elif defined(TARGET_xtensa)
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+ #include <elf/xtensa.h>
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++#elif defined(TARGET_riscv64)
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++#include <elf/riscv.h>
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+ #endif
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+
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+ #if defined(__MINGW32__)
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+@@ -123,6 +125,8 @@ const char *elf2flt_progname;
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+ #define ARCH "nios2"
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+ #elif defined(TARGET_xtensa)
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+ #define ARCH "xtensa"
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++#elif defined(TARGET_riscv64)
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++#define ARCH "riscv64"
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+ #else
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+ #error "Don't know how to support your CPU architecture??"
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+ #endif
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+@@ -818,6 +822,28 @@ output_relocs (
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+ goto good_32bit_resolved_reloc;
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+ default:
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+ goto bad_resolved_reloc;
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++#elif defined(TARGET_riscv64)
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++ case R_RISCV_NONE:
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++ case R_RISCV_32_PCREL:
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++ case R_RISCV_ADD8:
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++ case R_RISCV_ADD16:
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++ case R_RISCV_ADD32:
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++ case R_RISCV_ADD64:
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++ case R_RISCV_SUB6:
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++ case R_RISCV_SUB8:
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++ case R_RISCV_SUB16:
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++ case R_RISCV_SUB32:
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++ case R_RISCV_SUB64:
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++ case R_RISCV_SET6:
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++ case R_RISCV_SET8:
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++ case R_RISCV_SET16:
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++ case R_RISCV_SET32:
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++ continue;
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++ case R_RISCV_32:
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++ case R_RISCV_64:
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++ goto good_32bit_resolved_reloc;
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++ default:
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++ goto bad_resolved_reloc;
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+ #else
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+ default:
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+ /* The default is to assume that the
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+diff --git a/elf2flt.ld.in b/elf2flt.ld.in
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+index d86c0ba..5c5b2ff 100644
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+--- a/elf2flt.ld.in
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+@@ -106,6 +106,7 @@ W_RODAT: *(.gnu.linkonce.r*)
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+ . = ALIGN(0x20) ;
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+ LONG(-1)
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+ . = ALIGN(0x20) ;
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++RISCV_GP: __global_pointer$ = . + 0x800 ;
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+ R_RODAT: *(.rodata)
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+ R_RODAT: *(.rodata1)
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+ R_RODAT: *(.rodata.*)
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+diff --git a/ld-elf2flt.c b/ld-elf2flt.c
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+index 7cb02d5..75ee1bb 100644
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+--- a/ld-elf2flt.c
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+@@ -324,6 +324,14 @@ static int do_final_link(void)
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+ append_option(&other_options, concat(got_offset, "=", buf, NULL));
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+ }
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+
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++ /* riscv adds a global pointer symbol to the linker file with the
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++ "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
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++ the entire line for other architectures. */
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++ if (streq(TARGET_CPU, "riscv64"))
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++ append_sed(&sed, "^RISCV_GP:", "");
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++ else
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++ append_sed(&sed, "^RISCV_GP:", NULL);
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++
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+ /* Locate the default linker script, if we don't have one provided. */
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+ if (!linker_script)
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+ linker_script = concat(ldscriptpath, "/elf2flt.ld", NULL);
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+--
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+2.39.2
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+
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