add support for tilepro/tilegx toolchain, tilepro is broken

target/config/Config.in.cpu

@@ -997,7 +997,12 @@ config ADK_CPU_SPARC_V9
 	select ADK_TARGET_WITH_NPTL
 	select ADK_TARGET_WITH_MMU
 
-config ADK_CPU_TILE
+config ADK_CPU_TILEPRO
+	bool
+	select ADK_TARGET_WITH_NPTL
+	select ADK_TARGET_WITH_MMU
+
+config ADK_CPU_TILEGX
 	bool
 	select ADK_TARGET_WITH_NPTL
 	select ADK_TARGET_WITH_MMU
@@ -1255,6 +1260,8 @@ config ADK_TARGET_CPU_FLAGS
 	default "-m4a" if ADK_CPU_SH4A
 	default "-mcpu=powerpc64" if ADK_CPU_PPC64 && ADK_TARGET_BIG_ENDIAN
 	default "-mcpu=powerpc64le" if ADK_CPU_PPC64 && ADK_TARGET_LITTLE_ENDIAN
+	default "-mcpu=tilegx" if ADK_CPU_TILEGX
+	default "-mcpu=tilepro" if ADK_CPU_TILEPRO
 
 config ADK_TARGET_CPU_TYPE
 	string
@@ -1383,7 +1390,8 @@ config ADK_TARGET_CPU_ARCH
 	default "sh4aeb" if ADK_CPU_SH4A && ADK_TARGET_BIG_ENDIAN
 	default "sparc" if ADK_TARGET_ARCH_SPARC
 	default "sparc64" if ADK_TARGET_ARCH_SPARC64
-	default "tilegx" if ADK_TARGET_ARCH_TILE
+	default "tilegx" if ADK_CPU_TILEGX
+	default "tilepro" if ADK_CPU_TILEPRO
 	default "v850" if ADK_TARGET_ARCH_V850
 	default "x86_64" if ADK_TARGET_ARCH_X86_64
 	default "xtensa" if ADK_TARGET_ARCH_XTENSA

target/config/Config.in.tc

@@ -15,6 +15,7 @@ depends on (ADK_TARGET_TOOLCHAIN || ADK_TARGET_SIM || ADK_TARGET_SYSTEM_GENERIC_
 	|| ADK_TARGET_ARCH_PPC64 \
 	|| ADK_TARGET_ARCH_SH \
 	|| ADK_TARGET_ARCH_SPARC \
+	|| ADK_TARGET_ARCH_TILE \
 	|| ADK_TARGET_ARCH_X86 \
 	|| ADK_TARGET_ARCH_X86_64 )
 
@@ -500,6 +501,16 @@ config ADK_TARGET_CPU_SPARC_LEON
 	select ADK_CPU_SPARC_LEON
 	depends on ADK_TARGET_ARCH_SPARC
 
+config ADK_TARGET_CPU_TILE_TILEGX
+	bool "tilegx"
+	select ADK_CPU_TILEGX
+	depends on ADK_TARGET_ARCH_TILE
+
+config ADK_TARGET_CPU_TILE_TILEPRO
+	bool "tilepro"
+	select ADK_CPU_TILEPRO
+	depends on ADK_TARGET_ARCH_TILE
+
 config ADK_TARGET_CPU_X86_I486
 	bool "i486"
 	select ADK_CPU_I486

toolchain/gcc/patches/5.3.0/tile-fix-libgcc.patch

@@ -1,6 +1,6 @@
-diff -Nur gcc-5.2.0.orig/gcc/config/tilegx/linux.h gcc-5.2.0/gcc/config/tilegx/linux.h
---- gcc-5.2.0.orig/gcc/config/tilegx/linux.h	2015-01-05 13:33:28.000000000 +0100
-+++ gcc-5.2.0/gcc/config/tilegx/linux.h	2015-12-02 15:13:59.563521746 +0100
+diff -Nur gcc-5.3.0.orig/gcc/config/tilegx/linux.h gcc-5.3.0/gcc/config/tilegx/linux.h
+--- gcc-5.3.0.orig/gcc/config/tilegx/linux.h	2015-01-05 13:33:28.000000000 +0100
++++ gcc-5.3.0/gcc/config/tilegx/linux.h	2016-01-25 12:53:51.975221940 +0100
 @@ -55,8 +55,6 @@
  /* For __clear_cache in libgcc2.c.  */
  #ifdef IN_LIBGCC2
@@ -10,9 +10,21 @@ diff -Nur gcc-5.2.0.orig/gcc/config/tilegx/linux.h gcc-5.2.0/gcc/config/tilegx/l
  /* Use the minimum page size of 4K.  Alternatively we can call
     getpagesize() but it introduces a libc dependence.  */
  #undef CLEAR_INSN_CACHE
-diff -Nur gcc-5.2.0.orig/libgcc/config/tilepro/atomic.h gcc-5.2.0/libgcc/config/tilepro/atomic.h
---- gcc-5.2.0.orig/libgcc/config/tilepro/atomic.h	2015-01-05 13:33:28.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/tilepro/atomic.h	2015-12-02 15:41:08.868942210 +0100
+diff -Nur gcc-5.3.0.orig/gcc/config/tilepro/linux.h gcc-5.3.0/gcc/config/tilepro/linux.h
+--- gcc-5.3.0.orig/gcc/config/tilepro/linux.h	2015-01-05 13:33:28.000000000 +0100
++++ gcc-5.3.0/gcc/config/tilepro/linux.h	2016-01-25 12:56:33.687363200 +0100
+@@ -47,8 +47,6 @@
+ /* For __clear_cache in libgcc2.c.  */
+ #ifdef IN_LIBGCC2
+ 
+-#include <arch/icache.h>
+-
+ /* Use the minimum page size of 4K.  Alternatively we can call getpagesize()
+    but it introduces a libc dependence.  */
+ #undef CLEAR_INSN_CACHE
+diff -Nur gcc-5.3.0.orig/libgcc/config/tilepro/atomic.h gcc-5.3.0/libgcc/config/tilepro/atomic.h
+--- gcc-5.3.0.orig/libgcc/config/tilepro/atomic.h	2015-01-05 13:33:28.000000000 +0100
++++ gcc-5.3.0/libgcc/config/tilepro/atomic.h	2016-01-25 13:16:09.116389975 +0100
 @@ -46,6 +46,11 @@
     The "exchange" and "compare and exchange" macros may also take
     pointer values.  We use the pseudo-type "VAL" in the documentation
@@ -25,17 +37,22 @@ diff -Nur gcc-5.2.0.orig/libgcc/config/tilepro/atomic.h gcc-5.2.0/libgcc/config/
  #else
  /* Atomic instruction macros
  
-@@ -92,13 +97,6 @@
+@@ -90,14 +95,12 @@
+    syscall, as is the 64-bit compare-and-exchange.  The other 64-bit
+    routines are implemented by looping over the 64-bit
     compare-and-exchange routine, so may be potentially less efficient.  */
- #endif
+-#endif
  
 -#ifdef __tilegx__
 -#include <arch/spr_def.h>
 -#else
 -#include <asm/unistd.h>
 -#endif
--
--
++#define __NR_FAST_cmpxchg	-1
++#define __NR_FAST_atomic_update	-2
++#define __NR_FAST_cmpxchg64	-3
+ 
++#endif
+ 
  /* 32-bit integer compare-and-exchange.  */
  static __inline __attribute__ ((always_inline))
-      int arch_atomic_val_compare_and_exchange_4 (volatile int *mem,