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@@ -0,0 +1,114 @@
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+From b6506973a202de45561a8f52cd20b17453b77c14 Mon Sep 17 00:00:00 2001
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+From: ramin <lordrasmus@gmail.com>
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+Date: Mon, 24 Aug 2026 13:03:05 +0200
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+Subject: [PATCH] m68k: use the kernel helper on every core without CAS, not
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+ just ColdFire
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+
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+The atomic header split the world into ColdFire and "the rest", assuming the
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+rest was 68020 and up. That holds for the MMU port, but not for the 68000 and
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+68010, which have no atomic read-modify-write instruction either. Building for
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+one of them stops at the first cas:
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+
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+ Error: invalid instruction for this architecture; needs 68020 or higher
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+ (68020 [68k, 68ec020], 68030 [68ec030], 68040 [68ec040],
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+ 68060 [68ec060]) -- statement `cas.l %d0,%d1,(%a1)' ignored
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+
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+Reported by Waldemar Brodkorb from a Buildroot autobuilder failure; Buildroot
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+supports m68000 and has at least one user on it.
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+
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+Decide by the presence of CAS instead. The instruction came with the 68020, so
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+the test is the list of the 68020-and-up cores: gcc defines a separate macro
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+per core and does not imply __mc68020__ on the later ones, and __mc68000__ is
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+no help because it is defined on every m68k, the 68040 and ColdFire included.
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+
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+Nothing else changes: the kernel's atomic_cmpxchg_32 is syscall 335 "common"
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+in arch/m68k/kernel/syscalls/syscall.tbl and has an implementation for the MMU
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+as well as the noMMU port, so the branch the old cores now take is the one
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+ColdFire has been using all along - including its documented limit that the
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+8- and 16-bit variants stay non-atomic, since the helper is 32-bit only.
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+
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+Checked with a cross gcc over -m68000, -m68010, -m68020, -m68030, -m68040,
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+-m68060, -mcpu=5206 and -mcpu=5208: the three old cores and both ColdFires
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+select the helper, the four others select cas, and each branch assembles for
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+the cores that select it.
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+
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+Signed-off-by: Ramin Moussavi <ramin.moussavi@yacoub.de>
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+---
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+ libc/sysdeps/linux/m68k/bits/atomic.h | 32 ++++++++++++++++++---------
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+ 1 file changed, 22 insertions(+), 10 deletions(-)
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+
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+diff --git a/libc/sysdeps/linux/m68k/bits/atomic.h b/libc/sysdeps/linux/m68k/bits/atomic.h
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+index cf7fd5f65..6acec1ed8 100644
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+--- a/libc/sysdeps/linux/m68k/bits/atomic.h
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++++ b/libc/sysdeps/linux/m68k/bits/atomic.h
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+@@ -3,13 +3,15 @@
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+
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+ Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
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+
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+- m68k (68020 and up, which is everything the MMU Linux port runs on) has
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+- the CAS instruction. We implement the compare-and-exchange primitive
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+- with cas.b/cas.w/cas.l; include/atomic.h derives every higher-level
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+- operation from it.
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++ The CAS instruction arrived with the 68020. Where it exists we implement
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++ the compare-and-exchange primitive with cas.b/cas.w/cas.l and let
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++ include/atomic.h derive every higher-level operation from it.
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+
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+- ColdFire has no CAS at all, so there we use the kernel's
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+- atomic_cmpxchg_32 helper, which exists for exactly this reason.
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++ ColdFire, 68000 and 68010 have no atomic read-modify-write instruction at
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++ all. There we use the kernel's atomic_cmpxchg_32 helper, which exists for
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++ exactly this reason and is available on every m68k (syscall 335, "common"
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++ in arch/m68k/kernel/syscalls/syscall.tbl, with an implementation for both
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++ the MMU and the noMMU port).
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+
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+ Without this file m68k fell back to the generic non-atomic
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+ bits/atomic.h, whose "atomic" compare-and-exchange is a plain
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+@@ -22,7 +24,17 @@
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+ #define _M68K_BITS_ATOMIC_H 1
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+
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+ #include <stdint.h>
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+-#ifdef __mcoldfire__
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++
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++/* CAS came with the 68020. gcc sets a separate macro per core and does not
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++ imply __mc68020__ on the later ones, hence the list; __mc68000__ is no help
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++ here, it is defined on every m68k, the 68040 and ColdFire included.
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++ Everything without CAS - ColdFire, 68000, 68010 - uses the kernel helper. */
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++#if defined __mc68020__ || defined __mc68030__ \
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++ || defined __mc68040__ || defined __mc68060__
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++# define __M68K_HAVE_CAS 1
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++#endif
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++
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++#ifndef __M68K_HAVE_CAS
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+ # include <sys/syscall.h>
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+ #endif
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+
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+@@ -58,7 +70,7 @@ typedef uintmax_t uatomic_max_t;
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+ #define atomic_read_barrier() atomic_full_barrier ()
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+ #define atomic_write_barrier() atomic_full_barrier ()
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+
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+-#ifndef __mcoldfire__
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++#ifdef __M68K_HAVE_CAS
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+
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+ /* cas Dc,Du,<ea>: compare <ea> with Dc; if equal store Du, else load <ea>
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+ into Dc. Either way Dc ends up holding the original *MEM, which is the
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+@@ -87,7 +99,7 @@ typedef uintmax_t uatomic_max_t;
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+ : "memory"); \
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+ __ret; })
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+
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+-#else /* __mcoldfire__ */
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++#else /* !__M68K_HAVE_CAS */
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+
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+ /* d0 = syscall number, d1 = newval, d2 = oldval, a0 = mem; the helper
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+ returns the previous value. The swap happens inside the syscall, so
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+@@ -116,7 +128,7 @@ typedef uintmax_t uatomic_max_t;
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+ #define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
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+ __arch_compare_and_exchange_val_8_acq (mem, newval, oldval)
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+
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+-#endif /* __mcoldfire__ */
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++#endif /* __M68K_HAVE_CAS */
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+
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+ /* m68k has no 64-bit CAS; NPTL and include/atomic.h only use int- and
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+ pointer-sized objects, so the bysize dispatch never reaches this. */
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+--
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+2.53.0
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+
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