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@@ -0,0 +1,342 @@
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+diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.c gcc-6.2.0/gcc/config/sh/sh.c
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+--- gcc-6.2.0.orig/gcc/config/sh/sh.c 2016-04-22 13:09:22.000000000 +0200
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++++ gcc-6.2.0/gcc/config/sh/sh.c 2016-12-10 19:58:58.649784537 +0100
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+@@ -692,6 +692,7 @@
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+ model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
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+ model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
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+ model_names[sh_atomic_model::soft_imask] = "soft-imask";
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++ model_names[sh_atomic_model::hard_cas] = "hard-cas";
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+
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+ const char* model_cdef_names[sh_atomic_model::num_models];
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+ model_cdef_names[sh_atomic_model::none] = "NONE";
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+@@ -699,6 +700,7 @@
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+ model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
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+ model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
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+ model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
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++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
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+
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+ sh_atomic_model ret;
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+ ret.type = sh_atomic_model::none;
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+@@ -780,6 +782,9 @@
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+ if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
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+ err_ret ("cannot use atomic model %s in user mode", ret.name);
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+
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++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
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++ err_ret ("atomic model %s is only available J2 targets", ret.name);
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++
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+ return ret;
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+
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+ #undef err_ret
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+@@ -845,6 +850,8 @@
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+ sh_cpu = PROCESSOR_SH2E;
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+ if (TARGET_SH2A)
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+ sh_cpu = PROCESSOR_SH2A;
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++ if (TARGET_SHJ2)
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++ sh_cpu = PROCESSOR_SHJ2;
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+ if (TARGET_SH3)
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+ sh_cpu = PROCESSOR_SH3;
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+ if (TARGET_SH3E)
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+diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.h gcc-6.2.0/gcc/config/sh/sh.h
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+--- gcc-6.2.0.orig/gcc/config/sh/sh.h 2016-01-04 15:30:50.000000000 +0100
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++++ gcc-6.2.0/gcc/config/sh/sh.h 2016-12-10 19:58:58.649784537 +0100
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+@@ -106,6 +106,7 @@
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+ #define SUPPORT_SH4_SINGLE 1
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+ #define SUPPORT_SH2A 1
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+ #define SUPPORT_SH2A_SINGLE 1
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++#define SUPPORT_SHJ2 1
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+ #endif
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+
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+ #define TARGET_DIVIDE_INV \
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+@@ -157,6 +158,7 @@
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+ #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
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+ #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
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+ #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
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++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
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+
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+ #if SUPPORT_SH1
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+ #define SUPPORT_SH2 1
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+@@ -164,6 +166,7 @@
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+ #if SUPPORT_SH2
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+ #define SUPPORT_SH3 1
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+ #define SUPPORT_SH2A_NOFPU 1
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++#define SUPPORT_SHJ2 1
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+ #endif
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+ #if SUPPORT_SH3
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+ #define SUPPORT_SH4_NOFPU 1
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+@@ -211,7 +214,7 @@
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+ #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
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+ | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
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+ | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
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+- | MASK_FPU_SINGLE_ONLY)
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++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
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+
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+ /* This defaults us to big-endian. */
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+ #ifndef TARGET_ENDIAN_DEFAULT
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+@@ -289,8 +292,8 @@
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+ %{m5-compact*:--isa=SHcompact} \
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+ %{m5-32media*:--isa=SHmedia --abi=32} \
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+ %{m5-64media*:--isa=SHmedia --abi=64} \
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+-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
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+-
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++%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \
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++%{mj2:-isa=j2}"
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+ #define ASM_SPEC SH_ASM_SPEC
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+
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+ #ifndef SUBTARGET_ASM_ENDIAN_SPEC
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+@@ -1853,7 +1856,7 @@
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+
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+ /* Nonzero if the target supports dynamic shift instructions
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+ like shad and shld. */
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+-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
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++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
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+
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+ /* The cost of using the dynamic shift insns (shad, shld) are the same
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+ if they are available. If they are not available a library function will
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+@@ -2185,6 +2188,7 @@
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+ PROCESSOR_SH2,
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+ PROCESSOR_SH2E,
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+ PROCESSOR_SH2A,
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++ PROCESSOR_SHJ2,
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+ PROCESSOR_SH3,
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+ PROCESSOR_SH3E,
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+ PROCESSOR_SH4,
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+diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.opt gcc-6.2.0/gcc/config/sh/sh.opt
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+--- gcc-6.2.0.orig/gcc/config/sh/sh.opt 2016-01-04 15:30:50.000000000 +0100
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++++ gcc-6.2.0/gcc/config/sh/sh.opt 2016-12-10 19:58:58.649784537 +0100
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+@@ -71,6 +71,10 @@
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+ Target RejectNegative Condition(SUPPORT_SH2E)
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+ Generate SH2e code.
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+
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++mj2
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++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
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++Generate J2 code.
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++
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+ m3
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+ Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
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+ Generate SH3 code.
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+diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh-protos.h gcc-6.2.0/gcc/config/sh/sh-protos.h
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+--- gcc-6.2.0.orig/gcc/config/sh/sh-protos.h 2016-01-04 15:30:50.000000000 +0100
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++++ gcc-6.2.0/gcc/config/sh/sh-protos.h 2016-12-10 19:58:58.641785064 +0100
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+@@ -45,6 +45,7 @@
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+ hard_llcs,
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+ soft_tcb,
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+ soft_imask,
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++ hard_cas,
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+
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+ num_models
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+ };
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+@@ -88,6 +89,9 @@
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+ #define TARGET_ATOMIC_SOFT_IMASK \
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+ (selected_atomic_model ().type == sh_atomic_model::soft_imask)
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+
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++#define TARGET_ATOMIC_HARD_CAS \
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++ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
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++
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+ #ifdef RTX_CODE
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+ extern rtx sh_fsca_sf2int (void);
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+ extern rtx sh_fsca_int2sf (void);
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+diff -Nur gcc-6.2.0.orig/gcc/config/sh/sync.md gcc-6.2.0/gcc/config/sh/sync.md
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+--- gcc-6.2.0.orig/gcc/config/sh/sync.md 2016-01-04 15:30:50.000000000 +0100
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++++ gcc-6.2.0/gcc/config/sh/sync.md 2016-12-10 19:58:58.649784537 +0100
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+@@ -240,6 +240,9 @@
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+ || (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
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+ atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
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+ exp_val, new_val);
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++ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
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++ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
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++ exp_val, new_val);
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+ else if (TARGET_ATOMIC_SOFT_GUSA)
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+ atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
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+ exp_val, new_val);
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+@@ -306,6 +309,57 @@
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+ }
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+ [(set_attr "length" "14")])
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+
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++(define_expand "atomic_compare_and_swapsi_cas"
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++ [(set (match_operand:SI 0 "register_operand" "=r")
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++ (unspec_volatile:SI
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++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
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++ (match_operand:SI 2 "register_operand" "r")
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++ (match_operand:SI 3 "register_operand" "r")]
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++ UNSPECV_CMPXCHG_1))]
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++ "TARGET_ATOMIC_HARD_CAS"
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++{
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++ rtx mem = gen_rtx_REG (SImode, 0);
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++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
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++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
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++ DONE;
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++})
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++
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++(define_insn "shj2_cas"
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++ [(set (match_operand:SI 0 "register_operand" "=&r")
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++ (unspec_volatile:SI
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++ [(match_operand:SI 1 "register_operand" "=r")
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++ (match_operand:SI 2 "register_operand" "r")
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++ (match_operand:SI 3 "register_operand" "0")]
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++ UNSPECV_CMPXCHG_1))
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++ (set (reg:SI T_REG)
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++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
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++ "TARGET_ATOMIC_HARD_CAS"
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++ "cas.l %2,%0,@%1"
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++ [(set_attr "length" "2")]
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++)
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++
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++(define_expand "atomic_compare_and_swapqi_cas"
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++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
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++ (unspec_volatile:SI
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++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
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++ (match_operand:SI 2 "arith_operand" "rI08")
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++ (match_operand:SI 3 "arith_operand" "rI08")]
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++ UNSPECV_CMPXCHG_1))]
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++ "TARGET_ATOMIC_HARD_CAS"
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++{FAIL;}
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++)
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++
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++(define_expand "atomic_compare_and_swaphi_cas"
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++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
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++ (unspec_volatile:SI
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++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
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++ (match_operand:SI 2 "arith_operand" "rI08")
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++ (match_operand:SI 3 "arith_operand" "rI08")]
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++ UNSPECV_CMPXCHG_1))]
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++ "TARGET_ATOMIC_HARD_CAS"
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++{FAIL;}
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++)
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++
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+ ;; The QIHImode llcs patterns modify the address register of the memory
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+ ;; operand. In order to express that, we have to open code the memory
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+ ;; operand. Initially the insn is expanded like every other atomic insn
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+diff -Nur gcc-6.2.0.orig/gcc/config/sh/t-sh gcc-6.2.0/gcc/config/sh/t-sh
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+--- gcc-6.2.0.orig/gcc/config/sh/t-sh 2016-01-04 15:30:50.000000000 +0100
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++++ gcc-6.2.0/gcc/config/sh/t-sh 2016-12-10 19:58:58.649784537 +0100
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+@@ -52,7 +52,7 @@
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+ m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
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+ m4,m4-100,m4-200,m4-300,m4a \
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+ m5-32media,m5-compact,m5-32media \
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+- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
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++ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \
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+ subst= ; \
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+ for lib in `echo $$abi|tr , ' '` ; do \
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+ if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
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+@@ -65,9 +65,9 @@
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+
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+ # SH1 and SH2A support big endian only.
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+ ifeq ($(DEFAULT_ENDIAN),ml)
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+-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
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++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
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+ else
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+-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
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++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
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+ endif
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+
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+ MULTILIB_OSDIRNAMES = \
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+@@ -96,6 +96,7 @@
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+ m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
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+ m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
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+ m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
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++ mj2=!j2
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+
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+ $(out_object_file): gt-sh.h
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+ gt-sh.h : s-gtype ; @true
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+diff -Nur gcc-6.2.0.orig/gcc/config.gcc gcc-6.2.0/gcc/config.gcc
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+--- gcc-6.2.0.orig/gcc/config.gcc 2016-06-08 15:34:25.000000000 +0200
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++++ gcc-6.2.0/gcc/config.gcc 2016-12-10 19:58:58.641785064 +0100
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+@@ -471,7 +471,7 @@
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+ extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
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+ ;;
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|
+ # Note the 'l'; we need to be able to match e.g. "shle" or "shl".
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+-sh[123456789lbe]*-*-* | sh-*-*)
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|
++sh[123456789lbej]*-*-* | sh-*-*)
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+ cpu_type=sh
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|
+ extra_options="${extra_options} fused-madd.opt"
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|
+ extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
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|
|
+@@ -2613,19 +2613,19 @@
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|
+ extra_options="${extra_options} s390/tpf.opt"
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|
|
+ tmake_file="${tmake_file} s390/t-s390"
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|
|
+ ;;
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|
+-sh-*-elf* | sh[12346l]*-*-elf* | \
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|
+- sh-*-linux* | sh[2346lbe]*-*-linux* | \
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|
++sh-*-elf* | sh[12346lj]*-*-elf* | \
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|
++ sh-*-linux* | sh[2346lbej]*-*-linux* | \
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|
|
+ sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
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|
|
+ sh64-*-netbsd* | sh64l*-*-netbsd*)
|
|
|
+ tmake_file="${tmake_file} sh/t-sh sh/t-elf"
|
|
|
+ if test x${with_endian} = x; then
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|
|
+ case ${target} in
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|
|
+- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
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|
|
++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
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|
|
+ shbe-*-* | sheb-*-*) with_endian=big,little ;;
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|
|
+ sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
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|
|
+ shl* | sh64l* | sh*-*-linux* | \
|
|
|
+ sh5l* | sh-superh-elf) with_endian=little,big ;;
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|
|
+- sh[1234]*-*-*) with_endian=big ;;
|
|
|
++ sh[j1234]*-*-*) with_endian=big ;;
|
|
|
+ *) with_endian=big,little ;;
|
|
|
+ esac
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|
|
+ fi
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|
|
+@@ -2715,6 +2715,7 @@
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|
|
+ sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
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|
|
+ sh2a*) sh_cpu_target=sh2a ;;
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|
|
+ sh2e*) sh_cpu_target=sh2e ;;
|
|
|
++ shj2*) sh_cpu_target=shj2;;
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|
|
+ sh2*) sh_cpu_target=sh2 ;;
|
|
|
+ *) sh_cpu_target=sh1 ;;
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|
|
+ esac
|
|
|
+@@ -2739,7 +2740,7 @@
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|
|
+ sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
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|
|
+ sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
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|
|
+ sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
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|
+- sh3e | sh3 | sh2e | sh2 | sh1) ;;
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|
|
++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
|
|
|
+ "") sh_cpu_default=${sh_cpu_target} ;;
|
|
|
+ *) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
|
|
|
+ esac
|
|
|
+@@ -2750,9 +2751,9 @@
|
|
|
+ sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
|
|
|
+ sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
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|
|
+ sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
|
|
|
+- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
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++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
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+ sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
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+- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
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++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
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+ esac
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+ if test x$with_fp = xno; then
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+ sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
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+@@ -2770,7 +2771,8 @@
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+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
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+ m5-64media | m5-64media-nofpu | \
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+ m5-32media | m5-32media-nofpu | \
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+- m5-compact | m5-compact-nofpu)
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++ m5-compact | m5-compact-nofpu | \
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++ mj2)
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+ # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
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+ # It is passed to MULTIILIB_OPTIONS verbatim.
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+ TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
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+@@ -2787,7 +2789,7 @@
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+ done
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+ TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
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+ if test x${enable_incomplete_targets} = xyes ; then
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+- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
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++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1"
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+ fi
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+ tm_file="$tm_file ./sysroot-suffix.h"
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+ tmake_file="$tmake_file t-sysroot-suffix"
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+@@ -4268,6 +4270,8 @@
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+ ;;
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+ m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
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+ ;;
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++ mj2)
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++ ;;
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+ *)
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+ echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
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+ echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
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+@@ -4477,7 +4481,7 @@
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+ tmake_file="rs6000/t-rs6000 ${tmake_file}"
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+ ;;
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+
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+- sh[123456ble]*-*-* | sh-*-*)
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++ sh[123456blej]*-*-* | sh-*-*)
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+ c_target_objs="${c_target_objs} sh-c.o"
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+ cxx_target_objs="${cxx_target_objs} sh-c.o"
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+ ;;
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Waldemar Brodkorb