|  | @@ -0,0 +1,66 @@
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														|  | 
 |  | +From 44e34cb50f2d25848a85a59adbc561eee66278e8 Mon Sep 17 00:00:00 2001
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														|  | 
 |  | +From: Yimin Gu <ustcymgu@gmail.com>
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														|  | 
 |  | +Date: Wed, 14 Dec 2022 06:49:46 -0500
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														|  | 
 |  | +Subject: [PATCH] elf2flt: add RISC-V 32-bit support
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														|  | 
 |  | +
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														|  | 
 |  | +Allow elf2flt to work with RISC-V 32-bit targets. With these changes, the
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														|  | 
 |  | +uclibc toolchain and busybox can work fine for rv32 no MMU systems with
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														|  | 
 |  | +no noticable problem.
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														|  | 
 |  | +
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														|  | 
 |  | +Signed-off-by: Charles Lohr <lohr85@gmail.com>
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														|  | 
 |  | +[Rebased onto latest tree for upstreaming]
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														|  | 
 |  | +Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
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														|  | 
 |  | +[Add more ELF relco types and edit commit message]
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														|  | 
 |  | +Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
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														|  | 
 |  | +---
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														|  | 
 |  | + elf2flt.c    | 6 ++++--
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														|  | 
 |  | + ld-elf2flt.c | 2 +-
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														|  | 
 |  | + 2 files changed, 5 insertions(+), 3 deletions(-)
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														|  | 
 |  | +
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														|  | 
 |  | +diff --git a/elf2flt.c b/elf2flt.c
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														|  | 
 |  | +index f37cfa2..04b6b43 100644
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														|  | 
 |  | +--- a/elf2flt.c
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														|  | 
 |  | ++++ b/elf2flt.c
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														|  | 
 |  | +@@ -81,7 +81,7 @@ const char *elf2flt_progname;
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														|  | 
 |  | + #include <elf/v850.h>
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														|  | 
 |  | + #elif defined(TARGET_xtensa)
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														|  | 
 |  | + #include <elf/xtensa.h>
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														|  | 
 |  | +-#elif defined(TARGET_riscv64)
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														|  | 
 |  | ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
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														|  | 
 |  | + #include <elf/riscv.h>
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														|  | 
 |  | + #endif
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														|  | 
 |  | + 
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														|  | 
 |  | +@@ -127,6 +127,8 @@ const char *elf2flt_progname;
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														|  | 
 |  | + #define ARCH	"xtensa"
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														|  | 
 |  | + #elif defined(TARGET_riscv64)
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														|  | 
 |  | + #define ARCH	"riscv64"
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														|  | 
 |  | ++#elif defined(TARGET_riscv32)
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														|  | 
 |  | ++#define ARCH	"riscv32"
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														|  | 
 |  | + #else
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														|  | 
 |  | + #error "Don't know how to support your CPU architecture??"
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														|  | 
 |  | + #endif
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														|  | 
 |  | +@@ -822,7 +824,7 @@ output_relocs (
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														|  | 
 |  | + 					goto good_32bit_resolved_reloc_update_text;
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														|  | 
 |  | + 				default:
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														|  | 
 |  | + 					goto bad_resolved_reloc;
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														|  | 
 |  | +-#elif defined(TARGET_riscv64)
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														|  | 
 |  | ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
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														|  | 
 |  | + 				case R_RISCV_NONE:
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														|  | 
 |  | + 				case R_RISCV_32_PCREL:
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														|  | 
 |  | + 				case R_RISCV_ADD8:
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														|  | 
 |  | +diff --git a/ld-elf2flt.c b/ld-elf2flt.c
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														|  | 
 |  | +index 75ee1bb..68b2a4a 100644
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														|  | 
 |  | +--- a/ld-elf2flt.c
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														|  | 
 |  | ++++ b/ld-elf2flt.c
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														|  | 
 |  | +@@ -327,7 +327,7 @@ static int do_final_link(void)
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														|  | 
 |  | + 	/* riscv adds a global pointer symbol to the linker file with the
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														|  | 
 |  | + 	   "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
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														|  | 
 |  | + 	   the entire line for other architectures. */
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														|  | 
 |  | +-	if (streq(TARGET_CPU, "riscv64"))
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														|  | 
 |  | ++	if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
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														|  | 
 |  | + 		append_sed(&sed, "^RISCV_GP:", "");
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														|  | 
 |  | + 	else
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														|  | 
 |  | + 		append_sed(&sed, "^RISCV_GP:", NULL);
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														|  | 
 |  | +-- 
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														|  | 
 |  | +2.30.2
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														|  | 
 |  | +
 |