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@@ -0,0 +1,282 @@
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+# --- T2-COPYRIGHT-NOTE-BEGIN ---
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+# T2 SDE: package/*/strace/riscv32.patch
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+# Copyright (C) 2021 - 2022 The T2 SDE Project
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+#
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+# This Copyright note is generated by scripts/Create-CopyPatch,
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+# more information can be found in the files COPYING and README.
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+#
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+# This patch file is dual-licensed. It is available under the license the
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+# patched project is licensed under, as long as it is an OpenSource license
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+# as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
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+# of the GNU General Public License version 2 as used by the T2 SDE.
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+# --- T2-COPYRIGHT-NOTE-END ---
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+
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+Signed-off-by: Alistair Francis <alistair.francis at wdc.com>
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+---
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+ Makefile.am | 20 ++++++++--------
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+ configure.ac | 6 ++++-
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+ dist/INSTALL | 2 +-
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+ src/linux/{riscv64 => riscv}/arch_defs_.h | 16 +++++++++++++
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+ src/linux/{riscv64 => riscv}/arch_regs.c | 0
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+ src/linux/riscv/asm_stat.h | 26 +++++++++++++++++++++
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+ src/linux/{riscv64 => riscv}/get_error.c | 0
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+ src/linux/{riscv64 => riscv}/get_scno.c | 0
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+ src/linux/{riscv64 => riscv}/get_syscall_args.c | 0
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+ src/linux/{riscv64 => riscv}/ioctls_arch0.h | 0
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+ src/linux/riscv/ioctls_inc0.h | 7 ++++++
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+ src/linux/{riscv64 => riscv}/raw_syscall.h | 0
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+ src/linux/{riscv64 => riscv}/set_error.c | 0
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+ src/linux/{riscv64 => riscv}/set_scno.c | 0
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+ src/linux/{riscv64 => riscv}/syscallent.h | 8 ++++++-
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+ src/linux/riscv64/ioctls_inc0.h | 1 -
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+ src/riscv.c | 4 ++--
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+ 17 files changed, 74 insertions(+), 16 deletions(-)
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+ create mode 100644 src/linux/riscv/arch_defs_.h
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+ rename src/linux/{riscv64 => src/riscv}/arch_regs.c (100%)
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+ create mode 100644 src/linux/riscv/asm_stat.h
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+ rename src/linux/{riscv64 => src/riscv}/get_error.c (100%)
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+ rename src/linux/{riscv64 => src/riscv}/get_scno.c (100%)
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+ rename src/linux/{riscv64 => src/riscv}/get_syscall_args.c (100%)
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+ rename src/linux/{riscv64 => src/riscv}/ioctls_arch0.h (100%)
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+ create mode 100644 src/linux/riscv/ioctls_inc0.h
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+ rename src/linux/{riscv64 => src/riscv}/raw_syscall.h (100%)
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+ rename src/linux/{riscv64 => src/riscv}/set_error.c (100%)
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+ rename src/linux/{riscv64 => src/riscv}/set_scno.c (100%)
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+ rename src/linux/{riscv64 => src/riscv}/syscallent.h (64%)
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+ delete mode 100644 src/linux/riscv64/ioctls_inc0.h
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+
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+diff --git a/Makefile.am b/Makefile.am
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+index 9c62218f..4955654b 100644
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+--- a/src/Makefile.am
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++++ b/src/Makefile.am
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+@@ -802,19 +802,19 @@ extrA_DIST =
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+ linux/powerpc64le/set_scno.c \
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+ linux/powerpc64le/syscallent.h \
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+ linux/powerpc64le/userent.h \
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+- linux/riscv64/arch_defs_.h \
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+- linux/riscv64/arch_prstatus_regset.c \
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+- linux/riscv64/arch_prstatus_regset.h \
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+- linux/riscv64/arch_regs.c \
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+- linux/riscv64/get_error.c \
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+- linux/riscv64/get_scno.c \
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+- linux/riscv64/get_syscall_args.c \
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+- linux/riscv64/ioctls_arch0.h \
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+- linux/riscv64/ioctls_inc0.h \
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+- linux/riscv64/raw_syscall.h \
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+- linux/riscv64/set_error.c \
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+- linux/riscv64/set_scno.c \
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+- linux/riscv64/syscallent.h \
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++ linux/riscv/arch_defs_.h \
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++ linux/riscv/arch_prstatus_regset.c \
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++ linux/riscv/arch_prstatus_regset.h \
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++ linux/riscv/arch_regs.c \
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++ linux/riscv/get_error.c \
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++ linux/riscv/get_scno.c \
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++ linux/riscv/get_syscall_args.c \
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++ linux/riscv/ioctls_arch0.h \
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++ linux/riscv/ioctls_inc0.h \
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++ linux/riscv/raw_syscall.h \
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++ linux/riscv/set_error.c \
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++ linux/riscv/set_scno.c \
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++ linux/riscv/syscallent.h \
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+ linux/s390/arch_defs_.h \
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+ linux/s390/arch_prstatus_regset.c \
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+ linux/s390/arch_prstatus_regset.h \
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+diff --git a/configure.ac b/configure.ac
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+index dd4f13f4..4a53681c 100644
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+--- a/configure.ac
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++++ b/configure.ac
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+@@ -157,9 +157,12 @@
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+ esac
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+ fi
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+ ;;
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++riscv32*)
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++ arch=riscv
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++ AC_DEFINE([RISCV32], 1, [Define for the RISC-V 32-bit architecture])
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++ ;;
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+ riscv64*)
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+- arch=riscv64
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+- karch=riscv
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++ arch=riscv
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+ AC_DEFINE([RISCV64], 1, [Define for the RISC-V 64-bit architecture])
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+ ;;
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+ s390)
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+diff --git a/dist/INSTALL b/dist/INSTALL
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+index 0d22512b..19e059cf 100644
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+--- a/INSTALL
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++++ b/INSTALL
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+@@ -63,7 +63,7 @@ Taking the aforementioned into account, there are the following requirements:
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+
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+ - gawk (at least version 3)
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+ - Ability to compile for m32 personality (on architectures where it is supported)
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+- - On x86_64, x32, powerpc64, sparc64, riscv64, tile64: gcc -m32
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++ - On x86_64, x32, powerpc64, sparc64, riscv32, riscv64, tile64: gcc -m32
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+ - s390x: gcc -m31
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+ - AArch64: a separate compiler for armv7 EABI
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+ - See information about configuration in "1.3.2. AArch64: AArch32 support"
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+diff --git a/src/linux/riscv64/arch_defs_.h b/src/linux/riscv/arch_defs_.h
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+similarity index 20%
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+rename from src/linux/riscv64/arch_defs_.h
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+rename to src/linux/riscv/arch_defs_.h
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+index 0d22512b..19e059cf 100644
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+--- a/src/linux/riscv64/arch_defs_.h
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++++ b/src/linux/riscv/arch_defs_.h
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+@@ -1 +1,8 @@
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+-#define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV64, 0 }
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++#if defined(RISCV32)
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++# define ARCH_TIMESIZE 64
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++# define HAVE_ARCH_TIME32_SYSCALLS 0
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++# define HAVE_ARCH_OLD_TIME64_SYSCALLS 0
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++# define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV32, 0 }
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++#else
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++# define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV64, 0 }
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++#endif
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+diff --git a/src/linux/riscv64/arch_regs.c b/src/linux/riscv/arch_regs.c
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+similarity index 100%
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+rename from src/linux/riscv64/arch_regs.c
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+rename to src/linux/riscv/arch_regs.c
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+diff --git a/src/linux/riscv/asm_stat.h b/src/linux/riscv/asm_stat.h
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+new file mode 100644
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+index 00000000..73341454
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+--- /dev/null
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++++ b/src/linux/riscv/asm_stat.h
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+@@ -0,0 +1,26 @@
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++/*
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++ * Copyright (c) 2020 The strace developers.
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++ * All rights reserved.
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++ *
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++ * SPDX-License-Identifier: LGPL-2.1-or-later
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++ */
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++
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++#ifndef STRACE_RISCV_ASM_STAT_H
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++# define STRACE_RISCV_ASM_STAT_H
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++
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++# include "linux/generic/asm_stat.h"
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++
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++# if defined(RISCV32)
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++# undef dev_t
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++# undef ino_t
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++# undef off64_t
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++# undef off_t
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++# undef time_t
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++
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++# define dev_t __kernel_loff_t
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++# define ino_t __kernel_loff_t
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++# define off64_t __kernel_off64_t
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++# define off_t __kernel_off64_t
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++# define time_t __kernel_time64_t
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++# endif /* defined(RISCV32) */
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++#endif /* !STRACE_RISCV_ASM_STAT_H */
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+diff --git a/src/linux/riscv64/arch_prstatus_regset.h b/src/linux/riscv/arch_prstatus_regset.h
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+similarity index 100%
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+rename from src/linux/riscv64/arch_prstatus_regset.h
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+rename to src/linux/riscv/arch_prstatus_regset.h
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+diff --git a/src/linux/riscv64/arch_prstatus_regset.c b/src/linux/riscv/arch_prstatus_regset.c
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+similarity index 100%
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+rename from src/linux/riscv64/arch_prstatus_regset.c
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+rename to src/linux/riscv/arch_prstatus_regset.c
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+diff --git a/src/linux/riscv64/get_error.c b/src/linux/riscv/get_error.c
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+similarity index 100%
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+rename from src/linux/riscv64/get_error.c
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+rename to src/linux/riscv/get_error.c
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+diff --git a/src/linux/riscv64/get_scno.c b/src/linux/riscv/get_scno.c
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+similarity index 100%
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+rename from src/linux/riscv64/get_scno.c
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+rename to src/linux/riscv/get_scno.c
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+diff --git a/src/linux/riscv64/get_syscall_args.c b/src/linux/riscv/get_syscall_args.c
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+similarity index 100%
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+rename from src/linux/riscv64/get_syscall_args.c
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+rename to src/linux/riscv/get_syscall_args.c
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+diff --git a/src/linux/riscv64/ioctls_arch0.h b/src/linux/riscv/ioctls_arch0.h
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+similarity index 100%
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+rename from src/linux/riscv64/ioctls_arch0.h
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+rename to src/linux/riscv/ioctls_arch0.h
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+diff --git a/src/linux/riscv/ioctls_inc0.h b/src/linux/riscv/ioctls_inc0.h
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+new file mode 100644
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+index 00000000..cc39332f
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+--- /dev/null
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++++ b/src/linux/riscv/ioctls_inc0.h
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+@@ -0,0 +1,7 @@
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++#if defined(RISCV64)
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++# include "../64/ioctls_inc.h"
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++#elif defined(RISCV32)
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++# include "../32/ioctls_inc.h"
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++#else
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++# error "Unsupported RISC-V xlen"
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++#endif
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+diff --git a/src/linux/riscv64/raw_syscall.h b/src/linux/riscv/raw_syscall.h
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+similarity index 100%
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+rename from src/linux/riscv64/raw_syscall.h
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+rename to src/linux/riscv/raw_syscall.h
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+diff --git a/src/linux/riscv64/set_error.c b/src/linux/riscv/set_error.c
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+similarity index 100%
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+rename from src/linux/riscv64/set_error.c
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+rename to src/linux/riscv/set_error.c
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+diff --git a/src/linux/riscv64/set_scno.c b/src/linux/riscv/set_scno.c
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+similarity index 100%
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+rename from src/linux/riscv64/set_scno.c
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+rename to src/linux/riscv/set_scno.c
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+diff --git a/src/linux/riscv64/syscallent.h b/src/linux/riscv/syscallent.h
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+similarity index 64%
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+rename from src/linux/riscv64/syscallent.h
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+rename to src/linux/riscv/syscallent.h
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+index 60c6ce58..c8fb3b8f 100644
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+--- a/src/linux/riscv64/syscallent.h
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++++ b/src/linux/riscv/syscallent.h
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+@@ -5,7 +5,13 @@
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+ * SPDX-License-Identifier: LGPL-2.1-or-later
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+ */
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+
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+-#include "../64/syscallent.h"
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++#if defined(RISCV64)
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++# include "../64/syscallent.h"
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++#elif defined(RISCV32)
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++# include "../32/syscallent.h"
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++#else
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++# error "Unsupported RISC-V xlen"
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++#endif
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+
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+ /* #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) */
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+ [259] = { 3, TM, SEN(riscv_flush_icache), "riscv_flush_icache" },
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+diff --git a/src/linux/riscv64/ioctls_inc0.h b/src/linux/riscv64/ioctls_inc0.h
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+deleted file mode 100644
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+index f9939faa..00000000
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+--- a/src/linux/riscv64/ioctls_inc0.h
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++++ /dev/null
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+@@ -1 +0,0 @@
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+-#include "../64/ioctls_inc.h"
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+diff --git a/riscv.c b/riscv.c
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+index 825eb293..20094ba5 100644
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+--- a/src/riscv.c
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++++ b/src/riscv.c
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+@@ -9,7 +9,7 @@
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+
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+ #include "defs.h"
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+
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+-#ifdef RISCV64
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++#if defined(RISCV64) || defined(RISCV32)
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+
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+ # include "xlat/riscv_flush_icache_flags.h"
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+
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+@@ -30,4 +30,4 @@ SYS_FUNC(riscv_flush_icache)
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+ return RVAL_DECODED;
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+ }
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+
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+-#endif /* RISCV64 */
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++#endif /* defined(RISCV64) || defined(RISCV32) */
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+--
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+2.25.0
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+
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+--- strace-5.10/src/config.h.in.vanilla 2021-02-13 16:11:28.950662094 +0100
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++++ strace-5.10/src/config.h.in 2021-02-13 16:12:01.681663752 +0100
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+@@ -3776,6 +3779,9 @@
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+ /* Define for the little endian PowerPC64 architecture. */
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+ #undef POWERPC64LE
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+
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++/* Define for the RISC-V 32-bit architecture */
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++#undef RISCV32
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++
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+ /* Define for the RISC-V 64-bit architecture */
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+ #undef RISCV64
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+
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+
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