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+From 665b15088fae61aabbb85ad8dcb60c3fed6c5d50 Mon Sep 17 00:00:00 2001
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+From: Waldemar Brodkorb <wbx@openadk.org>
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+Date: Mon, 14 Feb 2022 11:03:00 +0100
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+Subject: [PATCH] Revert "RISC-V: Updated the default ISA spec to 20191213."
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+
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+This reverts commit aed44286efa8ae8717a77d94b51ac3614e2ca6dc.
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+
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+Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
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+---
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+ bfd/elfxx-riscv.c | 4 +---
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+ gas/config/tc-riscv.c | 2 +-
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+ gas/testsuite/gas/riscv/csr-version-1p10.d | 2 +-
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+ gas/testsuite/gas/riscv/csr-version-1p11.d | 2 +-
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+ gas/testsuite/gas/riscv/csr-version-1p12.d | 2 +-
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+ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 2 +-
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+ gas/testsuite/gas/riscv/option-arch-03.d | 2 +-
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+ gas/testsuite/gas/riscv/option-arch-03.s | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s | 2 +-
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+ ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s | 2 +-
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+ ld/testsuite/ld-riscv-elf/call-relax.d | 2 +-
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+ 18 files changed, 18 insertions(+), 20 deletions(-)
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+
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+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
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+index 9f52bb545ac..8409c0254e5 100644
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+--- a/bfd/elfxx-riscv.c
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++++ b/bfd/elfxx-riscv.c
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+@@ -1562,9 +1562,7 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
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+ rps->error_handler
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+ (_("x ISA extension `%s' must be set with the versions"),
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+ subset);
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+- /* Allow old ISA spec can recognize zicsr and zifencei. */
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+- else if (strcmp (subset, "zicsr") != 0
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+- && strcmp (subset, "zifencei") != 0)
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++ else
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+ rps->error_handler
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+ (_("cannot find default versions of the ISA extension `%s'"),
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+ subset);
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+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
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+index 25908597436..ebb31ec4b5e 100644
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+--- a/gas/config/tc-riscv.c
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++++ b/gas/config/tc-riscv.c
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+@@ -104,7 +104,7 @@ struct riscv_csr_extra
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+
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+ /* Need to sync the version with RISC-V compiler. */
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+ #ifndef DEFAULT_RISCV_ISA_SPEC
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+-#define DEFAULT_RISCV_ISA_SPEC "20191213"
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++#define DEFAULT_RISCV_ISA_SPEC "2.2"
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+ #endif
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+
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+ #ifndef DEFAULT_RISCV_PRIV_SPEC
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+diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
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+index 88da7240a78..ee56ae31f0c 100644
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+--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
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++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
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+@@ -1,4 +1,4 @@
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+-#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10
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++#as: -march=rv64i -mcsr-check -mpriv-spec=1.10
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+ #source: csr.s
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+ #warning_output: csr-version-1p10.l
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+ #objdump: -dr -Mpriv-spec=1.10
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+diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
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+index b40c1d5d6b9..a1d8169d7f7 100644
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+--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
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++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
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+@@ -1,4 +1,4 @@
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+-#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11
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++#as: -march=rv64i -mcsr-check -mpriv-spec=1.11
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+ #source: csr.s
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+ #warning_output: csr-version-1p11.l
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+ #objdump: -dr -Mpriv-spec=1.11
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+diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
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+index fbc30ee2fcc..c4c211829b2 100644
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+--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
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++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
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+@@ -1,4 +1,4 @@
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+-#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12
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++#as: -march=rv64i -mcsr-check -mpriv-spec=1.12
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+ #source: csr.s
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+ #warning_output: csr-version-1p12.l
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+ #objdump: -dr -Mpriv-spec=1.12
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+diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
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+index a96e8c9dbec..01e05ae4fbc 100644
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+--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
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++++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
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+@@ -1,4 +1,4 @@
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+-#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1
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++#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1
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+ #source: csr.s
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+ #warning_output: csr-version-1p9p1.l
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+ #objdump: -dr -Mpriv-spec=1.9.1
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+diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d
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+index 62d7f7d5ed2..b621d036c29 100644
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+--- a/gas/testsuite/gas/riscv/option-arch-03.d
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++++ b/gas/testsuite/gas/riscv/option-arch-03.d
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+@@ -4,5 +4,5 @@
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+
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+ Attribute Section: riscv
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+ File Attributes
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+- Tag_RISCV_arch: "rv32i2p1_c2p0"
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++ Tag_RISCV_arch: "rv32i2p0_c2p0"
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+ #...
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+diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s
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+index ccdb1c354b0..d982a0b0985 100644
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+--- a/gas/testsuite/gas/riscv/option-arch-03.s
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++++ b/gas/testsuite/gas/riscv/option-arch-03.s
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+@@ -1,3 +1,3 @@
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+ .attribute arch, "rv64ic"
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+ .option arch, +d2p0, -c
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+-.option arch, rv32i2p1c2p0
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++.option arch, rv32ic
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
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+index a4b0322a3d9..c148cdbc4f4 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
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+@@ -6,4 +6,4 @@
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+
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+ Attribute Section: riscv
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+ File Attributes
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+- Tag_RISCV_arch: "rv32i2p1_m2p0"
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++ Tag_RISCV_arch: "rv32i2p0_m2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
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+index ea097f99b04..acc98a53cf5 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
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+@@ -1 +1 @@
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+- .attribute arch, "rv32i2p1_m2p0"
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++ .attribute arch, "rv32i2p0_m2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
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+index ea097f99b04..acc98a53cf5 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
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+@@ -1 +1 @@
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+- .attribute arch, "rv32i2p1_m2p0"
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++ .attribute arch, "rv32i2p0_m2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
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+index 852fd55ae08..bc0e0fd1384 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
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+@@ -6,4 +6,4 @@
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+
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+ Attribute Section: riscv
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+ File Attributes
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+- Tag_RISCV_arch: "rv32i2p1_m2p0"
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++ Tag_RISCV_arch: "rv32i2p0_m2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
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+index ea097f99b04..acc98a53cf5 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
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+@@ -1 +1 @@
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+- .attribute arch, "rv32i2p1_m2p0"
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++ .attribute arch, "rv32i2p0_m2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
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+index 610c7e53c1a..65d0fefd5af 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
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+@@ -1 +1 @@
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+- .attribute arch, "rv32i2p1"
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++ .attribute arch, "rv32i2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
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+index c1cf8081dc7..374a043c69e 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
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+@@ -6,4 +6,4 @@
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+
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+ Attribute Section: riscv
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+ File Attributes
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+- Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0"
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++ Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
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+index 3a9fb97ac4e..b86cc558fbf 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
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+@@ -1 +1 @@
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+- .attribute arch, "rv32i2p1_m2p0_xfoo2p0"
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++ .attribute arch, "rv32i2p0_m2p0_xfoo2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
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+index 878f2de8e53..376e3737b2c 100644
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+--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
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++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
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+@@ -1 +1 @@
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+- .attribute arch, "rv32i2p1_xbar2p0"
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++ .attribute arch, "rv32i2p0_xbar2p0"
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+diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
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+index f8f02298232..c6022bec262 100644
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+--- a/ld/testsuite/ld-riscv-elf/call-relax.d
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++++ b/ld/testsuite/ld-riscv-elf/call-relax.d
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+@@ -3,7 +3,7 @@
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+ #source: call-relax-1.s
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+ #source: call-relax-2.s
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+ #source: call-relax-3.s
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+-#as: -march=rv32ic_zicsr -mno-arch-attr
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++#as: -march=rv32ic -mno-arch-attr
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+ #ld: -m[riscv_choose_ilp32_emul]
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+ #objdump: -d
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+ #pass
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+--
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+2.30.2
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+
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