numato-mimas-a7-mini: add basic support

mk/kernel-build.mk

@@ -37,9 +37,15 @@ ifeq ($(ADK_TARGET_KERNEL_IMAGE),y)
 KERNEL_FILE:=vmlinux
 endif
 ifeq ($(ADK_TARGET_KERNEL_SIMPLEIMAGE),y)
+ifeq ($(ADK_TARGET_LINUX_ARCH_LM32),y)
 KERNEL_FILE:=vmlinux.bin
 KERNEL_TARGET:=simpleImage.milkymist_one
 endif
+ifeq ($(ADK_TARGET_SYSTEM_NUMATO_MIMASA7_MINI),y)
+KERNEL_FILE:=vmlinux
+KERNEL_TARGET:=simpleImage.mimasa7_mini
+endif
+endif
 
 ifneq ($(KERNEL_MODULES_USED),)
 KERNEL_TARGET+=modules

package/glibc/Makefile

@@ -50,7 +50,7 @@ do-install:
 ifneq ($(ADK_TARGET_USE_STATIC_LIBS_ONLY),y)
 	${INSTALL_DIR} ${IDIR_GLIBC}/$(ADK_TARGET_LIBC_PATH)
 	$(CP) $(STAGING_TARGET_DIR)/lib/ld*.so* $(IDIR_GLIBC)/$(ADK_TARGET_LIBC_PATH)
-	for file in libc libpthread librt libdl libm libanl libnsl libresolv libutil libnss_dns libnss_files libmvec; do \
+	-for file in libc libpthread librt libdl libm libanl libnsl libresolv libutil libnss_dns libnss_files libmvec; do \
 		$(CP) $(STAGING_TARGET_DIR)/lib/$$file.so* $(IDIR_GLIBC)/$(ADK_TARGET_LIBC_PATH); \
 	done
 else

target/config/Config.in.kernelfmt

@@ -75,6 +75,7 @@ config ADK_TARGET_KERNEL
 	default "xipImage" if ADK_TARGET_KERNEL_XIPIMAGE
 	default "bzImage" if ADK_TARGET_KERNEL_BZIMAGE
 	default "bzImage" if ADK_TARGET_SYSTEM_GENERIC_X86_64 || ADK_TARGET_SYSTEM_GENERIC_X86
+	default "simpleImage.mimasa7_mini" if ADK_TARGET_SYSTEM_NUMATO_MIMASA7_MINI
 	default "vmlinux"
 
 config ADK_TARGET_NO_KERNEL

target/config/Config.in.runtime

@@ -372,7 +372,8 @@ config ADK_RUNTIME_CONSOLE_SERIAL_DEVICE
 	default "hvc0" if ADK_TARGET_SYSTEM_QEMU_PPC64
 	default "ttyBF0" if ADK_TARGET_ARCH_BFIN
 	default "ttyUL0" if ADK_TARGET_SYSTEM_QEMU_MICROBLAZE_S3ADSP1800 \
-				|| ADK_TARGET_SYSTEM_NUMATO_MIMASV2
+				|| ADK_TARGET_SYSTEM_NUMATO_MIMASV2 \
+				|| ADK_TARGET_SYSTEM_NUMATO_MIMASA7_MINI
 	default "ttyAMA0" if ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB \
 				|| ADK_TARGET_SYSTEM_QEMU_ARM_REALVIEW_EB_MPCORE \
 				|| ADK_TARGET_SYSTEM_QEMU_ARM_VEXPRESS_A9 \

target/linux/patches/6.18.18/microblaze-new-gcc.patch

@@ -0,0 +1,83 @@
+diff -Nur linux-6.18.18.orig/arch/microblaze/kernel/entry.S linux-6.18.18/arch/microblaze/kernel/entry.S
+--- linux-6.18.18.orig/arch/microblaze/kernel/entry.S	2026-03-13 17:23:30.000000000 +0100
++++ linux-6.18.18/arch/microblaze/kernel/entry.S	2026-03-27 08:00:11.173928808 +0100
+@@ -339,6 +339,9 @@
+  * Trap entered via brki instruction, so BIP bit is set, and interrupts
+  * are masked. This is nice, means we don't have to CLI before state save
+  */
++
++#define SYSCALL_ARGS_SIZE 36
++
+ C_ENTRY(_user_exception):
+ 	swi	r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
+ 	addi	r14, r14, 4	/* return address is 4 byte after call */
+@@ -422,16 +425,19 @@
+ 	lwi	r12, r12, sys_call_table
+ 	/* where the trap should return need -8 to adjust for rtsd r15, 8 */
+ 	addi	r15, r0, ret_from_trap-8
++	addik 	r1, r1, -SYSCALL_ARGS_SIZE
+ 	bra	r12
+ 
+ 	/* The syscall number is invalid, return an error.  */
+ 5:
+-	braid	ret_from_trap
++	braid	ret_from_trap2
+ 	addi	r3, r0, -ENOSYS;
+ 
+ /* Entry point used to return from a syscall/trap */
+ /* We re-enable BIP bit before state restore */
+ C_ENTRY(ret_from_trap):
++	addik	r1, r1, SYSCALL_ARGS_SIZE
++C_ENTRY(ret_from_trap2):
+ 	swi	r3, r1, PT_R3
+ 	swi	r4, r1, PT_R4
+ 
+@@ -504,7 +510,7 @@
+ 	bralid	r15, schedule_tail; /* ...which is schedule_tail's arg */
+ 	add	r5, r3, r0;	/* switch_thread returns the prev task */
+ 				/* ( in the delay slot ) */
+-	brid	ret_from_trap;	/* Do normal trap return */
++	brid	ret_from_trap2;	/* Do normal trap return */
+ 	add	r3, r0, r0;	/* Child's fork call should return 0. */
+ 
+ C_ENTRY(ret_from_kernel_thread):
+@@ -513,13 +519,13 @@
+ 				/* ( in the delay slot ) */
+ 	brald	r15, r20	/* fn was left in r20 */
+ 	addk	r5, r0, r19	/* ... and argument - in r19 */
+-	brid	ret_from_trap
++	brid	ret_from_trap2
+ 	add	r3, r0, r0
+ 
+ C_ENTRY(sys_rt_sigreturn_wrapper):
+ 	addik	r30, r0, 0		/* no restarts */
+ 	brid	sys_rt_sigreturn	/* Do real work */
+-	addik	r5, r1, 0;		/* add user context as 1st arg */
++	addik	r5, r1, SYSCALL_ARGS_SIZE; /* add user context as 1st arg */
+ 
+ /*
+  * HW EXCEPTION rutine start
+@@ -729,11 +735,13 @@
+ 	lwi	CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
+ 	tovirt(r1,r1)
+ 	addik	r15, r0, irq_call;
++	addik 	r1, r1, -8
+ irq_call:rtbd	r0, do_IRQ;
+-	addik	r5, r1, 0;
++	addik	r5, r1, 8;
+ 
+ /* MS: we are in virtual mode */
+ ret_from_irq:
++	addik 	r1, r1, 8
+ 	lwi	r11, r1, PT_MODE;
+ 	bnei	r11, 2f;
+ 
+@@ -1302,7 +1310,7 @@
+ .global microblaze_trap_handlers
+ microblaze_trap_handlers:
+ 	/* Exact matches come first */
+-	.word ret_from_trap; .word ret_from_trap   ; .word type_SYSCALL
++	.word ret_from_trap; .word ret_from_trap2  ; .word type_SYSCALL
+ 	.word ret_from_irq ; .word ret_from_irq    ; .word type_IRQ
+ 	/* Fuzzy matches go here */
+ 	.word ret_from_irq ; .word no_intr_resched ; .word type_IRQ_PREEMPT

target/linux/patches/6.18.18/numato-mimasa7-mini-dts.patch

@@ -0,0 +1,248 @@
+diff -Nur linux-6.18.18.orig/arch/microblaze/boot/dts/mimasa7_mini.dts linux-6.18.18/arch/microblaze/boot/dts/mimasa7_mini.dts
+--- linux-6.18.18.orig/arch/microblaze/boot/dts/mimasa7_mini.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-6.18.18/arch/microblaze/boot/dts/mimasa7_mini.dts	2026-03-25 06:33:23.647668507 +0100
+@@ -0,0 +1,244 @@
++/*
++ * CAUTION: This file is automatically generated by Xilinx.
++ * Version: XSCT 2022.1
++ * Today is: Wed Mar 25 04:08:33 2026
++ */
++
++/dts-v1/;
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	compatible = "xlnx,microblaze";
++	model = "Xilinx MicroBlaze";
++
++	chosen {
++		bootargs = "earlycon";
++		stdout-path = "serial0:115200n8";
++	};
++	aliases {
++		serial0 = &axi_uartlite_0;
++		spi0 = &axi_quad_spi_0;
++	};
++	memory@80000000 {
++		device_type = "memory";
++		reg = <0x80000000 0x10000000>;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#cpus = <1>;
++		#size-cells = <0>;
++		microblaze_0: cpu@0 {
++			bus-handle = <&amba_pl>;
++			clock-frequency = <100000000>;
++			clocks = <&clk_cpu>;
++			compatible = "xlnx,microblaze-11.0";
++			d-cache-baseaddr = <0x80000000>;
++			d-cache-highaddr = <0x8fffffff>;
++			d-cache-line-size = <0x10>;
++			d-cache-size = <0x4000>;
++			device_type = "cpu";
++			i-cache-baseaddr = <0x80000000>;
++			i-cache-highaddr = <0x8fffffff>;
++			i-cache-line-size = <0x20>;
++			i-cache-size = <0x4000>;
++			interrupt-handle = <&microblaze_0_axi_intc>;
++			model = "microblaze,11.0";
++			reg = <0>;
++			timebase-frequency = <100000000>;
++			xlnx,addr-size = <0x20>;
++			xlnx,addr-tag-bits = <0xe>;
++			xlnx,allow-dcache-wr = <0x1>;
++			xlnx,allow-icache-wr = <0x1>;
++			xlnx,area-optimized = <0x0>;
++			xlnx,async-interrupt = <0x1>;
++			xlnx,async-wakeup = <0x3>;
++			xlnx,avoid-primitives = <0x0>;
++			xlnx,base-vectors = <0x00000000 0x00000000>;
++			xlnx,branch-target-cache-size = <0x0>;
++			xlnx,cache-byte-size = <0x4000>;
++			xlnx,d-axi = <0x1>;
++			xlnx,d-lmb = <0x1>;
++			xlnx,d-lmb-mon = <0x0>;
++			xlnx,d-lmb-protocol = <0x0>;
++			xlnx,daddr-size = <0x20>;
++			xlnx,data-size = <0x20>;
++			xlnx,dc-axi-mon = <0x0>;
++			xlnx,dcache-addr-tag = <0xe>;
++			xlnx,dcache-always-used = <0x0>;
++			xlnx,dcache-byte-size = <0x4000>;
++			xlnx,dcache-data-width = <0x0>;
++			xlnx,dcache-force-tag-lutram = <0x0>;
++			xlnx,dcache-line-len = <0x4>;
++			xlnx,dcache-use-writeback = <0x0>;
++			xlnx,dcache-victims = <0x8>;
++			xlnx,debug-counter-width = <0x20>;
++			xlnx,debug-enabled = <0x1>;
++			xlnx,debug-event-counters = <0x5>;
++			xlnx,debug-external-trace = <0x0>;
++			xlnx,debug-interface = <0x0>;
++			xlnx,debug-latency-counters = <0x1>;
++			xlnx,debug-profile-size = <0x0>;
++			xlnx,debug-trace-async-reset = <0x0>;
++			xlnx,debug-trace-size = <0x2000>;
++			xlnx,div-zero-exception = <0x1>;
++			xlnx,dp-axi-mon = <0x0>;
++			xlnx,dynamic-bus-sizing = <0x0>;
++			xlnx,ecc-use-ce-exception = <0x0>;
++			xlnx,edge-is-positive = <0x1>;
++			xlnx,enable-discrete-ports = <0x0>;
++			xlnx,endianness = <0x1>;
++			xlnx,fault-tolerant = <0x0>;
++			xlnx,fpu-exception = <0x0>;
++			xlnx,freq = <0x5f5e100>;
++			xlnx,fsl-exception = <0x0>;
++			xlnx,fsl-links = <0x0>;
++			xlnx,i-axi = <0x0>;
++			xlnx,i-lmb = <0x1>;
++			xlnx,i-lmb-mon = <0x0>;
++			xlnx,i-lmb-protocol = <0x0>;
++			xlnx,iaddr-size = <0x20>;
++			xlnx,ic-axi-mon = <0x0>;
++			xlnx,icache-always-used = <0x1>;
++			xlnx,icache-data-width = <0x0>;
++			xlnx,icache-force-tag-lutram = <0x0>;
++			xlnx,icache-line-len = <0x8>;
++			xlnx,icache-streams = <0x1>;
++			xlnx,icache-victims = <0x8>;
++			xlnx,ill-opcode-exception = <0x1>;
++			xlnx,imprecise-exceptions = <0x0>;
++			xlnx,instr-size = <0x20>;
++			xlnx,interconnect = <0x2>;
++			xlnx,interrupt-is-edge = <0x0>;
++			xlnx,interrupt-mon = <0x0>;
++			xlnx,ip-axi-mon = <0x0>;
++			xlnx,lmb-data-size = <0x20>;
++			xlnx,lockstep-master = <0x0>;
++			xlnx,lockstep-select = <0x0>;
++			xlnx,lockstep-slave = <0x0>;
++			xlnx,mmu-dtlb-size = <0x4>;
++			xlnx,mmu-itlb-size = <0x2>;
++			xlnx,mmu-privileged-instr = <0x0>;
++			xlnx,mmu-tlb-access = <0x3>;
++			xlnx,mmu-zones = <0x2>;
++			xlnx,num-sync-ff-clk = <0x2>;
++			xlnx,num-sync-ff-clk-debug = <0x2>;
++			xlnx,num-sync-ff-clk-irq = <0x1>;
++			xlnx,num-sync-ff-dbg-clk = <0x1>;
++			xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
++			xlnx,number-of-pc-brk = <0x1>;
++			xlnx,number-of-rd-addr-brk = <0x0>;
++			xlnx,number-of-wr-addr-brk = <0x0>;
++			xlnx,opcode-0x0-illegal = <0x1>;
++			xlnx,optimization = <0x0>;
++			xlnx,pc-width = <0x20>;
++			xlnx,piaddr-size = <0x20>;
++			xlnx,pvr = <0x2>;
++			xlnx,pvr-user1 = <0x00>;
++			xlnx,pvr-user2 = <0x00000000>;
++			xlnx,reset-msr = <0x00000000>;
++			xlnx,reset-msr-bip = <0x0>;
++			xlnx,reset-msr-dce = <0x0>;
++			xlnx,reset-msr-ee = <0x0>;
++			xlnx,reset-msr-eip = <0x0>;
++			xlnx,reset-msr-ice = <0x0>;
++			xlnx,reset-msr-ie = <0x0>;
++			xlnx,sco = <0x0>;
++			xlnx,temporal-depth = <0x0>;
++			xlnx,trace = <0x0>;
++			xlnx,unaligned-exceptions = <0x1>;
++			xlnx,use-barrel = <0x1>;
++			xlnx,use-branch-target-cache = <0x0>;
++			xlnx,use-config-reset = <0x0>;
++			xlnx,use-dcache = <0x1>;
++			xlnx,use-div = <0x1>;
++			xlnx,use-ext-brk = <0x0>;
++			xlnx,use-ext-nm-brk = <0x0>;
++			xlnx,use-extended-fsl-instr = <0x0>;
++			xlnx,use-fpu = <0x0>;
++			xlnx,use-hw-mul = <0x2>;
++			xlnx,use-icache = <0x1>;
++			xlnx,use-interrupt = <0x2>;
++			xlnx,use-mmu = <0x3>;
++			xlnx,use-msr-instr = <0x1>;
++			xlnx,use-non-secure = <0x0>;
++			xlnx,use-pcmp-instr = <0x1>;
++			xlnx,use-reorder-instr = <0x1>;
++			xlnx,use-stack-protection = <0x0>;
++		};
++	};
++	clocks {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		clk_cpu: clk_cpu@0 {
++			#clock-cells = <0>;
++			clock-frequency = <100000000>;
++			clock-output-names = "clk_cpu";
++			compatible = "fixed-clock";
++			reg = <0>;
++		};
++		clk_bus_0: clk_bus_0@1 {
++			#clock-cells = <0>;
++			clock-frequency = <100000000>;
++			clock-output-names = "clk_bus_0";
++			compatible = "fixed-clock";
++			reg = <1>;
++		};
++	};
++	amba_pl: amba_pl {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "simple-bus";
++		ranges ;
++		axi_quad_spi_0: axi_quad_spi@44a00000 {
++			bits-per-word = <8>;
++			compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
++			fifo-size = <0>;
++			num-cs = <0x1>;
++			reg = <0x44a00000 0x10000>;
++			xlnx,num-ss-bits = <0x1>;
++			xlnx,spi-mode = <0>;
++			xlnx,startup-block ;
++		};
++		axi_timer_0: timer@41c00000 {
++			clock-frequency = <100000000>;
++			clocks = <&clk_bus_0>;
++			compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a";
++			interrupt-names = "interrupt";
++			interrupt-parent = <&microblaze_0_axi_intc>;
++			interrupts = <1 2>;
++			reg = <0x41c00000 0x10000>;
++			xlnx,count-width = <0x20>;
++			xlnx,gen0-assert = <0x1>;
++			xlnx,gen1-assert = <0x1>;
++			xlnx,one-timer-only = <0x0>;
++			xlnx,trig0-assert = <0x1>;
++			xlnx,trig1-assert = <0x1>;
++		};
++		axi_uartlite_0: serial@40600000 {
++			clock-frequency = <100000000>;
++			clocks = <&clk_bus_0>;
++			compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a";
++			current-speed = <115200>;
++			device_type = "serial";
++			interrupt-names = "interrupt";
++			interrupt-parent = <&microblaze_0_axi_intc>;
++			interrupts = <0 0>;
++			port-number = <0>;
++			reg = <0x40600000 0x10000>;
++			xlnx,baudrate = <0x1c200>;
++			xlnx,data-bits = <0x8>;
++			xlnx,odd-parity = <0x0>;
++			xlnx,s-axi-aclk-freq-hz-d = "100.0";
++			xlnx,use-parity = <0x0>;
++		};
++		microblaze_0_axi_intc: interrupt-controller@41200000 {
++			#interrupt-cells = <2>;
++			compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
++			interrupt-controller ;
++			reg = <0x41200000 0x10000>;
++			xlnx,kind-of-intr = <0x1>;
++			xlnx,num-intr-inputs = <0x2>;
++		};
++	};
++};

target/microblaze/Makefile

@@ -6,6 +6,9 @@ include $(ADK_TOPDIR)/mk/kernel-build.mk
 include $(ADK_TOPDIR)/mk/image.mk
 
 KERNEL:=$(LINUX_DIR)/arch/microblaze/boot/$(ADK_TARGET_KERNEL)
+ifeq ($(ADK_TARGET_SYSTEM_NUMATO_MIMASA7_MINI),y)
+KERNEL:=$(LINUX_DIR)/arch/microblaze/boot/simpleImage.mimasa7_mini
+endif
 
 QEMU_ARGS:=${ADK_QEMU_ARGS}
 ifeq ($(ADK_TARGET_SYSTEM_QEMU_MICROBLAZE_ML605),y)

target/microblaze/kernel/numato-mimasa7-mini

@@ -0,0 +1,14 @@
+CONFIG_MICROBLAZE=y
+CONFIG_PLATFORM_GENERIC=y
+CONFIG_KERNEL_BASE_ADDR=0x80000000
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_XILINX_MICROBLAZE0_FAMILY="artix7"
+CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
+CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
+CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
+CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
+CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=2
+CONFIG_XILINX_MICROBLAZE0_HW_VER="11.0"
+CONFIG_HZ_100=y
+CONFIG_SERIAL_UARTLITE=y
+CONFIG_SERIAL_UARTLITE_CONSOLE=y

target/microblaze/systems/numato-mimasa7-mini

@@ -0,0 +1,10 @@
+config ADK_TARGET_SYSTEM_NUMATO_MIMASA7_MINI
+	bool "Numato Mimas A7 Mini FPGA"
+	select ADK_TARGET_LITTLE_ENDIAN
+	select ADK_TARGET_WITH_SERIAL
+	select ADK_TARGET_KERNEL_SIMPLEIMAGE
+	select ADK_TARGET_KERNEL_WITH_COMPRESSION
+	select ADK_HOST_BUILD_DTC
+	help
+	  Support for Numato Mimas A7 Mini FPGA.
+