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@@ -0,0 +1,474 @@
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+From d339550fcb6a2048b829634612da96b186d97dfe Mon Sep 17 00:00:00 2001
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+From: Manuel Lauss <manuel.lauss@gmail.com>
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+Date: Fri, 7 Nov 2014 14:13:54 +0100
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+Subject: [PATCH] MIPS: Fix build with binutils 2.24.51+
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+
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+Starting with version 2.24.51.20140728 MIPS binutils complain loudly
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+about mixing soft-float and hard-float object files, leading to this
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+build failure since GCC is invoked with "-msoft-float" on MIPS:
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+
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+{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
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+ LD arch/mips/alchemy/common/built-in.o
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+mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
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+ uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
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+ arch/mips/alchemy/common/sleeper.o uses -mhard-float
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+
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+To fix this, we detect if GAS is new enough to support "-msoft-float" command
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+option, and if it does, we can let GCC pass it to GAS; but then we also need
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+to sprinkle the files which make use of floating point registers with the
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+necessary ".set hardfloat" directives.
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+
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+Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
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+Cc: Linux-MIPS <linux-mips@linux-mips.org>
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+Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
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+Cc: Markos Chandras <Markos.Chandras@imgtec.com>
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+Cc: Maciej W. Rozycki <macro@linux-mips.org>
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+Patchwork: https://patchwork.linux-mips.org/patch/8355/
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+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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+---
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+ arch/mips/Makefile | 9 +++++++++
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+ arch/mips/include/asm/asmmacro-32.h | 6 ++++++
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+ arch/mips/include/asm/asmmacro.h | 7 +++++++
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+ arch/mips/include/asm/fpregdef.h | 14 ++++++++++++++
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+ arch/mips/include/asm/mipsregs.h | 11 ++++++++++-
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+ arch/mips/kernel/branch.c | 2 +-
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+ arch/mips/kernel/genex.S | 1 +
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+ arch/mips/kernel/r2300_fpu.S | 6 ++++++
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+ arch/mips/kernel/r2300_switch.S | 5 +++++
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+ arch/mips/kernel/r4k_fpu.S | 27 +++++++++++++++++++++++++--
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+ arch/mips/kernel/r4k_switch.S | 11 ++++++++++-
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+ arch/mips/kernel/r6000_fpu.S | 5 +++++
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+ arch/mips/math-emu/cp1emu.c | 2 +-
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+ 13 files changed, 100 insertions(+), 6 deletions(-)
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+
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+diff --git a/arch/mips/Makefile b/arch/mips/Makefile
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+index 9b8556d..20f6379 100644
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+--- a/arch/mips/Makefile
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++++ b/arch/mips/Makefile
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+@@ -93,6 +93,15 @@ LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
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+ KBUILD_AFLAGS_MODULE += -mlong-calls
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+ KBUILD_CFLAGS_MODULE += -mlong-calls
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+
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++#
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++# pass -msoft-float to GAS if it supports it. However on newer binutils
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++# (specifically newer than 2.24.51.20140728) we then also need to explicitly
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++# set ".set hardfloat" in all files which manipulate floating point registers.
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++#
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++ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
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++ cflags-y += -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
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++endif
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++
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+ cflags-y += -ffreestanding
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+
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+ #
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+diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
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+index 70e1f17..8038647 100644
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+--- a/arch/mips/include/asm/asmmacro-32.h
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++++ b/arch/mips/include/asm/asmmacro-32.h
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+@@ -13,6 +13,8 @@
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+ #include <asm/mipsregs.h>
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+
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+ .macro fpu_save_single thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 \tmp, fcr31
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+ swc1 $f0, THREAD_FPR0(\thread)
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+ swc1 $f1, THREAD_FPR1(\thread)
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+@@ -47,9 +49,12 @@
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+ swc1 $f30, THREAD_FPR30(\thread)
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+ swc1 $f31, THREAD_FPR31(\thread)
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+ sw \tmp, THREAD_FCR31(\thread)
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++ .set pop
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+ .endm
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+
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+ .macro fpu_restore_single thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ lw \tmp, THREAD_FCR31(\thread)
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+ lwc1 $f0, THREAD_FPR0(\thread)
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+ lwc1 $f1, THREAD_FPR1(\thread)
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+@@ -84,6 +89,7 @@
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+ lwc1 $f30, THREAD_FPR30(\thread)
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+ lwc1 $f31, THREAD_FPR31(\thread)
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+ ctc1 \tmp, fcr31
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++ .set pop
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+ .endm
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+
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+ .macro cpu_save_nonscratch thread
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+diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
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+index 4225e99..d6d5b19 100644
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+--- a/arch/mips/include/asm/asmmacro.h
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++++ b/arch/mips/include/asm/asmmacro.h
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+@@ -74,6 +74,8 @@
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+ #endif /* CONFIG_MIPS_MT_SMTC */
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+
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+ .macro fpu_save_16even thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 \tmp, fcr31
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+ sdc1 $f0, THREAD_FPR0(\thread)
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+ sdc1 $f2, THREAD_FPR2(\thread)
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+@@ -92,11 +94,13 @@
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+ sdc1 $f28, THREAD_FPR28(\thread)
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+ sdc1 $f30, THREAD_FPR30(\thread)
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+ sw \tmp, THREAD_FCR31(\thread)
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++ .set pop
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+ .endm
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+
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+ .macro fpu_save_16odd thread
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+ .set push
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+ .set mips64r2
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++ SET_HARDFLOAT
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+ sdc1 $f1, THREAD_FPR1(\thread)
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+ sdc1 $f3, THREAD_FPR3(\thread)
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+ sdc1 $f5, THREAD_FPR5(\thread)
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+@@ -127,6 +131,8 @@
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+ .endm
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+
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+ .macro fpu_restore_16even thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ lw \tmp, THREAD_FCR31(\thread)
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+ ldc1 $f0, THREAD_FPR0(\thread)
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+ ldc1 $f2, THREAD_FPR2(\thread)
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+@@ -150,6 +156,7 @@
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+ .macro fpu_restore_16odd thread
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+ .set push
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+ .set mips64r2
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++ SET_HARDFLOAT
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+ ldc1 $f1, THREAD_FPR1(\thread)
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+ ldc1 $f3, THREAD_FPR3(\thread)
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+ ldc1 $f5, THREAD_FPR5(\thread)
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+diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
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+index 429481f..f184ba0 100644
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+--- a/arch/mips/include/asm/fpregdef.h
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++++ b/arch/mips/include/asm/fpregdef.h
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+@@ -14,6 +14,20 @@
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+
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+ #include <asm/sgidefs.h>
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+
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++/*
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++ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
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++ * hardfloat and softfloat object files. The kernel build uses soft-float by
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++ * default, so we also need to pass -msoft-float along to GAS if it supports it.
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++ * But this in turn causes assembler errors in files which access hardfloat
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++ * registers. We detect if GAS supports "-msoft-float" in the Makefile and
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++ * explicitly put ".set hardfloat" where floating point registers are touched.
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++ */
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++#ifdef GAS_HAS_SET_HARDFLOAT
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++#define SET_HARDFLOAT .set hardfloat
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++#else
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++#define SET_HARDFLOAT
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++#endif
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++
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+ #if _MIPS_SIM == _MIPS_SIM_ABI32
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+
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+ /*
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+diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
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+index bbc3dd4..d68ad1e 100644
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+--- a/arch/mips/include/asm/mipsregs.h
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++++ b/arch/mips/include/asm/mipsregs.h
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+@@ -1251,7 +1251,7 @@ do { \
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+ /*
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+ * Macros to access the floating point coprocessor control registers
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+ */
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+-#define read_32bit_cp1_register(source) \
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++#define _read_32bit_cp1_register(source, gas_hardfloat) \
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+ ({ \
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+ int __res; \
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+ \
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+@@ -1261,12 +1261,21 @@ do { \
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+ " # gas fails to assemble cfc1 for some archs, \n" \
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+ " # like Octeon. \n" \
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+ " .set mips1 \n" \
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++ " "STR(gas_hardfloat)" \n" \
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+ " cfc1 %0,"STR(source)" \n" \
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+ " .set pop \n" \
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+ : "=r" (__res)); \
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+ __res; \
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+ })
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+
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++#ifdef GAS_HAS_SET_HARDFLOAT
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++#define read_32bit_cp1_register(source) \
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++ _read_32bit_cp1_register(source, .set hardfloat)
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++#else
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++#define read_32bit_cp1_register(source) \
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++ _read_32bit_cp1_register(source, )
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++#endif
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++
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+ #ifdef HAVE_AS_DSP
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+ #define rddsp(mask) \
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+ ({ \
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+diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
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+index 4d78bf4..aa5dbd3 100644
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+--- a/arch/mips/kernel/branch.c
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++++ b/arch/mips/kernel/branch.c
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+@@ -366,7 +366,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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+ case cop1_op:
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+ preempt_disable();
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+ if (is_fpu_owner())
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+- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
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++ fcr31 = read_32bit_cp1_register(CP1_STATUS);
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+ else
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+ fcr31 = current->thread.fpu.fcr31;
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+ preempt_enable();
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+diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
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+index d84f6a5..00b507f 100644
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+--- a/arch/mips/kernel/genex.S
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++++ b/arch/mips/kernel/genex.S
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+@@ -408,6 +408,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
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+ .set push
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+ /* gas fails to assemble cfc1 for some archs (octeon).*/ \
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+ .set mips1
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++ SET_HARDFLOAT
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+ cfc1 a1, fcr31
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+ li a2, ~(0x3f << 12)
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+ and a2, a1
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+diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
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+index f31063d..5ce3b74 100644
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+--- a/arch/mips/kernel/r2300_fpu.S
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++++ b/arch/mips/kernel/r2300_fpu.S
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+@@ -28,6 +28,8 @@
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+ .set mips1
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+ /* Save floating point context */
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+ LEAF(_save_fp_context)
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++ .set push
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++ SET_HARDFLOAT
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+ li v0, 0 # assume success
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+ cfc1 t1,fcr31
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+ EX(swc1 $f0,(SC_FPREGS+0)(a0))
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+@@ -65,6 +67,7 @@ LEAF(_save_fp_context)
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+ EX(sw t1,(SC_FPC_CSR)(a0))
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+ cfc1 t0,$0 # implementation/version
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+ jr ra
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++ .set pop
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+ .set nomacro
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+ EX(sw t0,(SC_FPC_EIR)(a0))
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+ .set macro
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+@@ -80,6 +83,8 @@ LEAF(_save_fp_context)
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+ * stack frame which might have been changed by the user.
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+ */
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+ LEAF(_restore_fp_context)
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++ .set push
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++ SET_HARDFLOAT
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+ li v0, 0 # assume success
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+ EX(lw t0,(SC_FPC_CSR)(a0))
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+ EX(lwc1 $f0,(SC_FPREGS+0)(a0))
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+@@ -116,6 +121,7 @@ LEAF(_restore_fp_context)
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+ EX(lwc1 $f31,(SC_FPREGS+248)(a0))
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+ jr ra
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+ ctc1 t0,fcr31
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++ .set pop
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+ END(_restore_fp_context)
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+ .set reorder
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+
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+diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
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+index 20b7b04..435ea65 100644
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+--- a/arch/mips/kernel/r2300_switch.S
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++++ b/arch/mips/kernel/r2300_switch.S
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+@@ -120,6 +120,9 @@ LEAF(_restore_fp)
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+
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+ #define FPU_DEFAULT 0x00000000
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+
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++ .set push
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++ SET_HARDFLOAT
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++
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+ LEAF(_init_fpu)
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+ mfc0 t0, CP0_STATUS
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+ li t1, ST0_CU1
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+@@ -165,3 +168,5 @@ LEAF(_init_fpu)
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+ mtc1 t0, $f31
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+ jr ra
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+ END(_init_fpu)
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++
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++ .set pop
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+diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
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+index 73b0ddf..06f8b2a 100644
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+--- a/arch/mips/kernel/r4k_fpu.S
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++++ b/arch/mips/kernel/r4k_fpu.S
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+@@ -19,8 +19,12 @@
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+ #include <asm/asm-offsets.h>
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+ #include <asm/regdef.h>
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+
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++/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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++#undef fp
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++
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+ .macro EX insn, reg, src
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+ .set push
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++ SET_HARDFLOAT
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+ .set nomacro
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+ .ex\@: \insn \reg, \src
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+ .set pop
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+@@ -33,12 +37,17 @@
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+ .set mips3
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+
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+ LEAF(_save_fp_context)
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 t1, fcr31
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++ .set pop
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+
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+ #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
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+ .set push
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++ SET_HARDFLOAT
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+ #ifdef CONFIG_CPU_MIPS32_R2
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+- .set mips64r2
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++ .set mips32r2
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++ .set fp=64
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+ mfc0 t0, CP0_STATUS
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+ sll t0, t0, 5
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+ bgez t0, 1f # skip storing odd if FR=0
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+@@ -64,6 +73,8 @@ LEAF(_save_fp_context)
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+ 1: .set pop
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+ #endif
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+
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++ .set push
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++ SET_HARDFLOAT
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+ /* Store the 16 even double precision registers */
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+ EX sdc1 $f0, SC_FPREGS+0(a0)
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+ EX sdc1 $f2, SC_FPREGS+16(a0)
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+@@ -84,11 +95,14 @@ LEAF(_save_fp_context)
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+ EX sw t1, SC_FPC_CSR(a0)
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+ jr ra
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+ li v0, 0 # success
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++ .set pop
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+ END(_save_fp_context)
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+
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+ #ifdef CONFIG_MIPS32_COMPAT
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+ /* Save 32-bit process floating point context */
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+ LEAF(_save_fp_context32)
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 t1, fcr31
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+
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+ mfc0 t0, CP0_STATUS
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+@@ -134,6 +148,7 @@ LEAF(_save_fp_context32)
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+ EX sw t1, SC32_FPC_CSR(a0)
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+ cfc1 t0, $0 # implementation/version
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+ EX sw t0, SC32_FPC_EIR(a0)
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++ .set pop
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+
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+ jr ra
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+ li v0, 0 # success
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+@@ -150,8 +165,10 @@ LEAF(_restore_fp_context)
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+
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+ #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
|
|
|
+ .set push
|
|
|
++ SET_HARDFLOAT
|
|
|
+ #ifdef CONFIG_CPU_MIPS32_R2
|
|
|
+- .set mips64r2
|
|
|
++ .set mips32r2
|
|
|
++ .set fp=64
|
|
|
+ mfc0 t0, CP0_STATUS
|
|
|
+ sll t0, t0, 5
|
|
|
+ bgez t0, 1f # skip loading odd if FR=0
|
|
|
+@@ -175,6 +192,8 @@ LEAF(_restore_fp_context)
|
|
|
+ EX ldc1 $f31, SC_FPREGS+248(a0)
|
|
|
+ 1: .set pop
|
|
|
+ #endif
|
|
|
++ .set push
|
|
|
++ SET_HARDFLOAT
|
|
|
+ EX ldc1 $f0, SC_FPREGS+0(a0)
|
|
|
+ EX ldc1 $f2, SC_FPREGS+16(a0)
|
|
|
+ EX ldc1 $f4, SC_FPREGS+32(a0)
|
|
|
+@@ -192,6 +211,7 @@ LEAF(_restore_fp_context)
|
|
|
+ EX ldc1 $f28, SC_FPREGS+224(a0)
|
|
|
+ EX ldc1 $f30, SC_FPREGS+240(a0)
|
|
|
+ ctc1 t1, fcr31
|
|
|
++ .set pop
|
|
|
+ jr ra
|
|
|
+ li v0, 0 # success
|
|
|
+ END(_restore_fp_context)
|
|
|
+@@ -199,6 +219,8 @@ LEAF(_restore_fp_context)
|
|
|
+ #ifdef CONFIG_MIPS32_COMPAT
|
|
|
+ LEAF(_restore_fp_context32)
|
|
|
+ /* Restore an o32 sigcontext. */
|
|
|
++ .set push
|
|
|
++ SET_HARDFLOAT
|
|
|
+ EX lw t1, SC32_FPC_CSR(a0)
|
|
|
+
|
|
|
+ mfc0 t0, CP0_STATUS
|
|
|
+@@ -242,6 +264,7 @@ LEAF(_restore_fp_context32)
|
|
|
+ ctc1 t1, fcr31
|
|
|
+ jr ra
|
|
|
+ li v0, 0 # success
|
|
|
++ .set pop
|
|
|
+ END(_restore_fp_context32)
|
|
|
+ #endif
|
|
|
+
|
|
|
+diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
|
|
|
+index cc78dd9..83b4f05 100644
|
|
|
+--- a/arch/mips/kernel/r4k_switch.S
|
|
|
++++ b/arch/mips/kernel/r4k_switch.S
|
|
|
+@@ -22,6 +22,9 @@
|
|
|
+
|
|
|
+ #include <asm/asmmacro.h>
|
|
|
+
|
|
|
++/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
|
|
|
++#undef fp
|
|
|
++
|
|
|
+ /*
|
|
|
+ * Offset to the current process status flags, the first 32 bytes of the
|
|
|
+ * stack are not used.
|
|
|
+@@ -151,6 +154,9 @@ LEAF(_restore_fp)
|
|
|
+
|
|
|
+ #define FPU_DEFAULT 0x00000000
|
|
|
+
|
|
|
++ .set push
|
|
|
++ SET_HARDFLOAT
|
|
|
++
|
|
|
+ LEAF(_init_fpu)
|
|
|
+ #ifdef CONFIG_MIPS_MT_SMTC
|
|
|
+ /* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
|
|
|
+@@ -231,7 +237,8 @@ LEAF(_init_fpu)
|
|
|
+
|
|
|
+ #ifdef CONFIG_CPU_MIPS32_R2
|
|
|
+ .set push
|
|
|
+- .set mips64r2
|
|
|
++ .set mips32r2
|
|
|
++ .set fp=64
|
|
|
+ sll t0, t0, 5 # is Status.FR set?
|
|
|
+ bgez t0, 1f # no: skip setting upper 32b
|
|
|
+
|
|
|
+@@ -290,3 +297,5 @@ LEAF(_init_fpu)
|
|
|
+ #endif
|
|
|
+ jr ra
|
|
|
+ END(_init_fpu)
|
|
|
++
|
|
|
++ .set pop /* SET_HARDFLOAT */
|
|
|
+diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
|
|
|
+index da0fbe4..4707738 100644
|
|
|
+--- a/arch/mips/kernel/r6000_fpu.S
|
|
|
++++ b/arch/mips/kernel/r6000_fpu.S
|
|
|
+@@ -18,6 +18,9 @@
|
|
|
+
|
|
|
+ .set noreorder
|
|
|
+ .set mips2
|
|
|
++ .set push
|
|
|
++ SET_HARDFLOAT
|
|
|
++
|
|
|
+ /* Save floating point context */
|
|
|
+ LEAF(_save_fp_context)
|
|
|
+ mfc0 t0,CP0_STATUS
|
|
|
+@@ -85,3 +88,5 @@
|
|
|
+ 1: jr ra
|
|
|
+ nop
|
|
|
+ END(_restore_fp_context)
|
|
|
++
|
|
|
++ .set pop /* SET_HARDFLOAT */
|
|
|
+diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
|
|
|
+index 0b4e2e3..c0a0914 100644
|
|
|
+--- a/arch/mips/math-emu/cp1emu.c
|
|
|
++++ b/arch/mips/math-emu/cp1emu.c
|
|
|
+@@ -817,7 +817,7 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
+ if (insn.i_format.rs == bc_op) {
|
|
|
+ preempt_disable();
|
|
|
+ if (is_fpu_owner())
|
|
|
+- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
|
|
|
++ fcr31 = read_32bit_cp1_register(CP1_STATUS);
|
|
|
+ else
|
|
|
+ fcr31 = current->thread.fpu.fcr31;
|
|
|
+ preempt_enable();
|
|
|
+--
|
|
|
+2.4.5
|
|
|
+
|