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@@ -0,0 +1,369 @@
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+diff -Nur linux-3.14.67.orig/arch/mips/include/asm/asmmacro-32.h linux-3.14.67/arch/mips/include/asm/asmmacro-32.h
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+--- linux-3.14.67.orig/arch/mips/include/asm/asmmacro-32.h 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/include/asm/asmmacro-32.h 2016-04-27 16:18:41.729238756 +0200
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+@@ -13,6 +13,8 @@
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+ #include <asm/mipsregs.h>
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+
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+ .macro fpu_save_single thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 \tmp, fcr31
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+ swc1 $f0, THREAD_FPR0(\thread)
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+ swc1 $f1, THREAD_FPR1(\thread)
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+@@ -47,9 +49,12 @@
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+ swc1 $f30, THREAD_FPR30(\thread)
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+ swc1 $f31, THREAD_FPR31(\thread)
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+ sw \tmp, THREAD_FCR31(\thread)
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++ .set pop
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+ .endm
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+
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+ .macro fpu_restore_single thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ lw \tmp, THREAD_FCR31(\thread)
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+ lwc1 $f0, THREAD_FPR0(\thread)
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+ lwc1 $f1, THREAD_FPR1(\thread)
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+@@ -84,6 +89,7 @@
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+ lwc1 $f30, THREAD_FPR30(\thread)
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+ lwc1 $f31, THREAD_FPR31(\thread)
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+ ctc1 \tmp, fcr31
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++ .set pop
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+ .endm
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+
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+ .macro cpu_save_nonscratch thread
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+diff -Nur linux-3.14.67.orig/arch/mips/include/asm/asmmacro.h linux-3.14.67/arch/mips/include/asm/asmmacro.h
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+--- linux-3.14.67.orig/arch/mips/include/asm/asmmacro.h 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/include/asm/asmmacro.h 2016-04-27 16:18:41.729238756 +0200
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+@@ -74,6 +74,8 @@
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+ #endif /* CONFIG_MIPS_MT_SMTC */
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+
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+ .macro fpu_save_16even thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 \tmp, fcr31
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+ sdc1 $f0, THREAD_FPR0(\thread)
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+ sdc1 $f2, THREAD_FPR2(\thread)
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+@@ -127,6 +129,8 @@
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+ .endm
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+
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+ .macro fpu_restore_16even thread tmp=t0
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++ .set push
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++ SET_HARDFLOAT
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+ lw \tmp, THREAD_FCR31(\thread)
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+ ldc1 $f0, THREAD_FPR0(\thread)
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+ ldc1 $f2, THREAD_FPR2(\thread)
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+diff -Nur linux-3.14.67.orig/arch/mips/include/asm/fpregdef.h linux-3.14.67/arch/mips/include/asm/fpregdef.h
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+--- linux-3.14.67.orig/arch/mips/include/asm/fpregdef.h 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/include/asm/fpregdef.h 2016-04-27 16:18:41.729238756 +0200
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+@@ -14,6 +14,20 @@
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+
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+ #include <asm/sgidefs.h>
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+
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++/*
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++ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
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++ * hardfloat and softfloat object files. The kernel build uses soft-float by
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++ * default, so we also need to pass -msoft-float along to GAS if it supports it.
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++ * But this in turn causes assembler errors in files which access hardfloat
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++ * registers. We detect if GAS supports "-msoft-float" in the Makefile and
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++ * explicitly put ".set hardfloat" where floating point registers are touched.
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++ */
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++#ifdef GAS_HAS_SET_HARDFLOAT
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++#define SET_HARDFLOAT .set hardfloat
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++#else
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++#define SET_HARDFLOAT
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++#endif
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++
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+ #if _MIPS_SIM == _MIPS_SIM_ABI32
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+
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+ /*
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+diff -Nur linux-3.14.67.orig/arch/mips/include/asm/mipsregs.h linux-3.14.67/arch/mips/include/asm/mipsregs.h
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+--- linux-3.14.67.orig/arch/mips/include/asm/mipsregs.h 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/include/asm/mipsregs.h 2016-04-27 16:18:41.729238756 +0200
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+@@ -1251,7 +1251,7 @@
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+ /*
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+ * Macros to access the floating point coprocessor control registers
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+ */
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+-#define read_32bit_cp1_register(source) \
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++#define _read_32bit_cp1_register(source, gas_hardfloat) \
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+ ({ \
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+ int __res; \
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+ \
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+@@ -1261,12 +1261,21 @@
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+ " # gas fails to assemble cfc1 for some archs, \n" \
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+ " # like Octeon. \n" \
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+ " .set mips1 \n" \
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++ " "STR(gas_hardfloat)" \n" \
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+ " cfc1 %0,"STR(source)" \n" \
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+ " .set pop \n" \
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+ : "=r" (__res)); \
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+ __res; \
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+ })
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+
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++#ifdef GAS_HAS_SET_HARDFLOAT
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++#define read_32bit_cp1_register(source) \
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++ _read_32bit_cp1_register(source, .set hardfloat)
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++#else
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++#define read_32bit_cp1_register(source) \
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++ _read_32bit_cp1_register(source, )
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++#endif
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++
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+ #ifdef HAVE_AS_DSP
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+ #define rddsp(mask) \
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+ ({ \
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+diff -Nur linux-3.14.67.orig/arch/mips/kernel/genex.S linux-3.14.67/arch/mips/kernel/genex.S
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+--- linux-3.14.67.orig/arch/mips/kernel/genex.S 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/kernel/genex.S 2016-04-27 16:18:41.729238756 +0200
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+@@ -408,6 +408,7 @@
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+ .set push
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+ /* gas fails to assemble cfc1 for some archs (octeon).*/ \
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+ .set mips1
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++ SET_HARDFLOAT
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+ cfc1 a1, fcr31
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+ li a2, ~(0x3f << 12)
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+ and a2, a1
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+diff -Nur linux-3.14.67.orig/arch/mips/kernel/r2300_fpu.S linux-3.14.67/arch/mips/kernel/r2300_fpu.S
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+--- linux-3.14.67.orig/arch/mips/kernel/r2300_fpu.S 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/kernel/r2300_fpu.S 2016-04-27 16:18:41.729238756 +0200
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+@@ -28,6 +28,8 @@
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+ .set mips1
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+ /* Save floating point context */
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+ LEAF(_save_fp_context)
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++ .set push
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++ SET_HARDFLOAT
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+ li v0, 0 # assume success
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+ cfc1 t1,fcr31
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+ EX(swc1 $f0,(SC_FPREGS+0)(a0))
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+@@ -65,6 +67,7 @@
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+ EX(sw t1,(SC_FPC_CSR)(a0))
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+ cfc1 t0,$0 # implementation/version
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+ jr ra
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++ .set pop
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+ .set nomacro
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+ EX(sw t0,(SC_FPC_EIR)(a0))
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+ .set macro
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+@@ -80,6 +83,8 @@
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+ * stack frame which might have been changed by the user.
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+ */
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+ LEAF(_restore_fp_context)
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++ .set push
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++ SET_HARDFLOAT
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+ li v0, 0 # assume success
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+ EX(lw t0,(SC_FPC_CSR)(a0))
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+ EX(lwc1 $f0,(SC_FPREGS+0)(a0))
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+@@ -116,6 +121,7 @@
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+ EX(lwc1 $f31,(SC_FPREGS+248)(a0))
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+ jr ra
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+ ctc1 t0,fcr31
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++ .set pop
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+ END(_restore_fp_context)
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+ .set reorder
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+
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+diff -Nur linux-3.14.67.orig/arch/mips/kernel/r2300_switch.S linux-3.14.67/arch/mips/kernel/r2300_switch.S
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+--- linux-3.14.67.orig/arch/mips/kernel/r2300_switch.S 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/kernel/r2300_switch.S 2016-04-27 16:18:41.729238756 +0200
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+@@ -120,6 +120,9 @@
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+
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+ #define FPU_DEFAULT 0x00000000
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+
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++ .set push
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++ SET_HARDFLOAT
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++
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+ LEAF(_init_fpu)
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+ mfc0 t0, CP0_STATUS
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+ li t1, ST0_CU1
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+@@ -165,3 +168,5 @@
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+ mtc1 t0, $f31
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+ jr ra
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+ END(_init_fpu)
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++
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++ .set pop
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+diff -Nur linux-3.14.67.orig/arch/mips/kernel/r4k_fpu.S linux-3.14.67/arch/mips/kernel/r4k_fpu.S
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+--- linux-3.14.67.orig/arch/mips/kernel/r4k_fpu.S 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/kernel/r4k_fpu.S 2016-04-27 16:18:41.729238756 +0200
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+@@ -19,8 +19,12 @@
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+ #include <asm/asm-offsets.h>
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+ #include <asm/regdef.h>
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+
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++/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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++#undef fp
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++
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+ .macro EX insn, reg, src
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+ .set push
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++ SET_HARDFLOAT
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+ .set nomacro
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+ .ex\@: \insn \reg, \src
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+ .set pop
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+@@ -33,12 +37,17 @@
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+ .set mips3
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+
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+ LEAF(_save_fp_context)
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 t1, fcr31
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++ .set pop
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+
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+ #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
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+ .set push
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++ SET_HARDFLOAT
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+ #ifdef CONFIG_CPU_MIPS32_R2
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+- .set mips64r2
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++ .set mips32r2
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++ .set fp=64
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+ mfc0 t0, CP0_STATUS
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+ sll t0, t0, 5
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+ bgez t0, 1f # skip storing odd if FR=0
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+@@ -64,6 +73,8 @@
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+ 1: .set pop
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+ #endif
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+
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++ .set push
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++ SET_HARDFLOAT
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+ /* Store the 16 even double precision registers */
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+ EX sdc1 $f0, SC_FPREGS+0(a0)
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+ EX sdc1 $f2, SC_FPREGS+16(a0)
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+@@ -84,11 +95,14 @@
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+ EX sw t1, SC_FPC_CSR(a0)
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+ jr ra
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+ li v0, 0 # success
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++ .set pop
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+ END(_save_fp_context)
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+
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+ #ifdef CONFIG_MIPS32_COMPAT
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+ /* Save 32-bit process floating point context */
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+ LEAF(_save_fp_context32)
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++ .set push
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++ SET_HARDFLOAT
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+ cfc1 t1, fcr31
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+
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+ mfc0 t0, CP0_STATUS
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+@@ -134,6 +148,7 @@
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+ EX sw t1, SC32_FPC_CSR(a0)
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+ cfc1 t0, $0 # implementation/version
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+ EX sw t0, SC32_FPC_EIR(a0)
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++ .set pop
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+
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+ jr ra
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+ li v0, 0 # success
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+@@ -150,8 +165,10 @@
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+
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+ #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
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+ .set push
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++ SET_HARDFLOAT
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+ #ifdef CONFIG_CPU_MIPS32_R2
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+- .set mips64r2
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++ .set mips32r2
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++ .set fp=64
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+ mfc0 t0, CP0_STATUS
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+ sll t0, t0, 5
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+ bgez t0, 1f # skip loading odd if FR=0
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+@@ -175,6 +192,8 @@
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+ EX ldc1 $f31, SC_FPREGS+248(a0)
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+ 1: .set pop
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+ #endif
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++ .set push
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++ SET_HARDFLOAT
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+ EX ldc1 $f0, SC_FPREGS+0(a0)
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+ EX ldc1 $f2, SC_FPREGS+16(a0)
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+ EX ldc1 $f4, SC_FPREGS+32(a0)
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+@@ -192,6 +211,7 @@
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+ EX ldc1 $f28, SC_FPREGS+224(a0)
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+ EX ldc1 $f30, SC_FPREGS+240(a0)
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+ ctc1 t1, fcr31
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++ .set pop
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+ jr ra
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+ li v0, 0 # success
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+ END(_restore_fp_context)
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+@@ -199,6 +219,8 @@
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+ #ifdef CONFIG_MIPS32_COMPAT
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+ LEAF(_restore_fp_context32)
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+ /* Restore an o32 sigcontext. */
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++ .set push
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++ SET_HARDFLOAT
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+ EX lw t1, SC32_FPC_CSR(a0)
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+
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+ mfc0 t0, CP0_STATUS
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+@@ -242,6 +264,7 @@
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+ ctc1 t1, fcr31
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+ jr ra
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+ li v0, 0 # success
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++ .set pop
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+ END(_restore_fp_context32)
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+ #endif
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+
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+diff -Nur linux-3.14.67.orig/arch/mips/kernel/r4k_switch.S linux-3.14.67/arch/mips/kernel/r4k_switch.S
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+--- linux-3.14.67.orig/arch/mips/kernel/r4k_switch.S 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/kernel/r4k_switch.S 2016-04-27 16:18:41.729238756 +0200
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+@@ -22,6 +22,9 @@
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+
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+ #include <asm/asmmacro.h>
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+
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++/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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++#undef fp
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++
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+ /*
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+ * Offset to the current process status flags, the first 32 bytes of the
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+ * stack are not used.
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+@@ -151,6 +154,9 @@
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+
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+ #define FPU_DEFAULT 0x00000000
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+
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++ .set push
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++ SET_HARDFLOAT
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++
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+ LEAF(_init_fpu)
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+ #ifdef CONFIG_MIPS_MT_SMTC
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+ /* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
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+@@ -231,7 +237,8 @@
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+
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+ #ifdef CONFIG_CPU_MIPS32_R2
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+ .set push
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+- .set mips64r2
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++ .set mips32r2
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++ .set fp=64
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+ sll t0, t0, 5 # is Status.FR set?
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+ bgez t0, 1f # no: skip setting upper 32b
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+
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+@@ -290,3 +297,5 @@
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+ #endif
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+ jr ra
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+ END(_init_fpu)
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++
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++ .set pop /* SET_HARDFLOAT */
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+diff -Nur linux-3.14.67.orig/arch/mips/kernel/r6000_fpu.S linux-3.14.67/arch/mips/kernel/r6000_fpu.S
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+--- linux-3.14.67.orig/arch/mips/kernel/r6000_fpu.S 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/kernel/r6000_fpu.S 2016-04-27 16:18:41.729238756 +0200
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+@@ -18,6 +18,9 @@
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+
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+ .set noreorder
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+ .set mips2
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++ .set push
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++ SET_HARDFLOAT
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++
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+ /* Save floating point context */
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+ LEAF(_save_fp_context)
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+ mfc0 t0,CP0_STATUS
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+@@ -85,3 +88,5 @@
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+ 1: jr ra
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+ nop
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+ END(_restore_fp_context)
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++
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++ .set pop /* SET_HARDFLOAT */
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+diff -Nur linux-3.14.67.orig/arch/mips/Makefile linux-3.14.67/arch/mips/Makefile
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+--- linux-3.14.67.orig/arch/mips/Makefile 2016-04-20 08:41:04.000000000 +0200
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++++ linux-3.14.67/arch/mips/Makefile 2016-04-27 16:18:41.729238756 +0200
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+@@ -93,6 +93,15 @@
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+ KBUILD_AFLAGS_MODULE += -mlong-calls
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+ KBUILD_CFLAGS_MODULE += -mlong-calls
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+
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++#
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++# pass -msoft-float to GAS if it supports it. However on newer binutils
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++# (specifically newer than 2.24.51.20140728) we then also need to explicitly
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++# set ".set hardfloat" in all files which manipulate floating point registers.
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++#
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++ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
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++ cflags-y += -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
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++endif
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++
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+ cflags-y += -ffreestanding
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+
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+ #
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