diff -Nur linux-3.14.1/arch/alpha/include/asm/cputime.h linux-3.15-rc1.orig/arch/alpha/include/asm/cputime.h --- linux-3.14.1/arch/alpha/include/asm/cputime.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/alpha/include/asm/cputime.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,6 +0,0 @@ -#ifndef __ALPHA_CPUTIME_H -#define __ALPHA_CPUTIME_H - -#include - -#endif /* __ALPHA_CPUTIME_H */ diff -Nur linux-3.14.1/arch/alpha/include/asm/Kbuild linux-3.15-rc1.orig/arch/alpha/include/asm/Kbuild --- linux-3.14.1/arch/alpha/include/asm/Kbuild 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/alpha/include/asm/Kbuild 2014-04-13 23:18:35.000000000 +0200 @@ -1,7 +1,9 @@ -generic-y += clkdev.h +generic-y += clkdev.h +generic-y += cputime.h generic-y += exec.h -generic-y += trace_clock.h -generic-y += preempt.h generic-y += hash.h +generic-y += mcs_spinlock.h +generic-y += preempt.h +generic-y += trace_clock.h diff -Nur linux-3.14.1/arch/alpha/Kconfig linux-3.15-rc1.orig/arch/alpha/Kconfig --- linux-3.14.1/arch/alpha/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/alpha/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -22,6 +22,7 @@ select GENERIC_SMP_IDLE_THREAD select GENERIC_STRNCPY_FROM_USER select GENERIC_STRNLEN_USER + select HAVE_ARCH_AUDITSYSCALL select HAVE_MOD_ARCH_SPECIFIC select MODULES_USE_ELF_RELA select ODD_RT_SIGACTION diff -Nur linux-3.14.1/arch/alpha/kernel/pci.c linux-3.15-rc1.orig/arch/alpha/kernel/pci.c --- linux-3.14.1/arch/alpha/kernel/pci.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/alpha/kernel/pci.c 2014-04-13 23:18:35.000000000 +0200 @@ -254,12 +254,6 @@ } } -int -pcibios_enable_device(struct pci_dev *dev, int mask) -{ - return pci_enable_resources(dev, mask); -} - /* * If we set up a device for bus mastering, we need to check the latency * timer as certain firmware forgets to set it properly, as seen diff -Nur linux-3.14.1/arch/arc/boot/dts/skeleton.dts linux-3.15-rc1.orig/arch/arc/boot/dts/skeleton.dts --- linux-3.14.1/arch/arc/boot/dts/skeleton.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/boot/dts/skeleton.dts 1970-01-01 01:00:00.000000000 +0100 @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "skeleton.dtsi" diff -Nur linux-3.14.1/arch/arc/boot/.gitignore linux-3.15-rc1.orig/arch/arc/boot/.gitignore --- linux-3.14.1/arch/arc/boot/.gitignore 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/boot/.gitignore 2014-04-13 23:18:35.000000000 +0200 @@ -1 +1,2 @@ *.dtb* +uImage diff -Nur linux-3.14.1/arch/arc/include/asm/Kbuild linux-3.15-rc1.orig/arch/arc/include/asm/Kbuild --- linux-3.14.1/arch/arc/include/asm/Kbuild 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/include/asm/Kbuild 2014-04-13 23:18:35.000000000 +0200 @@ -1,15 +1,15 @@ generic-y += auxvec.h generic-y += barrier.h -generic-y += bugs.h generic-y += bitsperlong.h +generic-y += bugs.h generic-y += clkdev.h generic-y += cputime.h generic-y += device.h generic-y += div64.h generic-y += emergency-restart.h generic-y += errno.h -generic-y += fcntl.h generic-y += fb.h +generic-y += fcntl.h generic-y += ftrace.h generic-y += hardirq.h generic-y += hash.h @@ -22,6 +22,7 @@ generic-y += kvm_para.h generic-y += local.h generic-y += local64.h +generic-y += mcs_spinlock.h generic-y += mman.h generic-y += msgbuf.h generic-y += param.h @@ -30,6 +31,7 @@ generic-y += percpu.h generic-y += poll.h generic-y += posix_types.h +generic-y += preempt.h generic-y += resource.h generic-y += scatterlist.h generic-y += sembuf.h @@ -48,4 +50,3 @@ generic-y += user.h generic-y += vga.h generic-y += xor.h -generic-y += preempt.h diff -Nur linux-3.14.1/arch/arc/include/asm/linkage.h linux-3.15-rc1.orig/arch/arc/include/asm/linkage.h --- linux-3.14.1/arch/arc/include/asm/linkage.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/include/asm/linkage.h 2014-04-13 23:18:35.000000000 +0200 @@ -13,20 +13,6 @@ #define ASM_NL ` /* use '`' to mark new line in macro */ -/* Can't use the ENTRY macro in linux/linkage.h - * gas considers ';' as comment vs. newline - */ -.macro ARC_ENTRY name - .global \name - .align 4 - \name: -.endm - -.macro ARC_EXIT name -#define ASM_PREV_SYM_ADDR(name) .-##name - .size \ name, ASM_PREV_SYM_ADDR(\name) -.endm - /* annotation for data we want in DCCM - if enabled in .config */ .macro ARCFP_DATA nm #ifdef CONFIG_ARC_HAS_DCCM diff -Nur linux-3.14.1/arch/arc/Kconfig linux-3.15-rc1.orig/arch/arc/Kconfig --- linux-3.14.1/arch/arc/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -57,7 +57,7 @@ config MMU def_bool y -config NO_IOPORT +config NO_IOPORT_MAP def_bool y config GENERIC_CALIBRATE_DELAY @@ -356,7 +356,6 @@ config ARC_MISALIGN_ACCESS bool "Emulate unaligned memory access (userspace only)" - default N select SYSCTL_ARCH_UNALIGN_NO_WARN select SYSCTL_ARCH_UNALIGN_ALLOW help diff -Nur linux-3.14.1/arch/arc/kernel/ctx_sw_asm.S linux-3.15-rc1.orig/arch/arc/kernel/ctx_sw_asm.S --- linux-3.14.1/arch/arc/kernel/ctx_sw_asm.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/kernel/ctx_sw_asm.S 2014-04-13 23:18:35.000000000 +0200 @@ -62,4 +62,4 @@ ld.ab blink, [sp, 4] j [blink] -ARC_EXIT __switch_to +END(__switch_to) diff -Nur linux-3.14.1/arch/arc/kernel/entry.S linux-3.15-rc1.orig/arch/arc/kernel/entry.S --- linux-3.14.1/arch/arc/kernel/entry.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/kernel/entry.S 2014-04-13 23:18:35.000000000 +0200 @@ -141,7 +141,7 @@ VECTOR reserved ; Reserved Exceptions .endr -#include /* ARC_{EXTRY,EXIT} */ +#include /* {EXTRY,EXIT} */ #include /* SAVE_ALL_{INT1,INT2,SYS...} */ #include #include @@ -184,7 +184,7 @@ ; --------------------------------------------- ; Level 2 ISR: Can interrupt a Level 1 ISR ; --------------------------------------------- -ARC_ENTRY handle_interrupt_level2 +ENTRY(handle_interrupt_level2) ; TODO-vineetg for SMP this wont work ; free up r9 as scratchpad @@ -225,14 +225,14 @@ b ret_from_exception -ARC_EXIT handle_interrupt_level2 +END(handle_interrupt_level2) #endif ; --------------------------------------------- ; Level 1 ISR ; --------------------------------------------- -ARC_ENTRY handle_interrupt_level1 +ENTRY(handle_interrupt_level1) /* free up r9 as scratchpad */ #ifdef CONFIG_SMP @@ -265,7 +265,7 @@ sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg b ret_from_exception -ARC_EXIT handle_interrupt_level1 +END(handle_interrupt_level1) ;################### Non TLB Exception Handling ############################# @@ -273,7 +273,7 @@ ; Instruction Error Exception Handler ; --------------------------------------------- -ARC_ENTRY instr_service +ENTRY(instr_service) EXCEPTION_PROLOGUE @@ -284,13 +284,13 @@ bl do_insterror_or_kprobe b ret_from_exception -ARC_EXIT instr_service +END(instr_service) ; --------------------------------------------- ; Memory Error Exception Handler ; --------------------------------------------- -ARC_ENTRY mem_service +ENTRY(mem_service) EXCEPTION_PROLOGUE @@ -301,13 +301,13 @@ bl do_memory_error b ret_from_exception -ARC_EXIT mem_service +END(mem_service) ; --------------------------------------------- ; Machine Check Exception Handler ; --------------------------------------------- -ARC_ENTRY EV_MachineCheck +ENTRY(EV_MachineCheck) EXCEPTION_PROLOGUE @@ -331,13 +331,13 @@ j do_machine_check_fault -ARC_EXIT EV_MachineCheck +END(EV_MachineCheck) ; --------------------------------------------- ; Protection Violation Exception Handler ; --------------------------------------------- -ARC_ENTRY EV_TLBProtV +ENTRY(EV_TLBProtV) EXCEPTION_PROLOGUE @@ -385,12 +385,12 @@ b ret_from_exception -ARC_EXIT EV_TLBProtV +END(EV_TLBProtV) ; --------------------------------------------- ; Privilege Violation Exception Handler ; --------------------------------------------- -ARC_ENTRY EV_PrivilegeV +ENTRY(EV_PrivilegeV) EXCEPTION_PROLOGUE @@ -401,12 +401,12 @@ bl do_privilege_fault b ret_from_exception -ARC_EXIT EV_PrivilegeV +END(EV_PrivilegeV) ; --------------------------------------------- ; Extension Instruction Exception Handler ; --------------------------------------------- -ARC_ENTRY EV_Extension +ENTRY(EV_Extension) EXCEPTION_PROLOGUE @@ -417,7 +417,7 @@ bl do_extension_fault b ret_from_exception -ARC_EXIT EV_Extension +END(EV_Extension) ;######################### System Call Tracing ######################### @@ -504,7 +504,7 @@ ; (2) Break Points ;------------------------------------------------------------------ -ARC_ENTRY EV_Trap +ENTRY(EV_Trap) EXCEPTION_PROLOGUE @@ -534,9 +534,9 @@ jl [r9] ; Entry into Sys Call Handler ; fall through to ret_from_system_call -ARC_EXIT EV_Trap +END(EV_Trap) -ARC_ENTRY ret_from_system_call +ENTRY(ret_from_system_call) st r0, [sp, PT_r0] ; sys call return value in pt_regs @@ -546,7 +546,7 @@ ; ; If ret to user mode do we need to handle signals, schedule() et al. -ARC_ENTRY ret_from_exception +ENTRY(ret_from_exception) ; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32 ld r8, [sp, PT_status32] ; returning to User/Kernel Mode @@ -726,9 +726,9 @@ debug_marker_syscall: rtie -ARC_EXIT ret_from_exception +END(ret_from_exception) -ARC_ENTRY ret_from_fork +ENTRY(ret_from_fork) ; when the forked child comes here from the __switch_to function ; r0 has the last task pointer. ; put last task in scheduler queue @@ -745,11 +745,11 @@ ; special case of kernel_thread entry point returning back due to ; kernel_execve() - pretend return from syscall to ret to userland b ret_from_exception -ARC_EXIT ret_from_fork +END(ret_from_fork) ;################### Special Sys Call Wrappers ########################## -ARC_ENTRY sys_clone_wrapper +ENTRY(sys_clone_wrapper) SAVE_CALLEE_SAVED_USER bl @sys_clone DISCARD_CALLEE_SAVED_USER @@ -759,7 +759,7 @@ bnz tracesys_exit b ret_from_system_call -ARC_EXIT sys_clone_wrapper +END(sys_clone_wrapper) #ifdef CONFIG_ARC_DW2_UNWIND ; Workaround for bug 94179 (STAR ): diff -Nur linux-3.14.1/arch/arc/kernel/head.S linux-3.15-rc1.orig/arch/arc/kernel/head.S --- linux-3.14.1/arch/arc/kernel/head.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/kernel/head.S 2014-04-13 23:18:35.000000000 +0200 @@ -24,13 +24,13 @@ .globl stext stext: ;------------------------------------------------------------------- - ; Don't clobber r0-r4 yet. It might have bootloader provided info + ; Don't clobber r0-r2 yet. It might have bootloader provided info ;------------------------------------------------------------------- sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] #ifdef CONFIG_SMP - ; Only Boot (Master) proceeds. Others wait in platform dependent way + ; Ensure Boot (Master) proceeds. Others wait in platform dependent way ; IDENTITY Reg [ 3 2 1 0 ] ; (cpu-id) ^^^ => Zero for UP ARC700 ; => #Core-ID if SMP (Master 0) @@ -39,7 +39,8 @@ ; need to make sure only boot cpu takes this path. GET_CPU_ID r5 cmp r5, 0 - jnz arc_platform_smp_wait_to_boot + mov.ne r0, r5 + jne arc_platform_smp_wait_to_boot #endif ; Clear BSS before updating any globals ; XXX: use ZOL here diff -Nur linux-3.14.1/arch/arc/kernel/time.c linux-3.15-rc1.orig/arch/arc/kernel/time.c --- linux-3.14.1/arch/arc/kernel/time.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/kernel/time.c 2014-04-13 23:18:35.000000000 +0200 @@ -155,22 +155,6 @@ write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); } -/* - * Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic) - * -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted) - * -Rearming is done by setting the IE bit - * - * Small optimisation: Normal code would have been - * if (irq_reenable) - * CTRL_REG = (IE | NH); - * else - * CTRL_REG = NH; - * However since IE is BIT0 we can fold the branch - */ -static void arc_timer_event_ack(unsigned int irq_reenable) -{ - write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); -} static int arc_clkevent_set_next_event(unsigned long delta, struct clock_event_device *dev) @@ -207,10 +191,22 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id) { - struct clock_event_device *clk = this_cpu_ptr(&arc_clockevent_device); + /* + * Note that generic IRQ core could have passed @evt for @dev_id if + * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() + */ + struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); + int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC; + + /* + * Any write to CTRL reg ACks the interrupt, we rewrite the + * Count when [N]ot [H]alted bit. + * And re-arm it if perioid by [I]nterrupt [E]nable bit + */ + write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); + + evt->event_handler(evt); - arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC); - clk->event_handler(clk); return IRQ_HANDLED; } @@ -222,9 +218,8 @@ /* * Setup the local event timer for @cpu - * N.B. weak so that some exotic ARC SoCs can completely override it */ -void __weak arc_local_timer_setup(unsigned int cpu) +void arc_local_timer_setup(unsigned int cpu) { struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu); diff -Nur linux-3.14.1/arch/arc/lib/memcmp.S linux-3.15-rc1.orig/arch/arc/lib/memcmp.S --- linux-3.14.1/arch/arc/lib/memcmp.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/lib/memcmp.S 2014-04-13 23:18:35.000000000 +0200 @@ -6,7 +6,7 @@ * published by the Free Software Foundation. */ -#include +#include #ifdef __LITTLE_ENDIAN__ #define WORD2 r2 @@ -16,7 +16,7 @@ #define SHIFT r2 #endif -ARC_ENTRY memcmp +ENTRY(memcmp) or r12,r0,r1 asl_s r12,r12,30 sub r3,r2,1 @@ -121,4 +121,4 @@ .Lnil: j_s.d [blink] mov r0,0 -ARC_EXIT memcmp +END(memcmp) diff -Nur linux-3.14.1/arch/arc/lib/memcpy-700.S linux-3.15-rc1.orig/arch/arc/lib/memcpy-700.S --- linux-3.14.1/arch/arc/lib/memcpy-700.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/lib/memcpy-700.S 2014-04-13 23:18:35.000000000 +0200 @@ -6,9 +6,9 @@ * published by the Free Software Foundation. */ -#include +#include -ARC_ENTRY memcpy +ENTRY(memcpy) or r3,r0,r1 asl_s r3,r3,30 mov_s r5,r0 @@ -63,4 +63,4 @@ .Lendbloop: j_s.d [blink] stb r12,[r5,0] -ARC_EXIT memcpy +END(memcpy) diff -Nur linux-3.14.1/arch/arc/lib/memset.S linux-3.15-rc1.orig/arch/arc/lib/memset.S --- linux-3.14.1/arch/arc/lib/memset.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/lib/memset.S 2014-04-13 23:18:35.000000000 +0200 @@ -6,11 +6,11 @@ * published by the Free Software Foundation. */ -#include +#include #define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */ -ARC_ENTRY memset +ENTRY(memset) mov_s r4,r0 or r12,r0,r2 bmsk.f r12,r12,1 @@ -46,14 +46,14 @@ stb.ab r1,[r4,1] .Ltiny_end: j_s [blink] -ARC_EXIT memset +END(memset) ; memzero: @r0 = mem, @r1 = size_t ; memset: @r0 = mem, @r1 = char, @r2 = size_t -ARC_ENTRY memzero +ENTRY(memzero) ; adjust bzero args to memset args mov r2, r1 mov r1, 0 b memset ;tail call so need to tinker with blink -ARC_EXIT memzero +END(memzero) diff -Nur linux-3.14.1/arch/arc/lib/strchr-700.S linux-3.15-rc1.orig/arch/arc/lib/strchr-700.S --- linux-3.14.1/arch/arc/lib/strchr-700.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/lib/strchr-700.S 2014-04-13 23:18:35.000000000 +0200 @@ -11,9 +11,9 @@ presence of the norm instruction makes it easier to operate on whole words branch-free. */ -#include +#include -ARC_ENTRY strchr +ENTRY(strchr) extb_s r1,r1 asl r5,r1,8 bmsk r2,r0,1 @@ -130,4 +130,4 @@ j_s.d [blink] mov.mi r0,0 #endif /* ENDIAN */ -ARC_EXIT strchr +END(strchr) diff -Nur linux-3.14.1/arch/arc/lib/strcmp.S linux-3.15-rc1.orig/arch/arc/lib/strcmp.S --- linux-3.14.1/arch/arc/lib/strcmp.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/lib/strcmp.S 2014-04-13 23:18:35.000000000 +0200 @@ -13,9 +13,9 @@ source 1; however, that would increase the overhead for loop setup / finish, and strcmp might often terminate early. */ -#include +#include -ARC_ENTRY strcmp +ENTRY(strcmp) or r2,r0,r1 bmsk_s r2,r2,1 brne r2,0,.Lcharloop @@ -93,4 +93,4 @@ .Lcmpend: j_s.d [blink] sub r0,r2,r3 -ARC_EXIT strcmp +END(strcmp) diff -Nur linux-3.14.1/arch/arc/lib/strcpy-700.S linux-3.15-rc1.orig/arch/arc/lib/strcpy-700.S --- linux-3.14.1/arch/arc/lib/strcpy-700.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/lib/strcpy-700.S 2014-04-13 23:18:35.000000000 +0200 @@ -16,9 +16,9 @@ there, but the it is not likely to be taken often, and it would also be likey to cost an unaligned mispredict at the next call. */ -#include +#include -ARC_ENTRY strcpy +ENTRY(strcpy) or r2,r0,r1 bmsk_s r2,r2,1 brne.d r2,0,charloop @@ -67,4 +67,4 @@ brne.d r3,0,charloop stb.ab r3,[r10,1] j [blink] -ARC_EXIT strcpy +END(strcpy) diff -Nur linux-3.14.1/arch/arc/lib/strlen.S linux-3.15-rc1.orig/arch/arc/lib/strlen.S --- linux-3.14.1/arch/arc/lib/strlen.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/lib/strlen.S 2014-04-13 23:18:35.000000000 +0200 @@ -6,9 +6,9 @@ * published by the Free Software Foundation. */ -#include +#include -ARC_ENTRY strlen +ENTRY(strlen) or r3,r0,7 ld r2,[r3,-7] ld.a r6,[r3,-3] @@ -80,4 +80,4 @@ .Learly_end: b.d .Lend sub_s.ne r1,r1,r1 -ARC_EXIT strlen +END(strlen) diff -Nur linux-3.14.1/arch/arc/mm/cache_arc700.c linux-3.15-rc1.orig/arch/arc/mm/cache_arc700.c --- linux-3.14.1/arch/arc/mm/cache_arc700.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/mm/cache_arc700.c 2014-04-13 23:18:35.000000000 +0200 @@ -100,10 +100,9 @@ #define DC_CTRL_INV_MODE_FLUSH 0x40 #define DC_CTRL_FLUSH_STATUS 0x100 -char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len) +char *arc_cache_mumbojumbo(int c, char *buf, int len) { int n = 0; - unsigned int c = smp_processor_id(); #define PR_CACHE(p, enb, str) \ { \ diff -Nur linux-3.14.1/arch/arc/mm/init.c linux-3.15-rc1.orig/arch/arc/mm/init.c --- linux-3.14.1/arch/arc/mm/init.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/mm/init.c 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,9 @@ #include #include #include +#ifdef CONFIG_BLK_DEV_INITRD +#include +#endif #include #include #include @@ -42,6 +45,24 @@ pr_info("Memory size set via devicetree %ldM\n", TO_MB(arc_mem_sz)); } +#ifdef CONFIG_BLK_DEV_INITRD +static int __init early_initrd(char *p) +{ + unsigned long start, size; + char *endp; + + start = memparse(p, &endp); + if (*endp == ',') { + size = memparse(endp + 1, NULL); + + initrd_start = (unsigned long)__va(start); + initrd_end = (unsigned long)__va(start + size); + } + return 0; +} +early_param("initrd", early_initrd); +#endif + /* * First memory setup routine called from setup_arch() * 1. setup swapper's mm @init_mm @@ -80,6 +101,12 @@ memblock_reserve(CONFIG_LINUX_LINK_BASE, __pa(_end) - CONFIG_LINUX_LINK_BASE); +#ifdef CONFIG_BLK_DEV_INITRD + /*------------- reserve initrd image -----------------------*/ + if (initrd_start) + memblock_reserve(__pa(initrd_start), initrd_end - initrd_start); +#endif + memblock_dump_all(); /*-------------- node setup --------------------------------*/ diff -Nur linux-3.14.1/arch/arc/mm/tlbex.S linux-3.15-rc1.orig/arch/arc/mm/tlbex.S --- linux-3.14.1/arch/arc/mm/tlbex.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/mm/tlbex.S 2014-04-13 23:18:35.000000000 +0200 @@ -260,7 +260,7 @@ ; I-TLB Miss Exception Handler ;----------------------------------------------------------------------------- -ARC_ENTRY EV_TLBMissI +ENTRY(EV_TLBMissI) TLBMISS_FREEUP_REGS @@ -293,13 +293,13 @@ TLBMISS_RESTORE_REGS rtie -ARC_EXIT EV_TLBMissI +END(EV_TLBMissI) ;----------------------------------------------------------------------------- ; D-TLB Miss Exception Handler ;----------------------------------------------------------------------------- -ARC_ENTRY EV_TLBMissD +ENTRY(EV_TLBMissD) TLBMISS_FREEUP_REGS @@ -381,6 +381,4 @@ bl do_page_fault b ret_from_exception -ARC_EXIT EV_TLBMissD - -ARC_ENTRY EV_TLBMissB ; Bogus entry to measure sz of DTLBMiss hdlr +END(EV_TLBMissD) diff -Nur linux-3.14.1/arch/arc/plat-arcfpga/Kconfig linux-3.15-rc1.orig/arch/arc/plat-arcfpga/Kconfig --- linux-3.14.1/arch/arc/plat-arcfpga/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/plat-arcfpga/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -33,7 +33,6 @@ bool "ARC SMP Extensions (ISS Models only)" default n depends on SMP - select ARC_HAS_COH_RTSC help SMP Extensions to ARC700, in a "simulation only" Model, supported in ARC ISS (Instruction Set Simulator). diff -Nur linux-3.14.1/arch/arc/plat-arcfpga/platform.c linux-3.15-rc1.orig/arch/arc/plat-arcfpga/platform.c --- linux-3.14.1/arch/arc/plat-arcfpga/platform.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arc/plat-arcfpga/platform.c 2014-04-13 23:18:35.000000000 +0200 @@ -201,7 +201,7 @@ * callback set, by matching the DT compatible name. */ -static const char *aa4_compat[] __initdata = { +static const char *aa4_compat[] __initconst = { "snps,arc-angel4", NULL, }; @@ -216,7 +216,7 @@ #endif MACHINE_END -static const char *ml509_compat[] __initdata = { +static const char *ml509_compat[] __initconst = { "snps,arc-ml509", NULL, }; @@ -231,7 +231,7 @@ #endif MACHINE_END -static const char *nsimosci_compat[] __initdata = { +static const char *nsimosci_compat[] __initconst = { "snps,nsimosci", NULL, }; diff -Nur linux-3.14.1/arch/arm/boot/dts/am335x-evm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/am335x-evm.dts --- linux-3.14.1/arch/arm/boot/dts/am335x-evm.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/am335x-evm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -260,6 +260,12 @@ >; }; + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ @@ -434,9 +440,9 @@ ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ nand@0,0 { reg = <0 0 0>; /* CS0, offset 0 */ - nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; - gpmc,device-nand = "true"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; @@ -460,50 +466,51 @@ gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; - + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; - elm_id = <&elm>; - - /* MTD partition table */ partition@0 { - label = "SPL1"; + label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; - partition@1 { - label = "SPL2"; + label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; - partition@2 { - label = "SPL3"; + label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; - partition@3 { - label = "SPL4"; + label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; - partition@4 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; + label = "NAND.u-boot-spl"; + reg = <0x00080000 0x00040000>; }; - partition@5 { - label = "environment"; - reg = <0x00260000 0x00020000>; + label = "NAND.u-boot"; + reg = <0x000C0000 0x00100000>; }; - partition@6 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; + label = "NAND.u-boot-env"; + reg = <0x001C0000 0x00020000>; }; - partition@7 { - label = "File-System"; - reg = <0x00780000 0x0F880000>; + label = "NAND.u-boot-env.backup1"; + reg = <0x001E0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00A00000 0x0F600000>; }; }; }; @@ -643,6 +650,9 @@ status = "okay"; vmmc-supply = <&vmmc_reg>; bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; &sham { diff -Nur linux-3.14.1/arch/arm/boot/dts/am335x-evmsk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/am335x-evmsk.dts --- linux-3.14.1/arch/arm/boot/dts/am335x-evmsk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/am335x-evmsk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -45,6 +45,18 @@ regulator-boot-on; }; + wl12xx_vmmc: fixedregulator@2 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 29 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; @@ -270,6 +282,24 @@ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ + >; + }; }; &uart0 { @@ -342,9 +372,22 @@ status = "okay"; }; + usb-phy@47401b00 { + status = "okay"; + }; + usb@47401000 { status = "okay"; }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; }; &epwmss2 { @@ -440,6 +483,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; }; &davinci_mdio { @@ -451,11 +495,13 @@ &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <1>; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; }; &mmc1 { @@ -479,6 +525,16 @@ ti,no-reset-on-init; }; +&mmc2 { + status = "okay"; + vmmc-supply = <&wl12xx_vmmc>; + ti,non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + &mcasp1 { pinctrl-names = "default"; pinctrl-0 = <&mcasp1_pins>; diff -Nur linux-3.14.1/arch/arm/boot/dts/am33xx.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/am33xx.dtsi --- linux-3.14.1/arch/arm/boot/dts/am33xx.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/am33xx.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -58,6 +58,10 @@ 275000 1125000 >; voltage-tolerance = <2>; /* 2 percentage */ + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; @@ -318,6 +322,7 @@ compatible = "ti,omap4-hwspinlock"; reg = <0x480ca000 0x1000>; ti,hwmods = "spinlock"; + #hwlock-cells = <1>; }; wdt2: wdt@44e35000 { @@ -399,7 +404,7 @@ ti,timer-pwm; }; - rtc@44e3e000 { + rtc: rtc@44e3e000 { compatible = "ti,da830-rtc"; reg = <0x44e3e000 0x1000>; interrupts = <75 @@ -448,7 +453,7 @@ ti,hwmods = "usb_otg_hs"; status = "disabled"; - usb_ctrl_mod: control@44e10000 { + usb_ctrl_mod: control@44e10620 { compatible = "ti,am335x-usb-ctrl-module"; reg = <0x44e10620 0x10 0x44e10648 0x4>; @@ -551,7 +556,7 @@ "tx14", "tx15"; }; - cppi41dma: dma-controller@07402000 { + cppi41dma: dma-controller@47402000 { compatible = "ti,am3359-cppi41"; reg = <0x47400000 0x1000 0x47402000 0x1000 @@ -582,6 +587,8 @@ compatible = "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; + interrupts = <31>; + interrupt-names = "ecap0"; ti,hwmods = "ecap0"; status = "disabled"; }; @@ -610,6 +617,8 @@ compatible = "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; + interrupts = <47>; + interrupt-names = "ecap1"; ti,hwmods = "ecap1"; status = "disabled"; }; @@ -638,6 +647,8 @@ compatible = "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; + interrupts = <61>; + interrupt-names = "ecap2"; ti,hwmods = "ecap2"; status = "disabled"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/am3517-craneboard.dts linux-3.15-rc1.orig/arch/arm/boot/dts/am3517-craneboard.dts --- linux-3.14.1/arch/arm/boot/dts/am3517-craneboard.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/am3517-craneboard.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,174 @@ +/* + * See craneboard.org for more details + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am3517.dtsi" + +/ { + model = "TI AM3517 CraneBoard (TMDSEVM3517)"; + compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&davinci_emac { + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <2600000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + /* goes to expansion connector */ + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + /* goes to expansion connector */ + status = "disabled"; +}; + +&mmc1 { + vmmc-supply = <&vdd2_reg>; + bus-width = <8>; +}; + +&mmc2 { + /* goes to expansion connector */ + status = "disabled"; +}; + +&mmc3 { + /* goes to expansion connector */ + status = "disabled"; +}; + +#include "tps65910.dtsi" + +&omap3_pmx_core { + tps_pins: pinmux_tps_pins { + pinctrl-single,pins = < + 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ + >; + }; +}; + +&tps { + pinctrl-names = "default"; + pinctrl-0 = <&tps_pins>; + + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + ti,en-ck32k-xtal; + + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + /* + * Unused: + * VDIG1=2.7V,300mA max + * VDIG2=1.8V,300mA max + */ + + vpll_reg: regulator@7 { + /* VDDS_DPLL_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + /* VDDS_SRAM_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + /* VDDA1P8V_USBPHY */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* VAUX33 unused */ + + vdac_reg: regulator@8 { + /* VDDA_DAC_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + /* VDDA3P3V_USBPHY */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_CORE */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDDSHV_3V3 */ + regulator-name = "vdd_shv"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* VDD3 unused */ + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/am4372.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/am4372.dtsi --- linux-3.14.1/arch/arm/boot/dts/am4372.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/am4372.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include #include "skeleton.dtsi" @@ -33,6 +34,11 @@ compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; @@ -351,6 +357,13 @@ status = "disabled"; }; + hwspinlock: spinlock@480ca000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x480ca000 0x1000>; + ti,hwmods = "spinlock"; + #hwlock-cells = <1>; + }; + i2c0: i2c@44e0b000 { compatible = "ti,am4372-i2c","ti,omap4-i2c"; reg = <0x44e0b000 0x1000>; @@ -521,6 +534,7 @@ ecap0: ecap@48300100 { compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; status = "disabled"; @@ -528,6 +542,7 @@ ehrpwm0: ehrpwm@48300200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; reg = <0x48300200 0x80>; ti,hwmods = "ehrpwm0"; status = "disabled"; @@ -545,6 +560,7 @@ ecap1: ecap@48302100 { compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + #pwm-cells = <3>; reg = <0x48302100 0x80>; ti,hwmods = "ecap1"; status = "disabled"; @@ -552,6 +568,7 @@ ehrpwm1: ehrpwm@48302200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; reg = <0x48302200 0x80>; ti,hwmods = "ehrpwm1"; status = "disabled"; @@ -569,6 +586,7 @@ ecap2: ecap@48304100 { compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + #pwm-cells = <3>; reg = <0x48304100 0x80>; ti,hwmods = "ecap2"; status = "disabled"; @@ -576,6 +594,7 @@ ehrpwm2: ehrpwm@48304200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; reg = <0x48304200 0x80>; ti,hwmods = "ehrpwm2"; status = "disabled"; @@ -593,6 +612,7 @@ ehrpwm3: ehrpwm@48306200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; reg = <0x48306200 0x80>; ti,hwmods = "ehrpwm3"; status = "disabled"; @@ -610,6 +630,7 @@ ehrpwm4: ehrpwm@48308200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; reg = <0x48308200 0x80>; ti,hwmods = "ehrpwm4"; status = "disabled"; @@ -627,6 +648,7 @@ ehrpwm5: ehrpwm@4830a200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; reg = <0x4830a200 0x80>; ti,hwmods = "ehrpwm5"; status = "disabled"; @@ -689,6 +711,30 @@ <&edma 11>; dma-names = "tx", "rx"; }; + + elm: elm@48080000 { + compatible = "ti,am3352-elm"; + reg = <0x48080000 0x2000>; + interrupts = ; + ti,hwmods = "elm"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = ; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/am437x-gp-evm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/am437x-gp-evm.dts --- linux-3.14.1/arch/arm/boot/dts/am437x-gp-evm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/am437x-gp-evm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM437x GP EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include + +/ { + model = "TI AM437x GP EVM"; + compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ + &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ + &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ + + col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ + &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x00010202 /* P2 */ + 0x01000067 /* UP */ + 0x0101006a /* RIGHT */ + 0x02000069 /* LEFT */ + 0x0201006c>; /* DOWN */ + }; +}; + +&am43xx_pinmux { + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1_pins { + pinctrl-single,pins = < + 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/am43x-epos-evm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/am43x-epos-evm.dts --- linux-3.14.1/arch/arm/boot/dts/am43x-epos-evm.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/am43x-epos-evm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ #include "am4372.dtsi" #include #include +#include / { model = "TI AM43x EPOS EVM"; @@ -79,6 +80,64 @@ 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; + + nand_flash_x8: nand_flash_x8 { + pinctrl-single,pins = < + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ + 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ + 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ + 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ + 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ + 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ + 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; }; matrix_keypad: matrix_keypad@0 { @@ -113,12 +172,22 @@ 0x0203006c /* DOWN */ 0x03030069>; /* LEFT */ }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; }; &mmc1 { status = "okay"; vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; &mac { @@ -169,6 +238,12 @@ }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -184,3 +259,111 @@ &gpio3 { status = "okay"; }; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x8>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; /* cs-on-ns */ + gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,we-on-ns = <0>; /* cs-on-ns */ + gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ + gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ + gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ + gpmc,access-ns = <30>; /* tCEA + 4*/ + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x000C0000 0x00040000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00100000 0x00080000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x00180000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x00280000 0x00040000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x002C0000 0x00040000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00300000 0x00700000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00800000 0x1F600000>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-370-db.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-db.dts --- linux-3.14.1/arch/arm/boot/dts/armada-370-db.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-db.dts 2014-04-13 23:18:35.000000000 +0200 @@ -64,6 +64,22 @@ phy-mode = "rgmii-id"; }; + i2c@11000 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + audio_codec: audio-codec@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; + }; + + audio-controller@30000 { + pinctrl-0 = <&i2s_pins2>; + pinctrl-names = "default"; + status = "okay"; + }; + mvsdio@d4000 { pinctrl-0 = <&sdio_pins1>; pinctrl-names = "default"; @@ -80,6 +96,30 @@ broken-cd; }; + pinctrl { + /* + * These pins might be muxed as I2S by + * the bootloader, but it conflicts + * with the real I2S pins that are + * muxed using i2s_pins. We must mux + * those pins to a function other than + * I2S. + */ + pinctrl-0 = <&hog_pins1 &hog_pins2>; + pinctrl-names = "default"; + + hog_pins1: hog-pins1 { + marvell,pins = "mpp6", "mpp8", "mpp10", + "mpp12", "mpp13"; + marvell,function = "gpio"; + }; + + hog_pins2: hog-pins2 { + marvell,pins = "mpp5", "mpp7", "mpp9"; + marvell,function = "gpo"; + }; + }; + usb@50000 { status = "okay"; }; @@ -112,10 +152,26 @@ /* Port 0, Lane 0 */ status = "okay"; }; + pcie@2,0 { /* Port 1, Lane 0 */ status = "okay"; }; }; }; + + sound { + compatible = "marvell,a370db-audio"; + marvell,audio-controller = <&audio_controller>; + marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>; + status = "okay"; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + }; + + spdif_in: spdif-in { + compatible = "linux,spdif-dir"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-370.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370.dtsi --- linux-3.14.1/arch/arm/boot/dts/armada-370.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -132,6 +132,25 @@ "mpp51", "mpp52", "mpp53"; marvell,function = "sd0"; }; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + i2s_pins1: i2s-pins1 { + marvell,pins = "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", + "mpp12", "mpp13"; + marvell,function = "audio"; + }; + + i2s_pins2: i2s-pins2 { + marvell,pins = "mpp49", "mpp47", "mpp50", + "mpp59", "mpp57", "mpp61", + "mpp62", "mpp60", "mpp58"; + marvell,function = "audio"; + }; }; gpio0: gpio@18100 { @@ -196,6 +215,20 @@ clocks = <&coreclk 2>; }; + watchdog@20300 { + compatible = "marvell,armada-370-wdt"; + clocks = <&coreclk 2>; + }; + + audio_controller: audio-controller@30000 { + compatible = "marvell,armada370-audio"; + reg = <0x30000 0x4000>; + interrupts = <93>; + clocks = <&gateclk 0>; + clock-names = "internal"; + status = "disabled"; + }; + usb@50000 { clocks = <&coreclk 0>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-370-mirabox.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-mirabox.dts --- linux-3.14.1/arch/arm/boot/dts/armada-370-mirabox.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-mirabox.dts 2014-04-13 23:18:35.000000000 +0200 @@ -9,6 +9,7 @@ */ /dts-v1/; +#include #include "armada-370.dtsi" / { @@ -73,19 +74,19 @@ green_pwr_led { label = "mirabox:green:pwr"; - gpios = <&gpio1 31 1>; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; default-state = "keep"; }; blue_stat_led { label = "mirabox:blue:stat"; - gpios = <&gpio2 0 1>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; green_stat_led { label = "mirabox:green:stat"; - gpios = <&gpio2 1 1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-370-rd.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-rd.dts --- linux-3.14.1/arch/arm/boot/dts/armada-370-rd.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-rd.dts 2014-04-13 23:18:35.000000000 +0200 @@ -12,6 +12,8 @@ */ /dts-v1/; +#include +#include #include "armada-370.dtsi" / { @@ -100,8 +102,8 @@ #size-cells = <0>; button@1 { label = "Software Button"; - linux,code = <116>; - gpios = <&gpio0 6 1>; + linux,code = ; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-370-xp.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-xp.dtsi --- linux-3.14.1/arch/arm/boot/dts/armada-370-xp.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-370-xp.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -44,8 +44,8 @@ #size-cells = <1>; controller = <&mbusc>; interrupt-parent = <&mpic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; + pcie-mem-aperture = <0xf8000000 0x7e00000>; + pcie-io-aperture = <0xffe00000 0x100000>; devbus-bootcs { compatible = "marvell,mvebu-devbus"; @@ -199,6 +199,10 @@ interrupts = <37>, <38>, <39>, <40>, <5>, <6>; }; + watchdog@20300 { + reg = <0x20300 0x34>, <0x20704 0x4>; + }; + usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-375-db.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-375-db.dts --- linux-3.14.1/arch/arm/boot/dts/armada-375-db.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-375-db.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,130 @@ +/* + * Device Tree file for Marvell Armada 375 evaluation board + * (DB-88F6720) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include +#include "armada-375.dtsi" + +/ { + model = "Marvell Armada 375 Development Board"; + compatible = "marvell,a375-db", "marvell,armada375"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10600 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + /* + * SPI conflicts with NAND, so we disable it + * here, and select NAND as the enabled device + * by default. + */ + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + }; + + i2c@11100 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + pinctrl { + sdio_st_pins: sdio-st-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "gpio"; + }; + }; + + nand: nand@d0000 { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins &sdio_st_pins>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-375.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/armada-375.dtsi --- linux-3.14.1/arch/arm/boot/dts/armada-375.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-375.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,464 @@ +/* + * Device Tree Include file for Marvell Armada 375 family SoC + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "skeleton.dtsi" +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 375 family SoC"; + compatible = "marvell,armada375"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + }; + + serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + }; + + pinctrl { + compatible = "marvell,mv88f6720-pinctrl"; + reg = <0x18000 0x24>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp61", "mpp62"; + marvell,function = "i2c1"; + }; + + nand_pins: nand-pins { + marvell,pins = "mpp0", "mpp1", "mpp2", + "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13"; + marvell,function = "nand"; + }; + + sdio_pins: sdio-pins { + marvell,pins = "mpp24", "mpp25", "mpp26", + "mpp27", "mpp28", "mpp29"; + marvell,function = "sd"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp0", "mpp1", "mpp4", + "mpp5", "mpp8", "mpp9"; + marvell,function = "spi0"; + }; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + system-controller@18200 { + compatible = "marvell,armada-375-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-375-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20000 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = ; + }; + + timer@20300 { + compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 0>; + }; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60A00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 23>; + status = "okay"; + + xor10 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + sata@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x5000>; + interrupts = ; + clocks = <&gateclk 14>, <&gateclk 20>; + clock-names = "0", "1"; + status = "disabled"; + }; + + nand@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + mvsdio@d4000 { + compatible = "marvell,orion-sdio"; + reg = <0xd4000 0x200>; + interrupts = ; + clocks = <&gateclk 17>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + + coreclk: mvebu-sar@e8204 { + compatible = "marvell,armada-375-core-clock"; + reg = <0xe8204 0x04>; + #clock-cells = <1>; + }; + + coredivclk: corediv-clock@e8250 { + compatible = "marvell,armada-375-corediv-clock"; + reg = <0xe8250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-380.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/armada-380.dtsi --- linux-3.14.1/arch/arm/boot/dts/armada-380.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-380.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,117 @@ +/* + * Device Tree Include file for Marvell Armada 380 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 380 family SoC"; + compatible = "marvell,armada380", "marvell,armada38x"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + internal-regs { + pinctrl { + compatible = "marvell,mv88f6810-pinctrl"; + reg = <0x18000 0x20>; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; + + /* x1 port */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-385-db.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-385-db.dts --- linux-3.14.1/arch/arm/boot/dts/armada-385-db.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-385-db.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,122 @@ +/* + * Device Tree file for Marvell Armada 385 evaluation board + * (DB-88F6820) + * + * Copyright (C) 2014 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "armada-385.dtsi" + +/ { + model = "Marvell Armada 385 Development Board"; + compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q32"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@11100 { + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + flash@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-385.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/armada-385.dtsi --- linux-3.14.1/arch/arm/boot/dts/armada-385.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-385.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,149 @@ +/* + * Device Tree Include file for Marvell Armada 385 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 385 family SoC"; + compatible = "marvell,armada385", "marvell,armada38x"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + internal-regs { + pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-385-rd.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-385-rd.dts --- linux-3.14.1/arch/arm/boot/dts/armada-385-rd.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-385-rd.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,94 @@ +/* + * Device Tree file for Marvell Armada 385 Reference Design board + * (RD-88F6820-AP) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "armada-385.dtsi" + +/ { + model = "Marvell Armada 385 Reference Design"; + compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + pcie-controller { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-38x.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/armada-38x.dtsi --- linux-3.14.1/arch/arm/boot/dts/armada-38x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-38x.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,376 @@ +/* + * Device Tree Include file for Marvell Armada 38x family of SoCs. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "skeleton.dtsi" +#include +#include + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 38x family SoC"; + compatible = "marvell,armada38x"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + eth0 = ð0; + eth1 = ð1; + eth2 = ð2; + }; + + soc { + compatible = "marvell,armada380-mbus", "marvell,armada370-mbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + }; + + serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + }; + + pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <28>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + system-controller@18200 { + compatible = "marvell,armada-380-system-controller", + "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-380-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18600 { + compatible = "marvell,armada-380-core-clock"; + reg = <0x18600 0x04>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20000 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = ; + }; + + timer@20300 { + compatible = "marvell,armada-380-timer", + "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + eth1: ethernet@30000 { + compatible = "marvell,armada-370-neta"; + reg = <0x30000 0x4000>; + interrupts-extended = <&mpic 10>; + clocks = <&gateclk 3>; + status = "disabled"; + }; + + eth2: ethernet@34000 { + compatible = "marvell,armada-370-neta"; + reg = <0x34000 0x4000>; + interrupts-extended = <&mpic 12>; + clocks = <&gateclk 2>; + status = "disabled"; + }; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor10 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = ; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + eth0: ethernet@70000 { + compatible = "marvell,armada-370-neta"; + reg = <0x70000 0x4000>; + interrupts-extended = <&mpic 8>; + clocks = <&gateclk 4>; + status = "disabled"; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + }; + + coredivclk: clock@e4250 { + compatible = "marvell,armada-380-corediv-clock"; + reg = <0xe4250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + + flash@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + }; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-xp-axpwifiap.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-axpwifiap.dts --- linux-3.14.1/arch/arm/boot/dts/armada-xp-axpwifiap.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-axpwifiap.dts 2014-04-13 23:18:35.000000000 +0200 @@ -16,6 +16,8 @@ */ /dts-v1/; +#include +#include #include "armada-xp-mv78230.dtsi" / { @@ -157,8 +159,8 @@ button@1 { label = "Factory Reset Button"; - linux,code = <141>; /* KEY_SETUP */ - gpios = <&gpio1 1 1>; + linux,code = ; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-xp-db.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-db.dts --- linux-3.14.1/arch/arm/boot/dts/armada-xp-db.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-db.dts 2014-04-13 23:18:35.000000000 +0200 @@ -2,7 +2,7 @@ * Device Tree file for Marvell Armada XP evaluation board * (DB-78460-BP) * - * Copyright (C) 2012 Marvell + * Copyright (C) 2012-2014 Marvell * * Lior Amsalem * Gregory CLEMENT @@ -11,6 +11,15 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -30,7 +39,7 @@ }; soc { - ranges = ; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-xp.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp.dtsi --- linux-3.14.1/arch/arm/boot/dts/armada-xp.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -111,6 +111,12 @@ clock-names = "nbclk", "fixed"; }; + watchdog@20300 { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + armada-370-xp-pmsu@22000 { compatible = "marvell,armada-370-xp-pmsu"; reg = <0x22100 0x400>, <0x20800 0x20>; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-xp-gp.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-gp.dts --- linux-3.14.1/arch/arm/boot/dts/armada-xp-gp.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-gp.dts 2014-04-13 23:18:35.000000000 +0200 @@ -2,7 +2,7 @@ * Device Tree file for Marvell Armada XP development board * (DB-MV784MP-GP) * - * Copyright (C) 2013 Marvell + * Copyright (C) 2013-2014 Marvell * * Lior Amsalem * Gregory CLEMENT @@ -11,6 +11,15 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -30,16 +39,17 @@ * 8 GB of plug-in RAM modules by default.The amount * of memory available can be changed by the * bootloader according the size of the module - * actually plugged. Only 7GB are usable because - * addresses from 0xC0000000 to 0xffffffff are used by - * the internal registers of the SoC. + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). */ - reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, + reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, <0x00000001 0x00000000 0x00000001 0x00000000>; }; soc { - ranges = ; diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-xp-matrix.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-matrix.dts --- linux-3.14.1/arch/arm/boot/dts/armada-xp-matrix.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-matrix.dts 2014-04-13 23:18:35.000000000 +0200 @@ -23,7 +23,12 @@ memory { device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ + /* + * This board has 4 GB of RAM, but the last 256 MB of + * RAM are not usable due to the overlap with the MBus + * Window address range + */ + reg = <0 0x00000000 0 0xf0000000>; }; soc { diff -Nur linux-3.14.1/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts --- linux-3.14.1/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts 2014-04-13 23:18:35.000000000 +0200 @@ -11,6 +11,8 @@ */ /dts-v1/; +#include +#include #include "armada-xp-mv78260.dtsi" / { @@ -90,19 +92,19 @@ red_led { label = "red_led"; - gpios = <&gpio1 17 1>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; default-state = "off"; }; yellow_led { label = "yellow_led"; - gpios = <&gpio1 19 1>; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; default-state = "off"; }; green_led { label = "green_led"; - gpios = <&gpio1 21 1>; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; default-state = "keep"; }; }; @@ -114,8 +116,8 @@ button@1 { label = "Init Button"; - linux,code = <116>; - gpios = <&gpio1 28 0>; + linux,code = ; + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91-ariag25.dts linux-3.15-rc1.orig/arch/arm/boot/dts/at91-ariag25.dts --- linux-3.14.1/arch/arm/boot/dts/at91-ariag25.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91-ariag25.dts 2014-04-13 23:18:35.000000000 +0200 @@ -129,7 +129,6 @@ adc0: adc@f804c000 { status = "okay"; atmel,adc-channels-used = <0xf>; - atmel,adc-num-channels = <4>; }; dbgu: serial@fffff200 { diff -Nur linux-3.14.1/arch/arm/boot/dts/at91-cosino.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/at91-cosino.dtsi --- linux-3.14.1/arch/arm/boot/dts/at91-cosino.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91-cosino.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -64,7 +64,6 @@ }; adc0: adc@f804c000 { - atmel,adc-clock-rate = <1000000>; atmel,adc-ts-wires = <4>; atmel,adc-ts-pressure-threshold = <10000>; status = "okay"; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91-cosino_mega2560.dts linux-3.15-rc1.orig/arch/arm/boot/dts/at91-cosino_mega2560.dts --- linux-3.14.1/arch/arm/boot/dts/at91-cosino_mega2560.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91-cosino_mega2560.dts 2014-04-13 23:18:35.000000000 +0200 @@ -27,7 +27,6 @@ }; adc0: adc@f804c000 { - atmel,adc-clock-rate = <1000000>; atmel,adc-ts-wires = <4>; atmel,adc-ts-pressure-threshold = <10000>; status = "okay"; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9260.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9260.dtsi --- linux-3.14.1/arch/arm/boot/dts/at91sam9260.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9260.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -608,37 +608,38 @@ }; adc0: adc@fffe0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xf>; atmel,adc-vref = <3300>; - atmel,adc-num-channels = <4>; atmel,adc-startup-time = <15>; - atmel,adc-channel-base = <0x30>; - atmel,adc-drdy-mask = <0x10000>; - atmel,adc-status-register = <0x1c>; - atmel,adc-trigger-register = <0x04>; atmel,adc-res = <8 10>; atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; trigger@0 { + reg = <0>; trigger-name = "timer-counter-0"; trigger-value = <0x1>; }; trigger@1 { + reg = <1>; trigger-name = "timer-counter-1"; trigger-value = <0x3>; }; trigger@2 { + reg = <2>; trigger-name = "timer-counter-2"; trigger-value = <0x5>; }; trigger@3 { + reg = <3>; trigger-name = "external"; trigger-value = <0x13>; trigger-external; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9261.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9261.dtsi --- linux-3.14.1/arch/arm/boot/dts/at91sam9261.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9261.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,735 @@ +/* + * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC + * + * Copyright (C) 2013 Jean-Jacques Hiblot + * + * Licensed under GPLv2 only. + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include + +/ { + model = "Atmel AT91SAM9261 family SoC"; + compatible = "atmel,at91sam9261"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + tcb0 = &tcb0; + i2c0 = &i2c0; + ssc0 = &ssc0; + ssc1 = &ssc1; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x08000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + fb0: fb@0x00600000 { + compatible = "atmel,at91sam9261-lcdc"; + reg = <0x00600000 0x1000>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&hclk1>; + clock-names = "lcdc_clk", "hclk"; + status = "disabled"; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000>; + atmel,nand-addr-offset = <22>; + atmel,nand-cmd-offset = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + + gpios = <&pioC 15 GPIO_ACTIVE_HIGH>, + <&pioC 14 GPIO_ACTIVE_HIGH>, + <0>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>, + <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91rm9200-udc"; + reg = <0xfffa4000 0x4000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&udc_clk>, <&udpck>; + clock-names = "usb_clk", "udc_clk", "udpck"; + status = "disabled"; + }; + + mmc0: mmc@fffa8000 { + compatible = "atmel,hsmci"; + reg = <0xfffa8000 0x600>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9261-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_twi>; + reg = <0xfffac000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000{ + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fffbc000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffbc000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + status = "disabled"; + }; + + ssc1: ssc@fffc0000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc0000 0x4000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + status = "disabled"; + }; + + spi0: spi@fffc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffc8000 0x200>; + cs-gpios = <0>, <0>, <0>, <0>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ramc: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + matrix: matrix@ffffee00 { + compatible = "atmel,at91sam9260-bus-matrix"; + reg = <0xffffee00 0x200>; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <29 30 31>; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x600>; + + atmel,mux-mask = + /* A B */ + <0xffffffff 0xfffffff7>, /* pioA */ + <0xffffffff 0xfffffff4>, /* pioB */ + <0xffffffff 0xffffff07>; /* pioC */ + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + , + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + , + ; + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + , + , + ; + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + , + , + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + i2c0 { + pinctrl_i2c_bitbang: i2c-0-bitbang { + atmel,pins = + , + ; + }; + pinctrl_i2c_twi: i2c-0-twi { + atmel,pins = + , + ; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + clk32k: slck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&clk32k>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; + atmel,clk-output-range = <0 94000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + usb: usbck { + compatible = "atmel,at91rm9200-clk-usb"; + #clock-cells = <0>; + atmel,clk-divisors = <1 2 4 3>; + clocks = <&pllb>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + hclk0: hclk0 { + #clock-cells = <0>; + reg = <16>; + clocks = <&mck>; + }; + + hclk1: hclk1 { + #clock-cells = <0>; + reg = <17>; + clocks = <&mck>; + }; + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <8>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <9>; + }; + + udc_clk: udc_clk { + #clock-cells = <0>; + reg = <10>; + }; + + twi0_clk: twi0_clk { + reg = <11>; + #clock-cells = <0>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <13>; + }; + + tc0_clk: tc0_clk { + #clock-cells = <0>; + reg = <17>; + }; + + tc1_clk: tc1_clk { + #clock-cells = <0>; + reg = <18>; + }; + + tc2_clk: tc2_clk { + #clock-cells = <0>; + reg = <19>; + }; + + ohci_clk: ohci_clk { + #clock-cells = <0>; + reg = <20>; + }; + + lcd_clk: lcd_clk { + #clock-cells = <0>; + reg = <21>; + }; + }; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_bitbang>; + gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9261ek.dts linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9261ek.dts --- linux-3.14.1/arch/arm/boot/dts/at91sam9261ek.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9261ek.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,211 @@ +/* + * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board + * + * Copyright (C) 2013 Jean-Jacques Hiblot + * + * Licensed under GPLv2 only. + */ +/dts-v1/; +#include "at91sam9261.dtsi" + +/ { + model = "Atmel at91sam9261ek"; + compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <18432000>; + }; + }; + + ahb { + usb0: ohci@00500000 { + status = "okay"; + }; + + fb0: fb@0x00600000 { + display = <&display0>; + atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + atmel,lcd-wiring-mode = "BRG"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + + apb { + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffc8000 { + cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; + status = "okay"; + + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <0>; + spi-max-frequency = <15000000>; + }; + + tsc2046@0 { + reg = <2>; + compatible = "ti,ads7843"; + interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; + spi-max-frequency = <3000000>; + pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; + + ti,x-min = /bits/ 16 <150>; + ti,x-max = /bits/ 16 <3830>; + ti,y-min = /bits/ 16 <190>; + ti,y-max = /bits/ 16 <3830>; + ti,vref-delay-usecs = /bits/ 16 <450>; + ti,x-plate-ohms = /bits/ 16 <450>; + ti,y-plate-ohms = /bits/ 16 <250>; + ti,pressure-max = /bits/ 16 <15000>; + ti,debounce-rep = /bits/ 16 <0>; + ti,debounce-tol = /bits/ 16 <65535>; + ti,debounce-max = /bits/ 16 <1>; + + linux,wakeup; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + }; + }; + + leds { + compatible = "gpio-leds"; + + ds8 { + label = "ds8"; + gpios = <&pioA 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + ds7 { + label = "ds7"; + gpios = <&pioA 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + + ds1 { + label = "ds1"; + gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button_0 { + label = "button_0"; + gpios = <&pioA 27 GPIO_ACTIVE_LOW>; + linux,code = <256>; + gpio-key,wakeup; + }; + + button_1 { + label = "button_1"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + linux,code = <257>; + gpio-key,wakeup; + }; + + button_2 { + label = "button_2"; + gpios = <&pioA 25 GPIO_ACTIVE_LOW>; + linux,code = <258>; + gpio-key,wakeup; + }; + + button_3 { + label = "button_3"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + linux,code = <259>; + gpio-key,wakeup; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9g45.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9g45.dtsi --- linux-3.14.1/arch/arm/boot/dts/at91sam9g45.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9g45.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -632,40 +632,41 @@ }; adc0: adc@fffb0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "atmel,at91sam9260-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; - atmel,adc-num-channels = <8>; atmel,adc-startup-time = <40>; - atmel,adc-channel-base = <0x30>; - atmel,adc-drdy-mask = <0x10000>; - atmel,adc-status-register = <0x1c>; - atmel,adc-trigger-register = <0x08>; atmel,adc-res = <8 10>; atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; trigger@0 { + reg = <0>; trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; trigger@1 { + reg = <1>; trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; trigger@2 { + reg = <2>; trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; trigger@3 { + reg = <3>; trigger-name = "continuous"; trigger-value = <0x6>; }; @@ -817,6 +818,7 @@ >; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; gpios = <&pioC 8 GPIO_ACTIVE_HIGH diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9n12.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9n12.dtsi --- linux-3.14.1/arch/arm/boot/dts/at91sam9n12.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9n12.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -570,6 +570,7 @@ atmel,pmecc-lookup-table-offset = <0x0 0x8000>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; gpios = <&pioD 5 GPIO_ACTIVE_HIGH diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9rl.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9rl.dtsi --- linux-3.14.1/arch/arm/boot/dts/at91sam9rl.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9rl.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,802 @@ +/* + * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC + * + * Copyright (C) 2014 Alexandre Belloni + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include + +/ { + model = "Atmel AT91SAM9RL family SoC"; + compatible = "atmel,at91sam9rl", "atmel,at91sam9"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + ssc0 = &ssc0; + ssc1 = &ssc1; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x04000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000>, + <0xffffe800 0x200>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, + <&pioB 6 GPIO_ACTIVE_HIGH>, + <0>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, + <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; + clock-names = "t0_clk", "t1_clk", "t2_clk"; + }; + + mmc0: mmc@fffa4000 { + compatible = "atmel,hsmci"; + reg = <0xfffa4000 0x600>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + i2c0: i2c@fffa8000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffa8000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@fffac000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffac000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fffbc000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffbc000 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fffc0000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc0000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + status = "disabled"; + }; + + ssc1: ssc@fffc4000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc4000 0x4000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + status = "disabled"; + }; + + spi0: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + + atmel,mux-mask = + /* A B */ + <0xffffffff 0xe05c6738>, /* pioA */ + <0xffffffff 0x0000c780>, /* pioB */ + <0xffffffff 0xe3ffff0e>, /* pioC */ + <0x003fffff 0x0001ff3c>; /* pioD */ + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + , + ; + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + , + ; + }; + }; + + i2c_gpio1 { + pinctrl_i2c_gpio1: i2c_gpio1-0 { + atmel,pins = + , + ; + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + , + , + ; + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + , + ; + }; + + pinctrl_nand0_ale_cle: nand_ale_cle-0 { + atmel,pins = + , + ; + }; + + pinctrl_nand0_oe_we: nand_oe_we-0 { + atmel,pins = + , + ; + }; + + pinctrl_nand0_cs: nand_cs-0 { + atmel,pins = + ; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + , + , + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_dcd: usart0_dcd-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_ri: usart0_ri-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_sck: usart0_sck-0 { + atmel,pins = + ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_sck: usart1_sck-0 { + atmel,pins = + ; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_sck: usart2_sck-0 { + atmel,pins = + ; + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + ; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + }; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9g45-pmc"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + clk32k: slck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&clk32k>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; + atmel,clk-output-range = <0 94000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <4>; + }; + + pioD_clk: pioD_clk { + #clock-cells = <0>; + reg = <5>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <8>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <9>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <10>; + }; + + twi0_clk: twi0_clk { + #clock-cells = <0>; + reg = <11>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <12>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <13>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <15>; + }; + + tc0_clk: tc0_clk { + #clock-cells = <0>; + reg = <16>; + }; + + tc1_clk: tc1_clk { + #clock-cells = <0>; + reg = <17>; + }; + + tc2_clk: tc2_clk { + #clock-cells = <0>; + reg = <18>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <19>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <20>; + }; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <22>; + }; + + lcd_clk: lcd_clk { + #clock-cells = <0>; + reg = <23>; + }; + }; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; + + i2c@1 { + compatible = "i2c-gpio"; + gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio1>; + status = "disabled"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9rlek.dts linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9rlek.dts --- linux-3.14.1/arch/arm/boot/dts/at91sam9rlek.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9rlek.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,157 @@ +/* + * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board + * + * Copyright (C) 2014 Alexandre Belloni + * + * Licensed under GPLv2 only + */ +/dts-v1/; +#include "at91sam9rl.dtsi" + +/ { + model = "Atmel at91sam9rlek"; + compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt = <1>; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + + apb { + mmc0: mmc@fffa4000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = < + &pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts>; + status = "okay"; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; + }; + }; + }; + + pmc: pmc@fffffc00 { + main: mainck { + clock-frequency = <12000000>; + }; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + }; + + ds2 { + label = "ds2"; + gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + }; + + ds3 { + label = "ds3"; + gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + right_click { + label = "right_click"; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; + linux,code = <273>; + gpio-key,wakeup; + }; + + left_click { + label = "left_click"; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; + linux,code = <272>; + gpio-key,wakeup; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/at91sam9x5.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9x5.dtsi --- linux-3.14.1/arch/arm/boot/dts/at91sam9x5.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/at91sam9x5.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -621,41 +621,42 @@ }; adc0: adc@f804c000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "atmel,at91sam9260-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - atmel,adc-use-external; + atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xffff>; atmel,adc-vref = <3300>; - atmel,adc-num-channels = <12>; atmel,adc-startup-time = <40>; - atmel,adc-channel-base = <0x50>; - atmel,adc-drdy-mask = <0x1000000>; - atmel,adc-status-register = <0x30>; - atmel,adc-trigger-register = <0xc0>; atmel,adc-res = <8 10>; atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; trigger@0 { + reg = <0>; trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; trigger@1 { + reg = <1>; trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; trigger@2 { + reg = <2>; trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; trigger@3 { + reg = <3>; trigger-name = "continuous"; trigger-value = <0x6>; }; @@ -790,6 +791,7 @@ atmel,pmecc-lookup-table-offset = <0x0 0x8000>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; gpios = <&pioD 5 GPIO_ACTIVE_HIGH diff -Nur linux-3.14.1/arch/arm/boot/dts/atlas6.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/atlas6.dtsi --- linux-3.14.1/arch/arm/boot/dts/atlas6.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/atlas6.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -65,9 +65,10 @@ #clock-cells = <1>; }; - reset-controller@88010000 { + rstc: reset-controller@88010000 { compatible = "sirf,prima2-rstc"; reg = <0x88010000 0x1000>; + #reset-cells = <1>; }; rsc-controller@88020000 { @@ -217,8 +218,8 @@ interrupts = <17>; fifosize = <128>; clocks = <&clks 13>; - sirf,uart-dma-rx-channel = <21>; - sirf,uart-dma-tx-channel = <2>; + dmas = <&dmac1 5>, <&dmac0 2>; + dma-names = "rx", "tx"; }; uart1: uart@b0060000 { @@ -228,6 +229,7 @@ interrupts = <18>; fifosize = <32>; clocks = <&clks 14>; + dma-names = "no-rx", "no-tx"; }; uart2: uart@b0070000 { @@ -237,8 +239,8 @@ interrupts = <19>; fifosize = <128>; clocks = <&clks 15>; - sirf,uart-dma-rx-channel = <6>; - sirf,uart-dma-tx-channel = <7>; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "rx", "tx"; }; usp0: usp@b0080000 { @@ -248,8 +250,8 @@ interrupts = <20>; fifosize = <128>; clocks = <&clks 28>; - sirf,usp-dma-rx-channel = <17>; - sirf,usp-dma-tx-channel = <18>; + dmas = <&dmac1 1>, <&dmac1 2>; + dma-names = "rx", "tx"; }; usp1: usp@b0090000 { @@ -259,8 +261,8 @@ interrupts = <21>; fifosize = <128>; clocks = <&clks 29>; - sirf,usp-dma-rx-channel = <14>; - sirf,usp-dma-tx-channel = <15>; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "rx", "tx"; }; dmac0: dma-controller@b00b0000 { @@ -269,6 +271,7 @@ reg = <0xb00b0000 0x10000>; interrupts = <12>; clocks = <&clks 24>; + #dma-cells = <1>; }; dmac1: dma-controller@b0160000 { @@ -277,6 +280,7 @@ reg = <0xb0160000 0x10000>; interrupts = <13>; clocks = <&clks 25>; + #dma-cells = <1>; }; vip@b00C0000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm11351-brt.dts linux-3.15-rc1.orig/arch/arm/boot/dts/bcm11351-brt.dts --- linux-3.14.1/arch/arm/boot/dts/bcm11351-brt.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm11351-brt.dts 1970-01-01 01:00:00.000000000 +0100 @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2012 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include "bcm11351.dtsi" - -/ { - model = "BCM11351 BRT board"; - compatible = "brcm,bcm11351-brt", "brcm,bcm11351"; - - memory { - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - uart@3e000000 { - status = "okay"; - }; - - sdio1: sdio@3f180000 { - max-frequency = <48000000>; - status = "okay"; - }; - - sdio2: sdio@3f190000 { - non-removable; - max-frequency = <48000000>; - status = "okay"; - }; - - sdio4: sdio@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 14 0>; - status = "okay"; - }; - - usbotg: usb@3f120000 { - status = "okay"; - }; - - usbphy: usb-phy@3f130000 { - status = "okay"; - }; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm11351.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/bcm11351.dtsi --- linux-3.14.1/arch/arm/boot/dts/bcm11351.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm11351.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -14,6 +14,8 @@ #include #include +#include "dt-bindings/clock/bcm281xx.h" + #include "skeleton.dtsi" / { @@ -43,7 +45,7 @@ compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e000000 0x1000>; - clocks = <&uartb_clk>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -53,7 +55,7 @@ compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e001000 0x1000>; - clocks = <&uartb2_clk>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -63,7 +65,7 @@ compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e002000 0x1000>; - clocks = <&uartb3_clk>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -73,7 +75,7 @@ compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e003000 0x1000>; - clocks = <&uartb4_clk>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -95,7 +97,7 @@ compatible = "brcm,kona-timer"; reg = <0x35006000 0x1000>; interrupts = ; - clocks = <&hub_timer_clk>; + clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; }; gpio: gpio@35003000 { @@ -118,7 +120,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x10000>; interrupts = ; - clocks = <&sdio1_clk>; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; status = "disabled"; }; @@ -126,7 +128,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x10000>; interrupts = ; - clocks = <&sdio2_clk>; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; status = "disabled"; }; @@ -134,7 +136,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x10000>; interrupts = ; - clocks = <&sdio3_clk>; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; status = "disabled"; }; @@ -142,7 +144,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x10000>; interrupts = ; - clocks = <&sdio4_clk>; + clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; status = "disabled"; }; @@ -157,7 +159,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc1_clk>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; status = "disabled"; }; @@ -167,7 +169,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc2_clk>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; status = "disabled"; }; @@ -177,7 +179,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc3_clk>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; status = "disabled"; }; @@ -187,105 +189,191 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&pmu_bsc_clk>; + clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; status = "disabled"; }; clocks { - bsc1_clk: bsc1 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + root_ccu: root_ccu { + compatible = "brcm,bcm11351-root-ccu"; + reg = <0x35001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "frac_1m"; + }; + + hub_ccu: hub_ccu { + compatible = "brcm,bcm11351-hub-ccu"; + reg = <0x34000000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "tmon_1m"; + }; + + aon_ccu: aon_ccu { + compatible = "brcm,bcm11351-aon-ccu"; + reg = <0x35002000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "hub_timer", + "pmu_bsc", + "pmu_bsc_var"; + }; + + master_ccu: master_ccu { + compatible = "brcm,bcm11351-master-ccu"; + reg = <0x3f001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "sdio1", + "sdio2", + "sdio3", + "sdio4", + "usb_ic", + "hsic2_48m", + "hsic2_12m"; + }; + + slave_ccu: slave_ccu { + compatible = "brcm,bcm11351-slave-ccu"; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "uartb4", + "ssp0", + "ssp2", + "bsc1", + "bsc2", + "bsc3", + "pwm"; + }; + + ref_1m_clk: ref_1m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; }; - bsc2_clk: bsc2 { + ref_32k_clk: ref_32k { + #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <13000000>; + clock-frequency = <32768>; + }; + + bbl_32k_clk: bbl_32k { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; }; - bsc3_clk: bsc3 { + ref_13m_clk: ref_13m { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; - #clock-cells = <0>; }; - pmu_bsc_clk: pmu_bsc { + var_13m_clk: var_13m { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; - #clock-cells = <0>; }; - hub_timer_clk: hub_timer { - compatible = "fixed-clock"; - clock-frequency = <32768>; + dft_19_5m_clk: dft_19_5m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19500000>; }; - pwm_clk: pwm { + ref_crystal_clk: ref_crystal { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; - #clock-cells = <0>; }; - sdio1_clk: sdio1 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + ref_cx40_clk: ref_cx40 { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; }; - sdio2_clk: sdio2 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + ref_52m_clk: ref_52m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio3_clk: sdio3 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + var_52m_clk: var_52m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio4_clk: sdio4 { + usb_otg_ahb_clk: usb_otg_ahb { compatible = "fixed-clock"; - clock-frequency = <48000000>; + clock-frequency = <52000000>; #clock-cells = <0>; }; - tmon_1m_clk: tmon_1m { - compatible = "fixed-clock"; - clock-frequency = <1000000>; + ref_96m_clk: ref_96m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; }; - uartb_clk: uartb { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + var_96m_clk: var_96m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; }; - uartb2_clk: uartb2 { + ref_104m_clk: ref_104m { + #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <13000000>; + clock-frequency = <104000000>; + }; + + var_104m_clk: var_104m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; }; - uartb3_clk: uartb3 { + ref_156m_clk: ref_156m { + #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <13000000>; + clock-frequency = <156000000>; + }; + + var_156m_clk: var_156m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; }; - uartb4_clk: uartb4 { + ref_208m_clk: ref_208m { + #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <13000000>; + clock-frequency = <208000000>; + }; + + var_208m_clk: var_208m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <208000000>; }; - usb_otg_ahb_clk: usb_otg_ahb { + ref_312m_clk: ref_312m { + #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <52000000>; + clock-frequency = <312000000>; + }; + + var_312m_clk: var_312m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <312000000>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm21664.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/bcm21664.dtsi --- linux-3.14.1/arch/arm/boot/dts/bcm21664.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm21664.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "skeleton.dtsi" + +/ { + model = "BCM21664 SoC"; + compatible = "brcm,bcm21664"; + interrupt-parent = <&gic>; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gic: interrupt-controller@3ff00100 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x3ff01000 0x1000>, + <0x3ff00100 0x100>; + }; + + smc@0x3404e000 { + compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; + reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ + }; + + uart@3e000000 { + compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x3e000000 0x118>; + clocks = <&uartb_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@3e001000 { + compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x3e001000 0x118>; + clocks = <&uartb2_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@3e002000 { + compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x3e002000 0x118>; + clocks = <&uartb3_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x3ff20000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + brcm,resetmgr@35001f00 { + compatible = "brcm,bcm21664-resetmgr"; + reg = <0x35001f00 0x24>; + }; + + timer@35006000 { + compatible = "brcm,kona-timer"; + reg = <0x35006000 0x1c>; + interrupts = ; + clocks = <&hub_timer_clk>; + }; + + gpio: gpio@35003000 { + compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; + reg = <0x35003000 0x524>; + interrupts = + ; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + sdio1: sdio@3f180000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f180000 0x801c>; + interrupts = ; + clocks = <&sdio1_clk>; + status = "disabled"; + }; + + sdio2: sdio@3f190000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f190000 0x801c>; + interrupts = ; + clocks = <&sdio2_clk>; + status = "disabled"; + }; + + sdio3: sdio@3f1a0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f1a0000 0x801c>; + interrupts = ; + clocks = <&sdio3_clk>; + status = "disabled"; + }; + + sdio4: sdio@3f1b0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x3f1b0000 0x801c>; + interrupts = ; + clocks = <&sdio4_clk>; + status = "disabled"; + }; + + i2c@3e016000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e016000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bsc1_clk>; + status = "disabled"; + }; + + i2c@3e017000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e017000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bsc2_clk>; + status = "disabled"; + }; + + i2c@3e018000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e018000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bsc3_clk>; + status = "disabled"; + }; + + i2c@3e01c000 { + compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; + reg = <0x3e01c000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bsc4_clk>; + status = "disabled"; + }; + + clocks { + bsc1_clk: bsc1 { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + bsc2_clk: bsc2 { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + bsc3_clk: bsc3 { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + bsc4_clk: bsc4 { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + pmu_bsc_clk: pmu_bsc { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + hub_timer_clk: hub_timer { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + pwm_clk: pwm { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + sdio1_clk: sdio1 { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + sdio2_clk: sdio2 { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + sdio3_clk: sdio3 { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + sdio4_clk: sdio4 { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + tmon_1m_clk: tmon_1m { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + #clock-cells = <0>; + }; + + uartb_clk: uartb { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + uartb2_clk: uartb2 { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + uartb3_clk: uartb3 { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + usb_otg_ahb_clk: usb_otg_ahb { + compatible = "fixed-clock"; + clock-frequency = <52000000>; + #clock-cells = <0>; + }; + }; + + usbotg: usb@3f120000 { + compatible = "snps,dwc2"; + reg = <0x3f120000 0x10000>; + interrupts = ; + clocks = <&usb_otg_ahb_clk>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usbphy: usb-phy@3f130000 { + compatible = "brcm,kona-usb2-phy"; + reg = <0x3f130000 0x28>; + #phy-cells = <0>; + status = "disabled"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm21664-garnet.dts linux-3.15-rc1.orig/arch/arm/boot/dts/bcm21664-garnet.dts --- linux-3.14.1/arch/arm/boot/dts/bcm21664-garnet.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm21664-garnet.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include + +#include "bcm21664.dtsi" + +/ { + model = "BCM21664 Garnet board"; + compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; + + memory { + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + uart@3e000000 { + status = "okay"; + }; + + sdio1: sdio@3f180000 { + max-frequency = <48000000>; + status = "okay"; + }; + + sdio2: sdio@3f190000 { + non-removable; + max-frequency = <48000000>; + status = "okay"; + }; + + sdio4: sdio@3f1b0000 { + max-frequency = <48000000>; + cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + usbotg: usb@3f120000 { + status = "okay"; + }; + + usbphy: usb-phy@3f130000 { + status = "okay"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm28155-ap.dts linux-3.15-rc1.orig/arch/arm/boot/dts/bcm28155-ap.dts --- linux-3.14.1/arch/arm/boot/dts/bcm28155-ap.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm28155-ap.dts 2014-04-13 23:18:35.000000000 +0200 @@ -46,27 +46,32 @@ i2c@3500d000 { status="okay"; - clock-frequency = <400000>; - }; + clock-frequency = <100000>; - sdio1: sdio@3f180000 { - max-frequency = <48000000>; - status = "okay"; + pmu: pmu@8 { + reg = <0x08>; + }; }; sdio2: sdio@3f190000 { non-removable; max-frequency = <48000000>; + vmmc-supply = <&camldo1_reg>; + vqmmc-supply = <&iosr1_reg>; status = "okay"; }; sdio4: sdio@3f1b0000 { max-frequency = <48000000>; cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <&sdldo_reg>; + vqmmc-supply = <&sdxldo_reg>; status = "okay"; }; usbotg: usb@3f120000 { + vusb_d-supply = <&usbldo_reg>; + vusb_a-supply = <&iosr1_reg>; status = "okay"; }; @@ -74,3 +79,39 @@ status = "okay"; }; }; + +#include "bcm59056.dtsi" + +&pmu { + compatible = "brcm,bcm59056"; + interrupts = ; + regulators { + camldo1_reg: camldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdldo_reg: sdldo { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + sdxldo_reg: sdxldo { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + }; + + usbldo_reg: usbldo { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + iosr1_reg: iosr1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm2835.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/bcm2835.dtsi --- linux-3.14.1/arch/arm/boot/dts/bcm2835.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm2835.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -15,39 +15,52 @@ #size-cells = <1>; ranges = <0x7e000000 0x20000000 0x02000000>; - timer { + timer@7e003000 { compatible = "brcm,bcm2835-system-timer"; reg = <0x7e003000 0x1000>; interrupts = <1 0>, <1 1>, <1 2>, <1 3>; clock-frequency = <1000000>; }; - intc: interrupt-controller { + dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16>, + <1 17>, + <1 18>, + <1 19>, + <1 20>, + <1 21>, + <1 22>, + <1 23>, + <1 24>, + <1 25>, + <1 26>, + <1 27>, + <1 28>; + + #dma-cells = <1>; + brcm,dma-channel-mask = <0x7f35>; + }; + + intc: interrupt-controller@7e00b200 { compatible = "brcm,bcm2835-armctrl-ic"; reg = <0x7e00b200 0x200>; interrupt-controller; #interrupt-cells = <2>; }; - watchdog { + watchdog@7e100000 { compatible = "brcm,bcm2835-pm-wdt"; reg = <0x7e100000 0x28>; }; - rng { + rng@7e104000 { compatible = "brcm,bcm2835-rng"; reg = <0x7e104000 0x10>; }; - uart@20201000 { - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; - reg = <0x7e201000 0x1000>; - interrupts = <2 25>; - clock-frequency = <3000000>; - arm,primecell-periphid = <0x00241011>; - }; - - gpio: gpio { + gpio: gpio@7e200000 { compatible = "brcm,bcm2835-gpio"; reg = <0x7e200000 0xb4>; /* @@ -70,7 +83,25 @@ #interrupt-cells = <2>; }; - spi: spi@20204000 { + uart@7e201000 { + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x1000>; + interrupts = <2 25>; + clock-frequency = <3000000>; + arm,primecell-periphid = <0x00241011>; + }; + + i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = <0x7e203000 0x20>, + <0x7e101098 0x02>; + + dmas = <&dma 2>, + <&dma 3>; + dma-names = "tx", "rx"; + }; + + spi: spi@7e204000 { compatible = "brcm,bcm2835-spi"; reg = <0x7e204000 0x1000>; interrupts = <2 22>; @@ -90,7 +121,15 @@ status = "disabled"; }; - i2c1: i2c@20804000 { + sdhci: sdhci@7e300000 { + compatible = "brcm,bcm2835-sdhci"; + reg = <0x7e300000 0x100>; + interrupts = <2 30>; + clocks = <&clk_mmc>; + status = "disabled"; + }; + + i2c1: i2c@7e804000 { compatible = "brcm,bcm2835-i2c"; reg = <0x7e804000 0x1000>; interrupts = <2 21>; @@ -100,19 +139,15 @@ status = "disabled"; }; - sdhci: sdhci { - compatible = "brcm,bcm2835-sdhci"; - reg = <0x7e300000 0x100>; - interrupts = <2 30>; - clocks = <&clk_mmc>; - status = "disabled"; - }; - - usb { + usb@7e980000 { compatible = "brcm,bcm2835-usb"; reg = <0x7e980000 0x10000>; interrupts = <1 9>; }; + + arm-pmu { + compatible = "arm,arm1176-pmu"; + }; }; clocks { @@ -120,24 +155,27 @@ #address-cells = <1>; #size-cells = <0>; - clk_mmc: mmc { + clk_mmc: clock@0 { compatible = "fixed-clock"; reg = <0>; #clock-cells = <0>; + clock-output-names = "mmc"; clock-frequency = <100000000>; }; - clk_i2c: i2c { + clk_i2c: clock@1 { compatible = "fixed-clock"; reg = <1>; #clock-cells = <0>; + clock-output-names = "i2c"; clock-frequency = <250000000>; }; - clk_spi: spi { + clk_spi: clock@2 { compatible = "fixed-clock"; reg = <2>; #clock-cells = <0>; + clock-output-names = "spi"; clock-frequency = <250000000>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm4708.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/bcm4708.dtsi --- linux-3.14.1/arch/arm/boot/dts/bcm4708.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm4708.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,34 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for BCM4708 SoC. + * + * Copyright 2013-2014 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include "bcm5301x.dtsi" + +/ { + compatible = "brcm,bcm4708"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm4708-netgear-r6250.dts linux-3.15-rc1.orig/arch/arm/boot/dts/bcm4708-netgear-r6250.dts --- linux-3.14.1/arch/arm/boot/dts/bcm4708-netgear-r6250.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm4708-netgear-r6250.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,35 @@ +/* + * Broadcom BCM470X / BCM5301X arm platform code. + * DTS for Netgear R6250 V1 + * + * Copyright 2013 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "netgear,r6250v1", "brcm,bcm4708"; + model = "Netgear R6250 V1 (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + chipcommonA { + uart0: serial@0300 { + status = "okay"; + }; + + uart1: serial@0400 { + status = "okay"; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm5301x.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/bcm5301x.dtsi --- linux-3.14.1/arch/arm/boot/dts/bcm5301x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm5301x.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,95 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * + * Copyright 2013-2014 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include +#include +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + chipcommonA { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@0300 { + compatible = "ns16550"; + reg = <0x0300 0x100>; + interrupts = ; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart1: serial@0400 { + compatible = "ns16550"; + reg = <0x0400 0x100>; + interrupts = ; + clock-frequency = <100000000>; + status = "disabled"; + }; + }; + + mpcore { + compatible = "simple-bus"; + ranges = <0x00000000 0x19020000 0x00003000>; + #address-cells = <1>; + #size-cells = <1>; + + scu@0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x0000 0x100>; + }; + + timer@0200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x0200 0x100>; + interrupts = ; + clocks = <&clk_periph>; + }; + + local-timer@0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x0600 0x100>; + interrupts = ; + clocks = <&clk_periph>; + }; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x0100 0x100>; + }; + + L2: cache-controller@2000 { + compatible = "arm,pl310-cache"; + reg = <0x2000 0x1000>; + cache-unified; + cache-level = <2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + /* As long as we do not have a real clock driver us this + * fixed clock */ + clk_periph: periph { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/bcm59056.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/bcm59056.dtsi --- linux-3.14.1/arch/arm/boot/dts/bcm59056.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/bcm59056.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,74 @@ +/* +* Copyright 2014 Linaro Limited +* Author: Matt Porter +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +*/ + +&pmu { + compatible = "brcm,bcm59056"; + regulators { + rfldo_reg: rfldo { + }; + + camldo1_reg: camldo1 { + }; + + camldo2_reg: camldo2 { + }; + + simldo1_reg: simldo1 { + }; + + simldo2_reg: simldo2 { + }; + + sdldo_reg: sdldo { + }; + + sdxldo_reg: sdxldo { + }; + + mmcldo1_reg: mmcldo1 { + }; + + mmcldo2_reg: mmcldo2 { + }; + + audldo_reg: audldo { + }; + + micldo_reg: micldo { + }; + + usbldo_reg: usbldo { + }; + + vibldo_reg: vibldo { + }; + + csr_reg: csr { + }; + + iosr1_reg: iosr1 { + }; + + iosr2_reg: iosr2 { + }; + + msr_reg: msr { + }; + + sdsr1_reg: sdsr1 { + }; + + sdsr2_reg: sdsr2 { + }; + + vsr_reg: vsr { + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/dove.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/dove.dtsi --- linux-3.14.1/arch/arm/boot/dts/dove.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/dove.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -186,6 +186,11 @@ reg = <0x20000 0x80>, <0x800100 0x8>; }; + sysc: system-ctrl@20000 { + compatible = "marvell,orion-system-controller"; + reg = <0x20000 0x110>; + }; + bridge_intc: bridge-interrupt-ctrl@20110 { compatible = "marvell,orion-bridge-intc"; interrupt-controller; @@ -210,6 +215,14 @@ clocks = <&core_clk 0>; }; + watchdog@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>, <0x20108 0x4>; + interrupt-parent = <&bridge_intc>; + interrupts = <3>; + clocks = <&core_clk 0>; + }; + crypto: crypto-engine@30000 { compatible = "marvell,orion-crypto"; reg = <0x30000 0x10000>, @@ -381,7 +394,8 @@ pinctrl: pin-ctrl@d0200 { compatible = "marvell,dove-pinctrl"; - reg = <0xd0200 0x10>; + reg = <0xd0200 0x14>, + <0xd0440 0x04>; clocks = <&gate_clk 22>; pmx_gpio_0: pmx-gpio-0 { @@ -603,6 +617,12 @@ reg = <0xd8500 0x20>; }; + gconf: global-config@e802c { + compatible = "marvell,dove-global-config", + "syscon"; + reg = <0xe802c 0x14>; + }; + gpio2: gpio-ctrl@e8400 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; diff -Nur linux-3.14.1/arch/arm/boot/dts/dra7.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/dra7.dtsi --- linux-3.14.1/arch/arm/boot/dts/dra7.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/dra7.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -47,6 +47,11 @@ 1000000 1060000 1176000 1160000 >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ }; cpu@1 { device_type = "cpu"; @@ -149,6 +154,22 @@ ti,hwmods = "counter_32k"; }; + dra7_ctrl_general: tisyscon@4a002e00 { + compatible = "syscon"; + reg = <0x4a002e00 0x7c>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0 0x4>; + syscon = <&dra7_ctrl_general>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + dra7_pmx_core: pinmux@4a003400 { compatible = "pinctrl-single"; reg = <0x4a003400 0x0464>; @@ -464,6 +485,20 @@ ti,hwmods = "wd_timer2"; }; + hwspinlock: spinlock@4a0f6000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x4a0f6000 0x1000>; + ti,hwmods = "spinlock"; + #hwlock-cells = <1>; + }; + + dmm@4e000000 { + compatible = "ti,omap5-dmm"; + reg = <0x4e000000 0x800>; + interrupts = <0 113 0x4>; + ti,hwmods = "dmm"; + }; + i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; @@ -524,6 +559,7 @@ dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; status = "disabled"; + pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { @@ -559,6 +595,138 @@ status = "disabled"; }; + abb_mpu: regulator-abb-mpu { + compatible = "ti,abb-v3"; + regulator-name = "abb_mpu"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, + <0x4ae06014 0x4>, <0x4a003b20 0x8>, + <0x4ae0c158 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x80>; + /* LDOVBBMPU_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBMPU_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1060000 0 0x0 0 0x02000000 0x01F00000 + 1160000 0 0x4 0 0x02000000 0x01F00000 + 1210000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + + abb_ivahd: regulator-abb-ivahd { + compatible = "ti,abb-v3"; + regulator-name = "abb_ivahd"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, + <0x4ae06010 0x4>, <0x4a0025cc 0x8>, + <0x4a002470 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x40000000>; + /* LDOVBBIVA_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBIVA_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1055000 0 0x0 0 0x02000000 0x01F00000 + 1150000 0 0x4 0 0x02000000 0x01F00000 + 1250000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + + abb_dspeve: regulator-abb-dspeve { + compatible = "ti,abb-v3"; + regulator-name = "abb_dspeve"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, + <0x4ae06010 0x4>, <0x4a0025e0 0x8>, + <0x4a00246c 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x20000000>; + /* LDOVBBDSPEVE_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBDSPEVE_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1055000 0 0x0 0 0x02000000 0x01F00000 + 1150000 0 0x4 0 0x02000000 0x01F00000 + 1250000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + + abb_gpu: regulator-abb-gpu { + compatible = "ti,abb-v3"; + regulator-name = "abb_gpu"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin1>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, + <0x4ae06010 0x4>, <0x4a003b08 0x8>, + <0x4ae0c154 0x4>; + reg-names = "setup-address", "control-address", + "int-address", "efuse-address", + "ldo-address"; + ti,tranxdone-status-mask = <0x10000000>; + /* LDOVBBGPU_FBB_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBGPU_FBB_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1090000 0 0x0 0 0x02000000 0x01F00000 + 1210000 0 0x4 0 0x02000000 0x01F00000 + 1280000 0 0x8 0 0x02000000 0x01F00000 + >; + }; + mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; diff -Nur linux-3.14.1/arch/arm/boot/dts/efm32gg-dk3750.dts linux-3.15-rc1.orig/arch/arm/boot/dts/efm32gg-dk3750.dts --- linux-3.14.1/arch/arm/boot/dts/efm32gg-dk3750.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/efm32gg-dk3750.dts 2014-04-13 23:18:35.000000000 +0200 @@ -26,7 +26,7 @@ }; i2c@4000a000 { - location = <3>; + efm32,location = <3>; status = "ok"; temp@48 { diff -Nur linux-3.14.1/arch/arm/boot/dts/efm32gg.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/efm32gg.dtsi --- linux-3.14.1/arch/arm/boot/dts/efm32gg.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/efm32gg.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -84,7 +84,7 @@ status = "disabled"; }; - spi2: spi@40x4000c800 { /* USART2 */ + spi2: spi@4000c800 { /* USART2 */ #address-cells = <1>; #size-cells = <0>; compatible = "efm32,spi"; @@ -110,7 +110,7 @@ status = "disabled"; }; - uart2: uart@40x4000c800 { /* USART2 */ + uart2: uart@4000c800 { /* USART2 */ compatible = "efm32,uart"; reg = <0x4000c800 0x400>; interrupts = <18 19>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4210.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos4210.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -23,7 +23,7 @@ #include "exynos4210-pinctrl.dtsi" / { - compatible = "samsung,exynos4210"; + compatible = "samsung,exynos4210", "samsung,exynos4"; aliases { pinctrl0 = &pinctrl_0; @@ -53,7 +53,7 @@ reg = <0x10050000 0x800>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>; - clocks = <&clock 3>, <&clock 344>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map { @@ -109,7 +109,7 @@ interrupt-parent = <&combiner>; reg = <0x100C0000 0x100>; interrupts = <2 4>; - clocks = <&clock 383>; + clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; status = "disabled"; }; @@ -118,13 +118,14 @@ compatible = "samsung,s5pv210-g2d"; reg = <0x12800000 0x1000>; interrupts = <0 89 0>; - clocks = <&clock 177>, <&clock 277>; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; }; camera { - clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; fimc_0: fimc@11800000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4210-origen.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-origen.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4210-origen.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-origen.dts 2014-04-13 23:18:35.000000000 +0200 @@ -19,7 +19,7 @@ / { model = "Insignal Origen evaluation board based on Exynos4210"; - compatible = "insignal,origen", "samsung,exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; memory { reg = <0x40000000 0x10000000 diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4210-smdkv310.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-smdkv310.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4210-smdkv310.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-smdkv310.dts 2014-04-13 23:18:35.000000000 +0200 @@ -19,7 +19,7 @@ / { model = "Samsung smdkv310 evaluation board based on Exynos4210"; - compatible = "samsung,smdkv310", "samsung,exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; memory { reg = <0x40000000 0x80000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4210-trats.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-trats.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4210-trats.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-trats.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,7 +17,7 @@ / { model = "Samsung Trats based on Exynos4210"; - compatible = "samsung,trats", "samsung,exynos4210"; + compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; memory { reg = <0x40000000 0x10000000 @@ -353,6 +353,67 @@ }; }; + dsi_0: dsi@11C80000 { + vddcore-supply = <&vusb_reg>; + vddio-supply = <&vmipi_reg>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&dsi_in>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + }; + }; + }; + + panel@0 { + reg = <0>; + compatible = "samsung,s6e8aa0"; + vdd3-supply = <&vcclcd_reg>; + vci-supply = <&vlcd_reg>; + reset-gpios = <&gpy4 5 0>; + power-on-delay= <50>; + reset-delay = <100>; + init-delay = <100>; + flip-horizontal; + flip-vertical; + panel-width-mm = <58>; + panel-height-mm = <103>; + + display-timings { + timing-0 { + clock-frequency = <57153600>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <5>; + hback-porch = <5>; + hsync-len = <5>; + vfront-porch = <13>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; + + port { + dsi_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + + fimd@11c00000 { + status = "okay"; + }; + camera { pinctrl-names = "default"; pinctrl-0 = <>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4210-universal_c210.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-universal_c210.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4210-universal_c210.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4210-universal_c210.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,7 +17,7 @@ / { model = "Samsung Universal C210 based on Exynos4210 rev0"; - compatible = "samsung,universal_c210", "samsung,exynos4210"; + compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; memory { reg = <0x40000000 0x10000000 @@ -344,6 +344,70 @@ }; }; }; + + spi-lcd { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpy3 1 0>; + gpio-mosi = <&gpy3 3 0>; + num-chipselects = <1>; + cs-gpios = <&gpy4 3 0>; + + lcd@0 { + compatible = "samsung,ld9040"; + reg = <0>; + vdd3-supply = <&ldo7_reg>; + vci-supply = <&ldo17_reg>; + reset-gpios = <&gpy4 5 0>; + spi-max-frequency = <1200000>; + spi-cpol; + spi-cpha; + power-on-delay = <10>; + reset-delay = <10>; + panel-width-mm = <90>; + panel-height-mm = <154>; + display-timings { + timing { + clock-frequency = <23492370>; + hactive = <480>; + vactive = <800>; + hback-porch = <16>; + hfront-porch = <16>; + vback-porch = <2>; + vfront-porch = <28>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_dpi_ep>; + }; + }; + }; + }; + + fimd: fimd@11c00000 { + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + status = "okay"; + samsung,invert-vden; + samsung,invert-vclk; + #address-cells = <1>; + #size-cells = <0>; + port@3 { + reg = <3>; + fimd_dpi_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; + }; pwm@139D0000 { compatible = "samsung,s5p6440-pwm"; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4212.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4212.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos4212.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4212.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -20,18 +20,13 @@ #include "exynos4x12.dtsi" / { - compatible = "samsung,exynos4212"; + compatible = "samsung,exynos4212", "samsung,exynos4"; - gic: interrupt-controller@10490000 { - cpu-offset = <0x8000>; + combiner: interrupt-controller@10440000 { + samsung,combiner-nr = <18>; }; - interrupt-controller@10440000 { - samsung,combiner-nr = <18>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>; + gic: interrupt-controller@10490000 { + cpu-offset = <0x8000>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4412.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos4412.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -20,19 +20,13 @@ #include "exynos4x12.dtsi" / { - compatible = "samsung,exynos4412"; + compatible = "samsung,exynos4412", "samsung,exynos4"; - gic: interrupt-controller@10490000 { - cpu-offset = <0x4000>; - }; - - interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <20>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; }; + gic: interrupt-controller@10490000 { + cpu-offset = <0x4000>; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4412-odroidx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-odroidx.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4412-odroidx.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-odroidx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -16,7 +16,7 @@ / { model = "Hardkernel ODROID-X board based on Exynos4412"; - compatible = "hardkernel,odroid-x", "samsung,exynos4412"; + compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; memory { reg = <0x40000000 0x40000000>; @@ -251,7 +251,7 @@ buck2_reg: BUCK2 { regulator-name = "vdd_arm"; regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4412-origen.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-origen.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4412-origen.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-origen.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,7 +17,7 @@ / { model = "Insignal Origen evaluation board based on Exynos4412"; - compatible = "insignal,origen4412", "samsung,exynos4412"; + compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; memory { reg = <0x40000000 0x40000000>; @@ -459,8 +459,8 @@ buck2_reg: BUCK2 { regulator-name = "vdd_arm"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; op_mode = <1>; /* Normal Mode */ diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4412-smdk4412.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-smdk4412.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4412-smdk4412.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-smdk4412.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,7 +17,7 @@ / { model = "Samsung SMDK evaluation board based on Exynos4412"; - compatible = "samsung,smdk4412", "samsung,exynos4412"; + compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; memory { reg = <0x40000000 0x40000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4412-tiny4412.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-tiny4412.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4412-tiny4412.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-tiny4412.dts 2014-04-13 23:18:35.000000000 +0200 @@ -16,7 +16,7 @@ / { model = "FriendlyARM TINY4412 board based on Exynos4412"; - compatible = "friendlyarm,tiny4412", "samsung,exynos4412"; + compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; memory { reg = <0x40000000 0x40000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4412-trats2.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-trats2.dts --- linux-3.14.1/arch/arm/boot/dts/exynos4412-trats2.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4412-trats2.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,7 +17,7 @@ / { model = "Samsung Trats 2 based on Exynos4412"; - compatible = "samsung,trats2", "samsung,exynos4412"; + compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; aliases { i2c8 = &i2c_ak8975; @@ -71,6 +71,15 @@ enable-active-high; }; + lcd_vdd3_reg: voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "LCD_VDD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + gpio = <&gpc0 1 0>; + enable-active-high; + }; + /* More to come */ }; @@ -106,6 +115,11 @@ }; }; + adc: adc@126C0000 { + vdd-supply = <&ldo3_reg>; + status = "okay"; + }; + i2c@13890000 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -511,6 +525,67 @@ }; }; + dsi_0: dsi@11C80000 { + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&dsi_in>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + }; + }; + }; + + panel@0 { + compatible = "samsung,s6e8aa0"; + reg = <0>; + vdd3-supply = <&lcd_vdd3_reg>; + vci-supply = <&ldo25_reg>; + reset-gpios = <&gpy4 5 0>; + power-on-delay= <50>; + reset-delay = <100>; + init-delay = <100>; + flip-horizontal; + flip-vertical; + panel-width-mm = <58>; + panel-height-mm = <103>; + + display-timings { + timing-0 { + clock-frequency = <0>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <5>; + hback-porch = <5>; + hsync-len = <5>; + vfront-porch = <13>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; + + port { + dsi_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + + fimd@11c00000 { + status = "okay"; + }; + camera { pinctrl-0 = <&cam_port_b_clk_active>; pinctrl-names = "default"; @@ -589,4 +664,20 @@ }; }; }; + + thermistor-ap@0 { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; /* VCC_1.8V_AP */ + pullup-ohm = <100000>; /* 100K */ + pulldown-ohm = <100000>; /* 100K */ + io-channels = <&adc 1>; /* AP temperature */ + }; + + thermistor-battery@1 { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; /* VCC_1.8V_AP */ + pullup-ohm = <100000>; /* 100K */ + pulldown-ohm = <100000>; /* 100K */ + io-channels = <&adc 2>; /* Battery temperature */ + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos4.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -19,6 +19,7 @@ * published by the Free Software Foundation. */ +#include #include "skeleton.dtsi" / { @@ -85,6 +86,11 @@ reg = <0x10023CE0 0x20>; }; + pd_gps_alive: gps-alive-power-domain@10023D00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023D00 0x20>; + }; + gic: interrupt-controller@10490000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -104,6 +110,20 @@ reg = <0x10010000 0x400>; }; + dsi_0: dsi@11C80000 { + compatible = "samsung,exynos4210-mipi-dsi"; + reg = <0x11C80000 0x10000>; + interrupts = <0 79 0>; + samsung,power-domain = <&pd_lcd0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&clock 286>, <&clock 143>; + clock-names = "bus_clk", "pll_clk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + camera { compatible = "samsung,fimc", "simple-bus"; status = "disabled"; @@ -119,7 +139,7 @@ compatible = "samsung,exynos4210-fimc"; reg = <0x11800000 0x1000>; interrupts = <0 84 0>; - clocks = <&clock 256>, <&clock 128>; + clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; clock-names = "fimc", "sclk_fimc"; samsung,power-domain = <&pd_cam>; samsung,sysreg = <&sys_reg>; @@ -130,7 +150,7 @@ compatible = "samsung,exynos4210-fimc"; reg = <0x11810000 0x1000>; interrupts = <0 85 0>; - clocks = <&clock 257>, <&clock 129>; + clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; clock-names = "fimc", "sclk_fimc"; samsung,power-domain = <&pd_cam>; samsung,sysreg = <&sys_reg>; @@ -141,7 +161,7 @@ compatible = "samsung,exynos4210-fimc"; reg = <0x11820000 0x1000>; interrupts = <0 86 0>; - clocks = <&clock 258>, <&clock 130>; + clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; clock-names = "fimc", "sclk_fimc"; samsung,power-domain = <&pd_cam>; samsung,sysreg = <&sys_reg>; @@ -152,7 +172,7 @@ compatible = "samsung,exynos4210-fimc"; reg = <0x11830000 0x1000>; interrupts = <0 87 0>; - clocks = <&clock 259>, <&clock 131>; + clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; clock-names = "fimc", "sclk_fimc"; samsung,power-domain = <&pd_cam>; samsung,sysreg = <&sys_reg>; @@ -163,7 +183,7 @@ compatible = "samsung,exynos4210-csis"; reg = <0x11880000 0x4000>; interrupts = <0 78 0>; - clocks = <&clock 260>, <&clock 134>; + clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; clock-names = "csis", "sclk_csis"; bus-width = <4>; samsung,power-domain = <&pd_cam>; @@ -178,7 +198,7 @@ compatible = "samsung,exynos4210-csis"; reg = <0x11890000 0x4000>; interrupts = <0 80 0>; - clocks = <&clock 261>, <&clock 135>; + clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; clock-names = "csis", "sclk_csis"; bus-width = <2>; samsung,power-domain = <&pd_cam>; @@ -194,7 +214,7 @@ compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; interrupts = <0 43 0>; - clocks = <&clock 345>; + clocks = <&clock CLK_WDT>; clock-names = "watchdog"; status = "disabled"; }; @@ -203,7 +223,7 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 44 0>, <0 45 0>; - clocks = <&clock 346>; + clocks = <&clock CLK_RTC>; clock-names = "rtc"; status = "disabled"; }; @@ -212,7 +232,7 @@ compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; interrupts = <0 109 0>; - clocks = <&clock 347>; + clocks = <&clock CLK_KEYIF>; clock-names = "keypad"; status = "disabled"; }; @@ -221,7 +241,7 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; interrupts = <0 73 0>; - clocks = <&clock 297>, <&clock 145>; + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -230,7 +250,7 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; interrupts = <0 74 0>; - clocks = <&clock 298>, <&clock 146>; + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -239,7 +259,7 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; interrupts = <0 75 0>; - clocks = <&clock 299>, <&clock 147>; + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -248,7 +268,7 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; interrupts = <0 76 0>; - clocks = <&clock 300>, <&clock 148>; + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -257,7 +277,7 @@ compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; interrupts = <0 70 0>; - clocks = <&clock 304>; + clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; }; @@ -266,7 +286,7 @@ compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; interrupts = <0 70 0>; - clocks = <&clock 304>; + clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; }; @@ -276,7 +296,7 @@ reg = <0x13400000 0x10000>; interrupts = <0 94 0>; samsung,power-domain = <&pd_mfc>; - clocks = <&clock 273>; + clocks = <&clock CLK_MFC>; clock-names = "mfc"; status = "disabled"; }; @@ -285,7 +305,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; interrupts = <0 52 0>; - clocks = <&clock 312>, <&clock 151>; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -294,7 +314,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; interrupts = <0 53 0>; - clocks = <&clock 313>, <&clock 152>; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -303,7 +323,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; - clocks = <&clock 314>, <&clock 153>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -312,7 +332,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13830000 0x100>; interrupts = <0 55 0>; - clocks = <&clock 315>, <&clock 154>; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -323,7 +343,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; interrupts = <0 58 0>; - clocks = <&clock 317>; + clocks = <&clock CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; @@ -336,7 +356,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; interrupts = <0 59 0>; - clocks = <&clock 318>; + clocks = <&clock CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; @@ -349,7 +369,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; interrupts = <0 60 0>; - clocks = <&clock 319>; + clocks = <&clock CLK_I2C2>; clock-names = "i2c"; status = "disabled"; }; @@ -360,7 +380,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; interrupts = <0 61 0>; - clocks = <&clock 320>; + clocks = <&clock CLK_I2C3>; clock-names = "i2c"; status = "disabled"; }; @@ -371,7 +391,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; interrupts = <0 62 0>; - clocks = <&clock 321>; + clocks = <&clock CLK_I2C4>; clock-names = "i2c"; status = "disabled"; }; @@ -382,7 +402,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; interrupts = <0 63 0>; - clocks = <&clock 322>; + clocks = <&clock CLK_I2C5>; clock-names = "i2c"; status = "disabled"; }; @@ -393,7 +413,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; interrupts = <0 64 0>; - clocks = <&clock 323>; + clocks = <&clock CLK_I2C6>; clock-names = "i2c"; status = "disabled"; }; @@ -404,7 +424,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; interrupts = <0 65 0>; - clocks = <&clock 324>; + clocks = <&clock CLK_I2C7>; clock-names = "i2c"; status = "disabled"; }; @@ -417,7 +437,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 327>, <&clock 159>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; @@ -432,7 +452,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 328>, <&clock 160>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; @@ -447,7 +467,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 329>, <&clock 161>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; @@ -458,7 +478,7 @@ compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; - clocks = <&clock 336>; + clocks = <&clock CLK_PWM>; clock-names = "timers"; #pwm-cells = <2>; status = "disabled"; @@ -475,7 +495,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <0 35 0>; - clocks = <&clock 292>; + clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -486,7 +506,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <0 36 0>; - clocks = <&clock 293>; + clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -497,7 +517,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = <0 34 0>; - clocks = <&clock 279>; + clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -511,7 +531,7 @@ reg = <0x11c00000 0x20000>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock 140>, <&clock 283>; + clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; samsung,power-domain = <&pd_lcd0>; status = "disabled"; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos4x12.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4x12.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos4x12.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos4x12.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -31,6 +31,12 @@ mshc0 = &mshc_0; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + }; + pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; @@ -47,7 +53,7 @@ reg = <0x10050000 0x800>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>; - clocks = <&clock 3>, <&clock 344>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map { @@ -62,6 +68,14 @@ }; }; + combiner: interrupt-controller@10440000 { + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; + }; + pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; @@ -80,6 +94,18 @@ }; }; + adc: adc@126C0000 { + compatible = "samsung,exynos-adc-v1"; + reg = <0x126C0000 0x100>, <0x10020718 0x4>; + interrupt-parent = <&combiner>; + interrupts = <10 3>; + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + pinctrl_2: pinctrl@03860000 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x03860000 0x1000>; @@ -97,13 +123,14 @@ compatible = "samsung,exynos4212-g2d"; reg = <0x10800000 0x1000>; interrupts = <0 89 0>; - clocks = <&clock 177>, <&clock 277>; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; }; camera { - clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; fimc_0: fimc@11800000 { @@ -145,7 +172,7 @@ reg = <0x12390000 0x1000>; interrupts = <0 105 0>; samsung,power-domain = <&pd_isp>; - clocks = <&clock 353>; + clocks = <&clock CLK_FIMC_LITE0>; clock-names = "flite"; status = "disabled"; }; @@ -155,7 +182,7 @@ reg = <0x123A0000 0x1000>; interrupts = <0 106 0>; samsung,power-domain = <&pd_isp>; - clocks = <&clock 354>; + clocks = <&clock CLK_FIMC_LITE1>; clock-names = "flite"; status = "disabled"; }; @@ -165,12 +192,19 @@ reg = <0x12000000 0x260000>; interrupts = <0 90 0>, <0 95 0>; samsung,power-domain = <&pd_isp>; - clocks = <&clock 353>, <&clock 354>, <&clock 355>, - <&clock 356>, <&clock 17>, <&clock 357>, - <&clock 358>, <&clock 359>, <&clock 360>, - <&clock 450>,<&clock 451>, <&clock 452>, - <&clock 453>, <&clock 176>, <&clock 13>, - <&clock 454>, <&clock 395>, <&clock 455>; + clocks = <&clock CLK_FIMC_LITE0>, + <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, + <&clock CLK_PPMUISPMX>, + <&clock CLK_MOUT_MPLL_USER_T>, + <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, + <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, + <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, + <&clock CLK_DIV_MCUISP0>, + <&clock CLK_DIV_MCUISP1>, + <&clock CLK_SCLK_UART_ISP>, + <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, + <&clock CLK_ACLK400_MCUISP>, + <&clock CLK_DIV_ACLK400_MCUISP>; clock-names = "lite0", "lite1", "ppmuispx", "ppmuispmx", "mpll", "isp", "drc", "fd", "mcuisp", @@ -190,7 +224,7 @@ i2c1_isp: i2c-isp@12140000 { compatible = "samsung,exynos4212-i2c-isp"; reg = <0x12140000 0x100>; - clocks = <&clock 370>; + clocks = <&clock CLK_I2C1_ISP>; clock-names = "i2c_isp"; #address-cells = <1>; #size-cells = <0>; @@ -205,7 +239,7 @@ #address-cells = <1>; #size-cells = <0>; fifo-depth = <0x80>; - clocks = <&clock 301>, <&clock 149>; + clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; clock-names = "biu", "ciu"; status = "disabled"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5250-arndale.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250-arndale.dts --- linux-3.14.1/arch/arm/boot/dts/exynos5250-arndale.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250-arndale.dts 2014-04-13 23:18:35.000000000 +0200 @@ -15,7 +15,7 @@ / { model = "Insignal Arndale evaluation board based on EXYNOS5250"; - compatible = "insignal,arndale", "samsung,exynos5250"; + compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; memory { reg = <0x40000000 0x80000000>; @@ -25,6 +25,10 @@ bootargs = "console=ttySAC2,115200"; }; + rtc@101E0000 { + status = "okay"; + }; + codec@11000000 { samsung,mfc-r = <0x43000000 0x800000>; samsung,mfc-l = <0x51000000 0x800000>; @@ -287,6 +291,7 @@ regulator-name = "vdd_g3d"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-always-on; regulator-boot-on; op_mode = <1>; }; @@ -370,6 +375,27 @@ }; }; + i2c@121D0000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; + samsung,i2c-slave-addr = <0x38>; + + sata_phy_i2c:sata-phy@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; + }; + }; + + sata@122F0000 { + status = "okay"; + }; + + sata-phy@12170000 { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; + }; + mmc_0: mmc@12200000 { status = "okay"; num-slots = <1>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5250.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos5250.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -17,13 +17,14 @@ * published by the Free Software Foundation. */ +#include #include "exynos5.dtsi" #include "exynos5250-pinctrl.dtsi" -#include +#include / { - compatible = "samsung,exynos5250"; + compatible = "samsung,exynos5250", "samsung,exynos5"; aliases { spi0 = &spi_0; @@ -46,6 +47,7 @@ i2c6 = &i2c_6; i2c7 = &i2c_7; i2c8 = &i2c_8; + i2c9 = &i2c_9; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -90,7 +92,8 @@ compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; @@ -115,7 +118,7 @@ interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>; - clocks = <&clock 1>, <&clock 335>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map { @@ -167,16 +170,25 @@ interrupts = <0 47 0>; }; - watchdog { - clocks = <&clock 336>; + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5250-pmu", "syscon"; + reg = <0x10040000 0x5000>; + }; + + watchdog@101D0000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + clocks = <&clock CLK_WDT>; clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; }; g2d@10850000 { compatible = "samsung,exynos5250-g2d"; reg = <0x10850000 0x1000>; interrupts = <0 91 0>; - clocks = <&clock 345>; + clocks = <&clock CLK_G2D>; clock-names = "fimg2d"; }; @@ -185,55 +197,64 @@ reg = <0x11000000 0x10000>; interrupts = <0 96 0>; samsung,power-domain = <&pd_mfc>; - clocks = <&clock 266>; + clocks = <&clock CLK_MFC>; clock-names = "mfc"; }; rtc@101E0000 { - clocks = <&clock 337>; + clocks = <&clock CLK_RTC>; clock-names = "rtc"; - status = "okay"; + status = "disabled"; }; tmu@10060000 { compatible = "samsung,exynos5250-tmu"; reg = <0x10060000 0x100>; interrupts = <0 65 0>; - clocks = <&clock 338>; + clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; }; serial@12C00000 { - clocks = <&clock 289>, <&clock 146>; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C10000 { - clocks = <&clock 290>, <&clock 147>; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C20000 { - clocks = <&clock 291>, <&clock 148>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C30000 { - clocks = <&clock 292>, <&clock 149>; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; }; sata@122F0000 { - compatible = "samsung,exynos5-sata-ahci"; + compatible = "snps,dwc-ahci"; + samsung,sata-freq = <66>; reg = <0x122F0000 0x1ff>; interrupts = <0 115 0>; - clocks = <&clock 277>, <&clock 143>; + clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; clock-names = "sata", "sclk_sata"; + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; }; - sata-phy@12170000 { - compatible = "samsung,exynos5-sata-phy"; + sata_phy: sata-phy@12170000 { + compatible = "samsung,exynos5250-sata-phy"; reg = <0x12170000 0x1ff>; + clocks = <&clock 287>; + clock-names = "sata_phyctrl"; + #phy-cells = <0>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; }; i2c_0: i2c@12C60000 { @@ -242,7 +263,7 @@ interrupts = <0 56 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 294>; + clocks = <&clock CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; @@ -255,7 +276,7 @@ interrupts = <0 57 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 295>; + clocks = <&clock CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; @@ -268,7 +289,7 @@ interrupts = <0 58 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 296>; + clocks = <&clock CLK_I2C2>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; @@ -281,7 +302,7 @@ interrupts = <0 59 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 297>; + clocks = <&clock CLK_I2C3>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; @@ -294,7 +315,7 @@ interrupts = <0 60 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 298>; + clocks = <&clock CLK_I2C4>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c4_bus>; @@ -307,7 +328,7 @@ interrupts = <0 61 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 299>; + clocks = <&clock CLK_I2C5>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c5_bus>; @@ -320,7 +341,7 @@ interrupts = <0 62 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 300>; + clocks = <&clock CLK_I2C6>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c6_bus>; @@ -333,7 +354,7 @@ interrupts = <0 63 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 301>; + clocks = <&clock CLK_I2C7>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c7_bus>; @@ -346,17 +367,17 @@ interrupts = <0 64 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 302>; + clocks = <&clock CLK_I2C_HDMI>; clock-names = "i2c"; status = "disabled"; }; - i2c@121D0000 { + i2c_9: i2c@121D0000 { compatible = "samsung,exynos5-sata-phy-i2c"; reg = <0x121D0000 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 288>; + clocks = <&clock CLK_SATA_PHYI2C>; clock-names = "i2c"; status = "disabled"; }; @@ -371,7 +392,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 304>, <&clock 154>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; @@ -387,7 +408,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 305>, <&clock 155>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; @@ -403,7 +424,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 306>, <&clock 156>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; @@ -415,7 +436,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x1000>; - clocks = <&clock 280>, <&clock 139>; + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; status = "disabled"; @@ -427,7 +448,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x1000>; - clocks = <&clock 281>, <&clock 140>; + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; status = "disabled"; @@ -439,7 +460,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; - clocks = <&clock 282>, <&clock 141>; + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; status = "disabled"; @@ -451,7 +472,7 @@ interrupts = <0 78 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 283>, <&clock 142>; + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; status = "disabled"; @@ -481,7 +502,7 @@ dmas = <&pdma1 12 &pdma1 11>; dma-names = "tx", "rx"; - clocks = <&clock 307>, <&clock 157>; + clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; @@ -494,7 +515,7 @@ dmas = <&pdma0 12 &pdma0 11>; dma-names = "tx", "rx"; - clocks = <&clock 308>, <&clock 158>; + clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; @@ -502,7 +523,7 @@ usb@12000000 { compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock 286>; + clocks = <&clock CLK_USB3>; clock-names = "usbdrd30"; #address-cells = <1>; #size-cells = <1>; @@ -519,7 +540,7 @@ usb3_phy: usbphy@12100000 { compatible = "samsung,exynos5250-usb3phy"; reg = <0x12100000 0x100>; - clocks = <&clock 1>, <&clock 286>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; clock-names = "ext_xtal", "usbdrd30"; #address-cells = <1>; #size-cells = <1>; @@ -535,7 +556,7 @@ reg = <0x12110000 0x100>; interrupts = <0 71 0>; - clocks = <&clock 285>; + clocks = <&clock CLK_USB2>; clock-names = "usbhost"; }; @@ -544,14 +565,14 @@ reg = <0x12120000 0x100>; interrupts = <0 71 0>; - clocks = <&clock 285>; + clocks = <&clock CLK_USB2>; clock-names = "usbhost"; }; usb2_phy: usbphy@12130000 { compatible = "samsung,exynos5250-usb2phy"; reg = <0x12130000 0x100>; - clocks = <&clock 1>, <&clock 285>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; clock-names = "ext_xtal", "usbhost"; #address-cells = <1>; #size-cells = <1>; @@ -568,7 +589,7 @@ reg = <0x12dd0000 0x100>; samsung,pwm-outputs = <0>, <1>, <2>, <3>; #pwm-cells = <3>; - clocks = <&clock 311>; + clocks = <&clock CLK_PWM>; clock-names = "timers"; }; @@ -583,7 +604,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <0 34 0>; - clocks = <&clock 275>; + clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -594,7 +615,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <0 35 0>; - clocks = <&clock 276>; + clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -605,7 +626,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = <0 33 0>; - clocks = <&clock 346>; + clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -616,7 +637,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <0 124 0>; - clocks = <&clock 271>; + clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -629,7 +650,7 @@ reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; samsung,power-domain = <&pd_gsc>; - clocks = <&clock 256>; + clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; }; @@ -638,7 +659,7 @@ reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; samsung,power-domain = <&pd_gsc>; - clocks = <&clock 257>; + clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; }; @@ -647,7 +668,7 @@ reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; samsung,power-domain = <&pd_gsc>; - clocks = <&clock 258>; + clocks = <&clock CLK_GSCL2>; clock-names = "gscl"; }; @@ -656,7 +677,7 @@ reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; samsung,power-domain = <&pd_gsc>; - clocks = <&clock 259>; + clocks = <&clock CLK_GSCL3>; clock-names = "gscl"; }; @@ -664,8 +685,9 @@ compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; - clocks = <&clock 344>, <&clock 136>, <&clock 137>, - <&clock 159>, <&clock 1024>; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; }; @@ -674,7 +696,7 @@ compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; - clocks = <&clock 343>, <&clock 136>; + clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "sclk_hdmi"; }; @@ -685,14 +707,14 @@ }; dp-controller@145B0000 { - clocks = <&clock 342>; + clocks = <&clock CLK_DP>; clock-names = "dp"; phys = <&dp_phy>; phy-names = "dp"; }; fimd@14400000 { - clocks = <&clock 133>, <&clock 339>; + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; }; @@ -700,10 +722,18 @@ compatible = "samsung,exynos-adc-v1"; reg = <0x12D10000 0x100>, <0x10040718 0x4>; interrupts = <0 106 0>; - clocks = <&clock 303>; + clocks = <&clock CLK_ADC>; clock-names = "adc"; #io-channel-cells = <1>; io-channel-ranges; status = "disabled"; }; + + sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x10000>; + interrupts = <0 112 0>; + clocks = <&clock 348>; + clock-names = "secss"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5250-smdk5250.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250-smdk5250.dts --- linux-3.14.1/arch/arm/boot/dts/exynos5250-smdk5250.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250-smdk5250.dts 2014-04-13 23:18:35.000000000 +0200 @@ -14,7 +14,7 @@ / { model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; - compatible = "samsung,smdk5250", "samsung,exynos5250"; + compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; aliases { }; @@ -27,6 +27,10 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + rtc@101E0000 { + status = "okay"; + }; + i2c@12C60000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; @@ -36,6 +40,148 @@ compatible = "samsung,s524ad0xd1"; reg = <0x50>; }; + + max77686@09 { + compatible = "maxim,max77686"; + reg = <0x09>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "P1.0V_LDO_OUT1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "P1.2V_LDO_OUT2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "P1.8V_LDO_OUT3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "P2.8V_LDO_OUT4"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "P1.8V_LDO_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "P1.1V_LDO_OUT6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; }; vdd: fixed-regulator@0 { @@ -96,16 +242,12 @@ samsung,i2c-slave-addr = <0x38>; status = "okay"; - sata-phy { - compatible = "samsung,sata-phy"; + sata_phy_i2c:sata-phy@38 { + compatible = "samsung,exynos-sataphy-i2c"; reg = <0x38>; }; }; - sata@122F0000 { - samsung,sata-freq = <66>; - }; - i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; @@ -128,6 +270,15 @@ }; }; + sata@122F0000 { + status = "okay"; + }; + + sata-phy@12170000 { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; + }; + mmc@12200000 { status = "okay"; num-slots = <1>; @@ -164,10 +315,6 @@ }; }; - spi_0: spi@12d20000 { - status = "disabled"; - }; - spi_1: spi@12d30000 { status = "okay"; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5250-snow.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250-snow.dts --- linux-3.14.1/arch/arm/boot/dts/exynos5250-snow.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5250-snow.dts 2014-04-13 23:18:35.000000000 +0200 @@ -14,12 +14,16 @@ / { model = "Google Snow"; - compatible = "google,snow", "samsung,exynos5250"; + compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5"; aliases { i2c104 = &i2c_104; }; + rtc@101E0000 { + status = "okay"; + }; + pinctrl@11400000 { sd3_clk: sd3-clk { samsung,pin-drv = <0>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5420-arndale-octa.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5420-arndale-octa.dts --- linux-3.14.1/arch/arm/boot/dts/exynos5420-arndale-octa.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5420-arndale-octa.dts 2014-04-13 23:18:35.000000000 +0200 @@ -11,10 +11,12 @@ /dts-v1/; #include "exynos5420.dtsi" +#include +#include / { model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; - compatible = "insignal,arndale-octa", "samsung,exynos5420"; + compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; memory { reg = <0x20000000 0x80000000>; @@ -31,6 +33,10 @@ }; }; + rtc@101E0000 { + status = "okay"; + }; + mmc@12200000 { status = "okay"; broken-cd; @@ -41,6 +47,7 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + vmmc-supply = <&ldo10_reg>; slot@0 { reg = <0>; @@ -57,10 +64,316 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + vmmc-supply = <&ldo10_reg>; slot@0 { reg = <0>; bus-width = <4>; }; }; + + hsi2c_4: i2c@12CA0000 { + status = "okay"; + + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + s2mps11,buck2-ramp-delay = <12>; + s2mps11,buck34-ramp-delay = <12>; + s2mps11,buck16-ramp-delay = <12>; + s2mps11,buck6-ramp-enable = <1>; + s2mps11,buck2-ramp-enable = <1>; + s2mps11,buck3-ramp-enable = <1>; + s2mps11,buck4-ramp-enable = <1>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + + s2mps11_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "PVDD_ALIVE_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "PVDD_APIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "PVDD_APIO_MMCON_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "PVDD_ADC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "PVDD_PLL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "PVDD_ANAIP_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "PVDD_ANAIP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "PVDD_ABB_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "PVDD_USB_3V3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "PVDD_PRE_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "PVDD_USB_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "PVDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "PVDD_APIO_MMCOFF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "PVDD_PERI_2V8"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "PVDD_PERI_3V3"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "PVDD_EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "PVDD_TFLASH_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "PVDD_BTWIFI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "PVDD_CAM1IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "PVDD_MIFS_1V1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "PVDD_CAM1_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "PVDD_CAM0_AF_2V8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "PVDD_G3DS_1V0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "PVDD_TSP_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "PVDD_AUDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo31_reg: LDO31 { + regulator-name = "PVDD_PERI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo32_reg: LDO32 { + regulator-name = "PVDD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "PVDD_CAM0IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "PVDD_CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "PVDD_CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "PVDD_MIF_1V1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "PVDD_INT_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "PVDD_G3D_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "PVDD_LPDDR3_1V2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "PVDD_KFC_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO_1V4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO_2V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO_3V5"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "PVDD_EMMCF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + wakeup { + label = "SW-TACT1"; + gpios = <&gpx2 7 1>; + linux,code = ; + gpio-key,wakeup; + }; + }; + + amba { + mdma1: mdma@11C10000 { + /* + * MDMA1 can support both secure and non-secure + * AXI transactions. When this is enabled in the kernel + * for boards that run in secure mode, we are getting + * imprecise external aborts causing the kernel to oops. + */ + status = "disabled"; + }; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5420.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5420.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos5420.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5420.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -13,13 +13,14 @@ * published by the Free Software Foundation. */ +#include #include "exynos5.dtsi" #include "exynos5420-pinctrl.dtsi" -#include +#include / { - compatible = "samsung,exynos5420"; + compatible = "samsung,exynos5420", "samsung,exynos5"; aliases { mshc0 = &mmc_0; @@ -119,7 +120,8 @@ compatible = "samsung,exynos5420-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; @@ -127,7 +129,7 @@ compatible = "samsung,mfc-v7"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; - clocks = <&clock 401>; + clocks = <&clock CLK_MFC>; clock-names = "mfc"; }; @@ -137,7 +139,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x2000>; - clocks = <&clock 351>, <&clock 132>; + clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; status = "disabled"; @@ -149,7 +151,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x2000>; - clocks = <&clock 352>, <&clock 133>; + clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; status = "disabled"; @@ -161,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; - clocks = <&clock 353>, <&clock 134>; + clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; status = "disabled"; @@ -175,7 +177,7 @@ interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; - clocks = <&clock 1>, <&clock 315>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map { @@ -269,9 +271,9 @@ }; rtc@101E0000 { - clocks = <&clock 317>; + clocks = <&clock CLK_RTC>; clock-names = "rtc"; - status = "okay"; + status = "disabled"; }; amba { @@ -281,11 +283,22 @@ interrupt-parent = <&gic>; ranges; + adma: adma@03880000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x03880000 0x1000>; + interrupts = <0 110 0>; + clocks = <&clock_audss EXYNOS_ADMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <6>; + #dma-requests = <16>; + }; + pdma0: pdma@121A0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <0 34 0>; - clocks = <&clock 362>; + clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -296,7 +309,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <0 35 0>; - clocks = <&clock 363>; + clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -307,7 +320,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = <0 33 0>; - clocks = <&clock 473>; + clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -318,7 +331,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <0 124 0>; - clocks = <&clock 442>; + clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -326,6 +339,49 @@ }; }; + i2s0: i2s@03830000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x03830000 0x100>; + dmas = <&adma 0 + &adma 2 + &adma 1>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; + }; + + i2s1: i2s@12D60000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12D60000 0x100>; + dmas = <&pdma1 12 + &pdma1 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; + clock-names = "iis", "i2s_opclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; + + i2s2: i2s@12D70000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12D70000 0x100>; + dmas = <&pdma0 12 + &pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; + clock-names = "iis", "i2s_opclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + status = "disabled"; + }; + spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; @@ -337,7 +393,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; - clocks = <&clock 271>, <&clock 135>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; clock-names = "spi", "spi_busclk0"; status = "disabled"; }; @@ -353,7 +409,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; - clocks = <&clock 272>, <&clock 136>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; clock-names = "spi", "spi_busclk0"; status = "disabled"; }; @@ -369,28 +425,28 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; - clocks = <&clock 273>, <&clock 137>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; clock-names = "spi", "spi_busclk0"; status = "disabled"; }; serial@12C00000 { - clocks = <&clock 257>, <&clock 128>; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C10000 { - clocks = <&clock 258>, <&clock 129>; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C20000 { - clocks = <&clock 259>, <&clock 130>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C30000 { - clocks = <&clock 260>, <&clock 131>; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; }; @@ -399,7 +455,7 @@ reg = <0x12dd0000 0x100>; samsung,pwm-outputs = <0>, <1>, <2>, <3>; #pwm-cells = <3>; - clocks = <&clock 279>; + clocks = <&clock CLK_PWM>; clock-names = "timers"; }; @@ -410,7 +466,7 @@ }; dp-controller@145B0000 { - clocks = <&clock 412>; + clocks = <&clock CLK_DP1>; clock-names = "dp"; phys = <&dp_phy>; phy-names = "dp"; @@ -418,7 +474,7 @@ fimd@14400000 { samsung,power-domain = <&disp_pd>; - clocks = <&clock 147>, <&clock 421>; + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; }; @@ -426,7 +482,7 @@ compatible = "samsung,exynos-adc-v2"; reg = <0x12D10000 0x100>, <0x10040720 0x4>; interrupts = <0 106 0>; - clocks = <&clock 270>; + clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; io-channel-ranges; @@ -439,7 +495,7 @@ interrupts = <0 56 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 261>; + clocks = <&clock CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; @@ -452,7 +508,7 @@ interrupts = <0 57 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 262>; + clocks = <&clock CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; @@ -465,7 +521,7 @@ interrupts = <0 58 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 263>; + clocks = <&clock CLK_I2C2>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; @@ -478,7 +534,7 @@ interrupts = <0 59 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 264>; + clocks = <&clock CLK_I2C3>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; @@ -493,7 +549,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock 265>; + clocks = <&clock CLK_I2C4>; clock-names = "hsi2c"; status = "disabled"; }; @@ -506,7 +562,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock 266>; + clocks = <&clock CLK_I2C5>; clock-names = "hsi2c"; status = "disabled"; }; @@ -519,7 +575,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock 267>; + clocks = <&clock CLK_I2C6>; clock-names = "hsi2c"; status = "disabled"; }; @@ -532,7 +588,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock 268>; + clocks = <&clock CLK_I2C7>; clock-names = "hsi2c"; status = "disabled"; }; @@ -545,7 +601,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock 281>; + clocks = <&clock CLK_I2C8>; clock-names = "hsi2c"; status = "disabled"; }; @@ -558,7 +614,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock 282>; + clocks = <&clock CLK_I2C9>; clock-names = "hsi2c"; status = "disabled"; }; @@ -571,7 +627,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock 283>; + clocks = <&clock CLK_I2C10>; clock-names = "hsi2c"; status = "disabled"; }; @@ -580,8 +636,9 @@ compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; - clocks = <&clock 413>, <&clock 143>, <&clock 768>, - <&clock 158>, <&clock 640>; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; status = "disabled"; @@ -591,7 +648,7 @@ compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; - clocks = <&clock 431>, <&clock 143>; + clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "sclk_hdmi"; }; @@ -599,7 +656,7 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; - clocks = <&clock 465>; + clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; samsung,power-domain = <&gsc_pd>; }; @@ -608,16 +665,21 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; - clocks = <&clock 466>; + clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; samsung,power-domain = <&gsc_pd>; }; + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5420-pmu", "syscon"; + reg = <0x10040000 0x5000>; + }; + tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; interrupts = <0 65 0>; - clocks = <&clock 318>; + clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; }; @@ -625,7 +687,7 @@ compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; interrupts = <0 183 0>; - clocks = <&clock 318>; + clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; }; @@ -633,7 +695,7 @@ compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x10068000 0x100>, <0x1006c000 0x4>; interrupts = <0 184 0>; - clocks = <&clock 318>, <&clock 318>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; }; @@ -641,7 +703,7 @@ compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x1006c000 0x100>, <0x100a0000 0x4>; interrupts = <0 185 0>; - clocks = <&clock 318>, <&clock 319>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; }; @@ -649,7 +711,25 @@ compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x100a0000 0x100>, <0x10068000 0x4>; interrupts = <0 215 0>; - clocks = <&clock 319>, <&clock 318>; + clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; }; + + watchdog@101D0000 { + compatible = "samsung,exynos5420-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x10000>; + interrupts = <0 112 0>; + clocks = <&clock 471>; + clock-names = "secss"; + samsung,power-domain = <&g2d_pd>; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5420-smdk5420.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5420-smdk5420.dts --- linux-3.14.1/arch/arm/boot/dts/exynos5420-smdk5420.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5420-smdk5420.dts 2014-04-13 23:18:35.000000000 +0200 @@ -14,7 +14,7 @@ / { model = "Samsung SMDK5420 board based on EXYNOS5420"; - compatible = "samsung,smdk5420", "samsung,exynos5420"; + compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; memory { reg = <0x20000000 0x80000000>; @@ -31,6 +31,43 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd: fixed-regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + dbvdd: fixed-regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "dbvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + spkvdd: fixed-regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "spkvdd-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + + rtc@101E0000 { + status = "okay"; + }; + mmc@12200000 { status = "okay"; broken-cd; @@ -120,4 +157,220 @@ reg = <0x50>; }; }; + + hsi2c_4: i2c@12CA0000 { + status = "okay"; + + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + s2mps11,buck2-ramp-delay = <12>; + s2mps11,buck34-ramp-delay = <12>; + s2mps11,buck16-ramp-delay = <12>; + s2mps11,buck6-ramp-enable = <1>; + s2mps11,buck2-ramp-enable = <1>; + s2mps11,buck3-ramp-enable = <1>; + s2mps11,buck4-ramp-enable = <1>; + + s2mps11_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "tsp_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.0v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_1.8v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5440.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5440.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos5440.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5440.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -9,10 +9,11 @@ * published by the Free Software Foundation. */ +#include #include "skeleton.dtsi" / { - compatible = "samsung,exynos5440"; + compatible = "samsung,exynos5440", "samsung,exynos5"; interrupt-parent = <&gic>; @@ -105,7 +106,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>; interrupts = <0 2 0>; - clocks = <&clock 21>, <&clock 21>; + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; }; @@ -113,7 +114,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0xC0000 0x1000>; interrupts = <0 3 0>; - clocks = <&clock 21>, <&clock 21>; + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; }; @@ -125,7 +126,7 @@ #size-cells = <0>; samsung,spi-src-clk = <0>; num-cs = <1>; - clocks = <&clock 21>, <&clock 16>; + clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; clock-names = "spi", "spi_busclk0"; }; @@ -161,7 +162,7 @@ interrupts = <0 5 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "i2c"; }; @@ -171,7 +172,7 @@ interrupts = <0 6 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "i2c"; }; @@ -179,7 +180,7 @@ compatible = "samsung,s3c2410-wdt"; reg = <0x110000 0x1000>; interrupts = <0 1 0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "watchdog"; }; @@ -190,7 +191,7 @@ interrupts = <0 31 4>; interrupt-names = "macirq"; phy-mode = "sgmii"; - clocks = <&clock 25>; + clocks = <&clock CLK_GMAC0>; clock-names = "stmmaceth"; }; @@ -206,7 +207,7 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x130000 0x1000>; interrupts = <0 17 0>, <0 16 0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "rtc"; }; @@ -214,7 +215,7 @@ compatible = "samsung,exynos5440-tmu"; reg = <0x160118 0x230>, <0x160368 0x10>; interrupts = <0 58 0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; }; @@ -222,7 +223,7 @@ compatible = "samsung,exynos5440-tmu"; reg = <0x16011C 0x230>, <0x160368 0x10>; interrupts = <0 58 0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; }; @@ -230,7 +231,7 @@ compatible = "samsung,exynos5440-tmu"; reg = <0x160120 0x230>, <0x160368 0x10>; interrupts = <0 58 0>; - clocks = <&clock 21>; + clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; }; @@ -238,7 +239,7 @@ compatible = "snps,exynos5440-ahci"; reg = <0x210000 0x10000>; interrupts = <0 30 0>; - clocks = <&clock 23>; + clocks = <&clock CLK_SATA>; clock-names = "sata"; }; @@ -246,7 +247,7 @@ compatible = "samsung,exynos5440-ohci"; reg = <0x220000 0x1000>; interrupts = <0 29 0>; - clocks = <&clock 24>; + clocks = <&clock CLK_USB>; clock-names = "usbhost"; }; @@ -254,7 +255,7 @@ compatible = "samsung,exynos5440-ehci"; reg = <0x221000 0x1000>; interrupts = <0 29 0>; - clocks = <&clock 24>; + clocks = <&clock CLK_USB>; clock-names = "usbhost"; }; @@ -264,7 +265,7 @@ 0x270000 0x1000 0x271000 0x40>; interrupts = <0 20 0>, <0 21 0>, <0 22 0>; - clocks = <&clock 28>, <&clock 27>; + clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; #size-cells = <2>; @@ -285,7 +286,7 @@ 0x272000 0x1000 0x271040 0x40>; interrupts = <0 23 0>, <0 24 0>, <0 25 0>; - clocks = <&clock 29>, <&clock 27>; + clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; #size-cells = <2>; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5440-sd5v1.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5440-sd5v1.dts --- linux-3.14.1/arch/arm/boot/dts/exynos5440-sd5v1.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5440-sd5v1.dts 2014-04-13 23:18:35.000000000 +0200 @@ -14,7 +14,7 @@ / { model = "SAMSUNG SD5v1 board based on EXYNOS5440"; - compatible = "samsung,sd5v1", "samsung,exynos5440"; + compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5"; chosen { bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5440-ssdk5440.dts linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5440-ssdk5440.dts --- linux-3.14.1/arch/arm/boot/dts/exynos5440-ssdk5440.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5440-ssdk5440.dts 2014-04-13 23:18:35.000000000 +0200 @@ -14,7 +14,7 @@ / { model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; - compatible = "samsung,ssdk5440", "samsung,exynos5440"; + compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5"; chosen { bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; diff -Nur linux-3.14.1/arch/arm/boot/dts/exynos5.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5.dtsi --- linux-3.14.1/arch/arm/boot/dts/exynos5.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/exynos5.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -81,13 +81,6 @@ status = "disabled"; }; - watchdog { - compatible = "samsung,s3c2410-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - status = "disabled"; - }; - fimd@14400000 { compatible = "samsung,exynos5250-fimd"; interrupt-parent = <&combiner>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx23.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx23.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx23.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx23.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -23,6 +23,7 @@ serial1 = &auart1; spi0 = &ssp0; spi1 = &ssp1; + usbphy0 = &usbphy0; }; cpus { @@ -428,7 +429,7 @@ status = "disabled"; }; - lradc@80050000 { + lradc: lradc@80050000 { compatible = "fsl,imx23-lradc"; reg = <0x80050000 0x2000>; interrupts = <36 37 38 39 40 41 42 43 44>; @@ -526,4 +527,9 @@ status = "disabled"; }; }; + + iio_hwmon { + compatible = "iio-hwmon"; + io-channels = <&lradc 8>; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx23-evk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx23-evk.dts --- linux-3.14.1/arch/arm/boot/dts/imx23-evk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx23-evk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -127,17 +127,21 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_vddio_sd0: vddio-sd0 { + reg_vddio_sd0: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "vddio-sd0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 29 0>; }; - reg_lcd_3v3: lcd-3v3 { + reg_lcd_3v3: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "lcd-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx23-olinuxino.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx23-olinuxino.dts --- linux-3.14.1/arch/arm/boot/dts/imx23-olinuxino.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx23-olinuxino.dts 2014-04-13 23:18:35.000000000 +0200 @@ -100,9 +100,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb0_vbus: usb0_vbus { + reg_usb0_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx23-stmp378x_devb.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx23-stmp378x_devb.dts --- linux-3.14.1/arch/arm/boot/dts/imx23-stmp378x_devb.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx23-stmp378x_devb.dts 2014-04-13 23:18:35.000000000 +0200 @@ -66,9 +66,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_vddio_sd0: vddio-sd0 { + reg_vddio_sd0: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "vddio-sd0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx25.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx25.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx25.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx25.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,7 @@ */ #include "skeleton.dtsi" +#include "imx25-pinfunc.h" / { aliases { @@ -173,12 +174,12 @@ status = "disabled"; }; - iomuxc@43fac000{ + iomuxc: iomuxc@43fac000 { compatible = "fsl,imx25-iomuxc"; reg = <0x43fac000 0x4000>; }; - audmux@43fb0000 { + audmux: audmux@43fb0000 { compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; reg = <0x43fb0000 0x4000>; status = "disabled"; @@ -236,6 +237,11 @@ compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <11>; + clocks = <&clks 118>; + clock-names = "ipg"; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -266,6 +272,11 @@ compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; reg = <0x50034000 0x4000>; interrupts = <12>; + clocks = <&clks 117>; + clock-names = "ipg"; + dmas = <&sdma 28 1 0>, + <&sdma 29 1 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -436,13 +447,14 @@ #interrupt-cells = <2>; }; - sdma@53fd4000 { + sdma: sdma@53fd4000 { compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; reg = <0x53fd4000 0x4000>; clocks = <&clks 112>, <&clks 68>; clock-names = "ipg", "ahb"; #dma-cells = <3>; interrupts = <34>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; }; wdog@53fdc000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,73 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx25.dtsi" + +/ { + model = "Eukrea CPUIMX25"; + compatible = "eukrea,cpuimx25", "fsl,imx25"; + + memory { + reg = <0x80000000 0x4000000>; /* 64M */ + }; +}; + +&fec { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + imx25-eukrea-cpuimx25 { + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts --- linux-3.14.1/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,174 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include +#include "imx25-eukrea-cpuimx25.dtsi" + +/ { + model = "Eukrea MBIMXSD25"; + compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + bp1 { + label = "BP1"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx25-eukrea-tlv320aic23"; + ssi-controller = <&ssi1>; + fsl,mux-int-port = <1>; + fsl,mux-ext-port = <5>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 20>; + status = "okay"; +}; + +&i2c1 { + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&iomuxc { + imx25-eukrea-mbimxsd25-baseboard { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 + MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 + MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 + MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 + MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 + MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 + MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 + MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 + MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0 + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = ; + }; + + pinctrl_lcdc: lcdcgrp { + fsl,pins = < + MX25_PAD_LD0__LD0 0x1 + MX25_PAD_LD1__LD1 0x1 + MX25_PAD_LD2__LD2 0x1 + MX25_PAD_LD3__LD3 0x1 + MX25_PAD_LD4__LD4 0x1 + MX25_PAD_LD5__LD5 0x1 + MX25_PAD_LD6__LD6 0x1 + MX25_PAD_LD7__LD7 0x1 + MX25_PAD_LD8__LD8 0x1 + MX25_PAD_LD9__LD9 0x1 + MX25_PAD_LD10__LD10 0x1 + MX25_PAD_LD11__LD11 0x1 + MX25_PAD_LD12__LD12 0x1 + MX25_PAD_LD13__LD13 0x1 + MX25_PAD_LD14__LD14 0x1 + MX25_PAD_LD15__LD15 0x1 + MX25_PAD_GPIO_E__LD16 0x1 + MX25_PAD_GPIO_F__LD17 0x1 + MX25_PAD_HSYNC__HSYNC 0x80000000 + MX25_PAD_VSYNC__VSYNC 0x80000000 + MX25_PAD_LSCLK__LSCLK 0x80000000 + MX25_PAD_OE_ACD__OE_ACD 0x80000000 + MX25_PAD_CONTRAST__CONTRAST 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 + MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 + MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 + MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 + >; + }; + }; +}; + +&ssi1 { + codec-handle = <&tlv320aic23>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx25-pinfunc.h linux-3.15-rc1.orig/arch/arm/boot/dts/imx25-pinfunc.h --- linux-3.14.1/arch/arm/boot/dts/imx25-pinfunc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx25-pinfunc.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,494 @@ +/* + * Copyright 2013 Eukréa Electromatique + * Based on imx35-pinfunc.h in the same directory Which is: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX25_PINFUNC_H +#define __DTS_IMX25_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 +#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 + +#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 +#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 + +#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000 +#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000 + +#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000 +#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000 + +#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000 +#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000 + +#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000 +#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000 + +#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000 +#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000 +#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000 + +#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000 +#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000 +#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000 + +#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000 +#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000 +#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000 + +#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000 +#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000 +#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000 + +#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000 +#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000 + +#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000 +#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000 + +#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000 +#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000 +#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000 + +#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000 +#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000 +#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000 + +#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000 +#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000 +#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000 + +#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000 +#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000 +#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000 + +#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000 +#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000 +#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000 + +#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 +#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 + +#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000 +#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 +#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 + +#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000 +#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 +#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000 +#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000 + +#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000 +#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 +#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000 +#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000 + +#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000 +#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000 + +#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000 +#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000 +#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000 + +#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000 +#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000 +#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000 + +#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 +#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 + +#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000 +#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000 +#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000 + +#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000 +#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000 + +#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000 +#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000 + +#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000 +#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000 + +#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000 +#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000 + +#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000 +#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000 + +#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000 +#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000 + +#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 +#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 +#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 + +#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 +#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 +#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 + +#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 +#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 +#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 + +#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 +#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 + +#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 +#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 + +#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 +#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 +#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000 + +#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000 +#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000 +#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000 + +#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000 +#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000 +#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000 + +#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000 +#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000 + +#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000 +#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000 + +#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000 +#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000 + +#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000 +#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000 + +#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000 +#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000 + +#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000 +#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000 + +#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000 +#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000 + +#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 +#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 + +#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000 +#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000 +#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000 + +#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000 +#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000 +#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000 + +#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000 +#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000 + +#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000 +#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000 + +#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000 +#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000 + +#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000 +#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000 + +#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000 +#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000 + +#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000 +#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000 + +#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000 +#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000 + +#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000 +#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001 + +#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000 +#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001 + +#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000 +#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001 + +#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000 +#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001 + +#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000 +#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000 + +#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000 +#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000 + +#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000 +#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001 + +#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000 +#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000 + +#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000 +#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000 + +#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000 +#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000 + +#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000 +#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 + +#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 +#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 +#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 + +#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000 +#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000 +#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001 + +#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000 +#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001 +#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000 +#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 + +#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 +#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 +#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 + +#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000 +#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001 +#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000 +#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 + +#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 +#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 +#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 + +#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 +#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 + +#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 +#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 + +#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 +#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 + +#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 +#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 + +#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 +#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 + +#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 +#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 + +#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 +#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 + +#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 +#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 + +#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 +#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000 + +#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000 +#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 + +#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 + +#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 + +#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 + +#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 + +#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 + +#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000 + +#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000 +#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000 + +#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000 +#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000 + +#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 +#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 +#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 + +#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 +#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001 +#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000 + +#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000 +#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000 + +#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000 +#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000 + +#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 +#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 +#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 + +#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 +#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000 +#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 + +#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 +#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 +#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 + +#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 +#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 +#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 + +#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 +#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 + +#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 +#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000 +#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000 + +#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000 +#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002 +#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000 + +#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000 +#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002 +#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000 + +#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000 +#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000 + +#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000 +#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000 + +#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000 +#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002 +#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000 + +#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000 +#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002 +#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000 + +#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000 +#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001 +#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000 +#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000 + +#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000 +#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000 +#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000 +#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000 + +#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000 +#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000 +#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000 +#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000 + +#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000 +#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000 +#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000 +#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000 + +#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000 +#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001 +#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000 + +#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000 +#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001 +#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000 + +#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000 +#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000 + +#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000 +#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001 +#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000 + +#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000 +#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000 + +#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000 +#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000 + +#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000 +#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000 + +#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000 +#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000 +#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000 + +#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000 +#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000 + +#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000 +#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000 +#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000 + +#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000 +#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000 + +#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 + +#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000 +#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000 +#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000 + +#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000 +#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001 +#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001 + +#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000 +#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 + +#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 +#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 +#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 + +#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 +#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 +#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 + +#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 +#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 + +#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 +#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000 + +#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000 +#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000 + +#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000 +#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000 +#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000 +#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000 +#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000 + +#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000 +#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001 +#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000 + +#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000 +#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000 + +#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 +#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 +#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 +#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 + +#endif /* __DTS_IMX25_PINFUNC_H */ diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-apf27dev.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-apf27dev.dts --- linux-3.14.1/arch/arm/boot/dts/imx27-apf27dev.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-apf27dev.dts 2014-04-13 23:18:35.000000000 +0200 @@ -22,10 +22,10 @@ bits-per-pixel = <16>; /* non-standard but required */ fsl,pcr = <0xfae80083>; /* non-standard but required */ display-timings { - timing0: 640x480 { + timing0: 800x480 { clock-frequency = <33000033>; hactive = <800>; - vactive = <640>; + vactive = <480>; hback-porch = <96>; hfront-porch = <96>; vback-porch = <20>; @@ -38,20 +38,24 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; user-key { label = "user"; - gpios = <&gpio6 13 0>; + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; linux,code = <276>; /* BTN_EXTRA */ }; }; leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; user { label = "Heartbeat"; - gpios = <&gpio6 14 0>; + gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -59,25 +63,34 @@ &cspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 28 1>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; status = "okay"; }; &cspi2 { fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>, - <&gpio2 17 1>; + cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio2 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; status = "okay"; }; &fb { display = <&display>; fsl,dmacr = <0x00020010>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb1>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; rtc@68 { @@ -87,5 +100,127 @@ }; &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; }; + +&iomuxc { + imx27-apf27dev { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + >; + }; + + pinctrl_cspi1_cs: cspi1csgrp { + fsl,pins = ; + }; + + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + >; + }; + + pinctrl_cspi2_cs: cspi2csgrp { + fsl,pins = < + MX27_PAD_CSI_D5__GPIO2_17 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = ; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = ; + }; + + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_pwm: pwmgrp { + fsl,pins = < + MX27_PAD_PWMO__PWMO 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + >; + }; + + pinctrl_sdhc2_cd: sdhc2cdgrp { + fsl,pins = ; + }; + }; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-apf27.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-apf27.dts --- linux-3.14.1/arch/arm/boot/dts/imx27-apf27.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-apf27.dts 2014-04-13 23:18:35.000000000 +0200 @@ -34,11 +34,49 @@ }; }; +&iomuxc { + imx27-apf27 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + >; + }; + }; +}; + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx27.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx27.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,9 @@ */ #include "skeleton.dtsi" +#include "imx27-pinfunc.h" +#include +#include / { aliases { @@ -67,6 +70,26 @@ }; }; + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks 75>; + clock-names = "main_clk"; + }; + + usbphy2: usbphy@2 { + compatible = "usb-nop-xceiv"; + reg = <2>; + clocks = <&clks 75>; + clock-names = "main_clk"; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -204,6 +227,30 @@ status = "disabled"; }; + ssi1: ssi@10010000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; + reg = <0x10010000 0x1000>; + interrupts = <14>; + clocks = <&clks 26>; + dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; + dma-names = "rx0", "tx0", "rx1", "tx1"; + fsl,fifo-depth = <8>; + status = "disabled"; + }; + + ssi2: ssi@10011000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; + reg = <0x10011000 0x1000>; + interrupts = <13>; + clocks = <&clks 25>; + dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; + dma-names = "rx0", "tx0", "rx1", "tx1"; + fsl,fifo-depth = <8>; + status = "disabled"; + }; + i2c1: i2c@10012000 { #address-cells = <1>; #size-cells = <0>; @@ -236,64 +283,72 @@ status = "disabled"; }; - gpio1: gpio@10015000 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015000 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@10015100 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015100 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@10015200 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015200 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@10015300 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015300 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@10015400 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015400 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@10015500 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015500 0x100>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + iomuxc: iomuxc@10015000 { + compatible = "fsl,imx27-iomuxc"; + reg = <0x10015000 0x600>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@10015000 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015000 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@10015100 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015100 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@10015200 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015200 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@10015300 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015300 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@10015400 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015400 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@10015500 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015500 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; audmux: audmux@10016000 { @@ -404,6 +459,42 @@ iram = <&iram>; }; + usbotg: usb@10024000 { + compatible = "fsl,imx27-usb"; + reg = <0x10024000 0x200>; + interrupts = <56>; + clocks = <&clks 15>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usbh1: usb@10024200 { + compatible = "fsl,imx27-usb"; + reg = <0x10024200 0x200>; + interrupts = <54>; + clocks = <&clks 15>; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbh2: usb@10024400 { + compatible = "fsl,imx27-usb"; + reg = <0x10024400 0x200>; + interrupts = <55>; + clocks = <&clks 15>; + fsl,usbmisc = <&usbmisc 2>; + fsl,usbphy = <&usbphy2>; + status = "disabled"; + }; + + usbmisc: usbmisc@10024600 { + #index-cells = <1>; + compatible = "fsl,imx27-usbmisc"; + reg = <0x10024600 0x200>; + clocks = <&clks 62>; + }; + sahara2: sahara@10025000 { compatible = "fsl,imx27-sahara"; reg = <0x10025000 0x1000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts --- linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "imx27-phytec-phycard-s-som.dts" +#include "imx27-phytec-phycard-s-som.dtsi" / { model = "Phytec pca100 rapid development kit"; @@ -37,9 +37,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3v3: 3v3 { + reg_3v3: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -54,6 +57,8 @@ }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; rtc@51 { @@ -68,26 +73,92 @@ }; }; +&iomuxc { + imx27-phycard-s-rdk { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_owire1: owire1grp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX27_PAD_UART3_TXD__UART3_TXD 0x0 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 + >; + }; + }; +}; + &owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire1>; status = "okay"; }; &sdhci2 { - cd-gpios = <&gpio3 29 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2>; + cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; status = "okay"; }; &uart1 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &uart3 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts --- linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts 1970-01-01 01:00:00.000000000 +0100 @@ -1,44 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar - * and Markus Pargmann, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pca100"; - compatible = "phytec,imx27-pca100", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x08000000>; /* 128MB */ - }; -}; - -&cspi1 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 0>, - <&gpio4 27 0>; - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,103 @@ +/* + * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar + * and Markus Pargmann, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Phytec pca100"; + compatible = "phytec,imx27-pca100", "fsl,imx27"; + + memory { + reg = <0xa0000000 0x08000000>; /* 128MB */ + }; +}; + +&cspi1 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, + <&gpio4 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + at24@52 { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +&iomuxc { + imx27-phycard-s-som { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts --- linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -7,7 +7,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "imx27-phytec-phycore-som.dts" +#include "imx27-phytec-phycore-som.dtsi" / { model = "Phytec pcm970"; @@ -16,32 +16,200 @@ &cspi1 { fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, + <&gpio4 27 GPIO_ACTIVE_LOW>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + camgpio: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + imx27_phycore_rdk { + pinctrl_i2c1: i2c1grp { + /* Add pullup to DATA line */ + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x1 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_owire1: owire1grp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ + MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ + MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ + >; + }; + }; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire1>; + status = "okay"; +}; + +&pmicleds { + ledr1: led@3 { + reg = <3>; + label = "system:red1:user"; + }; + + ledg1: led@4 { + reg = <4>; + label = "system:green1:user"; + }; + + ledb1: led@5 { + reg = <5>; + label = "system:blue1:user"; + }; + + ledr2: led@6 { + reg = <6>; + label = "system:red2:user"; + }; + + ledg2: led@7 { + reg = <7>; + label = "system:green2:user"; + }; + + ledb2: led@8 { + reg = <8>; + label = "system:blue2:user"; + }; + + ledr3: led@9 { + reg = <9>; + label = "system:red3:nand"; + linux,default-trigger = "nand-disk"; + }; + + ledg3: led@10 { + reg = <10>; + label = "system:green3:live"; + linux,default-trigger = "heartbeat"; + }; + + ledb3: led@11 { + reg = <11>; + label = "system:blue3:cpu"; + linux,default-trigger = "cpu0"; + }; }; &sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2>; bus-width = <4>; - cd-gpios = <&gpio3 29 0>; - wp-gpios = <&gpio3 28 0>; + cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; vmmc-supply = <&vmmc1_reg>; status = "okay"; }; &uart1 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; }; &uart2 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + dr_mode = "host"; + phy_type = "ulpi"; + vbus-supply = <®_5v0>; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + vcc-supply = <®_5v0>; +}; + &weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + can@d4000000 { compatible = "nxp,sja1000"; reg = <4 0x00000000 0x00000100>; interrupt-parent = <&gpio5>; - interrupts = <19 0x2>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; nxp,external-clock-frequency = <16000000>; nxp,tx-output-config = <0x16>; nxp,no-comparator-bypass; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycore-som.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycore-som.dts --- linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycore-som.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycore-som.dts 1970-01-01 01:00:00.000000000 +0100 @@ -1,194 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pcm038"; - compatible = "phytec,imx27-pcm038", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x08000000>; - }; -}; - -&audmux { - status = "okay"; - - /* SSI0 <=> PINS_4 (MC13783 Audio) */ - ssi0 { - fsl,audmux-port = <0>; - fsl,port-config = <0xcb205000>; - }; - - pins4 { - fsl,audmux-port = <2>; - fsl,port-config = <0x00001000>; - }; -}; - -&cspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 28 0>; - status = "okay"; - - pmic: mc13783@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mc13783"; - spi-max-frequency = <20000000>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <23 0x4>; - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - regulators { - /* SW1A and SW1B joined operation */ - sw1_reg: sw1a { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1520000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SW2A and SW2B joined operation */ - sw2_reg: sw2a { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vaudio_reg: vaudio { - regulator-always-on; - regulator-boot-on; - }; - - violo_reg: violo { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - viohi_reg: viohi { - regulator-always-on; - regulator-boot-on; - }; - - vgen_reg: vgen { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vrf1_reg: vrf1 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vrf2_reg: vrf2 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc1_reg: vmmc1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - }; - - gpo1_reg: gpo1 { }; - - pwgt1spi_reg: pwgt1spi { - regulator-always-on; - }; - }; - }; -}; - -&fec { - phy-reset-gpios = <&gpio3 30 0>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - lm75@4a { - compatible = "national,lm75"; - reg = <0x4a>; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&weim { - status = "okay"; - - nor: nor@c0000000 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; - #address-cells = <1>; - #size-cells = <1>; - }; - - sram: sram@c8000000 { - compatible = "mtd-ram"; - reg = <1 0x00000000 0x00800000>; - bank-width = <2>; - linux,mtd-name = "mtd-ram.0"; - fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,317 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Phytec pcm038"; + compatible = "phytec,imx27-pcm038", "fsl,imx27"; + + memory { + reg = <0xa0000000 0x08000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; +}; + +&audmux { + status = "okay"; + + /* SSI0 <=> PINS_4 (MC13783 Audio) */ + ssi0 { + fsl,audmux-port = <0>; + fsl,port-config = <0xcb205000>; + }; + + pins4 { + fsl,audmux-port = <2>; + fsl,port-config = <0x00001000>; + }; +}; + +&cspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13783@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio2>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + pmicleds: leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; + }; + + regulators { + /* SW1A and SW1B joined operation */ + sw1_reg: sw1a { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1520000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SW2A and SW2B joined operation */ + sw2_reg: sw2a { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio_reg: vaudio { + regulator-always-on; + regulator-boot-on; + }; + + violo_reg: violo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi_reg: viohi { + regulator-always-on; + regulator-boot-on; + }; + + vgen_reg: vgen { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vrf1_reg: vrf1 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vrf2_reg: vrf2 { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc1_reg: vmmc1 { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + }; + + gpo1_reg: gpo1 { }; + + pwgt1spi_reg: pwgt1spi { + regulator-always-on; + }; + }; + }; +}; + +&fec { + phy-mode = "mii"; + phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; + phy-supply = <®_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + at24@52 { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + lm75@4a { + compatible = "national,lm75"; + reg = <0x4a>; + }; +}; + +&iomuxc { + imx27_phycore_som { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + phy_type = "ulpi"; + vbus-supply = <&sw3_reg>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&sw3_reg>; +}; + +&weim { + status = "okay"; + + nor: nor@c0000000 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; + #address-cells = <1>; + #size-cells = <1>; + }; + + sram: sram@c8000000 { + compatible = "mtd-ram"; + reg = <1 0x00000000 0x00800000>; + bank-width = <2>; + linux,mtd-name = "mtd-ram.0"; + fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx27-pinfunc.h linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-pinfunc.h --- linux-3.14.1/arch/arm/boot/dts/imx27-pinfunc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx27-pinfunc.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,526 @@ +/* + * Copyright 2013 Markus Pargmann , Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DTS_IMX27_PINFUNC_H +#define __DTS_IMX27_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + * mux_id consists of + * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) + * + * function: 0 - Primary function + * 1 - Alternate function + * 2 - GPIO + * direction: 0 - Input + * 1 - Output + * gpio_oconf: 0 - A_IN + * 1 - B_IN + * 2 - C_IN + * 3 - Data Register + * gpio_iconfa/b: 0 - GPIO_IN + * 1 - Interrupt Status Register + * 2 - 0 + * 3 - 1 + * + * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin + * number on the specific port (between 0 and 31). + */ + +#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 +#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032 +#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000 +#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032 +#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004 +#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032 +#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000 +#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032 +#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004 +#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032 +#define MX27_PAD_LSCLK__LSCLK 0x05 0x004 +#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032 +#define MX27_PAD_LD0__LD0 0x06 0x004 +#define MX27_PAD_LD0__GPIO1_6 0x06 0x032 +#define MX27_PAD_LD1__LD1 0x07 0x004 +#define MX27_PAD_LD1__GPIO1_7 0x07 0x032 +#define MX27_PAD_LD2__LD2 0x08 0x004 +#define MX27_PAD_LD2__GPIO1_8 0x08 0x032 +#define MX27_PAD_LD3__LD3 0x09 0x004 +#define MX27_PAD_LD3__GPIO1_9 0x09 0x032 +#define MX27_PAD_LD4__LD4 0x0a 0x004 +#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032 +#define MX27_PAD_LD5__LD5 0x0b 0x004 +#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032 +#define MX27_PAD_LD6__LD6 0x0c 0x004 +#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032 +#define MX27_PAD_LD7__LD7 0x0d 0x004 +#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032 +#define MX27_PAD_LD8__LD8 0x0e 0x004 +#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032 +#define MX27_PAD_LD9__LD9 0x0f 0x004 +#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032 +#define MX27_PAD_LD10__LD10 0x10 0x004 +#define MX27_PAD_LD10__GPIO1_16 0x10 0x032 +#define MX27_PAD_LD11__LD11 0x11 0x004 +#define MX27_PAD_LD11__GPIO1_17 0x11 0x032 +#define MX27_PAD_LD12__LD12 0x12 0x004 +#define MX27_PAD_LD12__GPIO1_18 0x12 0x032 +#define MX27_PAD_LD13__LD13 0x13 0x004 +#define MX27_PAD_LD13__GPIO1_19 0x13 0x032 +#define MX27_PAD_LD14__LD14 0x14 0x004 +#define MX27_PAD_LD14__GPIO1_20 0x14 0x032 +#define MX27_PAD_LD15__LD15 0x15 0x004 +#define MX27_PAD_LD15__GPIO1_21 0x15 0x032 +#define MX27_PAD_LD16__LD16 0x16 0x004 +#define MX27_PAD_LD16__GPIO1_22 0x16 0x032 +#define MX27_PAD_LD17__LD17 0x17 0x004 +#define MX27_PAD_LD17__GPIO1_23 0x17 0x032 +#define MX27_PAD_REV__REV 0x18 0x004 +#define MX27_PAD_REV__GPIO1_24 0x18 0x032 +#define MX27_PAD_CLS__CLS 0x19 0x004 +#define MX27_PAD_CLS__GPIO1_25 0x19 0x032 +#define MX27_PAD_PS__PS 0x1a 0x004 +#define MX27_PAD_PS__GPIO1_26 0x1a 0x032 +#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004 +#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032 +#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004 +#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032 +#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004 +#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032 +#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004 +#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 +#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 +#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 +#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004 +#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x032 +#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004 +#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x032 +#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004 +#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x032 +#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004 +#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x032 +#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 +#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 +#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 +#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004 +#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005 +#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032 +#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004 +#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005 +#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032 +#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004 +#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005 +#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032 +#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004 +#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005 +#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032 +#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004 +#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005 +#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032 +#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000 +#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005 +#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032 +#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000 +#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001 +#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032 +#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000 +#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005 +#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032 +#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000 +#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001 +#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032 +#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000 +#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032 +#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004 +#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032 +#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000 +#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032 +#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000 +#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032 +#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000 +#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005 +#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032 +#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000 +#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001 +#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032 +#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000 +#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005 +#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032 +#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000 +#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001 +#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032 +#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004 +#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032 +#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004 +#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032 +#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000 +#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032 +#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004 +#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032 +#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004 +#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001 +#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032 +#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004 +#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032 +#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004 +#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005 +#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032 +#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004 +#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005 +#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032 +#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004 +#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032 +#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 +#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 +#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 +#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004 +#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x032 +#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004 +#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x032 +#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004 +#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x032 +#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004 +#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x032 +#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004 +#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x032 +#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 +#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 +#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 +#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032 +#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004 +#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032 +#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004 +#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032 +#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004 +#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032 +#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004 +#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032 +#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004 +#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032 +#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004 +#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032 +#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004 +#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032 +#define MX27_PAD_TOUT__TOUT 0x4e 0x004 +#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032 +#define MX27_PAD_TIN__TIN 0x4f 0x000 +#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032 +#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004 +#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032 +#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004 +#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032 +#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004 +#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032 +#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004 +#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032 +#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004 +#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032 +#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004 +#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032 +#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004 +#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032 +#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004 +#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032 +#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004 +#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005 +#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032 +#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004 +#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001 +#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032 +#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004 +#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005 +#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032 +#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004 +#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001 +#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032 +#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004 +#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001 +#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032 +#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004 +#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001 +#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032 +#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004 +#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001 +#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032 +#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004 +#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001 +#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032 +#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004 +#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006 +#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032 +#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004 +#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005 +#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006 +#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032 +#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004 +#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005 +#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006 +#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032 +#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004 +#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005 +#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006 +#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032 +#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004 +#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005 +#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002 +#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032 +#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004 +#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005 +#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002 +#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032 +#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004 +#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005 +#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002 +#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032 +#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004 +#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005 +#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002 +#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032 +#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004 +#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005 +#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032 +#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004 +#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005 +#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006 +#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032 +#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004 +#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005 +#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002 +#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032 +#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004 +#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005 +#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002 +#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032 +#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004 +#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005 +#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002 +#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032 +#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004 +#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005 +#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002 +#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032 +#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004 +#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005 +#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002 +#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032 +#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004 +#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005 +#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002 +#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032 +#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004 +#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005 +#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006 +#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032 +#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004 +#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032 +#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004 +#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032 +#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004 +#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005 +#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032 +#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004 +#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005 +#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032 +#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004 +#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005 +#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032 +#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004 +#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005 +#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032 +#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004 +#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005 +#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032 +#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004 +#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005 +#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032 +#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000 +#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032 +#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004 +#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005 +#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032 +#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004 +#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032 +#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004 +#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032 +#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004 +#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032 +#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004 +#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032 +#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004 +#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032 +#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000 +#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005 +#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032 +#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004 +#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005 +#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032 +#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000 +#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005 +#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032 +#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004 +#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005 +#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032 +#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000 +#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005 +#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032 +#define MX27_PAD_PWMO__PWMO 0x85 0x004 +#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032 +#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004 +#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005 +#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032 +#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000 +#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005 +#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032 +#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004 +#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032 +#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000 +#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032 +#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004 +#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032 +#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000 +#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032 +#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004 +#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032 +#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000 +#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032 +#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004 +#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032 +#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000 +#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032 +#define MX27_PAD_RTCK__RTCK 0x90 0x004 +#define MX27_PAD_RTCK__OWIRE 0x90 0x005 +#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032 +#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004 +#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032 +#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004 +#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001 +#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032 +#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004 +#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032 +#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004 +#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032 +#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004 +#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005 +#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032 +#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004 +#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005 +#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032 +#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004 +#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005 +#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032 +#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000 +#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 +#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 +#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 +#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004 +#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x032 +#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004 +#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x032 +#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004 +#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x032 +#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004 +#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x032 +#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004 +#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x032 +#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004 +#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x032 +#define MX27_PAD_NFRB__NFRB 0xa0 0x000 +#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 +#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 +#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004 +#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005 +#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032 +#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004 +#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005 +#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032 +#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004 +#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005 +#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032 +#define MX27_PAD_NFALE__NFALE 0xa4 0x004 +#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005 +#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032 +#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004 +#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005 +#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032 +#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004 +#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005 +#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032 +#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004 +#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005 +#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032 +#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004 +#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001 +#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032 +#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000 +#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001 +#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032 +#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004 +#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005 +#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032 +#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000 +#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005 +#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032 +#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000 +#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001 +#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032 +#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000 +#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005 +#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032 +#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000 +#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005 +#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032 +#define MX27_PAD_CLKO__CLKO 0xaf 0x004 +#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032 +#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000 +#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005 +#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032 +#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000 +#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005 +#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032 +#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000 +#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005 +#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032 +#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000 +#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005 +#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032 +#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000 +#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005 +#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032 +#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004 +#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005 +#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032 +#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004 +#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005 +#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032 +#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004 +#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 +#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 +#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 +#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004 +#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x032 +#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004 +#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x032 +#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004 +#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x032 +#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004 +#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x032 +#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004 +#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x032 +#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004 +#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x032 +#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004 +#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x032 +#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004 +#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x032 + +#endif /* __DTS_IMX27_PINFUNC_H */ diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-apf28dev.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-apf28dev.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-apf28dev.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-apf28dev.dts 2014-04-13 23:18:35.000000000 +0200 @@ -48,6 +48,7 @@ MX28_PAD_LCD_D20__GPIO_1_20 MX28_PAD_LCD_D21__GPIO_1_21 MX28_PAD_LCD_D22__GPIO_1_22 + MX28_PAD_GPMI_CE1N__GPIO_0_17 >; fsl,drive-strength = ; fsl,voltage = ; @@ -66,6 +67,16 @@ fsl,voltage = ; fsl,pull-up = ; }; + + usb0_otg_apf28dev: otg-apf28dev@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D23__GPIO_1_23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; }; lcdif@80030000 { @@ -131,6 +142,8 @@ ahb@80080000 { usb0: usb@80080000 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_otg_apf28dev>; vbus-supply = <®_usb0_vbus>; status = "okay"; }; @@ -150,13 +163,17 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb0_vbus: usb0_vbus { + reg_usb0_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 23 1>; + enable-active-high; }; }; @@ -177,4 +194,14 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; + + gpio-keys { + compatible = "gpio-keys"; + + user-button { + label = "User button"; + gpios = <&gpio0 17 0>; + linux,code = <0x100>; + }; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-apx4devkit.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-apx4devkit.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-apx4devkit.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-apx4devkit.dts 2014-04-13 23:18:35.000000000 +0200 @@ -193,9 +193,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-cfa10036.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10036.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-cfa10036.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10036.dts 2014-04-13 23:18:35.000000000 +0200 @@ -100,6 +100,8 @@ usb0: usb@80080000 { pinctrl-names = "default"; pinctrl-0 = <&usb0_otg_cfa10036>; + dr_mode = "peripheral"; + phy_type = "utmi"; status = "okay"; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-cfa10037.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10037.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-cfa10037.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10037.dts 2014-04-13 23:18:35.000000000 +0200 @@ -54,7 +54,7 @@ ahb@80080000 { usb1: usb@80090000 { vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-0 = <&usb1_pins_a>; pinctrl-names = "default"; status = "okay"; }; @@ -72,9 +72,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&usb_pins_cfa10037>; regulator-name = "usb1_vbus"; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-cfa10049.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10049.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-cfa10049.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10049.dts 2014-04-13 23:18:35.000000000 +0200 @@ -229,15 +229,39 @@ i2c-parent = <&i2c1>; i2c@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; + + adc0: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; }; i2c@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + + adc1: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; }; i2c@2 { + #address-cells = <1>; + #size-cells = <0>; reg = <2>; + + adc2: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; }; i2c@3 { @@ -274,7 +298,7 @@ ahb@80080000 { usb1: usb@80090000 { vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-0 = <&usb1_pins_a>; pinctrl-names = "default"; status = "okay"; }; @@ -282,9 +306,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&usb_pins_cfa10049>; regulator-name = "usb1_vbus"; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-cfa10057.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10057.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-cfa10057.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10057.dts 2014-04-13 23:18:35.000000000 +0200 @@ -134,7 +134,7 @@ ahb@80080000 { usb1: usb@80090000 { vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-0 = <&usb1_pins_a>; pinctrl-names = "default"; status = "okay"; }; @@ -142,9 +142,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&usb_pins_cfa10057>; regulator-name = "usb1_vbus"; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-cfa10058.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10058.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-cfa10058.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-cfa10058.dts 2014-04-13 23:18:35.000000000 +0200 @@ -101,7 +101,7 @@ ahb@80080000 { usb1: usb@80090000 { vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-0 = <&usb1_pins_a>; pinctrl-names = "default"; status = "okay"; }; @@ -109,11 +109,14 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@0 { pinctrl-names = "default"; pinctrl-0 = <&usb_pins_cfa10058>; compatible = "regulator-fixed"; + reg = <0>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx28.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx28.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -32,6 +32,8 @@ serial4 = &auart4; spi0 = &ssp1; spi1 = &ssp2; + usbphy0 = &usbphy0; + usbphy1 = &usbphy1; }; cpus { @@ -343,6 +345,19 @@ fsl,pull-up = ; }; + auart2_pins_a: auart2-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__AUART2_RX + MX28_PAD_AUART2_TX__AUART2_TX + MX28_PAD_AUART2_CTS__AUART2_CTS + MX28_PAD_AUART2_RTS__AUART2_RTS + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + auart3_pins_a: auart3@0 { reg = <0>; fsl,pinmux-ids = < @@ -655,6 +670,33 @@ fsl,pull-up = ; }; + lcdif_18bit_pins_a: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + lcdif_16bit_pins_a: lcdif-16bit@0 { reg = <0>; fsl,pinmux-ids = < @@ -743,7 +785,7 @@ fsl,pull-up = ; }; - usbphy0_pins_a: usbphy0@0 { + usb0_pins_a: usb0@0 { reg = <0>; fsl,pinmux-ids = < MX28_PAD_SSP2_SS2__USB0_OVERCURRENT @@ -753,7 +795,7 @@ fsl,pull-up = ; }; - usbphy0_pins_b: usbphy0@1 { + usb0_pins_b: usb0@1 { reg = <1>; fsl,pinmux-ids = < MX28_PAD_AUART1_CTS__USB0_OVERCURRENT @@ -763,7 +805,7 @@ fsl,pull-up = ; }; - usbphy1_pins_a: usbphy1@0 { + usb1_pins_a: usb1@0 { reg = <0>; fsl,pinmux-ids = < MX28_PAD_SSP2_SS1__USB1_OVERCURRENT @@ -782,6 +824,17 @@ fsl,voltage = ; fsl,pull-up = ; }; + + usb0_id_pins_b: usb0id1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM2__USB0_ID + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; digctl: digctl@8001c000 { @@ -946,6 +999,7 @@ 20 21 22 23 24 25>; status = "disabled"; clocks = <&clks 41>; + #io-channel-cells = <1>; }; spdif: spdif@80054000 { @@ -1130,4 +1184,9 @@ status = "disabled"; }; }; + + iio_hwmon { + compatible = "iio-hwmon"; + io-channels = <&lradc 8>; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-duckbill.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-duckbill.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-duckbill.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-duckbill.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2013 Michael Heimpold + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "I2SE Duckbill"; + compatible = "i2se,duckbill", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins_a: led_gpio@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__GPIO_3_4 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + }; + + apbx@80040000 { + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + status = "okay"; + }; + + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_3p3v>; + phy-reset-gpios = <&gpio4 13 0>; + phy-reset-duration = <100>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a>; + + status { + label = "duckbill:green:status"; + gpios = <&gpio3 5 0>; + }; + + failure { + label = "duckbill:red:status"; + gpios = <&gpio3 4 0>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,71 @@ +/* + * Copyright 2013 Eukréa Electromatique + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC + */ + +/dts-v1/; +#include "imx28-eukrea-mbmx28lc.dtsi" + +/ { + model = "Eukrea Electromatique MBMX283LC"; + compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; + + memory { + reg = <0x40000000 0x04000000>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl{ + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_cpuimx283>; + + hog_pins_cpuimx283: hog-cpuimx283@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,50 @@ +/* + * Copyright 2013 Eukréa Electromatique + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC + */ + +#include "imx28-eukrea-mbmx283lc.dts" + +/ { + model = "Eukrea Electromatique MBMX287LC"; + compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>; + hog_pins_cpuimx287: hog-cpuimx287@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SPDIF__GPIO_3_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,326 @@ +/* + * Copyright 2013 Eukréa Electromatique + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "imx28.dtsi" + +/ { + model = "Eukrea Electromatique MBMX28LC"; + compatible = "eukrea,mbmx28lc", "fsl,imx28"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 4 1000000>; + brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; + default-brightness-level = <10>; + }; + + button-sw3 { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; + + sw3 { + label = "SW3"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + }; + + button-sw4 { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; + + sw4 { + label = "SW4"; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + }; + + led-d6 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_d6_pins_mbmx28lc>; + + led1 { + label = "d6"; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-d7 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_d7_pins_mbmx28lc>; + + led1 { + label = "d7"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_lcd_3v3: regulator@1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb0_vbus: regulator@2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_vbus: regulator@3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx28-mbmx28lc-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "imx28-mbmx28lc-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "okay"; + + display0: display0 { + model = "43WVF1G-0"; + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9072000>; + hactive = <480>; + vactive = <272>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <40>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&pinctrl { + gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D21__GPIO_1_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D20__GPIO_1_20 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_VSYNC__LCD_VSYNC + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D23__GPIO_1_23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D22__GPIO_1_22 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D18__GPIO_1_18 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D19__GPIO_1_19 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + cd-inverted; + status = "okay"; +}; + +&usb0 { + disable-over-current; + vbus-supply = <®_usb0_vbus>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pins_b>; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-evk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-evk.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-evk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-evk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -193,6 +193,7 @@ i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <400000>; status = "okay"; sgtl5000: codec@0a { @@ -278,33 +279,39 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_vddio_sd0: vddio-sd0 { + reg_vddio_sd0: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "vddio-sd0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 28 0>; }; - reg_fec_3v3: fec-3v3 { + reg_fec_3v3: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; regulator-name = "fec-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 15 0>; }; - reg_usb0_vbus: usb0_vbus { + reg_usb0_vbus: regulator@3 { compatible = "regulator-fixed"; + reg = <3>; regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -312,8 +319,9 @@ enable-active-high; }; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@4 { compatible = "regulator-fixed"; + reg = <4>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -321,8 +329,9 @@ enable-active-high; }; - reg_lcd_3v3: lcd-3v3 { + reg_lcd_3v3: regulator@5 { compatible = "regulator-fixed"; + reg = <5>; regulator-name = "lcd-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -330,8 +339,9 @@ enable-active-high; }; - reg_can_3v3: can-3v3 { + reg_can_3v3: regulator@6 { compatible = "regulator-fixed"; + reg = <6>; regulator-name = "can-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-m28cu3.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-m28cu3.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-m28cu3.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-m28cu3.dts 2014-04-13 23:18:35.000000000 +0200 @@ -116,7 +116,6 @@ pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_m28>; display = <&display>; - reset-active-high; status = "okay"; display: display0 { @@ -180,7 +179,7 @@ usb1: usb@80090000 { vbus-supply = <®_usb1_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-0 = <&usb1_pins_a>; disable-over-current; status = "okay"; }; @@ -229,33 +228,39 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_vddio_sd0: vddio-sd0 { + reg_vddio_sd0: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "vddio-sd0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 29 0>; }; - reg_vddio_sd1: vddio-sd1 { + reg_vddio_sd1: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; regulator-name = "vddio-sd1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 0>; }; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@3 { compatible = "regulator-fixed"; + reg = <3>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-m28evk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-m28evk.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-m28evk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-m28evk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -194,7 +194,7 @@ }; rtc: rtc@68 { - compatible = "stm,mt41t62"; + compatible = "stm,m41t62"; reg = <0x68>; }; }; @@ -248,14 +248,14 @@ usb0: usb@80080000 { vbus-supply = <®_usb0_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&usbphy0_pins_a>; + pinctrl-0 = <&usb0_pins_a>; status = "okay"; }; usb1: usb@80090000 { vbus-supply = <®_usb1_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-0 = <&usb1_pins_a>; status = "okay"; }; @@ -285,33 +285,39 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_vddio_sd0: vddio-sd0 { + reg_vddio_sd0: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "vddio-sd0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 28 0>; }; - reg_usb0_vbus: usb0_vbus { + reg_usb0_vbus: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio3 12 0>; }; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@3 { compatible = "regulator-fixed"; + reg = <3>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-sps1.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-sps1.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-sps1.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-sps1.dts 2014-04-13 23:18:35.000000000 +0200 @@ -106,7 +106,7 @@ usb0: usb@80080000 { vbus-supply = <®_usb0_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&usbphy0_pins_b>; + pinctrl-0 = <&usb0_pins_b>; status = "okay"; }; @@ -127,9 +127,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb0_vbus: usb0_vbus { + reg_usb0_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx28-tx28.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-tx28.dts --- linux-3.14.1/arch/arm/boot/dts/imx28-tx28.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx28-tx28.dts 2014-04-13 23:18:35.000000000 +0200 @@ -43,9 +43,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb0_vbus: usb0_vbus { + reg_usb0_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -53,8 +56,9 @@ enable-active-high; }; - reg_usb1_vbus: usb1_vbus { + reg_usb1_vbus: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -62,35 +66,38 @@ enable-active-high; }; - reg_2p5v: 2p5v { + reg_2p5v: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - reg_3p3v: 3p3v { + reg_3p3v: regulator@3 { compatible = "regulator-fixed"; + reg = <3>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_can_xcvr: can-xcvr { + reg_can_xcvr: regulator@4 { compatible = "regulator-fixed"; + reg = <4>; regulator-name = "CAN XCVR"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 0 0>; - enable-active-low; pinctrl-names = "default"; pinctrl-0 = <&tx28_flexcan_xcvr_pins>; }; - reg_lcd: lcd-power { + reg_lcd: regulator@5 { compatible = "regulator-fixed"; + reg = <5>; regulator-name = "LCD POWER"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -98,8 +105,9 @@ enable-active-high; }; - reg_lcd_reset: lcd-reset { + reg_lcd_reset: regulator@6 { compatible = "regulator-fixed"; + reg = <6>; regulator-name = "LCD RESET"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx35.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx35.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx35.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx35.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,359 @@ +/* + * Copyright 2012 Steffen Trumtrar, Pengutronix + * + * based on imx27.dtsi + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include "imx35-pinfunc.h" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &spi1; + spi1 = &spi2; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm1136"; + device_type = "cpu"; + }; + }; + + avic: avic-interrupt-controller@68000000 { + compatible = "fsl,imx35-avic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x68000000 0x10000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&avic>; + ranges; + + L2: l2-cache@30000000 { + compatible = "arm,l210-cache"; + reg = <0x30000000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + aips1: aips@43f00000 { + compatible = "fsl,aips", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x43f00000 0x100000>; + ranges; + + i2c1: i2c@43f80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; + reg = <0x43f80000 0x4000>; + clocks = <&clks 51>; + clock-names = "ipg_per"; + interrupts = <10>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; + reg = <0x43f84000 0x4000>; + clocks = <&clks 53>; + clock-names = "ipg_per"; + interrupts = <3>; + status = "disabled"; + }; + + uart1: serial@43f90000 { + compatible = "fsl,imx35-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + clocks = <&clks 9>, <&clks 70>; + clock-names = "ipg", "per"; + interrupts = <45>; + status = "disabled"; + }; + + uart2: serial@43f94000 { + compatible = "fsl,imx35-uart", "fsl,imx21-uart"; + reg = <0x43f94000 0x4000>; + clocks = <&clks 9>, <&clks 71>; + clock-names = "ipg", "per"; + interrupts = <32>; + status = "disabled"; + }; + + i2c2: i2c@43f98000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; + reg = <0x43f98000 0x4000>; + clocks = <&clks 52>; + clock-names = "ipg_per"; + interrupts = <4>; + status = "disabled"; + }; + + ssi1: ssi@43fa0000 { + compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; + reg = <0x43fa0000 0x4000>; + interrupts = <11>; + clocks = <&clks 68>; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + + spi1: cspi@43fa4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-cspi"; + reg = <0x43fa4000 0x4000>; + clocks = <&clks 35 &clks 35>; + clock-names = "ipg", "per"; + interrupts = <14>; + status = "disabled"; + }; + + iomuxc: iomuxc@43fac000 { + compatible = "fsl,imx35-iomuxc"; + reg = <0x43fac000 0x4000>; + }; + }; + + spba: spba-bus@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x100000>; + ranges; + + uart3: serial@5000c000 { + compatible = "fsl,imx35-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + clocks = <&clks 9>, <&clks 72>; + clock-names = "ipg", "per"; + interrupts = <18>; + status = "disabled"; + }; + + spi2: cspi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx35-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 36 &clks 36>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + fec: fec@50038000 { + compatible = "fsl,imx35-fec", "fsl,imx27-fec"; + reg = <0x50038000 0x4000>; + clocks = <&clks 46>, <&clks 8>; + clock-names = "ipg", "ahb"; + interrupts = <57>; + status = "disabled"; + }; + }; + + aips2: aips@53f00000 { + compatible = "fsl,aips", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x53f00000 0x100000>; + ranges; + + clks: ccm@53f80000 { + compatible = "fsl,imx35-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + esdhc1: esdhc@53fb4000 { + compatible = "fsl,imx35-esdhc"; + reg = <0x53fb4000 0x4000>; + interrupts = <7>; + clocks = <&clks 9>, <&clks 8>, <&clks 43>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc2: esdhc@53fb8000 { + compatible = "fsl,imx35-esdhc"; + reg = <0x53fb8000 0x4000>; + interrupts = <8>; + clocks = <&clks 9>, <&clks 8>, <&clks 44>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + esdhc3: esdhc@53fbc000 { + compatible = "fsl,imx35-esdhc"; + reg = <0x53fbc000 0x4000>; + interrupts = <9>; + clocks = <&clks 9>, <&clks 8>, <&clks 45>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + audmux: audmux@53fc4000 { + compatible = "fsl,imx35-audmux", "fsl,imx31-audmux"; + reg = <0x53fc4000 0x4000>; + status = "disabled"; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma@53fd4000 { + compatible = "fsl,imx35-sdma"; + reg = <0x53fd4000 0x4000>; + clocks = <&clks 9>, <&clks 65>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + interrupts = <34>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; + }; + + wdog: wdog@53fdc000 { + compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 74>; + clock-names = ""; + interrupts = <55>; + }; + + can1: can@53fe4000 { + compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fe4000 0x1000>; + clocks = <&clks 33>; + clock-names = "ipg"; + interrupts = <43>; + status = "disabled"; + }; + + can2: can@53fe8000 { + compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fe8000 0x1000>; + clocks = <&clks 34>; + clock-names = "ipg"; + interrupts = <44>; + status = "disabled"; + }; + + usbotg: usb@53ff4000 { + compatible = "fsl,imx35-usb", "fsl,imx27-usb"; + reg = <0x53ff4000 0x0200>; + interrupts = <37>; + clocks = <&clks 9>, <&clks 73>, <&clks 28>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbhost1: usb@53ff4400 { + compatible = "fsl,imx35-usb", "fsl,imx27-usb"; + reg = <0x53ff4400 0x0200>; + interrupts = <35>; + clocks = <&clks 9>, <&clks 73>, <&clks 28>; + clock-names = "ipg", "ahb", "per"; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbmisc: usbmisc@53ff4600 { + #index-cells = <1>; + compatible = "fsl,imx35-usbmisc"; + clocks = <&clks 9>, <&clks 73>, <&clks 28>; + clock-names = "ipg", "ahb", "per"; + reg = <0x53ff4600 0x00f>; + }; + }; + + emi@80000000 { /* External Memory Interface */ + compatible = "fsl,emi", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x40000000>; + ranges; + + nfc: nand@bb000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx35-nand", "fsl,imx25-nand"; + reg = <0xbb000000 0x2000>; + clocks = <&clks 29>; + clock-names = ""; + interrupts = <33>; + status = "disabled"; + }; + + weim: weim@b8002000 { + #address-cells = <2>; + #size-cells = <1>; + clocks = <&clks 0>; + compatible = "fsl,imx35-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + ranges = < + 0 0 0xa0000000 0x8000000 + 1 0 0xa8000000 0x8000000 + 2 0 0xb0000000 0x2000000 + 3 0 0xb2000000 0x2000000 + 4 0 0xb4000000 0x2000000 + 5 0 0xb6000000 0x2000000 + >; + status = "disabled"; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,81 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx35.dtsi" + +/ { + model = "Eukrea CPUIMX35"; + compatible = "eukrea,cpuimx35", "fsl,imx35"; + + memory { + reg = <0x80000000 0x8000000>; /* 128M */ + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + imx35-eukrea { + pinctrl_fec: fecgrp { + fsl,pins = < + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 + MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX35_PAD_FEC_COL__FEC_COL 0x80000000 + MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 + MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 + MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 + MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 + MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 + MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 + MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 + MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 + MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 + MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 + MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 + >; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts --- linux-3.14.1/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,143 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include +#include "imx35-eukrea-cpuimx35.dtsi" + +/ { + model = "Eukrea CPUIMX35"; + compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bp1>; + + bp1 { + label = "BP1"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + linux,input-type = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led1>; + + led1 { + label = "led1"; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio3 24>; + status = "okay"; +}; + +&i2c1 { + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&iomuxc { + imx35-eukrea { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 + MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 + MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 + >; + }; + + pinctrl_bp1: bp1grp { + fsl,pins = ; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 + MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ + >; + }; + + pinctrl_led1: led1grp { + fsl,pins = ; + }; + + pinctrl_reg_lcd_3v3: reg-lcd-3v3 { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 + MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 + MX35_PAD_CTS1__UART1_CTS 0x1c5 + MX35_PAD_RTS1__UART1_RTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 + MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 + MX35_PAD_RTS2__UART2_RTS 0x1c5 + MX35_PAD_CTS2__UART2_CTS 0x1c5 + >; + }; + }; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx50.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx50.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx50.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx50.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,478 @@ +/* + * Copyright 2013 Greg Ungerer + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "skeleton.dtsi" +#include "imx50-pinfunc.h" +#include + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + + tzic: tz-interrupt-controller@0fffc000 { + compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x0fffc000 0x4000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + aips@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + spba@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + esdhc1: esdhc@50004000 { + compatible = "fsl,imx50-esdhc"; + reg = <0x50004000 0x4000>; + interrupts = <1>; + clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc2: esdhc@50008000 { + compatible = "fsl,imx50-esdhc"; + reg = <0x50008000 0x4000>; + interrupts = <2>; + clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + uart3: serial@5000c000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi1: ecspi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + compatible = "fsl,imx50-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <30>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ + status = "disabled"; + }; + + esdhc3: esdhc@50020000 { + compatible = "fsl,imx50-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc4: esdhc@50024000 { + compatible = "fsl,imx50-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + }; + + usbotg: usb@53f80000 { + compatible = "fsl,imx50-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + status = "disabled"; + }; + + usbh1: usb@53f80200 { + compatible = "fsl,imx50-usb", "fsl,imx27-usb"; + reg = <0x53f80200 0x0200>; + interrupts = <14>; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + status = "disabled"; + }; + + usbh2: usb@53f80400 { + compatible = "fsl,imx50-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + status = "disabled"; + }; + + usbh3: usb@53f80600 { + compatible = "fsl,imx50-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + status = "disabled"; + }; + + gpio1: gpio@53f84000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53f88000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@53f8c000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@53f90000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wdog1: wdog@53f98000 { + compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + clocks = <&clks IMX5_CLK_DUMMY>; + }; + + gpt: timer@53fa0000 { + compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; + reg = <0x53fa0000 0x4000>; + interrupts = <39>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; + clock-names = "ipg", "per"; + }; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + gpr: iomuxc-gpr@53fa8000 { + compatible = "fsl,imx50-iomuxc-gpr", "syscon"; + reg = <0x53fa8000 0xc>; + }; + + pwm1: pwm@53fb4000 { + #pwm-cells = <2>; + compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; + + pwm2: pwm@53fb8000 { + #pwm-cells = <2>; + compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; + reg = <0x53fb8000 0x4000>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <94>; + }; + + uart1: serial@53fbc000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + src: src@53fd0000 { + compatible = "fsl,imx50-src", "fsl,imx51-src"; + reg = <0x53fd0000 0x4000>; + #reset-cells = <1>; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx50-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + + gpio5: gpio@53fdc000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53fdc000 0x4000>; + interrupts = <103 104>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@53fe0000 { + compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; + reg = <0x53fe0000 0x4000>; + interrupts = <105 106>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c3: i2c@53fec000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; + reg = <0x53fec000 0x4000>; + interrupts = <64>; + clocks = <&clks IMX5_CLK_I2C3_GATE>; + status = "disabled"; + }; + + uart4: serial@53ff0000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, + <&clks IMX5_CLK_UART4_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + aips@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + uart5: serial@63f90000 { + compatible = "fsl,imx50-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, + <&clks IMX5_CLK_UART5_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + owire: owire@63fa4000 { + compatible = "fsl,imx50-owire", "fsl,imx21-owire"; + reg = <0x63fa4000 0x4000>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; + status = "disabled"; + }; + + ecspi2: ecspi@63fac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sdma: sdma@63fb0000 { + compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_SDMA_GATE>; + clock-names = "ipg", "ahb"; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; + }; + + cspi: cspi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c2: i2c@63fc4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; + reg = <0x63fc4000 0x4000>; + interrupts = <63>; + clocks = <&clks IMX5_CLK_I2C2_GATE>; + status = "disabled"; + }; + + i2c1: i2c@63fc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; + reg = <0x63fc8000 0x4000>; + interrupts = <62>; + clocks = <&clks IMX5_CLK_I2C1_GATE>; + status = "disabled"; + }; + + ssi1: ssi@63fcc000 { + compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fcc000 0x4000>; + interrupts = <29>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ + status = "disabled"; + }; + + audmux: audmux@63fd0000 { + compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; + reg = <0x63fd0000 0x4000>; + status = "disabled"; + }; + + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx50-evk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx50-evk.dts --- linux-3.14.1/arch/arm/boot/dts/imx50-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx50-evk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,119 @@ +/* + * Copyright 2013 Greg Ungerer + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx50.dtsi" + +/ { + model = "Freescale i.MX50 Evaluation Kit"; + compatible = "fsl,imx50-evk", "fsl,imx50"; + + memory { + reg = <0x70000000 0x80000000>; + }; +}; + +&cspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi>; + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>; + status = "okay"; + + flash: m25p32@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p32", "m25p80"; + spi-max-frequency = <25000000>; + reg = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "kernel"; + reg = <0x100000 0x300000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 12 0>; + status = "okay"; +}; + +&iomuxc { + imx50-evk { + pinctrl_cspi: cspigrp { + fsl,pins = < + MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 + MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 + MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 + MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 + MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX50_PAD_SSI_RXFS__FEC_MDC 0x80 + MX50_PAD_SSI_RXC__FEC_MDIO 0x80 + MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 + MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 + MX50_PAD_DISP_D2__FEC_RX_DV 0x80 + MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 + MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 + MX50_PAD_DISP_D5__FEC_TX_EN 0x80 + MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 + MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 + MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 + MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 + MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbh2 { + status = "okay"; +}; + +&usbh3 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx50-pinfunc.h linux-3.15-rc1.orig/arch/arm/boot/dts/imx50-pinfunc.h --- linux-3.14.1/arch/arm/boot/dts/imx50-pinfunc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx50-pinfunc.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,923 @@ +/* + * Copyright 2013 Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX50_PINFUNC_H +#define __DTS_IMX50_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 +#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 +#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 +#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 +#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 +#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0 +#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0 +#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 +#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 +#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 +#define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 +#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 +#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 +#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 +#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 +#define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 +#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 +#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 +#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0 +#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0 +#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0 +#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0 +#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0 +#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0 +#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0 +#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0 +#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0 +#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0 +#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0 +#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1 +#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0 +#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0 +#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0 +#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0 +#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0 +#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1 +#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0 +#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0 +#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0 +#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0 +#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0 +#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0 +#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0 +#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0 +#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0 +#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0 +#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0 +#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0 +#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0 +#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0 +#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0 +#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0 +#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0 +#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1 +#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0 +#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0 +#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0 +#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0 +#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0 +#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0 +#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0 +#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0 +#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0 +#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0 +#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0 +#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0 +#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0 +#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0 +#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0 +#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0 +#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0 +#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0 +#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0 +#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0 +#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0 +#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0 +#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0 +#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0 +#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0 +#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0 +#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0 +#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0 +#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0 +#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0 +#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0 +#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0 +#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0 +#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0 +#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0 +#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0 +#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0 +#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0 +#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0 +#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0 +#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0 +#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0 +#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0 +#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0 +#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0 +#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0 +#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0 +#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0 +#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0 +#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0 +#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0 +#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0 +#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0 +#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0 +#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0 +#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0 +#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1 +#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0 +#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0 +#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0 +#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1 +#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0 +#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0 +#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0 +#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0 +#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1 +#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0 +#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0 +#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0 +#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0 +#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2 +#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0 +#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0 +#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0 +#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3 +#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0 +#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3 +#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0 +#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0 +#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0 +#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2 +#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0 +#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0 +#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1 +#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0 +#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3 +#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0 +#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0 +#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1 +#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0 +#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0 +#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0 +#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1 +#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1 +#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0 +#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2 +#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0 +#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1 +#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1 +#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0 +#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0 +#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0 +#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0 +#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0 +#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0 +#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0 +#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0 +#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1 +#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0 +#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0 +#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0 +#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0 +#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0 +#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0 +#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0 +#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0 +#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0 +#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0 +#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0 +#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0 +#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0 +#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1 +#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0 +#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1 +#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0 +#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0 +#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0 +#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0 +#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0 +#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0 +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0 +#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0 +#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0 +#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0 +#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0 +#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1 +#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2 +#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0 +#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1 +#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0 +#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0 +#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1 +#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0 +#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0 +#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0 +#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0 +#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1 +#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0 +#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0 +#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0 +#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0 +#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0 +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0 +#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1 +#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1 +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0 +#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1 +#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4 +#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0 +#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1 +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0 +#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0 +#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0 +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0 +#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5 +#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0 +#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0 +#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1 +#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0 +#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0 +#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0 +#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0 +#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0 +#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0 +#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0 +#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0 +#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0 +#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0 +#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0 +#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0 +#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0 +#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0 +#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0 +#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0 +#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0 +#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0 +#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0 +#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0 +#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0 +#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0 +#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0 +#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0 +#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0 +#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0 +#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0 +#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0 +#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0 +#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0 +#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0 +#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0 +#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0 +#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0 +#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0 +#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0 +#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0 +#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0 +#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0 +#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0 +#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0 +#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0 +#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0 +#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0 +#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0 +#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0 +#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0 +#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0 +#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0 +#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0 +#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0 +#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0 +#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0 +#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0 +#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0 +#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0 +#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0 +#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0 +#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0 +#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0 +#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0 +#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0 +#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0 +#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1 +#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0 +#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0 +#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0 +#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0 +#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1 +#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0 +#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0 +#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0 +#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0 +#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0 +#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0 +#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0 +#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0 +#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0 +#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0 +#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0 +#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0 +#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0 +#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0 +#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0 +#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0 +#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0 +#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0 +#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0 +#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0 +#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0 +#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0 +#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0 +#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0 +#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0 +#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1 +#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0 +#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0 +#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0 +#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0 +#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0 +#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0 +#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0 +#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0 +#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0 +#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0 +#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0 +#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0 +#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0 +#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0 +#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0 +#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0 +#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0 +#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1 +#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0 +#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0 +#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0 +#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0 +#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0 +#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0 +#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0 +#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0 +#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0 +#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0 +#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0 +#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0 +#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0 +#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0 +#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0 +#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0 +#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0 +#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0 +#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0 +#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0 +#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0 +#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0 +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1 +#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0 +#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0 +#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0 +#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0 +#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0 +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1 +#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0 +#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0 +#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0 +#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0 +#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2 +#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0 +#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0 +#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0 +#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0 +#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0 +#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0 +#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0 +#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0 +#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0 +#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0 +#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0 +#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0 +#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0 +#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0 +#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0 +#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0 +#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0 +#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0 +#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0 +#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0 +#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0 +#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1 +#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0 +#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0 +#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0 +#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0 +#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0 +#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0 +#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0 +#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0 +#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0 +#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1 +#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0 +#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0 +#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0 +#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0 +#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0 +#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0 +#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0 +#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0 +#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0 +#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0 +#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0 +#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0 +#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0 +#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0 +#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0 +#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0 +#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0 +#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0 +#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0 +#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0 +#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0 +#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0 +#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0 +#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0 +#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0 +#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0 +#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0 +#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0 +#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0 +#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0 +#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2 +#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1 +#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1 +#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0 +#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0 +#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0 +#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0 +#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0 +#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2 +#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1 +#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1 +#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0 +#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0 +#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0 +#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0 +#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0 +#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0 +#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1 +#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1 +#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0 +#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0 +#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0 +#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1 +#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1 +#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1 +#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0 +#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0 +#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0 +#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0 +#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0 +#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1 +#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1 +#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1 +#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0 +#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0 +#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0 +#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0 +#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0 +#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1 +#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1 +#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0 +#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0 +#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0 +#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0 +#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1 +#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0 +#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0 +#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1 +#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0 +#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0 +#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0 +#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0 +#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1 +#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0 +#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0 +#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1 +#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0 +#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1 +#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1 +#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1 +#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2 +#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1 +#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3 +#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1 +#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1 +#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1 +#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1 +#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2 +#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2 +#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2 +#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2 +#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1 +#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1 +#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1 +#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0 +#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0 +#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0 +#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1 +#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0 +#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0 +#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0 +#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0 +#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0 +#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0 +#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0 +#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0 +#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0 +#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0 +#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0 +#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1 +#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1 +#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0 +#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1 +#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1 +#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0 +#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1 +#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1 +#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1 +#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1 +#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1 +#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1 +#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1 +#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1 +#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0 +#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1 +#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1 +#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1 +#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0 +#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1 +#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0 +#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0 +#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0 +#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0 +#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1 +#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0 +#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0 +#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1 +#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1 +#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0 +#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1 +#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1 +#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1 +#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0 +#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0 +#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1 +#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2 +#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2 +#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2 +#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2 +#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2 +#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2 +#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2 +#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2 +#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0 +#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2 +#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0 +#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0 +#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0 +#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2 +#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0 +#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0 +#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0 +#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0 +#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0 +#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0 +#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0 +#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0 +#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0 +#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0 +#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0 +#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0 +#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0 +#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0 +#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0 +#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0 +#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0 +#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0 +#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0 +#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0 +#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0 +#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0 +#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0 +#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0 +#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0 +#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0 +#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0 +#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0 +#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0 +#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0 +#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0 +#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0 +#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0 +#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0 +#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0 +#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0 +#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0 +#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0 +#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0 +#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0 +#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0 +#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0 + +#endif /* __DTS_IMX50_PINFUNC_H */ diff -Nur linux-3.14.1/arch/arm/boot/dts/imx51-apf51dev.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-apf51dev.dts --- linux-3.14.1/arch/arm/boot/dts/imx51-apf51dev.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-apf51dev.dts 2014-04-13 23:18:35.000000000 +0200 @@ -18,10 +18,9 @@ display@di1 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 0>; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1_1>; + pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { lw700 { @@ -41,6 +40,12 @@ pixelclk-active = <0>; }; }; + + port { + display_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; }; gpio-keys { @@ -48,7 +53,7 @@ user-key { label = "user"; - gpios = <&gpio1 3 0>; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; linux,code = <256>; /* BTN_0 */ }; }; @@ -58,7 +63,7 @@ user { label = "Heartbeat"; - gpios = <&gpio1 2 0>; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -66,31 +71,33 @@ &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; + pinctrl-0 = <&pinctrl_ecspi1>; fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_HIGH>; status = "okay"; }; &ecspi2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2_1>; + pinctrl-0 = <&pinctrl_ecspi2>; fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>; + cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, + <&gpio3 27 GPIO_ACTIVE_LOW>; status = "okay"; }; &esdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_1>; - cd-gpios = <&gpio2 29 0>; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; &esdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2_1>; + pinctrl-0 = <&pinctrl_esdhc2>; bus-width = <4>; non-removable; status = "okay"; @@ -98,7 +105,7 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_2>; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; }; @@ -106,7 +113,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx51-apf51dev { pinctrl_hog: hoggrp { fsl,pins = < MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 @@ -120,5 +127,85 @@ MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 >; }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 + MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 + MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed + MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + >; + }; }; }; + +&ipu_di0_disp0 { + remote-endpoint = <&display_in>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx51-apf51.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-apf51.dts --- linux-3.14.1/arch/arm/boot/dts/imx51-apf51.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-apf51.dts 2014-04-13 23:18:35.000000000 +0200 @@ -34,13 +34,47 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_2>; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "mii"; - phy-reset-gpios = <&gpio3 0 0>; + phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; phy-reset-duration = <1>; status = "okay"; }; +&iomuxc { + imx51-apf51 { + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + }; +}; + &nfc { nand-bus-width = <8>; nand-ecc-mode = "hw"; @@ -50,6 +84,6 @@ &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_2>; + pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx51-babbage.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-babbage.dts --- linux-3.14.1/arch/arm/boot/dts/imx51-babbage.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-babbage.dts 2014-04-13 23:18:35.000000000 +0200 @@ -21,12 +21,11 @@ reg = <0x90000000 0x20000000>; }; - display@di0 { + display0: display@di0 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 0>; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1_1>; + pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { native-mode = <&timing0>; timing0: dvi { @@ -41,14 +40,19 @@ vsync-len = <10>; }; }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; }; - display@di1 { + display1: display@di1 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 1>; interface-pix-fmt = "rgb565"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp2_1>; + pinctrl-0 = <&pinctrl_ipu_disp2>; status = "disabled"; display-timings { native-mode = <&timing1>; @@ -68,6 +72,12 @@ pixelclk-active = <0>; }; }; + + port { + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; }; gpio-keys { @@ -75,12 +85,23 @@ power { label = "Power Button"; - gpios = <&gpio2 21 0>; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-diagnostic { + label = "diagnostic"; + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; + }; + sound { compatible = "fsl,imx51-babbage-sgtl5000", "fsl,imx-audio-sgtl5000"; @@ -105,14 +126,14 @@ reg=<0>; #clock-cells = <0>; clock-frequency = <26000000>; - gpios = <&gpio4 26 1>; + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; }; }; }; &esdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_1>; + pinctrl-0 = <&pinctrl_esdhc1>; fsl,cd-controller; fsl,wp-controller; status = "okay"; @@ -120,24 +141,25 @@ &esdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2_1>; - cd-gpios = <&gpio1 6 0>; - wp-gpios = <&gpio1 5 0>; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>; + pinctrl-0 = <&pinctrl_uart3>; fsl,uart-has-rtscts; status = "okay"; }; &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; + pinctrl-0 = <&pinctrl_ecspi1>; fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; status = "okay"; pmic: mc13892@0 { @@ -148,7 +170,7 @@ spi-cs-high; reg = <0>; interrupt-parent = <&gpio1>; - interrupts = <8 0x4>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; regulators { sw1_reg: sw1 { @@ -258,6 +280,14 @@ }; }; +&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + &ssi2 { fsl,mode = "i2s-slave"; status = "okay"; @@ -267,7 +297,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx51-babbage { pinctrl_hog: hoggrp { fsl,pins = < MX51_PAD_GPIO1_0__SD1_CD 0x20d5 @@ -280,25 +310,194 @@ MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 >; }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 + MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 + MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 + MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 + MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 + MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX51_PAD_EIM_D22__GPIO2_6 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + >; + }; + + pinctrl_ipu_disp2: ipudisp2grp { + fsl,pins = < + MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 + MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 + MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 + MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 + MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 + MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 + MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 + MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 + MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 + MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 + MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 + MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 + MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 + MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 + MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 + MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 + MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 + MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 + MX51_PAD_DI_GP4__DI2_PIN15 0x5 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 + MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 + MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 + MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 + MX51_PAD_KEY_COL0__KEY_COL0 0xe8 + MX51_PAD_KEY_COL1__KEY_COL1 0xe8 + MX51_PAD_KEY_COL2__KEY_COL2 0xe8 + MX51_PAD_KEY_COL3__KEY_COL3 0xe8 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + MX51_PAD_EIM_D27__UART3_RTS 0x1c5 + MX51_PAD_EIM_D24__UART3_CTS 0x1c5 + >; + }; }; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>; + pinctrl-0 = <&pinctrl_uart1>; fsl,uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; sgtl5000: codec@0a { @@ -312,35 +511,39 @@ &audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; + pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; status = "okay"; }; &kpp { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_1>; - linux,keymap = <0x00000067 /* KEY_UP */ - 0x0001006c /* KEY_DOWN */ - 0x00020072 /* KEY_VOLUMEDOWN */ - 0x00030066 /* KEY_HOME */ - 0x0100006a /* KEY_RIGHT */ - 0x01010069 /* KEY_LEFT */ - 0x0102001c /* KEY_ENTER */ - 0x01030073 /* KEY_VOLUMEUP */ - 0x02000040 /* KEY_F6 */ - 0x02010042 /* KEY_F8 */ - 0x02020043 /* KEY_F9 */ - 0x02030044 /* KEY_F10 */ - 0x0300003b /* KEY_F1 */ - 0x0301003c /* KEY_F2 */ - 0x0302003d /* KEY_F3 */ - 0x03030074>; /* KEY_POWER */ + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 3, KEY_HOME) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_ENTER) + MATRIX_KEY(1, 3, KEY_VOLUMEUP) + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(2, 1, KEY_F8) + MATRIX_KEY(2, 2, KEY_F9) + MATRIX_KEY(2, 3, KEY_F10) + MATRIX_KEY(3, 0, KEY_F1) + MATRIX_KEY(3, 1, KEY_F2) + MATRIX_KEY(3, 2, KEY_F3) + MATRIX_KEY(3, 3, KEY_POWER) + >; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx51.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx51.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx51.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx51.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -12,6 +12,10 @@ #include "skeleton.dtsi" #include "imx51-pinfunc.h" +#include +#include +#include +#include / { aliases { @@ -21,6 +25,10 @@ gpio3 = &gpio4; i2c0 = &i2c1; i2c1 = &i2c2; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -64,21 +72,40 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a8"; reg = <0>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks 24>; + clock-latency = <62500>; + clocks = <&clks IMX5_CLK_CPU_PODF>; clock-names = "cpu"; operating-points = < - /* kHz uV (No regulator support) */ - 160000 0 - 800000 0 + 166000 1000000 + 600000 1050000 + 800000 1100000 >; + voltage-tolerance = <5>; }; }; + usbphy { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>, <&ipu_di1>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -92,13 +119,30 @@ }; ipu: ipu@40000000 { - #crtc-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; compatible = "fsl,imx51-ipu"; reg = <0x40000000 0x20000000>; interrupts = <11 10>; - clocks = <&clks 59>, <&clks 110>, <&clks 61>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; + + ipu_di0: port@2 { + reg = <2>; + + ipu_di0_disp0: endpoint { + }; + }; + + ipu_di1: port@3 { + reg = <3>; + + ipu_di1_disp1: endpoint { + }; + }; }; aips@70000000 { /* AIPS1 */ @@ -119,7 +163,9 @@ compatible = "fsl,imx51-esdhc"; reg = <0x70004000 0x4000>; interrupts = <1>; - clocks = <&clks 44>, <&clks 0>, <&clks 71>; + clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -128,7 +174,9 @@ compatible = "fsl,imx51-esdhc"; reg = <0x70008000 0x4000>; interrupts = <2>; - clocks = <&clks 45>, <&clks 0>, <&clks 72>; + clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -138,7 +186,8 @@ compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x7000c000 0x4000>; interrupts = <33>; - clocks = <&clks 32>, <&clks 33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -149,7 +198,8 @@ compatible = "fsl,imx51-ecspi"; reg = <0x70010000 0x4000>; interrupts = <36>; - clocks = <&clks 51>, <&clks 52>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -158,7 +208,7 @@ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; - clocks = <&clks 49>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; @@ -171,7 +221,9 @@ compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; interrupts = <3>; - clocks = <&clks 46>, <&clks 0>, <&clks 73>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -181,25 +233,20 @@ compatible = "fsl,imx51-esdhc"; reg = <0x70024000 0x4000>; interrupts = <4>; - clocks = <&clks 47>, <&clks 0>, <&clks 74>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; }; }; - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks 75>; - clock-names = "main_clk"; - status = "okay"; - }; - usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; interrupts = <18>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 0>; fsl,usbphy = <&usbphy0>; status = "disabled"; @@ -209,7 +256,7 @@ compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80200 0x0200>; interrupts = <14>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -218,7 +265,7 @@ compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80400 0x0200>; interrupts = <16>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -227,7 +274,7 @@ compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80600 0x0200>; interrupts = <17>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; @@ -236,7 +283,7 @@ #index-cells = <1>; compatible = "fsl,imx51-usbmisc"; reg = <0x73f80800 0x200>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@73f84000 { @@ -283,7 +330,7 @@ compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; reg = <0x73f94000 0x4000>; interrupts = <60>; - clocks = <&clks 0>; + clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; @@ -291,14 +338,14 @@ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; - clocks = <&clks 0>; + clocks = <&clks IMX5_CLK_DUMMY>; }; wdog2: wdog@73f9c000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f9c000 0x4000>; interrupts = <59>; - clocks = <&clks 0>; + clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; @@ -306,7 +353,8 @@ compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; reg = <0x73fa0000 0x4000>; interrupts = <39>; - clocks = <&clks 36>, <&clks 41>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; @@ -319,7 +367,8 @@ #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; - clocks = <&clks 37>, <&clks 38>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -328,7 +377,8 @@ #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; - clocks = <&clks 39>, <&clks 40>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -337,7 +387,8 @@ compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; - clocks = <&clks 28>, <&clks 29>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -346,7 +397,8 @@ compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fc0000 0x4000>; interrupts = <32>; - clocks = <&clks 30>, <&clks 31>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -376,14 +428,14 @@ compatible = "fsl,imx51-iim", "fsl,imx27-iim"; reg = <0x83f98000 0x4000>; interrupts = <69>; - clocks = <&clks 107>; + clocks = <&clks IMX5_CLK_IIM_GATE>; }; owire: owire@83fa4000 { compatible = "fsl,imx51-owire", "fsl,imx21-owire"; reg = <0x83fa4000 0x4000>; interrupts = <88>; - clocks = <&clks 159>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; status = "disabled"; }; @@ -393,7 +445,8 @@ compatible = "fsl,imx51-ecspi"; reg = <0x83fac000 0x4000>; interrupts = <37>; - clocks = <&clks 53>, <&clks 54>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -402,7 +455,8 @@ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; - clocks = <&clks 56>, <&clks 56>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; @@ -414,7 +468,8 @@ compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; reg = <0x83fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 55>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -425,7 +480,7 @@ compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; reg = <0x83fc4000 0x4000>; interrupts = <63>; - clocks = <&clks 35>; + clocks = <&clks IMX5_CLK_I2C2_GATE>; status = "disabled"; }; @@ -435,7 +490,7 @@ compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; reg = <0x83fc8000 0x4000>; interrupts = <62>; - clocks = <&clks 34>; + clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; @@ -443,7 +498,7 @@ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; - clocks = <&clks 48>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; @@ -455,6 +510,8 @@ audmux: audmux@83fd0000 { compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; reg = <0x83fd0000 0x4000>; + clocks = <&clks IMX5_CLK_DUMMY>; + clock-names = "audmux"; status = "disabled"; }; @@ -463,7 +520,7 @@ #size-cells = <1>; compatible = "fsl,imx51-weim"; reg = <0x83fda000 0x1000>; - clocks = <&clks 57>; + clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; ranges = < 0 0 0xb0000000 0x08000000 1 0 0xb8000000 0x08000000 @@ -479,7 +536,7 @@ compatible = "fsl,imx51-nand"; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; interrupts = <8>; - clocks = <&clks 60>; + clocks = <&clks IMX5_CLK_NFC_GATE>; status = "disabled"; }; @@ -487,7 +544,7 @@ compatible = "fsl,imx51-pata", "fsl,imx27-pata"; reg = <0x83fe0000 0x4000>; interrupts = <70>; - clocks = <&clks 172>; + clocks = <&clks IMX5_CLK_PATA_GATE>; status = "disabled"; }; @@ -495,7 +552,7 @@ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; - clocks = <&clks 50>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; @@ -508,336 +565,12 @@ compatible = "fsl,imx51-fec", "fsl,imx27-fec"; reg = <0x83fec000 0x4000>; interrupts = <87>; - clocks = <&clks 42>, <&clks 42>, <&clks 42>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; }; }; }; - -&iomuxc { - audmux { - pinctrl_audmux_1: audmuxgrp-1 { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - }; - - fec { - pinctrl_fec_1: fecgrp-1 { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 - MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 - MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 - MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 - >; - }; - - pinctrl_fec_2: fecgrp-2 { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - >; - }; - }; - - ecspi2 { - pinctrl_ecspi2_1: ecspi2grp-1 { - fsl,pins = < - MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 - MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 - MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 - >; - }; - }; - - esdhc1 { - pinctrl_esdhc1_1: esdhc1grp-1 { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - }; - - esdhc2 { - pinctrl_esdhc2_1: esdhc2grp-1 { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - }; - - i2c2 { - pinctrl_i2c2_1: i2c2grp-1 { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_i2c2_2: i2c2grp-2 { - fsl,pins = < - MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed - MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_i2c2_3: i2c2grp-3 { - fsl,pins = < - MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed - MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed - >; - }; - }; - - ipu_disp1 { - pinctrl_ipu_disp1_1: ipudisp1grp-1 { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ - >; - }; - }; - - ipu_disp2 { - pinctrl_ipu_disp2_1: ipudisp2grp-1 { - fsl,pins = < - MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 - MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 - MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 - MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 - MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 - MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 - MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 - MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 - MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 - MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 - MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 - MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 - MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 - MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 - MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 - MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 - MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ - MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */ - MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */ - >; - }; - }; - - kpp { - pinctrl_kpp_1: kppgrp-1 { - fsl,pins = < - MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 - MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 - MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 - MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 - MX51_PAD_KEY_COL0__KEY_COL0 0xe8 - MX51_PAD_KEY_COL1__KEY_COL1 0xe8 - MX51_PAD_KEY_COL2__KEY_COL2 0xe8 - MX51_PAD_KEY_COL3__KEY_COL3 0xe8 - >; - }; - }; - - pata { - pinctrl_pata_1: patagrp-1 { - fsl,pins = < - MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 - MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 - MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 - MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 - MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 - MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 - MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 - MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 - MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 - MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 - MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 - MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 - MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 - MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 - MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 - MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 - MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 - MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 - MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 - MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 - MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 - MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 - MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 - MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 - MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 - MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 - MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 - MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 - MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart1_rtscts_1: uart1rtscts-1 { - fsl,pins = < - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 - >; - }; - }; - - uart2 { - pinctrl_uart2_1: uart2grp-1 { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - }; - - uart3 { - pinctrl_uart3_1: uart3grp-1 { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - >; - }; - - pinctrl_uart3_rtscts_1: uart3rtscts-1 { - fsl,pins = < - MX51_PAD_EIM_D27__UART3_RTS 0x1c5 - MX51_PAD_EIM_D24__UART3_CTS 0x1c5 - >; - }; - - pinctrl_uart3_2: uart3grp-2 { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - }; - - usbh1 { - pinctrl_usbh1_1: usbh1grp-1 { - fsl,pins = < - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - >; - }; - }; - - usbh2 { - pinctrl_usbh2_1: usbh2grp-1 { - fsl,pins = < - MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 - MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 - MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 - MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 - MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 - MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 - MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 - MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 - MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 - MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 - MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 - MX51_PAD_EIM_A26__USBH2_STP 0x1e5 - >; - }; - }; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,93 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "imx51.dtsi" + +/ { + model = "Eukrea CPUIMX51"; + compatible = "eukrea,cpuimx51", "fsl,imx51"; + + memory { + reg = <0x90000000 0x10000000>; /* 256M */ + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + imx51-eukrea { + pinctrl_tsc2007_1: tsc2007grp-1 { + fsl,pins = < + MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 + MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed + MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed + >; + }; + }; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts --- linux-3.14.1/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,175 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +/dts-v1/; +#include "imx51-eukrea-cpuimx51.dtsi" +#include + +/ { + model = "Eukrea CPUIMX51"; + compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys_1>; + + button-1 { + label = "BP1"; + gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + linux,code = <256>; + gpio-key,wakeup; + linux,input-type = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx51-eukrea-tlv320aic23"; + ssi-controller = <&ssi2>; + fsl,mux-int-port = <2>; + fsl,mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; + fsl,cd-controller; + status = "okay"; +}; + +&i2c1 { + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + }; +}; + +&iomuxc { + imx51-eukrea { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_uart3_rtscts: uart3rtsctsgrp { + fsl,pins = < + MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 + MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 + >; + }; + + pinctrl_backlight_1: backlightgrp-1 { + fsl,pins = < + MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 + >; + }; + + pinctrl_esdhc1_cd: esdhc1_cd { + fsl,pins = < + MX51_PAD_GPIO1_0__SD1_CD 0x20d5 + >; + }; + + pinctrl_gpiokeys_1: gpiokeysgrp-1 { + fsl,pins = < + MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 + >; + }; + + pinctrl_gpioled: gpioledgrp-1 { + fsl,pins = < + MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 + >; + }; + + pinctrl_reg_lcd_3v3: reg_lcd_3v3 { + fsl,pins = < + MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 + >; + }; + }; +}; + +&ssi2 { + codec-handle = <&tlv320aic23>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; + fsl,uart-has-rtscts; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-ard.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-ard.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-ard.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-ard.dts 2014-04-13 23:18:35.000000000 +0200 @@ -49,9 +49,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -99,7 +102,7 @@ &esdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_2>; + pinctrl-0 = <&pinctrl_esdhc1>; cd-gpios = <&gpio1 1 0>; wp-gpios = <&gpio1 9 0>; status = "okay"; @@ -109,7 +112,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx53-ard { pinctrl_hog: hoggrp { fsl,pins = < MX53_PAD_GPIO_1__GPIO1_1 0x80000000 @@ -148,11 +151,33 @@ MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 >; }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; }; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_2>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx53.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx53.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -12,6 +12,9 @@ #include "skeleton.dtsi" #include "imx53-pinfunc.h" +#include +#include +#include / { aliases { @@ -25,6 +28,10 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -45,6 +52,11 @@ }; }; + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>, <&ipu_di1>; + }; + tzic: tz-interrupt-controller@0fffc000 { compatible = "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; @@ -84,14 +96,63 @@ interrupt-parent = <&tzic>; ranges; + sata: sata@10000000 { + compatible = "fsl,imx53-ahci"; + reg = <0x10000000 0x1000>; + interrupts = <28>; + clocks = <&clks IMX5_CLK_SATA_GATE>, + <&clks IMX5_CLK_SATA_REF>, + <&clks IMX5_CLK_AHB>; + clock-names = "sata_gate", "sata_ref", "ahb"; + status = "disabled"; + }; + ipu: ipu@18000000 { - #crtc-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; compatible = "fsl,imx53-ipu"; reg = <0x18000000 0x080000000>; interrupts = <11 10>; - clocks = <&clks 59>, <&clks 110>, <&clks 61>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; + + ipu_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu_di0_lvds0: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds0_in>; + }; + }; + + ipu_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu_di1_disp1: endpoint@0 { + reg = <0>; + }; + + ipu_di1_lvds1: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds1_in>; + }; + + ipu_di1_tve: endpoint@2 { + reg = <2>; + remote-endpoint = <&tve_in>; + }; + }; }; aips@50000000 { /* AIPS1 */ @@ -112,7 +173,9 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; - clocks = <&clks 44>, <&clks 0>, <&clks 71>; + clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -122,7 +185,9 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; - clocks = <&clks 45>, <&clks 0>, <&clks 72>; + clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -132,7 +197,8 @@ compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <33>; - clocks = <&clks 32>, <&clks 33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -143,16 +209,19 @@ compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x50010000 0x4000>; interrupts = <36>; - clocks = <&clks 51>, <&clks 52>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; ssi2: ssi@50014000 { - compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; + compatible = "fsl,imx53-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <30>; - clocks = <&clks 49>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; @@ -165,7 +234,9 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; - clocks = <&clks 46>, <&clks 0>, <&clks 73>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -175,7 +246,9 @@ compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; - clocks = <&clks 47>, <&clks 0>, <&clks 74>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -184,14 +257,14 @@ usbphy0: usbphy@0 { compatible = "usb-nop-xceiv"; - clocks = <&clks 124>; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; clock-names = "main_clk"; status = "okay"; }; usbphy1: usbphy@1 { compatible = "usb-nop-xceiv"; - clocks = <&clks 125>; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; clock-names = "main_clk"; status = "okay"; }; @@ -200,7 +273,7 @@ compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 0>; fsl,usbphy = <&usbphy0>; status = "disabled"; @@ -210,7 +283,7 @@ compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80200 0x0200>; interrupts = <14>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 1>; fsl,usbphy = <&usbphy1>; status = "disabled"; @@ -220,7 +293,7 @@ compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80400 0x0200>; interrupts = <16>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -229,7 +302,7 @@ compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80600 0x0200>; interrupts = <17>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; @@ -238,7 +311,7 @@ #index-cells = <1>; compatible = "fsl,imx53-usbmisc"; reg = <0x53f80800 0x200>; - clocks = <&clks 108>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@53f84000 { @@ -281,18 +354,26 @@ #interrupt-cells = <2>; }; + kpp: kpp@53f94000 { + compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; + reg = <0x53f94000 0x4000>; + interrupts = <60>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + wdog1: wdog@53f98000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; - clocks = <&clks 0>; + clocks = <&clks IMX5_CLK_DUMMY>; }; wdog2: wdog@53f9c000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; - clocks = <&clks 0>; + clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; @@ -300,521 +381,14 @@ compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; reg = <0x53fa0000 0x4000>; interrupts = <39>; - clocks = <&clks 36>, <&clks 41>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; iomuxc: iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc"; reg = <0x53fa8000 0x4000>; - - audmux { - pinctrl_audmux_1: audmuxgrp-1 { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_audmux_2: audmuxgrp-2 { - fsl,pins = < - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 - >; - }; - - pinctrl_audmux_3: audmuxgrp-3 { - fsl,pins = < - MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 - MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 - MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 - MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 - >; - }; - }; - - fec { - pinctrl_fec_1: fecgrp-1 { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_fec_2: fecgrp-2 { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - MX53_PAD_KEY_ROW1__FEC_COL 0x80000000 - MX53_PAD_KEY_COL3__FEC_CRS 0x80000000 - MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000 - MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000 - MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000 - MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000 - MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000 - MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000 - >; - }; - }; - - csi { - pinctrl_csi_1: csigrp-1 { - fsl,pins = < - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5 - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 - MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5 - MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5 - MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5 - MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5 - MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5 - MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5 - MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5 - MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5 - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 - >; - }; - - pinctrl_csi_2: csigrp-2 { - fsl,pins = < - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 - >; - }; - }; - - cspi { - pinctrl_cspi_1: cspigrp-1 { - fsl,pins = < - MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 - MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 - MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 - >; - }; - - pinctrl_cspi_2: cspigrp-2 { - fsl,pins = < - MX53_PAD_EIM_D22__CSPI_MISO 0x1d5 - MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5 - MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_ecspi1_2: ecspi1grp-2 { - fsl,pins = < - MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 - MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 - >; - }; - }; - - ecspi2 { - pinctrl_ecspi2_1: ecspi2grp-1 { - fsl,pins = < - MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000 - MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000 - MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000 - >; - }; - }; - - esdhc1 { - pinctrl_esdhc1_1: esdhc1grp-1 { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc1_2: esdhc1grp-2 { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - }; - - esdhc2 { - pinctrl_esdhc2_1: esdhc2grp-1 { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - }; - - esdhc3 { - pinctrl_esdhc3_1: esdhc3grp-1 { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - }; - - can1 { - pinctrl_can1_1: can1grp-1 { - fsl,pins = < - MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000 - MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can1_2: can1grp-2 { - fsl,pins = < - MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 - MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can1_3: can1grp-3 { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 - >; - }; - }; - - can2 { - pinctrl_can2_1: can2grp-1 { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - }; - - i2c1 { - pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 - MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 - >; - }; - - pinctrl_i2c1_2: i2c1grp-2 { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - }; - - i2c2 { - pinctrl_i2c2_1: i2c2grp-1 { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_i2c2_2: i2c2grp-2 { - fsl,pins = < - MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 - MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 - >; - }; - }; - - i2c3 { - pinctrl_i2c3_1: i2c3grp-1 { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 - >; - }; - }; - - ipu_disp0 { - pinctrl_ipu_disp0_1: ipudisp0grp-1 { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - }; - - ipu_disp1 { - pinctrl_ipu_disp1_1: ipudisp1grp-1 { - fsl,pins = < - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 - MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 - MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 - MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 - MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 - >; - }; - }; - - ipu_disp2 { - pinctrl_ipu_disp2_1: ipudisp2grp-1 { - fsl,pins = < - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 - >; - }; - }; - - nand { - pinctrl_nand_1: nandgrp-1 { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - }; - - owire { - pinctrl_owire_1: owiregrp-1 { - fsl,pins = < - MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000 - >; - }; - }; - - pwm1 { - pinctrl_pwm1_1: pwm1grp-1 { - fsl,pins = < - MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 - >; - }; - }; - - pwm2 { - pinctrl_pwm2_1: pwm2grp-1 { - fsl,pins = < - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart1_2: uart1grp-2 { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart1_3: uart1grp-3 { - fsl,pins = < - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 - >; - }; - }; - - uart2 { - pinctrl_uart2_1: uart2grp-1 { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2_2: uart2grp-2 { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 - >; - }; - }; - - uart3 { - pinctrl_uart3_1: uart3grp-1 { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - - pinctrl_uart3_2: uart3grp-2 { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - >; - }; - - }; - - uart4 { - pinctrl_uart4_1: uart4grp-1 { - fsl,pins = < - MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 - MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 - >; - }; - }; - - uart5 { - pinctrl_uart5_1: uart5grp-1 { - fsl,pins = < - MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 - MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 - >; - }; - }; }; gpr: iomuxc-gpr@53fa8000 { @@ -828,9 +402,12 @@ compatible = "fsl,imx53-ldb"; reg = <0x53fa8008 0x4>; gpr = <&gpr>; - clocks = <&clks 122>, <&clks 120>, - <&clks 115>, <&clks 116>, - <&clks 123>, <&clks 85>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; @@ -838,14 +415,24 @@ lvds-channel@0 { reg = <0>; - crtcs = <&ipu 0>; status = "disabled"; + + port { + lvds0_in: endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; }; lvds-channel@1 { reg = <1>; - crtcs = <&ipu 1>; status = "disabled"; + + port { + lvds1_in: endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; }; }; @@ -853,7 +440,8 @@ #pwm-cells = <2>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; - clocks = <&clks 37>, <&clks 38>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -862,7 +450,8 @@ #pwm-cells = <2>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; - clocks = <&clks 39>, <&clks 40>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -871,7 +460,8 @@ compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; interrupts = <31>; - clocks = <&clks 28>, <&clks 29>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -880,7 +470,8 @@ compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fc0000 0x4000>; interrupts = <32>; - clocks = <&clks 30>, <&clks 31>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -889,7 +480,8 @@ compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fc8000 0x4000>; interrupts = <82>; - clocks = <&clks 158>, <&clks 157>; + clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, + <&clks IMX5_CLK_CAN1_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -898,7 +490,8 @@ compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fcc000 0x4000>; interrupts = <83>; - clocks = <&clks 87>, <&clks 86>; + clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, + <&clks IMX5_CLK_CAN2_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -952,7 +545,7 @@ compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x53fec000 0x4000>; interrupts = <64>; - clocks = <&clks 88>; + clocks = <&clks IMX5_CLK_I2C3_GATE>; status = "disabled"; }; @@ -960,7 +553,8 @@ compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53ff0000 0x4000>; interrupts = <13>; - clocks = <&clks 65>, <&clks 66>; + clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, + <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -977,14 +571,15 @@ compatible = "fsl,imx53-iim", "fsl,imx27-iim"; reg = <0x63f98000 0x4000>; interrupts = <69>; - clocks = <&clks 107>; + clocks = <&clks IMX5_CLK_IIM_GATE>; }; uart5: serial@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; interrupts = <86>; - clocks = <&clks 67>, <&clks 68>; + clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, + <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -992,7 +587,7 @@ owire: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>; - clocks = <&clks 159>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; status = "disabled"; }; @@ -1002,7 +597,8 @@ compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x63fac000 0x4000>; interrupts = <37>; - clocks = <&clks 53>, <&clks 54>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -1011,7 +607,8 @@ compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; - clocks = <&clks 56>, <&clks 56>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; @@ -1023,7 +620,8 @@ compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; reg = <0x63fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 55>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -1034,7 +632,7 @@ compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc4000 0x4000>; interrupts = <63>; - clocks = <&clks 35>; + clocks = <&clks IMX5_CLK_I2C2_GATE>; status = "disabled"; }; @@ -1044,15 +642,16 @@ compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc8000 0x4000>; interrupts = <62>; - clocks = <&clks 34>; + clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; ssi1: ssi@63fcc000 { - compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; interrupts = <29>; - clocks = <&clks 48>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; @@ -1071,15 +670,16 @@ compatible = "fsl,imx53-nand"; reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; interrupts = <8>; - clocks = <&clks 60>; + clocks = <&clks IMX5_CLK_NFC_GATE>; status = "disabled"; }; ssi3: ssi@63fe8000 { - compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; interrupts = <96>; - clocks = <&clks 50>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; @@ -1092,7 +692,9 @@ compatible = "fsl,imx53-fec", "fsl,imx25-fec"; reg = <0x63fec000 0x4000>; interrupts = <87>; - clocks = <&clks 42>, <&clks 42>, <&clks 42>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; @@ -1101,17 +703,24 @@ compatible = "fsl,imx53-tve"; reg = <0x63ff0000 0x1000>; interrupts = <92>; - clocks = <&clks 69>, <&clks 116>; + clocks = <&clks IMX5_CLK_TVE_GATE>, + <&clks IMX5_CLK_IPU_DI1_SEL>; clock-names = "tve", "di_sel"; - crtcs = <&ipu 1>; status = "disabled"; + + port { + tve_in: endpoint { + remote-endpoint = <&ipu_di1_tve>; + }; + }; }; vpu: vpu@63ff4000 { compatible = "fsl,imx53-vpu"; reg = <0x63ff4000 0x1000>; interrupts = <9>; - clocks = <&clks 63>, <&clks 63>; + clocks = <&clks IMX5_CLK_VPU_GATE>, + <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; iram = <&ocram>; status = "disabled"; @@ -1121,7 +730,7 @@ ocram: sram@f8000000 { compatible = "mmio-sram"; reg = <0xf8000000 0x20000>; - clocks = <&clks 186>; + clocks = <&clks IMX5_CLK_OCRAM>; }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-evk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-evk.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-evk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-evk.dts 1970-01-01 01:00:00.000000000 +0100 @@ -1,126 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Freescale i.MX53 Evaluation Kit"; - compatible = "fsl,imx53-evk", "fsl,imx53"; - - memory { - reg = <0x70000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "Heartbeat"; - gpios = <&gpio7 7 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_1>; - cd-gpios = <&gpio3 13 0>; - wp-gpios = <&gpio3 14 0>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; - status = "okay"; - - flash: at45db321d@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0x3c0000>; - }; - }; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3_1>; - cd-gpios = <&gpio3 11 0>; - wp-gpios = <&gpio3 12 0>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 - MX53_PAD_EIM_D19__GPIO3_19 0x80000000 - MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 - MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 - MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 - MX53_PAD_EIM_DA14__GPIO3_14 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_1>; - status = "okay"; - - pmic: mc13892@08 { - compatible = "fsl,mc13892", "fsl,mc13xxx"; - reg = <0x08>; - }; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 0>; - status = "okay"; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-m53evk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-m53evk.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-m53evk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-m53evk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -21,12 +21,11 @@ }; soc { - display@di1 { + display1: display@di1 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 1>; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp2_1>; + pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { 800x480p60 { @@ -44,6 +43,12 @@ }; }; }; + + port { + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; }; backlight { @@ -51,6 +56,7 @@ pwms = <&pwm1 0 3000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; + power-supply = <®_backlight>; }; leds { @@ -73,14 +79,36 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p2v: 3p2v { + reg_3p2v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P2V"; regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3200000>; regulator-always-on; }; + + + reg_backlight: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd-supply"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 0>; + }; }; sound { @@ -102,25 +130,25 @@ &audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_2>; + pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; &can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_3>; + pinctrl-0 = <&pinctrl_can1>; status = "okay"; }; &can2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2_1>; + pinctrl-0 = <&pinctrl_can2>; status = "okay"; }; &esdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_1>; + pinctrl-0 = <&pinctrl_esdhc1>; cd-gpios = <&gpio1 1 0>; wp-gpios = <&gpio1 9 0>; status = "okay"; @@ -128,14 +156,14 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; status = "okay"; }; &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_2>; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; sgtl5000: codec@0a { @@ -143,13 +171,13 @@ reg = <0x0a>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; - clocks = <&clks 150>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; }; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_2>; + pinctrl-0 = <&pinctrl_i2c2>; clock-frequency = <400000>; status = "okay"; @@ -193,7 +221,7 @@ &i2c3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; }; @@ -201,14 +229,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx53-m53evk { pinctrl_hog: hoggrp { fsl,pins = < MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 - + MX53_PAD_GPIO_2__GPIO1_2 0x80000000 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 >; }; @@ -218,12 +246,172 @@ MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 >; }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 + MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 + MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 + MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 + MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 + MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 + MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 + MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 + >; + }; }; }; +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + &nfc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand_1>; + pinctrl-0 = <&pinctrl_nand>; nand-bus-width = <8>; nand-ecc-mode = "hw"; status = "okay"; @@ -231,7 +419,11 @@ &pwm1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_1>; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sata { status = "okay"; }; @@ -242,18 +434,29 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_2>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-mba53.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-mba53.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-mba53.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-mba53.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,14 +17,6 @@ model = "TQ MBa53 starter kit"; compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; - reg_backlight: fixed@0 { - compatible = "regulator-fixed"; - regulator-name = "lcd-supply"; - gpio = <&gpio2 5 0>; - startup-delay-us = <5000>; - enable-active-low; - }; - backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; @@ -38,17 +30,37 @@ compatible = "fsl,imx-parallel-display"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp1_1>; - crtcs = <&ipu 1>; interface-pix-fmt = "rgb24"; status = "disabled"; + + port { + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; }; - reg_3p2v: 3p2v { - compatible = "regulator-fixed"; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_backlight: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "lcd-supply"; + gpio = <&gpio2 5 0>; + startup-delay-us = <5000>; + }; + + reg_3p2v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; }; sound { @@ -141,6 +153,10 @@ }; }; +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + &cspi { status = "okay"; }; @@ -148,14 +164,14 @@ &audmux { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; + pinctrl-0 = <&pinctrl_audmux>; }; &i2c2 { codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 150>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; }; @@ -228,7 +244,7 @@ &tve { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_vga_sync_1>; - ddc = <&i2c3>; + i2c-ddc-bus = <&i2c3>; fsl,tve-mode = "vga"; fsl,hsync-pin = <4>; fsl,vsync-pin = <6>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-qsb-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-qsb-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx53-qsb-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-qsb-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,345 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx53.dtsi" + +/ { + memory { + reg = <0x70000000 0x40000000>; + }; + + display0: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0>; + status = "disabled"; + display-timings { + claawvga { + native-mode; + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <60>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio1 8 0>; + linux,code = <116>; /* KEY_POWER */ + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio7_7>; + + user { + label = "Heartbeat"; + gpios = <&gpio7 7 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 0>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx53-qsb-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-qsb-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <5>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-qsb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_GPIO_8__GPIO1_8 0x80000000 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 + MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 + MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + >; + }; + + led_pin_gpio7_7: led_gpio7_7@0 { + fsl,pins = < + MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_ipu_disp0: ipudisp0grp { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p2v>; + VDDIO-supply = <®_3p2v>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-qsb.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-qsb.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-qsb.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-qsb.dts 2014-04-13 23:18:35.000000000 +0200 @@ -11,193 +11,14 @@ */ /dts-v1/; -#include "imx53.dtsi" +#include "imx53-qsb-common.dtsi" / { model = "Freescale i.MX53 Quick Start Board"; compatible = "fsl,imx53-qsb", "fsl,imx53"; - - memory { - reg = <0x70000000 0x40000000>; - }; - - display@di0 { - compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 0>; - interface-pix-fmt = "rgb565"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp0_1>; - status = "disabled"; - display-timings { - claawvga { - native-mode; - clock-frequency = <27000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <60>; - vback-porch = <10>; - vfront-porch = <10>; - hsync-len = <20>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power Button"; - gpios = <&gpio1 8 0>; - linux,code = <116>; /* KEY_POWER */ - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio2 14 0>; - linux,code = <115>; /* KEY_VOLUMEUP */ - gpio-key,wakeup; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio2 15 0>; - linux,code = <114>; /* KEY_VOLUMEDOWN */ - gpio-key,wakeup; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio7_7>; - - user { - label = "Heartbeat"; - gpios = <&gpio7 7 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p2v: 3p2v { - compatible = "regulator-fixed"; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_usb_vbus: usb_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 0>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx53-qsb-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-qsb-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_1>; - status = "okay"; -}; - -&ssi2 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3_1>; - cd-gpios = <&gpio3 11 0>; - wp-gpios = <&gpio3 12 0>; - bus-width = <8>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 - MX53_PAD_GPIO_8__GPIO1_8 0x80000000 - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 - MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 - MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 - >; - }; - - led_pin_gpio7_7: led_gpio7_7@0 { - fsl,pins = < - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 - >; - }; - }; - -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_1>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - clocks = <&clks 150>; - }; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; - pmic: dialog@48 { compatible = "dlg,da9053-aa", "dlg,da9052"; reg = <0x48>; @@ -292,32 +113,3 @@ }; }; }; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 0>; - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-qsrb.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-qsrb.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-qsrb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-qsrb.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,158 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx53-qsb-common.dtsi" + +/ { + model = "Freescale i.MX53 Quick Start-R Board"; + compatible = "fsl,imx53-qsrb", "fsl,imx53"; +}; + +&iomuxc { + i2c1 { + /* open drain */ + pinctrl_i2c1_qsrb: i2c1grp-1 { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec + MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec + >; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_qsrb>; + status = "okay"; + + pmic: mc34708@8 { + compatible = "fsl,mc34708"; + reg = <0x08>; + interrupt-parent = <&gpio5>; + interrupts = <23 0x8>; + regulators { + sw1_reg: sw1a { + regulator-name = "SW1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + }; + + sw1b_reg: sw1b { + regulator-name = "SW1B"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-name = "SW2"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1437500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1425000>; + regulator-boot-on; + }; + + sw4a_reg: sw4a { + regulator-name = "SW4A"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4b_reg: sw4b { + regulator-name = "SW4B"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw5_reg: sw5 { + regulator-name = "SW5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-name = "SWBST"; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-name = "VPLL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + vrefddr_reg: vrefddr { + regulator-name = "VREFDDR"; + regulator-boot-on; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-name = "VUSB"; + regulator-boot-on; + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-name = "VUSB2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vdac_reg: vdac { + regulator-name = "VDAC"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-name = "VGEN1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-name = "VGEN2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-smd.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-smd.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-smd.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-smd.dts 2014-04-13 23:18:35.000000000 +0200 @@ -40,7 +40,7 @@ &esdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_1>; + pinctrl-0 = <&pinctrl_esdhc1>; cd-gpios = <&gpio3 13 0>; wp-gpios = <&gpio4 11 0>; status = "okay"; @@ -48,21 +48,21 @@ &esdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2_1>; + pinctrl-0 = <&pinctrl_esdhc2>; non-removable; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-0 = <&pinctrl_uart3>; fsl,uart-has-rtscts; status = "okay"; }; &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; + pinctrl-0 = <&pinctrl_ecspi1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; @@ -95,7 +95,7 @@ &esdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3_1>; + pinctrl-0 = <&pinctrl_esdhc3>; non-removable; status = "okay"; }; @@ -104,7 +104,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx53-smd { pinctrl_hog: hoggrp { fsl,pins = < MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 @@ -116,24 +116,121 @@ MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 >; }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 + >; + }; }; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; codec: sgtl5000@0a { @@ -154,7 +251,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; accelerometer: mma8450@1c { @@ -175,7 +272,7 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-tqma53.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tqma53.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx53-tqma53.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tqma53.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -22,9 +22,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -35,8 +38,8 @@ &esdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2_1>, - <&pinctrl_tqma53_esdhc2_2>; + pinctrl-0 = <&pinctrl_esdhc2>, + <&pinctrl_esdhc2_cdwp>; vmmc-supply = <®_3p3v>; wp-gpios = <&gpio1 2 0>; cd-gpios = <&gpio1 4 0>; @@ -45,13 +48,13 @@ &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_2>; + pinctrl-0 = <&pinctrl_uart3>; status = "disabled"; }; &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; + pinctrl-0 = <&pinctrl_ecspi1>; fsl,spi-num-chipselects = <4>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio3 24 0>, <&gpio3 25 0>; @@ -60,7 +63,7 @@ &esdhc3 { /* EMMC */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3_1>; + pinctrl-0 = <&pinctrl_esdhc3>; vmmc-supply = <®_3p3v>; non-removable; bus-width = <8>; @@ -71,27 +74,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - esdhc2_2 { - pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 { - fsl,pins = < - MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ - >; - }; - }; - - i2s { - pinctrl_i2s_1: i2s-grp1 { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */ - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */ - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */ - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */ - >; - }; - }; - - hog { + imx53-tqma53 { pinctrl_hog: hoggrp { fsl,pins = < MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ @@ -107,43 +90,165 @@ MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ >; }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 + MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 + >; + }; + + pinctrl_cspi: cspigrp { + fsl,pins = < + MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 + MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 + MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + >; + }; + + pinctrl_esdhc2_cdwp: esdhc2cdwp { + fsl,pins = < + MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ + MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + >; + }; }; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_2>; + pinctrl-0 = <&pinctrl_uart1>; fsl,uart-has-rtscts; status = "disabled"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; + pinctrl-0 = <&pinctrl_uart2>; status = "disabled"; }; &can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_2>; + pinctrl-0 = <&pinctrl_can1>; status = "disabled"; }; &can2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2_1>; + pinctrl-0 = <&pinctrl_can2>; status = "disabled"; }; &i2c3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-0 = <&pinctrl_i2c3>; status = "disabled"; }; &cspi { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi_1>; + pinctrl-0 = <&pinctrl_cspi>; fsl,spi-num-chipselects = <3>; cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, <&gpio1 21 0>; @@ -152,7 +257,7 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; pmic: mc34708@8 { @@ -177,7 +282,7 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; status = "disabled"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-tx53.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tx53.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx53-tx53.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tx53.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -1,122 +1,550 @@ /* - * Copyright 2013 Steffen Trumtrar + * Copyright 2012 + * based on imx53-qsb.dts + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * Version 2 at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ -/include/ "imx53.dtsi" +#include "imx53.dtsi" +#include / { - model = "Ka-Ro TX53"; + model = "Ka-Ro electronics TX53 module"; compatible = "karo,tx53", "fsl,imx53"; - memory { - reg = <0x70000000 0x40000000>; /* Up to 1GiB */ + aliases { + can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ + can1 = &can1; + ipu = &ipu; + reg_can_xcvr = ®_can_xcvr; + usbh1 = &usbh1; + usbotg = &usbotg; + }; + + clocks { + ckih1 { + clock-frequency = <0>; + }; + + mclk: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_key>; + + power { + label = "Power Button"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stk5led>; + + user { + label = "Heartbeat"; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; }; regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2v5: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; - reg_3p3v: 3p3v { + reg_3v3: regulator@1 { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + reg = <1>; + regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; + }; + + reg_can_xcvr: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + reg_usbh1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; + + sound { + compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000"; + model = "tx53-audio-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + /* '1' based port numbers according to datasheet names */ + mux-int-port = <1>; + mux-ext-port = <5>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + status = "okay"; }; &can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_2>; - status = "disabled"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; }; &can2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2_1>; - status = "disabled"; + pinctrl-0 = <&pinctrl_can2>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; }; &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_2>; - status = "disabled"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <2>; + status = "okay"; + + cs-gpios = < + &gpio2 30 GPIO_ACTIVE_HIGH + &gpio3 19 GPIO_ACTIVE_HIGH + >; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <54000000>; + }; + + spidev1: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <54000000>; + }; }; &esdhc1 { + cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + fsl,wp-controller; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1_2>; - status = "disabled"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; }; &esdhc2 { + cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + fsl,wp-controller; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2_1>; - status = "disabled"; + pinctrl-0 = <&pinctrl_esdhc2>; + status = "okay"; }; &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; - status = "disabled"; + phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + phy-handle = <&phy0>; + mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ + status = "okay"; + + phy0: ethernet-phy@0 { + interrupt-parent = <&gpio2>; + interrupts = <4>; + device_type = "ethernet-phy"; + }; }; -&i2c3 { +&i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_2>; - status = "disabled"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + rtc1: ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ds1339>; + interrupt-parent = <&gpio4>; + interrupts = <20 0>; + }; }; -&owire { +&iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire_1>; - status = "disabled"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-tx53 { + pinctrl_hog: hoggrp { + /* pins not in use by any device on the Starterkit board series */ + fsl,pins = < + /* CMOS Sensor Interface */ + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 + MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 + MX53_PAD_GPIO_0__GPIO1_0 0x1f4 + /* Module Specific Signal */ + /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ + /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ + MX53_PAD_EIM_D29__GPIO3_29 0x1f4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 + /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ + /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ + MX53_PAD_EIM_A19__GPIO2_19 0x1f4 + MX53_PAD_EIM_A20__GPIO2_18 0x1f4 + MX53_PAD_EIM_A21__GPIO2_17 0x1f4 + MX53_PAD_EIM_A22__GPIO2_16 0x1f4 + MX53_PAD_EIM_A23__GPIO6_6 0x1f4 + MX53_PAD_EIM_A24__GPIO5_4 0x1f4 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 + /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ + /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ + MX53_PAD_GPIO_13__GPIO4_3 0x1f4 + MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 + MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 + MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 + MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 + MX53_PAD_EIM_OE__GPIO2_25 0x1f4 + MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 + MX53_PAD_EIM_RW__GPIO2_26 0x1f4 + MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 + MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 + MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 + MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 + MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 + MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 + MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 + MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = ; /* Flexcan XCVR enable */ + }; + + pinctrl_ds1339: ds1339grp { + fsl,pins = ; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 + MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_EIM_D24__GPIO3_24 0x1f0 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + MX53_PAD_EIM_D25__GPIO3_25 0x1f0 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_gpio_key: gpio-keygrp { + fsl,pins = ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 + >; + }; + + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_ssi2: ssi2grp { + fsl,pins = < + MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 + MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 + MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 + MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 + MX53_PAD_EIM_D27__GPIO3_27 0x1f0 + >; + }; + + pinctrl_stk5led: stk5ledgrp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbusgrp { + fsl,pins = < + MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ + MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ + >; + }; + }; +}; + +&ipu { + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; }; &pwm2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2_1>; - status = "disabled"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +&sdma { + fsl,sdma-ram-script-name = "sdma-imx53.bin"; }; &ssi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; - status = "disabled"; + fsl,mode = "i2s-slave"; + codec-handle = <&sgtl5000>; + status = "okay"; }; &ssi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_2>; status = "disabled"; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_2>, - <&pinctrl_uart1_3>; + pinctrl-0 = <&pinctrl_uart1>; fsl,uart-has-rtscts; - status = "disabled"; + status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_2>; + pinctrl-0 = <&pinctrl_uart2>; fsl,uart-has-rtscts; - status = "disabled"; + status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-0 = <&pinctrl_uart3>; fsl,uart-has-rtscts; - status = "disabled"; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + phy_type = "utmi"; + disable-over-current; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "peripheral"; + disable-over-current; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-tx53-x03x.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tx53-x03x.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-tx53-x03x.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tx53-x03x.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,315 @@ +/* + * Copyright 2013 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx53-tx53.dtsi" +#include +#include + +/ { + model = "Ka-Ro electronics TX53 module (LCD)"; + compatible = "karo,tx53", "fsl,imx53"; + + aliases { + display = &display; + }; + + soc { + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + crtcs = <&ipu 0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_vga1>; + status = "okay"; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_3v3>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <50>; + }; + + regulators { + reg_lcd_pwr: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_lcd_reset: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06_1>; + interrupt-parent = <&gpio6>; + interrupts = <15 0>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007>; + interrupt-parent = <&gpio3>; + interrupts = <26 0>; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <660>; + linux,wakeup; + }; +}; + +&iomuxc { + imx53-tx53-x03x { + pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { + fsl,pins = < + MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ + MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ + MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 + MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 + MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 + MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 + MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 + MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 + MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 + MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 + >; + }; + + pinctrl_rgb24_vga1: rgb24-vgagrp1 { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_tsc2007: tsc2007grp { + fsl,pins = < + MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ + >; + }; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + /* sample keymap */ + /* row/col 0,1 are mapped to KPP row/col 6,7 */ + linux,keymap = < + MATRIX_KEY(6, 6, KEY_POWER) + MATRIX_KEY(6, 7, KEY_KP0) + MATRIX_KEY(6, 2, KEY_KP1) + MATRIX_KEY(6, 3, KEY_KP2) + MATRIX_KEY(7, 6, KEY_KP3) + MATRIX_KEY(7, 7, KEY_KP4) + MATRIX_KEY(7, 2, KEY_KP5) + MATRIX_KEY(7, 3, KEY_KP6) + MATRIX_KEY(2, 6, KEY_KP7) + MATRIX_KEY(2, 7, KEY_KP8) + MATRIX_KEY(2, 2, KEY_KP9) + >; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-tx53-x13x.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tx53-x13x.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-tx53-x13x.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-tx53-x13x.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,243 @@ +/* + * Copyright 2013 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx53-tx53.dtsi" +#include + +/ { + model = "Ka-Ro electronics TX53 module (LVDS)"; + compatible = "karo,tx53", "fsl,imx53"; + + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 0>; + power-supply = <®_3v3>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 0>; + power-supply = <®_3v3>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <50>; + }; + + regulators { + reg_lcd_pwr0: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "LVDS0 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_lcd_pwr1: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "LVDS1 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + touchscreen2: eeti@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eeti2>; + interrupt-parent = <&gpio3>; + interrupts = <23 0>; + wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + linux,wakeup; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; + + touchscreen1: eeti@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eeti1>; + interrupt-parent = <&gpio3>; + interrupts = <22 0>; + wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + linux,wakeup; + }; +}; + +&iomuxc { + imx53-tx53-x13x { + pinctrl_i2c2: i2c2-grp1 { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_lvds0: lvds0grp { + fsl,pins = < + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + >; + }; + + pinctrl_lvds1: lvds1grp { + fsl,pins = < + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = ; + }; + + pinctrl_eeti1: eeti1grp { + fsl,pins = < + MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ + >; + }; + + pinctrl_eeti2: eeti2grp { + fsl,pins = < + MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>; + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&lvds_timing0>; + lvds_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hsync-len = <60>; + hfront-porch = <40>; + vback-porch = <21>; + vsync-len = <10>; + vfront-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&lvds_timing1>; + lvds_timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hsync-len = <60>; + hfront-porch = <40>; + vback-porch = <21>; + vsync-len = <10>; + vfront-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&sata { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-voipac-bsb.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-voipac-bsb.dts --- linux-3.14.1/arch/arm/boot/dts/imx53-voipac-bsb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-voipac-bsb.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,159 @@ +/* + * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx53-voipac-dmm-668.dtsi" + +/ { + sound { + compatible = "fsl,imx53-voipac-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-voipac-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio>; + + led1 { + label = "led-red"; + gpios = <&gpio3 29 0>; + default-state = "off"; + }; + + led2 { + label = "led-orange"; + gpios = <&gpio2 31 0>; + default-state = "off"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-voipac { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SD2_CD */ + MX53_PAD_EIM_D25__GPIO3_25 0x80000000 + /* SD2_WP */ + MX53_PAD_EIM_A19__GPIO2_19 0x80000000 + >; + }; + + led_pin_gpio: led_gpio { + fsl,pins = < + MX53_PAD_EIM_D29__GPIO3_29 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + >; + }; + + /* Keyboard controller */ + pinctrl_kpp_1: kppgrp-1 { + fsl,pins = < + MX53_PAD_GPIO_9__KPP_COL_6 0xe8 + MX53_PAD_GPIO_4__KPP_COL_7 0xe8 + MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 + MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 + MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 + MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 + MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 + MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 + MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 + MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + >; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */ + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio3 25 0>; + wp-gpios = <&gpio2 19 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&clks 150>; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp_1>; + linux,keymap = < + 0x0203003b /* KEY_F1 */ + 0x0603003c /* KEY_F2 */ + 0x0207003d /* KEY_F3 */ + 0x0607003e /* KEY_F4 */ + >; + keypad,num-rows = <8>; + keypad,num-columns = <1>; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,277 @@ +/* + * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx53.dtsi" + +/ { + model = "Voipac i.MX53 X53-DMM-668"; + compatible = "voipac,imx53-dmm-668", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>; + }; + + memory@b0000000 { + device_type = "memory"; + reg = <0xb0000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 0>; /* PEN */ + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-voipac { + pinctrl_hog: hoggrp { + fsl,pins = < + /* Make DA9053 regulator functional */ + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + /* FEC Power enable */ + MX53_PAD_GPIO_11__GPIO4_1 0x80000000 + /* FEC RST */ + MX53_PAD_GPIO_12__GPIO4_2 0x80000000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <4>; + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 2 0>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: dialog@48 { + compatible = "dlg,da9053-aa", "dlg,da9052"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */ + + regulators { + buck1_reg: buck1 { + regulator-name = "BUCKCORE"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "BUCKPRO"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "BUCKMEM"; + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1580000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-name = "BUCKPERI"; + regulator-min-microvolt = <2370000>; + regulator-max-microvolt = <2630000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4_2v775"; + regulator-min-microvolt = <2770000>; + regulator-max-microvolt = <2780000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7_2v75"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8_1v8"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1850000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9_1v5"; + regulator-min-microvolt = <1450000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-name = "ldo10_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts --- linux-3.14.1/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Sascha Hauer + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DTS_V1__ +#define __DTS_V1__ +/dts-v1/; +#endif + +#include "imx6dl.dtsi" +#include "imx6qdl-dfi-fs700-m60.dtsi" + +/ { + model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; + compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6dl.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -8,6 +8,7 @@ * */ +#include #include "imx6dl-pinfunc.h" #include "imx6qdl.dtsi" @@ -21,6 +22,26 @@ device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; cpu@1 { @@ -45,17 +66,17 @@ pxp: pxp@020f0000 { reg = <0x020f0000 0x4000>; - interrupts = <0 98 0x04>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; }; epdc: epdc@020f4000 { reg = <0x020f4000 0x4000>; - interrupts = <0 97 0x04>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; lcdif: lcdif@020f8000 { reg = <0x020f8000 0x4000>; - interrupts = <0 39 0x04>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -65,11 +86,20 @@ #size-cells = <0>; compatible = "fsl,imx1-i2c"; reg = <0x021f8000 0x4000>; - interrupts = <0 35 0x04>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu1_di0>, <&ipu1_di1>; + }; +}; + +&hdmi { + compatible = "fsl,imx6dl-hdmi"; }; &ldb { @@ -79,12 +109,4 @@ clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; - - lvds-channel@0 { - crtcs = <&ipu1 0>, <&ipu1 1>; - }; - - lvds-channel@1 { - crtcs = <&ipu1 0>, <&ipu1 1>; - }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-gw51xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw51xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6dl-gw51xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw51xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw51xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW51XX"; + compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-gw52xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw52xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6dl-gw52xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw52xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw52xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW52XX"; + compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-gw53xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw53xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6dl-gw53xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw53xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw53xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW53XX"; + compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-gw54xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw54xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6dl-gw54xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-gw54xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw54xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW54XX"; + compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-nitrogen6x.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-nitrogen6x.dts --- linux-3.14.1/arch/arm/boot/dts/imx6dl-nitrogen6x.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-nitrogen6x.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,21 @@ +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6x Board"; + compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-pinfunc.h linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-pinfunc.h --- linux-3.14.1/arch/arm/boot/dts/imx6dl-pinfunc.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-pinfunc.h 2014-04-13 23:18:35.000000000 +0200 @@ -755,6 +755,7 @@ #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 +#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 @@ -950,6 +951,7 @@ #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 +#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6dl-sabrelite.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-sabrelite.dts --- linux-3.14.1/arch/arm/boot/dts/imx6dl-sabrelite.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6dl-sabrelite.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,20 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-sabrelite.dtsi" + +/ { + model = "Freescale i.MX6 DualLite SABRE Lite Board"; + compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-arm2.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-arm2.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-arm2.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-arm2.dts 2014-04-13 23:18:35.000000000 +0200 @@ -23,14 +23,27 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; }; leds { @@ -46,7 +59,7 @@ &gpmi { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand_1>; + pinctrl-0 = <&pinctrl_gpmi_nand>; status = "disabled"; /* gpmi nand conflicts with SD */ }; @@ -54,28 +67,131 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx6q-arm2 { pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 >; }; - }; - arm2 { - pinctrl_usdhc3_arm2: usdhc3grp-arm2 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { fsl,pins = < MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 >; }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; }; }; &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_2>; + pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; status = "okay"; }; @@ -84,8 +200,8 @@ wp-gpios = <&gpio6 14 0>; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_1 - &pinctrl_usdhc3_arm2>; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; status = "okay"; }; @@ -93,13 +209,13 @@ non-removable; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-0 = <&pinctrl_usdhc4>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_2>; + pinctrl-0 = <&pinctrl_uart2>; fsl,dte-mode; fsl,uart-has-rtscts; status = "okay"; @@ -107,6 +223,6 @@ &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_1>; + pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-cm-fx6.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-cm-fx6.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,107 @@ +/* + * Copyright 2013 CompuLab Ltd. + * + * Author: Valentin Raevsky + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" + +/ { + model = "CompuLab CM-FX6"; + compatible = "compulab,cm-fx6", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat-led { + label = "Heartbeat"; + gpios = <&gpio2 31 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&iomuxc { + imx6q-cm-fx6 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Sascha Hauer + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DTS_V1__ +#define __DTS_V1__ +/dts-v1/; +#endif + +#include "imx6q.dtsi" +#include "imx6qdl-dfi-fs700-m60.dtsi" + +/ { + model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; + compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,199 @@ +/ { + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + dummy_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "dummy-supply"; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + chosen { + linux,stdout-path = &uart1; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf040b", "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + phy-mode = "rgmii"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-dfi-fs700-m60 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ + >; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { /* module slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio2 2 0>; + status = "okay"; +}; + +&usdhc3 { /* baseboard slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; +}; + +&usdhc4 { /* eMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -14,6 +14,8 @@ / { aliases { + can0 = &can1; + can1 = &can2; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -24,6 +26,10 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -33,6 +39,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; }; intc: interrupt-controller@00a01000 { @@ -75,7 +83,10 @@ dma_apbh: dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; - interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; @@ -88,7 +99,7 @@ #size-cells = <1>; reg = <0x00112000 0x2000>, <0x00114000 0x2000>; reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 0x04>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "bch"; clocks = <&clks 152>, <&clks 153>, <&clks 151>, <&clks 150>, <&clks 149>; @@ -109,7 +120,7 @@ L2: l2-cache@00a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; - interrupts = <0 92 0x04>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; arm,tag-latency = <4 2 3>; @@ -126,7 +137,7 @@ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = <0 123 0x04>; + interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; status = "disabled"; @@ -134,7 +145,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 0x04>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; aips-bus@02000000 { /* AIPS1 */ @@ -154,7 +165,7 @@ spdif: spdif@02004000 { compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; - interrupts = <0 52 0x04>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; dma-names = "rx", "tx"; @@ -176,9 +187,11 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; - interrupts = <0 31 0x04>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 112>, <&clks 112>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -187,9 +200,11 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; - interrupts = <0 32 0x04>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 113>, <&clks 113>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -198,9 +213,11 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; - interrupts = <0 33 0x04>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 114>, <&clks 114>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -209,16 +226,18 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; - interrupts = <0 34 0x04>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 115>, <&clks 115>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@02020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; - interrupts = <0 26 0x04>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; @@ -228,13 +247,15 @@ esai: esai@02024000 { reg = <0x02024000 0x4000>; - interrupts = <0 51 0x04>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; }; ssi1: ssi@02028000 { - compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x02028000 0x4000>; - interrupts = <0 46 0x04>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 178>; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; @@ -245,9 +266,11 @@ }; ssi2: ssi@0202c000 { - compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x0202c000 0x4000>; - interrupts = <0 47 0x04>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 179>; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; @@ -258,9 +281,11 @@ }; ssi3: ssi@02030000 { - compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x02030000 0x4000>; - interrupts = <0 48 0x04>; + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 180>; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; @@ -272,7 +297,7 @@ asrc: asrc@02034000 { reg = <0x02034000 0x4000>; - interrupts = <0 50 0x04>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; }; spba@0203c000 { @@ -282,7 +307,8 @@ vpu: vpu@02040000 { reg = <0x02040000 0x3c000>; - interrupts = <0 3 0x04 0 12 0x04>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>; }; aipstz@0207c000 { /* AIPSTZ1 */ @@ -293,7 +319,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; - interrupts = <0 83 0x04>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 145>; clock-names = "ipg", "per"; }; @@ -302,7 +328,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; - interrupts = <0 84 0x04>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 146>; clock-names = "ipg", "per"; }; @@ -311,7 +337,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; - interrupts = <0 85 0x04>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 147>; clock-names = "ipg", "per"; }; @@ -320,7 +346,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; - interrupts = <0 86 0x04>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 148>; clock-names = "ipg", "per"; }; @@ -328,23 +354,25 @@ can1: flexcan@02090000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; - interrupts = <0 110 0x04>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 108>, <&clks 109>; clock-names = "ipg", "per"; + status = "disabled"; }; can2: flexcan@02094000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; - interrupts = <0 111 0x04>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 110>, <&clks 111>; clock-names = "ipg", "per"; + status = "disabled"; }; gpt: gpt@02098000 { compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; - interrupts = <0 55 0x04>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 119>, <&clks 120>; clock-names = "ipg", "per"; }; @@ -352,7 +380,8 @@ gpio1: gpio@0209c000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; - interrupts = <0 66 0x04 0 67 0x04>; + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, + <0 67 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -362,7 +391,8 @@ gpio2: gpio@020a0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; - interrupts = <0 68 0x04 0 69 0x04>; + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, + <0 69 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -372,7 +402,8 @@ gpio3: gpio@020a4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; - interrupts = <0 70 0x04 0 71 0x04>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, + <0 71 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -382,7 +413,8 @@ gpio4: gpio@020a8000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; - interrupts = <0 72 0x04 0 73 0x04>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, + <0 73 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -392,7 +424,8 @@ gpio5: gpio@020ac000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; - interrupts = <0 74 0x04 0 75 0x04>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, + <0 75 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -402,7 +435,8 @@ gpio6: gpio@020b0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>; - interrupts = <0 76 0x04 0 77 0x04>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, + <0 77 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -412,7 +446,8 @@ gpio7: gpio@020b4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>; - interrupts = <0 78 0x04 0 79 0x04>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, + <0 79 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -421,20 +456,20 @@ kpp: kpp@020b8000 { reg = <0x020b8000 0x4000>; - interrupts = <0 82 0x04>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; }; wdog1: wdog@020bc000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; - interrupts = <0 80 0x04>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 0>; }; wdog2: wdog@020c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; - interrupts = <0 81 0x04>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 0>; status = "disabled"; }; @@ -442,14 +477,17 @@ clks: ccm@020c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; - interrupts = <0 87 0x04 0 88 0x04>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; }; anatop: anatop@020c8000 { compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; - interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, + <0 54 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; regulator-1p1@110 { compatible = "fsl,anatop-regulator"; @@ -495,7 +533,7 @@ reg_arm: regulator-vddcore@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "cpu"; + regulator-name = "vddarm"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; regulator-always-on; @@ -547,23 +585,26 @@ tempmon: tempmon { compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 0x04>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; fsl,tempmon-data = <&ocotp>; + clocks = <&clks 172>; }; usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; - interrupts = <0 44 0x04>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 182>; + fsl,anatop = <&anatop>; }; usbphy2: usbphy@020ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; - interrupts = <0 45 0x04>; + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 183>; + fsl,anatop = <&anatop>; }; snvs@020cc000 { @@ -575,31 +616,34 @@ snvs-rtc-lp@34 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; reg = <0x34 0x58>; - interrupts = <0 19 0x04 0 20 0x04>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>; }; }; epit1: epit@020d0000 { /* EPIT1 */ reg = <0x020d0000 0x4000>; - interrupts = <0 56 0x04>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; }; epit2: epit@020d4000 { /* EPIT2 */ reg = <0x020d4000 0x4000>; - interrupts = <0 57 0x04>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; src: src@020d8000 { compatible = "fsl,imx6q-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; - interrupts = <0 91 0x04 0 96 0x04>; + interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, + <0 96 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; gpc: gpc@020dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; - interrupts = <0 89 0x04 0 90 0x04>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, + <0 90 IRQ_TYPE_LEVEL_HIGH>; }; gpr: iomuxc-gpr@020e0000 { @@ -610,778 +654,103 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; + }; - audmux { - pinctrl_audmux_1: audmux-1 { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 - >; - }; - - pinctrl_audmux_2: audmux-2 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 - >; - }; - - pinctrl_audmux_3: audmux-3 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi1_2: ecspi1grp-2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - >; - }; - }; - - ecspi3 { - pinctrl_ecspi3_1: ecspi3grp-1 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - }; - - enet { - pinctrl_enet_1: enetgrp-1 { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_enet_2: enetgrp-2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - - pinctrl_enet_3: enetgrp-3 { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - }; - - esai { - pinctrl_esai_1: esaigrp-1 { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 - MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 - MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 - >; - }; - - pinctrl_esai_2: esaigrp-2 { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 - MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 - MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 - MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 - MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 - >; - }; - }; - - flexcan1 { - pinctrl_flexcan1_1: flexcan1grp-1 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 - >; - }; - - pinctrl_flexcan1_2: flexcan1grp-2 { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - >; - }; - }; - - flexcan2 { - pinctrl_flexcan2_1: flexcan2grp-1 { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 - >; - }; - }; - - gpmi-nand { - pinctrl_gpmi_nand_1: gpmi-nand-1 { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - }; - - hdmi_hdcp { - pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 - >; - }; - - pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 - >; - }; - - pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 - >; - }; - }; - - hdmi_cec { - pinctrl_hdmi_cec_1: hdmicecgrp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hdmi_cec_2: hdmicecgrp-2 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - }; - - i2c1 { - pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_2: i2c1grp-2 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - }; - - i2c2 { - pinctrl_i2c2_1: i2c2grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_2: i2c2grp-2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_3: i2c2grp-3 { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - }; - - i2c3 { - pinctrl_i2c3_1: i2c3grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_2: i2c3grp-2 { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_3: i2c3grp-3 { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_4: i2c3grp-4 { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - }; - - ipu1 { - pinctrl_ipu1_1: ipu1grp-1 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 - MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 - >; - }; - - pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 - MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 - MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 - MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 - MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 - MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 - MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 - MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 - >; - }; - }; - - mlb { - pinctrl_mlb_1: mlbgrp-1 { - fsl,pins = < - MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 - MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 - MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 - >; - }; - - pinctrl_mlb_2: mlbgrp-2 { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 - MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 - MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 - >; - }; - }; - - pwm0 { - pinctrl_pwm0_1: pwm0grp-1 { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - }; - - pwm3 { - pinctrl_pwm3_1: pwm3grp-1 { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - }; - - spdif { - pinctrl_spdif_1: spdifgrp-1 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 - >; - }; - - pinctrl_spdif_2: spdifgrp-2 { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_spdif_3: spdifgrp-3 { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - }; - - uart2 { - pinctrl_uart2_1: uart2grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; - }; - - uart3 { - pinctrl_uart3_1: uart3grp-1 { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3_2: uart3grp-2 { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - }; - - uart4 { - pinctrl_uart4_1: uart4grp-1 { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - }; - - usbotg { - pinctrl_usbotg_1: usbotggrp-1 { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotg_2: usbotggrp-2 { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - }; - - usbh2 { - pinctrl_usbh2_1: usbh2grp-1 { - fsl,pins = < - MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 - >; - }; - - pinctrl_usbh2_2: usbh2grp-2 { - fsl,pins = < - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 - >; - }; - }; - - usbh3 { - pinctrl_usbh3_1: usbh3grp-1 { - fsl,pins = < - MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 - MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 - >; - }; + ldb: ldb@020e0008 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; - pinctrl_usbh3_2: usbh3grp-2 { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 - >; - }; - }; + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; - usdhc1 { - pinctrl_usdhc1_1: usdhc1grp-1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 - >; - }; + port@0 { + reg = <0>; - pinctrl_usdhc1_2: usdhc1grp-2 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; + lvds0_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; }; - }; - usdhc2 { - pinctrl_usdhc2_1: usdhc2grp-1 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; + port@1 { + reg = <1>; - pinctrl_usdhc2_2: usdhc2grp-2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; + lvds0_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds0>; + }; }; }; - usdhc3 { - pinctrl_usdhc3_1: usdhc3grp-1 { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; - pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; + port@0 { + reg = <0>; - pinctrl_usdhc3_2: usdhc3grp-2 { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; + lvds1_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds1>; + }; }; - }; - usdhc4 { - pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; + port@1 { + reg = <1>; - pinctrl_usdhc4_2: usdhc4grp-2 { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - >; - }; - }; - - weim { - pinctrl_weim_cs0_1: weim_cs0grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor_1: weim_norgrp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - /* data */ - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - /* address */ - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; + lvds1_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds1>; + }; }; }; }; - ldb: ldb@020e0008 { + hdmi: hdmi@0120000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + reg = <0x00120000 0x9000>; + interrupts = <0 115 0x04>; gpr = <&gpr>; + clocks = <&clks 123>, <&clks 124>; + clock-names = "iahb", "isfr"; status = "disabled"; - lvds-channel@0 { + port@0 { reg = <0>; - status = "disabled"; + + hdmi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_hdmi>; + }; }; - lvds-channel@1 { + port@1 { reg = <1>; - status = "disabled"; + + hdmi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_hdmi>; + }; }; }; dcic1: dcic@020e4000 { reg = <0x020e4000 0x4000>; - interrupts = <0 124 0x04>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; }; dcic2: dcic@020e8000 { reg = <0x020e8000 0x4000>; - interrupts = <0 125 0x04>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; }; sdma: sdma@020ec000 { compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; - interrupts = <0 2 0x04>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 155>, <&clks 155>; clock-names = "ipg", "ahb"; #dma-cells = <3>; @@ -1398,7 +767,8 @@ caam@02100000 { reg = <0x02100000 0x40000>; - interrupts = <0 105 0x04 0 106 0x04>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, + <0 106 IRQ_TYPE_LEVEL_HIGH>; }; aipstz@0217c000 { /* AIPSTZ2 */ @@ -1408,7 +778,7 @@ usbotg: usb@02184000 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; - interrupts = <0 43 0x04>; + interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 162>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; @@ -1418,7 +788,7 @@ usbh1: usb@02184200 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; - interrupts = <0 40 0x04>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 162>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; @@ -1428,7 +798,7 @@ usbh2: usb@02184400 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; - interrupts = <0 41 0x04>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 162>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; @@ -1437,7 +807,7 @@ usbh3: usb@02184600 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; - interrupts = <0 42 0x04>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 162>; fsl,usbmisc = <&usbmisc 3>; status = "disabled"; @@ -1453,7 +823,9 @@ fec: ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; - interrupts = <0 118 0x04 0 119 0x04>; + interrupts-extended = + <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 117>, <&clks 117>, <&clks 190>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; @@ -1461,13 +833,15 @@ mlb@0218c000 { reg = <0x0218c000 0x4000>; - interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; + interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, + <0 117 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>; }; usdhc1: usdhc@02190000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; - interrupts = <0 22 0x04>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 163>, <&clks 163>, <&clks 163>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -1477,7 +851,7 @@ usdhc2: usdhc@02194000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; - interrupts = <0 23 0x04>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 164>, <&clks 164>, <&clks 164>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -1487,7 +861,7 @@ usdhc3: usdhc@02198000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; - interrupts = <0 24 0x04>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 165>, <&clks 165>, <&clks 165>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -1497,7 +871,7 @@ usdhc4: usdhc@0219c000 { compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; - interrupts = <0 25 0x04>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 166>, <&clks 166>, <&clks 166>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; @@ -1509,7 +883,7 @@ #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021a0000 0x4000>; - interrupts = <0 36 0x04>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 125>; status = "disabled"; }; @@ -1519,7 +893,7 @@ #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021a4000 0x4000>; - interrupts = <0 37 0x04>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 126>; status = "disabled"; }; @@ -1529,7 +903,7 @@ #size-cells = <0>; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021a8000 0x4000>; - interrupts = <0 38 0x04>; + interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 127>; status = "disabled"; }; @@ -1550,7 +924,7 @@ weim: weim@021b8000 { compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; - interrupts = <0 14 0x04>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 196>; }; @@ -1561,12 +935,12 @@ tzasc@021d0000 { /* TZASC1 */ reg = <0x021d0000 0x4000>; - interrupts = <0 108 0x04>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; }; tzasc@021d4000 { /* TZASC2 */ reg = <0x021d4000 0x4000>; - interrupts = <0 109 0x04>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; }; audmux: audmux@021d8000 { @@ -1575,23 +949,42 @@ status = "disabled"; }; - mipi@021dc000 { /* MIPI-CSI */ + mipi_csi: mipi@021dc000 { reg = <0x021dc000 0x4000>; }; - mipi@021e0000 { /* MIPI-DSI */ + mipi_dsi: mipi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x021e0000 0x4000>; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + + port@1 { + reg = <1>; + + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; }; vdoa@021e4000 { reg = <0x021e4000 0x4000>; - interrupts = <0 18 0x04>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; }; uart2: serial@021e8000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; - interrupts = <0 27 0x04>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; @@ -1602,7 +995,7 @@ uart3: serial@021ec000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; - interrupts = <0 28 0x04>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; @@ -1613,7 +1006,7 @@ uart4: serial@021f0000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; - interrupts = <0 29 0x04>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; @@ -1624,7 +1017,7 @@ uart5: serial@021f4000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; - interrupts = <0 30 0x04>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; @@ -1634,13 +1027,65 @@ }; ipu1: ipu@02400000 { - #crtc-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; compatible = "fsl,imx6q-ipu"; reg = <0x02400000 0x400000>; - interrupts = <0 6 0x4 0 5 0x4>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 130>, <&clks 131>, <&clks 132>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; + + ipu1_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu1_di0_disp0: endpoint@0 { + }; + + ipu1_di0_hdmi: endpoint@1 { + remote-endpoint = <&hdmi_mux_0>; + }; + + ipu1_di0_mipi: endpoint@2 { + remote-endpoint = <&mipi_mux_0>; + }; + + ipu1_di0_lvds0: endpoint@3 { + remote-endpoint = <&lvds0_mux_0>; + }; + + ipu1_di0_lvds1: endpoint@4 { + remote-endpoint = <&lvds1_mux_0>; + }; + }; + + ipu1_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu1_di0_disp1: endpoint@0 { + }; + + ipu1_di1_hdmi: endpoint@1 { + remote-endpoint = <&hdmi_mux_1>; + }; + + ipu1_di1_mipi: endpoint@2 { + remote-endpoint = <&mipi_mux_1>; + }; + + ipu1_di1_lvds0: endpoint@3 { + remote-endpoint = <&lvds0_mux_1>; + }; + + ipu1_di1_lvds1: endpoint@4 { + remote-endpoint = <&lvds1_mux_1>; + }; + }; }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,374 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + can0 = &can1; + ethernet0 = &fec; + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio1 26 0>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 30 0>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + hwmon: gsc@29 { + compatible = "gw,gsp"; + reg = <0x29>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: ltc3676@3c { + compatible = "ltc,ltc3676"; + reg = <0x3c>; + + regulators { + sw1_reg: ltc3676__sw1 { + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1175000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: ltc3676__sw2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: ltc3676__sw3 { + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1175000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: ltc3676__sw4 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ltc3676__ldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ltc3676__ldo4 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + videoin: adv7180@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-gw51xx { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + }; +}; + +&pcie { + reset-gpio = <&gpio1 0 0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,490 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + ethernet0 = &fec; + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + usdhc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio1 26 0>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + /* remove this fixed regulator once ltc3676__sw2 driver available */ + reg_1p8v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-sabrelite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-sabrelite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 30 0>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + hwmon: gsc@29 { + compatible = "gw,gsp"; + reg = <0x29>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pciswitch: pex8609@3f { + compatible = "plx,pex8609"; + reg = <0x3f>; + }; + + pmic: ltc3676@3c { + compatible = "ltc,ltc3676"; + reg = <0x3c>; + + regulators { + sw1_reg: ltc3676__sw1 { + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1175000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: ltc3676__sw2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: ltc3676__sw3 { + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1175000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: ltc3676__sw4 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ltc3676__ldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ltc3676__ldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ltc3676__ldo4 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accelerometer: fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x13>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 169>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; /* gpio7_12 active low */ + wakeup-gpios = <&gpio7 12 0>; + }; + + videoin: adv7180@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-gw52xx { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + +&ldb { + status = "okay"; + lvds-channel@0 { + crtcs = <&ipu1 0>, <&ipu1 1>; + }; +}; + +&pcie { + reset-gpio = <&gpio1 29 0>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,553 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + can0 = &can1; + ethernet0 = &fec; + ethernet1 = ð1; + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + sky2 = ð1; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + usdhc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio1 26 0>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + /* remove when pmic 1p8 regulator available */ + reg_1p8v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-sabrelite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-sabrelite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 30 0>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + hwmon: gsc@29 { + compatible = "gw,gsp"; + reg = <0x29>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pciclkgen: si53156@6b { + compatible = "sil,si53156"; + reg = <0x6b>; + }; + + pciswitch: pex8606@3f { + compatible = "plx,pex8606"; + reg = <0x3f>; + }; + + pmic: ltc3676@3c { + compatible = "ltc,ltc3676"; + reg = <0x3c>; + + regulators { + /* VDD_SOC */ + sw1_reg: ltc3676__sw1 { + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1175000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 */ + sw2_reg: ltc3676__sw2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM */ + sw3_reg: ltc3676__sw3 { + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1175000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR */ + sw4_reg: ltc3676__sw4 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 */ + ldo2_reg: ltc3676__ldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 */ + ldo3_reg: ltc3676__ldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH */ + ldo4_reg: ltc3676__ldo4 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accelerometer: fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + hdmiin: adv7611@4c { + compatible = "adi,adv7611"; + reg = <0x4c>; + }; + + touchscreen: egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <11 2>; /* gpio1_11 active low */ + wakeup-gpios = <&gpio1 11 0>; + }; + + videoout: adv7393@2a { + compatible = "adi,adv7393"; + reg = <0x2a>; + }; + + videoin: adv7180@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-gw53xx { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + reset-gpio = <&gpio1 29 0>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; + }; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,580 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + can0 = &can1; + ethernet0 = &fec; + ethernet1 = ð1; + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + sky2 = ð1; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + usdhc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio1 26 0>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-sabrelite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-sabrelite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 30 0>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + hwmon: gsc@29 { + compatible = "gw,gsp"; + reg = <0x29>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + pciswitch: pex8609@3f { + compatible = "plx,pex8609"; + reg = <0x3f>; + }; + + pciclkgen: si52147@6b { + compatible = "sil,si52147"; + reg = <0x6b>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accelerometer: fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <&sw4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + hdmiin: adv7611@4c { + compatible = "adi,adv7611"; + reg = <0x4c>; + }; + + touchscreen: egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; /* gpio7_12 active low */ + wakeup-gpios = <&gpio7 12 0>; + }; + + videoout: adv7393@2a { + compatible = "adi,adv7393"; + reg = <0x2a>; + }; + + videoin: adv7180@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-gw54xx { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + reset-gpio = <&gpio1 29 0>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; + }; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,422 @@ +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +/ { + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6x-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6x-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 27 0>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-nitrogen6x { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio2 6 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,17 +10,46 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include + / { memory { reg = <0x10000000 0x80000000>; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + user { + label = "debug"; + gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx-sabreauto-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; }; &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "disabled"; /* pin conflict with WEIM NOR */ flash: m25p80@0 { @@ -34,22 +63,130 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_2>; + pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; &gpmi { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand_1>; + pinctrl-0 = <&pinctrl_gpmi_nand>; status = "okay"; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx6qdl-sabreauto { pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 @@ -57,28 +194,245 @@ MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 >; }; - }; - ecspi1 { - pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs { fsl,pins = < MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 >; }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm3: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor: weimnorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; }; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_1>; + pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3_1>; - pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio6 15 0>; wp-gpios = <&gpio1 13 0>; status = "okay"; @@ -86,7 +440,7 @@ &weim { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x08000000 0x08000000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,423 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +/ { + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound { + compatible = "fsl,imx6q-sabrelite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-sabrelite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-sabrelite { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + cd-gpios = <&gpio2 6 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-sabresd.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,9 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include +#include + / { memory { reg = <0x10000000 0x40000000>; @@ -17,9 +20,12 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb_otg_vbus: usb_otg_vbus { + reg_usb_otg_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -27,8 +33,9 @@ enable-active-high; }; - reg_usb_h1_vbus: usb_h1_vbus { + reg_usb_h1_vbus: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -36,8 +43,9 @@ enable-active-high; }; - reg_audio: wm8962_supply { + reg_audio: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; regulator-name = "wm8962-supply"; gpio = <&gpio4 10 0>; enable-active-high; @@ -46,19 +54,28 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = ; + }; volume-up { label = "Volume Up"; - gpios = <&gpio1 4 0>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; gpio-key,wakeup; - linux,code = <115>; /* KEY_VOLUMEUP */ + linux,code = ; }; volume-down { label = "Volume Down"; - gpios = <&gpio1 5 0>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; gpio-key,wakeup; - linux,code = <114>; /* KEY_VOLUMEDOWN */ + linux,code = ; }; }; @@ -92,7 +109,7 @@ &audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_2>; + pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; @@ -100,7 +117,7 @@ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 9 0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_2>; + pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; flash: m25p80@0 { @@ -114,7 +131,7 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; + pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 25 0>; status = "okay"; @@ -123,7 +140,7 @@ &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_2>; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; codec: wm8962@1a { @@ -149,10 +166,116 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_2>; + pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; egalax_ts@04 { @@ -168,11 +291,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx6qdl-sabresd { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 @@ -184,6 +305,122 @@ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 >; }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; }; }; @@ -214,7 +451,7 @@ &pwm1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_1>; + pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; @@ -225,7 +462,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; @@ -237,14 +474,14 @@ &usbotg { vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_2>; + pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-0 = <&pinctrl_usdhc2>; bus-width = <8>; cd-gpios = <&gpio2 2 0>; wp-gpios = <&gpio2 3 0>; @@ -253,7 +490,7 @@ &usdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-0 = <&pinctrl_usdhc3>; bus-width = <8>; cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6qdl-wandboard.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-wandboard.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6qdl-wandboard.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6qdl-wandboard.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -12,17 +12,21 @@ / { regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_2p5v: 2p5v { + reg_2p5v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - reg_3p3v: 3p3v { + reg_3p3v: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -54,14 +58,14 @@ &audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_2>; + pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_2>; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; codec: sgtl5000@0a { @@ -77,7 +81,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx6qdl-wandboard { pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 @@ -91,20 +95,121 @@ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 >; }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; }; }; &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; + pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 29 0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; &spdif { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_3>; + pinctrl-0 = <&pinctrl_spdif>; status = "okay"; }; @@ -115,13 +220,13 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_2>; + pinctrl-0 = <&pinctrl_uart3>; fsl,uart-has-rtscts; status = "okay"; }; @@ -132,7 +237,7 @@ &usbotg { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_1>; + pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; dr_mode = "peripheral"; status = "okay"; @@ -140,21 +245,21 @@ &usdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_2>; + pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio1 2 0>; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_2>; + pinctrl-0 = <&pinctrl_usdhc2>; non-removable; status = "okay"; }; &usdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2>; + pinctrl-0 = <&pinctrl_usdhc3>; cd-gpios = <&gpio3 9 0>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,372 @@ +/* + * Copyright 2013 Data Modul AG + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" + +/ { + model = "Data Modul eDM-QMX6 Board"; + compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; + + aliases { + gpio7 = &stmpe_gpio; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 0>; + }; + + reg_usb_host1: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_host1_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 0>; + enable-active-high; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + label = "blue"; + gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-green { + label = "green"; + gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>; + }; + + led-pink { + label = "pink"; + gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>; + }; + + led-red { + label = "red"; + gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + phy-supply = <&vgen2_1v2_eth>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2 + &pinctrl_stmpe>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + interrupt-parent = <&gpio3>; + interrupts = <20 8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vdd_high_in: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + stmpe: stmpe1601@40 { + compatible = "st,stmpe1601"; + reg = <0x40>; + interrupts = <30 0>; + interrupt-parent = <&gpio3>; + + stmpe_gpio: stmpe_gpio { + #gpio-cells = <2>; + compatible = "st,stmpe-gpio"; + }; + }; + + temp1: ad7414@4c { + compatible = "ad,ad7414"; + reg = <0x4c>; + }; + + temp2: ad7414@4d { + compatible = "ad,ad7414"; + reg = <0x4d>; + }; + + rtc: m41t62@68 { + compatible = "stm,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-dmo-edmqmx6 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host1>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + vmmc-supply = <®_3p3v>; + non-removable; + bus-width = <8>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6q.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -8,10 +8,15 @@ * */ +#include #include "imx6q-pinfunc.h" #include "imx6qdl.dtsi" / { + aliases { + spi4 = &ecspi5; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -25,8 +30,17 @@ /* kHz uV */ 1200000 1275000 996000 1250000 + 852000 1250000 792000 1150000 - 396000 950000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks 104>, <&clks 6>, <&clks 16>, @@ -74,7 +88,7 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02018000 0x4000>; - interrupts = <0 35 0x04>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 116>, <&clks 116>; clock-names = "ipg", "per"; status = "disabled"; @@ -125,20 +139,92 @@ sata: sata@02200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; - interrupts = <0 39 0x04>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 154>, <&clks 187>, <&clks 105>; clock-names = "sata", "sata_ref", "ahb"; status = "disabled"; }; ipu2: ipu@02800000 { - #crtc-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; compatible = "fsl,imx6q-ipu"; reg = <0x02800000 0x400000>; - interrupts = <0 8 0x4 0 7 0x4>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 133>, <&clks 134>, <&clks 137>; clock-names = "bus", "di0", "di1"; resets = <&src 4>; + + ipu2_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu2_di0_disp0: endpoint@0 { + }; + + ipu2_di0_hdmi: endpoint@1 { + remote-endpoint = <&hdmi_mux_2>; + }; + + ipu2_di0_mipi: endpoint@2 { + }; + + ipu2_di0_lvds0: endpoint@3 { + remote-endpoint = <&lvds0_mux_2>; + }; + + ipu2_di0_lvds1: endpoint@4 { + remote-endpoint = <&lvds1_mux_2>; + }; + }; + + ipu2_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu2_di1_hdmi: endpoint@1 { + remote-endpoint = <&hdmi_mux_3>; + }; + + ipu2_di1_mipi: endpoint@2 { + }; + + ipu2_di1_lvds0: endpoint@3 { + remote-endpoint = <&lvds0_mux_3>; + }; + + ipu2_di1_lvds1: endpoint@4 { + remote-endpoint = <&lvds1_mux_3>; + }; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; + }; +}; + +&hdmi { + compatible = "fsl,imx6q-hdmi"; + + port@2 { + reg = <2>; + + hdmi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_hdmi>; + }; + }; + + port@3 { + reg = <3>; + + hdmi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_hdmi>; }; }; }; @@ -152,10 +238,56 @@ "di0", "di1"; lvds-channel@0 { - crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; + port@2 { + reg = <2>; + + lvds0_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_lvds0>; + }; + }; + + port@3 { + reg = <3>; + + lvds0_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_lvds0>; + }; + }; }; lvds-channel@1 { - crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; + port@2 { + reg = <2>; + + lvds1_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_lvds1>; + }; + }; + + port@3 { + reg = <3>; + + lvds1_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_lvds1>; + }; + }; + }; +}; + +&mipi_dsi { + port@2 { + reg = <2>; + + mipi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_mipi>; + }; + }; + + port@3 { + reg = <3>; + + mipi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_mipi>; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-gk802.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gk802.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-gk802.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gk802.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2013 Philipp Zabel + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "imx6q.dtsi" + +/ { + model = "Zealz GK802"; + compatible = "zealz,imx6q-gk802", "fsl,imx6q"; + + chosen { + linux,stdout-path = &uart4; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + recovery-button { + label = "recovery"; + gpios = <&gpio3 16 1>; + linux,code = <0x198>; /* KEY_RESTART */ + gpio-key,wakeup; + }; + }; +}; + +/* Internal I2C */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */ + eeprom: dm2016@51 { + compatible = "sdmc,dm2016"; + reg = <0x51>; + }; +}; + +/* External I2C via HDMI */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-gk802 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* Recovery button, active-low */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 + /* RTL8192CU enable GPIO, active-low */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + >; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* External USB-A port (USBOTG) */ +&usbotg { + disable-over-current; + status = "okay"; +}; + +/* Internal USB port (USBH1), connected to RTL8192CU */ +&usbh1 { + disable-over-current; + status = "okay"; +}; + +/* External microSD */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio6 11 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* Internal microSD */ +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-gw51xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw51xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-gw51xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw51xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw54xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Quad GW51XX"; + compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-gw52xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw52xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-gw52xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw52xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw52xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Quad GW52XX"; + compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-gw53xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw53xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-gw53xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw53xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw53xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Quad GW53XX"; + compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-gw5400-a.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw5400-a.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-gw5400-a.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw5400-a.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,546 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" + +/ { + model = "Gateworks Ventana GW5400-A"; + compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; + + /* these are used by bootloader for disabling nodes */ + aliases { + ethernet0 = &fec; + ethernet1 = ð1; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + led0 = &led0; + led1 = &led1; + led2 = &led2; + sky2 = ð1; + ssi0 = &ssi1; + spi0 = &ecspi1; + usb0 = &usbh1; + usb1 = &usbotg; + usdhc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio1 5 0>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6q-sabrelite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-sabrelite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,w25q256"; + spi-max-frequency = <30000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 30 0>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + hwmon: gsc@29 { + compatible = "gw,gsp"; + reg = <0x29>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + pciswitch: pex8609@3f { + compatible = "plx,pex8609"; + reg = <0x3f>; + }; + + pciclkgen: si52147@6b { + compatible = "sil,si52147"; + reg = <0x6b>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <&sw4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + hdmiin: adv7611@4c { + compatible = "adi,adv7611"; + reg = <0x4c>; + }; + + touchscreen: egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; /* gpio7_12 active low */ + wakeup-gpios = <&gpio7 12 0>; + }; + + videoout: adv7393@2a { + compatible = "adi,adv7393"; + reg = <0x2a>; + }; + + videoin: adv7180@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-gw5400-a { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + +&ldb { + status = "okay"; + lvds-channel@0 { + crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; + }; +}; + +&pcie { + reset-gpio = <&gpio1 29 0>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; + }; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-gw54xx.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw54xx.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-gw54xx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-gw54xx.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw54xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Quad GW54XX"; + compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-nitrogen6x.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-nitrogen6x.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-nitrogen6x.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-nitrogen6x.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6x Board"; + compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-phytec-pbab01.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-phytec-pbab01.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-phytec-pbab01.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-phytec-pbab01.dts 2014-04-13 23:18:35.000000000 +0200 @@ -21,10 +21,26 @@ status = "okay"; }; +&gpmi { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + &uart4 { status = "okay"; }; +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + &usdhc2 { status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -18,11 +18,35 @@ memory { reg = <0x10000000 0x80000000>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 0>; + }; + + reg_usb_h1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 0>; + }; + }; }; &ecspi3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3_1>; + pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 24 0>; @@ -36,7 +60,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; eeprom@50 { @@ -128,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx6q-phytec-pfla02 { pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 @@ -136,10 +160,109 @@ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ >; }; - }; - pfla02 { - pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { fsl,pins = < MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 @@ -150,21 +273,43 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3>; + pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 0>; status = "disabled"; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_1>; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; status = "disabled"; }; &usdhc2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_2>; + pinctrl-0 = <&pinctrl_usdhc2>; cd-gpios = <&gpio1 4 0>; wp-gpios = <&gpio1 2 0>; status = "disabled"; @@ -172,8 +317,8 @@ &usdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2 - &pinctrl_usdhc3_pfla02>; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; cd-gpios = <&gpio1 27 0>; wp-gpios = <&gpio1 29 0>; status = "disabled"; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-pinfunc.h linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-pinfunc.h --- linux-3.14.1/arch/arm/boot/dts/imx6q-pinfunc.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-pinfunc.h 2014-04-13 23:18:35.000000000 +0200 @@ -673,6 +673,7 @@ #define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 #define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 +#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 @@ -1024,6 +1025,7 @@ #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 +#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 #define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-sabrelite.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-sabrelite.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-sabrelite.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-sabrelite.dts 2014-04-13 23:18:35.000000000 +0200 @@ -12,189 +12,13 @@ /dts-v1/; #include "imx6q.dtsi" +#include "imx6qdl-sabrelite.dtsi" / { model = "Freescale i.MX6 Quad SABRE Lite Board"; compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - - reg_2p5v: 2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: usb_otg_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "sst,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks 201>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; }; &sata { status = "okay"; }; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_1>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2>; - cd-gpios = <&gpio7 0 0>; - wp-gpios = <&gpio7 1 0>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4_2>; - cd-gpios = <&gpio2 6 0>; - wp-gpios = <&gpio2 7 0>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-sbc6x.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-sbc6x.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-sbc6x.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-sbc6x.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,28 +17,78 @@ }; }; + &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; + pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; status = "okay"; }; +&iomuxc { + imx6q-sbc6x { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &usbotg { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_1>; + pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; status = "okay"; }; &usdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2>; + pinctrl-0 = <&pinctrl_usdhc3>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6q-udoo.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-udoo.dts --- linux-3.14.1/arch/arm/boot/dts/imx6q-udoo.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6q-udoo.dts 2014-04-13 23:18:35.000000000 +0200 @@ -21,19 +21,69 @@ }; }; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&iomuxc { + imx6q-udoo { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + &sata { status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &usdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2>; + pinctrl-0 = <&pinctrl_usdhc3>; non-removable; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6sl.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/imx6sl.dtsi --- linux-3.14.1/arch/arm/boot/dts/imx6sl.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6sl.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -7,6 +7,7 @@ * */ +#include #include "skeleton.dtsi" #include "imx6sl-pinfunc.h" #include @@ -27,6 +28,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; }; cpus { @@ -38,6 +41,27 @@ device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1225000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; @@ -73,10 +97,16 @@ interrupt-parent = <&intc>; ranges; + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + L2: l2-cache@00a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; - interrupts = <0 92 0x04>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; arm,tag-latency = <4 2 3>; @@ -85,7 +115,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 0x04>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; aips1: aips-bus@02000000 { @@ -104,7 +134,7 @@ spdif: spdif@02004000 { reg = <0x02004000 0x4000>; - interrupts = <0 52 0x04>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; }; ecspi1: ecspi@02008000 { @@ -112,7 +142,7 @@ #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; - interrupts = <0 31 0x04>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_ECSPI1>, <&clks IMX6SL_CLK_ECSPI1>; clock-names = "ipg", "per"; @@ -124,7 +154,7 @@ #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; - interrupts = <0 32 0x04>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_ECSPI2>, <&clks IMX6SL_CLK_ECSPI2>; clock-names = "ipg", "per"; @@ -136,7 +166,7 @@ #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; - interrupts = <0 33 0x04>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_ECSPI3>, <&clks IMX6SL_CLK_ECSPI3>; clock-names = "ipg", "per"; @@ -148,7 +178,7 @@ #size-cells = <0>; compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; - interrupts = <0 34 0x04>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_ECSPI4>, <&clks IMX6SL_CLK_ECSPI4>; clock-names = "ipg", "per"; @@ -159,7 +189,7 @@ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; - interrupts = <0 30 0x04>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; @@ -172,7 +202,7 @@ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; - interrupts = <0 26 0x04>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; @@ -185,7 +215,7 @@ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; - interrupts = <0 27 0x04>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; @@ -195,9 +225,11 @@ }; ssi1: ssi@02028000 { - compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6sl-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x02028000 0x4000>; - interrupts = <0 46 0x04>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SSI1>; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; @@ -207,9 +239,11 @@ }; ssi2: ssi@0202c000 { - compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6sl-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x0202c000 0x4000>; - interrupts = <0 47 0x04>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SSI2>; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; @@ -219,9 +253,11 @@ }; ssi3: ssi@02030000 { - compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6sl-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x02030000 0x4000>; - interrupts = <0 48 0x04>; + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SSI3>; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; @@ -234,7 +270,7 @@ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02034000 0x4000>; - interrupts = <0 28 0x04>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; @@ -247,7 +283,7 @@ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02038000 0x4000>; - interrupts = <0 29 0x04>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; @@ -261,7 +297,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; - interrupts = <0 83 0x04>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_PWM1>, <&clks IMX6SL_CLK_PWM1>; clock-names = "ipg", "per"; @@ -271,7 +307,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; - interrupts = <0 84 0x04>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_PWM2>, <&clks IMX6SL_CLK_PWM2>; clock-names = "ipg", "per"; @@ -281,7 +317,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; - interrupts = <0 85 0x04>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_PWM3>, <&clks IMX6SL_CLK_PWM3>; clock-names = "ipg", "per"; @@ -291,7 +327,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; - interrupts = <0 86 0x04>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_PWM4>, <&clks IMX6SL_CLK_PWM4>; clock-names = "ipg", "per"; @@ -300,7 +336,7 @@ gpt: gpt@02098000 { compatible = "fsl,imx6sl-gpt"; reg = <0x02098000 0x4000>; - interrupts = <0 55 0x04>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_GPT>, <&clks IMX6SL_CLK_GPT_SERIAL>; clock-names = "ipg", "per"; @@ -309,7 +345,8 @@ gpio1: gpio@0209c000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; - interrupts = <0 66 0x04 0 67 0x04>; + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, + <0 67 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -319,7 +356,8 @@ gpio2: gpio@020a0000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; - interrupts = <0 68 0x04 0 69 0x04>; + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, + <0 69 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -329,7 +367,8 @@ gpio3: gpio@020a4000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; - interrupts = <0 70 0x04 0 71 0x04>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, + <0 71 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -339,7 +378,8 @@ gpio4: gpio@020a8000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; - interrupts = <0 72 0x04 0 73 0x04>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, + <0 73 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -349,7 +389,8 @@ gpio5: gpio@020ac000 { compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; - interrupts = <0 74 0x04 0 75 0x04>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, + <0 75 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -357,21 +398,23 @@ }; kpp: kpp@020b8000 { + compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; - interrupts = <0 82 0x04>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; }; wdog1: wdog@020bc000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; - interrupts = <0 80 0x04>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_DUMMY>; }; wdog2: wdog@020c0000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; - interrupts = <0 81 0x04>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_DUMMY>; status = "disabled"; }; @@ -379,7 +422,8 @@ clks: ccm@020c4000 { compatible = "fsl,imx6sl-ccm"; reg = <0x020c4000 0x4000>; - interrupts = <0 87 0x04 0 88 0x04>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; }; @@ -388,7 +432,9 @@ "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; - interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, + <0 54 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; regulator-1p1@110 { compatible = "fsl,anatop-regulator"; @@ -434,7 +480,7 @@ reg_arm: regulator-vddcore@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "cpu"; + regulator-name = "vddarm"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; regulator-always-on; @@ -487,15 +533,17 @@ usbphy1: usbphy@020c9000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; - interrupts = <0 44 0x04>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY1>; + fsl,anatop = <&anatop>; }; usbphy2: usbphy@020ca000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; - interrupts = <0 45 0x04>; + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY2>; + fsl,anatop = <&anatop>; }; snvs@020cc000 { @@ -507,31 +555,33 @@ snvs-rtc-lp@34 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; reg = <0x34 0x58>; - interrupts = <0 19 0x04 0 20 0x04>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>; }; }; epit1: epit@020d0000 { reg = <0x020d0000 0x4000>; - interrupts = <0 56 0x04>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; }; epit2: epit@020d4000 { reg = <0x020d4000 0x4000>; - interrupts = <0 57 0x04>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; src: src@020d8000 { compatible = "fsl,imx6sl-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; - interrupts = <0 91 0x04 0 96 0x04>; + interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, + <0 96 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; gpc: gpc@020dc000 { compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; - interrupts = <0 89 0x04>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; }; gpr: iomuxc-gpr@020e0000 { @@ -543,235 +593,22 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6sl-iomuxc"; reg = <0x020e0000 0x4000>; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 - MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 - MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 - >; - }; - }; - - fec { - pinctrl_fec_1: fecgrp-1 { - fsl,pins = < - MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 - MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 - MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 - MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 - MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - >; - }; - }; - - usbotg1 { - pinctrl_usbotg1_1: usbotg1grp-1 { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_2: usbotg1grp-2 { - fsl,pins = < - MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_3: usbotg1grp-3 { - fsl,pins = < - MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_4: usbotg1grp-4 { - fsl,pins = < - MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_5: usbotg1grp-5 { - fsl,pins = < - MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059 - >; - }; - }; - - usbotg2 { - pinctrl_usbotg2_1: usbotg2grp-1 { - fsl,pins = < - MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059 - >; - }; - - pinctrl_usbotg2_2: usbotg2grp-2 { - fsl,pins = < - MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059 - >; - }; - - pinctrl_usbotg2_3: usbotg2grp-3 { - fsl,pins = < - MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059 - >; - }; - - pinctrl_usbotg2_4: usbotg2grp-4 { - fsl,pins = < - MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059 - >; - }; - }; - - usdhc1 { - pinctrl_usdhc1_1: usdhc1grp-1 { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 - >; - }; - - - }; - - usdhc2 { - pinctrl_usdhc2_1: usdhc2grp-1 { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - }; - - usdhc3 { - pinctrl_usdhc3_1: usdhc3grp-1 { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - }; }; csi: csi@020e4000 { reg = <0x020e4000 0x4000>; - interrupts = <0 7 0x04>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; spdc: spdc@020e8000 { reg = <0x020e8000 0x4000>; - interrupts = <0 6 0x04>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; }; sdma: sdma@020ec000 { compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; - interrupts = <0 2 0x04>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SDMA>, <&clks IMX6SL_CLK_SDMA>; clock-names = "ipg", "ahb"; @@ -782,22 +619,22 @@ pxp: pxp@020f0000 { reg = <0x020f0000 0x4000>; - interrupts = <0 98 0x04>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; }; epdc: epdc@020f4000 { reg = <0x020f4000 0x4000>; - interrupts = <0 97 0x04>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; lcdif: lcdif@020f8000 { reg = <0x020f8000 0x4000>; - interrupts = <0 39 0x04>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; }; dcp: dcp@020fc000 { reg = <0x020fc000 0x4000>; - interrupts = <0 99 0x04>; + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -811,7 +648,7 @@ usbotg1: usb@02184000 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; - interrupts = <0 43 0x04>; + interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; @@ -821,7 +658,7 @@ usbotg2: usb@02184200 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; - interrupts = <0 42 0x04>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; @@ -831,7 +668,7 @@ usbh: usb@02184400 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; - interrupts = <0 40 0x04>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; @@ -847,7 +684,7 @@ fec: ethernet@02188000 { compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; reg = <0x02188000 0x4000>; - interrupts = <0 114 0x04>; + interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_ENET_REF>, <&clks IMX6SL_CLK_ENET_REF>; clock-names = "ipg", "ahb"; @@ -857,7 +694,7 @@ usdhc1: usdhc@02190000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; - interrupts = <0 22 0x04>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USDHC1>, <&clks IMX6SL_CLK_USDHC1>, <&clks IMX6SL_CLK_USDHC1>; @@ -869,7 +706,7 @@ usdhc2: usdhc@02194000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; - interrupts = <0 23 0x04>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USDHC2>, <&clks IMX6SL_CLK_USDHC2>, <&clks IMX6SL_CLK_USDHC2>; @@ -881,7 +718,7 @@ usdhc3: usdhc@02198000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; - interrupts = <0 24 0x04>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USDHC3>, <&clks IMX6SL_CLK_USDHC3>, <&clks IMX6SL_CLK_USDHC3>; @@ -893,7 +730,7 @@ usdhc4: usdhc@0219c000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; - interrupts = <0 25 0x04>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USDHC4>, <&clks IMX6SL_CLK_USDHC4>, <&clks IMX6SL_CLK_USDHC4>; @@ -907,7 +744,7 @@ #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; reg = <0x021a0000 0x4000>; - interrupts = <0 36 0x04>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_I2C1>; status = "disabled"; }; @@ -917,7 +754,7 @@ #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; reg = <0x021a4000 0x4000>; - interrupts = <0 37 0x04>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_I2C2>; status = "disabled"; }; @@ -927,7 +764,7 @@ #size-cells = <0>; compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; reg = <0x021a8000 0x4000>; - interrupts = <0 38 0x04>; + interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_I2C3>; status = "disabled"; }; @@ -939,12 +776,12 @@ rngb: rngb@021b4000 { reg = <0x021b4000 0x4000>; - interrupts = <0 5 0x04>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; }; weim: weim@021b8000 { reg = <0x021b8000 0x4000>; - interrupts = <0 14 0x04>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; }; ocotp: ocotp@021bc000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/imx6sl-evk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/imx6sl-evk.dts --- linux-3.14.1/arch/arm/boot/dts/imx6sl-evk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/imx6sl-evk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -8,6 +8,8 @@ /dts-v1/; +#include +#include #include "imx6sl.dtsi" / { @@ -18,11 +20,26 @@ reg = <0x80000000 0x40000000>; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user { + label = "debug"; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_usb_otg1_vbus: usb_otg1_vbus { + reg_usb_otg1_vbus: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "usb_otg1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -30,22 +47,63 @@ enable-active-high; }; - reg_usb_otg2_vbus: usb_otg2_vbus { + reg_usb_otg2_vbus: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "usb_otg2_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio4 2 0>; enable-active-high; }; + + reg_aud3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; }; &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 11 0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; + pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; flash: m25p80@0 { @@ -59,16 +117,144 @@ &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec_1>; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx6sl-evk { pinctrl_hog: hoggrp { fsl,pins = < MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 @@ -78,21 +264,230 @@ MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 + MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 + MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 + MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 + MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 + MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 + MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 + MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 + MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 + MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 + MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 + MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 + MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 + MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 + MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 + MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 + MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 >; }; }; }; +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ + MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ + MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ + MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ + MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ + MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ + MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ + MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ + >; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_1>; + pinctrl-0 = <&pinctrl_usbotg1>; disable-over-current; status = "okay"; }; @@ -106,9 +501,9 @@ &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1_1>; - pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; cd-gpios = <&gpio4 7 0>; wp-gpios = <&gpio4 6 0>; @@ -117,9 +512,9 @@ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2_1>; - pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; cd-gpios = <&gpio5 0 0>; wp-gpios = <&gpio4 29 0>; status = "okay"; @@ -127,9 +522,9 @@ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3_1>; - pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio3 22 0>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/integratorap.dts linux-3.15-rc1.orig/arch/arm/boot/dts/integratorap.dts --- linux-3.14.1/arch/arm/boot/dts/integratorap.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/integratorap.dts 2014-04-13 23:18:35.000000000 +0200 @@ -18,6 +18,28 @@ bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; }; + /* 24 MHz chrystal on the core module */ + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* The UART clock is 14.74 MHz divided by an ICS525 */ + uartclk: uartclk@14.74M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <14745600>; + }; + syscon { compatible = "arm,integrator-ap-syscon"; reg = <0x11000000 0x100>; @@ -28,14 +50,17 @@ timer0: timer@13000000 { compatible = "arm,integrator-timer"; + clocks = <&xtal24mhz>; }; timer1: timer@13000100 { compatible = "arm,integrator-timer"; + clocks = <&xtal24mhz>; }; timer2: timer@13000200 { compatible = "arm,integrator-timer"; + clocks = <&xtal24mhz>; }; pic: pic@14000000 { @@ -92,26 +117,36 @@ rtc: rtc@15000000 { compatible = "arm,pl030", "arm,primecell"; arm,primecell-periphid = <0x00041030>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; uart0: uart@16000000 { compatible = "arm,pl010", "arm,primecell"; arm,primecell-periphid = <0x00041010>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; uart1: uart@17000000 { compatible = "arm,pl010", "arm,primecell"; arm,primecell-periphid = <0x00041010>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; kmi0: kmi@18000000 { compatible = "arm,pl050", "arm,primecell"; arm,primecell-periphid = <0x00041050>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; }; kmi1: kmi@19000000 { compatible = "arm,pl050", "arm,primecell"; arm,primecell-periphid = <0x00041050>; + clocks = <&xtal24mhz>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/integratorcp.dts linux-3.15-rc1.orig/arch/arm/boot/dts/integratorcp.dts --- linux-3.14.1/arch/arm/boot/dts/integratorcp.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/integratorcp.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,25 +13,107 @@ bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; }; + /* + * The Integrator/CP overall clocking architecture can be found in + * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which + * appear to illustrate the layout used in most configurations. + */ + + /* The codec chrystal operates at 24.576 MHz */ + xtal_codec: xtal24.576@24.576M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + /* The chrystal is divided by 2 by the codec for the AACI bit clock */ + aaci_bitclk: aaci_bitclk@12.288M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&xtal_codec>; + }; + + /* This is a 25MHz chrystal on the base board */ + xtal25mhz: xtal25mhz@25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ + uartclk: uartclk@14.74M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <14745600>; + }; + + /* Actually sysclk I think */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + core-module@10000000 { + /* 24 MHz chrystal on the core module */ + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + /* + * External oscillator on the core module, usually used + * to drive video circuitry. Driven from the 24MHz clock. + */ + auxosc: cm_aux_osc@25M { + #clock-cells = <0>; + compatible = "arm,integrator-cm-auxosc"; + clocks = <&xtal24mhz>; + }; + + /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ + kmiclk: kmiclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <3>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* The timer clock is the 24 MHz oscillator divided to 1MHz */ + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + }; + syscon { compatible = "arm,integrator-cp-syscon"; reg = <0xcb000000 0x100>; }; timer0: timer@13000000 { - /* TIMER0 runs @ 25MHz */ + /* TIMER0 runs directly on the 25MHz chrystal */ compatible = "arm,integrator-cp-timer"; - status = "disabled"; + clocks = <&xtal25mhz>; }; timer1: timer@13000100 { /* TIMER1 runs @ 1MHz */ compatible = "arm,integrator-cp-timer"; + clocks = <&timclk>; }; timer2: timer@13000200 { /* TIMER2 runs @ 1MHz */ compatible = "arm,integrator-cp-timer"; + clocks = <&timclk>; }; pic: pic@14000000 { @@ -74,22 +156,32 @@ */ rtc@15000000 { compatible = "arm,pl031", "arm,primecell"; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; uart@16000000 { compatible = "arm,pl011", "arm,primecell"; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; uart@17000000 { compatible = "arm,pl011", "arm,primecell"; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; kmi@18000000 { compatible = "arm,pl050", "arm,primecell"; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; }; kmi@19000000 { compatible = "arm,pl050", "arm,primecell"; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; }; /* @@ -100,18 +192,24 @@ reg = <0x1c000000 0x1000>; interrupts = <23 24>; max-frequency = <515633>; + clocks = <&uartclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; }; aaci@1d000000 { compatible = "arm,pl041", "arm,primecell"; reg = <0x1d000000 0x1000>; interrupts = <25>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; clcd@c0000000 { compatible = "arm,pl110", "arm,primecell"; reg = <0xC0000000 0x1000>; interrupts = <22>; + clocks = <&auxosc>, <&pclk>; + clock-names = "clcd", "apb_pclk"; }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2e-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/k2e-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/k2e-clocks.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2e-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,78 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Edison SoC specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>; + reg-names = "control", "multiplier"; + fixed-postdiv = <2>; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "pa-pll-clk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkusb1: clkusb1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "usb"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkhyperlink0: clkhyperlink0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkpcie1: clkpcie1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie"; + reg = <0x0235006c 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkxge: clkxge { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2e.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/k2e.dtsi --- linux-3.14.1/arch/arm/boot/dts/k2e.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2e.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,80 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Edison soc device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + soc { + /include/ "k2e-clocks.dtsi" + + usb: usb@2680000 { + interrupts = ; + dwc3@2690000 { + interrupts = ; + }; + }; + + usb1_phy: usb_phy@2620750 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620750 24>; + status = "disabled"; + }; + + usb1: usb@25000000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x25000000 0x10000>; + clocks = <&clkusb1>; + clock-names = "usb"; + interrupts = ; + ranges; + status = "disabled"; + + dwc3@25010000 { + compatible = "synopsys,dwc3"; + reg = <0x25010000 0x70000>; + interrupts = ; + usb-phy = <&usb1_phy>, <&usb1_phy>; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2e-evm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/k2e-evm.dts --- linux-3.14.1/arch/arm/boot/dts/k2e-evm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2e-evm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,60 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Edison EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "k2e.dtsi" + +/ { + compatible = "ti,k2e-evm","ti,keystone"; + model = "Texas Instruments Keystone 2 Edison EVM"; + + soc { + + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-pass"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2hk-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/k2hk-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/k2hk-clocks.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2hk-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,426 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking SoC clock nodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkarm>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>; + reg-names = "control", "multiplier"; + fixed-postdiv = <2>; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "pa-pll-clk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + ddr3bpllclk: ddr3bpllclk@2620368 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3b>; + clock-output-names = "ddr-3b-pll-clk"; + reg = <0x02620368 4>; + reg-names = "control"; + }; + + clktsip: clktsip { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "tsip"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clksrio: clksrio { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1rstiso13>; + clock-output-names = "srio"; + reg = <0x0235002c 0xb00>, <0x02350010 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkhyperlink0: clkhyperlink0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkgem1: clkgem1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clkgem4: clkgem4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem4"; + reg = <0x0235004c 0xb00>, <0x02350030 0x400>; + reg-names = "control", "domain"; + domain-id = <12>; + }; + + clkgem5: clkgem5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem5"; + reg = <0x02350050 0xb00>, <0x02350034 0x400>; + reg-names = "control", "domain"; + domain-id = <13>; + }; + + clkgem6: clkgem6 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem6"; + reg = <0x02350054 0xb00>, <0x02350038 0x400>; + reg-names = "control", "domain"; + domain-id = <14>; + }; + + clkgem7: clkgem7 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem7"; + reg = <0x02350058 0xb00>, <0x0235003c 0x400>; + reg-names = "control", "domain"; + domain-id = <15>; + }; + + clkddr31: clkddr31 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "ddr3-1"; + reg = <0x02350060 0xb00>, <0x02350040 0x400>; + reg-names = "control", "domain"; + domain-id = <16>; + }; + + clktac: clktac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac01: clkrac01 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-01"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac23: clkrac23 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-23"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc1: clkfftc1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x02350074 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc2: clkfftc2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-2"; + reg = <0x02350078 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc3: clkfftc3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-3"; + reg = <0x0235007c 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc4: clkfftc4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-4"; + reg = <0x02350080 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc5: clkfftc5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-5"; + reg = <0x02350084 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkaif: clkaif { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "aif"; + reg = <0x02350088 0xb00>, <0x02350054 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350090 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d2: clktcp3d2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-2"; + reg = <0x02350094 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clktcp3d3: clktcp3d3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-3"; + reg = <0x02350098 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp4: clkvcp4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-4"; + reg = <0x023500ac 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp5: clkvcp5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-5"; + reg = <0x023500b0 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp6: clkvcp6 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-6"; + reg = <0x023500b4 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp7: clkvcp7 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-7"; + reg = <0x023500b8 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkbcp: clkbcp { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdxb: clkdxb { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dxb"; + reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkhyperlink1: clkhyperlink1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-1"; + reg = <0x023500c4 0xb00>, <0x02350070 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkxge: clkxge { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2hk.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/k2hk.dtsi --- linux-3.14.1/arch/arm/boot/dts/k2hk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2hk.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,46 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking soc specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + soc { + /include/ "k2hk-clocks.dtsi" + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2hk-evm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/k2hk-evm.dts --- linux-3.14.1/arch/arm/boot/dts/k2hk-evm.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2hk-evm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright 2013 Texas Instruments, Inc. + * Copyright 2013-2014 Texas Instruments, Inc. * * Keystone 2 Kepler/Hawking EVM device tree * @@ -10,12 +10,14 @@ /dts-v1/; #include "keystone.dtsi" +#include "k2hk.dtsi" / { - compatible = "ti,keystone-evm"; + compatible = "ti,k2hk-evm","ti,keystone"; + model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; soc { - clock { + clocks { refclksys: refclksys { #clock-cells = <0>; compatible = "fixed-clock"; @@ -52,6 +54,29 @@ }; }; }; + + leds { + compatible = "gpio-leds"; + debug1_1 { + label = "keystone:green:debug1"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ + }; + + debug1_2 { + label = "keystone:red:debug1"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ + }; + + debug2 { + label = "keystone:blue:debug2"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ + }; + + debug3 { + label = "keystone:blue:debug3"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ + }; + }; }; &usb_phy { @@ -61,3 +86,55 @@ &usb { status = "okay"; }; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1fe80000>; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2l-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/k2l-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/k2l-clocks.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2l-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,267 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 lamarr SoC clock nodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>; + reg-names = "control", "multiplier"; + fixed-postdiv = <2>; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "pa-pll-clk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkdfeiqnsys: clkdfeiqnsys { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "dfe"; + reg-names = "control", "domain"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + domain-id = <0>; + }; + + clkpcie1: clkpcie1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie"; + reg = <0x0235002c 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkgem1: clkgem1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clktac: clktac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac: clkrac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkdfepd0: clkdfepd0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd0"; + reg = <0x0235006c 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkosr: clkosr { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "osr"; + reg = <0x02350088 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350094 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkbcp: clkbcp { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdfepd1: clkdfepd1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd1"; + reg = <0x023500c0 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkfftc1: clkfftc1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkiqnail: clkiqnail { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "iqn-ail"; + reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; + + clkuart2: clkuart2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart2"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart3: clkuart3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart3"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2l.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/k2l.dtsi --- linux-3.14.1/arch/arm/boot/dts/k2l.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2l.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Lamarr SoC specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + }; + + soc { + + /include/ "k2l-clocks.dtsi" + + uart2: serial@02348400 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348400 0x100>; + clocks = <&clkuart2>; + interrupts = ; + }; + + uart3: serial@02348800 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348800 0x100>; + clocks = <&clkuart3>; + interrupts = ; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/k2l-evm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/k2l-evm.dts --- linux-3.14.1/arch/arm/boot/dts/k2l-evm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/k2l-evm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,37 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Lamarr EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "k2l.dtsi" + +/ { + compatible = "ti,k2l-evm","ti,keystone"; + model = "Texas Instruments Keystone 2 Lamarr EVM"; + + soc { + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/keystone-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/keystone-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/keystone-clocks.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/keystone-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -13,51 +13,6 @@ #size-cells = <1>; ranges; - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>; - reg-names = "control", "multiplier"; - fixed-postdiv = <2>; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "pa-pll-clk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - ddr3bpllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3b>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - }; - - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkarm>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - mainmuxclk: mainmuxclk@2310108 { #clock-cells = <0>; compatible = "ti,keystone,pll-mux-clock"; @@ -244,7 +199,7 @@ clock-output-names = "debugss-trc"; reg = <0x02350014 0xb00>, <0x02350000 0x400>; reg-names = "control", "domain"; - domain-id = <0>; + domain-id = <1>; }; clktetbtrc: clktetbtrc { @@ -297,26 +252,6 @@ domain-id = <3>; }; - clksrio: clksrio { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - clksr: clksr { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; @@ -327,16 +262,6 @@ domain-id = <6>; }; - clkmsmcsram: clkmsmcsram { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "msmcsram"; - reg = <0x02350038 0xb00>, <0x0235001c 0x400>; - reg-names = "control", "domain"; - domain-id = <7>; - }; - clkgem0: clkgem0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; @@ -347,76 +272,6 @@ domain-id = <8>; }; - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - clkddr30: clkddr30 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; @@ -427,276 +282,6 @@ domain-id = <16>; }; - clkddr31: clkddr31 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clktac01 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clktac23 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - clkwdtimer0: clkwdtimer0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; @@ -735,6 +320,16 @@ reg = <0x02350000 0xb00>, <0x02350000 0x400>; reg-names = "control", "domain"; domain-id = <0>; + }; + + clktimer15: clktimer15 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer15"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; }; clkuart0: clkuart0 { diff -Nur linux-3.14.1/arch/arm/boot/dts/keystone.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/keystone.dtsi --- linux-3.14.1/arch/arm/boot/dts/keystone.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/keystone.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -7,6 +7,7 @@ */ #include +#include #include "skeleton.dtsi" @@ -24,37 +25,6 @@ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - gic: interrupt-controller { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -208,5 +178,75 @@ usb-phy = <&usb_phy>, <&usb_phy>; }; }; + + wdt: wdt@022f0080 { + compatible = "ti,keystone-wdt","ti,davinci-wdt"; + reg = <0x022f0080 0x80>; + clocks = <&clkwdtimer0>; + }; + + clock_event: timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = ; + clocks = <&clktimer15>; + }; + + gpio0: gpio@260bf00 { + compatible = "ti,keystone-gpio"; + reg = <0x0260bf00 0x100>; + gpio-controller; + #gpio-cells = <2>; + /* HW Interrupts mapped to GPIO pins */ + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clkgpio>; + clock-names = "gpio"; + ti,ngpio = <32>; + ti,davinci-gpio-unbanked = <32>; + }; + + aemif: aemif@21000A00 { + compatible = "ti,keystone-aemif", "ti,davinci-aemif"; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&clkaemif>; + clock-names = "aemif"; + clock-ranges; + + reg = <0x21000A00 0x00000100>; + ranges = <0 0 0x30000000 0x10000000 + 1 0 0x21000A00 0x00000100>; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-b3.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-b3.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-b3.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-b3.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,204 @@ +/* + * Device Tree file for Excito Bubba B3 + * + * Copyright (C) 2013, Andrew Lunn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Note: This requires a new'ish version of u-boot, which disables the + * L2 cache. If your B3 silently fails to boot, u-boot is probably too + * old. Either upgrade, or consider the following email: + * + * http://lists.debian.org/debian-arm/2012/08/msg00128.html + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Excito B3"; + compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + memory { /* 512 MB */ + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + mbus { + pcie-controller { + status = "okay"; + + /* Wifi model has Atheros chipset on pcie port */ + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pmx_button_power: pmx-button-power { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_green: pmx-led-green { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_red: pmx-led-red { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_led_blue: pmx-led-blue { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_beeper: pmx-beeper { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + }; + + spi@10600 { + status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + + m25p16@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p16"; + reg = <0>; + spi-max-frequency = <40000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0xc0000>; + label = "u-boot"; + }; + + partition@c0000 { + reg = <0xc0000 0x20000>; + label = "u-boot env"; + }; + + partition@e0000 { + reg = <0xe0000 0x120000>; + label = "data"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + /* + * There is something on the bus at address 0x64. + * Not yet identified what it is, maybe the eeprom + * for the Atheros WiFi chip? + */ + }; + + + serial@12000 { + /* Internal on test pins, 3.3v TTL + * UART0_RX = Testpoint 65 + * UART0_TX = Testpoint 66 + * See the Excito Wiki for more details. + */ + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "okay"; + }; + + sata@80000 { + /* One internal, the second as eSATA */ + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-leds { + /* + * There is one LED "port" on the front and the colours + * mix together giving some interesting combinations. + */ + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_green &pmx_led_red + &pmx_led_blue >; + pinctrl-names = "default"; + + programming_led { + label = "bubba3:green:programming"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + error_led { + label = "bubba3:red:error"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + active_led { + label = "bubba3:blue:active"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_button_power>; + pinctrl-names = "default"; + + power-button { + /* On the back */ + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; + + beeper: beeper { + /* 4KHz Piezoelectric buzzer */ + compatible = "gpio-beeper"; + pinctrl-0 = <&pmx_beeper>; + pinctrl-names = "default"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; + + ethphy1: ethernet-phy@24 { + device_type = "ethernet-phy"; + reg = <24>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds109.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds109.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds109.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds109.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,41 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS109, DS110, DS110jv20"; + compatible = "synology,ds109", "synology,ds110jv20", + "synology,ds110", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds110jv10.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds110jv10.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds110jv10.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds110jv10.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,41 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS110j v10 and v30"; + compatible = "synology,ds110jv10", "synology,ds110jv30", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds111.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds111.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds111.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds111.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS111"; + compatible = "synology,ds111", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-21-1 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds112.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds112.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds112.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds112.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS111"; + compatible = "synology,ds111", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-21-2 { + status = "okay"; + }; + + regulators-hdd-30 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds209.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds209.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds209.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds209.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS209"; + compatible = "synology,ds209", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; + + regulators-hdd-31 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds210.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds210.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds210.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds210.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,46 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS210 v10, v20, v30, DS211j"; + compatible = "synology,ds210jv10", "synology,ds210jv20", + "synology,ds210jv30", "synology,ds211j", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; + + regulators-hdd-31 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds212.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds212.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds212.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds212.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,47 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; + compatible = "synology,ds212", "synology,ds212pv10", + "synology,ds212pv10", "synology,ds212pv20", + "synology,ds213airv10", "synology,ds213v10", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds212j.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds212j.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds212j.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds212j.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,41 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS212j v10, v20"; + compatible = "synology,ds212jv10", "synology,ds212jv20", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-21-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds409.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds409.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds409.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds409.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS409, DS410j"; + compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + gpio-leds-alarm-12 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&rs5c372 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds409slim.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds409slim.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds409slim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds409slim.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,40 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology 409slim"; + compatible = "synology,ds409slim", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-32-35 { + status = "okay"; + }; + + gpio-leds-hdd-20 { + status = "okay"; + }; +}; + +&rs5c372 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds411.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds411.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds411.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds411.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,52 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411, DS413jv10"; + compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + regulators-hdd-34 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds411j.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds411j.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds411j.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds411j.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411j"; + compatible = "synology,ds411j", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; + + gpio-leds-alarm-12 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ds411slim.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds411slim.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ds411slim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ds411slim.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology DS411slim"; + compatible = "synology,ds411slim", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-1 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood.dtsi --- linux-3.14.1/arch/arm/boot/dts/kirkwood.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -24,6 +24,7 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; + i2c0 = &i2c0; }; mbus { @@ -111,7 +112,7 @@ clocks = <&gate_clk 7>; }; - i2c@11000 { + i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; @@ -145,6 +146,11 @@ reg = <0x20000 0x80>, <0x1500 0x20>; }; + system-controller@20000 { + compatible = "marvell,orion-system-controller"; + reg = <0x20000 0x120>; + }; + bridge_intc: bridge-interrupt-ctrl@20110 { compatible = "marvell,orion-bridge-intc"; interrupt-controller; @@ -161,6 +167,11 @@ #clock-cells = <1>; }; + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; + intc: main-interrupt-ctrl@20200 { compatible = "marvell,orion-intc"; interrupt-controller; @@ -178,7 +189,7 @@ wdt: watchdog-timer@20300 { compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>; + reg = <0x20300 0x28>, <0x20108 0x4>; interrupt-parent = <&bridge_intc>; interrupts = <3>; clocks = <&gate_clk 7>; @@ -300,5 +311,14 @@ #phy-cells = <0>; status = "ok"; }; + + audio0: audio-controller@a0000 { + compatible = "marvell,kirkwood-audio"; + reg = <0xa0000 0x2210>; + interrupts = <24>; + clocks = <&gate_clk 9>; + clock-names = "internal"; + status = "disabled"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts 2014-04-13 23:18:35.000000000 +0200 @@ -122,4 +122,66 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0>; + dsa,mii-bus = <ðphy0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@ff { + reg = <0xff>; /* No phy attached */ + speed = <1000>; + duplex = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6192.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6192.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6192.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6192.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,112 @@ +/* + * Marvell RD88F6192 Board descrition + * + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the three + * variants of the Marvell Kirkwood Development Board. + */ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "Marvell RD88F6192 reference design"; + compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp10"; + marvell,function = "gpo"; + }; + }; + + serial@12000 { + status = "okay"; + + }; + + spi@10600 { + status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + }; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + usb_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "USB VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; \ Kein Zeilenumbruch am Dateiende. diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,26 @@ +/* + * Marvell RD88F6181 A0 Board descrition + * + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions for the board with the A0 variant of + * the SoC. The ethernet switch does not have a "wan" port. + */ + +/dts-v1/; +#include "kirkwood-rd88f6281.dtsi" + +/ { + model = "Marvell RD88f6281 Reference design, with A0 SoC"; + compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + + dsa@0 { + switch@0 { + reg = <10 0>; /* MDIO address 10, switch 0 in tree */ + }; + }; +}; \ Kein Zeilenumbruch am Dateiende. diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,31 @@ +/* + * Marvell RD88F6181 A1 Board descrition + * + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions for the board with the A1 variant of + * the SoC. The ethernet switch has a "wan" port. + */ + +/dts-v1/; + +#include "kirkwood-rd88f6281.dtsi" + +/ { + model = "Marvell RD88f6281 Reference design, with A1 SoC"; + compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + + dsa@0 { + switch@0 { + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + port@4 { + reg = <4>; + label = "wan"; + }; + }; + }; +}; \ Kein Zeilenumbruch am Dateiende. diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi --- linux-3.14.1/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,152 @@ +/* + * Marvell RD88F6181 Common Board descrition + * + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the two + * variants of the Marvell Kirkwood Development Board. + */ + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-0 = <&pmx_sdio_cd>; + pinctrl-names = "default"; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + /* No WP GPIO */ + }; + }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0>; + dsa,mii-bus = <ðphy1>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x200000>; + }; + + partition@300000 { + label = "data"; + reg = <0x0300000 0x500000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@ff { + reg = <0xff>; /* No PHY attached */ + speed = <1000>; + duple = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-rs212.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rs212.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-rs212.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rs212.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,48 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS212"; + compatible = "synology,rs212", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-3 { + status = "okay"; + }; + + gpio-leds-hdd-38 { + status = "okay"; + }; + + regulators-hdd-30-2 { + status = "okay"; + }; +}; + +&s35390a { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-rs409.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rs409.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-rs409.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rs409.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS409"; + compatible = "synology,rs409", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-150-15-18 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&rs5c372 { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-rs411.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rs411.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-rs411.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-rs411.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,44 @@ +/* + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-synology.dtsi" + +/ { + model = "Synology RS411 RS812"; + compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + gpio-fan-100-15-35-3 { + status = "okay"; + }; + + gpio-leds-hdd-36 { + status = "okay"; + }; +}; + +ð1 { + status = "okay"; +}; + +&s35390a { + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-synology.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-synology.dtsi --- linux-3.14.1/arch/arm/boot/dts/kirkwood-synology.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-synology.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,871 @@ +/* + * Nodes for Marvell 628x Synology devices + * + * Andrew Lunn + * Ben Peddell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/ { + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie2: pcie@2,0 { + status = "disabled"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pmx_alarmled_12: pmx-alarmled-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_15: pmx-fanctrl-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_16: pmx-fanctrl-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_17: pmx-fanctrl-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_18: pmx-fanalarm-18 { + marvell,pins = "mpp18"; + marvell,function = "gpo"; + }; + + pmx_hddled_20: pmx-hddled-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_hddled_21: pmx-hddled-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_hddled_22: pmx-hddled-22 { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_hddled_23: pmx-hddled-23 { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + pmx_hddled_24: pmx-hddled-24 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_hddled_25: pmx-hddled-25 { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + pmx_hddled_26: pmx-hddled-26 { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + pmx_hddled_27: pmx-hddled-27 { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + pmx_hddled_28: pmx-hddled-28 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + + pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_32: pmx-fanctrl-32 { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + pmx_fanctrl_33: pmx-fanctrl-33 { + marvell,pins = "mpp33"; + marvell,function = "gpo"; + }; + + pmx_fanctrl_34: pmx-fanctrl-34 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_35: pmx-fanalarm-35 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + pmx_hddled_36: pmx-hddled-36 { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_hddled_37: pmx-hddled-37 { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_hddled_38: pmx-hddled-38 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_hddled_39: pmx-hddled-39 { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_hddled_40: pmx-hddled-40 { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_hddled_41: pmx-hddled-41 { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_hddled_42: pmx-hddled-42 { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_hddled_43: pmx-hddled-43 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + pmx_hddled_44: pmx-hddled-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_hddled_45: pmx-hddled-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_44: pmx-fanalarm-44 { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_fanalarm_45: pmx-fanalarm-45 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + }; + + rtc@10300 { + status = "disabled"; + }; + + spi@10600 { + status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + reg = <0>; + spi-max-frequency = <20000000>; + mode = <0>; + + partition@00000000 { + reg = <0x00000000 0x00080000>; + label = "RedBoot"; + }; + + partition@00080000 { + reg = <0x00080000 0x00200000>; + label = "zImage"; + }; + + partition@00280000 { + reg = <0x00280000 0x00140000>; + label = "rd.gz"; + }; + + partition@003c0000 { + reg = <0x003c0000 0x00010000>; + label = "vendor"; + }; + + partition@003d0000 { + reg = <0x003d0000 0x00020000>; + label = "RedBoot config"; + }; + + partition@003f0000 { + reg = <0x003f0000 0x00010000>; + label = "FIS directory"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; + + rs5c372: rs5c372@32 { + status = "disabled"; + compatible = "ricoh,rs5c372"; + reg = <0x32>; + }; + + s35390a: s35390a@30 { + status = "disabled"; + compatible = "ssi,s35390a"; + reg = <0x30>; + }; + }; + + serial@12000 { + status = "okay"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + }; + + serial@12100 { + status = "okay"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-fan-150-32-35 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH + &gpio1 1 GPIO_ACTIVE_HIGH + &gpio1 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2200 1 + 2500 2 + 3000 4 + 3300 3 + 3700 5 + 3800 6 + 4200 7 >; + }; + + gpio-fan-150-15-18 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_18>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2200 1 + 2500 2 + 3000 4 + 3300 3 + 3700 5 + 3800 6 + 4200 7 >; + }; + + gpio-fan-100-32-35 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH + &gpio1 1 GPIO_ACTIVE_HIGH + &gpio1 2 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-18 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_18>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-35-1 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_35>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-fan-100-15-35-3 { + status = "disabled"; + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 + &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; + pinctrl-names = "default"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH + &gpio0 16 GPIO_ACTIVE_HIGH + &gpio0 17 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH + &gpio1 12 GPIO_ACTIVE_HIGH + &gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 2500 1 + 3100 2 + 3800 3 + 4600 4 + 4800 5 + 4900 6 + 5000 7 >; + }; + + gpio-leds-alarm-12 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_alarmled_12>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:alarm"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-20 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 + &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 + &pmx_hddled_26 &pmx_hddled_27>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + hdd3-green { + label = "synology:green:hdd3"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + hdd3-amber { + label = "synology:amber:hdd3"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + hdd4-green { + label = "synology:green:hdd4"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + + hdd4-amber { + label = "synology:amber:hdd4"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-21-1 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-21-2 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-36 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 + &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 + &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 + &pmx_hddled_45>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hdd3-green { + label = "synology:green:hdd3"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + hdd3-amber { + label = "synology:amber:hdd3"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + hdd4-green { + label = "synology:green:hdd4"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + hdd4-amber { + label = "synology:amber:hdd4"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + hdd5-green { + label = "synology:green:hdd5"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + + hdd5-amber { + label = "synology:amber:hdd5"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds-hdd-38 { + status = "disabled"; + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; + pinctrl-names = "default"; + + hdd1-green { + label = "synology:green:hdd1"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hdd1-amber { + label = "synology:amber:hdd1"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hdd2-green { + label = "synology:green:hdd2"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + + hdd2-amber { + label = "synology:amber:hdd2"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + }; + + regulators-hdd-29 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-1 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-2 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-30-4 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 + &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-31 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd2_pwr_31>; + pinctrl-names = "default"; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators-hdd-34 { + status = "disabled"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 + &pmx_hdd4_pwr_45>; + pinctrl-names = "default"; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd2power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "hdd3power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "hdd4power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <8>; + }; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + reg = <9>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "disabled"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-t5325.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-t5325.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-t5325.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-t5325.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,208 @@ +/* + * Device Tree file for HP t5325 Thin Client" + * + * Copyright (C) 2014 + * + * Thomas Petazzoni + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "HP t5325 Thin Client"; + compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-0 = <&pmx_i2s &pmx_sysrst>; + pinctrl-names = "default"; + + pmx_button_power: pmx-button_power { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_off: pmx-power-off { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_led: pmx-led { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + /* + * Redefined from kirkwood-6281.dtsi, because + * we don't use SPI CS on MPP0, but on MPP7. + */ + pmx_spi: pmx-spi { + marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; + marvell,function = "spi"; + }; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_i2s: pmx-i2s { + marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", + "mpp43"; + marvell,function = "audio"; + }; + }; + + spi@10600 { + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80"; + spi-max-frequency = <86000000>; + reg = <0>; + mode = <0>; + + partition@0 { + reg = <0x0 0x80000>; + label = "u-boot"; + }; + + partition@1 { + reg = <0x80000 0x40000>; + label = "SSD firmware"; + }; + + partition@2 { + reg = <0xc0000 0x10000>; + label = "u-boot env"; + }; + + partition@3 { + reg = <0xd0000 0x10000>; + label = "permanent u-boot env"; + }; + + partition@4 { + reg = <0xd0000 0x10000>; + label = "permanent u-boot env"; + }; + }; + }; + + i2c@11000 { + status = "okay"; + + alc5621: alc5621@1a { + compatible = "realtek,alc5621"; + reg = <0x1a>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + audio: audio-controller@a0000 { + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_sata_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB-SATA Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_power>; + pinctrl-names = "default"; + + button@1 { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ts419-6281.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ts419-6281.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ts419-6281.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ts419-6281.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,20 @@ +/* + * Device Tree file for QNAP TS41X with 6281 SoC + * + * Copyright (C) 2013, Andrew Lunn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-ts219.dtsi" +#include "kirkwood-ts419.dtsi" + +ðphy0 { reg = <8>; }; +ðphy1 { reg = <0>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ts419-6282.dts linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ts419-6282.dts --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ts419-6282.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ts419-6282.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,32 @@ +/* + * Device Tree file for QNAP TS41X with 6282 SoC + * + * Copyright (C) 2013, Andrew Lunn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-ts219.dtsi" +#include "kirkwood-ts419.dtsi" + +/ { + mbus { + pcie-controller { + status = "okay"; + + pcie@2,0 { + status = "okay"; + }; + }; + }; +}; + +ðphy0 { reg = <0>; }; +ðphy1 { reg = <1>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/kirkwood-ts419.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ts419.dtsi --- linux-3.14.1/arch/arm/boot/dts/kirkwood-ts419.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/kirkwood-ts419.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,75 @@ +/* + * Device Tree include file for QNAP TS41X + * + * Copyright (C) 2013, Andrew Lunn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/ { + model = "QNAP TS419 family"; + compatible = "qnap,ts419", "marvell,kirkwood"; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-names = "default"; + + pmx_USB_copy_button: pmx-USB-copy-button { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + /* + * JP1 indicates if an LCD module is installed + * on the serial port (0), or if the port is used + * as a console (1). + */ + pmx_jumper_jp1: pmx-jumper_jp1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + + button@1 { + label = "USB Copy"; + linux,code = ; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + button@2 { + label = "Reset"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + /* overwrite reg property in board file */ + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/Makefile linux-3.15-rc1.orig/arch/arm/boot/dts/Makefile --- linux-3.14.1/arch/arm/boot/dts/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb +# sam9261 +dtb-$(CONFIG_ARCH_AT91) += at91sam9261ek.dtb # sam9263 dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb @@ -29,6 +31,8 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb # sam9n12 dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb +# sam9rl +dtb-$(CONFIG_ARCH_AT91) += at91sam9rlek.dtb # sam9x5 dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb @@ -47,19 +51,15 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb -dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ - bcm28155-ap.dtb +dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ + bcm21664-garnet.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb +dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2-sony-nsz-gs7.dtb \ berlin2cd-google-chromecast.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb -dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ - dove-cubox.dtb \ - dove-d2plug.dtb \ - dove-d3plug.dtb \ - dove-dove-db.dtb dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ @@ -82,14 +82,30 @@ ecx-2000.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb -dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb -dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ +dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ + k2l-evm.dtb \ + k2e-evm.dtb +kirkwood := \ + kirkwood-b3.dtb \ + kirkwood-cloudbox.dtb \ kirkwood-db-88f6281.dtb \ kirkwood-db-88f6282.dtb \ kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ kirkwood-dreamplug.dtb \ + kirkwood-ds109.dtb \ + kirkwood-ds110jv10.dtb \ + kirkwood-ds111.dtb \ + kirkwood-ds209.dtb \ + kirkwood-ds210.dtb \ + kirkwood-ds212.dtb \ + kirkwood-ds212j.dtb \ + kirkwood-ds409.dtb \ + kirkwood-ds409slim.dtb \ + kirkwood-ds411.dtb \ + kirkwood-ds411j.dtb \ + kirkwood-ds411slim.dtb \ kirkwood-goflexnet.dtb \ kirkwood-guruplug-server-plus.dtb \ kirkwood-ib62x0.dtb \ @@ -112,54 +128,74 @@ kirkwood-nsa310a.dtb \ kirkwood-openblocks_a6.dtb \ kirkwood-openblocks_a7.dtb \ + kirkwood-rd88f6192.dtb \ + kirkwood-rd88f6281-a0.dtb \ + kirkwood-rd88f6281-a1.dtb \ + kirkwood-rs212.dtb \ + kirkwood-rs409.dtb \ + kirkwood-rs411.dtb \ kirkwood-sheevaplug.dtb \ kirkwood-sheevaplug-esata.dtb \ + kirkwood-t5325.dtb \ kirkwood-topkick.dtb \ kirkwood-ts219-6281.dtb \ - kirkwood-ts219-6282.dtb + kirkwood-ts219-6282.dtb \ + kirkwood-ts419-6281.dtb \ + kirkwood-ts419-6282.dtb +dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood) +dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood) +dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb -dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-apq8074-dragonboard.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ - armada-370-mirabox.dtb \ - armada-370-netgear-rn102.dtb \ - armada-370-netgear-rn104.dtb \ - armada-370-rd.dtb \ - armada-xp-axpwifiap.dtb \ - armada-xp-db.dtb \ - armada-xp-gp.dtb \ - armada-xp-netgear-rn2120.dtb \ - armada-xp-matrix.dtb \ - armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_ARCH_MXC) += \ + imx25-eukrea-mbimxsd25-baseboard.dtb \ imx25-karo-tx25.dtb \ imx25-pdk.dtb \ imx27-apf27.dtb \ imx27-apf27dev.dtb \ imx27-pdk.dtb \ - imx27-phytec-phycore-som.dtb \ imx27-phytec-phycore-rdk.dtb \ - imx27-phytec-phycard-s-som.dtb \ imx27-phytec-phycard-s-rdk.dtb \ imx31-bug.dtb \ + imx35-eukrea-mbimxsd35-baseboard.dtb \ + imx50-evk.dtb \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ imx51-babbage.dtb \ + imx51-eukrea-mbimxsd51-baseboard.dtb \ imx53-ard.dtb \ - imx53-evk.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ imx53-qsb.dtb \ + imx53-qsrb.dtb \ imx53-smd.dtb \ + imx53-tx53-x03x.dtb \ + imx53-tx53-x13x.dtb \ + imx53-voipac-bsb.dtb \ imx6dl-cubox-i.dtb \ + imx6dl-dfi-fs700-m60.dtb \ + imx6dl-gw51xx.dtb \ + imx6dl-gw52xx.dtb \ + imx6dl-gw53xx.dtb \ + imx6dl-gw54xx.dtb \ imx6dl-hummingboard.dtb \ + imx6dl-nitrogen6x.dtb \ imx6dl-sabreauto.dtb \ + imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ imx6dl-wandboard.dtb \ imx6q-arm2.dtb \ + imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ + imx6q-dfi-fs700-m60.dtb \ + imx6q-dmo-edmqmx6.dtb \ + imx6q-gk802.dtb \ + imx6q-gw51xx.dtb \ + imx6q-gw52xx.dtb \ + imx6q-gw53xx.dtb \ + imx6q-gw5400-a.dtb \ + imx6q-gw54xx.dtb \ + imx6q-nitrogen6x.dtb \ imx6q-phytec-pbab01.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ @@ -183,6 +219,9 @@ imx28-cfa10056.dtb \ imx28-cfa10057.dtb \ imx28-cfa10058.dtb \ + imx28-duckbill.dtb \ + imx28-eukrea-mbmx283lc.dtb \ + imx28-eukrea-mbmx287lc.dtb \ imx28-evk.dtb \ imx28-m28cu3.dtb \ imx28-m28evk.dtb \ @@ -199,6 +238,10 @@ omap2420-n810-wimax.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ + omap3-cm-t3517.dtb \ + omap3-sbc-t3517.dtb \ + omap3-cm-t3530.dtb \ + omap3-sbc-t3530.dtb \ omap3-cm-t3730.dtb \ omap3-sbc-t3730.dtb \ omap3-devkit8000.dtb \ @@ -209,12 +252,24 @@ omap3-n900.dtb \ omap3-n9.dtb \ omap3-n950.dtb \ + omap3-overo-alto35.dtb \ + omap3-overo-storm-alto35.dtb \ + omap3-overo-chestnut43.dtb \ + omap3-overo-storm-chestnut43.dtb \ + omap3-overo-gallop43.dtb \ + omap3-overo-storm-gallop43.dtb \ + omap3-overo-palo43.dtb \ + omap3-overo-storm-palo43.dtb \ + omap3-overo-summit.dtb \ + omap3-overo-storm-summit.dtb \ omap3-overo-tobi.dtb \ omap3-overo-storm-tobi.dtb \ omap3-gta04.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ + omap3-lilly-dbb056.dtb \ omap3-zoom3.dtb \ + omap4-duovero-parlor.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ omap4-panda-es.dtb \ @@ -228,12 +283,17 @@ am335x-boneblack.dtb \ am335x-nano.dtb \ am335x-base0033.dtb \ + am3517-craneboard.dtb \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ am43x-epos-evm.dtb \ + am437x-gp-evm.dtb \ dra7-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-apq8074-dragonboard.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ ste-hrefprev60-stuib.dtb \ ste-hrefprev60-tvk.dtb \ @@ -284,6 +344,9 @@ sun4i-a10-cubieboard.dtb \ sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ @@ -322,8 +385,31 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zed.dtb +dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-db.dtb \ + armada-370-mirabox.dtb \ + armada-370-netgear-rn102.dtb \ + armada-370-netgear-rn104.dtb \ + armada-370-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb +dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db.dtb \ + armada-385-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ + armada-xp-db.dtb \ + armada-xp-gp.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-matrix.dtb \ + armada-xp-openblocks-ax3-4.dtb +dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ + dove-cubox.dtb \ + dove-d2plug.dtb \ + dove-d3plug.dtb \ + dove-dove-db.dtb -targets += dtbs +targets += dtbs dtbs_install targets += $(dtb-y) endif @@ -333,3 +419,5 @@ $(Q)rm -f $(obj)/../*.dtb clean-files := *.dtb + +dtbs_install: $(addsuffix _dtbinst_, $(dtb-y)) diff -Nur linux-3.14.1/arch/arm/boot/dts/marco.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/marco.dtsi --- linux-3.14.1/arch/arm/boot/dts/marco.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/marco.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -58,9 +58,10 @@ #size-cells = <1>; ranges = <0xc2000000 0xc2000000 0x1000000>; - reset-controller@c2000000 { + rstc: reset-controller@c2000000 { compatible = "sirf,marco-rstc"; reg = <0xc2000000 0x10000>; + #reset-cells = <1>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap2420.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap2420.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap2420.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap2420.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -99,6 +99,7 @@ dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp2: mcbsp@48076000 { @@ -112,6 +113,7 @@ dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; + status = "disabled"; }; msdi1: mmc@4809c000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap2430.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap2430.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap2430.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap2430.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -29,6 +29,22 @@ pinctrl-single,function-mask = <0x3f>; }; + omap2_scm_general: tisyscon@49002270 { + compatible = "syscon"; + reg = <0x49002270 0x240>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x230 0x4>; + syscon = <&omap2_scm_general>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + gpio1: gpio@4900c000 { compatible = "ti,omap2-gpio"; reg = <0x4900c000 0x200>; @@ -113,6 +129,7 @@ dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp2: mcbsp@48076000 { @@ -128,6 +145,7 @@ dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp3: mcbsp@4808c000 { @@ -143,6 +161,7 @@ dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp4: mcbsp@4808e000 { @@ -158,6 +177,7 @@ dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp5: mcbsp@48096000 { @@ -173,6 +193,7 @@ dmas = <&sdma 21>, <&sdma 22>; dma-names = "tx", "rx"; + status = "disabled"; }; mmc1: mmc@4809c000 { @@ -183,6 +204,7 @@ ti,dual-volt; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap2.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap2.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap2.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap2.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -271,5 +271,36 @@ ti,hwmods = "timer12"; ti,timer-pwm; }; + + dss: dss@48050000 { + compatible = "ti,omap2-dss"; + reg = <0x48050000 0x400>; + status = "disabled"; + ti,hwmods = "dss_core"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@48050400 { + compatible = "ti,omap2-dispc"; + reg = <0x48050400 0x400>; + interrupts = <25>; + ti,hwmods = "dss_dispc"; + }; + + rfbi: encoder@48050800 { + compatible = "ti,omap2-rfbi"; + reg = <0x48050800 0x400>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + }; + + venc: encoder@48050c00 { + compatible = "ti,omap2-venc"; + reg = <0x48050c00 0x400>; + status = "disabled"; + ti,hwmods = "dss_venc"; + }; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3430es1-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3430es1-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3430es1-clocks.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3430es1-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -82,16 +82,16 @@ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; - ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 { + ssi_ssr_fck: ssi_ssr_fck_3430es1 { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; }; - ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 { + ssi_sst_fck: ssi_sst_fck_3430es1 { #clock-cells = <0>; compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck_3430es1>; + clocks = <&ssi_ssr_fck>; clock-mult = <1>; clock-div = <2>; }; @@ -120,7 +120,7 @@ clock-div = <1>; }; - ssi_ick_3430es1: ssi_ick_3430es1 { + ssi_ick: ssi_ick_3430es1 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&ssi_l4_ick>; @@ -152,7 +152,7 @@ clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 { + dss1_alwon_fck: dss1_alwon_fck_3430es1 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m4x2_ck>; @@ -161,7 +161,7 @@ ti,set-rate-parent; }; - dss_ick_3430es1: dss_ick_3430es1 { + dss_ick: dss_ick_3430es1 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&l4_ick>; @@ -184,7 +184,7 @@ dss_clkdm: dss_clkdm { compatible = "ti,clockdomain"; clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>; + <&dss1_alwon_fck>, <&dss_ick>; }; d2d_clkdm: d2d_clkdm { @@ -203,6 +203,6 @@ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>; + <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3430-sdp.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3430-sdp.dts --- linux-3.14.1/arch/arm/boot/dts/omap3430-sdp.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3430-sdp.dts 2014-04-13 23:18:35.000000000 +0200 @@ -34,6 +34,10 @@ &mmc1 { vmmc-supply = <&vmmc1>; vmmc_aux-supply = <&vsim>; + /* + * S6-3 must be in ON position for 8 bit mode to function + * Else, use 4 bit mode + */ bus-width = <8>; }; @@ -103,9 +107,8 @@ #address-cells = <1>; #size-cells = <1>; reg = <1 0 0x08000000>; + ti,nand-ecc-opt = "ham1"; nand-bus-width = <8>; - - ti,nand-ecc-opt = "sw"; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <36>; gpmc,cs-wr-off-ns = <36>; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -160,7 +160,7 @@ ti,bit-shift = <30>; }; - dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 { + dss1_alwon_fck: dss1_alwon_fck_3430es2 { #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clocks = <&dpll4_m4x2_ck>; @@ -169,7 +169,7 @@ ti,set-rate-parent; }; - dss_ick_3430es2: dss_ick_3430es2 { + dss_ick: dss_ick_3430es2 { #clock-cells = <0>; compatible = "ti,omap3-dss-interface-clock"; clocks = <&l4_ick>; @@ -216,7 +216,7 @@ dss_clkdm: dss_clkdm { compatible = "ti,clockdomain"; clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; + <&dss1_alwon_fck>, <&dss_ick>; }; core_l4_clkdm: core_l4_clkdm { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap36xx-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap36xx-clocks.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -70,6 +70,26 @@ }; }; +&dpll4_m2x2_mul_ck { + clock-mult = <1>; +}; + +&dpll4_m3x2_mul_ck { + clock-mult = <1>; +}; + +&dpll4_m4x2_mul_ck { + ti,clock-mult = <1>; +}; + +&dpll4_m5x2_mul_ck { + clock-mult = <1>; +}; + +&dpll4_m6x2_mul_ck { + clock-mult = <1>; +}; + &cm_clockdomains { dpll4_clkdm: dpll4_clkdm { compatible = "ti,clockdomain"; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap36xx.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap36xx.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -39,6 +39,26 @@ clock-frequency = <48000000>; }; + abb_mpu_iva: regulator-abb-mpu { + compatible = "ti,abb-v1"; + regulator-name = "abb_mpu_iva"; + #address-cell = <0>; + #size-cells = <0>; + reg = <0x483072f0 0x8>, <0x48306818 0x4>; + reg-names = "base-address", "int-address"; + ti,tranxdone-status-mask = <0x4000000>; + clocks = <&sys_ck>; + ti,settling-time = <30>; + ti,clock-cycles = <8>; + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1012500 0 0 0 0 0 + 1200000 0 0 0 0 0 + 1325000 0 0 0 0 0 + 1375000 1 0 0 0 0 + >; + }; + omap3_pmx_core2: pinmux@480025a0 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x480025a0 0x5c>; @@ -52,7 +72,13 @@ }; }; -/include/ "omap36xx-clocks.dtsi" +/* OMAP3630 needs dss_96m_fck for VENC */ +&venc { + clocks = <&dss_tv_fck>, <&dss_96m_fck>; + clock-names = "fck", "tv_dac_clk"; +}; + /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-clocks.dtsi" diff -Nur linux-3.14.1/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -25,16 +25,16 @@ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; - ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 { + ssi_ssr_fck: ssi_ssr_fck_3430es2 { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; }; - ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 { + ssi_sst_fck: ssi_sst_fck_3430es2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck_3430es2>; + clocks = <&ssi_ssr_fck>; clock-mult = <1>; clock-div = <2>; }; @@ -55,7 +55,7 @@ clock-div = <1>; }; - ssi_ick_3430es2: ssi_ick_3430es2 { + ssi_ick: ssi_ick_3430es2 { #clock-cells = <0>; compatible = "ti,omap3-ssi-interface-clock"; clocks = <&ssi_l4_ick>; @@ -193,6 +193,6 @@ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&ssi_ick_3430es2>; + <&ssi_ick>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-beagle.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-beagle.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-beagle.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-beagle.dts 2014-04-13 23:18:35.000000000 +0200 @@ -24,6 +24,11 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + aliases { + display0 = &dvi0; + display1 = &tv0; + }; + leds { compatible = "gpio-leds"; pmu_stat { @@ -80,6 +85,61 @@ }; }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ + + pinctrl-names = "default"; + pinctrl-0 = <&tfp410_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector@1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; }; &omap3_pmx_wkup { @@ -113,6 +173,45 @@ 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; + + tfp410_pins: pinmux_tfp410_pins { + pinctrl-single,pins = < + 0x194 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; }; &omap3_pmx_core2 { @@ -152,6 +251,10 @@ #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" +&i2c3 { + clock-frequency = <100000>; +}; + &mmc1 { vmmc-supply = <&vmmc1>; vmmc_aux-supply = <&vsim>; @@ -211,3 +314,39 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + +&mcbsp2 { + status = "okay"; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-beagle-xm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-beagle-xm.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-beagle-xm.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-beagle-xm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -24,6 +24,11 @@ reg = <0x80000000 0x20000000>; /* 512 MB */ }; + aliases { + display0 = &dvi0; + display1 = &tv0; + }; + leds { compatible = "gpio-leds"; @@ -86,6 +91,60 @@ reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; + + /* XXX pinctrl from twl */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector@1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; }; &omap3_pmx_wkup { @@ -94,6 +153,17 @@ 0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; + + dss_dpi_pins2: pinmux_dss_dpi_pins1 { + pinctrl-single,pins = < + 0x0a (PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + 0x0c (PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + 0x10 (PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + 0x12 (PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + 0x14 (PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + 0x16 (PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; }; &omap3_pmx_core { @@ -119,6 +189,35 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ >; }; + + dss_dpi_pins1: pinmux_dss_dpi_pins2 { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; }; &omap3_pmx_core2 { @@ -164,15 +263,6 @@ &i2c3 { clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; }; &mmc1 { @@ -234,3 +324,37 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + +&mcbsp2 { + status = "okay"; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins1 + &dss_dpi_pins2 + >; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3517.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3517.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3517.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3517.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,136 @@ +/* + * Support for CompuLab CM-T3517 + */ +/dts-v1/; + +#include "am3517.dtsi" +#include "omap3-cm-t3x.dtsi" + +/ { + model = "CompuLab CM-T3517"; + compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; + + vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vw1271"; + pinctrl-names = "default"; + pinctrl-0 = < + &wl12xx_wkup_pins + &wl12xx_core_pins + >; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */ + startup-delay-us = <20000>; + enable-active-high; + }; + + wl12xx_vaux2: wl12xx_vaux2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271_vaux2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&omap3_pmx_wkup { + + wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ + >; + }; +}; + +&omap3_pmx_core { + + phy1_reset_pins: pinmux_hsusb1_phy_reset_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ + >; + }; + + phy2_reset_pins: pinmux_hsusb2_phy_reset_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ + >; + }; + + otg_drv_vbus: pinmux_otg_drv_vbus { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + wl12xx_core_pins: pinmux_wl12xx_core_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ + OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ + >; + }; + + usb_hub_pins: pinmux_usb_hub_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ + >; + }; +}; + +&hsusb1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&phy1_reset_pins>; + reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; +}; + +&hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&phy2_reset_pins>; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; +}; + +&davinci_emac { + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&am35x_otg_hs { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&otg_drv_vbus>; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + vmmc_aux-supply = <&wl12xx_vaux2>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3530.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3530.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3530.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3530.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,48 @@ +/* + * Support for CompuLab CM-T3530 + */ +/dts-v1/; + +#include "omap34xx.dtsi" +#include "omap3-cm-t3x30.dtsi" + +/ { + model = "CompuLab CM-T3530"; + compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; + + /* Regulator to trigger the reset signal of the Wifi module */ + mmc2_sdio_reset: regulator-mmc2-sdio-reset { + compatible = "regulator-fixed"; + regulator-name = "regulator-mmc2-sdio-reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&omap3_pmx_core { + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&mmc2_sdio_reset>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3730.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3730.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3730.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3730.dts 2014-04-13 23:18:35.000000000 +0200 @@ -32,57 +32,26 @@ }; &omap3_pmx_core { - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < - 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - smsc1_pins: pinmux_smsc1_pins { - pinctrl-single,pins = < - 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ - 0x16a (PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ >; }; wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < - 0xb2 (PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ - 0x134 (PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ >; }; }; -&mmc1 { - vmmc-supply = <&vmmc1>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; @@ -92,13 +61,3 @@ bus-width = <4>; cap-power-off-card; }; - -&smsc1 { - pinctrl-names = "default"; - pinctrl-0 = <&smsc1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3x30.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3x30.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3x30.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3x30.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -1,28 +1,16 @@ /* - * Common support for CompuLab CM-T3530 and CM-T3730 + * Common support for CompuLab CM-T3x30 CoMs */ -/ { - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; +#include "omap3-cm-t3x.dtsi" +/ { cpus { cpu@0 { cpu0-supply = <&vcc>; }; }; - leds { - compatible = "gpio-leds"; - ledb { - label = "cm-t35:green"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ - linux,default-trigger = "heartbeat"; - }; - }; - vddvario: regulator-vddvario { compatible = "regulator-fixed"; regulator-name = "vddvario"; @@ -36,11 +24,40 @@ }; }; +&omap3_pmx_core { + + smsc1_pins: pinmux_smsc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ + OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ + >; + }; + + hsusb0_pins: pinmux_hsusb0_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; +}; + &gpmc { ranges = <5 0 0x2c000000 0x01000000>; smsc1: ethernet@5,0 { compatible = "smsc,lan9221", "smsc,lan9115"; + pinctrl-names = "default"; + pinctrl-0 = <&smsc1_pins>; interrupt-parent = <&gpio6>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; reg = <5 0 0xff>; @@ -74,8 +91,6 @@ }; &i2c1 { - clock-frequency = <400000>; - twl: twl@48 { reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ @@ -86,10 +101,31 @@ #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" -&i2c3 { - clock-frequency = <400000>; +&mmc1 { + vmmc-supply = <&vmmc1>; }; &twl_gpio { ti,use-leds; + /* pullups: BIT(0) */ + ti,pullups = <0x000001>; +}; + +&hsusb1_phy { + reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; +}; + +&hsusb2_phy { + reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb0_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3x.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3x.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-cm-t3x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-cm-t3x.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,110 @@ +/* + * Common support for CompuLab CM-T3x CoMs + */ + +/ { + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&green_led_pins>; + ledb { + label = "cm-t3x:green"; + gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ + linux,default-trigger = "heartbeat"; + }; + }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&hsusb1_power>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&hsusb2_power>; + }; +}; + +&omap3_pmx_core { + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + green_led_pins: pinmux_green_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ + >; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; +}; + +&mmc3 { + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; +&usbhshost { + port1-mode = "ehci-phy"; + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy &hsusb2_phy>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-devkit8000.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-devkit8000.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-devkit8000.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-devkit8000.dts 2014-04-13 23:18:35.000000000 +0200 @@ -101,20 +101,8 @@ status = "disabled"; }; -&mcbsp1 { - status = "disabled"; -}; - -&mcbsp3 { - status = "disabled"; -}; - -&mcbsp4 { - status = "disabled"; -}; - -&mcbsp5 { - status = "disabled"; +&mcbsp2 { + status = "okay"; }; &gpmc { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -35,6 +35,11 @@ compatible = "arm,cortex-a8"; device_type = "cpu"; reg = <0x0>; + + clocks = <&dpll1_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; @@ -176,6 +181,22 @@ pinctrl-single,function-mask = <0xff1f>; }; + omap3_scm_general: tisyscon@48002270 { + compatible = "syscon"; + reg = <0x48002270 0x2f0>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x2b0 0x4>; + syscon = <&omap3_scm_general>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + gpio1: gpio@48310000 { compatible = "ti,omap3-gpio"; reg = <0x48310000 0x200>; @@ -390,6 +411,7 @@ ti,dual-volt; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { @@ -411,10 +433,19 @@ }; mmu_isp: mmu@480bd400 { - compatible = "ti,omap3-mmu-isp"; - ti,hwmods = "mmu_isp"; + compatible = "ti,omap2-iommu"; reg = <0x480bd400 0x80>; - interrupts = <8>; + interrupts = <24>; + ti,hwmods = "mmu_isp"; + ti,#tlb-entries = <8>; + }; + + mmu_iva: mmu@5d000000 { + compatible = "ti,omap2-iommu"; + reg = <0x5d000000 0x80>; + interrupts = <28>; + ti,hwmods = "mmu_iva"; + status = "disabled"; }; wdt2: wdt@48314000 { @@ -436,6 +467,7 @@ dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp2: mcbsp@49022000 { @@ -453,6 +485,7 @@ dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp3: mcbsp@49024000 { @@ -470,6 +503,7 @@ dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp4: mcbsp@49026000 { @@ -485,6 +519,7 @@ dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp5: mcbsp@48096000 { @@ -500,6 +535,7 @@ dmas = <&sdma 21>, <&sdma 22>; dma-names = "tx", "rx"; + status = "disabled"; }; sham: sham@480c3000 { @@ -634,14 +670,14 @@ ranges; usbhsohci: ohci@48064400 { - compatible = "ti,ohci-omap3", "usb-ohci"; + compatible = "ti,ohci-omap3"; reg = <0x48064400 0x400>; interrupt-parent = <&intc>; interrupts = <76>; }; usbhsehci: ehci@48064800 { - compatible = "ti,ehci-omap", "usb-ehci"; + compatible = "ti,ehci-omap"; reg = <0x48064800 0x400>; interrupt-parent = <&intc>; interrupts = <77>; @@ -669,6 +705,58 @@ num-eps = <16>; ram-bits = <12>; }; + + dss: dss@48050000 { + compatible = "ti,omap3-dss"; + reg = <0x48050000 0x200>; + status = "disabled"; + ti,hwmods = "dss_core"; + clocks = <&dss1_alwon_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@48050400 { + compatible = "ti,omap3-dispc"; + reg = <0x48050400 0x400>; + interrupts = <25>; + ti,hwmods = "dss_dispc"; + clocks = <&dss1_alwon_fck>; + clock-names = "fck"; + }; + + dsi: encoder@4804fc00 { + compatible = "ti,omap3-dsi"; + reg = <0x4804fc00 0x200>, + <0x4804fe00 0x40>, + <0x4804ff00 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = <25>; + status = "disabled"; + ti,hwmods = "dss_dsi1"; + clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; + clock-names = "fck", "sys_clk"; + }; + + rfbi: encoder@48050800 { + compatible = "ti,omap3-rfbi"; + reg = <0x48050800 0x100>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + clocks = <&dss1_alwon_fck>, <&dss_ick>; + clock-names = "fck", "ick"; + }; + + venc: encoder@48050c00 { + compatible = "ti,omap3-venc"; + reg = <0x48050c00 0x100>; + status = "disabled"; + ti,hwmods = "dss_venc"; + clocks = <&dss_tv_fck>; + clock-names = "fck"; + }; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-gta04.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-gta04.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-gta04.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-gta04.dts 2014-04-13 23:18:35.000000000 +0200 @@ -36,6 +36,14 @@ gpio-key,wakeup; }; }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "gta04"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; }; &omap3_pmx_core { @@ -80,6 +88,12 @@ interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; }; #include "twl4030.dtsi" @@ -96,6 +110,14 @@ interrupts = <17 IRQ_TYPE_EDGE_RISING>; }; + /* accelerometer */ + bma180@41 { + compatible = "bosch,bma180"; + reg = <0x41>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; + /* leds */ tca6507@45 { compatible = "ti,tca6507"; @@ -124,6 +146,22 @@ reg = <0x4>; }; }; + + /* compass aka magnetometer */ + hmc5843@1e { + compatible = "honeywell,hmc5843"; + reg = <0x1e>; + }; + + /* touchscreen */ + tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio6>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <600>; + }; }; &i2c3 { @@ -148,7 +186,9 @@ }; &mmc2 { - status = "disabled"; + vmmc-supply = <&vaux4>; + bus-width = <4>; + ti,non-removable; }; &mmc3 { @@ -170,3 +210,12 @@ pinctrl-0 = <&uart3_pins>; }; +&charger { + bb_uvolt = <3200000>; + bb_uamp = <150>; +}; + +&vaux4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-igep0020.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-igep0020.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-igep0020.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-igep0020.dts 2014-04-13 23:18:35.000000000 +0200 @@ -61,22 +61,63 @@ reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ vcc-supply = <&hsusb1_power>; }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; }; &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < &tfp410_pins - &dss_pins + &dss_dpi_pins >; - tfp410_pins: tfp410_dvi_pins { + tfp410_pins: pinmux_tfp410_pins { pinctrl-single,pins = < 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ >; }; - dss_pins: pinmux_dss_dvi_pins { + dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -226,3 +267,14 @@ /* Needed for DSS */ regulator-name = "vdds_dsi"; }; + +&dss { + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-igep.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-igep.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-igep.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-igep.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -170,6 +170,7 @@ &mcbsp2 { pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; }; &mmc1 { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-ldp.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-ldp.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-ldp.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-ldp.dts 2014-04-13 23:18:35.000000000 +0200 @@ -174,8 +174,20 @@ }; &mmc1 { + /* See 35xx errata 2.1.1.128 in SPRZ278F */ + compatible = "ti,omap3-pre-es3-hsmmc"; vmmc-supply = <&vmmc1>; bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&mmc2 { + status="disabled"; +}; + +&mmc3 { + status="disabled"; }; &omap3_pmx_core { @@ -209,6 +221,17 @@ 0x174 (PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ >; }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + >; + }; }; &usb_otg_hs { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-lilly-a83x.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-lilly-a83x.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-lilly-a83x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-lilly-a83x.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2014 Christoph Fritz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "omap36xx.dtsi" + +/ { + model = "INCOstartec LILLY-A83X module (DM3730)"; + compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; + + chosen { + bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x8000000>; /* 128 MB */ + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "lilly-a83x::led1"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "lilly-a83x"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; + + reg_vcc3: vcc3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_vcc3>; + }; +}; + +&omap3_pmx_wkup { + pinctrl-names = "default"; + + lan9221_pins: pinmux_lan9221_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ + >; + }; + + tsc2048_pins: pinmux_tsc2048_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ + >; + }; + + mmc1cd_pins: pinmux_mmc1cd_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ + >; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + hsusb1_pins: pinmux_hsusb1_pins { + pinctrl-single,pins = < + + /* GPIO 182 controls USB-Hub reset. But USB-Phy its + * reset can't be controlled. So we clamp this GPIO to + * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. + */ + + OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ + >; + }; + + hsusb_otg_pins: pinmux_hsusb_otg_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + spi2_pins: pinmux_spi2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb1_2_pins + >; + + hsusb1_2_pins: pinmux_hsusb1_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + >; + }; + + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ + >; + }; + +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&gpio6 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; +}; + +&i2c1 { + clock-frequency = <2600000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl { + vmmc1: regulator-vmmc1 { + regulator-always-on; + }; + + vdd1: regulator-vdd1 { + regulator-always-on; + }; + + vdd2: regulator-vdd2 { + regulator-always-on; + }; +}; + +&i2c2 { + clock-frequency = <2600000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + clock-frequency = <2600000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + gpiom1: gpio@20 { + compatible = "mcp,mcp23017"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + status = "disabled"; +}; + +&mmc1 { + cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + cd-inverted; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mcspi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + + tsc2046@0 { + reg = <0>; /* CS0 */ + compatible = "ti,tsc2046"; + interrupt-parent = <&gpio1>; + interrupts = <8 0>; /* boot6 / gpio_8 */ + spi-max-frequency = <1000000>; + pendown-gpio = <&gpio1 8 0>; + vcc-supply = <®_vcc3>; + pinctrl-names = "default"; + pinctrl-0 = <&tsc2048_pins>; + + ti,x-min = <300>; + ti,x-max = <3000>; + ti,y-min = <600>; + ti,y-max = <3600>; + ti,x-plate-ohms = <80>; + ti,pressure-max = <255>; + ti,swap-xy; + + linux,wakeup; + }; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + +&usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_2_pins>; + num-ports = <2>; + port1-mode = "ehci-phy"; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, + <7 0 0x15000000 0x01000000>; + + nand@0,0 { + reg = <0 0 0x1000000>; + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + /* no elm on omap3 */ + + gpmc,mux-add-data = <0>; + gpmc,device-nand; + gpmc,device-width = <2>; + gpmc,wait-pin = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,burst-length= <4>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <100>; + gpmc,cs-wr-off-ns = <100>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <100>; + gpmc,adv-wr-off-ns = <100>; + gpmc,oe-on-ns = <5>; + gpmc,oe-off-ns = <75>; + gpmc,we-on-ns = <5>; + gpmc,we-off-ns = <75>; + gpmc,rd-cycle-ns = <100>; + gpmc,wr-cycle-ns = <100>; + gpmc,access-ns = <60>; + gpmc,page-burst-access-ns = <5>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-delay-ns = <50>; + gpmc,wr-data-mux-bus-ns = <75>; + gpmc,wr-access-ns = <155>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MLO"; + reg = <0 0x80000>; + }; + + partition@0x80000 { + label = "u-boot"; + reg = <0x80000 0x1e0000>; + }; + + partition@0x260000 { + label = "u-boot-environment"; + reg = <0x260000 0x20000>; + }; + + partition@0x280000 { + label = "kernel"; + reg = <0x280000 0x500000>; + }; + + partition@0x780000 { + label = "filesystem"; + reg = <0x780000 0xf880000>; + }; + }; + + ethernet@7,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + bank-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <60>; + gpmc,cs-wr-off-ns = <60>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <60>; + gpmc,rd-cycle-ns = <100>; + gpmc,wr-cycle-ns = <100>; + gpmc,access-ns = <50>; + gpmc,page-burst-access-ns = <5>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wr-data-mux-bus-ns = <15>; + gpmc,wr-access-ns = <75>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <®_vcc3>; + vdd33a-supply = <®_vcc3>; + reg-io-width = <4>; + interrupt-parent = <&gpio5>; + interrupts = <1 0x2>; + reg = <7 0 0xff>; + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + phy-mode = "mii"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-lilly-dbb056.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-lilly-dbb056.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-lilly-dbb056.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-lilly-dbb056.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2014 Christoph Fritz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +/dts-v1/; + +#include "omap3-lilly-a83x.dtsi" + +/ { + model = "INCOstartec LILLY-DBB056 (DM3730)"; + compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; +}; + +&twl { + vaux2: regulator-vaux2 { + compatible = "ti,twl4030-vaux2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + lan9117_pins: pinmux_lan9117_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ + >; + }; + + gpio4_pins: pinmux_gpio4_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ + >; + }; + + gpio5_pins: pinmux_gpio5_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ + >; + }; + + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ + OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio4_pins>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio5_pins>; +}; + +&mmc2 { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vmmc1>; + cd-gpios = <&gpio6 4 0>; /* gpio_164 */ + wp-gpios = <&gpio6 3 0>; /* gpio_163 */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + ti,dual-volt; +}; + +&mcspi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ + <4 0 0x20000000 0x01000000>, + <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + bank-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <65>; + gpmc,cs-wr-off-ns = <65>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <65>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <65>; + gpmc,rd-cycle-ns = <100>; + gpmc,wr-cycle-ns = <100>; + gpmc,access-ns = <60>; + gpmc,page-burst-access-ns = <5>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wr-data-mux-bus-ns = <15>; + gpmc,wr-access-ns = <75>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <®_vcc3>; + vdd33a-supply = <®_vcc3>; + reg-io-width = <4>; + interrupt-parent = <&gpio4>; + interrupts = <2 0x2>; + reg = <4 0 0xff>; + pinctrl-names = "default"; + pinctrl-0 = <&lan9117_pins>; + phy-mode = "mii"; + smsc,force-internal-phy; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-n900.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-n900.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-n900.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-n900.dts 2014-04-13 23:18:35.000000000 +0200 @@ -74,6 +74,22 @@ }; }; + isp1704: isp1704 { + compatible = "nxp,isp1704"; + nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + usb-phy = <&usb2_phy>; + }; + + tv: connector { + compatible = "composite-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; }; &omap3_pmx_core { @@ -140,11 +156,23 @@ >; }; - display_pins: pinmux_display_pins { + acx565akm_pins: pinmux_acx565akm_pins { pinctrl-single,pins = < 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ >; }; + + dss_sdi_pins: pinmux_dss_sdi_pins { + pinctrl-single,pins = < + 0x0c0 (PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ + 0x0c2 (PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ + 0x0c4 (PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ + 0x0c6 (PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ + + 0x0d8 (PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ + 0x0da (PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ + >; + }; }; &i2c1 { @@ -254,6 +282,61 @@ }; }; +&twl_keypad { + linux,keymap = < 0x00000010 /* KEY_Q */ + 0x00010018 /* KEY_O */ + 0x00020019 /* KEY_P */ + 0x00030033 /* KEY_COMMA */ + 0x0004000e /* KEY_BACKSPACE */ + 0x0006001e /* KEY_A */ + 0x0007001f /* KEY_S */ + + 0x01000011 /* KEY_W */ + 0x01010020 /* KEY_D */ + 0x01020021 /* KEY_F */ + 0x01030022 /* KEY_G */ + 0x01040023 /* KEY_H */ + 0x01050024 /* KEY_J */ + 0x01060025 /* KEY_K */ + 0x01070026 /* KEY_L */ + + 0x02000012 /* KEY_E */ + 0x02010034 /* KEY_DOT */ + 0x02020067 /* KEY_UP */ + 0x0203001c /* KEY_ENTER */ + 0x0205002c /* KEY_Z */ + 0x0206002d /* KEY_X */ + 0x0207002e /* KEY_C */ + 0x02080043 /* KEY_F9 */ + + 0x03000013 /* KEY_R */ + 0x0301002f /* KEY_V */ + 0x03020030 /* KEY_B */ + 0x03030031 /* KEY_N */ + 0x03040032 /* KEY_M */ + 0x03050039 /* KEY_SPACE */ + 0x03060039 /* KEY_SPACE */ + 0x03070069 /* KEY_LEFT */ + + 0x04000014 /* KEY_T */ + 0x0401006c /* KEY_DOWN */ + 0x0402006a /* KEY_RIGHT */ + 0x0404001d /* KEY_LEFTCTRL */ + 0x04050064 /* KEY_RIGHTALT */ + 0x0406002a /* KEY_LEFTSHIFT */ + 0x04080044 /* KEY_F10 */ + + 0x05000015 /* KEY_Y */ + 0x05080057 /* KEY_F11 */ + + 0x06000016 /* KEY_U */ + + 0x07000017 /* KEY_I */ + 0x07010041 /* KEY_F7 */ + 0x07020042 /* KEY_F8 */ + >; +}; + &twl_gpio { ti,pullups = <0x0>; ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ @@ -291,6 +374,13 @@ DVDD-supply = <&vio>; }; + tsl2563: tsl2563@29 { + compatible = "amstaos,tsl2563"; + reg = <0x29>; + + amstaos,cover-comp-gain = <16>; + }; + lp5523: lp5523@32 { compatible = "national,lp5523"; reg = <0x32>; @@ -356,6 +446,29 @@ compatible = "ti,bq27200"; reg = <0x55>; }; + + tpa6130a2: tpa6130a2@60 { + compatible = "ti,tpa6130a2"; + reg = <0x60>; + + Vdd-supply = <&vmmc2>; + + power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ + }; + + bq24150a: bq24150a@6b { + compatible = "ti,bq24150a"; + reg = <0x6b>; + + ti,current-limit = <100>; + ti,weak-battery-voltage = <3400>; + ti,battery-regulation-voltage = <4200>; + ti,charge-current = <650>; + ti,termination-current = <100>; + ti,resistor-sense = <68>; + + ti,usb-charger-detection = <&isp1704>; + }; }; &i2c3 { @@ -471,13 +584,23 @@ spi-max-frequency = <6000000>; reg = <0>; }; - mipid@2 { - compatible = "acx565akm"; + + acx565akm@2 { + compatible = "sony,acx565akm"; spi-max-frequency = <6000000>; reg = <2>; pinctrl-names = "default"; - pinctrl-0 = <&display_pins>; + pinctrl-0 = <&acx565akm_pins>; + + label = "lcd"; + reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&sdi_out>; + }; + }; }; }; @@ -503,3 +626,39 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_sdi_pins>; + + vdds_sdi-supply = <&vaux1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + sdi_out: endpoint { + remote-endpoint = <&lcd_in>; + datapairs = <2>; + }; + }; + }; +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <1>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Alto35 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + gpio148 { + label = "overo:red:gpio148"; + gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */ + }; + gpio150 { + label = "overo:yellow:gpio150"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */ + }; + gpio151 { + label = "overo:blue:gpio151"; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */ + }; + gpio170 { + label = "overo:green:gpio170"; + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + button0@10 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ + gpio-key,wakeup; + }; + }; +}; + +&omap3_pmx_core { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ + OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ + OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */ + OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; +}; + +&omap3_pmx_wkup { + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ + >; + }; +}; + +&usbhshost { + status = "disabled"; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-alto35.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-alto35.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-alto35.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-alto35.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Alto35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-alto35-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Alto35"; + compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-base.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-base.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-base.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-base.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,221 @@ +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * The Gumstix Overo must be combined with an expansion board. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + + overo { + label = "overo:blue:COM"; + pwms = <&twl_pwmled 1 7812500>; + max-brightness = <127>; + linux,default-trigger = "mmc0"; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "overo"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio6 8 0>; /* gpio_168: vbus enable */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ + vcc-supply = <&hsusb2_power>; + }; + + /* Regulator to trigger the nPoweron signal of the Wifi module */ + w3cbw003c_npoweron: regulator-w3cbw003c-npoweron { + compatible = "regulator-fixed"; + regulator-name = "regulator-w3cbw003c-npoweron"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */ + enable-active-high; + }; + + /* Regulator to trigger the nReset signal of the Wifi module */ + w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset { + pinctrl-names = "default"; + pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>; + compatible = "regulator-fixed"; + regulator-name = "regulator-w3cbw003c-wifi-nreset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */ + startup-delay-us = <10000>; + }; + + /* Regulator to trigger the nReset signal of the Bluetooth module */ + w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset { + compatible = "regulator-fixed"; + regulator-name = "regulator-w3cbw003c-bt-nreset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164: BT nReset */ + startup-delay-us = <10000>; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + /* WiFi/BT combo */ + w3cbw003c_pins: pinmux_w3cbw003c_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ + >; + }; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */ + >; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +/* i2c2 pins are used for gpio */ +&i2c2 { + status = "disabled"; +}; + +/* on board microSD slot */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +/* optional on board WiFi */ +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&w3cbw003c_npoweron>; + vqmmc-supply = <&w3cbw003c_bt_nreset>; + vmmc_aux-supply = <&w3cbw003c_wifi_nreset>; + bus-width = <4>; + cap-sdio-irq; + non-removable; +}; + +&twl_gpio { + ti,use-leds; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Chestnut43 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0@23 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + gpio-key,wakeup; + }; + button1@14 { + label = "button1"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + gpio-key,wakeup; + }; + }; +}; + +#include "omap-gpmc-smsc9221.dtsi" + +&gpmc { + ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ + + ethernet@gpmc { + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ + }; +}; + +&lis33de { + status = "disabled"; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-chestnut43.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-chestnut43.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-chestnut43.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-chestnut43.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Chestnut43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-chestnut43-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Chestnut43"; + compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...) + */ + +/ { + lis33_3v3: lis33-3v3-reg { + compatible = "regulator-fixed"; + regulator-name = "lis33-3v3-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lis33_1v8: lis33-1v8-reg { + compatible = "regulator-fixed"; + regulator-name = "lis33-1v8-reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&omap3_pmx_core { + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + + /* optional 1K EEPROM with revision information */ + eeprom@51 { + compatible = "atmel,24c01"; + reg = <0x51>; + pagesize = <8>; + }; + + lis33de: lis33de@1d { + compatible = "st,lis33de", "st,lis3lv02d"; + reg = <0x1d>; + Vdd-supply = <&lis33_1v8>; + Vdd_IO-supply = <&lis33_3v3>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -1,94 +1,38 @@ /* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/* - * The Gumstix Overo must be combined with an expansion board. - */ +#include "omap34xx.dtsi" +#include "omap3-overo-base.dtsi" -/ { - pwmleds { - compatible = "pwm-leds"; - - overo { - label = "overo:blue:COM"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - linux,default-trigger = "mmc0"; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "overo"; - - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -/* i2c2 pins are used for gpio */ -&i2c2 { - status = "disabled"; -}; -/* on board microSD slot */ -&mmc1 { - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -/* optional on board WiFi */ -&mmc2 { - bus-width = <4>; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&omap3_pmx_core { - uart3_pins: pinmux_uart3_pins { + w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { pinctrl-single,pins = < - 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ >; }; }; -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; +&mcbsp2 { + status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Gallop43 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0@23 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + gpio-key,wakeup; + }; + button1@14 { + label = "button1"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + gpio-key,wakeup; + }; + }; +}; + +&usbhshost { + status = "disabled"; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-gallop43.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-gallop43.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-gallop43.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-gallop43.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Gallop43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-gallop43-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Gallop43"; + compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Palo43 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0@23 { + label = "button0"; + linux,code = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + gpio-key,wakeup; + }; + button1@14 { + label = "button1"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + gpio-key,wakeup; + }; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-palo43.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-palo43.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-palo43.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-palo43.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Palo43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-palo43-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Palo43"; + compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-alto35.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-alto35.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-alto35.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-alto35.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Alto35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-alto35-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; + compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Chestnut43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-chestnut43-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; + compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap36xx.dtsi" +#include "omap3-overo-base.dtsi" + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Gallop43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-gallop43-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; + compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-palo43.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-palo43.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-palo43.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-palo43.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Palo43 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-palo43-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; + compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-summit.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-summit.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-summit.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-summit.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Summit expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-summit-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; + compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-tobi.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-tobi.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-storm-tobi.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-storm-tobi.dts 2014-04-13 23:18:35.000000000 +0200 @@ -12,7 +12,7 @@ /dts-v1/; -#include "omap36xx.dtsi" +#include "omap3-overo-storm.dtsi" #include "omap3-overo-tobi-common.dtsi" / { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-summit-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-summit-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-summit-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-summit-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Summit expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&lis33de { + status = "disabled"; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-summit.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-summit.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-summit.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-summit.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Summit expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-summit-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Summit"; + compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + >; + }; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,7 +10,7 @@ * Tobi expansion board is manufactured by Gumstix Inc. */ -#include "omap3-overo.dtsi" +#include "omap3-overo-common-peripherals.dtsi" / { leds { @@ -21,60 +21,21 @@ linux,default-trigger = "heartbeat"; }; }; - - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; }; +#include "omap-gpmc-smsc9221.dtsi" + &gpmc { ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ - ethernet@5,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; + ethernet@gpmc { reg = <5 0 0xff>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <42>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <42>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <36>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <54>; - gpmc,access-ns = <36>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wr-data-mux-bus-ns = <18>; - gpmc,wr-access-ns = <42>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - interrupt-parent = <&gpio6>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - reg-io-width = <4>; }; }; -&i2c3 { - clock-frequency = <100000>; -}; - -&mmc3 { +&lis33de { status = "disabled"; }; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-overo-tobi.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-tobi.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-overo-tobi.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-overo-tobi.dts 2014-04-13 23:18:35.000000000 +0200 @@ -12,7 +12,7 @@ /dts-v1/; -#include "omap34xx.dtsi" +#include "omap3-overo.dtsi" #include "omap3-overo-tobi-common.dtsi" / { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-sbc-t3517.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sbc-t3517.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-sbc-t3517.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sbc-t3517.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,43 @@ +/* + * Suppport for CompuLab SBC-T3517 with CM-T3517 + */ + +#include "omap3-cm-t3517.dts" +#include "omap3-sb-t35.dtsi" + +/ { + model = "CompuLab SBC-T3517 with CM-T3517"; + compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &sb_t35_usb_hub_pins + &usb_hub_pins + >; + + mmc1_aux_pins: pinmux_mmc1_aux_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ + >; + }; + + sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc1_pins + &mmc1_aux_pins + >; + + wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ + cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-sbc-t3530.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sbc-t3530.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-sbc-t3530.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sbc-t3530.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,36 @@ +/* + * Suppport for CompuLab SBC-T3530 with CM-T3530 + */ + +#include "omap3-cm-t3530.dts" +#include "omap3-sb-t35.dtsi" + +/ { + model = "CompuLab SBC-T3530 with CM-T3530"; + compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&sb_t35_usb_hub_pins>; + + sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ + >; + }; +}; + +/* + * The following ranges correspond to SMSC9x eth chips on CM-T3530 CoM and + * SB-T35 baseboard respectively. + * This setting includes both chips in SBC-T3530 board device tree. + */ +&gpmc { + ranges = <5 0 0x2c000000 0x01000000>, + <4 0 0x2d000000 0x01000000>; +}; + +&mmc1 { + cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-sbc-t3730.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sbc-t3730.dts --- linux-3.14.1/arch/arm/boot/dts/omap3-sbc-t3730.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sbc-t3730.dts 2014-04-13 23:18:35.000000000 +0200 @@ -10,21 +10,18 @@ compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; }; -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, - <4 0 0x2d000000 0x01000000>; -}; - -&smsc2 { +&omap3_pmx_core { pinctrl-names = "default"; - pinctrl-0 = <&smsc2_pins>; -}; + pinctrl-0 = <&sb_t35_usb_hub_pins>; -&omap3_pmx_core { - smsc2_pins: pinmux_smsc2_pins { + sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { pinctrl-single,pins = < - 0x86 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ - 0xa2 (PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ + OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ >; }; -}; \ Kein Zeilenumbruch am Dateiende. +}; + +&gpmc { + ranges = <5 0 0x2c000000 0x01000000>, + <4 0 0x2d000000 0x01000000>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3-sb-t35.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sb-t35.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3-sb-t35.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3-sb-t35.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -2,11 +2,36 @@ * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 */ +/ { + vddvario_sb_t35: regulator-vddvario-sb-t35 { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a_sb_t35: regulator-vdd33a-sb-t35 { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&omap3_pmx_core { + smsc2_pins: pinmux_smsc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ + OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ + >; + }; +}; + &gpmc { ranges = <4 0 0x2d000000 0x01000000>; smsc2: ethernet@4,0 { compatible = "smsc,lan9221", "smsc,lan9115"; + pinctrl-names = "default"; + pinctrl-0 = <&smsc2_pins>; interrupt-parent = <&gpio3>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; reg = <4 0 0xff>; @@ -32,8 +57,8 @@ gpmc,wr-access-ns = <186>; gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-diffcsen; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; + vddvario-supply = <&vddvario_sb_t35>; + vdd33a-supply = <&vdd33a_sb_t35>; reg-io-width = <4>; smsc,save-mac-address; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap3xxx-clocks.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap3xxx-clocks.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap3xxx-clocks.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap3xxx-clocks.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -425,10 +425,11 @@ dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { #clock-cells = <0>; - compatible = "fixed-factor-clock"; + compatible = "ti,fixed-factor-clock"; clocks = <&dpll4_m4_ck>; - clock-mult = <2>; - clock-div = <1>; + ti,clock-mult = <2>; + ti,clock-div = <1>; + ti,set-rate-parent; }; dpll4_m4x2_ck: dpll4_m4x2_ck { @@ -438,6 +439,7 @@ ti,bit-shift = <0x1d>; reg = <0x0d00>; ti,set-bit-to-disable; + ti,set-rate-parent; }; dpll4_m5_ck: dpll4_m5_ck { diff -Nur linux-3.14.1/arch/arm/boot/dts/omap443x.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap443x.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap443x.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap443x.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -43,6 +43,32 @@ #thermal-sensor-cells = <0>; }; }; + + ocp { + abb_mpu: regulator-abb-mpu { + status = "okay"; + + reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; + reg-names = "base-address", "int-address"; + + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1025000 0 0 0 0 0 + 1200000 0 0 0 0 0 + 1313000 0 0 0 0 0 + 1375000 1 0 0 0 0 + 1389000 1 0 0 0 0 + >; + }; + + /* Default unused, just provide register info for record */ + abb_iva: regulator-abb-iva { + reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; + reg-names = "base-address", "int-address"; + }; + + }; + }; /include/ "omap443x-clocks.dtsi" diff -Nur linux-3.14.1/arch/arm/boot/dts/omap4460.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap4460.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap4460.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap4460.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -50,7 +50,44 @@ #thermal-sensor-cells = <0>; }; + + abb_mpu: regulator-abb-mpu { + status = "okay"; + + reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, + <0x4A002268 0x4>; + reg-names = "base-address", "int-address", + "efuse-address"; + + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1025000 0 0 0 0 0 + 1200000 0 0 0 0 0 + 1313000 0 0 0x100000 0x40000 0 + 1375000 1 0 0 0 0 + 1389000 1 0 0 0 0 + >; + }; + + abb_iva: regulator-abb-iva { + status = "okay"; + + reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, + <0x4A002268 0x4>; + reg-names = "base-address", "int-address", + "efuse-address"; + + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 950000 0 0 0 0 0 + 1140000 0 0 0 0 0 + 1291000 0 0 0x200000 0 0 + 1375000 1 0 0 0 0 + 1376000 1 0 0 0 0 + >; + }; }; + }; /include/ "omap446x-clocks.dtsi" diff -Nur linux-3.14.1/arch/arm/boot/dts/omap4.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap4.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap4.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap4.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -36,6 +36,11 @@ device_type = "cpu"; next-level-cache = <&L2>; reg = <0x0>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ }; cpu@1 { compatible = "arm,cortex-a9"; @@ -186,6 +191,22 @@ pinctrl-single,function-mask = <0x7fff>; }; + omap4_padconf_global: tisyscon@4a1005a0 { + compatible = "syscon"; + reg = <0x4a1005a0 0x170>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap4_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap4 { + regulator-name = "pbias_mmc_omap4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -275,6 +296,8 @@ gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; ti,no-idle-on-init; + clocks = <&l3_div_ck>; + clock-names = "fck"; }; uart1: serial@4806a000 { @@ -313,6 +336,7 @@ compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; ti,hwmods = "spinlock"; + #hwlock-cells = <1>; }; i2c1: i2c@48070000 { @@ -419,6 +443,7 @@ ti,needs-special-reset; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { @@ -461,6 +486,21 @@ dma-names = "tx", "rx"; }; + mmu_dsp: mmu@4a066000 { + compatible = "ti,omap4-iommu"; + reg = <0x4a066000 0x100>; + interrupts = ; + ti,hwmods = "mmu_dsp"; + }; + + mmu_ipu: mmu@55082000 { + compatible = "ti,omap4-iommu"; + reg = <0x55082000 0x100>; + interrupts = ; + ti,hwmods = "mmu_ipu"; + ti,iommu-bus-err-back; + }; + wdt2: wdt@4a314000 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x4a314000 0x80>; @@ -478,6 +518,7 @@ dmas = <&sdma 65>, <&sdma 66>; dma-names = "up_link", "dn_link"; + status = "disabled"; }; dmic: dmic@4012e000 { @@ -489,6 +530,7 @@ ti,hwmods = "dmic"; dmas = <&sdma 67>; dma-names = "up_link"; + status = "disabled"; }; mcbsp1: mcbsp@40122000 { @@ -503,6 +545,7 @@ dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp2: mcbsp@40124000 { @@ -517,6 +560,7 @@ dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp3: mcbsp@40126000 { @@ -531,6 +575,7 @@ dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp4: mcbsp@48096000 { @@ -544,6 +589,7 @@ dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; + status = "disabled"; }; keypad: keypad@4a31c000 { @@ -554,6 +600,13 @@ ti,hwmods = "kbd"; }; + dmm@4e000000 { + compatible = "ti,omap4-dmm"; + reg = <0x4e000000 0x800>; + interrupts = <0 113 0x4>; + ti,hwmods = "dmm"; + }; + emif1: emif@4c000000 { compatible = "ti,emif-4d"; reg = <0x4c000000 0x100>; @@ -697,16 +750,22 @@ #address-cells = <1>; #size-cells = <1>; ranges; + clocks = <&init_60m_fclk>, + <&xclk60mhsp1_ck>, + <&xclk60mhsp2_ck>; + clock-names = "refclk_60m_int", + "refclk_60m_ext_p1", + "refclk_60m_ext_p2"; usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3", "usb-ohci"; + compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; interrupt-parent = <&gic>; interrupts = ; }; usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap", "usb-ehci"; + compatible = "ti,ehci-omap"; reg = <0x4a064c00 0x400>; interrupt-parent = <&gic>; interrupts = ; @@ -757,6 +816,111 @@ dmas = <&sdma 117>, <&sdma 116>; dma-names = "tx", "rx"; }; + + abb_mpu: regulator-abb-mpu { + compatible = "ti,abb-v2"; + regulator-name = "abb_mpu"; + #address-cells = <0>; + #size-cells = <0>; + ti,tranxdone-status-mask = <0x80>; + clocks = <&sys_clkin_ck>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + status = "disabled"; + }; + + abb_iva: regulator-abb-iva { + compatible = "ti,abb-v2"; + regulator-name = "abb_iva"; + #address-cells = <0>; + #size-cells = <0>; + ti,tranxdone-status-mask = <0x80000000>; + clocks = <&sys_clkin_ck>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + status = "disabled"; + }; + + dss: dss@58000000 { + compatible = "ti,omap4-dss"; + reg = <0x58000000 0x80>; + status = "disabled"; + ti,hwmods = "dss_core"; + clocks = <&dss_dss_clk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@58001000 { + compatible = "ti,omap4-dispc"; + reg = <0x58001000 0x1000>; + interrupts = ; + ti,hwmods = "dss_dispc"; + clocks = <&dss_dss_clk>; + clock-names = "fck"; + }; + + rfbi: encoder@58002000 { + compatible = "ti,omap4-rfbi"; + reg = <0x58002000 0x1000>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + clocks = <&dss_dss_clk>, <&dss_fck>; + clock-names = "fck", "ick"; + }; + + venc: encoder@58003000 { + compatible = "ti,omap4-venc"; + reg = <0x58003000 0x1000>; + status = "disabled"; + ti,hwmods = "dss_venc"; + clocks = <&dss_tv_clk>; + clock-names = "fck"; + }; + + dsi1: encoder@58004000 { + compatible = "ti,omap4-dsi"; + reg = <0x58004000 0x200>, + <0x58004200 0x40>, + <0x58004300 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = ; + status = "disabled"; + ti,hwmods = "dss_dsi1"; + clocks = <&dss_dss_clk>, <&dss_sys_clk>; + clock-names = "fck", "sys_clk"; + }; + + dsi2: encoder@58005000 { + compatible = "ti,omap4-dsi"; + reg = <0x58005000 0x200>, + <0x58005200 0x40>, + <0x58005300 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = ; + status = "disabled"; + ti,hwmods = "dss_dsi2"; + clocks = <&dss_dss_clk>, <&dss_sys_clk>; + clock-names = "fck", "sys_clk"; + }; + + hdmi: encoder@58006000 { + compatible = "ti,omap4-hdmi"; + reg = <0x58006000 0x200>, + <0x58006200 0x100>, + <0x58006300 0x100>, + <0x58006400 0x1000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = ; + status = "disabled"; + ti,hwmods = "dss_hdmi"; + clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; + clock-names = "fck", "sys_clk"; + }; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap4-duovero.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-duovero.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap4-duovero.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-duovero.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap443x.dtsi" + +/ { + model = "Gumstix Duovero"; + compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + sound { + compatible = "ti,abe-twl6040"; + ti,model = "DuoVero"; + + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias"; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1phy_pins>; + + clocks = <&auxclk3_ck>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + }; + + /* regulator for w2cbw0015 on sdio5 */ + w2cbw0015_vmmc: w2cbw0015_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&w2cbw0015_pins>; + compatible = "regulator-fixed"; + regulator-name = "w2cbw0015"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */ + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &mcpdm_pins + &mcbsp1_pins + &hsusbb1_pins + >; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + 0x126 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ + 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ + 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ + 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ + 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ + 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ + >; + }; + + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ + 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ + 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ + 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ + >; + }; + + hsusbb1_pins: pinmux_hsusbb1_pins { + pinctrl-single,pins = < + 0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ + 0x84 (PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ + 0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ + 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ + 0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ + 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ + 0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ + 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ + 0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ + 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ + 0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ + 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ + >; + }; + + hsusb1phy_pins: pinmux_hsusb1phy_pins { + pinctrl-single,pins = < + 0x4c (PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ + >; + }; + + w2cbw0015_pins: pinmux_w2cbw0015_pins { + pinctrl-single,pins = < + 0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ + 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c4_pins: pinmux_i2c4_pins { + pinctrl-single,pins = < + 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0xa2 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ + 0xa6 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ + 0xaa (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ + >; + }; + + mmc5_pins: pinmux_mmc5_pins { + pinctrl-single,pins = < + 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ + 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ + 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ + 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ + 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ + >; + }; +}; + +/* PMIC */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + interrupt-parent = <&gic>; + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + interrupts = ; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +/* on-board bluetooth / WiFi module */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <&vmmc>; + ti,bus-width = <4>; + ti,non-removable; /* FIXME: use PMIC_MMC detect */ +}; + +&mmc2 { + status = "disabled"; +}; + +/* mmc3 is available to the expansion board */ + +&mmc4 { + status = "disabled"; +}; + +/* on-board WiFi module */ +&mmc5 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc5_pins>; + + vmmc-supply = <&w2cbw0015_vmmc>; + ti,bus-width = <4>; + ti,non-removable; + cap-power-off-card; +}; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; + +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap4-duovero-parlor.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-duovero-parlor.dts --- linux-3.14.1/arch/arm/boot/dts/omap4-duovero-parlor.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-duovero-parlor.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap4-duovero.dtsi" + +#include + +/ { + model = "OMAP4430 Gumstix Duovero on Parlor"; + compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; + + leds { + compatible = "gpio-leds"; + led0 { + label = "duovero:blue:led0"; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button0@121 { + label = "button0"; + linux,code = ; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ + gpio-key,wakeup; + }; + }; +}; + +&omap4_pmx_core { + pinctrl-0 = < + &led_pins + &button_pins + &smsc_pins + >; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + 0xd6 (PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + 0xd4 (PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + smsc_pins: pinmux_smsc_pins { + pinctrl-single,pins = < + 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ + 0x2a (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ + 0x30 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ + >; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <100000>; + + /* optional 1K EEPROM with revision information */ + eeprom@51 { + compatible = "atmel,24c01"; + reg = <0x51>; + pagesize = <8>; + }; +}; + +&mmc3 { + status = "disabled"; +}; + +#include "omap-gpmc-smsc911x.dtsi" + +&gpmc { + ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ + + ethernet@gpmc { + reg = <5 0 0xff>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ + + phy-mode = "mii"; + + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <50>; + gpmc,cs-wr-off-ns = <50>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <15>; + gpmc,oe-off-ns = <50>; + gpmc,we-on-ns = <15>; + gpmc,we-off-ns = <50>; + gpmc,rd-cycle-ns = <50>; + gpmc,wr-cycle-ns = <50>; + gpmc,access-ns = <50>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <35>; + gpmc,cycle2cycle-delay-ns = <35>; + gpmc,wr-data-mux-bus-ns = <35>; + gpmc,wr-access-ns = <50>; + + gpmc,mux-add-data = <2>; + gpmc,sync-read; + gpmc,sync-write; + gpmc,clk-activation-ns = <5>; + gpmc,sync-clk-ps = <20000>; + }; +}; + + diff -Nur linux-3.14.1/arch/arm/boot/dts/omap4-panda-common.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-panda-common.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap4-panda-common.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-panda-common.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -16,6 +16,11 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; + aliases { + display0 = &dvi0; + display1 = &hdmi0; + }; + leds: leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -83,12 +88,8 @@ compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ vcc-supply = <&hsusb1_power>; - /** - * FIXME: - * put the right clock phandle here when available - * clocks = <&auxclk3>; - * clock-names = "main_clk"; - */ + clocks = <&auxclk3_ck>; + clock-names = "main_clk"; clock-frequency = <19200000>; }; @@ -104,14 +105,94 @@ startup-delay-us = <70000>; enable-active-high; }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tpd12s015: encoder@1 { + compatible = "ti,tpd12s015"; + + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ + <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ + <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + hdmi0: connector@1 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; }; &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &twl6040_pins - &mcpdm_pins - &mcbsp1_pins &dss_dpi_pins &tfp410_pins &dss_hdmi_pins @@ -300,6 +381,10 @@ twl6040: twl@4b { compatible = "ti,twl6040"; reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + /* IRQ# = 119 */ interrupts = ; /* IRQ_SYS_2N cascaded to gic */ interrupt-parent = <&gic>; @@ -380,16 +465,16 @@ device-handle = <&elpida_ECB240ABACN>; }; -&mcbsp2 { - status = "disabled"; -}; - -&mcbsp3 { - status = "disabled"; +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; }; -&dmic { - status = "disabled"; +&mcpdm { + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; }; &twl_usb_comparator { @@ -409,3 +494,30 @@ &usbhsehci { phys = <&hsusb1_phy>; }; + +&dss { + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&dsi2 { + status = "ok"; + vdd-supply = <&vcxio>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap4-sdp.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-sdp.dts --- linux-3.14.1/arch/arm/boot/dts/omap4-sdp.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap4-sdp.dts 2014-04-13 23:18:35.000000000 +0200 @@ -19,6 +19,12 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; + aliases { + display0 = &lcd0; + display1 = &lcd1; + display2 = &hdmi0; + }; + vdd_eth: fixedregulator-vdd-eth { compatible = "regulator-fixed"; regulator-name = "VDD_ETH"; @@ -153,16 +159,53 @@ startup-delay-us = <70000>; enable-active-high; }; + + tpd12s015: encoder@0 { + compatible = "ti,tpd12s015"; + + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ + <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ + <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + hdmi0: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "c"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; }; &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &twl6040_pins - &mcpdm_pins - &dmic_pins - &mcbsp1_pins - &mcbsp2_pins &dss_hdmi_pins &tpd12s015_pins >; @@ -326,6 +369,10 @@ twl6040: twl@4b { compatible = "ti,twl6040"; reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ interrupts = ; /* IRQ_SYS_2N cascaded to gic */ interrupt-parent = <&gic>; @@ -537,8 +584,28 @@ pinctrl-0 = <&uart4_pins>; }; -&mcbsp3 { - status = "disabled"; +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&mcbsp2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + +&dmic { + pinctrl-names = "default"; + pinctrl-0 = <&dmic_pins>; + status = "okay"; +}; + +&mcpdm { + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; }; &twl_usb_comparator { @@ -550,3 +617,68 @@ mode = <3>; power = <50>; }; + +&dss { + status = "ok"; +}; + +&dsi1 { + status = "ok"; + vdd-supply = <&vcxio>; + + port { + dsi1_out_ep: endpoint { + remote-endpoint = <&lcd0_in>; + lanes = <0 1 2 3 4 5>; + }; + }; + + lcd0: display { + compatible = "tpo,taal", "panel-dsi-cm"; + label = "lcd0"; + + reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ + + port { + lcd0_in: endpoint { + remote-endpoint = <&dsi1_out_ep>; + }; + }; + }; +}; + +&dsi2 { + status = "ok"; + vdd-supply = <&vcxio>; + + port { + dsi2_out_ep: endpoint { + remote-endpoint = <&lcd1_in>; + lanes = <0 1 2 3 4 5>; + }; + }; + + lcd1: display { + compatible = "tpo,taal", "panel-dsi-cm"; + label = "lcd1"; + + reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ + + port { + lcd1_in: endpoint { + remote-endpoint = <&dsi2_out_ep>; + }; + }; + }; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap5.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap5.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap5.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap5.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -49,6 +49,12 @@ 1000000 1060000 1500000 1250000 >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + /* cooling options */ cooling-min-level = <0>; cooling-max-level = <2>; @@ -192,6 +198,22 @@ pinctrl-single,function-mask = <0x7fff>; }; + omap5_padconf_global: tisyscon@4a002da0 { + compatible = "syscon"; + reg = <0x4A002da0 0xec>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap5_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -302,6 +324,8 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; }; i2c1: i2c@48070000 { @@ -353,6 +377,7 @@ compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; ti,hwmods = "spinlock"; + #hwlock-cells = <1>; }; mcspi1: spi@48098000 { @@ -471,6 +496,7 @@ ti,needs-special-reset; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { @@ -513,6 +539,21 @@ dma-names = "tx", "rx"; }; + mmu_dsp: mmu@4a066000 { + compatible = "ti,omap4-iommu"; + reg = <0x4a066000 0x100>; + interrupts = ; + ti,hwmods = "mmu_dsp"; + }; + + mmu_ipu: mmu@55082000 { + compatible = "ti,omap4-iommu"; + reg = <0x55082000 0x100>; + interrupts = ; + ti,hwmods = "mmu_ipu"; + ti,iommu-bus-err-back; + }; + keypad: keypad@4ae1c000 { compatible = "ti,omap4-keypad"; reg = <0x4ae1c000 0x400>; @@ -529,6 +570,7 @@ dmas = <&sdma 65>, <&sdma 66>; dma-names = "up_link", "dn_link"; + status = "disabled"; }; dmic: dmic@4012e000 { @@ -540,6 +582,7 @@ ti,hwmods = "dmic"; dmas = <&sdma 67>; dma-names = "up_link"; + status = "disabled"; }; mcbsp1: mcbsp@40122000 { @@ -554,6 +597,7 @@ dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp2: mcbsp@40124000 { @@ -568,6 +612,7 @@ dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; + status = "disabled"; }; mcbsp3: mcbsp@40126000 { @@ -582,6 +627,7 @@ dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; + status = "disabled"; }; timer1: timer@4ae18000 { @@ -683,6 +729,13 @@ ti,hwmods = "wd_timer2"; }; + dmm@4e000000 { + compatible = "ti,omap5-dmm"; + reg = <0x4e000000 0x800>; + interrupts = <0 113 0x4>; + ti,hwmods = "dmm"; + }; + emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; @@ -732,7 +785,8 @@ compatible = "snps,dwc3"; reg = <0x4a030000 0x10000>; interrupts = ; - usb-phy = <&usb2_phy>, <&usb3_phy>; + phys = <&usb2_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; dr_mode = "peripheral"; tx-fifo-resize; }; @@ -749,6 +803,7 @@ compatible = "ti,omap-usb2"; reg = <0x4a084000 0x7c>; ctrl-module = <&omap_control_usb2phy>; + #phy-cells = <0>; }; usb3_phy: usb3phy@4a084400 { @@ -758,6 +813,7 @@ <0x4a084c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; ctrl-module = <&omap_control_usb3phy>; + #phy-cells = <0>; }; }; @@ -775,16 +831,22 @@ #address-cells = <1>; #size-cells = <1>; ranges; + clocks = <&l3init_60m_fclk>, + <&xclk60mhsp1_ck>, + <&xclk60mhsp2_ck>; + clock-names = "refclk_60m_int", + "refclk_60m_ext_p1", + "refclk_60m_ext_p2"; usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3", "usb-ohci"; + compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; interrupt-parent = <&gic>; interrupts = ; }; usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap", "usb-ehci"; + compatible = "ti,ehci-omap"; reg = <0x4a064c00 0x400>; interrupt-parent = <&gic>; interrupts = ; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap5-uevm.dts linux-3.15-rc1.orig/arch/arm/boot/dts/omap5-uevm.dts --- linux-3.14.1/arch/arm/boot/dts/omap5-uevm.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap5-uevm.dts 2014-04-13 23:18:35.000000000 +0200 @@ -31,12 +31,8 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ - /** - * FIXME - * Put the right clock phandle here when available - * clocks = <&auxclk1>; - * clock-names = "main_clk"; - */ + clocks = <&auxclk1_ck>; + clock-names = "main_clk"; clock-frequency = <19200000>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi --- linux-3.14.1/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,58 @@ +/* + * Common file for GPMC connected smsc9221 on omaps + * + * Compared to smsc911x, smsc9221 (and others like smsc9217 + * or smsc 9218) has faster timings, leading to higher + * bandwidth. + * + * Note that the board specifc DTS file needs to specify + * ranges, pinctrl, reg, interrupt parent and interrupts. + */ + +/ { + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&gpmc { + ethernet@gpmc { + compatible = "smsc,lan9221","smsc,lan9115"; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <42>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <42>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <36>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <54>; + gpmc,access-ns = <36>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wr-data-mux-bus-ns = <18>; + gpmc,wr-access-ns = <42>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/prima2.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/prima2.dtsi --- linux-3.14.1/arch/arm/boot/dts/prima2.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/prima2.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -76,9 +76,10 @@ #clock-cells = <1>; }; - reset-controller@88010000 { + rstc: reset-controller@88010000 { compatible = "sirf,prima2-rstc"; reg = <0x88010000 0x1000>; + #reset-cells = <1>; }; rsc-controller@88020000 { @@ -223,8 +224,8 @@ interrupts = <17>; fifosize = <128>; clocks = <&clks 13>; - sirf,uart-dma-rx-channel = <21>; - sirf,uart-dma-tx-channel = <2>; + dmas = <&dmac1 5>, <&dmac0 2>; + dma-names = "rx", "tx"; }; uart1: uart@b0060000 { @@ -243,8 +244,8 @@ interrupts = <19>; fifosize = <128>; clocks = <&clks 15>; - sirf,uart-dma-rx-channel = <6>; - sirf,uart-dma-tx-channel = <7>; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "rx", "tx"; }; usp0: usp@b0080000 { @@ -254,8 +255,8 @@ interrupts = <20>; fifosize = <128>; clocks = <&clks 28>; - sirf,usp-dma-rx-channel = <17>; - sirf,usp-dma-tx-channel = <18>; + dmas = <&dmac1 1>, <&dmac1 2>; + dma-names = "rx", "tx"; }; usp1: usp@b0090000 { @@ -265,8 +266,8 @@ interrupts = <21>; fifosize = <128>; clocks = <&clks 29>; - sirf,usp-dma-rx-channel = <14>; - sirf,usp-dma-tx-channel = <15>; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "rx", "tx"; }; usp2: usp@b00a0000 { @@ -276,8 +277,8 @@ interrupts = <22>; fifosize = <128>; clocks = <&clks 30>; - sirf,usp-dma-rx-channel = <10>; - sirf,usp-dma-tx-channel = <11>; + dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "rx", "tx"; }; dmac0: dma-controller@b00b0000 { @@ -286,6 +287,7 @@ reg = <0xb00b0000 0x10000>; interrupts = <12>; clocks = <&clks 24>; + #dma-cells = <1>; }; dmac1: dma-controller@b0160000 { @@ -294,6 +296,7 @@ reg = <0xb0160000 0x10000>; interrupts = <13>; clocks = <&clks 25>; + #dma-cells = <1>; }; vip@b00C0000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/qcom-msm8660.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8660.dtsi --- linux-3.14.1/arch/arm/boot/dts/qcom-msm8660.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8660.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,87 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" + +#include + +/ { + model = "Qualcomm MSM8660"; + compatible = "qcom,msm8660"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + intc: interrupt-controller@2080000 { + compatible = "qcom,msm-8660-qgic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02080000 0x1000 >, + < 0x02081000 0x1000 >; + }; + + timer@2000000 { + compatible = "qcom,scss-timer", "qcom,msm-timer"; + interrupts = <1 0 0x301>, + <1 1 0x301>, + <1 2 0x301>; + reg = <0x02000000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x40000>; + }; + + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + reg = <0x00800000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <173>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8660"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + serial@19c40000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x19c40000 0x1000>, + <0x19c00000 0x1000>; + interrupts = <0 195 0x0>; + clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; + clock-names = "core", "iface"; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/qcom-msm8660-surf.dts linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8660-surf.dts --- linux-3.14.1/arch/arm/boot/dts/qcom-msm8660-surf.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8660-surf.dts 2014-04-13 23:18:35.000000000 +0200 @@ -1,63 +1,6 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" - -#include +#include "qcom-msm8660.dtsi" / { model = "Qualcomm MSM8660 SURF"; compatible = "qcom,msm8660-surf", "qcom,msm8660"; - interrupt-parent = <&intc>; - - intc: interrupt-controller@2080000 { - compatible = "qcom,msm-8660-qgic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02080000 0x1000 >, - < 0x02081000 0x1000 >; - }; - - timer@2000000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; - reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x40000>; - }; - - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - reg = <0x00800000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - ngpio = <173>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8660"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 0x0>; - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/qcom-msm8960-cdp.dts linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8960-cdp.dts --- linux-3.14.1/arch/arm/boot/dts/qcom-msm8960-cdp.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8960-cdp.dts 2014-04-13 23:18:35.000000000 +0200 @@ -1,70 +1,6 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" - -#include +#include "qcom-msm8960.dtsi" / { model = "Qualcomm MSM8960 CDP"; compatible = "qcom,msm8960-cdp", "qcom,msm8960"; - interrupt-parent = <&intc>; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02000000 0x1000 >, - < 0x02002000 0x1000 >; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpio = <150>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/qcom-msm8960.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8960.dtsi --- linux-3.14.1/arch/arm/boot/dts/qcom-msm8960.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8960.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,135 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" + +#include + +/ { + model = "Qualcomm MSM8960"; + compatible = "qcom,msm8960"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 14 0x304>; + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + qcom,no-pc-write; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >, + < 0x02002000 0x1000 >; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <150>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <0 154 0x0>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/qcom-msm8974.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8974.dtsi --- linux-3.14.1/arch/arm/boot/dts/qcom-msm8974.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/qcom-msm8974.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -9,6 +9,54 @@ compatible = "qcom,msm8974"; interrupt-parent = <&intc>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + qcom,saw = <&saw_l2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 7 0xf04>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -91,6 +139,32 @@ }; }; + saw_l2: regulator@f9012000 { + compatible = "qcom,saw2"; + reg = <0xf9012000 0x1000>; + regulator; + }; + + acc0: clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + }; + + acc1: clock-controller@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + }; + + acc2: clock-controller@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + }; + + acc3: clock-controller@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + }; + restart@fc4ab000 { compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; @@ -117,5 +191,12 @@ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; }; + + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/r7s72100.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/r7s72100.dtsi --- linux-3.14.1/arch/arm/boot/dts/r7s72100.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r7s72100.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -8,12 +8,26 @@ * kind, whether express or implied. */ +#include + / { compatible = "renesas,r7s72100"; interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -33,4 +47,137 @@ reg = <0xe8201000 0x1000>, <0xe8202000 0x1000>; }; + + i2c0: i2c@fcfee000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, + <0 158 IRQ_TYPE_EDGE_RISING>, + <0 159 IRQ_TYPE_EDGE_RISING>, + <0 160 IRQ_TYPE_LEVEL_HIGH>, + <0 161 IRQ_TYPE_LEVEL_HIGH>, + <0 162 IRQ_TYPE_LEVEL_HIGH>, + <0 163 IRQ_TYPE_LEVEL_HIGH>, + <0 164 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@fcfee400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee400 0x44>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, + <0 166 IRQ_TYPE_EDGE_RISING>, + <0 167 IRQ_TYPE_EDGE_RISING>, + <0 168 IRQ_TYPE_LEVEL_HIGH>, + <0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 172 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@fcfee800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee800 0x44>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, + <0 174 IRQ_TYPE_EDGE_RISING>, + <0 175 IRQ_TYPE_EDGE_RISING>, + <0 176 IRQ_TYPE_LEVEL_HIGH>, + <0 177 IRQ_TYPE_LEVEL_HIGH>, + <0 178 IRQ_TYPE_LEVEL_HIGH>, + <0 179 IRQ_TYPE_LEVEL_HIGH>, + <0 180 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@fcfeec00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfeec00 0x44>; + interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, + <0 182 IRQ_TYPE_EDGE_RISING>, + <0 183 IRQ_TYPE_EDGE_RISING>, + <0 184 IRQ_TYPE_LEVEL_HIGH>, + <0 185 IRQ_TYPE_LEVEL_HIGH>, + <0 186 IRQ_TYPE_LEVEL_HIGH>, + <0 187 IRQ_TYPE_LEVEL_HIGH>, + <0 188 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + spi0: spi@e800c800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800c800 0x24>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>, + <0 239 IRQ_TYPE_LEVEL_HIGH>, + <0 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@e800d000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d000 0x24>; + interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>, + <0 242 IRQ_TYPE_LEVEL_HIGH>, + <0 243 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@e800d800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800d800 0x24>; + interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>, + <0 245 IRQ_TYPE_LEVEL_HIGH>, + <0 246 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@e800e000 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e000 0x24>; + interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>, + <0 248 IRQ_TYPE_LEVEL_HIGH>, + <0 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@e800e800 { + compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; + reg = <0xe800e800 0x24>; + interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>, + <0 251 IRQ_TYPE_LEVEL_HIGH>, + <0 252 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/r7s72100-genmai-reference.dts linux-3.15-rc1.orig/arch/arm/boot/dts/r7s72100-genmai-reference.dts --- linux-3.14.1/arch/arm/boot/dts/r7s72100-genmai-reference.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r7s72100-genmai-reference.dts 2014-04-13 23:18:35.000000000 +0200 @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r7s72100.dtsi" +#include "r7s72100.dtsi" / { model = "Genmai"; @@ -29,3 +29,14 @@ #size-cells = <1>; }; }; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "renesas,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/r8a7778-bockw-reference.dts linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7778-bockw-reference.dts --- linux-3.14.1/arch/arm/boot/dts/r8a7778-bockw-reference.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7778-bockw-reference.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,6 +17,7 @@ /dts-v1/; #include "r8a7778.dtsi" #include +#include / { model = "bockw"; @@ -84,7 +85,7 @@ sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", - "sdhi0_cd", "sdhi0_wp"; + "sdhi0_cd"; renesas,function = "sdhi0"; }; @@ -101,6 +102,7 @@ vmmc-supply = <&fixedregulator3v3>; bus-width = <4>; status = "okay"; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; }; &hspi0 { diff -Nur linux-3.14.1/arch/arm/boot/dts/r8a7778.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7778.dtsi --- linux-3.14.1/arch/arm/boot/dts/r8a7778.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7778.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -203,46 +203,6 @@ status = "disabled"; }; - i2c0: i2c@ffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc70000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c1: i2c@ffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc71000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c2: i2c@ffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc72000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c3: i2c@ffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc73000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - hspi0: spi@fffc7000 { compatible = "renesas,hspi"; reg = <0xfffc7000 0x18>; diff -Nur linux-3.14.1/arch/arm/boot/dts/r8a7790.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7790.dtsi --- linux-3.14.1/arch/arm/boot/dts/r8a7790.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7790.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -1,7 +1,8 @@ /* * Device Tree Source for the r8a7790 SoC * - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -18,6 +19,13 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -94,7 +102,6 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6050000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -106,7 +113,6 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6051000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -118,7 +124,6 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6052000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -130,7 +135,6 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6053000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -142,7 +146,6 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6054000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -154,7 +157,6 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xe6055000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -166,8 +168,8 @@ thermal@e61f0000 { compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupt-parent = <&gic>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; }; timer { @@ -183,7 +185,6 @@ #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; - interrupt-parent = <&gic>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, @@ -195,7 +196,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6508000 0 0x40>; - interrupt-parent = <&gic>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C0>; status = "disabled"; @@ -206,7 +206,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6518000 0 0x40>; - interrupt-parent = <&gic>; interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C1>; status = "disabled"; @@ -217,7 +216,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6530000 0 0x40>; - interrupt-parent = <&gic>; interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C2>; status = "disabled"; @@ -228,7 +226,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6540000 0 0x40>; - interrupt-parent = <&gic>; interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C3>; status = "disabled"; @@ -237,7 +234,6 @@ mmcif0: mmcif@ee200000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; - interrupt-parent = <&gic>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; reg-io-width = <4>; @@ -247,7 +243,6 @@ mmcif1: mmc@ee220000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; - interrupt-parent = <&gic>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; reg-io-width = <4>; @@ -262,7 +257,6 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee100000 0 0x200>; - interrupt-parent = <&gic>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; cap-sd-highspeed; @@ -272,7 +266,6 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee120000 0 0x200>; - interrupt-parent = <&gic>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; cap-sd-highspeed; @@ -282,7 +275,6 @@ sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee140000 0 0x100>; - interrupt-parent = <&gic>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; cap-sd-highspeed; @@ -292,13 +284,129 @@ sdhi3: sd@ee160000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee160000 0 0x100>; - interrupt-parent = <&gic>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; cap-sd-highspeed; status = "disabled"; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7790", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7790", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7790", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7790", "renesas,scifb"; + reg = <0 0xe6c20000 0 64>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7790", "renesas,scifb"; + reg = <0 0xe6c30000 0 64>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7790", "renesas,scifb"; + reg = <0 0xe6ce0000 0 64>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7790", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7790", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7790", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7790", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7790"; + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_ETHER>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7790"; + reg = <0 0xee300000 0 0x2000>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_SATA0>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7790"; + reg = <0 0xee500000 0 0x2000>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_SATA1>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -313,6 +421,29 @@ clock-output-names = "extal"; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency clocks by + * default. Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "audio_clk_a"; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "audio_clk_b"; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "audio_clk_c"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7790-cpg-clocks", @@ -607,10 +738,16 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&p_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, + <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = ; - clock-output-names = "ether"; + renesas,clock-indices = < + R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 + R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 + R8A7790_CLK_SATA0 + >; + clock-output-names = + "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -627,4 +764,15 @@ "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; }; }; + + spi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7790", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/r8a7790-lager.dts linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7790-lager.dts --- linux-3.14.1/arch/arm/boot/dts/r8a7790-lager.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7790-lager.dts 2014-04-13 23:18:35.000000000 +0200 @@ -1,7 +1,8 @@ /* * Device Tree Source for the Lager board * - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -56,6 +57,54 @@ regulator-boot-on; regulator-always-on; }; + + vcc_sdhi0: regulator@1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator@2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi2: regulator@3 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi2: regulator@4 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &extal_clk { @@ -63,23 +112,68 @@ }; &pfc { - pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; pinctrl-names = "default"; + du_pins: du { + renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; + renesas,function = "du"; + }; + scif0_pins: serial0 { renesas,groups = "scif0_data"; renesas,function = "scif0"; }; + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq0"; + renesas,function = "intc"; + }; + scif1_pins: serial1 { renesas,groups = "scif1_data"; renesas,function = "scif1"; }; + sdhi0_pins: sd0 { + renesas,gpios = "sdhi0_data4", "sdhi0_ctrl"; + renesas,function = "sdhi0"; + }; + + sdhi2_pins: sd2 { + renesas,gpios = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; + }; + mmc1_pins: mmc1 { renesas,groups = "mmc1_data8", "mmc1_ctrl"; renesas,function = "mmc1"; }; + + qspi_pins: spi { + renesas,groups = "qspi_ctrl", "qspi_data4"; + renesas,function = "qspi"; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "ok"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; }; &mmcif1 { @@ -91,3 +185,58 @@ non-removable; status = "okay"; }; + +&sata1 { + status = "okay"; +}; + +&spi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s"; + reg = <0>; + spi-max-frequency = <30000000>; + m25p,fast-read; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash"; + reg = <0x00440000 0x03bc0000>; + }; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/r8a7791.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7791.dtsi --- linux-3.14.1/arch/arm/boot/dts/r8a7791.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7791.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -2,7 +2,8 @@ * Device Tree Source for the r8a7791 SoC * * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -19,6 +20,15 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -53,7 +63,6 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6050000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -65,7 +74,6 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6051000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -77,7 +85,6 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6052000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -89,7 +96,6 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6053000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -101,7 +107,6 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6054000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -113,7 +118,6 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6055000 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -125,7 +129,6 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6055400 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -137,7 +140,6 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xe6055800 0 0x50>; - interrupt-parent = <&gic>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -149,8 +151,8 @@ thermal@e61f0000 { compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupt-parent = <&gic>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; }; timer { @@ -166,7 +168,6 @@ #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; - interrupt-parent = <&gic>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, @@ -179,12 +180,288 @@ <0 17 IRQ_TYPE_LEVEL_HIGH>; }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C3>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C4>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_I2C5>; + status = "disabled"; + }; + pfc: pfc@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; #gpio-range-cells = <3>; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7791"; + reg = <0 0xee100000 0 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7791"; + reg = <0 0xee140000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7791"; + reg = <0 0xee160000 0 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; + status = "disabled"; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7791", "renesas,scifb"; + reg = <0 0xe6c20000 0 64>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7791", "renesas,scifb"; + reg = <0 0xe6c30000 0 64>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7791", "renesas,scifb"; + reg = <0 0xe6ce0000 0 64>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7791", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7791", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7791", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7791"; + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_ETHER>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7791"; + reg = <0 0xee300000 0 0x2000>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_SATA0>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7791"; + reg = <0 0xee500000 0 0x2000>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_SATA1>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -429,7 +706,7 @@ R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 >; clock-output-names = - "scifa2", "scifa1", "scifa0", "misof2", "scifb0", + "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", "scifb1", "msiof1", "scifb2"; }; mstp3_clks: mstp3_clks@e615013c { @@ -474,10 +751,15 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&p_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; - renesas,clock-indices = ; - clock-output-names = "ether"; + renesas,clock-indices = < + R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 + R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 + >; + clock-output-names = + "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -488,7 +770,7 @@ #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD - R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 + R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 >; clock-output-names = @@ -506,4 +788,15 @@ clock-output-names = "scifa3", "scifa4", "scifa5"; }; }; + + spi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7791", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/r8a7791-koelsch.dts linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7791-koelsch.dts --- linux-3.14.1/arch/arm/boot/dts/r8a7791-koelsch.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7791-koelsch.dts 2014-04-13 23:18:35.000000000 +0200 @@ -2,7 +2,8 @@ * Device Tree Source for the Koelsch board * * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -23,7 +24,12 @@ memory@40000000 { device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; }; lbsc { @@ -31,6 +37,60 @@ #size-cells = <1>; }; + gpio-keys { + compatible = "gpio-keys"; + + key-a { + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + linux,code = <30>; + label = "SW30"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = <48>; + label = "SW31"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; + linux,code = <46>; + label = "SW32"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; + linux,code = <32>; + label = "SW33"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-e { + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + linux,code = <18>; + label = "SW34"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-f { + gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; + linux,code = <33>; + label = "SW35"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-g { + gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + linux,code = <34>; + label = "SW36"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; led6 { @@ -43,16 +103,112 @@ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; }; }; + + vcc_sdhi0: regulator@0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator@1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator@2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator@3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi2: regulator@4 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi2: regulator@5 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &extal_clk { clock-frequency = <20000000>; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "renesas,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + &pfc { - pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; pinctrl-names = "default"; + i2c2_pins: i2c { + renesas,groups = "i2c2"; + renesas,function = "i2c2"; + }; + + du_pins: du { + renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0"; + renesas,function = "du"; + }; + scif0_pins: serial0 { renesas,groups = "scif0_data_d"; renesas,function = "scif0"; @@ -62,4 +218,116 @@ renesas,groups = "scif1_data_d"; renesas,function = "scif1"; }; + + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq0"; + renesas,function = "intc"; + }; + + sdhi0_pins: sd0 { + renesas,gpios = "sdhi0_data4", "sdhi0_ctrl"; + renesas,function = "sdhi0"; + }; + + sdhi1_pins: sd1 { + renesas,gpios = "sdhi1_data4", "sdhi1_ctrl"; + renesas,function = "sdhi1"; + }; + + sdhi2_pins: sd2 { + renesas,gpios = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; + }; + + qspi_pins: spi { + renesas,groups = "qspi_ctrl", "qspi_data4"; + renesas,function = "qspi"; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "ok"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s"; + reg = <0>; + spi-max-frequency = <30000000>; + m25p,fast-read; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + partition@80000 { + label = "bootenv"; + reg = <0x00080000 0x00080000>; + read-only; + }; + partition@100000 { + label = "data"; + reg = <0x00100000 0x03f00000>; + }; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/r8a7791-koelsch-reference.dts linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7791-koelsch-reference.dts --- linux-3.14.1/arch/arm/boot/dts/r8a7791-koelsch-reference.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/r8a7791-koelsch-reference.dts 1970-01-01 01:00:00.000000000 +0100 @@ -1,115 +0,0 @@ -/* - * Device Tree Source for the Koelsch board - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include - -/ { - model = "Koelsch"; - compatible = "renesas,koelsch-reference", "renesas,r8a7791"; - - chosen { - bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = <30>; - label = "SW30"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = <48>; - label = "SW31"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = <46>; - label = "SW32"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = <32>; - label = "SW33"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = <18>; - label = "SW34"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = <33>; - label = "SW35"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = <34>; - label = "SW36"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pfc { - pinctrl-0 = <&scif0_pins &scif1_pins>; - pinctrl-names = "default"; - - scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; - }; - - scif1_pins: serial1 { - renesas,groups = "scif1_data_d"; - renesas,function = "scif1"; - }; -}; diff -Nur linux-3.14.1/arch/arm/boot/dts/rk3066a.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/rk3066a.dtsi --- linux-3.14.1/arch/arm/boot/dts/rk3066a.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/rk3066a.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -64,6 +64,19 @@ clock-names = "timer", "pclk"; }; + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; reg = <0x20008000 0x150>; diff -Nur linux-3.14.1/arch/arm/boot/dts/rk3188.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/rk3188.dtsi --- linux-3.14.1/arch/arm/boot/dts/rk3188.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/rk3188.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -60,6 +60,19 @@ interrupts = ; }; + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x8000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; reg = <0x20008000 0xa0>, diff -Nur linux-3.14.1/arch/arm/boot/dts/rk3xxx.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/rk3xxx.dtsi --- linux-3.14.1/arch/arm/boot/dts/rk3xxx.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/rk3xxx.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -26,6 +26,16 @@ compatible = "simple-bus"; ranges; + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + + pmu@20004000 { + compatible = "rockchip,rk3066-pmu"; + reg = <0x20004000 0x100>; + }; + gic: interrupt-controller@1013d000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; diff -Nur linux-3.14.1/arch/arm/boot/dts/sama5d3.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sama5d3.dtsi --- linux-3.14.1/arch/arm/boot/dts/sama5d3.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sama5d3.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -239,7 +239,9 @@ }; adc0: adc@f8018000 { - compatible = "atmel,at91sam9260-adc"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9x5-adc"; reg = <0xf8018000 0x100>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; @@ -261,52 +263,39 @@ clocks = <&adc_clk>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channel-base = <0x50>; atmel,adc-channels-used = <0xfff>; - atmel,adc-drdy-mask = <0x1000000>; - atmel,adc-num-channels = <12>; atmel,adc-startup-time = <40>; - atmel,adc-status-register = <0x30>; - atmel,adc-trigger-register = <0xc0>; - atmel,adc-use-external; + atmel,adc-use-external-triggers; atmel,adc-vref = <3000>; atmel,adc-res = <10 12>; atmel,adc-res-names = "lowres", "highres"; status = "disabled"; trigger@0 { + reg = <0>; trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; trigger@1 { + reg = <1>; trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; trigger@2 { + reg = <2>; trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; trigger@3 { + reg = <3>; trigger-name = "continuous"; trigger-value = <0x6>; }; }; - tsadcc: tsadcc@f8018000 { - compatible = "atmel,at91sam9x5-tsadcc"; - reg = <0xf8018000 0x4000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,tsadcc_clock = <300000>; - atmel,filtering_average = <0x03>; - atmel,pendet_debounce = <0x08>; - atmel,pendet_sensitivity = <0x02>; - atmel,ts_sample_hold_time = <0x0a>; - status = "disabled"; - }; - i2c2: i2c@f801c000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf801c000 0x4000>; @@ -1256,6 +1245,7 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_ale_cle>; atmel,pmecc-lookup-table-offset = <0x0 0x8000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/sama5d3xdm.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sama5d3xdm.dtsi --- linux-3.14.1/arch/arm/boot/dts/sama5d3xdm.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sama5d3xdm.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -23,10 +23,8 @@ }; adc0: adc@f8018000 { - status = "disabled"; - }; - - tsadcc: tsadcc@f8018000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/socfpga_arria5.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_arria5.dtsi --- linux-3.14.1/arch/arm/boot/dts/socfpga_arria5.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_arria5.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -27,6 +27,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + serial0@ffc02000 { clock-frequency = <100000000>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/socfpga_arria5_socdk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_arria5_socdk.dts --- linux-3.14.1/arch/arm/boot/dts/socfpga_arria5_socdk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_arria5_socdk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -37,4 +37,25 @@ */ ethernet0 = &gmac1; }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/socfpga_cyclone5.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_cyclone5.dtsi --- linux-3.14.1/arch/arm/boot/dts/socfpga_cyclone5.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_cyclone5.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -28,6 +28,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff702000 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ diff -Nur linux-3.14.1/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts --- linux-3.14.1/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts 2014-04-13 23:18:35.000000000 +0200 @@ -38,3 +38,17 @@ ethernet0 = &gmac1; }; }; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts --- linux-3.14.1/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts 2014-04-13 23:18:35.000000000 +0200 @@ -30,8 +30,25 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; }; &gmac1 { status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/socfpga.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga.dtsi --- linux-3.14.1/arch/arm/boot/dts/socfpga.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -92,7 +92,12 @@ #address-cells = <1>; #size-cells = <0>; - osc: osc1 { + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { #clock-cells = <0>; compatible = "fixed-clock"; }; @@ -100,7 +105,11 @@ f2s_periph_ref_clk: f2s_periph_ref_clk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <10000000>; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; }; main_pll: main_pll { @@ -108,7 +117,7 @@ #size-cells = <0>; #clock-cells = <0>; compatible = "altr,socfpga-pll-clock"; - clocks = <&osc>; + clocks = <&osc1>; reg = <0x40>; mpuclk: mpuclk { @@ -162,7 +171,7 @@ #size-cells = <0>; #clock-cells = <0>; compatible = "altr,socfpga-pll-clock"; - clocks = <&osc>; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; reg = <0x80>; emac0_clk: emac0_clk { @@ -213,7 +222,7 @@ #size-cells = <0>; #clock-cells = <0>; compatible = "altr,socfpga-pll-clock"; - clocks = <&osc>; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; reg = <0xC0>; ddr_dqs_clk: ddr_dqs_clk { @@ -415,6 +424,7 @@ compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; + clk-phase = <0 135>; }; nand_x_clk: nand_x_clk { @@ -443,6 +453,7 @@ gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; reg = <0xff700000 0x2000>; interrupts = <0 115 4>; interrupt-names = "macirq"; @@ -454,6 +465,7 @@ gmac1: ethernet@ff702000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; reg = <0xff702000 0x2000>; interrupts = <0 120 4>; interrupt-names = "macirq"; @@ -473,6 +485,17 @@ arm,data-latency = <2 1 1>; }; + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; @@ -526,9 +549,9 @@ reg = <0xffd05000 0x1000>; }; - sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; - reg = <0xffd08000 0x4000>; - }; + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/socfpga_vt.dts linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_vt.dts --- linux-3.14.1/arch/arm/boot/dts/socfpga_vt.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/socfpga_vt.dts 2014-04-13 23:18:35.000000000 +0200 @@ -41,6 +41,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff700000 { phy-mode = "gmii"; status = "okay"; @@ -75,3 +86,8 @@ }; }; }; + +&gmac0 { + status = "okay"; + phy-mode = "gmii"; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/ste-dbx5x0.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/ste-dbx5x0.dtsi --- linux-3.14.1/arch/arm/boot/dts/ste-dbx5x0.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/ste-dbx5x0.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -705,7 +705,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "ssp0clk", "apb_pclk"; + clock-names = "SSPCLK", "apb_pclk"; dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -718,7 +718,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "ssp1clk", "apb_pclk"; + clock-names = "SSPCLK", "apb_pclk"; dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -732,7 +732,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "spi0clk", "apb_pclk"; + clock-names = "SSPCLK", "apb_pclk"; dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ <&dma 0 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -746,7 +746,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "spi1clk", "apb_pclk"; + clock-names = "SSPCLK", "apb_pclk"; dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ <&dma 35 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -760,7 +760,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "spi2clk", "apb_pclk"; + clock-names = "SSPCLK", "apb_pclk"; dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ <&dma 33 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -774,7 +774,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "spi3clk", "apb_pclk"; + clock-names = "SSPCLK", "apb_pclk"; dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; diff -Nur linux-3.14.1/arch/arm/boot/dts/ste-href-ab8500.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/ste-href-ab8500.dtsi --- linux-3.14.1/arch/arm/boot/dts/ste-href-ab8500.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/ste-href-ab8500.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,428 @@ +/* + * Copyright 2014 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + soc { + prcmu@80157000 { + ab8500 { + ab8500-gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_default_mode>, + <&gpio4_default_mode>, + <&gpio10_default_mode>, + <&gpio11_default_mode>, + <&gpio12_default_mode>, + <&gpio13_default_mode>, + <&gpio16_default_mode>, + <&gpio24_default_mode>, + <&gpio25_default_mode>, + <&gpio36_default_mode>, + <&gpio37_default_mode>, + <&gpio38_default_mode>, + <&gpio39_default_mode>, + <&gpio42_default_mode>, + <&gpio26_default_mode>, + <&gpio35_default_mode>, + <&ycbcr_default_mode>, + <&pwm_default_mode>, + <&adi1_default_mode>, + <&usbuicc_default_mode>, + <&dmic_default_mode>, + <&extcpena_default_mode>, + <&modsclsda_default_mode>; + + /* + * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 + * are muxed in as GPIO, and configured as INPUT PULL DOWN + */ + gpio2 { + gpio2_default_mode: gpio2_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio2_a_1"; + }; + default_cfg { + ste,pins = "GPIO2_T9"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio4 { + gpio4_default_mode: gpio4_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio4_a_1"; + }; + default_cfg { + ste,pins = "GPIO4_W2"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio10 { + gpio10_default_mode: gpio10_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio10_d_1"; + }; + default_cfg { + ste,pins = "GPIO10_U17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio11 { + gpio11_default_mode: gpio11_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio11_d_1"; + }; + default_cfg { + ste,pins = "GPIO11_AA18"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio12 { + gpio12_default_mode: gpio12_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio12_d_1"; + }; + default_cfg { + ste,pins = "GPIO12_U16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio13 { + gpio13_default_mode: gpio13_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio13_d_1"; + }; + default_cfg { + ste,pins = "GPIO13_W17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio16 { + gpio16_default_mode: gpio16_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio16_a_1"; + }; + default_cfg { + ste,pins = "GPIO16_F15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio24 { + gpio24_default_mode: gpio24_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio24_a_1"; + }; + default_cfg { + ste,pins = "GPIO24_T14"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio25 { + gpio25_default_mode: gpio25_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio25_a_1"; + }; + default_cfg { + ste,pins = "GPIO25_R16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio36 { + gpio36_default_mode: gpio36_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio36_a_1"; + }; + default_cfg { + ste,pins = "GPIO36_A17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio37 { + gpio37_default_mode: gpio37_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio37_a_1"; + }; + default_cfg { + ste,pins = "GPIO37_E15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio38 { + gpio38_default_mode: gpio38_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio38_a_1"; + }; + default_cfg { + ste,pins = "GPIO38_C17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio39 { + gpio39_default_mode: gpio39_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio39_a_1"; + }; + default_cfg { + ste,pins = "GPIO39_E16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio42 { + gpio42_default_mode: gpio42_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio42_a_1"; + }; + default_cfg { + ste,pins = "GPIO42_U2"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW + */ + gpio26 { + gpio26_default_mode: gpio26_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio26_d_1"; + }; + default_cfg { + ste,pins = "GPIO26_M16"; + output-low; + }; + }; + }; + gpio35 { + gpio35_default_mode: gpio35_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio35_d_1"; + }; + default_cfg { + ste,pins = "GPIO35_W15"; + output-low; + }; + }; + }; + /* + * This sets up the YCBCR connector pins, i.e. analog video out. + * Set as input with no bias. + */ + ycbcr { + ycbcr_default_mode: ycbcr_default { + default_mux { + ste,function = "ycbcr"; + ste,pins = "ycbcr0123_d_1"; + }; + default_cfg { + ste,pins = "GPIO6_Y18", + "GPIO7_AA20", + "GPIO8_W18", + "GPIO9_AA19"; + input-enable; + bias-disable; + }; + }; + }; + /* This sets up the PWM pins 14 and 15 */ + pwm { + pwm_default_mode: pwm_default { + default_mux { + ste,function = "pwmout"; + ste,pins = "pwmout1_d_1", "pwmout2_d_1"; + }; + default_cfg { + ste,pins = "GPIO14_F14", + "GPIO15_B17"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up audio interface 1 */ + adi1 { + adi1_default_mode: adi1_default { + default_mux { + ste,function = "adi1"; + ste,pins = "adi1_d_1"; + }; + default_cfg { + ste,pins = "GPIO17_P5", + "GPIO18_R5", + "GPIO19_U5", + "GPIO20_T5"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up the USB UICC pins */ + usbuicc { + usbuicc_default_mode: usbuicc_default { + default_mux { + ste,function = "usbuicc"; + ste,pins = "usbuicc_d_1"; + }; + default_cfg { + ste,pins = "GPIO21_H19", + "GPIO22_G20", + "GPIO23_G19"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up the microphone pins */ + dmic { + dmic_default_mode: dmic_default { + default_mux { + ste,function = "dmic"; + ste,pins = "dmic12_d_1", + "dmic34_d_1", + "dmic56_d_1"; + }; + default_cfg { + ste,pins = "GPIO27_J6", + "GPIO28_K6", + "GPIO29_G6", + "GPIO30_H6", + "GPIO31_F5", + "GPIO32_G5"; + input-enable; + bias-pull-down; + }; + }; + }; + extcpena { + extcpena_default_mode: extcpena_default { + default_mux { + ste,function = "extcpena"; + ste,pins = "extcpena_d_1"; + }; + default_cfg { + ste,pins = "GPIO34_R17"; + input-enable; + bias-pull-down; + }; + }; + }; + /* Modem I2C setup (SCL and SDA pins) */ + modsclsda { + modsclsda_default_mode: modsclsda_default { + default_mux { + ste,function = "modsclsda"; + ste,pins = "modsclsda_d_1"; + }; + default_cfg { + ste,pins = "GPIO40_T19", + "GPIO41_U19"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Clock output pins associated with regulators. + */ + sysclkreq2 { + sysclkreq2_default_mode: sysclkreq2_default { + default_mux { + ste,function = "sysclkreq"; + ste,pins = "sysclkreq2_d_1"; + }; + default_cfg { + ste,pins = "GPIO1_T10"; + input-enable; + bias-disable; + }; + }; + sysclkreq2_sleep_mode: sysclkreq2_sleep { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio1_a_1"; + }; + default_cfg { + ste,pins = "GPIO1_T10"; + input-enable; + bias-pull-down; + }; + }; + }; + sysclkreq4 { + sysclkreq4_default_mode: sysclkreq4_default { + default_mux { + ste,function = "sysclkreq"; + ste,pins = "sysclkreq4_d_1"; + }; + default_cfg { + ste,pins = "GPIO3_U9"; + input-enable; + bias-disable; + }; + }; + sysclkreq4_sleep_mode: sysclkreq4_sleep { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio3_a_1"; + }; + default_cfg { + ste,pins = "GPIO3_U9"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/ste-href-ab8505.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/ste-href-ab8505.dtsi --- linux-3.14.1/arch/arm/boot/dts/ste-href-ab8505.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/ste-href-ab8505.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,240 @@ +/* + * Copyright 2014 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + soc { + prcmu@80157000 { + ab8505 { + ab8505-gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_default_mode>, + <&gpio10_default_mode>, + <&gpio11_default_mode>, + <&gpio13_default_mode>, + <&gpio34_default_mode>, + <&gpio50_default_mode>, + <&pwm_default_mode>, + <&adi2_default_mode>, + <&modsclsda_default_mode>, + <&resethw_default_mode>, + <&service_default_mode>; + + /* + * Pins 2, 10, 11, 13, 34 and 50 + * are muxed in as GPIO, and configured as INPUT PULL DOWN + */ + gpio2 { + gpio2_default_mode: gpio2_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio2_a_1"; + }; + default_cfg { + ste,pins = "GPIO2_R5"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio10 { + gpio10_default_mode: gpio10_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio10_d_1"; + }; + default_cfg { + ste,pins = "GPIO10_B16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio11 { + gpio11_default_mode: gpio11_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio11_d_1"; + }; + default_cfg { + ste,pins = "GPIO11_B17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio13 { + gpio13_default_mode: gpio13_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio13_d_1"; + }; + default_cfg { + ste,pins = "GPIO13_D17"; + input-enable; + bias-disable; + }; + }; + }; + gpio34 { + gpio34_default_mode: gpio34_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio34_a_1"; + }; + default_cfg { + ste,pins = "GPIO34_H14"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio50 { + gpio50_default_mode: gpio50_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio50_d_1"; + }; + default_cfg { + ste,pins = "GPIO50_L4"; + input-enable; + bias-disable; + }; + }; + }; + /* This sets up the PWM pin 14 */ + pwm { + pwm_default_mode: pwm_default { + default_mux { + ste,function = "pwmout"; + ste,pins = "pwmout1_d_1"; + }; + default_cfg { + ste,pins = "GPIO14_C16"; + input-enable; + bias-pull-down; + }; + }; + }; + /* This sets up audio interface 2 */ + adi2 { + adi2_default_mode: adi2_default { + default_mux { + ste,function = "adi2"; + ste,pins = "adi2_d_1"; + }; + default_cfg { + ste,pins = "GPIO17_P2", + "GPIO18_N3", + "GPIO19_T1", + "GPIO20_P3"; + input-enable; + bias-pull-down; + }; + }; + }; + /* Modem I2C setup (SCL and SDA pins) */ + modsclsda { + modsclsda_default_mode: modsclsda_default { + default_mux { + ste,function = "modsclsda"; + ste,pins = "modsclsda_d_1"; + }; + default_cfg { + ste,pins = "GPIO40_J15", + "GPIO41_J14"; + input-enable; + bias-pull-down; + }; + }; + }; + resethw { + resethw_default_mode: resethw_default { + default_mux { + ste,function = "resethw"; + ste,pins = "resethw_d_1"; + }; + default_cfg { + ste,pins = "GPIO52_D16"; + input-enable; + bias-pull-down; + }; + }; + }; + service { + service_default_mode: service_default { + default_mux { + ste,function = "service"; + ste,pins = "service_d_1"; + }; + default_cfg { + ste,pins = "GPIO53_D15"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Clock output pins associated with regulators. + */ + sysclkreq2 { + sysclkreq2_default_mode: sysclkreq2_default { + default_mux { + ste,function = "sysclkreq"; + ste,pins = "sysclkreq2_d_1"; + }; + default_cfg { + ste,pins = "GPIO1_N4"; + input-enable; + bias-disable; + }; + }; + sysclkreq2_sleep_mode: sysclkreq2_sleep { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio1_a_1"; + }; + default_cfg { + ste,pins = "GPIO1_N4"; + input-enable; + bias-pull-down; + }; + }; + }; + sysclkreq4 { + sysclkreq4_default_mode: sysclkreq4_default { + default_mux { + ste,function = "sysclkreq"; + ste,pins = "sysclkreq4_d_1"; + }; + default_cfg { + ste,pins = "GPIO3_P5"; + input-enable; + bias-disable; + }; + }; + sysclkreq4_sleep_mode: sysclkreq4_sleep { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio3_a_1"; + }; + default_cfg { + ste,pins = "GPIO3_P5"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/ste-hrefprev60.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/ste-hrefprev60.dtsi --- linux-3.14.1/arch/arm/boot/dts/ste-hrefprev60.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/ste-hrefprev60.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -12,6 +12,7 @@ */ #include "ste-dbx5x0.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-href.dtsi" / { diff -Nur linux-3.14.1/arch/arm/boot/dts/ste-hrefv60plus.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/ste-hrefv60plus.dtsi --- linux-3.14.1/arch/arm/boot/dts/ste-hrefv60plus.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/ste-hrefv60plus.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,7 @@ */ #include "ste-dbx5x0.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-href.dtsi" / { diff -Nur linux-3.14.1/arch/arm/boot/dts/ste-snowball.dts linux-3.15-rc1.orig/arch/arm/boot/dts/ste-snowball.dts --- linux-3.14.1/arch/arm/boot/dts/ste-snowball.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/ste-snowball.dts 2014-04-13 23:18:35.000000000 +0200 @@ -11,6 +11,7 @@ /dts-v1/; #include "ste-dbx5x0.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-href-family-pinctrl.dtsi" / { diff -Nur linux-3.14.1/arch/arm/boot/dts/ste-u300.dts linux-3.15-rc1.orig/arch/arm/boot/dts/ste-u300.dts --- linux-3.14.1/arch/arm/boot/dts/ste-u300.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/ste-u300.dts 2014-04-13 23:18:35.000000000 +0200 @@ -457,7 +457,7 @@ interrupt-parent = <&vica>; interrupts = <23>; clocks = <&spi_clk>, <&spi_clk>; - clock-names = "apb_pclk", "spi_clk"; + clock-names = "SSPCLK", "apb_pclk"; dmas = <&dmac 27 &dmac 28>; dma-names = "tx", "rx"; num-cs = <3>; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih415-clock.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih415-clock.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih415-clock.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih415-clock.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -34,5 +34,19 @@ compatible = "fixed-clock"; clock-frequency = <100000000>; }; + + CLKS_GMAC0_PHY: clockgenA1@7 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "CLKS_GMAC0_PHY"; + }; + + CLKS_ETH1_PHY: clockgenA0@7 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "CLKS_ETH1_PHY"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih415.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih415.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih415.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih415.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,7 @@ #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" #include +#include / { L2: cache-controller { @@ -28,6 +29,16 @@ ranges; compatible = "simple-bus"; + powerdown: powerdown-controller { + #reset-cells = <1>; + compatible = "st,stih415-powerdown"; + }; + + softreset: softreset-controller { + #reset-cells = <1>; + compatible = "st,stih415-softreset"; + }; + syscfg_sbc: sbc-syscfg@fe600000{ compatible = "st,stih415-sbc-syscfg", "syscon"; reg = <0xfe600000 0xb4>; @@ -136,5 +147,64 @@ status = "disabled"; }; + + ethernet0: dwmac@fe810000 { + device_type = "network"; + compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; + status = "disabled"; + + reg = <0xfe810000 0x8000>, <0x148 0x4>; + reg-names = "stmmaceth", "sti-ethconf"; + + interrupts = <0 147 0>, <0 148 0>, <0 149 0>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + resets = <&softreset STIH415_ETH0_SOFTRESET>; + reset-names = "stmmaceth"; + + snps,pbl = <32>; + snps,mixed-burst; + snps,force_sf_dma_mode; + + st,syscon = <&syscfg_rear>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mii0>; + clock-names = "stmmaceth"; + clocks = <&CLKS_GMAC0_PHY>; + }; + + ethernet1: dwmac@fef08000 { + device_type = "network"; + compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; + status = "disabled"; + reg = <0xfef08000 0x8000>, <0x74 0x4>; + reg-names = "stmmaceth", "sti-ethconf"; + interrupts = <0 150 0>, <0 151 0>, <0 152 0>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + + snps,pbl = <32>; + snps,mixed-burst; + snps,force_sf_dma_mode; + + st,syscon = <&syscfg_sbc>; + + resets = <&softreset STIH415_ETH1_SOFTRESET>; + reset-names = "stmmaceth"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mii1>; + clock-names = "stmmaceth"; + clocks = <&CLKS_ETH1_PHY>; + }; + + rc: rc@fe518000 { + compatible = "st,comms-irb"; + reg = <0xfe518000 0x234>; + interrupts = <0 203 0>; + clocks = <&CLK_SYSIN>; + rx-mode = "infrared"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + resets = <&softreset STIH415_IRB_SOFTRESET>; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih415-pinctrl.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih415-pinctrl.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih415-pinctrl.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih415-pinctrl.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -7,6 +7,7 @@ * publishhed by the Free Software Foundation. */ #include "st-pincfg.h" +#include / { aliases { @@ -45,35 +46,49 @@ #size-cells = <1>; compatible = "st,stih415-sbc-pinctrl"; st,syscfg = <&syscfg_sbc>; + reg = <0xfe61f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfe610000 0x5000>; PIO0: gpio@fe610000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO0"; }; PIO1: gpio@fe611000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; PIO2: gpio@fe612000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; PIO3: gpio@fe613000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; PIO4: gpio@fe614000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO4"; }; @@ -104,6 +119,64 @@ }; }; }; + + rc{ + pinctrl_ir: ir0 { + st,pins { + ir = <&PIO4 0 ALT2 IN>; + }; + }; + }; + + gmac1 { + pinctrl_mii1: mii1 { + st,pins { + txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&PIO0 7 ALT1 IN BYPASS 1000>; + mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; + mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&PIO1 2 ALT1 IN BYPASS 1000>; + mdint = <&PIO1 3 ALT1 IN BYPASS 0>; + rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; + }; + }; + + pinctrl_rgmii1: rgmii1-0 { + st,pins { + txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; + txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; + txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; + txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; + txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; + mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; + mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; + rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; + rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; + rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; + rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; + + rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; + rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; + + clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; + }; + }; + }; }; pin-controller-front { @@ -111,53 +184,73 @@ #size-cells = <1>; compatible = "st,stih415-front-pinctrl"; st,syscfg = <&syscfg_front>; + reg = <0xfee0f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfee00000 0x8000>; PIO5: gpio@fee00000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO5"; }; PIO6: gpio@fee01000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO6"; }; PIO7: gpio@fee02000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO7"; }; PIO8: gpio@fee03000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO8"; }; PIO9: gpio@fee04000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO9"; }; PIO10: gpio@fee05000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO10"; }; PIO11: gpio@fee06000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x6000 0x100>; st,bank-name = "PIO11"; }; PIO12: gpio@fee07000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; @@ -186,41 +279,57 @@ #size-cells = <1>; compatible = "st,stih415-rear-pinctrl"; st,syscfg = <&syscfg_rear>; + reg = <0xfe82f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfe820000 0x8000>; PIO13: gpio@fe820000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO13"; }; PIO14: gpio@fe821000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO14"; }; PIO15: gpio@fe822000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO15"; }; PIO16: gpio@fe823000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO16"; }; PIO17: gpio@fe824000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO17"; }; PIO18: gpio@fe825000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO18"; }; @@ -233,6 +342,77 @@ }; }; }; + + gmac0{ + pinctrl_mii0: mii0 { + st,pins { + mdint = <&PIO13 6 ALT2 IN BYPASS 0>; + txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + + txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + + txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + crs = <&PIO15 2 ALT2 IN BYPASS 1000>; + col = <&PIO15 3 ALT2 IN BYPASS 1000>; + mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; + mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; + phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; + + }; + }; + + pinctrl_gmii0: gmii0 { + st,pins { + mdint = <&PIO13 6 ALT2 IN BYPASS 0>; + mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; + mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; + txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + + txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + + txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + crs = <&PIO15 2 ALT2 IN BYPASS 1000>; + col = <&PIO15 3 ALT2 IN BYPASS 1000>; + rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + + rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + + rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; + clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; + + + }; + }; + }; }; pin-controller-left { @@ -240,23 +420,33 @@ #size-cells = <1>; compatible = "st,stih415-left-pinctrl"; st,syscfg = <&syscfg_left>; + reg = <0xfd6bf080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfd6b0000 0x3000>; PIO100: gpio@fd6b0000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO100"; }; PIO101: gpio@fd6b1000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO101"; }; PIO102: gpio@fd6b2000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO102"; }; @@ -267,35 +457,49 @@ #size-cells = <1>; compatible = "st,stih415-right-pinctrl"; st,syscfg = <&syscfg_right>; + reg = <0xfd33f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfd330000 0x5000>; PIO103: gpio@fd330000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO103"; }; PIO104: gpio@fd331000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO104"; }; PIO105: gpio@fd332000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO105"; }; PIO106: gpio@fd333000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO106"; }; PIO107: gpio@fd334000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO107"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih416-clock.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih416-clock.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih416-clock.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih416-clock.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -37,5 +37,19 @@ clock-frequency = <100000000>; clock-output-names = "CLK_S_ICN_REG_0"; }; + + CLK_S_GMAC0_PHY: clockgenA1@7 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "CLK_S_GMAC0_PHY"; + }; + + CLK_S_ETH1_PHY: clockgenA0@7 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "CLK_S_ETH1_PHY"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih416.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih416.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih416.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih416.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,7 @@ #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" #include +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -27,6 +28,16 @@ ranges; compatible = "simple-bus"; + powerdown: powerdown-controller { + #reset-cells = <1>; + compatible = "st,stih416-powerdown"; + }; + + softreset: softreset-controller { + #reset-cells = <1>; + compatible = "st,stih416-softreset"; + }; + syscfg_sbc:sbc-syscfg@fe600000{ compatible = "st,stih416-sbc-syscfg", "syscon"; reg = <0xfe600000 0x1000>; @@ -145,5 +156,73 @@ status = "disabled"; }; + + ethernet0: dwmac@fe810000 { + device_type = "network"; + compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; + status = "disabled"; + reg = <0xfe810000 0x8000>, <0x8bc 0x4>; + reg-names = "stmmaceth", "sti-ethconf"; + + interrupts = <0 133 0>, <0 134 0>, <0 135 0>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + + snps,pbl = <32>; + snps,mixed-burst; + + st,syscon = <&syscfg_rear>; + resets = <&softreset STIH416_ETH0_SOFTRESET>; + reset-names = "stmmaceth"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mii0>; + clock-names = "stmmaceth"; + clocks = <&CLK_S_GMAC0_PHY>; + }; + + ethernet1: dwmac@fef08000 { + device_type = "network"; + compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; + status = "disabled"; + reg = <0xfef08000 0x8000>, <0x7f0 0x4>; + reg-names = "stmmaceth", "sti-ethconf"; + interrupts = <0 136 0>, <0 137 0>, <0 138 0>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + + snps,pbl = <32>; + snps,mixed-burst; + + st,syscon = <&syscfg_sbc>; + + resets = <&softreset STIH416_ETH1_SOFTRESET>; + reset-names = "stmmaceth"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mii1>; + clock-names = "stmmaceth"; + clocks = <&CLK_S_ETH1_PHY>; + }; + + rc: rc@fe518000 { + compatible = "st,comms-irb"; + reg = <0xfe518000 0x234>; + interrupts = <0 203 0>; + rx-mode = "infrared"; + clocks = <&CLK_SYSIN>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + resets = <&softreset STIH416_IRB_SOFTRESET>; + }; + + /* FSM */ + spifsm: spifsm@fe902000 { + compatible = "st,spi-fsm"; + reg = <0xfe902000 0x1000>; + pinctrl-0 = <&pinctrl_fsm>; + + st,syscfg = <&syscfg_rear>; + st,boot-device-reg = <0x958>; + st,boot-device-spi = <0x1a>; + + status = "disabled"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih416-pinctrl.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih416-pinctrl.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih416-pinctrl.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih416-pinctrl.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -8,6 +8,7 @@ * publishhed by the Free Software Foundation. */ #include "st-pincfg.h" +#include / { aliases { @@ -49,46 +50,69 @@ #size-cells = <1>; compatible = "st,stih416-sbc-pinctrl"; st,syscfg = <&syscfg_sbc>; + reg = <0xfe61f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfe610000 0x6000>; PIO0: gpio@fe610000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO0"; }; PIO1: gpio@fe611000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; PIO2: gpio@fe612000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; PIO3: gpio@fe613000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; PIO4: gpio@fe614000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO4"; }; PIO40: gpio@fe615000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO40"; st,retime-pin-mask = <0x7f>; }; + rc{ + pinctrl_ir: ir0 { + st,pins { + ir = <&PIO4 0 ALT2 IN>; + }; + }; + }; sbc_serial1 { pinctrl_sbc_serial1: sbc_serial1 { st,pins { @@ -115,6 +139,58 @@ }; }; }; + + gmac1 { + pinctrl_mii1: mii1 { + st,pins { + txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&PIO0 7 ALT1 IN BYPASS 1000>; + + mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; + mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&PIO1 2 ALT1 IN BYPASS 1000>; + mdint = <&PIO1 3 ALT1 IN BYPASS 0>; + rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + + rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + pinctrl_rgmii1: rgmii1-0 { + st,pins { + txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; + txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; + txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; + txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; + txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; + + mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; + mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; + rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; + rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; + rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; + rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; + + rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; + rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; + + clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; + }; + }; + }; }; pin-controller-front { @@ -122,65 +198,89 @@ #size-cells = <1>; compatible = "st,stih416-front-pinctrl"; st,syscfg = <&syscfg_front>; + reg = <0xfee0f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfee00000 0x10000>; PIO5: gpio@fee00000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO5"; }; PIO6: gpio@fee01000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO6"; }; PIO7: gpio@fee02000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO7"; }; PIO8: gpio@fee03000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO8"; }; PIO9: gpio@fee04000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO9"; }; PIO10: gpio@fee05000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO10"; }; PIO11: gpio@fee06000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x6000 0x100>; st,bank-name = "PIO11"; }; PIO12: gpio@fee07000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; PIO30: gpio@fee08000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x8000 0x100>; st,bank-name = "PIO30"; }; PIO31: gpio@fee09000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x9000 0x100>; st,bank-name = "PIO31"; }; @@ -210,6 +310,19 @@ }; }; }; + + fsm { + pinctrl_fsm: fsm { + st,pins { + spi-fsm-clk = <&PIO12 2 ALT1 OUT>; + spi-fsm-cs = <&PIO12 3 ALT1 OUT>; + spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; + spi-fsm-miso = <&PIO12 5 ALT1 IN>; + spi-fsm-hol = <&PIO12 6 ALT1 OUT>; + spi-fsm-wp = <&PIO12 7 ALT1 OUT>; + }; + }; + }; }; pin-controller-rear { @@ -217,41 +330,57 @@ #size-cells = <1>; compatible = "st,stih416-rear-pinctrl"; st,syscfg = <&syscfg_rear>; + reg = <0xfe82f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfe820000 0x6000>; PIO13: gpio@fe820000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO13"; }; PIO14: gpio@fe821000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO14"; }; PIO15: gpio@fe822000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO15"; }; PIO16: gpio@fe823000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO16"; }; PIO17: gpio@fe824000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO17"; }; PIO18: gpio@fe825000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO18"; st,retime-pin-mask = <0xf>; @@ -265,6 +394,63 @@ }; }; }; + + gmac0 { + pinctrl_mii0: mii0 { + st,pins { + mdint = <&PIO13 6 ALT2 IN BYPASS 0>; + txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + + txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + crs = <&PIO15 2 ALT2 IN BYPASS 1000>; + col = <&PIO15 3 ALT2 IN BYPASS 1000>; + mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; + mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; + phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; + }; + }; + + pinctrl_gmii0: gmii0 { + st,pins { + }; + }; + pinctrl_rgmii0: rgmii0 { + st,pins { + phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; + txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; + txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; + txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; + txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; + txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; + txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; + + mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; + mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; + rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; + rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; + rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; + rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; + rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; + + clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; + }; + }; + }; }; pin-controller-fvdp-fe { @@ -272,23 +458,33 @@ #size-cells = <1>; compatible = "st,stih416-fvdp-fe-pinctrl"; st,syscfg = <&syscfg_fvdp_fe>; + reg = <0xfd6bf080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfd6b0000 0x3000>; PIO100: gpio@fd6b0000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO100"; }; PIO101: gpio@fd6b1000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO101"; }; PIO102: gpio@fd6b2000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO102"; }; @@ -299,29 +495,41 @@ #size-cells = <1>; compatible = "st,stih416-fvdp-lite-pinctrl"; st,syscfg = <&syscfg_fvdp_lite>; + reg = <0xfd33f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupts-names = "irqmux"; ranges = <0 0xfd330000 0x5000>; PIO103: gpio@fd330000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0 0x100>; st,bank-name = "PIO103"; }; PIO104: gpio@fd331000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x1000 0x100>; st,bank-name = "PIO104"; }; PIO105: gpio@fd332000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x2000 0x100>; st,bank-name = "PIO105"; }; PIO106: gpio@fd333000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x3000 0x100>; st,bank-name = "PIO106"; }; @@ -329,6 +537,8 @@ PIO107: gpio@fd334000 { gpio-controller; #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x4000 0x100>; st,bank-name = "PIO107"; st,retime-pin-mask = <0xf>; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih41x-b2000.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih41x-b2000.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih41x-b2000.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih41x-b2000.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -20,6 +20,8 @@ aliases { ttyAS0 = &serial2; + ethernet0 = ðernet0; + ethernet1 = ðernet1; }; soc { @@ -46,5 +48,25 @@ status = "okay"; }; + + ethernet0: dwmac@fe810000 { + status = "okay"; + phy-mode = "mii"; + pinctrl-0 = <&pinctrl_mii0>; + + snps,reset-gpio = <&PIO106 2>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + }; + + ethernet1: dwmac@fef08000 { + status = "disabled"; + phy-mode = "mii"; + st,tx-retime-src = "txclk"; + + snps,reset-gpio = <&PIO4 7>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih41x-b2020.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih41x-b2020.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih41x-b2020.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih41x-b2020.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -6,6 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. */ +#include "stih41x-b2020x.dtsi" / { memory{ device_type = "memory"; @@ -19,6 +20,7 @@ aliases { ttyAS0 = &sbc_serial1; + ethernet1 = ðernet1; }; soc { sbc_serial1: serial@fe531000 { @@ -60,5 +62,17 @@ i2c@fe541000 { status = "okay"; }; + + ethernet1: dwmac@fef08000 { + status = "okay"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + st,tx-retime-src = "clk_125"; + snps,reset-gpio = <&PIO3 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + + pinctrl-0 = <&pinctrl_rgmii1>; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/stih41x-b2020x.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/stih41x-b2020x.dtsi --- linux-3.14.1/arch/arm/boot/dts/stih41x-b2020x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/stih41x-b2020x.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Lee Jones + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/ { + soc { + spifsm: spifsm@fe902000 { + #address-cells = <1>; + #size-cells = <1>; + + status = "okay"; + + partition@0 { + label = "SerialFlash1"; + reg = <0x00000000 0x00500000>; + }; + + partition@500000 { + label = "SerialFlash2"; + reg = <0x00500000 0x00b00000>; + }; + }; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10-a1000.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-a1000.dts --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10-a1000.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-a1000.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ /dts-v1/; /include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Mele A1000"; @@ -35,6 +36,32 @@ }; }; + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + pinctrl@01c20800 { emac_power_pin_a1000: emac_power_pin@0 { allwinner,pins = "PH15"; @@ -80,18 +107,22 @@ }; }; - regulators { - compatible = "simple-bus"; + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&emac_power_pin_a1000>; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 15 0>; + }; - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_a1000>; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 15 0>; - }; + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10-cubieboard.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-cubieboard.dts --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10-cubieboard.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-cubieboard.dts 2014-04-13 23:18:35.000000000 +0200 @@ -12,6 +12,7 @@ /dts-v1/; /include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Cubietech Cubieboard"; @@ -33,6 +34,33 @@ }; }; + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + pinctrl@01c20800 { led_pins_cubieboard: led_pins@0 { allwinner,pins = "PH20", "PH21"; @@ -77,4 +105,16 @@ linux,default-trigger = "heartbeat"; }; }; + + reg_ahci_5v: ahci-5v { + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10.dtsi --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -19,6 +19,12 @@ ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; }; cpus { @@ -52,44 +58,48 @@ clock-frequency = <0>; }; - osc24M: osc24M@01c20050 { + osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; - osc32k: osc32k { + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1@01c20000 { + pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4@01c20018 { + pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5@01c20020 { + pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6@01c20028 { + pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -98,21 +108,23 @@ /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; }; axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; + clock-output-names = "axi"; }; - axi_gates: axi_gates@01c2005c { + axi_gates: clk@01c2005c { #clock-cells = <1>; - compatible = "allwinner,sun4i-axi-gates-clk"; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; clock-output-names = "axi_dram"; @@ -120,14 +132,15 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; + clock-output-names = "ahb"; }; - ahb_gates: ahb_gates@01c20060 { + ahb_gates: clk@01c20060 { #clock-cells = <1>; - compatible = "allwinner,sun4i-ahb-gates-clk"; + compatible = "allwinner,sun4i-a10-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; clock-output-names = "ahb_usb0", "ahb_ehci0", @@ -145,14 +158,15 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; + clock-output-names = "apb0"; }; - apb0_gates: apb0_gates@01c20068 { + apb0_gates: clk@01c20068 { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb0-gates-clk"; + compatible = "allwinner,sun4i-a10-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; clock-output-names = "apb0_codec", "apb0_spdif", @@ -162,21 +176,23 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1_mux"; }; apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; + clock-output-names = "apb1"; }; - apb1_gates: apb1_gates@01c2006c { + apb1_gates: clk@01c2006c { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb1-gates-clk"; + compatible = "allwinner,sun4i-a10-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; clock-output-names = "apb1_i2c0", "apb1_i2c1", @@ -189,7 +205,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -197,7 +213,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -205,7 +221,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -213,7 +229,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -221,7 +237,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -229,7 +245,7 @@ mmc3_clk: clk@01c20094 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20094 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc3"; @@ -237,7 +253,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -245,7 +261,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -253,7 +269,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -261,7 +277,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -269,7 +285,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -277,7 +293,7 @@ pata_clk: clk@01c200ac { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "pata"; @@ -285,7 +301,7 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; @@ -293,15 +309,24 @@ ir1_clk: clk@01c200b4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir1"; }; + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + }; + spi3_clk: clk@01c200d4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200d4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi3"; @@ -314,6 +339,28 @@ #size-cells = <1>; ranges; + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; @@ -330,8 +377,90 @@ #size-cells = <0>; }; + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>, <&usb_clk 2>; + reset-names = "usb1_reset", "usb2_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <64>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@01c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <56>; + clocks = <&pll6 0>, <&ahb_gates 25>; + status = "disabled"; + }; + + ehci1: usb@01c1c000 { + compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <40>; + clocks = <&ahb_gates 3>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1c400 { + compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <65>; + clocks = <&usb_clk 7>, <&ahb_gates 4>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + spi3: spi@01c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <50>; + clocks = <&ahb_gates 23>, <&spi3_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-ic"; + compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; @@ -403,25 +532,25 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>; }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; rtc: rtc@01c20d00 { - compatible = "allwinner,sun4i-rtc"; + compatible = "allwinner,sun4i-a10-rtc"; reg = <0x01c20d00 0x20>; interrupts = <24>; }; sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-sid"; + compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10-hackberry.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-hackberry.dts --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10-hackberry.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-hackberry.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ /dts-v1/; /include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Miniand Hackberry"; @@ -35,6 +36,28 @@ }; }; + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + pio: pinctrl@01c20800 { pinctrl-names = "default"; pinctrl-0 = <&hackberry_hogs>; @@ -45,6 +68,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; uart0: serial@01c28000 { @@ -54,16 +84,22 @@ }; }; - regulators { - compatible = "simple-bus"; + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 19 0>; + }; - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 19 0>; - }; + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + pinctrl-0 = <&usb2_vbus_pin_hackberry>; + gpio = <&pio 7 12 0>; + status = "okay"; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,69 @@ +/* + * Copyright 2014 Open Source Support GmbH + * + * David Lanzendörfer + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "INet-97F Rev 02"; + compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + soc@01c00000 { + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,16 +13,47 @@ /dts-v1/; /include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "PineRiver Mini X-Plus"; compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; soc@01c00000 { + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,111 @@ +/* + * Copyright 2014 - Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Olimex A10-OLinuXino-LIME"; + compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; + + soc@01c00000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + led_pins_olinuxinolime: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; + + green { + label = "a10-olinuxino-lime:green:usr"; + gpios = <&pio 7 2 0>; + default-state = "on"; + }; + }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; + gpio = <&pio 2 3 0>; + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun4i-a10-pcduino.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-pcduino.dts --- linux-3.14.1/arch/arm/boot/dts/sun4i-a10-pcduino.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun4i-a10-pcduino.dts 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,79 @@ +/* + * Copyright 2014 Zoltan HERPAI + * Zoltan HERPAI + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "LinkSprite pcDuino"; + compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; + + soc@01c00000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun5i-a10s.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a10s.dtsi --- linux-3.14.1/arch/arm/boot/dts/sun5i-a10s.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a10s.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -18,6 +18,10 @@ aliases { ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; }; cpus { @@ -47,44 +51,48 @@ clock-frequency = <0>; }; - osc24M: osc24M@01c20050 { + osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; - osc32k: osc32k { + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1@01c20000 { + pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4@01c20018 { + pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5@01c20020 { + pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6@01c20028 { + pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -93,21 +101,23 @@ /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; }; axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; + clock-output-names = "axi"; }; - axi_gates: axi_gates@01c2005c { + axi_gates: clk@01c2005c { #clock-cells = <1>; - compatible = "allwinner,sun4i-axi-gates-clk"; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; clock-output-names = "axi_dram"; @@ -115,12 +125,13 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; + clock-output-names = "ahb"; }; - ahb_gates: ahb_gates@01c20060 { + ahb_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; reg = <0x01c20060 0x8>; @@ -136,12 +147,13 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; + clock-output-names = "apb0"; }; - apb0_gates: apb0_gates@01c20068 { + apb0_gates: clk@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; reg = <0x01c20068 0x4>; @@ -152,19 +164,21 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1_mux"; }; apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; + clock-output-names = "apb1"; }; - apb1_gates: apb1_gates@01c2006c { + apb1_gates: clk@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; reg = <0x01c2006c 0x4>; @@ -176,7 +190,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -184,7 +198,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -192,7 +206,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -200,7 +214,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -208,7 +222,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -216,7 +230,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -224,7 +238,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -232,7 +246,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -240,7 +254,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -248,7 +262,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -256,15 +270,24 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; }; + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mbus"; @@ -277,6 +300,28 @@ #size-cells = <1>; ranges; + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; @@ -293,8 +338,51 @@ #size-cells = <0>; }; + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>; + reset-names = "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-ic"; + compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; @@ -366,19 +454,19 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>; }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-sid"; + compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts --- linux-3.14.1/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ /dts-v1/; /include/ "sun5i-a10s.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Olimex A10s-Olinuxino Micro"; @@ -34,6 +35,19 @@ }; }; + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + pinctrl@01c20800 { led_pins_olinuxino: led_pins@0 { allwinner,pins = "PE3"; @@ -41,6 +55,13 @@ allwinner,drive = <1>; allwinner,pull = <0>; }; + + usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { + allwinner,pins = "PB10"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; uart0: serial@01c28000 { @@ -98,4 +119,10 @@ default-state = "on"; }; }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>; + gpio = <&pio 1 10 0>; + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun5i-a13.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a13.dtsi --- linux-3.14.1/arch/arm/boot/dts/sun5i-a13.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a13.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -16,6 +16,11 @@ / { interrupt-parent = <&intc>; + aliases { + serial0 = &uart1; + serial1 = &uart3; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -47,44 +52,48 @@ clock-frequency = <0>; }; - osc24M: osc24M@01c20050 { + osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; - osc32k: osc32k { + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1@01c20000 { + pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4@01c20018 { + pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5@01c20020 { + pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6@01c20028 { + pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -93,21 +102,23 @@ /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; }; axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; + clock-output-names = "axi"; }; - axi_gates: axi_gates@01c2005c { + axi_gates: clk@01c2005c { #clock-cells = <1>; - compatible = "allwinner,sun4i-axi-gates-clk"; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; clock-output-names = "axi_dram"; @@ -115,12 +126,13 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; + clock-output-names = "ahb"; }; - ahb_gates: ahb_gates@01c20060 { + ahb_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun5i-a13-ahb-gates-clk"; reg = <0x01c20060 0x8>; @@ -135,12 +147,13 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; + clock-output-names = "apb0"; }; - apb0_gates: apb0_gates@01c20068 { + apb0_gates: clk@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun5i-a13-apb0-gates-clk"; reg = <0x01c20068 0x4>; @@ -150,19 +163,21 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1_mux"; }; apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; + clock-output-names = "apb1"; }; - apb1_gates: apb1_gates@01c2006c { + apb1_gates: clk@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun5i-a13-apb1-gates-clk"; reg = <0x01c2006c 0x4>; @@ -173,7 +188,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -181,7 +196,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -189,7 +204,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -197,7 +212,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -205,7 +220,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -213,7 +228,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -221,7 +236,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -229,7 +244,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -237,7 +252,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -245,7 +260,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -253,15 +268,24 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; }; + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mbus"; @@ -274,8 +298,73 @@ #size-cells = <1>; ranges; + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>; + reset-names = "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-ic"; + compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; @@ -329,19 +418,19 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>; }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-sid"; + compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun5i-a13-olinuxino.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a13-olinuxino.dts --- linux-3.14.1/arch/arm/boot/dts/sun5i-a13-olinuxino.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a13-olinuxino.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,12 +13,26 @@ /dts-v1/; /include/ "sun5i-a13.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Olimex A13-Olinuxino"; compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; soc@01c00000 { + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + pinctrl@01c20800 { led_pins_olinuxino: led_pins@0 { allwinner,pins = "PG9"; @@ -26,6 +40,13 @@ allwinner,drive = <1>; allwinner,pull = <0>; }; + + usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { + allwinner,pins = "PG11"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; uart1: serial@01c28400 { @@ -63,4 +84,10 @@ default-state = "on"; }; }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_olinuxino>; + gpio = <&pio 6 11 0>; + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts --- linux-3.14.1/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts 2014-04-13 23:18:35.000000000 +0200 @@ -14,12 +14,26 @@ /dts-v1/; /include/ "sun5i-a13.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Olimex A13-Olinuxino Micro"; compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; soc@01c00000 { + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + pinctrl@01c20800 { led_pins_olinuxinom: led_pins@0 { allwinner,pins = "PG9"; @@ -27,6 +41,13 @@ allwinner,drive = <1>; allwinner,pull = <0>; }; + + usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { + allwinner,pins = "PG11"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; uart1: serial@01c28400 { @@ -65,4 +86,10 @@ default-state = "on"; }; }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; + gpio = <&pio 6 11 0>; + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun6i-a31-colombus.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun6i-a31-colombus.dts --- linux-3.14.1/arch/arm/boot/dts/sun6i-a31-colombus.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun6i-a31-colombus.dts 2014-04-13 23:18:35.000000000 +0200 @@ -28,5 +28,23 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "fail"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun6i-a31.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sun6i-a31.dtsi --- linux-3.14.1/arch/arm/boot/dts/sun6i-a31.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun6i-a31.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -16,6 +16,16 @@ / { interrupt-parent = <&gic>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + cpus { #address-cells = <1>; #size-cells = <0>; @@ -60,34 +70,32 @@ clock-frequency = <24000000>; }; - osc32k: osc32k { + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1@01c20000 { + pll1: clk@01c20000 { #clock-cells = <0>; compatible = "allwinner,sun6i-a31-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - pll6: pll6 { + pll6: clk@01c20028 { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6"; }; cpu: cpu@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20050 0x4>; /* @@ -97,13 +105,15 @@ * Allwinner. */ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; }; axi: axi@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20050 0x4>; clocks = <&cpu>; + clock-output-names = "axi"; }; ahb1_mux: ahb1_mux@01c20054 { @@ -111,16 +121,18 @@ compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; + clock-output-names = "ahb1_mux"; }; ahb1: ahb1@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb1_mux>; + clock-output-names = "ahb1"; }; - ahb1_gates: ahb1_gates@01c20060 { + ahb1_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; reg = <0x01c20060 0x8>; @@ -143,12 +155,13 @@ apb1: apb1@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb1>; + clock-output-names = "apb1"; }; - apb1_gates: apb1_gates@01c20060 { + apb1_gates: clk@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb1-gates-clk"; reg = <0x01c20068 0x4>; @@ -160,9 +173,10 @@ apb2_mux: apb2_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "apb2_mux"; }; apb2: apb2@01c20058 { @@ -170,9 +184,10 @@ compatible = "allwinner,sun6i-a31-apb2-div-clk"; reg = <0x01c20058 0x4>; clocks = <&apb2_mux>; + clock-output-names = "apb2"; }; - apb2_gates: apb2_gates@01c2006c { + apb2_gates: clk@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb2-gates-clk"; reg = <0x01c2006c 0x4>; @@ -182,6 +197,38 @@ "apb2_uart1", "apb2_uart2", "apb2_uart3", "apb2_uart4", "apb2_uart5"; }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi2"; + }; + + spi3_clk: clk@01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi3"; + }; }; soc@01c00000 { @@ -190,6 +237,14 @@ #size-cells = <1>; ranges; + nmi_intc: interrupt-controller@01f00c0c { + compatible = "allwinner,sun6i-a31-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c0c 0x38>; + interrupts = <0 32 4>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; @@ -210,6 +265,27 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PH14", "PH15"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PH16", "PH17"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PH18", "PH19"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { @@ -231,7 +307,7 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <0 18 4>, <0 19 4>, @@ -242,7 +318,7 @@ }; wdt1: watchdog@01c20ca0 { - compatible = "allwinner,sun6i-wdt"; + compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; }; @@ -312,6 +388,86 @@ status = "disabled"; }; + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <0 6 4>; + clocks = <&apb2_gates 0>; + clock-frequency = <100000>; + resets = <&apb2_rst 0>; + status = "disabled"; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <0 7 4>; + clocks = <&apb2_gates 1>; + clock-frequency = <100000>; + resets = <&apb2_rst 1>; + status = "disabled"; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <0 8 4>; + clocks = <&apb2_gates 2>; + clock-frequency = <100000>; + resets = <&apb2_rst 2>; + status = "disabled"; + }; + + i2c3: i2c@01c2b800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = <0 9 4>; + clocks = <&apb2_gates 3>; + clock-frequency = <100000>; + resets = <&apb2_rst 3>; + status = "disabled"; + }; + + spi0: spi@01c68000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <0 65 4>; + clocks = <&ahb1_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 20>; + status = "disabled"; + }; + + spi1: spi@01c69000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c69000 0x1000>; + interrupts = <0 66 4>; + clocks = <&ahb1_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 21>; + status = "disabled"; + }; + + spi2: spi@01c6a000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c6a000 0x1000>; + interrupts = <0 67 4>; + clocks = <&ahb1_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 22>; + status = "disabled"; + }; + + spi3: spi@01c6b000 { + compatible = "allwinner,sun6i-a31-spi"; + reg = <0x01c6b000 0x1000>; + interrupts = <0 68 4>; + clocks = <&ahb1_gates 23>, <&spi3_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 23>; + status = "disabled"; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff -Nur linux-3.14.1/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts --- linux-3.14.1/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,25 +13,38 @@ /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Cubietech Cubieboard2"; compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; }; - mdio@01c0b080 { + ehci0: usb@01c14000 { status = "okay"; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; }; pinctrl@01c20800 { @@ -60,6 +73,18 @@ pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; }; leds { @@ -77,4 +102,16 @@ gpios = <&pio 7 20 0>; }; }; + + reg_ahci_5v: ahci-5v { + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun7i-a20-cubietruck.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20-cubietruck.dts --- linux-3.14.1/arch/arm/boot/dts/sun7i-a20-cubietruck.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20-cubietruck.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,13 +13,48 @@ /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Cubietech Cubietruck"; compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; soc@01c00000 { + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + pinctrl@01c20800 { + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + led_pins_cubietruck: led_pins@0 { allwinner,pins = "PH7", "PH11", "PH20", "PH21"; allwinner,function = "gpio_out"; @@ -51,6 +86,18 @@ pinctrl-0 = <&i2c2_pins_a>; status = "okay"; }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; }; leds { @@ -78,4 +125,18 @@ gpios = <&pio 7 7 0>; }; }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_cubietruck>; + gpio = <&pio 7 12 0>; + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun7i-a20.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20.dtsi --- linux-3.14.1/arch/arm/boot/dts/sun7i-a20.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -17,7 +17,15 @@ interrupt-parent = <&gic>; aliases { - ethernet0 = &emac; + ethernet0 = &gmac; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; }; cpus { @@ -41,16 +49,25 @@ reg = <0x40000000 0x80000000>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; ranges; - osc24M: osc24M@01c20050 { + osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; osc32k: clk@0 { @@ -60,31 +77,33 @@ clock-output-names = "osc32k"; }; - pll1: pll1@01c20000 { + pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4@01c20018 { + pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5@01c20020 { + pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6@01c20028 { + pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -92,26 +111,29 @@ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; + clock-output-names = "cpu"; }; axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; + clock-output-names = "axi"; }; ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; + clock-output-names = "ahb"; }; - ahb_gates: ahb_gates@01c20060 { + ahb_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-ahb-gates-clk"; reg = <0x01c20060 0x8>; @@ -133,12 +155,13 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; + clock-output-names = "apb0"; }; - apb0_gates: apb0_gates@01c20068 { + apb0_gates: clk@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb0-gates-clk"; reg = <0x01c20068 0x4>; @@ -151,19 +174,21 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1_mux"; }; apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; + clock-output-names = "apb1"; }; - apb1_gates: apb1_gates@01c2006c { + apb1_gates: clk@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb1-gates-clk"; reg = <0x01c2006c 0x4>; @@ -178,7 +203,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -186,7 +211,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -194,7 +219,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -202,7 +227,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -210,7 +235,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -218,7 +243,7 @@ mmc3_clk: clk@01c20094 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20094 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc3"; @@ -226,7 +251,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -234,7 +259,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -242,7 +267,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -250,7 +275,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -258,7 +283,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -266,7 +291,7 @@ pata_clk: clk@01c200ac { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "pata"; @@ -274,7 +299,7 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; @@ -282,15 +307,24 @@ ir1_clk: clk@01c200b4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir1"; }; + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + }; + spi3_clk: clk@01c200d4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200d4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi3"; @@ -298,13 +332,41 @@ mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; clock-output-names = "mbus"; }; /* + * The following two are dummy clocks, placeholders used in the gmac_tx + * clock. The gmac driver will choose one parent depending on the PHY + * interface mode, using clk_set_rate auto-reparenting. + * The actual TX clock rate is not controlled by the gmac_tx clock. + */ + mii_phy_tx_clk: clk@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: clk@3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@01c20164 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c20164 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + + /* * Dummy clock used by output clocks */ osc24M_32k: clk@1 { @@ -339,6 +401,36 @@ #size-cells = <1>; ranges; + nmi_intc: interrupt-controller@01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = <0 0 4>; + }; + + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <0 10 4>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <0 11 4>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; @@ -355,6 +447,88 @@ #size-cells = <0>; }; + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun7i-a20-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>, <&usb_clk 2>; + reset-names = "usb1_reset", "usb2_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <0 39 4>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <0 64 4>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <0 12 4>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@01c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <0 56 4>; + clocks = <&pll6 0>, <&ahb_gates 25>; + status = "disabled"; + }; + + ehci1: usb@01c1c000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <0 40 4>; + clocks = <&ahb_gates 3>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1c400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <0 65 4>; + clocks = <&usb_clk 7>, <&ahb_gates 4>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + spi3: spi@01c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb_gates 23>, <&spi3_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; @@ -373,6 +547,13 @@ allwinner,pull = <0>; }; + uart2_pins_a: uart2@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "uart2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart6_pins_a: uart6@0 { allwinner,pins = "PI12", "PI13"; allwinner,function = "uart6"; @@ -432,10 +613,50 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "gmac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = <3>; + allwinner,pull = <0>; + }; + + spi1_pins_a: spi1@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "spi1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + spi2_pins_a: spi2@0 { + allwinner,pins = "PC19", "PC20", "PC21", "PC22"; + allwinner,function = "spi2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <0 22 4>, <0 23 4>, @@ -447,7 +668,7 @@ }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; @@ -593,6 +814,21 @@ status = "disabled"; }; + gmac: ethernet@01c50000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x01c50000 0x10000>; + interrupts = <0 85 4>; + interrupt-names = "macirq"; + clocks = <&ahb_gates 49>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + hstimer@01c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; diff -Nur linux-3.14.1/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts --- linux-3.14.1/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts 2014-04-13 23:18:35.000000000 +0200 @@ -13,25 +13,55 @@ /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Olimex A20-Olinuxino Micro"; compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; + aliases { + spi0 = &spi1; + spi1 = &spi2; + }; + soc@01c00000 { - emac: ethernet@01c0b000 { + spi1: spi@01c06000 { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; + pinctrl-0 = <&spi1_pins_a>; status = "okay"; }; - mdio@01c0b080 { + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + spi2: spi@01c17000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; }; pinctrl@01c20800 { @@ -78,6 +108,18 @@ pinctrl-0 = <&i2c2_pins_a>; status = "okay"; }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; }; leds { @@ -91,4 +133,16 @@ default-state = "on"; }; }; + + reg_ahci_5v: ahci-5v { + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/sunxi-common-regulators.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/sunxi-common-regulators.dtsi --- linux-3.14.1/arch/arm/boot/dts/sunxi-common-regulators.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/sunxi-common-regulators.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,75 @@ +/* + * sunxi boards common regulator (ahci target power supply, usb-vbus) code + * + * Copyright 2014 - Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + soc@01c00000 { + pio: pinctrl@01c20800 { + ahci_pwr_pin_a: ahci_pwr_pin@0 { + allwinner,pins = "PB8"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + usb1_vbus_pin_a: usb1_vbus_pin@0 { + allwinner,pins = "PH6"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + usb2_vbus_pin_a: usb2_vbus_pin@0 { + allwinner,pins = "PH3"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + }; + + reg_ahci_5v: ahci-5v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&ahci_pwr_pin_a>; + regulator-name = "ahci-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 1 8 0>; + status = "disabled"; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_a>; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 6 0>; + status = "disabled"; + }; + + reg_usb2_vbus: usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_pin_a>; + regulator-name = "usb2-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 3 0>; + status = "disabled"; + }; +}; diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra114-dalmore.dts linux-3.15-rc1.orig/arch/arm/boot/dts/tegra114-dalmore.dts --- linux-3.14.1/arch/arm/boot/dts/tegra114-dalmore.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra114-dalmore.dts 2014-04-13 23:18:35.000000000 +0200 @@ -1,3 +1,8 @@ +/* + * This dts file supports Dalmore A04. + * Other board revisions are not supported + */ + /dts-v1/; #include @@ -715,7 +720,6 @@ nvidia,pins = "drive_sdio1"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <36>; nvidia,pull-up-strength = <20>; nvidia,slew-rate-rising = ; @@ -725,7 +729,6 @@ nvidia,pins = "drive_sdio3"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <22>; nvidia,pull-up-strength = <36>; nvidia,slew-rate-rising = ; @@ -735,12 +738,10 @@ nvidia,pins = "drive_gma"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <2>; nvidia,pull-up-strength = <1>; nvidia,slew-rate-rising = ; nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra114.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/tegra114.dtsi --- linux-3.14.1/arch/arm/boot/dts/tegra114.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra114.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -604,7 +604,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; resets = <&tegra_car 14>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@78000200 { @@ -614,7 +614,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; resets = <&tegra_car 9>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@78000400 { @@ -624,7 +624,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; resets = <&tegra_car 69>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@78000600 { @@ -634,7 +634,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; resets = <&tegra_car 15>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; usb@7d000000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra124.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/tegra124.dtsi --- linux-3.14.1/arch/arm/boot/dts/tegra124.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra124.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -8,22 +8,91 @@ / { compatible = "nvidia,tegra124"; interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; - gic: interrupt-controller@50041000 { + host1x@0,50000000 { + compatible = "nvidia,tegra124-host1x", "simple-bus"; + reg = <0x0 0x50000000 0x0 0x00034000>; + interrupts = , /* syncpt */ + ; /* general */ + clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; + + dc@0,54200000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x0 0x54200000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DISP1>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + nvidia,head = <0>; + }; + + dc@0,54240000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x0 0x54240000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DISP2>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + nvidia,head = <1>; + }; + + sor@0,54540000 { + compatible = "nvidia,tegra124-sor"; + reg = <0x0 0x54540000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA124_CLK_PLL_DP>, + <&tegra_car TEGRA124_CLK_CLK_M>; + clock-names = "sor", "parent", "dp", "safe"; + resets = <&tegra_car 182>; + reset-names = "sor"; + status = "disabled"; + }; + + dpaux@0,545c0000 { + compatible = "nvidia,tegra124-dpaux"; + reg = <0x0 0x545c0000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DPAUX>, + <&tegra_car TEGRA124_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 181>; + reset-names = "dpaux"; + status = "disabled"; + }; + }; + + gic: interrupt-controller@0,50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x50041000 0x1000>, - <0x50042000 0x1000>, - <0x50044000 0x2000>, - <0x50046000 0x2000>; + reg = <0x0 0x50041000 0x0 0x1000>, + <0x0 0x50042000 0x0 0x1000>, + <0x0 0x50044000 0x0 0x2000>, + <0x0 0x50046000 0x0 0x2000>; interrupts = ; }; - timer@60005000 { + timer@0,60005000 { compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; + reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , , @@ -33,16 +102,16 @@ clocks = <&tegra_car TEGRA124_CLK_TIMER>; }; - tegra_car: clock@60006000 { + tegra_car: clock@0,60006000 { compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; + reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - gpio: gpio@6000d000 { + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; + reg = <0x0 0x6000d000 0x0 0x1000>; interrupts = , , , @@ -57,9 +126,9 @@ interrupt-controller; }; - apbdma: dma@60020000 { + apbdma: dma@0,60020000 { compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x60020000 0x1400>; + reg = <0x0 0x60020000 0x0 0x1400>; interrupts = , , , @@ -98,10 +167,10 @@ #dma-cells = <1>; }; - pinmux: pinmux@70000868 { + pinmux: pinmux@0,70000868 { compatible = "nvidia,tegra124-pinmux"; - reg = <0x70000868 0x164>, /* Pad control registers */ - <0x70003000 0x434>; /* Mux registers */ + reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ + <0x0 0x70003000 0x0 0x434>; /* Mux registers */ }; /* @@ -112,9 +181,9 @@ * the APB DMA based serial driver, the comptible is * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". */ - serial@70006000 { + serial@0,70006000 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; + reg = <0x0 0x70006000 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTA>; @@ -125,9 +194,9 @@ status = "disabled"; }; - serial@70006040 { + serial@0,70006040 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; + reg = <0x0 0x70006040 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTB>; @@ -138,9 +207,9 @@ status = "disabled"; }; - serial@70006200 { + serial@0,70006200 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x40>; + reg = <0x0 0x70006200 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTC>; @@ -151,9 +220,9 @@ status = "disabled"; }; - serial@70006300 { + serial@0,70006300 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x40>; + reg = <0x0 0x70006300 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTD>; @@ -164,9 +233,9 @@ status = "disabled"; }; - serial@70006400 { + serial@0,70006400 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x40>; + reg = <0x0 0x70006400 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTE>; @@ -177,9 +246,9 @@ status = "disabled"; }; - pwm@7000a000 { + pwm@0,7000a000 { compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; + reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA124_CLK_PWM>; resets = <&tegra_car 17>; @@ -187,9 +256,9 @@ status = "disabled"; }; - i2c@7000c000 { + i2c@0,7000c000 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; + reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -202,9 +271,9 @@ status = "disabled"; }; - i2c@7000c400 { + i2c@0,7000c400 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; + reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -217,9 +286,9 @@ status = "disabled"; }; - i2c@7000c500 { + i2c@0,7000c500 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; + reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -232,9 +301,9 @@ status = "disabled"; }; - i2c@7000c700 { + i2c@0,7000c700 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; + reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -247,9 +316,9 @@ status = "disabled"; }; - i2c@7000d000 { + i2c@0,7000d000 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; + reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -262,9 +331,9 @@ status = "disabled"; }; - i2c@7000d100 { + i2c@0,7000d100 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000d100 0x100>; + reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -277,9 +346,9 @@ status = "disabled"; }; - spi@7000d400 { + spi@0,7000d400 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000d400 0x200>; + reg = <0x0 0x7000d400 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -292,9 +361,9 @@ status = "disabled"; }; - spi@7000d600 { + spi@0,7000d600 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; + reg = <0x0 0x7000d600 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -307,9 +376,9 @@ status = "disabled"; }; - spi@7000d800 { + spi@0,7000d800 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000d800 0x200>; + reg = <0x0 0x7000d800 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -322,9 +391,9 @@ status = "disabled"; }; - spi@7000da00 { + spi@0,7000da00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000da00 0x200>; + reg = <0x0 0x7000da00 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -337,9 +406,9 @@ status = "disabled"; }; - spi@7000dc00 { + spi@0,7000dc00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000dc00 0x200>; + reg = <0x0 0x7000dc00 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -352,9 +421,9 @@ status = "disabled"; }; - spi@7000de00 { + spi@0,7000de00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000de00 0x200>; + reg = <0x0 0x7000de00 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -367,65 +436,65 @@ status = "disabled"; }; - rtc@7000e000 { + rtc@0,7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; + reg = <0x0 0x7000e000 0x0 0x100>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_RTC>; }; - pmc@7000e400 { + pmc@0,7000e400 { compatible = "nvidia,tegra124-pmc"; - reg = <0x7000e400 0x400>; + reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; - sdhci@700b0000 { + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0000 0x200>; + reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; resets = <&tegra_car 14>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; - sdhci@700b0200 { + sdhci@0,700b0200 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0200 0x200>; + reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; resets = <&tegra_car 9>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; - sdhci@700b0400 { + sdhci@0,700b0400 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0400 0x200>; + reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; resets = <&tegra_car 69>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; - sdhci@700b0600 { + sdhci@0,700b0600 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0600 0x200>; + reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; resets = <&tegra_car 15>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; - ahub@70300000 { + ahub@0,70300000 { compatible = "nvidia,tegra124-ahub"; - reg = <0x70300000 0x200>, - <0x70300800 0x800>, - <0x70300200 0x600>; + reg = <0x0 0x70300000 0x0 0x200>, + <0x0 0x70300800 0x0 0x800>, + <0x0 0x70300200 0x0 0x600>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, <&tegra_car TEGRA124_CLK_APBIF>; @@ -470,12 +539,12 @@ "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9"; ranges; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; - tegra_i2s0: i2s@70301000 { + tegra_i2s0: i2s@0,70301000 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301000 0x100>; + reg = <0x0 0x70301000 0x0 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA124_CLK_I2S0>; resets = <&tegra_car 30>; @@ -483,9 +552,9 @@ status = "disabled"; }; - tegra_i2s1: i2s@70301100 { + tegra_i2s1: i2s@0,70301100 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301100 0x100>; + reg = <0x0 0x70301100 0x0 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA124_CLK_I2S1>; resets = <&tegra_car 11>; @@ -493,9 +562,9 @@ status = "disabled"; }; - tegra_i2s2: i2s@70301200 { + tegra_i2s2: i2s@0,70301200 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301200 0x100>; + reg = <0x0 0x70301200 0x0 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA124_CLK_I2S2>; resets = <&tegra_car 18>; @@ -503,9 +572,9 @@ status = "disabled"; }; - tegra_i2s3: i2s@70301300 { + tegra_i2s3: i2s@0,70301300 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301300 0x100>; + reg = <0x0 0x70301300 0x0 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA124_CLK_I2S3>; resets = <&tegra_car 101>; @@ -513,9 +582,9 @@ status = "disabled"; }; - tegra_i2s4: i2s@70301400 { + tegra_i2s4: i2s@0,70301400 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301400 0x100>; + reg = <0x0 0x70301400 0x0 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA124_CLK_I2S4>; resets = <&tegra_car 102>; @@ -524,6 +593,108 @@ }; }; + usb@0,7d000000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@0,7d000000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d000000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + + usb@0,7d004000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x0 0x7d004000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + status = "disabled"; + }; + + phy2: usb-phy@0,7d004000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d004000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB2>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + + usb@0,7d008000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x0 0x7d008000 0x0 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@0,7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d008000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra124-venice2.dts linux-3.15-rc1.orig/arch/arm/boot/dts/tegra124-venice2.dts --- linux-3.14.1/arch/arm/boot/dts/tegra124-venice2.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra124-venice2.dts 2014-04-13 23:18:35.000000000 +0200 @@ -8,15 +8,29 @@ compatible = "nvidia,venice2", "nvidia,tegra124"; aliases { - rtc0 = "/i2c@7000d000/as3722@40"; - rtc1 = "/rtc@7000e000"; + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; }; memory { - reg = <0x80000000 0x80000000>; + reg = <0x0 0x80000000 0x0 0x80000000>; }; - pinmux: pinmux@70000868 { + host1x@0,50000000 { + sor@0,54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux: dpaux@0,545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + pinmux: pinmux@0,70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -138,14 +152,9 @@ nvidia,enable-input = ; }; sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; + nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,enable-input = ; + nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; @@ -402,19 +411,11 @@ nvidia,enable-input = ; }; usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; nvidia,function = "usb"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,enable-input = ; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,lock = ; nvidia,open-drain = ; @@ -423,7 +424,6 @@ nvidia,pins = "drive_sdio1"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <32>; nvidia,pull-up-strength = <42>; nvidia,slew-rate-rising = ; @@ -433,7 +433,6 @@ nvidia,pins = "drive_sdio3"; nvidia,high-speed-mode = ; nvidia,schmitt = ; - nvidia,low-power-mode = ; nvidia,pull-down-strength = <20>; nvidia,pull-up-strength = <36>; nvidia,slew-rate-rising = ; @@ -572,15 +571,15 @@ }; }; - serial@70006000 { + serial@0,70006000 { status = "okay"; }; - pwm: pwm@7000a000 { + pwm: pwm@0,7000a000 { status = "okay"; }; - i2c@7000c000 { + i2c@0,7000c000 { status = "okay"; clock-frequency = <100000>; @@ -592,30 +591,32 @@ }; }; - i2c@7000c400 { + i2c@0,7000c400 { status = "okay"; clock-frequency = <100000>; }; - i2c@7000c500 { + i2c@0,7000c500 { status = "okay"; clock-frequency = <100000>; }; - i2c@7000c700 { + i2c@0,7000c700 { status = "okay"; clock-frequency = <100000>; }; - i2c@7000d000 { + i2c@0,7000d000 { status = "okay"; clock-frequency = <400000>; - as3722: as3722@40 { + pmic: pmic@40 { compatible = "ams,as3722"; reg = <0x40>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + ams,system-power-controller; + #interrupt-cells = <2>; interrupt-controller; @@ -650,19 +651,19 @@ }; regulators { - vsup-sd2-supply = <&vdd_ac_bat_reg>; - vsup-sd3-supply = <&vdd_ac_bat_reg>; - vsup-sd4-supply = <&vdd_ac_bat_reg>; - vsup-sd5-supply = <&vdd_ac_bat_reg>; - vin-ldo0-supply = <&as3722_sd2>; - vin-ldo1-6-supply = <&vdd_ac_bat_reg>; - vin-ldo2-5-7-supply = <&as3722_sd5>; - vin-ldo3-4-supply = <&vdd_ac_bat_reg>; - vin-ldo9-10-supply = <&vdd_ac_bat_reg>; - vin-ldo11-supply = <&vdd_ac_bat_reg>; + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; sd0 { - regulator-name = "vdd-cpu"; + regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; regulator-min-microamp = <3500000>; @@ -673,7 +674,7 @@ }; sd1 { - regulator-name = "vdd-core"; + regulator-name = "+VDD_CORE"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; regulator-min-microamp = <2500000>; @@ -683,8 +684,8 @@ ams,external-control = <1>; }; - as3722_sd2: sd2 { - regulator-name = "vddio-ddr"; + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -692,7 +693,7 @@ }; sd3 { - regulator-name = "vddio-ddr-2phase"; + regulator-name = "+1.35V_LP0(sd3)"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -700,15 +701,13 @@ }; sd4 { - regulator-name = "avdd-pex-sata"; + regulator-name = "+1.05V_RUN"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; }; - as3722_sd5: sd5 { - regulator-name = "vddio-sys"; + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -716,7 +715,7 @@ }; sd6 { - regulator-name = "vdd-gpu"; + regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; regulator-min-microamp = <3500000>; @@ -726,7 +725,7 @@ }; ldo0 { - regulator-name = "avdd_pll"; + regulator-name = "+1.05V_RUN_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-boot-on; @@ -735,13 +734,13 @@ }; ldo1 { - regulator-name = "run-cam-1.8"; + regulator-name = "+1.8V_RUN_CAM"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo2 { - regulator-name = "gen-avdd,vddio-hsic"; + regulator-name = "+1.2V_GEN_AVDD"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-boot-on; @@ -749,7 +748,7 @@ }; ldo3 { - regulator-name = "vdd-rtc"; + regulator-name = "+1.00V_LP0_VDD_RTC"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; @@ -757,48 +756,44 @@ ams,enable-tracking; }; - ldo4 { - regulator-name = "vdd-cam"; + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; }; ldo5 { - regulator-name = "vdd-cam-front"; + regulator-name = "+1.2V_RUN_CAM_FRONT"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo6 { - regulator-name = "vddio-sdmmc3"; + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; }; ldo7 { - regulator-name = "vdd-cam-rear"; + regulator-name = "+1.05V_RUN_CAM_REAR"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; ldo9 { - regulator-name = "vdd-touch"; + regulator-name = "+2.8V_RUN_TOUCH"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; ldo10 { - regulator-name = "vdd-cam-af"; + regulator-name = "+2.8V_RUN_CAM_AF"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; ldo11 { - regulator-name = "vpp-fuse"; + regulator-name = "+1.8V_RUN_VPP_FUSE"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; @@ -806,7 +801,7 @@ }; }; - spi@7000d400 { + spi@0,7000d400 { status = "okay"; cros-ec@0 { @@ -912,7 +907,17 @@ }; }; - pmc@7000e400 { + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@0,7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <500>; @@ -923,24 +928,63 @@ nvidia,sys-clock-req-active-high; }; - sdhci@700b0400 { + sdhci@0,700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; status = "okay"; bus-width = <4>; + vmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { + sdhci@0,700b0600 { status = "okay"; bus-width = <8>; }; - ahub@70300000 { - i2s@70301100 { + ahub@0,70300000 { + i2s@0,70301100 { status = "okay"; }; }; + usb@0,7d000000 { + status = "okay"; + }; + + usb-phy@0,7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@0,7d004000 { + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@0,7d008000 { + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -948,7 +992,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; @@ -966,104 +1010,140 @@ }; }; + panel: panel { + compatible = "lg,lp129qe", "simple-panel"; + + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - vdd_ac_bat_reg: regulator@0 { + vdd_mux: regulator@0 { compatible = "regulator-fixed"; reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; regulator-always-on; + regulator-boot-on; }; - vdd_3v3_reg: regulator@1 { + vdd_5v0_sys: regulator@1 { compatible = "regulator-fixed"; reg = <1>; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; - enable-active-high; - gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_mux>; }; - vdd_3v3_modem_reg: regulator@2 { + vdd_3v3_sys: regulator@2 { compatible = "regulator-fixed"; reg = <2>; - regulator-name = "vdd-modem-3v3"; + regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; }; - vdd_hdmi_5v0_reg: regulator@3 { + vdd_3v3_run: regulator@3 { compatible = "regulator-fixed"; reg = <3>; - regulator-name = "vdd-hdmi-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_3v3_sys>; }; - vdd_bl_reg: regulator@4 { + vdd_3v3_hdmi: regulator@4 { compatible = "regulator-fixed"; reg = <4>; - regulator-name = "vdd-bl"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_3v3_run>; }; - vdd_ts_sw_5v0: regulator@5 { + vdd_led: regulator@5 { compatible = "regulator-fixed"; reg = <5>; - regulator-name = "vdd_ts_sw"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_mux>; }; - usb1_vbus_reg: regulator@6 { + vdd_5v0_ts: regulator@6 { compatible = "regulator-fixed"; reg = <6>; - regulator-name = "usb1_vbus"; + regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; }; - usb3_vbus_reg: regulator@7 { + vdd_usb1_vbus: regulator@7 { compatible = "regulator-fixed"; reg = <7>; - regulator-name = "usb3_vbus"; + regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; }; - panel_3v3_reg: regulator@8 { + vdd_usb3_vbus: regulator@8 { compatible = "regulator-fixed"; reg = <8>; - regulator-name = "panel_3v3"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; enable-active-high; - gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_3v3_sys>; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra20.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20.dtsi --- linux-3.14.1/arch/arm/boot/dts/tegra20.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -556,6 +556,10 @@ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ interrupt-names = "intr", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra20-paz00.dts linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20-paz00.dts --- linux-3.14.1/arch/arm/boot/dts/tegra20-paz00.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20-paz00.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,6 +17,14 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; @@ -257,7 +265,11 @@ status = "okay"; }; - i2c@7000c000 { + pwm: pwm@7000a000 { + status = "okay"; + }; + + lvds_ddc: i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -475,6 +487,18 @@ non-removable; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; + default-brightness-level = <10>; + + backlight-boot-off; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -509,6 +533,16 @@ }; }; + panel: panel { + compatible = "samsung,ltn101nt05", "simple-panel"; + + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -522,6 +556,16 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + vdd_pnl_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+3VS,vdd_pnl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; sound { diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra20-seaboard.dts linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20-seaboard.dts --- linux-3.14.1/arch/arm/boot/dts/tegra20-seaboard.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20-seaboard.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,6 +17,14 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; @@ -312,6 +320,10 @@ status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -369,7 +381,7 @@ #size-cells = <0>; }; - i2c@1 { + lvds_ddc: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -762,6 +774,17 @@ non-removable; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -795,6 +818,16 @@ }; }; + panel: panel { + compatible = "chunghwa,claa101wa01a", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -839,6 +872,26 @@ regulator-always-on; regulator-boot-on; }; + + vdd_pnl_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; sound { diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra20-ventana.dts linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20-ventana.dts --- linux-3.14.1/arch/arm/boot/dts/tegra20-ventana.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra20-ventana.dts 2014-04-13 23:18:35.000000000 +0200 @@ -17,6 +17,14 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; @@ -309,6 +317,10 @@ status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -359,7 +371,7 @@ #size-cells = <0>; }; - i2c@1 { + lvds_ddc: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -557,6 +569,17 @@ non-removable; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -581,6 +604,16 @@ }; }; + panel: panel { + compatible = "chunghwa,claa101wa01a", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -614,7 +647,7 @@ enable-active-high; }; - regulator@3 { + vdd_pnl_reg: regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vdd_pnl"; @@ -624,7 +657,7 @@ enable-active-high; }; - regulator@4 { + vdd_bl_reg: regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "vdd_bl"; diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra30-cardhu.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/tegra30-cardhu.dtsi --- linux-3.14.1/arch/arm/boot/dts/tegra30-cardhu.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra30-cardhu.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -187,6 +187,13 @@ interrupt-parent = <&gpio>; interrupts = ; }; + + i2cmux@70 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; }; i2c@7000c700 { diff -Nur linux-3.14.1/arch/arm/boot/dts/tegra30.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/tegra30.dtsi --- linux-3.14.1/arch/arm/boot/dts/tegra30.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tegra30.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -28,6 +28,10 @@ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ interrupt-names = "intr", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; @@ -144,9 +148,9 @@ compatible = "nvidia,tegra30-gr2d"; reg = <0x54140000 0x00040000>; interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; - clocks = <&tegra_car TEGRA30_CLK_GR2D>; }; gr3d@54180000 { diff -Nur linux-3.14.1/arch/arm/boot/dts/tps65910.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/tps65910.dtsi --- linux-3.14.1/arch/arm/boot/dts/tps65910.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/tps65910.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -82,5 +82,10 @@ reg = <12>; regulator-compatible = "vmmc"; }; + + vbb_reg: regulator@13 { + reg = <13>; + regulator-compatible = "vbb"; + }; }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/twl4030.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/twl4030.dtsi --- linux-3.14.1/arch/arm/boot/dts/twl4030.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/twl4030.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -145,4 +145,11 @@ compatible = "ti,twl4030-pwrbutton"; interrupts = <8>; }; + + twl_keypad: keypad { + compatible = "ti,twl4030-keypad"; + interrupts = <1>; + keypad,num-rows = <8>; + keypad,num-columns = <8>; + }; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/vf610-cosmic.dts linux-3.15-rc1.orig/arch/arm/boot/dts/vf610-cosmic.dts --- linux-3.14.1/arch/arm/boot/dts/vf610-cosmic.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/vf610-cosmic.dts 2014-04-13 23:18:35.000000000 +0200 @@ -36,12 +36,37 @@ &fec1 { phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1_1>; + pinctrl-0 = <&pinctrl_fec1>; status = "okay"; }; +&iomuxc { + vf610-cosmic { + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + }; +}; + &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/vf610.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/vf610.dtsi --- linux-3.14.1/arch/arm/boot/dts/vf610.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/vf610.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,7 @@ #include "skeleton.dtsi" #include "vf610-pinfunc.h" #include +#include / { aliases { @@ -87,39 +88,66 @@ arm,tag-latency = <2 2 2>; }; + edma0: dma-controller@40018000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40018000 0x2000>, + <0x40024000 0x1000>, + <0x40025000 0x1000>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX0>, + <&clks VF610_CLK_DMAMUX1>; + }; + uart0: serial@40027000 { compatible = "fsl,vf610-lpuart"; reg = <0x40027000 0x1000>; - interrupts = <0 61 0x00>; + interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART0>; clock-names = "ipg"; + dmas = <&edma0 0 2>, + <&edma0 0 3>; + dma-names = "rx","tx"; status = "disabled"; }; uart1: serial@40028000 { compatible = "fsl,vf610-lpuart"; reg = <0x40028000 0x1000>; - interrupts = <0 62 0x04>; + interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART1>; clock-names = "ipg"; + dmas = <&edma0 0 4>, + <&edma0 0 5>; + dma-names = "rx","tx"; status = "disabled"; }; uart2: serial@40029000 { compatible = "fsl,vf610-lpuart"; reg = <0x40029000 0x1000>; - interrupts = <0 63 0x04>; + interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART2>; clock-names = "ipg"; + dmas = <&edma0 0 6>, + <&edma0 0 7>; + dma-names = "rx","tx"; status = "disabled"; }; uart3: serial@4002a000 { compatible = "fsl,vf610-lpuart"; reg = <0x4002a000 0x1000>; - interrupts = <0 64 0x04>; + interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART3>; clock-names = "ipg"; + dmas = <&edma0 0 8>, + <&edma0 0 9>; + dma-names = "rx","tx"; status = "disabled"; }; @@ -128,7 +156,7 @@ #size-cells = <0>; compatible = "fsl,vf610-dspi"; reg = <0x4002c000 0x1000>; - interrupts = <0 67 0x04>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <5>; @@ -138,20 +166,32 @@ sai2: sai@40031000 { compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; - interrupts = <0 86 0x04>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_SAI2>; clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 0 21>, + <&edma0 0 20>; status = "disabled"; }; pit: pit@40037000 { compatible = "fsl,vf610-pit"; reg = <0x40037000 0x1000>; - interrupts = <0 39 0x04>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_PIT>; clock-names = "pit"; }; + adc0: adc@4003b000 { + compatible = "fsl,vf610-adc"; + reg = <0x4003b000 0x1000>; + interrupts = <0 53 0x04>; + clocks = <&clks VF610_CLK_ADC0>; + clock-names = "adc"; + status = "disabled"; + }; + wdog@4003e000 { compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; reg = <0x4003e000 0x1000>; @@ -164,7 +204,7 @@ #size-cells = <0>; compatible = "fsl,vf610-qspi"; reg = <0x40044000 0x1000>; - interrupts = <0 24 0x04>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_QSPI0_EN>, <&clks VF610_CLK_QSPI0>; clock-names = "qspi_en", "qspi"; @@ -175,182 +215,12 @@ compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; #gpio-range-cells = <3>; - - /* functions and groups pins */ - - dcu0 { - pinctrl_dcu0_1: dcu0grp_1 { - fsl,pins = < - VF610_PAD_PTB8__GPIO_30 0x42 - VF610_PAD_PTE0__DCU0_HSYNC 0x42 - VF610_PAD_PTE1__DCU0_VSYNC 0x42 - VF610_PAD_PTE2__DCU0_PCLK 0x42 - VF610_PAD_PTE4__DCU0_DE 0x42 - VF610_PAD_PTE5__DCU0_R0 0x42 - VF610_PAD_PTE6__DCU0_R1 0x42 - VF610_PAD_PTE7__DCU0_R2 0x42 - VF610_PAD_PTE8__DCU0_R3 0x42 - VF610_PAD_PTE9__DCU0_R4 0x42 - VF610_PAD_PTE10__DCU0_R5 0x42 - VF610_PAD_PTE11__DCU0_R6 0x42 - VF610_PAD_PTE12__DCU0_R7 0x42 - VF610_PAD_PTE13__DCU0_G0 0x42 - VF610_PAD_PTE14__DCU0_G1 0x42 - VF610_PAD_PTE15__DCU0_G2 0x42 - VF610_PAD_PTE16__DCU0_G3 0x42 - VF610_PAD_PTE17__DCU0_G4 0x42 - VF610_PAD_PTE18__DCU0_G5 0x42 - VF610_PAD_PTE19__DCU0_G6 0x42 - VF610_PAD_PTE20__DCU0_G7 0x42 - VF610_PAD_PTE21__DCU0_B0 0x42 - VF610_PAD_PTE22__DCU0_B1 0x42 - VF610_PAD_PTE23__DCU0_B2 0x42 - VF610_PAD_PTE24__DCU0_B3 0x42 - VF610_PAD_PTE25__DCU0_B4 0x42 - VF610_PAD_PTE26__DCU0_B5 0x42 - VF610_PAD_PTE27__DCU0_B6 0x42 - VF610_PAD_PTE28__DCU0_B7 0x42 - >; - }; - }; - - dspi0 { - pinctrl_dspi0_1: dspi0grp_1 { - fsl,pins = < - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - }; - - esdhc1 { - pinctrl_esdhc1_1: esdhc1grp_1 { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTA7__GPIO_134 0x219d - >; - }; - }; - - fec0 { - pinctrl_fec0_1: fec0grp_1 { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 - >; - }; - }; - - fec1 { - pinctrl_fec1_1: fec1grp_1 { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - }; - - i2c0 { - pinctrl_i2c0_1: i2c0grp_1 { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x30d3 - VF610_PAD_PTB15__I2C0_SDA 0x30d3 - >; - }; - }; - - pwm0 { - pinctrl_pwm0_1: pwm0grp_1 { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1582 - VF610_PAD_PTB1__FTM0_CH1 0x1582 - VF610_PAD_PTB2__FTM0_CH2 0x1582 - VF610_PAD_PTB3__FTM0_CH3 0x1582 - VF610_PAD_PTB6__FTM0_CH6 0x1582 - VF610_PAD_PTB7__FTM0_CH7 0x1582 - >; - }; - }; - - qspi0 { - pinctrl_qspi0_1: qspi0grp_1 { - fsl,pins = < - VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b - VF610_PAD_PTD1__QSPI0_A_CS0 0x307f - VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073 - VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073 - VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073 - VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b - VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b - VF610_PAD_PTD8__QSPI0_B_CS0 0x307f - VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b - >; - }; - }; - - sai2 { - pinctrl_sai2_1: sai2grp_1 { - fsl,pins = < - VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed - VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee - VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed - VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed - VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed - VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed - VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp_1 { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - }; - - usbvbus { - pinctrl_usbvbus_1: usbvbusgrp_1 { - fsl,pins = < - VF610_PAD_PTA24__USB1_VBUS_EN 0x219c - VF610_PAD_PTA16__USB0_VBUS_EN 0x219c - >; - }; - }; - }; gpio1: gpio@40049000 { compatible = "fsl,vf610-gpio"; reg = <0x40049000 0x1000 0x400ff000 0x40>; - interrupts = <0 107 0x04>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -361,7 +231,7 @@ gpio2: gpio@4004a000 { compatible = "fsl,vf610-gpio"; reg = <0x4004a000 0x1000 0x400ff040 0x40>; - interrupts = <0 108 0x04>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -372,7 +242,7 @@ gpio3: gpio@4004b000 { compatible = "fsl,vf610-gpio"; reg = <0x4004b000 0x1000 0x400ff080 0x40>; - interrupts = <0 109 0x04>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -383,7 +253,7 @@ gpio4: gpio@4004c000 { compatible = "fsl,vf610-gpio"; reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; - interrupts = <0 110 0x04>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -394,7 +264,7 @@ gpio5: gpio@4004d000 { compatible = "fsl,vf610-gpio"; reg = <0x4004d000 0x1000 0x400ff100 0x40>; - interrupts = <0 111 0x04>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -412,9 +282,12 @@ #size-cells = <0>; compatible = "fsl,vf610-i2c"; reg = <0x40066000 0x1000>; - interrupts =<0 71 0x04>; + interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_I2C0>; clock-names = "ipg"; + dmas = <&edma0 0 50>, + <&edma0 0 51>; + dma-names = "rx","tx"; status = "disabled"; }; @@ -432,10 +305,25 @@ reg = <0x40080000 0x80000>; ranges; + edma1: dma-controller@40098000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40098000 0x2000>, + <0x400a1000 0x1000>, + <0x400a2000 0x1000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX2>, + <&clks VF610_CLK_DMAMUX3>; + }; + uart4: serial@400a9000 { compatible = "fsl,vf610-lpuart"; reg = <0x400a9000 0x1000>; - interrupts = <0 65 0x04>; + interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART4>; clock-names = "ipg"; status = "disabled"; @@ -444,16 +332,25 @@ uart5: serial@400aa000 { compatible = "fsl,vf610-lpuart"; reg = <0x400aa000 0x1000>; - interrupts = <0 66 0x04>; + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART5>; clock-names = "ipg"; status = "disabled"; }; + adc1: adc@400bb000 { + compatible = "fsl,vf610-adc"; + reg = <0x400bb000 0x1000>; + interrupts = <0 54 0x04>; + clocks = <&clks VF610_CLK_ADC1>; + clock-names = "adc"; + status = "disabled"; + }; + fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; - interrupts = <0 78 0x04>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET>; @@ -464,7 +361,7 @@ fec1: ethernet@400d1000 { compatible = "fsl,mvf600-fec"; reg = <0x400d1000 0x1000>; - interrupts = <0 79 0x04>; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET>; diff -Nur linux-3.14.1/arch/arm/boot/dts/vf610-twr.dts linux-3.15-rc1.orig/arch/arm/boot/dts/vf610-twr.dts --- linux-3.14.1/arch/arm/boot/dts/vf610-twr.dts 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/vf610-twr.dts 2014-04-13 23:18:35.000000000 +0200 @@ -34,12 +34,70 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vcc_3v3_mcu: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + master-clkdir-out; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + }; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_ad5>; + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; }; &dspi0 { bus-num = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0_1>; + pinctrl-0 = <&pinctrl_dspi0>; status = "okay"; sflash: at26df081a@0 { @@ -56,26 +114,116 @@ &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0_1>; + pinctrl-0 = <&pinctrl_fec0>; status = "okay"; }; &fec1 { phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1_1>; + pinctrl-0 = <&pinctrl_fec1>; status = "okay"; }; &i2c0 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_1>; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + codec: sgtl5000@0a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&clks VF610_CLK_SAI2>; + }; +}; + +&iomuxc { + vf610-twr { + pinctrl_adc0_ad5: adc0ad5grp { + fsl,pins = < + VF610_PAD_PTC30__ADC0_SE5 0xa1 + >; + }; + + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_fec0: fec0grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x30d3 + VF610_PAD_PTB15__I2C0_SDA 0x30d3 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed + VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee + VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed + VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed + VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed + VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed + VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + }; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; status = "okay"; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; diff -Nur linux-3.14.1/arch/arm/boot/dts/zynq-7000.dtsi linux-3.15-rc1.orig/arch/arm/boot/dts/zynq-7000.dtsi --- linux-3.14.1/arch/arm/boot/dts/zynq-7000.dtsi 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/boot/dts/zynq-7000.dtsi 2014-04-13 23:18:35.000000000 +0200 @@ -24,6 +24,12 @@ device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + 222223 1000000 + >; }; cpu@1 { @@ -123,29 +129,28 @@ } ; slcr: slcr@f8000000 { - compatible = "xlnx,zynq-slcr"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon"; reg = <0xF8000000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - clkc: clkc { - #clock-cells = <1>; - compatible = "xlnx,ps7-clkc"; - ps-clk-frequency = <33333333>; - clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", - "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", - "dci", "lqspi", "smc", "pcap", "gem0", "gem1", - "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", - "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", - "dma", "usb0_aper", "usb1_aper", "gem0_aper", - "gem1_aper", "sdio0_aper", "sdio1_aper", - "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", - "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", - "gpio_aper", "lqspi_aper", "smc_aper", "swdt", - "dbg_trc", "dbg_apb"; - }; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + fclk-enable = <0>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; }; }; diff -Nur linux-3.14.1/arch/arm/common/Makefile linux-3.15-rc1.orig/arch/arm/common/Makefile --- linux-3.14.1/arch/arm/common/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/common/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o +CFLAGS_REMOVE_mcpm_entry.o = -pg AFLAGS_mcpm_head.o := -march=armv7-a AFLAGS_vlock.o := -march=armv7-a obj-$(CONFIG_TI_PRIV_EDMA) += edma.o diff -Nur linux-3.14.1/arch/arm/common/scoop.c linux-3.15-rc1.orig/arch/arm/common/scoop.c --- linux-3.14.1/arch/arm/common/scoop.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/common/scoop.c 2014-04-13 23:18:35.000000000 +0200 @@ -232,8 +232,6 @@ return 0; - if (devptr->gpio.base != -1) - temp = gpiochip_remove(&devptr->gpio); err_gpio: platform_set_drvdata(pdev, NULL); err_ioremap: diff -Nur linux-3.14.1/arch/arm/common/timer-sp.c linux-3.15-rc1.orig/arch/arm/common/timer-sp.c --- linux-3.14.1/arch/arm/common/timer-sp.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/common/timer-sp.c 2014-04-13 23:18:35.000000000 +0200 @@ -271,10 +271,14 @@ void __iomem *base; int irq; const char *name = of_get_property(np, "compatible", NULL); + struct clk *clk; base = of_iomap(np, 0); if (WARN_ON(!base)) return; + clk = of_clk_get(np, 0); + if (WARN_ON(IS_ERR(clk))) + return; /* Ensure timer is disabled */ writel(0, base + TIMER_CTRL); @@ -283,13 +287,13 @@ goto err; if (!init_count) - sp804_clocksource_init(base, name); + __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); else { irq = irq_of_parse_and_map(np, 0); if (irq <= 0) goto err; - sp804_clockevents_init(base, irq, name); + __sp804_clockevents_init(base, irq, clk, name); } init_count++; diff -Nur linux-3.14.1/arch/arm/configs/ape6evm_defconfig linux-3.15-rc1.orig/arch/arm/configs/ape6evm_defconfig --- linux-3.14.1/arch/arm/configs/ape6evm_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/ape6evm_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -48,6 +48,8 @@ # CONFIG_IPV6_SIT is not set CONFIG_NETFILTER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_NETDEVICES=y # CONFIG_NET_CADENCE is not set diff -Nur linux-3.14.1/arch/arm/configs/armadillo800eva_defconfig linux-3.15-rc1.orig/arch/arm/configs/armadillo800eva_defconfig --- linux-3.14.1/arch/arm/configs/armadillo800eva_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/armadillo800eva_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -58,6 +58,8 @@ # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_MD=y diff -Nur linux-3.14.1/arch/arm/configs/at91_dt_defconfig linux-3.15-rc1.orig/arch/arm/configs/at91_dt_defconfig --- linux-3.14.1/arch/arm/configs/at91_dt_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/at91_dt_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -16,10 +16,12 @@ CONFIG_ARCH_AT91=y CONFIG_SOC_AT91RM9200=y CONFIG_SOC_AT91SAM9260=y +CONFIG_SOC_AT91SAM9261=y CONFIG_SOC_AT91SAM9263=y CONFIG_SOC_AT91SAM9G45=y CONFIG_SOC_AT91SAM9X5=y CONFIG_SOC_AT91SAM9N12=y +CONFIG_SOC_AT91SAM9RL=y CONFIG_MACH_AT91RM9200_DT=y CONFIG_MACH_AT91SAM9_DT=y CONFIG_AT91_TIMER_HZ=128 @@ -119,6 +121,7 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y # CONFIG_SERIO is not set CONFIG_LEGACY_PTY_COUNT=4 CONFIG_SERIAL_ATMEL=y diff -Nur linux-3.14.1/arch/arm/configs/at91sam9260_9g20_defconfig linux-3.15-rc1.orig/arch/arm/configs/at91sam9260_9g20_defconfig --- linux-3.14.1/arch/arm/configs/at91sam9260_9g20_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/at91sam9260_9g20_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -3,6 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -30,15 +31,12 @@ CONFIG_AT91_SLOW_CLOCK=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y -CONFIG_LEDS=y -CONFIG_LEDS_CPU=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" CONFIG_AUTO_ZRELADDR=y -CONFIG_FPE_NWFPE=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -57,15 +55,14 @@ CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_OF_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT25=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y @@ -112,8 +109,6 @@ CONFIG_SND_SEQUENCER_OSS=y # CONFIG_SND_VERBOSE_PROCFS is not set CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y diff -Nur linux-3.14.1/arch/arm/configs/at91sam9rl_defconfig linux-3.15-rc1.orig/arch/arm/configs/at91sam9rl_defconfig --- linux-3.14.1/arch/arm/configs/at91sam9rl_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/at91sam9rl_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -1,8 +1,8 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EMBEDDED=y CONFIG_BLK_DEV_INITRD=y CONFIG_SLAB=y CONFIG_MODULES=y @@ -14,20 +14,23 @@ CONFIG_ARCH_AT91SAM9RL=y CONFIG_MACH_AT91SAM9RLEK=y # CONFIG_ARM_THUMB is not set +CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw" -CONFIG_FPE_NWFPE=y +CONFIG_AUTO_ZRELADDR=y CONFIG_NET=y CONFIG_UNIX=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=4 @@ -66,6 +69,7 @@ CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y CONFIG_CRAMFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y diff -Nur linux-3.14.1/arch/arm/configs/bcm2835_defconfig linux-3.15-rc1.orig/arch/arm/configs/bcm2835_defconfig --- linux-3.14.1/arch/arm/configs/bcm2835_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/bcm2835_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -31,6 +31,7 @@ CONFIG_JUMP_LABEL=y CONFIG_ARCH_MULTI_V6=y # CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM2835=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y diff -Nur linux-3.14.1/arch/arm/configs/bcm_defconfig linux-3.15-rc1.orig/arch/arm/configs/bcm_defconfig --- linux-3.14.1/arch/arm/configs/bcm_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/bcm_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -79,6 +79,13 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y # CONFIG_HWMON is not set +CONFIG_MFD_BCM590XX=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=y +CONFIG_REGULATOR_BCM590XX=y + CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y diff -Nur linux-3.14.1/arch/arm/configs/bockw_defconfig linux-3.15-rc1.orig/arch/arm/configs/bockw_defconfig --- linux-3.14.1/arch/arm/configs/bockw_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/bockw_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -44,6 +44,8 @@ # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set diff -Nur linux-3.14.1/arch/arm/configs/clps711x_defconfig linux-3.15-rc1.orig/arch/arm/configs/clps711x_defconfig --- linux-3.14.1/arch/arm/configs/clps711x_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/clps711x_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -15,7 +15,6 @@ CONFIG_ARCH_CLEP7312=y CONFIG_ARCH_EDB7211=y CONFIG_ARCH_P720T=y -CONFIG_ARCH_FORTUNET=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -27,7 +26,6 @@ # CONFIG_IPV6 is not set CONFIG_IRDA=y CONFIG_IRTTY_SIR=y -CONFIG_EP7211_DONGLE=y # CONFIG_WIRELESS is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y @@ -58,6 +56,7 @@ # CONFIG_INPUT is not set # CONFIG_SERIO is not set # CONFIG_VT is not set +CONFIG_SERIAL_CLPS711X=y CONFIG_SERIAL_CLPS711X_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y diff -Nur linux-3.14.1/arch/arm/configs/da8xx_omapl_defconfig linux-3.15-rc1.orig/arch/arm/configs/da8xx_omapl_defconfig --- linux-3.14.1/arch/arm/configs/da8xx_omapl_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/da8xx_omapl_defconfig 1970-01-01 01:00:00.000000000 +0100 @@ -1,139 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CGROUPS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_DAVINCI=y -CONFIG_ARCH_DAVINCI_DA830=y -CONFIG_ARCH_DAVINCI_DA850=y -CONFIG_MACH_DA8XX_DT=y -CONFIG_MACH_MITYOMAPL138=y -CONFIG_MACH_OMAPL138_HAWKBOARD=y -CONFIG_DAVINCI_RESET_CLOCKS=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_LEDS=y -CONFIG_USE_OF=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=m -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_IDLE=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_LRO is not set -CONFIG_NETFILTER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FW_LOADER is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=1 -CONFIG_BLK_DEV_RAM_SIZE=32768 -CONFIG_EEPROM_AT24=y -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -CONFIG_NETDEVICES=y -CONFIG_TUN=m -CONFIG_LXT_PHY=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_TI_DAVINCI_EMAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_NETCONSOLE=y -CONFIG_NETPOLL_TRAP=y -CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m -CONFIG_KEYBOARD_ATKBD=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_XTKBD=m -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_VT_CONSOLE is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_DAVINCI=y -CONFIG_PINCTRL_SINGLE=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DUMMY=y -CONFIG_REGULATOR_TPS6507X=y -CONFIG_FB=y -CONFIG_FB_DA8XX=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_SOC=m -CONFIG_SND_DAVINCI_SOC=m -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_DMADEVICES=y -CONFIG_TI_EDMA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_XFS_FS=m -CONFIG_INOTIFY=y -CONFIG_AUTOFS4_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_CRAMFS=y -CONFIG_MINIX_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_TIMER_STATS=y -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC_T10DIF=m diff -Nur linux-3.14.1/arch/arm/configs/davinci_all_defconfig linux-3.15-rc1.orig/arch/arm/configs/davinci_all_defconfig --- linux-3.14.1/arch/arm/configs/davinci_all_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/davinci_all_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -20,9 +20,14 @@ CONFIG_ARCH_DAVINCI_DM355=y CONFIG_ARCH_DAVINCI_DM646x=y CONFIG_ARCH_DAVINCI_DM365=y +CONFIG_ARCH_DAVINCI_DA830=y +CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_MACH_DA8XX_DT=y CONFIG_MACH_SFFSDR=y CONFIG_MACH_NEUROS_OSD2=y CONFIG_MACH_DM355_LEOPARD=y +CONFIG_MACH_MITYOMAPL138=y +CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_DAVINCI_MUX_DEBUG=y CONFIG_DAVINCI_MUX_WARNINGS=y CONFIG_DAVINCI_RESET_CLOCKS=y @@ -32,8 +37,18 @@ CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_LEDS=y +CONFIG_USE_OF=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=m +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_IDLE=y CONFIG_PM_RUNTIME=y CONFIG_NET=y CONFIG_PACKET=y @@ -57,6 +72,7 @@ CONFIG_MTD_PHYSMAP=m CONFIG_MTD_NAND=m CONFIG_MTD_NAND_DAVINCI=m +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -71,6 +87,7 @@ CONFIG_LXT_PHY=y CONFIG_LSI_ET1011C_PHY=y CONFIG_NET_ETHERNET=y +CONFIG_MII=y CONFIG_TI_DAVINCI_EMAC=y CONFIG_DM9000=y # CONFIG_NETDEV_1000 is not set @@ -97,15 +114,21 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=3 # CONFIG_HW_RANDOM is not set +CONFIG_SERIAL_OF_PLATFORM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DAVINCI=y +CONFIG_PINCTRL_SINGLE=y CONFIG_GPIO_PCF857X=y CONFIG_WATCHDOG=y CONFIG_DAVINCI_WATCHDOG=m CONFIG_MFD_DM355EVM_MSP=y +CONFIG_TPS6507X=y CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_TPS6507X=y CONFIG_FB=y +CONFIG_FB_DA8XX=y CONFIG_FIRMWARE_EDID=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y @@ -198,3 +221,5 @@ # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_CRC_T10DIF=m +CONFIG_GPIO_PCA953X=y +CONFIG_KEYBOARD_GPIO_POLLED=y diff -Nur linux-3.14.1/arch/arm/configs/dove_defconfig linux-3.15-rc1.orig/arch/arm/configs/dove_defconfig --- linux-3.14.1/arch/arm/configs/dove_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/dove_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -48,7 +48,6 @@ CONFIG_MTD_CFI_STAA=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_M25P80=y -CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -80,6 +79,8 @@ # CONFIG_HWMON is not set CONFIG_THERMAL=y CONFIG_DOVE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_ORION_WATCHDOG=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff -Nur linux-3.14.1/arch/arm/configs/exynos_defconfig linux-3.15-rc1.orig/arch/arm/configs/exynos_defconfig --- linux-3.14.1/arch/arm/configs/exynos_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/exynos_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -94,7 +94,7 @@ CONFIG_LOGO=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_S5P=y +CONFIG_USB_EHCI_EXYNOS=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC3=y CONFIG_USB_PHY=y diff -Nur linux-3.14.1/arch/arm/configs/genmai_defconfig linux-3.15-rc1.orig/arch/arm/configs/genmai_defconfig --- linux-3.14.1/arch/arm/configs/genmai_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/genmai_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -50,6 +50,9 @@ # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EEPROM_AT24=y CONFIG_NETDEVICES=y # CONFIG_NET_CORE is not set # CONFIG_NET_VENDOR_ARC is not set @@ -78,7 +81,10 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=10 CONFIG_SERIAL_SH_SCI_CONSOLE=y # CONFIG_HW_RANDOM is not set -CONFIG_I2C_SH_MOBILE=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_RIIC=y +CONFIG_SPI=y +CONFIG_SPI_RSPI=y # CONFIG_HWMON is not set CONFIG_THERMAL=y CONFIG_RCAR_THERMAL=y diff -Nur linux-3.14.1/arch/arm/configs/imx_v4_v5_defconfig linux-3.15-rc1.orig/arch/arm/configs/imx_v4_v5_defconfig --- linux-3.14.1/arch/arm/configs/imx_v4_v5_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/imx_v4_v5_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -154,6 +154,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y diff -Nur linux-3.14.1/arch/arm/configs/imx_v6_v7_defconfig linux-3.15-rc1.orig/arch/arm/configs/imx_v6_v7_defconfig --- linux-3.14.1/arch/arm/configs/imx_v6_v7_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/imx_v6_v7_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -39,6 +39,8 @@ CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_VF610=y +CONFIG_PCI=y +CONFIG_PCI_IMX6=y CONFIG_SMP=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT_VOLUNTARY=y @@ -165,6 +167,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_REGULATOR_PFUZE100=y @@ -186,6 +189,7 @@ CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_SOUND=y @@ -211,6 +215,7 @@ CONFIG_USB_ETH=m CONFIG_USB_MASS_STORAGE=m CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y @@ -225,6 +230,7 @@ CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_SNVS=y @@ -277,6 +283,7 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y +CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set CONFIG_PROVE_LOCKING=y diff -Nur linux-3.14.1/arch/arm/configs/keystone_defconfig linux-3.15-rc1.orig/arch/arm/configs/keystone_defconfig --- linux-3.14.1/arch/arm/configs/keystone_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/keystone_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -111,6 +111,7 @@ CONFIG_MTD_PLATRAM=y CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_DAVINCI=y CONFIG_MTD_UBI=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y @@ -131,6 +132,8 @@ CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_DAVINCI_WATCHDOG=y CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -145,6 +148,7 @@ CONFIG_TI_EDMA=y CONFIG_COMMON_CLK_DEBUG=y CONFIG_MEMORY=y +CONFIG_TI_AEMIF=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_MSDOS_FS=y @@ -177,3 +181,14 @@ CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_DAVINCI=y +CONFIG_LEDS_CLASS=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y diff -Nur linux-3.14.1/arch/arm/configs/koelsch_defconfig linux-3.15-rc1.orig/arch/arm/configs/koelsch_defconfig --- linux-3.14.1/arch/arm/configs/koelsch_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/koelsch_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -8,7 +8,6 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y CONFIG_SLAB=y -# CONFIG_BLOCK is not set CONFIG_ARCH_SHMOBILE_LEGACY=y CONFIG_ARCH_R8A7791=y CONFIG_MACH_KOELSCH=y @@ -35,7 +34,14 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_RCAR=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_CADENCE is not set @@ -53,18 +59,31 @@ # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_SH_SCI=y CONFIG_SERIAL_SH_SCI_NR_UARTS=20 CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_RCAR=y +CONFIG_SPI=y +CONFIG_SPI_RSPI=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_RCAR=y # CONFIG_HWMON is not set CONFIG_THERMAL=y CONFIG_RCAR_THERMAL=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y # CONFIG_HID is not set # CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y # CONFIG_IOMMU_SUPPORT is not set # CONFIG_DNOTIFY is not set CONFIG_TMPFS=y diff -Nur linux-3.14.1/arch/arm/configs/kzm9d_defconfig linux-3.15-rc1.orig/arch/arm/configs/kzm9d_defconfig --- linux-3.14.1/arch/arm/configs/kzm9d_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/kzm9d_defconfig 1970-01-01 01:00:00.000000000 +0100 @@ -1,89 +0,0 @@ -# CONFIG_ARM_PATCH_PHYS_VIRT is not set -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_EMEV2=y -CONFIG_MACH_KZM9D=y -CONFIG_MEMORY_START=0x40000000 -CONFIG_MEMORY_SIZE=0x10000000 -# CONFIG_SH_TIMER_TMU is not set -# CONFIG_SWP_EMULATE is not set -# CONFIG_CACHE_L2X0 is not set -CONFIG_SMP=y -CONFIG_NR_CPUS=2 -CONFIG_HOTPLUG_CPU=y -# CONFIG_LOCAL_TIMERS is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_CROSS_MEMORY_ATTACH is not set -CONFIG_FORCE_MAX_ZONEORDER=13 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_VFP=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_BLK_DEV is not set -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMSC911X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EM=y -# CONFIG_HW_RANDOM is not set -CONFIG_GPIOLIB=y -CONFIG_GPIO_EM=y -# CONFIG_HWMON is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_IOMMU_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -# CONFIG_FTRACE is not set diff -Nur linux-3.14.1/arch/arm/configs/kzm9g_defconfig linux-3.15-rc1.orig/arch/arm/configs/kzm9g_defconfig --- linux-3.14.1/arch/arm/configs/kzm9g_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/kzm9g_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -60,6 +60,8 @@ CONFIG_SH_IRDA=y # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y diff -Nur linux-3.14.1/arch/arm/configs/lager_defconfig linux-3.15-rc1.orig/arch/arm/configs/lager_defconfig --- linux-3.14.1/arch/arm/configs/lager_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/lager_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -49,6 +49,13 @@ # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_RCAR=y CONFIG_NETDEVICES=y # CONFIG_NET_CORE is not set # CONFIG_NET_VENDOR_ARC is not set @@ -81,6 +88,8 @@ CONFIG_I2C=y CONFIG_I2C_GPIO=y CONFIG_I2C_RCAR=y +CONFIG_SPI=y +CONFIG_SPI_RSPI=y CONFIG_GPIO_SH_PFC=y CONFIG_GPIOLIB=y CONFIG_GPIO_RCAR=y @@ -90,8 +99,20 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_PLATFORM=y +CONFIG_VIDEO_RCAR_VIN=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_VIDEO_ADV7180=y CONFIG_DRM=y CONFIG_DRM_RCAR_DU=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_RCAR=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_SDHI=y diff -Nur linux-3.14.1/arch/arm/configs/mackerel_defconfig linux-3.15-rc1.orig/arch/arm/configs/mackerel_defconfig --- linux-3.14.1/arch/arm/configs/mackerel_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/mackerel_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -42,6 +42,8 @@ # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_MTD=y CONFIG_MTD_CONCAT=y diff -Nur linux-3.14.1/arch/arm/configs/marzen_defconfig linux-3.15-rc1.orig/arch/arm/configs/marzen_defconfig --- linux-3.14.1/arch/arm/configs/marzen_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/marzen_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -43,6 +43,8 @@ # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set diff -Nur linux-3.14.1/arch/arm/configs/multi_v5_defconfig linux-3.15-rc1.orig/arch/arm/configs/multi_v5_defconfig --- linux-3.14.1/arch/arm/configs/multi_v5_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/configs/multi_v5_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,190 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_MVEBU=y +CONFIG_MACH_KIRKWOOD=y +CONFIG_MACH_T5325=y +CONFIG_ARCH_MXC=y +CONFIG_MACH_IMX25_DT=y +CONFIG_MACH_IMX27_DT=y +CONFIG_ARCH_U300=y +CONFIG_PCI_MVEBU=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_KIRKWOOD_CPUIDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IPV6 is not set +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_NETDEVICES=y +CONFIG_NET_DSA_MV88E6123_61_65=y +CONFIG_MV643XX_ETH=y +CONFIG_R8169=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_NOMADIK=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_QNAP=y +CONFIG_SENSORS_ADT7475=y +CONFIG_SENSORS_LM63=y +CONFIG_SENSORS_LM75=y +CONFIG_SENSORS_LM85=y +CONFIG_THERMAL=y +CONFIG_KIRKWOOD_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_ORION_WATCHDOG=y +CONFIG_FB=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +# CONFIG_ABX500_CORE is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_RS5C372=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_STAGING=y +CONFIG_FB_XGI=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_MV_CESA=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff -Nur linux-3.14.1/arch/arm/configs/multi_v7_defconfig linux-3.15-rc1.orig/arch/arm/configs/multi_v7_defconfig --- linux-3.14.1/arch/arm/configs/multi_v7_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/multi_v7_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -1,4 +1,5 @@ CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -9,8 +10,12 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y +CONFIG_MACH_ARMADA_375=y +CONFIG_MACH_ARMADA_38X=y CONFIG_MACH_ARMADA_XP=y +CONFIG_MACH_DOVE=y CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM_5301X=y CONFIG_ARCH_BCM_MOBILE=y CONFIG_ARCH_BERLIN=y CONFIG_MACH_BERLIN_BG2=y @@ -31,6 +36,10 @@ CONFIG_SOC_AM33XX=y CONFIG_SOC_DRA7XX=y CONFIG_SOC_AM43XX=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_MSM8X60=y +CONFIG_ARCH_MSM8960=y +CONFIG_ARCH_MSM8974=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_SOCFPGA=y CONFIG_PLAT_SPEAR=y @@ -55,6 +64,7 @@ CONFIG_ARCH_VIRT=y CONFIG_ARCH_WM8850=y CONFIG_ARCH_ZYNQ=y +CONFIG_NEON=y CONFIG_TRUSTED_FOUNDATIONS=y CONFIG_PCI=y CONFIG_PCI_MSI=y @@ -94,6 +104,7 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 CONFIG_OMAP_OCP2SCP=y CONFIG_MTD=y CONFIG_MTD_M25P80=y @@ -111,6 +122,7 @@ CONFIG_NETDEVICES=y CONFIG_SUN4I_EMAC=y CONFIG_NET_CALXEDA_XGMAC=y +CONFIG_MV643XX_ETH=y CONFIG_MVNETA=y CONFIG_KS8851=y CONFIG_R8169=y @@ -146,6 +158,8 @@ CONFIG_SERIAL_TEGRA=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_VT8500=y CONFIG_SERIAL_VT8500_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y @@ -159,6 +173,7 @@ CONFIG_SERIAL_ST_ASC_CONSOLE=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_MV64XXX=y @@ -187,7 +202,10 @@ CONFIG_POWER_RESET_GPIO=y CONFIG_SENSORS_LM90=y CONFIG_THERMAL=y +CONFIG_DOVE_THERMAL=y CONFIG_ARMADA_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_ORION_WATCHDOG=y CONFIG_MFD_AS3722=y CONFIG_MFD_CROS_EC=y CONFIG_MFD_CROS_EC_SPI=y @@ -212,6 +230,8 @@ CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_GSPCA=y CONFIG_DRM=y CONFIG_DRM_TEGRA=y CONFIG_DRM_PANEL_SIMPLE=y @@ -254,6 +274,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_MMC_SDHCI_DOVE=y CONFIG_MMC_SDHCI_SPEAR=y CONFIG_MMC_SDHCI_BCM_KONA=y CONFIG_MMC_OMAP=y @@ -294,6 +315,10 @@ CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y CONFIG_NVEC_POWER=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_MSM_GCC_8660=y +CONFIG_MSM_MMCC_8960=y +CONFIG_MSM_MMCC_8974=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_MEMORY=y diff -Nur linux-3.14.1/arch/arm/configs/mvebu_defconfig linux-3.15-rc1.orig/arch/arm/configs/mvebu_defconfig --- linux-3.14.1/arch/arm/configs/mvebu_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/mvebu_defconfig 1970-01-01 01:00:00.000000000 +0100 @@ -1,107 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IRQ_DOMAIN_DEBUG=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_MVEBU=y -CONFIG_MACH_ARMADA_370=y -CONFIG_MACH_ARMADA_XP=y -# CONFIG_CACHE_L2X0 is not set -# CONFIG_SWP_EMULATE is not set -CONFIG_PCI=y -CONFIG_PCI_MVEBU=y -CONFIG_SMP=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -# CONFIG_COMPACTION is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_VFP=y -CONFIG_NET=y -CONFIG_INET=y -CONFIG_BT=y -CONFIG_BT_MRVL=y -CONFIG_BT_MRVL_SDIO=y -CONFIG_CFG80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_SD=y -CONFIG_ATA=y -CONFIG_SATA_MV=y -CONFIG_NETDEVICES=y -CONFIG_MVNETA=y -CONFIG_MARVELL_PHY=y -CONFIG_MWIFIEX=y -CONFIG_MWIFIEX_SDIO=y -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_I2C=y -CONFIG_SPI=y -CONFIG_SPI_ORION=y -CONFIG_I2C_MV64XXX=y -CONFIG_MTD=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_PXA3xx=y -CONFIG_SERIAL_8250_DW=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_THERMAL=y -CONFIG_ARMADA_THERMAL=y -CONFIG_USB_SUPPORT=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_STORAGE=y -CONFIG_USB_XHCI_HCD=y -CONFIG_MMC=y -CONFIG_MMC_MVSDIO=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_CLASS=m -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_S35390A=y -CONFIG_RTC_DRV_MV=y -CONFIG_DMADEVICES=y -CONFIG_MV_XOR=y -CONFIG_MEMORY=y -CONFIG_MVEBU_DEVBUS=y -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_UTF8=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y diff -Nur linux-3.14.1/arch/arm/configs/mvebu_v5_defconfig linux-3.15-rc1.orig/arch/arm/configs/mvebu_v5_defconfig --- linux-3.14.1/arch/arm/configs/mvebu_v5_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/configs/mvebu_v5_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,181 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_MVEBU=y +CONFIG_MACH_KIRKWOOD=y +CONFIG_MACH_T5325=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_PCI_MVEBU=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_IDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IPV6 is not set +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_NETDEVICES=y +CONFIG_NET_DSA_MV88E6123_61_65=y +CONFIG_MV643XX_ETH=y +CONFIG_R8169=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_QNAP=y +CONFIG_SENSORS_ADT7475=y +CONFIG_SENSORS_LM63=y +CONFIG_SENSORS_LM75=y +CONFIG_SENSORS_LM85=y +CONFIG_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_ORION_WATCHDOG=y +CONFIG_FB=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_RS5C372=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_STAGING=y +CONFIG_FB_XGI=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_MV_CESA=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff -Nur linux-3.14.1/arch/arm/configs/mvebu_v7_defconfig linux-3.15-rc1.orig/arch/arm/configs/mvebu_v7_defconfig --- linux-3.14.1/arch/arm/configs/mvebu_v7_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/configs/mvebu_v7_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,117 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_ARCH_MVEBU=y +CONFIG_MACH_ARMADA_370=y +CONFIG_MACH_ARMADA_375=y +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_XP=y +CONFIG_NEON=y +# CONFIG_CACHE_L2X0 is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y +CONFIG_SMP=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +# CONFIG_COMPACTION is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y +CONFIG_NET=y +CONFIG_INET=y +CONFIG_BT=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y +CONFIG_CFG80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_MV=y +CONFIG_NETDEVICES=y +CONFIG_MVNETA=y +CONFIG_MARVELL_PHY=y +CONFIG_MWIFIEX=y +CONFIG_MWIFIEX_SDIO=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_I2C=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_I2C_MV64XXX=y +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_PXA3xx=y +CONFIG_SERIAL_8250_DW=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_THERMAL=y +CONFIG_ARMADA_THERMAL=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=y +CONFIG_WATCHDOG=y +CONFIG_ORION_WATCHDOG=y +CONFIG_USB_SUPPORT=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_USB_XHCI_HCD=y +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_CLASS=m +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_MEMORY=y +CONFIG_MVEBU_DEVBUS=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y diff -Nur linux-3.14.1/arch/arm/configs/omap2plus_defconfig linux-3.15-rc1.orig/arch/arm/configs/omap2plus_defconfig --- linux-3.14.1/arch/arm/configs/omap2plus_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/omap2plus_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -28,6 +28,7 @@ CONFIG_ARCH_OMAP4=y CONFIG_SOC_OMAP5=y CONFIG_SOC_AM33XX=y +CONFIG_SOC_AM43XX=y CONFIG_SOC_DRA7XX=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_ERRATA_411920=y @@ -169,6 +170,7 @@ CONFIG_WATCHDOG=y CONFIG_OMAP_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y +CONFIG_MFD_SYSCON=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65910=y @@ -180,6 +182,7 @@ CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TWL4030=y +CONFIG_REGULATOR_PBIAS=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y diff -Nur linux-3.14.1/arch/arm/configs/shmobile_defconfig linux-3.15-rc1.orig/arch/arm/configs/shmobile_defconfig --- linux-3.14.1/arch/arm/configs/shmobile_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/configs/shmobile_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,129 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y +CONFIG_ARCH_SHMOBILE_MULTI=y +CONFIG_ARCH_EMEV2=y +CONFIG_ARCH_R8A7790=y +CONFIG_ARCH_R8A7791=y +CONFIG_MACH_KOELSCH=y +CONFIG_MACH_LAGER=y +# CONFIG_SWP_EMULATE is not set +CONFIG_CPU_BPREDICT_DISABLE=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_PCI=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_NR_CPUS=8 +CONFIG_AEABI=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_KEXEC=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_RCAR=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_SH_ETH=y +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_SMSC_PHY=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_EM=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=20 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_RCAR=y +CONFIG_SPI=y +CONFIG_SPI_RSPI=y +CONFIG_GPIO_EM=y +CONFIG_GPIO_RCAR=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_RCAR_THERMAL=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_PLATFORM=y +CONFIG_VIDEO_RCAR_VIN=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_VIDEO_ADV7180=y +CONFIG_DRM=y +CONFIG_DRM_RCAR_DU=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_RCAR=y +CONFIG_USB_RCAR_GEN2_PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_SH_MMCIF=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_SH_DMAE=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_ARM_UNWIND is not set diff -Nur linux-3.14.1/arch/arm/configs/socfpga_defconfig linux-3.15-rc1.orig/arch/arm/configs/socfpga_defconfig --- linux-3.14.1/arch/arm/configs/socfpga_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/socfpga_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -52,6 +52,7 @@ # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y CONFIG_STMMAC_ETH=y +CONFIG_MICREL_PHY=y # CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set CONFIG_INPUT_EVDEV=y # CONFIG_SERIO_SERPORT is not set @@ -66,6 +67,9 @@ CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT3_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set CONFIG_VFAT_FS=y @@ -82,3 +86,5 @@ CONFIG_ENABLE_DEFAULT_TRACERS=y CONFIG_DEBUG_USER=y CONFIG_XZ_DEC=y +CONFIG_MMC=y +CONFIG_MMC_DW=y diff -Nur linux-3.14.1/arch/arm/configs/sunxi_defconfig linux-3.15-rc1.orig/arch/arm/configs/sunxi_defconfig --- linux-3.14.1/arch/arm/configs/sunxi_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/sunxi_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -24,6 +24,7 @@ # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EEPROM_SUNXI_SID=y CONFIG_NETDEVICES=y CONFIG_SUN4I_EMAC=y # CONFIG_NET_CADENCE is not set @@ -48,6 +49,8 @@ # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_SUN6I=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y diff -Nur linux-3.14.1/arch/arm/configs/tegra_defconfig linux-3.15-rc1.orig/arch/arm/configs/tegra_defconfig --- linux-3.14.1/arch/arm/configs/tegra_defconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/configs/tegra_defconfig 2014-04-13 23:18:35.000000000 +0200 @@ -1,4 +1,5 @@ CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y @@ -86,6 +87,7 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 CONFIG_MTD=y CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y @@ -125,6 +127,7 @@ CONFIG_SERIAL_OF_PLATFORM=y # CONFIG_HW_RANDOM is not set # CONFIG_I2C_COMPAT is not set +CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_TEGRA=y CONFIG_SPI=y @@ -141,6 +144,7 @@ CONFIG_BATTERY_SBS=y CONFIG_CHARGER_TPS65090=y CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_GPIO=y CONFIG_SENSORS_LM90=y CONFIG_MFD_AS3722=y @@ -166,7 +170,8 @@ CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_GSPCA=y CONFIG_DRM=y CONFIG_DRM_TEGRA=y CONFIG_DRM_PANEL_SIMPLE=y diff -Nur linux-3.14.1/arch/arm/firmware/Kconfig linux-3.15-rc1.orig/arch/arm/firmware/Kconfig --- linux-3.14.1/arch/arm/firmware/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/firmware/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -11,6 +11,7 @@ config TRUSTED_FOUNDATIONS bool "Trusted Foundations secure monitor support" depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS + default y help Some devices (including most Tegra-based consumer devices on the market) are booted with the Trusted Foundations secure monitor @@ -20,7 +21,7 @@ This option allows the kernel to invoke the secure monitor whenever required on devices using Trusted Foundations. See arch/arm/include/asm/trusted_foundations.h or the - tl,trusted-foundations device tree binding documentation for details + tlm,trusted-foundations device tree binding documentation for details on how to use it. Say n if you don't know what this is about. diff -Nur linux-3.14.1/arch/arm/firmware/trusted_foundations.c linux-3.15-rc1.orig/arch/arm/firmware/trusted_foundations.c --- linux-3.14.1/arch/arm/firmware/trusted_foundations.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/firmware/trusted_foundations.c 2014-04-13 23:18:35.000000000 +0200 @@ -22,6 +22,15 @@ #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CPU_PM 0xfffffffc +#define TF_CPU_PM_S3 0xffffffe3 +#define TF_CPU_PM_S2 0xffffffe6 +#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5 +#define TF_CPU_PM_S1 0xffffffe4 +#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7 + +static unsigned long cpu_boot_addr; + static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) { asm volatile( @@ -41,13 +50,22 @@ static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) { - tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0); + cpu_boot_addr = boot_addr; + tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0); + + return 0; +} + +static int tf_prepare_idle(void) +{ + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr); return 0; } static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, + .prepare_idle = tf_prepare_idle, }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) diff -Nur linux-3.14.1/arch/arm/include/asm/assembler.h linux-3.15-rc1.orig/arch/arm/include/asm/assembler.h --- linux-3.14.1/arch/arm/include/asm/assembler.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/assembler.h 2014-04-13 23:18:35.000000000 +0200 @@ -23,6 +23,7 @@ #include #include #include +#include #define IOMEM(x) (x) @@ -30,8 +31,8 @@ * Endian independent macros for shifting bytes within registers. */ #ifndef __ARMEB__ -#define pull lsr -#define push lsl +#define lspull lsr +#define lspush lsl #define get_byte_0 lsl #0 #define get_byte_1 lsr #8 #define get_byte_2 lsr #16 @@ -41,8 +42,8 @@ #define put_byte_2 lsl #16 #define put_byte_3 lsl #24 #else -#define pull lsl -#define push lsr +#define lspull lsl +#define lspush lsr #define get_byte_0 lsr #24 #define get_byte_1 lsr #16 #define get_byte_2 lsr #8 @@ -174,6 +175,47 @@ restore_irqs_notrace \oldcpsr .endm +/* + * Get current thread_info. + */ + .macro get_thread_info, rd + ARM( mov \rd, sp, lsr #13 ) + THUMB( mov \rd, sp ) + THUMB( lsr \rd, \rd, #13 ) + mov \rd, \rd, lsl #13 + .endm + +/* + * Increment/decrement the preempt count. + */ +#ifdef CONFIG_PREEMPT_COUNT + .macro inc_preempt_count, ti, tmp + ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count + add \tmp, \tmp, #1 @ increment it + str \tmp, [\ti, #TI_PREEMPT] + .endm + + .macro dec_preempt_count, ti, tmp + ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count + sub \tmp, \tmp, #1 @ decrement it + str \tmp, [\ti, #TI_PREEMPT] + .endm + + .macro dec_preempt_count_ti, ti, tmp + get_thread_info \ti + dec_preempt_count \ti, \tmp + .endm +#else + .macro inc_preempt_count, ti, tmp + .endm + + .macro dec_preempt_count, ti, tmp + .endm + + .macro dec_preempt_count_ti, ti, tmp + .endm +#endif + #define USER(x...) \ 9999: x; \ .pushsection __ex_table,"a"; \ diff -Nur linux-3.14.1/arch/arm/include/asm/atomic.h linux-3.15-rc1.orig/arch/arm/include/asm/atomic.h --- linux-3.14.1/arch/arm/include/asm/atomic.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/atomic.h 2014-04-13 23:18:35.000000000 +0200 @@ -60,6 +60,7 @@ int result; smp_mb(); + prefetchw(&v->counter); __asm__ __volatile__("@ atomic_add_return\n" "1: ldrex %0, [%3]\n" @@ -99,6 +100,7 @@ int result; smp_mb(); + prefetchw(&v->counter); __asm__ __volatile__("@ atomic_sub_return\n" "1: ldrex %0, [%3]\n" @@ -121,6 +123,7 @@ unsigned long res; smp_mb(); + prefetchw(&ptr->counter); do { __asm__ __volatile__("@ atomic_cmpxchg\n" @@ -138,6 +141,33 @@ return oldval; } +static inline int __atomic_add_unless(atomic_t *v, int a, int u) +{ + int oldval, newval; + unsigned long tmp; + + smp_mb(); + prefetchw(&v->counter); + + __asm__ __volatile__ ("@ atomic_add_unless\n" +"1: ldrex %0, [%4]\n" +" teq %0, %5\n" +" beq 2f\n" +" add %1, %0, %6\n" +" strex %2, %1, [%4]\n" +" teq %2, #0\n" +" bne 1b\n" +"2:" + : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter) + : "r" (&v->counter), "r" (u), "r" (a) + : "cc"); + + if (oldval != u) + smp_mb(); + + return oldval; +} + #else /* ARM_ARCH_6 */ #ifdef CONFIG_SMP @@ -186,10 +216,6 @@ return ret; } -#endif /* __LINUX_ARM_ARCH__ */ - -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) - static inline int __atomic_add_unless(atomic_t *v, int a, int u) { int c, old; @@ -200,6 +226,10 @@ return c; } +#endif /* __LINUX_ARM_ARCH__ */ + +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + #define atomic_inc(v) atomic_add(1, v) #define atomic_dec(v) atomic_sub(1, v) @@ -299,6 +329,7 @@ unsigned long tmp; smp_mb(); + prefetchw(&v->counter); __asm__ __volatile__("@ atomic64_add_return\n" "1: ldrexd %0, %H0, [%3]\n" @@ -340,6 +371,7 @@ unsigned long tmp; smp_mb(); + prefetchw(&v->counter); __asm__ __volatile__("@ atomic64_sub_return\n" "1: ldrexd %0, %H0, [%3]\n" @@ -364,6 +396,7 @@ unsigned long res; smp_mb(); + prefetchw(&ptr->counter); do { __asm__ __volatile__("@ atomic64_cmpxchg\n" @@ -388,6 +421,7 @@ unsigned long tmp; smp_mb(); + prefetchw(&ptr->counter); __asm__ __volatile__("@ atomic64_xchg\n" "1: ldrexd %0, %H0, [%3]\n" @@ -409,6 +443,7 @@ unsigned long tmp; smp_mb(); + prefetchw(&v->counter); __asm__ __volatile__("@ atomic64_dec_if_positive\n" "1: ldrexd %0, %H0, [%3]\n" @@ -436,6 +471,7 @@ int ret = 1; smp_mb(); + prefetchw(&v->counter); __asm__ __volatile__("@ atomic64_add_unless\n" "1: ldrexd %0, %H0, [%4]\n" diff -Nur linux-3.14.1/arch/arm/include/asm/cmpxchg.h linux-3.15-rc1.orig/arch/arm/include/asm/cmpxchg.h --- linux-3.14.1/arch/arm/include/asm/cmpxchg.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/cmpxchg.h 2014-04-13 23:18:35.000000000 +0200 @@ -2,6 +2,7 @@ #define __ASM_ARM_CMPXCHG_H #include +#include #include #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) @@ -35,6 +36,7 @@ #endif smp_mb(); + prefetchw((const void *)ptr); switch (size) { #if __LINUX_ARM_ARCH__ >= 6 @@ -138,6 +140,8 @@ { unsigned long oldval, res; + prefetchw((const void *)ptr); + switch (size) { #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ case 1: @@ -230,6 +234,8 @@ unsigned long long oldval; unsigned long res; + prefetchw(ptr); + __asm__ __volatile__( "1: ldrexd %1, %H1, [%3]\n" " teq %1, %4\n" diff -Nur linux-3.14.1/arch/arm/include/asm/cputype.h linux-3.15-rc1.orig/arch/arm/include/asm/cputype.h --- linux-3.14.1/arch/arm/include/asm/cputype.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/cputype.h 2014-04-13 23:18:35.000000000 +0200 @@ -71,6 +71,7 @@ #define ARM_CPU_PART_CORTEX_A5 0xC050 #define ARM_CPU_PART_CORTEX_A15 0xC0F0 #define ARM_CPU_PART_CORTEX_A7 0xC070 +#define ARM_CPU_PART_CORTEX_A12 0xC0D0 #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 @@ -220,4 +221,23 @@ #define cpu_is_xscale() 1 #endif +/* + * Marvell's PJ4 core is based on V7 version. It has some modification + * for coprocessor setting. For this reason, we need a way to distinguish + * it. + */ +#ifndef CONFIG_CPU_PJ4 +#define cpu_is_pj4() 0 +#else +static inline int cpu_is_pj4(void) +{ + unsigned int id; + + id = read_cpuid_id(); + if ((id & 0xfffffff0) == 0x562f5840) + return 1; + + return 0; +} +#endif #endif diff -Nur linux-3.14.1/arch/arm/include/asm/dma-iommu.h linux-3.15-rc1.orig/arch/arm/include/asm/dma-iommu.h --- linux-3.14.1/arch/arm/include/asm/dma-iommu.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/dma-iommu.h 2014-04-13 23:18:35.000000000 +0200 @@ -13,9 +13,12 @@ /* iommu specific data */ struct iommu_domain *domain; - void *bitmap; - size_t bits; - unsigned int order; + unsigned long **bitmaps; /* array of bitmaps */ + unsigned int nr_bitmaps; /* nr of elements in array */ + unsigned int extensions; + size_t bitmap_size; /* size of a single bitmap */ + size_t bits; /* per bitmap */ + unsigned int size; /* per bitmap */ dma_addr_t base; spinlock_t lock; @@ -23,8 +26,7 @@ }; struct dma_iommu_mapping * -arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size, - int order); +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size); void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping); diff -Nur linux-3.14.1/arch/arm/include/asm/firmware.h linux-3.15-rc1.orig/arch/arm/include/asm/firmware.h --- linux-3.14.1/arch/arm/include/asm/firmware.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/firmware.h 2014-04-13 23:18:35.000000000 +0200 @@ -22,6 +22,10 @@ */ struct firmware_ops { /* + * Inform the firmware we intend to enter CPU idle mode + */ + int (*prepare_idle)(void); + /* * Enters CPU idle mode */ int (*do_idle)(void); diff -Nur linux-3.14.1/arch/arm/include/asm/floppy.h linux-3.15-rc1.orig/arch/arm/include/asm/floppy.h --- linux-3.14.1/arch/arm/include/asm/floppy.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/floppy.h 2014-04-13 23:18:35.000000000 +0200 @@ -25,7 +25,7 @@ #define fd_inb(port) inb((port)) #define fd_request_irq() request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\ - IRQF_DISABLED,"floppy",NULL) + 0,"floppy",NULL) #define fd_free_irq() free_irq(IRQ_FLOPPYDISK,NULL) #define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK) #define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK) diff -Nur linux-3.14.1/arch/arm/include/asm/futex.h linux-3.15-rc1.orig/arch/arm/include/asm/futex.h --- linux-3.14.1/arch/arm/include/asm/futex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/futex.h 2014-04-13 23:18:35.000000000 +0200 @@ -3,11 +3,6 @@ #ifdef __KERNEL__ -#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP) -/* ARM doesn't provide unprivileged exclusive memory accessors */ -#include -#else - #include #include #include @@ -28,6 +23,7 @@ #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ smp_mb(); \ + prefetchw(uaddr); \ __asm__ __volatile__( \ "1: ldrex %1, [%3]\n" \ " " insn "\n" \ @@ -51,6 +47,8 @@ return -EFAULT; smp_mb(); + /* Prefetching cannot fault */ + prefetchw(uaddr); __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" "1: ldrex %1, [%4]\n" " teq %1, %2\n" @@ -164,6 +162,5 @@ return ret; } -#endif /* !(CPU_USE_DOMAINS && SMP) */ #endif /* __KERNEL__ */ #endif /* _ASM_ARM_FUTEX_H */ diff -Nur linux-3.14.1/arch/arm/include/asm/hardware/cache-feroceon-l2.h linux-3.15-rc1.orig/arch/arm/include/asm/hardware/cache-feroceon-l2.h --- linux-3.14.1/arch/arm/include/asm/hardware/cache-feroceon-l2.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/include/asm/hardware/cache-feroceon-l2.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,13 @@ +/* + * arch/arm/include/asm/hardware/cache-feroceon-l2.h + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +extern void __init feroceon_l2_init(int l2_wt_override); +extern int __init feroceon_of_init(void); + diff -Nur linux-3.14.1/arch/arm/include/asm/hw_breakpoint.h linux-3.15-rc1.orig/arch/arm/include/asm/hw_breakpoint.h --- linux-3.14.1/arch/arm/include/asm/hw_breakpoint.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/hw_breakpoint.h 2014-04-13 23:18:35.000000000 +0200 @@ -51,6 +51,7 @@ #define ARM_DEBUG_ARCH_V7_ECP14 3 #define ARM_DEBUG_ARCH_V7_MM 4 #define ARM_DEBUG_ARCH_V7_1 5 +#define ARM_DEBUG_ARCH_V8 6 /* Breakpoint */ #define ARM_BREAKPOINT_EXECUTE 0 diff -Nur linux-3.14.1/arch/arm/include/asm/hwcap.h linux-3.15-rc1.orig/arch/arm/include/asm/hwcap.h --- linux-3.14.1/arch/arm/include/asm/hwcap.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/hwcap.h 2014-04-13 23:18:35.000000000 +0200 @@ -9,6 +9,7 @@ * instruction set this cpu supports. */ #define ELF_HWCAP (elf_hwcap) -extern unsigned int elf_hwcap; +#define ELF_HWCAP2 (elf_hwcap2) +extern unsigned int elf_hwcap, elf_hwcap2; #endif #endif diff -Nur linux-3.14.1/arch/arm/include/asm/jump_label.h linux-3.15-rc1.orig/arch/arm/include/asm/jump_label.h --- linux-3.14.1/arch/arm/include/asm/jump_label.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/jump_label.h 2014-04-13 23:18:35.000000000 +0200 @@ -4,7 +4,6 @@ #ifdef __KERNEL__ #include -#include #define JUMP_LABEL_NOP_SIZE 4 diff -Nur linux-3.14.1/arch/arm/include/asm/Kbuild linux-3.15-rc1.orig/arch/arm/include/asm/Kbuild --- linux-3.14.1/arch/arm/include/asm/Kbuild 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/Kbuild 2014-04-13 23:18:35.000000000 +0200 @@ -7,16 +7,19 @@ generic-y += emergency-restart.h generic-y += errno.h generic-y += exec.h +generic-y += hash.h generic-y += ioctl.h generic-y += ipcbuf.h generic-y += irq_regs.h generic-y += kdebug.h generic-y += local.h generic-y += local64.h +generic-y += mcs_spinlock.h generic-y += msgbuf.h generic-y += param.h generic-y += parport.h generic-y += poll.h +generic-y += preempt.h generic-y += resource.h generic-y += sections.h generic-y += segment.h @@ -33,5 +36,3 @@ generic-y += timex.h generic-y += trace_clock.h generic-y += unaligned.h -generic-y += preempt.h -generic-y += hash.h diff -Nur linux-3.14.1/arch/arm/include/asm/kprobes.h linux-3.15-rc1.orig/arch/arm/include/asm/kprobes.h --- linux-3.14.1/arch/arm/include/asm/kprobes.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/kprobes.h 2014-04-13 23:18:35.000000000 +0200 @@ -18,7 +18,7 @@ #include #include -#include +#include #define __ARCH_WANT_KPROBES_INSN_SLOT #define MAX_INSN_SIZE 2 @@ -28,21 +28,10 @@ #define kretprobe_blacklist_size 0 typedef u32 kprobe_opcode_t; - struct kprobe; -typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *); -typedef unsigned long (kprobe_check_cc)(unsigned long); -typedef void (kprobe_insn_singlestep_t)(struct kprobe *, struct pt_regs *); -typedef void (kprobe_insn_fn_t)(void); - -/* Architecture specific copy of original instruction. */ -struct arch_specific_insn { - kprobe_opcode_t *insn; - kprobe_insn_handler_t *insn_handler; - kprobe_check_cc *insn_check_cc; - kprobe_insn_singlestep_t *insn_singlestep; - kprobe_insn_fn_t *insn_fn; -}; +#include + +#define arch_specific_insn arch_probes_insn struct prev_kprobe { struct kprobe *kp; diff -Nur linux-3.14.1/arch/arm/include/asm/kvm_arm.h linux-3.15-rc1.orig/arch/arm/include/asm/kvm_arm.h --- linux-3.14.1/arch/arm/include/asm/kvm_arm.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/kvm_arm.h 2014-04-13 23:18:35.000000000 +0200 @@ -55,6 +55,7 @@ * The bits we set in HCR: * TAC: Trap ACTLR * TSC: Trap SMC + * TVM: Trap VM ops (until MMU and caches are on) * TSW: Trap cache operations by set/way * TWI: Trap WFI * TWE: Trap WFE @@ -68,8 +69,7 @@ */ #define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ - HCR_TWE | HCR_SWIO | HCR_TIDCP) -#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) + HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP) /* System Control Register (SCTLR) bits */ #define SCTLR_TE (1 << 30) diff -Nur linux-3.14.1/arch/arm/include/asm/kvm_asm.h linux-3.15-rc1.orig/arch/arm/include/asm/kvm_asm.h --- linux-3.14.1/arch/arm/include/asm/kvm_asm.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/kvm_asm.h 2014-04-13 23:18:35.000000000 +0200 @@ -48,7 +48,9 @@ #define c13_TID_URO 26 /* Thread ID, User R/O */ #define c13_TID_PRIV 27 /* Thread ID, Privileged */ #define c14_CNTKCTL 28 /* Timer Control Register (PL1) */ -#define NR_CP15_REGS 29 /* Number of regs (incl. invalid) */ +#define c10_AMAIR0 29 /* Auxilary Memory Attribute Indirection Reg0 */ +#define c10_AMAIR1 30 /* Auxilary Memory Attribute Indirection Reg1 */ +#define NR_CP15_REGS 31 /* Number of regs (incl. invalid) */ #define ARM_EXCEPTION_RESET 0 #define ARM_EXCEPTION_UNDEFINED 1 diff -Nur linux-3.14.1/arch/arm/include/asm/kvm_host.h linux-3.15-rc1.orig/arch/arm/include/asm/kvm_host.h --- linux-3.14.1/arch/arm/include/asm/kvm_host.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/kvm_host.h 2014-04-13 23:18:35.000000000 +0200 @@ -101,6 +101,12 @@ /* The CPU type we expose to the VM */ u32 midr; + /* HYP trapping configuration */ + u32 hcr; + + /* Interrupt related fields */ + u32 irq_lines; /* IRQ and FIQ levels */ + /* Exception Information */ struct kvm_vcpu_fault_info fault; @@ -128,9 +134,6 @@ /* IO related fields */ struct kvm_decode mmio_decode; - /* Interrupt related fields */ - u32 irq_lines; /* IRQ and FIQ levels */ - /* Cache some mmu pages needed inside spinlock regions */ struct kvm_mmu_memory_cache mmu_page_cache; diff -Nur linux-3.14.1/arch/arm/include/asm/kvm_mmu.h linux-3.15-rc1.orig/arch/arm/include/asm/kvm_mmu.h --- linux-3.14.1/arch/arm/include/asm/kvm_mmu.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/kvm_mmu.h 2014-04-13 23:18:35.000000000 +0200 @@ -114,11 +114,34 @@ pmd_val(*pmd) |= L_PMD_S2_RDWR; } +/* Open coded p*d_addr_end that can deal with 64bit addresses */ +#define kvm_pgd_addr_end(addr, end) \ +({ u64 __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ + (__boundary - 1 < (end) - 1)? __boundary: (end); \ +}) + +#define kvm_pud_addr_end(addr,end) (end) + +#define kvm_pmd_addr_end(addr, end) \ +({ u64 __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ + (__boundary - 1 < (end) - 1)? __boundary: (end); \ +}) + struct kvm; -static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva, - unsigned long size) +#define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l)) + +static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) { + return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101; +} + +static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva, + unsigned long size) +{ + if (!vcpu_has_cache_enabled(vcpu)) + kvm_flush_dcache_to_poc((void *)hva, size); + /* * If we are going to insert an instruction page and the icache is * either VIPT or PIPT, there is a potential problem where the host @@ -139,9 +162,10 @@ } } -#define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l)) #define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x)) +void stage2_flush_vm(struct kvm *kvm); + #endif /* !__ASSEMBLY__ */ #endif /* __ARM_KVM_MMU_H__ */ diff -Nur linux-3.14.1/arch/arm/include/asm/memory.h linux-3.15-rc1.orig/arch/arm/include/asm/memory.h --- linux-3.14.1/arch/arm/include/asm/memory.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/memory.h 2014-04-13 23:18:35.000000000 +0200 @@ -166,9 +166,17 @@ * Physical vs virtual RAM address space conversion. These are * private definitions which should NOT be used outside memory.h * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. + * + * PFNs are used to describe any physical page; this means + * PFN 0 == physical address 0. */ -#ifndef __virt_to_phys -#ifdef CONFIG_ARM_PATCH_PHYS_VIRT +#if defined(__virt_to_phys) +#define PHYS_OFFSET PLAT_PHYS_OFFSET +#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT)) + +#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) + +#elif defined(CONFIG_ARM_PATCH_PHYS_VIRT) /* * Constants used to force the right instruction encodings and shifts @@ -177,12 +185,17 @@ #define __PV_BITS_31_24 0x81000000 #define __PV_BITS_7_0 0x81 -extern u64 __pv_phys_offset; +extern unsigned long __pv_phys_pfn_offset; extern u64 __pv_offset; extern void fixup_pv_table(const void *, unsigned long); extern const void *__pv_table_begin, *__pv_table_end; -#define PHYS_OFFSET __pv_phys_offset +#define PHYS_OFFSET ((phys_addr_t)__pv_phys_pfn_offset << PAGE_SHIFT) +#define PHYS_PFN_OFFSET (__pv_phys_pfn_offset) + +#define virt_to_pfn(kaddr) \ + ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \ + PHYS_PFN_OFFSET) #define __pv_stub(from,to,instr,type) \ __asm__("@ __pv_stub\n" \ @@ -243,6 +256,7 @@ #else #define PHYS_OFFSET PLAT_PHYS_OFFSET +#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT)) static inline phys_addr_t __virt_to_phys(unsigned long x) { @@ -254,18 +268,11 @@ return x - PHYS_OFFSET + PAGE_OFFSET; } -#endif -#endif +#define virt_to_pfn(kaddr) \ + ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \ + PHYS_PFN_OFFSET) -/* - * PFNs are used to describe any physical page; this means - * PFN 0 == physical address 0. - * - * This is the PFN of the first RAM page in the kernel - * direct-mapped view. We assume this is the first page - * of RAM in the mem_map as well. - */ -#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT)) +#endif /* * These are *only* valid on the kernel direct mapped RAM memory. @@ -343,9 +350,9 @@ */ #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET -#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) +#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr)) #define virt_addr_valid(kaddr) (((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) \ - && pfn_valid(__pa(kaddr) >> PAGE_SHIFT) ) + && pfn_valid(virt_to_pfn(kaddr))) #endif diff -Nur linux-3.14.1/arch/arm/include/asm/pgtable-2level.h linux-3.15-rc1.orig/arch/arm/include/asm/pgtable-2level.h --- linux-3.14.1/arch/arm/include/asm/pgtable-2level.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/pgtable-2level.h 2014-04-13 23:18:35.000000000 +0200 @@ -140,6 +140,7 @@ #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */ #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) #ifndef __ASSEMBLY__ diff -Nur linux-3.14.1/arch/arm/include/asm/pgtable.h linux-3.15-rc1.orig/arch/arm/include/asm/pgtable.h --- linux-3.14.1/arch/arm/include/asm/pgtable.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/pgtable.h 2014-04-13 23:18:35.000000000 +0200 @@ -216,13 +216,16 @@ #define pte_none(pte) (!pte_val(pte)) #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) +#define pte_valid(pte) (pte_val(pte) & L_PTE_VALID) +#define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) #define pte_write(pte) (!(pte_val(pte) & L_PTE_RDONLY)) #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) #define pte_exec(pte) (!(pte_val(pte) & L_PTE_XN)) #define pte_special(pte) (0) -#define pte_present_user(pte) (pte_present(pte) && (pte_val(pte) & L_PTE_USER)) +#define pte_valid_user(pte) \ + (pte_valid(pte) && (pte_val(pte) & L_PTE_USER) && pte_young(pte)) #if __LINUX_ARM_ARCH__ < 6 static inline void __sync_icache_dcache(pte_t pteval) @@ -237,7 +240,7 @@ { unsigned long ext = 0; - if (addr < TASK_SIZE && pte_present_user(pteval)) { + if (addr < TASK_SIZE && pte_valid_user(pteval)) { __sync_icache_dcache(pteval); ext |= PTE_EXT_NG; } diff -Nur linux-3.14.1/arch/arm/include/asm/pmu.h linux-3.15-rc1.orig/arch/arm/include/asm/pmu.h --- linux-3.14.1/arch/arm/include/asm/pmu.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/pmu.h 2014-04-13 23:18:35.000000000 +0200 @@ -71,6 +71,8 @@ void (*disable)(struct perf_event *event); int (*get_event_idx)(struct pmu_hw_events *hw_events, struct perf_event *event); + void (*clear_event_idx)(struct pmu_hw_events *hw_events, + struct perf_event *event); int (*set_event_filter)(struct hw_perf_event *evt, struct perf_event_attr *attr); u32 (*read_counter)(struct perf_event *event); diff -Nur linux-3.14.1/arch/arm/include/asm/probes.h linux-3.15-rc1.orig/arch/arm/include/asm/probes.h --- linux-3.14.1/arch/arm/include/asm/probes.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/include/asm/probes.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,43 @@ +/* + * arch/arm/include/asm/probes.h + * + * Original contents copied from arch/arm/include/asm/kprobes.h + * which contains the following notice... + * + * Copyright (C) 2006, 2007 Motorola Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef _ASM_PROBES_H +#define _ASM_PROBES_H + +typedef u32 probes_opcode_t; + +struct arch_probes_insn; +typedef void (probes_insn_handler_t)(probes_opcode_t, + struct arch_probes_insn *, + struct pt_regs *); +typedef unsigned long (probes_check_cc)(unsigned long); +typedef void (probes_insn_singlestep_t)(probes_opcode_t, + struct arch_probes_insn *, + struct pt_regs *); +typedef void (probes_insn_fn_t)(void); + +/* Architecture specific copy of original instruction. */ +struct arch_probes_insn { + probes_opcode_t *insn; + probes_insn_handler_t *insn_handler; + probes_check_cc *insn_check_cc; + probes_insn_singlestep_t *insn_singlestep; + probes_insn_fn_t *insn_fn; +}; + +#endif diff -Nur linux-3.14.1/arch/arm/include/asm/ptrace.h linux-3.15-rc1.orig/arch/arm/include/asm/ptrace.h --- linux-3.14.1/arch/arm/include/asm/ptrace.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/ptrace.h 2014-04-13 23:18:35.000000000 +0200 @@ -27,9 +27,13 @@ #define thumb_mode(regs) (0) #endif +#ifndef CONFIG_CPU_V7M #define isa_mode(regs) \ - ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ - (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) + ((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \ + (((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT)))) +#else +#define isa_mode(regs) 1 /* Thumb */ +#endif #define processor_mode(regs) \ ((regs)->ARM_cpsr & MODE_MASK) @@ -80,6 +84,12 @@ #define instruction_pointer(regs) (regs)->ARM_pc +static inline void instruction_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + instruction_pointer(regs) = val; +} + #ifdef CONFIG_SMP extern unsigned long profile_pc(struct pt_regs *regs); #else diff -Nur linux-3.14.1/arch/arm/include/asm/smp.h linux-3.15-rc1.orig/arch/arm/include/asm/smp.h --- linux-3.14.1/arch/arm/include/asm/smp.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/smp.h 2014-04-13 23:18:35.000000000 +0200 @@ -74,6 +74,7 @@ }; extern struct secondary_data secondary_data; extern volatile int pen_release; +extern void secondary_startup(void); extern int __cpu_disable(void); @@ -114,6 +115,15 @@ #endif }; +struct of_cpu_method { + const char *method; + struct smp_operations *ops; +}; + +#define CPU_METHOD_OF_DECLARE(name, _method, _ops) \ + static const struct of_cpu_method __cpu_method_of_table_##name \ + __used __section(__cpu_method_of_table) \ + = { .method = _method, .ops = _ops } /* * set platform specific SMP operations */ diff -Nur linux-3.14.1/arch/arm/include/asm/sync_bitops.h linux-3.15-rc1.orig/arch/arm/include/asm/sync_bitops.h --- linux-3.14.1/arch/arm/include/asm/sync_bitops.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/sync_bitops.h 2014-04-13 23:18:35.000000000 +0200 @@ -2,7 +2,6 @@ #define __ASM_SYNC_BITOPS_H__ #include -#include /* sync_bitops functions are equivalent to the SMP implementation of the * original functions, independently from CONFIG_SMP being defined. diff -Nur linux-3.14.1/arch/arm/include/asm/syscall.h linux-3.15-rc1.orig/arch/arm/include/asm/syscall.h --- linux-3.14.1/arch/arm/include/asm/syscall.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/syscall.h 2014-04-13 23:18:35.000000000 +0200 @@ -7,7 +7,7 @@ #ifndef _ASM_ARM_SYSCALL_H #define _ASM_ARM_SYSCALL_H -#include /* for AUDIT_ARCH_* */ +#include /* for AUDIT_ARCH_* */ #include /* for ELF_EM */ #include #include @@ -103,8 +103,7 @@ memcpy(®s->ARM_r0 + i, args, n * sizeof(args[0])); } -static inline int syscall_get_arch(struct task_struct *task, - struct pt_regs *regs) +static inline int syscall_get_arch(void) { /* ARM tasks don't change audit architectures on the fly. */ return AUDIT_ARCH_ARM; diff -Nur linux-3.14.1/arch/arm/include/asm/system.h linux-3.15-rc1.orig/arch/arm/include/asm/system.h --- linux-3.14.1/arch/arm/include/asm/system.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/system.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,7 +0,0 @@ -/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */ -#include -#include -#include -#include -#include -#include diff -Nur linux-3.14.1/arch/arm/include/asm/thread_info.h linux-3.15-rc1.orig/arch/arm/include/asm/thread_info.h --- linux-3.14.1/arch/arm/include/asm/thread_info.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/thread_info.h 2014-04-13 23:18:35.000000000 +0200 @@ -153,6 +153,7 @@ #define TIF_SIGPENDING 0 #define TIF_NEED_RESCHED 1 #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ +#define TIF_UPROBE 7 #define TIF_SYSCALL_TRACE 8 #define TIF_SYSCALL_AUDIT 9 #define TIF_SYSCALL_TRACEPOINT 10 @@ -165,6 +166,7 @@ #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) +#define _TIF_UPROBE (1 << TIF_UPROBE) #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) @@ -178,7 +180,8 @@ /* * Change these and you break ASM code in entry-common.S */ -#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | _TIF_NOTIFY_RESUME) +#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \ + _TIF_NOTIFY_RESUME | _TIF_UPROBE) #endif /* __KERNEL__ */ #endif /* __ASM_ARM_THREAD_INFO_H */ diff -Nur linux-3.14.1/arch/arm/include/asm/timex.h linux-3.15-rc1.orig/arch/arm/include/asm/timex.h --- linux-3.14.1/arch/arm/include/asm/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/timex.h 2014-04-13 23:18:35.000000000 +0200 @@ -12,12 +12,6 @@ #ifndef _ASMARM_TIMEX_H #define _ASMARM_TIMEX_H -#ifdef CONFIG_ARCH_MULTIPLATFORM -#define CLOCK_TICK_RATE 1000000 -#else -#include -#endif - typedef unsigned long cycles_t; #define get_cycles() ({ cycles_t c; read_current_timer(&c) ? 0 : c; }) diff -Nur linux-3.14.1/arch/arm/include/asm/topology.h linux-3.15-rc1.orig/arch/arm/include/asm/topology.h --- linux-3.14.1/arch/arm/include/asm/topology.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/topology.h 2014-04-13 23:18:35.000000000 +0200 @@ -20,9 +20,6 @@ #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) -#define mc_capable() (cpu_topology[0].socket_id != -1) -#define smt_capable() (cpu_topology[0].thread_id != -1) - void init_cpu_topology(void); void store_cpu_topology(unsigned int cpuid); const struct cpumask *cpu_coregroup_mask(int cpu); diff -Nur linux-3.14.1/arch/arm/include/asm/trusted_foundations.h linux-3.15-rc1.orig/arch/arm/include/asm/trusted_foundations.h --- linux-3.14.1/arch/arm/include/asm/trusted_foundations.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/trusted_foundations.h 2014-04-13 23:18:35.000000000 +0200 @@ -30,6 +30,8 @@ #include #include #include +#include +#include struct trusted_foundations_platform_data { unsigned int version_major; @@ -47,10 +49,13 @@ struct trusted_foundations_platform_data *pd) { /* - * If we try to register TF, this means the system needs it to continue. - * Its absence if thus a fatal error. + * If the system requires TF and we cannot provide it, continue booting + * but disable features that cannot be provided. */ - panic("No support for Trusted Foundations, stopping...\n"); + pr_err("No support for Trusted Foundations, continuing in degraded mode.\n"); + pr_err("Secondary processors as well as CPU PM will be disabled.\n"); + setup_max_cpus = 0; + cpu_idle_poll_ctrl(true); } static inline void of_register_trusted_foundations(void) @@ -59,7 +64,7 @@ * If we find the target should enable TF but does not support it, * fail as the system won't be able to do much anyway */ - if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations")) + if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations")) register_trusted_foundations(NULL); } #endif /* CONFIG_TRUSTED_FOUNDATIONS */ diff -Nur linux-3.14.1/arch/arm/include/asm/uaccess.h linux-3.15-rc1.orig/arch/arm/include/asm/uaccess.h --- linux-3.14.1/arch/arm/include/asm/uaccess.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/uaccess.h 2014-04-13 23:18:35.000000000 +0200 @@ -19,7 +19,7 @@ #include #include -#if __LINUX_ARM_ARCH__ < 6 +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS #include #else #define __get_user_unaligned __get_user diff -Nur linux-3.14.1/arch/arm/include/asm/unistd.h linux-3.15-rc1.orig/arch/arm/include/asm/unistd.h --- linux-3.14.1/arch/arm/include/asm/unistd.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/unistd.h 2014-04-13 23:18:35.000000000 +0200 @@ -48,6 +48,5 @@ */ #define __IGNORE_fadvise64_64 #define __IGNORE_migrate_pages -#define __IGNORE_kcmp #endif /* __ASM_ARM_UNISTD_H */ diff -Nur linux-3.14.1/arch/arm/include/asm/uprobes.h linux-3.15-rc1.orig/arch/arm/include/asm/uprobes.h --- linux-3.14.1/arch/arm/include/asm/uprobes.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/include/asm/uprobes.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 Rabin Vincent + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _ASM_UPROBES_H +#define _ASM_UPROBES_H + +#include +#include + +typedef u32 uprobe_opcode_t; + +#define MAX_UINSN_BYTES 4 +#define UPROBE_XOL_SLOT_BYTES 64 + +#define UPROBE_SWBP_ARM_INSN 0xe7f001f9 +#define UPROBE_SS_ARM_INSN 0xe7f001fa +#define UPROBE_SWBP_INSN __opcode_to_mem_arm(UPROBE_SWBP_ARM_INSN) +#define UPROBE_SWBP_INSN_SIZE 4 + +struct arch_uprobe_task { + u32 backup; + unsigned long saved_trap_no; +}; + +struct arch_uprobe { + u8 insn[MAX_UINSN_BYTES]; + unsigned long ixol[2]; + uprobe_opcode_t bpinsn; + bool simulate; + u32 pcreg; + void (*prehandler)(struct arch_uprobe *auprobe, + struct arch_uprobe_task *autask, + struct pt_regs *regs); + void (*posthandler)(struct arch_uprobe *auprobe, + struct arch_uprobe_task *autask, + struct pt_regs *regs); + struct arch_probes_insn asi; +}; + +#endif diff -Nur linux-3.14.1/arch/arm/include/asm/xen/page.h linux-3.15-rc1.orig/arch/arm/include/asm/xen/page.h --- linux-3.14.1/arch/arm/include/asm/xen/page.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/asm/xen/page.h 2014-04-13 23:18:35.000000000 +0200 @@ -97,16 +97,13 @@ return NULL; } -static inline int m2p_add_override(unsigned long mfn, struct page *page, - struct gnttab_map_grant_ref *kmap_op) -{ - return 0; -} +extern int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops, + struct gnttab_map_grant_ref *kmap_ops, + struct page **pages, unsigned int count); -static inline int m2p_remove_override(struct page *page, bool clear_pte) -{ - return 0; -} +extern int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops, + struct gnttab_map_grant_ref *kmap_ops, + struct page **pages, unsigned int count); bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn); bool __set_phys_to_machine_multi(unsigned long pfn, unsigned long mfn, diff -Nur linux-3.14.1/arch/arm/include/debug/samsung.S linux-3.15-rc1.orig/arch/arm/include/debug/samsung.S --- linux-3.14.1/arch/arm/include/debug/samsung.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/debug/samsung.S 2014-04-13 23:18:35.000000000 +0200 @@ -9,7 +9,7 @@ * published by the Free Software Foundation. */ -#include +#include /* The S5PV210/S5PC110 implementations are as belows. */ diff -Nur linux-3.14.1/arch/arm/include/debug/tegra.S linux-3.15-rc1.orig/arch/arm/include/debug/tegra.S --- linux-3.14.1/arch/arm/include/debug/tegra.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/debug/tegra.S 2014-04-13 23:18:35.000000000 +0200 @@ -53,8 +53,7 @@ #define checkuart(rp, rv, lhu, bit, uart) \ /* Load address of CLK_RST register */ \ - movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \ - movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \ + ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \ /* Load value from CLK_RST register */ \ ldr rp, [rp, #0] ; \ /* Test UART's reset bit */ \ @@ -62,8 +61,7 @@ /* If set, can't use UART; jump to save no UART */ \ bne 90f ; \ /* Load address of CLK_OUT_ENB register */ \ - movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \ - movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \ + ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \ /* Load value from CLK_OUT_ENB register */ \ ldr rp, [rp, #0] ; \ /* Test UART's clock enable bit */ \ @@ -71,8 +69,7 @@ /* If clear, can't use UART; jump to save no UART */ \ beq 90f ; \ /* Passed all tests, load address of UART registers */ \ - movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \ - movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \ + ldr rp, =TEGRA_UART##uart##_BASE ; \ /* Jump to save UART address */ \ b 91f @@ -90,15 +87,16 @@ #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA /* Check ODMDATA */ -10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff - movt \rp, #TEGRA_PMC_SCRATCH20 >> 16 +10: ldr \rp, =TEGRA_PMC_SCRATCH20 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20 - ubfx \rv, \rp, #18, #2 @ 19:18 are console type + lsr \rv, \rp, #18 @ 19:18 are console type + and \rv, \rv, #3 cmp \rv, #2 @ 2 and 3 mean DCC, UART beq 11f @ some boards swap the meaning cmp \rv, #3 @ so accept either bne 90f -11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID +11: lsr \rv, \rp, #15 @ 17:15 are UART ID + and \rv, #7 cmp \rv, #0 @ UART 0? beq 20f cmp \rv, #1 @ UART 1? diff -Nur linux-3.14.1/arch/arm/include/debug/zynq.S linux-3.15-rc1.orig/arch/arm/include/debug/zynq.S --- linux-3.14.1/arch/arm/include/debug/zynq.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/debug/zynq.S 2014-04-13 23:18:35.000000000 +0200 @@ -42,6 +42,9 @@ .endm .macro waituart,rd,rx +1001: ldr \rd, [\rx, #UART_SR_OFFSET] + tst \rd, #UART_SR_TXEMPTY + beq 1001b .endm .macro busyuart,rd,rx diff -Nur linux-3.14.1/arch/arm/include/uapi/asm/hwcap.h linux-3.15-rc1.orig/arch/arm/include/uapi/asm/hwcap.h --- linux-3.14.1/arch/arm/include/uapi/asm/hwcap.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/include/uapi/asm/hwcap.h 2014-04-13 23:18:35.000000000 +0200 @@ -28,4 +28,13 @@ #define HWCAP_LPAE (1 << 20) #define HWCAP_EVTSTRM (1 << 21) +/* + * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2 + */ +#define HWCAP2_AES (1 << 0) +#define HWCAP2_PMULL (1 << 1) +#define HWCAP2_SHA1 (1 << 2) +#define HWCAP2_SHA2 (1 << 3) +#define HWCAP2_CRC32 (1 << 4) + #endif /* _UAPI__ASMARM_HWCAP_H */ diff -Nur linux-3.14.1/arch/arm/Kconfig linux-3.15-rc1.orig/arch/arm/Kconfig --- linux-3.14.1/arch/arm/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -24,6 +24,7 @@ select GENERIC_STRNCPY_FROM_USER select GENERIC_STRNLEN_USER select HARDIRQS_SW_RESEND + select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) @@ -113,9 +114,6 @@ endif -config HAVE_PWM - bool - config MIGHT_HAVE_PCI bool @@ -129,7 +127,7 @@ config HAVE_PROC_CPU bool -config NO_IOPORT +config NO_IOPORT_MAP bool config EISA @@ -207,6 +205,9 @@ config NEED_DMA_MAP_STATE def_bool y +config ARCH_SUPPORTS_UPROBES + def_bool y + config ARCH_HAS_DMA_SET_COHERENT_MASK bool @@ -306,9 +307,12 @@ config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" depends on MMU + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_HAS_SG_CHAIN select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR select COMMON_CLK + select GENERIC_CLOCKEVENTS select MULTI_IRQ_HANDLER select SPARSE_IRQ select USE_OF @@ -388,8 +392,6 @@ select CPU_ARM720T select GENERIC_CLOCKEVENTS select MFD_SYSCON - select MULTI_IRQ_HANDLER - select SPARSE_IRQ help Support for Cirrus Logic 711x/721x/731x based boards. @@ -409,7 +411,7 @@ select ISA select NEED_MACH_IO_H select NEED_MACH_MEMORY_H - select NO_IOPORT + select NO_IOPORT_MAP help This is an evaluation board for the StrongARM processor available from Digital. It has limited hardware on-board, including an @@ -420,16 +422,14 @@ bool "Energy Micro efm32" depends on !MMU select ARCH_REQUIRE_GPIOLIB + select AUTO_ZRELADDR select ARM_NVIC - # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged, - # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO - select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK select CPU_V7M select GENERIC_CLOCKEVENTS select NO_DMA - select NO_IOPORT + select NO_IOPORT_MAP select SPARSE_IRQ select USE_OF help @@ -534,7 +534,6 @@ select PINCTRL select PINCTRL_DOVE select PLAT_ORION_LEGACY - select USB_ARCH_HAS_EHCI help Support for the Marvell Dove SoC 88AP510 @@ -632,8 +631,6 @@ select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_IDE - select HAVE_PWM - select USB_ARCH_HAS_OHCI select USE_OF help Support for the NXP LPC32XX family of processors @@ -657,9 +654,8 @@ help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. -config ARCH_MSM_NODT - bool "Qualcomm MSM" - select ARCH_MSM +config ARCH_MSM + bool "Qualcomm MSM (non-multiplatform)" select ARCH_REQUIRE_GPIOLIB select COMMON_CLK select GENERIC_CLOCKEVENTS @@ -682,7 +678,7 @@ select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select MULTI_IRQ_HANDLER - select NO_IOPORT + select NO_IOPORT_MAP select PINCTRL select PM_GENERIC_DOMAINS if PM select SPARSE_IRQ @@ -697,13 +693,14 @@ select ARCH_MAY_HAVE_PC_FDC select ARCH_SPARSEMEM_ENABLE select ARCH_USES_GETTIMEOFFSET + select CPU_SA110 select FIQ select HAVE_IDE select HAVE_PATA_PLATFORM select ISA_DMA_API select NEED_MACH_IO_H select NEED_MACH_MEMORY_H - select NO_IOPORT + select NO_IOPORT_MAP select VIRT_TO_BUS help On the Acorn Risc-PC, Linux can support the internal IDE disk and @@ -731,6 +728,7 @@ bool "Samsung S3C24XX SoCs" select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS @@ -753,6 +751,7 @@ select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select ARM_VIC + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select COMMON_CLK @@ -762,20 +761,20 @@ select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_TCM - select NO_IOPORT + select NO_IOPORT_MAP select PLAT_SAMSUNG - select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS if PM select S3C_DEV_NAND select S3C_GPIO_TRACK select SAMSUNG_ATAGS select SAMSUNG_WAKEMASK select SAMSUNG_WDT_RESET - select USB_ARCH_HAS_OHCI help Samsung S3C64XX series based systems config ARCH_S5P64X0 bool "Samsung S5P6440 S5P6450" + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select CPU_V6 @@ -794,6 +793,7 @@ config ARCH_S5PC100 bool "Samsung S5PC100" select ARCH_REQUIRE_GPIOLIB + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select CPU_V7 @@ -813,6 +813,7 @@ select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SPARSEMEM_ENABLE + select ATAGS select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select CPU_V7 @@ -886,6 +887,12 @@ comment "CPU Core family selection" +config ARCH_MULTI_V4 + bool "ARMv4 based platforms (FA526)" + depends on !ARCH_MULTI_V6_V7 + select ARCH_MULTI_V4_V5 + select CPU_FA526 + config ARCH_MULTI_V4T bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" depends on !ARCH_MULTI_V6_V7 @@ -898,7 +905,7 @@ bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" depends on !ARCH_MULTI_V6_V7 select ARCH_MULTI_V4_V5 - select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ + select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) @@ -908,16 +915,18 @@ config ARCH_MULTI_V6 bool "ARMv6 based platforms (ARM11)" select ARCH_MULTI_V6_V7 - select CPU_V6 + select CPU_V6K config ARCH_MULTI_V7 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" default y select ARCH_MULTI_V6_V7 select CPU_V7 + select HAVE_SMP config ARCH_MULTI_V6_V7 bool + select MIGHT_HAVE_CACHE_L2X0 config ARCH_MULTI_CPU_AUTO def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) @@ -925,6 +934,13 @@ endmenu +config ARCH_VIRT + bool "Dummy Virtual Machine" if ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select ARM_PSCI + select HAVE_ARM_ARCH_TIMER + # # This is sorted alphabetically by mach-* pathname. However, plat-* # Kconfigs may be included either alphabetically (according to the @@ -936,8 +952,6 @@ source "arch/arm/mach-bcm/Kconfig" -source "arch/arm/mach-bcm2835/Kconfig" - source "arch/arm/mach-berlin/Kconfig" source "arch/arm/mach-clps711x/Kconfig" @@ -1005,6 +1019,8 @@ source "arch/arm/mach-mmp/Kconfig" +source "arch/arm/mach-qcom/Kconfig" + source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-rockchip/Kconfig" @@ -1048,8 +1064,6 @@ source "arch/arm/mach-vexpress/Kconfig" source "arch/arm/plat-versatile/Kconfig" -source "arch/arm/mach-virt/Kconfig" - source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-w90x900/Kconfig" @@ -1921,6 +1935,7 @@ select IRQ_DOMAIN select OF select OF_EARLY_FLATTREE + select OF_RESERVED_MEM help Include support for flattened device tree machine descriptions. @@ -2273,7 +2288,7 @@ config ARCH_SUSPEND_POSSIBLE depends on !ARCH_S5PC100 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ - CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK + CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK def_bool y config ARM_CPU_SUSPEND diff -Nur linux-3.14.1/arch/arm/Kconfig.debug linux-3.15-rc1.orig/arch/arm/Kconfig.debug --- linux-3.14.1/arch/arm/Kconfig.debug 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/Kconfig.debug 2014-04-13 23:18:35.000000000 +0200 @@ -106,9 +106,14 @@ depends on ARCH_BCM2835 select DEBUG_UART_PL01X + config DEBUG_BCM_5301X + bool "Kernel low-level debugging on BCM5301X UART1" + depends on ARCH_BCM_5301X + select DEBUG_UART_PL01X + config DEBUG_BCM_KONA_UART bool "Kernel low-level debugging messages via BCM KONA UART" - depends on ARCH_BCM + depends on ARCH_BCM_MOBILE select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support @@ -171,15 +176,6 @@ Say Y here if you want the debug print routines to direct their output to UART0 serial port on DaVinci DMx devices. - config DEBUG_DAVINCI_TNETV107X_UART1 - bool "Kernel low-level debugging on DaVinci TNETV107x using UART1" - depends on ARCH_DAVINCI_TNETV107X - select DEBUG_UART_8250 - help - Say Y here if you want the debug print routines to direct - their output to UART1 serial port on DaVinci TNETV107X - devices. - config DEBUG_ZYNQ_UART0 bool "Kernel low-level debugging on Xilinx Zynq using UART0" depends on ARCH_ZYNQ @@ -956,7 +952,7 @@ config DEBUG_MSM_UART bool - depends on ARCH_MSM + depends on ARCH_MSM || ARCH_QCOM config DEBUG_LL_INCLUDE string @@ -1014,7 +1010,6 @@ default 0x02530c00 if DEBUG_KEYSTONE_UART0 default 0x02531000 if DEBUG_KEYSTONE_UART1 default 0x03010fe0 if ARCH_RPC - default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1 default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \ DEBUG_VEXPRESS_UART0_CA9 default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT @@ -1023,6 +1018,7 @@ default 0x101f1000 if ARCH_VERSATILE default 0x101fb000 if DEBUG_NOMADIK_UART default 0x16000000 if ARCH_INTEGRATOR + default 0x18000300 if DEBUG_BCM_5301X default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 default 0x20060000 if DEBUG_RK29_UART0 default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 @@ -1071,6 +1067,7 @@ default 0xf0009000 if DEBUG_CNS3XXX default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf0201000 if DEBUG_BCM2835 + default 0xf1000300 if DEBUG_BCM_5301X default 0xf11f1000 if ARCH_VERSATILE default 0xf1600000 if ARCH_INTEGRATOR default 0xf1c28000 if DEBUG_SUNXI_UART0 @@ -1110,7 +1107,6 @@ default 0xfed12000 if ARCH_KIRKWOOD default 0xfedc0000 if ARCH_EP93XX default 0xfee003f8 if FOOTBRIDGE - default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1 default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART default 0xfef36000 if DEBUG_HIGHBANK_UART default 0xfee82340 if ARCH_IOP13XX @@ -1135,7 +1131,7 @@ default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \ ARCH_KEYSTONE || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ - DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \ + DEBUG_DAVINCI_DA8XX_UART2 || \ DEBUG_BCM_KONA_UART config DEBUG_UART_8250_FLOW_CONTROL @@ -1145,7 +1141,7 @@ config DEBUG_UNCOMPRESS bool - depends on ARCH_MULTIPLATFORM || ARCH_MSM + depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \ (!DEBUG_TEGRA_UART || !ZBOOT_ROM) help @@ -1161,7 +1157,8 @@ config UNCOMPRESS_INCLUDE string - default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM + default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ + PLAT_SAMSUNG || ARCH_EFM32 default "mach/uncompress.h" config EARLY_PRINTK diff -Nur linux-3.14.1/arch/arm/kernel/armksyms.c linux-3.15-rc1.orig/arch/arm/kernel/armksyms.c --- linux-3.14.1/arch/arm/kernel/armksyms.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/armksyms.c 2014-04-13 23:18:35.000000000 +0200 @@ -158,6 +158,6 @@ #endif #ifdef CONFIG_ARM_PATCH_PHYS_VIRT -EXPORT_SYMBOL(__pv_phys_offset); +EXPORT_SYMBOL(__pv_phys_pfn_offset); EXPORT_SYMBOL(__pv_offset); #endif diff -Nur linux-3.14.1/arch/arm/kernel/asm-offsets.c linux-3.15-rc1.orig/arch/arm/kernel/asm-offsets.c --- linux-3.14.1/arch/arm/kernel/asm-offsets.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/asm-offsets.c 2014-04-13 23:18:35.000000000 +0200 @@ -174,6 +174,7 @@ DEFINE(VCPU_FIQ_REGS, offsetof(struct kvm_vcpu, arch.regs.fiq_regs)); DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc)); DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr)); + DEFINE(VCPU_HCR, offsetof(struct kvm_vcpu, arch.hcr)); DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines)); DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.fault.hsr)); DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.fault.hxfar)); diff -Nur linux-3.14.1/arch/arm/kernel/bios32.c linux-3.15-rc1.orig/arch/arm/kernel/bios32.c --- linux-3.14.1/arch/arm/kernel/bios32.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/bios32.c 2014-04-13 23:18:35.000000000 +0200 @@ -19,7 +19,7 @@ static int debug_pci; /* - * We can't use pci_find_device() here since we are + * We can't use pci_get_device() here since we are * called from interrupt context. */ static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) @@ -57,13 +57,10 @@ void pcibios_report_status(u_int status_mask, int warn) { - struct list_head *l; - - list_for_each(l, &pci_root_buses) { - struct pci_bus *bus = pci_bus_b(l); + struct pci_bus *bus; + list_for_each_entry(bus, &pci_root_buses, node) pcibios_bus_report_status(bus, status_mask, warn); - } } /* @@ -608,41 +605,10 @@ */ int pcibios_enable_device(struct pci_dev *dev, int mask) { - u16 cmd, old_cmd; - int idx; - struct resource *r; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for (idx = 0; idx < 6; idx++) { - /* Only set up the requested stuff */ - if (!(mask & (1 << idx))) - continue; - - r = dev->resource + idx; - if (!r->start && r->end) { - printk(KERN_ERR "PCI: Device %s not available because" - " of resource collisions\n", pci_name(dev)); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - - /* - * Bridges (eg, cardbus bridges) need to be fully enabled - */ - if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) - cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + if (pci_has_flag(PCI_PROBE_ONLY)) + return 0; - if (cmd != old_cmd) { - printk("PCI: enabling device %s (%04x -> %04x)\n", - pci_name(dev), old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; + return pci_enable_resources(dev, mask); } int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, diff -Nur linux-3.14.1/arch/arm/kernel/crash_dump.c linux-3.15-rc1.orig/arch/arm/kernel/crash_dump.c --- linux-3.14.1/arch/arm/kernel/crash_dump.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/crash_dump.c 2014-04-13 23:18:35.000000000 +0200 @@ -39,7 +39,7 @@ if (!csize) return 0; - vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE); + vaddr = ioremap(__pfn_to_phys(pfn), PAGE_SIZE); if (!vaddr) return -ENOMEM; diff -Nur linux-3.14.1/arch/arm/kernel/devtree.c linux-3.15-rc1.orig/arch/arm/kernel/devtree.c --- linux-3.14.1/arch/arm/kernel/devtree.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/devtree.c 2014-04-13 23:18:35.000000000 +0200 @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -63,6 +64,34 @@ } } +#ifdef CONFIG_SMP +extern struct of_cpu_method __cpu_method_of_table_begin[]; +extern struct of_cpu_method __cpu_method_of_table_end[]; + +static int __init set_smp_ops_by_method(struct device_node *node) +{ + const char *method; + struct of_cpu_method *m = __cpu_method_of_table_begin; + + if (of_property_read_string(node, "enable-method", &method)) + return 0; + + for (; m < __cpu_method_of_table_end; m++) + if (!strcmp(m->method, method)) { + smp_set_ops(m->ops); + return 1; + } + + return 0; +} +#else +static inline int set_smp_ops_by_method(struct device_node *node) +{ + return 1; +} +#endif + + /* * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree * and builds the cpu logical map array containing MPIDR values related to @@ -79,6 +108,7 @@ * read as 0. */ struct device_node *cpu, *cpus; + int found_method = 0; u32 i, j, cpuidx = 1; u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; @@ -150,8 +180,18 @@ } tmp_map[i] = hwid; + + if (!found_method) + found_method = set_smp_ops_by_method(cpu); } + /* + * Fallback to an enable-method in the cpus node if nothing found in + * a cpu node. + */ + if (!found_method) + set_smp_ops_by_method(cpus); + if (!bootcpu_valid) { pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); return; diff -Nur linux-3.14.1/arch/arm/kernel/entry-header.S linux-3.15-rc1.orig/arch/arm/kernel/entry-header.S --- linux-3.14.1/arch/arm/kernel/entry-header.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/entry-header.S 2014-04-13 23:18:35.000000000 +0200 @@ -236,11 +236,6 @@ movs pc, lr @ return & move spsr_svc into cpsr .endm - .macro get_thread_info, rd - mov \rd, sp, lsr #13 - mov \rd, \rd, lsl #13 - .endm - @ @ 32-bit wide "mov pc, reg" @ @@ -306,12 +301,6 @@ .endm #endif /* ifdef CONFIG_CPU_V7M / else */ - .macro get_thread_info, rd - mov \rd, sp - lsr \rd, \rd, #13 - mov \rd, \rd, lsl #13 - .endm - @ @ 32-bit wide "mov pc, reg" @ diff -Nur linux-3.14.1/arch/arm/kernel/ftrace.c linux-3.15-rc1.orig/arch/arm/kernel/ftrace.c --- linux-3.14.1/arch/arm/kernel/ftrace.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/ftrace.c 2014-04-13 23:18:35.000000000 +0200 @@ -156,10 +156,8 @@ return ret; } -int __init ftrace_dyn_arch_init(void *data) +int __init ftrace_dyn_arch_init(void) { - *(unsigned long *)data = 0; - return 0; } #endif /* CONFIG_DYNAMIC_FTRACE */ diff -Nur linux-3.14.1/arch/arm/kernel/head.S linux-3.15-rc1.orig/arch/arm/kernel/head.S --- linux-3.14.1/arch/arm/kernel/head.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/head.S 2014-04-13 23:18:35.000000000 +0200 @@ -584,9 +584,10 @@ subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET add r4, r4, r3 @ adjust table start address add r5, r5, r3 @ adjust table end address - add r6, r6, r3 @ adjust __pv_phys_offset address + add r6, r6, r3 @ adjust __pv_phys_pfn_offset address add r7, r7, r3 @ adjust __pv_offset address - str r8, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_offset + mov r0, r8, lsr #12 @ convert to PFN + str r0, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits mov r6, r3, lsr #24 @ constant for add/sub instructions teq r3, r6, lsl #24 @ must be 16MiB aligned @@ -600,7 +601,7 @@ 1: .long . .long __pv_table_begin .long __pv_table_end -2: .long __pv_phys_offset +2: .long __pv_phys_pfn_offset .long __pv_offset .text @@ -688,11 +689,11 @@ ENDPROC(fixup_pv_table) .data - .globl __pv_phys_offset - .type __pv_phys_offset, %object -__pv_phys_offset: - .quad 0 - .size __pv_phys_offset, . -__pv_phys_offset + .globl __pv_phys_pfn_offset + .type __pv_phys_pfn_offset, %object +__pv_phys_pfn_offset: + .word 0 + .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset .globl __pv_offset .type __pv_offset, %object diff -Nur linux-3.14.1/arch/arm/kernel/hw_breakpoint.c linux-3.15-rc1.orig/arch/arm/kernel/hw_breakpoint.c --- linux-3.14.1/arch/arm/kernel/hw_breakpoint.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/hw_breakpoint.c 2014-04-13 23:18:35.000000000 +0200 @@ -167,7 +167,7 @@ /* Can we determine the watchpoint access type from the fsr? */ static int debug_exception_updates_fsr(void) { - return 0; + return get_debug_arch() >= ARM_DEBUG_ARCH_V8; } /* Determine number of WRP registers available. */ @@ -257,6 +257,7 @@ break; case ARM_DEBUG_ARCH_V7_ECP14: case ARM_DEBUG_ARCH_V7_1: + case ARM_DEBUG_ARCH_V8: ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN)); isb(); break; @@ -1072,6 +1073,8 @@ core_num_brps = get_num_brps(); core_num_wrps = get_num_wrps(); + cpu_notifier_register_begin(); + /* * We need to tread carefully here because DBGSWENABLE may be * driven low on this core and there isn't an architected way to @@ -1088,6 +1091,7 @@ if (!cpumask_empty(&debug_err_mask)) { core_num_brps = 0; core_num_wrps = 0; + cpu_notifier_register_done(); return 0; } @@ -1107,7 +1111,10 @@ TRAP_HWBKPT, "breakpoint debug exception"); /* Register hotplug and PM notifiers. */ - register_cpu_notifier(&dbg_reset_nb); + __register_cpu_notifier(&dbg_reset_nb); + + cpu_notifier_register_done(); + pm_init(); return 0; } diff -Nur linux-3.14.1/arch/arm/kernel/kprobes-arm.c linux-3.15-rc1.orig/arch/arm/kernel/kprobes-arm.c --- linux-3.14.1/arch/arm/kernel/kprobes-arm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes-arm.c 2014-04-13 23:18:35.000000000 +0200 @@ -60,13 +60,10 @@ #include #include -#include +#include #include "kprobes.h" - -#define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit))))) - -#define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25) +#include "probes-arm.h" #if __LINUX_ARM_ARCH__ >= 6 #define BLX(reg) "blx "reg" \n\t" @@ -75,92 +72,11 @@ "mov pc, "reg" \n\t" #endif -/* - * To avoid the complications of mimicing single-stepping on a - * processor without a Next-PC or a single-step mode, and to - * avoid having to deal with the side-effects of boosting, we - * simulate or emulate (almost) all ARM instructions. - * - * "Simulation" is where the instruction's behavior is duplicated in - * C code. "Emulation" is where the original instruction is rewritten - * and executed, often by altering its registers. - * - * By having all behavior of the kprobe'd instruction completed before - * returning from the kprobe_handler(), all locks (scheduler and - * interrupt) can safely be released. There is no need for secondary - * breakpoints, no race with MP or preemptable kernels, nor having to - * clean up resources counts at a later time impacting overall system - * performance. By rewriting the instruction, only the minimum registers - * need to be loaded and saved back optimizing performance. - * - * Calling the insnslot_*_rwflags version of a function doesn't hurt - * anything even when the CPSR flags aren't updated by the - * instruction. It's just a little slower in return for saving - * a little space by not having a duplicate function that doesn't - * update the flags. (The same optimization can be said for - * instructions that do or don't perform register writeback) - * Also, instructions can either read the flags, only write the - * flags, or read and write the flags. To save combinations - * rather than for sheer performance, flag functions just assume - * read and write of flags. - */ - -static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs) -{ - kprobe_opcode_t insn = p->opcode; - long iaddr = (long)p->addr; - int disp = branch_displacement(insn); - - if (insn & (1 << 24)) - regs->ARM_lr = iaddr + 4; - - regs->ARM_pc = iaddr + 8 + disp; -} - -static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs) -{ - kprobe_opcode_t insn = p->opcode; - long iaddr = (long)p->addr; - int disp = branch_displacement(insn); - - regs->ARM_lr = iaddr + 4; - regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2); - regs->ARM_cpsr |= PSR_T_BIT; -} - -static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs) -{ - kprobe_opcode_t insn = p->opcode; - int rm = insn & 0xf; - long rmv = regs->uregs[rm]; - - if (insn & (1 << 5)) - regs->ARM_lr = (long)p->addr + 4; - - regs->ARM_pc = rmv & ~0x1; - regs->ARM_cpsr &= ~PSR_T_BIT; - if (rmv & 0x1) - regs->ARM_cpsr |= PSR_T_BIT; -} - -static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs) -{ - kprobe_opcode_t insn = p->opcode; - int rd = (insn >> 12) & 0xf; - unsigned long mask = 0xf8ff03df; /* Mask out execution state */ - regs->uregs[rd] = regs->ARM_cpsr & mask; -} - -static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs) -{ - regs->uregs[12] = regs->uregs[13]; -} - static void __kprobes -emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs) +emulate_ldrdstrd(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = (unsigned long)p->addr + 8; + unsigned long pc = regs->ARM_pc + 4; int rt = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -175,7 +91,7 @@ BLX("%[fn]") : "=r" (rtv), "=r" (rt2v), "=r" (rnv) : "0" (rtv), "1" (rt2v), "2" (rnv), "r" (rmv), - [fn] "r" (p->ainsn.insn_fn) + [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -186,10 +102,10 @@ } static void __kprobes -emulate_ldr(struct kprobe *p, struct pt_regs *regs) +emulate_ldr(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = (unsigned long)p->addr + 8; + unsigned long pc = regs->ARM_pc + 4; int rt = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -202,7 +118,7 @@ __asm__ __volatile__ ( BLX("%[fn]") : "=r" (rtv), "=r" (rnv) - : "1" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn) + : "1" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -216,11 +132,11 @@ } static void __kprobes -emulate_str(struct kprobe *p, struct pt_regs *regs) +emulate_str(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long rtpc = (unsigned long)p->addr + str_pc_offset; - unsigned long rnpc = (unsigned long)p->addr + 8; + unsigned long rtpc = regs->ARM_pc - 4 + str_pc_offset; + unsigned long rnpc = regs->ARM_pc + 4; int rt = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -234,7 +150,7 @@ __asm__ __volatile__ ( BLX("%[fn]") : "=r" (rnv) - : "r" (rtv), "0" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn) + : "r" (rtv), "0" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -243,10 +159,10 @@ } static void __kprobes -emulate_rd12rn16rm0rs8_rwflags(struct kprobe *p, struct pt_regs *regs) +emulate_rd12rn16rm0rs8_rwflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = (unsigned long)p->addr + 8; + unsigned long pc = regs->ARM_pc + 4; int rd = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -266,7 +182,7 @@ "mrs %[cpsr], cpsr \n\t" : "=r" (rdv), [cpsr] "=r" (cpsr) : "0" (rdv), "r" (rnv), "r" (rmv), "r" (rsv), - "1" (cpsr), [fn] "r" (p->ainsn.insn_fn) + "1" (cpsr), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -278,9 +194,9 @@ } static void __kprobes -emulate_rd12rn16rm0_rwflags_nopc(struct kprobe *p, struct pt_regs *regs) +emulate_rd12rn16rm0_rwflags_nopc(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rd = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -296,7 +212,7 @@ "mrs %[cpsr], cpsr \n\t" : "=r" (rdv), [cpsr] "=r" (cpsr) : "0" (rdv), "r" (rnv), "r" (rmv), - "1" (cpsr), [fn] "r" (p->ainsn.insn_fn) + "1" (cpsr), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -305,9 +221,10 @@ } static void __kprobes -emulate_rd16rn12rm0rs8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs) +emulate_rd16rn12rm0rs8_rwflags_nopc(probes_opcode_t insn, + struct arch_probes_insn *asi, + struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rd = (insn >> 16) & 0xf; int rn = (insn >> 12) & 0xf; int rm = insn & 0xf; @@ -325,7 +242,7 @@ "mrs %[cpsr], cpsr \n\t" : "=r" (rdv), [cpsr] "=r" (cpsr) : "0" (rdv), "r" (rnv), "r" (rmv), "r" (rsv), - "1" (cpsr), [fn] "r" (p->ainsn.insn_fn) + "1" (cpsr), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -334,9 +251,9 @@ } static void __kprobes -emulate_rd12rm0_noflags_nopc(struct kprobe *p, struct pt_regs *regs) +emulate_rd12rm0_noflags_nopc(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rd = (insn >> 12) & 0xf; int rm = insn & 0xf; @@ -346,7 +263,7 @@ __asm__ __volatile__ ( BLX("%[fn]") : "=r" (rdv) - : "0" (rdv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn) + : "0" (rdv), "r" (rmv), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -354,9 +271,10 @@ } static void __kprobes -emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs) +emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(probes_opcode_t insn, + struct arch_probes_insn *asi, + struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rdlo = (insn >> 12) & 0xf; int rdhi = (insn >> 16) & 0xf; int rn = insn & 0xf; @@ -374,7 +292,7 @@ "mrs %[cpsr], cpsr \n\t" : "=r" (rdlov), "=r" (rdhiv), [cpsr] "=r" (cpsr) : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv), - "2" (cpsr), [fn] "r" (p->ainsn.insn_fn) + "2" (cpsr), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -383,623 +301,43 @@ regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); } -/* - * For the instruction masking and comparisons in all the "space_*" - * functions below, Do _not_ rearrange the order of tests unless - * you're very, very sure of what you are doing. For the sake of - * efficiency, the masks for some tests sometimes assume other test - * have been done prior to them so the number of patterns to test - * for an instruction set can be as broad as possible to reduce the - * number of tests needed. - */ - -static const union decode_item arm_1111_table[] = { - /* Unconditional instructions */ - - /* memory hint 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */ - /* PLDI (immediate) 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */ - /* PLDW (immediate) 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */ - /* PLD (immediate) 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */ - DECODE_SIMULATE (0xfe300000, 0xf4100000, kprobe_simulate_nop), - - /* memory hint 1111 0110 x001 xxxx xxxx xxxx xxx0 xxxx */ - /* PLDI (register) 1111 0110 x101 xxxx xxxx xxxx xxx0 xxxx */ - /* PLDW (register) 1111 0111 x001 xxxx xxxx xxxx xxx0 xxxx */ - /* PLD (register) 1111 0111 x101 xxxx xxxx xxxx xxx0 xxxx */ - DECODE_SIMULATE (0xfe300010, 0xf6100000, kprobe_simulate_nop), - - /* BLX (immediate) 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */ - DECODE_SIMULATE (0xfe000000, 0xfa000000, simulate_blx1), - - /* CPS 1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */ - /* SETEND 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */ - /* SRS 1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */ - /* RFE 1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ - - /* Coprocessor instructions... */ - /* MCRR2 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */ - /* MRRC2 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */ - /* LDC2 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ - /* STC2 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ - /* CDP2 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ - /* MCR2 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ - /* MRC2 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - - /* Other unallocated instructions... */ - DECODE_END -}; - -static const union decode_item arm_cccc_0001_0xx0____0xxx_table[] = { - /* Miscellaneous instructions */ - - /* MRS cpsr cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */ - DECODE_SIMULATEX(0x0ff000f0, 0x01000000, simulate_mrs, - REGS(0, NOPC, 0, 0, 0)), - - /* BX cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */ - DECODE_SIMULATE (0x0ff000f0, 0x01200010, simulate_blx2bx), - - /* BLX (register) cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */ - DECODE_SIMULATEX(0x0ff000f0, 0x01200030, simulate_blx2bx, - REGS(0, 0, 0, 0, NOPC)), - - /* CLZ cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */ - DECODE_EMULATEX (0x0ff000f0, 0x01600010, emulate_rd12rm0_noflags_nopc, - REGS(0, NOPC, 0, 0, NOPC)), - - /* QADD cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx */ - /* QSUB cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx */ - /* QDADD cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx */ - /* QDSUB cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx */ - DECODE_EMULATEX (0x0f9000f0, 0x01000050, emulate_rd12rn16rm0_rwflags_nopc, - REGS(NOPC, NOPC, 0, 0, NOPC)), - - /* BXJ cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ - /* MSR cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ - /* MRS spsr cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */ - /* BKPT 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ - /* SMC cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */ - /* And unallocated instructions... */ - DECODE_END -}; - -static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = { - /* Halfword multiply and multiply-accumulate */ - - /* SMLALxy cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */ - DECODE_EMULATEX (0x0ff00090, 0x01400080, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc, - REGS(NOPC, NOPC, NOPC, 0, NOPC)), - - /* SMULWy cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */ - DECODE_OR (0x0ff000b0, 0x012000a0), - /* SMULxy cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */ - DECODE_EMULATEX (0x0ff00090, 0x01600080, emulate_rd16rn12rm0rs8_rwflags_nopc, - REGS(NOPC, 0, NOPC, 0, NOPC)), - - /* SMLAxy cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx */ - DECODE_OR (0x0ff00090, 0x01000080), - /* SMLAWy cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx */ - DECODE_EMULATEX (0x0ff000b0, 0x01200080, emulate_rd16rn12rm0rs8_rwflags_nopc, - REGS(NOPC, NOPC, NOPC, 0, NOPC)), - - DECODE_END -}; - -static const union decode_item arm_cccc_0000_____1001_table[] = { - /* Multiply and multiply-accumulate */ - - /* MUL cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx */ - /* MULS cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx */ - DECODE_EMULATEX (0x0fe000f0, 0x00000090, emulate_rd16rn12rm0rs8_rwflags_nopc, - REGS(NOPC, 0, NOPC, 0, NOPC)), - - /* MLA cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx */ - /* MLAS cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx */ - DECODE_OR (0x0fe000f0, 0x00200090), - /* MLS cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx */ - DECODE_EMULATEX (0x0ff000f0, 0x00600090, emulate_rd16rn12rm0rs8_rwflags_nopc, - REGS(NOPC, NOPC, NOPC, 0, NOPC)), - - /* UMAAL cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx */ - DECODE_OR (0x0ff000f0, 0x00400090), - /* UMULL cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx */ - /* UMULLS cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx */ - /* UMLAL cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx */ - /* UMLALS cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx */ - /* SMULL cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx */ - /* SMULLS cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */ - /* SMLAL cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */ - /* SMLALS cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */ - DECODE_EMULATEX (0x0f8000f0, 0x00800090, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc, - REGS(NOPC, NOPC, NOPC, 0, NOPC)), - - DECODE_END +const union decode_action kprobes_arm_actions[NUM_PROBES_ARM_ACTIONS] = { + [PROBES_EMULATE_NONE] = {.handler = probes_emulate_none}, + [PROBES_SIMULATE_NOP] = {.handler = probes_simulate_nop}, + [PROBES_PRELOAD_IMM] = {.handler = probes_simulate_nop}, + [PROBES_PRELOAD_REG] = {.handler = probes_simulate_nop}, + [PROBES_BRANCH_IMM] = {.handler = simulate_blx1}, + [PROBES_MRS] = {.handler = simulate_mrs}, + [PROBES_BRANCH_REG] = {.handler = simulate_blx2bx}, + [PROBES_CLZ] = {.handler = emulate_rd12rm0_noflags_nopc}, + [PROBES_SATURATING_ARITHMETIC] = { + .handler = emulate_rd12rn16rm0_rwflags_nopc}, + [PROBES_MUL1] = {.handler = emulate_rdlo12rdhi16rn0rm8_rwflags_nopc}, + [PROBES_MUL2] = {.handler = emulate_rd16rn12rm0rs8_rwflags_nopc}, + [PROBES_SWP] = {.handler = emulate_rd12rn16rm0_rwflags_nopc}, + [PROBES_LDRSTRD] = {.handler = emulate_ldrdstrd}, + [PROBES_LOAD_EXTRA] = {.handler = emulate_ldr}, + [PROBES_LOAD] = {.handler = emulate_ldr}, + [PROBES_STORE_EXTRA] = {.handler = emulate_str}, + [PROBES_STORE] = {.handler = emulate_str}, + [PROBES_MOV_IP_SP] = {.handler = simulate_mov_ipsp}, + [PROBES_DATA_PROCESSING_REG] = { + .handler = emulate_rd12rn16rm0rs8_rwflags}, + [PROBES_DATA_PROCESSING_IMM] = { + .handler = emulate_rd12rn16rm0rs8_rwflags}, + [PROBES_MOV_HALFWORD] = {.handler = emulate_rd12rm0_noflags_nopc}, + [PROBES_SEV] = {.handler = probes_emulate_none}, + [PROBES_WFE] = {.handler = probes_simulate_nop}, + [PROBES_SATURATE] = {.handler = emulate_rd12rn16rm0_rwflags_nopc}, + [PROBES_REV] = {.handler = emulate_rd12rm0_noflags_nopc}, + [PROBES_MMI] = {.handler = emulate_rd12rn16rm0_rwflags_nopc}, + [PROBES_PACK] = {.handler = emulate_rd12rn16rm0_rwflags_nopc}, + [PROBES_EXTEND] = {.handler = emulate_rd12rm0_noflags_nopc}, + [PROBES_EXTEND_ADD] = {.handler = emulate_rd12rn16rm0_rwflags_nopc}, + [PROBES_MUL_ADD_LONG] = { + .handler = emulate_rdlo12rdhi16rn0rm8_rwflags_nopc}, + [PROBES_MUL_ADD] = {.handler = emulate_rd16rn12rm0rs8_rwflags_nopc}, + [PROBES_BITFIELD] = {.handler = emulate_rd12rm0_noflags_nopc}, + [PROBES_BRANCH] = {.handler = simulate_bbl}, + [PROBES_LDMSTM] = {.decoder = kprobe_decode_ldmstm} }; - -static const union decode_item arm_cccc_0001_____1001_table[] = { - /* Synchronization primitives */ - -#if __LINUX_ARM_ARCH__ < 6 - /* Deprecated on ARMv6 and may be UNDEFINED on v7 */ - /* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */ - DECODE_EMULATEX (0x0fb000f0, 0x01000090, emulate_rd12rn16rm0_rwflags_nopc, - REGS(NOPC, NOPC, 0, 0, NOPC)), -#endif - /* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */ - /* And unallocated instructions... */ - DECODE_END -}; - -static const union decode_item arm_cccc_000x_____1xx1_table[] = { - /* Extra load/store instructions */ - - /* STRHT cccc 0000 xx10 xxxx xxxx xxxx 1011 xxxx */ - /* ??? cccc 0000 xx10 xxxx xxxx xxxx 11x1 xxxx */ - /* LDRHT cccc 0000 xx11 xxxx xxxx xxxx 1011 xxxx */ - /* LDRSBT cccc 0000 xx11 xxxx xxxx xxxx 1101 xxxx */ - /* LDRSHT cccc 0000 xx11 xxxx xxxx xxxx 1111 xxxx */ - DECODE_REJECT (0x0f200090, 0x00200090), - - /* LDRD/STRD lr,pc,{... cccc 000x x0x0 xxxx 111x xxxx 1101 xxxx */ - DECODE_REJECT (0x0e10e0d0, 0x0000e0d0), - - /* LDRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx */ - /* STRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx */ - DECODE_EMULATEX (0x0e5000d0, 0x000000d0, emulate_ldrdstrd, - REGS(NOPCWB, NOPCX, 0, 0, NOPC)), - - /* LDRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx */ - /* STRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx */ - DECODE_EMULATEX (0x0e5000d0, 0x004000d0, emulate_ldrdstrd, - REGS(NOPCWB, NOPCX, 0, 0, 0)), - - /* STRH (register) cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx */ - DECODE_EMULATEX (0x0e5000f0, 0x000000b0, emulate_str, - REGS(NOPCWB, NOPC, 0, 0, NOPC)), - - /* LDRH (register) cccc 000x x0x1 xxxx xxxx xxxx 1011 xxxx */ - /* LDRSB (register) cccc 000x x0x1 xxxx xxxx xxxx 1101 xxxx */ - /* LDRSH (register) cccc 000x x0x1 xxxx xxxx xxxx 1111 xxxx */ - DECODE_EMULATEX (0x0e500090, 0x00100090, emulate_ldr, - REGS(NOPCWB, NOPC, 0, 0, NOPC)), - - /* STRH (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1011 xxxx */ - DECODE_EMULATEX (0x0e5000f0, 0x004000b0, emulate_str, - REGS(NOPCWB, NOPC, 0, 0, 0)), - - /* LDRH (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1011 xxxx */ - /* LDRSB (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1101 xxxx */ - /* LDRSH (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1111 xxxx */ - DECODE_EMULATEX (0x0e500090, 0x00500090, emulate_ldr, - REGS(NOPCWB, NOPC, 0, 0, 0)), - - DECODE_END -}; - -static const union decode_item arm_cccc_000x_table[] = { - /* Data-processing (register) */ - - /* S PC, ... cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */ - DECODE_REJECT (0x0e10f000, 0x0010f000), - - /* MOV IP, SP 1110 0001 1010 0000 1100 0000 0000 1101 */ - DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, simulate_mov_ipsp), - - /* TST (register) cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */ - /* TEQ (register) cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */ - /* CMP (register) cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */ - /* CMN (register) cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */ - DECODE_EMULATEX (0x0f900010, 0x01100000, emulate_rd12rn16rm0rs8_rwflags, - REGS(ANY, 0, 0, 0, ANY)), - - /* MOV (register) cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */ - /* MVN (register) cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */ - DECODE_EMULATEX (0x0fa00010, 0x01a00000, emulate_rd12rn16rm0rs8_rwflags, - REGS(0, ANY, 0, 0, ANY)), - - /* AND (register) cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */ - /* EOR (register) cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */ - /* SUB (register) cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */ - /* RSB (register) cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */ - /* ADD (register) cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */ - /* ADC (register) cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */ - /* SBC (register) cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */ - /* RSC (register) cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */ - /* ORR (register) cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */ - /* BIC (register) cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */ - DECODE_EMULATEX (0x0e000010, 0x00000000, emulate_rd12rn16rm0rs8_rwflags, - REGS(ANY, ANY, 0, 0, ANY)), - - /* TST (reg-shift reg) cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */ - /* TEQ (reg-shift reg) cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */ - /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */ - /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */ - DECODE_EMULATEX (0x0f900090, 0x01100010, emulate_rd12rn16rm0rs8_rwflags, - REGS(ANY, 0, NOPC, 0, ANY)), - - /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */ - /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */ - DECODE_EMULATEX (0x0fa00090, 0x01a00010, emulate_rd12rn16rm0rs8_rwflags, - REGS(0, ANY, NOPC, 0, ANY)), - - /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */ - /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */ - /* SUB (reg-shift reg) cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */ - /* RSB (reg-shift reg) cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */ - /* ADD (reg-shift reg) cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */ - /* ADC (reg-shift reg) cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */ - /* SBC (reg-shift reg) cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */ - /* RSC (reg-shift reg) cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */ - /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */ - /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */ - DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags, - REGS(ANY, ANY, NOPC, 0, ANY)), - - DECODE_END -}; - -static const union decode_item arm_cccc_001x_table[] = { - /* Data-processing (immediate) */ - - /* MOVW cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */ - /* MOVT cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0fb00000, 0x03000000, emulate_rd12rm0_noflags_nopc, - REGS(0, NOPC, 0, 0, 0)), - - /* YIELD cccc 0011 0010 0000 xxxx xxxx 0000 0001 */ - DECODE_OR (0x0fff00ff, 0x03200001), - /* SEV cccc 0011 0010 0000 xxxx xxxx 0000 0100 */ - DECODE_EMULATE (0x0fff00ff, 0x03200004, kprobe_emulate_none), - /* NOP cccc 0011 0010 0000 xxxx xxxx 0000 0000 */ - /* WFE cccc 0011 0010 0000 xxxx xxxx 0000 0010 */ - /* WFI cccc 0011 0010 0000 xxxx xxxx 0000 0011 */ - DECODE_SIMULATE (0x0fff00fc, 0x03200000, kprobe_simulate_nop), - /* DBG cccc 0011 0010 0000 xxxx xxxx ffff xxxx */ - /* unallocated hints cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */ - /* MSR (immediate) cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0x0fb00000, 0x03200000), - - /* S PC, ... cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */ - DECODE_REJECT (0x0e10f000, 0x0210f000), - - /* TST (immediate) cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx */ - /* TEQ (immediate) cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx */ - /* CMP (immediate) cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx */ - /* CMN (immediate) cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0f900000, 0x03100000, emulate_rd12rn16rm0rs8_rwflags, - REGS(ANY, 0, 0, 0, 0)), - - /* MOV (immediate) cccc 0011 101x xxxx xxxx xxxx xxxx xxxx */ - /* MVN (immediate) cccc 0011 111x xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0fa00000, 0x03a00000, emulate_rd12rn16rm0rs8_rwflags, - REGS(0, ANY, 0, 0, 0)), - - /* AND (immediate) cccc 0010 000x xxxx xxxx xxxx xxxx xxxx */ - /* EOR (immediate) cccc 0010 001x xxxx xxxx xxxx xxxx xxxx */ - /* SUB (immediate) cccc 0010 010x xxxx xxxx xxxx xxxx xxxx */ - /* RSB (immediate) cccc 0010 011x xxxx xxxx xxxx xxxx xxxx */ - /* ADD (immediate) cccc 0010 100x xxxx xxxx xxxx xxxx xxxx */ - /* ADC (immediate) cccc 0010 101x xxxx xxxx xxxx xxxx xxxx */ - /* SBC (immediate) cccc 0010 110x xxxx xxxx xxxx xxxx xxxx */ - /* RSC (immediate) cccc 0010 111x xxxx xxxx xxxx xxxx xxxx */ - /* ORR (immediate) cccc 0011 100x xxxx xxxx xxxx xxxx xxxx */ - /* BIC (immediate) cccc 0011 110x xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0e000000, 0x02000000, emulate_rd12rn16rm0rs8_rwflags, - REGS(ANY, ANY, 0, 0, 0)), - - DECODE_END -}; - -static const union decode_item arm_cccc_0110_____xxx1_table[] = { - /* Media instructions */ - - /* SEL cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx */ - DECODE_EMULATEX (0x0ff000f0, 0x068000b0, emulate_rd12rn16rm0_rwflags_nopc, - REGS(NOPC, NOPC, 0, 0, NOPC)), - - /* SSAT cccc 0110 101x xxxx xxxx xxxx xx01 xxxx */ - /* USAT cccc 0110 111x xxxx xxxx xxxx xx01 xxxx */ - DECODE_OR(0x0fa00030, 0x06a00010), - /* SSAT16 cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx */ - /* USAT16 cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx */ - DECODE_EMULATEX (0x0fb000f0, 0x06a00030, emulate_rd12rn16rm0_rwflags_nopc, - REGS(0, NOPC, 0, 0, NOPC)), - - /* REV cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */ - /* REV16 cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */ - /* RBIT cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */ - /* REVSH cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */ - DECODE_EMULATEX (0x0fb00070, 0x06b00030, emulate_rd12rm0_noflags_nopc, - REGS(0, NOPC, 0, 0, NOPC)), - - /* ??? cccc 0110 0x00 xxxx xxxx xxxx xxx1 xxxx */ - DECODE_REJECT (0x0fb00010, 0x06000010), - /* ??? cccc 0110 0xxx xxxx xxxx xxxx 1011 xxxx */ - DECODE_REJECT (0x0f8000f0, 0x060000b0), - /* ??? cccc 0110 0xxx xxxx xxxx xxxx 1101 xxxx */ - DECODE_REJECT (0x0f8000f0, 0x060000d0), - /* SADD16 cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx */ - /* SADDSUBX cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx */ - /* SSUBADDX cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx */ - /* SSUB16 cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx */ - /* SADD8 cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx */ - /* SSUB8 cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx */ - /* QADD16 cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx */ - /* QADDSUBX cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx */ - /* QSUBADDX cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx */ - /* QSUB16 cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx */ - /* QADD8 cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx */ - /* QSUB8 cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx */ - /* SHADD16 cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx */ - /* SHADDSUBX cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx */ - /* SHSUBADDX cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx */ - /* SHSUB16 cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx */ - /* SHADD8 cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx */ - /* SHSUB8 cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx */ - /* UADD16 cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx */ - /* UADDSUBX cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx */ - /* USUBADDX cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx */ - /* USUB16 cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx */ - /* UADD8 cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx */ - /* USUB8 cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx */ - /* UQADD16 cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx */ - /* UQADDSUBX cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx */ - /* UQSUBADDX cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx */ - /* UQSUB16 cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx */ - /* UQADD8 cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx */ - /* UQSUB8 cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx */ - /* UHADD16 cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx */ - /* UHADDSUBX cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx */ - /* UHSUBADDX cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx */ - /* UHSUB16 cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx */ - /* UHADD8 cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx */ - /* UHSUB8 cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx */ - DECODE_EMULATEX (0x0f800010, 0x06000010, emulate_rd12rn16rm0_rwflags_nopc, - REGS(NOPC, NOPC, 0, 0, NOPC)), - - /* PKHBT cccc 0110 1000 xxxx xxxx xxxx x001 xxxx */ - /* PKHTB cccc 0110 1000 xxxx xxxx xxxx x101 xxxx */ - DECODE_EMULATEX (0x0ff00030, 0x06800010, emulate_rd12rn16rm0_rwflags_nopc, - REGS(NOPC, NOPC, 0, 0, NOPC)), - - /* ??? cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx */ - /* ??? cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx */ - DECODE_REJECT (0x0fb000f0, 0x06900070), - - /* SXTB16 cccc 0110 1000 1111 xxxx xxxx 0111 xxxx */ - /* SXTB cccc 0110 1010 1111 xxxx xxxx 0111 xxxx */ - /* SXTH cccc 0110 1011 1111 xxxx xxxx 0111 xxxx */ - /* UXTB16 cccc 0110 1100 1111 xxxx xxxx 0111 xxxx */ - /* UXTB cccc 0110 1110 1111 xxxx xxxx 0111 xxxx */ - /* UXTH cccc 0110 1111 1111 xxxx xxxx 0111 xxxx */ - DECODE_EMULATEX (0x0f8f00f0, 0x068f0070, emulate_rd12rm0_noflags_nopc, - REGS(0, NOPC, 0, 0, NOPC)), - - /* SXTAB16 cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx */ - /* SXTAB cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx */ - /* SXTAH cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx */ - /* UXTAB16 cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx */ - /* UXTAB cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx */ - /* UXTAH cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx */ - DECODE_EMULATEX (0x0f8000f0, 0x06800070, emulate_rd12rn16rm0_rwflags_nopc, - REGS(NOPCX, NOPC, 0, 0, NOPC)), - - DECODE_END -}; - -static const union decode_item arm_cccc_0111_____xxx1_table[] = { - /* Media instructions */ - - /* UNDEFINED cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */ - DECODE_REJECT (0x0ff000f0, 0x07f000f0), - - /* SMLALD cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */ - /* SMLSLD cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */ - DECODE_EMULATEX (0x0ff00090, 0x07400010, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc, - REGS(NOPC, NOPC, NOPC, 0, NOPC)), - - /* SMUAD cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */ - /* SMUSD cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */ - DECODE_OR (0x0ff0f090, 0x0700f010), - /* SMMUL cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx */ - DECODE_OR (0x0ff0f0d0, 0x0750f010), - /* USAD8 cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */ - DECODE_EMULATEX (0x0ff0f0f0, 0x0780f010, emulate_rd16rn12rm0rs8_rwflags_nopc, - REGS(NOPC, 0, NOPC, 0, NOPC)), - - /* SMLAD cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx */ - /* SMLSD cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx */ - DECODE_OR (0x0ff00090, 0x07000010), - /* SMMLA cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx */ - DECODE_OR (0x0ff000d0, 0x07500010), - /* USADA8 cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */ - DECODE_EMULATEX (0x0ff000f0, 0x07800010, emulate_rd16rn12rm0rs8_rwflags_nopc, - REGS(NOPC, NOPCX, NOPC, 0, NOPC)), - - /* SMMLS cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx */ - DECODE_EMULATEX (0x0ff000d0, 0x075000d0, emulate_rd16rn12rm0rs8_rwflags_nopc, - REGS(NOPC, NOPC, NOPC, 0, NOPC)), - - /* SBFX cccc 0111 101x xxxx xxxx xxxx x101 xxxx */ - /* UBFX cccc 0111 111x xxxx xxxx xxxx x101 xxxx */ - DECODE_EMULATEX (0x0fa00070, 0x07a00050, emulate_rd12rm0_noflags_nopc, - REGS(0, NOPC, 0, 0, NOPC)), - - /* BFC cccc 0111 110x xxxx xxxx xxxx x001 1111 */ - DECODE_EMULATEX (0x0fe0007f, 0x07c0001f, emulate_rd12rm0_noflags_nopc, - REGS(0, NOPC, 0, 0, 0)), - - /* BFI cccc 0111 110x xxxx xxxx xxxx x001 xxxx */ - DECODE_EMULATEX (0x0fe00070, 0x07c00010, emulate_rd12rm0_noflags_nopc, - REGS(0, NOPC, 0, 0, NOPCX)), - - DECODE_END -}; - -static const union decode_item arm_cccc_01xx_table[] = { - /* Load/store word and unsigned byte */ - - /* LDRB/STRB pc,[...] cccc 01xx x0xx xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0x0c40f000, 0x0440f000), - - /* STRT cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */ - /* LDRT cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */ - /* STRBT cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */ - /* LDRBT cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0x0d200000, 0x04200000), - - /* STR (immediate) cccc 010x x0x0 xxxx xxxx xxxx xxxx xxxx */ - /* STRB (immediate) cccc 010x x1x0 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0e100000, 0x04000000, emulate_str, - REGS(NOPCWB, ANY, 0, 0, 0)), - - /* LDR (immediate) cccc 010x x0x1 xxxx xxxx xxxx xxxx xxxx */ - /* LDRB (immediate) cccc 010x x1x1 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0e100000, 0x04100000, emulate_ldr, - REGS(NOPCWB, ANY, 0, 0, 0)), - - /* STR (register) cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx */ - /* STRB (register) cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0e100000, 0x06000000, emulate_str, - REGS(NOPCWB, ANY, 0, 0, NOPC)), - - /* LDR (register) cccc 011x x0x1 xxxx xxxx xxxx xxxx xxxx */ - /* LDRB (register) cccc 011x x1x1 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0x0e100000, 0x06100000, emulate_ldr, - REGS(NOPCWB, ANY, 0, 0, NOPC)), - - DECODE_END -}; - -static const union decode_item arm_cccc_100x_table[] = { - /* Block data transfer instructions */ - - /* LDM cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ - /* STM cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */ - DECODE_CUSTOM (0x0e400000, 0x08000000, kprobe_decode_ldmstm), - - /* STM (user registers) cccc 100x x1x0 xxxx xxxx xxxx xxxx xxxx */ - /* LDM (user registers) cccc 100x x1x1 xxxx 0xxx xxxx xxxx xxxx */ - /* LDM (exception ret) cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */ - DECODE_END -}; - -const union decode_item kprobe_decode_arm_table[] = { - /* - * Unconditional instructions - * 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xf0000000, 0xf0000000, arm_1111_table), - - /* - * Miscellaneous instructions - * cccc 0001 0xx0 xxxx xxxx xxxx 0xxx xxxx - */ - DECODE_TABLE (0x0f900080, 0x01000000, arm_cccc_0001_0xx0____0xxx_table), - - /* - * Halfword multiply and multiply-accumulate - * cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx - */ - DECODE_TABLE (0x0f900090, 0x01000080, arm_cccc_0001_0xx0____1xx0_table), - - /* - * Multiply and multiply-accumulate - * cccc 0000 xxxx xxxx xxxx xxxx 1001 xxxx - */ - DECODE_TABLE (0x0f0000f0, 0x00000090, arm_cccc_0000_____1001_table), - - /* - * Synchronization primitives - * cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx - */ - DECODE_TABLE (0x0f0000f0, 0x01000090, arm_cccc_0001_____1001_table), - - /* - * Extra load/store instructions - * cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx - */ - DECODE_TABLE (0x0e000090, 0x00000090, arm_cccc_000x_____1xx1_table), - - /* - * Data-processing (register) - * cccc 000x xxxx xxxx xxxx xxxx xxx0 xxxx - * Data-processing (register-shifted register) - * cccc 000x xxxx xxxx xxxx xxxx 0xx1 xxxx - */ - DECODE_TABLE (0x0e000000, 0x00000000, arm_cccc_000x_table), - - /* - * Data-processing (immediate) - * cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0x0e000000, 0x02000000, arm_cccc_001x_table), - - /* - * Media instructions - * cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx - */ - DECODE_TABLE (0x0f000010, 0x06000010, arm_cccc_0110_____xxx1_table), - DECODE_TABLE (0x0f000010, 0x07000010, arm_cccc_0111_____xxx1_table), - - /* - * Load/store word and unsigned byte - * cccc 01xx xxxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0x0c000000, 0x04000000, arm_cccc_01xx_table), - - /* - * Block data transfer instructions - * cccc 100x xxxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0x0e000000, 0x08000000, arm_cccc_100x_table), - - /* B cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */ - /* BL cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */ - DECODE_SIMULATE (0x0e000000, 0x0a000000, simulate_bbl), - - /* - * Supervisor Call, and coprocessor instructions - */ - - /* MCRR cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx */ - /* MRRC cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx */ - /* LDC cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ - /* STC cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ - /* CDP cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ - /* MCR cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ - /* MRC cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - /* SVC cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0x0c000000, 0x0c000000), - - DECODE_END -}; -#ifdef CONFIG_ARM_KPROBES_TEST_MODULE -EXPORT_SYMBOL_GPL(kprobe_decode_arm_table); -#endif - -static void __kprobes arm_singlestep(struct kprobe *p, struct pt_regs *regs) -{ - regs->ARM_pc += 4; - p->ainsn.insn_handler(p, regs); -} - -/* Return: - * INSN_REJECTED If instruction is one not allowed to kprobe, - * INSN_GOOD If instruction is supported and uses instruction slot, - * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot. - * - * For instructions we don't want to kprobe (INSN_REJECTED return result): - * These are generally ones that modify the processor state making - * them "hard" to simulate such as switches processor modes or - * make accesses in alternate modes. Any of these could be simulated - * if the work was put into it, but low return considering they - * should also be very rare. - */ -enum kprobe_insn __kprobes -arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi) -{ - asi->insn_singlestep = arm_singlestep; - asi->insn_check_cc = kprobe_condition_checks[insn>>28]; - return kprobe_decode_insn(insn, asi, kprobe_decode_arm_table, false); -} diff -Nur linux-3.14.1/arch/arm/kernel/kprobes.c linux-3.15-rc1.orig/arch/arm/kernel/kprobes.c --- linux-3.14.1/arch/arm/kernel/kprobes.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes.c 2014-04-13 23:18:35.000000000 +0200 @@ -26,9 +26,14 @@ #include #include #include +#include #include +#include +#include #include "kprobes.h" +#include "probes-arm.h" +#include "probes-thumb.h" #include "patch.h" #define MIN_STACK_SIZE(addr) \ @@ -54,6 +59,7 @@ unsigned long addr = (unsigned long)p->addr; bool thumb; kprobe_decode_insn_t *decode_insn; + const union decode_action *actions; int is; if (in_exception_text(addr)) @@ -62,25 +68,29 @@ #ifdef CONFIG_THUMB2_KERNEL thumb = true; addr &= ~1; /* Bit 0 would normally be set to indicate Thumb code */ - insn = ((u16 *)addr)[0]; + insn = __mem_to_opcode_thumb16(((u16 *)addr)[0]); if (is_wide_instruction(insn)) { - insn <<= 16; - insn |= ((u16 *)addr)[1]; - decode_insn = thumb32_kprobe_decode_insn; - } else - decode_insn = thumb16_kprobe_decode_insn; + u16 inst2 = __mem_to_opcode_thumb16(((u16 *)addr)[1]); + insn = __opcode_thumb32_compose(insn, inst2); + decode_insn = thumb32_probes_decode_insn; + actions = kprobes_t32_actions; + } else { + decode_insn = thumb16_probes_decode_insn; + actions = kprobes_t16_actions; + } #else /* !CONFIG_THUMB2_KERNEL */ thumb = false; if (addr & 0x3) return -EINVAL; - insn = *p->addr; - decode_insn = arm_kprobe_decode_insn; + insn = __mem_to_opcode_arm(*p->addr); + decode_insn = arm_probes_decode_insn; + actions = kprobes_arm_actions; #endif p->opcode = insn; p->ainsn.insn = tmp_insn; - switch ((*decode_insn)(insn, &p->ainsn)) { + switch ((*decode_insn)(insn, &p->ainsn, true, actions)) { case INSN_REJECTED: /* not supported */ return -EINVAL; @@ -92,7 +102,7 @@ p->ainsn.insn[is] = tmp_insn[is]; flush_insns(p->ainsn.insn, sizeof(p->ainsn.insn[0]) * MAX_INSN_SIZE); - p->ainsn.insn_fn = (kprobe_insn_fn_t *) + p->ainsn.insn_fn = (probes_insn_fn_t *) ((uintptr_t)p->ainsn.insn | thumb); break; @@ -197,7 +207,7 @@ static inline void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) { - p->ainsn.insn_singlestep(p, regs); + p->ainsn.insn_singlestep(p->opcode, &p->ainsn, regs); } /* @@ -607,7 +617,7 @@ int __init arch_init_kprobes() { - arm_kprobe_decode_init(); + arm_probes_decode_init(); #ifdef CONFIG_THUMB2_KERNEL register_undef_hook(&kprobes_thumb16_break_hook); register_undef_hook(&kprobes_thumb32_break_hook); diff -Nur linux-3.14.1/arch/arm/kernel/kprobes-common.c linux-3.15-rc1.orig/arch/arm/kernel/kprobes-common.c --- linux-3.14.1/arch/arm/kernel/kprobes-common.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes-common.c 2014-04-13 23:18:35.000000000 +0200 @@ -13,178 +13,15 @@ #include #include -#include +#include #include "kprobes.h" -#ifndef find_str_pc_offset - -/* - * For STR and STM instructions, an ARM core may choose to use either - * a +8 or a +12 displacement from the current instruction's address. - * Whichever value is chosen for a given core, it must be the same for - * both instructions and may not change. This function measures it. - */ - -int str_pc_offset; - -void __init find_str_pc_offset(void) -{ - int addr, scratch, ret; - - __asm__ ( - "sub %[ret], pc, #4 \n\t" - "str pc, %[addr] \n\t" - "ldr %[scr], %[addr] \n\t" - "sub %[ret], %[scr], %[ret] \n\t" - : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr)); - - str_pc_offset = ret; -} - -#endif /* !find_str_pc_offset */ - - -#ifndef test_load_write_pc_interworking - -bool load_write_pc_interworks; - -void __init test_load_write_pc_interworking(void) -{ - int arch = cpu_architecture(); - BUG_ON(arch == CPU_ARCH_UNKNOWN); - load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T; -} - -#endif /* !test_load_write_pc_interworking */ - - -#ifndef test_alu_write_pc_interworking - -bool alu_write_pc_interworks; - -void __init test_alu_write_pc_interworking(void) -{ - int arch = cpu_architecture(); - BUG_ON(arch == CPU_ARCH_UNKNOWN); - alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7; -} - -#endif /* !test_alu_write_pc_interworking */ - - -void __init arm_kprobe_decode_init(void) -{ - find_str_pc_offset(); - test_load_write_pc_interworking(); - test_alu_write_pc_interworking(); -} - - -static unsigned long __kprobes __check_eq(unsigned long cpsr) -{ - return cpsr & PSR_Z_BIT; -} - -static unsigned long __kprobes __check_ne(unsigned long cpsr) -{ - return (~cpsr) & PSR_Z_BIT; -} - -static unsigned long __kprobes __check_cs(unsigned long cpsr) -{ - return cpsr & PSR_C_BIT; -} - -static unsigned long __kprobes __check_cc(unsigned long cpsr) -{ - return (~cpsr) & PSR_C_BIT; -} - -static unsigned long __kprobes __check_mi(unsigned long cpsr) -{ - return cpsr & PSR_N_BIT; -} - -static unsigned long __kprobes __check_pl(unsigned long cpsr) -{ - return (~cpsr) & PSR_N_BIT; -} - -static unsigned long __kprobes __check_vs(unsigned long cpsr) -{ - return cpsr & PSR_V_BIT; -} - -static unsigned long __kprobes __check_vc(unsigned long cpsr) -{ - return (~cpsr) & PSR_V_BIT; -} - -static unsigned long __kprobes __check_hi(unsigned long cpsr) -{ - cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ - return cpsr & PSR_C_BIT; -} - -static unsigned long __kprobes __check_ls(unsigned long cpsr) -{ - cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ - return (~cpsr) & PSR_C_BIT; -} - -static unsigned long __kprobes __check_ge(unsigned long cpsr) -{ - cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ - return (~cpsr) & PSR_N_BIT; -} - -static unsigned long __kprobes __check_lt(unsigned long cpsr) -{ - cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ - return cpsr & PSR_N_BIT; -} - -static unsigned long __kprobes __check_gt(unsigned long cpsr) -{ - unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ - temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ - return (~temp) & PSR_N_BIT; -} - -static unsigned long __kprobes __check_le(unsigned long cpsr) -{ - unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ - temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ - return temp & PSR_N_BIT; -} - -static unsigned long __kprobes __check_al(unsigned long cpsr) -{ - return true; -} - -kprobe_check_cc * const kprobe_condition_checks[16] = { - &__check_eq, &__check_ne, &__check_cs, &__check_cc, - &__check_mi, &__check_pl, &__check_vs, &__check_vc, - &__check_hi, &__check_ls, &__check_ge, &__check_lt, - &__check_gt, &__check_le, &__check_al, &__check_al -}; - - -void __kprobes kprobe_simulate_nop(struct kprobe *p, struct pt_regs *regs) -{ -} - -void __kprobes kprobe_emulate_none(struct kprobe *p, struct pt_regs *regs) -{ - p->ainsn.insn_fn(); -} - -static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs) +static void __kprobes simulate_ldm1stm1(probes_opcode_t insn, + struct arch_probes_insn *asi, + struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rn = (insn >> 16) & 0xf; int lbit = insn & (1 << 20); int wbit = insn & (1 << 21); @@ -223,24 +60,31 @@ } } -static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs) +static void __kprobes simulate_stm1_pc(probes_opcode_t insn, + struct arch_probes_insn *asi, + struct pt_regs *regs) { - regs->ARM_pc = (long)p->addr + str_pc_offset; - simulate_ldm1stm1(p, regs); - regs->ARM_pc = (long)p->addr + 4; + unsigned long addr = regs->ARM_pc - 4; + + regs->ARM_pc = (long)addr + str_pc_offset; + simulate_ldm1stm1(insn, asi, regs); + regs->ARM_pc = (long)addr + 4; } -static void __kprobes simulate_ldm1_pc(struct kprobe *p, struct pt_regs *regs) +static void __kprobes simulate_ldm1_pc(probes_opcode_t insn, + struct arch_probes_insn *asi, + struct pt_regs *regs) { - simulate_ldm1stm1(p, regs); + simulate_ldm1stm1(insn, asi, regs); load_write_pc(regs->ARM_pc, regs); } static void __kprobes -emulate_generic_r0_12_noflags(struct kprobe *p, struct pt_regs *regs) +emulate_generic_r0_12_noflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { register void *rregs asm("r1") = regs; - register void *rfn asm("lr") = p->ainsn.insn_fn; + register void *rfn asm("lr") = asi->insn_fn; __asm__ __volatile__ ( "stmdb sp!, {%[regs], r11} \n\t" @@ -264,22 +108,27 @@ } static void __kprobes -emulate_generic_r2_14_noflags(struct kprobe *p, struct pt_regs *regs) +emulate_generic_r2_14_noflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - emulate_generic_r0_12_noflags(p, (struct pt_regs *)(regs->uregs+2)); + emulate_generic_r0_12_noflags(insn, asi, + (struct pt_regs *)(regs->uregs+2)); } static void __kprobes -emulate_ldm_r3_15(struct kprobe *p, struct pt_regs *regs) +emulate_ldm_r3_15(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - emulate_generic_r0_12_noflags(p, (struct pt_regs *)(regs->uregs+3)); + emulate_generic_r0_12_noflags(insn, asi, + (struct pt_regs *)(regs->uregs+3)); load_write_pc(regs->ARM_pc, regs); } -enum kprobe_insn __kprobes -kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi) +enum probes_insn __kprobes +kprobe_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *h) { - kprobe_insn_handler_t *handler = 0; + probes_insn_handler_t *handler = 0; unsigned reglist = insn & 0xffff; int is_ldm = insn & 0x100000; int rn = (insn >> 16) & 0xf; @@ -305,7 +154,8 @@ if (handler) { /* We can emulate the instruction in (possibly) modified form */ - asi->insn[0] = (insn & 0xfff00000) | (rn << 16) | reglist; + asi->insn[0] = __opcode_to_mem_arm((insn & 0xfff00000) | + (rn << 16) | reglist); asi->insn_handler = handler; return INSN_GOOD; } @@ -319,260 +169,3 @@ return INSN_GOOD_NO_SLOT; } - -/* - * Prepare an instruction slot to receive an instruction for emulating. - * This is done by placing a subroutine return after the location where the - * instruction will be placed. We also modify ARM instructions to be - * unconditional as the condition code will already be checked before any - * emulation handler is called. - */ -static kprobe_opcode_t __kprobes -prepare_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi, - bool thumb) -{ -#ifdef CONFIG_THUMB2_KERNEL - if (thumb) { - u16 *thumb_insn = (u16 *)asi->insn; - thumb_insn[1] = 0x4770; /* Thumb bx lr */ - thumb_insn[2] = 0x4770; /* Thumb bx lr */ - return insn; - } - asi->insn[1] = 0xe12fff1e; /* ARM bx lr */ -#else - asi->insn[1] = 0xe1a0f00e; /* mov pc, lr */ -#endif - /* Make an ARM instruction unconditional */ - if (insn < 0xe0000000) - insn = (insn | 0xe0000000) & ~0x10000000; - return insn; -} - -/* - * Write a (probably modified) instruction into the slot previously prepared by - * prepare_emulated_insn - */ -static void __kprobes -set_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi, - bool thumb) -{ -#ifdef CONFIG_THUMB2_KERNEL - if (thumb) { - u16 *ip = (u16 *)asi->insn; - if (is_wide_instruction(insn)) - *ip++ = insn >> 16; - *ip++ = insn; - return; - } -#endif - asi->insn[0] = insn; -} - -/* - * When we modify the register numbers encoded in an instruction to be emulated, - * the new values come from this define. For ARM and 32-bit Thumb instructions - * this gives... - * - * bit position 16 12 8 4 0 - * ---------------+---+---+---+---+---+ - * register r2 r0 r1 -- r3 - */ -#define INSN_NEW_BITS 0x00020103 - -/* Each nibble has same value as that at INSN_NEW_BITS bit 16 */ -#define INSN_SAMEAS16_BITS 0x22222222 - -/* - * Validate and modify each of the registers encoded in an instruction. - * - * Each nibble in regs contains a value from enum decode_reg_type. For each - * non-zero value, the corresponding nibble in pinsn is validated and modified - * according to the type. - */ -static bool __kprobes decode_regs(kprobe_opcode_t* pinsn, u32 regs) -{ - kprobe_opcode_t insn = *pinsn; - kprobe_opcode_t mask = 0xf; /* Start at least significant nibble */ - - for (; regs != 0; regs >>= 4, mask <<= 4) { - - kprobe_opcode_t new_bits = INSN_NEW_BITS; - - switch (regs & 0xf) { - - case REG_TYPE_NONE: - /* Nibble not a register, skip to next */ - continue; - - case REG_TYPE_ANY: - /* Any register is allowed */ - break; - - case REG_TYPE_SAMEAS16: - /* Replace register with same as at bit position 16 */ - new_bits = INSN_SAMEAS16_BITS; - break; - - case REG_TYPE_SP: - /* Only allow SP (R13) */ - if ((insn ^ 0xdddddddd) & mask) - goto reject; - break; - - case REG_TYPE_PC: - /* Only allow PC (R15) */ - if ((insn ^ 0xffffffff) & mask) - goto reject; - break; - - case REG_TYPE_NOSP: - /* Reject SP (R13) */ - if (((insn ^ 0xdddddddd) & mask) == 0) - goto reject; - break; - - case REG_TYPE_NOSPPC: - case REG_TYPE_NOSPPCX: - /* Reject SP and PC (R13 and R15) */ - if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0) - goto reject; - break; - - case REG_TYPE_NOPCWB: - if (!is_writeback(insn)) - break; /* No writeback, so any register is OK */ - /* fall through... */ - case REG_TYPE_NOPC: - case REG_TYPE_NOPCX: - /* Reject PC (R15) */ - if (((insn ^ 0xffffffff) & mask) == 0) - goto reject; - break; - } - - /* Replace value of nibble with new register number... */ - insn &= ~mask; - insn |= new_bits & mask; - } - - *pinsn = insn; - return true; - -reject: - return false; -} - -static const int decode_struct_sizes[NUM_DECODE_TYPES] = { - [DECODE_TYPE_TABLE] = sizeof(struct decode_table), - [DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom), - [DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate), - [DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate), - [DECODE_TYPE_OR] = sizeof(struct decode_or), - [DECODE_TYPE_REJECT] = sizeof(struct decode_reject) -}; - -/* - * kprobe_decode_insn operates on data tables in order to decode an ARM - * architecture instruction onto which a kprobe has been placed. - * - * These instruction decoding tables are a concatenation of entries each - * of which consist of one of the following structs: - * - * decode_table - * decode_custom - * decode_simulate - * decode_emulate - * decode_or - * decode_reject - * - * Each of these starts with a struct decode_header which has the following - * fields: - * - * type_regs - * mask - * value - * - * The least significant DECODE_TYPE_BITS of type_regs contains a value - * from enum decode_type, this indicates which of the decode_* structs - * the entry contains. The value DECODE_TYPE_END indicates the end of the - * table. - * - * When the table is parsed, each entry is checked in turn to see if it - * matches the instruction to be decoded using the test: - * - * (insn & mask) == value - * - * If no match is found before the end of the table is reached then decoding - * fails with INSN_REJECTED. - * - * When a match is found, decode_regs() is called to validate and modify each - * of the registers encoded in the instruction; the data it uses to do this - * is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding - * to fail with INSN_REJECTED. - * - * Once the instruction has passed the above tests, further processing - * depends on the type of the table entry's decode struct. - * - */ -int __kprobes -kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi, - const union decode_item *table, bool thumb) -{ - const struct decode_header *h = (struct decode_header *)table; - const struct decode_header *next; - bool matched = false; - - insn = prepare_emulated_insn(insn, asi, thumb); - - for (;; h = next) { - enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK; - u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS; - - if (type == DECODE_TYPE_END) - return INSN_REJECTED; - - next = (struct decode_header *) - ((uintptr_t)h + decode_struct_sizes[type]); - - if (!matched && (insn & h->mask.bits) != h->value.bits) - continue; - - if (!decode_regs(&insn, regs)) - return INSN_REJECTED; - - switch (type) { - - case DECODE_TYPE_TABLE: { - struct decode_table *d = (struct decode_table *)h; - next = (struct decode_header *)d->table.table; - break; - } - - case DECODE_TYPE_CUSTOM: { - struct decode_custom *d = (struct decode_custom *)h; - return (*d->decoder.decoder)(insn, asi); - } - - case DECODE_TYPE_SIMULATE: { - struct decode_simulate *d = (struct decode_simulate *)h; - asi->insn_handler = d->handler.handler; - return INSN_GOOD_NO_SLOT; - } - - case DECODE_TYPE_EMULATE: { - struct decode_emulate *d = (struct decode_emulate *)h; - asi->insn_handler = d->handler.handler; - set_emulated_insn(insn, asi, thumb); - return INSN_GOOD; - } - - case DECODE_TYPE_OR: - matched = true; - break; - - case DECODE_TYPE_REJECT: - default: - return INSN_REJECTED; - } - } - } diff -Nur linux-3.14.1/arch/arm/kernel/kprobes.h linux-3.15-rc1.orig/arch/arm/kernel/kprobes.h --- linux-3.14.1/arch/arm/kernel/kprobes.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes.h 2014-04-13 23:18:35.000000000 +0200 @@ -19,6 +19,8 @@ #ifndef _ARM_KERNEL_KPROBES_H #define _ARM_KERNEL_KPROBES_H +#include "probes.h" + /* * These undefined instructions must be unique and * reserved solely for kprobes' use. @@ -27,402 +29,24 @@ #define KPROBE_THUMB16_BREAKPOINT_INSTRUCTION 0xde18 #define KPROBE_THUMB32_BREAKPOINT_INSTRUCTION 0xf7f0a018 - -enum kprobe_insn { - INSN_REJECTED, - INSN_GOOD, - INSN_GOOD_NO_SLOT -}; - -typedef enum kprobe_insn (kprobe_decode_insn_t)(kprobe_opcode_t, - struct arch_specific_insn *); +enum probes_insn __kprobes +kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *h); + +typedef enum probes_insn (kprobe_decode_insn_t)(probes_opcode_t, + struct arch_probes_insn *, + bool, + const union decode_action *); #ifdef CONFIG_THUMB2_KERNEL -enum kprobe_insn thumb16_kprobe_decode_insn(kprobe_opcode_t, - struct arch_specific_insn *); -enum kprobe_insn thumb32_kprobe_decode_insn(kprobe_opcode_t, - struct arch_specific_insn *); +extern const union decode_action kprobes_t32_actions[]; +extern const union decode_action kprobes_t16_actions[]; #else /* !CONFIG_THUMB2_KERNEL */ -enum kprobe_insn arm_kprobe_decode_insn(kprobe_opcode_t, - struct arch_specific_insn *); -#endif - -void __init arm_kprobe_decode_init(void); - -extern kprobe_check_cc * const kprobe_condition_checks[16]; - - -#if __LINUX_ARM_ARCH__ >= 7 - -/* str_pc_offset is architecturally defined from ARMv7 onwards */ -#define str_pc_offset 8 -#define find_str_pc_offset() - -#else /* __LINUX_ARM_ARCH__ < 7 */ - -/* We need a run-time check to determine str_pc_offset */ -extern int str_pc_offset; -void __init find_str_pc_offset(void); +extern const union decode_action kprobes_arm_actions[]; #endif - -/* - * Update ITSTATE after normal execution of an IT block instruction. - * - * The 8 IT state bits are split into two parts in CPSR: - * ITSTATE<1:0> are in CPSR<26:25> - * ITSTATE<7:2> are in CPSR<15:10> - */ -static inline unsigned long it_advance(unsigned long cpsr) - { - if ((cpsr & 0x06000400) == 0) { - /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */ - cpsr &= ~PSR_IT_MASK; - } else { - /* We need to shift left ITSTATE<4:0> */ - const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */ - unsigned long it = cpsr & mask; - it <<= 1; - it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */ - it &= mask; - cpsr &= ~mask; - cpsr |= it; - } - return cpsr; -} - -static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs) -{ - long cpsr = regs->ARM_cpsr; - if (pcv & 0x1) { - cpsr |= PSR_T_BIT; - pcv &= ~0x1; - } else { - cpsr &= ~PSR_T_BIT; - pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */ - } - regs->ARM_cpsr = cpsr; - regs->ARM_pc = pcv; -} - - -#if __LINUX_ARM_ARCH__ >= 6 - -/* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */ -#define load_write_pc_interworks true -#define test_load_write_pc_interworking() - -#else /* __LINUX_ARM_ARCH__ < 6 */ - -/* We need run-time testing to determine if load_write_pc() should interwork. */ -extern bool load_write_pc_interworks; -void __init test_load_write_pc_interworking(void); - -#endif - -static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs) -{ - if (load_write_pc_interworks) - bx_write_pc(pcv, regs); - else - regs->ARM_pc = pcv; -} - - -#if __LINUX_ARM_ARCH__ >= 7 - -#define alu_write_pc_interworks true -#define test_alu_write_pc_interworking() - -#elif __LINUX_ARM_ARCH__ <= 5 - -/* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */ -#define alu_write_pc_interworks false -#define test_alu_write_pc_interworking() - -#else /* __LINUX_ARM_ARCH__ == 6 */ - -/* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */ -extern bool alu_write_pc_interworks; -void __init test_alu_write_pc_interworking(void); - -#endif /* __LINUX_ARM_ARCH__ == 6 */ - -static inline void __kprobes alu_write_pc(long pcv, struct pt_regs *regs) -{ - if (alu_write_pc_interworks) - bx_write_pc(pcv, regs); - else - regs->ARM_pc = pcv; -} - - -void __kprobes kprobe_simulate_nop(struct kprobe *p, struct pt_regs *regs); -void __kprobes kprobe_emulate_none(struct kprobe *p, struct pt_regs *regs); - -enum kprobe_insn __kprobes -kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi); - -/* - * Test if load/store instructions writeback the address register. - * if P (bit 24) == 0 or W (bit 21) == 1 - */ -#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000) - -/* - * The following definitions and macros are used to build instruction - * decoding tables for use by kprobe_decode_insn. - * - * These tables are a concatenation of entries each of which consist of one of - * the decode_* structs. All of the fields in every type of decode structure - * are of the union type decode_item, therefore the entire decode table can be - * viewed as an array of these and declared like: - * - * static const union decode_item table_name[] = {}; - * - * In order to construct each entry in the table, macros are used to - * initialise a number of sequential decode_item values in a layout which - * matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct - * decode_simulate by initialising four decode_item objects like this... - * - * {.bits = _type}, - * {.bits = _mask}, - * {.bits = _value}, - * {.handler = _handler}, - * - * Initialising a specified member of the union means that the compiler - * will produce a warning if the argument is of an incorrect type. - * - * Below is a list of each of the macros used to initialise entries and a - * description of the action performed when that entry is matched to an - * instruction. A match is found when (instruction & mask) == value. - * - * DECODE_TABLE(mask, value, table) - * Instruction decoding jumps to parsing the new sub-table 'table'. - * - * DECODE_CUSTOM(mask, value, decoder) - * The custom function 'decoder' is called to the complete decoding - * of an instruction. - * - * DECODE_SIMULATE(mask, value, handler) - * Set the probes instruction handler to 'handler', this will be used - * to simulate the instruction when the probe is hit. Decoding returns - * with INSN_GOOD_NO_SLOT. - * - * DECODE_EMULATE(mask, value, handler) - * Set the probes instruction handler to 'handler', this will be used - * to emulate the instruction when the probe is hit. The modified - * instruction (see below) is placed in the probes instruction slot so it - * may be called by the emulation code. Decoding returns with INSN_GOOD. - * - * DECODE_REJECT(mask, value) - * Instruction decoding fails with INSN_REJECTED - * - * DECODE_OR(mask, value) - * This allows the mask/value test of multiple table entries to be - * logically ORed. Once an 'or' entry is matched the decoding action to - * be performed is that of the next entry which isn't an 'or'. E.g. - * - * DECODE_OR (mask1, value1) - * DECODE_OR (mask2, value2) - * DECODE_SIMULATE (mask3, value3, simulation_handler) - * - * This means that if any of the three mask/value pairs match the - * instruction being decoded, then 'simulation_handler' will be used - * for it. - * - * Both the SIMULATE and EMULATE macros have a second form which take an - * additional 'regs' argument. - * - * DECODE_SIMULATEX(mask, value, handler, regs) - * DECODE_EMULATEX (mask, value, handler, regs) - * - * These are used to specify what kind of CPU register is encoded in each of the - * least significant 5 nibbles of the instruction being decoded. The regs value - * is specified using the REGS macro, this takes any of the REG_TYPE_* values - * from enum decode_reg_type as arguments; only the '*' part of the name is - * given. E.g. - * - * REGS(0, ANY, NOPC, 0, ANY) - * - * This indicates an instruction is encoded like: - * - * bits 19..16 ignore - * bits 15..12 any register allowed here - * bits 11.. 8 any register except PC allowed here - * bits 7.. 4 ignore - * bits 3.. 0 any register allowed here - * - * This register specification is checked after a decode table entry is found to - * match an instruction (through the mask/value test). Any invalid register then - * found in the instruction will cause decoding to fail with INSN_REJECTED. In - * the above example this would happen if bits 11..8 of the instruction were - * 1111, indicating R15 or PC. - * - * As well as checking for legal combinations of registers, this data is also - * used to modify the registers encoded in the instructions so that an - * emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.) - * - * Here is a real example which matches ARM instructions of the form - * "AND ,,, " - * - * DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags, - * REGS(ANY, ANY, NOPC, 0, ANY)), - * ^ ^ ^ ^ - * Rn Rd Rs Rm - * - * Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because - * Rs == R15 - * - * Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the - * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into - * the kprobes instruction slot. This can then be called later by the handler - * function emulate_rd12rn16rm0rs8_rwflags in order to simulate the instruction. - */ - -enum decode_type { - DECODE_TYPE_END, - DECODE_TYPE_TABLE, - DECODE_TYPE_CUSTOM, - DECODE_TYPE_SIMULATE, - DECODE_TYPE_EMULATE, - DECODE_TYPE_OR, - DECODE_TYPE_REJECT, - NUM_DECODE_TYPES /* Must be last enum */ -}; - -#define DECODE_TYPE_BITS 4 -#define DECODE_TYPE_MASK ((1 << DECODE_TYPE_BITS) - 1) - -enum decode_reg_type { - REG_TYPE_NONE = 0, /* Not a register, ignore */ - REG_TYPE_ANY, /* Any register allowed */ - REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */ - REG_TYPE_SP, /* Register must be SP */ - REG_TYPE_PC, /* Register must be PC */ - REG_TYPE_NOSP, /* Register must not be SP */ - REG_TYPE_NOSPPC, /* Register must not be SP or PC */ - REG_TYPE_NOPC, /* Register must not be PC */ - REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */ - - /* The following types are used when the encoding for PC indicates - * another instruction form. This distiction only matters for test - * case coverage checks. - */ - REG_TYPE_NOPCX, /* Register must not be PC */ - REG_TYPE_NOSPPCX, /* Register must not be SP or PC */ - - /* Alias to allow '0' arg to be used in REGS macro. */ - REG_TYPE_0 = REG_TYPE_NONE -}; - -#define REGS(r16, r12, r8, r4, r0) \ - ((REG_TYPE_##r16) << 16) + \ - ((REG_TYPE_##r12) << 12) + \ - ((REG_TYPE_##r8) << 8) + \ - ((REG_TYPE_##r4) << 4) + \ - (REG_TYPE_##r0) - -union decode_item { - u32 bits; - const union decode_item *table; - kprobe_insn_handler_t *handler; - kprobe_decode_insn_t *decoder; -}; - - -#define DECODE_END \ - {.bits = DECODE_TYPE_END} - - -struct decode_header { - union decode_item type_regs; - union decode_item mask; - union decode_item value; -}; - -#define DECODE_HEADER(_type, _mask, _value, _regs) \ - {.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)}, \ - {.bits = (_mask)}, \ - {.bits = (_value)} - - -struct decode_table { - struct decode_header header; - union decode_item table; -}; - -#define DECODE_TABLE(_mask, _value, _table) \ - DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0), \ - {.table = (_table)} - - -struct decode_custom { - struct decode_header header; - union decode_item decoder; -}; - -#define DECODE_CUSTOM(_mask, _value, _decoder) \ - DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0), \ - {.decoder = (_decoder)} - - -struct decode_simulate { - struct decode_header header; - union decode_item handler; -}; - -#define DECODE_SIMULATEX(_mask, _value, _handler, _regs) \ - DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs), \ - {.handler = (_handler)} - -#define DECODE_SIMULATE(_mask, _value, _handler) \ - DECODE_SIMULATEX(_mask, _value, _handler, 0) - - -struct decode_emulate { - struct decode_header header; - union decode_item handler; -}; - -#define DECODE_EMULATEX(_mask, _value, _handler, _regs) \ - DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs), \ - {.handler = (_handler)} - -#define DECODE_EMULATE(_mask, _value, _handler) \ - DECODE_EMULATEX(_mask, _value, _handler, 0) - - -struct decode_or { - struct decode_header header; -}; - -#define DECODE_OR(_mask, _value) \ - DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0) - - -struct decode_reject { - struct decode_header header; -}; - -#define DECODE_REJECT(_mask, _value) \ - DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0) - - -#ifdef CONFIG_THUMB2_KERNEL -extern const union decode_item kprobe_decode_thumb16_table[]; -extern const union decode_item kprobe_decode_thumb32_table[]; -#else -extern const union decode_item kprobe_decode_arm_table[]; -#endif - - -int kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi, - const union decode_item *table, bool thumb16); - - #endif /* _ARM_KERNEL_KPROBES_H */ diff -Nur linux-3.14.1/arch/arm/kernel/kprobes-test-arm.c linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test-arm.c --- linux-3.14.1/arch/arm/kernel/kprobes-test-arm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test-arm.c 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,8 @@ #include #include +#include +#include #include "kprobes-test.h" @@ -158,9 +160,9 @@ TEST_SUPPORTED("cmp sp, #0x1000"); /* Data-processing with PC as shift*/ - TEST_UNSUPPORTED(".word 0xe15c0f1e @ cmp r12, r14, asl pc") - TEST_UNSUPPORTED(".word 0xe1a0cf1e @ mov r12, r14, asl pc") - TEST_UNSUPPORTED(".word 0xe08caf1e @ add r10, r12, r14, asl pc") + TEST_UNSUPPORTED(__inst_arm(0xe15c0f1e) " @ cmp r12, r14, asl pc") + TEST_UNSUPPORTED(__inst_arm(0xe1a0cf1e) " @ mov r12, r14, asl pc") + TEST_UNSUPPORTED(__inst_arm(0xe08caf1e) " @ add r10, r12, r14, asl pc") /* Data-processing with PC as shift*/ TEST_UNSUPPORTED("movs pc, r1") @@ -202,7 +204,7 @@ TEST("mrs r0, cpsr") TEST("mrspl r7, cpsr") TEST("mrs r14, cpsr") - TEST_UNSUPPORTED(".word 0xe10ff000 @ mrs r15, cpsr") + TEST_UNSUPPORTED(__inst_arm(0xe10ff000) " @ mrs r15, cpsr") TEST_UNSUPPORTED("mrs r0, spsr") TEST_UNSUPPORTED("mrs lr, spsr") @@ -218,8 +220,8 @@ TEST_R("clzeq r7, r",14,0x1,"") TEST_R("clz lr, r",7, 0xffffffff,"") TEST( "clz r4, sp") - TEST_UNSUPPORTED(".word 0x016fff10 @ clz pc, r0") - TEST_UNSUPPORTED(".word 0x016f0f1f @ clz r0, pc") + TEST_UNSUPPORTED(__inst_arm(0x016fff10) " @ clz pc, r0") + TEST_UNSUPPORTED(__inst_arm(0x016f0f1f) " @ clz r0, pc") #if __LINUX_ARM_ARCH__ >= 6 TEST_UNSUPPORTED("bxj r0") @@ -228,7 +230,7 @@ TEST_BF_R("blx r",0,2f,"") TEST_BB_R("blx r",7,2f,"") TEST_BF_R("blxeq r",14,2f,"") - TEST_UNSUPPORTED(".word 0x0120003f @ blx pc") + TEST_UNSUPPORTED(__inst_arm(0x0120003f) " @ blx pc") TEST_RR( "qadd r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "qaddvs lr, r",9, VAL2,", r",8, VAL1,"") @@ -242,190 +244,190 @@ TEST_RR( "qdsub r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "qdsubvs lr, r",9, VAL2,", r",8, VAL1,"") TEST_R( "qdsub lr, r",9, VAL2,", r13") - TEST_UNSUPPORTED(".word 0xe101f050 @ qadd pc, r0, r1") - TEST_UNSUPPORTED(".word 0xe121f050 @ qsub pc, r0, r1") - TEST_UNSUPPORTED(".word 0xe141f050 @ qdadd pc, r0, r1") - TEST_UNSUPPORTED(".word 0xe161f050 @ qdsub pc, r0, r1") - TEST_UNSUPPORTED(".word 0xe16f2050 @ qdsub r2, r0, pc") - TEST_UNSUPPORTED(".word 0xe161205f @ qdsub r2, pc, r1") + TEST_UNSUPPORTED(__inst_arm(0xe101f050) " @ qadd pc, r0, r1") + TEST_UNSUPPORTED(__inst_arm(0xe121f050) " @ qsub pc, r0, r1") + TEST_UNSUPPORTED(__inst_arm(0xe141f050) " @ qdadd pc, r0, r1") + TEST_UNSUPPORTED(__inst_arm(0xe161f050) " @ qdsub pc, r0, r1") + TEST_UNSUPPORTED(__inst_arm(0xe16f2050) " @ qdsub r2, r0, pc") + TEST_UNSUPPORTED(__inst_arm(0xe161205f) " @ qdsub r2, pc, r1") TEST_UNSUPPORTED("bkpt 0xffff") TEST_UNSUPPORTED("bkpt 0x0000") - TEST_UNSUPPORTED(".word 0xe1600070 @ smc #0") + TEST_UNSUPPORTED(__inst_arm(0xe1600070) " @ smc #0") TEST_GROUP("Halfword multiply and multiply-accumulate") TEST_RRR( "smlabb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "smlabbge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "smlabb lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe10f3281 @ smlabb pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe10f3281) " @ smlabb pc, r1, r2, r3") TEST_RRR( "smlatb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "smlatbge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "smlatb lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe10f32a1 @ smlatb pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe10f32a1) " @ smlatb pc, r1, r2, r3") TEST_RRR( "smlabt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "smlabtge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "smlabt lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe10f32c1 @ smlabt pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe10f32c1) " @ smlabt pc, r1, r2, r3") TEST_RRR( "smlatt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "smlattge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "smlatt lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe10f32e1 @ smlatt pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe10f32e1) " @ smlatt pc, r1, r2, r3") TEST_RRR( "smlawb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "smlawbge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "smlawb lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe12f3281 @ smlawb pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe12f3281) " @ smlawb pc, r1, r2, r3") TEST_RRR( "smlawt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "smlawtge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "smlawt lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe12f32c1 @ smlawt pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe12032cf @ smlawt r0, pc, r2, r3") - TEST_UNSUPPORTED(".word 0xe1203fc1 @ smlawt r0, r1, pc, r3") - TEST_UNSUPPORTED(".word 0xe120f2c1 @ smlawt r0, r1, r2, pc") + TEST_UNSUPPORTED(__inst_arm(0xe12f32c1) " @ smlawt pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe12032cf) " @ smlawt r0, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe1203fc1) " @ smlawt r0, r1, pc, r3") + TEST_UNSUPPORTED(__inst_arm(0xe120f2c1) " @ smlawt r0, r1, r2, pc") TEST_RR( "smulwb r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "smulwbge r7, r",8, VAL3,", r",9, VAL1,"") TEST_R( "smulwb lr, r",1, VAL2,", r13") - TEST_UNSUPPORTED(".word 0xe12f02a1 @ smulwb pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe12f02a1) " @ smulwb pc, r1, r2") TEST_RR( "smulwt r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "smulwtge r7, r",8, VAL3,", r",9, VAL1,"") TEST_R( "smulwt lr, r",1, VAL2,", r13") - TEST_UNSUPPORTED(".word 0xe12f02e1 @ smulwt pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe12f02e1) " @ smulwt pc, r1, r2") TEST_RRRR( "smlalbb r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "smlalbble r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "smlalbb r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe14f1382 @ smlalbb pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe141f382 @ smlalbb r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe14f1382) " @ smlalbb pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe141f382) " @ smlalbb r1, pc, r2, r3") TEST_RRRR( "smlaltb r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "smlaltble r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "smlaltb r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe14f13a2 @ smlaltb pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe141f3a2 @ smlaltb r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe14f13a2) " @ smlaltb pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe141f3a2) " @ smlaltb r1, pc, r2, r3") TEST_RRRR( "smlalbt r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "smlalbtle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "smlalbt r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe14f13c2 @ smlalbt pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe141f3c2 @ smlalbt r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe14f13c2) " @ smlalbt pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe141f3c2) " @ smlalbt r1, pc, r2, r3") TEST_RRRR( "smlaltt r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "smlalttle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "smlaltt r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe14f13e2 @ smlalbb pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe140f3e2 @ smlalbb r0, pc, r2, r3") - TEST_UNSUPPORTED(".word 0xe14013ef @ smlalbb r0, r1, pc, r3") - TEST_UNSUPPORTED(".word 0xe1401fe2 @ smlalbb r0, r1, r2, pc") + TEST_UNSUPPORTED(__inst_arm(0xe14f13e2) " @ smlalbb pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe140f3e2) " @ smlalbb r0, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe14013ef) " @ smlalbb r0, r1, pc, r3") + TEST_UNSUPPORTED(__inst_arm(0xe1401fe2) " @ smlalbb r0, r1, r2, pc") TEST_RR( "smulbb r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "smulbbge r7, r",8, VAL3,", r",9, VAL1,"") TEST_R( "smulbb lr, r",1, VAL2,", r13") - TEST_UNSUPPORTED(".word 0xe16f0281 @ smulbb pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe16f0281) " @ smulbb pc, r1, r2") TEST_RR( "smultb r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "smultbge r7, r",8, VAL3,", r",9, VAL1,"") TEST_R( "smultb lr, r",1, VAL2,", r13") - TEST_UNSUPPORTED(".word 0xe16f02a1 @ smultb pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe16f02a1) " @ smultb pc, r1, r2") TEST_RR( "smulbt r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "smulbtge r7, r",8, VAL3,", r",9, VAL1,"") TEST_R( "smulbt lr, r",1, VAL2,", r13") - TEST_UNSUPPORTED(".word 0xe16f02c1 @ smultb pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe16f02c1) " @ smultb pc, r1, r2") TEST_RR( "smultt r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "smulttge r7, r",8, VAL3,", r",9, VAL1,"") TEST_R( "smultt lr, r",1, VAL2,", r13") - TEST_UNSUPPORTED(".word 0xe16f02e1 @ smultt pc, r1, r2") - TEST_UNSUPPORTED(".word 0xe16002ef @ smultt r0, pc, r2") - TEST_UNSUPPORTED(".word 0xe1600fe1 @ smultt r0, r1, pc") + TEST_UNSUPPORTED(__inst_arm(0xe16f02e1) " @ smultt pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe16002ef) " @ smultt r0, pc, r2") + TEST_UNSUPPORTED(__inst_arm(0xe1600fe1) " @ smultt r0, r1, pc") TEST_GROUP("Multiply and multiply-accumulate") TEST_RR( "mul r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "mulls r7, r",8, VAL2,", r",9, VAL2,"") TEST_R( "mul lr, r",4, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe00f0291 @ mul pc, r1, r2") - TEST_UNSUPPORTED(".word 0xe000029f @ mul r0, pc, r2") - TEST_UNSUPPORTED(".word 0xe0000f91 @ mul r0, r1, pc") + TEST_UNSUPPORTED(__inst_arm(0xe00f0291) " @ mul pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe000029f) " @ mul r0, pc, r2") + TEST_UNSUPPORTED(__inst_arm(0xe0000f91) " @ mul r0, r1, pc") TEST_RR( "muls r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "mullss r7, r",8, VAL2,", r",9, VAL2,"") TEST_R( "muls lr, r",4, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe01f0291 @ muls pc, r1, r2") + TEST_UNSUPPORTED(__inst_arm(0xe01f0291) " @ muls pc, r1, r2") TEST_RRR( "mla r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "mlahi r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "mla lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe02f3291 @ mla pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe02f3291) " @ mla pc, r1, r2, r3") TEST_RRR( "mlas r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "mlahis r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "mlas lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe03f3291 @ mlas pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe03f3291) " @ mlas pc, r1, r2, r3") #if __LINUX_ARM_ARCH__ >= 6 TEST_RR( "umaal r0, r1, r",2, VAL1,", r",3, VAL2,"") TEST_RR( "umaalls r7, r8, r",9, VAL2,", r",10, VAL1,"") TEST_R( "umaal lr, r12, r",11,VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe041f392 @ umaal pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3") - TEST_UNSUPPORTED(".word 0xe0500090 @ undef") - TEST_UNSUPPORTED(".word 0xe05fff9f @ undef") + TEST_UNSUPPORTED(__inst_arm(0xe041f392) " @ umaal pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe04f0392) " @ umaal r0, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0500090) " @ undef") + TEST_UNSUPPORTED(__inst_arm(0xe05fff9f) " @ undef") #endif #if __LINUX_ARM_ARCH__ >= 7 TEST_RRR( "mls r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "mlshi r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "mls lr, r",1, VAL2,", r",2, VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3") - TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3") - TEST_UNSUPPORTED(".word 0xe060f291 @ mls r0, r1, r2, pc") + TEST_UNSUPPORTED(__inst_arm(0xe06f3291) " @ mls pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe060329f) " @ mls r0, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0603f91) " @ mls r0, r1, pc, r3") + TEST_UNSUPPORTED(__inst_arm(0xe060f291) " @ mls r0, r1, r2, pc") #endif - TEST_UNSUPPORTED(".word 0xe0700090 @ undef") - TEST_UNSUPPORTED(".word 0xe07fff9f @ undef") + TEST_UNSUPPORTED(__inst_arm(0xe0700090) " @ undef") + TEST_UNSUPPORTED(__inst_arm(0xe07fff9f) " @ undef") TEST_RR( "umull r0, r1, r",2, VAL1,", r",3, VAL2,"") TEST_RR( "umullls r7, r8, r",9, VAL2,", r",10, VAL1,"") TEST_R( "umull lr, r12, r",11,VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe081f392 @ umull pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe08f1392 @ umull r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe081f392) " @ umull pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe08f1392) " @ umull r1, pc, r2, r3") TEST_RR( "umulls r0, r1, r",2, VAL1,", r",3, VAL2,"") TEST_RR( "umulllss r7, r8, r",9, VAL2,", r",10, VAL1,"") TEST_R( "umulls lr, r12, r",11,VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe091f392 @ umulls pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe09f1392 @ umulls r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe091f392) " @ umulls pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe09f1392) " @ umulls r1, pc, r2, r3") TEST_RRRR( "umlal r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "umlalle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "umlal r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe0af1392 @ umlal pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe0a1f392 @ umlal r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0af1392) " @ umlal pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0a1f392) " @ umlal r1, pc, r2, r3") TEST_RRRR( "umlals r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "umlalles r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "umlals r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe0bf1392 @ umlals pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe0b1f392 @ umlals r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0bf1392) " @ umlals pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0b1f392) " @ umlals r1, pc, r2, r3") TEST_RR( "smull r0, r1, r",2, VAL1,", r",3, VAL2,"") TEST_RR( "smullls r7, r8, r",9, VAL2,", r",10, VAL1,"") TEST_R( "smull lr, r12, r",11,VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe0c1f392 @ smull pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe0cf1392 @ smull r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0c1f392) " @ smull pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0cf1392) " @ smull r1, pc, r2, r3") TEST_RR( "smulls r0, r1, r",2, VAL1,", r",3, VAL2,"") TEST_RR( "smulllss r7, r8, r",9, VAL2,", r",10, VAL1,"") TEST_R( "smulls lr, r12, r",11,VAL3,", r13") - TEST_UNSUPPORTED(".word 0xe0d1f392 @ smulls pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe0df1392 @ smulls r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0d1f392) " @ smulls pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0df1392) " @ smulls r1, pc, r2, r3") TEST_RRRR( "smlal r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "smlalle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "smlal r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe0ef1392 @ smlal pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe0e1f392 @ smlal r1, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0ef1392) " @ smlal pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0e1f392) " @ smlal r1, pc, r2, r3") TEST_RRRR( "smlals r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4) TEST_RRRR( "smlalles r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3) TEST_RRR( "smlals r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13") - TEST_UNSUPPORTED(".word 0xe0ff1392 @ smlals pc, r1, r2, r3") - TEST_UNSUPPORTED(".word 0xe0f0f392 @ smlals r0, pc, r2, r3") - TEST_UNSUPPORTED(".word 0xe0f0139f @ smlals r0, r1, pc, r3") - TEST_UNSUPPORTED(".word 0xe0f01f92 @ smlals r0, r1, r2, pc") + TEST_UNSUPPORTED(__inst_arm(0xe0ff1392) " @ smlals pc, r1, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0f0f392) " @ smlals r0, pc, r2, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0f0139f) " @ smlals r0, r1, pc, r3") + TEST_UNSUPPORTED(__inst_arm(0xe0f01f92) " @ smlals r0, r1, r2, pc") TEST_GROUP("Synchronization primitives") @@ -434,28 +436,28 @@ TEST_R( "swpvs r0, r",1,VAL1,", [sp]") TEST_RP("swp sp, r",14,VAL2,", [r",12,13*4,"]") #else - TEST_UNSUPPORTED(".word 0xe108e097 @ swp lr, r7, [r8]") - TEST_UNSUPPORTED(".word 0x610d0091 @ swpvs r0, r1, [sp]") - TEST_UNSUPPORTED(".word 0xe10cd09e @ swp sp, r14 [r12]") + TEST_UNSUPPORTED(__inst_arm(0xe108e097) " @ swp lr, r7, [r8]") + TEST_UNSUPPORTED(__inst_arm(0x610d0091) " @ swpvs r0, r1, [sp]") + TEST_UNSUPPORTED(__inst_arm(0xe10cd09e) " @ swp sp, r14 [r12]") #endif - TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]") - TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]") - TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]") + TEST_UNSUPPORTED(__inst_arm(0xe102f091) " @ swp pc, r1, [r2]") + TEST_UNSUPPORTED(__inst_arm(0xe102009f) " @ swp r0, pc, [r2]") + TEST_UNSUPPORTED(__inst_arm(0xe10f0091) " @ swp r0, r1, [pc]") #if __LINUX_ARM_ARCH__ < 6 TEST_RP("swpb lr, r",7,VAL2,", [r",8,0,"]") TEST_R( "swpvsb r0, r",1,VAL1,", [sp]") #else - TEST_UNSUPPORTED(".word 0xe148e097 @ swpb lr, r7, [r8]") - TEST_UNSUPPORTED(".word 0x614d0091 @ swpvsb r0, r1, [sp]") + TEST_UNSUPPORTED(__inst_arm(0xe148e097) " @ swpb lr, r7, [r8]") + TEST_UNSUPPORTED(__inst_arm(0x614d0091) " @ swpvsb r0, r1, [sp]") #endif - TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]") + TEST_UNSUPPORTED(__inst_arm(0xe142f091) " @ swpb pc, r1, [r2]") - TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe1200090") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe1300090") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe1500090") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe1600090") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe1700090") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe1100090)) /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe1200090)) /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe1300090)) /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe1500090)) /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe1600090)) /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe1700090)) /* Unallocated space */ #if __LINUX_ARM_ARCH__ >= 6 TEST_UNSUPPORTED("ldrex r2, [sp]") #endif @@ -475,9 +477,9 @@ TEST_RPR( "strneh r",12,VAL2,", [r",11,48,", -r",10,24,"]!") TEST_RPR( "strh r",2, VAL1,", [r",3, 24,"], r",4, 48,"") TEST_RPR( "strh r",10,VAL2,", [r",9, 48,"], -r",11,24,"") - TEST_UNSUPPORTED(".word 0xe1afc0ba @ strh r12, [pc, r10]!") - TEST_UNSUPPORTED(".word 0xe089f0bb @ strh pc, [r9], r11") - TEST_UNSUPPORTED(".word 0xe089a0bf @ strh r10, [r9], pc") + TEST_UNSUPPORTED(__inst_arm(0xe1afc0ba) " @ strh r12, [pc, r10]!") + TEST_UNSUPPORTED(__inst_arm(0xe089f0bb) " @ strh pc, [r9], r11") + TEST_UNSUPPORTED(__inst_arm(0xe089a0bf) " @ strh r10, [r9], pc") TEST_PR( "ldrh r0, [r",0, 48,", -r",2, 24,"]") TEST_PR( "ldrcsh r14, [r",13,0, ", r",12, 48,"]") @@ -485,9 +487,9 @@ TEST_PR( "ldrcch r12, [r",11,48,", -r",10,24,"]!") TEST_PR( "ldrh r2, [r",3, 24,"], r",4, 48,"") TEST_PR( "ldrh r10, [r",9, 48,"], -r",11,24,"") - TEST_UNSUPPORTED(".word 0xe1bfc0ba @ ldrh r12, [pc, r10]!") - TEST_UNSUPPORTED(".word 0xe099f0bb @ ldrh pc, [r9], r11") - TEST_UNSUPPORTED(".word 0xe099a0bf @ ldrh r10, [r9], pc") + TEST_UNSUPPORTED(__inst_arm(0xe1bfc0ba) " @ ldrh r12, [pc, r10]!") + TEST_UNSUPPORTED(__inst_arm(0xe099f0bb) " @ ldrh pc, [r9], r11") + TEST_UNSUPPORTED(__inst_arm(0xe099a0bf) " @ ldrh r10, [r9], pc") TEST_RP( "strh r",0, VAL1,", [r",1, 24,", #-2]") TEST_RP( "strmih r",14,VAL2,", [r",13,0, ", #2]") @@ -495,8 +497,8 @@ TEST_RP( "strplh r",12,VAL2,", [r",11,24,", #-4]!") TEST_RP( "strh r",2, VAL1,", [r",3, 24,"], #48") TEST_RP( "strh r",10,VAL2,", [r",9, 64,"], #-48") - TEST_UNSUPPORTED(".word 0xe1efc3b0 @ strh r12, [pc, #48]!") - TEST_UNSUPPORTED(".word 0xe0c9f3b0 @ strh pc, [r9], #48") + TEST_UNSUPPORTED(__inst_arm(0xe1efc3b0) " @ strh r12, [pc, #48]!") + TEST_UNSUPPORTED(__inst_arm(0xe0c9f3b0) " @ strh pc, [r9], #48") TEST_P( "ldrh r0, [r",0, 24,", #-2]") TEST_P( "ldrvsh r14, [r",13,0, ", #2]") @@ -505,8 +507,8 @@ TEST_P( "ldrh r2, [r",3, 24,"], #48") TEST_P( "ldrh r10, [r",9, 64,"], #-48") TEST( "ldrh r0, [pc, #0]") - TEST_UNSUPPORTED(".word 0xe1ffc3b0 @ ldrh r12, [pc, #48]!") - TEST_UNSUPPORTED(".word 0xe0d9f3b0 @ ldrh pc, [r9], #48") + TEST_UNSUPPORTED(__inst_arm(0xe1ffc3b0) " @ ldrh r12, [pc, #48]!") + TEST_UNSUPPORTED(__inst_arm(0xe0d9f3b0) " @ ldrh pc, [r9], #48") TEST_PR( "ldrsb r0, [r",0, 48,", -r",2, 24,"]") TEST_PR( "ldrhisb r14, [r",13,0,", r",12, 48,"]") @@ -514,8 +516,8 @@ TEST_PR( "ldrlssb r12, [r",11,48,", -r",10,24,"]!") TEST_PR( "ldrsb r2, [r",3, 24,"], r",4, 48,"") TEST_PR( "ldrsb r10, [r",9, 48,"], -r",11,24,"") - TEST_UNSUPPORTED(".word 0xe1bfc0da @ ldrsb r12, [pc, r10]!") - TEST_UNSUPPORTED(".word 0xe099f0db @ ldrsb pc, [r9], r11") + TEST_UNSUPPORTED(__inst_arm(0xe1bfc0da) " @ ldrsb r12, [pc, r10]!") + TEST_UNSUPPORTED(__inst_arm(0xe099f0db) " @ ldrsb pc, [r9], r11") TEST_P( "ldrsb r0, [r",0, 24,", #-1]") TEST_P( "ldrgesb r14, [r",13,0, ", #1]") @@ -524,8 +526,8 @@ TEST_P( "ldrsb r2, [r",3, 24,"], #48") TEST_P( "ldrsb r10, [r",9, 64,"], #-48") TEST( "ldrsb r0, [pc, #0]") - TEST_UNSUPPORTED(".word 0xe1ffc3d0 @ ldrsb r12, [pc, #48]!") - TEST_UNSUPPORTED(".word 0xe0d9f3d0 @ ldrsb pc, [r9], #48") + TEST_UNSUPPORTED(__inst_arm(0xe1ffc3d0) " @ ldrsb r12, [pc, #48]!") + TEST_UNSUPPORTED(__inst_arm(0xe0d9f3d0) " @ ldrsb pc, [r9], #48") TEST_PR( "ldrsh r0, [r",0, 48,", -r",2, 24,"]") TEST_PR( "ldrgtsh r14, [r",13,0, ", r",12, 48,"]") @@ -533,8 +535,8 @@ TEST_PR( "ldrlesh r12, [r",11,48,", -r",10,24,"]!") TEST_PR( "ldrsh r2, [r",3, 24,"], r",4, 48,"") TEST_PR( "ldrsh r10, [r",9, 48,"], -r",11,24,"") - TEST_UNSUPPORTED(".word 0xe1bfc0fa @ ldrsh r12, [pc, r10]!") - TEST_UNSUPPORTED(".word 0xe099f0fb @ ldrsh pc, [r9], r11") + TEST_UNSUPPORTED(__inst_arm(0xe1bfc0fa) " @ ldrsh r12, [pc, r10]!") + TEST_UNSUPPORTED(__inst_arm(0xe099f0fb) " @ ldrsh pc, [r9], r11") TEST_P( "ldrsh r0, [r",0, 24,", #-1]") TEST_P( "ldreqsh r14, [r",13,0 ,", #1]") @@ -543,8 +545,8 @@ TEST_P( "ldrsh r2, [r",3, 24,"], #48") TEST_P( "ldrsh r10, [r",9, 64,"], #-48") TEST( "ldrsh r0, [pc, #0]") - TEST_UNSUPPORTED(".word 0xe1ffc3f0 @ ldrsh r12, [pc, #48]!") - TEST_UNSUPPORTED(".word 0xe0d9f3f0 @ ldrsh pc, [r9], #48") + TEST_UNSUPPORTED(__inst_arm(0xe1ffc3f0) " @ ldrsh r12, [pc, #48]!") + TEST_UNSUPPORTED(__inst_arm(0xe0d9f3f0) " @ ldrsh pc, [r9], #48") #if __LINUX_ARM_ARCH__ >= 7 TEST_UNSUPPORTED("strht r1, [r2], r3") @@ -563,7 +565,7 @@ TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!") TEST_RPR( "strd r",2, VAL1,", [r",5, 24,"], r",4,48,"") TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"") - TEST_UNSUPPORTED(".word 0xe1afc0fa @ strd r12, [pc, r10]!") + TEST_UNSUPPORTED(__inst_arm(0xe1afc0fa) " @ strd r12, [pc, r10]!") TEST_PR( "ldrd r0, [r",0, 48,", -r",2,24,"]") TEST_PR( "ldrmid r8, [r",13,0, ", r",12,48,"]") @@ -571,10 +573,10 @@ TEST_PR( "ldrpld r6, [r",11,48,", -r",10,24,"]!") TEST_PR( "ldrd r2, [r",5, 24,"], r",4,48,"") TEST_PR( "ldrd r10, [r",9,48,"], -r",7,24,"") - TEST_UNSUPPORTED(".word 0xe1afc0da @ ldrd r12, [pc, r10]!") - TEST_UNSUPPORTED(".word 0xe089f0db @ ldrd pc, [r9], r11") - TEST_UNSUPPORTED(".word 0xe089e0db @ ldrd lr, [r9], r11") - TEST_UNSUPPORTED(".word 0xe089c0df @ ldrd r12, [r9], pc") + TEST_UNSUPPORTED(__inst_arm(0xe1afc0da) " @ ldrd r12, [pc, r10]!") + TEST_UNSUPPORTED(__inst_arm(0xe089f0db) " @ ldrd pc, [r9], r11") + TEST_UNSUPPORTED(__inst_arm(0xe089e0db) " @ ldrd lr, [r9], r11") + TEST_UNSUPPORTED(__inst_arm(0xe089c0df) " @ ldrd r12, [r9], pc") TEST_RP( "strd r",0, VAL1,", [r",1, 24,", #-8]") TEST_RP( "strvsd r",8, VAL2,", [r",13,0, ", #8]") @@ -582,7 +584,7 @@ TEST_RP( "strvcd r",12,VAL2,", [r",11,24,", #-16]!") TEST_RP( "strd r",2, VAL1,", [r",4, 24,"], #48") TEST_RP( "strd r",10,VAL2,", [r",9, 64,"], #-48") - TEST_UNSUPPORTED(".word 0xe1efc3f0 @ strd r12, [pc, #48]!") + TEST_UNSUPPORTED(__inst_arm(0xe1efc3f0) " @ strd r12, [pc, #48]!") TEST_P( "ldrd r0, [r",0, 24,", #-8]") TEST_P( "ldrhid r8, [r",13,0, ", #8]") @@ -590,9 +592,9 @@ TEST_P( "ldrlsd r6, [r",11,24,", #-16]!") TEST_P( "ldrd r2, [r",5, 24,"], #48") TEST_P( "ldrd r10, [r",9,6,"], #-48") - TEST_UNSUPPORTED(".word 0xe1efc3d0 @ ldrd r12, [pc, #48]!") - TEST_UNSUPPORTED(".word 0xe0c9f3d0 @ ldrd pc, [r9], #48") - TEST_UNSUPPORTED(".word 0xe0c9e3d0 @ ldrd lr, [r9], #48") + TEST_UNSUPPORTED(__inst_arm(0xe1efc3d0) " @ ldrd r12, [pc, #48]!") + TEST_UNSUPPORTED(__inst_arm(0xe0c9f3d0) " @ ldrd pc, [r9], #48") + TEST_UNSUPPORTED(__inst_arm(0xe0c9e3d0) " @ ldrd lr, [r9], #48") TEST_GROUP("Miscellaneous") @@ -600,11 +602,11 @@ TEST("movw r0, #0") TEST("movw r0, #0xffff") TEST("movw lr, #0xffff") - TEST_UNSUPPORTED(".word 0xe300f000 @ movw pc, #0") + TEST_UNSUPPORTED(__inst_arm(0xe300f000) " @ movw pc, #0") TEST_R("movt r",0, VAL1,", #0") TEST_R("movt r",0, VAL2,", #0xffff") TEST_R("movt r",14,VAL1,", #0xffff") - TEST_UNSUPPORTED(".word 0xe340f000 @ movt pc, #0") + TEST_UNSUPPORTED(__inst_arm(0xe340f000) " @ movt pc, #0") #endif TEST_UNSUPPORTED("msr cpsr, 0x13") @@ -672,20 +674,20 @@ #ifdef CONFIG_THUMB2_KERNEL TEST_ARM_TO_THUMB_INTERWORK_P("ldr pc, [r",0,0,", #15*4]") #endif - TEST_UNSUPPORTED(".word 0xe5af6008 @ str r6, [pc, #8]!") - TEST_UNSUPPORTED(".word 0xe7af6008 @ str r6, [pc, r8]!") - TEST_UNSUPPORTED(".word 0xe5bf6008 @ ldr r6, [pc, #8]!") - TEST_UNSUPPORTED(".word 0xe7bf6008 @ ldr r6, [pc, r8]!") - TEST_UNSUPPORTED(".word 0xe788600f @ str r6, [r8, pc]") - TEST_UNSUPPORTED(".word 0xe798600f @ ldr r6, [r8, pc]") + TEST_UNSUPPORTED(__inst_arm(0xe5af6008) " @ str r6, [pc, #8]!") + TEST_UNSUPPORTED(__inst_arm(0xe7af6008) " @ str r6, [pc, r8]!") + TEST_UNSUPPORTED(__inst_arm(0xe5bf6008) " @ ldr r6, [pc, #8]!") + TEST_UNSUPPORTED(__inst_arm(0xe7bf6008) " @ ldr r6, [pc, r8]!") + TEST_UNSUPPORTED(__inst_arm(0xe788600f) " @ str r6, [r8, pc]") + TEST_UNSUPPORTED(__inst_arm(0xe798600f) " @ ldr r6, [r8, pc]") LOAD_STORE("b") - TEST_UNSUPPORTED(".word 0xe5f7f008 @ ldrb pc, [r7, #8]!") - TEST_UNSUPPORTED(".word 0xe7f7f008 @ ldrb pc, [r7, r8]!") - TEST_UNSUPPORTED(".word 0xe5ef6008 @ strb r6, [pc, #8]!") - TEST_UNSUPPORTED(".word 0xe7ef6008 @ strb r6, [pc, r3]!") - TEST_UNSUPPORTED(".word 0xe5ff6008 @ ldrb r6, [pc, #8]!") - TEST_UNSUPPORTED(".word 0xe7ff6008 @ ldrb r6, [pc, r3]!") + TEST_UNSUPPORTED(__inst_arm(0xe5f7f008) " @ ldrb pc, [r7, #8]!") + TEST_UNSUPPORTED(__inst_arm(0xe7f7f008) " @ ldrb pc, [r7, r8]!") + TEST_UNSUPPORTED(__inst_arm(0xe5ef6008) " @ strb r6, [pc, #8]!") + TEST_UNSUPPORTED(__inst_arm(0xe7ef6008) " @ strb r6, [pc, r3]!") + TEST_UNSUPPORTED(__inst_arm(0xe5ff6008) " @ ldrb r6, [pc, #8]!") + TEST_UNSUPPORTED(__inst_arm(0xe7ff6008) " @ ldrb r6, [pc, r3]!") TEST_UNSUPPORTED("ldrt r0, [r1], #4") TEST_UNSUPPORTED("ldrt r1, [r2], r3") @@ -699,153 +701,153 @@ #if __LINUX_ARM_ARCH__ >= 7 TEST_GROUP("Parallel addition and subtraction, signed") - TEST_UNSUPPORTED(".word 0xe6000010") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe60fffff") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe6000010) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe60fffff) "") /* Unallocated space */ TEST_RR( "sadd16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "sadd16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe61cff1a @ sadd16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe61cff1a) " @ sadd16 pc, r12, r10") TEST_RR( "sasx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "sasx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe61cff3a @ sasx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe61cff3a) " @ sasx pc, r12, r10") TEST_RR( "ssax r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "ssax r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe61cff5a @ ssax pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe61cff5a) " @ ssax pc, r12, r10") TEST_RR( "ssub16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "ssub16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe61cff7a @ ssub16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe61cff7a) " @ ssub16 pc, r12, r10") TEST_RR( "sadd8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "sadd8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe61cff9a @ sadd8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe61000b0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe61fffbf") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe61000d0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe61fffdf") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe61cff9a) " @ sadd8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe61000b0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe61fffbf) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe61000d0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe61fffdf) "") /* Unallocated space */ TEST_RR( "ssub8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "ssub8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe61cfffa @ ssub8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe61cfffa) " @ ssub8 pc, r12, r10") TEST_RR( "qadd16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "qadd16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe62cff1a @ qadd16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe62cff1a) " @ qadd16 pc, r12, r10") TEST_RR( "qasx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "qasx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe62cff3a @ qasx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe62cff3a) " @ qasx pc, r12, r10") TEST_RR( "qsax r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "qsax r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe62cff5a @ qsax pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe62cff5a) " @ qsax pc, r12, r10") TEST_RR( "qsub16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "qsub16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe62cff7a @ qsub16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe62cff7a) " @ qsub16 pc, r12, r10") TEST_RR( "qadd8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "qadd8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe62cff9a @ qadd8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe62000b0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe62fffbf") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe62000d0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe62fffdf") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe62cff9a) " @ qadd8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe62000b0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe62fffbf) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe62000d0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe62fffdf) "") /* Unallocated space */ TEST_RR( "qsub8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "qsub8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe62cfffa @ qsub8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe62cfffa) " @ qsub8 pc, r12, r10") TEST_RR( "shadd16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "shadd16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe63cff1a @ shadd16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe63cff1a) " @ shadd16 pc, r12, r10") TEST_RR( "shasx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "shasx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe63cff3a @ shasx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe63cff3a) " @ shasx pc, r12, r10") TEST_RR( "shsax r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "shsax r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe63cff5a @ shsax pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe63cff5a) " @ shsax pc, r12, r10") TEST_RR( "shsub16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "shsub16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe63cff7a @ shsub16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe63cff7a) " @ shsub16 pc, r12, r10") TEST_RR( "shadd8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "shadd8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe63cff9a @ shadd8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe63000b0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe63fffbf") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe63000d0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe63fffdf") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe63cff9a) " @ shadd8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe63000b0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe63fffbf) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe63000d0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe63fffdf) "") /* Unallocated space */ TEST_RR( "shsub8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "shsub8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe63cfffa @ shsub8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe63cfffa) " @ shsub8 pc, r12, r10") TEST_GROUP("Parallel addition and subtraction, unsigned") - TEST_UNSUPPORTED(".word 0xe6400010") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe64fffff") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe6400010) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe64fffff) "") /* Unallocated space */ TEST_RR( "uadd16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uadd16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe65cff1a @ uadd16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe65cff1a) " @ uadd16 pc, r12, r10") TEST_RR( "uasx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uasx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe65cff3a @ uasx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe65cff3a) " @ uasx pc, r12, r10") TEST_RR( "usax r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "usax r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe65cff5a @ usax pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe65cff5a) " @ usax pc, r12, r10") TEST_RR( "usub16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "usub16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe65cff7a @ usub16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe65cff7a) " @ usub16 pc, r12, r10") TEST_RR( "uadd8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uadd8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe65cff9a @ uadd8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe65000b0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe65fffbf") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe65000d0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe65fffdf") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe65cff9a) " @ uadd8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe65000b0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe65fffbf) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe65000d0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe65fffdf) "") /* Unallocated space */ TEST_RR( "usub8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "usub8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe65cfffa @ usub8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe65cfffa) " @ usub8 pc, r12, r10") TEST_RR( "uqadd16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uqadd16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe66cff1a @ uqadd16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe66cff1a) " @ uqadd16 pc, r12, r10") TEST_RR( "uqasx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uqasx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe66cff3a @ uqasx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe66cff3a) " @ uqasx pc, r12, r10") TEST_RR( "uqsax r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uqsax r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe66cff5a @ uqsax pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe66cff5a) " @ uqsax pc, r12, r10") TEST_RR( "uqsub16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uqsub16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe66cff7a @ uqsub16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe66cff7a) " @ uqsub16 pc, r12, r10") TEST_RR( "uqadd8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uqadd8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe66cff9a @ uqadd8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe66000b0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe66fffbf") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe66000d0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe66fffdf") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe66cff9a) " @ uqadd8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe66000b0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe66fffbf) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe66000d0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe66fffdf) "") /* Unallocated space */ TEST_RR( "uqsub8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uqsub8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe66cfffa @ uqsub8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe66cfffa) " @ uqsub8 pc, r12, r10") TEST_RR( "uhadd16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uhadd16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe67cff1a @ uhadd16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe67cff1a) " @ uhadd16 pc, r12, r10") TEST_RR( "uhasx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uhasx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe67cff3a @ uhasx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe67cff3a) " @ uhasx pc, r12, r10") TEST_RR( "uhsax r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uhsax r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe67cff5a @ uhsax pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe67cff5a) " @ uhsax pc, r12, r10") TEST_RR( "uhsub16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uhsub16 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe67cff7a @ uhsub16 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe67cff7a) " @ uhsub16 pc, r12, r10") TEST_RR( "uhadd8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uhadd8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe67cff9a @ uhadd8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe67000b0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe67fffbf") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe67000d0") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe67fffdf") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe67cff9a) " @ uhadd8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe67000b0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe67fffbf) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe67000d0) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe67fffdf) "") /* Unallocated space */ TEST_RR( "uhsub8 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uhsub8 r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe67cfffa @ uhsub8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe67feffa @ uhsub8 r14, pc, r10") - TEST_UNSUPPORTED(".word 0xe67cefff @ uhsub8 r14, r12, pc") + TEST_UNSUPPORTED(__inst_arm(0xe67cfffa) " @ uhsub8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe67feffa) " @ uhsub8 r14, pc, r10") + TEST_UNSUPPORTED(__inst_arm(0xe67cefff) " @ uhsub8 r14, r12, pc") #endif /* __LINUX_ARM_ARCH__ >= 7 */ #if __LINUX_ARM_ARCH__ >= 6 @@ -853,99 +855,99 @@ TEST_RR( "pkhbt r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "pkhbt r14,r",12, HH1,", r",10,HH2,", lsl #2") - TEST_UNSUPPORTED(".word 0xe68cf11a @ pkhbt pc, r12, r10, lsl #2") + TEST_UNSUPPORTED(__inst_arm(0xe68cf11a) " @ pkhbt pc, r12, r10, lsl #2") TEST_RR( "pkhtb r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "pkhtb r14,r",12, HH1,", r",10,HH2,", asr #2") - TEST_UNSUPPORTED(".word 0xe68cf15a @ pkhtb pc, r12, r10, asr #2") - TEST_UNSUPPORTED(".word 0xe68fe15a @ pkhtb r14, pc, r10, asr #2") - TEST_UNSUPPORTED(".word 0xe68ce15f @ pkhtb r14, r12, pc, asr #2") - TEST_UNSUPPORTED(".word 0xe6900010") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe69fffdf") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe68cf15a) " @ pkhtb pc, r12, r10, asr #2") + TEST_UNSUPPORTED(__inst_arm(0xe68fe15a) " @ pkhtb r14, pc, r10, asr #2") + TEST_UNSUPPORTED(__inst_arm(0xe68ce15f) " @ pkhtb r14, r12, pc, asr #2") + TEST_UNSUPPORTED(__inst_arm(0xe6900010) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe69fffdf) "") /* Unallocated space */ TEST_R( "ssat r0, #24, r",0, VAL1,"") TEST_R( "ssat r14, #24, r",12, VAL2,"") TEST_R( "ssat r0, #24, r",0, VAL1,", lsl #8") TEST_R( "ssat r14, #24, r",12, VAL2,", asr #8") - TEST_UNSUPPORTED(".word 0xe6b7f01c @ ssat pc, #24, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6b7f01c) " @ ssat pc, #24, r12") TEST_R( "usat r0, #24, r",0, VAL1,"") TEST_R( "usat r14, #24, r",12, VAL2,"") TEST_R( "usat r0, #24, r",0, VAL1,", lsl #8") TEST_R( "usat r14, #24, r",12, VAL2,", asr #8") - TEST_UNSUPPORTED(".word 0xe6f7f01c @ usat pc, #24, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6f7f01c) " @ usat pc, #24, r12") TEST_RR( "sxtab16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "sxtab16 r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "sxtb16 r8, r",7, HH1,"") - TEST_UNSUPPORTED(".word 0xe68cf47a @ sxtab16 pc,r12, r10, ror #8") + TEST_UNSUPPORTED(__inst_arm(0xe68cf47a) " @ sxtab16 pc,r12, r10, ror #8") TEST_RR( "sel r0, r",0, VAL1,", r",1, VAL2,"") TEST_RR( "sel r14, r",12,VAL1,", r",10, VAL2,"") - TEST_UNSUPPORTED(".word 0xe68cffba @ sel pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe68fefba @ sel r14, pc, r10") - TEST_UNSUPPORTED(".word 0xe68cefbf @ sel r14, r12, pc") + TEST_UNSUPPORTED(__inst_arm(0xe68cffba) " @ sel pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe68fefba) " @ sel r14, pc, r10") + TEST_UNSUPPORTED(__inst_arm(0xe68cefbf) " @ sel r14, r12, pc") TEST_R( "ssat16 r0, #12, r",0, HH1,"") TEST_R( "ssat16 r14, #12, r",12, HH2,"") - TEST_UNSUPPORTED(".word 0xe6abff3c @ ssat16 pc, #12, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6abff3c) " @ ssat16 pc, #12, r12") TEST_RR( "sxtab r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "sxtab r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "sxtb r8, r",7, HH1,"") - TEST_UNSUPPORTED(".word 0xe6acf47a @ sxtab pc,r12, r10, ror #8") + TEST_UNSUPPORTED(__inst_arm(0xe6acf47a) " @ sxtab pc,r12, r10, ror #8") TEST_R( "rev r0, r",0, VAL1,"") TEST_R( "rev r14, r",12, VAL2,"") - TEST_UNSUPPORTED(".word 0xe6bfff3c @ rev pc, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6bfff3c) " @ rev pc, r12") TEST_RR( "sxtah r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "sxtah r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "sxth r8, r",7, HH1,"") - TEST_UNSUPPORTED(".word 0xe6bcf47a @ sxtah pc,r12, r10, ror #8") + TEST_UNSUPPORTED(__inst_arm(0xe6bcf47a) " @ sxtah pc,r12, r10, ror #8") TEST_R( "rev16 r0, r",0, VAL1,"") TEST_R( "rev16 r14, r",12, VAL2,"") - TEST_UNSUPPORTED(".word 0xe6bfffbc @ rev16 pc, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6bfffbc) " @ rev16 pc, r12") TEST_RR( "uxtab16 r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uxtab16 r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "uxtb16 r8, r",7, HH1,"") - TEST_UNSUPPORTED(".word 0xe6ccf47a @ uxtab16 pc,r12, r10, ror #8") + TEST_UNSUPPORTED(__inst_arm(0xe6ccf47a) " @ uxtab16 pc,r12, r10, ror #8") TEST_R( "usat16 r0, #12, r",0, HH1,"") TEST_R( "usat16 r14, #12, r",12, HH2,"") - TEST_UNSUPPORTED(".word 0xe6ecff3c @ usat16 pc, #12, r12") - TEST_UNSUPPORTED(".word 0xe6ecef3f @ usat16 r14, #12, pc") + TEST_UNSUPPORTED(__inst_arm(0xe6ecff3c) " @ usat16 pc, #12, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6ecef3f) " @ usat16 r14, #12, pc") TEST_RR( "uxtab r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uxtab r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "uxtb r8, r",7, HH1,"") - TEST_UNSUPPORTED(".word 0xe6ecf47a @ uxtab pc,r12, r10, ror #8") + TEST_UNSUPPORTED(__inst_arm(0xe6ecf47a) " @ uxtab pc,r12, r10, ror #8") #if __LINUX_ARM_ARCH__ >= 7 TEST_R( "rbit r0, r",0, VAL1,"") TEST_R( "rbit r14, r",12, VAL2,"") - TEST_UNSUPPORTED(".word 0xe6ffff3c @ rbit pc, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6ffff3c) " @ rbit pc, r12") #endif TEST_RR( "uxtah r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uxtah r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "uxth r8, r",7, HH1,"") - TEST_UNSUPPORTED(".word 0xe6fff077 @ uxth pc, r7") - TEST_UNSUPPORTED(".word 0xe6ff807f @ uxth r8, pc") - TEST_UNSUPPORTED(".word 0xe6fcf47a @ uxtah pc, r12, r10, ror #8") - TEST_UNSUPPORTED(".word 0xe6fce47f @ uxtah r14, r12, pc, ror #8") + TEST_UNSUPPORTED(__inst_arm(0xe6fff077) " @ uxth pc, r7") + TEST_UNSUPPORTED(__inst_arm(0xe6ff807f) " @ uxth r8, pc") + TEST_UNSUPPORTED(__inst_arm(0xe6fcf47a) " @ uxtah pc, r12, r10, ror #8") + TEST_UNSUPPORTED(__inst_arm(0xe6fce47f) " @ uxtah r14, r12, pc, ror #8") TEST_R( "revsh r0, r",0, VAL1,"") TEST_R( "revsh r14, r",12, VAL2,"") - TEST_UNSUPPORTED(".word 0xe6ffff3c @ revsh pc, r12") - TEST_UNSUPPORTED(".word 0xe6ffef3f @ revsh r14, pc") + TEST_UNSUPPORTED(__inst_arm(0xe6ffff3c) " @ revsh pc, r12") + TEST_UNSUPPORTED(__inst_arm(0xe6ffef3f) " @ revsh r14, pc") - TEST_UNSUPPORTED(".word 0xe6900070") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe69fff7f") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe6900070) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe69fff7f) "") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe6d00070") /* Unallocated space */ - TEST_UNSUPPORTED(".word 0xe6dfff7f") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe6d00070) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_arm(0xe6dfff7f) "") /* Unallocated space */ #endif /* __LINUX_ARM_ARCH__ >= 6 */ #if __LINUX_ARM_ARCH__ >= 6 @@ -953,79 +955,79 @@ TEST_RRR( "smlad r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"") TEST_RRR( "smlad r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe70f8a1c @ smlad pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe70f8a1c) " @ smlad pc, r12, r10, r8") TEST_RRR( "smladx r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"") TEST_RRR( "smladx r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe70f8a3c @ smladx pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe70f8a3c) " @ smladx pc, r12, r10, r8") TEST_RR( "smuad r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "smuad r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe70ffa1c @ smuad pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe70ffa1c) " @ smuad pc, r12, r10") TEST_RR( "smuadx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "smuadx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe70ffa3c @ smuadx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe70ffa3c) " @ smuadx pc, r12, r10") TEST_RRR( "smlsd r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"") TEST_RRR( "smlsd r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe70f8a5c @ smlsd pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe70f8a5c) " @ smlsd pc, r12, r10, r8") TEST_RRR( "smlsdx r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"") TEST_RRR( "smlsdx r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe70f8a7c @ smlsdx pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe70f8a7c) " @ smlsdx pc, r12, r10, r8") TEST_RR( "smusd r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "smusd r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe70ffa5c @ smusd pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe70ffa5c) " @ smusd pc, r12, r10") TEST_RR( "smusdx r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "smusdx r14, r",12,HH2,", r",10,HH1,"") - TEST_UNSUPPORTED(".word 0xe70ffa7c @ smusdx pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe70ffa7c) " @ smusdx pc, r12, r10") TEST_RRRR( "smlald r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2) TEST_RRRR( "smlald r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1) - TEST_UNSUPPORTED(".word 0xe74af819 @ smlald pc, r10, r9, r8") - TEST_UNSUPPORTED(".word 0xe74fb819 @ smlald r11, pc, r9, r8") - TEST_UNSUPPORTED(".word 0xe74ab81f @ smlald r11, r10, pc, r8") - TEST_UNSUPPORTED(".word 0xe74abf19 @ smlald r11, r10, r9, pc") + TEST_UNSUPPORTED(__inst_arm(0xe74af819) " @ smlald pc, r10, r9, r8") + TEST_UNSUPPORTED(__inst_arm(0xe74fb819) " @ smlald r11, pc, r9, r8") + TEST_UNSUPPORTED(__inst_arm(0xe74ab81f) " @ smlald r11, r10, pc, r8") + TEST_UNSUPPORTED(__inst_arm(0xe74abf19) " @ smlald r11, r10, r9, pc") TEST_RRRR( "smlaldx r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2) TEST_RRRR( "smlaldx r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1) - TEST_UNSUPPORTED(".word 0xe74af839 @ smlaldx pc, r10, r9, r8") - TEST_UNSUPPORTED(".word 0xe74fb839 @ smlaldx r11, pc, r9, r8") + TEST_UNSUPPORTED(__inst_arm(0xe74af839) " @ smlaldx pc, r10, r9, r8") + TEST_UNSUPPORTED(__inst_arm(0xe74fb839) " @ smlaldx r11, pc, r9, r8") TEST_RRR( "smmla r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"") TEST_RRR( "smmla r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe75f8a1c @ smmla pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe75f8a1c) " @ smmla pc, r12, r10, r8") TEST_RRR( "smmlar r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"") TEST_RRR( "smmlar r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe75f8a3c @ smmlar pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe75f8a3c) " @ smmlar pc, r12, r10, r8") TEST_RR( "smmul r0, r",0, VAL1,", r",1, VAL2,"") TEST_RR( "smmul r14, r",12,VAL2,", r",10,VAL1,"") - TEST_UNSUPPORTED(".word 0xe75ffa1c @ smmul pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe75ffa1c) " @ smmul pc, r12, r10") TEST_RR( "smmulr r0, r",0, VAL1,", r",1, VAL2,"") TEST_RR( "smmulr r14, r",12,VAL2,", r",10,VAL1,"") - TEST_UNSUPPORTED(".word 0xe75ffa3c @ smmulr pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe75ffa3c) " @ smmulr pc, r12, r10") TEST_RRR( "smmls r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"") TEST_RRR( "smmls r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe75f8adc @ smmls pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe75f8adc) " @ smmls pc, r12, r10, r8") TEST_RRR( "smmlsr r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"") TEST_RRR( "smmlsr r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"") - TEST_UNSUPPORTED(".word 0xe75f8afc @ smmlsr pc, r12, r10, r8") - TEST_UNSUPPORTED(".word 0xe75e8aff @ smmlsr r14, pc, r10, r8") - TEST_UNSUPPORTED(".word 0xe75e8ffc @ smmlsr r14, r12, pc, r8") - TEST_UNSUPPORTED(".word 0xe75efafc @ smmlsr r14, r12, r10, pc") + TEST_UNSUPPORTED(__inst_arm(0xe75f8afc) " @ smmlsr pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe75e8aff) " @ smmlsr r14, pc, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe75e8ffc) " @ smmlsr r14, r12, pc, r8") + TEST_UNSUPPORTED(__inst_arm(0xe75efafc) " @ smmlsr r14, r12, r10, pc") TEST_RR( "usad8 r0, r",0, VAL1,", r",1, VAL2,"") TEST_RR( "usad8 r14, r",12,VAL2,", r",10,VAL1,"") - TEST_UNSUPPORTED(".word 0xe75ffa1c @ usad8 pc, r12, r10") - TEST_UNSUPPORTED(".word 0xe75efa1f @ usad8 r14, pc, r10") - TEST_UNSUPPORTED(".word 0xe75eff1c @ usad8 r14, r12, pc") + TEST_UNSUPPORTED(__inst_arm(0xe75ffa1c) " @ usad8 pc, r12, r10") + TEST_UNSUPPORTED(__inst_arm(0xe75efa1f) " @ usad8 r14, pc, r10") + TEST_UNSUPPORTED(__inst_arm(0xe75eff1c) " @ usad8 r14, r12, pc") TEST_RRR( "usada8 r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL3,"") TEST_RRR( "usada8 r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL3,"") - TEST_UNSUPPORTED(".word 0xe78f8a1c @ usada8 pc, r12, r10, r8") - TEST_UNSUPPORTED(".word 0xe78e8a1f @ usada8 r14, pc, r10, r8") - TEST_UNSUPPORTED(".word 0xe78e8f1c @ usada8 r14, r12, pc, r8") + TEST_UNSUPPORTED(__inst_arm(0xe78f8a1c) " @ usada8 pc, r12, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe78e8a1f) " @ usada8 r14, pc, r10, r8") + TEST_UNSUPPORTED(__inst_arm(0xe78e8f1c) " @ usada8 r14, r12, pc, r8") #endif /* __LINUX_ARM_ARCH__ >= 6 */ #if __LINUX_ARM_ARCH__ >= 7 @@ -1034,26 +1036,26 @@ TEST_R( "sbfx r0, r",0 , VAL1,", #0, #31") TEST_R( "sbfxeq r14, r",12, VAL2,", #8, #16") TEST_R( "sbfx r4, r",10, VAL1,", #16, #15") - TEST_UNSUPPORTED(".word 0xe7aff45c @ sbfx pc, r12, #8, #16") + TEST_UNSUPPORTED(__inst_arm(0xe7aff45c) " @ sbfx pc, r12, #8, #16") TEST_R( "ubfx r0, r",0 , VAL1,", #0, #31") TEST_R( "ubfxcs r14, r",12, VAL2,", #8, #16") TEST_R( "ubfx r4, r",10, VAL1,", #16, #15") - TEST_UNSUPPORTED(".word 0xe7eff45c @ ubfx pc, r12, #8, #16") - TEST_UNSUPPORTED(".word 0xe7efc45f @ ubfx r12, pc, #8, #16") + TEST_UNSUPPORTED(__inst_arm(0xe7eff45c) " @ ubfx pc, r12, #8, #16") + TEST_UNSUPPORTED(__inst_arm(0xe7efc45f) " @ ubfx r12, pc, #8, #16") TEST_R( "bfc r",0, VAL1,", #4, #20") TEST_R( "bfcvs r",14,VAL2,", #4, #20") TEST_R( "bfc r",7, VAL1,", #0, #31") TEST_R( "bfc r",8, VAL2,", #0, #31") - TEST_UNSUPPORTED(".word 0xe7def01f @ bfc pc, #0, #31"); + TEST_UNSUPPORTED(__inst_arm(0xe7def01f) " @ bfc pc, #0, #31"); TEST_RR( "bfi r",0, VAL1,", r",0 , VAL2,", #0, #31") TEST_RR( "bfipl r",12,VAL1,", r",14 , VAL2,", #4, #20") - TEST_UNSUPPORTED(".word 0xe7d7f21e @ bfi pc, r14, #4, #20") + TEST_UNSUPPORTED(__inst_arm(0xe7d7f21e) " @ bfi pc, r14, #4, #20") - TEST_UNSUPPORTED(".word 0x07f000f0") /* Permanently UNDEFINED */ - TEST_UNSUPPORTED(".word 0x07ffffff") /* Permanently UNDEFINED */ + TEST_UNSUPPORTED(__inst_arm(0x07f000f0) "") /* Permanently UNDEFINED */ + TEST_UNSUPPORTED(__inst_arm(0x07ffffff) "") /* Permanently UNDEFINED */ #endif /* __LINUX_ARM_ARCH__ >= 6 */ TEST_GROUP("Branch, branch with link, and block data transfer") @@ -1180,43 +1182,43 @@ \ TEST_COPROCESSOR( "stc"two" 0, cr0, [r15, #4]") \ TEST_COPROCESSOR( "stc"two" 0, cr0, [r15, #-4]") \ - TEST_UNSUPPORTED(".word 0x"cc"daf0001 @ stc"two" 0, cr0, [r15, #4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"d2f0001 @ stc"two" 0, cr0, [r15, #-4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"caf0001 @ stc"two" 0, cr0, [r15], #4") \ - TEST_UNSUPPORTED(".word 0x"cc"c2f0001 @ stc"two" 0, cr0, [r15], #-4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##daf0001) " @ stc"two" 0, cr0, [r15, #4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##d2f0001) " @ stc"two" 0, cr0, [r15, #-4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##caf0001) " @ stc"two" 0, cr0, [r15], #4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c2f0001) " @ stc"two" 0, cr0, [r15], #-4") \ TEST_COPROCESSOR( "stc"two" 0, cr0, [r15], {1}") \ TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15, #4]") \ TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15, #-4]") \ - TEST_UNSUPPORTED(".word 0x"cc"def0001 @ stc"two"l 0, cr0, [r15, #4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"d6f0001 @ stc"two"l 0, cr0, [r15, #-4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"cef0001 @ stc"two"l 0, cr0, [r15], #4") \ - TEST_UNSUPPORTED(".word 0x"cc"c6f0001 @ stc"two"l 0, cr0, [r15], #-4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##def0001) " @ stc"two"l 0, cr0, [r15, #4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##d6f0001) " @ stc"two"l 0, cr0, [r15, #-4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##cef0001) " @ stc"two"l 0, cr0, [r15], #4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c6f0001) " @ stc"two"l 0, cr0, [r15], #-4") \ TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15], {1}") \ TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15, #4]") \ TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15, #-4]") \ - TEST_UNSUPPORTED(".word 0x"cc"dbf0001 @ ldc"two" 0, cr0, [r15, #4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"d3f0001 @ ldc"two" 0, cr0, [r15, #-4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"cbf0001 @ ldc"two" 0, cr0, [r15], #4") \ - TEST_UNSUPPORTED(".word 0x"cc"c3f0001 @ ldc"two" 0, cr0, [r15], #-4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##dbf0001) " @ ldc"two" 0, cr0, [r15, #4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##d3f0001) " @ ldc"two" 0, cr0, [r15, #-4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##cbf0001) " @ ldc"two" 0, cr0, [r15], #4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c3f0001) " @ ldc"two" 0, cr0, [r15], #-4") \ TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15], {1}") \ TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15, #4]") \ TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15, #-4]") \ - TEST_UNSUPPORTED(".word 0x"cc"dff0001 @ ldc"two"l 0, cr0, [r15, #4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"d7f0001 @ ldc"two"l 0, cr0, [r15, #-4]!") \ - TEST_UNSUPPORTED(".word 0x"cc"cff0001 @ ldc"two"l 0, cr0, [r15], #4") \ - TEST_UNSUPPORTED(".word 0x"cc"c7f0001 @ ldc"two"l 0, cr0, [r15], #-4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##dff0001) " @ ldc"two"l 0, cr0, [r15, #4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##d7f0001) " @ ldc"two"l 0, cr0, [r15, #-4]!") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##cff0001) " @ ldc"two"l 0, cr0, [r15], #4") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c7f0001) " @ ldc"two"l 0, cr0, [r15], #-4") \ TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15], {1}") #define COPROCESSOR_INSTRUCTIONS_MC_MR(two,cc) \ \ TEST_COPROCESSOR( "mcrr"two" 0, 15, r0, r14, cr0") \ TEST_COPROCESSOR( "mcrr"two" 15, 0, r14, r0, cr15") \ - TEST_UNSUPPORTED(".word 0x"cc"c4f00f0 @ mcrr"two" 0, 15, r0, r15, cr0") \ - TEST_UNSUPPORTED(".word 0x"cc"c40ff0f @ mcrr"two" 15, 0, r15, r0, cr15") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c4f00f0) " @ mcrr"two" 0, 15, r0, r15, cr0") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c40ff0f) " @ mcrr"two" 15, 0, r15, r0, cr15") \ TEST_COPROCESSOR( "mrrc"two" 0, 15, r0, r14, cr0") \ TEST_COPROCESSOR( "mrrc"two" 15, 0, r14, r0, cr15") \ - TEST_UNSUPPORTED(".word 0x"cc"c5f00f0 @ mrrc"two" 0, 15, r0, r15, cr0") \ - TEST_UNSUPPORTED(".word 0x"cc"c50ff0f @ mrrc"two" 15, 0, r15, r0, cr15") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c5f00f0) " @ mrrc"two" 0, 15, r0, r15, cr0") \ + TEST_UNSUPPORTED(__inst_arm(0x##cc##c50ff0f) " @ mrrc"two" 15, 0, r15, r0, cr15") \ TEST_COPROCESSOR( "cdp"two" 15, 15, cr15, cr15, cr15, 7") \ TEST_COPROCESSOR( "cdp"two" 0, 0, cr0, cr0, cr0, 0") \ TEST_COPROCESSOR( "mcr"two" 15, 7, r15, cr15, cr15, 7") \ @@ -1224,8 +1226,8 @@ TEST_COPROCESSOR( "mrc"two" 15, 7, r15, cr15, cr15, 7") \ TEST_COPROCESSOR( "mrc"two" 0, 0, r0, cr0, cr0, 0") - COPROCESSOR_INSTRUCTIONS_ST_LD("","e") - COPROCESSOR_INSTRUCTIONS_MC_MR("","e") + COPROCESSOR_INSTRUCTIONS_ST_LD("",e) + COPROCESSOR_INSTRUCTIONS_MC_MR("",e) TEST_UNSUPPORTED("svc 0") TEST_UNSUPPORTED("svc 0xffffff") @@ -1251,14 +1253,14 @@ TEST_UNSUPPORTED("rfedb sp!") TEST_UNSUPPORTED("rfeia sp!") TEST_UNSUPPORTED("rfeib sp!") - TEST_UNSUPPORTED(".word 0xf81d0a00 @ rfeda pc") - TEST_UNSUPPORTED(".word 0xf91d0a00 @ rfedb pc") - TEST_UNSUPPORTED(".word 0xf89d0a00 @ rfeia pc") - TEST_UNSUPPORTED(".word 0xf99d0a00 @ rfeib pc") - TEST_UNSUPPORTED(".word 0xf83d0a00 @ rfeda pc!") - TEST_UNSUPPORTED(".word 0xf93d0a00 @ rfedb pc!") - TEST_UNSUPPORTED(".word 0xf8bd0a00 @ rfeia pc!") - TEST_UNSUPPORTED(".word 0xf9bd0a00 @ rfeib pc!") + TEST_UNSUPPORTED(__inst_arm(0xf81d0a00) " @ rfeda pc") + TEST_UNSUPPORTED(__inst_arm(0xf91d0a00) " @ rfedb pc") + TEST_UNSUPPORTED(__inst_arm(0xf89d0a00) " @ rfeia pc") + TEST_UNSUPPORTED(__inst_arm(0xf99d0a00) " @ rfeib pc") + TEST_UNSUPPORTED(__inst_arm(0xf83d0a00) " @ rfeda pc!") + TEST_UNSUPPORTED(__inst_arm(0xf93d0a00) " @ rfedb pc!") + TEST_UNSUPPORTED(__inst_arm(0xf8bd0a00) " @ rfeia pc!") + TEST_UNSUPPORTED(__inst_arm(0xf9bd0a00) " @ rfeib pc!") #endif /* __LINUX_ARM_ARCH__ >= 6 */ #if __LINUX_ARM_ARCH__ >= 6 @@ -1285,9 +1287,9 @@ TEST( "blx __dummy_thumb_subroutine_odd") #endif /* __LINUX_ARM_ARCH__ >= 6 */ - COPROCESSOR_INSTRUCTIONS_ST_LD("2","f") + COPROCESSOR_INSTRUCTIONS_ST_LD("2",f) #if __LINUX_ARM_ARCH__ >= 6 - COPROCESSOR_INSTRUCTIONS_MC_MR("2","f") + COPROCESSOR_INSTRUCTIONS_MC_MR("2",f) #endif TEST_GROUP("Miscellaneous instructions, memory hints, and Advanced SIMD instructions") @@ -1317,9 +1319,9 @@ #endif #if __LINUX_ARM_ARCH__ >= 7 - TEST_SUPPORTED( ".word 0xf590f000 @ pldw [r0, #0]") - TEST_SUPPORTED( ".word 0xf797f000 @ pldw [r7, r0]") - TEST_SUPPORTED( ".word 0xf798f18c @ pldw [r8, r12, lsl #3]"); + TEST_SUPPORTED( __inst_arm(0xf590f000) " @ pldw [r0, #0]") + TEST_SUPPORTED( __inst_arm(0xf797f000) " @ pldw [r7, r0]") + TEST_SUPPORTED( __inst_arm(0xf798f18c) " @ pldw [r8, r12, lsl #3]"); #endif #if __LINUX_ARM_ARCH__ >= 7 diff -Nur linux-3.14.1/arch/arm/kernel/kprobes-test.c linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test.c --- linux-3.14.1/arch/arm/kernel/kprobes-test.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test.c 2014-04-13 23:18:35.000000000 +0200 @@ -113,7 +113,7 @@ * @ start of inline data... * .ascii "mov r0, r7" @ text title for test case * .byte 0 - * .align 2 + * .align 2, 0 * * @ TEST_ARG_REG * .byte ARG_TYPE_REG @@ -201,10 +201,14 @@ #include #include #include - +#include +#include +#include #include #include "kprobes.h" +#include "probes-arm.h" +#include "probes-thumb.h" #include "kprobes-test.h" @@ -1329,7 +1333,8 @@ static unsigned long next_instruction(unsigned long pc) { #ifdef CONFIG_THUMB2_KERNEL - if ((pc & 1) && !is_wide_instruction(*(u16 *)(pc - 1))) + if ((pc & 1) && + !is_wide_instruction(__mem_to_opcode_thumb16(*(u16 *)(pc - 1)))) return pc + 2; else #endif @@ -1374,13 +1379,13 @@ if (test_case_is_thumb) { u16 *p = (u16 *)(test_code & ~1); - current_instruction = p[0]; + current_instruction = __mem_to_opcode_thumb16(p[0]); if (is_wide_instruction(current_instruction)) { - current_instruction <<= 16; - current_instruction |= p[1]; + u16 instr2 = __mem_to_opcode_thumb16(p[1]); + current_instruction = __opcode_thumb32_compose(current_instruction, instr2); } } else { - current_instruction = *(u32 *)test_code; + current_instruction = __mem_to_opcode_arm(*(u32 *)test_code); } if (current_title[0] == '.') @@ -1608,7 +1613,7 @@ goto out; pr_info("ARM instruction simulation\n"); - ret = run_test_cases(kprobe_arm_test_cases, kprobe_decode_arm_table); + ret = run_test_cases(kprobe_arm_test_cases, probes_decode_arm_table); if (ret) goto out; @@ -1631,13 +1636,13 @@ pr_info("16-bit Thumb instruction simulation\n"); ret = run_test_cases(kprobe_thumb16_test_cases, - kprobe_decode_thumb16_table); + probes_decode_thumb16_table); if (ret) goto out; pr_info("32-bit Thumb instruction simulation\n"); ret = run_test_cases(kprobe_thumb32_test_cases, - kprobe_decode_thumb32_table); + probes_decode_thumb32_table); if (ret) goto out; #endif diff -Nur linux-3.14.1/arch/arm/kernel/kprobes-test.h linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test.h --- linux-3.14.1/arch/arm/kernel/kprobes-test.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test.h 2014-04-13 23:18:35.000000000 +0200 @@ -115,7 +115,7 @@ /* multiple strings to be concatenated. */ \ ".ascii "#title" \n\t" \ ".byte 0 \n\t" \ - ".align 2 \n\t" + ".align 2, 0 \n\t" #define TEST_ARG_REG(reg, val) \ ".byte "__stringify(ARG_TYPE_REG)" \n\t" \ diff -Nur linux-3.14.1/arch/arm/kernel/kprobes-test-thumb.c linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test-thumb.c --- linux-3.14.1/arch/arm/kernel/kprobes-test-thumb.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes-test-thumb.c 2014-04-13 23:18:35.000000000 +0200 @@ -10,6 +10,7 @@ #include #include +#include #include "kprobes-test.h" @@ -119,7 +120,7 @@ TEST_R( "add sp" ", r",8,-8, "") TEST_R( "add r",14,VAL1,", pc") TEST_BF_R("add pc" ", r",0,2f-1f-8,"") - TEST_UNSUPPORTED(".short 0x44ff @ add pc, pc") + TEST_UNSUPPORTED(__inst_thumb16(0x44ff) " @ add pc, pc") TEST_RR( "cmp r",3,VAL1,", r",8,VAL2,"") TEST_RR( "cmp r",8,VAL2,", r",0,VAL1,"") @@ -150,7 +151,7 @@ TEST_BF_R("blx r",0, 2f+1,"") TEST_BB_R("blx r",14,2f+1,"") - TEST_UNSUPPORTED(".short 0x47f8 @ blx pc") + TEST_UNSUPPORTED(__inst_thumb16(0x47f8) " @ blx pc") TEST_GROUP("Load from Literal Pool") @@ -237,8 +238,8 @@ TEST_R("rev r7, r",0, VAL2,"") TEST_R("rev16 r0, r",7, VAL1,"") TEST_R("rev16 r7, r",0, VAL2,"") - TEST_UNSUPPORTED(".short 0xba80") - TEST_UNSUPPORTED(".short 0xbabf") + TEST_UNSUPPORTED(__inst_thumb16(0xba80) "") + TEST_UNSUPPORTED(__inst_thumb16(0xbabf) "") TEST_R("revsh r0, r",7, VAL1,"") TEST_R("revsh r7, r",0, VAL2,"") @@ -272,8 +273,8 @@ TEST("nop") TEST("wfi") TEST_SUPPORTED("wfe") - TEST_UNSUPPORTED(".short 0xbf50") /* Unassigned hints */ - TEST_UNSUPPORTED(".short 0xbff0") /* Unassigned hints */ + TEST_UNSUPPORTED(__inst_thumb16(0xbf50) "") /* Unassigned hints */ + TEST_UNSUPPORTED(__inst_thumb16(0xbff0) "") /* Unassigned hints */ #define TEST_IT(code, code2) \ TESTCASE_START(code) \ @@ -310,8 +311,8 @@ TEST_BF("bgt 2f") TEST_BB("blt 2b") ) - TEST_UNSUPPORTED(".short 0xde00") - TEST_UNSUPPORTED(".short 0xdeff") + TEST_UNSUPPORTED(__inst_thumb16(0xde00) "") + TEST_UNSUPPORTED(__inst_thumb16(0xdeff) "") TEST_UNSUPPORTED("svc #0x00") TEST_UNSUPPORTED("svc #0xff") @@ -380,13 +381,13 @@ TEST_THUMB_TO_ARM_INTERWORK_P("ldmia r",0,14*4,", {r12,pc}") TEST_THUMB_TO_ARM_INTERWORK_P("ldmia r",13,2*4,", {r0-r12,pc}") - TEST_UNSUPPORTED(".short 0xe88f,0x0101 @ stmia pc, {r0,r8}") - TEST_UNSUPPORTED(".short 0xe92f,0x5f00 @ stmdb pc!, {r8-r12,r14}") - TEST_UNSUPPORTED(".short 0xe8bd,0xc000 @ ldmia r13!, {r14,pc}") - TEST_UNSUPPORTED(".short 0xe93e,0xc000 @ ldmdb r14!, {r14,pc}") - TEST_UNSUPPORTED(".short 0xe8a7,0x3f00 @ stmia r7!, {r8-r12,sp}") - TEST_UNSUPPORTED(".short 0xe8a7,0x9f00 @ stmia r7!, {r8-r12,pc}") - TEST_UNSUPPORTED(".short 0xe93e,0x2010 @ ldmdb r14!, {r4,sp}") + TEST_UNSUPPORTED(__inst_thumb32(0xe88f0101) " @ stmia pc, {r0,r8}") + TEST_UNSUPPORTED(__inst_thumb32(0xe92f5f00) " @ stmdb pc!, {r8-r12,r14}") + TEST_UNSUPPORTED(__inst_thumb32(0xe8bdc000) " @ ldmia r13!, {r14,pc}") + TEST_UNSUPPORTED(__inst_thumb32(0xe93ec000) " @ ldmdb r14!, {r14,pc}") + TEST_UNSUPPORTED(__inst_thumb32(0xe8a73f00) " @ stmia r7!, {r8-r12,sp}") + TEST_UNSUPPORTED(__inst_thumb32(0xe8a79f00) " @ stmia r7!, {r8-r12,pc}") + TEST_UNSUPPORTED(__inst_thumb32(0xe93e2010) " @ ldmdb r14!, {r4,sp}") TEST_GROUP("Load/store double or exclusive, table branch") @@ -402,12 +403,12 @@ "3: .word "__stringify(VAL1)" \n\t" " .word "__stringify(VAL2)) - TEST_UNSUPPORTED(".short 0xe9ff,0xec04 @ ldrd r14, r12, [pc, #16]!") - TEST_UNSUPPORTED(".short 0xe8ff,0xec04 @ ldrd r14, r12, [pc], #16") - TEST_UNSUPPORTED(".short 0xe9d4,0xd800 @ ldrd sp, r8, [r4]") - TEST_UNSUPPORTED(".short 0xe9d4,0xf800 @ ldrd pc, r8, [r4]") - TEST_UNSUPPORTED(".short 0xe9d4,0x7d00 @ ldrd r7, sp, [r4]") - TEST_UNSUPPORTED(".short 0xe9d4,0x7f00 @ ldrd r7, pc, [r4]") + TEST_UNSUPPORTED(__inst_thumb32(0xe9ffec04) " @ ldrd r14, r12, [pc, #16]!") + TEST_UNSUPPORTED(__inst_thumb32(0xe8ffec04) " @ ldrd r14, r12, [pc], #16") + TEST_UNSUPPORTED(__inst_thumb32(0xe9d4d800) " @ ldrd sp, r8, [r4]") + TEST_UNSUPPORTED(__inst_thumb32(0xe9d4f800) " @ ldrd pc, r8, [r4]") + TEST_UNSUPPORTED(__inst_thumb32(0xe9d47d00) " @ ldrd r7, sp, [r4]") + TEST_UNSUPPORTED(__inst_thumb32(0xe9d47f00) " @ ldrd r7, pc, [r4]") TEST_RRP("strd r",0, VAL1,", r",1, VAL2,", [r",1, 24,", #-16]") TEST_RR( "strd r",12,VAL2,", r",14,VAL1,", [sp, #16]") @@ -415,8 +416,8 @@ TEST_RR( "strd r",14,VAL2,", r",12,VAL1,", [sp, #16]!") TEST_RRP("strd r",1, VAL1,", r",0, VAL2,", [r",7, 24,"], #16") TEST_RR( "strd r",7, VAL2,", r",8, VAL1,", [sp], #-16") - TEST_UNSUPPORTED(".short 0xe9ef,0xec04 @ strd r14, r12, [pc, #16]!") - TEST_UNSUPPORTED(".short 0xe8ef,0xec04 @ strd r14, r12, [pc], #16") + TEST_UNSUPPORTED(__inst_thumb32(0xe9efec04) " @ strd r14, r12, [pc, #16]!") + TEST_UNSUPPORTED(__inst_thumb32(0xe8efec04) " @ strd r14, r12, [pc], #16") TEST_RX("tbb [pc, r",0, (9f-(1f+4)),"]", "9: \n\t" @@ -460,9 +461,9 @@ "3: mvn r0, r0 \n\t" "2: nop \n\t") - TEST_UNSUPPORTED(".short 0xe8d1,0xf01f @ tbh [r1, pc]") - TEST_UNSUPPORTED(".short 0xe8d1,0xf01d @ tbh [r1, sp]") - TEST_UNSUPPORTED(".short 0xe8dd,0xf012 @ tbh [sp, r2]") + TEST_UNSUPPORTED(__inst_thumb32(0xe8d1f01f) " @ tbh [r1, pc]") + TEST_UNSUPPORTED(__inst_thumb32(0xe8d1f01d) " @ tbh [r1, sp]") + TEST_UNSUPPORTED(__inst_thumb32(0xe8ddf012) " @ tbh [sp, r2]") TEST_UNSUPPORTED("strexb r0, r1, [r2]") TEST_UNSUPPORTED("strexh r0, r1, [r2]") @@ -540,40 +541,40 @@ TEST_RR("pkhtb r0, r",0, HH1,", r",1, HH2,"") TEST_RR("pkhtb r14,r",12, HH1,", r",10,HH2,", asr #2") - TEST_UNSUPPORTED(".short 0xea17,0x0f0d @ tst.w r7, sp") - TEST_UNSUPPORTED(".short 0xea17,0x0f0f @ tst.w r7, pc") - TEST_UNSUPPORTED(".short 0xea1d,0x0f07 @ tst.w sp, r7") - TEST_UNSUPPORTED(".short 0xea1f,0x0f07 @ tst.w pc, r7") - TEST_UNSUPPORTED(".short 0xf01d,0x1f08 @ tst sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf01f,0x1f08 @ tst pc, #0x00080008") - - TEST_UNSUPPORTED(".short 0xea97,0x0f0d @ teq.w r7, sp") - TEST_UNSUPPORTED(".short 0xea97,0x0f0f @ teq.w r7, pc") - TEST_UNSUPPORTED(".short 0xea9d,0x0f07 @ teq.w sp, r7") - TEST_UNSUPPORTED(".short 0xea9f,0x0f07 @ teq.w pc, r7") - TEST_UNSUPPORTED(".short 0xf09d,0x1f08 @ tst sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf09f,0x1f08 @ tst pc, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xea170f0d) " @ tst.w r7, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xea170f0f) " @ tst.w r7, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xea1d0f07) " @ tst.w sp, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xea1f0f07) " @ tst.w pc, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xf01d1f08) " @ tst sp, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf01f1f08) " @ tst pc, #0x00080008") + + TEST_UNSUPPORTED(__inst_thumb32(0xea970f0d) " @ teq.w r7, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xea970f0f) " @ teq.w r7, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xea9d0f07) " @ teq.w sp, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xea9f0f07) " @ teq.w pc, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xf09d1f08) " @ tst sp, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf09f1f08) " @ tst pc, #0x00080008") - TEST_UNSUPPORTED(".short 0xeb17,0x0f0d @ cmn.w r7, sp") - TEST_UNSUPPORTED(".short 0xeb17,0x0f0f @ cmn.w r7, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xeb170f0d) " @ cmn.w r7, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xeb170f0f) " @ cmn.w r7, pc") TEST_P("cmn.w sp, r",7,0,"") - TEST_UNSUPPORTED(".short 0xeb1f,0x0f07 @ cmn.w pc, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xeb1f0f07) " @ cmn.w pc, r7") TEST( "cmn sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf11f,0x1f08 @ cmn pc, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf11f1f08) " @ cmn pc, #0x00080008") - TEST_UNSUPPORTED(".short 0xebb7,0x0f0d @ cmp.w r7, sp") - TEST_UNSUPPORTED(".short 0xebb7,0x0f0f @ cmp.w r7, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xebb70f0d) " @ cmp.w r7, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xebb70f0f) " @ cmp.w r7, pc") TEST_P("cmp.w sp, r",7,0,"") - TEST_UNSUPPORTED(".short 0xebbf,0x0f07 @ cmp.w pc, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xebbf0f07) " @ cmp.w pc, r7") TEST( "cmp sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf1bf,0x1f08 @ cmp pc, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf1bf1f08) " @ cmp pc, #0x00080008") - TEST_UNSUPPORTED(".short 0xea5f,0x070d @ movs.w r7, sp") - TEST_UNSUPPORTED(".short 0xea5f,0x070f @ movs.w r7, pc") - TEST_UNSUPPORTED(".short 0xea5f,0x0d07 @ movs.w sp, r7") - TEST_UNSUPPORTED(".short 0xea4f,0x0f07 @ mov.w pc, r7") - TEST_UNSUPPORTED(".short 0xf04f,0x1d08 @ mov sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf04f,0x1f08 @ mov pc, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xea5f070d) " @ movs.w r7, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xea5f070f) " @ movs.w r7, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xea5f0d07) " @ movs.w sp, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xea4f0f07) " @ mov.w pc, r7") + TEST_UNSUPPORTED(__inst_thumb32(0xf04f1d08) " @ mov sp, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf04f1f08) " @ mov pc, #0x00080008") TEST_R("add.w r0, sp, r",1, 4,"") TEST_R("adds r0, sp, r",1, 4,", asl #3") @@ -581,15 +582,15 @@ TEST_R("add r0, sp, r",1, 16,", ror #1") TEST_R("add.w sp, sp, r",1, 4,"") TEST_R("add sp, sp, r",1, 4,", asl #3") - TEST_UNSUPPORTED(".short 0xeb0d,0x1d01 @ add sp, sp, r1, asl #4") - TEST_UNSUPPORTED(".short 0xeb0d,0x0d71 @ add sp, sp, r1, ror #1") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0d1d01) " @ add sp, sp, r1, asl #4") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0d71) " @ add sp, sp, r1, ror #1") TEST( "add.w r0, sp, #24") TEST( "add.w sp, sp, #24") - TEST_UNSUPPORTED(".short 0xeb0d,0x0f01 @ add pc, sp, r1") - TEST_UNSUPPORTED(".short 0xeb0d,0x000f @ add r0, sp, pc") - TEST_UNSUPPORTED(".short 0xeb0d,0x000d @ add r0, sp, sp") - TEST_UNSUPPORTED(".short 0xeb0d,0x0d0f @ add sp, sp, pc") - TEST_UNSUPPORTED(".short 0xeb0d,0x0d0d @ add sp, sp, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0f01) " @ add pc, sp, r1") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0d000f) " @ add r0, sp, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0d000d) " @ add r0, sp, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0d0f) " @ add sp, sp, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0d0d) " @ add sp, sp, sp") TEST_R("sub.w r0, sp, r",1, 4,"") TEST_R("subs r0, sp, r",1, 4,", asl #3") @@ -597,54 +598,54 @@ TEST_R("sub r0, sp, r",1, 16,", ror #1") TEST_R("sub.w sp, sp, r",1, 4,"") TEST_R("sub sp, sp, r",1, 4,", asl #3") - TEST_UNSUPPORTED(".short 0xebad,0x1d01 @ sub sp, sp, r1, asl #4") - TEST_UNSUPPORTED(".short 0xebad,0x0d71 @ sub sp, sp, r1, ror #1") - TEST_UNSUPPORTED(".short 0xebad,0x0f01 @ sub pc, sp, r1") + TEST_UNSUPPORTED(__inst_thumb32(0xebad1d01) " @ sub sp, sp, r1, asl #4") + TEST_UNSUPPORTED(__inst_thumb32(0xebad0d71) " @ sub sp, sp, r1, ror #1") + TEST_UNSUPPORTED(__inst_thumb32(0xebad0f01) " @ sub pc, sp, r1") TEST( "sub.w r0, sp, #24") TEST( "sub.w sp, sp, #24") - TEST_UNSUPPORTED(".short 0xea02,0x010f @ and r1, r2, pc") - TEST_UNSUPPORTED(".short 0xea0f,0x0103 @ and r1, pc, r3") - TEST_UNSUPPORTED(".short 0xea02,0x0f03 @ and pc, r2, r3") - TEST_UNSUPPORTED(".short 0xea02,0x010d @ and r1, r2, sp") - TEST_UNSUPPORTED(".short 0xea0d,0x0103 @ and r1, sp, r3") - TEST_UNSUPPORTED(".short 0xea02,0x0d03 @ and sp, r2, r3") - TEST_UNSUPPORTED(".short 0xf00d,0x1108 @ and r1, sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf00f,0x1108 @ and r1, pc, #0x00080008") - TEST_UNSUPPORTED(".short 0xf002,0x1d08 @ and sp, r8, #0x00080008") - TEST_UNSUPPORTED(".short 0xf002,0x1f08 @ and pc, r8, #0x00080008") - - TEST_UNSUPPORTED(".short 0xeb02,0x010f @ add r1, r2, pc") - TEST_UNSUPPORTED(".short 0xeb0f,0x0103 @ add r1, pc, r3") - TEST_UNSUPPORTED(".short 0xeb02,0x0f03 @ add pc, r2, r3") - TEST_UNSUPPORTED(".short 0xeb02,0x010d @ add r1, r2, sp") - TEST_SUPPORTED( ".short 0xeb0d,0x0103 @ add r1, sp, r3") - TEST_UNSUPPORTED(".short 0xeb02,0x0d03 @ add sp, r2, r3") - TEST_SUPPORTED( ".short 0xf10d,0x1108 @ add r1, sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf10d,0x1f08 @ add pc, sp, #0x00080008") - TEST_UNSUPPORTED(".short 0xf10f,0x1108 @ add r1, pc, #0x00080008") - TEST_UNSUPPORTED(".short 0xf102,0x1d08 @ add sp, r8, #0x00080008") - TEST_UNSUPPORTED(".short 0xf102,0x1f08 @ add pc, r8, #0x00080008") - - TEST_UNSUPPORTED(".short 0xeaa0,0x0000") - TEST_UNSUPPORTED(".short 0xeaf0,0x0000") - TEST_UNSUPPORTED(".short 0xeb20,0x0000") - TEST_UNSUPPORTED(".short 0xeb80,0x0000") - TEST_UNSUPPORTED(".short 0xebe0,0x0000") - - TEST_UNSUPPORTED(".short 0xf0a0,0x0000") - TEST_UNSUPPORTED(".short 0xf0c0,0x0000") - TEST_UNSUPPORTED(".short 0xf0f0,0x0000") - TEST_UNSUPPORTED(".short 0xf120,0x0000") - TEST_UNSUPPORTED(".short 0xf180,0x0000") - TEST_UNSUPPORTED(".short 0xf1e0,0x0000") + TEST_UNSUPPORTED(__inst_thumb32(0xea02010f) " @ and r1, r2, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xea0f0103) " @ and r1, pc, r3") + TEST_UNSUPPORTED(__inst_thumb32(0xea020f03) " @ and pc, r2, r3") + TEST_UNSUPPORTED(__inst_thumb32(0xea02010d) " @ and r1, r2, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xea0d0103) " @ and r1, sp, r3") + TEST_UNSUPPORTED(__inst_thumb32(0xea020d03) " @ and sp, r2, r3") + TEST_UNSUPPORTED(__inst_thumb32(0xf00d1108) " @ and r1, sp, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf00f1108) " @ and r1, pc, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf0021d08) " @ and sp, r8, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf0021f08) " @ and pc, r8, #0x00080008") + + TEST_UNSUPPORTED(__inst_thumb32(0xeb02010f) " @ add r1, r2, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xeb0f0103) " @ add r1, pc, r3") + TEST_UNSUPPORTED(__inst_thumb32(0xeb020f03) " @ add pc, r2, r3") + TEST_UNSUPPORTED(__inst_thumb32(0xeb02010d) " @ add r1, r2, sp") + TEST_SUPPORTED( __inst_thumb32(0xeb0d0103) " @ add r1, sp, r3") + TEST_UNSUPPORTED(__inst_thumb32(0xeb020d03) " @ add sp, r2, r3") + TEST_SUPPORTED( __inst_thumb32(0xf10d1108) " @ add r1, sp, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf10d1f08) " @ add pc, sp, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf10f1108) " @ add r1, pc, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf1021d08) " @ add sp, r8, #0x00080008") + TEST_UNSUPPORTED(__inst_thumb32(0xf1021f08) " @ add pc, r8, #0x00080008") + + TEST_UNSUPPORTED(__inst_thumb32(0xeaa00000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xeaf00000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xeb200000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xeb800000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xebe00000) "") + + TEST_UNSUPPORTED(__inst_thumb32(0xf0a00000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf0c00000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf0f00000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf1200000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf1800000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf1e00000) "") TEST_GROUP("Coprocessor instructions") - TEST_UNSUPPORTED(".short 0xec00,0x0000") - TEST_UNSUPPORTED(".short 0xeff0,0x0000") - TEST_UNSUPPORTED(".short 0xfc00,0x0000") - TEST_UNSUPPORTED(".short 0xfff0,0x0000") + TEST_UNSUPPORTED(__inst_thumb32(0xec000000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xeff00000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xfc000000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xfff00000) "") TEST_GROUP("Data-processing (plain binary immediate)") @@ -652,92 +653,92 @@ TEST( "addw r14, sp, #0xf5a") TEST( "addw sp, sp, #0x20") TEST( "addw r7, pc, #0x888") - TEST_UNSUPPORTED(".short 0xf20f,0x1f20 @ addw pc, pc, #0x120") - TEST_UNSUPPORTED(".short 0xf20d,0x1f20 @ addw pc, sp, #0x120") - TEST_UNSUPPORTED(".short 0xf20f,0x1d20 @ addw sp, pc, #0x120") - TEST_UNSUPPORTED(".short 0xf200,0x1d20 @ addw sp, r0, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf20f1f20) " @ addw pc, pc, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf20d1f20) " @ addw pc, sp, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf20f1d20) " @ addw sp, pc, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf2001d20) " @ addw sp, r0, #0x120") TEST_R("subw r0, r",1, VAL1,", #0x123") TEST( "subw r14, sp, #0xf5a") TEST( "subw sp, sp, #0x20") TEST( "subw r7, pc, #0x888") - TEST_UNSUPPORTED(".short 0xf2af,0x1f20 @ subw pc, pc, #0x120") - TEST_UNSUPPORTED(".short 0xf2ad,0x1f20 @ subw pc, sp, #0x120") - TEST_UNSUPPORTED(".short 0xf2af,0x1d20 @ subw sp, pc, #0x120") - TEST_UNSUPPORTED(".short 0xf2a0,0x1d20 @ subw sp, r0, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf2af1f20) " @ subw pc, pc, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf2ad1f20) " @ subw pc, sp, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf2af1d20) " @ subw sp, pc, #0x120") + TEST_UNSUPPORTED(__inst_thumb32(0xf2a01d20) " @ subw sp, r0, #0x120") TEST("movw r0, #0") TEST("movw r0, #0xffff") TEST("movw lr, #0xffff") - TEST_UNSUPPORTED(".short 0xf240,0x0d00 @ movw sp, #0") - TEST_UNSUPPORTED(".short 0xf240,0x0f00 @ movw pc, #0") + TEST_UNSUPPORTED(__inst_thumb32(0xf2400d00) " @ movw sp, #0") + TEST_UNSUPPORTED(__inst_thumb32(0xf2400f00) " @ movw pc, #0") TEST_R("movt r",0, VAL1,", #0") TEST_R("movt r",0, VAL2,", #0xffff") TEST_R("movt r",14,VAL1,", #0xffff") - TEST_UNSUPPORTED(".short 0xf2c0,0x0d00 @ movt sp, #0") - TEST_UNSUPPORTED(".short 0xf2c0,0x0f00 @ movt pc, #0") + TEST_UNSUPPORTED(__inst_thumb32(0xf2c00d00) " @ movt sp, #0") + TEST_UNSUPPORTED(__inst_thumb32(0xf2c00f00) " @ movt pc, #0") TEST_R( "ssat r0, #24, r",0, VAL1,"") TEST_R( "ssat r14, #24, r",12, VAL2,"") TEST_R( "ssat r0, #24, r",0, VAL1,", lsl #8") TEST_R( "ssat r14, #24, r",12, VAL2,", asr #8") - TEST_UNSUPPORTED(".short 0xf30c,0x0d17 @ ssat sp, #24, r12") - TEST_UNSUPPORTED(".short 0xf30c,0x0f17 @ ssat pc, #24, r12") - TEST_UNSUPPORTED(".short 0xf30d,0x0c17 @ ssat r12, #24, sp") - TEST_UNSUPPORTED(".short 0xf30f,0x0c17 @ ssat r12, #24, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xf30c0d17) " @ ssat sp, #24, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf30c0f17) " @ ssat pc, #24, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf30d0c17) " @ ssat r12, #24, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xf30f0c17) " @ ssat r12, #24, pc") TEST_R( "usat r0, #24, r",0, VAL1,"") TEST_R( "usat r14, #24, r",12, VAL2,"") TEST_R( "usat r0, #24, r",0, VAL1,", lsl #8") TEST_R( "usat r14, #24, r",12, VAL2,", asr #8") - TEST_UNSUPPORTED(".short 0xf38c,0x0d17 @ usat sp, #24, r12") - TEST_UNSUPPORTED(".short 0xf38c,0x0f17 @ usat pc, #24, r12") - TEST_UNSUPPORTED(".short 0xf38d,0x0c17 @ usat r12, #24, sp") - TEST_UNSUPPORTED(".short 0xf38f,0x0c17 @ usat r12, #24, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xf38c0d17) " @ usat sp, #24, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf38c0f17) " @ usat pc, #24, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf38d0c17) " @ usat r12, #24, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xf38f0c17) " @ usat r12, #24, pc") TEST_R( "ssat16 r0, #12, r",0, HH1,"") TEST_R( "ssat16 r14, #12, r",12, HH2,"") - TEST_UNSUPPORTED(".short 0xf32c,0x0d0b @ ssat16 sp, #12, r12") - TEST_UNSUPPORTED(".short 0xf32c,0x0f0b @ ssat16 pc, #12, r12") - TEST_UNSUPPORTED(".short 0xf32d,0x0c0b @ ssat16 r12, #12, sp") - TEST_UNSUPPORTED(".short 0xf32f,0x0c0b @ ssat16 r12, #12, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xf32c0d0b) " @ ssat16 sp, #12, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf32c0f0b) " @ ssat16 pc, #12, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf32d0c0b) " @ ssat16 r12, #12, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xf32f0c0b) " @ ssat16 r12, #12, pc") TEST_R( "usat16 r0, #12, r",0, HH1,"") TEST_R( "usat16 r14, #12, r",12, HH2,"") - TEST_UNSUPPORTED(".short 0xf3ac,0x0d0b @ usat16 sp, #12, r12") - TEST_UNSUPPORTED(".short 0xf3ac,0x0f0b @ usat16 pc, #12, r12") - TEST_UNSUPPORTED(".short 0xf3ad,0x0c0b @ usat16 r12, #12, sp") - TEST_UNSUPPORTED(".short 0xf3af,0x0c0b @ usat16 r12, #12, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xf3ac0d0b) " @ usat16 sp, #12, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf3ac0f0b) " @ usat16 pc, #12, r12") + TEST_UNSUPPORTED(__inst_thumb32(0xf3ad0c0b) " @ usat16 r12, #12, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xf3af0c0b) " @ usat16 r12, #12, pc") TEST_R( "sbfx r0, r",0 , VAL1,", #0, #31") TEST_R( "sbfx r14, r",12, VAL2,", #8, #16") TEST_R( "sbfx r4, r",10, VAL1,", #16, #15") - TEST_UNSUPPORTED(".short 0xf34c,0x2d0f @ sbfx sp, r12, #8, #16") - TEST_UNSUPPORTED(".short 0xf34c,0x2f0f @ sbfx pc, r12, #8, #16") - TEST_UNSUPPORTED(".short 0xf34d,0x2c0f @ sbfx r12, sp, #8, #16") - TEST_UNSUPPORTED(".short 0xf34f,0x2c0f @ sbfx r12, pc, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf34c2d0f) " @ sbfx sp, r12, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf34c2f0f) " @ sbfx pc, r12, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf34d2c0f) " @ sbfx r12, sp, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf34f2c0f) " @ sbfx r12, pc, #8, #16") TEST_R( "ubfx r0, r",0 , VAL1,", #0, #31") TEST_R( "ubfx r14, r",12, VAL2,", #8, #16") TEST_R( "ubfx r4, r",10, VAL1,", #16, #15") - TEST_UNSUPPORTED(".short 0xf3cc,0x2d0f @ ubfx sp, r12, #8, #16") - TEST_UNSUPPORTED(".short 0xf3cc,0x2f0f @ ubfx pc, r12, #8, #16") - TEST_UNSUPPORTED(".short 0xf3cd,0x2c0f @ ubfx r12, sp, #8, #16") - TEST_UNSUPPORTED(".short 0xf3cf,0x2c0f @ ubfx r12, pc, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf3cc2d0f) " @ ubfx sp, r12, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf3cc2f0f) " @ ubfx pc, r12, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf3cd2c0f) " @ ubfx r12, sp, #8, #16") + TEST_UNSUPPORTED(__inst_thumb32(0xf3cf2c0f) " @ ubfx r12, pc, #8, #16") TEST_R( "bfc r",0, VAL1,", #4, #20") TEST_R( "bfc r",14,VAL2,", #4, #20") TEST_R( "bfc r",7, VAL1,", #0, #31") TEST_R( "bfc r",8, VAL2,", #0, #31") - TEST_UNSUPPORTED(".short 0xf36f,0x0d1e @ bfc sp, #0, #31") - TEST_UNSUPPORTED(".short 0xf36f,0x0f1e @ bfc pc, #0, #31") + TEST_UNSUPPORTED(__inst_thumb32(0xf36f0d1e) " @ bfc sp, #0, #31") + TEST_UNSUPPORTED(__inst_thumb32(0xf36f0f1e) " @ bfc pc, #0, #31") TEST_RR( "bfi r",0, VAL1,", r",0 , VAL2,", #0, #31") TEST_RR( "bfi r",12,VAL1,", r",14 , VAL2,", #4, #20") - TEST_UNSUPPORTED(".short 0xf36e,0x1d17 @ bfi sp, r14, #4, #20") - TEST_UNSUPPORTED(".short 0xf36e,0x1f17 @ bfi pc, r14, #4, #20") - TEST_UNSUPPORTED(".short 0xf36d,0x1e17 @ bfi r14, sp, #4, #20") + TEST_UNSUPPORTED(__inst_thumb32(0xf36e1d17) " @ bfi sp, r14, #4, #20") + TEST_UNSUPPORTED(__inst_thumb32(0xf36e1f17) " @ bfi pc, r14, #4, #20") + TEST_UNSUPPORTED(__inst_thumb32(0xf36d1e17) " @ bfi r14, sp, #4, #20") TEST_GROUP("Branches and miscellaneous control") @@ -775,14 +776,14 @@ TEST("mrs r0, cpsr") TEST("mrs r14, cpsr") - TEST_UNSUPPORTED(".short 0xf3ef,0x8d00 @ mrs sp, spsr") - TEST_UNSUPPORTED(".short 0xf3ef,0x8f00 @ mrs pc, spsr") + TEST_UNSUPPORTED(__inst_thumb32(0xf3ef8d00) " @ mrs sp, spsr") + TEST_UNSUPPORTED(__inst_thumb32(0xf3ef8f00) " @ mrs pc, spsr") TEST_UNSUPPORTED("mrs r0, spsr") TEST_UNSUPPORTED("mrs lr, spsr") - TEST_UNSUPPORTED(".short 0xf7f0,0x8000 @ smc #0") + TEST_UNSUPPORTED(__inst_thumb32(0xf7f08000) " @ smc #0") - TEST_UNSUPPORTED(".short 0xf7f0,0xa000 @ undefeined") + TEST_UNSUPPORTED(__inst_thumb32(0xf7f0a000) " @ undefeined") TEST_BF( "b.w 2f") TEST_BB( "b.w 2b") @@ -829,15 +830,15 @@ SINGLE_STORE("") TEST("str sp, [sp]") - TEST_UNSUPPORTED(".short 0xf8cf,0xe000 @ str r14, [pc]") - TEST_UNSUPPORTED(".short 0xf8ce,0xf000 @ str pc, [r14]") + TEST_UNSUPPORTED(__inst_thumb32(0xf8cfe000) " @ str r14, [pc]") + TEST_UNSUPPORTED(__inst_thumb32(0xf8cef000) " @ str pc, [r14]") TEST_GROUP("Advanced SIMD element or structure load/store instructions") - TEST_UNSUPPORTED(".short 0xf900,0x0000") - TEST_UNSUPPORTED(".short 0xf92f,0xffff") - TEST_UNSUPPORTED(".short 0xf980,0x0000") - TEST_UNSUPPORTED(".short 0xf9ef,0xffff") + TEST_UNSUPPORTED(__inst_thumb32(0xf9000000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf92fffff) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf9800000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xf9efffff) "") TEST_GROUP("Load single data item and memory hints") @@ -881,20 +882,20 @@ TEST_SUPPORTED("ldr sp, 99f") TEST_SUPPORTED("ldr pc, 99f") - TEST_UNSUPPORTED(".short 0xf854,0x700d @ ldr r7, [r4, sp]") - TEST_UNSUPPORTED(".short 0xf854,0x700f @ ldr r7, [r4, pc]") - TEST_UNSUPPORTED(".short 0xf814,0x700d @ ldrb r7, [r4, sp]") - TEST_UNSUPPORTED(".short 0xf814,0x700f @ ldrb r7, [r4, pc]") - TEST_UNSUPPORTED(".short 0xf89f,0xd004 @ ldrb sp, 99f") - TEST_UNSUPPORTED(".short 0xf814,0xd008 @ ldrb sp, [r4, r8]") - TEST_UNSUPPORTED(".short 0xf894,0xd000 @ ldrb sp, [r4]") - - TEST_UNSUPPORTED(".short 0xf860,0x0000") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xf9ff,0xffff") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xf950,0x0000") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xf95f,0xffff") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xf800,0x0800") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xf97f,0xfaff") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xf854700d) " @ ldr r7, [r4, sp]") + TEST_UNSUPPORTED(__inst_thumb32(0xf854700f) " @ ldr r7, [r4, pc]") + TEST_UNSUPPORTED(__inst_thumb32(0xf814700d) " @ ldrb r7, [r4, sp]") + TEST_UNSUPPORTED(__inst_thumb32(0xf814700f) " @ ldrb r7, [r4, pc]") + TEST_UNSUPPORTED(__inst_thumb32(0xf89fd004) " @ ldrb sp, 99f") + TEST_UNSUPPORTED(__inst_thumb32(0xf814d008) " @ ldrb sp, [r4, r8]") + TEST_UNSUPPORTED(__inst_thumb32(0xf894d000) " @ ldrb sp, [r4]") + + TEST_UNSUPPORTED(__inst_thumb32(0xf8600000) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xf9ffffff) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xf9500000) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xf95fffff) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xf8000800) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xf97ffaff) "") /* Unallocated space */ TEST( "pli [pc, #4]") TEST( "pli [pc, #-4]") @@ -902,22 +903,22 @@ TEST( "pld [pc, #-4]") TEST_P( "pld [r",0,-1024,", #1024]") - TEST( ".short 0xf8b0,0xf400 @ pldw [r0, #1024]") + TEST( __inst_thumb32(0xf8b0f400) " @ pldw [r0, #1024]") TEST_P( "pli [r",4, 0b,", #1024]") TEST_P( "pld [r",7, 120,", #-120]") - TEST( ".short 0xf837,0xfc78 @ pldw [r7, #-120]") + TEST( __inst_thumb32(0xf837fc78) " @ pldw [r7, #-120]") TEST_P( "pli [r",11,120,", #-120]") TEST( "pld [sp, #0]") TEST_PR("pld [r",7, 24, ", r",0, 16,"]") TEST_PR("pld [r",8, 24, ", r",12,16,", lsl #3]") - TEST_SUPPORTED(".short 0xf837,0xf000 @ pldw [r7, r0]") - TEST_SUPPORTED(".short 0xf838,0xf03c @ pldw [r8, r12, lsl #3]"); + TEST_SUPPORTED(__inst_thumb32(0xf837f000) " @ pldw [r7, r0]") + TEST_SUPPORTED(__inst_thumb32(0xf838f03c) " @ pldw [r8, r12, lsl #3]"); TEST_RR("pli [r",12,0b,", r",0, 16,"]") TEST_RR("pli [r",0, 0b,", r",12,16,", lsl #3]") TEST_R( "pld [sp, r",1, 16,"]") - TEST_UNSUPPORTED(".short 0xf817,0xf00d @pld [r7, sp]") - TEST_UNSUPPORTED(".short 0xf817,0xf00f @pld [r7, pc]") + TEST_UNSUPPORTED(__inst_thumb32(0xf817f00d) " @pld [r7, sp]") + TEST_UNSUPPORTED(__inst_thumb32(0xf817f00f) " @pld [r7, pc]") TEST_GROUP("Data-processing (register)") @@ -934,21 +935,21 @@ SHIFTS32("ror") SHIFTS32("rors") - TEST_UNSUPPORTED(".short 0xfa01,0xff02 @ lsl pc, r1, r2") - TEST_UNSUPPORTED(".short 0xfa01,0xfd02 @ lsl sp, r1, r2") - TEST_UNSUPPORTED(".short 0xfa0f,0xf002 @ lsl r0, pc, r2") - TEST_UNSUPPORTED(".short 0xfa0d,0xf002 @ lsl r0, sp, r2") - TEST_UNSUPPORTED(".short 0xfa01,0xf00f @ lsl r0, r1, pc") - TEST_UNSUPPORTED(".short 0xfa01,0xf00d @ lsl r0, r1, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xfa01ff02) " @ lsl pc, r1, r2") + TEST_UNSUPPORTED(__inst_thumb32(0xfa01fd02) " @ lsl sp, r1, r2") + TEST_UNSUPPORTED(__inst_thumb32(0xfa0ff002) " @ lsl r0, pc, r2") + TEST_UNSUPPORTED(__inst_thumb32(0xfa0df002) " @ lsl r0, sp, r2") + TEST_UNSUPPORTED(__inst_thumb32(0xfa01f00f) " @ lsl r0, r1, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xfa01f00d) " @ lsl r0, r1, sp") TEST_RR( "sxtah r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "sxtah r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "sxth r8, r",7, HH1,"") - TEST_UNSUPPORTED(".short 0xfa0f,0xff87 @ sxth pc, r7"); - TEST_UNSUPPORTED(".short 0xfa0f,0xfd87 @ sxth sp, r7"); - TEST_UNSUPPORTED(".short 0xfa0f,0xf88f @ sxth r8, pc"); - TEST_UNSUPPORTED(".short 0xfa0f,0xf88d @ sxth r8, sp"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa0fff87) " @ sxth pc, r7"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa0ffd87) " @ sxth sp, r7"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa0ff88f) " @ sxth r8, pc"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa0ff88d) " @ sxth r8, sp"); TEST_RR( "uxtah r0, r",0, HH1,", r",1, HH2,"") TEST_RR( "uxtah r14,r",12, HH2,", r",10,HH1,", ror #8") @@ -970,8 +971,8 @@ TEST_RR( "uxtab r14,r",12, HH2,", r",10,HH1,", ror #8") TEST_R( "uxtb r8, r",7, HH1,"") - TEST_UNSUPPORTED(".short 0xfa60,0x00f0") - TEST_UNSUPPORTED(".short 0xfa7f,0xffff") + TEST_UNSUPPORTED(__inst_thumb32(0xfa6000f0) "") + TEST_UNSUPPORTED(__inst_thumb32(0xfa7fffff) "") #define PARALLEL_ADD_SUB(op) \ TEST_RR( op"add16 r0, r",0, HH1,", r",1, HH2,"") \ @@ -1019,10 +1020,10 @@ TEST_R("revsh.w r0, r",0, VAL1,"") TEST_R("revsh r14, r",12, VAL2,"") - TEST_UNSUPPORTED(".short 0xfa9c,0xff8c @ rev pc, r12"); - TEST_UNSUPPORTED(".short 0xfa9c,0xfd8c @ rev sp, r12"); - TEST_UNSUPPORTED(".short 0xfa9f,0xfe8f @ rev r14, pc"); - TEST_UNSUPPORTED(".short 0xfa9d,0xfe8d @ rev r14, sp"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa9cff8c) " @ rev pc, r12"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa9cfd8c) " @ rev sp, r12"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa9ffe8f) " @ rev r14, pc"); + TEST_UNSUPPORTED(__inst_thumb32(0xfa9dfe8d) " @ rev r14, sp"); TEST_RR("sel r0, r",0, VAL1,", r",1, VAL2,"") TEST_RR("sel r14, r",12,VAL1,", r",10, VAL2,"") @@ -1031,31 +1032,31 @@ TEST_R("clz r7, r",14,0x1,"") TEST_R("clz lr, r",7, 0xffffffff,"") - TEST_UNSUPPORTED(".short 0xfa80,0xf030") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfab0,0xf000") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfa80f030) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfaffff7f) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfab0f000) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfaffff7f) "") /* Unallocated space */ TEST_GROUP("Multiply, multiply accumulate, and absolute difference operations") TEST_RR( "mul r0, r",1, VAL1,", r",2, VAL2,"") TEST_RR( "mul r7, r",8, VAL2,", r",9, VAL2,"") - TEST_UNSUPPORTED(".short 0xfb08,0xff09 @ mul pc, r8, r9") - TEST_UNSUPPORTED(".short 0xfb08,0xfd09 @ mul sp, r8, r9") - TEST_UNSUPPORTED(".short 0xfb0f,0xf709 @ mul r7, pc, r9") - TEST_UNSUPPORTED(".short 0xfb0d,0xf709 @ mul r7, sp, r9") - TEST_UNSUPPORTED(".short 0xfb08,0xf70f @ mul r7, r8, pc") - TEST_UNSUPPORTED(".short 0xfb08,0xf70d @ mul r7, r8, sp") + TEST_UNSUPPORTED(__inst_thumb32(0xfb08ff09) " @ mul pc, r8, r9") + TEST_UNSUPPORTED(__inst_thumb32(0xfb08fd09) " @ mul sp, r8, r9") + TEST_UNSUPPORTED(__inst_thumb32(0xfb0ff709) " @ mul r7, pc, r9") + TEST_UNSUPPORTED(__inst_thumb32(0xfb0df709) " @ mul r7, sp, r9") + TEST_UNSUPPORTED(__inst_thumb32(0xfb08f70f) " @ mul r7, r8, pc") + TEST_UNSUPPORTED(__inst_thumb32(0xfb08f70d) " @ mul r7, r8, sp") TEST_RRR( "mla r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "mla r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") - TEST_UNSUPPORTED(".short 0xfb08,0xaf09 @ mla pc, r8, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb08,0xad09 @ mla sp, r8, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb0f,0xa709 @ mla r7, pc, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb0d,0xa709 @ mla r7, sp, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb08,0xa70f @ mla r7, r8, pc, r10"); - TEST_UNSUPPORTED(".short 0xfb08,0xa70d @ mla r7, r8, sp, r10"); - TEST_UNSUPPORTED(".short 0xfb08,0xd709 @ mla r7, r8, r9, sp"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb08af09) " @ mla pc, r8, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb08ad09) " @ mla sp, r8, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb0fa709) " @ mla r7, pc, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb0da709) " @ mla r7, sp, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb08a70f) " @ mla r7, r8, pc, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb08a70d) " @ mla r7, r8, sp, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb08d709) " @ mla r7, r8, r9, sp"); TEST_RRR( "mls r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "mls r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") @@ -1123,25 +1124,25 @@ TEST_RR( "usad8 r0, r",0, VAL1,", r",1, VAL2,"") TEST_RR( "usad8 r14, r",12,VAL2,", r",10,VAL1,"") - TEST_UNSUPPORTED(".short 0xfb00,0xf010") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfb0f,0xff1f") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfb70,0xf010") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfb70,0x0010") /* Unallocated space */ - TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfb00f010) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfb0fff1f) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfb70f010) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfb7fff1f) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfb700010) "") /* Unallocated space */ + TEST_UNSUPPORTED(__inst_thumb32(0xfb7fff1f) "") /* Unallocated space */ TEST_GROUP("Long multiply, long multiply accumulate, and divide") TEST_RR( "smull r0, r1, r",2, VAL1,", r",3, VAL2,"") TEST_RR( "smull r7, r8, r",9, VAL2,", r",10, VAL1,"") - TEST_UNSUPPORTED(".short 0xfb89,0xf80a @ smull pc, r8, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb89,0xd80a @ smull sp, r8, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb89,0x7f0a @ smull r7, pc, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb89,0x7d0a @ smull r7, sp, r9, r10"); - TEST_UNSUPPORTED(".short 0xfb8f,0x780a @ smull r7, r8, pc, r10"); - TEST_UNSUPPORTED(".short 0xfb8d,0x780a @ smull r7, r8, sp, r10"); - TEST_UNSUPPORTED(".short 0xfb89,0x780f @ smull r7, r8, r9, pc"); - TEST_UNSUPPORTED(".short 0xfb89,0x780d @ smull r7, r8, r9, sp"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb89f80a) " @ smull pc, r8, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb89d80a) " @ smull sp, r8, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb897f0a) " @ smull r7, pc, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb897d0a) " @ smull r7, sp, r9, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb8f780a) " @ smull r7, r8, pc, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb8d780a) " @ smull r7, r8, sp, r10"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb89780f) " @ smull r7, r8, r9, pc"); + TEST_UNSUPPORTED(__inst_thumb32(0xfb89780d) " @ smull r7, r8, r9, sp"); TEST_RR( "umull r0, r1, r",2, VAL1,", r",3, VAL2,"") TEST_RR( "umull r7, r8, r",9, VAL2,", r",10, VAL1,"") @@ -1175,8 +1176,8 @@ TEST_GROUP("Coprocessor instructions") - TEST_UNSUPPORTED(".short 0xfc00,0x0000") - TEST_UNSUPPORTED(".short 0xffff,0xffff") + TEST_UNSUPPORTED(__inst_thumb32(0xfc000000) "") + TEST_UNSUPPORTED(__inst_thumb32(0xffffffff) "") TEST_GROUP("Testing instructions in IT blocks") diff -Nur linux-3.14.1/arch/arm/kernel/kprobes-thumb.c linux-3.15-rc1.orig/arch/arm/kernel/kprobes-thumb.c --- linux-3.14.1/arch/arm/kernel/kprobes-thumb.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/kprobes-thumb.c 2014-04-13 23:18:35.000000000 +0200 @@ -8,41 +8,25 @@ * published by the Free Software Foundation. */ +#include #include +#include #include -#include #include "kprobes.h" +#include "probes-thumb.h" +/* These emulation encodings are functionally equivalent... */ +#define t32_emulate_rd8rn16rm0ra12_noflags \ + t32_emulate_rdlo12rdhi8rn16rm0_noflags -/* - * True if current instruction is in an IT block. - */ -#define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000) - -/* - * Return the condition code to check for the currently executing instruction. - * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if - * in_it_block returns true. - */ -#define current_cond(cpsr) ((cpsr >> 12) & 0xf) - -/* - * Return the PC value for a probe in thumb code. - * This is the address of the probed instruction plus 4. - * We subtract one because the address will have bit zero set to indicate - * a pointer to thumb code. - */ -static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p) -{ - return (unsigned long)p->addr - 1 + 4; -} +/* t32 thumb actions */ static void __kprobes -t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs) +t32_simulate_table_branch(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -59,19 +43,19 @@ } static void __kprobes -t32_simulate_mrs(struct kprobe *p, struct pt_regs *regs) +t32_simulate_mrs(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rd = (insn >> 8) & 0xf; unsigned long mask = 0xf8ff03df; /* Mask out execution state */ regs->uregs[rd] = regs->ARM_cpsr & mask; } static void __kprobes -t32_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs) +t32_simulate_cond_branch(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc; long offset = insn & 0x7ff; /* imm11 */ offset += (insn & 0x003f0000) >> 5; /* imm6 */ @@ -82,20 +66,21 @@ regs->ARM_pc = pc + (offset * 2); } -static enum kprobe_insn __kprobes -t32_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static enum probes_insn __kprobes +t32_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) { int cc = (insn >> 22) & 0xf; - asi->insn_check_cc = kprobe_condition_checks[cc]; + asi->insn_check_cc = probes_condition_checks[cc]; asi->insn_handler = t32_simulate_cond_branch; return INSN_GOOD_NO_SLOT; } static void __kprobes -t32_simulate_branch(struct kprobe *p, struct pt_regs *regs) +t32_simulate_branch(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc; long offset = insn & 0x7ff; /* imm11 */ offset += (insn & 0x03ff0000) >> 5; /* imm10 */ @@ -108,7 +93,7 @@ if (insn & (1 << 14)) { /* BL or BLX */ - regs->ARM_lr = (unsigned long)p->addr + 4; + regs->ARM_lr = regs->ARM_pc | 1; if (!(insn & (1 << 12))) { /* BLX so switch to ARM mode */ regs->ARM_cpsr &= ~PSR_T_BIT; @@ -120,10 +105,10 @@ } static void __kprobes -t32_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs) +t32_simulate_ldr_literal(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long addr = thumb_probe_pc(p) & ~3; + unsigned long addr = regs->ARM_pc & ~3; int rt = (insn >> 12) & 0xf; unsigned long rtv; @@ -157,24 +142,25 @@ regs->uregs[rt] = rtv; } -static enum kprobe_insn __kprobes -t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static enum probes_insn __kprobes +t32_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) { - enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi); + enum probes_insn ret = kprobe_decode_ldmstm(insn, asi, d); /* Fixup modified instruction to have halfwords in correct order...*/ - insn = asi->insn[0]; - ((u16 *)asi->insn)[0] = insn >> 16; - ((u16 *)asi->insn)[1] = insn & 0xffff; + insn = __mem_to_opcode_arm(asi->insn[0]); + ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn >> 16); + ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0xffff); return ret; } static void __kprobes -t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs) +t32_emulate_ldrdstrd(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p) & ~3; + unsigned long pc = regs->ARM_pc & ~3; int rt1 = (insn >> 12) & 0xf; int rt2 = (insn >> 8) & 0xf; int rn = (insn >> 16) & 0xf; @@ -187,7 +173,7 @@ __asm__ __volatile__ ( "blx %[fn]" : "=r" (rt1v), "=r" (rt2v), "=r" (rnv) - : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn) + : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -198,9 +184,9 @@ } static void __kprobes -t32_emulate_ldrstr(struct kprobe *p, struct pt_regs *regs) +t32_emulate_ldrstr(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rt = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -212,7 +198,7 @@ __asm__ __volatile__ ( "blx %[fn]" : "=r" (rtv), "=r" (rnv) - : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn) + : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -224,9 +210,9 @@ } static void __kprobes -t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs) +t32_emulate_rd8rn16rm0_rwflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rd = (insn >> 8) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; @@ -242,7 +228,7 @@ "mrs %[cpsr], cpsr \n\t" : "=r" (rdv), [cpsr] "=r" (cpsr) : "0" (rdv), "r" (rnv), "r" (rmv), - "1" (cpsr), [fn] "r" (p->ainsn.insn_fn) + "1" (cpsr), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -251,10 +237,10 @@ } static void __kprobes -t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs) +t32_emulate_rd8pc16_noflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc; int rd = (insn >> 8) & 0xf; register unsigned long rdv asm("r1") = regs->uregs[rd]; @@ -263,7 +249,7 @@ __asm__ __volatile__ ( "blx %[fn]" : "=r" (rdv) - : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn) + : "0" (rdv), "r" (rnv), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -271,9 +257,9 @@ } static void __kprobes -t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs) +t32_emulate_rd8rn16_noflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rd = (insn >> 8) & 0xf; int rn = (insn >> 16) & 0xf; @@ -283,7 +269,7 @@ __asm__ __volatile__ ( "blx %[fn]" : "=r" (rdv) - : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn) + : "0" (rdv), "r" (rnv), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -291,9 +277,10 @@ } static void __kprobes -t32_emulate_rdlo12rdhi8rn16rm0_noflags(struct kprobe *p, struct pt_regs *regs) +t32_emulate_rdlo12rdhi8rn16rm0_noflags(probes_opcode_t insn, + struct arch_probes_insn *asi, + struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rdlo = (insn >> 12) & 0xf; int rdhi = (insn >> 8) & 0xf; int rn = (insn >> 16) & 0xf; @@ -308,674 +295,43 @@ "blx %[fn]" : "=r" (rdlov), "=r" (rdhiv) : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv), - [fn] "r" (p->ainsn.insn_fn) + [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); regs->uregs[rdlo] = rdlov; regs->uregs[rdhi] = rdhiv; } - -/* These emulation encodings are functionally equivalent... */ -#define t32_emulate_rd8rn16rm0ra12_noflags \ - t32_emulate_rdlo12rdhi8rn16rm0_noflags - -static const union decode_item t32_table_1110_100x_x0xx[] = { - /* Load/store multiple instructions */ - - /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfe4f0000, 0xe80f0000), - - /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */ - /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xffc00000, 0xe8000000), - /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */ - /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xffc00000, 0xe9800000), - - /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfe508000, 0xe8008000), - /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */ - DECODE_REJECT (0xfe50c000, 0xe810c000), - /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */ - DECODE_REJECT (0xfe402000, 0xe8002000), - - /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */ - /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */ - /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */ - /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */ - DECODE_CUSTOM (0xfe400000, 0xe8000000, t32_decode_ldmstm), - - DECODE_END -}; - -static const union decode_item t32_table_1110_100x_x1xx[] = { - /* Load/store dual, load/store exclusive, table branch */ - - /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */ - /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */ - DECODE_OR (0xff600000, 0xe8600000), - /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */ - /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd, - REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)), - - /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */ - /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */ - DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch, - REGS(NOSP, 0, 0, 0, NOSPPC)), - - /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */ - /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */ - /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */ - /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */ - /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */ - /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */ - /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */ - /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */ - /* And unallocated instructions... */ - DECODE_END -}; - -static const union decode_item t32_table_1110_101x[] = { - /* Data-processing (shifted register) */ - - /* TST 1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */ - /* TEQ 1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */ - DECODE_EMULATEX (0xff700f00, 0xea100f00, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOSPPC, 0, 0, 0, NOSPPC)), - - /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */ - DECODE_OR (0xfff00f00, 0xeb100f00), - /* CMP 1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */ - DECODE_EMULATEX (0xfff00f00, 0xebb00f00, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOPC, 0, 0, 0, NOSPPC)), - - /* MOV 1110 1010 010x 1111 xxxx xxxx xxxx xxxx */ - /* MVN 1110 1010 011x 1111 xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xffcf0000, 0xea4f0000, t32_emulate_rd8rn16rm0_rwflags, - REGS(0, 0, NOSPPC, 0, NOSPPC)), - - /* ??? 1110 1010 101x xxxx xxxx xxxx xxxx xxxx */ - /* ??? 1110 1010 111x xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xffa00000, 0xeaa00000), - /* ??? 1110 1011 001x xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xffe00000, 0xeb200000), - /* ??? 1110 1011 100x xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xffe00000, 0xeb800000), - /* ??? 1110 1011 111x xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xffe00000, 0xebe00000), - - /* ADD/SUB SP, SP, Rm, LSL #0..3 */ - /* 1110 1011 x0xx 1101 x000 1101 xx00 xxxx */ - DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, t32_emulate_rd8rn16rm0_rwflags, - REGS(SP, 0, SP, 0, NOSPPC)), - - /* ADD/SUB SP, SP, Rm, shift */ - /* 1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */ - DECODE_REJECT (0xff4f0f00, 0xeb0d0d00), - - /* ADD/SUB Rd, SP, Rm, shift */ - /* 1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, t32_emulate_rd8rn16rm0_rwflags, - REGS(SP, 0, NOPC, 0, NOSPPC)), - - /* AND 1110 1010 000x xxxx xxxx xxxx xxxx xxxx */ - /* BIC 1110 1010 001x xxxx xxxx xxxx xxxx xxxx */ - /* ORR 1110 1010 010x xxxx xxxx xxxx xxxx xxxx */ - /* ORN 1110 1010 011x xxxx xxxx xxxx xxxx xxxx */ - /* EOR 1110 1010 100x xxxx xxxx xxxx xxxx xxxx */ - /* PKH 1110 1010 110x xxxx xxxx xxxx xxxx xxxx */ - /* ADD 1110 1011 000x xxxx xxxx xxxx xxxx xxxx */ - /* ADC 1110 1011 010x xxxx xxxx xxxx xxxx xxxx */ - /* SBC 1110 1011 011x xxxx xxxx xxxx xxxx xxxx */ - /* SUB 1110 1011 101x xxxx xxxx xxxx xxxx xxxx */ - /* RSB 1110 1011 110x xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfe000000, 0xea000000, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)), - - DECODE_END -}; - -static const union decode_item t32_table_1111_0x0x___0[] = { - /* Data-processing (modified immediate) */ - - /* TST 1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */ - /* TEQ 1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */ - DECODE_EMULATEX (0xfb708f00, 0xf0100f00, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOSPPC, 0, 0, 0, 0)), - - /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */ - DECODE_OR (0xfbf08f00, 0xf1100f00), - /* CMP 1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */ - DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOPC, 0, 0, 0, 0)), - - /* MOV 1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */ - /* MVN 1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, t32_emulate_rd8rn16rm0_rwflags, - REGS(0, 0, NOSPPC, 0, 0)), - - /* ??? 1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfbe08000, 0xf0a00000), - /* ??? 1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */ - /* ??? 1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfbc08000, 0xf0c00000), - /* ??? 1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfbe08000, 0xf1200000), - /* ??? 1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfbe08000, 0xf1800000), - /* ??? 1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfbe08000, 0xf1e00000), - - /* ADD Rd, SP, #imm 1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */ - /* SUB Rd, SP, #imm 1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, t32_emulate_rd8rn16rm0_rwflags, - REGS(SP, 0, NOPC, 0, 0)), - - /* AND 1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */ - /* BIC 1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */ - /* ORR 1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */ - /* ORN 1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */ - /* EOR 1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */ - /* ADD 1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */ - /* ADC 1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */ - /* SBC 1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */ - /* SUB 1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */ - /* RSB 1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfa008000, 0xf0000000, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOSPPC, 0, NOSPPC, 0, 0)), - - DECODE_END -}; - -static const union decode_item t32_table_1111_0x1x___0[] = { - /* Data-processing (plain binary immediate) */ - - /* ADDW Rd, PC, #imm 1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */ - DECODE_OR (0xfbff8000, 0xf20f0000), - /* SUBW Rd, PC, #imm 1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfbff8000, 0xf2af0000, t32_emulate_rd8pc16_noflags, - REGS(PC, 0, NOSPPC, 0, 0)), - - /* ADDW SP, SP, #imm 1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */ - DECODE_OR (0xfbff8f00, 0xf20d0d00), - /* SUBW SP, SP, #imm 1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */ - DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, t32_emulate_rd8rn16_noflags, - REGS(SP, 0, SP, 0, 0)), - - /* ADDW 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */ - DECODE_OR (0xfbf08000, 0xf2000000), - /* SUBW 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfbf08000, 0xf2a00000, t32_emulate_rd8rn16_noflags, - REGS(NOPCX, 0, NOSPPC, 0, 0)), - - /* MOVW 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */ - /* MOVT 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfb708000, 0xf2400000, t32_emulate_rd8rn16_noflags, - REGS(0, 0, NOSPPC, 0, 0)), - - /* SSAT16 1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */ - /* SSAT 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */ - /* USAT16 1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */ - /* USAT 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfb508000, 0xf3000000, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOSPPC, 0, NOSPPC, 0, 0)), - - /* SFBX 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */ - /* UFBX 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfb708000, 0xf3400000, t32_emulate_rd8rn16_noflags, - REGS(NOSPPC, 0, NOSPPC, 0, 0)), - - /* BFC 1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfbff8000, 0xf36f0000, t32_emulate_rd8rn16_noflags, - REGS(0, 0, NOSPPC, 0, 0)), - - /* BFI 1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfbf08000, 0xf3600000, t32_emulate_rd8rn16_noflags, - REGS(NOSPPCX, 0, NOSPPC, 0, 0)), - - DECODE_END -}; - -static const union decode_item t32_table_1111_0xxx___1[] = { - /* Branches and miscellaneous control */ - - /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */ - DECODE_OR (0xfff0d7ff, 0xf3a08001), - /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */ - DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none), - /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */ - /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */ - /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */ - DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop), - - /* MRS Rd, CPSR 1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */ - DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, t32_simulate_mrs, - REGS(0, 0, NOSPPC, 0, 0)), - - /* - * Unsupported instructions - * 1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx - * - * MSR 1111 0011 100x xxxx 10x0 xxxx xxxx xxxx - * DBG hint 1111 0011 1010 xxxx 10x0 x000 1111 xxxx - * Unallocated hints 1111 0011 1010 xxxx 10x0 x000 xxxx xxxx - * CPS 1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx - * CLREX/DSB/DMB/ISB 1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx - * BXJ 1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx - * SUBS PC,LR,# 1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx - * MRS Rd, SPSR 1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx - * SMC 1111 0111 1111 xxxx 1000 xxxx xxxx xxxx - * UNDEFINED 1111 0111 1111 xxxx 1010 xxxx xxxx xxxx - * ??? 1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx - */ - DECODE_REJECT (0xfb80d000, 0xf3808000), - - /* Bcc 1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */ - DECODE_CUSTOM (0xf800d000, 0xf0008000, t32_decode_cond_branch), - - /* BLX 1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */ - DECODE_OR (0xf800d001, 0xf000c000), - /* B 1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */ - /* BL 1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */ - DECODE_SIMULATE (0xf8009000, 0xf0009000, t32_simulate_branch), - - DECODE_END -}; - -static const union decode_item t32_table_1111_100x_x0x1__1111[] = { - /* Memory hints */ - - /* PLD (literal) 1111 1000 x001 1111 1111 xxxx xxxx xxxx */ - /* PLI (literal) 1111 1001 x001 1111 1111 xxxx xxxx xxxx */ - DECODE_SIMULATE (0xfe7ff000, 0xf81ff000, kprobe_simulate_nop), - - /* PLD{W} (immediate) 1111 1000 10x1 xxxx 1111 xxxx xxxx xxxx */ - DECODE_OR (0xffd0f000, 0xf890f000), - /* PLD{W} (immediate) 1111 1000 00x1 xxxx 1111 1100 xxxx xxxx */ - DECODE_OR (0xffd0ff00, 0xf810fc00), - /* PLI (immediate) 1111 1001 1001 xxxx 1111 xxxx xxxx xxxx */ - DECODE_OR (0xfff0f000, 0xf990f000), - /* PLI (immediate) 1111 1001 0001 xxxx 1111 1100 xxxx xxxx */ - DECODE_SIMULATEX(0xfff0ff00, 0xf910fc00, kprobe_simulate_nop, - REGS(NOPCX, 0, 0, 0, 0)), - - /* PLD{W} (register) 1111 1000 00x1 xxxx 1111 0000 00xx xxxx */ - DECODE_OR (0xffd0ffc0, 0xf810f000), - /* PLI (register) 1111 1001 0001 xxxx 1111 0000 00xx xxxx */ - DECODE_SIMULATEX(0xfff0ffc0, 0xf910f000, kprobe_simulate_nop, - REGS(NOPCX, 0, 0, 0, NOSPPC)), - - /* Other unallocated instructions... */ - DECODE_END -}; - -static const union decode_item t32_table_1111_100x[] = { - /* Store/Load single data item */ - - /* ??? 1111 100x x11x xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfe600000, 0xf8600000), - - /* ??? 1111 1001 0101 xxxx xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xfff00000, 0xf9500000), - - /* ??? 1111 100x 0xxx xxxx xxxx 10x0 xxxx xxxx */ - DECODE_REJECT (0xfe800d00, 0xf8000800), - - /* STRBT 1111 1000 0000 xxxx xxxx 1110 xxxx xxxx */ - /* STRHT 1111 1000 0010 xxxx xxxx 1110 xxxx xxxx */ - /* STRT 1111 1000 0100 xxxx xxxx 1110 xxxx xxxx */ - /* LDRBT 1111 1000 0001 xxxx xxxx 1110 xxxx xxxx */ - /* LDRSBT 1111 1001 0001 xxxx xxxx 1110 xxxx xxxx */ - /* LDRHT 1111 1000 0011 xxxx xxxx 1110 xxxx xxxx */ - /* LDRSHT 1111 1001 0011 xxxx xxxx 1110 xxxx xxxx */ - /* LDRT 1111 1000 0101 xxxx xxxx 1110 xxxx xxxx */ - DECODE_REJECT (0xfe800f00, 0xf8000e00), - - /* STR{,B,H} Rn,[PC...] 1111 1000 xxx0 1111 xxxx xxxx xxxx xxxx */ - DECODE_REJECT (0xff1f0000, 0xf80f0000), - - /* STR{,B,H} PC,[Rn...] 1111 1000 xxx0 xxxx 1111 xxxx xxxx xxxx */ - DECODE_REJECT (0xff10f000, 0xf800f000), - - /* LDR (literal) 1111 1000 x101 1111 xxxx xxxx xxxx xxxx */ - DECODE_SIMULATEX(0xff7f0000, 0xf85f0000, t32_simulate_ldr_literal, - REGS(PC, ANY, 0, 0, 0)), - - /* STR (immediate) 1111 1000 0100 xxxx xxxx 1xxx xxxx xxxx */ - /* LDR (immediate) 1111 1000 0101 xxxx xxxx 1xxx xxxx xxxx */ - DECODE_OR (0xffe00800, 0xf8400800), - /* STR (immediate) 1111 1000 1100 xxxx xxxx xxxx xxxx xxxx */ - /* LDR (immediate) 1111 1000 1101 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xffe00000, 0xf8c00000, t32_emulate_ldrstr, - REGS(NOPCX, ANY, 0, 0, 0)), - - /* STR (register) 1111 1000 0100 xxxx xxxx 0000 00xx xxxx */ - /* LDR (register) 1111 1000 0101 xxxx xxxx 0000 00xx xxxx */ - DECODE_EMULATEX (0xffe00fc0, 0xf8400000, t32_emulate_ldrstr, - REGS(NOPCX, ANY, 0, 0, NOSPPC)), - - /* LDRB (literal) 1111 1000 x001 1111 xxxx xxxx xxxx xxxx */ - /* LDRSB (literal) 1111 1001 x001 1111 xxxx xxxx xxxx xxxx */ - /* LDRH (literal) 1111 1000 x011 1111 xxxx xxxx xxxx xxxx */ - /* LDRSH (literal) 1111 1001 x011 1111 xxxx xxxx xxxx xxxx */ - DECODE_SIMULATEX(0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal, - REGS(PC, NOSPPCX, 0, 0, 0)), - - /* STRB (immediate) 1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */ - /* STRH (immediate) 1111 1000 0010 xxxx xxxx 1xxx xxxx xxxx */ - /* LDRB (immediate) 1111 1000 0001 xxxx xxxx 1xxx xxxx xxxx */ - /* LDRSB (immediate) 1111 1001 0001 xxxx xxxx 1xxx xxxx xxxx */ - /* LDRH (immediate) 1111 1000 0011 xxxx xxxx 1xxx xxxx xxxx */ - /* LDRSH (immediate) 1111 1001 0011 xxxx xxxx 1xxx xxxx xxxx */ - DECODE_OR (0xfec00800, 0xf8000800), - /* STRB (immediate) 1111 1000 1000 xxxx xxxx xxxx xxxx xxxx */ - /* STRH (immediate) 1111 1000 1010 xxxx xxxx xxxx xxxx xxxx */ - /* LDRB (immediate) 1111 1000 1001 xxxx xxxx xxxx xxxx xxxx */ - /* LDRSB (immediate) 1111 1001 1001 xxxx xxxx xxxx xxxx xxxx */ - /* LDRH (immediate) 1111 1000 1011 xxxx xxxx xxxx xxxx xxxx */ - /* LDRSH (immediate) 1111 1001 1011 xxxx xxxx xxxx xxxx xxxx */ - DECODE_EMULATEX (0xfec00000, 0xf8800000, t32_emulate_ldrstr, - REGS(NOPCX, NOSPPCX, 0, 0, 0)), - - /* STRB (register) 1111 1000 0000 xxxx xxxx 0000 00xx xxxx */ - /* STRH (register) 1111 1000 0010 xxxx xxxx 0000 00xx xxxx */ - /* LDRB (register) 1111 1000 0001 xxxx xxxx 0000 00xx xxxx */ - /* LDRSB (register) 1111 1001 0001 xxxx xxxx 0000 00xx xxxx */ - /* LDRH (register) 1111 1000 0011 xxxx xxxx 0000 00xx xxxx */ - /* LDRSH (register) 1111 1001 0011 xxxx xxxx 0000 00xx xxxx */ - DECODE_EMULATEX (0xfe800fc0, 0xf8000000, t32_emulate_ldrstr, - REGS(NOPCX, NOSPPCX, 0, 0, NOSPPC)), - - /* Other unallocated instructions... */ - DECODE_END -}; - -static const union decode_item t32_table_1111_1010___1111[] = { - /* Data-processing (register) */ - - /* ??? 1111 1010 011x xxxx 1111 xxxx 1xxx xxxx */ - DECODE_REJECT (0xffe0f080, 0xfa60f080), - - /* SXTH 1111 1010 0000 1111 1111 xxxx 1xxx xxxx */ - /* UXTH 1111 1010 0001 1111 1111 xxxx 1xxx xxxx */ - /* SXTB16 1111 1010 0010 1111 1111 xxxx 1xxx xxxx */ - /* UXTB16 1111 1010 0011 1111 1111 xxxx 1xxx xxxx */ - /* SXTB 1111 1010 0100 1111 1111 xxxx 1xxx xxxx */ - /* UXTB 1111 1010 0101 1111 1111 xxxx 1xxx xxxx */ - DECODE_EMULATEX (0xff8ff080, 0xfa0ff080, t32_emulate_rd8rn16rm0_rwflags, - REGS(0, 0, NOSPPC, 0, NOSPPC)), - - - /* ??? 1111 1010 1xxx xxxx 1111 xxxx 0x11 xxxx */ - DECODE_REJECT (0xff80f0b0, 0xfa80f030), - /* ??? 1111 1010 1x11 xxxx 1111 xxxx 0xxx xxxx */ - DECODE_REJECT (0xffb0f080, 0xfab0f000), - - /* SADD16 1111 1010 1001 xxxx 1111 xxxx 0000 xxxx */ - /* SASX 1111 1010 1010 xxxx 1111 xxxx 0000 xxxx */ - /* SSAX 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx */ - /* SSUB16 1111 1010 1101 xxxx 1111 xxxx 0000 xxxx */ - /* SADD8 1111 1010 1000 xxxx 1111 xxxx 0000 xxxx */ - /* SSUB8 1111 1010 1100 xxxx 1111 xxxx 0000 xxxx */ - - /* QADD16 1111 1010 1001 xxxx 1111 xxxx 0001 xxxx */ - /* QASX 1111 1010 1010 xxxx 1111 xxxx 0001 xxxx */ - /* QSAX 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx */ - /* QSUB16 1111 1010 1101 xxxx 1111 xxxx 0001 xxxx */ - /* QADD8 1111 1010 1000 xxxx 1111 xxxx 0001 xxxx */ - /* QSUB8 1111 1010 1100 xxxx 1111 xxxx 0001 xxxx */ - - /* SHADD16 1111 1010 1001 xxxx 1111 xxxx 0010 xxxx */ - /* SHASX 1111 1010 1010 xxxx 1111 xxxx 0010 xxxx */ - /* SHSAX 1111 1010 1110 xxxx 1111 xxxx 0010 xxxx */ - /* SHSUB16 1111 1010 1101 xxxx 1111 xxxx 0010 xxxx */ - /* SHADD8 1111 1010 1000 xxxx 1111 xxxx 0010 xxxx */ - /* SHSUB8 1111 1010 1100 xxxx 1111 xxxx 0010 xxxx */ - - /* UADD16 1111 1010 1001 xxxx 1111 xxxx 0100 xxxx */ - /* UASX 1111 1010 1010 xxxx 1111 xxxx 0100 xxxx */ - /* USAX 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx */ - /* USUB16 1111 1010 1101 xxxx 1111 xxxx 0100 xxxx */ - /* UADD8 1111 1010 1000 xxxx 1111 xxxx 0100 xxxx */ - /* USUB8 1111 1010 1100 xxxx 1111 xxxx 0100 xxxx */ - - /* UQADD16 1111 1010 1001 xxxx 1111 xxxx 0101 xxxx */ - /* UQASX 1111 1010 1010 xxxx 1111 xxxx 0101 xxxx */ - /* UQSAX 1111 1010 1110 xxxx 1111 xxxx 0101 xxxx */ - /* UQSUB16 1111 1010 1101 xxxx 1111 xxxx 0101 xxxx */ - /* UQADD8 1111 1010 1000 xxxx 1111 xxxx 0101 xxxx */ - /* UQSUB8 1111 1010 1100 xxxx 1111 xxxx 0101 xxxx */ - - /* UHADD16 1111 1010 1001 xxxx 1111 xxxx 0110 xxxx */ - /* UHASX 1111 1010 1010 xxxx 1111 xxxx 0110 xxxx */ - /* UHSAX 1111 1010 1110 xxxx 1111 xxxx 0110 xxxx */ - /* UHSUB16 1111 1010 1101 xxxx 1111 xxxx 0110 xxxx */ - /* UHADD8 1111 1010 1000 xxxx 1111 xxxx 0110 xxxx */ - /* UHSUB8 1111 1010 1100 xxxx 1111 xxxx 0110 xxxx */ - DECODE_OR (0xff80f080, 0xfa80f000), - - /* SXTAH 1111 1010 0000 xxxx 1111 xxxx 1xxx xxxx */ - /* UXTAH 1111 1010 0001 xxxx 1111 xxxx 1xxx xxxx */ - /* SXTAB16 1111 1010 0010 xxxx 1111 xxxx 1xxx xxxx */ - /* UXTAB16 1111 1010 0011 xxxx 1111 xxxx 1xxx xxxx */ - /* SXTAB 1111 1010 0100 xxxx 1111 xxxx 1xxx xxxx */ - /* UXTAB 1111 1010 0101 xxxx 1111 xxxx 1xxx xxxx */ - DECODE_OR (0xff80f080, 0xfa00f080), - - /* QADD 1111 1010 1000 xxxx 1111 xxxx 1000 xxxx */ - /* QDADD 1111 1010 1000 xxxx 1111 xxxx 1001 xxxx */ - /* QSUB 1111 1010 1000 xxxx 1111 xxxx 1010 xxxx */ - /* QDSUB 1111 1010 1000 xxxx 1111 xxxx 1011 xxxx */ - DECODE_OR (0xfff0f0c0, 0xfa80f080), - - /* SEL 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */ - DECODE_OR (0xfff0f0f0, 0xfaa0f080), - - /* LSL 1111 1010 000x xxxx 1111 xxxx 0000 xxxx */ - /* LSR 1111 1010 001x xxxx 1111 xxxx 0000 xxxx */ - /* ASR 1111 1010 010x xxxx 1111 xxxx 0000 xxxx */ - /* ROR 1111 1010 011x xxxx 1111 xxxx 0000 xxxx */ - DECODE_EMULATEX (0xff80f0f0, 0xfa00f000, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)), - - /* CLZ 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */ - DECODE_OR (0xfff0f0f0, 0xfab0f080), - - /* REV 1111 1010 1001 xxxx 1111 xxxx 1000 xxxx */ - /* REV16 1111 1010 1001 xxxx 1111 xxxx 1001 xxxx */ - /* RBIT 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx */ - /* REVSH 1111 1010 1001 xxxx 1111 xxxx 1011 xxxx */ - DECODE_EMULATEX (0xfff0f0c0, 0xfa90f080, t32_emulate_rd8rn16_noflags, - REGS(NOSPPC, 0, NOSPPC, 0, SAMEAS16)), - - /* Other unallocated instructions... */ - DECODE_END -}; - -static const union decode_item t32_table_1111_1011_0[] = { - /* Multiply, multiply accumulate, and absolute difference */ - - /* ??? 1111 1011 0000 xxxx 1111 xxxx 0001 xxxx */ - DECODE_REJECT (0xfff0f0f0, 0xfb00f010), - /* ??? 1111 1011 0111 xxxx 1111 xxxx 0001 xxxx */ - DECODE_REJECT (0xfff0f0f0, 0xfb70f010), - - /* SMULxy 1111 1011 0001 xxxx 1111 xxxx 00xx xxxx */ - DECODE_OR (0xfff0f0c0, 0xfb10f000), - /* MUL 1111 1011 0000 xxxx 1111 xxxx 0000 xxxx */ - /* SMUAD{X} 1111 1011 0010 xxxx 1111 xxxx 000x xxxx */ - /* SMULWy 1111 1011 0011 xxxx 1111 xxxx 000x xxxx */ - /* SMUSD{X} 1111 1011 0100 xxxx 1111 xxxx 000x xxxx */ - /* SMMUL{R} 1111 1011 0101 xxxx 1111 xxxx 000x xxxx */ - /* USAD8 1111 1011 0111 xxxx 1111 xxxx 0000 xxxx */ - DECODE_EMULATEX (0xff80f0e0, 0xfb00f000, t32_emulate_rd8rn16rm0_rwflags, - REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)), - - /* ??? 1111 1011 0111 xxxx xxxx xxxx 0001 xxxx */ - DECODE_REJECT (0xfff000f0, 0xfb700010), - - /* SMLAxy 1111 1011 0001 xxxx xxxx xxxx 00xx xxxx */ - DECODE_OR (0xfff000c0, 0xfb100000), - /* MLA 1111 1011 0000 xxxx xxxx xxxx 0000 xxxx */ - /* MLS 1111 1011 0000 xxxx xxxx xxxx 0001 xxxx */ - /* SMLAD{X} 1111 1011 0010 xxxx xxxx xxxx 000x xxxx */ - /* SMLAWy 1111 1011 0011 xxxx xxxx xxxx 000x xxxx */ - /* SMLSD{X} 1111 1011 0100 xxxx xxxx xxxx 000x xxxx */ - /* SMMLA{R} 1111 1011 0101 xxxx xxxx xxxx 000x xxxx */ - /* SMMLS{R} 1111 1011 0110 xxxx xxxx xxxx 000x xxxx */ - /* USADA8 1111 1011 0111 xxxx xxxx xxxx 0000 xxxx */ - DECODE_EMULATEX (0xff8000c0, 0xfb000000, t32_emulate_rd8rn16rm0ra12_noflags, - REGS(NOSPPC, NOSPPCX, NOSPPC, 0, NOSPPC)), - - /* Other unallocated instructions... */ - DECODE_END -}; - -static const union decode_item t32_table_1111_1011_1[] = { - /* Long multiply, long multiply accumulate, and divide */ - - /* UMAAL 1111 1011 1110 xxxx xxxx xxxx 0110 xxxx */ - DECODE_OR (0xfff000f0, 0xfbe00060), - /* SMLALxy 1111 1011 1100 xxxx xxxx xxxx 10xx xxxx */ - DECODE_OR (0xfff000c0, 0xfbc00080), - /* SMLALD{X} 1111 1011 1100 xxxx xxxx xxxx 110x xxxx */ - /* SMLSLD{X} 1111 1011 1101 xxxx xxxx xxxx 110x xxxx */ - DECODE_OR (0xffe000e0, 0xfbc000c0), - /* SMULL 1111 1011 1000 xxxx xxxx xxxx 0000 xxxx */ - /* UMULL 1111 1011 1010 xxxx xxxx xxxx 0000 xxxx */ - /* SMLAL 1111 1011 1100 xxxx xxxx xxxx 0000 xxxx */ - /* UMLAL 1111 1011 1110 xxxx xxxx xxxx 0000 xxxx */ - DECODE_EMULATEX (0xff9000f0, 0xfb800000, t32_emulate_rdlo12rdhi8rn16rm0_noflags, - REGS(NOSPPC, NOSPPC, NOSPPC, 0, NOSPPC)), - - /* SDIV 1111 1011 1001 xxxx xxxx xxxx 1111 xxxx */ - /* UDIV 1111 1011 1011 xxxx xxxx xxxx 1111 xxxx */ - /* Other unallocated instructions... */ - DECODE_END -}; - -const union decode_item kprobe_decode_thumb32_table[] = { - - /* - * Load/store multiple instructions - * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx), - - /* - * Load/store dual, load/store exclusive, table branch - * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx), - - /* - * Data-processing (shifted register) - * 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xfe000000, 0xea000000, t32_table_1110_101x), - - /* - * Coprocessor instructions - * 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_REJECT (0xfc000000, 0xec000000), - - /* - * Data-processing (modified immediate) - * 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0), - - /* - * Data-processing (plain binary immediate) - * 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0), - - /* - * Branches and miscellaneous control - * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1), - - /* - * Advanced SIMD element or structure load/store instructions - * 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx - */ - DECODE_REJECT (0xff100000, 0xf9000000), - - /* - * Memory hints - * 1111 100x x0x1 xxxx 1111 xxxx xxxx xxxx - */ - DECODE_TABLE (0xfe50f000, 0xf810f000, t32_table_1111_100x_x0x1__1111), - - /* - * Store single data item - * 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx - * Load single data items - * 1111 100x xxx1 xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xfe000000, 0xf8000000, t32_table_1111_100x), - - /* - * Data-processing (register) - * 1111 1010 xxxx xxxx 1111 xxxx xxxx xxxx - */ - DECODE_TABLE (0xff00f000, 0xfa00f000, t32_table_1111_1010___1111), - - /* - * Multiply, multiply accumulate, and absolute difference - * 1111 1011 0xxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xff800000, 0xfb000000, t32_table_1111_1011_0), - - /* - * Long multiply, long multiply accumulate, and divide - * 1111 1011 1xxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_TABLE (0xff800000, 0xfb800000, t32_table_1111_1011_1), - - /* - * Coprocessor instructions - * 1111 11xx xxxx xxxx xxxx xxxx xxxx xxxx - */ - DECODE_END -}; -#ifdef CONFIG_ARM_KPROBES_TEST_MODULE -EXPORT_SYMBOL_GPL(kprobe_decode_thumb32_table); -#endif +/* t16 thumb actions */ static void __kprobes -t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs) +t16_simulate_bxblx(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc + 2; int rm = (insn >> 3) & 0xf; unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm]; if (insn & (1 << 7)) /* BLX ? */ - regs->ARM_lr = (unsigned long)p->addr + 2; + regs->ARM_lr = regs->ARM_pc | 1; bx_write_pc(rmv, regs); } static void __kprobes -t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs) +t16_simulate_ldr_literal(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3); + unsigned long *base = (unsigned long *)((regs->ARM_pc + 2) & ~3); long index = insn & 0xff; int rt = (insn >> 8) & 0x7; regs->uregs[rt] = base[index]; } static void __kprobes -t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs) +t16_simulate_ldrstr_sp_relative(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; unsigned long* base = (unsigned long *)regs->ARM_sp; long index = insn & 0xff; int rt = (insn >> 8) & 0x7; @@ -986,20 +342,20 @@ } static void __kprobes -t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs) +t16_simulate_reladr(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; unsigned long base = (insn & 0x800) ? regs->ARM_sp - : (thumb_probe_pc(p) & ~3); + : ((regs->ARM_pc + 2) & ~3); long offset = insn & 0xff; int rt = (insn >> 8) & 0x7; regs->uregs[rt] = base + offset * 4; } static void __kprobes -t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs) +t16_simulate_add_sp_imm(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; long imm = insn & 0x7f; if (insn & 0x80) /* SUB */ regs->ARM_sp -= imm * 4; @@ -1008,21 +364,22 @@ } static void __kprobes -t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs) +t16_simulate_cbz(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; int rn = insn & 0x7; - kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn; + probes_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn; if (nonzero & 0x800) { long i = insn & 0x200; long imm5 = insn & 0xf8; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc + 2; regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2); } } static void __kprobes -t16_simulate_it(struct kprobe *p, struct pt_regs *regs) +t16_simulate_it(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { /* * The 8 IT state bits are split into two parts in CPSR: @@ -1030,7 +387,6 @@ * ITSTATE<7:2> are in CPSR<15:10> * The new IT state is in the lower byte of insn. */ - kprobe_opcode_t insn = p->opcode; unsigned long cpsr = regs->ARM_cpsr; cpsr &= ~PSR_IT_MASK; cpsr |= (insn & 0xfc) << 8; @@ -1039,50 +395,54 @@ } static void __kprobes -t16_singlestep_it(struct kprobe *p, struct pt_regs *regs) +t16_singlestep_it(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { regs->ARM_pc += 2; - t16_simulate_it(p, regs); + t16_simulate_it(insn, asi, regs); } -static enum kprobe_insn __kprobes -t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static enum probes_insn __kprobes +t16_decode_it(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) { asi->insn_singlestep = t16_singlestep_it; return INSN_GOOD_NO_SLOT; } static void __kprobes -t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs) +t16_simulate_cond_branch(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc + 2; long offset = insn & 0x7f; offset -= insn & 0x80; /* Apply sign bit */ regs->ARM_pc = pc + (offset * 2); } -static enum kprobe_insn __kprobes -t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static enum probes_insn __kprobes +t16_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) { int cc = (insn >> 8) & 0xf; - asi->insn_check_cc = kprobe_condition_checks[cc]; + asi->insn_check_cc = probes_condition_checks[cc]; asi->insn_handler = t16_simulate_cond_branch; return INSN_GOOD_NO_SLOT; } static void __kprobes -t16_simulate_branch(struct kprobe *p, struct pt_regs *regs) +t16_simulate_branch(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc + 2; long offset = insn & 0x3ff; offset -= insn & 0x400; /* Apply sign bit */ regs->ARM_pc = pc + (offset * 2); } static unsigned long __kprobes -t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs) +t16_emulate_loregs(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { unsigned long oldcpsr = regs->ARM_cpsr; unsigned long newcpsr; @@ -1095,7 +455,7 @@ "mrs %[newcpsr], cpsr \n\t" : [newcpsr] "=r" (newcpsr) : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs), - [fn] "r" (p->ainsn.insn_fn) + [fn] "r" (asi->insn_fn) : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "lr", "memory", "cc" ); @@ -1104,24 +464,26 @@ } static void __kprobes -t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs) +t16_emulate_loregs_rwflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - regs->ARM_cpsr = t16_emulate_loregs(p, regs); + regs->ARM_cpsr = t16_emulate_loregs(insn, asi, regs); } static void __kprobes -t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs) +t16_emulate_loregs_noitrwflags(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - unsigned long cpsr = t16_emulate_loregs(p, regs); + unsigned long cpsr = t16_emulate_loregs(insn, asi, regs); if (!in_it_block(cpsr)) regs->ARM_cpsr = cpsr; } static void __kprobes -t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs) +t16_emulate_hiregs(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { - kprobe_opcode_t insn = p->opcode; - unsigned long pc = thumb_probe_pc(p); + unsigned long pc = regs->ARM_pc + 2; int rdn = (insn & 0x7) | ((insn & 0x80) >> 4); int rm = (insn >> 3) & 0xf; @@ -1137,7 +499,7 @@ "blx %[fn] \n\t" "mrs %[cpsr], cpsr \n\t" : "=r" (rdnv), [cpsr] "=r" (cpsr) - : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn) + : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (asi->insn_fn) : "lr", "memory", "cc" ); @@ -1148,18 +510,20 @@ regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); } -static enum kprobe_insn __kprobes -t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static enum probes_insn __kprobes +t16_decode_hiregs(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) { insn &= ~0x00ff; insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */ - ((u16 *)asi->insn)[0] = insn; + ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn); asi->insn_handler = t16_emulate_hiregs; return INSN_GOOD; } static void __kprobes -t16_emulate_push(struct kprobe *p, struct pt_regs *regs) +t16_emulate_push(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { __asm__ __volatile__ ( "ldr r9, [%[regs], #13*4] \n\t" @@ -1168,28 +532,32 @@ "blx %[fn] \n\t" "str r9, [%[regs], #13*4] \n\t" : - : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn) + : [regs] "r" (regs), [fn] "r" (asi->insn_fn) : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "lr", "memory", "cc" ); } -static enum kprobe_insn __kprobes -t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static enum probes_insn __kprobes +t16_decode_push(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) { /* * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}" * and call it with R9=SP and LR in the register list represented * by R8. */ - ((u16 *)asi->insn)[0] = 0xe929; /* 1st half STMDB R9!,{} */ - ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */ + /* 1st half STMDB R9!,{} */ + ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe929); + /* 2nd half (register list) */ + ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff); asi->insn_handler = t16_emulate_push; return INSN_GOOD; } static void __kprobes -t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs) +t16_emulate_pop_nopc(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { __asm__ __volatile__ ( "ldr r9, [%[regs], #13*4] \n\t" @@ -1198,14 +566,15 @@ "stmia %[regs], {r0-r7} \n\t" "str r9, [%[regs], #13*4] \n\t" : - : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn) + : [regs] "r" (regs), [fn] "r" (asi->insn_fn) : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9", "lr", "memory", "cc" ); } static void __kprobes -t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs) +t16_emulate_pop_pc(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) { register unsigned long pc asm("r8"); @@ -1216,7 +585,7 @@ "stmia %[regs], {r0-r7} \n\t" "str r9, [%[regs], #13*4] \n\t" : "=r" (pc) - : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn) + : [regs] "r" (regs), [fn] "r" (asi->insn_fn) : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9", "lr", "memory", "cc" ); @@ -1224,246 +593,74 @@ bx_write_pc(pc, regs); } -static enum kprobe_insn __kprobes -t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static enum probes_insn __kprobes +t16_decode_pop(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) { /* * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}" * and call it with R9=SP and PC in the register list represented * by R8. */ - ((u16 *)asi->insn)[0] = 0xe8b9; /* 1st half LDMIA R9!,{} */ - ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */ + /* 1st half LDMIA R9!,{} */ + ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe8b9); + /* 2nd half (register list) */ + ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff); asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc : t16_emulate_pop_nopc; return INSN_GOOD; } -static const union decode_item t16_table_1011[] = { - /* Miscellaneous 16-bit instructions */ - - /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */ - /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */ - DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm), - - /* CBZ 1011 00x1 xxxx xxxx */ - /* CBNZ 1011 10x1 xxxx xxxx */ - DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz), - - /* SXTH 1011 0010 00xx xxxx */ - /* SXTB 1011 0010 01xx xxxx */ - /* UXTH 1011 0010 10xx xxxx */ - /* UXTB 1011 0010 11xx xxxx */ - /* REV 1011 1010 00xx xxxx */ - /* REV16 1011 1010 01xx xxxx */ - /* ??? 1011 1010 10xx xxxx */ - /* REVSH 1011 1010 11xx xxxx */ - DECODE_REJECT (0xffc0, 0xba80), - DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags), - - /* PUSH 1011 010x xxxx xxxx */ - DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push), - /* POP 1011 110x xxxx xxxx */ - DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop), - - /* - * If-Then, and hints - * 1011 1111 xxxx xxxx - */ - - /* YIELD 1011 1111 0001 0000 */ - DECODE_OR (0xffff, 0xbf10), - /* SEV 1011 1111 0100 0000 */ - DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none), - /* NOP 1011 1111 0000 0000 */ - /* WFE 1011 1111 0010 0000 */ - /* WFI 1011 1111 0011 0000 */ - DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop), - /* Unassigned hints 1011 1111 xxxx 0000 */ - DECODE_REJECT (0xff0f, 0xbf00), - /* IT 1011 1111 xxxx xxxx */ - DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it), - - /* SETEND 1011 0110 010x xxxx */ - /* CPS 1011 0110 011x xxxx */ - /* BKPT 1011 1110 xxxx xxxx */ - /* And unallocated instructions... */ - DECODE_END -}; - -const union decode_item kprobe_decode_thumb16_table[] = { - - /* - * Shift (immediate), add, subtract, move, and compare - * 00xx xxxx xxxx xxxx - */ - - /* CMP (immediate) 0010 1xxx xxxx xxxx */ - DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags), - - /* ADD (register) 0001 100x xxxx xxxx */ - /* SUB (register) 0001 101x xxxx xxxx */ - /* LSL (immediate) 0000 0xxx xxxx xxxx */ - /* LSR (immediate) 0000 1xxx xxxx xxxx */ - /* ASR (immediate) 0001 0xxx xxxx xxxx */ - /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */ - /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */ - /* MOV (immediate) 0010 0xxx xxxx xxxx */ - /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */ - /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */ - DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags), - - /* - * 16-bit Thumb data-processing instructions - * 0100 00xx xxxx xxxx - */ - - /* TST (register) 0100 0010 00xx xxxx */ - DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags), - /* CMP (register) 0100 0010 10xx xxxx */ - /* CMN (register) 0100 0010 11xx xxxx */ - DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags), - /* AND (register) 0100 0000 00xx xxxx */ - /* EOR (register) 0100 0000 01xx xxxx */ - /* LSL (register) 0100 0000 10xx xxxx */ - /* LSR (register) 0100 0000 11xx xxxx */ - /* ASR (register) 0100 0001 00xx xxxx */ - /* ADC (register) 0100 0001 01xx xxxx */ - /* SBC (register) 0100 0001 10xx xxxx */ - /* ROR (register) 0100 0001 11xx xxxx */ - /* RSB (immediate) 0100 0010 01xx xxxx */ - /* ORR (register) 0100 0011 00xx xxxx */ - /* MUL 0100 0011 00xx xxxx */ - /* BIC (register) 0100 0011 10xx xxxx */ - /* MVN (register) 0100 0011 10xx xxxx */ - DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags), - - /* - * Special data instructions and branch and exchange - * 0100 01xx xxxx xxxx - */ - - /* BLX pc 0100 0111 1111 1xxx */ - DECODE_REJECT (0xfff8, 0x47f8), - - /* BX (register) 0100 0111 0xxx xxxx */ - /* BLX (register) 0100 0111 1xxx xxxx */ - DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx), - - /* ADD pc, pc 0100 0100 1111 1111 */ - DECODE_REJECT (0xffff, 0x44ff), - - /* ADD (register) 0100 0100 xxxx xxxx */ - /* CMP (register) 0100 0101 xxxx xxxx */ - /* MOV (register) 0100 0110 xxxx xxxx */ - DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs), - - /* - * Load from Literal Pool - * LDR (literal) 0100 1xxx xxxx xxxx - */ - DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal), - - /* - * 16-bit Thumb Load/store instructions - * 0101 xxxx xxxx xxxx - * 011x xxxx xxxx xxxx - * 100x xxxx xxxx xxxx - */ - - /* STR (register) 0101 000x xxxx xxxx */ - /* STRH (register) 0101 001x xxxx xxxx */ - /* STRB (register) 0101 010x xxxx xxxx */ - /* LDRSB (register) 0101 011x xxxx xxxx */ - /* LDR (register) 0101 100x xxxx xxxx */ - /* LDRH (register) 0101 101x xxxx xxxx */ - /* LDRB (register) 0101 110x xxxx xxxx */ - /* LDRSH (register) 0101 111x xxxx xxxx */ - /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */ - /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */ - /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */ - /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */ - DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags), - /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */ - /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */ - DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags), - /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */ - /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */ - DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative), - - /* - * Generate PC-/SP-relative address - * ADR (literal) 1010 0xxx xxxx xxxx - * ADD (SP plus immediate) 1010 1xxx xxxx xxxx - */ - DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr), - - /* - * Miscellaneous 16-bit instructions - * 1011 xxxx xxxx xxxx - */ - DECODE_TABLE (0xf000, 0xb000, t16_table_1011), - - /* STM 1100 0xxx xxxx xxxx */ - /* LDM 1100 1xxx xxxx xxxx */ - DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags), - - /* - * Conditional branch, and Supervisor Call - */ - - /* Permanently UNDEFINED 1101 1110 xxxx xxxx */ - /* SVC 1101 1111 xxxx xxxx */ - DECODE_REJECT (0xfe00, 0xde00), - - /* Conditional branch 1101 xxxx xxxx xxxx */ - DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch), - - /* - * Unconditional branch - * B 1110 0xxx xxxx xxxx - */ - DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch), - - DECODE_END +const union decode_action kprobes_t16_actions[NUM_PROBES_T16_ACTIONS] = { + [PROBES_T16_ADD_SP] = {.handler = t16_simulate_add_sp_imm}, + [PROBES_T16_CBZ] = {.handler = t16_simulate_cbz}, + [PROBES_T16_SIGN_EXTEND] = {.handler = t16_emulate_loregs_rwflags}, + [PROBES_T16_PUSH] = {.decoder = t16_decode_push}, + [PROBES_T16_POP] = {.decoder = t16_decode_pop}, + [PROBES_T16_SEV] = {.handler = probes_emulate_none}, + [PROBES_T16_WFE] = {.handler = probes_simulate_nop}, + [PROBES_T16_IT] = {.decoder = t16_decode_it}, + [PROBES_T16_CMP] = {.handler = t16_emulate_loregs_rwflags}, + [PROBES_T16_ADDSUB] = {.handler = t16_emulate_loregs_noitrwflags}, + [PROBES_T16_LOGICAL] = {.handler = t16_emulate_loregs_noitrwflags}, + [PROBES_T16_LDR_LIT] = {.handler = t16_simulate_ldr_literal}, + [PROBES_T16_BLX] = {.handler = t16_simulate_bxblx}, + [PROBES_T16_HIREGOPS] = {.decoder = t16_decode_hiregs}, + [PROBES_T16_LDRHSTRH] = {.handler = t16_emulate_loregs_rwflags}, + [PROBES_T16_LDRSTR] = {.handler = t16_simulate_ldrstr_sp_relative}, + [PROBES_T16_ADR] = {.handler = t16_simulate_reladr}, + [PROBES_T16_LDMSTM] = {.handler = t16_emulate_loregs_rwflags}, + [PROBES_T16_BRANCH_COND] = {.decoder = t16_decode_cond_branch}, + [PROBES_T16_BRANCH] = {.handler = t16_simulate_branch}, +}; + +const union decode_action kprobes_t32_actions[NUM_PROBES_T32_ACTIONS] = { + [PROBES_T32_LDMSTM] = {.decoder = t32_decode_ldmstm}, + [PROBES_T32_LDRDSTRD] = {.handler = t32_emulate_ldrdstrd}, + [PROBES_T32_TABLE_BRANCH] = {.handler = t32_simulate_table_branch}, + [PROBES_T32_TST] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_MOV] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_ADDSUB] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_LOGICAL] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_CMP] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_ADDWSUBW_PC] = {.handler = t32_emulate_rd8pc16_noflags,}, + [PROBES_T32_ADDWSUBW] = {.handler = t32_emulate_rd8rn16_noflags}, + [PROBES_T32_MOVW] = {.handler = t32_emulate_rd8rn16_noflags}, + [PROBES_T32_SAT] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_BITFIELD] = {.handler = t32_emulate_rd8rn16_noflags}, + [PROBES_T32_SEV] = {.handler = probes_emulate_none}, + [PROBES_T32_WFE] = {.handler = probes_simulate_nop}, + [PROBES_T32_MRS] = {.handler = t32_simulate_mrs}, + [PROBES_T32_BRANCH_COND] = {.decoder = t32_decode_cond_branch}, + [PROBES_T32_BRANCH] = {.handler = t32_simulate_branch}, + [PROBES_T32_PLDI] = {.handler = probes_simulate_nop}, + [PROBES_T32_LDR_LIT] = {.handler = t32_simulate_ldr_literal}, + [PROBES_T32_LDRSTR] = {.handler = t32_emulate_ldrstr}, + [PROBES_T32_SIGN_EXTEND] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_MEDIA] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_REVERSE] = {.handler = t32_emulate_rd8rn16_noflags}, + [PROBES_T32_MUL_ADD] = {.handler = t32_emulate_rd8rn16rm0_rwflags}, + [PROBES_T32_MUL_ADD2] = {.handler = t32_emulate_rd8rn16rm0ra12_noflags}, + [PROBES_T32_MUL_ADD_LONG] = { + .handler = t32_emulate_rdlo12rdhi8rn16rm0_noflags}, }; -#ifdef CONFIG_ARM_KPROBES_TEST_MODULE -EXPORT_SYMBOL_GPL(kprobe_decode_thumb16_table); -#endif - -static unsigned long __kprobes thumb_check_cc(unsigned long cpsr) -{ - if (unlikely(in_it_block(cpsr))) - return kprobe_condition_checks[current_cond(cpsr)](cpsr); - return true; -} - -static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs) -{ - regs->ARM_pc += 2; - p->ainsn.insn_handler(p, regs); - regs->ARM_cpsr = it_advance(regs->ARM_cpsr); -} - -static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs) -{ - regs->ARM_pc += 4; - p->ainsn.insn_handler(p, regs); - regs->ARM_cpsr = it_advance(regs->ARM_cpsr); -} - -enum kprobe_insn __kprobes -thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi) -{ - asi->insn_singlestep = thumb16_singlestep; - asi->insn_check_cc = thumb_check_cc; - return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true); -} - -enum kprobe_insn __kprobes -thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi) -{ - asi->insn_singlestep = thumb32_singlestep; - asi->insn_check_cc = thumb_check_cc; - return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true); -} diff -Nur linux-3.14.1/arch/arm/kernel/Makefile linux-3.15-rc1.orig/arch/arm/kernel/Makefile --- linux-3.14.1/arch/arm/kernel/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -50,11 +50,12 @@ obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o -obj-$(CONFIG_KPROBES) += kprobes.o kprobes-common.o patch.o +obj-$(CONFIG_UPROBES) += probes.o probes-arm.o uprobes.o uprobes-arm.o +obj-$(CONFIG_KPROBES) += probes.o kprobes.o kprobes-common.o patch.o ifdef CONFIG_THUMB2_KERNEL -obj-$(CONFIG_KPROBES) += kprobes-thumb.o +obj-$(CONFIG_KPROBES) += kprobes-thumb.o probes-thumb.o else -obj-$(CONFIG_KPROBES) += kprobes-arm.o +obj-$(CONFIG_KPROBES) += kprobes-arm.o probes-arm.o endif obj-$(CONFIG_ARM_KPROBES_TEST) += test-kprobes.o test-kprobes-objs := kprobes-test.o diff -Nur linux-3.14.1/arch/arm/kernel/perf_event.c linux-3.15-rc1.orig/arch/arm/kernel/perf_event.c --- linux-3.14.1/arch/arm/kernel/perf_event.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/perf_event.c 2014-04-13 23:18:35.000000000 +0200 @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include @@ -205,6 +207,8 @@ armpmu_stop(event, PERF_EF_UPDATE); hw_events->events[idx] = NULL; clear_bit(idx, hw_events->used_mask); + if (armpmu->clear_event_idx) + armpmu->clear_event_idx(hw_events, event); perf_event_update_userpage(event); } @@ -295,14 +299,27 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) { - struct arm_pmu *armpmu = (struct arm_pmu *) dev; - struct platform_device *plat_device = armpmu->plat_device; - struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); + struct arm_pmu *armpmu; + struct platform_device *plat_device; + struct arm_pmu_platdata *plat; + int ret; + u64 start_clock, finish_clock; + + if (irq_is_percpu(irq)) + dev = *(void **)dev; + armpmu = dev; + plat_device = armpmu->plat_device; + plat = dev_get_platdata(&plat_device->dev); + start_clock = sched_clock(); if (plat && plat->handle_irq) - return plat->handle_irq(irq, dev, armpmu->handle_irq); + ret = plat->handle_irq(irq, dev, armpmu->handle_irq); else - return armpmu->handle_irq(irq, dev); + ret = armpmu->handle_irq(irq, dev); + finish_clock = sched_clock(); + + perf_sample_event_took(finish_clock - start_clock); + return ret; } static void diff -Nur linux-3.14.1/arch/arm/kernel/perf_event_cpu.c linux-3.15-rc1.orig/arch/arm/kernel/perf_event_cpu.c --- linux-3.14.1/arch/arm/kernel/perf_event_cpu.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/perf_event_cpu.c 2014-04-13 23:18:35.000000000 +0200 @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include @@ -33,6 +35,7 @@ /* Set at runtime when we know what CPU type we are. */ static struct arm_pmu *cpu_pmu; +static DEFINE_PER_CPU(struct arm_pmu *, percpu_pmu); static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); @@ -71,6 +74,26 @@ return this_cpu_ptr(&cpu_hw_events); } +static void cpu_pmu_enable_percpu_irq(void *data) +{ + struct arm_pmu *cpu_pmu = data; + struct platform_device *pmu_device = cpu_pmu->plat_device; + int irq = platform_get_irq(pmu_device, 0); + + enable_percpu_irq(irq, IRQ_TYPE_NONE); + cpumask_set_cpu(smp_processor_id(), &cpu_pmu->active_irqs); +} + +static void cpu_pmu_disable_percpu_irq(void *data) +{ + struct arm_pmu *cpu_pmu = data; + struct platform_device *pmu_device = cpu_pmu->plat_device; + int irq = platform_get_irq(pmu_device, 0); + + cpumask_clear_cpu(smp_processor_id(), &cpu_pmu->active_irqs); + disable_percpu_irq(irq); +} + static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu) { int i, irq, irqs; @@ -78,12 +101,18 @@ irqs = min(pmu_device->num_resources, num_possible_cpus()); - for (i = 0; i < irqs; ++i) { - if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs)) - continue; - irq = platform_get_irq(pmu_device, i); - if (irq >= 0) - free_irq(irq, cpu_pmu); + irq = platform_get_irq(pmu_device, 0); + if (irq >= 0 && irq_is_percpu(irq)) { + on_each_cpu(cpu_pmu_disable_percpu_irq, cpu_pmu, 1); + free_percpu_irq(irq, &percpu_pmu); + } else { + for (i = 0; i < irqs; ++i) { + if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs)) + continue; + irq = platform_get_irq(pmu_device, i); + if (irq >= 0) + free_irq(irq, cpu_pmu); + } } } @@ -101,33 +130,44 @@ return -ENODEV; } - for (i = 0; i < irqs; ++i) { - err = 0; - irq = platform_get_irq(pmu_device, i); - if (irq < 0) - continue; - - /* - * If we have a single PMU interrupt that we can't shift, - * assume that we're running on a uniprocessor machine and - * continue. Otherwise, continue without this interrupt. - */ - if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { - pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", - irq, i); - continue; - } - - err = request_irq(irq, handler, - IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu", - cpu_pmu); + irq = platform_get_irq(pmu_device, 0); + if (irq >= 0 && irq_is_percpu(irq)) { + err = request_percpu_irq(irq, handler, "arm-pmu", &percpu_pmu); if (err) { pr_err("unable to request IRQ%d for ARM PMU counters\n", irq); return err; } + on_each_cpu(cpu_pmu_enable_percpu_irq, cpu_pmu, 1); + } else { + for (i = 0; i < irqs; ++i) { + err = 0; + irq = platform_get_irq(pmu_device, i); + if (irq < 0) + continue; + + /* + * If we have a single PMU interrupt that we can't shift, + * assume that we're running on a uniprocessor machine and + * continue. Otherwise, continue without this interrupt. + */ + if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { + pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", + irq, i); + continue; + } + + err = request_irq(irq, handler, + IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu", + cpu_pmu); + if (err) { + pr_err("unable to request IRQ%d for ARM PMU counters\n", + irq); + return err; + } - cpumask_set_cpu(i, &cpu_pmu->active_irqs); + cpumask_set_cpu(i, &cpu_pmu->active_irqs); + } } return 0; @@ -141,6 +181,7 @@ events->events = per_cpu(hw_events, cpu); events->used_mask = per_cpu(used_mask, cpu); raw_spin_lock_init(&events->pmu_lock); + per_cpu(percpu_pmu, cpu) = cpu_pmu; } cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events; @@ -181,6 +222,7 @@ */ static struct of_device_id cpu_pmu_of_device_ids[] = { {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, + {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init}, {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, @@ -188,6 +230,7 @@ {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init}, {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init}, + {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, {}, }; @@ -225,15 +268,6 @@ case ARM_CPU_PART_CORTEX_A9: ret = armv7_a9_pmu_init(pmu); break; - case ARM_CPU_PART_CORTEX_A5: - ret = armv7_a5_pmu_init(pmu); - break; - case ARM_CPU_PART_CORTEX_A15: - ret = armv7_a15_pmu_init(pmu); - break; - case ARM_CPU_PART_CORTEX_A7: - ret = armv7_a7_pmu_init(pmu); - break; } /* Intel CPUs [xscale]. */ } else if (implementor == ARM_CPU_IMP_INTEL) { @@ -270,6 +304,9 @@ return -ENOMEM; } + cpu_pmu = pmu; + cpu_pmu->plat_device = pdev; + if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) { init_fn = of_id->data; ret = init_fn(pmu); @@ -282,8 +319,6 @@ goto out_free; } - cpu_pmu = pmu; - cpu_pmu->plat_device = pdev; cpu_pmu_init(cpu_pmu); ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW); diff -Nur linux-3.14.1/arch/arm/kernel/perf_event_v7.c linux-3.15-rc1.orig/arch/arm/kernel/perf_event_v7.c --- linux-3.14.1/arch/arm/kernel/perf_event_v7.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/perf_event_v7.c 2014-04-13 23:18:35.000000000 +0200 @@ -18,6 +18,10 @@ #ifdef CONFIG_CPU_V7 +#include +#include +#include "../vfp/vfpinstr.h" + /* * Common ARMv7 event types * @@ -109,6 +113,33 @@ ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76, }; +/* ARMv7 Cortex-A12 specific event types */ +enum armv7_a12_perf_types { + ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40, + ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41, + + ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ = 0x50, + ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51, + + ARMV7_A12_PERFCTR_PC_WRITE_SPEC = 0x76, + + ARMV7_A12_PERFCTR_PF_TLB_REFILL = 0xe7, +}; + +/* ARMv7 Krait specific event types */ +enum krait_perf_types { + KRAIT_PMRESR0_GROUP0 = 0xcc, + KRAIT_PMRESR1_GROUP0 = 0xd0, + KRAIT_PMRESR2_GROUP0 = 0xd4, + KRAIT_VPMRESR0_GROUP0 = 0xd8, + + KRAIT_PERFCTR_L1_ICACHE_ACCESS = 0x10011, + KRAIT_PERFCTR_L1_ICACHE_MISS = 0x10010, + + KRAIT_PERFCTR_L1_ITLB_ACCESS = 0x12222, + KRAIT_PERFCTR_L1_DTLB_ACCESS = 0x12210, +}; + /* * Cortex-A8 HW events mapping * @@ -732,6 +763,262 @@ }; /* + * Cortex-A12 HW events mapping + */ +static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, + [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, + [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, + [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC, + [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, +}; + +static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(L1D)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(L1I)] = { + /* + * Not all performance counters differentiate between read + * and write accesses/misses so we're not always strictly + * correct, but it's the best we can do. Writes and reads get + * combined in these cases. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL, + }, + }, + [C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(BPU)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(NODE)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, +}; + +/* + * Krait HW events mapping + */ +static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, + [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, + [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, + [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, +}; + +static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, + [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, + [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, +}; + +static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(L1D)] = { + /* + * The performance counters don't differentiate between read + * and write accesses/misses so this isn't strictly correct, + * but it's the best we can do. Writes and reads get + * combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, + [C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(BPU)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(NODE)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, +}; + +/* * Perf Events' indices */ #define ARMV7_IDX_CYCLE_COUNTER 0 @@ -1212,6 +1499,24 @@ &armv7_a7_perf_cache_map, 0xFF); } +static int armv7_a12_map_event(struct perf_event *event) +{ + return armpmu_map_event(event, &armv7_a12_perf_map, + &armv7_a12_perf_cache_map, 0xFF); +} + +static int krait_map_event(struct perf_event *event) +{ + return armpmu_map_event(event, &krait_perf_map, + &krait_perf_cache_map, 0xFFFFF); +} + +static int krait_map_event_no_branch(struct perf_event *event) +{ + return armpmu_map_event(event, &krait_perf_map_no_branch, + &krait_perf_cache_map, 0xFFFFF); +} + static void armv7pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq = armv7pmu_handle_irq; @@ -1283,6 +1588,408 @@ cpu_pmu->set_event_filter = armv7pmu_set_event_filter; return 0; } + +static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) +{ + armv7pmu_init(cpu_pmu); + cpu_pmu->name = "ARMv7 Cortex-A12"; + cpu_pmu->map_event = armv7_a12_map_event; + cpu_pmu->num_events = armv7_read_num_pmnc_events(); + cpu_pmu->set_event_filter = armv7pmu_set_event_filter; + return 0; +} + +/* + * Krait Performance Monitor Region Event Selection Register (PMRESRn) + * + * 31 30 24 16 8 0 + * +--------------------------------+ + * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0 + * +--------------------------------+ + * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1 + * +--------------------------------+ + * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2 + * +--------------------------------+ + * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ? + * +--------------------------------+ + * EN | G=3 | G=2 | G=1 | G=0 + * + * Event Encoding: + * + * hwc->config_base = 0xNRCCG + * + * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR) + * R = region register + * CC = class of events the group G is choosing from + * G = group or particular event + * + * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2 + * + * A region (R) corresponds to a piece of the CPU (execution unit, instruction + * unit, etc.) while the event code (CC) corresponds to a particular class of + * events (interrupts for example). An event code is broken down into + * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for + * example). + */ + +#define KRAIT_EVENT (1 << 16) +#define VENUM_EVENT (2 << 16) +#define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT) +#define PMRESRn_EN BIT(31) + +static u32 krait_read_pmresrn(int n) +{ + u32 val; + + switch (n) { + case 0: + asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); + break; + case 1: + asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); + break; + case 2: + asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); + break; + default: + BUG(); /* Should be validated in krait_pmu_get_event_idx() */ + } + + return val; +} + +static void krait_write_pmresrn(int n, u32 val) +{ + switch (n) { + case 0: + asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); + break; + case 1: + asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); + break; + case 2: + asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); + break; + default: + BUG(); /* Should be validated in krait_pmu_get_event_idx() */ + } +} + +static u32 krait_read_vpmresr0(void) +{ + u32 val; + asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); + return val; +} + +static void krait_write_vpmresr0(u32 val) +{ + asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); +} + +static void krait_pre_vpmresr0(u32 *venum_orig_val, u32 *fp_orig_val) +{ + u32 venum_new_val; + u32 fp_new_val; + + BUG_ON(preemptible()); + /* CPACR Enable CP10 and CP11 access */ + *venum_orig_val = get_copro_access(); + venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11); + set_copro_access(venum_new_val); + + /* Enable FPEXC */ + *fp_orig_val = fmrx(FPEXC); + fp_new_val = *fp_orig_val | FPEXC_EN; + fmxr(FPEXC, fp_new_val); +} + +static void krait_post_vpmresr0(u32 venum_orig_val, u32 fp_orig_val) +{ + BUG_ON(preemptible()); + /* Restore FPEXC */ + fmxr(FPEXC, fp_orig_val); + isb(); + /* Restore CPACR */ + set_copro_access(venum_orig_val); +} + +static u32 krait_get_pmresrn_event(unsigned int region) +{ + static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0, + KRAIT_PMRESR1_GROUP0, + KRAIT_PMRESR2_GROUP0 }; + return pmresrn_table[region]; +} + +static void krait_evt_setup(int idx, u32 config_base) +{ + u32 val; + u32 mask; + u32 vval, fval; + unsigned int region; + unsigned int group; + unsigned int code; + unsigned int group_shift; + bool venum_event; + + venum_event = !!(config_base & VENUM_EVENT); + region = (config_base >> 12) & 0xf; + code = (config_base >> 4) & 0xff; + group = (config_base >> 0) & 0xf; + + group_shift = group * 8; + mask = 0xff << group_shift; + + /* Configure evtsel for the region and group */ + if (venum_event) + val = KRAIT_VPMRESR0_GROUP0; + else + val = krait_get_pmresrn_event(region); + val += group; + /* Mix in mode-exclusion bits */ + val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); + armv7_pmnc_write_evtsel(idx, val); + + asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); + + if (venum_event) { + krait_pre_vpmresr0(&vval, &fval); + val = krait_read_vpmresr0(); + val &= ~mask; + val |= code << group_shift; + val |= PMRESRn_EN; + krait_write_vpmresr0(val); + krait_post_vpmresr0(vval, fval); + } else { + val = krait_read_pmresrn(region); + val &= ~mask; + val |= code << group_shift; + val |= PMRESRn_EN; + krait_write_pmresrn(region, val); + } +} + +static u32 krait_clear_pmresrn_group(u32 val, int group) +{ + u32 mask; + int group_shift; + + group_shift = group * 8; + mask = 0xff << group_shift; + val &= ~mask; + + /* Don't clear enable bit if entire region isn't disabled */ + if (val & ~PMRESRn_EN) + return val |= PMRESRn_EN; + + return 0; +} + +static void krait_clearpmu(u32 config_base) +{ + u32 val; + u32 vval, fval; + unsigned int region; + unsigned int group; + bool venum_event; + + venum_event = !!(config_base & VENUM_EVENT); + region = (config_base >> 12) & 0xf; + group = (config_base >> 0) & 0xf; + + if (venum_event) { + krait_pre_vpmresr0(&vval, &fval); + val = krait_read_vpmresr0(); + val = krait_clear_pmresrn_group(val, group); + krait_write_vpmresr0(val); + krait_post_vpmresr0(vval, fval); + } else { + val = krait_read_pmresrn(region); + val = krait_clear_pmresrn_group(val, group); + krait_write_pmresrn(region, val); + } +} + +static void krait_pmu_disable_event(struct perf_event *event) +{ + unsigned long flags; + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + + /* Disable counter and interrupt */ + raw_spin_lock_irqsave(&events->pmu_lock, flags); + + /* Disable counter */ + armv7_pmnc_disable_counter(idx); + + /* + * Clear pmresr code (if destined for PMNx counters) + */ + if (hwc->config_base & KRAIT_EVENT_MASK) + krait_clearpmu(hwc->config_base); + + /* Disable interrupt for this counter */ + armv7_pmnc_disable_intens(idx); + + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + +static void krait_pmu_enable_event(struct perf_event *event) +{ + unsigned long flags; + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + + /* + * Enable counter and interrupt, and set the counter to count + * the event that we're interested in. + */ + raw_spin_lock_irqsave(&events->pmu_lock, flags); + + /* Disable counter */ + armv7_pmnc_disable_counter(idx); + + /* + * Set event (if destined for PMNx counters) + * We set the event for the cycle counter because we + * have the ability to perform event filtering. + */ + if (hwc->config_base & KRAIT_EVENT_MASK) + krait_evt_setup(idx, hwc->config_base); + else + armv7_pmnc_write_evtsel(idx, hwc->config_base); + + /* Enable interrupt for this counter */ + armv7_pmnc_enable_intens(idx); + + /* Enable counter */ + armv7_pmnc_enable_counter(idx); + + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + +static void krait_pmu_reset(void *info) +{ + u32 vval, fval; + + armv7pmu_reset(info); + + /* Clear all pmresrs */ + krait_write_pmresrn(0, 0); + krait_write_pmresrn(1, 0); + krait_write_pmresrn(2, 0); + + krait_pre_vpmresr0(&vval, &fval); + krait_write_vpmresr0(0); + krait_post_vpmresr0(vval, fval); +} + +static int krait_event_to_bit(struct perf_event *event, unsigned int region, + unsigned int group) +{ + int bit; + struct hw_perf_event *hwc = &event->hw; + struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); + + if (hwc->config_base & VENUM_EVENT) + bit = KRAIT_VPMRESR0_GROUP0; + else + bit = krait_get_pmresrn_event(region); + bit -= krait_get_pmresrn_event(0); + bit += group; + /* + * Lower bits are reserved for use by the counters (see + * armv7pmu_get_event_idx() for more info) + */ + bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; + + return bit; +} + +/* + * We check for column exclusion constraints here. + * Two events cant use the same group within a pmresr register. + */ +static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + int idx; + int bit; + unsigned int prefix; + unsigned int region; + unsigned int code; + unsigned int group; + bool krait_event; + struct hw_perf_event *hwc = &event->hw; + + region = (hwc->config_base >> 12) & 0xf; + code = (hwc->config_base >> 4) & 0xff; + group = (hwc->config_base >> 0) & 0xf; + krait_event = !!(hwc->config_base & KRAIT_EVENT_MASK); + + if (krait_event) { + /* Ignore invalid events */ + if (group > 3 || region > 2) + return -EINVAL; + prefix = hwc->config_base & KRAIT_EVENT_MASK; + if (prefix != KRAIT_EVENT && prefix != VENUM_EVENT) + return -EINVAL; + if (prefix == VENUM_EVENT && (code & 0xe0)) + return -EINVAL; + + bit = krait_event_to_bit(event, region, group); + if (test_and_set_bit(bit, cpuc->used_mask)) + return -EAGAIN; + } + + idx = armv7pmu_get_event_idx(cpuc, event); + if (idx < 0 && krait_event) + clear_bit(bit, cpuc->used_mask); + + return idx; +} + +static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + int bit; + struct hw_perf_event *hwc = &event->hw; + unsigned int region; + unsigned int group; + bool krait_event; + + region = (hwc->config_base >> 12) & 0xf; + group = (hwc->config_base >> 0) & 0xf; + krait_event = !!(hwc->config_base & KRAIT_EVENT_MASK); + + if (krait_event) { + bit = krait_event_to_bit(event, region, group); + clear_bit(bit, cpuc->used_mask); + } +} + +static int krait_pmu_init(struct arm_pmu *cpu_pmu) +{ + armv7pmu_init(cpu_pmu); + cpu_pmu->name = "ARMv7 Krait"; + /* Some early versions of Krait don't support PC write events */ + if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node, + "qcom,no-pc-write")) + cpu_pmu->map_event = krait_map_event_no_branch; + else + cpu_pmu->map_event = krait_map_event; + cpu_pmu->num_events = armv7_read_num_pmnc_events(); + cpu_pmu->set_event_filter = armv7pmu_set_event_filter; + cpu_pmu->reset = krait_pmu_reset; + cpu_pmu->enable = krait_pmu_enable_event; + cpu_pmu->disable = krait_pmu_disable_event; + cpu_pmu->get_event_idx = krait_pmu_get_event_idx; + cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx; + return 0; +} #else static inline int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) { @@ -1308,4 +2015,14 @@ { return -ENODEV; } + +static inline int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) +{ + return -ENODEV; +} + +static inline int krait_pmu_init(struct arm_pmu *cpu_pmu) +{ + return -ENODEV; +} #endif /* CONFIG_CPU_V7 */ diff -Nur linux-3.14.1/arch/arm/kernel/pj4-cp0.c linux-3.15-rc1.orig/arch/arm/kernel/pj4-cp0.c --- linux-3.14.1/arch/arm/kernel/pj4-cp0.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/pj4-cp0.c 2014-04-13 23:18:35.000000000 +0200 @@ -17,6 +17,7 @@ #include #include #include +#include static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) { @@ -80,6 +81,9 @@ { u32 cp_access; + if (!cpu_is_pj4()) + return 0; + cp_access = pj4_cp_access_read() & ~0xf; pj4_cp_access_write(cp_access); diff -Nur linux-3.14.1/arch/arm/kernel/probes-arm.c linux-3.15-rc1.orig/arch/arm/kernel/probes-arm.c --- linux-3.14.1/arch/arm/kernel/probes-arm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/probes-arm.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,734 @@ +/* + * arch/arm/kernel/probes-arm.c + * + * Some code moved here from arch/arm/kernel/kprobes-arm.c + * + * Copyright (C) 2006, 2007 Motorola Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include +#include + +#include "probes.h" +#include "probes-arm.h" + +#define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit))))) + +#define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25) + +/* + * To avoid the complications of mimicing single-stepping on a + * processor without a Next-PC or a single-step mode, and to + * avoid having to deal with the side-effects of boosting, we + * simulate or emulate (almost) all ARM instructions. + * + * "Simulation" is where the instruction's behavior is duplicated in + * C code. "Emulation" is where the original instruction is rewritten + * and executed, often by altering its registers. + * + * By having all behavior of the kprobe'd instruction completed before + * returning from the kprobe_handler(), all locks (scheduler and + * interrupt) can safely be released. There is no need for secondary + * breakpoints, no race with MP or preemptable kernels, nor having to + * clean up resources counts at a later time impacting overall system + * performance. By rewriting the instruction, only the minimum registers + * need to be loaded and saved back optimizing performance. + * + * Calling the insnslot_*_rwflags version of a function doesn't hurt + * anything even when the CPSR flags aren't updated by the + * instruction. It's just a little slower in return for saving + * a little space by not having a duplicate function that doesn't + * update the flags. (The same optimization can be said for + * instructions that do or don't perform register writeback) + * Also, instructions can either read the flags, only write the + * flags, or read and write the flags. To save combinations + * rather than for sheer performance, flag functions just assume + * read and write of flags. + */ + +void __kprobes simulate_bbl(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) +{ + long iaddr = (long) regs->ARM_pc - 4; + int disp = branch_displacement(insn); + + if (insn & (1 << 24)) + regs->ARM_lr = iaddr + 4; + + regs->ARM_pc = iaddr + 8 + disp; +} + +void __kprobes simulate_blx1(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) +{ + long iaddr = (long) regs->ARM_pc - 4; + int disp = branch_displacement(insn); + + regs->ARM_lr = iaddr + 4; + regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2); + regs->ARM_cpsr |= PSR_T_BIT; +} + +void __kprobes simulate_blx2bx(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) +{ + int rm = insn & 0xf; + long rmv = regs->uregs[rm]; + + if (insn & (1 << 5)) + regs->ARM_lr = (long) regs->ARM_pc; + + regs->ARM_pc = rmv & ~0x1; + regs->ARM_cpsr &= ~PSR_T_BIT; + if (rmv & 0x1) + regs->ARM_cpsr |= PSR_T_BIT; +} + +void __kprobes simulate_mrs(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) +{ + int rd = (insn >> 12) & 0xf; + unsigned long mask = 0xf8ff03df; /* Mask out execution state */ + regs->uregs[rd] = regs->ARM_cpsr & mask; +} + +void __kprobes simulate_mov_ipsp(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) +{ + regs->uregs[12] = regs->uregs[13]; +} + +/* + * For the instruction masking and comparisons in all the "space_*" + * functions below, Do _not_ rearrange the order of tests unless + * you're very, very sure of what you are doing. For the sake of + * efficiency, the masks for some tests sometimes assume other test + * have been done prior to them so the number of patterns to test + * for an instruction set can be as broad as possible to reduce the + * number of tests needed. + */ + +static const union decode_item arm_1111_table[] = { + /* Unconditional instructions */ + + /* memory hint 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */ + /* PLDI (immediate) 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */ + /* PLDW (immediate) 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */ + /* PLD (immediate) 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */ + DECODE_SIMULATE (0xfe300000, 0xf4100000, PROBES_PRELOAD_IMM), + + /* memory hint 1111 0110 x001 xxxx xxxx xxxx xxx0 xxxx */ + /* PLDI (register) 1111 0110 x101 xxxx xxxx xxxx xxx0 xxxx */ + /* PLDW (register) 1111 0111 x001 xxxx xxxx xxxx xxx0 xxxx */ + /* PLD (register) 1111 0111 x101 xxxx xxxx xxxx xxx0 xxxx */ + DECODE_SIMULATE (0xfe300010, 0xf6100000, PROBES_PRELOAD_REG), + + /* BLX (immediate) 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */ + DECODE_SIMULATE (0xfe000000, 0xfa000000, PROBES_BRANCH_IMM), + + /* CPS 1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */ + /* SETEND 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */ + /* SRS 1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */ + /* RFE 1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ + + /* Coprocessor instructions... */ + /* MCRR2 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */ + /* MRRC2 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */ + /* LDC2 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ + /* STC2 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ + /* CDP2 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ + /* MCR2 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ + /* MRC2 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ + + /* Other unallocated instructions... */ + DECODE_END +}; + +static const union decode_item arm_cccc_0001_0xx0____0xxx_table[] = { + /* Miscellaneous instructions */ + + /* MRS cpsr cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */ + DECODE_SIMULATEX(0x0ff000f0, 0x01000000, PROBES_MRS, + REGS(0, NOPC, 0, 0, 0)), + + /* BX cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */ + DECODE_SIMULATE (0x0ff000f0, 0x01200010, PROBES_BRANCH_REG), + + /* BLX (register) cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */ + DECODE_SIMULATEX(0x0ff000f0, 0x01200030, PROBES_BRANCH_REG, + REGS(0, 0, 0, 0, NOPC)), + + /* CLZ cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */ + DECODE_EMULATEX (0x0ff000f0, 0x01600010, PROBES_CLZ, + REGS(0, NOPC, 0, 0, NOPC)), + + /* QADD cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx */ + /* QSUB cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx */ + /* QDADD cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx */ + /* QDSUB cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx */ + DECODE_EMULATEX (0x0f9000f0, 0x01000050, PROBES_SATURATING_ARITHMETIC, + REGS(NOPC, NOPC, 0, 0, NOPC)), + + /* BXJ cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ + /* MSR cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ + /* MRS spsr cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */ + /* BKPT 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ + /* SMC cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */ + /* And unallocated instructions... */ + DECODE_END +}; + +static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = { + /* Halfword multiply and multiply-accumulate */ + + /* SMLALxy cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */ + DECODE_EMULATEX (0x0ff00090, 0x01400080, PROBES_MUL1, + REGS(NOPC, NOPC, NOPC, 0, NOPC)), + + /* SMULWy cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */ + DECODE_OR (0x0ff000b0, 0x012000a0), + /* SMULxy cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */ + DECODE_EMULATEX (0x0ff00090, 0x01600080, PROBES_MUL2, + REGS(NOPC, 0, NOPC, 0, NOPC)), + + /* SMLAxy cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx */ + DECODE_OR (0x0ff00090, 0x01000080), + /* SMLAWy cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx */ + DECODE_EMULATEX (0x0ff000b0, 0x01200080, PROBES_MUL2, + REGS(NOPC, NOPC, NOPC, 0, NOPC)), + + DECODE_END +}; + +static const union decode_item arm_cccc_0000_____1001_table[] = { + /* Multiply and multiply-accumulate */ + + /* MUL cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx */ + /* MULS cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx */ + DECODE_EMULATEX (0x0fe000f0, 0x00000090, PROBES_MUL2, + REGS(NOPC, 0, NOPC, 0, NOPC)), + + /* MLA cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx */ + /* MLAS cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx */ + DECODE_OR (0x0fe000f0, 0x00200090), + /* MLS cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx */ + DECODE_EMULATEX (0x0ff000f0, 0x00600090, PROBES_MUL2, + REGS(NOPC, NOPC, NOPC, 0, NOPC)), + + /* UMAAL cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx */ + DECODE_OR (0x0ff000f0, 0x00400090), + /* UMULL cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx */ + /* UMULLS cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx */ + /* UMLAL cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx */ + /* UMLALS cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx */ + /* SMULL cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx */ + /* SMULLS cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */ + /* SMLAL cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */ + /* SMLALS cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */ + DECODE_EMULATEX (0x0f8000f0, 0x00800090, PROBES_MUL1, + REGS(NOPC, NOPC, NOPC, 0, NOPC)), + + DECODE_END +}; + +static const union decode_item arm_cccc_0001_____1001_table[] = { + /* Synchronization primitives */ + +#if __LINUX_ARM_ARCH__ < 6 + /* Deprecated on ARMv6 and may be UNDEFINED on v7 */ + /* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */ + DECODE_EMULATEX (0x0fb000f0, 0x01000090, PROBES_SWP, + REGS(NOPC, NOPC, 0, 0, NOPC)), +#endif + /* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */ + /* And unallocated instructions... */ + DECODE_END +}; + +static const union decode_item arm_cccc_000x_____1xx1_table[] = { + /* Extra load/store instructions */ + + /* STRHT cccc 0000 xx10 xxxx xxxx xxxx 1011 xxxx */ + /* ??? cccc 0000 xx10 xxxx xxxx xxxx 11x1 xxxx */ + /* LDRHT cccc 0000 xx11 xxxx xxxx xxxx 1011 xxxx */ + /* LDRSBT cccc 0000 xx11 xxxx xxxx xxxx 1101 xxxx */ + /* LDRSHT cccc 0000 xx11 xxxx xxxx xxxx 1111 xxxx */ + DECODE_REJECT (0x0f200090, 0x00200090), + + /* LDRD/STRD lr,pc,{... cccc 000x x0x0 xxxx 111x xxxx 1101 xxxx */ + DECODE_REJECT (0x0e10e0d0, 0x0000e0d0), + + /* LDRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx */ + /* STRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx */ + DECODE_EMULATEX (0x0e5000d0, 0x000000d0, PROBES_LDRSTRD, + REGS(NOPCWB, NOPCX, 0, 0, NOPC)), + + /* LDRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx */ + /* STRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx */ + DECODE_EMULATEX (0x0e5000d0, 0x004000d0, PROBES_LDRSTRD, + REGS(NOPCWB, NOPCX, 0, 0, 0)), + + /* STRH (register) cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx */ + DECODE_EMULATEX (0x0e5000f0, 0x000000b0, PROBES_STORE_EXTRA, + REGS(NOPCWB, NOPC, 0, 0, NOPC)), + + /* LDRH (register) cccc 000x x0x1 xxxx xxxx xxxx 1011 xxxx */ + /* LDRSB (register) cccc 000x x0x1 xxxx xxxx xxxx 1101 xxxx */ + /* LDRSH (register) cccc 000x x0x1 xxxx xxxx xxxx 1111 xxxx */ + DECODE_EMULATEX (0x0e500090, 0x00100090, PROBES_LOAD_EXTRA, + REGS(NOPCWB, NOPC, 0, 0, NOPC)), + + /* STRH (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1011 xxxx */ + DECODE_EMULATEX (0x0e5000f0, 0x004000b0, PROBES_STORE_EXTRA, + REGS(NOPCWB, NOPC, 0, 0, 0)), + + /* LDRH (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1011 xxxx */ + /* LDRSB (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1101 xxxx */ + /* LDRSH (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1111 xxxx */ + DECODE_EMULATEX (0x0e500090, 0x00500090, PROBES_LOAD_EXTRA, + REGS(NOPCWB, NOPC, 0, 0, 0)), + + DECODE_END +}; + +static const union decode_item arm_cccc_000x_table[] = { + /* Data-processing (register) */ + + /* S PC, ... cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */ + DECODE_REJECT (0x0e10f000, 0x0010f000), + + /* MOV IP, SP 1110 0001 1010 0000 1100 0000 0000 1101 */ + DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, PROBES_MOV_IP_SP), + + /* TST (register) cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */ + /* TEQ (register) cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */ + /* CMP (register) cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */ + /* CMN (register) cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */ + DECODE_EMULATEX (0x0f900010, 0x01100000, PROBES_DATA_PROCESSING_REG, + REGS(ANY, 0, 0, 0, ANY)), + + /* MOV (register) cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */ + /* MVN (register) cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */ + DECODE_EMULATEX (0x0fa00010, 0x01a00000, PROBES_DATA_PROCESSING_REG, + REGS(0, ANY, 0, 0, ANY)), + + /* AND (register) cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */ + /* EOR (register) cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */ + /* SUB (register) cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */ + /* RSB (register) cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */ + /* ADD (register) cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */ + /* ADC (register) cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */ + /* SBC (register) cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */ + /* RSC (register) cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */ + /* ORR (register) cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */ + /* BIC (register) cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */ + DECODE_EMULATEX (0x0e000010, 0x00000000, PROBES_DATA_PROCESSING_REG, + REGS(ANY, ANY, 0, 0, ANY)), + + /* TST (reg-shift reg) cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */ + /* TEQ (reg-shift reg) cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */ + /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */ + /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */ + DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG, + REGS(ANY, 0, NOPC, 0, ANY)), + + /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */ + /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */ + DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG, + REGS(0, ANY, NOPC, 0, ANY)), + + /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */ + /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */ + /* SUB (reg-shift reg) cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */ + /* RSB (reg-shift reg) cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */ + /* ADD (reg-shift reg) cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */ + /* ADC (reg-shift reg) cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */ + /* SBC (reg-shift reg) cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */ + /* RSC (reg-shift reg) cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */ + /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */ + /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */ + DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG, + REGS(ANY, ANY, NOPC, 0, ANY)), + + DECODE_END +}; + +static const union decode_item arm_cccc_001x_table[] = { + /* Data-processing (immediate) */ + + /* MOVW cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */ + /* MOVT cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0fb00000, 0x03000000, PROBES_DATA_PROCESSING_IMM, + REGS(0, NOPC, 0, 0, 0)), + + /* YIELD cccc 0011 0010 0000 xxxx xxxx 0000 0001 */ + DECODE_OR (0x0fff00ff, 0x03200001), + /* SEV cccc 0011 0010 0000 xxxx xxxx 0000 0100 */ + DECODE_EMULATE (0x0fff00ff, 0x03200004, PROBES_EMULATE_NONE), + /* NOP cccc 0011 0010 0000 xxxx xxxx 0000 0000 */ + /* WFE cccc 0011 0010 0000 xxxx xxxx 0000 0010 */ + /* WFI cccc 0011 0010 0000 xxxx xxxx 0000 0011 */ + DECODE_SIMULATE (0x0fff00fc, 0x03200000, PROBES_SIMULATE_NOP), + /* DBG cccc 0011 0010 0000 xxxx xxxx ffff xxxx */ + /* unallocated hints cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */ + /* MSR (immediate) cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0x0fb00000, 0x03200000), + + /* S PC, ... cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */ + DECODE_REJECT (0x0e10f000, 0x0210f000), + + /* TST (immediate) cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx */ + /* TEQ (immediate) cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx */ + /* CMP (immediate) cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx */ + /* CMN (immediate) cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0f900000, 0x03100000, PROBES_DATA_PROCESSING_IMM, + REGS(ANY, 0, 0, 0, 0)), + + /* MOV (immediate) cccc 0011 101x xxxx xxxx xxxx xxxx xxxx */ + /* MVN (immediate) cccc 0011 111x xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0fa00000, 0x03a00000, PROBES_DATA_PROCESSING_IMM, + REGS(0, ANY, 0, 0, 0)), + + /* AND (immediate) cccc 0010 000x xxxx xxxx xxxx xxxx xxxx */ + /* EOR (immediate) cccc 0010 001x xxxx xxxx xxxx xxxx xxxx */ + /* SUB (immediate) cccc 0010 010x xxxx xxxx xxxx xxxx xxxx */ + /* RSB (immediate) cccc 0010 011x xxxx xxxx xxxx xxxx xxxx */ + /* ADD (immediate) cccc 0010 100x xxxx xxxx xxxx xxxx xxxx */ + /* ADC (immediate) cccc 0010 101x xxxx xxxx xxxx xxxx xxxx */ + /* SBC (immediate) cccc 0010 110x xxxx xxxx xxxx xxxx xxxx */ + /* RSC (immediate) cccc 0010 111x xxxx xxxx xxxx xxxx xxxx */ + /* ORR (immediate) cccc 0011 100x xxxx xxxx xxxx xxxx xxxx */ + /* BIC (immediate) cccc 0011 110x xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0e000000, 0x02000000, PROBES_DATA_PROCESSING_IMM, + REGS(ANY, ANY, 0, 0, 0)), + + DECODE_END +}; + +static const union decode_item arm_cccc_0110_____xxx1_table[] = { + /* Media instructions */ + + /* SEL cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx */ + DECODE_EMULATEX (0x0ff000f0, 0x068000b0, PROBES_SATURATE, + REGS(NOPC, NOPC, 0, 0, NOPC)), + + /* SSAT cccc 0110 101x xxxx xxxx xxxx xx01 xxxx */ + /* USAT cccc 0110 111x xxxx xxxx xxxx xx01 xxxx */ + DECODE_OR(0x0fa00030, 0x06a00010), + /* SSAT16 cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx */ + /* USAT16 cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx */ + DECODE_EMULATEX (0x0fb000f0, 0x06a00030, PROBES_SATURATE, + REGS(0, NOPC, 0, 0, NOPC)), + + /* REV cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */ + /* REV16 cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */ + /* RBIT cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */ + /* REVSH cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */ + DECODE_EMULATEX (0x0fb00070, 0x06b00030, PROBES_REV, + REGS(0, NOPC, 0, 0, NOPC)), + + /* ??? cccc 0110 0x00 xxxx xxxx xxxx xxx1 xxxx */ + DECODE_REJECT (0x0fb00010, 0x06000010), + /* ??? cccc 0110 0xxx xxxx xxxx xxxx 1011 xxxx */ + DECODE_REJECT (0x0f8000f0, 0x060000b0), + /* ??? cccc 0110 0xxx xxxx xxxx xxxx 1101 xxxx */ + DECODE_REJECT (0x0f8000f0, 0x060000d0), + /* SADD16 cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx */ + /* SADDSUBX cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx */ + /* SSUBADDX cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx */ + /* SSUB16 cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx */ + /* SADD8 cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx */ + /* SSUB8 cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx */ + /* QADD16 cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx */ + /* QADDSUBX cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx */ + /* QSUBADDX cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx */ + /* QSUB16 cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx */ + /* QADD8 cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx */ + /* QSUB8 cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx */ + /* SHADD16 cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx */ + /* SHADDSUBX cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx */ + /* SHSUBADDX cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx */ + /* SHSUB16 cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx */ + /* SHADD8 cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx */ + /* SHSUB8 cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx */ + /* UADD16 cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx */ + /* UADDSUBX cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx */ + /* USUBADDX cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx */ + /* USUB16 cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx */ + /* UADD8 cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx */ + /* USUB8 cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx */ + /* UQADD16 cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx */ + /* UQADDSUBX cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx */ + /* UQSUBADDX cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx */ + /* UQSUB16 cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx */ + /* UQADD8 cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx */ + /* UQSUB8 cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx */ + /* UHADD16 cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx */ + /* UHADDSUBX cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx */ + /* UHSUBADDX cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx */ + /* UHSUB16 cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx */ + /* UHADD8 cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx */ + /* UHSUB8 cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx */ + DECODE_EMULATEX (0x0f800010, 0x06000010, PROBES_MMI, + REGS(NOPC, NOPC, 0, 0, NOPC)), + + /* PKHBT cccc 0110 1000 xxxx xxxx xxxx x001 xxxx */ + /* PKHTB cccc 0110 1000 xxxx xxxx xxxx x101 xxxx */ + DECODE_EMULATEX (0x0ff00030, 0x06800010, PROBES_PACK, + REGS(NOPC, NOPC, 0, 0, NOPC)), + + /* ??? cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx */ + /* ??? cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx */ + DECODE_REJECT (0x0fb000f0, 0x06900070), + + /* SXTB16 cccc 0110 1000 1111 xxxx xxxx 0111 xxxx */ + /* SXTB cccc 0110 1010 1111 xxxx xxxx 0111 xxxx */ + /* SXTH cccc 0110 1011 1111 xxxx xxxx 0111 xxxx */ + /* UXTB16 cccc 0110 1100 1111 xxxx xxxx 0111 xxxx */ + /* UXTB cccc 0110 1110 1111 xxxx xxxx 0111 xxxx */ + /* UXTH cccc 0110 1111 1111 xxxx xxxx 0111 xxxx */ + DECODE_EMULATEX (0x0f8f00f0, 0x068f0070, PROBES_EXTEND, + REGS(0, NOPC, 0, 0, NOPC)), + + /* SXTAB16 cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx */ + /* SXTAB cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx */ + /* SXTAH cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx */ + /* UXTAB16 cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx */ + /* UXTAB cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx */ + /* UXTAH cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx */ + DECODE_EMULATEX (0x0f8000f0, 0x06800070, PROBES_EXTEND_ADD, + REGS(NOPCX, NOPC, 0, 0, NOPC)), + + DECODE_END +}; + +static const union decode_item arm_cccc_0111_____xxx1_table[] = { + /* Media instructions */ + + /* UNDEFINED cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */ + DECODE_REJECT (0x0ff000f0, 0x07f000f0), + + /* SMLALD cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */ + /* SMLSLD cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */ + DECODE_EMULATEX (0x0ff00090, 0x07400010, PROBES_MUL_ADD_LONG, + REGS(NOPC, NOPC, NOPC, 0, NOPC)), + + /* SMUAD cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */ + /* SMUSD cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */ + DECODE_OR (0x0ff0f090, 0x0700f010), + /* SMMUL cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx */ + DECODE_OR (0x0ff0f0d0, 0x0750f010), + /* USAD8 cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */ + DECODE_EMULATEX (0x0ff0f0f0, 0x0780f010, PROBES_MUL_ADD, + REGS(NOPC, 0, NOPC, 0, NOPC)), + + /* SMLAD cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx */ + /* SMLSD cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx */ + DECODE_OR (0x0ff00090, 0x07000010), + /* SMMLA cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx */ + DECODE_OR (0x0ff000d0, 0x07500010), + /* USADA8 cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */ + DECODE_EMULATEX (0x0ff000f0, 0x07800010, PROBES_MUL_ADD, + REGS(NOPC, NOPCX, NOPC, 0, NOPC)), + + /* SMMLS cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx */ + DECODE_EMULATEX (0x0ff000d0, 0x075000d0, PROBES_MUL_ADD, + REGS(NOPC, NOPC, NOPC, 0, NOPC)), + + /* SBFX cccc 0111 101x xxxx xxxx xxxx x101 xxxx */ + /* UBFX cccc 0111 111x xxxx xxxx xxxx x101 xxxx */ + DECODE_EMULATEX (0x0fa00070, 0x07a00050, PROBES_BITFIELD, + REGS(0, NOPC, 0, 0, NOPC)), + + /* BFC cccc 0111 110x xxxx xxxx xxxx x001 1111 */ + DECODE_EMULATEX (0x0fe0007f, 0x07c0001f, PROBES_BITFIELD, + REGS(0, NOPC, 0, 0, 0)), + + /* BFI cccc 0111 110x xxxx xxxx xxxx x001 xxxx */ + DECODE_EMULATEX (0x0fe00070, 0x07c00010, PROBES_BITFIELD, + REGS(0, NOPC, 0, 0, NOPCX)), + + DECODE_END +}; + +static const union decode_item arm_cccc_01xx_table[] = { + /* Load/store word and unsigned byte */ + + /* LDRB/STRB pc,[...] cccc 01xx x0xx xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0x0c40f000, 0x0440f000), + + /* STRT cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */ + /* LDRT cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */ + /* STRBT cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */ + /* LDRBT cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0x0d200000, 0x04200000), + + /* STR (immediate) cccc 010x x0x0 xxxx xxxx xxxx xxxx xxxx */ + /* STRB (immediate) cccc 010x x1x0 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0e100000, 0x04000000, PROBES_STORE, + REGS(NOPCWB, ANY, 0, 0, 0)), + + /* LDR (immediate) cccc 010x x0x1 xxxx xxxx xxxx xxxx xxxx */ + /* LDRB (immediate) cccc 010x x1x1 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0e100000, 0x04100000, PROBES_LOAD, + REGS(NOPCWB, ANY, 0, 0, 0)), + + /* STR (register) cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx */ + /* STRB (register) cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0e100000, 0x06000000, PROBES_STORE, + REGS(NOPCWB, ANY, 0, 0, NOPC)), + + /* LDR (register) cccc 011x x0x1 xxxx xxxx xxxx xxxx xxxx */ + /* LDRB (register) cccc 011x x1x1 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0x0e100000, 0x06100000, PROBES_LOAD, + REGS(NOPCWB, ANY, 0, 0, NOPC)), + + DECODE_END +}; + +static const union decode_item arm_cccc_100x_table[] = { + /* Block data transfer instructions */ + + /* LDM cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ + /* STM cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */ + DECODE_CUSTOM (0x0e400000, 0x08000000, PROBES_LDMSTM), + + /* STM (user registers) cccc 100x x1x0 xxxx xxxx xxxx xxxx xxxx */ + /* LDM (user registers) cccc 100x x1x1 xxxx 0xxx xxxx xxxx xxxx */ + /* LDM (exception ret) cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */ + DECODE_END +}; + +const union decode_item probes_decode_arm_table[] = { + /* + * Unconditional instructions + * 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xf0000000, 0xf0000000, arm_1111_table), + + /* + * Miscellaneous instructions + * cccc 0001 0xx0 xxxx xxxx xxxx 0xxx xxxx + */ + DECODE_TABLE (0x0f900080, 0x01000000, arm_cccc_0001_0xx0____0xxx_table), + + /* + * Halfword multiply and multiply-accumulate + * cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx + */ + DECODE_TABLE (0x0f900090, 0x01000080, arm_cccc_0001_0xx0____1xx0_table), + + /* + * Multiply and multiply-accumulate + * cccc 0000 xxxx xxxx xxxx xxxx 1001 xxxx + */ + DECODE_TABLE (0x0f0000f0, 0x00000090, arm_cccc_0000_____1001_table), + + /* + * Synchronization primitives + * cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx + */ + DECODE_TABLE (0x0f0000f0, 0x01000090, arm_cccc_0001_____1001_table), + + /* + * Extra load/store instructions + * cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx + */ + DECODE_TABLE (0x0e000090, 0x00000090, arm_cccc_000x_____1xx1_table), + + /* + * Data-processing (register) + * cccc 000x xxxx xxxx xxxx xxxx xxx0 xxxx + * Data-processing (register-shifted register) + * cccc 000x xxxx xxxx xxxx xxxx 0xx1 xxxx + */ + DECODE_TABLE (0x0e000000, 0x00000000, arm_cccc_000x_table), + + /* + * Data-processing (immediate) + * cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0x0e000000, 0x02000000, arm_cccc_001x_table), + + /* + * Media instructions + * cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx + */ + DECODE_TABLE (0x0f000010, 0x06000010, arm_cccc_0110_____xxx1_table), + DECODE_TABLE (0x0f000010, 0x07000010, arm_cccc_0111_____xxx1_table), + + /* + * Load/store word and unsigned byte + * cccc 01xx xxxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0x0c000000, 0x04000000, arm_cccc_01xx_table), + + /* + * Block data transfer instructions + * cccc 100x xxxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0x0e000000, 0x08000000, arm_cccc_100x_table), + + /* B cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */ + /* BL cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */ + DECODE_SIMULATE (0x0e000000, 0x0a000000, PROBES_BRANCH), + + /* + * Supervisor Call, and coprocessor instructions + */ + + /* MCRR cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx */ + /* MRRC cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx */ + /* LDC cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ + /* STC cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ + /* CDP cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ + /* MCR cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ + /* MRC cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ + /* SVC cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0x0c000000, 0x0c000000), + + DECODE_END +}; +#ifdef CONFIG_ARM_KPROBES_TEST_MODULE +EXPORT_SYMBOL_GPL(probes_decode_arm_table); +#endif + +static void __kprobes arm_singlestep(probes_opcode_t insn, + struct arch_probes_insn *asi, struct pt_regs *regs) +{ + regs->ARM_pc += 4; + asi->insn_handler(insn, asi, regs); +} + +/* Return: + * INSN_REJECTED If instruction is one not allowed to kprobe, + * INSN_GOOD If instruction is supported and uses instruction slot, + * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot. + * + * For instructions we don't want to kprobe (INSN_REJECTED return result): + * These are generally ones that modify the processor state making + * them "hard" to simulate such as switches processor modes or + * make accesses in alternate modes. Any of these could be simulated + * if the work was put into it, but low return considering they + * should also be very rare. + */ +enum probes_insn __kprobes +arm_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + bool emulate, const union decode_action *actions) +{ + asi->insn_singlestep = arm_singlestep; + asi->insn_check_cc = probes_condition_checks[insn>>28]; + return probes_decode_insn(insn, asi, probes_decode_arm_table, false, + emulate, actions); +} diff -Nur linux-3.14.1/arch/arm/kernel/probes-arm.h linux-3.15-rc1.orig/arch/arm/kernel/probes-arm.h --- linux-3.14.1/arch/arm/kernel/probes-arm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/probes-arm.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,73 @@ +/* + * arch/arm/kernel/probes-arm.h + * + * Copyright 2013 Linaro Ltd. + * Written by: David A. Long + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _ARM_KERNEL_PROBES_ARM_H +#define _ARM_KERNEL_PROBES_ARM_H + +enum probes_arm_action { + PROBES_EMULATE_NONE, + PROBES_SIMULATE_NOP, + PROBES_PRELOAD_IMM, + PROBES_PRELOAD_REG, + PROBES_BRANCH_IMM, + PROBES_BRANCH_REG, + PROBES_MRS, + PROBES_CLZ, + PROBES_SATURATING_ARITHMETIC, + PROBES_MUL1, + PROBES_MUL2, + PROBES_SWP, + PROBES_LDRSTRD, + PROBES_LOAD, + PROBES_STORE, + PROBES_LOAD_EXTRA, + PROBES_STORE_EXTRA, + PROBES_MOV_IP_SP, + PROBES_DATA_PROCESSING_REG, + PROBES_DATA_PROCESSING_IMM, + PROBES_MOV_HALFWORD, + PROBES_SEV, + PROBES_WFE, + PROBES_SATURATE, + PROBES_REV, + PROBES_MMI, + PROBES_PACK, + PROBES_EXTEND, + PROBES_EXTEND_ADD, + PROBES_MUL_ADD_LONG, + PROBES_MUL_ADD, + PROBES_BITFIELD, + PROBES_BRANCH, + PROBES_LDMSTM, + NUM_PROBES_ARM_ACTIONS +}; + +void __kprobes simulate_bbl(probes_opcode_t opcode, + struct arch_probes_insn *asi, struct pt_regs *regs); +void __kprobes simulate_blx1(probes_opcode_t opcode, + struct arch_probes_insn *asi, struct pt_regs *regs); +void __kprobes simulate_blx2bx(probes_opcode_t opcode, + struct arch_probes_insn *asi, struct pt_regs *regs); +void __kprobes simulate_mrs(probes_opcode_t opcode, + struct arch_probes_insn *asi, struct pt_regs *regs); +void __kprobes simulate_mov_ipsp(probes_opcode_t opcode, + struct arch_probes_insn *asi, struct pt_regs *regs); + +extern const union decode_item probes_decode_arm_table[]; + +enum probes_insn arm_probes_decode_insn(probes_opcode_t, + struct arch_probes_insn *, bool emulate, + const union decode_action *actions); + +#endif diff -Nur linux-3.14.1/arch/arm/kernel/probes.c linux-3.15-rc1.orig/arch/arm/kernel/probes.c --- linux-3.14.1/arch/arm/kernel/probes.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/probes.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,456 @@ +/* + * arch/arm/kernel/probes.c + * + * Copyright (C) 2011 Jon Medhurst . + * + * Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is + * Copyright (C) 2006, 2007 Motorola Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "probes.h" + + +#ifndef find_str_pc_offset + +/* + * For STR and STM instructions, an ARM core may choose to use either + * a +8 or a +12 displacement from the current instruction's address. + * Whichever value is chosen for a given core, it must be the same for + * both instructions and may not change. This function measures it. + */ + +int str_pc_offset; + +void __init find_str_pc_offset(void) +{ + int addr, scratch, ret; + + __asm__ ( + "sub %[ret], pc, #4 \n\t" + "str pc, %[addr] \n\t" + "ldr %[scr], %[addr] \n\t" + "sub %[ret], %[scr], %[ret] \n\t" + : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr)); + + str_pc_offset = ret; +} + +#endif /* !find_str_pc_offset */ + + +#ifndef test_load_write_pc_interworking + +bool load_write_pc_interworks; + +void __init test_load_write_pc_interworking(void) +{ + int arch = cpu_architecture(); + BUG_ON(arch == CPU_ARCH_UNKNOWN); + load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T; +} + +#endif /* !test_load_write_pc_interworking */ + + +#ifndef test_alu_write_pc_interworking + +bool alu_write_pc_interworks; + +void __init test_alu_write_pc_interworking(void) +{ + int arch = cpu_architecture(); + BUG_ON(arch == CPU_ARCH_UNKNOWN); + alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7; +} + +#endif /* !test_alu_write_pc_interworking */ + + +void __init arm_probes_decode_init(void) +{ + find_str_pc_offset(); + test_load_write_pc_interworking(); + test_alu_write_pc_interworking(); +} + + +static unsigned long __kprobes __check_eq(unsigned long cpsr) +{ + return cpsr & PSR_Z_BIT; +} + +static unsigned long __kprobes __check_ne(unsigned long cpsr) +{ + return (~cpsr) & PSR_Z_BIT; +} + +static unsigned long __kprobes __check_cs(unsigned long cpsr) +{ + return cpsr & PSR_C_BIT; +} + +static unsigned long __kprobes __check_cc(unsigned long cpsr) +{ + return (~cpsr) & PSR_C_BIT; +} + +static unsigned long __kprobes __check_mi(unsigned long cpsr) +{ + return cpsr & PSR_N_BIT; +} + +static unsigned long __kprobes __check_pl(unsigned long cpsr) +{ + return (~cpsr) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_vs(unsigned long cpsr) +{ + return cpsr & PSR_V_BIT; +} + +static unsigned long __kprobes __check_vc(unsigned long cpsr) +{ + return (~cpsr) & PSR_V_BIT; +} + +static unsigned long __kprobes __check_hi(unsigned long cpsr) +{ + cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return cpsr & PSR_C_BIT; +} + +static unsigned long __kprobes __check_ls(unsigned long cpsr) +{ + cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return (~cpsr) & PSR_C_BIT; +} + +static unsigned long __kprobes __check_ge(unsigned long cpsr) +{ + cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return (~cpsr) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_lt(unsigned long cpsr) +{ + cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return cpsr & PSR_N_BIT; +} + +static unsigned long __kprobes __check_gt(unsigned long cpsr) +{ + unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ + return (~temp) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_le(unsigned long cpsr) +{ + unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ + return temp & PSR_N_BIT; +} + +static unsigned long __kprobes __check_al(unsigned long cpsr) +{ + return true; +} + +probes_check_cc * const probes_condition_checks[16] = { + &__check_eq, &__check_ne, &__check_cs, &__check_cc, + &__check_mi, &__check_pl, &__check_vs, &__check_vc, + &__check_hi, &__check_ls, &__check_ge, &__check_lt, + &__check_gt, &__check_le, &__check_al, &__check_al +}; + + +void __kprobes probes_simulate_nop(probes_opcode_t opcode, + struct arch_probes_insn *asi, + struct pt_regs *regs) +{ +} + +void __kprobes probes_emulate_none(probes_opcode_t opcode, + struct arch_probes_insn *asi, + struct pt_regs *regs) +{ + asi->insn_fn(); +} + +/* + * Prepare an instruction slot to receive an instruction for emulating. + * This is done by placing a subroutine return after the location where the + * instruction will be placed. We also modify ARM instructions to be + * unconditional as the condition code will already be checked before any + * emulation handler is called. + */ +static probes_opcode_t __kprobes +prepare_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + bool thumb) +{ +#ifdef CONFIG_THUMB2_KERNEL + if (thumb) { + u16 *thumb_insn = (u16 *)asi->insn; + /* Thumb bx lr */ + thumb_insn[1] = __opcode_to_mem_thumb16(0x4770); + thumb_insn[2] = __opcode_to_mem_thumb16(0x4770); + return insn; + } + asi->insn[1] = __opcode_to_mem_arm(0xe12fff1e); /* ARM bx lr */ +#else + asi->insn[1] = __opcode_to_mem_arm(0xe1a0f00e); /* mov pc, lr */ +#endif + /* Make an ARM instruction unconditional */ + if (insn < 0xe0000000) + insn = (insn | 0xe0000000) & ~0x10000000; + return insn; +} + +/* + * Write a (probably modified) instruction into the slot previously prepared by + * prepare_emulated_insn + */ +static void __kprobes +set_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + bool thumb) +{ +#ifdef CONFIG_THUMB2_KERNEL + if (thumb) { + u16 *ip = (u16 *)asi->insn; + if (is_wide_instruction(insn)) + *ip++ = __opcode_to_mem_thumb16(insn >> 16); + *ip++ = __opcode_to_mem_thumb16(insn); + return; + } +#endif + asi->insn[0] = __opcode_to_mem_arm(insn); +} + +/* + * When we modify the register numbers encoded in an instruction to be emulated, + * the new values come from this define. For ARM and 32-bit Thumb instructions + * this gives... + * + * bit position 16 12 8 4 0 + * ---------------+---+---+---+---+---+ + * register r2 r0 r1 -- r3 + */ +#define INSN_NEW_BITS 0x00020103 + +/* Each nibble has same value as that at INSN_NEW_BITS bit 16 */ +#define INSN_SAMEAS16_BITS 0x22222222 + +/* + * Validate and modify each of the registers encoded in an instruction. + * + * Each nibble in regs contains a value from enum decode_reg_type. For each + * non-zero value, the corresponding nibble in pinsn is validated and modified + * according to the type. + */ +static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify) +{ + probes_opcode_t insn = *pinsn; + probes_opcode_t mask = 0xf; /* Start at least significant nibble */ + + for (; regs != 0; regs >>= 4, mask <<= 4) { + + probes_opcode_t new_bits = INSN_NEW_BITS; + + switch (regs & 0xf) { + + case REG_TYPE_NONE: + /* Nibble not a register, skip to next */ + continue; + + case REG_TYPE_ANY: + /* Any register is allowed */ + break; + + case REG_TYPE_SAMEAS16: + /* Replace register with same as at bit position 16 */ + new_bits = INSN_SAMEAS16_BITS; + break; + + case REG_TYPE_SP: + /* Only allow SP (R13) */ + if ((insn ^ 0xdddddddd) & mask) + goto reject; + break; + + case REG_TYPE_PC: + /* Only allow PC (R15) */ + if ((insn ^ 0xffffffff) & mask) + goto reject; + break; + + case REG_TYPE_NOSP: + /* Reject SP (R13) */ + if (((insn ^ 0xdddddddd) & mask) == 0) + goto reject; + break; + + case REG_TYPE_NOSPPC: + case REG_TYPE_NOSPPCX: + /* Reject SP and PC (R13 and R15) */ + if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0) + goto reject; + break; + + case REG_TYPE_NOPCWB: + if (!is_writeback(insn)) + break; /* No writeback, so any register is OK */ + /* fall through... */ + case REG_TYPE_NOPC: + case REG_TYPE_NOPCX: + /* Reject PC (R15) */ + if (((insn ^ 0xffffffff) & mask) == 0) + goto reject; + break; + } + + /* Replace value of nibble with new register number... */ + insn &= ~mask; + insn |= new_bits & mask; + } + + if (modify) + *pinsn = insn; + + return true; + +reject: + return false; +} + +static const int decode_struct_sizes[NUM_DECODE_TYPES] = { + [DECODE_TYPE_TABLE] = sizeof(struct decode_table), + [DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom), + [DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate), + [DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate), + [DECODE_TYPE_OR] = sizeof(struct decode_or), + [DECODE_TYPE_REJECT] = sizeof(struct decode_reject) +}; + +/* + * probes_decode_insn operates on data tables in order to decode an ARM + * architecture instruction onto which a kprobe has been placed. + * + * These instruction decoding tables are a concatenation of entries each + * of which consist of one of the following structs: + * + * decode_table + * decode_custom + * decode_simulate + * decode_emulate + * decode_or + * decode_reject + * + * Each of these starts with a struct decode_header which has the following + * fields: + * + * type_regs + * mask + * value + * + * The least significant DECODE_TYPE_BITS of type_regs contains a value + * from enum decode_type, this indicates which of the decode_* structs + * the entry contains. The value DECODE_TYPE_END indicates the end of the + * table. + * + * When the table is parsed, each entry is checked in turn to see if it + * matches the instruction to be decoded using the test: + * + * (insn & mask) == value + * + * If no match is found before the end of the table is reached then decoding + * fails with INSN_REJECTED. + * + * When a match is found, decode_regs() is called to validate and modify each + * of the registers encoded in the instruction; the data it uses to do this + * is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding + * to fail with INSN_REJECTED. + * + * Once the instruction has passed the above tests, further processing + * depends on the type of the table entry's decode struct. + * + */ +int __kprobes +probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + const union decode_item *table, bool thumb, + bool emulate, const union decode_action *actions) +{ + const struct decode_header *h = (struct decode_header *)table; + const struct decode_header *next; + bool matched = false; + + if (emulate) + insn = prepare_emulated_insn(insn, asi, thumb); + + for (;; h = next) { + enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK; + u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS; + + if (type == DECODE_TYPE_END) + return INSN_REJECTED; + + next = (struct decode_header *) + ((uintptr_t)h + decode_struct_sizes[type]); + + if (!matched && (insn & h->mask.bits) != h->value.bits) + continue; + + if (!decode_regs(&insn, regs, emulate)) + return INSN_REJECTED; + + switch (type) { + + case DECODE_TYPE_TABLE: { + struct decode_table *d = (struct decode_table *)h; + next = (struct decode_header *)d->table.table; + break; + } + + case DECODE_TYPE_CUSTOM: { + struct decode_custom *d = (struct decode_custom *)h; + return actions[d->decoder.action].decoder(insn, asi, h); + } + + case DECODE_TYPE_SIMULATE: { + struct decode_simulate *d = (struct decode_simulate *)h; + asi->insn_handler = actions[d->handler.action].handler; + return INSN_GOOD_NO_SLOT; + } + + case DECODE_TYPE_EMULATE: { + struct decode_emulate *d = (struct decode_emulate *)h; + + if (!emulate) + return actions[d->handler.action].decoder(insn, + asi, h); + + asi->insn_handler = actions[d->handler.action].handler; + set_emulated_insn(insn, asi, thumb); + return INSN_GOOD; + } + + case DECODE_TYPE_OR: + matched = true; + break; + + case DECODE_TYPE_REJECT: + default: + return INSN_REJECTED; + } + } +} diff -Nur linux-3.14.1/arch/arm/kernel/probes.h linux-3.15-rc1.orig/arch/arm/kernel/probes.h --- linux-3.14.1/arch/arm/kernel/probes.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/probes.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,407 @@ +/* + * arch/arm/kernel/probes.h + * + * Copyright (C) 2011 Jon Medhurst . + * + * Some contents moved here from arch/arm/include/asm/kprobes.h which is + * Copyright (C) 2006, 2007 Motorola Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef _ARM_KERNEL_PROBES_H +#define _ARM_KERNEL_PROBES_H + +#include +#include +#include + +void __init arm_probes_decode_init(void); + +extern probes_check_cc * const probes_condition_checks[16]; + +#if __LINUX_ARM_ARCH__ >= 7 + +/* str_pc_offset is architecturally defined from ARMv7 onwards */ +#define str_pc_offset 8 +#define find_str_pc_offset() + +#else /* __LINUX_ARM_ARCH__ < 7 */ + +/* We need a run-time check to determine str_pc_offset */ +extern int str_pc_offset; +void __init find_str_pc_offset(void); + +#endif + + +/* + * Update ITSTATE after normal execution of an IT block instruction. + * + * The 8 IT state bits are split into two parts in CPSR: + * ITSTATE<1:0> are in CPSR<26:25> + * ITSTATE<7:2> are in CPSR<15:10> + */ +static inline unsigned long it_advance(unsigned long cpsr) + { + if ((cpsr & 0x06000400) == 0) { + /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */ + cpsr &= ~PSR_IT_MASK; + } else { + /* We need to shift left ITSTATE<4:0> */ + const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */ + unsigned long it = cpsr & mask; + it <<= 1; + it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */ + it &= mask; + cpsr &= ~mask; + cpsr |= it; + } + return cpsr; +} + +static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs) +{ + long cpsr = regs->ARM_cpsr; + if (pcv & 0x1) { + cpsr |= PSR_T_BIT; + pcv &= ~0x1; + } else { + cpsr &= ~PSR_T_BIT; + pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */ + } + regs->ARM_cpsr = cpsr; + regs->ARM_pc = pcv; +} + + +#if __LINUX_ARM_ARCH__ >= 6 + +/* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */ +#define load_write_pc_interworks true +#define test_load_write_pc_interworking() + +#else /* __LINUX_ARM_ARCH__ < 6 */ + +/* We need run-time testing to determine if load_write_pc() should interwork. */ +extern bool load_write_pc_interworks; +void __init test_load_write_pc_interworking(void); + +#endif + +static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs) +{ + if (load_write_pc_interworks) + bx_write_pc(pcv, regs); + else + regs->ARM_pc = pcv; +} + + +#if __LINUX_ARM_ARCH__ >= 7 + +#define alu_write_pc_interworks true +#define test_alu_write_pc_interworking() + +#elif __LINUX_ARM_ARCH__ <= 5 + +/* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */ +#define alu_write_pc_interworks false +#define test_alu_write_pc_interworking() + +#else /* __LINUX_ARM_ARCH__ == 6 */ + +/* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */ +extern bool alu_write_pc_interworks; +void __init test_alu_write_pc_interworking(void); + +#endif /* __LINUX_ARM_ARCH__ == 6 */ + +static inline void __kprobes alu_write_pc(long pcv, struct pt_regs *regs) +{ + if (alu_write_pc_interworks) + bx_write_pc(pcv, regs); + else + regs->ARM_pc = pcv; +} + + +/* + * Test if load/store instructions writeback the address register. + * if P (bit 24) == 0 or W (bit 21) == 1 + */ +#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000) + +/* + * The following definitions and macros are used to build instruction + * decoding tables for use by probes_decode_insn. + * + * These tables are a concatenation of entries each of which consist of one of + * the decode_* structs. All of the fields in every type of decode structure + * are of the union type decode_item, therefore the entire decode table can be + * viewed as an array of these and declared like: + * + * static const union decode_item table_name[] = {}; + * + * In order to construct each entry in the table, macros are used to + * initialise a number of sequential decode_item values in a layout which + * matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct + * decode_simulate by initialising four decode_item objects like this... + * + * {.bits = _type}, + * {.bits = _mask}, + * {.bits = _value}, + * {.action = _handler}, + * + * Initialising a specified member of the union means that the compiler + * will produce a warning if the argument is of an incorrect type. + * + * Below is a list of each of the macros used to initialise entries and a + * description of the action performed when that entry is matched to an + * instruction. A match is found when (instruction & mask) == value. + * + * DECODE_TABLE(mask, value, table) + * Instruction decoding jumps to parsing the new sub-table 'table'. + * + * DECODE_CUSTOM(mask, value, decoder) + * The value of 'decoder' is used as an index into the array of + * action functions, and the retrieved decoder function is invoked + * to complete decoding of the instruction. + * + * DECODE_SIMULATE(mask, value, handler) + * The probes instruction handler is set to the value found by + * indexing into the action array using the value of 'handler'. This + * will be used to simulate the instruction when the probe is hit. + * Decoding returns with INSN_GOOD_NO_SLOT. + * + * DECODE_EMULATE(mask, value, handler) + * The probes instruction handler is set to the value found by + * indexing into the action array using the value of 'handler'. This + * will be used to emulate the instruction when the probe is hit. The + * modified instruction (see below) is placed in the probes instruction + * slot so it may be called by the emulation code. Decoding returns + * with INSN_GOOD. + * + * DECODE_REJECT(mask, value) + * Instruction decoding fails with INSN_REJECTED + * + * DECODE_OR(mask, value) + * This allows the mask/value test of multiple table entries to be + * logically ORed. Once an 'or' entry is matched the decoding action to + * be performed is that of the next entry which isn't an 'or'. E.g. + * + * DECODE_OR (mask1, value1) + * DECODE_OR (mask2, value2) + * DECODE_SIMULATE (mask3, value3, simulation_handler) + * + * This means that if any of the three mask/value pairs match the + * instruction being decoded, then 'simulation_handler' will be used + * for it. + * + * Both the SIMULATE and EMULATE macros have a second form which take an + * additional 'regs' argument. + * + * DECODE_SIMULATEX(mask, value, handler, regs) + * DECODE_EMULATEX (mask, value, handler, regs) + * + * These are used to specify what kind of CPU register is encoded in each of the + * least significant 5 nibbles of the instruction being decoded. The regs value + * is specified using the REGS macro, this takes any of the REG_TYPE_* values + * from enum decode_reg_type as arguments; only the '*' part of the name is + * given. E.g. + * + * REGS(0, ANY, NOPC, 0, ANY) + * + * This indicates an instruction is encoded like: + * + * bits 19..16 ignore + * bits 15..12 any register allowed here + * bits 11.. 8 any register except PC allowed here + * bits 7.. 4 ignore + * bits 3.. 0 any register allowed here + * + * This register specification is checked after a decode table entry is found to + * match an instruction (through the mask/value test). Any invalid register then + * found in the instruction will cause decoding to fail with INSN_REJECTED. In + * the above example this would happen if bits 11..8 of the instruction were + * 1111, indicating R15 or PC. + * + * As well as checking for legal combinations of registers, this data is also + * used to modify the registers encoded in the instructions so that an + * emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.) + * + * Here is a real example which matches ARM instructions of the form + * "AND ,,, " + * + * DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG, + * REGS(ANY, ANY, NOPC, 0, ANY)), + * ^ ^ ^ ^ + * Rn Rd Rs Rm + * + * Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because + * Rs == R15 + * + * Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the + * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into + * the kprobes instruction slot. This can then be called later by the handler + * function emulate_rd12rn16rm0rs8_rwflags (a pointer to which is retrieved from + * the indicated slot in the action array), in order to simulate the instruction. + */ + +enum decode_type { + DECODE_TYPE_END, + DECODE_TYPE_TABLE, + DECODE_TYPE_CUSTOM, + DECODE_TYPE_SIMULATE, + DECODE_TYPE_EMULATE, + DECODE_TYPE_OR, + DECODE_TYPE_REJECT, + NUM_DECODE_TYPES /* Must be last enum */ +}; + +#define DECODE_TYPE_BITS 4 +#define DECODE_TYPE_MASK ((1 << DECODE_TYPE_BITS) - 1) + +enum decode_reg_type { + REG_TYPE_NONE = 0, /* Not a register, ignore */ + REG_TYPE_ANY, /* Any register allowed */ + REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */ + REG_TYPE_SP, /* Register must be SP */ + REG_TYPE_PC, /* Register must be PC */ + REG_TYPE_NOSP, /* Register must not be SP */ + REG_TYPE_NOSPPC, /* Register must not be SP or PC */ + REG_TYPE_NOPC, /* Register must not be PC */ + REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */ + + /* The following types are used when the encoding for PC indicates + * another instruction form. This distiction only matters for test + * case coverage checks. + */ + REG_TYPE_NOPCX, /* Register must not be PC */ + REG_TYPE_NOSPPCX, /* Register must not be SP or PC */ + + /* Alias to allow '0' arg to be used in REGS macro. */ + REG_TYPE_0 = REG_TYPE_NONE +}; + +#define REGS(r16, r12, r8, r4, r0) \ + (((REG_TYPE_##r16) << 16) + \ + ((REG_TYPE_##r12) << 12) + \ + ((REG_TYPE_##r8) << 8) + \ + ((REG_TYPE_##r4) << 4) + \ + (REG_TYPE_##r0)) + +union decode_item { + u32 bits; + const union decode_item *table; + int action; +}; + +struct decode_header; +typedef enum probes_insn (probes_custom_decode_t)(probes_opcode_t, + struct arch_probes_insn *, + const struct decode_header *); + +union decode_action { + probes_insn_handler_t *handler; + probes_custom_decode_t *decoder; +}; + +#define DECODE_END \ + {.bits = DECODE_TYPE_END} + + +struct decode_header { + union decode_item type_regs; + union decode_item mask; + union decode_item value; +}; + +#define DECODE_HEADER(_type, _mask, _value, _regs) \ + {.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)}, \ + {.bits = (_mask)}, \ + {.bits = (_value)} + + +struct decode_table { + struct decode_header header; + union decode_item table; +}; + +#define DECODE_TABLE(_mask, _value, _table) \ + DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0), \ + {.table = (_table)} + + +struct decode_custom { + struct decode_header header; + union decode_item decoder; +}; + +#define DECODE_CUSTOM(_mask, _value, _decoder) \ + DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0), \ + {.action = (_decoder)} + + +struct decode_simulate { + struct decode_header header; + union decode_item handler; +}; + +#define DECODE_SIMULATEX(_mask, _value, _handler, _regs) \ + DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs), \ + {.action = (_handler)} + +#define DECODE_SIMULATE(_mask, _value, _handler) \ + DECODE_SIMULATEX(_mask, _value, _handler, 0) + + +struct decode_emulate { + struct decode_header header; + union decode_item handler; +}; + +#define DECODE_EMULATEX(_mask, _value, _handler, _regs) \ + DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs), \ + {.action = (_handler)} + +#define DECODE_EMULATE(_mask, _value, _handler) \ + DECODE_EMULATEX(_mask, _value, _handler, 0) + + +struct decode_or { + struct decode_header header; +}; + +#define DECODE_OR(_mask, _value) \ + DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0) + +enum probes_insn { + INSN_REJECTED, + INSN_GOOD, + INSN_GOOD_NO_SLOT +}; + +struct decode_reject { + struct decode_header header; +}; + +#define DECODE_REJECT(_mask, _value) \ + DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0) + +probes_insn_handler_t probes_simulate_nop; +probes_insn_handler_t probes_emulate_none; + +int __kprobes +probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + const union decode_item *table, bool thumb, bool emulate, + const union decode_action *actions); + +#endif diff -Nur linux-3.14.1/arch/arm/kernel/probes-thumb.c linux-3.15-rc1.orig/arch/arm/kernel/probes-thumb.c --- linux-3.14.1/arch/arm/kernel/probes-thumb.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/probes-thumb.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,882 @@ +/* + * arch/arm/kernel/probes-thumb.c + * + * Copyright (C) 2011 Jon Medhurst . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include "probes.h" +#include "probes-thumb.h" + + +static const union decode_item t32_table_1110_100x_x0xx[] = { + /* Load/store multiple instructions */ + + /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfe4f0000, 0xe80f0000), + + /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */ + /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xffc00000, 0xe8000000), + /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */ + /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xffc00000, 0xe9800000), + + /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfe508000, 0xe8008000), + /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */ + DECODE_REJECT (0xfe50c000, 0xe810c000), + /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */ + DECODE_REJECT (0xfe402000, 0xe8002000), + + /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */ + /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */ + /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */ + /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */ + DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM), + + DECODE_END +}; + +static const union decode_item t32_table_1110_100x_x1xx[] = { + /* Load/store dual, load/store exclusive, table branch */ + + /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */ + /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */ + DECODE_OR (0xff600000, 0xe8600000), + /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */ + /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD, + REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)), + + /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */ + /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */ + DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, PROBES_T32_TABLE_BRANCH, + REGS(NOSP, 0, 0, 0, NOSPPC)), + + /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */ + /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */ + /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */ + /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */ + /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */ + /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */ + /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */ + /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */ + /* And unallocated instructions... */ + DECODE_END +}; + +static const union decode_item t32_table_1110_101x[] = { + /* Data-processing (shifted register) */ + + /* TST 1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */ + /* TEQ 1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */ + DECODE_EMULATEX (0xff700f00, 0xea100f00, PROBES_T32_TST, + REGS(NOSPPC, 0, 0, 0, NOSPPC)), + + /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */ + DECODE_OR (0xfff00f00, 0xeb100f00), + /* CMP 1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */ + DECODE_EMULATEX (0xfff00f00, 0xebb00f00, PROBES_T32_TST, + REGS(NOPC, 0, 0, 0, NOSPPC)), + + /* MOV 1110 1010 010x 1111 xxxx xxxx xxxx xxxx */ + /* MVN 1110 1010 011x 1111 xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xffcf0000, 0xea4f0000, PROBES_T32_MOV, + REGS(0, 0, NOSPPC, 0, NOSPPC)), + + /* ??? 1110 1010 101x xxxx xxxx xxxx xxxx xxxx */ + /* ??? 1110 1010 111x xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xffa00000, 0xeaa00000), + /* ??? 1110 1011 001x xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xffe00000, 0xeb200000), + /* ??? 1110 1011 100x xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xffe00000, 0xeb800000), + /* ??? 1110 1011 111x xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xffe00000, 0xebe00000), + + /* ADD/SUB SP, SP, Rm, LSL #0..3 */ + /* 1110 1011 x0xx 1101 x000 1101 xx00 xxxx */ + DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, PROBES_T32_ADDSUB, + REGS(SP, 0, SP, 0, NOSPPC)), + + /* ADD/SUB SP, SP, Rm, shift */ + /* 1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */ + DECODE_REJECT (0xff4f0f00, 0xeb0d0d00), + + /* ADD/SUB Rd, SP, Rm, shift */ + /* 1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, PROBES_T32_ADDSUB, + REGS(SP, 0, NOPC, 0, NOSPPC)), + + /* AND 1110 1010 000x xxxx xxxx xxxx xxxx xxxx */ + /* BIC 1110 1010 001x xxxx xxxx xxxx xxxx xxxx */ + /* ORR 1110 1010 010x xxxx xxxx xxxx xxxx xxxx */ + /* ORN 1110 1010 011x xxxx xxxx xxxx xxxx xxxx */ + /* EOR 1110 1010 100x xxxx xxxx xxxx xxxx xxxx */ + /* PKH 1110 1010 110x xxxx xxxx xxxx xxxx xxxx */ + /* ADD 1110 1011 000x xxxx xxxx xxxx xxxx xxxx */ + /* ADC 1110 1011 010x xxxx xxxx xxxx xxxx xxxx */ + /* SBC 1110 1011 011x xxxx xxxx xxxx xxxx xxxx */ + /* SUB 1110 1011 101x xxxx xxxx xxxx xxxx xxxx */ + /* RSB 1110 1011 110x xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfe000000, 0xea000000, PROBES_T32_LOGICAL, + REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)), + + DECODE_END +}; + +static const union decode_item t32_table_1111_0x0x___0[] = { + /* Data-processing (modified immediate) */ + + /* TST 1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */ + /* TEQ 1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */ + DECODE_EMULATEX (0xfb708f00, 0xf0100f00, PROBES_T32_TST, + REGS(NOSPPC, 0, 0, 0, 0)), + + /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */ + DECODE_OR (0xfbf08f00, 0xf1100f00), + /* CMP 1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */ + DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, PROBES_T32_CMP, + REGS(NOPC, 0, 0, 0, 0)), + + /* MOV 1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */ + /* MVN 1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, PROBES_T32_MOV, + REGS(0, 0, NOSPPC, 0, 0)), + + /* ??? 1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfbe08000, 0xf0a00000), + /* ??? 1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */ + /* ??? 1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfbc08000, 0xf0c00000), + /* ??? 1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfbe08000, 0xf1200000), + /* ??? 1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfbe08000, 0xf1800000), + /* ??? 1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfbe08000, 0xf1e00000), + + /* ADD Rd, SP, #imm 1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */ + /* SUB Rd, SP, #imm 1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, PROBES_T32_ADDSUB, + REGS(SP, 0, NOPC, 0, 0)), + + /* AND 1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */ + /* BIC 1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */ + /* ORR 1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */ + /* ORN 1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */ + /* EOR 1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */ + /* ADD 1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */ + /* ADC 1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */ + /* SBC 1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */ + /* SUB 1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */ + /* RSB 1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfa008000, 0xf0000000, PROBES_T32_LOGICAL, + REGS(NOSPPC, 0, NOSPPC, 0, 0)), + + DECODE_END +}; + +static const union decode_item t32_table_1111_0x1x___0[] = { + /* Data-processing (plain binary immediate) */ + + /* ADDW Rd, PC, #imm 1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */ + DECODE_OR (0xfbff8000, 0xf20f0000), + /* SUBW Rd, PC, #imm 1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfbff8000, 0xf2af0000, PROBES_T32_ADDWSUBW_PC, + REGS(PC, 0, NOSPPC, 0, 0)), + + /* ADDW SP, SP, #imm 1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */ + DECODE_OR (0xfbff8f00, 0xf20d0d00), + /* SUBW SP, SP, #imm 1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */ + DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, PROBES_T32_ADDWSUBW, + REGS(SP, 0, SP, 0, 0)), + + /* ADDW 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */ + DECODE_OR (0xfbf08000, 0xf2000000), + /* SUBW 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfbf08000, 0xf2a00000, PROBES_T32_ADDWSUBW, + REGS(NOPCX, 0, NOSPPC, 0, 0)), + + /* MOVW 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */ + /* MOVT 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfb708000, 0xf2400000, PROBES_T32_MOVW, + REGS(0, 0, NOSPPC, 0, 0)), + + /* SSAT16 1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */ + /* SSAT 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */ + /* USAT16 1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */ + /* USAT 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfb508000, 0xf3000000, PROBES_T32_SAT, + REGS(NOSPPC, 0, NOSPPC, 0, 0)), + + /* SFBX 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */ + /* UFBX 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfb708000, 0xf3400000, PROBES_T32_BITFIELD, + REGS(NOSPPC, 0, NOSPPC, 0, 0)), + + /* BFC 1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfbff8000, 0xf36f0000, PROBES_T32_BITFIELD, + REGS(0, 0, NOSPPC, 0, 0)), + + /* BFI 1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfbf08000, 0xf3600000, PROBES_T32_BITFIELD, + REGS(NOSPPCX, 0, NOSPPC, 0, 0)), + + DECODE_END +}; + +static const union decode_item t32_table_1111_0xxx___1[] = { + /* Branches and miscellaneous control */ + + /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */ + DECODE_OR (0xfff0d7ff, 0xf3a08001), + /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */ + DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, PROBES_T32_SEV), + /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */ + /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */ + /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */ + DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, PROBES_T32_WFE), + + /* MRS Rd, CPSR 1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */ + DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, PROBES_T32_MRS, + REGS(0, 0, NOSPPC, 0, 0)), + + /* + * Unsupported instructions + * 1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx + * + * MSR 1111 0011 100x xxxx 10x0 xxxx xxxx xxxx + * DBG hint 1111 0011 1010 xxxx 10x0 x000 1111 xxxx + * Unallocated hints 1111 0011 1010 xxxx 10x0 x000 xxxx xxxx + * CPS 1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx + * CLREX/DSB/DMB/ISB 1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx + * BXJ 1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx + * SUBS PC,LR,# 1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx + * MRS Rd, SPSR 1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx + * SMC 1111 0111 1111 xxxx 1000 xxxx xxxx xxxx + * UNDEFINED 1111 0111 1111 xxxx 1010 xxxx xxxx xxxx + * ??? 1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx + */ + DECODE_REJECT (0xfb80d000, 0xf3808000), + + /* Bcc 1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */ + DECODE_CUSTOM (0xf800d000, 0xf0008000, PROBES_T32_BRANCH_COND), + + /* BLX 1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */ + DECODE_OR (0xf800d001, 0xf000c000), + /* B 1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */ + /* BL 1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */ + DECODE_SIMULATE (0xf8009000, 0xf0009000, PROBES_T32_BRANCH), + + DECODE_END +}; + +static const union decode_item t32_table_1111_100x_x0x1__1111[] = { + /* Memory hints */ + + /* PLD (literal) 1111 1000 x001 1111 1111 xxxx xxxx xxxx */ + /* PLI (literal) 1111 1001 x001 1111 1111 xxxx xxxx xxxx */ + DECODE_SIMULATE (0xfe7ff000, 0xf81ff000, PROBES_T32_PLDI), + + /* PLD{W} (immediate) 1111 1000 10x1 xxxx 1111 xxxx xxxx xxxx */ + DECODE_OR (0xffd0f000, 0xf890f000), + /* PLD{W} (immediate) 1111 1000 00x1 xxxx 1111 1100 xxxx xxxx */ + DECODE_OR (0xffd0ff00, 0xf810fc00), + /* PLI (immediate) 1111 1001 1001 xxxx 1111 xxxx xxxx xxxx */ + DECODE_OR (0xfff0f000, 0xf990f000), + /* PLI (immediate) 1111 1001 0001 xxxx 1111 1100 xxxx xxxx */ + DECODE_SIMULATEX(0xfff0ff00, 0xf910fc00, PROBES_T32_PLDI, + REGS(NOPCX, 0, 0, 0, 0)), + + /* PLD{W} (register) 1111 1000 00x1 xxxx 1111 0000 00xx xxxx */ + DECODE_OR (0xffd0ffc0, 0xf810f000), + /* PLI (register) 1111 1001 0001 xxxx 1111 0000 00xx xxxx */ + DECODE_SIMULATEX(0xfff0ffc0, 0xf910f000, PROBES_T32_PLDI, + REGS(NOPCX, 0, 0, 0, NOSPPC)), + + /* Other unallocated instructions... */ + DECODE_END +}; + +static const union decode_item t32_table_1111_100x[] = { + /* Store/Load single data item */ + + /* ??? 1111 100x x11x xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfe600000, 0xf8600000), + + /* ??? 1111 1001 0101 xxxx xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xfff00000, 0xf9500000), + + /* ??? 1111 100x 0xxx xxxx xxxx 10x0 xxxx xxxx */ + DECODE_REJECT (0xfe800d00, 0xf8000800), + + /* STRBT 1111 1000 0000 xxxx xxxx 1110 xxxx xxxx */ + /* STRHT 1111 1000 0010 xxxx xxxx 1110 xxxx xxxx */ + /* STRT 1111 1000 0100 xxxx xxxx 1110 xxxx xxxx */ + /* LDRBT 1111 1000 0001 xxxx xxxx 1110 xxxx xxxx */ + /* LDRSBT 1111 1001 0001 xxxx xxxx 1110 xxxx xxxx */ + /* LDRHT 1111 1000 0011 xxxx xxxx 1110 xxxx xxxx */ + /* LDRSHT 1111 1001 0011 xxxx xxxx 1110 xxxx xxxx */ + /* LDRT 1111 1000 0101 xxxx xxxx 1110 xxxx xxxx */ + DECODE_REJECT (0xfe800f00, 0xf8000e00), + + /* STR{,B,H} Rn,[PC...] 1111 1000 xxx0 1111 xxxx xxxx xxxx xxxx */ + DECODE_REJECT (0xff1f0000, 0xf80f0000), + + /* STR{,B,H} PC,[Rn...] 1111 1000 xxx0 xxxx 1111 xxxx xxxx xxxx */ + DECODE_REJECT (0xff10f000, 0xf800f000), + + /* LDR (literal) 1111 1000 x101 1111 xxxx xxxx xxxx xxxx */ + DECODE_SIMULATEX(0xff7f0000, 0xf85f0000, PROBES_T32_LDR_LIT, + REGS(PC, ANY, 0, 0, 0)), + + /* STR (immediate) 1111 1000 0100 xxxx xxxx 1xxx xxxx xxxx */ + /* LDR (immediate) 1111 1000 0101 xxxx xxxx 1xxx xxxx xxxx */ + DECODE_OR (0xffe00800, 0xf8400800), + /* STR (immediate) 1111 1000 1100 xxxx xxxx xxxx xxxx xxxx */ + /* LDR (immediate) 1111 1000 1101 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xffe00000, 0xf8c00000, PROBES_T32_LDRSTR, + REGS(NOPCX, ANY, 0, 0, 0)), + + /* STR (register) 1111 1000 0100 xxxx xxxx 0000 00xx xxxx */ + /* LDR (register) 1111 1000 0101 xxxx xxxx 0000 00xx xxxx */ + DECODE_EMULATEX (0xffe00fc0, 0xf8400000, PROBES_T32_LDRSTR, + REGS(NOPCX, ANY, 0, 0, NOSPPC)), + + /* LDRB (literal) 1111 1000 x001 1111 xxxx xxxx xxxx xxxx */ + /* LDRSB (literal) 1111 1001 x001 1111 xxxx xxxx xxxx xxxx */ + /* LDRH (literal) 1111 1000 x011 1111 xxxx xxxx xxxx xxxx */ + /* LDRSH (literal) 1111 1001 x011 1111 xxxx xxxx xxxx xxxx */ + DECODE_SIMULATEX(0xfe5f0000, 0xf81f0000, PROBES_T32_LDR_LIT, + REGS(PC, NOSPPCX, 0, 0, 0)), + + /* STRB (immediate) 1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */ + /* STRH (immediate) 1111 1000 0010 xxxx xxxx 1xxx xxxx xxxx */ + /* LDRB (immediate) 1111 1000 0001 xxxx xxxx 1xxx xxxx xxxx */ + /* LDRSB (immediate) 1111 1001 0001 xxxx xxxx 1xxx xxxx xxxx */ + /* LDRH (immediate) 1111 1000 0011 xxxx xxxx 1xxx xxxx xxxx */ + /* LDRSH (immediate) 1111 1001 0011 xxxx xxxx 1xxx xxxx xxxx */ + DECODE_OR (0xfec00800, 0xf8000800), + /* STRB (immediate) 1111 1000 1000 xxxx xxxx xxxx xxxx xxxx */ + /* STRH (immediate) 1111 1000 1010 xxxx xxxx xxxx xxxx xxxx */ + /* LDRB (immediate) 1111 1000 1001 xxxx xxxx xxxx xxxx xxxx */ + /* LDRSB (immediate) 1111 1001 1001 xxxx xxxx xxxx xxxx xxxx */ + /* LDRH (immediate) 1111 1000 1011 xxxx xxxx xxxx xxxx xxxx */ + /* LDRSH (immediate) 1111 1001 1011 xxxx xxxx xxxx xxxx xxxx */ + DECODE_EMULATEX (0xfec00000, 0xf8800000, PROBES_T32_LDRSTR, + REGS(NOPCX, NOSPPCX, 0, 0, 0)), + + /* STRB (register) 1111 1000 0000 xxxx xxxx 0000 00xx xxxx */ + /* STRH (register) 1111 1000 0010 xxxx xxxx 0000 00xx xxxx */ + /* LDRB (register) 1111 1000 0001 xxxx xxxx 0000 00xx xxxx */ + /* LDRSB (register) 1111 1001 0001 xxxx xxxx 0000 00xx xxxx */ + /* LDRH (register) 1111 1000 0011 xxxx xxxx 0000 00xx xxxx */ + /* LDRSH (register) 1111 1001 0011 xxxx xxxx 0000 00xx xxxx */ + DECODE_EMULATEX (0xfe800fc0, 0xf8000000, PROBES_T32_LDRSTR, + REGS(NOPCX, NOSPPCX, 0, 0, NOSPPC)), + + /* Other unallocated instructions... */ + DECODE_END +}; + +static const union decode_item t32_table_1111_1010___1111[] = { + /* Data-processing (register) */ + + /* ??? 1111 1010 011x xxxx 1111 xxxx 1xxx xxxx */ + DECODE_REJECT (0xffe0f080, 0xfa60f080), + + /* SXTH 1111 1010 0000 1111 1111 xxxx 1xxx xxxx */ + /* UXTH 1111 1010 0001 1111 1111 xxxx 1xxx xxxx */ + /* SXTB16 1111 1010 0010 1111 1111 xxxx 1xxx xxxx */ + /* UXTB16 1111 1010 0011 1111 1111 xxxx 1xxx xxxx */ + /* SXTB 1111 1010 0100 1111 1111 xxxx 1xxx xxxx */ + /* UXTB 1111 1010 0101 1111 1111 xxxx 1xxx xxxx */ + DECODE_EMULATEX (0xff8ff080, 0xfa0ff080, PROBES_T32_SIGN_EXTEND, + REGS(0, 0, NOSPPC, 0, NOSPPC)), + + + /* ??? 1111 1010 1xxx xxxx 1111 xxxx 0x11 xxxx */ + DECODE_REJECT (0xff80f0b0, 0xfa80f030), + /* ??? 1111 1010 1x11 xxxx 1111 xxxx 0xxx xxxx */ + DECODE_REJECT (0xffb0f080, 0xfab0f000), + + /* SADD16 1111 1010 1001 xxxx 1111 xxxx 0000 xxxx */ + /* SASX 1111 1010 1010 xxxx 1111 xxxx 0000 xxxx */ + /* SSAX 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx */ + /* SSUB16 1111 1010 1101 xxxx 1111 xxxx 0000 xxxx */ + /* SADD8 1111 1010 1000 xxxx 1111 xxxx 0000 xxxx */ + /* SSUB8 1111 1010 1100 xxxx 1111 xxxx 0000 xxxx */ + + /* QADD16 1111 1010 1001 xxxx 1111 xxxx 0001 xxxx */ + /* QASX 1111 1010 1010 xxxx 1111 xxxx 0001 xxxx */ + /* QSAX 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx */ + /* QSUB16 1111 1010 1101 xxxx 1111 xxxx 0001 xxxx */ + /* QADD8 1111 1010 1000 xxxx 1111 xxxx 0001 xxxx */ + /* QSUB8 1111 1010 1100 xxxx 1111 xxxx 0001 xxxx */ + + /* SHADD16 1111 1010 1001 xxxx 1111 xxxx 0010 xxxx */ + /* SHASX 1111 1010 1010 xxxx 1111 xxxx 0010 xxxx */ + /* SHSAX 1111 1010 1110 xxxx 1111 xxxx 0010 xxxx */ + /* SHSUB16 1111 1010 1101 xxxx 1111 xxxx 0010 xxxx */ + /* SHADD8 1111 1010 1000 xxxx 1111 xxxx 0010 xxxx */ + /* SHSUB8 1111 1010 1100 xxxx 1111 xxxx 0010 xxxx */ + + /* UADD16 1111 1010 1001 xxxx 1111 xxxx 0100 xxxx */ + /* UASX 1111 1010 1010 xxxx 1111 xxxx 0100 xxxx */ + /* USAX 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx */ + /* USUB16 1111 1010 1101 xxxx 1111 xxxx 0100 xxxx */ + /* UADD8 1111 1010 1000 xxxx 1111 xxxx 0100 xxxx */ + /* USUB8 1111 1010 1100 xxxx 1111 xxxx 0100 xxxx */ + + /* UQADD16 1111 1010 1001 xxxx 1111 xxxx 0101 xxxx */ + /* UQASX 1111 1010 1010 xxxx 1111 xxxx 0101 xxxx */ + /* UQSAX 1111 1010 1110 xxxx 1111 xxxx 0101 xxxx */ + /* UQSUB16 1111 1010 1101 xxxx 1111 xxxx 0101 xxxx */ + /* UQADD8 1111 1010 1000 xxxx 1111 xxxx 0101 xxxx */ + /* UQSUB8 1111 1010 1100 xxxx 1111 xxxx 0101 xxxx */ + + /* UHADD16 1111 1010 1001 xxxx 1111 xxxx 0110 xxxx */ + /* UHASX 1111 1010 1010 xxxx 1111 xxxx 0110 xxxx */ + /* UHSAX 1111 1010 1110 xxxx 1111 xxxx 0110 xxxx */ + /* UHSUB16 1111 1010 1101 xxxx 1111 xxxx 0110 xxxx */ + /* UHADD8 1111 1010 1000 xxxx 1111 xxxx 0110 xxxx */ + /* UHSUB8 1111 1010 1100 xxxx 1111 xxxx 0110 xxxx */ + DECODE_OR (0xff80f080, 0xfa80f000), + + /* SXTAH 1111 1010 0000 xxxx 1111 xxxx 1xxx xxxx */ + /* UXTAH 1111 1010 0001 xxxx 1111 xxxx 1xxx xxxx */ + /* SXTAB16 1111 1010 0010 xxxx 1111 xxxx 1xxx xxxx */ + /* UXTAB16 1111 1010 0011 xxxx 1111 xxxx 1xxx xxxx */ + /* SXTAB 1111 1010 0100 xxxx 1111 xxxx 1xxx xxxx */ + /* UXTAB 1111 1010 0101 xxxx 1111 xxxx 1xxx xxxx */ + DECODE_OR (0xff80f080, 0xfa00f080), + + /* QADD 1111 1010 1000 xxxx 1111 xxxx 1000 xxxx */ + /* QDADD 1111 1010 1000 xxxx 1111 xxxx 1001 xxxx */ + /* QSUB 1111 1010 1000 xxxx 1111 xxxx 1010 xxxx */ + /* QDSUB 1111 1010 1000 xxxx 1111 xxxx 1011 xxxx */ + DECODE_OR (0xfff0f0c0, 0xfa80f080), + + /* SEL 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */ + DECODE_OR (0xfff0f0f0, 0xfaa0f080), + + /* LSL 1111 1010 000x xxxx 1111 xxxx 0000 xxxx */ + /* LSR 1111 1010 001x xxxx 1111 xxxx 0000 xxxx */ + /* ASR 1111 1010 010x xxxx 1111 xxxx 0000 xxxx */ + /* ROR 1111 1010 011x xxxx 1111 xxxx 0000 xxxx */ + DECODE_EMULATEX (0xff80f0f0, 0xfa00f000, PROBES_T32_MEDIA, + REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)), + + /* CLZ 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */ + DECODE_OR (0xfff0f0f0, 0xfab0f080), + + /* REV 1111 1010 1001 xxxx 1111 xxxx 1000 xxxx */ + /* REV16 1111 1010 1001 xxxx 1111 xxxx 1001 xxxx */ + /* RBIT 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx */ + /* REVSH 1111 1010 1001 xxxx 1111 xxxx 1011 xxxx */ + DECODE_EMULATEX (0xfff0f0c0, 0xfa90f080, PROBES_T32_REVERSE, + REGS(NOSPPC, 0, NOSPPC, 0, SAMEAS16)), + + /* Other unallocated instructions... */ + DECODE_END +}; + +static const union decode_item t32_table_1111_1011_0[] = { + /* Multiply, multiply accumulate, and absolute difference */ + + /* ??? 1111 1011 0000 xxxx 1111 xxxx 0001 xxxx */ + DECODE_REJECT (0xfff0f0f0, 0xfb00f010), + /* ??? 1111 1011 0111 xxxx 1111 xxxx 0001 xxxx */ + DECODE_REJECT (0xfff0f0f0, 0xfb70f010), + + /* SMULxy 1111 1011 0001 xxxx 1111 xxxx 00xx xxxx */ + DECODE_OR (0xfff0f0c0, 0xfb10f000), + /* MUL 1111 1011 0000 xxxx 1111 xxxx 0000 xxxx */ + /* SMUAD{X} 1111 1011 0010 xxxx 1111 xxxx 000x xxxx */ + /* SMULWy 1111 1011 0011 xxxx 1111 xxxx 000x xxxx */ + /* SMUSD{X} 1111 1011 0100 xxxx 1111 xxxx 000x xxxx */ + /* SMMUL{R} 1111 1011 0101 xxxx 1111 xxxx 000x xxxx */ + /* USAD8 1111 1011 0111 xxxx 1111 xxxx 0000 xxxx */ + DECODE_EMULATEX (0xff80f0e0, 0xfb00f000, PROBES_T32_MUL_ADD, + REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)), + + /* ??? 1111 1011 0111 xxxx xxxx xxxx 0001 xxxx */ + DECODE_REJECT (0xfff000f0, 0xfb700010), + + /* SMLAxy 1111 1011 0001 xxxx xxxx xxxx 00xx xxxx */ + DECODE_OR (0xfff000c0, 0xfb100000), + /* MLA 1111 1011 0000 xxxx xxxx xxxx 0000 xxxx */ + /* MLS 1111 1011 0000 xxxx xxxx xxxx 0001 xxxx */ + /* SMLAD{X} 1111 1011 0010 xxxx xxxx xxxx 000x xxxx */ + /* SMLAWy 1111 1011 0011 xxxx xxxx xxxx 000x xxxx */ + /* SMLSD{X} 1111 1011 0100 xxxx xxxx xxxx 000x xxxx */ + /* SMMLA{R} 1111 1011 0101 xxxx xxxx xxxx 000x xxxx */ + /* SMMLS{R} 1111 1011 0110 xxxx xxxx xxxx 000x xxxx */ + /* USADA8 1111 1011 0111 xxxx xxxx xxxx 0000 xxxx */ + DECODE_EMULATEX (0xff8000c0, 0xfb000000, PROBES_T32_MUL_ADD2, + REGS(NOSPPC, NOSPPCX, NOSPPC, 0, NOSPPC)), + + /* Other unallocated instructions... */ + DECODE_END +}; + +static const union decode_item t32_table_1111_1011_1[] = { + /* Long multiply, long multiply accumulate, and divide */ + + /* UMAAL 1111 1011 1110 xxxx xxxx xxxx 0110 xxxx */ + DECODE_OR (0xfff000f0, 0xfbe00060), + /* SMLALxy 1111 1011 1100 xxxx xxxx xxxx 10xx xxxx */ + DECODE_OR (0xfff000c0, 0xfbc00080), + /* SMLALD{X} 1111 1011 1100 xxxx xxxx xxxx 110x xxxx */ + /* SMLSLD{X} 1111 1011 1101 xxxx xxxx xxxx 110x xxxx */ + DECODE_OR (0xffe000e0, 0xfbc000c0), + /* SMULL 1111 1011 1000 xxxx xxxx xxxx 0000 xxxx */ + /* UMULL 1111 1011 1010 xxxx xxxx xxxx 0000 xxxx */ + /* SMLAL 1111 1011 1100 xxxx xxxx xxxx 0000 xxxx */ + /* UMLAL 1111 1011 1110 xxxx xxxx xxxx 0000 xxxx */ + DECODE_EMULATEX (0xff9000f0, 0xfb800000, PROBES_T32_MUL_ADD_LONG, + REGS(NOSPPC, NOSPPC, NOSPPC, 0, NOSPPC)), + + /* SDIV 1111 1011 1001 xxxx xxxx xxxx 1111 xxxx */ + /* UDIV 1111 1011 1011 xxxx xxxx xxxx 1111 xxxx */ + /* Other unallocated instructions... */ + DECODE_END +}; + +const union decode_item probes_decode_thumb32_table[] = { + + /* + * Load/store multiple instructions + * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx), + + /* + * Load/store dual, load/store exclusive, table branch + * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx), + + /* + * Data-processing (shifted register) + * 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xfe000000, 0xea000000, t32_table_1110_101x), + + /* + * Coprocessor instructions + * 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_REJECT (0xfc000000, 0xec000000), + + /* + * Data-processing (modified immediate) + * 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0), + + /* + * Data-processing (plain binary immediate) + * 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0), + + /* + * Branches and miscellaneous control + * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1), + + /* + * Advanced SIMD element or structure load/store instructions + * 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx + */ + DECODE_REJECT (0xff100000, 0xf9000000), + + /* + * Memory hints + * 1111 100x x0x1 xxxx 1111 xxxx xxxx xxxx + */ + DECODE_TABLE (0xfe50f000, 0xf810f000, t32_table_1111_100x_x0x1__1111), + + /* + * Store single data item + * 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx + * Load single data items + * 1111 100x xxx1 xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xfe000000, 0xf8000000, t32_table_1111_100x), + + /* + * Data-processing (register) + * 1111 1010 xxxx xxxx 1111 xxxx xxxx xxxx + */ + DECODE_TABLE (0xff00f000, 0xfa00f000, t32_table_1111_1010___1111), + + /* + * Multiply, multiply accumulate, and absolute difference + * 1111 1011 0xxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xff800000, 0xfb000000, t32_table_1111_1011_0), + + /* + * Long multiply, long multiply accumulate, and divide + * 1111 1011 1xxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_TABLE (0xff800000, 0xfb800000, t32_table_1111_1011_1), + + /* + * Coprocessor instructions + * 1111 11xx xxxx xxxx xxxx xxxx xxxx xxxx + */ + DECODE_END +}; +#ifdef CONFIG_ARM_KPROBES_TEST_MODULE +EXPORT_SYMBOL_GPL(probes_decode_thumb32_table); +#endif + +static const union decode_item t16_table_1011[] = { + /* Miscellaneous 16-bit instructions */ + + /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */ + /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */ + DECODE_SIMULATE (0xff00, 0xb000, PROBES_T16_ADD_SP), + + /* CBZ 1011 00x1 xxxx xxxx */ + /* CBNZ 1011 10x1 xxxx xxxx */ + DECODE_SIMULATE (0xf500, 0xb100, PROBES_T16_CBZ), + + /* SXTH 1011 0010 00xx xxxx */ + /* SXTB 1011 0010 01xx xxxx */ + /* UXTH 1011 0010 10xx xxxx */ + /* UXTB 1011 0010 11xx xxxx */ + /* REV 1011 1010 00xx xxxx */ + /* REV16 1011 1010 01xx xxxx */ + /* ??? 1011 1010 10xx xxxx */ + /* REVSH 1011 1010 11xx xxxx */ + DECODE_REJECT (0xffc0, 0xba80), + DECODE_EMULATE (0xf500, 0xb000, PROBES_T16_SIGN_EXTEND), + + /* PUSH 1011 010x xxxx xxxx */ + DECODE_CUSTOM (0xfe00, 0xb400, PROBES_T16_PUSH), + /* POP 1011 110x xxxx xxxx */ + DECODE_CUSTOM (0xfe00, 0xbc00, PROBES_T16_POP), + + /* + * If-Then, and hints + * 1011 1111 xxxx xxxx + */ + + /* YIELD 1011 1111 0001 0000 */ + DECODE_OR (0xffff, 0xbf10), + /* SEV 1011 1111 0100 0000 */ + DECODE_EMULATE (0xffff, 0xbf40, PROBES_T16_SEV), + /* NOP 1011 1111 0000 0000 */ + /* WFE 1011 1111 0010 0000 */ + /* WFI 1011 1111 0011 0000 */ + DECODE_SIMULATE (0xffcf, 0xbf00, PROBES_T16_WFE), + /* Unassigned hints 1011 1111 xxxx 0000 */ + DECODE_REJECT (0xff0f, 0xbf00), + /* IT 1011 1111 xxxx xxxx */ + DECODE_CUSTOM (0xff00, 0xbf00, PROBES_T16_IT), + + /* SETEND 1011 0110 010x xxxx */ + /* CPS 1011 0110 011x xxxx */ + /* BKPT 1011 1110 xxxx xxxx */ + /* And unallocated instructions... */ + DECODE_END +}; + +const union decode_item probes_decode_thumb16_table[] = { + + /* + * Shift (immediate), add, subtract, move, and compare + * 00xx xxxx xxxx xxxx + */ + + /* CMP (immediate) 0010 1xxx xxxx xxxx */ + DECODE_EMULATE (0xf800, 0x2800, PROBES_T16_CMP), + + /* ADD (register) 0001 100x xxxx xxxx */ + /* SUB (register) 0001 101x xxxx xxxx */ + /* LSL (immediate) 0000 0xxx xxxx xxxx */ + /* LSR (immediate) 0000 1xxx xxxx xxxx */ + /* ASR (immediate) 0001 0xxx xxxx xxxx */ + /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */ + /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */ + /* MOV (immediate) 0010 0xxx xxxx xxxx */ + /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */ + /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */ + DECODE_EMULATE (0xc000, 0x0000, PROBES_T16_ADDSUB), + + /* + * 16-bit Thumb data-processing instructions + * 0100 00xx xxxx xxxx + */ + + /* TST (register) 0100 0010 00xx xxxx */ + DECODE_EMULATE (0xffc0, 0x4200, PROBES_T16_CMP), + /* CMP (register) 0100 0010 10xx xxxx */ + /* CMN (register) 0100 0010 11xx xxxx */ + DECODE_EMULATE (0xff80, 0x4280, PROBES_T16_CMP), + /* AND (register) 0100 0000 00xx xxxx */ + /* EOR (register) 0100 0000 01xx xxxx */ + /* LSL (register) 0100 0000 10xx xxxx */ + /* LSR (register) 0100 0000 11xx xxxx */ + /* ASR (register) 0100 0001 00xx xxxx */ + /* ADC (register) 0100 0001 01xx xxxx */ + /* SBC (register) 0100 0001 10xx xxxx */ + /* ROR (register) 0100 0001 11xx xxxx */ + /* RSB (immediate) 0100 0010 01xx xxxx */ + /* ORR (register) 0100 0011 00xx xxxx */ + /* MUL 0100 0011 00xx xxxx */ + /* BIC (register) 0100 0011 10xx xxxx */ + /* MVN (register) 0100 0011 10xx xxxx */ + DECODE_EMULATE (0xfc00, 0x4000, PROBES_T16_LOGICAL), + + /* + * Special data instructions and branch and exchange + * 0100 01xx xxxx xxxx + */ + + /* BLX pc 0100 0111 1111 1xxx */ + DECODE_REJECT (0xfff8, 0x47f8), + + /* BX (register) 0100 0111 0xxx xxxx */ + /* BLX (register) 0100 0111 1xxx xxxx */ + DECODE_SIMULATE (0xff00, 0x4700, PROBES_T16_BLX), + + /* ADD pc, pc 0100 0100 1111 1111 */ + DECODE_REJECT (0xffff, 0x44ff), + + /* ADD (register) 0100 0100 xxxx xxxx */ + /* CMP (register) 0100 0101 xxxx xxxx */ + /* MOV (register) 0100 0110 xxxx xxxx */ + DECODE_CUSTOM (0xfc00, 0x4400, PROBES_T16_HIREGOPS), + + /* + * Load from Literal Pool + * LDR (literal) 0100 1xxx xxxx xxxx + */ + DECODE_SIMULATE (0xf800, 0x4800, PROBES_T16_LDR_LIT), + + /* + * 16-bit Thumb Load/store instructions + * 0101 xxxx xxxx xxxx + * 011x xxxx xxxx xxxx + * 100x xxxx xxxx xxxx + */ + + /* STR (register) 0101 000x xxxx xxxx */ + /* STRH (register) 0101 001x xxxx xxxx */ + /* STRB (register) 0101 010x xxxx xxxx */ + /* LDRSB (register) 0101 011x xxxx xxxx */ + /* LDR (register) 0101 100x xxxx xxxx */ + /* LDRH (register) 0101 101x xxxx xxxx */ + /* LDRB (register) 0101 110x xxxx xxxx */ + /* LDRSH (register) 0101 111x xxxx xxxx */ + /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */ + /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */ + /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */ + /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */ + DECODE_EMULATE (0xc000, 0x4000, PROBES_T16_LDRHSTRH), + /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */ + /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */ + DECODE_EMULATE (0xf000, 0x8000, PROBES_T16_LDRHSTRH), + /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */ + /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */ + DECODE_SIMULATE (0xf000, 0x9000, PROBES_T16_LDRSTR), + + /* + * Generate PC-/SP-relative address + * ADR (literal) 1010 0xxx xxxx xxxx + * ADD (SP plus immediate) 1010 1xxx xxxx xxxx + */ + DECODE_SIMULATE (0xf000, 0xa000, PROBES_T16_ADR), + + /* + * Miscellaneous 16-bit instructions + * 1011 xxxx xxxx xxxx + */ + DECODE_TABLE (0xf000, 0xb000, t16_table_1011), + + /* STM 1100 0xxx xxxx xxxx */ + /* LDM 1100 1xxx xxxx xxxx */ + DECODE_EMULATE (0xf000, 0xc000, PROBES_T16_LDMSTM), + + /* + * Conditional branch, and Supervisor Call + */ + + /* Permanently UNDEFINED 1101 1110 xxxx xxxx */ + /* SVC 1101 1111 xxxx xxxx */ + DECODE_REJECT (0xfe00, 0xde00), + + /* Conditional branch 1101 xxxx xxxx xxxx */ + DECODE_CUSTOM (0xf000, 0xd000, PROBES_T16_BRANCH_COND), + + /* + * Unconditional branch + * B 1110 0xxx xxxx xxxx + */ + DECODE_SIMULATE (0xf800, 0xe000, PROBES_T16_BRANCH), + + DECODE_END +}; +#ifdef CONFIG_ARM_KPROBES_TEST_MODULE +EXPORT_SYMBOL_GPL(probes_decode_thumb16_table); +#endif + +static unsigned long __kprobes thumb_check_cc(unsigned long cpsr) +{ + if (unlikely(in_it_block(cpsr))) + return probes_condition_checks[current_cond(cpsr)](cpsr); + return true; +} + +static void __kprobes thumb16_singlestep(probes_opcode_t opcode, + struct arch_probes_insn *asi, + struct pt_regs *regs) +{ + regs->ARM_pc += 2; + asi->insn_handler(opcode, asi, regs); + regs->ARM_cpsr = it_advance(regs->ARM_cpsr); +} + +static void __kprobes thumb32_singlestep(probes_opcode_t opcode, + struct arch_probes_insn *asi, + struct pt_regs *regs) +{ + regs->ARM_pc += 4; + asi->insn_handler(opcode, asi, regs); + regs->ARM_cpsr = it_advance(regs->ARM_cpsr); +} + +enum probes_insn __kprobes +thumb16_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + bool emulate, const union decode_action *actions) +{ + asi->insn_singlestep = thumb16_singlestep; + asi->insn_check_cc = thumb_check_cc; + return probes_decode_insn(insn, asi, probes_decode_thumb16_table, true, + emulate, actions); +} + +enum probes_insn __kprobes +thumb32_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + bool emulate, const union decode_action *actions) +{ + asi->insn_singlestep = thumb32_singlestep; + asi->insn_check_cc = thumb_check_cc; + return probes_decode_insn(insn, asi, probes_decode_thumb32_table, true, + emulate, actions); +} diff -Nur linux-3.14.1/arch/arm/kernel/probes-thumb.h linux-3.15-rc1.orig/arch/arm/kernel/probes-thumb.h --- linux-3.14.1/arch/arm/kernel/probes-thumb.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/probes-thumb.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,97 @@ +/* + * arch/arm/kernel/probes-thumb.h + * + * Copyright 2013 Linaro Ltd. + * Written by: David A. Long + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _ARM_KERNEL_PROBES_THUMB_H +#define _ARM_KERNEL_PROBES_THUMB_H + +/* + * True if current instruction is in an IT block. + */ +#define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000) + +/* + * Return the condition code to check for the currently executing instruction. + * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if + * in_it_block returns true. + */ +#define current_cond(cpsr) ((cpsr >> 12) & 0xf) + +enum probes_t32_action { + PROBES_T32_EMULATE_NONE, + PROBES_T32_SIMULATE_NOP, + PROBES_T32_LDMSTM, + PROBES_T32_LDRDSTRD, + PROBES_T32_TABLE_BRANCH, + PROBES_T32_TST, + PROBES_T32_CMP, + PROBES_T32_MOV, + PROBES_T32_ADDSUB, + PROBES_T32_LOGICAL, + PROBES_T32_ADDWSUBW_PC, + PROBES_T32_ADDWSUBW, + PROBES_T32_MOVW, + PROBES_T32_SAT, + PROBES_T32_BITFIELD, + PROBES_T32_SEV, + PROBES_T32_WFE, + PROBES_T32_MRS, + PROBES_T32_BRANCH_COND, + PROBES_T32_BRANCH, + PROBES_T32_PLDI, + PROBES_T32_LDR_LIT, + PROBES_T32_LDRSTR, + PROBES_T32_SIGN_EXTEND, + PROBES_T32_MEDIA, + PROBES_T32_REVERSE, + PROBES_T32_MUL_ADD, + PROBES_T32_MUL_ADD2, + PROBES_T32_MUL_ADD_LONG, + NUM_PROBES_T32_ACTIONS +}; + +enum probes_t16_action { + PROBES_T16_ADD_SP, + PROBES_T16_CBZ, + PROBES_T16_SIGN_EXTEND, + PROBES_T16_PUSH, + PROBES_T16_POP, + PROBES_T16_SEV, + PROBES_T16_WFE, + PROBES_T16_IT, + PROBES_T16_CMP, + PROBES_T16_ADDSUB, + PROBES_T16_LOGICAL, + PROBES_T16_BLX, + PROBES_T16_HIREGOPS, + PROBES_T16_LDR_LIT, + PROBES_T16_LDRHSTRH, + PROBES_T16_LDRSTR, + PROBES_T16_ADR, + PROBES_T16_LDMSTM, + PROBES_T16_BRANCH_COND, + PROBES_T16_BRANCH, + NUM_PROBES_T16_ACTIONS +}; + +extern const union decode_item probes_decode_thumb32_table[]; +extern const union decode_item probes_decode_thumb16_table[]; + +enum probes_insn __kprobes +thumb16_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + bool emulate, const union decode_action *actions); +enum probes_insn __kprobes +thumb32_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, + bool emulate, const union decode_action *actions); + +#endif diff -Nur linux-3.14.1/arch/arm/kernel/process.c linux-3.15-rc1.orig/arch/arm/kernel/process.c --- linux-3.14.1/arch/arm/kernel/process.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/process.c 2014-04-13 23:18:35.000000000 +0200 @@ -30,7 +30,6 @@ #include #include #include -#include #include #include @@ -39,6 +38,7 @@ #include #include #include +#include #include #include @@ -48,14 +48,14 @@ EXPORT_SYMBOL(__stack_chk_guard); #endif -static const char *processor_modes[] = { +static const char *processor_modes[] __maybe_unused = { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" , "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32" }; -static const char *isa_modes[] = { +static const char *isa_modes[] __maybe_unused = { "ARM" , "Thumb" , "Jazelle", "ThumbEE" }; @@ -100,7 +100,7 @@ u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack); /* Disable interrupts first */ - local_irq_disable(); + raw_local_irq_disable(); local_fiq_disable(); /* Disable the L2 if we're the last man standing. */ @@ -133,7 +133,11 @@ void (*arm_pm_idle)(void); -static void default_idle(void) +/* + * Called from the core idle loop. + */ + +void arch_cpu_idle(void) { if (arm_pm_idle) arm_pm_idle(); @@ -168,15 +172,6 @@ #endif /* - * Called from the core idle loop. - */ -void arch_cpu_idle(void) -{ - if (cpuidle_idle_call()) - default_idle(); -} - -/* * Called by kexec, immediately prior to machine_kexec(). * * This must completely disable all secondary CPUs; simply causing those CPUs @@ -276,12 +271,17 @@ buf[3] = flags & PSR_V_BIT ? 'V' : 'v'; buf[4] = '\0'; +#ifndef CONFIG_CPU_V7M printk("Flags: %s IRQs o%s FIQs o%s Mode %s ISA %s Segment %s\n", buf, interrupts_enabled(regs) ? "n" : "ff", fast_interrupts_enabled(regs) ? "n" : "ff", processor_modes[processor_mode(regs)], isa_modes[isa_mode(regs)], get_fs() == get_ds() ? "kernel" : "user"); +#else + printk("xPSR: %08lx\n", regs->ARM_cpsr); +#endif + #ifdef CONFIG_CPU_CP15 { unsigned int ctrl; diff -Nur linux-3.14.1/arch/arm/kernel/setup.c linux-3.15-rc1.orig/arch/arm/kernel/setup.c --- linux-3.14.1/arch/arm/kernel/setup.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/setup.c 2014-04-13 23:18:35.000000000 +0200 @@ -100,6 +100,9 @@ unsigned int elf_hwcap __read_mostly; EXPORT_SYMBOL(elf_hwcap); +unsigned int elf_hwcap2 __read_mostly; +EXPORT_SYMBOL(elf_hwcap2); + #ifdef MULTI_CPU struct processor processor __read_mostly; @@ -1005,6 +1008,15 @@ NULL }; +static const char *hwcap2_str[] = { + "aes", + "pmull", + "sha1", + "sha2", + "crc32", + NULL +}; + static int c_show(struct seq_file *m, void *v) { int i, j; @@ -1028,6 +1040,10 @@ if (elf_hwcap & (1 << j)) seq_printf(m, "%s ", hwcap_str[j]); + for (j = 0; hwcap2_str[j]; j++) + if (elf_hwcap2 & (1 << j)) + seq_printf(m, "%s ", hwcap2_str[j]); + seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24); seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]); diff -Nur linux-3.14.1/arch/arm/kernel/signal.c linux-3.15-rc1.orig/arch/arm/kernel/signal.c --- linux-3.14.1/arch/arm/kernel/signal.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/signal.c 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -590,6 +591,9 @@ return restart; } syscall = 0; + } else if (thread_flags & _TIF_UPROBE) { + clear_thread_flag(TIF_UPROBE); + uprobe_notify_resume(regs); } else { clear_thread_flag(TIF_NOTIFY_RESUME); tracehook_notify_resume(regs); diff -Nur linux-3.14.1/arch/arm/kernel/smp.c linux-3.15-rc1.orig/arch/arm/kernel/smp.c --- linux-3.14.1/arch/arm/kernel/smp.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/smp.c 2014-04-13 23:18:35.000000000 +0200 @@ -674,8 +674,7 @@ } if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || - (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || - (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) { + (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { loops_per_jiffy = cpufreq_scale(global_l_p_j_ref, global_l_p_j_ref_freq, freq->new); diff -Nur linux-3.14.1/arch/arm/kernel/smp_twd.c linux-3.15-rc1.orig/arch/arm/kernel/smp_twd.c --- linux-3.14.1/arch/arm/kernel/smp_twd.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/smp_twd.c 2014-04-13 23:18:35.000000000 +0200 @@ -166,7 +166,7 @@ * frequency. The timer is local to a cpu, so cross-call to the * changing cpu. */ - if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE) + if (state == CPUFREQ_POSTCHANGE) smp_call_function_single(freqs->cpu, twd_update_frequency, NULL, 1); diff -Nur linux-3.14.1/arch/arm/kernel/sys_oabi-compat.c linux-3.15-rc1.orig/arch/arm/kernel/sys_oabi-compat.c --- linux-3.14.1/arch/arm/kernel/sys_oabi-compat.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/sys_oabi-compat.c 2014-04-13 23:18:35.000000000 +0200 @@ -203,6 +203,9 @@ int ret; switch (cmd) { + case F_GETLKP: + case F_SETLKP: + case F_SETLKPW: case F_GETLK64: case F_SETLK64: case F_SETLKW64: diff -Nur linux-3.14.1/arch/arm/kernel/traps.c linux-3.15-rc1.orig/arch/arm/kernel/traps.c --- linux-3.14.1/arch/arm/kernel/traps.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/traps.c 2014-04-13 23:18:35.000000000 +0200 @@ -445,6 +445,7 @@ if (user_debug & UDBG_UNDEFINED) { printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n", current->comm, task_pid_nr(current), pc); + __show_regs(regs); dump_instr(KERN_INFO, regs); } #endif diff -Nur linux-3.14.1/arch/arm/kernel/unwind.c linux-3.15-rc1.orig/arch/arm/kernel/unwind.c --- linux-3.14.1/arch/arm/kernel/unwind.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kernel/unwind.c 2014-04-13 23:18:35.000000000 +0200 @@ -68,6 +68,12 @@ struct unwind_ctrl_block { unsigned long vrs[16]; /* virtual register set */ const unsigned long *insn; /* pointer to the current instructions word */ + unsigned long sp_high; /* highest value of sp allowed */ + /* + * 1 : check for stack overflow for each register pop. + * 0 : save overhead if there is plenty of stack remaining. + */ + int check_each_pop; int entries; /* number of entries left to interpret */ int byte; /* current byte number in the instructions word */ }; @@ -235,12 +241,85 @@ return ret; } +/* Before poping a register check whether it is feasible or not */ +static int unwind_pop_register(struct unwind_ctrl_block *ctrl, + unsigned long **vsp, unsigned int reg) +{ + if (unlikely(ctrl->check_each_pop)) + if (*vsp >= (unsigned long *)ctrl->sp_high) + return -URC_FAILURE; + + ctrl->vrs[reg] = *(*vsp)++; + return URC_OK; +} + +/* Helper functions to execute the instructions */ +static int unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl, + unsigned long mask) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int load_sp, reg = 4; + + load_sp = mask & (1 << (13 - 4)); + while (mask) { + if (mask & 1) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + mask >>= 1; + reg++; + } + if (!load_sp) + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl, + unsigned long insn) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int reg; + + /* pop R4-R[4+bbb] */ + for (reg = 4; reg <= 4 + (insn & 7); reg++) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + + if (insn & 0x80) + if (unwind_pop_register(ctrl, &vsp, 14)) + return -URC_FAILURE; + + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, + unsigned long mask) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int reg = 0; + + /* pop R0-R3 according to mask */ + while (mask) { + if (mask & 1) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + mask >>= 1; + reg++; + } + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + /* * Execute the current unwind instruction. */ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) { unsigned long insn = unwind_get_byte(ctrl); + int ret = URC_OK; pr_debug("%s: insn = %08lx\n", __func__, insn); @@ -250,8 +329,6 @@ ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; else if ((insn & 0xf0) == 0x80) { unsigned long mask; - unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; - int load_sp, reg = 4; insn = (insn << 8) | unwind_get_byte(ctrl); mask = insn & 0x0fff; @@ -261,29 +338,16 @@ return -URC_FAILURE; } - /* pop R4-R15 according to mask */ - load_sp = mask & (1 << (13 - 4)); - while (mask) { - if (mask & 1) - ctrl->vrs[reg] = *vsp++; - mask >>= 1; - reg++; - } - if (!load_sp) - ctrl->vrs[SP] = (unsigned long)vsp; + ret = unwind_exec_pop_subset_r4_to_r13(ctrl, mask); + if (ret) + goto error; } else if ((insn & 0xf0) == 0x90 && (insn & 0x0d) != 0x0d) ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; else if ((insn & 0xf0) == 0xa0) { - unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; - int reg; - - /* pop R4-R[4+bbb] */ - for (reg = 4; reg <= 4 + (insn & 7); reg++) - ctrl->vrs[reg] = *vsp++; - if (insn & 0x80) - ctrl->vrs[14] = *vsp++; - ctrl->vrs[SP] = (unsigned long)vsp; + ret = unwind_exec_pop_r4_to_rN(ctrl, insn); + if (ret) + goto error; } else if (insn == 0xb0) { if (ctrl->vrs[PC] == 0) ctrl->vrs[PC] = ctrl->vrs[LR]; @@ -291,8 +355,6 @@ ctrl->entries = 0; } else if (insn == 0xb1) { unsigned long mask = unwind_get_byte(ctrl); - unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; - int reg = 0; if (mask == 0 || mask & 0xf0) { pr_warning("unwind: Spare encoding %04lx\n", @@ -300,14 +362,9 @@ return -URC_FAILURE; } - /* pop R0-R3 according to mask */ - while (mask) { - if (mask & 1) - ctrl->vrs[reg] = *vsp++; - mask >>= 1; - reg++; - } - ctrl->vrs[SP] = (unsigned long)vsp; + ret = unwind_exec_pop_subset_r0_to_r3(ctrl, mask); + if (ret) + goto error; } else if (insn == 0xb2) { unsigned long uleb128 = unwind_get_byte(ctrl); @@ -320,7 +377,8 @@ pr_debug("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx\n", __func__, ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); - return URC_OK; +error: + return ret; } /* @@ -329,13 +387,13 @@ */ int unwind_frame(struct stackframe *frame) { - unsigned long high, low; + unsigned long low; const struct unwind_idx *idx; struct unwind_ctrl_block ctrl; - /* only go to a higher address on the stack */ + /* store the highest address on the stack to avoid crossing it*/ low = frame->sp; - high = ALIGN(low, THREAD_SIZE); + ctrl.sp_high = ALIGN(low, THREAD_SIZE); pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__, frame->pc, frame->lr, frame->sp); @@ -382,11 +440,16 @@ return -URC_FAILURE; } + ctrl.check_each_pop = 0; + while (ctrl.entries > 0) { - int urc = unwind_exec_insn(&ctrl); + int urc; + if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs)) + ctrl.check_each_pop = 1; + urc = unwind_exec_insn(&ctrl); if (urc < 0) return urc; - if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) + if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high) return -URC_FAILURE; } diff -Nur linux-3.14.1/arch/arm/kernel/uprobes-arm.c linux-3.15-rc1.orig/arch/arm/kernel/uprobes-arm.c --- linux-3.14.1/arch/arm/kernel/uprobes-arm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/uprobes-arm.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2012 Rabin Vincent + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include "probes.h" +#include "probes-arm.h" +#include "uprobes.h" + +static int uprobes_substitute_pc(unsigned long *pinsn, u32 oregs) +{ + probes_opcode_t insn = __mem_to_opcode_arm(*pinsn); + probes_opcode_t temp; + probes_opcode_t mask; + int freereg; + u32 free = 0xffff; + u32 regs; + + for (regs = oregs; regs; regs >>= 4, insn >>= 4) { + if ((regs & 0xf) == REG_TYPE_NONE) + continue; + + free &= ~(1 << (insn & 0xf)); + } + + /* No PC, no problem */ + if (free & (1 << 15)) + return 15; + + if (!free) + return -1; + + /* + * fls instead of ffs ensures that for "ldrd r0, r1, [pc]" we would + * pick LR instead of R1. + */ + freereg = free = fls(free) - 1; + + temp = __mem_to_opcode_arm(*pinsn); + insn = temp; + regs = oregs; + mask = 0xf; + + for (; regs; regs >>= 4, mask <<= 4, free <<= 4, temp >>= 4) { + if ((regs & 0xf) == REG_TYPE_NONE) + continue; + + if ((temp & 0xf) != 15) + continue; + + insn &= ~mask; + insn |= free & mask; + } + + *pinsn = __opcode_to_mem_arm(insn); + return freereg; +} + +static void uprobe_set_pc(struct arch_uprobe *auprobe, + struct arch_uprobe_task *autask, + struct pt_regs *regs) +{ + u32 pcreg = auprobe->pcreg; + + autask->backup = regs->uregs[pcreg]; + regs->uregs[pcreg] = regs->ARM_pc + 8; +} + +static void uprobe_unset_pc(struct arch_uprobe *auprobe, + struct arch_uprobe_task *autask, + struct pt_regs *regs) +{ + /* PC will be taken care of by common code */ + regs->uregs[auprobe->pcreg] = autask->backup; +} + +static void uprobe_aluwrite_pc(struct arch_uprobe *auprobe, + struct arch_uprobe_task *autask, + struct pt_regs *regs) +{ + u32 pcreg = auprobe->pcreg; + + alu_write_pc(regs->uregs[pcreg], regs); + regs->uregs[pcreg] = autask->backup; +} + +static void uprobe_write_pc(struct arch_uprobe *auprobe, + struct arch_uprobe_task *autask, + struct pt_regs *regs) +{ + u32 pcreg = auprobe->pcreg; + + load_write_pc(regs->uregs[pcreg], regs); + regs->uregs[pcreg] = autask->backup; +} + +enum probes_insn +decode_pc_ro(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) +{ + struct arch_uprobe *auprobe = container_of(asi, struct arch_uprobe, + asi); + struct decode_emulate *decode = (struct decode_emulate *) d; + u32 regs = decode->header.type_regs.bits >> DECODE_TYPE_BITS; + int reg; + + reg = uprobes_substitute_pc(&auprobe->ixol[0], regs); + if (reg == 15) + return INSN_GOOD; + + if (reg == -1) + return INSN_REJECTED; + + auprobe->pcreg = reg; + auprobe->prehandler = uprobe_set_pc; + auprobe->posthandler = uprobe_unset_pc; + + return INSN_GOOD; +} + +enum probes_insn +decode_wb_pc(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d, bool alu) +{ + struct arch_uprobe *auprobe = container_of(asi, struct arch_uprobe, + asi); + enum probes_insn ret = decode_pc_ro(insn, asi, d); + + if (((insn >> 12) & 0xf) == 15) + auprobe->posthandler = alu ? uprobe_aluwrite_pc + : uprobe_write_pc; + + return ret; +} + +enum probes_insn +decode_rd12rn16rm0rs8_rwflags(probes_opcode_t insn, + struct arch_probes_insn *asi, + const struct decode_header *d) +{ + return decode_wb_pc(insn, asi, d, true); +} + +enum probes_insn +decode_ldr(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d) +{ + return decode_wb_pc(insn, asi, d, false); +} + +enum probes_insn +uprobe_decode_ldmstm(probes_opcode_t insn, + struct arch_probes_insn *asi, + const struct decode_header *d) +{ + struct arch_uprobe *auprobe = container_of(asi, struct arch_uprobe, + asi); + unsigned reglist = insn & 0xffff; + int rn = (insn >> 16) & 0xf; + int lbit = insn & (1 << 20); + unsigned used = reglist | (1 << rn); + + if (rn == 15) + return INSN_REJECTED; + + if (!(used & (1 << 15))) + return INSN_GOOD; + + if (used & (1 << 14)) + return INSN_REJECTED; + + /* Use LR instead of PC */ + insn ^= 0xc000; + + auprobe->pcreg = 14; + auprobe->ixol[0] = __opcode_to_mem_arm(insn); + + auprobe->prehandler = uprobe_set_pc; + if (lbit) + auprobe->posthandler = uprobe_write_pc; + else + auprobe->posthandler = uprobe_unset_pc; + + return INSN_GOOD; +} + +const union decode_action uprobes_probes_actions[] = { + [PROBES_EMULATE_NONE] = {.handler = probes_simulate_nop}, + [PROBES_SIMULATE_NOP] = {.handler = probes_simulate_nop}, + [PROBES_PRELOAD_IMM] = {.handler = probes_simulate_nop}, + [PROBES_PRELOAD_REG] = {.handler = probes_simulate_nop}, + [PROBES_BRANCH_IMM] = {.handler = simulate_blx1}, + [PROBES_MRS] = {.handler = simulate_mrs}, + [PROBES_BRANCH_REG] = {.handler = simulate_blx2bx}, + [PROBES_CLZ] = {.handler = probes_simulate_nop}, + [PROBES_SATURATING_ARITHMETIC] = {.handler = probes_simulate_nop}, + [PROBES_MUL1] = {.handler = probes_simulate_nop}, + [PROBES_MUL2] = {.handler = probes_simulate_nop}, + [PROBES_SWP] = {.handler = probes_simulate_nop}, + [PROBES_LDRSTRD] = {.decoder = decode_pc_ro}, + [PROBES_LOAD_EXTRA] = {.decoder = decode_pc_ro}, + [PROBES_LOAD] = {.decoder = decode_ldr}, + [PROBES_STORE_EXTRA] = {.decoder = decode_pc_ro}, + [PROBES_STORE] = {.decoder = decode_pc_ro}, + [PROBES_MOV_IP_SP] = {.handler = simulate_mov_ipsp}, + [PROBES_DATA_PROCESSING_REG] = { + .decoder = decode_rd12rn16rm0rs8_rwflags}, + [PROBES_DATA_PROCESSING_IMM] = { + .decoder = decode_rd12rn16rm0rs8_rwflags}, + [PROBES_MOV_HALFWORD] = {.handler = probes_simulate_nop}, + [PROBES_SEV] = {.handler = probes_simulate_nop}, + [PROBES_WFE] = {.handler = probes_simulate_nop}, + [PROBES_SATURATE] = {.handler = probes_simulate_nop}, + [PROBES_REV] = {.handler = probes_simulate_nop}, + [PROBES_MMI] = {.handler = probes_simulate_nop}, + [PROBES_PACK] = {.handler = probes_simulate_nop}, + [PROBES_EXTEND] = {.handler = probes_simulate_nop}, + [PROBES_EXTEND_ADD] = {.handler = probes_simulate_nop}, + [PROBES_MUL_ADD_LONG] = {.handler = probes_simulate_nop}, + [PROBES_MUL_ADD] = {.handler = probes_simulate_nop}, + [PROBES_BITFIELD] = {.handler = probes_simulate_nop}, + [PROBES_BRANCH] = {.handler = simulate_bbl}, + [PROBES_LDMSTM] = {.decoder = uprobe_decode_ldmstm} +}; diff -Nur linux-3.14.1/arch/arm/kernel/uprobes.c linux-3.15-rc1.orig/arch/arm/kernel/uprobes.c --- linux-3.14.1/arch/arm/kernel/uprobes.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/uprobes.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2012 Rabin Vincent + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "probes.h" +#include "probes-arm.h" +#include "uprobes.h" + +#define UPROBE_TRAP_NR UINT_MAX + +bool is_swbp_insn(uprobe_opcode_t *insn) +{ + return (__mem_to_opcode_arm(*insn) & 0x0fffffff) == + (UPROBE_SWBP_ARM_INSN & 0x0fffffff); +} + +int set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm, + unsigned long vaddr) +{ + return uprobe_write_opcode(mm, vaddr, + __opcode_to_mem_arm(auprobe->bpinsn)); +} + +bool arch_uprobe_ignore(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + if (!auprobe->asi.insn_check_cc(regs->ARM_cpsr)) { + regs->ARM_pc += 4; + return true; + } + + return false; +} + +bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + probes_opcode_t opcode; + + if (!auprobe->simulate) + return false; + + opcode = __mem_to_opcode_arm(*(unsigned int *) auprobe->insn); + + auprobe->asi.insn_singlestep(opcode, &auprobe->asi, regs); + + return true; +} + +unsigned long +arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, + struct pt_regs *regs) +{ + unsigned long orig_ret_vaddr; + + orig_ret_vaddr = regs->ARM_lr; + /* Replace the return addr with trampoline addr */ + regs->ARM_lr = trampoline_vaddr; + return orig_ret_vaddr; +} + +int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, + unsigned long addr) +{ + unsigned int insn; + unsigned int bpinsn; + enum probes_insn ret; + + /* Thumb not yet support */ + if (addr & 0x3) + return -EINVAL; + + insn = __mem_to_opcode_arm(*(unsigned int *)auprobe->insn); + auprobe->ixol[0] = __opcode_to_mem_arm(insn); + auprobe->ixol[1] = __opcode_to_mem_arm(UPROBE_SS_ARM_INSN); + + ret = arm_probes_decode_insn(insn, &auprobe->asi, false, + uprobes_probes_actions); + switch (ret) { + case INSN_REJECTED: + return -EINVAL; + + case INSN_GOOD_NO_SLOT: + auprobe->simulate = true; + break; + + case INSN_GOOD: + default: + break; + } + + bpinsn = UPROBE_SWBP_ARM_INSN & 0x0fffffff; + if (insn >= 0xe0000000) + bpinsn |= 0xe0000000; /* Unconditional instruction */ + else + bpinsn |= insn & 0xf0000000; /* Copy condition from insn */ + + auprobe->bpinsn = bpinsn; + + return 0; +} + +int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + struct uprobe_task *utask = current->utask; + + if (auprobe->prehandler) + auprobe->prehandler(auprobe, &utask->autask, regs); + + utask->autask.saved_trap_no = current->thread.trap_no; + current->thread.trap_no = UPROBE_TRAP_NR; + regs->ARM_pc = utask->xol_vaddr; + + return 0; +} + +int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + struct uprobe_task *utask = current->utask; + + WARN_ON_ONCE(current->thread.trap_no != UPROBE_TRAP_NR); + + current->thread.trap_no = utask->autask.saved_trap_no; + regs->ARM_pc = utask->vaddr + 4; + + if (auprobe->posthandler) + auprobe->posthandler(auprobe, &utask->autask, regs); + + return 0; +} + +bool arch_uprobe_xol_was_trapped(struct task_struct *t) +{ + if (t->thread.trap_no != UPROBE_TRAP_NR) + return true; + + return false; +} + +void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + struct uprobe_task *utask = current->utask; + + current->thread.trap_no = utask->autask.saved_trap_no; + instruction_pointer_set(regs, utask->vaddr); +} + +int arch_uprobe_exception_notify(struct notifier_block *self, + unsigned long val, void *data) +{ + return NOTIFY_DONE; +} + +static int uprobe_trap_handler(struct pt_regs *regs, unsigned int instr) +{ + unsigned long flags; + + local_irq_save(flags); + instr &= 0x0fffffff; + if (instr == (UPROBE_SWBP_ARM_INSN & 0x0fffffff)) + uprobe_pre_sstep_notifier(regs); + else if (instr == (UPROBE_SS_ARM_INSN & 0x0fffffff)) + uprobe_post_sstep_notifier(regs); + local_irq_restore(flags); + + return 0; +} + +unsigned long uprobe_get_swbp_addr(struct pt_regs *regs) +{ + return instruction_pointer(regs); +} + +static struct undef_hook uprobes_arm_break_hook = { + .instr_mask = 0x0fffffff, + .instr_val = (UPROBE_SWBP_ARM_INSN & 0x0fffffff), + .cpsr_mask = MODE_MASK, + .cpsr_val = USR_MODE, + .fn = uprobe_trap_handler, +}; + +static struct undef_hook uprobes_arm_ss_hook = { + .instr_mask = 0x0fffffff, + .instr_val = (UPROBE_SS_ARM_INSN & 0x0fffffff), + .cpsr_mask = MODE_MASK, + .cpsr_val = USR_MODE, + .fn = uprobe_trap_handler, +}; + +static int arch_uprobes_init(void) +{ + register_undef_hook(&uprobes_arm_break_hook); + register_undef_hook(&uprobes_arm_ss_hook); + + return 0; +} +device_initcall(arch_uprobes_init); diff -Nur linux-3.14.1/arch/arm/kernel/uprobes.h linux-3.15-rc1.orig/arch/arm/kernel/uprobes.h --- linux-3.14.1/arch/arm/kernel/uprobes.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/kernel/uprobes.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2012 Rabin Vincent + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARM_KERNEL_UPROBES_H +#define __ARM_KERNEL_UPROBES_H + +enum probes_insn uprobe_decode_ldmstm(probes_opcode_t insn, + struct arch_probes_insn *asi, + const struct decode_header *d); + +enum probes_insn decode_ldr(probes_opcode_t insn, + struct arch_probes_insn *asi, + const struct decode_header *d); + +enum probes_insn +decode_rd12rn16rm0rs8_rwflags(probes_opcode_t insn, + struct arch_probes_insn *asi, + const struct decode_header *d); + +enum probes_insn +decode_wb_pc(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d, bool alu); + +enum probes_insn +decode_pc_ro(probes_opcode_t insn, struct arch_probes_insn *asi, + const struct decode_header *d); + +extern const union decode_action uprobes_probes_actions[]; + +#endif diff -Nur linux-3.14.1/arch/arm/kvm/arm.c linux-3.15-rc1.orig/arch/arm/kvm/arm.c --- linux-3.14.1/arch/arm/kvm/arm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/arm.c 2014-04-13 23:18:35.000000000 +0200 @@ -1051,21 +1051,26 @@ } } + cpu_notifier_register_begin(); + err = init_hyp_mode(); if (err) goto out_err; - err = register_cpu_notifier(&hyp_init_cpu_nb); + err = __register_cpu_notifier(&hyp_init_cpu_nb); if (err) { kvm_err("Cannot register HYP init CPU notifier (%d)\n", err); goto out_err; } + cpu_notifier_register_done(); + hyp_cpu_pm_init(); kvm_coproc_table_init(); return 0; out_err: + cpu_notifier_register_done(); return err; } diff -Nur linux-3.14.1/arch/arm/kvm/coproc_a15.c linux-3.15-rc1.orig/arch/arm/kvm/coproc_a15.c --- linux-3.14.1/arch/arm/kvm/coproc_a15.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/coproc_a15.c 2014-04-13 23:18:35.000000000 +0200 @@ -34,7 +34,7 @@ static const struct coproc_reg a15_regs[] = { /* SCTLR: swapped by interrupt.S. */ { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, - NULL, reset_val, c1_SCTLR, 0x00C50078 }, + access_sctlr, reset_val, c1_SCTLR, 0x00C50078 }, }; static struct kvm_coproc_target_table a15_target_table = { diff -Nur linux-3.14.1/arch/arm/kvm/coproc_a7.c linux-3.15-rc1.orig/arch/arm/kvm/coproc_a7.c --- linux-3.14.1/arch/arm/kvm/coproc_a7.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/coproc_a7.c 2014-04-13 23:18:35.000000000 +0200 @@ -37,7 +37,7 @@ static const struct coproc_reg a7_regs[] = { /* SCTLR: swapped by interrupt.S. */ { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, - NULL, reset_val, c1_SCTLR, 0x00C50878 }, + access_sctlr, reset_val, c1_SCTLR, 0x00C50878 }, }; static struct kvm_coproc_target_table a7_target_table = { diff -Nur linux-3.14.1/arch/arm/kvm/coproc.c linux-3.15-rc1.orig/arch/arm/kvm/coproc.c --- linux-3.14.1/arch/arm/kvm/coproc.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/coproc.c 2014-04-13 23:18:35.000000000 +0200 @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -205,6 +206,44 @@ } /* + * Generic accessor for VM registers. Only called as long as HCR_TVM + * is set. + */ +static bool access_vm_reg(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + BUG_ON(!p->is_write); + + vcpu->arch.cp15[r->reg] = *vcpu_reg(vcpu, p->Rt1); + if (p->is_64bit) + vcpu->arch.cp15[r->reg + 1] = *vcpu_reg(vcpu, p->Rt2); + + return true; +} + +/* + * SCTLR accessor. Only called as long as HCR_TVM is set. If the + * guest enables the MMU, we stop trapping the VM sys_regs and leave + * it in complete control of the caches. + * + * Used by the cpu-specific code. + */ +bool access_sctlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + access_vm_reg(vcpu, p, r); + + if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */ + vcpu->arch.hcr &= ~HCR_TVM; + stage2_flush_vm(vcpu->kvm); + } + + return true; +} + +/* * We could trap ID_DFR0 and tell the guest we don't support performance * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was * NAKed, so it will read the PMCR anyway. @@ -261,33 +300,36 @@ { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32, NULL, reset_val, c1_CPACR, 0x00000000 }, - /* TTBR0/TTBR1: swapped by interrupt.S. */ - { CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 }, - { CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 }, - - /* TTBCR: swapped by interrupt.S. */ + /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */ + { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 }, + { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32, + access_vm_reg, reset_unknown, c2_TTBR0 }, + { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32, + access_vm_reg, reset_unknown, c2_TTBR1 }, { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32, - NULL, reset_val, c2_TTBCR, 0x00000000 }, + access_vm_reg, reset_val, c2_TTBCR, 0x00000000 }, + { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 }, + /* DACR: swapped by interrupt.S. */ { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32, - NULL, reset_unknown, c3_DACR }, + access_vm_reg, reset_unknown, c3_DACR }, /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */ { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32, - NULL, reset_unknown, c5_DFSR }, + access_vm_reg, reset_unknown, c5_DFSR }, { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32, - NULL, reset_unknown, c5_IFSR }, + access_vm_reg, reset_unknown, c5_IFSR }, { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32, - NULL, reset_unknown, c5_ADFSR }, + access_vm_reg, reset_unknown, c5_ADFSR }, { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32, - NULL, reset_unknown, c5_AIFSR }, + access_vm_reg, reset_unknown, c5_AIFSR }, /* DFAR/IFAR: swapped by interrupt.S. */ { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32, - NULL, reset_unknown, c6_DFAR }, + access_vm_reg, reset_unknown, c6_DFAR }, { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32, - NULL, reset_unknown, c6_IFAR }, + access_vm_reg, reset_unknown, c6_IFAR }, /* PAR swapped by interrupt.S */ { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR }, @@ -324,9 +366,15 @@ /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */ { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32, - NULL, reset_unknown, c10_PRRR}, + access_vm_reg, reset_unknown, c10_PRRR}, { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32, - NULL, reset_unknown, c10_NMRR}, + access_vm_reg, reset_unknown, c10_NMRR}, + + /* AMAIR0/AMAIR1: swapped by interrupt.S. */ + { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32, + access_vm_reg, reset_unknown, c10_AMAIR0}, + { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32, + access_vm_reg, reset_unknown, c10_AMAIR1}, /* VBAR: swapped by interrupt.S. */ { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32, @@ -334,7 +382,7 @@ /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */ { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32, - NULL, reset_val, c13_CID, 0x00000000 }, + access_vm_reg, reset_val, c13_CID, 0x00000000 }, { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32, NULL, reset_unknown, c13_TID_URW }, { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32, @@ -443,7 +491,7 @@ { struct coproc_params params; - params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf; + params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf; params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf; params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0); params.is_64bit = true; @@ -451,7 +499,7 @@ params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf; params.Op2 = 0; params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf; - params.CRn = 0; + params.CRm = 0; return emulate_cp15(vcpu, ¶ms); } diff -Nur linux-3.14.1/arch/arm/kvm/coproc.h linux-3.15-rc1.orig/arch/arm/kvm/coproc.h --- linux-3.14.1/arch/arm/kvm/coproc.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/coproc.h 2014-04-13 23:18:35.000000000 +0200 @@ -58,8 +58,8 @@ { /* Look, we even formatted it for you to paste into the table! */ if (p->is_64bit) { - kvm_pr_unimpl(" { CRm(%2lu), Op1(%2lu), is64, func_%s },\n", - p->CRm, p->Op1, p->is_write ? "write" : "read"); + kvm_pr_unimpl(" { CRm64(%2lu), Op1(%2lu), is64, func_%s },\n", + p->CRn, p->Op1, p->is_write ? "write" : "read"); } else { kvm_pr_unimpl(" { CRn(%2lu), CRm(%2lu), Op1(%2lu), Op2(%2lu), is32," " func_%s },\n", @@ -135,13 +135,13 @@ return -1; if (i1->CRn != i2->CRn) return i1->CRn - i2->CRn; - if (i1->is_64 != i2->is_64) - return i2->is_64 - i1->is_64; if (i1->CRm != i2->CRm) return i1->CRm - i2->CRm; if (i1->Op1 != i2->Op1) return i1->Op1 - i2->Op1; - return i1->Op2 - i2->Op2; + if (i1->Op2 != i2->Op2) + return i1->Op2 - i2->Op2; + return i2->is_64 - i1->is_64; } @@ -153,4 +153,8 @@ #define is64 .is_64 = true #define is32 .is_64 = false +bool access_sctlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r); + #endif /* __ARM_KVM_COPROC_LOCAL_H__ */ diff -Nur linux-3.14.1/arch/arm/kvm/guest.c linux-3.15-rc1.orig/arch/arm/kvm/guest.c --- linux-3.14.1/arch/arm/kvm/guest.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/guest.c 2014-04-13 23:18:35.000000000 +0200 @@ -38,6 +38,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) { + vcpu->arch.hcr = HCR_GUEST_MASK; return 0; } diff -Nur linux-3.14.1/arch/arm/kvm/interrupts_head.S linux-3.15-rc1.orig/arch/arm/kvm/interrupts_head.S --- linux-3.14.1/arch/arm/kvm/interrupts_head.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/interrupts_head.S 2014-04-13 23:18:35.000000000 +0200 @@ -303,13 +303,17 @@ mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL mrrc p15, 0, r4, r5, c7 @ PAR + mrc p15, 0, r6, c10, c3, 0 @ AMAIR0 + mrc p15, 0, r7, c10, c3, 1 @ AMAIR1 .if \store_to_vcpu == 0 - push {r2,r4-r5} + push {r2,r4-r7} .else str r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)] add r12, vcpu, #CP15_OFFSET(c7_PAR) strd r4, r5, [r12] + str r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)] + str r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)] .endif .endm @@ -322,15 +326,19 @@ */ .macro write_cp15_state read_from_vcpu .if \read_from_vcpu == 0 - pop {r2,r4-r5} + pop {r2,r4-r7} .else ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)] add r12, vcpu, #CP15_OFFSET(c7_PAR) ldrd r4, r5, [r12] + ldr r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)] + ldr r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)] .endif mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL mcrr p15, 0, r4, r5, c7 @ PAR + mcr p15, 0, r6, c10, c3, 0 @ AMAIR0 + mcr p15, 0, r7, c10, c3, 1 @ AMAIR1 .if \read_from_vcpu == 0 pop {r2-r12} @@ -597,17 +605,14 @@ /* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */ .macro configure_hyp_role operation - mrc p15, 4, r2, c1, c1, 0 @ HCR - bic r2, r2, #HCR_VIRT_EXCP_MASK - ldr r3, =HCR_GUEST_MASK .if \operation == vmentry - orr r2, r2, r3 + ldr r2, [vcpu, #VCPU_HCR] ldr r3, [vcpu, #VCPU_IRQ_LINES] orr r2, r2, r3 .else - bic r2, r2, r3 + mov r2, #0 .endif - mcr p15, 4, r2, c1, c1, 0 + mcr p15, 4, r2, c1, c1, 0 @ HCR .endm .macro load_vcpu diff -Nur linux-3.14.1/arch/arm/kvm/mmu.c linux-3.15-rc1.orig/arch/arm/kvm/mmu.c --- linux-3.14.1/arch/arm/kvm/mmu.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/kvm/mmu.c 2014-04-13 23:18:35.000000000 +0200 @@ -144,8 +144,9 @@ while (addr < end) { pgd = pgdp + pgd_index(addr); pud = pud_offset(pgd, addr); + pte = NULL; if (pud_none(*pud)) { - addr = pud_addr_end(addr, end); + addr = kvm_pud_addr_end(addr, end); continue; } @@ -155,13 +156,13 @@ * move on. */ clear_pud_entry(kvm, pud, addr); - addr = pud_addr_end(addr, end); + addr = kvm_pud_addr_end(addr, end); continue; } pmd = pmd_offset(pud, addr); if (pmd_none(*pmd)) { - addr = pmd_addr_end(addr, end); + addr = kvm_pmd_addr_end(addr, end); continue; } @@ -174,12 +175,12 @@ /* * If the pmd entry is to be cleared, walk back up the ladder */ - if (kvm_pmd_huge(*pmd) || page_empty(pte)) { + if (kvm_pmd_huge(*pmd) || (pte && page_empty(pte))) { clear_pmd_entry(kvm, pmd, addr); - next = pmd_addr_end(addr, end); + next = kvm_pmd_addr_end(addr, end); if (page_empty(pmd) && !page_empty(pud)) { clear_pud_entry(kvm, pud, addr); - next = pud_addr_end(addr, end); + next = kvm_pud_addr_end(addr, end); } } @@ -187,6 +188,99 @@ } } +static void stage2_flush_ptes(struct kvm *kvm, pmd_t *pmd, + phys_addr_t addr, phys_addr_t end) +{ + pte_t *pte; + + pte = pte_offset_kernel(pmd, addr); + do { + if (!pte_none(*pte)) { + hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT); + kvm_flush_dcache_to_poc((void*)hva, PAGE_SIZE); + } + } while (pte++, addr += PAGE_SIZE, addr != end); +} + +static void stage2_flush_pmds(struct kvm *kvm, pud_t *pud, + phys_addr_t addr, phys_addr_t end) +{ + pmd_t *pmd; + phys_addr_t next; + + pmd = pmd_offset(pud, addr); + do { + next = kvm_pmd_addr_end(addr, end); + if (!pmd_none(*pmd)) { + if (kvm_pmd_huge(*pmd)) { + hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT); + kvm_flush_dcache_to_poc((void*)hva, PMD_SIZE); + } else { + stage2_flush_ptes(kvm, pmd, addr, next); + } + } + } while (pmd++, addr = next, addr != end); +} + +static void stage2_flush_puds(struct kvm *kvm, pgd_t *pgd, + phys_addr_t addr, phys_addr_t end) +{ + pud_t *pud; + phys_addr_t next; + + pud = pud_offset(pgd, addr); + do { + next = kvm_pud_addr_end(addr, end); + if (!pud_none(*pud)) { + if (pud_huge(*pud)) { + hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT); + kvm_flush_dcache_to_poc((void*)hva, PUD_SIZE); + } else { + stage2_flush_pmds(kvm, pud, addr, next); + } + } + } while (pud++, addr = next, addr != end); +} + +static void stage2_flush_memslot(struct kvm *kvm, + struct kvm_memory_slot *memslot) +{ + phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT; + phys_addr_t end = addr + PAGE_SIZE * memslot->npages; + phys_addr_t next; + pgd_t *pgd; + + pgd = kvm->arch.pgd + pgd_index(addr); + do { + next = kvm_pgd_addr_end(addr, end); + stage2_flush_puds(kvm, pgd, addr, next); + } while (pgd++, addr = next, addr != end); +} + +/** + * stage2_flush_vm - Invalidate cache for pages mapped in stage 2 + * @kvm: The struct kvm pointer + * + * Go through the stage 2 page tables and invalidate any cache lines + * backing memory already mapped to the VM. + */ +void stage2_flush_vm(struct kvm *kvm) +{ + struct kvm_memslots *slots; + struct kvm_memory_slot *memslot; + int idx; + + idx = srcu_read_lock(&kvm->srcu); + spin_lock(&kvm->mmu_lock); + + slots = kvm_memslots(kvm); + kvm_for_each_memslot(memslot, slots) + stage2_flush_memslot(kvm, memslot); + + spin_unlock(&kvm->mmu_lock); + srcu_read_unlock(&kvm->srcu, idx); +} + /** * free_boot_hyp_pgd - free HYP boot page tables * @@ -715,7 +809,7 @@ kvm_set_s2pmd_writable(&new_pmd); kvm_set_pfn_dirty(pfn); } - coherent_icache_guest_page(kvm, hva & PMD_MASK, PMD_SIZE); + coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE); ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd); } else { pte_t new_pte = pfn_pte(pfn, PAGE_S2); @@ -723,7 +817,7 @@ kvm_set_s2pte_writable(&new_pte); kvm_set_pfn_dirty(pfn); } - coherent_icache_guest_page(kvm, hva, PAGE_SIZE); + coherent_cache_guest_page(vcpu, hva, PAGE_SIZE); ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, false); } diff -Nur linux-3.14.1/arch/arm/lib/bitops.h linux-3.15-rc1.orig/arch/arm/lib/bitops.h --- linux-3.14.1/arch/arm/lib/bitops.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/lib/bitops.h 2014-04-13 23:18:35.000000000 +0200 @@ -37,6 +37,11 @@ add r1, r1, r0, lsl #2 @ Get word offset mov r3, r2, lsl r3 @ create mask smp_dmb +#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) + .arch_extension mp + ALT_SMP(W(pldw) [r1]) + ALT_UP(W(nop)) +#endif 1: ldrex r2, [r1] ands r0, r2, r3 @ save old value of bit \instr r2, r2, r3 @ toggle bit diff -Nur linux-3.14.1/arch/arm/lib/copy_template.S linux-3.15-rc1.orig/arch/arm/lib/copy_template.S --- linux-3.14.1/arch/arm/lib/copy_template.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/lib/copy_template.S 2014-04-13 23:18:35.000000000 +0200 @@ -197,24 +197,24 @@ 12: PLD( pld [r1, #124] ) 13: ldr4w r1, r4, r5, r6, r7, abort=19f - mov r3, lr, pull #\pull + mov r3, lr, lspull #\pull subs r2, r2, #32 ldr4w r1, r8, r9, ip, lr, abort=19f - orr r3, r3, r4, push #\push - mov r4, r4, pull #\pull - orr r4, r4, r5, push #\push - mov r5, r5, pull #\pull - orr r5, r5, r6, push #\push - mov r6, r6, pull #\pull - orr r6, r6, r7, push #\push - mov r7, r7, pull #\pull - orr r7, r7, r8, push #\push - mov r8, r8, pull #\pull - orr r8, r8, r9, push #\push - mov r9, r9, pull #\pull - orr r9, r9, ip, push #\push - mov ip, ip, pull #\pull - orr ip, ip, lr, push #\push + orr r3, r3, r4, lspush #\push + mov r4, r4, lspull #\pull + orr r4, r4, r5, lspush #\push + mov r5, r5, lspull #\pull + orr r5, r5, r6, lspush #\push + mov r6, r6, lspull #\pull + orr r6, r6, r7, lspush #\push + mov r7, r7, lspull #\pull + orr r7, r7, r8, lspush #\push + mov r8, r8, lspull #\pull + orr r8, r8, r9, lspush #\push + mov r9, r9, lspull #\pull + orr r9, r9, ip, lspush #\push + mov ip, ip, lspull #\pull + orr ip, ip, lr, lspush #\push str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f bge 12b PLD( cmn r2, #96 ) @@ -225,10 +225,10 @@ 14: ands ip, r2, #28 beq 16f -15: mov r3, lr, pull #\pull +15: mov r3, lr, lspull #\pull ldr1w r1, lr, abort=21f subs ip, ip, #4 - orr r3, r3, lr, push #\push + orr r3, r3, lr, lspush #\push str1w r0, r3, abort=21f bgt 15b CALGN( cmp r2, #0 ) diff -Nur linux-3.14.1/arch/arm/lib/csumpartialcopygeneric.S linux-3.15-rc1.orig/arch/arm/lib/csumpartialcopygeneric.S --- linux-3.14.1/arch/arm/lib/csumpartialcopygeneric.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/lib/csumpartialcopygeneric.S 2014-04-13 23:18:35.000000000 +0200 @@ -141,7 +141,7 @@ tst len, #2 mov r5, r4, get_byte_0 beq .Lexit - adcs sum, sum, r4, push #16 + adcs sum, sum, r4, lspush #16 strb r5, [dst], #1 mov r5, r4, get_byte_1 strb r5, [dst], #1 @@ -171,23 +171,23 @@ cmp ip, #2 beq .Lsrc2_aligned bhi .Lsrc3_aligned - mov r4, r5, pull #8 @ C = 0 + mov r4, r5, lspull #8 @ C = 0 bics ip, len, #15 beq 2f 1: load4l r5, r6, r7, r8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 - mov r7, r7, pull #8 - orr r7, r7, r8, push #24 + orr r4, r4, r5, lspush #24 + mov r5, r5, lspull #8 + orr r5, r5, r6, lspush #24 + mov r6, r6, lspull #8 + orr r6, r6, r7, lspush #24 + mov r7, r7, lspull #8 + orr r7, r7, r8, lspush #24 stmia dst!, {r4, r5, r6, r7} adcs sum, sum, r4 adcs sum, sum, r5 adcs sum, sum, r6 adcs sum, sum, r7 - mov r4, r8, pull #8 + mov r4, r8, lspull #8 sub ip, ip, #16 teq ip, #0 bne 1b @@ -196,50 +196,50 @@ tst ip, #8 beq 3f load2l r5, r6 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 + orr r4, r4, r5, lspush #24 + mov r5, r5, lspull #8 + orr r5, r5, r6, lspush #24 stmia dst!, {r4, r5} adcs sum, sum, r4 adcs sum, sum, r5 - mov r4, r6, pull #8 + mov r4, r6, lspull #8 tst ip, #4 beq 4f 3: load1l r5 - orr r4, r4, r5, push #24 + orr r4, r4, r5, lspush #24 str r4, [dst], #4 adcs sum, sum, r4 - mov r4, r5, pull #8 + mov r4, r5, lspull #8 4: ands len, len, #3 beq .Ldone mov r5, r4, get_byte_0 tst len, #2 beq .Lexit - adcs sum, sum, r4, push #16 + adcs sum, sum, r4, lspush #16 strb r5, [dst], #1 mov r5, r4, get_byte_1 strb r5, [dst], #1 mov r5, r4, get_byte_2 b .Lexit -.Lsrc2_aligned: mov r4, r5, pull #16 +.Lsrc2_aligned: mov r4, r5, lspull #16 adds sum, sum, #0 bics ip, len, #15 beq 2f 1: load4l r5, r6, r7, r8 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 - mov r7, r7, pull #16 - orr r7, r7, r8, push #16 + orr r4, r4, r5, lspush #16 + mov r5, r5, lspull #16 + orr r5, r5, r6, lspush #16 + mov r6, r6, lspull #16 + orr r6, r6, r7, lspush #16 + mov r7, r7, lspull #16 + orr r7, r7, r8, lspush #16 stmia dst!, {r4, r5, r6, r7} adcs sum, sum, r4 adcs sum, sum, r5 adcs sum, sum, r6 adcs sum, sum, r7 - mov r4, r8, pull #16 + mov r4, r8, lspull #16 sub ip, ip, #16 teq ip, #0 bne 1b @@ -248,20 +248,20 @@ tst ip, #8 beq 3f load2l r5, r6 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 + orr r4, r4, r5, lspush #16 + mov r5, r5, lspull #16 + orr r5, r5, r6, lspush #16 stmia dst!, {r4, r5} adcs sum, sum, r4 adcs sum, sum, r5 - mov r4, r6, pull #16 + mov r4, r6, lspull #16 tst ip, #4 beq 4f 3: load1l r5 - orr r4, r4, r5, push #16 + orr r4, r4, r5, lspush #16 str r4, [dst], #4 adcs sum, sum, r4 - mov r4, r5, pull #16 + mov r4, r5, lspull #16 4: ands len, len, #3 beq .Ldone mov r5, r4, get_byte_0 @@ -276,24 +276,24 @@ load1b r5 b .Lexit -.Lsrc3_aligned: mov r4, r5, pull #24 +.Lsrc3_aligned: mov r4, r5, lspull #24 adds sum, sum, #0 bics ip, len, #15 beq 2f 1: load4l r5, r6, r7, r8 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 - mov r7, r7, pull #24 - orr r7, r7, r8, push #8 + orr r4, r4, r5, lspush #8 + mov r5, r5, lspull #24 + orr r5, r5, r6, lspush #8 + mov r6, r6, lspull #24 + orr r6, r6, r7, lspush #8 + mov r7, r7, lspull #24 + orr r7, r7, r8, lspush #8 stmia dst!, {r4, r5, r6, r7} adcs sum, sum, r4 adcs sum, sum, r5 adcs sum, sum, r6 adcs sum, sum, r7 - mov r4, r8, pull #24 + mov r4, r8, lspull #24 sub ip, ip, #16 teq ip, #0 bne 1b @@ -302,20 +302,20 @@ tst ip, #8 beq 3f load2l r5, r6 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 + orr r4, r4, r5, lspush #8 + mov r5, r5, lspull #24 + orr r5, r5, r6, lspush #8 stmia dst!, {r4, r5} adcs sum, sum, r4 adcs sum, sum, r5 - mov r4, r6, pull #24 + mov r4, r6, lspull #24 tst ip, #4 beq 4f 3: load1l r5 - orr r4, r4, r5, push #8 + orr r4, r4, r5, lspush #8 str r4, [dst], #4 adcs sum, sum, r4 - mov r4, r5, pull #24 + mov r4, r5, lspull #24 4: ands len, len, #3 beq .Ldone mov r5, r4, get_byte_0 @@ -326,7 +326,7 @@ load1l r4 mov r5, r4, get_byte_0 strb r5, [dst], #1 - adcs sum, sum, r4, push #24 + adcs sum, sum, r4, lspush #24 mov r5, r4, get_byte_1 b .Lexit FN_EXIT diff -Nur linux-3.14.1/arch/arm/lib/io-readsl.S linux-3.15-rc1.orig/arch/arm/lib/io-readsl.S --- linux-3.14.1/arch/arm/lib/io-readsl.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/lib/io-readsl.S 2014-04-13 23:18:35.000000000 +0200 @@ -47,25 +47,25 @@ strb ip, [r1], #1 4: subs r2, r2, #1 - mov ip, r3, pull #24 + mov ip, r3, lspull #24 ldrne r3, [r0] - orrne ip, ip, r3, push #8 + orrne ip, ip, r3, lspush #8 strne ip, [r1], #4 bne 4b b 8f 5: subs r2, r2, #1 - mov ip, r3, pull #16 + mov ip, r3, lspull #16 ldrne r3, [r0] - orrne ip, ip, r3, push #16 + orrne ip, ip, r3, lspush #16 strne ip, [r1], #4 bne 5b b 7f 6: subs r2, r2, #1 - mov ip, r3, pull #8 + mov ip, r3, lspull #8 ldrne r3, [r0] - orrne ip, ip, r3, push #24 + orrne ip, ip, r3, lspush #24 strne ip, [r1], #4 bne 6b diff -Nur linux-3.14.1/arch/arm/lib/io-writesl.S linux-3.15-rc1.orig/arch/arm/lib/io-writesl.S --- linux-3.14.1/arch/arm/lib/io-writesl.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/lib/io-writesl.S 2014-04-13 23:18:35.000000000 +0200 @@ -41,26 +41,26 @@ blt 5f bgt 6f -4: mov ip, r3, pull #16 +4: mov ip, r3, lspull #16 ldr r3, [r1], #4 subs r2, r2, #1 - orr ip, ip, r3, push #16 + orr ip, ip, r3, lspush #16 str ip, [r0] bne 4b mov pc, lr -5: mov ip, r3, pull #8 +5: mov ip, r3, lspull #8 ldr r3, [r1], #4 subs r2, r2, #1 - orr ip, ip, r3, push #24 + orr ip, ip, r3, lspush #24 str ip, [r0] bne 5b mov pc, lr -6: mov ip, r3, pull #24 +6: mov ip, r3, lspull #24 ldr r3, [r1], #4 subs r2, r2, #1 - orr ip, ip, r3, push #8 + orr ip, ip, r3, lspush #8 str ip, [r0] bne 6b mov pc, lr diff -Nur linux-3.14.1/arch/arm/lib/memmove.S linux-3.15-rc1.orig/arch/arm/lib/memmove.S --- linux-3.14.1/arch/arm/lib/memmove.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/lib/memmove.S 2014-04-13 23:18:35.000000000 +0200 @@ -147,24 +147,24 @@ 12: PLD( pld [r1, #-128] ) 13: ldmdb r1!, {r7, r8, r9, ip} - mov lr, r3, push #\push + mov lr, r3, lspush #\push subs r2, r2, #32 ldmdb r1!, {r3, r4, r5, r6} - orr lr, lr, ip, pull #\pull - mov ip, ip, push #\push - orr ip, ip, r9, pull #\pull - mov r9, r9, push #\push - orr r9, r9, r8, pull #\pull - mov r8, r8, push #\push - orr r8, r8, r7, pull #\pull - mov r7, r7, push #\push - orr r7, r7, r6, pull #\pull - mov r6, r6, push #\push - orr r6, r6, r5, pull #\pull - mov r5, r5, push #\push - orr r5, r5, r4, pull #\pull - mov r4, r4, push #\push - orr r4, r4, r3, pull #\pull + orr lr, lr, ip, lspull #\pull + mov ip, ip, lspush #\push + orr ip, ip, r9, lspull #\pull + mov r9, r9, lspush #\push + orr r9, r9, r8, lspull #\pull + mov r8, r8, lspush #\push + orr r8, r8, r7, lspull #\pull + mov r7, r7, lspush #\push + orr r7, r7, r6, lspull #\pull + mov r6, r6, lspush #\push + orr r6, r6, r5, lspull #\pull + mov r5, r5, lspush #\push + orr r5, r5, r4, lspull #\pull + mov r4, r4, lspush #\push + orr r4, r4, r3, lspull #\pull stmdb r0!, {r4 - r9, ip, lr} bge 12b PLD( cmn r2, #96 ) @@ -175,10 +175,10 @@ 14: ands ip, r2, #28 beq 16f -15: mov lr, r3, push #\push +15: mov lr, r3, lspush #\push ldr r3, [r1, #-4]! subs ip, ip, #4 - orr lr, lr, r3, pull #\pull + orr lr, lr, r3, lspull #\pull str lr, [r0, #-4]! bgt 15b CALGN( cmp r2, #0 ) diff -Nur linux-3.14.1/arch/arm/lib/uaccess.S linux-3.15-rc1.orig/arch/arm/lib/uaccess.S --- linux-3.14.1/arch/arm/lib/uaccess.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/lib/uaccess.S 2014-04-13 23:18:35.000000000 +0200 @@ -117,9 +117,9 @@ .Lc2u_1fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .Lc2u_1nowords - mov r3, r7, pull #8 + mov r3, r7, lspull #8 ldr r7, [r1], #4 - orr r3, r3, r7, push #24 + orr r3, r3, r7, lspush #24 USER( TUSER( str) r3, [r0], #4) @ May fault mov ip, r0, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -131,30 +131,30 @@ subs ip, ip, #16 blt .Lc2u_1rem8lp -.Lc2u_1cpy8lp: mov r3, r7, pull #8 +.Lc2u_1cpy8lp: mov r3, r7, lspull #8 ldmia r1!, {r4 - r7} subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 + orr r3, r3, r4, lspush #24 + mov r4, r4, lspull #8 + orr r4, r4, r5, lspush #24 + mov r5, r5, lspull #8 + orr r5, r5, r6, lspush #24 + mov r6, r6, lspull #8 + orr r6, r6, r7, lspush #24 stmia r0!, {r3 - r6} @ Shouldnt fault bpl .Lc2u_1cpy8lp .Lc2u_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 + movne r3, r7, lspull #8 ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 + orrne r3, r3, r4, lspush #24 + movne r4, r4, lspull #8 + orrne r4, r4, r7, lspush #24 stmneia r0!, {r3 - r4} @ Shouldnt fault tst ip, #4 - movne r3, r7, pull #8 + movne r3, r7, lspull #8 ldrne r7, [r1], #4 - orrne r3, r3, r7, push #24 + orrne r3, r3, r7, lspush #24 TUSER( strne) r3, [r0], #4 @ Shouldnt fault ands ip, ip, #3 beq .Lc2u_1fupi @@ -172,9 +172,9 @@ .Lc2u_2fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .Lc2u_2nowords - mov r3, r7, pull #16 + mov r3, r7, lspull #16 ldr r7, [r1], #4 - orr r3, r3, r7, push #16 + orr r3, r3, r7, lspush #16 USER( TUSER( str) r3, [r0], #4) @ May fault mov ip, r0, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -186,30 +186,30 @@ subs ip, ip, #16 blt .Lc2u_2rem8lp -.Lc2u_2cpy8lp: mov r3, r7, pull #16 +.Lc2u_2cpy8lp: mov r3, r7, lspull #16 ldmia r1!, {r4 - r7} subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 + orr r3, r3, r4, lspush #16 + mov r4, r4, lspull #16 + orr r4, r4, r5, lspush #16 + mov r5, r5, lspull #16 + orr r5, r5, r6, lspush #16 + mov r6, r6, lspull #16 + orr r6, r6, r7, lspush #16 stmia r0!, {r3 - r6} @ Shouldnt fault bpl .Lc2u_2cpy8lp .Lc2u_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 + movne r3, r7, lspull #16 ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 + orrne r3, r3, r4, lspush #16 + movne r4, r4, lspull #16 + orrne r4, r4, r7, lspush #16 stmneia r0!, {r3 - r4} @ Shouldnt fault tst ip, #4 - movne r3, r7, pull #16 + movne r3, r7, lspull #16 ldrne r7, [r1], #4 - orrne r3, r3, r7, push #16 + orrne r3, r3, r7, lspush #16 TUSER( strne) r3, [r0], #4 @ Shouldnt fault ands ip, ip, #3 beq .Lc2u_2fupi @@ -227,9 +227,9 @@ .Lc2u_3fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .Lc2u_3nowords - mov r3, r7, pull #24 + mov r3, r7, lspull #24 ldr r7, [r1], #4 - orr r3, r3, r7, push #8 + orr r3, r3, r7, lspush #8 USER( TUSER( str) r3, [r0], #4) @ May fault mov ip, r0, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -241,30 +241,30 @@ subs ip, ip, #16 blt .Lc2u_3rem8lp -.Lc2u_3cpy8lp: mov r3, r7, pull #24 +.Lc2u_3cpy8lp: mov r3, r7, lspull #24 ldmia r1!, {r4 - r7} subs ip, ip, #16 - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 + orr r3, r3, r4, lspush #8 + mov r4, r4, lspull #24 + orr r4, r4, r5, lspush #8 + mov r5, r5, lspull #24 + orr r5, r5, r6, lspush #8 + mov r6, r6, lspull #24 + orr r6, r6, r7, lspush #8 stmia r0!, {r3 - r6} @ Shouldnt fault bpl .Lc2u_3cpy8lp .Lc2u_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 + movne r3, r7, lspull #24 ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 + orrne r3, r3, r4, lspush #8 + movne r4, r4, lspull #24 + orrne r4, r4, r7, lspush #8 stmneia r0!, {r3 - r4} @ Shouldnt fault tst ip, #4 - movne r3, r7, pull #24 + movne r3, r7, lspull #24 ldrne r7, [r1], #4 - orrne r3, r3, r7, push #8 + orrne r3, r3, r7, lspush #8 TUSER( strne) r3, [r0], #4 @ Shouldnt fault ands ip, ip, #3 beq .Lc2u_3fupi @@ -382,9 +382,9 @@ .Lcfu_1fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .Lcfu_1nowords - mov r3, r7, pull #8 + mov r3, r7, lspull #8 USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #24 + orr r3, r3, r7, lspush #24 str r3, [r0], #4 mov ip, r1, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -396,30 +396,30 @@ subs ip, ip, #16 blt .Lcfu_1rem8lp -.Lcfu_1cpy8lp: mov r3, r7, pull #8 +.Lcfu_1cpy8lp: mov r3, r7, lspull #8 ldmia r1!, {r4 - r7} @ Shouldnt fault subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 + orr r3, r3, r4, lspush #24 + mov r4, r4, lspull #8 + orr r4, r4, r5, lspush #24 + mov r5, r5, lspull #8 + orr r5, r5, r6, lspush #24 + mov r6, r6, lspull #8 + orr r6, r6, r7, lspush #24 stmia r0!, {r3 - r6} bpl .Lcfu_1cpy8lp .Lcfu_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 + movne r3, r7, lspull #8 ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 + orrne r3, r3, r4, lspush #24 + movne r4, r4, lspull #8 + orrne r4, r4, r7, lspush #24 stmneia r0!, {r3 - r4} tst ip, #4 - movne r3, r7, pull #8 + movne r3, r7, lspull #8 USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #24 + orrne r3, r3, r7, lspush #24 strne r3, [r0], #4 ands ip, ip, #3 beq .Lcfu_1fupi @@ -437,9 +437,9 @@ .Lcfu_2fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .Lcfu_2nowords - mov r3, r7, pull #16 + mov r3, r7, lspull #16 USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #16 + orr r3, r3, r7, lspush #16 str r3, [r0], #4 mov ip, r1, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -452,30 +452,30 @@ blt .Lcfu_2rem8lp -.Lcfu_2cpy8lp: mov r3, r7, pull #16 +.Lcfu_2cpy8lp: mov r3, r7, lspull #16 ldmia r1!, {r4 - r7} @ Shouldnt fault subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 + orr r3, r3, r4, lspush #16 + mov r4, r4, lspull #16 + orr r4, r4, r5, lspush #16 + mov r5, r5, lspull #16 + orr r5, r5, r6, lspush #16 + mov r6, r6, lspull #16 + orr r6, r6, r7, lspush #16 stmia r0!, {r3 - r6} bpl .Lcfu_2cpy8lp .Lcfu_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 + movne r3, r7, lspull #16 ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 + orrne r3, r3, r4, lspush #16 + movne r4, r4, lspull #16 + orrne r4, r4, r7, lspush #16 stmneia r0!, {r3 - r4} tst ip, #4 - movne r3, r7, pull #16 + movne r3, r7, lspull #16 USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #16 + orrne r3, r3, r7, lspush #16 strne r3, [r0], #4 ands ip, ip, #3 beq .Lcfu_2fupi @@ -493,9 +493,9 @@ .Lcfu_3fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .Lcfu_3nowords - mov r3, r7, pull #24 + mov r3, r7, lspull #24 USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #8 + orr r3, r3, r7, lspush #8 str r3, [r0], #4 mov ip, r1, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -507,30 +507,30 @@ subs ip, ip, #16 blt .Lcfu_3rem8lp -.Lcfu_3cpy8lp: mov r3, r7, pull #24 +.Lcfu_3cpy8lp: mov r3, r7, lspull #24 ldmia r1!, {r4 - r7} @ Shouldnt fault - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 + orr r3, r3, r4, lspush #8 + mov r4, r4, lspull #24 + orr r4, r4, r5, lspush #8 + mov r5, r5, lspull #24 + orr r5, r5, r6, lspush #8 + mov r6, r6, lspull #24 + orr r6, r6, r7, lspush #8 stmia r0!, {r3 - r6} subs ip, ip, #16 bpl .Lcfu_3cpy8lp .Lcfu_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 + movne r3, r7, lspull #24 ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 + orrne r3, r3, r4, lspush #8 + movne r4, r4, lspull #24 + orrne r4, r4, r7, lspush #8 stmneia r0!, {r3 - r4} tst ip, #4 - movne r3, r7, pull #24 + movne r3, r7, lspull #24 USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #8 + orrne r3, r3, r7, lspush #8 strne r3, [r0], #4 ands ip, ip, #3 beq .Lcfu_3fupi diff -Nur linux-3.14.1/arch/arm/mach-at91/at91rm9200.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91rm9200.c --- linux-3.14.1/arch/arm/mach-at91/at91rm9200.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91rm9200.c 2014-04-13 23:18:35.000000000 +0200 @@ -21,6 +21,7 @@ #include #include #include +#include #include "at91_aic.h" #include "soc.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/at91rm9200_devices.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91rm9200_devices.c --- linux-3.14.1/arch/arm/mach-at91/at91rm9200_devices.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91rm9200_devices.c 2014-04-13 23:18:35.000000000 +0200 @@ -21,6 +21,7 @@ #include #include #include +#include #include "board.h" #include "generic.h" @@ -922,6 +923,7 @@ static struct atmel_uart_data dbgu_data = { .use_dma_tx = 0, .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .rts_gpio = -EINVAL, }; static u64 dbgu_dmamask = DMA_BIT_MASK(32); @@ -960,6 +962,7 @@ static struct atmel_uart_data uart0_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart0_dmamask = DMA_BIT_MASK(32); @@ -987,9 +990,10 @@ if (pins & ATMEL_UART_RTS) { /* * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. - * We need to drive the pin manually. Default is off (RTS is active low). + * We need to drive the pin manually. The serial driver will driver + * this to high when initializing. */ - at91_set_gpio_output(AT91_PIN_PA21, 1); + uart0_data.rts_gpio = AT91_PIN_PA21; } } @@ -1009,6 +1013,7 @@ static struct atmel_uart_data uart1_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart1_dmamask = DMA_BIT_MASK(32); @@ -1060,6 +1065,7 @@ static struct atmel_uart_data uart2_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart2_dmamask = DMA_BIT_MASK(32); @@ -1103,6 +1109,7 @@ static struct atmel_uart_data uart3_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart3_dmamask = DMA_BIT_MASK(32); diff -Nur linux-3.14.1/arch/arm/mach-at91/at91rm9200_time.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91rm9200_time.c --- linux-3.14.1/arch/arm/mach-at91/at91rm9200_time.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91rm9200_time.c 2014-04-13 23:18:35.000000000 +0200 @@ -31,6 +31,7 @@ #include #include +#include static unsigned long last_crtr; static u32 irqmask; diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9260.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9260.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9260.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9260.c 2014-04-13 23:18:35.000000000 +0200 @@ -21,6 +21,7 @@ #include #include #include +#include #include "at91_aic.h" #include "at91_rstc.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9260_devices.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9260_devices.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9260_devices.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9260_devices.c 2014-04-13 23:18:35.000000000 +0200 @@ -25,6 +25,7 @@ #include #include #include +#include #include "board.h" #include "generic.h" @@ -819,6 +820,7 @@ static struct atmel_uart_data dbgu_data = { .use_dma_tx = 0, .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .rts_gpio = -EINVAL, }; static u64 dbgu_dmamask = DMA_BIT_MASK(32); @@ -857,6 +859,7 @@ static struct atmel_uart_data uart0_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart0_dmamask = DMA_BIT_MASK(32); @@ -908,6 +911,7 @@ static struct atmel_uart_data uart1_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart1_dmamask = DMA_BIT_MASK(32); @@ -951,6 +955,7 @@ static struct atmel_uart_data uart2_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart2_dmamask = DMA_BIT_MASK(32); @@ -994,6 +999,7 @@ static struct atmel_uart_data uart3_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart3_dmamask = DMA_BIT_MASK(32); @@ -1037,6 +1043,7 @@ static struct atmel_uart_data uart4_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart4_dmamask = DMA_BIT_MASK(32); @@ -1075,6 +1082,7 @@ static struct atmel_uart_data uart5_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart5_dmamask = DMA_BIT_MASK(32); @@ -1255,12 +1263,8 @@ at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */ at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */ - if (data->flags & AT91_CF_TRUE_IDE) -#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) + if (IS_ENABLED(CONFIG_PATA_AT91) && (data->flags & AT91_CF_TRUE_IDE)) pdev->name = "pata_at91"; -#else -#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91" -#endif else pdev->name = "at91_cf"; diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9261.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9261.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9261.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9261.c 2014-04-13 23:18:35.000000000 +0200 @@ -20,15 +20,18 @@ #include #include #include +#include #include "at91_aic.h" #include "at91_rstc.h" #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" #include "pm.h" +#if defined(CONFIG_OLD_CLK_AT91) +#include "clock.h" + /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -189,6 +192,23 @@ CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), + /* more lookup table for DT entries */ + CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), + CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), + CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk), + CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk), + CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk), + CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk), + CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk), + CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0), + CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1), + CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk), + CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk), + CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk), + CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -247,7 +267,9 @@ clk_register(&hck0); clk_register(&hck1); } - +#else +#define at91sam9261_register_clocks NULL +#endif /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9261_devices.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9261_devices.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9261_devices.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9261_devices.c 2014-04-13 23:18:35.000000000 +0200 @@ -25,6 +25,7 @@ #include #include #include +#include #include "board.h" #include "generic.h" @@ -880,6 +881,7 @@ static struct atmel_uart_data dbgu_data = { .use_dma_tx = 0, .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .rts_gpio = -EINVAL, }; static u64 dbgu_dmamask = DMA_BIT_MASK(32); @@ -918,6 +920,7 @@ static struct atmel_uart_data uart0_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart0_dmamask = DMA_BIT_MASK(32); @@ -961,6 +964,7 @@ static struct atmel_uart_data uart1_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart1_dmamask = DMA_BIT_MASK(32); @@ -1004,6 +1008,7 @@ static struct atmel_uart_data uart2_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart2_dmamask = DMA_BIT_MASK(32); diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9263.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9263.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9263.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9263.c 2014-04-13 23:18:35.000000000 +0200 @@ -19,6 +19,7 @@ #include #include #include +#include #include "at91_aic.h" #include "at91_rstc.h" @@ -223,6 +224,7 @@ CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk), CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk), CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk), + CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9263_devices.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9263_devices.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9263_devices.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9263_devices.c 2014-04-13 23:18:35.000000000 +0200 @@ -24,6 +24,7 @@ #include #include #include +#include #include "board.h" #include "generic.h" @@ -1324,6 +1325,7 @@ static struct atmel_uart_data dbgu_data = { .use_dma_tx = 0, .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .rts_gpio = -EINVAL, }; static u64 dbgu_dmamask = DMA_BIT_MASK(32); @@ -1362,6 +1364,7 @@ static struct atmel_uart_data uart0_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart0_dmamask = DMA_BIT_MASK(32); @@ -1405,6 +1408,7 @@ static struct atmel_uart_data uart1_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart1_dmamask = DMA_BIT_MASK(32); @@ -1448,6 +1452,7 @@ static struct atmel_uart_data uart2_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart2_dmamask = DMA_BIT_MASK(32); diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam926x_time.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam926x_time.c --- linux-3.14.1/arch/arm/mach-at91/at91sam926x_time.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam926x_time.c 2014-04-13 23:18:35.000000000 +0200 @@ -19,6 +19,7 @@ #include #include +#include #define AT91_PIT_MR 0x00 /* Mode Register */ #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9g45.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9g45.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9g45.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9g45.c 2014-04-13 23:18:35.000000000 +0200 @@ -20,6 +20,7 @@ #include #include #include +#include #include "at91_aic.h" #include "soc.h" @@ -284,6 +285,7 @@ CLKDEV_CON_ID("pioE", &pioDE_clk), /* Fake adc clock */ CLKDEV_CON_ID("adc_clk", &tsc_clk), + CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9g45_devices.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9g45_devices.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9g45_devices.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9g45_devices.c 2014-04-13 23:18:35.000000000 +0200 @@ -32,6 +32,7 @@ #include #include #include +#include #include @@ -1587,6 +1588,7 @@ static struct atmel_uart_data dbgu_data = { .use_dma_tx = 0, .use_dma_rx = 0, + .rts_gpio = -EINVAL, }; static u64 dbgu_dmamask = DMA_BIT_MASK(32); @@ -1625,6 +1627,7 @@ static struct atmel_uart_data uart0_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart0_dmamask = DMA_BIT_MASK(32); @@ -1668,6 +1671,7 @@ static struct atmel_uart_data uart1_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart1_dmamask = DMA_BIT_MASK(32); @@ -1711,6 +1715,7 @@ static struct atmel_uart_data uart2_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart2_dmamask = DMA_BIT_MASK(32); @@ -1754,6 +1759,7 @@ static struct atmel_uart_data uart3_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart3_dmamask = DMA_BIT_MASK(32); diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9n12.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9n12.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9n12.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9n12.c 2014-04-13 23:18:35.000000000 +0200 @@ -182,6 +182,7 @@ /* additional fake clock for macb_hclk */ CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk), CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk), + CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk), }; /* diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9rl.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9rl.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9rl.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9rl.c 2014-04-13 23:18:35.000000000 +0200 @@ -20,18 +20,20 @@ #include #include #include +#include #include "at91_aic.h" #include "at91_rstc.h" #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" #include "pm.h" /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ +#if defined(CONFIG_OLD_CLK_AT91) +#include "clock.h" /* * The peripheral clocks. @@ -196,6 +198,24 @@ CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), CLKDEV_CON_ID("pioD", &pioD_clk), + /* more lookup table for DT entries */ + CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), + CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), + CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk), + CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk), + CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk), + CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk), + CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk), + CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk), + CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk), + CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk), + CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk), + CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk), + CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -238,6 +258,7 @@ clk_register(&pck0); clk_register(&pck1); } +#endif /* -------------------------------------------------------------------- * GPIO @@ -350,6 +371,8 @@ .default_irq_priority = at91sam9rl_default_irq_priority, .extern_irq = (1 << AT91SAM9RL_ID_IRQ0), .ioremap_registers = at91sam9rl_ioremap_registers, +#if defined(CONFIG_OLD_CLK_AT91) .register_clocks = at91sam9rl_register_clocks, +#endif .init = at91sam9rl_initialize, AT91_SOC_END diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9rl_devices.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9rl_devices.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9rl_devices.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9rl_devices.c 2014-04-13 23:18:35.000000000 +0200 @@ -21,6 +21,7 @@ #include #include #include +#include #include #include "board.h" @@ -956,6 +957,7 @@ static struct atmel_uart_data dbgu_data = { .use_dma_tx = 0, .use_dma_rx = 0, /* DBGU not capable of receive DMA */ + .rts_gpio = -EINVAL, }; static u64 dbgu_dmamask = DMA_BIT_MASK(32); @@ -994,6 +996,7 @@ static struct atmel_uart_data uart0_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart0_dmamask = DMA_BIT_MASK(32); @@ -1045,6 +1048,7 @@ static struct atmel_uart_data uart1_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart1_dmamask = DMA_BIT_MASK(32); @@ -1088,6 +1092,7 @@ static struct atmel_uart_data uart2_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart2_dmamask = DMA_BIT_MASK(32); @@ -1131,6 +1136,7 @@ static struct atmel_uart_data uart3_data = { .use_dma_tx = 1, .use_dma_rx = 1, + .rts_gpio = -EINVAL, }; static u64 uart3_dmamask = DMA_BIT_MASK(32); diff -Nur linux-3.14.1/arch/arm/mach-at91/at91sam9x5.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9x5.c --- linux-3.14.1/arch/arm/mach-at91/at91sam9x5.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91sam9x5.c 2014-04-13 23:18:35.000000000 +0200 @@ -253,6 +253,7 @@ CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), + CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk), }; /* diff -Nur linux-3.14.1/arch/arm/mach-at91/at91x40.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91x40.c --- linux-3.14.1/arch/arm/mach-at91/at91x40.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91x40.c 2014-04-13 23:18:35.000000000 +0200 @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include "at91_aic.h" #include "generic.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/at91x40_time.c linux-3.15-rc1.orig/arch/arm/mach-at91/at91x40_time.c --- linux-3.14.1/arch/arm/mach-at91/at91x40_time.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/at91x40_time.c 2014-04-13 23:18:35.000000000 +0200 @@ -25,6 +25,7 @@ #include #include #include +#include #include #include "at91_tc.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/board-dt-sam9.c linux-3.15-rc1.orig/arch/arm/mach-at91/board-dt-sam9.c --- linux-3.14.1/arch/arm/mach-at91/board-dt-sam9.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/board-dt-sam9.c 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -25,6 +26,14 @@ #include "generic.h" +static void __init sam9_dt_timer_init(void) +{ +#if defined(CONFIG_COMMON_CLK) + of_clk_init(NULL); +#endif + at91sam926x_pit_init(); +} + static const struct of_device_id irq_of_match[] __initconst = { { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init }, @@ -43,7 +52,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") /* Maintainer: Atmel */ - .init_time = at91sam926x_pit_init, + .init_time = sam9_dt_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = at91_dt_initialize, diff -Nur linux-3.14.1/arch/arm/mach-at91/board-gsia18s.c linux-3.15-rc1.orig/arch/arm/mach-at91/board-gsia18s.c --- linux-3.14.1/arch/arm/mach-at91/board-gsia18s.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/board-gsia18s.c 2014-04-13 23:18:35.000000000 +0200 @@ -31,6 +31,7 @@ #include #include +#include #include "at91_aic.h" #include "board.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/board-pcontrol-g20.c linux-3.15-rc1.orig/arch/arm/mach-at91/board-pcontrol-g20.c --- linux-3.14.1/arch/arm/mach-at91/board-pcontrol-g20.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/board-pcontrol-g20.c 2014-04-13 23:18:35.000000000 +0200 @@ -30,6 +30,7 @@ #include #include +#include #include "at91_aic.h" #include "board.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/board-stamp9g20.c linux-3.15-rc1.orig/arch/arm/mach-at91/board-stamp9g20.c --- linux-3.14.1/arch/arm/mach-at91/board-stamp9g20.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/board-stamp9g20.c 2014-04-13 23:18:35.000000000 +0200 @@ -26,6 +26,7 @@ #include #include +#include #include "at91_aic.h" #include "board.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/include/mach/at91x40.h linux-3.15-rc1.orig/arch/arm/mach-at91/include/mach/at91x40.h --- linux-3.14.1/arch/arm/mach-at91/include/mach/at91x40.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/include/mach/at91x40.h 2014-04-13 23:18:35.000000000 +0200 @@ -55,4 +55,6 @@ #define AT91_PS_CR (AT91_PS + 0) /* PS Control register */ #define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */ +#define AT91X40_MASTER_CLOCK 40000000 + #endif /* AT91X40_H */ diff -Nur linux-3.14.1/arch/arm/mach-at91/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-at91/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-at91/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/timex.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#include - -#ifdef CONFIG_ARCH_AT91X40 - -#define AT91X40_MASTER_CLOCK 40000000 -#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) - -#else - -#define CLOCK_TICK_RATE 12345678 - -#endif - -#endif /* __ASM_ARCH_TIMEX_H */ diff -Nur linux-3.14.1/arch/arm/mach-at91/Kconfig linux-3.15-rc1.orig/arch/arm/mach-at91/Kconfig --- linux-3.14.1/arch/arm/mach-at91/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -57,6 +57,7 @@ select GENERIC_CLOCKEVENTS select MULTI_IRQ_HANDLER select SPARSE_IRQ + select USE_OF menu "Atmel AT91 System-on-Chip" @@ -64,11 +65,22 @@ prompt "Core type" +config ARCH_AT91X40 + bool "ARM7 AT91X40" + depends on !MMU + select CPU_ARM7TDMI + select ARCH_USES_GETTIMEOFFSET + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + + help + Select this if you are using one of Atmel's AT91X40 SoC. + config SOC_SAM_V4_V5 - bool "ARM7/ARM9" + bool "ARM9 AT91SAM9/AT91RM9200" help - Select this if you are using one of Atmel's AT91SAM9, AT91RM9200 - or AT91X40 SoC. + Select this if you are using one of Atmel's AT91SAM9 or + AT91RM9200 SoC. config SOC_SAM_V7 bool "Cortex A5" @@ -119,7 +131,6 @@ select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 - select AT91_USE_OLD_CLK select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. @@ -137,7 +148,6 @@ select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 - select AT91_USE_OLD_CLK select HAVE_AT91_UTMI config SOC_AT91SAM9G45 @@ -179,9 +189,12 @@ Select this if you are using Atmel's AT91SAM9N12 SoC. # ---------------------------------------------------------- +endif # SOC_SAM_V4_V5 + +if SOC_SAM_V4_V5 || ARCH_AT91X40 source arch/arm/mach-at91/Kconfig.non_dt -endif # SOC_SAM_V4_V5 +endif comment "Generic Board Type" diff -Nur linux-3.14.1/arch/arm/mach-at91/Kconfig.non_dt linux-3.15-rc1.orig/arch/arm/mach-at91/Kconfig.non_dt --- linux-3.14.1/arch/arm/mach-at91/Kconfig.non_dt 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/Kconfig.non_dt 2014-04-13 23:18:35.000000000 +0200 @@ -5,6 +5,7 @@ choice prompt "Atmel AT91 Processor Devices for non DT boards" + depends on !ARCH_AT91X40 config ARCH_AT91_NONE bool "None" @@ -39,13 +40,6 @@ select SOC_AT91SAM9G45 select AT91_USE_OLD_CLK -config ARCH_AT91X40 - bool "AT91x40" - depends on !MMU - select ARCH_USES_GETTIMEOFFSET - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - endchoice config ARCH_AT91SAM9G20 diff -Nur linux-3.14.1/arch/arm/mach-at91/pm.c linux-3.15-rc1.orig/arch/arm/mach-at91/pm.c --- linux-3.14.1/arch/arm/mach-at91/pm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/pm.c 2014-04-13 23:18:35.000000000 +0200 @@ -27,6 +27,7 @@ #include #include +#include #include "at91_aic.h" #include "generic.h" diff -Nur linux-3.14.1/arch/arm/mach-at91/sam9_smc.c linux-3.15-rc1.orig/arch/arm/mach-at91/sam9_smc.c --- linux-3.14.1/arch/arm/mach-at91/sam9_smc.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/sam9_smc.c 2014-04-13 23:18:35.000000000 +0200 @@ -36,6 +36,7 @@ { sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); } +EXPORT_SYMBOL_GPL(sam9_smc_write_mode); static void sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config *config) @@ -69,6 +70,7 @@ { sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); } +EXPORT_SYMBOL_GPL(sam9_smc_configure); static void sam9_smc_cs_read_mode(void __iomem *base, struct sam9_smc_config *config) @@ -84,6 +86,7 @@ { sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); } +EXPORT_SYMBOL_GPL(sam9_smc_read_mode); static void sam9_smc_cs_read(void __iomem *base, struct sam9_smc_config *config) diff -Nur linux-3.14.1/arch/arm/mach-at91/setup.c linux-3.15-rc1.orig/arch/arm/mach-at91/setup.c --- linux-3.14.1/arch/arm/mach-at91/setup.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-at91/setup.c 2014-04-13 23:18:35.000000000 +0200 @@ -351,7 +351,7 @@ panic("Impossible to ioremap at91_matrix_base\n"); } -#if defined(CONFIG_OF) +#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40) static struct of_device_id rstc_ids[] = { { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart }, { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart }, diff -Nur linux-3.14.1/arch/arm/mach-bcm/bcm_5301x.c linux-3.15-rc1.orig/arch/arm/mach-bcm/bcm_5301x.c --- linux-3.14.1/arch/arm/mach-bcm/bcm_5301x.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/bcm_5301x.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,61 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * + * Copyright 2013 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include +#include + +#include +#include +#include + + +static bool first_fault = true; + +static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + if (fsr == 0x1c06 && first_fault) { + first_fault = false; + + /* + * These faults with code 0x1c06 happens for no good reason, + * possibly left over from the CFE boot loader. + */ + pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n", + addr, fsr); + + /* Returning non-zero causes fault display and panic */ + return 0; + } + + /* Others should cause a fault */ + return 1; +} + +static void __init bcm5301x_init_early(void) +{ + /* Install our hook */ + hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR, + "imprecise external abort"); +} + +static void __init bcm5301x_dt_init(void) +{ + l2x0_of_init(0, ~0UL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char __initconst *bcm5301x_dt_compat[] = { + "brcm,bcm4708", + NULL, +}; + +DT_MACHINE_START(BCM5301X, "BCM5301X") + .init_early = bcm5301x_init_early, + .init_machine = bcm5301x_dt_init, + .dt_compat = bcm5301x_dt_compat, +MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-bcm/board_bcm21664.c linux-3.15-rc1.orig/arch/arm/mach-bcm/board_bcm21664.c --- linux-3.14.1/arch/arm/mach-bcm/board_bcm21664.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/board_bcm21664.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include + +#include "bcm_kona_smc.h" +#include "kona.h" + +#define RSTMGR_DT_STRING "brcm,bcm21664-resetmgr" + +#define RSTMGR_REG_WR_ACCESS_OFFSET 0 +#define RSTMGR_REG_CHIP_SOFT_RST_OFFSET 4 + +#define RSTMGR_WR_PASSWORD 0xa5a5 +#define RSTMGR_WR_PASSWORD_SHIFT 8 +#define RSTMGR_WR_ACCESS_ENABLE 1 + +static void bcm21664_restart(enum reboot_mode mode, const char *cmd) +{ + void __iomem *base; + struct device_node *resetmgr; + + resetmgr = of_find_compatible_node(NULL, NULL, RSTMGR_DT_STRING); + if (!resetmgr) { + pr_emerg("Couldn't find " RSTMGR_DT_STRING "\n"); + return; + } + base = of_iomap(resetmgr, 0); + if (!base) { + pr_emerg("Couldn't map " RSTMGR_DT_STRING "\n"); + return; + } + + /* + * A soft reset is triggered by writing a 0 to bit 0 of the soft reset + * register. To write to that register we must first write the password + * and the enable bit in the write access enable register. + */ + writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) | + RSTMGR_WR_ACCESS_ENABLE, + base + RSTMGR_REG_WR_ACCESS_OFFSET); + writel(0, base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET); + + /* Wait for reset */ + while (1); +} + +static void __init bcm21664_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, + &platform_bus); + kona_l2_cache_init(); +} + +static const char * const bcm21664_dt_compat[] = { + "brcm,bcm21664", + NULL, +}; + +DT_MACHINE_START(BCM21664_DT, "BCM21664 Broadcom Application Processor") + .init_machine = bcm21664_init, + .restart = bcm21664_restart, + .dt_compat = bcm21664_dt_compat, +MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-bcm/board_bcm281xx.c linux-3.15-rc1.orig/arch/arm/mach-bcm/board_bcm281xx.c --- linux-3.14.1/arch/arm/mach-bcm/board_bcm281xx.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/board_bcm281xx.c 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012-2013 Broadcom Corporation + * Copyright (C) 2012-2014 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -11,64 +11,65 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include #include +#include +#include #include -#include -#include -#include "bcm_kona_smc.h" #include "kona.h" -static int __init kona_l2_cache_init(void) -{ - if (!IS_ENABLED(CONFIG_CACHE_L2X0)) - return 0; +#define SECWDOG_OFFSET 0x00000000 +#define SECWDOG_RESERVED_MASK 0xe2000000 +#define SECWDOG_WD_LOAD_FLAG_MASK 0x10000000 +#define SECWDOG_EN_MASK 0x08000000 +#define SECWDOG_SRSTEN_MASK 0x04000000 +#define SECWDOG_CLKS_SHIFT 20 +#define SECWDOG_COUNT_SHIFT 0 - if (bcm_kona_smc_init() < 0) { - pr_info("Kona secure API not available. Skipping L2 init\n"); - return 0; +static void bcm281xx_restart(enum reboot_mode mode, const char *cmd) +{ + uint32_t val; + void __iomem *base; + struct device_node *np_wdog; + + np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt"); + if (!np_wdog) { + pr_emerg("Couldn't find brcm,kona-wdt\n"); + return; + } + base = of_iomap(np_wdog, 0); + if (!base) { + pr_emerg("Couldn't map brcm,kona-wdt\n"); + return; } - bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); - - /* - * The aux_val and aux_mask have no effect since L2 cache is already - * enabled. Pass 0s for aux_val and 1s for aux_mask for default value. - */ - return l2x0_of_init(0, ~0); -} - -static void bcm_board_setup_restart(void) -{ - struct device_node *np; + /* Enable watchdog with short timeout (244us). */ + val = readl(base + SECWDOG_OFFSET); + val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK; + val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK | + (0x15 << SECWDOG_CLKS_SHIFT) | + (0x8 << SECWDOG_COUNT_SHIFT); + writel(val, base + SECWDOG_OFFSET); - np = of_find_compatible_node(NULL, NULL, "brcm,bcm11351"); - if (np) { - if (of_device_is_available(np)) - bcm_kona_setup_restart(); - of_node_put(np); - } - /* Restart setup for other boards goes here */ + /* Wait for reset */ + while (1); } -static void __init board_init(void) +static void __init bcm281xx_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, &platform_bus); - - bcm_board_setup_restart(); kona_l2_cache_init(); } -static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, }; - -DT_MACHINE_START(BCM11351_DT, "BCM281xx Broadcom Application Processor") - .init_machine = board_init, - .restart = bcm_kona_restart, - .dt_compat = bcm11351_dt_compat, +static const char * const bcm281xx_dt_compat[] = { + "brcm,bcm11351", /* Have to use the first number upstreamed */ + NULL, +}; + +DT_MACHINE_START(BCM281XX_DT, "BCM281xx Broadcom Application Processor") + .init_machine = bcm281xx_init, + .restart = bcm281xx_restart, + .dt_compat = bcm281xx_dt_compat, MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-bcm/board_bcm2835.c linux-3.15-rc1.orig/arch/arm/mach-bcm/board_bcm2835.c --- linux-3.14.1/arch/arm/mach-bcm/board_bcm2835.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/board_bcm2835.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2010 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define PM_RSTC 0x1c +#define PM_RSTS 0x20 +#define PM_WDOG 0x24 + +#define PM_PASSWORD 0x5a000000 +#define PM_RSTC_WRCFG_MASK 0x00000030 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +#define PM_RSTS_HADWRH_SET 0x00000040 + +#define BCM2835_PERIPH_PHYS 0x20000000 +#define BCM2835_PERIPH_VIRT 0xf0000000 +#define BCM2835_PERIPH_SIZE SZ_16M + +static void __iomem *wdt_regs; + +/* + * The machine restart method can be called from an atomic context so we won't + * be able to ioremap the regs then. + */ +static void bcm2835_setup_restart(void) +{ + struct device_node *np = of_find_compatible_node(NULL, NULL, + "brcm,bcm2835-pm-wdt"); + if (WARN(!np, "unable to setup watchdog restart")) + return; + + wdt_regs = of_iomap(np, 0); + WARN(!wdt_regs, "failed to remap watchdog regs"); +} + +static void bcm2835_restart(enum reboot_mode mode, const char *cmd) +{ + u32 val; + + if (!wdt_regs) + return; + + /* use a timeout of 10 ticks (~150us) */ + writel_relaxed(10 | PM_PASSWORD, wdt_regs + PM_WDOG); + val = readl_relaxed(wdt_regs + PM_RSTC); + val &= ~PM_RSTC_WRCFG_MASK; + val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; + writel_relaxed(val, wdt_regs + PM_RSTC); + + /* No sleeping, possibly atomic. */ + mdelay(1); +} + +/* + * We can't really power off, but if we do the normal reset scheme, and + * indicate to bootcode.bin not to reboot, then most of the chip will be + * powered off. + */ +static void bcm2835_power_off(void) +{ + u32 val; + + /* + * We set the watchdog hard reset bit here to distinguish this reset + * from the normal (full) reset. bootcode.bin will not reboot after a + * hard reset. + */ + val = readl_relaxed(wdt_regs + PM_RSTS); + val &= ~PM_RSTC_WRCFG_MASK; + val |= PM_PASSWORD | PM_RSTS_HADWRH_SET; + writel_relaxed(val, wdt_regs + PM_RSTS); + + /* Continue with normal reset mechanism */ + bcm2835_restart(REBOOT_HARD, ""); +} + +static struct map_desc io_map __initdata = { + .virtual = BCM2835_PERIPH_VIRT, + .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS), + .length = BCM2835_PERIPH_SIZE, + .type = MT_DEVICE +}; + +static void __init bcm2835_map_io(void) +{ + iotable_init(&io_map, 1); +} + +static void __init bcm2835_init(void) +{ + int ret; + + bcm2835_setup_restart(); + if (wdt_regs) + pm_power_off = bcm2835_power_off; + + bcm2835_init_clocks(); + + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, + NULL); + if (ret) { + pr_err("of_platform_populate failed: %d\n", ret); + BUG(); + } +} + +static const char * const bcm2835_compat[] = { + "brcm,bcm2835", + NULL +}; + +DT_MACHINE_START(BCM2835, "BCM2835") + .map_io = bcm2835_map_io, + .init_irq = irqchip_init, + .init_machine = bcm2835_init, + .restart = bcm2835_restart, + .dt_compat = bcm2835_compat +MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-bcm/Kconfig linux-3.15-rc1.orig/arch/arm/mach-bcm/Kconfig --- linux-3.14.1/arch/arm/mach-bcm/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -16,12 +16,7 @@ select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_GIC - select CPU_V7 - select CLKSRC_OF - select GENERIC_CLOCKEVENTS - select GENERIC_TIME select GPIO_BCM_KONA - select SPARSE_IRQ select TICK_ONESHOT select CACHE_L2X0 select HAVE_ARM_ARCH_TIMER @@ -32,6 +27,48 @@ BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 variants. +config ARCH_BCM2835 + bool "Broadcom BCM2835 family" if ARCH_MULTI_V6 + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select ARM_ERRATA_411920 + select ARM_TIMER_SP804 + select CLKDEV_LOOKUP + select CLKSRC_OF + select CPU_V6 + select GENERIC_CLOCKEVENTS + select PINCTRL + select PINCTRL_BCM2835 + help + This enables support for the Broadcom BCM2835 SoC. This SoC is + used in the Raspberry Pi and Roku 2 devices. + +config ARCH_BCM_5301X + bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 + depends on MMU + select ARM_GIC + select CACHE_L2X0 + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select HAVE_SMP + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select ARM_GLOBAL_TIMER + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK + select MIGHT_HAVE_PCI + help + Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. + + This is a network SoC line mostly used in home routers and + wifi access points, it's internal name is Northstar. + This inclused the following SoC: BCM53010, BCM53011, BCM53012, + BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707, + BCM4708 and BCM4709. + + Do not confuse this with the BCM4760 which is a totally + different SoC or with the older BCM47XX and BCM53XX based + network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx + endmenu endif diff -Nur linux-3.14.1/arch/arm/mach-bcm/kona.c linux-3.15-rc1.orig/arch/arm/mach-bcm/kona.c --- linux-3.14.1/arch/arm/mach-bcm/kona.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/kona.c 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Broadcom Corporation + * Copyright (C) 2012-2014 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -11,55 +11,33 @@ * GNU General Public License for more details. */ -#include -#include +#include +#include +#include "bcm_kona_smc.h" #include "kona.h" -static void __iomem *watchdog_base; - -void bcm_kona_setup_restart(void) +void __init kona_l2_cache_init(void) { - struct device_node *np_wdog; + int ret; - /* - * The assumption is that whoever calls bcm_kona_setup_restart() - * also needs a Kona Watchdog Timer entry in Device Tree, i.e. we - * report an error if the DT entry is missing. - */ - np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt"); - if (!np_wdog) { - pr_err("brcm,kona-wdt not found in DT, reboot disabled\n"); + if (!IS_ENABLED(CONFIG_CACHE_L2X0)) return; - } - watchdog_base = of_iomap(np_wdog, 0); - WARN(!watchdog_base, "failed to map watchdog base"); - of_node_put(np_wdog); -} - -#define SECWDOG_OFFSET 0x00000000 -#define SECWDOG_RESERVED_MASK 0xE2000000 -#define SECWDOG_WD_LOAD_FLAG_MASK 0x10000000 -#define SECWDOG_EN_MASK 0x08000000 -#define SECWDOG_SRSTEN_MASK 0x04000000 -#define SECWDOG_CLKS_SHIFT 20 -#define SECWDOG_LOCK_SHIFT 0 -void bcm_kona_restart(enum reboot_mode mode, const char *cmd) -{ - uint32_t val; - - if (!watchdog_base) - panic("Watchdog not mapped. Reboot failed.\n"); + ret = bcm_kona_smc_init(); + if (ret) { + pr_info("Secure API not available (%d). Skipping L2 init.\n", + ret); + return; + } - /* Enable watchdog2 with very short timeout. */ - val = readl(watchdog_base + SECWDOG_OFFSET); - val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK; - val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK | - (0x8 << SECWDOG_CLKS_SHIFT) | - (0x8 << SECWDOG_LOCK_SHIFT); - writel(val, watchdog_base + SECWDOG_OFFSET); + bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); - while (1) - ; + /* + * The aux_val and aux_mask have no effect since L2 cache is already + * enabled. Pass 0s for aux_val and 1s for aux_mask for default value. + */ + ret = l2x0_of_init(0, ~0); + if (ret) + pr_err("Couldn't enable L2 cache: %d\n", ret); } diff -Nur linux-3.14.1/arch/arm/mach-bcm/kona.h linux-3.15-rc1.orig/arch/arm/mach-bcm/kona.h --- linux-3.14.1/arch/arm/mach-bcm/kona.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/kona.h 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Broadcom Corporation + * Copyright (C) 2012-2014 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -11,7 +11,4 @@ * GNU General Public License for more details. */ -#include - -void bcm_kona_setup_restart(void); -void bcm_kona_restart(enum reboot_mode mode, const char *cmd); +void __init kona_l2_cache_init(void); diff -Nur linux-3.14.1/arch/arm/mach-bcm/Makefile linux-3.15-rc1.orig/arch/arm/mach-bcm/Makefile --- linux-3.14.1/arch/arm/mach-bcm/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ # -# Copyright (C) 2012-2013 Broadcom Corporation +# Copyright (C) 2012-2014 Broadcom Corporation # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -10,6 +10,10 @@ # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o +obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o board_bcm21664.o \ + bcm_kona_smc.o bcm_kona_smc_asm.o kona.o +obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o + plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) +obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o diff -Nur linux-3.14.1/arch/arm/mach-bcm2835/bcm2835.c linux-3.15-rc1.orig/arch/arm/mach-bcm2835/bcm2835.c --- linux-3.14.1/arch/arm/mach-bcm2835/bcm2835.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm2835/bcm2835.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,137 +0,0 @@ -/* - * Copyright (C) 2010 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#define PM_RSTC 0x1c -#define PM_RSTS 0x20 -#define PM_WDOG 0x24 - -#define PM_PASSWORD 0x5a000000 -#define PM_RSTC_WRCFG_MASK 0x00000030 -#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 -#define PM_RSTS_HADWRH_SET 0x00000040 - -#define BCM2835_PERIPH_PHYS 0x20000000 -#define BCM2835_PERIPH_VIRT 0xf0000000 -#define BCM2835_PERIPH_SIZE SZ_16M - -static void __iomem *wdt_regs; - -/* - * The machine restart method can be called from an atomic context so we won't - * be able to ioremap the regs then. - */ -static void bcm2835_setup_restart(void) -{ - struct device_node *np = of_find_compatible_node(NULL, NULL, - "brcm,bcm2835-pm-wdt"); - if (WARN(!np, "unable to setup watchdog restart")) - return; - - wdt_regs = of_iomap(np, 0); - WARN(!wdt_regs, "failed to remap watchdog regs"); -} - -static void bcm2835_restart(enum reboot_mode mode, const char *cmd) -{ - u32 val; - - if (!wdt_regs) - return; - - /* use a timeout of 10 ticks (~150us) */ - writel_relaxed(10 | PM_PASSWORD, wdt_regs + PM_WDOG); - val = readl_relaxed(wdt_regs + PM_RSTC); - val &= ~PM_RSTC_WRCFG_MASK; - val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; - writel_relaxed(val, wdt_regs + PM_RSTC); - - /* No sleeping, possibly atomic. */ - mdelay(1); -} - -/* - * We can't really power off, but if we do the normal reset scheme, and - * indicate to bootcode.bin not to reboot, then most of the chip will be - * powered off. - */ -static void bcm2835_power_off(void) -{ - u32 val; - - /* - * We set the watchdog hard reset bit here to distinguish this reset - * from the normal (full) reset. bootcode.bin will not reboot after a - * hard reset. - */ - val = readl_relaxed(wdt_regs + PM_RSTS); - val &= ~PM_RSTC_WRCFG_MASK; - val |= PM_PASSWORD | PM_RSTS_HADWRH_SET; - writel_relaxed(val, wdt_regs + PM_RSTS); - - /* Continue with normal reset mechanism */ - bcm2835_restart(REBOOT_HARD, ""); -} - -static struct map_desc io_map __initdata = { - .virtual = BCM2835_PERIPH_VIRT, - .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS), - .length = BCM2835_PERIPH_SIZE, - .type = MT_DEVICE -}; - -static void __init bcm2835_map_io(void) -{ - iotable_init(&io_map, 1); -} - -static void __init bcm2835_init(void) -{ - int ret; - - bcm2835_setup_restart(); - if (wdt_regs) - pm_power_off = bcm2835_power_off; - - bcm2835_init_clocks(); - - ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, - NULL); - if (ret) { - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); - } -} - -static const char * const bcm2835_compat[] = { - "brcm,bcm2835", - NULL -}; - -DT_MACHINE_START(BCM2835, "BCM2835") - .map_io = bcm2835_map_io, - .init_irq = irqchip_init, - .init_machine = bcm2835_init, - .restart = bcm2835_restart, - .dt_compat = bcm2835_compat -MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-bcm2835/Kconfig linux-3.15-rc1.orig/arch/arm/mach-bcm2835/Kconfig --- linux-3.14.1/arch/arm/mach-bcm2835/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm2835/Kconfig 1970-01-01 01:00:00.000000000 +0100 @@ -1,15 +0,0 @@ -config ARCH_BCM2835 - bool "Broadcom BCM2835 family" if ARCH_MULTI_V6 - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select ARM_ERRATA_411920 - select ARM_TIMER_SP804 - select CLKDEV_LOOKUP - select CLKSRC_OF - select CPU_V6 - select GENERIC_CLOCKEVENTS - select PINCTRL - select PINCTRL_BCM2835 - help - This enables support for the Broadcom BCM2835 SoC. This SoC is - used in the Raspberry Pi and Roku 2 devices. diff -Nur linux-3.14.1/arch/arm/mach-bcm2835/Makefile linux-3.15-rc1.orig/arch/arm/mach-bcm2835/Makefile --- linux-3.14.1/arch/arm/mach-bcm2835/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-bcm2835/Makefile 1970-01-01 01:00:00.000000000 +0100 @@ -1 +0,0 @@ -obj-y += bcm2835.o diff -Nur linux-3.14.1/arch/arm/mach-berlin/Kconfig linux-3.15-rc1.orig/arch/arm/mach-berlin/Kconfig --- linux-3.14.1/arch/arm/mach-berlin/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-berlin/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -1,9 +1,7 @@ config ARCH_BERLIN bool "Marvell Berlin SoCs" if ARCH_MULTI_V7 select ARM_GIC - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select COMMON_CLK select DW_APB_ICTL select DW_APB_TIMER_OF @@ -16,12 +14,10 @@ select CACHE_L2X0 select CPU_PJ4B select HAVE_ARM_TWD if SMP - select HAVE_SMP config MACH_BERLIN_BG2CD bool "Marvell Armada 1500-mini (BG2CD)" select CACHE_L2X0 - select CPU_V7 select HAVE_ARM_TWD if SMP endmenu diff -Nur linux-3.14.1/arch/arm/mach-clps711x/board-autcpu12.c linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-autcpu12.c --- linux-3.14.1/arch/arm/mach-clps711x/board-autcpu12.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-autcpu12.c 2014-04-13 23:18:35.000000000 +0200 @@ -73,7 +73,7 @@ #define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */ #define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2) #define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3) -#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3) +#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 4) /* LCD contrast digital potentiometer */ #define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0) @@ -265,14 +265,12 @@ MACHINE_START(AUTCPU12, "autronix autcpu12") /* Maintainer: Thomas Gleixner */ .atag_offset = 0x20000, - .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = autcpu12_init, .init_late = autcpu12_init_late, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-clps711x/board-cdb89712.c linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-cdb89712.c --- linux-3.14.1/arch/arm/mach-clps711x/board-cdb89712.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-cdb89712.c 2014-04-13 23:18:35.000000000 +0200 @@ -139,12 +139,10 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712") /* Maintainer: Ray Lehtiniemi */ .atag_offset = 0x100, - .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = cdb89712_init, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-clps711x/board-clep7312.c linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-clep7312.c --- linux-3.14.1/arch/arm/mach-clps711x/board-clep7312.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-clep7312.c 2014-04-13 23:18:35.000000000 +0200 @@ -36,12 +36,10 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") /* Maintainer: Nobody */ .atag_offset = 0x0100, - .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_clep7312, .map_io = clps711x_map_io, .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-clps711x/board-edb7211.c linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-edb7211.c --- linux-3.14.1/arch/arm/mach-clps711x/board-edb7211.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-edb7211.c 2014-04-13 23:18:35.000000000 +0200 @@ -177,7 +177,6 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") /* Maintainer: Jon McClintock */ .atag_offset = VIDEORAM_SIZE + 0x100, - .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_edb7211, .reserve = edb7211_reserve, .map_io = clps711x_map_io, @@ -186,6 +185,5 @@ .init_time = clps711x_timer_init, .init_machine = edb7211_init, .init_late = edb7211_init_late, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-clps711x/board-p720t.c linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-p720t.c --- linux-3.14.1/arch/arm/mach-clps711x/board-p720t.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/board-p720t.c 2014-04-13 23:18:35.000000000 +0200 @@ -363,7 +363,6 @@ MACHINE_START(P720T, "ARM-Prospector720T") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .atag_offset = 0x100, - .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_p720t, .map_io = clps711x_map_io, .init_early = clps711x_init_early, @@ -371,6 +370,5 @@ .init_time = clps711x_timer_init, .init_machine = p720t_init, .init_late = p720t_init_late, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-clps711x/common.c linux-3.15-rc1.orig/arch/arm/mach-clps711x/common.c --- linux-3.14.1/arch/arm/mach-clps711x/common.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/common.c 2014-04-13 23:18:35.000000000 +0200 @@ -31,14 +31,14 @@ #include #include -#include -#include #include #include #include #include +#include "common.h" + static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh, *clk_tint, *clk_spi; @@ -59,204 +59,9 @@ iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc)); } -static void int1_mask(struct irq_data *d) -{ - u32 intmr1; - - intmr1 = clps_readl(INTMR1); - intmr1 &= ~(1 << d->irq); - clps_writel(intmr1, INTMR1); -} - -static void int1_eoi(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_CSINT: clps_writel(0, COEOI); break; - case IRQ_TC1OI: clps_writel(0, TC1EOI); break; - case IRQ_TC2OI: clps_writel(0, TC2EOI); break; - case IRQ_RTCMI: clps_writel(0, RTCEOI); break; - case IRQ_TINT: clps_writel(0, TEOI); break; - case IRQ_UMSINT: clps_writel(0, UMSEOI); break; - } -} - -static void int1_unmask(struct irq_data *d) -{ - u32 intmr1; - - intmr1 = clps_readl(INTMR1); - intmr1 |= 1 << d->irq; - clps_writel(intmr1, INTMR1); -} - -static struct irq_chip int1_chip = { - .name = "Interrupt Vector 1", - .irq_eoi = int1_eoi, - .irq_mask = int1_mask, - .irq_unmask = int1_unmask, -}; - -static void int2_mask(struct irq_data *d) -{ - u32 intmr2; - - intmr2 = clps_readl(INTMR2); - intmr2 &= ~(1 << (d->irq - 16)); - clps_writel(intmr2, INTMR2); -} - -static void int2_eoi(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_KBDINT: clps_writel(0, KBDEOI); break; - } -} - -static void int2_unmask(struct irq_data *d) -{ - u32 intmr2; - - intmr2 = clps_readl(INTMR2); - intmr2 |= 1 << (d->irq - 16); - clps_writel(intmr2, INTMR2); -} - -static struct irq_chip int2_chip = { - .name = "Interrupt Vector 2", - .irq_eoi = int2_eoi, - .irq_mask = int2_mask, - .irq_unmask = int2_unmask, -}; - -static void int3_mask(struct irq_data *d) -{ - u32 intmr3; - - intmr3 = clps_readl(INTMR3); - intmr3 &= ~(1 << (d->irq - 32)); - clps_writel(intmr3, INTMR3); -} - -static void int3_unmask(struct irq_data *d) -{ - u32 intmr3; - - intmr3 = clps_readl(INTMR3); - intmr3 |= 1 << (d->irq - 32); - clps_writel(intmr3, INTMR3); -} - -static struct irq_chip int3_chip = { - .name = "Interrupt Vector 3", - .irq_mask = int3_mask, - .irq_unmask = int3_unmask, -}; - -static struct { - int nr; - struct irq_chip *chip; - irq_flow_handler_t handle; -} clps711x_irqdescs[] __initdata = { - { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, }, - { IRQ_EINT1, &int1_chip, handle_level_irq, }, - { IRQ_EINT2, &int1_chip, handle_level_irq, }, - { IRQ_EINT3, &int1_chip, handle_level_irq, }, - { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, }, - { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, }, - { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, }, - { IRQ_TINT, &int1_chip, handle_fasteoi_irq, }, - { IRQ_UTXINT1, &int1_chip, handle_level_irq, }, - { IRQ_URXINT1, &int1_chip, handle_level_irq, }, - { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, }, - { IRQ_SSEOTI, &int1_chip, handle_level_irq, }, - { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, }, - { IRQ_SS2RX, &int2_chip, handle_level_irq, }, - { IRQ_SS2TX, &int2_chip, handle_level_irq, }, - { IRQ_UTXINT2, &int2_chip, handle_level_irq, }, - { IRQ_URXINT2, &int2_chip, handle_level_irq, }, -}; - void __init clps711x_init_irq(void) { - unsigned int i; - - /* Disable interrupts */ - clps_writel(0, INTMR1); - clps_writel(0, INTMR2); - clps_writel(0, INTMR3); - - /* Clear down any pending interrupts */ - clps_writel(0, BLEOI); - clps_writel(0, MCEOI); - clps_writel(0, COEOI); - clps_writel(0, TC1EOI); - clps_writel(0, TC2EOI); - clps_writel(0, RTCEOI); - clps_writel(0, TEOI); - clps_writel(0, UMSEOI); - clps_writel(0, KBDEOI); - clps_writel(0, SRXEOF); - clps_writel(0xffffffff, DAISR); - - for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) { - irq_set_chip_and_handler(clps711x_irqdescs[i].nr, - clps711x_irqdescs[i].chip, - clps711x_irqdescs[i].handle); - set_irq_flags(clps711x_irqdescs[i].nr, - IRQF_VALID | IRQF_PROBE); - } - - if (IS_ENABLED(CONFIG_FIQ)) { - init_FIQ(0); - irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip, - handle_bad_irq); - set_irq_flags(IRQ_DAIINT, - IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); - } -} - -static inline u32 fls16(u32 x) -{ - u32 r = 15; - - if (!(x & 0xff00)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf000)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc000)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x8000)) - r--; - - return r; -} - -asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) -{ - do { - u32 irqstat; - void __iomem *base = CLPS711X_VIRT_BASE; - - irqstat = readw_relaxed(base + INTSR1) & - readw_relaxed(base + INTMR1); - if (irqstat) - handle_IRQ(fls16(irqstat), regs); - - irqstat = readw_relaxed(base + INTSR2) & - readw_relaxed(base + INTMR2); - if (irqstat) { - handle_IRQ(fls16(irqstat) + 16, regs); - continue; - } - - break; - } while (1); + clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K); } static u64 notrace clps711x_sched_clock_read(void) diff -Nur linux-3.14.1/arch/arm/mach-clps711x/common.h linux-3.15-rc1.orig/arch/arm/mach-clps711x/common.h --- linux-3.14.1/arch/arm/mach-clps711x/common.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/common.h 2014-04-13 23:18:35.000000000 +0200 @@ -6,13 +6,14 @@ #include -#define CLPS711X_NR_IRQS (33) #define CLPS711X_NR_GPIO (4 * 8 + 3) #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit)) extern void clps711x_map_io(void); extern void clps711x_init_irq(void); extern void clps711x_timer_init(void); -extern void clps711x_handle_irq(struct pt_regs *regs); extern void clps711x_restart(enum reboot_mode mode, const char *cmd); extern void clps711x_init_early(void); + +/* drivers/irqchip/irq-clps711x.c */ +void clps711x_intc_init(phys_addr_t, resource_size_t); diff -Nur linux-3.14.1/arch/arm/mach-clps711x/include/mach/clps711x.h linux-3.15-rc1.orig/arch/arm/mach-clps711x/include/mach/clps711x.h --- linux-3.14.1/arch/arm/mach-clps711x/include/mach/clps711x.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/include/mach/clps711x.h 2014-04-13 23:18:35.000000000 +0200 @@ -40,8 +40,6 @@ #define MEMCFG1 (0x0180) #define MEMCFG2 (0x01c0) #define DRFPR (0x0200) -#define INTSR1 (0x0240) -#define INTMR1 (0x0280) #define LCDCON (0x02c0) #define TC1D (0x0300) #define TC2D (0x0340) @@ -55,28 +53,16 @@ #define PALLSW (0x0540) #define PALMSW (0x0580) #define STFCLR (0x05c0) -#define BLEOI (0x0600) -#define MCEOI (0x0640) -#define TEOI (0x0680) -#define TC1EOI (0x06c0) -#define TC2EOI (0x0700) -#define RTCEOI (0x0740) -#define UMSEOI (0x0780) -#define COEOI (0x07c0) #define HALT (0x0800) #define STDBY (0x0840) #define FBADDR (0x1000) #define SYSCON2 (0x1100) #define SYSFLG2 (0x1140) -#define INTSR2 (0x1240) -#define INTMR2 (0x1280) #define UARTDR2 (0x1480) #define UBRLCR2 (0x14c0) #define SS2DR (0x1500) -#define SRXEOF (0x1600) #define SS2POP (0x16c0) -#define KBDEOI (0x1700) #define DAIR (0x2000) #define DAIDR0 (0x2040) @@ -84,8 +70,6 @@ #define DAIDR2 (0x20c0) #define DAISR (0x2100) #define SYSCON3 (0x2200) -#define INTSR3 (0x2240) -#define INTMR3 (0x2280) #define LEDFLSH (0x22c0) #define SDCONF (0x2300) #define SDRFPR (0x2340) diff -Nur linux-3.14.1/arch/arm/mach-clps711x/include/mach/hardware.h linux-3.15-rc1.orig/arch/arm/mach-clps711x/include/mach/hardware.h --- linux-3.14.1/arch/arm/mach-clps711x/include/mach/hardware.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/include/mach/hardware.h 2014-04-13 23:18:35.000000000 +0200 @@ -38,13 +38,6 @@ #define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off)) #endif -/* - * The physical addresses that the external chip select signals map to is - * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 - * processors. CONFIG_EP72XX_BOOT_ROM is only available if these - * processors are in use. - */ -#ifndef CONFIG_EP72XX_ROM_BOOT #define CS0_PHYS_BASE (0x00000000) #define CS1_PHYS_BASE (0x10000000) #define CS2_PHYS_BASE (0x20000000) @@ -53,16 +46,6 @@ #define CS5_PHYS_BASE (0x50000000) #define CS6_PHYS_BASE (0x60000000) #define CS7_PHYS_BASE (0x70000000) -#else -#define CS0_PHYS_BASE (0x70000000) -#define CS1_PHYS_BASE (0x60000000) -#define CS2_PHYS_BASE (0x50000000) -#define CS3_PHYS_BASE (0x40000000) -#define CS4_PHYS_BASE (0x30000000) -#define CS5_PHYS_BASE (0x20000000) -#define CS6_PHYS_BASE (0x10000000) -#define CS7_PHYS_BASE (0x00000000) -#endif #define CLPS711X_SRAM_BASE CS6_PHYS_BASE #define CLPS711X_SRAM_SIZE (48 * 1024) diff -Nur linux-3.14.1/arch/arm/mach-clps711x/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-clps711x/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-clps711x/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,2 +0,0 @@ -/* Bogus value */ -#define CLOCK_TICK_RATE 512000 diff -Nur linux-3.14.1/arch/arm/mach-clps711x/Kconfig linux-3.15-rc1.orig/arch/arm/mach-clps711x/Kconfig --- linux-3.14.1/arch/arm/mach-clps711x/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-clps711x/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -33,20 +33,6 @@ Say Y here if you intend to run this kernel on the ARM Prospector 720T. -config EP72XX_ROM_BOOT - bool "EP721x/EP731x ROM boot" - help - If you say Y here, your CLPS711x-based kernel will use the bootstrap - mode memory map instead of the normal memory map. - - Processors derived from the Cirrus CLPS711X core support two boot - modes. Normal mode boots from the external memory device at CS0. - Bootstrap mode rearranges parts of the memory map, placing an - internal 128 byte bootstrap ROM at CS0. This option performs the - address map changes required to support booting in this mode. - - You almost surely want to say N here. - endmenu endif diff -Nur linux-3.14.1/arch/arm/mach-cns3xxx/cns3420vb.c linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/cns3420vb.c --- linux-3.14.1/arch/arm/mach-cns3xxx/cns3420vb.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/cns3420vb.c 2014-04-13 23:18:35.000000000 +0200 @@ -246,7 +246,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .atag_offset = 0x100, - .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, diff -Nur linux-3.14.1/arch/arm/mach-cns3xxx/core.c linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/core.c --- linux-3.14.1/arch/arm/mach-cns3xxx/core.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/core.c 2014-04-13 23:18:35.000000000 +0200 @@ -47,6 +47,38 @@ .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), .length = SZ_4K, .type = MT_DEVICE, +#ifdef CONFIG_PCI + }, { + .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), + .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), + .length = SZ_16M, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), + .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), + .length = SZ_16M, + .type = MT_DEVICE, +#endif }, }; @@ -155,7 +187,7 @@ static struct irqaction cns3xxx_timer_irq = { .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = cns3xxx_timer_interrupt, }; @@ -368,7 +400,6 @@ DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") .dt_compat = cns3xxx_dt_compat, - .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3xxx_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, diff -Nur linux-3.14.1/arch/arm/mach-cns3xxx/Kconfig linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/Kconfig --- linux-3.14.1/arch/arm/mach-cns3xxx/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -1,9 +1,6 @@ config ARCH_CNS3XXX bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 select ARM_GIC - select CPU_V6K - select GENERIC_CLOCKEVENTS - select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI help diff -Nur linux-3.14.1/arch/arm/mach-cns3xxx/pcie.c linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/pcie.c --- linux-3.14.1/arch/arm/mach-cns3xxx/pcie.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-cns3xxx/pcie.c 2014-04-13 23:18:35.000000000 +0200 @@ -23,15 +23,10 @@ #include "cns3xxx.h" #include "core.h" -enum cns3xxx_access_type { - CNS3XXX_HOST_TYPE = 0, - CNS3XXX_CFG0_TYPE, - CNS3XXX_CFG1_TYPE, - CNS3XXX_NUM_ACCESS_TYPES, -}; - struct cns3xxx_pcie { - struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES]; + void __iomem *host_regs; /* PCI config registers for host bridge */ + void __iomem *cfg0_regs; /* PCI Type 0 config registers */ + void __iomem *cfg1_regs; /* PCI Type 1 config registers */ unsigned int irqs[2]; struct resource res_io; struct resource res_mem; @@ -66,7 +61,6 @@ int busno = bus->number; int slot = PCI_SLOT(devfn); int offset; - enum cns3xxx_access_type type; void __iomem *base; /* If there is no link, just show the CNS PCI bridge. */ @@ -78,17 +72,21 @@ * we still want to access it. For this to work, we must place * the first device on the same bus as the CNS PCI bridge. */ - if (busno == 0) { - if (slot > 1) - return NULL; - type = slot; - } else { - type = CNS3XXX_CFG1_TYPE; - } + if (busno == 0) { /* directly connected PCIe bus */ + switch (slot) { + case 0: /* host bridge device, function 0 only */ + base = cnspci->host_regs; + break; + case 1: /* directly connected device */ + base = cnspci->cfg0_regs; + break; + default: + return NULL; /* no such device */ + } + } else /* remote PCI bus */ + base = cnspci->cfg1_regs; - base = (void __iomem *)cnspci->cfg_bases[type].virtual; offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc); - return base + offset; } @@ -180,36 +178,19 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = { [0] = { - .cfg_bases = { - [CNS3XXX_HOST_TYPE] = { - .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG0_TYPE] = { - .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG1_TYPE] = { - .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - }, + .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT, + .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT, + .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT, .res_io = { .name = "PCIe0 I/O space", .start = CNS3XXX_PCIE0_IO_BASE, - .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1, + .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */ .flags = IORESOURCE_IO, }, .res_mem = { .name = "PCIe0 non-prefetchable", .start = CNS3XXX_PCIE0_MEM_BASE, - .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1, + .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */ .flags = IORESOURCE_MEM, }, .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, @@ -222,36 +203,19 @@ }, }, [1] = { - .cfg_bases = { - [CNS3XXX_HOST_TYPE] = { - .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG0_TYPE] = { - .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - [CNS3XXX_CFG1_TYPE] = { - .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, - }, + .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT, + .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT, + .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT, .res_io = { .name = "PCIe1 I/O space", .start = CNS3XXX_PCIE1_IO_BASE, - .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1, + .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */ .flags = IORESOURCE_IO, }, .res_mem = { .name = "PCIe1 non-prefetchable", .start = CNS3XXX_PCIE1_MEM_BASE, - .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1, + .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */ .flags = IORESOURCE_MEM, }, .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, @@ -307,18 +271,15 @@ .ops = &cns3xxx_pcie_ops, .sysdata = &sd, }; - u32 io_base = cnspci->res_io.start >> 16; - u32 mem_base = cnspci->res_mem.start >> 16; - u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn; - u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn; + u16 mem_base = cnspci->res_mem.start >> 16; + u16 mem_limit = cnspci->res_mem.end >> 16; + u16 io_base = cnspci->res_io.start >> 16; + u16 io_limit = cnspci->res_io.end >> 16; u32 devfn = 0; u8 tmp8; u16 pos; u16 dc; - host_base = (__pfn_to_phys(host_base) - 1) >> 16; - cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16; - pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0); pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1); pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1); @@ -328,9 +289,9 @@ pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8); pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base); - pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base); + pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit); pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base); - pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base); + pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit); if (!cnspci->linked) return; @@ -368,8 +329,6 @@ "imprecise external abort"); for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { - iotable_init(cns3xxx_pcie[i].cfg_bases, - ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); diff -Nur linux-3.14.1/arch/arm/mach-davinci/aemif.c linux-3.15-rc1.orig/arch/arm/mach-davinci/aemif.c --- linux-3.14.1/arch/arm/mach-davinci/aemif.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/aemif.c 2014-04-13 23:18:35.000000000 +0200 @@ -16,6 +16,7 @@ #include #include +#include /* Timing value configuration */ @@ -43,6 +44,17 @@ WSTROBE(WSTROBE_MAX) | \ WSETUP(WSETUP_MAX)) +static inline unsigned int davinci_aemif_readl(void __iomem *base, int offset) +{ + return readl_relaxed(base + offset); +} + +static inline void davinci_aemif_writel(void __iomem *base, + int offset, unsigned long value) +{ + writel_relaxed(value, base + offset); +} + /* * aemif_calc_rate - calculate timing data. * @wanted: The cycle time needed in nanoseconds. @@ -76,6 +88,7 @@ * @t: timing values to be progammed * @base: The virtual base address of the AEMIF interface * @cs: chip-select to program the timing values for + * @clkrate: the AEMIF clkrate * * This function programs the given timing values (in real clock) into the * AEMIF registers taking the AEMIF clock into account. @@ -86,24 +99,17 @@ * * Returns 0 on success, else negative errno. */ -int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, - void __iomem *base, unsigned cs) +static int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs, + unsigned long clkrate) { unsigned set, val; int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned offset = A1CR_OFFSET + cs * 4; - struct clk *aemif_clk; - unsigned long clkrate; if (!t) return 0; /* Nothing to do */ - aemif_clk = clk_get(NULL, "aemif"); - if (IS_ERR(aemif_clk)) - return PTR_ERR(aemif_clk); - - clkrate = clk_get_rate(aemif_clk); - clkrate /= 1000; /* turn clock into kHz for ease of use */ ta = aemif_calc_rate(t->ta, clkrate, TA_MAX); @@ -130,4 +136,83 @@ return 0; } -EXPORT_SYMBOL(davinci_aemif_setup_timing); + +/** + * davinci_aemif_setup - setup AEMIF interface by davinci_nand_pdata + * @pdev - link to platform device to setup settings for + * + * This function does not use any locking while programming the AEMIF + * because it is expected that there is only one user of a given + * chip-select. + * + * Returns 0 on success, else negative errno. + */ +int davinci_aemif_setup(struct platform_device *pdev) +{ + struct davinci_nand_pdata *pdata = dev_get_platdata(&pdev->dev); + uint32_t val; + unsigned long clkrate; + struct resource *res; + void __iomem *base; + struct clk *clk; + int ret = 0; + + clk = clk_get(&pdev->dev, "aemif"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(clk); + if (ret < 0) { + dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", + ret); + goto err_put; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "cannot get IORESOURCE_MEM\n"); + ret = -ENOMEM; + goto err; + } + + base = ioremap(res->start, resource_size(res)); + if (!base) { + dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res); + ret = -ENOMEM; + goto err; + } + + /* + * Setup Async configuration register in case we did not boot + * from NAND and so bootloader did not bother to set it up. + */ + val = davinci_aemif_readl(base, A1CR_OFFSET + pdev->id * 4); + /* + * Extended Wait is not valid and Select Strobe mode is not + * used + */ + val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK); + if (pdata->options & NAND_BUSWIDTH_16) + val |= 0x1; + + davinci_aemif_writel(base, A1CR_OFFSET + pdev->id * 4, val); + + clkrate = clk_get_rate(clk); + + if (pdata->timing) + ret = davinci_aemif_setup_timing(pdata->timing, base, pdev->id, + clkrate); + + if (ret < 0) + dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); + + iounmap(base); +err: + clk_disable_unprepare(clk); +err_put: + clk_put(clk); + return ret; +} diff -Nur linux-3.14.1/arch/arm/mach-davinci/board-da830-evm.c linux-3.15-rc1.orig/arch/arm/mach-davinci/board-da830-evm.c --- linux-3.14.1/arch/arm/mach-davinci/board-da830-evm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/board-da830-evm.c 2014-04-13 23:18:35.000000000 +0200 @@ -419,6 +419,9 @@ if (ret) pr_warning("da830_evm_init: NAND device not registered.\n"); + if (davinci_aemif_setup(&da830_evm_nand_device)) + pr_warn("%s: Cannot configure AEMIF.\n", __func__); + gpio_direction_output(mux_mode, 1); } #else diff -Nur linux-3.14.1/arch/arm/mach-davinci/board-da850-evm.c linux-3.15-rc1.orig/arch/arm/mach-davinci/board-da850-evm.c --- linux-3.14.1/arch/arm/mach-davinci/board-da850-evm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/board-da850-evm.c 2014-04-13 23:18:35.000000000 +0200 @@ -358,6 +358,9 @@ platform_add_devices(da850_evm_devices, ARRAY_SIZE(da850_evm_devices)); + + if (davinci_aemif_setup(&da850_evm_nandflash_device)) + pr_warn("%s: Cannot configure AEMIF.\n", __func__); } } diff -Nur linux-3.14.1/arch/arm/mach-davinci/board-dm644x-evm.c linux-3.15-rc1.orig/arch/arm/mach-davinci/board-dm644x-evm.c --- linux-3.14.1/arch/arm/mach-davinci/board-dm644x-evm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/board-dm644x-evm.c 2014-04-13 23:18:35.000000000 +0200 @@ -778,6 +778,11 @@ /* only one device will be jumpered and detected */ if (HAS_NAND) { platform_device_register(&davinci_evm_nandflash_device); + + if (davinci_aemif_setup(&davinci_evm_nandflash_device)) + pr_warn("%s: Cannot configure AEMIF.\n", + __func__); + evm_leds[7].default_trigger = "nand-disk"; if (HAS_NOR) pr_warning("WARNING: both NAND and NOR flash " @@ -799,11 +804,12 @@ /* irlml6401 switches over 1A, in under 8 msec */ davinci_setup_usb(1000, 8); - soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; - /* Register the fixup for PHY on DaVinci */ - phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, - davinci_phy_fixup); - + if (IS_BUILTIN(CONFIG_PHYLIB)) { + soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; + /* Register the fixup for PHY on DaVinci */ + phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, + davinci_phy_fixup); + } } MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") diff -Nur linux-3.14.1/arch/arm/mach-davinci/board-dm646x-evm.c linux-3.15-rc1.orig/arch/arm/mach-davinci/board-dm646x-evm.c --- linux-3.14.1/arch/arm/mach-davinci/board-dm646x-evm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/board-dm646x-evm.c 2014-04-13 23:18:35.000000000 +0200 @@ -805,6 +805,9 @@ platform_device_register(&davinci_nand_device); + if (davinci_aemif_setup(&davinci_nand_device)) + pr_warn("%s: Cannot configure AEMIF.\n", __func__); + dm646x_init_edma(dm646x_edma_rsv); if (HAS_ATA) diff -Nur linux-3.14.1/arch/arm/mach-davinci/board-mityomapl138.c linux-3.15-rc1.orig/arch/arm/mach-davinci/board-mityomapl138.c --- linux-3.14.1/arch/arm/mach-davinci/board-mityomapl138.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/board-mityomapl138.c 2014-04-13 23:18:35.000000000 +0200 @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -432,6 +433,9 @@ { platform_add_devices(mityomapl138_devices, ARRAY_SIZE(mityomapl138_devices)); + + if (davinci_aemif_setup(&mityomapl138_nandflash_device)) + pr_warn("%s: Cannot configure AEMIF.\n", __func__); } static const short mityomap_mii_pins[] = { diff -Nur linux-3.14.1/arch/arm/mach-davinci/board-tnetv107x-evm.c linux-3.15-rc1.orig/arch/arm/mach-davinci/board-tnetv107x-evm.c --- linux-3.14.1/arch/arm/mach-davinci/board-tnetv107x-evm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/board-tnetv107x-evm.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,287 +0,0 @@ -/* - * Texas Instruments TNETV107X EVM Board Support - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#define EVM_MMC_WP_GPIO 21 -#define EVM_MMC_CD_GPIO 24 -#define EVM_SPI_CS_GPIO 54 - -static int initialize_gpio(int gpio, char *desc) -{ - int ret; - - ret = gpio_request(gpio, desc); - if (ret < 0) { - pr_err_ratelimited("cannot open %s gpio\n", desc); - return -ENOSYS; - } - gpio_direction_input(gpio); - return gpio; -} - -static int mmc_get_cd(int index) -{ - static int gpio; - - if (!gpio) - gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect"); - - if (gpio < 0) - return gpio; - - return gpio_get_value(gpio) ? 0 : 1; -} - -static int mmc_get_ro(int index) -{ - static int gpio; - - if (!gpio) - gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect"); - - if (gpio < 0) - return gpio; - - return gpio_get_value(gpio) ? 1 : 0; -} - -static struct davinci_mmc_config mmc_config = { - .get_cd = mmc_get_cd, - .get_ro = mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static const short sdio1_pins[] __initconst = { - TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1, - TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1, - TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1, - TNETV107X_GPIO21, TNETV107X_GPIO24, - -1 -}; - -static const short uart1_pins[] __initconst = { - TNETV107X_UART1_RD, TNETV107X_UART1_TD, - -1 -}; - -static const short ssp_pins[] __initconst = { - TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2, - TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2, - TNETV107X_SSP1_3, -1 -}; - -static struct mtd_partition nand_partitions[] = { - /* bootloader (U-Boot, etc) in first 12 sectors */ - { - .name = "bootloader", - .offset = 0, - .size = (12*SZ_128K), - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M, - .mask_flags = 0, - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } -}; - -static struct davinci_nand_pdata nand_config = { - .mask_cle = 0x4000, - .mask_ale = 0x2000, - .parts = nand_partitions, - .nr_parts = ARRAY_SIZE(nand_partitions), - .ecc_mode = NAND_ECC_HW, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 1, -}; - -static struct davinci_uart_config serial_config __initconst = { - .enabled_uarts = BIT(1), -}; - -static const uint32_t keymap[] = { - KEY(0, 0, KEY_NUMERIC_1), - KEY(0, 1, KEY_NUMERIC_2), - KEY(0, 2, KEY_NUMERIC_3), - KEY(0, 3, KEY_FN_F1), - KEY(0, 4, KEY_MENU), - - KEY(1, 0, KEY_NUMERIC_4), - KEY(1, 1, KEY_NUMERIC_5), - KEY(1, 2, KEY_NUMERIC_6), - KEY(1, 3, KEY_UP), - KEY(1, 4, KEY_FN_F2), - - KEY(2, 0, KEY_NUMERIC_7), - KEY(2, 1, KEY_NUMERIC_8), - KEY(2, 2, KEY_NUMERIC_9), - KEY(2, 3, KEY_LEFT), - KEY(2, 4, KEY_ENTER), - - KEY(3, 0, KEY_NUMERIC_STAR), - KEY(3, 1, KEY_NUMERIC_0), - KEY(3, 2, KEY_NUMERIC_POUND), - KEY(3, 3, KEY_DOWN), - KEY(3, 4, KEY_RIGHT), - - KEY(4, 0, KEY_FN_F3), - KEY(4, 1, KEY_FN_F4), - KEY(4, 2, KEY_MUTE), - KEY(4, 3, KEY_HOME), - KEY(4, 4, KEY_BACK), - - KEY(5, 0, KEY_VOLUMEDOWN), - KEY(5, 1, KEY_VOLUMEUP), - KEY(5, 2, KEY_F1), - KEY(5, 3, KEY_F2), - KEY(5, 4, KEY_F3), -}; - -static const struct matrix_keymap_data keymap_data = { - .keymap = keymap, - .keymap_size = ARRAY_SIZE(keymap), -}; - -static struct matrix_keypad_platform_data keypad_config = { - .keymap_data = &keymap_data, - .num_row_gpios = 6, - .num_col_gpios = 5, - .debounce_ms = 0, /* minimum */ - .active_low = 0, /* pull up realization */ - .no_autorepeat = 0, -}; - -static void spi_select_device(int cs) -{ - static int gpio; - - if (!gpio) { - int ret; - ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel"); - if (ret < 0) { - pr_err("cannot open spi chipsel gpio\n"); - gpio = -ENOSYS; - return; - } else { - gpio = EVM_SPI_CS_GPIO; - gpio_direction_output(gpio, 0); - } - } - - if (gpio < 0) - return; - - return gpio_set_value(gpio, cs ? 1 : 0); -} - -static struct ti_ssp_spi_data spi_master_data = { - .num_cs = 2, - .select = spi_select_device, - .iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) | - SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) | - SSP_INPUT_SEL(3), -}; - -static struct ti_ssp_data ssp_config = { - .out_clock = 250 * 1000, - .dev_data = { - [1] = { - .dev_name = "ti-ssp-spi", - .pdata = &spi_master_data, - .pdata_size = sizeof(spi_master_data), - }, - }, -}; - -static struct tnetv107x_device_info evm_device_info __initconst = { - .serial_config = &serial_config, - .mmc_config[1] = &mmc_config, /* controller 1 */ - .nand_config[0] = &nand_config, /* chip select 0 */ - .keypad_config = &keypad_config, - .ssp_config = &ssp_config, -}; - -static struct spi_board_info spi_info[] __initconst = { -}; - -static __init void tnetv107x_evm_board_init(void) -{ - davinci_cfg_reg_list(sdio1_pins); - davinci_cfg_reg_list(uart1_pins); - davinci_cfg_reg_list(ssp_pins); - - tnetv107x_devices_init(&evm_device_info); - - spi_register_board_info(spi_info, ARRAY_SIZE(spi_info)); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init tnetv107x_evm_console_init(void) -{ - return add_preferred_console("ttyS", 0, "115200"); -} -console_initcall(tnetv107x_evm_console_init); -#endif - -MACHINE_START(TNETV107X, "TNETV107X EVM") - .atag_offset = 0x100, - .map_io = tnetv107x_init, - .init_irq = cp_intc_init, - .init_time = davinci_timer_init, - .init_machine = tnetv107x_evm_board_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .restart = tnetv107x_restart, -MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-davinci/da850.c linux-3.15-rc1.orig/arch/arm/mach-davinci/da850.c --- linux-3.14.1/arch/arm/mach-davinci/da850.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/da850.c 2014-04-13 23:18:35.000000000 +0200 @@ -472,7 +472,7 @@ CLK("spi_davinci.0", NULL, &spi0_clk), CLK("spi_davinci.1", NULL, &spi1_clk), CLK("vpif", NULL, &vpif_clk), - CLK("ahci", NULL, &sata_clk), + CLK("ahci_da850", NULL, &sata_clk), CLK("davinci-rproc.0", NULL, &dsp_clk), CLK("ehrpwm", "fck", &ehrpwm_clk), CLK("ehrpwm", "tbclk", &ehrpwm_tbclk), diff -Nur linux-3.14.1/arch/arm/mach-davinci/davinci.h linux-3.15-rc1.orig/arch/arm/mach-davinci/davinci.h --- linux-3.14.1/arch/arm/mach-davinci/davinci.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/davinci.h 2014-04-13 23:18:35.000000000 +0200 @@ -79,6 +79,8 @@ #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 +int davinci_init_wdt(void); + /* DM355 function declarations */ void dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, diff -Nur linux-3.14.1/arch/arm/mach-davinci/devices.c linux-3.15-rc1.orig/arch/arm/mach-davinci/devices.c --- linux-3.14.1/arch/arm/mach-davinci/devices.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/devices.c 2014-04-13 23:18:35.000000000 +0200 @@ -313,9 +313,9 @@ davinci_watchdog_reset(&davinci_wdt_device); } -static void davinci_init_wdt(void) +int davinci_init_wdt(void) { - platform_device_register(&davinci_wdt_device); + return platform_device_register(&davinci_wdt_device); } static struct platform_device davinci_gpio_device = { @@ -348,16 +348,3 @@ }, }; -/*-------------------------------------------------------------------------*/ - -static int __init davinci_init_devices(void) -{ - /* please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ - davinci_init_wdt(); - - return 0; -} -arch_initcall(davinci_init_devices); - diff -Nur linux-3.14.1/arch/arm/mach-davinci/devices-da8xx.c linux-3.15-rc1.orig/arch/arm/mach-davinci/devices-da8xx.c --- linux-3.14.1/arch/arm/mach-davinci/devices-da8xx.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/devices-da8xx.c 2014-04-13 23:18:35.000000000 +0200 @@ -1020,7 +1020,6 @@ } #ifdef CONFIG_ARCH_DAVINCI_DA850 - static struct resource da850_sata_resources[] = { { .start = DA850_SATA_BASE, @@ -1028,103 +1027,22 @@ .flags = IORESOURCE_MEM, }, { + .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, + .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, + .flags = IORESOURCE_MEM, + }, + { .start = IRQ_DA850_SATAINT, .flags = IORESOURCE_IRQ, }, }; -/* SATA PHY Control Register offset from AHCI base */ -#define SATA_P0PHYCR_REG 0x178 - -#define SATA_PHY_MPY(x) ((x) << 0) -#define SATA_PHY_LOS(x) ((x) << 6) -#define SATA_PHY_RXCDR(x) ((x) << 10) -#define SATA_PHY_RXEQ(x) ((x) << 13) -#define SATA_PHY_TXSWING(x) ((x) << 19) -#define SATA_PHY_ENPLL(x) ((x) << 31) - -static struct clk *da850_sata_clk; -static unsigned long da850_sata_refclkpn; - -/* Supported DA850 SATA crystal frequencies */ -#define KHZ_TO_HZ(freq) ((freq) * 1000) -static unsigned long da850_sata_xtal[] = { - KHZ_TO_HZ(300000), - KHZ_TO_HZ(250000), - 0, /* Reserved */ - KHZ_TO_HZ(187500), - KHZ_TO_HZ(150000), - KHZ_TO_HZ(125000), - KHZ_TO_HZ(120000), - KHZ_TO_HZ(100000), - KHZ_TO_HZ(75000), - KHZ_TO_HZ(60000), -}; - -static int da850_sata_init(struct device *dev, void __iomem *addr) -{ - int i, ret; - unsigned int val; - - da850_sata_clk = clk_get(dev, NULL); - if (IS_ERR(da850_sata_clk)) - return PTR_ERR(da850_sata_clk); - - ret = clk_prepare_enable(da850_sata_clk); - if (ret) - goto err0; - - /* Enable SATA clock receiver */ - val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); - val &= ~BIT(0); - __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); - - /* Get the multiplier needed for 1.5GHz PLL output */ - for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++) - if (da850_sata_xtal[i] == da850_sata_refclkpn) - break; - - if (i == ARRAY_SIZE(da850_sata_xtal)) { - ret = -EINVAL; - goto err1; - } - - val = SATA_PHY_MPY(i + 1) | - SATA_PHY_LOS(1) | - SATA_PHY_RXCDR(4) | - SATA_PHY_RXEQ(1) | - SATA_PHY_TXSWING(3) | - SATA_PHY_ENPLL(1); - - __raw_writel(val, addr + SATA_P0PHYCR_REG); - - return 0; - -err1: - clk_disable_unprepare(da850_sata_clk); -err0: - clk_put(da850_sata_clk); - return ret; -} - -static void da850_sata_exit(struct device *dev) -{ - clk_disable_unprepare(da850_sata_clk); - clk_put(da850_sata_clk); -} - -static struct ahci_platform_data da850_sata_pdata = { - .init = da850_sata_init, - .exit = da850_sata_exit, -}; - static u64 da850_sata_dmamask = DMA_BIT_MASK(32); static struct platform_device da850_sata_device = { - .name = "ahci", + .name = "ahci_da850", .id = -1, .dev = { - .platform_data = &da850_sata_pdata, .dma_mask = &da850_sata_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), }, @@ -1134,9 +1052,8 @@ int __init da850_register_sata(unsigned long refclkpn) { - da850_sata_refclkpn = refclkpn; - if (!da850_sata_refclkpn) - return -EINVAL; + /* please see comment in drivers/ata/ahci_da850.c */ + BUG_ON(refclkpn != 100 * 1000 * 1000); return platform_device_register(&da850_sata_device); } diff -Nur linux-3.14.1/arch/arm/mach-davinci/devices-tnetv107x.c linux-3.15-rc1.orig/arch/arm/mach-davinci/devices-tnetv107x.c --- linux-3.14.1/arch/arm/mach-davinci/devices-tnetv107x.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/devices-tnetv107x.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,434 +0,0 @@ -/* - * Texas Instruments TNETV107X SoC devices - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "clock.h" - -/* Base addresses for on-chip devices */ -#define TNETV107X_TPCC_BASE 0x01c00000 -#define TNETV107X_TPTC0_BASE 0x01c10000 -#define TNETV107X_TPTC1_BASE 0x01c10400 -#define TNETV107X_WDOG_BASE 0x08086700 -#define TNETV107X_TSC_BASE 0x08088500 -#define TNETV107X_SDIO0_BASE 0x08088700 -#define TNETV107X_SDIO1_BASE 0x08088800 -#define TNETV107X_KEYPAD_BASE 0x08088a00 -#define TNETV107X_SSP_BASE 0x08088c00 -#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 -#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 - -/* TNETV107X specific EDMA3 information */ -#define EDMA_TNETV107X_NUM_DMACH 64 -#define EDMA_TNETV107X_NUM_TCC 64 -#define EDMA_TNETV107X_NUM_PARAMENTRY 128 -#define EDMA_TNETV107X_NUM_EVQUE 2 -#define EDMA_TNETV107X_NUM_TC 2 -#define EDMA_TNETV107X_CHMAP_EXIST 0 -#define EDMA_TNETV107X_NUM_REGIONS 4 -#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u -#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu - -#define TNETV107X_DMACH_SDIO0_RX 26 -#define TNETV107X_DMACH_SDIO0_TX 27 -#define TNETV107X_DMACH_SDIO1_RX 28 -#define TNETV107X_DMACH_SDIO1_TX 29 - -static s8 edma_tc_mapping[][2] = { - /* event queue no TC no */ - { 0, 0 }, - { 1, 1 }, - { -1, -1 } -}; - -static s8 edma_priority_mapping[][2] = { - /* event queue no Prio */ - { 0, 3 }, - { 1, 7 }, - { -1, -1 } -}; - -static struct edma_soc_info edma_cc0_info = { - .n_channel = EDMA_TNETV107X_NUM_DMACH, - .n_region = EDMA_TNETV107X_NUM_REGIONS, - .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY, - .n_tc = EDMA_TNETV107X_NUM_TC, - .n_cc = 1, - .queue_tc_mapping = edma_tc_mapping, - .queue_priority_mapping = edma_priority_mapping, - .default_queue = EVENTQ_1, -}; - -static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, -}; - -static struct resource edma_resources[] = { - { - .name = "edma_cc0", - .start = TNETV107X_TPCC_BASE, - .end = TNETV107X_TPCC_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc0", - .start = TNETV107X_TPTC0_BASE, - .end = TNETV107X_TPTC0_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc1", - .start = TNETV107X_TPTC1_BASE, - .end = TNETV107X_TPTC1_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma0", - .start = IRQ_TNETV107X_TPCC, - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma0_err", - .start = IRQ_TNETV107X_TPCC_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device edma_device = { - .name = "edma", - .id = -1, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, - .dev.platform_data = tnetv107x_edma_info, -}; - -static struct plat_serial8250_port serial0_platform_data[] = { - { - .mapbase = TNETV107X_UART0_BASE, - .irq = IRQ_TNETV107X_UART0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_FIXED_TYPE | UPF_IOREMAP, - .type = PORT_AR7, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port serial1_platform_data[] = { - { - .mapbase = TNETV107X_UART1_BASE, - .irq = IRQ_TNETV107X_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_FIXED_TYPE | UPF_IOREMAP, - .type = PORT_AR7, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port serial2_platform_data[] = { - { - .mapbase = TNETV107X_UART2_BASE, - .irq = IRQ_TNETV107X_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_FIXED_TYPE | UPF_IOREMAP, - .type = PORT_AR7, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; - - -struct platform_device tnetv107x_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = serial0_platform_data, - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev.platform_data = serial1_platform_data, - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev.platform_data = serial2_platform_data, - }, - { - } -}; - -static struct resource mmc0_resources[] = { - { /* Memory mapped registers */ - .start = TNETV107X_SDIO0_BASE, - .end = TNETV107X_SDIO0_BASE + 0x0ff, - .flags = IORESOURCE_MEM - }, - { /* MMC interrupt */ - .start = IRQ_TNETV107X_MMC0, - .flags = IORESOURCE_IRQ - }, - { /* SDIO interrupt */ - .start = IRQ_TNETV107X_SDIO0, - .flags = IORESOURCE_IRQ - }, - { /* DMA RX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX), - .flags = IORESOURCE_DMA - }, - { /* DMA TX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX), - .flags = IORESOURCE_DMA - }, -}; - -static struct resource mmc1_resources[] = { - { /* Memory mapped registers */ - .start = TNETV107X_SDIO1_BASE, - .end = TNETV107X_SDIO1_BASE + 0x0ff, - .flags = IORESOURCE_MEM - }, - { /* MMC interrupt */ - .start = IRQ_TNETV107X_MMC1, - .flags = IORESOURCE_IRQ - }, - { /* SDIO interrupt */ - .start = IRQ_TNETV107X_SDIO1, - .flags = IORESOURCE_IRQ - }, - { /* DMA RX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX), - .flags = IORESOURCE_DMA - }, - { /* DMA TX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX), - .flags = IORESOURCE_DMA - }, -}; - -static u64 mmc0_dma_mask = DMA_BIT_MASK(32); -static u64 mmc1_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device mmc_devices[2] = { - { - .name = "dm6441-mmc", - .id = 0, - .dev = { - .dma_mask = &mmc0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmc0_resources), - .resource = mmc0_resources - }, - { - .name = "dm6441-mmc", - .id = 1, - .dev = { - .dma_mask = &mmc1_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmc1_resources), - .resource = mmc1_resources - }, -}; - -static const u32 emif_windows[] = { - TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE, - TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE, -}; - -static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M }; - -static struct resource wdt_resources[] = { - { - .start = TNETV107X_WDOG_BASE, - .end = TNETV107X_WDOG_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device tnetv107x_wdt_device = { - .name = "tnetv107x_wdt", - .id = 0, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -static int __init nand_init(int chipsel, struct davinci_nand_pdata *data) -{ - struct resource res[2]; - struct platform_device *pdev; - u32 range; - int ret; - - /* Figure out the resource range from the ale/cle masks */ - range = max(data->mask_cle, data->mask_ale); - range = PAGE_ALIGN(range + 4) - 1; - - if (range >= emif_window_sizes[chipsel]) - return -EINVAL; - - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) - return -ENOMEM; - - pdev->name = "davinci_nand"; - pdev->id = chipsel; - pdev->dev.platform_data = data; - - memset(res, 0, sizeof(res)); - - res[0].start = emif_windows[chipsel]; - res[0].end = res[0].start + range; - res[0].flags = IORESOURCE_MEM; - - res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE; - res[1].end = res[1].start + SZ_4K - 1; - res[1].flags = IORESOURCE_MEM; - - ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); - if (ret < 0) { - kfree(pdev); - return ret; - } - - return platform_device_register(pdev); -} - -static struct resource keypad_resources[] = { - { - .start = TNETV107X_KEYPAD_BASE, - .end = TNETV107X_KEYPAD_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_TNETV107X_KEYPAD, - .flags = IORESOURCE_IRQ, - .name = "press", - }, - { - .start = IRQ_TNETV107X_KEYPAD_FREE, - .flags = IORESOURCE_IRQ, - .name = "release", - }, -}; - -static struct platform_device keypad_device = { - .name = "tnetv107x-keypad", - .num_resources = ARRAY_SIZE(keypad_resources), - .resource = keypad_resources, -}; - -static struct resource tsc_resources[] = { - { - .start = TNETV107X_TSC_BASE, - .end = TNETV107X_TSC_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_TNETV107X_TSC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tsc_device = { - .name = "tnetv107x-ts", - .num_resources = ARRAY_SIZE(tsc_resources), - .resource = tsc_resources, -}; - -static struct resource ssp_resources[] = { - { - .start = TNETV107X_SSP_BASE, - .end = TNETV107X_SSP_BASE + 0x1ff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_TNETV107X_SSP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ssp_device = { - .name = "ti-ssp", - .id = -1, - .num_resources = ARRAY_SIZE(ssp_resources), - .resource = ssp_resources, -}; - -void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) -{ - int i, error; - struct clk *tsc_clk; - - /* - * The reset defaults for tnetv107x tsc clock divider is set too high. - * This forces the clock down to a range that allows the ADC to - * complete sample conversion in time. - */ - tsc_clk = clk_get(NULL, "sys_tsc_clk"); - if (!IS_ERR(tsc_clk)) { - error = clk_set_rate(tsc_clk, 5000000); - WARN_ON(error < 0); - clk_put(tsc_clk); - } - - platform_device_register(&edma_device); - platform_device_register(&tnetv107x_wdt_device); - platform_device_register(&tsc_device); - - if (info->serial_config) - davinci_serial_init(tnetv107x_serial_device); - - for (i = 0; i < 2; i++) - if (info->mmc_config[i]) { - mmc_devices[i].dev.platform_data = info->mmc_config[i]; - platform_device_register(&mmc_devices[i]); - } - - for (i = 0; i < 4; i++) - if (info->nand_config[i]) - nand_init(i, info->nand_config[i]); - - if (info->keypad_config) { - keypad_device.dev.platform_data = info->keypad_config; - platform_device_register(&keypad_device); - } - - if (info->ssp_config) { - ssp_device.dev.platform_data = info->ssp_config; - platform_device_register(&ssp_device); - } -} diff -Nur linux-3.14.1/arch/arm/mach-davinci/dm355.c linux-3.15-rc1.orig/arch/arm/mach-davinci/dm355.c --- linux-3.14.1/arch/arm/mach-davinci/dm355.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/dm355.c 2014-04-13 23:18:35.000000000 +0200 @@ -1076,12 +1076,18 @@ static int __init dm355_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm355()) return 0; davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm355_init_devices); diff -Nur linux-3.14.1/arch/arm/mach-davinci/dm365.c linux-3.15-rc1.orig/arch/arm/mach-davinci/dm365.c --- linux-3.14.1/arch/arm/mach-davinci/dm365.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/dm365.c 2014-04-13 23:18:35.000000000 +0200 @@ -1436,6 +1436,8 @@ static int __init dm365_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm365()) return 0; @@ -1445,6 +1447,10 @@ platform_device_register(&dm365_mdio_device); platform_device_register(&dm365_emac_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm365_init_devices); diff -Nur linux-3.14.1/arch/arm/mach-davinci/dm644x.c linux-3.15-rc1.orig/arch/arm/mach-davinci/dm644x.c --- linux-3.14.1/arch/arm/mach-davinci/dm644x.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/dm644x.c 2014-04-13 23:18:35.000000000 +0200 @@ -964,6 +964,8 @@ static int __init dm644x_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm644x()) return 0; @@ -972,6 +974,10 @@ platform_device_register(&dm644x_mdio_device); platform_device_register(&dm644x_emac_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm644x_init_devices); diff -Nur linux-3.14.1/arch/arm/mach-davinci/dm646x.c linux-3.15-rc1.orig/arch/arm/mach-davinci/dm646x.c --- linux-3.14.1/arch/arm/mach-davinci/dm646x.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/dm646x.c 2014-04-13 23:18:35.000000000 +0200 @@ -955,12 +955,18 @@ static int __init dm646x_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm646x()) return 0; platform_device_register(&dm646x_mdio_device); platform_device_register(&dm646x_emac_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm646x_init_devices); diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/cputype.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/cputype.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/cputype.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/cputype.h 2014-04-13 23:18:35.000000000 +0200 @@ -33,7 +33,6 @@ #define DAVINCI_CPU_ID_DM365 0x03650000 #define DAVINCI_CPU_ID_DA830 0x08300000 #define DAVINCI_CPU_ID_DA850 0x08500000 -#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) -IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -85,10 +83,4 @@ #define cpu_is_davinci_da850() 0 #endif -#ifdef CONFIG_ARCH_DAVINCI_TNETV107X -#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x() -#else -#define cpu_is_davinci_tnetv107x() 0 -#endif - #endif diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/irqs.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/irqs.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/irqs.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/irqs.h 2014-04-13 23:18:35.000000000 +0200 @@ -401,103 +401,6 @@ #define DA850_N_CP_INTC_IRQ 101 - -/* TNETV107X specific interrupts */ -#define IRQ_TNETV107X_TDM1_TXDMA 0 -#define IRQ_TNETV107X_EXT_INT_0 1 -#define IRQ_TNETV107X_EXT_INT_1 2 -#define IRQ_TNETV107X_GPIO_INT12 3 -#define IRQ_TNETV107X_GPIO_INT13 4 -#define IRQ_TNETV107X_TIMER_0_TINT12 5 -#define IRQ_TNETV107X_TIMER_1_TINT12 6 -#define IRQ_TNETV107X_UART0 7 -#define IRQ_TNETV107X_TDM1_RXDMA 8 -#define IRQ_TNETV107X_MCDMA_INT0 9 -#define IRQ_TNETV107X_MCDMA_INT1 10 -#define IRQ_TNETV107X_TPCC 11 -#define IRQ_TNETV107X_TPCC_INT0 12 -#define IRQ_TNETV107X_TPCC_INT1 13 -#define IRQ_TNETV107X_TPCC_INT2 14 -#define IRQ_TNETV107X_TPCC_INT3 15 -#define IRQ_TNETV107X_TPTC0 16 -#define IRQ_TNETV107X_TPTC1 17 -#define IRQ_TNETV107X_TIMER_0_TINT34 18 -#define IRQ_TNETV107X_ETHSS 19 -#define IRQ_TNETV107X_TIMER_1_TINT34 20 -#define IRQ_TNETV107X_DSP2ARM_INT0 21 -#define IRQ_TNETV107X_DSP2ARM_INT1 22 -#define IRQ_TNETV107X_ARM_NPMUIRQ 23 -#define IRQ_TNETV107X_USB1 24 -#define IRQ_TNETV107X_VLYNQ 25 -#define IRQ_TNETV107X_UART0_DMATX 26 -#define IRQ_TNETV107X_UART0_DMARX 27 -#define IRQ_TNETV107X_TDM1_TXMCSP 28 -#define IRQ_TNETV107X_SSP 29 -#define IRQ_TNETV107X_MCDMA_INT2 30 -#define IRQ_TNETV107X_MCDMA_INT3 31 -#define IRQ_TNETV107X_TDM_CODECIF_EOT 32 -#define IRQ_TNETV107X_IMCOP_SQR_ARM 33 -#define IRQ_TNETV107X_USB0 34 -#define IRQ_TNETV107X_USB_CDMA 35 -#define IRQ_TNETV107X_LCD 36 -#define IRQ_TNETV107X_KEYPAD 37 -#define IRQ_TNETV107X_KEYPAD_FREE 38 -#define IRQ_TNETV107X_RNG 39 -#define IRQ_TNETV107X_PKA 40 -#define IRQ_TNETV107X_TDM0_TXDMA 41 -#define IRQ_TNETV107X_TDM0_RXDMA 42 -#define IRQ_TNETV107X_TDM0_TXMCSP 43 -#define IRQ_TNETV107X_TDM0_RXMCSP 44 -#define IRQ_TNETV107X_TDM1_RXMCSP 45 -#define IRQ_TNETV107X_SDIO1 46 -#define IRQ_TNETV107X_SDIO0 47 -#define IRQ_TNETV107X_TSC 48 -#define IRQ_TNETV107X_TS 49 -#define IRQ_TNETV107X_UART1 50 -#define IRQ_TNETV107X_MBX_LITE 51 -#define IRQ_TNETV107X_GPIO_INT00 52 -#define IRQ_TNETV107X_GPIO_INT01 53 -#define IRQ_TNETV107X_GPIO_INT02 54 -#define IRQ_TNETV107X_GPIO_INT03 55 -#define IRQ_TNETV107X_UART2 56 -#define IRQ_TNETV107X_UART2_DMATX 57 -#define IRQ_TNETV107X_UART2_DMARX 58 -#define IRQ_TNETV107X_IMCOP_IMX 59 -#define IRQ_TNETV107X_IMCOP_VLCD 60 -#define IRQ_TNETV107X_AES 61 -#define IRQ_TNETV107X_DES 62 -#define IRQ_TNETV107X_SHAMD5 63 -#define IRQ_TNETV107X_TPCC_ERR 68 -#define IRQ_TNETV107X_TPCC_PROT 69 -#define IRQ_TNETV107X_TPTC0_ERR 70 -#define IRQ_TNETV107X_TPTC1_ERR 71 -#define IRQ_TNETV107X_UART0_ERR 72 -#define IRQ_TNETV107X_UART1_ERR 73 -#define IRQ_TNETV107X_AEMIF_ERR 74 -#define IRQ_TNETV107X_DDR_ERR 75 -#define IRQ_TNETV107X_WDTARM_INT0 76 -#define IRQ_TNETV107X_MCDMA_ERR 77 -#define IRQ_TNETV107X_GPIO_ERR 78 -#define IRQ_TNETV107X_MPU_ADDR 79 -#define IRQ_TNETV107X_MPU_PROT 80 -#define IRQ_TNETV107X_IOPU_ADDR 81 -#define IRQ_TNETV107X_IOPU_PROT 82 -#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83 -#define IRQ_TNETV107X_WDT0_ADDR_ERR 84 -#define IRQ_TNETV107X_WDT1_ADDR_ERR 85 -#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86 -#define IRQ_TNETV107X_PLL_UNLOCK 87 -#define IRQ_TNETV107X_WDTDSP_INT0 88 -#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89 -#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90 -#define IRQ_TNETV107X_PBIST_CPU 91 -#define IRQ_TNETV107X_WDTARM 92 -#define IRQ_TNETV107X_PSC 93 -#define IRQ_TNETV107X_MMC0 94 -#define IRQ_TNETV107X_MMC1 95 - -#define TNETV107X_N_CP_INTC_IRQ 96 - /* da850 currently has the most gpio pins (144) */ #define DAVINCI_N_GPIO 144 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/mux.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/mux.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/mux.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/mux.h 2014-04-13 23:18:35.000000000 +0200 @@ -972,275 +972,6 @@ DA850_VPIF_CLKO3, }; -enum davinci_tnetv107x_index { - TNETV107X_ASR_A00, - TNETV107X_GPIO32, - TNETV107X_ASR_A01, - TNETV107X_GPIO33, - TNETV107X_ASR_A02, - TNETV107X_GPIO34, - TNETV107X_ASR_A03, - TNETV107X_GPIO35, - TNETV107X_ASR_A04, - TNETV107X_GPIO36, - TNETV107X_ASR_A05, - TNETV107X_GPIO37, - TNETV107X_ASR_A06, - TNETV107X_GPIO38, - TNETV107X_ASR_A07, - TNETV107X_GPIO39, - TNETV107X_ASR_A08, - TNETV107X_GPIO40, - TNETV107X_ASR_A09, - TNETV107X_GPIO41, - TNETV107X_ASR_A10, - TNETV107X_GPIO42, - TNETV107X_ASR_A11, - TNETV107X_BOOT_STRP_0, - TNETV107X_ASR_A12, - TNETV107X_BOOT_STRP_1, - TNETV107X_ASR_A13, - TNETV107X_GPIO43, - TNETV107X_ASR_A14, - TNETV107X_GPIO44, - TNETV107X_ASR_A15, - TNETV107X_GPIO45, - TNETV107X_ASR_A16, - TNETV107X_GPIO46, - TNETV107X_ASR_A17, - TNETV107X_GPIO47, - TNETV107X_ASR_A18, - TNETV107X_GPIO48, - TNETV107X_SDIO1_DATA3_0, - TNETV107X_ASR_A19, - TNETV107X_GPIO49, - TNETV107X_SDIO1_DATA2_0, - TNETV107X_ASR_A20, - TNETV107X_GPIO50, - TNETV107X_SDIO1_DATA1_0, - TNETV107X_ASR_A21, - TNETV107X_GPIO51, - TNETV107X_SDIO1_DATA0_0, - TNETV107X_ASR_A22, - TNETV107X_GPIO52, - TNETV107X_SDIO1_CMD_0, - TNETV107X_ASR_A23, - TNETV107X_GPIO53, - TNETV107X_SDIO1_CLK_0, - TNETV107X_ASR_BA_1, - TNETV107X_GPIO54, - TNETV107X_SYS_PLL_CLK, - TNETV107X_ASR_CS0, - TNETV107X_ASR_CS1, - TNETV107X_ASR_CS2, - TNETV107X_TDM_PLL_CLK, - TNETV107X_ASR_CS3, - TNETV107X_ETH_PHY_CLK, - TNETV107X_ASR_D00, - TNETV107X_GPIO55, - TNETV107X_ASR_D01, - TNETV107X_GPIO56, - TNETV107X_ASR_D02, - TNETV107X_GPIO57, - TNETV107X_ASR_D03, - TNETV107X_GPIO58, - TNETV107X_ASR_D04, - TNETV107X_GPIO59_0, - TNETV107X_ASR_D05, - TNETV107X_GPIO60_0, - TNETV107X_ASR_D06, - TNETV107X_GPIO61_0, - TNETV107X_ASR_D07, - TNETV107X_GPIO62_0, - TNETV107X_ASR_D08, - TNETV107X_GPIO63_0, - TNETV107X_ASR_D09, - TNETV107X_GPIO64_0, - TNETV107X_ASR_D10, - TNETV107X_SDIO1_DATA3_1, - TNETV107X_ASR_D11, - TNETV107X_SDIO1_DATA2_1, - TNETV107X_ASR_D12, - TNETV107X_SDIO1_DATA1_1, - TNETV107X_ASR_D13, - TNETV107X_SDIO1_DATA0_1, - TNETV107X_ASR_D14, - TNETV107X_SDIO1_CMD_1, - TNETV107X_ASR_D15, - TNETV107X_SDIO1_CLK_1, - TNETV107X_ASR_OE, - TNETV107X_BOOT_STRP_2, - TNETV107X_ASR_RNW, - TNETV107X_GPIO29_0, - TNETV107X_ASR_WAIT, - TNETV107X_GPIO30_0, - TNETV107X_ASR_WE, - TNETV107X_BOOT_STRP_3, - TNETV107X_ASR_WE_DQM0, - TNETV107X_GPIO31, - TNETV107X_LCD_PD17_0, - TNETV107X_ASR_WE_DQM1, - TNETV107X_ASR_BA0_0, - TNETV107X_VLYNQ_CLK, - TNETV107X_GPIO14, - TNETV107X_LCD_PD19_0, - TNETV107X_VLYNQ_RXD0, - TNETV107X_GPIO15, - TNETV107X_LCD_PD20_0, - TNETV107X_VLYNQ_RXD1, - TNETV107X_GPIO16, - TNETV107X_LCD_PD21_0, - TNETV107X_VLYNQ_TXD0, - TNETV107X_GPIO17, - TNETV107X_LCD_PD22_0, - TNETV107X_VLYNQ_TXD1, - TNETV107X_GPIO18, - TNETV107X_LCD_PD23_0, - TNETV107X_SDIO0_CLK, - TNETV107X_GPIO19, - TNETV107X_SDIO0_CMD, - TNETV107X_GPIO20, - TNETV107X_SDIO0_DATA0, - TNETV107X_GPIO21, - TNETV107X_SDIO0_DATA1, - TNETV107X_GPIO22, - TNETV107X_SDIO0_DATA2, - TNETV107X_GPIO23, - TNETV107X_SDIO0_DATA3, - TNETV107X_GPIO24, - TNETV107X_EMU0, - TNETV107X_EMU1, - TNETV107X_RTCK, - TNETV107X_TRST_N, - TNETV107X_TCK, - TNETV107X_TDI, - TNETV107X_TDO, - TNETV107X_TMS, - TNETV107X_TDM1_CLK, - TNETV107X_TDM1_RX, - TNETV107X_TDM1_TX, - TNETV107X_TDM1_FS, - TNETV107X_KEYPAD_R0, - TNETV107X_KEYPAD_R1, - TNETV107X_KEYPAD_R2, - TNETV107X_KEYPAD_R3, - TNETV107X_KEYPAD_R4, - TNETV107X_KEYPAD_R5, - TNETV107X_KEYPAD_R6, - TNETV107X_GPIO12, - TNETV107X_KEYPAD_R7, - TNETV107X_GPIO10, - TNETV107X_KEYPAD_C0, - TNETV107X_KEYPAD_C1, - TNETV107X_KEYPAD_C2, - TNETV107X_KEYPAD_C3, - TNETV107X_KEYPAD_C4, - TNETV107X_KEYPAD_C5, - TNETV107X_KEYPAD_C6, - TNETV107X_GPIO13, - TNETV107X_TEST_CLK_IN, - TNETV107X_KEYPAD_C7, - TNETV107X_GPIO11, - TNETV107X_SSP0_0, - TNETV107X_SCC_DCLK, - TNETV107X_LCD_PD20_1, - TNETV107X_SSP0_1, - TNETV107X_SCC_CS_N, - TNETV107X_LCD_PD21_1, - TNETV107X_SSP0_2, - TNETV107X_SCC_D, - TNETV107X_LCD_PD22_1, - TNETV107X_SSP0_3, - TNETV107X_SCC_RESETN, - TNETV107X_LCD_PD23_1, - TNETV107X_SSP1_0, - TNETV107X_GPIO25, - TNETV107X_UART2_CTS, - TNETV107X_SSP1_1, - TNETV107X_GPIO26, - TNETV107X_UART2_RD, - TNETV107X_SSP1_2, - TNETV107X_GPIO27, - TNETV107X_UART2_RTS, - TNETV107X_SSP1_3, - TNETV107X_GPIO28, - TNETV107X_UART2_TD, - TNETV107X_UART0_CTS, - TNETV107X_UART0_RD, - TNETV107X_UART0_RTS, - TNETV107X_UART0_TD, - TNETV107X_UART1_RD, - TNETV107X_UART1_TD, - TNETV107X_LCD_AC_NCS, - TNETV107X_LCD_HSYNC_RNW, - TNETV107X_LCD_VSYNC_A0, - TNETV107X_LCD_MCLK, - TNETV107X_LCD_PD16_0, - TNETV107X_LCD_PCLK_E, - TNETV107X_LCD_PD00, - TNETV107X_LCD_PD01, - TNETV107X_LCD_PD02, - TNETV107X_LCD_PD03, - TNETV107X_LCD_PD04, - TNETV107X_LCD_PD05, - TNETV107X_LCD_PD06, - TNETV107X_LCD_PD07, - TNETV107X_LCD_PD08, - TNETV107X_GPIO59_1, - TNETV107X_LCD_PD09, - TNETV107X_GPIO60_1, - TNETV107X_LCD_PD10, - TNETV107X_ASR_BA0_1, - TNETV107X_GPIO61_1, - TNETV107X_LCD_PD11, - TNETV107X_GPIO62_1, - TNETV107X_LCD_PD12, - TNETV107X_GPIO63_1, - TNETV107X_LCD_PD13, - TNETV107X_GPIO64_1, - TNETV107X_LCD_PD14, - TNETV107X_GPIO29_1, - TNETV107X_LCD_PD15, - TNETV107X_GPIO30_1, - TNETV107X_EINT0, - TNETV107X_GPIO08, - TNETV107X_EINT1, - TNETV107X_GPIO09, - TNETV107X_GPIO00, - TNETV107X_LCD_PD20_2, - TNETV107X_TDM_CLK_IN_2, - TNETV107X_GPIO01, - TNETV107X_LCD_PD21_2, - TNETV107X_24M_CLK_OUT_1, - TNETV107X_GPIO02, - TNETV107X_LCD_PD22_2, - TNETV107X_GPIO03, - TNETV107X_LCD_PD23_2, - TNETV107X_GPIO04, - TNETV107X_LCD_PD16_1, - TNETV107X_USB0_RXERR, - TNETV107X_GPIO05, - TNETV107X_LCD_PD17_1, - TNETV107X_TDM_CLK_IN_1, - TNETV107X_GPIO06, - TNETV107X_LCD_PD18, - TNETV107X_24M_CLK_OUT_2, - TNETV107X_GPIO07, - TNETV107X_LCD_PD19_1, - TNETV107X_USB1_RXERR, - TNETV107X_ETH_PLL_CLK, - TNETV107X_MDIO, - TNETV107X_MDC, - TNETV107X_AIC_MUTE_STAT_N, - TNETV107X_TDM0_CLK, - TNETV107X_AIC_HNS_EN_N, - TNETV107X_TDM0_FS, - TNETV107X_AIC_HDS_EN_STAT_N, - TNETV107X_TDM0_TX, - TNETV107X_AIC_HNF_EN_STAT_N, - TNETV107X_TDM0_RX, -}; - #define PINMUX(x) (4 * (x)) #ifdef CONFIG_DAVINCI_MUX diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/psc.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/psc.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/psc.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/psc.h 2014-04-13 23:18:35.000000000 +0200 @@ -182,53 +182,6 @@ #define DA8XX_LPSC1_CR_P3_SS 26 #define DA8XX_LPSC1_L3_CBA_RAM 31 -/* TNETV107X LPSC Assignments */ -#define TNETV107X_LPSC_ARM 0 -#define TNETV107X_LPSC_GEM 1 -#define TNETV107X_LPSC_DDR2_PHY 2 -#define TNETV107X_LPSC_TPCC 3 -#define TNETV107X_LPSC_TPTC0 4 -#define TNETV107X_LPSC_TPTC1 5 -#define TNETV107X_LPSC_RAM 6 -#define TNETV107X_LPSC_MBX_LITE 7 -#define TNETV107X_LPSC_LCD 8 -#define TNETV107X_LPSC_ETHSS 9 -#define TNETV107X_LPSC_AEMIF 10 -#define TNETV107X_LPSC_CHIP_CFG 11 -#define TNETV107X_LPSC_TSC 12 -#define TNETV107X_LPSC_ROM 13 -#define TNETV107X_LPSC_UART2 14 -#define TNETV107X_LPSC_PKTSEC 15 -#define TNETV107X_LPSC_SECCTL 16 -#define TNETV107X_LPSC_KEYMGR 17 -#define TNETV107X_LPSC_KEYPAD 18 -#define TNETV107X_LPSC_GPIO 19 -#define TNETV107X_LPSC_MDIO 20 -#define TNETV107X_LPSC_SDIO0 21 -#define TNETV107X_LPSC_UART0 22 -#define TNETV107X_LPSC_UART1 23 -#define TNETV107X_LPSC_TIMER0 24 -#define TNETV107X_LPSC_TIMER1 25 -#define TNETV107X_LPSC_WDT_ARM 26 -#define TNETV107X_LPSC_WDT_DSP 27 -#define TNETV107X_LPSC_SSP 28 -#define TNETV107X_LPSC_TDM0 29 -#define TNETV107X_LPSC_VLYNQ 30 -#define TNETV107X_LPSC_MCDMA 31 -#define TNETV107X_LPSC_USB0 32 -#define TNETV107X_LPSC_TDM1 33 -#define TNETV107X_LPSC_DEBUGSS 34 -#define TNETV107X_LPSC_ETHSS_RGMII 35 -#define TNETV107X_LPSC_SYSTEM 36 -#define TNETV107X_LPSC_IMCOP 37 -#define TNETV107X_LPSC_SPARE 38 -#define TNETV107X_LPSC_SDIO1 39 -#define TNETV107X_LPSC_USB1 40 -#define TNETV107X_LPSC_USBSS 41 -#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 -#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 -#define TNETV107X_LPSC_MAX 44 - /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/serial.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/serial.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/serial.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/serial.h 2014-04-13 23:18:35.000000000 +0200 @@ -23,14 +23,6 @@ #define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) #define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) -#define TNETV107X_UART0_BASE 0x08108100 -#define TNETV107X_UART1_BASE 0x08088400 -#define TNETV107X_UART2_BASE 0x08108300 - -#define TNETV107X_UART0_VIRT IOMEM(0xfee08100) -#define TNETV107X_UART1_VIRT IOMEM(0xfed88400) -#define TNETV107X_UART2_VIRT IOMEM(0xfee08300) - /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,22 +0,0 @@ -/* - * DaVinci timer defines - * - * Author: Kevin Hilman, MontaVista Software, Inc. - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* - * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz, - * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/ - * linux/jiffies.h) are not used directly in code. Currently none of the - * code relevant to DaVinci platform depends on these values directly. - */ -#define CLOCK_TICK_RATE 27000000 - -#endif /* __ASM_ARCH_TIMEX_H__ */ diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/tnetv107x.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/tnetv107x.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/tnetv107x.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/tnetv107x.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,61 +0,0 @@ -/* - * Texas Instruments TNETV107X SoC Specific Defines - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H -#define __ASM_ARCH_DAVINCI_TNETV107X_H - -#include - -#define TNETV107X_DDR_BASE 0x80000000 - -/* - * Fixed mapping for early init starts here. If low-level debug is enabled, - * this area also gets mapped via io_pg_offset and io_phys by the boot code. - * To fit in with the io_pg_offset calculation, the io base address selected - * here _must_ be a multiple of 2^20. - */ -#define TNETV107X_IO_BASE 0x08000000 -#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M) - -#define TNETV107X_N_GPIO 65 - -#ifndef __ASSEMBLY__ - -#include -#include -#include -#include - -#include -#include -#include - -struct tnetv107x_device_info { - struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ - struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ - struct matrix_keypad_platform_data *keypad_config; - struct ti_ssp_data *ssp_config; -}; - -extern struct platform_device tnetv107x_wdt_device; -extern struct platform_device tnetv107x_serial_device[]; - -extern void tnetv107x_init(void); -extern void tnetv107x_devices_init(struct tnetv107x_device_info *); -extern void tnetv107x_irq_init(void); -void tnetv107x_restart(enum reboot_mode mode, const char *cmd); - -#endif - -#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */ diff -Nur linux-3.14.1/arch/arm/mach-davinci/include/mach/uncompress.h linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/uncompress.h --- linux-3.14.1/arch/arm/mach-davinci/include/mach/uncompress.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/include/mach/uncompress.h 2014-04-13 23:18:35.000000000 +0200 @@ -68,9 +68,6 @@ #define DEBUG_LL_DA8XX(machine, port) \ _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE) -#define DEBUG_LL_TNETV107X(machine, port) \ - _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE) - static inline void __arch_decomp_setup(unsigned long arch_id) { /* @@ -94,9 +91,6 @@ DEBUG_LL_DA8XX(davinci_da850_evm, 2); DEBUG_LL_DA8XX(mityomapl138, 1); DEBUG_LL_DA8XX(omapl138_hawkboard, 2); - - /* TNETV107x boards */ - DEBUG_LL_TNETV107X(tnetv107x, 1); } while (0); } diff -Nur linux-3.14.1/arch/arm/mach-davinci/Kconfig linux-3.15-rc1.orig/arch/arm/mach-davinci/Kconfig --- linux-3.14.1/arch/arm/mach-davinci/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -51,11 +51,6 @@ select AINTC select ARCH_DAVINCI_DMx -config ARCH_DAVINCI_TNETV107X - bool "TNETV107X based system" - select CPU_V6 - select CP_INTC - comment "DaVinci Board Type" config MACH_DA8XX_DT @@ -214,18 +209,6 @@ Say Y if you want to use a wl1271 expansion card connected to the AM18x EVM. -config GPIO_PCA953X - default MACH_DAVINCI_DA850_EVM - -config KEYBOARD_GPIO_POLLED - default MACH_DAVINCI_DA850_EVM - -config MACH_TNETV107X - bool "TI TNETV107X Reference Platform" - default ARCH_DAVINCI_TNETV107X - depends on ARCH_DAVINCI_TNETV107X - help - Say Y here to select the TI TNETV107X Evaluation Module. config MACH_MITYOMAPL138 bool "Critical Link MityDSP-L138/MityARM-1808 SoM" diff -Nur linux-3.14.1/arch/arm/mach-davinci/Makefile linux-3.15-rc1.orig/arch/arm/mach-davinci/Makefile --- linux-3.14.1/arch/arm/mach-davinci/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o -obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o @@ -32,7 +31,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o -obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o diff -Nur linux-3.14.1/arch/arm/mach-davinci/Makefile.boot linux-3.15-rc1.orig/arch/arm/mach-davinci/Makefile.boot --- linux-3.14.1/arch/arm/mach-davinci/Makefile.boot 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/Makefile.boot 2014-04-13 23:18:35.000000000 +0200 @@ -1,13 +1,7 @@ -ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y) -ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y) -$(error Cannot enable DaVinci and DA8XX platforms concurrently) -else - zreladdr-y += 0xc0008000 -params_phys-y := 0xc0000100 -initrd_phys-y := 0xc0800000 -endif -else - zreladdr-y += 0x80008000 -params_phys-y := 0x80000100 -initrd_phys-y := 0x80800000 -endif +zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX) += 0xc0008000 +params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0000100 +initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0800000 + +zreladdr-$(CONFIG_ARCH_DAVINCI_DMx) += 0x80008000 +params_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80000100 +initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80800000 diff -Nur linux-3.14.1/arch/arm/mach-davinci/tnetv107x.c linux-3.15-rc1.orig/arch/arm/mach-davinci/tnetv107x.c --- linux-3.14.1/arch/arm/mach-davinci/tnetv107x.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-davinci/tnetv107x.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,766 +0,0 @@ -/* - * Texas Instruments TNETV107X SoC Support - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clock.h" -#include "mux.h" - -/* Base addresses for on-chip devices */ -#define TNETV107X_INTC_BASE 0x03000000 -#define TNETV107X_TIMER0_BASE 0x08086500 -#define TNETV107X_TIMER1_BASE 0x08086600 -#define TNETV107X_CHIP_CFG_BASE 0x08087000 -#define TNETV107X_GPIO_BASE 0x08088000 -#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000 -#define TNETV107X_PSC_BASE 0x0808b000 - -/* Reference clock frequencies */ -#define OSC_FREQ_ONCHIP (24000 * 1000) -#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000) -#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000) -#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000) - -#define N_PLLS 3 - -/* Clock Control Registers */ -struct clk_ctrl_regs { - u32 pll_bypass; - u32 _reserved0; - u32 gem_lrst; - u32 _reserved1; - u32 pll_unlock_stat; - u32 sys_unlock; - u32 eth_unlock; - u32 tdm_unlock; -}; - -/* SSPLL Registers */ -struct sspll_regs { - u32 modes; - u32 post_div; - u32 pre_div; - u32 mult_factor; - u32 divider_range; - u32 bw_divider; - u32 spr_amount; - u32 spr_rate_div; - u32 diag; -}; - -/* Watchdog Timer Registers */ -struct wdt_regs { - u32 kick_lock; - u32 kick; - u32 change_lock; - u32 change ; - u32 disable_lock; - u32 disable; - u32 prescale_lock; - u32 prescale; -}; - -static struct clk_ctrl_regs __iomem *clk_ctrl_regs; - -static struct sspll_regs __iomem *sspll_regs[N_PLLS]; -static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 }; - -/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */ -static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) }; - -/* offchip (external) reference clock frequencies */ -static u32 pll_ext_freq[] = { - OSC_FREQ_OFFCHIP_SYS, - OSC_FREQ_OFFCHIP_TDM, - OSC_FREQ_OFFCHIP_ETH -}; - -/* PSC control registers */ -static u32 psc_regs[] = { TNETV107X_PSC_BASE }; - -/* Host map for interrupt controller */ -static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; - -static unsigned long clk_sspll_recalc(struct clk *clk); - -/* Level 1 - the PLLs */ -#define define_pll_clk(cname, pll, divmask, base) \ - static struct pll_data pll_##cname##_data = { \ - .num = pll, \ - .div_ratio_mask = divmask, \ - .phys_base = base + \ - TNETV107X_CLOCK_CONTROL_BASE, \ - }; \ - static struct clk pll_##cname##_clk = { \ - .name = "pll_" #cname "_clk", \ - .pll_data = &pll_##cname##_data, \ - .flags = CLK_PLL, \ - .recalc = clk_sspll_recalc, \ - } - -define_pll_clk(sys, 0, 0x1ff, 0x600); -define_pll_clk(tdm, 1, 0x0ff, 0x200); -define_pll_clk(eth, 2, 0x0ff, 0x400); - -/* Level 2 - divided outputs from the PLLs */ -#define define_pll_div_clk(pll, cname, div) \ - static struct clk pll##_##cname##_clk = { \ - .name = #pll "_" #cname "_clk", \ - .parent = &pll_##pll##_clk, \ - .flags = CLK_PLL, \ - .div_reg = PLLDIV##div, \ - .set_rate = davinci_set_sysclk_rate, \ - } - -define_pll_div_clk(sys, arm1176, 1); -define_pll_div_clk(sys, dsp, 2); -define_pll_div_clk(sys, ddr, 3); -define_pll_div_clk(sys, full, 4); -define_pll_div_clk(sys, lcd, 5); -define_pll_div_clk(sys, vlynq_ref, 6); -define_pll_div_clk(sys, tsc, 7); -define_pll_div_clk(sys, half, 8); - -define_pll_div_clk(eth, 5mhz, 1); -define_pll_div_clk(eth, 50mhz, 2); -define_pll_div_clk(eth, 125mhz, 3); -define_pll_div_clk(eth, 250mhz, 4); -define_pll_div_clk(eth, 25mhz, 5); - -define_pll_div_clk(tdm, 0, 1); -define_pll_div_clk(tdm, extra, 2); -define_pll_div_clk(tdm, 1, 3); - - -/* Level 3 - LPSC gated clocks */ -#define __lpsc_clk(cname, _parent, mod, flg) \ - static struct clk clk_##cname = { \ - .name = #cname, \ - .parent = &_parent, \ - .lpsc = TNETV107X_LPSC_##mod,\ - .flags = flg, \ - } - -#define lpsc_clk_enabled(cname, parent, mod) \ - __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED) - -#define lpsc_clk(cname, parent, mod) \ - __lpsc_clk(cname, parent, mod, 0) - -lpsc_clk_enabled(arm, sys_arm1176_clk, ARM); -lpsc_clk_enabled(gem, sys_dsp_clk, GEM); -lpsc_clk_enabled(ddr2_phy, sys_ddr_clk, DDR2_PHY); -lpsc_clk_enabled(tpcc, sys_full_clk, TPCC); -lpsc_clk_enabled(tptc0, sys_full_clk, TPTC0); -lpsc_clk_enabled(tptc1, sys_full_clk, TPTC1); -lpsc_clk_enabled(ram, sys_full_clk, RAM); -lpsc_clk_enabled(aemif, sys_full_clk, AEMIF); -lpsc_clk_enabled(chipcfg, sys_half_clk, CHIP_CFG); -lpsc_clk_enabled(rom, sys_half_clk, ROM); -lpsc_clk_enabled(secctl, sys_half_clk, SECCTL); -lpsc_clk_enabled(keymgr, sys_half_clk, KEYMGR); -lpsc_clk_enabled(gpio, sys_half_clk, GPIO); -lpsc_clk_enabled(debugss, sys_half_clk, DEBUGSS); -lpsc_clk_enabled(system, sys_half_clk, SYSTEM); -lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); -lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); -lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); -lpsc_clk_enabled(timer1, sys_half_clk, TIMER1); - -lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); -lpsc_clk(ethss, eth_125mhz_clk, ETHSS); -lpsc_clk(tsc, sys_tsc_clk, TSC); -lpsc_clk(uart0, sys_half_clk, UART0); -lpsc_clk(uart1, sys_half_clk, UART1); -lpsc_clk(uart2, sys_half_clk, UART2); -lpsc_clk(pktsec, sys_half_clk, PKTSEC); -lpsc_clk(keypad, sys_half_clk, KEYPAD); -lpsc_clk(mdio, sys_half_clk, MDIO); -lpsc_clk(sdio0, sys_half_clk, SDIO0); -lpsc_clk(sdio1, sys_half_clk, SDIO1); -lpsc_clk(timer0, sys_half_clk, TIMER0); -lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); -lpsc_clk(ssp, sys_half_clk, SSP); -lpsc_clk(tdm0, tdm_0_clk, TDM0); -lpsc_clk(tdm1, tdm_1_clk, TDM1); -lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); -lpsc_clk(mcdma, sys_half_clk, MCDMA); -lpsc_clk(usbss, sys_half_clk, USBSS); -lpsc_clk(usb0, clk_usbss, USB0); -lpsc_clk(usb1, clk_usbss, USB1); -lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); -lpsc_clk(imcop, sys_dsp_clk, IMCOP); -lpsc_clk(spare, sys_half_clk, SPARE); - -/* LCD needs a full power down to clear controller state */ -__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE); - - -/* Level 4 - leaf clocks for LPSC modules shared across drivers */ -static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec }; -static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec }; - -static struct clk_lookup clks[] = { - CLK(NULL, "pll_sys_clk", &pll_sys_clk), - CLK(NULL, "pll_eth_clk", &pll_eth_clk), - CLK(NULL, "pll_tdm_clk", &pll_tdm_clk), - CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk), - CLK(NULL, "sys_dsp_clk", &sys_dsp_clk), - CLK(NULL, "sys_ddr_clk", &sys_ddr_clk), - CLK(NULL, "sys_full_clk", &sys_full_clk), - CLK(NULL, "sys_lcd_clk", &sys_lcd_clk), - CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk), - CLK(NULL, "sys_tsc_clk", &sys_tsc_clk), - CLK(NULL, "sys_half_clk", &sys_half_clk), - CLK(NULL, "eth_5mhz_clk", ð_5mhz_clk), - CLK(NULL, "eth_50mhz_clk", ð_50mhz_clk), - CLK(NULL, "eth_125mhz_clk", ð_125mhz_clk), - CLK(NULL, "eth_250mhz_clk", ð_250mhz_clk), - CLK(NULL, "eth_25mhz_clk", ð_25mhz_clk), - CLK(NULL, "tdm_0_clk", &tdm_0_clk), - CLK(NULL, "tdm_extra_clk", &tdm_extra_clk), - CLK(NULL, "tdm_1_clk", &tdm_1_clk), - CLK(NULL, "clk_arm", &clk_arm), - CLK(NULL, "clk_gem", &clk_gem), - CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy), - CLK(NULL, "clk_tpcc", &clk_tpcc), - CLK(NULL, "clk_tptc0", &clk_tptc0), - CLK(NULL, "clk_tptc1", &clk_tptc1), - CLK(NULL, "clk_ram", &clk_ram), - CLK(NULL, "clk_mbx_lite", &clk_mbx_lite), - CLK("tnetv107x-fb.0", NULL, &clk_lcd), - CLK(NULL, "clk_ethss", &clk_ethss), - CLK(NULL, "aemif", &clk_aemif), - CLK(NULL, "clk_chipcfg", &clk_chipcfg), - CLK("tnetv107x-ts.0", NULL, &clk_tsc), - CLK(NULL, "clk_rom", &clk_rom), - CLK("serial8250.2", NULL, &clk_uart2), - CLK(NULL, "clk_pktsec", &clk_pktsec), - CLK("tnetv107x-rng.0", NULL, &clk_rng), - CLK("tnetv107x-pka.0", NULL, &clk_pka), - CLK(NULL, "clk_secctl", &clk_secctl), - CLK(NULL, "clk_keymgr", &clk_keymgr), - CLK("tnetv107x-keypad.0", NULL, &clk_keypad), - CLK(NULL, "clk_gpio", &clk_gpio), - CLK(NULL, "clk_mdio", &clk_mdio), - CLK("dm6441-mmc.0", NULL, &clk_sdio0), - CLK("serial8250.0", NULL, &clk_uart0), - CLK("serial8250.1", NULL, &clk_uart1), - CLK(NULL, "timer0", &clk_timer0), - CLK(NULL, "timer1", &clk_timer1), - CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), - CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), - CLK("ti-ssp", NULL, &clk_ssp), - CLK(NULL, "clk_tdm0", &clk_tdm0), - CLK(NULL, "clk_vlynq", &clk_vlynq), - CLK(NULL, "clk_mcdma", &clk_mcdma), - CLK(NULL, "clk_usbss", &clk_usbss), - CLK(NULL, "clk_usb0", &clk_usb0), - CLK(NULL, "clk_usb1", &clk_usb1), - CLK(NULL, "clk_tdm1", &clk_tdm1), - CLK(NULL, "clk_debugss", &clk_debugss), - CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), - CLK(NULL, "clk_system", &clk_system), - CLK(NULL, "clk_imcop", &clk_imcop), - CLK(NULL, "clk_spare", &clk_spare), - CLK("dm6441-mmc.1", NULL, &clk_sdio1), - CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), - CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), - CLK(NULL, NULL, NULL), -}; - -static const struct mux_config pins[] = { -#ifdef CONFIG_DAVINCI_MUX - MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false) -#endif -}; - -/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ -static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = { - /* fill in default priority 7 */ - [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)] = 7, - /* now override as needed, e.g. [xxx] = 5 */ -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id ids[] = { - { - .variant = 0x0, - .part_no = 0xb8a1, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_TNETV107X, - .name = "tnetv107x rev 1.0", - }, - { - .variant = 0x1, - .part_no = 0xb8a1, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_TNETV107X, - .name = "tnetv107x rev 1.1/1.2", - }, -}; - -static struct davinci_timer_instance timer_instance[2] = { - { - .base = TNETV107X_TIMER0_BASE, - .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12, - .top_irq = IRQ_TNETV107X_TIMER_0_TINT34, - }, - { - .base = TNETV107X_TIMER1_BASE, - .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12, - .top_irq = IRQ_TNETV107X_TIMER_1_TINT34, - }, -}; - -static struct davinci_timer_info timer_info = { - .timers = timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, -}; - -/* - * TNETV107X platforms do not use the static mappings from Davinci - * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses, - * and changing IO_PHYS would break away from existing Davinci SOCs. - * - * The primary impact of the current model is that IO_ADDRESS() is not to be - * used to map registers on TNETV107X. - * - * 1. The first chunk is for INTC: This needs to be mapped in via iotable - * because ioremap() does not seem to be operational at the time when - * irqs are initialized. Without this, consistent dma init bombs. - * - * 2. The second chunk maps in register areas that need to be populated into - * davinci_soc_info. Note that alignment restrictions come into play if - * low-level debug is enabled (see note in ). - */ -static struct map_desc io_desc[] = { - { /* INTC */ - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(TNETV107X_INTC_BASE), - .length = SZ_16K, - .type = MT_DEVICE - }, - { /* Most of the rest */ - .virtual = TNETV107X_IO_VIRT, - .pfn = __phys_to_pfn(TNETV107X_IO_BASE), - .length = IO_SIZE - SZ_1M, - .type = MT_DEVICE - }, -}; - -static unsigned long clk_sspll_recalc(struct clk *clk) -{ - int pll; - unsigned long mult = 0, prediv = 1, postdiv = 1; - unsigned long ref = OSC_FREQ_ONCHIP, ret; - u32 tmp; - - if (WARN_ON(!clk->pll_data)) - return clk->rate; - - if (!clk_ctrl_regs) { - void __iomem *tmp; - - tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K); - - if (WARN(!tmp, "failed ioremap for clock control regs\n")) - return clk->parent ? clk->parent->rate : 0; - - for (pll = 0; pll < N_PLLS; pll++) - sspll_regs[pll] = tmp + sspll_regs_base[pll]; - - clk_ctrl_regs = tmp; - } - - pll = clk->pll_data->num; - - tmp = __raw_readl(&clk_ctrl_regs->pll_bypass); - if (!(tmp & bypass_mask[pll])) { - mult = __raw_readl(&sspll_regs[pll]->mult_factor); - prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1; - postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1; - } - - tmp = __raw_readl(clk->pll_data->base + PLLCTL); - if (tmp & PLLCTL_CLKMODE) - ref = pll_ext_freq[pll]; - - clk->pll_data->input_rate = ref; - - tmp = __raw_readl(clk->pll_data->base + PLLCTL); - if (!(tmp & PLLCTL_PLLEN)) - return ref; - - ret = ref; - if (mult) - ret += ((unsigned long long)ref * mult) / 256; - - ret /= (prediv * postdiv); - - return ret; -} - -static void tnetv107x_watchdog_reset(struct platform_device *pdev) -{ - struct wdt_regs __iomem *regs; - - regs = ioremap(pdev->resource[0].start, SZ_4K); - - /* disable watchdog */ - __raw_writel(0x7777, ®s->disable_lock); - __raw_writel(0xcccc, ®s->disable_lock); - __raw_writel(0xdddd, ®s->disable_lock); - __raw_writel(0, ®s->disable); - - /* program prescale */ - __raw_writel(0x5a5a, ®s->prescale_lock); - __raw_writel(0xa5a5, ®s->prescale_lock); - __raw_writel(0, ®s->prescale); - - /* program countdown */ - __raw_writel(0x6666, ®s->change_lock); - __raw_writel(0xbbbb, ®s->change_lock); - __raw_writel(1, ®s->change); - - /* enable watchdog */ - __raw_writel(0x7777, ®s->disable_lock); - __raw_writel(0xcccc, ®s->disable_lock); - __raw_writel(0xdddd, ®s->disable_lock); - __raw_writel(1, ®s->disable); - - /* kick */ - __raw_writel(0x5555, ®s->kick_lock); - __raw_writel(0xaaaa, ®s->kick_lock); - __raw_writel(1, ®s->kick); -} - -void tnetv107x_restart(enum reboot_mode mode, const char *cmd) -{ - tnetv107x_watchdog_reset(&tnetv107x_wdt_device); -} - -static struct davinci_soc_info tnetv107x_soc_info = { - .io_desc = io_desc, - .io_desc_num = ARRAY_SIZE(io_desc), - .ids = ids, - .ids_num = ARRAY_SIZE(ids), - .jtag_id_reg = TNETV107X_CHIP_CFG_BASE + 0x018, - .cpu_clks = clks, - .psc_bases = psc_regs, - .psc_bases_num = ARRAY_SIZE(psc_regs), - .pinmux_base = TNETV107X_CHIP_CFG_BASE + 0x150, - .pinmux_pins = pins, - .pinmux_pins_num = ARRAY_SIZE(pins), - .intc_type = DAVINCI_INTC_TYPE_CP_INTC, - .intc_base = TNETV107X_INTC_BASE, - .intc_irq_prios = irq_prios, - .intc_irq_num = TNETV107X_N_CP_INTC_IRQ, - .intc_host_map = intc_host_map, - .gpio_base = TNETV107X_GPIO_BASE, - .gpio_type = GPIO_TYPE_TNETV107X, - .gpio_num = TNETV107X_N_GPIO, - .timer_info = &timer_info, - .serial_dev = tnetv107x_serial_device, -}; - -void __init tnetv107x_init(void) -{ - davinci_common_init(&tnetv107x_soc_info); -} diff -Nur linux-3.14.1/arch/arm/mach-dove/board-dt.c linux-3.15-rc1.orig/arch/arm/mach-dove/board-dt.c --- linux-3.14.1/arch/arm/mach-dove/board-dt.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-dove/board-dt.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-dove/board-dt.c - * - * Marvell Dove 88AP510 System On Chip FDT Board - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -static void __init dove_dt_init(void) -{ - pr_info("Dove 88AP510 SoC\n"); - -#ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(0); -#endif - BUG_ON(mvebu_mbus_dt_init()); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char * const dove_dt_board_compat[] = { - "marvell,dove", - NULL -}; - -DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") - .map_io = dove_map_io, - .init_machine = dove_dt_init, - .restart = dove_restart, - .dt_compat = dove_dt_board_compat, -MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-dove/include/mach/bridge-regs.h linux-3.15-rc1.orig/arch/arm/mach-dove/include/mach/bridge-regs.h --- linux-3.14.1/arch/arm/mach-dove/include/mach/bridge-regs.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-dove/include/mach/bridge-regs.h 2014-04-13 23:18:35.000000000 +0200 @@ -21,6 +21,7 @@ #define CPU_CTRL_PCIE1_LINK 0x00000008 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) +#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) diff -Nur linux-3.14.1/arch/arm/mach-dove/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-dove/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-dove/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-dove/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/timex.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define CLOCK_TICK_RATE (100 * HZ) diff -Nur linux-3.14.1/arch/arm/mach-dove/Kconfig linux-3.15-rc1.orig/arch/arm/mach-dove/Kconfig --- linux-3.14.1/arch/arm/mach-dove/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-dove/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -20,18 +20,6 @@ Say 'Y' here if you want your kernel to support the CompuLab CM-A510 Board. -config MACH_DOVE_DT - bool "Marvell Dove Flattened Device Tree" - select DOVE_CLK - select ORION_IRQCHIP - select ORION_TIMER - select REGULATOR - select REGULATOR_FIXED_VOLTAGE - select USE_OF - help - Say 'Y' here if you want your kernel to support the - Marvell Dove using flattened device tree. - endmenu endif diff -Nur linux-3.14.1/arch/arm/mach-dove/Makefile linux-3.15-rc1.orig/arch/arm/mach-dove/Makefile --- linux-3.14.1/arch/arm/mach-dove/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-dove/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -2,5 +2,4 @@ obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o obj-$(CONFIG_PCI) += pcie.o obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o -obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff -Nur linux-3.14.1/arch/arm/mach-ebsa110/core.c linux-3.15-rc1.orig/arch/arm/mach-ebsa110/core.c --- linux-3.14.1/arch/arm/mach-ebsa110/core.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-ebsa110/core.c 2014-04-13 23:18:35.000000000 +0200 @@ -206,7 +206,7 @@ static struct irqaction ebsa110_timer_irq = { .name = "EBSA110 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = ebsa110_timer_interrupt, }; diff -Nur linux-3.14.1/arch/arm/mach-ebsa110/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-ebsa110/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-ebsa110/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-ebsa110/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-ebsa110/include/mach/timex.h - * - * Copyright (C) 1997, 1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * EBSA110 architecture timex specifications - */ - -/* - * On the EBSA, the clock ticks at weird rates. - * This is therefore not used to calculate the - * divisor. - */ -#define CLOCK_TICK_RATE 47894000 - diff -Nur linux-3.14.1/arch/arm/mach-efm32/include/mach/entry-macro.S linux-3.15-rc1.orig/arch/arm/mach-efm32/include/mach/entry-macro.S --- linux-3.14.1/arch/arm/mach-efm32/include/mach/entry-macro.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-efm32/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 @@ -1,4 +0,0 @@ -/* - * Empty file waiting for deletion once isn't needed any - * more. Patch "ARM: v7-M: drop using mach/entry-macro.S" sitting in next. - */ diff -Nur linux-3.14.1/arch/arm/mach-efm32/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-efm32/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-efm32/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-efm32/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,3 +0,0 @@ -/* - * Empty file waiting for deletion once isn't needed any more. - */ diff -Nur linux-3.14.1/arch/arm/mach-ep93xx/core.c linux-3.15-rc1.orig/arch/arm/mach-ep93xx/core.c --- linux-3.14.1/arch/arm/mach-ep93xx/core.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-ep93xx/core.c 2014-04-13 23:18:35.000000000 +0200 @@ -117,7 +117,7 @@ #define EP93XX_TIMER4_CLOCK 983040 #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) -#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) +#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ) static unsigned int last_jiffy_time; @@ -242,6 +242,7 @@ v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT; return v; } +EXPORT_SYMBOL_GPL(ep93xx_chip_revision); /************************************************************************* * EP93xx GPIO diff -Nur linux-3.14.1/arch/arm/mach-ep93xx/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-ep93xx/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-ep93xx/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-ep93xx/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-ep93xx/include/mach/timex.h - */ - -#define CLOCK_TICK_RATE 983040 diff -Nur linux-3.14.1/arch/arm/mach-exynos/common.c linux-3.15-rc1.orig/arch/arm/mach-exynos/common.c --- linux-3.14.1/arch/arm/mach-exynos/common.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/common.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,418 +0,0 @@ -/* - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Common Codes for EXYNOS - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "common.h" -#include "regs-pmu.h" - -#define L2_AUX_VAL 0x7C470001 -#define L2_AUX_MASK 0xC200ffff - -static const char name_exynos4210[] = "EXYNOS4210"; -static const char name_exynos4212[] = "EXYNOS4212"; -static const char name_exynos4412[] = "EXYNOS4412"; -static const char name_exynos5250[] = "EXYNOS5250"; -static const char name_exynos5420[] = "EXYNOS5420"; -static const char name_exynos5440[] = "EXYNOS5440"; - -static void exynos4_map_io(void); -static void exynos5_map_io(void); -static int exynos_init(void); - -static struct cpu_table cpu_ids[] __initdata = { - { - .idcode = EXYNOS4210_CPU_ID, - .idmask = EXYNOS4_CPU_MASK, - .map_io = exynos4_map_io, - .init = exynos_init, - .name = name_exynos4210, - }, { - .idcode = EXYNOS4212_CPU_ID, - .idmask = EXYNOS4_CPU_MASK, - .map_io = exynos4_map_io, - .init = exynos_init, - .name = name_exynos4212, - }, { - .idcode = EXYNOS4412_CPU_ID, - .idmask = EXYNOS4_CPU_MASK, - .map_io = exynos4_map_io, - .init = exynos_init, - .name = name_exynos4412, - }, { - .idcode = EXYNOS5250_SOC_ID, - .idmask = EXYNOS5_SOC_MASK, - .map_io = exynos5_map_io, - .init = exynos_init, - .name = name_exynos5250, - }, { - .idcode = EXYNOS5420_SOC_ID, - .idmask = EXYNOS5_SOC_MASK, - .map_io = exynos5_map_io, - .init = exynos_init, - .name = name_exynos5420, - }, { - .idcode = EXYNOS5440_SOC_ID, - .idmask = EXYNOS5_SOC_MASK, - .init = exynos_init, - .name = name_exynos5440, - }, -}; - -/* Initial IO mappings */ - -static struct map_desc exynos4_iodesc[] __initdata = { - { - .virtual = (unsigned long)S3C_VA_SYS, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_TIMER, - .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_WATCHDOG, - .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SYSTIMER, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_PMU, - .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_COMBINER_BASE, - .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GIC_CPU, - .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GIC_DIST, - .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_CMU, - .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), - .length = SZ_128K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_COREPERI_BASE, - .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_L2CC, - .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_DMC0, - .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_DMC1, - .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_USB_HSPHY, - .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4_iodesc0[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4_iodesc1[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4210_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM_NS, - .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4x12_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM_NS, - .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos5250_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM_NS, - .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos5_iodesc[] __initdata = { - { - .virtual = (unsigned long)S3C_VA_SYS, - .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_TIMER, - .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_WATCHDOG, - .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_CMU, - .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), - .length = 144 * SZ_1K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_PMU, - .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), - .length = SZ_64K, - .type = MT_DEVICE, - }, -}; - -void exynos4_restart(enum reboot_mode mode, const char *cmd) -{ - __raw_writel(0x1, S5P_SWRESET); -} - -void exynos5_restart(enum reboot_mode mode, const char *cmd) -{ - struct device_node *np; - u32 val; - void __iomem *addr; - - val = 0x1; - addr = EXYNOS_SWRESET; - - if (of_machine_is_compatible("samsung,exynos5440")) { - u32 status; - np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); - - addr = of_iomap(np, 0) + 0xbc; - status = __raw_readl(addr); - - addr = of_iomap(np, 0) + 0xcc; - val = __raw_readl(addr); - - val = (val & 0xffff0000) | (status & 0xffff); - } - - __raw_writel(val, addr); -} - -static struct platform_device exynos_cpuidle = { - .name = "exynos_cpuidle", - .id = -1, -}; - -void __init exynos_cpuidle_init(void) -{ - platform_device_register(&exynos_cpuidle); -} - -void __init exynos_cpufreq_init(void) -{ - platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); -} - -void __init exynos_init_late(void) -{ - if (of_machine_is_compatible("samsung,exynos5440")) - /* to be supported later */ - return; - - pm_genpd_poweroff_unused(); -} - -static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, - int depth, void *data) -{ - struct map_desc iodesc; - __be32 *reg; - unsigned long len; - - if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") && - !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock")) - return 0; - - reg = of_get_flat_dt_prop(node, "reg", &len); - if (reg == NULL || len != (sizeof(unsigned long) * 2)) - return 0; - - iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); - iodesc.length = be32_to_cpu(reg[1]) - 1; - iodesc.virtual = (unsigned long)S5P_VA_CHIPID; - iodesc.type = MT_DEVICE; - iotable_init(&iodesc, 1); - return 1; -} - -/* - * exynos_map_io - * - * register the standard cpu IO areas - */ - -void __init exynos_init_io(void) -{ - debug_ll_io_init(); - - of_scan_flat_dt(exynos_fdt_map_chipid, NULL); - - /* detect cpu id and rev. */ - s5p_init_cpu(S5P_VA_CHIPID); - - s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); -} - -static void __init exynos4_map_io(void) -{ - iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); - - if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) - iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0)); - else - iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); - - if (soc_is_exynos4210()) - iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); - if (soc_is_exynos4212() || soc_is_exynos4412()) - iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); -} - -static void __init exynos5_map_io(void) -{ - iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); - - if (soc_is_exynos5250()) - iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); -} - -struct bus_type exynos_subsys = { - .name = "exynos-core", - .dev_name = "exynos-core", -}; - -static struct device exynos4_dev = { - .bus = &exynos_subsys, -}; - -static int __init exynos_core_init(void) -{ - return subsys_system_register(&exynos_subsys, NULL); -} -core_initcall(exynos_core_init); - -static int __init exynos4_l2x0_cache_init(void) -{ - int ret; - - ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); - if (ret) - return ret; - - l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); - return 0; -} -early_initcall(exynos4_l2x0_cache_init); - -static int __init exynos_init(void) -{ - printk(KERN_INFO "EXYNOS: Initializing architecture\n"); - - return device_register(&exynos4_dev); -} diff -Nur linux-3.14.1/arch/arm/mach-exynos/common.h linux-3.15-rc1.orig/arch/arm/mach-exynos/common.h --- linux-3.14.1/arch/arm/mach-exynos/common.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/common.h 2014-04-13 23:18:35.000000000 +0200 @@ -19,14 +19,27 @@ struct map_desc; void exynos_init_io(void); -void exynos4_restart(enum reboot_mode mode, const char *cmd); -void exynos5_restart(enum reboot_mode mode, const char *cmd); +void exynos_restart(enum reboot_mode mode, const char *cmd); void exynos_cpuidle_init(void); void exynos_cpufreq_init(void); void exynos_init_late(void); void exynos_firmware_init(void); +#ifdef CONFIG_PINCTRL_EXYNOS +extern u32 exynos_get_eint_wake_mask(void); +#else +static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } +#endif + +#ifdef CONFIG_PM_SLEEP +extern void __init exynos_pm_init(void); +#else +static inline void exynos_pm_init(void) {} +#endif + +extern void exynos_cpu_resume(void); + extern struct smp_operations exynos_smp_ops; extern void exynos_cpu_die(unsigned int cpu); diff -Nur linux-3.14.1/arch/arm/mach-exynos/cpuidle.c linux-3.15-rc1.orig/arch/arm/mach-exynos/cpuidle.c --- linux-3.14.1/arch/arm/mach-exynos/cpuidle.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/cpuidle.c 2014-04-13 23:18:35.000000000 +0200 @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -26,7 +27,6 @@ #include #include -#include #include #include "common.h" @@ -127,7 +127,7 @@ /* Set value of power down register for aftr mode */ exynos_sys_powerdown_conf(SYS_AFTR); - __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR); + __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR); __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); save_cpu_arch_register(); diff -Nur linux-3.14.1/arch/arm/mach-exynos/exynos.c linux-3.15-rc1.orig/arch/arm/mach-exynos/exynos.c --- linux-3.14.1/arch/arm/mach-exynos/exynos.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/exynos.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,411 @@ +/* + * SAMSUNG EXYNOS Flattened Device Tree enabled machine + * + * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "mfc.h" +#include "regs-pmu.h" + +#define L2_AUX_VAL 0x7C470001 +#define L2_AUX_MASK 0xC200ffff + +static struct map_desc exynos4_iodesc[] __initdata = { + { + .virtual = (unsigned long)S3C_VA_SYS, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_TIMER, + .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_PMU, + .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_COMBINER_BASE, + .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GIC_CPU, + .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GIC_DIST, + .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_CMU, + .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), + .length = SZ_128K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_COREPERI_BASE, + .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_L2CC, + .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC0, + .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC1, + .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_USB_HSPHY, + .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos4_iodesc0[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos4_iodesc1[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos4210_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos4x12_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos5250_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc exynos5_iodesc[] __initdata = { + { + .virtual = (unsigned long)S3C_VA_SYS, + .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_TIMER, + .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_CMU, + .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), + .length = 144 * SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_PMU, + .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), + .length = SZ_64K, + .type = MT_DEVICE, + }, +}; + +void exynos_restart(enum reboot_mode mode, const char *cmd) +{ + struct device_node *np; + u32 val = 0x1; + void __iomem *addr = EXYNOS_SWRESET; + + if (of_machine_is_compatible("samsung,exynos5440")) { + u32 status; + np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); + + addr = of_iomap(np, 0) + 0xbc; + status = __raw_readl(addr); + + addr = of_iomap(np, 0) + 0xcc; + val = __raw_readl(addr); + + val = (val & 0xffff0000) | (status & 0xffff); + } + + __raw_writel(val, addr); +} + +static struct platform_device exynos_cpuidle = { + .name = "exynos_cpuidle", + .id = -1, +}; + +void __init exynos_cpuidle_init(void) +{ + platform_device_register(&exynos_cpuidle); +} + +void __init exynos_cpufreq_init(void) +{ + platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); +} + +void __init exynos_init_late(void) +{ + if (of_machine_is_compatible("samsung,exynos5440")) + /* to be supported later */ + return; + + pm_genpd_poweroff_unused(); + exynos_pm_init(); +} + +static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, + int depth, void *data) +{ + struct map_desc iodesc; + __be32 *reg; + unsigned long len; + + if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") && + !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock")) + return 0; + + reg = of_get_flat_dt_prop(node, "reg", &len); + if (reg == NULL || len != (sizeof(unsigned long) * 2)) + return 0; + + iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); + iodesc.length = be32_to_cpu(reg[1]) - 1; + iodesc.virtual = (unsigned long)S5P_VA_CHIPID; + iodesc.type = MT_DEVICE; + iotable_init(&iodesc, 1); + return 1; +} + +/* + * exynos_map_io + * + * register the standard cpu IO areas + */ +static void __init exynos_map_io(void) +{ + if (soc_is_exynos4()) + iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); + + if (soc_is_exynos5()) + iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); + + if (soc_is_exynos4210()) { + if (samsung_rev() == EXYNOS4210_REV_0) + iotable_init(exynos4_iodesc0, + ARRAY_SIZE(exynos4_iodesc0)); + else + iotable_init(exynos4_iodesc1, + ARRAY_SIZE(exynos4_iodesc1)); + iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); + } + if (soc_is_exynos4212() || soc_is_exynos4412()) + iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); + if (soc_is_exynos5250()) + iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); +} + +void __init exynos_init_io(void) +{ + debug_ll_io_init(); + + of_scan_flat_dt(exynos_fdt_map_chipid, NULL); + + /* detect cpu id and rev. */ + s5p_init_cpu(S5P_VA_CHIPID); + + exynos_map_io(); +} + +struct bus_type exynos_subsys = { + .name = "exynos-core", + .dev_name = "exynos-core", +}; + +static int __init exynos_core_init(void) +{ + return subsys_system_register(&exynos_subsys, NULL); +} +core_initcall(exynos_core_init); + +static int __init exynos4_l2x0_cache_init(void) +{ + int ret; + + ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); + if (ret) + return ret; + + if (IS_ENABLED(CONFIG_S5P_SLEEP)) { + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + } + return 0; +} +early_initcall(exynos4_l2x0_cache_init); + +static void __init exynos_dt_machine_init(void) +{ + struct device_node *i2c_np; + const char *i2c_compat = "samsung,s3c2440-i2c"; + unsigned int tmp; + int id; + + /* + * Exynos5's legacy i2c controller and new high speed i2c + * controller have muxed interrupt sources. By default the + * interrupts for 4-channel HS-I2C controller are enabled. + * If node for first four channels of legacy i2c controller + * are available then re-configure the interrupts via the + * system register. + */ + if (soc_is_exynos5()) { + for_each_compatible_node(i2c_np, NULL, i2c_compat) { + if (of_device_is_available(i2c_np)) { + id = of_alias_get_id(i2c_np, "i2c"); + if (id < 4) { + tmp = readl(EXYNOS5_SYS_I2C_CFG); + writel(tmp & ~(0x1 << id), + EXYNOS5_SYS_I2C_CFG); + } + } + } + } + + exynos_cpuidle_init(); + exynos_cpufreq_init(); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static char const *exynos_dt_compat[] __initconst = { + "samsung,exynos4", + "samsung,exynos4210", + "samsung,exynos4212", + "samsung,exynos4412", + "samsung,exynos5", + "samsung,exynos5250", + "samsung,exynos5420", + "samsung,exynos5440", + NULL +}; + +static void __init exynos_reserve(void) +{ +#ifdef CONFIG_S5P_DEV_MFC + int i; + char *mfc_mem[] = { + "samsung,mfc-v5", + "samsung,mfc-v6", + "samsung,mfc-v7", + }; + + for (i = 0; i < ARRAY_SIZE(mfc_mem); i++) + if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i])) + break; +#endif +} + +DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") + /* Maintainer: Thomas Abraham */ + /* Maintainer: Kukjin Kim */ + .smp = smp_ops(exynos_smp_ops), + .map_io = exynos_init_io, + .init_early = exynos_firmware_init, + .init_machine = exynos_dt_machine_init, + .init_late = exynos_init_late, + .dt_compat = exynos_dt_compat, + .restart = exynos_restart, + .reserve = exynos_reserve, +MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-exynos/include/mach/hardware.h linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/hardware.h --- linux-3.14.1/arch/arm/mach-exynos/include/mach/hardware.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,18 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/hardware.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Hardware support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H __FILE__ - -/* currently nothing here, placeholder */ - -#endif /* __ASM_ARCH_HARDWARE_H */ diff -Nur linux-3.14.1/arch/arm/mach-exynos/include/mach/pm-core.h linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/pm-core.h --- linux-3.14.1/arch/arm/mach-exynos/include/mach/pm-core.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/pm-core.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,75 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h, - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_PM_CORE_H -#define __ASM_ARCH_PM_CORE_H __FILE__ - -#include -#include - -#define S5P_EINT_WAKEUP_MASK (S5P_VA_PMU + 0x0604) -#define S5P_WAKEUP_MASK (S5P_VA_PMU + 0x0608) - -#ifdef CONFIG_PINCTRL_EXYNOS -extern u32 exynos_get_eint_wake_mask(void); -#else -static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } -#endif - -static inline void s3c_pm_debug_init_uart(void) -{ - /* nothing here yet */ -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); - __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ - /* nothing here yet */ -} - -static inline void s3c_pm_arch_show_resume_irqs(void) -{ - /* nothing here yet */ -} - -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ - /* nothing here yet */ -} - -static inline void s3c_pm_restored_gpios(void) -{ - /* nothing here yet */ -} - -static inline void samsung_pm_saved_gpios(void) -{ - /* nothing here yet */ -} - -/* Compatibility definitions to make plat-samsung/pm.c compile */ -#define IRQ_EINT_BIT(x) 1 -#define s3c_irqwake_intallow 0 -#define s3c_irqwake_eintallow 0 - -#endif /* __ASM_ARCH_PM_CORE_H */ diff -Nur linux-3.14.1/arch/arm/mach-exynos/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-exynos/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,29 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/timex.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (c) 2003-2010 Simtec Electronics - * Ben Dooks - * - * Based on arch/arm/mach-s5p6442/include/mach/timex.h - * - * EXYNOS4 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H __FILE__ - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - -#define CLOCK_TICK_RATE 12000000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff -Nur linux-3.14.1/arch/arm/mach-exynos/include/mach/uncompress.h linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/uncompress.h --- linux-3.14.1/arch/arm/mach-exynos/include/mach/uncompress.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H __FILE__ - -#include - -#include -#include - -static unsigned int __raw_readl(unsigned int ptr) -{ - return *((volatile unsigned int *)ptr); -} - -static void arch_detect_cpu(void) -{ - u32 chip_id = __raw_readl(EXYNOS_PA_CHIPID); - - /* - * product_id is bits 31:12 - * bits 23:20 describe the exynosX family - * bits 27:24 describe the exynosX family in exynos5420 - */ - chip_id >>= 20; - - if ((chip_id & 0x0f) == 0x5 || (chip_id & 0xf0) == 0x50) - uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); - else - uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); - - /* - * For preventing FIFO overrun or infinite loop of UART console, - * fifo_max should be the minimum fifo size of all of the UART channels - */ - fifo_mask = S5PV210_UFSTAT_TXMASK; - fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT; -} -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff -Nur linux-3.14.1/arch/arm/mach-exynos/Kconfig linux-3.15-rc1.orig/arch/arm/mach-exynos/Kconfig --- linux-3.14.1/arch/arm/mach-exynos/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -24,7 +24,7 @@ select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL - select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS if PM_RUNTIME select S5P_DEV_MFC help Samsung EXYNOS4 SoCs based systems @@ -36,7 +36,6 @@ select HAVE_ARM_SCU if SMP select HAVE_SMP select PINCTRL - select USB_ARCH_HAS_XHCI help Samsung EXYNOS5 (Cortex-A15) SoC based systems @@ -47,10 +46,8 @@ default y depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP - select ARM_CPU_SUSPEND if PM + select ARM_CPU_SUSPEND if PM_SLEEP select PINCTRL_EXYNOS - select S5P_PM if PM - select S5P_SLEEP if PM select SAMSUNG_DMADEV help Enable EXYNOS4210 CPU support @@ -61,8 +58,6 @@ depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select S5P_PM if PM - select S5P_SLEEP if PM select SAMSUNG_DMADEV help Enable EXYNOS4212 SoC support @@ -83,9 +78,7 @@ depends on ARCH_EXYNOS5 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM - select S5P_PM if PM - select S5P_SLEEP if PM + select PM_GENERIC_DOMAINS if PM_RUNTIME select S5P_DEV_MFC select SAMSUNG_DMADEV help @@ -95,9 +88,7 @@ bool "SAMSUNG EXYNOS5420" default y depends on ARCH_EXYNOS5 - select PM_GENERIC_DOMAINS if PM - select S5P_PM if PM - select S5P_SLEEP if PM + select PM_GENERIC_DOMAINS if PM_RUNTIME help Enable EXYNOS5420 SoC support diff -Nur linux-3.14.1/arch/arm/mach-exynos/mach-exynos4-dt.c linux-3.15-rc1.orig/arch/arm/mach-exynos/mach-exynos4-dt.c --- linux-3.14.1/arch/arm/mach-exynos/mach-exynos4-dt.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/mach-exynos4-dt.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,59 +0,0 @@ -/* - * Samsung's EXYNOS4 flattened device tree enabled machine - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include - -#include -#include - -#include "common.h" - -static void __init exynos4_dt_machine_init(void) -{ - exynos_cpuidle_init(); - exynos_cpufreq_init(); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static char const *exynos4_dt_compat[] __initdata = { - "samsung,exynos4210", - "samsung,exynos4212", - "samsung,exynos4412", - NULL -}; - -static void __init exynos4_reserve(void) -{ -#ifdef CONFIG_S5P_DEV_MFC - struct s5p_mfc_dt_meminfo mfc_mem; - - /* Reserve memory for MFC only if it's available */ - mfc_mem.compatible = "samsung,mfc-v5"; - if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem)) - s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff, - mfc_mem.lsize); -#endif -} -DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") - /* Maintainer: Thomas Abraham */ - .smp = smp_ops(exynos_smp_ops), - .map_io = exynos_init_io, - .init_early = exynos_firmware_init, - .init_machine = exynos4_dt_machine_init, - .init_late = exynos_init_late, - .dt_compat = exynos4_dt_compat, - .restart = exynos4_restart, - .reserve = exynos4_reserve, -MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-exynos/mach-exynos5-dt.c linux-3.15-rc1.orig/arch/arm/mach-exynos/mach-exynos5-dt.c --- linux-3.14.1/arch/arm/mach-exynos/mach-exynos5-dt.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/mach-exynos5-dt.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,81 +0,0 @@ -/* - * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include - -#include -#include - -#include "common.h" -#include "regs-pmu.h" - -static void __init exynos5_dt_machine_init(void) -{ - struct device_node *i2c_np; - const char *i2c_compat = "samsung,s3c2440-i2c"; - unsigned int tmp; - - /* - * Exynos5's legacy i2c controller and new high speed i2c - * controller have muxed interrupt sources. By default the - * interrupts for 4-channel HS-I2C controller are enabled. - * If node for first four channels of legacy i2c controller - * are available then re-configure the interrupts via the - * system register. - */ - for_each_compatible_node(i2c_np, NULL, i2c_compat) { - if (of_device_is_available(i2c_np)) { - if (of_alias_get_id(i2c_np, "i2c") < 4) { - tmp = readl(EXYNOS5_SYS_I2C_CFG); - writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")), - EXYNOS5_SYS_I2C_CFG); - } - } - } - - exynos_cpuidle_init(); - exynos_cpufreq_init(); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static char const *exynos5_dt_compat[] __initdata = { - "samsung,exynos5250", - "samsung,exynos5420", - "samsung,exynos5440", - NULL -}; - -static void __init exynos5_reserve(void) -{ -#ifdef CONFIG_S5P_DEV_MFC - struct s5p_mfc_dt_meminfo mfc_mem; - - /* Reserve memory for MFC only if it's available */ - mfc_mem.compatible = "samsung,mfc-v6"; - if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem)) - s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff, - mfc_mem.lsize); -#endif -} - -DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") - /* Maintainer: Kukjin Kim */ - .smp = smp_ops(exynos_smp_ops), - .map_io = exynos_init_io, - .init_machine = exynos5_dt_machine_init, - .init_late = exynos_init_late, - .dt_compat = exynos5_dt_compat, - .restart = exynos5_restart, - .reserve = exynos5_reserve, -MACHINE_END diff -Nur linux-3.14.1/arch/arm/mach-exynos/Makefile linux-3.15-rc1.orig/arch/arm/mach-exynos/Makefile --- linux-3.14.1/arch/arm/mach-exynos/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -12,9 +12,9 @@ # Core -obj-$(CONFIG_ARCH_EXYNOS) += common.o +obj-$(CONFIG_ARCH_EXYNOS) += exynos.o -obj-$(CONFIG_S5P_PM) += pm.o +obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o @@ -29,8 +29,3 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) - -# machine support - -obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o -obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o diff -Nur linux-3.14.1/arch/arm/mach-exynos/mfc.h linux-3.15-rc1.orig/arch/arm/mach-exynos/mfc.h --- linux-3.14.1/arch/arm/mach-exynos/mfc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/mfc.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 Samsung Electronics Co.Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MACH_EXYNOS_MFC_H +#define __MACH_EXYNOS_MFC_H __FILE__ + +int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, + int depth, void *data); + +#endif /* __MACH_EXYNOS_MFC_H */ diff -Nur linux-3.14.1/arch/arm/mach-exynos/platsmp.c linux-3.15-rc1.orig/arch/arm/mach-exynos/platsmp.c --- linux-3.14.1/arch/arm/mach-exynos/platsmp.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/platsmp.c 2014-04-13 23:18:35.000000000 +0200 @@ -26,8 +26,6 @@ #include #include -#include - #include #include "common.h" diff -Nur linux-3.14.1/arch/arm/mach-exynos/pm.c linux-3.15-rc1.orig/arch/arm/mach-exynos/pm.c --- linux-3.14.1/arch/arm/mach-exynos/pm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/pm.c 2014-04-13 23:18:35.000000000 +0200 @@ -17,72 +17,33 @@ #include #include #include +#include #include #include #include #include #include +#include #include -#include +#include #include #include #include -#include #include "common.h" #include "regs-pmu.h" -#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010) -#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020) - -#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110) -#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114) -#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120) -#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124) - -#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310) -#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320) -#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324) -#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334) -#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C) -#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340) -#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350) -#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354) - -#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300) - -#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) -#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) - -#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) - -static const struct sleep_save exynos4_set_clksrc[] = { - { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, - { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, - { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, - { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, - { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, - { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, }, - { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, - { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, - { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, -}; - -static const struct sleep_save exynos4210_set_clksrc[] = { - { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, -}; - -static struct sleep_save exynos4_epll_save[] = { - SAVE_ITEM(EXYNOS4_EPLL_CON0), - SAVE_ITEM(EXYNOS4_EPLL_CON1), -}; - -static struct sleep_save exynos4_vpll_save[] = { - SAVE_ITEM(EXYNOS4_VPLL_CON0), - SAVE_ITEM(EXYNOS4_VPLL_CON1), +/** + * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping + * @hwirq: Hardware IRQ signal of the GIC + * @mask: Mask in PMU wake-up mask register + */ +struct exynos_wkup_irq { + unsigned int hwirq; + u32 mask; }; static struct sleep_save exynos5_sys_save[] = { @@ -98,6 +59,46 @@ SAVE_ITEM(S5P_SROM_BC3), }; +/* + * GIC wake-up support + */ + +static u32 exynos_irqwake_intmask = 0xffffffff; + +static const struct exynos_wkup_irq exynos4_wkup_irq[] = { + { 76, BIT(1) }, /* RTC alarm */ + { 77, BIT(2) }, /* RTC tick */ + { /* sentinel */ }, +}; + +static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { + { 75, BIT(1) }, /* RTC alarm */ + { 76, BIT(2) }, /* RTC tick */ + { /* sentinel */ }, +}; + +static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) +{ + const struct exynos_wkup_irq *wkup_irq; + + if (soc_is_exynos5250()) + wkup_irq = exynos5250_wkup_irq; + else + wkup_irq = exynos4_wkup_irq; + + while (wkup_irq->mask) { + if (wkup_irq->hwirq == data->hwirq) { + if (!state) + exynos_irqwake_intmask |= wkup_irq->mask; + else + exynos_irqwake_intmask &= ~wkup_irq->mask; + return 0; + } + ++wkup_irq; + } + + return -ENOENT; +} /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -122,12 +123,13 @@ { unsigned int tmp; + /* Set wake-up mask registers */ + __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); + __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); + s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (!soc_is_exynos5250()) { - s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); - s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); - } else { + if (soc_is_exynos5250()) { s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); /* Disable USE_RETENTION of JPEG_MEM_OPTION */ tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); @@ -142,128 +144,9 @@ /* ensure at least INFORM0 has the resume address */ - __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); - - /* Before enter central sequence mode, clock src register have to set */ - - if (!soc_is_exynos5250()) - s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); - - if (soc_is_exynos4210()) - s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc)); - + __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); } -static int exynos_pm_add(struct device *dev, struct subsys_interface *sif) -{ - pm_cpu_prep = exynos_pm_prepare; - pm_cpu_sleep = exynos_cpu_suspend; - - return 0; -} - -static unsigned long pll_base_rate; - -static void exynos4_restore_pll(void) -{ - unsigned long pll_con, locktime, lockcnt; - unsigned long pll_in_rate; - unsigned int p_div, epll_wait = 0, vpll_wait = 0; - - if (pll_base_rate == 0) - return; - - pll_in_rate = pll_base_rate; - - /* EPLL */ - pll_con = exynos4_epll_save[0].val; - - if (pll_con & (1 << 31)) { - pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT); - p_div = (pll_con >> PLL46XX_PDIV_SHIFT); - - pll_in_rate /= 1000000; - - locktime = (3000 / pll_in_rate) * p_div; - lockcnt = locktime * 10000 / (10000 / pll_in_rate); - - __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); - - s3c_pm_do_restore_core(exynos4_epll_save, - ARRAY_SIZE(exynos4_epll_save)); - epll_wait = 1; - } - - pll_in_rate = pll_base_rate; - - /* VPLL */ - pll_con = exynos4_vpll_save[0].val; - - if (pll_con & (1 << 31)) { - pll_in_rate /= 1000000; - /* 750us */ - locktime = 750; - lockcnt = locktime * 10000 / (10000 / pll_in_rate); - - __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); - - s3c_pm_do_restore_core(exynos4_vpll_save, - ARRAY_SIZE(exynos4_vpll_save)); - vpll_wait = 1; - } - - /* Wait PLL locking */ - - do { - if (epll_wait) { - pll_con = __raw_readl(EXYNOS4_EPLL_CON0); - if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT)) - epll_wait = 0; - } - - if (vpll_wait) { - pll_con = __raw_readl(EXYNOS4_VPLL_CON0); - if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT)) - vpll_wait = 0; - } - } while (epll_wait || vpll_wait); -} - -static struct subsys_interface exynos_pm_interface = { - .name = "exynos_pm", - .subsys = &exynos_subsys, - .add_dev = exynos_pm_add, -}; - -static __init int exynos_pm_drvinit(void) -{ - struct clk *pll_base; - unsigned int tmp; - - if (soc_is_exynos5440()) - return 0; - - s3c_pm_init(); - - /* All wakeup disable */ - - tmp = __raw_readl(S5P_WAKEUP_MASK); - tmp |= ((0xFF << 8) | (0x1F << 1)); - __raw_writel(tmp, S5P_WAKEUP_MASK); - - if (!soc_is_exynos5250()) { - pll_base = clk_get(NULL, "xtal"); - - if (!IS_ERR(pll_base)) { - pll_base_rate = clk_get_rate(pll_base); - clk_put(pll_base); - } - } - - return subsys_interface_register(&exynos_pm_interface); -} -arch_initcall(exynos_pm_drvinit); - static int exynos_pm_suspend(void) { unsigned long tmp; @@ -343,13 +226,8 @@ s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (!soc_is_exynos5250()) { - exynos4_restore_pll(); - -#ifdef CONFIG_SMP + if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250()) scu_enable(S5P_VA_SCU); -#endif - } early_wakeup: @@ -364,12 +242,80 @@ .resume = exynos_pm_resume, }; -static __init int exynos_pm_syscore_init(void) +/* + * Suspend Ops + */ + +static int exynos_suspend_enter(suspend_state_t state) { - if (soc_is_exynos5440()) - return 0; + int ret; + + s3c_pm_debug_init(); + + S3C_PMDBG("%s: suspending the system...\n", __func__); + + S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, + exynos_irqwake_intmask, exynos_get_eint_wake_mask()); + + if (exynos_irqwake_intmask == -1U + && exynos_get_eint_wake_mask() == -1U) { + pr_err("%s: No wake-up sources!\n", __func__); + pr_err("%s: Aborting sleep\n", __func__); + return -EINVAL; + } + + s3c_pm_save_uarts(); + exynos_pm_prepare(); + flush_cache_all(); + s3c_pm_check_store(); + + ret = cpu_suspend(0, exynos_cpu_suspend); + if (ret) + return ret; + + s3c_pm_restore_uarts(); + + S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, + __raw_readl(S5P_WAKEUP_STAT)); + + s3c_pm_check_restore(); + + S3C_PMDBG("%s: resuming the system...\n", __func__); + + return 0; +} + +static int exynos_suspend_prepare(void) +{ + s3c_pm_check_prepare(); - register_syscore_ops(&exynos_pm_syscore_ops); return 0; } -arch_initcall(exynos_pm_syscore_init); + +static void exynos_suspend_finish(void) +{ + s3c_pm_check_cleanup(); +} + +static const struct platform_suspend_ops exynos_suspend_ops = { + .enter = exynos_suspend_enter, + .prepare = exynos_suspend_prepare, + .finish = exynos_suspend_finish, + .valid = suspend_valid_only_mem, +}; + +void __init exynos_pm_init(void) +{ + u32 tmp; + + /* Platform-specific GIC callback */ + gic_arch_extn.irq_set_wake = exynos_irq_set_wake; + + /* All wakeup disable */ + tmp = __raw_readl(S5P_WAKEUP_MASK); + tmp |= ((0xFF << 8) | (0x1F << 1)); + __raw_writel(tmp, S5P_WAKEUP_MASK); + + register_syscore_ops(&exynos_pm_syscore_ops); + suspend_set_ops(&exynos_suspend_ops); +} diff -Nur linux-3.14.1/arch/arm/mach-exynos/pm_domains.c linux-3.15-rc1.orig/arch/arm/mach-exynos/pm_domains.c --- linux-3.14.1/arch/arm/mach-exynos/pm_domains.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/pm_domains.c 2014-04-13 23:18:35.000000000 +0200 @@ -22,8 +22,6 @@ #include #include -#include - #include "regs-pmu.h" /* diff -Nur linux-3.14.1/arch/arm/mach-exynos/regs-pmu.h linux-3.15-rc1.orig/arch/arm/mach-exynos/regs-pmu.h --- linux-3.14.1/arch/arm/mach-exynos/regs-pmu.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/regs-pmu.h 2014-04-13 23:18:35.000000000 +0200 @@ -26,11 +26,12 @@ #define S5P_USE_STANDBY_WFI0 (1 << 16) #define S5P_USE_STANDBY_WFE0 (1 << 24) -#define S5P_SWRESET S5P_PMUREG(0x0400) #define EXYNOS_SWRESET S5P_PMUREG(0x0400) #define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) +#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) +#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) diff -Nur linux-3.14.1/arch/arm/mach-exynos/sleep.S linux-3.15-rc1.orig/arch/arm/mach-exynos/sleep.S --- linux-3.14.1/arch/arm/mach-exynos/sleep.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-exynos/sleep.S 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Exynos low-level resume code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define CPU_MASK 0xff0ffff0 +#define CPU_CORTEX_A9 0x410fc090 + + /* + * The following code is located into the .data section. This is to + * allow l2x0_regs_phys to be accessed with a relative load while we + * can't rely on any MMU translation. We could have put l2x0_regs_phys + * in the .text section as well, but some setups might insist on it to + * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) + */ + .data + .align + + /* + * sleep magic, to allow the bootloader to check for an valid + * image to resume to. Must be the first word before the + * exynos_cpu_resume entry. + */ + + .word 0x2bedf00d + + /* + * exynos_cpu_resume + * + * resume code entry for bootloader to call + */ + +ENTRY(exynos_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =CPU_MASK + and r0, r0, r1 + ldr r1, =CPU_CORTEX_A9 + cmp r0, r1 + bne skip_l2_resume + adr r0, l2x0_regs_phys + ldr r0, [r0] + cmp r0, #0 + beq skip_l2_resume + ldr r1, [r0, #L2X0_R_PHY_BASE] + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne skip_l2_resume + ldr r2, [r0, #L2X0_R_AUX_CTRL] + str r2, [r1, #L2X0_AUX_CTRL] + ldr r2, [r0, #L2X0_R_TAG_LATENCY] + str r2, [r1, #L2X0_TAG_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + str r2, [r1, #L2X0_DATA_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] + str r2, [r1, #L2X0_PREFETCH_CTRL] + ldr r2, [r0, #L2X0_R_PWR_CTRL] + str r2, [r1, #L2X0_POWER_CTRL] + mov r2, #1 + str r2, [r1, #L2X0_CTRL] +skip_l2_resume: +#endif + b cpu_resume +ENDPROC(exynos_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_regs_phys +l2x0_regs_phys: + .long 0 +#endif diff -Nur linux-3.14.1/arch/arm/mach-footbridge/cats-hw.c linux-3.15-rc1.orig/arch/arm/mach-footbridge/cats-hw.c --- linux-3.14.1/arch/arm/mach-footbridge/cats-hw.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-footbridge/cats-hw.c 2014-04-13 23:18:35.000000000 +0200 @@ -78,9 +78,11 @@ static void __init fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi) { +#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) screen_info.orig_video_lines = 25; screen_info.orig_video_points = 16; screen_info.orig_y = 24; +#endif } MACHINE_START(CATS, "Chalice-CATS") diff -Nur linux-3.14.1/arch/arm/mach-footbridge/dc21285.c linux-3.15-rc1.orig/arch/arm/mach-footbridge/dc21285.c --- linux-3.14.1/arch/arm/mach-footbridge/dc21285.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-footbridge/dc21285.c 2014-04-13 23:18:35.000000000 +0200 @@ -334,15 +334,15 @@ /* * We don't care if these fail. */ - dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED, + dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0, "PCI system error", &serr_timer); - dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED, + dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0, "PCI parity error", &perr_timer); - dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED, + dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0, "PCI abort", NULL); - dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED, + dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0, "Discard timer", NULL); - dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED, + dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0, "PCI data parity", NULL); if (cfn_mode) { diff -Nur linux-3.14.1/arch/arm/mach-footbridge/dc21285-timer.c linux-3.15-rc1.orig/arch/arm/mach-footbridge/dc21285-timer.c --- linux-3.14.1/arch/arm/mach-footbridge/dc21285-timer.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-footbridge/dc21285-timer.c 2014-04-13 23:18:35.000000000 +0200 @@ -105,7 +105,7 @@ static struct irqaction footbridge_timer_irq = { .name = "dc21285_timer1", .handler = timer1_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .dev_id = &ckevt_dc21285, }; @@ -125,7 +125,7 @@ clockevents_config_and_register(ce, rate, 0x4, 0xffffff); } -static u32 notrace footbridge_read_sched_clock(void) +static u64 notrace footbridge_read_sched_clock(void) { return ~*CSR_TIMER3_VALUE; } @@ -138,5 +138,5 @@ *CSR_TIMER3_CLR = 0; *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; - setup_sched_clock(footbridge_read_sched_clock, 24, rate); + sched_clock_register(footbridge_read_sched_clock, 24, rate); } diff -Nur linux-3.14.1/arch/arm/mach-footbridge/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-footbridge/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-footbridge/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-footbridge/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,18 +0,0 @@ -/* - * arch/arm/mach-footbridge/include/mach/timex.h - * - * Copyright (C) 1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * EBSA285 architecture timex specifications - */ - -/* - * We assume a constant here; this satisfies the maths in linux/timex.h - * and linux/time.h. CLOCK_TICK_RATE is actually system dependent, but - * this must be a constant. - */ -#define CLOCK_TICK_RATE (50000000/16) diff -Nur linux-3.14.1/arch/arm/mach-footbridge/isa-timer.c linux-3.15-rc1.orig/arch/arm/mach-footbridge/isa-timer.c --- linux-3.14.1/arch/arm/mach-footbridge/isa-timer.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-footbridge/isa-timer.c 2014-04-13 23:18:35.000000000 +0200 @@ -27,7 +27,7 @@ static struct irqaction pit_timer_irq = { .name = "pit", .handler = pit_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .dev_id = &i8253_clockevent, }; diff -Nur linux-3.14.1/arch/arm/mach-footbridge/Kconfig linux-3.15-rc1.orig/arch/arm/mach-footbridge/Kconfig --- linux-3.14.1/arch/arm/mach-footbridge/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-footbridge/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -52,6 +52,7 @@ select FOOTBRIDGE_HOST select ISA select ISA_DMA + select ARCH_MAY_HAVE_PC_FDC select PCI help Say Y here if you intend to run this kernel on the EBSA285 card @@ -94,6 +95,5 @@ # EBSA285 board in either host or addin mode config ARCH_EBSA285 bool - select ARCH_MAY_HAVE_PC_FDC endif diff -Nur linux-3.14.1/arch/arm/mach-footbridge/Makefile linux-3.15-rc1.orig/arch/arm/mach-footbridge/Makefile --- linux-3.14.1/arch/arm/mach-footbridge/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-footbridge/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -4,11 +4,12 @@ # Object file lists. -obj-y := common.o dc21285.o dma.o isa-irq.o +obj-y := common.o dma.o isa-irq.o obj-m := obj-n := obj- := +pci-y += dc21285.o pci-$(CONFIG_ARCH_CATS) += cats-pci.o pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o diff -Nur linux-3.14.1/arch/arm/mach-gemini/idle.c linux-3.15-rc1.orig/arch/arm/mach-gemini/idle.c --- linux-3.14.1/arch/arm/mach-gemini/idle.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-gemini/idle.c 2014-04-13 23:18:35.000000000 +0200 @@ -3,7 +3,7 @@ */ #include -#include +#include #include static void gemini_idle(void) diff -Nur linux-3.14.1/arch/arm/mach-gemini/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-gemini/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-gemini/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-gemini/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,13 +0,0 @@ -/* - * Gemini timex specifications - * - * Copyright (C) 2008-2009 Paulius Zaleckas - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/* When AHB bus frequency is 150MHz */ -#define CLOCK_TICK_RATE 38000000 diff -Nur linux-3.14.1/arch/arm/mach-highbank/Kconfig linux-3.15-rc1.orig/arch/arm/mach-highbank/Kconfig --- linux-3.14.1/arch/arm/mach-highbank/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-highbank/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -5,7 +5,6 @@ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_OPP select ARCH_SUPPORTS_BIG_ENDIAN - select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 @@ -14,14 +13,8 @@ select ARM_PSCI select ARM_TIMER_SP804 select CACHE_L2X0 - select COMMON_CLK - select CPU_V7 - select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP - select HAVE_SMP select MAILBOX select PL320_MBOX - select SPARSE_IRQ - select USE_OF select ZONE_DMA if ARM_LPAE diff -Nur linux-3.14.1/arch/arm/mach-hisi/hotplug.c linux-3.15-rc1.orig/arch/arm/mach-hisi/hotplug.c --- linux-3.14.1/arch/arm/mach-hisi/hotplug.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-hisi/hotplug.c 2014-04-13 23:18:35.000000000 +0200 @@ -178,6 +178,7 @@ : "cc"); } +#ifdef CONFIG_HOTPLUG_CPU void hi3xxx_cpu_die(unsigned int cpu) { cpu_enter_lowpower(); @@ -198,3 +199,4 @@ hi3xxx_set_cpu(cpu, false); return 1; } +#endif diff -Nur linux-3.14.1/arch/arm/mach-hisi/Kconfig linux-3.15-rc1.orig/arch/arm/mach-hisi/Kconfig --- linux-3.14.1/arch/arm/mach-hisi/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-hisi/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -3,13 +3,9 @@ select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 - select ARCH_WANT_OPTIONAL_GPIOLIB select CACHE_L2X0 - select CLKSRC_OF - select GENERIC_CLOCKEVENTS - select HAVE_ARM_SCU + select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_SMP select PINCTRL select PINCTRL_SINGLE help diff -Nur linux-3.14.1/arch/arm/mach-hisi/Makefile linux-3.15-rc1.orig/arch/arm/mach-hisi/Makefile --- linux-3.14.1/arch/arm/mach-hisi/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-hisi/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -3,5 +3,4 @@ # obj-y += hisilicon.o -obj-$(CONFIG_SMP) += platsmp.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_SMP) += platsmp.o hotplug.o diff -Nur linux-3.14.1/arch/arm/mach-imx/clk-imx21.c linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx21.c --- linux-3.14.1/arch/arm/mach-imx/clk-imx21.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx21.c 2014-04-13 23:18:35.000000000 +0200 @@ -149,7 +149,6 @@ clk_register_clkdev(clk[per1], "per", "imx-gpt.1"); clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2"); clk_register_clkdev(clk[per1], "per", "imx-gpt.2"); - clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0"); clk_register_clkdev(clk[per2], "per", "imx21-cspi.0"); clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0"); clk_register_clkdev(clk[per2], "per", "imx21-cspi.1"); diff -Nur linux-3.14.1/arch/arm/mach-imx/clk-imx25.c linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx25.c --- linux-3.14.1/arch/arm/mach-imx/clk-imx25.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx25.c 2014-04-13 23:18:35.000000000 +0200 @@ -265,14 +265,6 @@ clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0"); clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1"); clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.0"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.1"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.2"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.3"); clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad"); clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc"); clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0"); diff -Nur linux-3.14.1/arch/arm/mach-imx/clk-imx27.c linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx27.c --- linux-3.14.1/arch/arm/mach-imx/clk-imx27.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx27.c 2014-04-13 23:18:35.000000000 +0200 @@ -231,7 +231,6 @@ clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4"); clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5"); clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5"); - clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0"); clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0"); clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0"); clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1"); diff -Nur linux-3.14.1/arch/arm/mach-imx/clk-imx51-imx53.c linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx51-imx53.c --- linux-3.14.1/arch/arm/mach-imx/clk-imx51-imx53.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx51-imx53.c 2014-04-13 23:18:35.000000000 +0200 @@ -266,8 +266,6 @@ clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1"); clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1"); clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0"); - clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1"); clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0"); clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1"); clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0"); diff -Nur linux-3.14.1/arch/arm/mach-imx/clk-imx6q.c linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx6q.c --- linux-3.14.1/arch/arm/mach-imx/clk-imx6q.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx6q.c 2014-04-13 23:18:35.000000000 +0200 @@ -437,12 +437,7 @@ clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); - clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); - clk_register_clkdev(clk[ahb], "ahb", NULL); - clk_register_clkdev(clk[cko1], "cko1", NULL); - clk_register_clkdev(clk[arm], NULL, "cpu0"); - clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); - clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); + clk_register_clkdev(clk[enet_ref], "enet_ref", NULL); if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { diff -Nur linux-3.14.1/arch/arm/mach-imx/clk-imx6sl.c linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx6sl.c --- linux-3.14.1/arch/arm/mach-imx/clk-imx6sl.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/clk-imx6sl.c 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -18,27 +18,43 @@ #include "clk.h" #include "common.h" -static const char const *step_sels[] = { "osc", "pll2_pfd2", }; -static const char const *pll1_sw_sels[] = { "pll1_sys", "step", }; -static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; -static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", }; -static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; -static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; -static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; -static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; -static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; -static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; -static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; -static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; -static const char const *perclk_sels[] = { "ipg", "osc", }; -static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; -static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; -static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; -static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; -static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; -static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; -static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; -static const char const *uart_sels[] = { "pll3_80m", "osc", }; +#define CCSR 0xc +#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define CACRR 0x10 +#define CDHIPR 0x48 +#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define ARM_WAIT_DIV_396M 2 +#define ARM_WAIT_DIV_792M 4 +#define ARM_WAIT_DIV_996M 6 + +#define PLL_ARM 0x0 +#define BM_PLL_ARM_DIV_SELECT (0x7f << 0) +#define BM_PLL_ARM_POWERDOWN (1 << 12) +#define BM_PLL_ARM_ENABLE (1 << 13) +#define BM_PLL_ARM_LOCK (1 << 31) +#define PLL_ARM_DIV_792M 66 + +static const char *step_sels[] = { "osc", "pll2_pfd2", }; +static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; +static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; +static const char *ocram_sels[] = { "periph", "ocram_alt_sels", }; +static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; +static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; +static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; +static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; +static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; +static const char *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; +static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; +static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; +static const char *perclk_sels[] = { "ipg", "osc", }; +static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; +static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; +static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; +static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; +static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; +static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; +static const char *ecspi_sels[] = { "pll3_60m", "osc", }; +static const char *uart_sels[] = { "pll3_80m", "osc", }; static struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, @@ -65,6 +81,89 @@ static struct clk *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; +static void __iomem *ccm_base; +static void __iomem *anatop_base; + +static const u32 clks_init_on[] __initconst = { + IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, +}; + +/* + * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken + * during WAIT mode entry process could cause cache memory + * corruption. + * + * Software workaround: + * To prevent this issue from occurring, software should ensure that the + * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before + * entering WAIT mode. + * + * This function will set the ARM clk to max value within the 12:5 limit. + * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz), + * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since + * the clk APIs can NOT be called in idle thread(may cause kernel schedule + * as there is sleep function in PLL wait function), so here we just slow + * down ARM to below freq according to previous freq: + * + * run mode wait mode + * 396MHz -> 132MHz; + * 792MHz -> 158.4MHz; + * 996MHz -> 142.3MHz; + */ +static int imx6sl_get_arm_divider_for_wait(void) +{ + if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { + return ARM_WAIT_DIV_396M; + } else { + if ((readl_relaxed(anatop_base + PLL_ARM) & + BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M) + return ARM_WAIT_DIV_792M; + else + return ARM_WAIT_DIV_996M; + } +} + +static void imx6sl_enable_pll_arm(bool enable) +{ + static u32 saved_pll_arm; + u32 val; + + if (enable) { + saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); + val |= BM_PLL_ARM_ENABLE; + val &= ~BM_PLL_ARM_POWERDOWN; + writel_relaxed(val, anatop_base + PLL_ARM); + while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) + ; + } else { + writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); + } +} + +void imx6sl_set_wait_clk(bool enter) +{ + static unsigned long saved_arm_div; + int arm_div_for_wait = imx6sl_get_arm_divider_for_wait(); + + /* + * According to hardware design, arm podf change need + * PLL1 clock enabled. + */ + if (arm_div_for_wait == ARM_WAIT_DIV_396M) + imx6sl_enable_pll_arm(true); + + if (enter) { + saved_arm_div = readl_relaxed(ccm_base + CACRR); + writel_relaxed(arm_div_for_wait, ccm_base + CACRR); + } else { + writel_relaxed(saved_arm_div, ccm_base + CACRR); + } + while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) + ; + + if (arm_div_for_wait == ARM_WAIT_DIV_396M) + imx6sl_enable_pll_arm(false); +} static void __init imx6sl_clocks_init(struct device_node *ccm_node) { @@ -72,6 +171,7 @@ void __iomem *base; int irq; int i; + int ret; clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); @@ -80,6 +180,7 @@ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); base = of_iomap(np, 0); WARN_ON(!base); + anatop_base = base; /* type name parent base div_mask */ clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); @@ -127,6 +228,7 @@ np = ccm_node; base = of_iomap(np, 0); WARN_ON(!base); + ccm_base = base; /* Reuse imx6q pm code */ imx6q_pm_set_ccm_base(base); @@ -258,6 +360,19 @@ clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0"); clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); + /* Ensure the AHB clk is at 132MHz. */ + ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); + if (ret) + pr_warn("%s: failed to set AHB clock rate %d!\n", + __func__, ret); + + /* + * Make sure those always on clocks are enabled to maintain the correct + * usecount and enabling/disabling of parent PLLs. + */ + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clks[clks_init_on[i]]); + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); diff -Nur linux-3.14.1/arch/arm/mach-imx/clk-vf610.c linux-3.15-rc1.orig/arch/arm/mach-imx/clk-vf610.c --- linux-3.14.1/arch/arm/mach-imx/clk-vf610.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/clk-vf610.c 2014-04-13 23:18:35.000000000 +0200 @@ -63,25 +63,25 @@ static void __iomem *ccm_base; /* sources for multiplexer clocks, this is used multiple times */ -static const char const *fast_sels[] = { "firc", "fxosc", }; -static const char const *slow_sels[] = { "sirc_32k", "sxosc", }; -static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; -static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; -static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; -static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; -static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; -static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; -static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; -static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; -static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; -static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; -static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; -static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; -static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; -static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; +static const char *fast_sels[] = { "firc", "fxosc", }; +static const char *slow_sels[] = { "sirc_32k", "sxosc", }; +static const char *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; +static const char *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; +static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; +static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; +static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; +static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; +static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; +static const char *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; +static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; +static const char *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; +static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; +static const char *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; /* FTM counter clock source, not module clock */ -static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; -static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; +static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; +static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; static struct clk_div_table pll4_main_div_table[] = { { .val = 0, .div = 1 }, diff -Nur linux-3.14.1/arch/arm/mach-imx/common.h linux-3.15-rc1.orig/arch/arm/mach-imx/common.h --- linux-3.14.1/arch/arm/mach-imx/common.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/common.h 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -116,7 +116,6 @@ void imx_set_cpu_jump(int cpu, void *jump_addr); u32 imx_get_cpu_arg(int cpu); void imx_set_cpu_arg(int cpu, u32 arg); -void v7_cpu_resume(void); #ifdef CONFIG_SMP void v7_secondary_startup(void); void imx_scu_map_io(void); @@ -139,13 +138,25 @@ void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -void imx6q_set_chicken_bit(void); +void imx6q_set_int_mem_clk_lpm(void); +void imx6sl_set_wait_clk(bool enter); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); +#ifdef CONFIG_SUSPEND +void v7_cpu_resume(void); +void imx6_suspend(void __iomem *ocram_vbase); +#else +static inline void v7_cpu_resume(void) {} +static inline void imx6_suspend(void __iomem *ocram_vbase) {} +#endif + void imx6q_pm_init(void); +void imx6dl_pm_init(void); +void imx6sl_pm_init(void); void imx6q_pm_set_ccm_base(void __iomem *base); + #ifdef CONFIG_PM void imx5_pm_init(void); #else diff -Nur linux-3.14.1/arch/arm/mach-imx/cpuidle.h linux-3.15-rc1.orig/arch/arm/mach-imx/cpuidle.h --- linux-3.14.1/arch/arm/mach-imx/cpuidle.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/cpuidle.h 2014-04-13 23:18:35.000000000 +0200 @@ -13,6 +13,7 @@ #ifdef CONFIG_CPU_IDLE extern int imx5_cpuidle_init(void); extern int imx6q_cpuidle_init(void); +extern int imx6sl_cpuidle_init(void); #else static inline int imx5_cpuidle_init(void) { @@ -22,4 +23,8 @@ { return 0; } +static inline int imx6sl_cpuidle_init(void) +{ + return 0; +} #endif diff -Nur linux-3.14.1/arch/arm/mach-imx/cpuidle-imx6q.c linux-3.15-rc1.orig/arch/arm/mach-imx/cpuidle-imx6q.c --- linux-3.14.1/arch/arm/mach-imx/cpuidle-imx6q.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/cpuidle-imx6q.c 2014-04-13 23:18:35.000000000 +0200 @@ -68,8 +68,8 @@ /* Need to enable SCU standby for entering WAIT modes */ imx_scu_standby_enable(); - /* Set chicken bit to get a reliable WAIT mode support */ - imx6q_set_chicken_bit(); + /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ + imx6q_set_int_mem_clk_lpm(); return cpuidle_register(&imx6q_cpuidle_driver, NULL); } diff -Nur linux-3.14.1/arch/arm/mach-imx/cpuidle-imx6sl.c linux-3.15-rc1.orig/arch/arm/mach-imx/cpuidle-imx6sl.c --- linux-3.14.1/arch/arm/mach-imx/cpuidle-imx6sl.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/cpuidle-imx6sl.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include "common.h" +#include "cpuidle.h" + +static int imx6sl_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + imx6q_set_lpm(WAIT_UNCLOCKED); + /* + * Software workaround for ERR005311, see function + * description for details. + */ + imx6sl_set_wait_clk(true); + cpu_do_idle(); + imx6sl_set_wait_clk(false); + imx6q_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6sl_cpuidle_driver = { + .name = "imx6sl_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_TIMER_STOP, + .enter = imx6sl_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + }, + .state_count = 2, + .safe_state_index = 0, +}; + +int __init imx6sl_cpuidle_init(void) +{ + return cpuidle_register(&imx6sl_cpuidle_driver, NULL); +} diff -Nur linux-3.14.1/arch/arm/mach-imx/devices/devices-common.h linux-3.15-rc1.orig/arch/arm/mach-imx/devices/devices-common.h --- linux-3.14.1/arch/arm/mach-imx/devices/devices-common.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/devices/devices-common.h 2014-04-13 23:18:35.000000000 +0200 @@ -290,15 +290,6 @@ struct platform_device *__init imx_add_pata_imx( const struct imx_pata_imx_data *data); -struct imx_mxc_pwm_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_pwm( - const struct imx_mxc_pwm_data *data); - /* mxc_rtc */ struct imx_mxc_rtc_data { const char *devid; diff -Nur linux-3.14.1/arch/arm/mach-imx/devices/Kconfig linux-3.15-rc1.orig/arch/arm/mach-imx/devices/Kconfig --- linux-3.14.1/arch/arm/mach-imx/devices/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/devices/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -67,9 +67,6 @@ config IMX_HAVE_PLATFORM_MXC_NAND bool -config IMX_HAVE_PLATFORM_MXC_PWM - bool - config IMX_HAVE_PLATFORM_MXC_RNGA bool select ARCH_HAS_RNGA diff -Nur linux-3.14.1/arch/arm/mach-imx/devices/Makefile linux-3.15-rc1.orig/arch/arm/mach-imx/devices/Makefile --- linux-3.14.1/arch/arm/mach-imx/devices/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/devices/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -23,7 +23,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o diff -Nur linux-3.14.1/arch/arm/mach-imx/devices/platform-mxc_pwm.c linux-3.15-rc1.orig/arch/arm/mach-imx/devices/platform-mxc_pwm.c --- linux-3.14.1/arch/arm/mach-imx/devices/platform-mxc_pwm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/devices/platform-mxc_pwm.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_PWM ## _hwid, \ - } -#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { -#define imx25_mxc_pwm_data_entry(_id, _hwid) \ - imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_mxc_pwm_data_entry(0, 1), - imx25_mxc_pwm_data_entry(1, 2), - imx25_mxc_pwm_data_entry(2, 3), - imx25_mxc_pwm_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = { -#define imx51_mxc_pwm_data_entry(_id, _hwid) \ - imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K) - imx51_mxc_pwm_data_entry(0, 1), - imx51_mxc_pwm_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -struct platform_device *__init imx_add_mxc_pwm( - const struct imx_mxc_pwm_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("mxc_pwm", data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff -Nur linux-3.14.1/arch/arm/mach-imx/devices-imx25.h linux-3.15-rc1.orig/arch/arm/mach-imx/devices-imx25.h --- linux-3.14.1/arch/arm/mach-imx/devices-imx25.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/devices-imx25.h 2014-04-13 23:18:35.000000000 +0200 @@ -83,7 +83,3 @@ #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) - -extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[]; -#define imx25_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx25_mxc_pwm_data[id]) diff -Nur linux-3.14.1/arch/arm/mach-imx/devices-imx51.h linux-3.15-rc1.orig/arch/arm/mach-imx/devices-imx51.h --- linux-3.14.1/arch/arm/mach-imx/devices-imx51.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/devices-imx51.h 2014-04-13 23:18:35.000000000 +0200 @@ -57,10 +57,6 @@ #define imx51_add_imx2_wdt(id) \ imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) -extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; -#define imx51_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx51_mxc_pwm_data[id]) - extern const struct imx_imx_keypad_data imx51_imx_keypad_data; #define imx51_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) diff -Nur linux-3.14.1/arch/arm/mach-imx/hardware.h linux-3.15-rc1.orig/arch/arm/mach-imx/hardware.h --- linux-3.14.1/arch/arm/mach-imx/hardware.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/hardware.h 2014-04-13 23:18:35.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -20,7 +20,9 @@ #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #define __ASM_ARCH_MXC_HARDWARE_H__ +#ifndef __ASSEMBLY__ #include +#endif #include #define addr_in_module(addr, mod) \ diff -Nur linux-3.14.1/arch/arm/mach-imx/headsmp.S linux-3.15-rc1.orig/arch/arm/mach-imx/headsmp.S --- linux-3.14.1/arch/arm/mach-imx/headsmp.S 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/headsmp.S 2014-04-13 23:18:35.000000000 +0200 @@ -12,12 +12,7 @@ #include #include -#include -#include - .section ".text.head", "ax" - -#ifdef CONFIG_SMP diag_reg_offset: .word g_diag_reg - . @@ -34,38 +29,3 @@ set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) -#endif - -#ifdef CONFIG_ARM_CPU_SUSPEND -/* - * The following code must assume it is running from physical address - * where absolute virtual addresses to the data section have to be - * turned into relative ones. - */ - -#ifdef CONFIG_CACHE_L2X0 - .macro pl310_resume - adr r0, l2x0_saved_regs_offset - ldr r2, [r0] - add r2, r2, r0 - ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 - ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value - str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl - mov r1, #0x1 - str r1, [r0, #L2X0_CTRL] @ re-enable L2 - .endm - -l2x0_saved_regs_offset: - .word l2x0_saved_regs - . - -#else - .macro pl310_resume - .endm -#endif - -ENTRY(v7_cpu_resume) - bl v7_invalidate_l1 - pl310_resume - b cpu_resume -ENDPROC(v7_cpu_resume) -#endif diff -Nur linux-3.14.1/arch/arm/mach-imx/Kconfig linux-3.15-rc1.orig/arch/arm/mach-imx/Kconfig --- linux-3.14.1/arch/arm/mach-imx/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -1,19 +1,15 @@ config ARCH_MXC bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM - select ARM_PATCH_PHYS_VIRT select CLKSRC_MMIO - select COMMON_CLK - select GENERIC_ALLOCATOR - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 - select MULTI_IRQ_HANDLER select PINCTRL + select PM_OPP if PM select SOC_BUS - select SPARSE_IRQ - select USE_OF + select SRAM help Support for Freescale MXC/iMX-based family of processors @@ -121,18 +117,16 @@ config SOC_IMX35 bool select ARCH_MXC_IOMUX_V3 - select CPU_V6K select HAVE_EPIT select MXC_AVIC + select PINCTRL_IMX35 select SMP_ON_UP if SMP - select PINCTRL config SOC_IMX5 bool select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP select ARCH_MXC_IOMUX_V3 - select CPU_V7 select MXC_TZIC config SOC_IMX51 @@ -777,65 +771,50 @@ config SOC_IMX53 bool "i.MX53 support" select HAVE_IMX_SRC - select IMX_HAVE_PLATFORM_IMX2_WDT select PINCTRL_IMX53 select SOC_IMX5 help This enables support for Freescale i.MX53 processor. -config SOC_IMX6Q - bool "i.MX6 Quad/DualLite support" - select ARCH_HAS_CPUFREQ - select ARCH_HAS_OPP +config SOC_IMX6 + bool select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 select ARM_GIC - select CPU_V7 - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP select HAVE_IMX_ANATOP select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC - select HAVE_SMP select MFD_SYSCON - select MIGHT_HAVE_PCI - select PCI_DOMAINS if PCI - select PINCTRL_IMX6Q select PL310_ERRATA_588369 if CACHE_PL310 select PL310_ERRATA_727915 if CACHE_PL310 select PL310_ERRATA_769419 if CACHE_PL310 - select PM_OPP if PM + +config SOC_IMX6Q + bool "i.MX6 Quad/DualLite support" + select ARM_ERRATA_764369 if SMP + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + select PINCTRL_IMX6Q + select SOC_IMX6 help This enables support for Freescale i.MX6 Quad processor. config SOC_IMX6SL bool "i.MX6 SoloLite support" - select ARM_ERRATA_754322 - select ARM_ERRATA_775420 - select ARM_GIC - select CPU_V7 - select HAVE_IMX_ANATOP - select HAVE_IMX_GPC - select HAVE_IMX_MMDC - select HAVE_IMX_SRC - select MFD_SYSCON select PINCTRL_IMX6SL - select PL310_ERRATA_588369 if CACHE_PL310 - select PL310_ERRATA_727915 if CACHE_PL310 - select PL310_ERRATA_769419 if CACHE_PL310 + select SOC_IMX6 help This enables support for Freescale i.MX6 SoloLite processor. config SOC_VF610 bool "Vybrid Family VF610 support" - select CPU_V7 select ARM_GIC - select CLKSRC_OF select PINCTRL_VF610 select VF_PIT_TIMER select PL310_ERRATA_588369 if CACHE_PL310 diff -Nur linux-3.14.1/arch/arm/mach-imx/mach-imx6q.c linux-3.15-rc1.orig/arch/arm/mach-imx/mach-imx6q.c --- linux-3.14.1/arch/arm/mach-imx/mach-imx6q.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/mach-imx6q.c 2014-04-13 23:18:35.000000000 +0200 @@ -182,16 +182,83 @@ static void __init imx6q_1588_init(void) { + struct device_node *np; + struct clk *ptp_clk; + struct clk *enet_ref; struct regmap *gpr; + u32 clksel; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); + if (!np) { + pr_warn("%s: failed to find fec node\n", __func__); + return; + } + ptp_clk = of_clk_get(np, 2); + if (IS_ERR(ptp_clk)) { + pr_warn("%s: failed to get ptp clock\n", __func__); + goto put_node; + } + + enet_ref = clk_get_sys(NULL, "enet_ref"); + if (IS_ERR(enet_ref)) { + pr_warn("%s: failed to get enet clock\n", __func__); + goto put_ptp_clk; + } + + /* + * If enet_ref from ANATOP/CCM is the PTP clock source, we need to + * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad + * (external OSC), and we need to clear the bit. + */ + clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : + IMX6Q_GPR1_ENET_CLK_SEL_PAD; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_ENET_CLK_SEL_MASK, - IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); + clksel); else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); + clk_put(enet_ref); +put_ptp_clk: + clk_put(ptp_clk); +put_node: + of_node_put(np); +} + +static void __init imx6q_axi_init(void) +{ + struct regmap *gpr; + unsigned int mask; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + /* + * Enable the cacheable attribute of VPU and IPU + * AXI transactions. + */ + mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL | + IMX6Q_GPR4_VPU_RD_CACHE_SEL | + IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | + IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK | + IMX6Q_GPR4_IPU_WR_CACHE_CTL | + IMX6Q_GPR4_IPU_RD_CACHE_CTL; + regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask); + + /* Increase IPU read QoS priority */ + regmap_update_bits(gpr, IOMUXC_GPR6, + IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | + IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); + regmap_update_bits(gpr, IOMUXC_GPR7, + IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | + IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); + } else { + pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + } } static void __init imx6q_init_machine(void) @@ -212,15 +279,18 @@ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); imx_anatop_init(); - imx6q_pm_init(); + cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); imx6q_1588_init(); + imx6q_axi_init(); } #define OCOTP_CFG3 0x440 #define OCOTP_CFG3_SPEED_SHIFT 16 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 +#define OCOTP_CFG3_SPEED_996MHZ 0x2 +#define OCOTP_CFG3_SPEED_852MHZ 0x1 -static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) +static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) { struct device_node *np; void __iomem *base; @@ -238,11 +308,29 @@ goto put_node; } + /* + * SPEED_GRADING[1:0] defines the max speed of ARM: + * 2b'11: 1200000000Hz; + * 2b'10: 996000000Hz; + * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. + * 2b'00: 792000000Hz; + * We need to set the max speed of ARM according to fuse map. + */ val = readl_relaxed(base + OCOTP_CFG3); val >>= OCOTP_CFG3_SPEED_SHIFT; - if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) + val &= 0x3; + + if (val != OCOTP_CFG3_SPEED_1P2GHZ) if (dev_pm_opp_disable(cpu_dev, 1200000000)) pr_warn("failed to disable 1.2 GHz OPP\n"); + if (val < OCOTP_CFG3_SPEED_996MHZ) + if (dev_pm_opp_disable(cpu_dev, 996000000)) + pr_warn("failed to disable 996 MHz OPP\n"); + if (cpu_is_imx6q()) { + if (val != OCOTP_CFG3_SPEED_852MHZ) + if (dev_pm_opp_disable(cpu_dev, 852000000)) + pr_warn("failed to disable 852 MHz OPP\n"); + } put_node: of_node_put(np); @@ -268,7 +356,7 @@ goto put_node; } - imx6q_opp_check_1p2ghz(cpu_dev); + imx6q_opp_check_speed_grading(cpu_dev); put_node: of_node_put(np); diff -Nur linux-3.14.1/arch/arm/mach-imx/mach-imx6sl.c linux-3.15-rc1.orig/arch/arm/mach-imx/mach-imx6sl.c --- linux-3.14.1/arch/arm/mach-imx/mach-imx6sl.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/mach-imx6sl.c 2014-04-13 23:18:35.000000000 +0200 @@ -17,6 +17,7 @@ #include #include "common.h" +#include "cpuidle.h" static void __init imx6sl_fec_init(void) { @@ -39,6 +40,8 @@ /* imx6sl reuses imx6q cpufreq driver */ if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); + + imx6sl_cpuidle_init(); } static void __init imx6sl_init_machine(void) @@ -55,8 +58,7 @@ imx6sl_fec_init(); imx_anatop_init(); - /* Reuse imx6q pm code */ - imx6q_pm_init(); + imx6sl_pm_init(); } static void __init imx6sl_init_irq(void) diff -Nur linux-3.14.1/arch/arm/mach-imx/mach-mx27ads.c linux-3.15-rc1.orig/arch/arm/mach-imx/mach-mx27ads.c --- linux-3.14.1/arch/arm/mach-imx/mach-mx27ads.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/mach-mx27ads.c 2014-04-13 23:18:35.000000000 +0200 @@ -21,6 +21,10 @@ #include #include #include + +#include +#include + #include #include #include @@ -195,14 +199,58 @@ static struct i2c_board_info mx27ads_i2c_devices[] = { }; -void lcd_power(int on) +static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value) { - if (on) + if (value) __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); else __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); } +static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value) +{ + return 0; +} + +#define MX27ADS_LCD_GPIO (6 * 32) + +static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer = + REGULATOR_SUPPLY("lcd", "imx-fb.0"); + +static struct regulator_init_data mx27ads_lcd_regulator_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, +}, + .consumer_supplies = &mx27ads_lcd_regulator_consumer, + .num_consumer_supplies = 1, +}; + +static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = { + .supply_name = "LCD", + .microvolts = 3300000, + .gpio = MX27ADS_LCD_GPIO, + .init_data = &mx27ads_lcd_regulator_init_data, +}; + +static void __init mx27ads_regulator_init(void) +{ + struct gpio_chip *vchip; + + vchip = kzalloc(sizeof(*vchip), GFP_KERNEL); + vchip->owner = THIS_MODULE; + vchip->label = "LCD"; + vchip->base = MX27ADS_LCD_GPIO; + vchip->ngpio = 1; + vchip->direction_output = vgpio_dir_out; + vchip->set = vgpio_set; + gpiochip_add(vchip); + + platform_device_register_data(&platform_bus, "reg-fixed-voltage", + PLATFORM_DEVID_AUTO, + &mx27ads_lcd_regulator_pdata, + sizeof(mx27ads_lcd_regulator_pdata)); +} + static struct imx_fb_videomode mx27ads_modes[] = { { .mode = { @@ -239,8 +287,6 @@ .pwmr = 0x00A903FF, .lscr1 = 0x00120300, .dmacr = 0x00020010, - - .lcd_power = lcd_power, }; static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, @@ -304,6 +350,7 @@ i2c_register_board_info(1, mx27ads_i2c_devices, ARRAY_SIZE(mx27ads_i2c_devices)); imx27_add_imx_i2c(1, &mx27ads_i2c1_data); + mx27ads_regulator_init(); imx27_add_imx_fb(&mx27ads_fb_data); imx27_add_mxc_mmc(0, &sdhc1_pdata); imx27_add_mxc_mmc(1, &sdhc2_pdata); diff -Nur linux-3.14.1/arch/arm/mach-imx/mach-mx31moboard.c linux-3.15-rc1.orig/arch/arm/mach-imx/mach-mx31moboard.c --- linux-3.14.1/arch/arm/mach-imx/mach-mx31moboard.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/mach-mx31moboard.c 2014-04-13 23:18:35.000000000 +0200 @@ -128,27 +128,15 @@ .num_resources = 1, }; -static int moboard_uart0_init(struct platform_device *pdev) +static void __init moboard_uart0_init(void) { - int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); - if (ret) - return ret; - - ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); - if (ret) + if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack")) { + gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); - - return ret; -} - -static void moboard_uart0_exit(struct platform_device *pdev) -{ - gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); + } } static const struct imxuart_platform_data uart0_pdata __initconst = { - .init = moboard_uart0_init, - .exit = moboard_uart0_exit, }; static const struct imxuart_platform_data uart4_pdata __initconst = { @@ -543,6 +531,7 @@ imx31_add_imx2_wdt(); + moboard_uart0_init(); imx31_add_imx_uart0(&uart0_pdata); imx31_add_imx_uart4(&uart4_pdata); diff -Nur linux-3.14.1/arch/arm/mach-imx/Makefile linux-3.15-rc1.orig/arch/arm/mach-imx/Makefile --- linux-3.14.1/arch/arm/mach-imx/Makefile 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/Makefile 2014-04-13 23:18:35.000000000 +0200 @@ -30,6 +30,7 @@ ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o endif ifdef CONFIG_SND_IMX_SOC @@ -101,9 +102,11 @@ obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o -# i.MX6SL reuses i.MX6Q code -obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o +ifeq ($(CONFIG_SUSPEND),y) +AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o +endif +obj-$(CONFIG_SOC_IMX6) += pm-imx6.o # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o diff -Nur linux-3.14.1/arch/arm/mach-imx/pm-imx6.c linux-3.15-rc1.orig/arch/arm/mach-imx/pm-imx6.c --- linux-3.14.1/arch/arm/mach-imx/pm-imx6.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/pm-imx6.c 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,551 @@ +/* + * Copyright 2011-2014 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +#define CCR 0x0 +#define BM_CCR_WB_COUNT (0x7 << 16) +#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) +#define BM_CCR_RBC_EN (0x1 << 27) + +#define CLPCR 0x54 +#define BP_CLPCR_LPM 0 +#define BM_CLPCR_LPM (0x3 << 0) +#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) +#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define BM_CLPCR_SBYOS (0x1 << 6) +#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define BM_CLPCR_VSTBY (0x1 << 8) +#define BP_CLPCR_STBY_COUNT 9 +#define BM_CLPCR_STBY_COUNT (0x3 << 9) +#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) +#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) +#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) +#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) +#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) +#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) +#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) +#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) +#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) +#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) + +#define CGPR 0x64 +#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) + +#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 +#define MX6_MAX_MMDC_IO_NUM 33 + +static void __iomem *ccm_base; +static void __iomem *suspend_ocram_base; +static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); + +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx6_suspend code + * PM_INFO structure(imx6_cpu_pm_info) + * ======================== low address ======================= + */ + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_pm_socdata { + u32 cpu_type; + const char *mmdc_compat; + const char *src_compat; + const char *iomuxc_compat; + const char *gpc_compat; + const u32 mmdc_io_num; + const u32 *mmdc_io_offset; +}; + +static const u32 imx6q_mmdc_io_offset[] __initconst = { + 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ + 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ + 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ + 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ + 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ + 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, /* GPR_ADDS */ +}; + +static const u32 imx6dl_mmdc_io_offset[] __initconst = { + 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ + 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ + 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ + 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ + 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ + 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, /* GPR_ADDS */ +}; + +static const u32 imx6sl_mmdc_io_offset[] __initconst = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ +}; + +static const struct imx6_pm_socdata imx6q_pm_data __initconst = { + .cpu_type = MXC_CPU_IMX6Q, + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6q-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), + .mmdc_io_offset = imx6q_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { + .cpu_type = MXC_CPU_IMX6DL, + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6dl-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), + .mmdc_io_offset = imx6dl_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { + .cpu_type = MXC_CPU_IMX6SL, + .mmdc_compat = "fsl,imx6sl-mmdc", + .src_compat = "fsl,imx6sl-src", + .iomuxc_compat = "fsl,imx6sl-iomuxc", + .gpc_compat = "fsl,imx6sl-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), + .mmdc_io_offset = imx6sl_mmdc_io_offset, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, + * otherwise, the suspend to ocram function will be broken! + */ +struct imx6_cpu_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 cpu_type; + u32 pm_info_size; /* Size of pm_info. */ + struct imx6_pm_base mmdc_base; + struct imx6_pm_base src_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base l2_base; + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +void imx6q_set_int_mem_clk_lpm(void) +{ + u32 val = readl_relaxed(ccm_base + CGPR); + + val |= BM_CGPR_INT_MEM_CLK_LPM; + writel_relaxed(val, ccm_base + CGPR); +} + +static void imx6q_enable_rbc(bool enable) +{ + u32 val; + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpc_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_EN; + val |= enable ? BM_CCR_RBC_EN : 0; + writel_relaxed(val, ccm_base + CCR); + + /* configure RBC count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_BYPASS_COUNT; + val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; + writel(val, ccm_base + CCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpc_restore_all(); +} + +static void imx6q_enable_wb(bool enable) +{ + u32 val; + + /* configure well bias enable bit */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_WB_PER_AT_LPM; + val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; + writel_relaxed(val, ccm_base + CLPCR); + + /* configure well bias count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_WB_COUNT; + val |= enable ? BM_CCR_WB_COUNT : 0; + writel_relaxed(val, ccm_base + CCR); +} + +int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) +{ + struct irq_data *iomuxc_irq_data = irq_get_irq_data(32); + u32 val = readl_relaxed(ccm_base + CLPCR); + + val &= ~BM_CLPCR_LPM; + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + val |= 0x1 << BP_CLPCR_LPM; + val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; + break; + case STOP_POWER_ON: + val |= 0x2 << BP_CLPCR_LPM; + break; + case WAIT_UNCLOCKED_POWER_OFF: + val |= 0x1 << BP_CLPCR_LPM; + val &= ~BM_CLPCR_VSTBY; + val &= ~BM_CLPCR_SBYOS; + break; + case STOP_POWER_OFF: + val |= 0x2 << BP_CLPCR_LPM; + val |= 0x3 << BP_CLPCR_STBY_COUNT; + val |= BM_CLPCR_VSTBY; + val |= BM_CLPCR_SBYOS; + if (cpu_is_imx6sl()) { + val |= BM_CLPCR_BYPASS_PMIC_READY; + val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + } else { + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } + break; + default: + return -EINVAL; + } + + /* + * ERR007265: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_GINT. + * 2) Software should then unmask IRQ #32 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #32 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + imx_gpc_irq_unmask(iomuxc_irq_data); + writel_relaxed(val, ccm_base + CLPCR); + imx_gpc_irq_mask(iomuxc_irq_data); + + return 0; +} + +static int imx6q_suspend_finish(unsigned long val) +{ + if (!imx6_suspend_in_ocram_fn) { + cpu_do_idle(); + } else { + /* + * call low level suspend function in ocram, + * as we need to float DDR IO. + */ + local_flush_tlb_all(); + imx6_suspend_in_ocram_fn(suspend_ocram_base); + } + + return 0; +} + +static int imx6q_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_MEM: + imx6q_set_lpm(STOP_POWER_OFF); + imx6q_enable_wb(true); + /* + * For suspend into ocram, asm code already take care of + * RBC setting, so we do NOT need to do that here. + */ + if (!imx6_suspend_in_ocram_fn) + imx6q_enable_rbc(true); + imx_gpc_pre_suspend(); + imx_anatop_pre_suspend(); + imx_set_cpu_jump(0, v7_cpu_resume); + /* Zzz ... */ + cpu_suspend(0, imx6q_suspend_finish); + if (cpu_is_imx6q() || cpu_is_imx6dl()) + imx_smp_prepare(); + imx_anatop_post_resume(); + imx_gpc_post_resume(); + imx6q_enable_rbc(false); + imx6q_enable_wb(false); + imx6q_set_lpm(WAIT_CLOCKED); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct platform_suspend_ops imx6q_pm_ops = { + .enter = imx6q_pm_enter, + .valid = suspend_valid_only_mem, +}; + +void __init imx6q_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + +static int __init imx6_pm_get_base(struct imx6_pm_base *base, + const char *compat) +{ + struct device_node *node; + struct resource res; + int ret = 0; + + node = of_find_compatible_node(NULL, NULL, compat); + if (!node) { + ret = -ENODEV; + goto out; + } + + ret = of_address_to_resource(node, 0, &res); + if (ret) + goto put_node; + + base->pbase = res.start; + base->vbase = ioremap(res.start, resource_size(&res)); + if (!base->vbase) + ret = -ENOMEM; + +put_node: + of_node_put(node); +out: + return ret; +} + +static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) +{ + phys_addr_t ocram_pbase; + struct device_node *node; + struct platform_device *pdev; + struct imx6_cpu_pm_info *pm_info; + struct gen_pool *ocram_pool; + unsigned long ocram_base; + int i, ret = 0; + const u32 *mmdc_offset_array; + + suspend_set_ops(&imx6q_pm_ops); + + if (!socdata) { + pr_warn("%s: invalid argument!\n", __func__); + return -EINVAL; + } + + node = of_find_compatible_node(NULL, NULL, "mmio-sram"); + if (!node) { + pr_warn("%s: failed to find ocram node!\n", __func__); + return -ENODEV; + } + + pdev = of_find_device_by_node(node); + if (!pdev) { + pr_warn("%s: failed to find ocram device!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_pool = dev_get_gen_pool(&pdev->dev); + if (!ocram_pool) { + pr_warn("%s: ocram pool unavailable!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); + if (!ocram_base) { + pr_warn("%s: unable to alloc ocram!\n", __func__); + ret = -ENOMEM; + goto put_node; + } + + ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); + + suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, + MX6Q_SUSPEND_OCRAM_SIZE, false); + + pm_info = suspend_ocram_base; + pm_info->pbase = ocram_pbase; + pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + /* + * ccm physical address is not used by asm code currently, + * so get ccm virtual address directly, as we already have + * it from ccm driver. + */ + pm_info->ccm_base.vbase = ccm_base; + + ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); + if (ret) { + pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); + goto put_node; + } + + ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); + if (ret) { + pr_warn("%s: failed to get src base %d!\n", __func__, ret); + goto src_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); + if (ret) { + pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); + goto iomuxc_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); + if (ret) { + pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); + goto gpc_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache"); + if (ret) { + pr_warn("%s: failed to get pl310-cache base %d!\n", + __func__, ret); + goto pl310_cache_map_failed; + } + + pm_info->cpu_type = socdata->cpu_type; + pm_info->mmdc_io_num = socdata->mmdc_io_num; + mmdc_offset_array = socdata->mmdc_io_offset; + + for (i = 0; i < pm_info->mmdc_io_num; i++) { + pm_info->mmdc_io_val[i][0] = + mmdc_offset_array[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(pm_info->iomuxc_base.vbase + + mmdc_offset_array[i]); + } + + imx6_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx6_suspend, + MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + + goto put_node; + +pl310_cache_map_failed: + iounmap(&pm_info->gpc_base.vbase); +gpc_map_failed: + iounmap(&pm_info->iomuxc_base.vbase); +iomuxc_map_failed: + iounmap(&pm_info->src_base.vbase); +src_map_failed: + iounmap(&pm_info->mmdc_base.vbase); +put_node: + of_node_put(node); + + return ret; +} + +static void __init imx6_pm_common_init(const struct imx6_pm_socdata + *socdata) +{ + struct regmap *gpr; + int ret; + + WARN_ON(!ccm_base); + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx6q_suspend_init(socdata); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } + + /* + * This is for SW workaround step #1 of ERR007265, see comments + * in imx6q_set_lpm for details of this errata. + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, + IMX6Q_GPR1_GINT); +} + +void __init imx6q_pm_init(void) +{ + imx6_pm_common_init(&imx6q_pm_data); +} + +void __init imx6dl_pm_init(void) +{ + imx6_pm_common_init(&imx6dl_pm_data); +} + +void __init imx6sl_pm_init(void) +{ + imx6_pm_common_init(&imx6sl_pm_data); +} diff -Nur linux-3.14.1/arch/arm/mach-imx/pm-imx6q.c linux-3.15-rc1.orig/arch/arm/mach-imx/pm-imx6q.c --- linux-3.14.1/arch/arm/mach-imx/pm-imx6q.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/pm-imx6q.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,241 +0,0 @@ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common.h" -#include "hardware.h" - -#define CCR 0x0 -#define BM_CCR_WB_COUNT (0x7 << 16) -#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) -#define BM_CCR_RBC_EN (0x1 << 27) - -#define CLPCR 0x54 -#define BP_CLPCR_LPM 0 -#define BM_CLPCR_LPM (0x3 << 0) -#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) -#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define BM_CLPCR_SBYOS (0x1 << 6) -#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define BM_CLPCR_VSTBY (0x1 << 8) -#define BP_CLPCR_STBY_COUNT 9 -#define BM_CLPCR_STBY_COUNT (0x3 << 9) -#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) -#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) -#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) -#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) -#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) -#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) -#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) -#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) -#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) -#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) - -#define CGPR 0x64 -#define BM_CGPR_CHICKEN_BIT (0x1 << 17) - -static void __iomem *ccm_base; - -void imx6q_set_chicken_bit(void) -{ - u32 val = readl_relaxed(ccm_base + CGPR); - - val |= BM_CGPR_CHICKEN_BIT; - writel_relaxed(val, ccm_base + CGPR); -} - -static void imx6q_enable_rbc(bool enable) -{ - u32 val; - - /* - * need to mask all interrupts in GPC before - * operating RBC configurations - */ - imx_gpc_mask_all(); - - /* configure RBC enable bit */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_EN; - val |= enable ? BM_CCR_RBC_EN : 0; - writel_relaxed(val, ccm_base + CCR); - - /* configure RBC count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_BYPASS_COUNT; - val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; - writel(val, ccm_base + CCR); - - /* - * need to delay at least 2 cycles of CKIL(32K) - * due to hardware design requirement, which is - * ~61us, here we use 65us for safe - */ - udelay(65); - - /* restore GPC interrupt mask settings */ - imx_gpc_restore_all(); -} - -static void imx6q_enable_wb(bool enable) -{ - u32 val; - - /* configure well bias enable bit */ - val = readl_relaxed(ccm_base + CLPCR); - val &= ~BM_CLPCR_WB_PER_AT_LPM; - val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; - writel_relaxed(val, ccm_base + CLPCR); - - /* configure well bias count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_WB_COUNT; - val |= enable ? BM_CCR_WB_COUNT : 0; - writel_relaxed(val, ccm_base + CCR); -} - -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) -{ - struct irq_desc *iomuxc_irq_desc; - u32 val = readl_relaxed(ccm_base + CLPCR); - - val &= ~BM_CLPCR_LPM; - switch (mode) { - case WAIT_CLOCKED: - break; - case WAIT_UNCLOCKED: - val |= 0x1 << BP_CLPCR_LPM; - val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; - break; - case STOP_POWER_ON: - val |= 0x2 << BP_CLPCR_LPM; - break; - case WAIT_UNCLOCKED_POWER_OFF: - val |= 0x1 << BP_CLPCR_LPM; - val &= ~BM_CLPCR_VSTBY; - val &= ~BM_CLPCR_SBYOS; - break; - case STOP_POWER_OFF: - val |= 0x2 << BP_CLPCR_LPM; - val |= 0x3 << BP_CLPCR_STBY_COUNT; - val |= BM_CLPCR_VSTBY; - val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) { - val |= BM_CLPCR_BYPASS_PMIC_READY; - val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; - } else { - val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; - } - break; - default: - return -EINVAL; - } - - /* - * ERR007265: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #32 (IOMUX) to be always pending - * by setting IOMUX_GPR1_GINT. - * 2) Software should then unmask IRQ #32 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #32 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - iomuxc_irq_desc = irq_to_desc(32); - imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); - writel_relaxed(val, ccm_base + CLPCR); - imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data); - - return 0; -} - -static int imx6q_suspend_finish(unsigned long val) -{ - cpu_do_idle(); - return 0; -} - -static int imx6q_pm_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_MEM: - imx6q_set_lpm(STOP_POWER_OFF); - imx6q_enable_wb(true); - imx6q_enable_rbc(true); - imx_gpc_pre_suspend(); - imx_anatop_pre_suspend(); - imx_set_cpu_jump(0, v7_cpu_resume); - /* Zzz ... */ - cpu_suspend(0, imx6q_suspend_finish); - if (cpu_is_imx6q() || cpu_is_imx6dl()) - imx_smp_prepare(); - imx_anatop_post_resume(); - imx_gpc_post_resume(); - imx6q_enable_rbc(false); - imx6q_enable_wb(false); - imx6q_set_lpm(WAIT_CLOCKED); - break; - default: - return -EINVAL; - } - - return 0; -} - -static const struct platform_suspend_ops imx6q_pm_ops = { - .enter = imx6q_pm_enter, - .valid = suspend_valid_only_mem, -}; - -void __init imx6q_pm_set_ccm_base(void __iomem *base) -{ - ccm_base = base; -} - -void __init imx6q_pm_init(void) -{ - struct regmap *gpr; - - WARN_ON(!ccm_base); - - /* - * This is for SW workaround step #1 of ERR007265, see comments - * in imx6q_set_lpm for details of this errata. - * Force IOMUXC irq pending, so that the interrupt to GPC can be - * used to deassert dsm_request signal when the signal gets - * asserted unexpectedly. - */ - gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); - if (!IS_ERR(gpr)) - regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, - IMX6Q_GPR1_GINT); - - - suspend_set_ops(&imx6q_pm_ops); -} diff -Nur linux-3.14.1/arch/arm/mach-imx/suspend-imx6.S linux-3.15-rc1.orig/arch/arm/mach-imx/suspend-imx6.S --- linux-3.14.1/arch/arm/mach-imx/suspend-imx6.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/suspend-imx6.S 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,361 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * r1 ~ r4: for saving pm_info members; + * r5 ~ r10: free registers; + * r11: io base address. + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx6_suspend code + * PM_INFO structure(imx6_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx6_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx6q.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_CPU_TYPE_OFFSET 0x8 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24 +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34 +#define PM_INFO_MX6Q_L2_P_OFFSET 0x38 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + + .align 3 + + .macro sync_l2_cache + + /* sync L2 cache to drain L2's buffers to DRAM. */ +#ifdef CONFIG_CACHE_L2X0 + ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r6, #0x0 + str r6, [r11, #L2X0_CACHE_SYNC] +1: + ldr r6, [r11, #L2X0_CACHE_SYNC] + ands r6, r6, #0x1 + bne 1b +#endif + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +1: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 1b + + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + cmp r3, #MXC_CPU_IMX6SL + bne 4f + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +2: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 2b + + /* reset FIFO a second time */ + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +3: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 3b +4: + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r11, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 5b + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX6Q_MMDC_MAPSR] + + .endm + +ENTRY(imx6_suspend) + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] + ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx6_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r4 + add r9, r8, r7 + + /* + * make sure TLB contain the addr we want, + * as we will access them after MMDC IO floated. + */ + + ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r6, [r11, #0x0] + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r6, [r11, #0x0] + + /* use r11 to store the IO address */ + ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #MX6Q_SRC_GPR1] + str r1, [r11, #MX6Q_SRC_GPR2] + + /* need to sync L2 cache before DSM. */ + sync_l2_cache + + ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + /* + * put DDR explicitly into self-refresh and + * disable automatic power savings. + */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r11, #MX6Q_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r11, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set + + ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 + /* i.MX6SL's last 3 IOs need special setting */ + cmp r3, #MXC_CPU_IMX6SL + subeq r7, r7, #0x3 +set_mmdc_io_lpm: + ldr r9, [r8], #0x8 + str r6, [r11, r9] + subs r7, r7, #0x1 + bne set_mmdc_io_lpm + + cmp r3, #MXC_CPU_IMX6SL + bne set_mmdc_io_lpm_done + ldr r6, =0x1000 + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r6, =0x80000 + ldr r9, [r8] + str r6, [r11, r9] +set_mmdc_io_lpm_done: + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r6, [r11, #MX6Q_GPC_IMR1] + ldr r7, [r11, #MX6Q_GPC_IMR2] + ldr r8, [r11, #MX6Q_GPC_IMR3] + ldr r9, [r11, #MX6Q_GPC_IMR4] + + ldr r10, =0xffffffff + str r10, [r11, #MX6Q_GPC_IMR1] + str r10, [r11, #MX6Q_GPC_IMR2] + str r10, [r11, #MX6Q_GPC_IMR3] + str r10, [r11, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 32 (1ms), Minimum RBC delay should be + * 400us for the analog LDOs to power down. + */ + ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r10, [r11, #MX6Q_CCM_CCR] + bic r10, r10, #(0x3f << 21) + orr r10, r10, #(0x20 << 21) + str r10, [r11, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r10, [r11, #MX6Q_CCM_CCR] + orr r10, r10, #(0x1 << 27) + str r10, [r11, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r6, [r11, #MX6Q_GPC_IMR1] + str r7, [r11, #MX6Q_GPC_IMR2] + str r8, [r11, #MX6Q_GPC_IMR3] + str r9, [r11, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r6, =2000 +rbc_loop: + subs r6, r6, #0x1 + bne rbc_loop + + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + /* + * run to here means there is pending + * wakeup source, system should auto + * resume, we need to restore MMDC IO first + */ + mov r5, #0x0 + resume_mmdc + + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r11, #MX6Q_SRC_GPR1] + str r7, [r11, #MX6Q_SRC_GPR2] + + ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] + mov r5, #0x1 + resume_mmdc + + mov pc, lr +ENDPROC(imx6_suspend) + +/* + * The following code must assume it is running from physical address + * where absolute virtual addresses to the data section have to be + * turned into relative ones. + */ + +#ifdef CONFIG_CACHE_L2X0 + .macro pl310_resume + adr r0, l2x0_saved_regs_offset + ldr r2, [r0] + add r2, r2, r0 + ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 + ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value + str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl + mov r1, #0x1 + str r1, [r0, #L2X0_CTRL] @ re-enable L2 + .endm + +l2x0_saved_regs_offset: + .word l2x0_saved_regs - . + +#else + .macro pl310_resume + .endm +#endif + +ENTRY(v7_cpu_resume) + bl v7_invalidate_l1 + pl310_resume + b cpu_resume +ENDPROC(v7_cpu_resume) diff -Nur linux-3.14.1/arch/arm/mach-imx/time.c linux-3.15-rc1.orig/arch/arm/mach-imx/time.c --- linux-3.14.1/arch/arm/mach-imx/time.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-imx/time.c 2014-04-13 23:18:35.000000000 +0200 @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -116,11 +117,22 @@ return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; } +static struct delay_timer imx_delay_timer; + +static unsigned long imx_read_current_timer(void) +{ + return __raw_readl(sched_clock_reg); +} + static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); + imx_delay_timer.read_current_timer = &imx_read_current_timer; + imx_delay_timer.freq = c; + register_current_timer_delay(&imx_delay_timer); + sched_clock_reg = reg; sched_clock_register(mxc_read_sched_clock, 32, c); diff -Nur linux-3.14.1/arch/arm/mach-integrator/core.c linux-3.15-rc1.orig/arch/arm/mach-integrator/core.c --- linux-3.14.1/arch/arm/mach-integrator/core.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/core.c 2014-04-13 23:18:35.000000000 +0200 @@ -25,13 +25,11 @@ #include #include -#include -#include - #include #include #include +#include "hardware.h" #include "cm.h" #include "common.h" diff -Nur linux-3.14.1/arch/arm/mach-integrator/hardware.h linux-3.15-rc1.orig/arch/arm/mach-integrator/hardware.h --- linux-3.14.1/arch/arm/mach-integrator/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/hardware.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,354 @@ +/* + * This file contains the hardware definitions of the Integrator. + * + * Copyright (C) 1998-1999 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef INTEGRATOR_HARDWARE_H +#define INTEGRATOR_HARDWARE_H + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ +#define IO_BASE 0xF0000000 // VA of IO +#define IO_SIZE 0x0B000000 // How much? +#define IO_START INTEGRATOR_HDR_BASE // PA of IO + +/* macro to get at IO space when running virtually */ +#ifdef CONFIG_MMU +#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) +#else +#define IO_ADDRESS(x) (x) +#endif + +#define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) + +/* + * Integrator memory map + */ +#define INTEGRATOR_BOOT_ROM_LO 0x00000000 +#define INTEGRATOR_BOOT_ROM_HI 0x20000000 +#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ +#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K + +/* + * New Core Modules have different amounts of SSRAM, the amount of SSRAM + * fitted can be found in HDR_STAT. + * + * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to + * the minimum amount of SSRAM fitted on any core module. + * + * New Core Modules also alias the SSRAM. + * + */ +#define INTEGRATOR_SSRAM_BASE 0x00000000 +#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 +#define INTEGRATOR_SSRAM_SIZE SZ_256K + +#define INTEGRATOR_FLASH_BASE 0x24000000 +#define INTEGRATOR_FLASH_SIZE SZ_32M + +#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 +#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K + +/* + * SDRAM is a SIMM therefore the size is not known. + */ +#define INTEGRATOR_SDRAM_BASE 0x00040000 + +#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 +#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 +#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 +#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 +#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 + +/* + * Logic expansion modules + * + */ +#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 +#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 +#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 +#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 +#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 + +/* + * Integrator header card registers + */ +#define INTEGRATOR_HDR_ID_OFFSET 0x00 +#define INTEGRATOR_HDR_PROC_OFFSET 0x04 +#define INTEGRATOR_HDR_OSC_OFFSET 0x08 +#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C +#define INTEGRATOR_HDR_STAT_OFFSET 0x10 +#define INTEGRATOR_HDR_LOCK_OFFSET 0x14 +#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 +#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ +#define INTEGRATOR_HDR_IC_OFFSET 0x40 +#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 +#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 + +#define INTEGRATOR_HDR_BASE 0x10000000 +#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) +#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) +#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) +#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) +#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) +#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) +#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) +#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) +#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) +#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) +#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) + +#define INTEGRATOR_HDR_CTRL_LED 0x01 +#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 +#define INTEGRATOR_HDR_CTRL_REMAP 0x04 +#define INTEGRATOR_HDR_CTRL_RESET 0x08 +#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 +#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 +#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 +#define INTEGRATOR_HDR_CTRL_SYNC 0x80 + +#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 +#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 +#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C +#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 +#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 +#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B +#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 +#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 +#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A +#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F +#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 +#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 +#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E +#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 +#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 +#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D +#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 +#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 +#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C +#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 +#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 +#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B +#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 +#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 +#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A +#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F +#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 +#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 +#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E +#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 +#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 +#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF + +#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 +#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 +#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 +#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 +#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 +#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 +#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 +#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 +#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 +#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 +#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 + +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 +#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 + +#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) + +/* + * Integrator system registers + */ + +/* + * System Controller + */ +#define INTEGRATOR_SC_ID_OFFSET 0x00 +#define INTEGRATOR_SC_OSC_OFFSET 0x04 +#define INTEGRATOR_SC_CTRLS_OFFSET 0x08 +#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C +#define INTEGRATOR_SC_DEC_OFFSET 0x10 +#define INTEGRATOR_SC_ARB_OFFSET 0x14 +#define INTEGRATOR_SC_LOCK_OFFSET 0x1C + +#define INTEGRATOR_SC_BASE 0x11000000 +#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) +#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) +#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) +#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) +#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) +#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) +#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) +#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) + +#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 +#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 +#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 +#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C +#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C +#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF + +#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 +#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 +#define INTEGRATOR_SC_OSC_PCI_MASK 0x100 + +#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) +#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) +#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) +#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) +#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) +#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) +#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) + +/* + * External Bus Interface + */ +#define INTEGRATOR_EBI_BASE 0x12000000 + +#define INTEGRATOR_EBI_CSR0_OFFSET 0x00 +#define INTEGRATOR_EBI_CSR1_OFFSET 0x04 +#define INTEGRATOR_EBI_CSR2_OFFSET 0x08 +#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C +#define INTEGRATOR_EBI_LOCK_OFFSET 0x20 + +#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) +#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) +#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) +#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) +#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) + +#define INTEGRATOR_EBI_8_BIT 0x00 +#define INTEGRATOR_EBI_16_BIT 0x01 +#define INTEGRATOR_EBI_32_BIT 0x02 +#define INTEGRATOR_EBI_WRITE_ENABLE 0x04 +#define INTEGRATOR_EBI_SYNC 0x08 +#define INTEGRATOR_EBI_WS_2 0x00 +#define INTEGRATOR_EBI_WS_3 0x10 +#define INTEGRATOR_EBI_WS_4 0x20 +#define INTEGRATOR_EBI_WS_5 0x30 +#define INTEGRATOR_EBI_WS_6 0x40 +#define INTEGRATOR_EBI_WS_7 0x50 +#define INTEGRATOR_EBI_WS_8 0x60 +#define INTEGRATOR_EBI_WS_9 0x70 +#define INTEGRATOR_EBI_WS_10 0x80 +#define INTEGRATOR_EBI_WS_11 0x90 +#define INTEGRATOR_EBI_WS_12 0xA0 +#define INTEGRATOR_EBI_WS_13 0xB0 +#define INTEGRATOR_EBI_WS_14 0xC0 +#define INTEGRATOR_EBI_WS_15 0xD0 +#define INTEGRATOR_EBI_WS_16 0xE0 +#define INTEGRATOR_EBI_WS_17 0xF0 + + +#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ +#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ +#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ +#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ +#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ +#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ +#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ + +/* + * LED's & Switches + */ +#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 +#define INTEGRATOR_DBG_LEDS_OFFSET 0x04 +#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 + +#define INTEGRATOR_DBG_BASE 0x1A000000 +#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) +#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) +#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) + +#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ + +#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ +#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ +#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ +#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ +#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ +#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ + +/* PS2 Keyboard interface */ +#define KMI0_BASE INTEGRATOR_KBD_BASE + +/* PS2 Mouse interface */ +#define KMI1_BASE INTEGRATOR_MOUSE_BASE + +/* + * Integrator Interrupt Controllers + * + * + * Offsets from interrupt controller base + * + * System Controller interrupt controller base is + * + * INTEGRATOR_IC_BASE + (header_number << 6) + * + * Core Module interrupt controller base is + * + * INTEGRATOR_HDR_IC + */ +#define IRQ_STATUS 0 +#define IRQ_RAW_STATUS 0x04 +#define IRQ_ENABLE 0x08 +#define IRQ_ENABLE_SET 0x08 +#define IRQ_ENABLE_CLEAR 0x0C + +#define INT_SOFT_SET 0x10 +#define INT_SOFT_CLEAR 0x14 + +#define FIQ_STATUS 0x20 +#define FIQ_RAW_STATUS 0x24 +#define FIQ_ENABLE 0x28 +#define FIQ_ENABLE_SET 0x28 +#define FIQ_ENABLE_CLEAR 0x2C + + +/* + * LED's + */ +#define GREEN_LED 0x01 +#define YELLOW_LED 0x02 +#define RED_LED 0x04 +#define GREEN_LED_2 0x08 +#define ALL_LEDS 0x0F + +#define LED_BANK INTEGRATOR_DBG_LEDS + +/* + * Timer definitions + * + * Only use timer 1 & 2 + * (both run at 24MHz and will need the clock divider set to 16). + * + * Timer 0 runs at bus frequency + */ +#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE +#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) +#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) + +#define INTEGRATOR_CSR_BASE 0x10000000 +#define INTEGRATOR_CSR_SIZE 0x10000000 + +#endif /* INTEGRATOR_HARDWARE_H */ diff -Nur linux-3.14.1/arch/arm/mach-integrator/impd1.c linux-3.15-rc1.orig/arch/arm/mach-integrator/impd1.c --- linux-3.14.1/arch/arm/mach-integrator/impd1.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/impd1.c 2014-04-13 23:18:35.000000000 +0200 @@ -23,10 +23,11 @@ #include #include #include +#include -#include -#include #include +#include "lm.h" +#include "impd1.h" static int module_id; @@ -35,6 +36,7 @@ struct impd1_module { void __iomem *base; + void __iomem *vic_base; }; void impd1_tweak_control(struct device *dev, u32 mask, u32 val) @@ -262,9 +264,6 @@ static struct impd1_device impd1_devs[] = { { - .offset = 0x03000000, - .id = 0x00041190, - }, { .offset = 0x00100000, .irq = { 1 }, .id = 0x00141011, @@ -304,46 +303,72 @@ } }; -static int impd1_probe(struct lm_device *dev) +/* + * Valid IRQs: 0 thru 9 and 11, 10 unused. + */ +#define IMPD1_VALID_IRQS 0x00000bffU + +static int __init impd1_probe(struct lm_device *dev) { struct impd1_module *impd1; - int i, ret; + int irq_base; + int i; if (dev->id != module_id) return -EINVAL; - if (!request_mem_region(dev->resource.start, SZ_4K, "LM registers")) + if (!devm_request_mem_region(&dev->dev, dev->resource.start, + SZ_4K, "LM registers")) return -EBUSY; - impd1 = kzalloc(sizeof(struct impd1_module), GFP_KERNEL); - if (!impd1) { - ret = -ENOMEM; - goto release_lm; - } + impd1 = devm_kzalloc(&dev->dev, sizeof(struct impd1_module), + GFP_KERNEL); + if (!impd1) + return -ENOMEM; + + impd1->base = devm_ioremap(&dev->dev, dev->resource.start, SZ_4K); + if (!impd1->base) + return -ENOMEM; - impd1->base = ioremap(dev->resource.start, SZ_4K); - if (!impd1->base) { - ret = -ENOMEM; - goto free_impd1; - } + integrator_impd1_clk_init(impd1->base, dev->id); - lm_set_drvdata(dev, impd1); + if (!devm_request_mem_region(&dev->dev, + dev->resource.start + 0x03000000, + SZ_4K, "VIC")) + return -EBUSY; - printk("IM-PD1 found at 0x%08lx\n", - (unsigned long)dev->resource.start); + impd1->vic_base = devm_ioremap(&dev->dev, + dev->resource.start + 0x03000000, + SZ_4K); + if (!impd1->vic_base) + return -ENOMEM; - integrator_impd1_clk_init(impd1->base, dev->id); + irq_base = vic_init_cascaded(impd1->vic_base, dev->irq, + IMPD1_VALID_IRQS, 0); + + lm_set_drvdata(dev, impd1); + + dev_info(&dev->dev, "IM-PD1 found at 0x%08lx\n", + (unsigned long)dev->resource.start); for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) { struct impd1_device *idev = impd1_devs + i; struct amba_device *d; unsigned long pc_base; char devname[32]; + int irq1 = idev->irq[0]; + int irq2 = idev->irq[1]; + + /* Translate IRQs to IM-PD1 local numberspace */ + if (irq1) + irq1 += irq_base; + if (irq2) + irq2 += irq_base; pc_base = dev->resource.start + idev->offset; snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12); d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K, - dev->irq, dev->irq, + irq1, irq2, idev->platform_data, idev->id, &dev->resource); if (IS_ERR(d)) { @@ -353,14 +378,6 @@ } return 0; - - free_impd1: - if (impd1 && impd1->base) - iounmap(impd1->base); - kfree(impd1); - release_lm: - release_mem_region(dev->resource.start, SZ_4K); - return ret; } static int impd1_remove_one(struct device *dev, void *data) @@ -371,16 +388,10 @@ static void impd1_remove(struct lm_device *dev) { - struct impd1_module *impd1 = lm_get_drvdata(dev); - device_for_each_child(&dev->dev, NULL, impd1_remove_one); integrator_impd1_clk_exit(dev->id); lm_set_drvdata(dev, NULL); - - iounmap(impd1->base); - kfree(impd1); - release_mem_region(dev->resource.start, SZ_4K); } static struct lm_driver impd1_driver = { diff -Nur linux-3.14.1/arch/arm/mach-integrator/impd1.h linux-3.15-rc1.orig/arch/arm/mach-integrator/impd1.h --- linux-3.14.1/arch/arm/mach-integrator/impd1.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/impd1.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,14 @@ +#define IMPD1_LEDS 0x0c +#define IMPD1_INT 0x10 +#define IMPD1_SW 0x14 +#define IMPD1_CTRL 0x18 + +#define IMPD1_CTRL_DISP_LCD (0 << 0) +#define IMPD1_CTRL_DISP_VGA (1 << 0) +#define IMPD1_CTRL_DISP_LCD1 (2 << 0) +#define IMPD1_CTRL_DISP_ENABLE (1 << 2) +#define IMPD1_CTRL_DISP_MASK (7 << 0) + +struct device; + +void impd1_tweak_control(struct device *dev, u32 mask, u32 val); diff -Nur linux-3.14.1/arch/arm/mach-integrator/include/mach/hardware.h linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/hardware.h --- linux-3.14.1/arch/arm/mach-integrator/include/mach/hardware.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/hardware.h - * - * This file contains the hardware definitions of the Integrator. - * - * Copyright (C) 1999 ARM Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define IO_BASE 0xF0000000 // VA of IO -#define IO_SIZE 0x0B000000 // How much? -#define IO_START INTEGRATOR_HDR_BASE // PA of IO - -/* macro to get at IO space when running virtually */ -#ifdef CONFIG_MMU -#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) -#else -#define IO_ADDRESS(x) (x) -#endif - -#define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) - -#endif - diff -Nur linux-3.14.1/arch/arm/mach-integrator/include/mach/impd1.h linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/impd1.h --- linux-3.14.1/arch/arm/mach-integrator/include/mach/impd1.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/impd1.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,18 +0,0 @@ -#define IMPD1_OSC1 0x00 -#define IMPD1_OSC2 0x04 -#define IMPD1_LOCK 0x08 -#define IMPD1_LEDS 0x0c -#define IMPD1_INT 0x10 -#define IMPD1_SW 0x14 -#define IMPD1_CTRL 0x18 - -#define IMPD1_CTRL_DISP_LCD (0 << 0) -#define IMPD1_CTRL_DISP_VGA (1 << 0) -#define IMPD1_CTRL_DISP_LCD1 (2 << 0) -#define IMPD1_CTRL_DISP_ENABLE (1 << 2) -#define IMPD1_CTRL_DISP_MASK (7 << 0) - -struct device; - -void impd1_tweak_control(struct device *dev, u32 mask, u32 val); - diff -Nur linux-3.14.1/arch/arm/mach-integrator/include/mach/lm.h linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/lm.h --- linux-3.14.1/arch/arm/mach-integrator/include/mach/lm.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/lm.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,23 +0,0 @@ - -struct lm_device { - struct device dev; - struct resource resource; - unsigned int irq; - unsigned int id; -}; - -struct lm_driver { - struct device_driver drv; - int (*probe)(struct lm_device *); - void (*remove)(struct lm_device *); - int (*suspend)(struct lm_device *, pm_message_t); - int (*resume)(struct lm_device *); -}; - -int lm_driver_register(struct lm_driver *drv); -void lm_driver_unregister(struct lm_driver *drv); - -int lm_device_register(struct lm_device *dev); - -#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev) -#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d) diff -Nur linux-3.14.1/arch/arm/mach-integrator/include/mach/platform.h linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/platform.h --- linux-3.14.1/arch/arm/mach-integrator/include/mach/platform.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,382 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/************************************************************************** - * * Copyright © ARM Limited 1998. All rights reserved. - * ***********************************************************************/ -/* ************************************************************************ - * - * Integrator address map - * - * ***********************************************************************/ - -#ifndef __address_h -#define __address_h 1 - -/* ======================================================================== - * Integrator definitions - * ======================================================================== - * ------------------------------------------------------------------------ - * Memory definitions - * ------------------------------------------------------------------------ - * Integrator memory map - * - */ -#define INTEGRATOR_BOOT_ROM_LO 0x00000000 -#define INTEGRATOR_BOOT_ROM_HI 0x20000000 -#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ -#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K - -/* - * New Core Modules have different amounts of SSRAM, the amount of SSRAM - * fitted can be found in HDR_STAT. - * - * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to - * the minimum amount of SSRAM fitted on any core module. - * - * New Core Modules also alias the SSRAM. - * - */ -#define INTEGRATOR_SSRAM_BASE 0x00000000 -#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 -#define INTEGRATOR_SSRAM_SIZE SZ_256K - -#define INTEGRATOR_FLASH_BASE 0x24000000 -#define INTEGRATOR_FLASH_SIZE SZ_32M - -#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 -#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K - -/* - * SDRAM is a SIMM therefore the size is not known. - * - */ -#define INTEGRATOR_SDRAM_BASE 0x00040000 - -#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 -#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 -#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 -#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 - -/* - * Logic expansion modules - * - */ -#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 -#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 -#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 -#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 -#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 - -/* ------------------------------------------------------------------------ - * Integrator header card registers - * ------------------------------------------------------------------------ - * - */ -#define INTEGRATOR_HDR_ID_OFFSET 0x00 -#define INTEGRATOR_HDR_PROC_OFFSET 0x04 -#define INTEGRATOR_HDR_OSC_OFFSET 0x08 -#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C -#define INTEGRATOR_HDR_STAT_OFFSET 0x10 -#define INTEGRATOR_HDR_LOCK_OFFSET 0x14 -#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 -#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ -#define INTEGRATOR_HDR_IC_OFFSET 0x40 -#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 -#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 - -#define INTEGRATOR_HDR_BASE 0x10000000 -#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) -#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) -#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) -#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) -#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) -#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) -#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) -#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) -#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) -#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) -#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) - -#define INTEGRATOR_HDR_CTRL_LED 0x01 -#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 -#define INTEGRATOR_HDR_CTRL_REMAP 0x04 -#define INTEGRATOR_HDR_CTRL_RESET 0x08 -#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 -#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 -#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 -#define INTEGRATOR_HDR_CTRL_SYNC 0x80 - -#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 -#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 -#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C -#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 -#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 -#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B -#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 -#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 -#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A -#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F -#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 -#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 -#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E -#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 -#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 -#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D -#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 -#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 -#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C -#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 -#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 -#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B -#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 -#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 -#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A -#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F -#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 -#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 -#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E -#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 -#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 -#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF - -#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 -#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 -#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 -#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 -#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 -#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 -#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 -#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 -#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 -#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 -#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 - -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 -#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 - -#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) - - -/* ------------------------------------------------------------------------ - * Integrator system registers - * ------------------------------------------------------------------------ - * - */ - -/* - * System Controller - * - */ -#define INTEGRATOR_SC_ID_OFFSET 0x00 -#define INTEGRATOR_SC_OSC_OFFSET 0x04 -#define INTEGRATOR_SC_CTRLS_OFFSET 0x08 -#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C -#define INTEGRATOR_SC_DEC_OFFSET 0x10 -#define INTEGRATOR_SC_ARB_OFFSET 0x14 -#define INTEGRATOR_SC_LOCK_OFFSET 0x1C - -#define INTEGRATOR_SC_BASE 0x11000000 -#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) -#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) -#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) -#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) -#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) -#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) -#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) -#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) - -#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 -#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 -#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 -#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C -#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C -#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF - -#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 -#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 -#define INTEGRATOR_SC_OSC_PCI_MASK 0x100 - -#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) -#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) -#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) -#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) -#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) -#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) -#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) - -/* - * External Bus Interface - * - */ -#define INTEGRATOR_EBI_BASE 0x12000000 - -#define INTEGRATOR_EBI_CSR0_OFFSET 0x00 -#define INTEGRATOR_EBI_CSR1_OFFSET 0x04 -#define INTEGRATOR_EBI_CSR2_OFFSET 0x08 -#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C -#define INTEGRATOR_EBI_LOCK_OFFSET 0x20 - -#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) -#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) -#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) -#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) -#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) - -#define INTEGRATOR_EBI_8_BIT 0x00 -#define INTEGRATOR_EBI_16_BIT 0x01 -#define INTEGRATOR_EBI_32_BIT 0x02 -#define INTEGRATOR_EBI_WRITE_ENABLE 0x04 -#define INTEGRATOR_EBI_SYNC 0x08 -#define INTEGRATOR_EBI_WS_2 0x00 -#define INTEGRATOR_EBI_WS_3 0x10 -#define INTEGRATOR_EBI_WS_4 0x20 -#define INTEGRATOR_EBI_WS_5 0x30 -#define INTEGRATOR_EBI_WS_6 0x40 -#define INTEGRATOR_EBI_WS_7 0x50 -#define INTEGRATOR_EBI_WS_8 0x60 -#define INTEGRATOR_EBI_WS_9 0x70 -#define INTEGRATOR_EBI_WS_10 0x80 -#define INTEGRATOR_EBI_WS_11 0x90 -#define INTEGRATOR_EBI_WS_12 0xA0 -#define INTEGRATOR_EBI_WS_13 0xB0 -#define INTEGRATOR_EBI_WS_14 0xC0 -#define INTEGRATOR_EBI_WS_15 0xD0 -#define INTEGRATOR_EBI_WS_16 0xE0 -#define INTEGRATOR_EBI_WS_17 0xF0 - - -#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ -#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ -#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ -#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ -#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ -#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ -#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ - -/* - * LED's & Switches - * - */ -#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 -#define INTEGRATOR_DBG_LEDS_OFFSET 0x04 -#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 - -#define INTEGRATOR_DBG_BASE 0x1A000000 -#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) -#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) -#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) - -#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ - -#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ -#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ -#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ -#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ -#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ -#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ - -/* ------------------------------------------------------------------------ - * KMI keyboard/mouse definitions - * ------------------------------------------------------------------------ - */ -/* PS2 Keyboard interface */ -#define KMI0_BASE INTEGRATOR_KBD_BASE - -/* PS2 Mouse interface */ -#define KMI1_BASE INTEGRATOR_MOUSE_BASE - -/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ - -/* ------------------------------------------------------------------------ - * Integrator Interrupt Controllers - * ------------------------------------------------------------------------ - * - * Offsets from interrupt controller base - * - * System Controller interrupt controller base is - * - * INTEGRATOR_IC_BASE + (header_number << 6) - * - * Core Module interrupt controller base is - * - * INTEGRATOR_HDR_IC - * - */ -#define IRQ_STATUS 0 -#define IRQ_RAW_STATUS 0x04 -#define IRQ_ENABLE 0x08 -#define IRQ_ENABLE_SET 0x08 -#define IRQ_ENABLE_CLEAR 0x0C - -#define INT_SOFT_SET 0x10 -#define INT_SOFT_CLEAR 0x14 - -#define FIQ_STATUS 0x20 -#define FIQ_RAW_STATUS 0x24 -#define FIQ_ENABLE 0x28 -#define FIQ_ENABLE_SET 0x28 -#define FIQ_ENABLE_CLEAR 0x2C - - -/* ------------------------------------------------------------------------ - * Interrupts - * ------------------------------------------------------------------------ - * - * - * Each Core Module has two interrupts controllers, one on the core module - * itself and one in the system controller on the motherboard. The - * READ_INT macro in target.s reads both interrupt controllers and returns - * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller - * and bits 24 to 31 are from the core module. - * - * The following definitions relate to the bitmask returned by READ_INT. - * - */ - -/* ------------------------------------------------------------------------ - * LED's - * ------------------------------------------------------------------------ - * - */ -#define GREEN_LED 0x01 -#define YELLOW_LED 0x02 -#define RED_LED 0x04 -#define GREEN_LED_2 0x08 -#define ALL_LEDS 0x0F - -#define LED_BANK INTEGRATOR_DBG_LEDS - -/* - * Timer definitions - * - * Only use timer 1 & 2 - * (both run at 24MHz and will need the clock divider set to 16). - * - * Timer 0 runs at bus frequency - */ - -#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE -#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) -#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) - -#define INTEGRATOR_CSR_BASE 0x10000000 -#define INTEGRATOR_CSR_SIZE 0x10000000 - -#endif diff -Nur linux-3.14.1/arch/arm/mach-integrator/include/mach/timex.h linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/timex.h --- linux-3.14.1/arch/arm/mach-integrator/include/mach/timex.h 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/timex.h - * - * Integrator architecture timex specifications - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * ?? - */ -#define CLOCK_TICK_RATE (50000000 / 16) diff -Nur linux-3.14.1/arch/arm/mach-integrator/integrator_ap.c linux-3.15-rc1.orig/arch/arm/mach-integrator/integrator_ap.c --- linux-3.14.1/arch/arm/mach-integrator/integrator_ap.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/integrator_ap.c 2014-04-13 23:18:35.000000000 +0200 @@ -42,24 +42,23 @@ #include #include #include +#include -#include -#include #include #include #include /* HZ */ #include -#include - #include #include #include #include +#include "hardware.h" #include "cm.h" #include "common.h" #include "pci_v3.h" +#include "lm.h" /* Base address to the AP system controller */ void __iomem *ap_syscon_base; @@ -358,7 +357,7 @@ static struct irqaction integrator_timer_irq = { .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = integrator_timer_interrupt, .dev_id = &integrator_clockevent, }; @@ -402,10 +401,7 @@ struct clk *clk; unsigned long rate; - clk = clk_get_sys("ap_timer", NULL); - BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); - rate = clk_get_rate(clk); + of_clk_init(NULL); err = of_property_read_string(of_aliases, "arm,timer-primary", &path); @@ -415,6 +411,12 @@ base = of_iomap(node, 0); if (WARN_ON(!base)) return; + + clk = of_clk_get(node, 0); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + writel(0, base + TIMER_CTRL); integrator_clocksource_init(rate, base); @@ -427,6 +429,12 @@ if (WARN_ON(!base)) return; irq = irq_of_parse_and_map(node, 0); + + clk = of_clk_get(node, 0); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + writel(0, base + TIMER_CTRL); integrator_clockevent_init(rate, base, irq); } @@ -440,7 +448,6 @@ { cm_init(); of_irq_init(fpga_irq_of_match); - integrator_clk_init(false); } /* For the Device Tree, add in the UART callbacks as AUXDATA */ diff -Nur linux-3.14.1/arch/arm/mach-integrator/integrator_cp.c linux-3.15-rc1.orig/arch/arm/mach-integrator/integrator_cp.c --- linux-3.14.1/arch/arm/mach-integrator/integrator_cp.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/integrator_cp.c 2014-04-13 23:18:35.000000000 +0200 @@ -23,31 +23,22 @@ #include #include #include -#include #include #include #include #include +#include -#include -#include #include #include -#include -#include - -#include - #include #include #include #include -#include - #include -#include +#include "hardware.h" #include "cm.h" #include "common.h" @@ -234,11 +225,14 @@ #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) +static u64 notrace intcp_read_sched_clock(void) +{ + return readl(REFCOUNTER); +} + static void __init intcp_init_early(void) { -#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK - versatile_sched_clock_init(REFCOUNTER, 24000000); -#endif + sched_clock_register(intcp_read_sched_clock, 32, 24000000); } static const struct of_device_id fpga_irq_of_match[] __initconst = { @@ -250,7 +244,6 @@ { cm_init(); of_irq_init(fpga_irq_of_match); - integrator_clk_init(true); } /* diff -Nur linux-3.14.1/arch/arm/mach-integrator/Kconfig linux-3.15-rc1.orig/arch/arm/mach-integrator/Kconfig --- linux-3.14.1/arch/arm/mach-integrator/Kconfig 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/Kconfig 2014-04-13 23:18:35.000000000 +0200 @@ -6,8 +6,8 @@ bool "Support Integrator/AP and Integrator/PP2 platforms" select CLKSRC_MMIO select MIGHT_HAVE_PCI - select SERIAL_AMBA_PL010 - select SERIAL_AMBA_PL010_CONSOLE + select SERIAL_AMBA_PL010 if TTY + select SERIAL_AMBA_PL010_CONSOLE if TTY select SOC_BUS help Include support for the ARM(R) Integrator/AP and @@ -18,8 +18,8 @@ select ARCH_CINTEGRATOR select ARM_TIMER_SP804 select PLAT_VERSATILE_CLCD - select SERIAL_AMBA_PL011 - select SERIAL_AMBA_PL011_CONSOLE + select SERIAL_AMBA_PL011 if TTY + select SERIAL_AMBA_PL011_CONSOLE if TTY select SOC_BUS help Include support for the ARM(R) Integrator CP platform. @@ -30,6 +30,9 @@ config INTEGRATOR_IMPD1 tristate "Include support for Integrator/IM-PD1" depends on ARCH_INTEGRATOR_AP + select ARCH_REQUIRE_GPIOLIB + select ARM_VIC + select GPIO_PL061 if GPIOLIB help The IM-PD1 is an add-on logic module for the Integrator which allows ARM(R) Ltd PrimeCells to be developed and evaluated. diff -Nur linux-3.14.1/arch/arm/mach-integrator/leds.c linux-3.15-rc1.orig/arch/arm/mach-integrator/leds.c --- linux-3.14.1/arch/arm/mach-integrator/leds.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/leds.c 2014-04-13 23:18:35.000000000 +0200 @@ -11,9 +11,7 @@ #include #include -#include -#include - +#include "hardware.h" #include "cm.h" #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) diff -Nur linux-3.14.1/arch/arm/mach-integrator/lm.c linux-3.15-rc1.orig/arch/arm/mach-integrator/lm.c --- linux-3.14.1/arch/arm/mach-integrator/lm.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/lm.c 2014-04-13 23:18:35.000000000 +0200 @@ -12,7 +12,7 @@ #include #include -#include +#include "lm.h" #define to_lm_device(d) container_of(d, struct lm_device, dev) #define to_lm_driver(d) container_of(d, struct lm_driver, drv) diff -Nur linux-3.14.1/arch/arm/mach-integrator/lm.h linux-3.15-rc1.orig/arch/arm/mach-integrator/lm.h --- linux-3.14.1/arch/arm/mach-integrator/lm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/lm.h 2014-04-13 23:18:35.000000000 +0200 @@ -0,0 +1,23 @@ + +struct lm_device { + struct device dev; + struct resource resource; + unsigned int irq; + unsigned int id; +}; + +struct lm_driver { + struct device_driver drv; + int (*probe)(struct lm_device *); + void (*remove)(struct lm_device *); + int (*suspend)(struct lm_device *, pm_message_t); + int (*resume)(struct lm_device *); +}; + +int lm_driver_register(struct lm_driver *drv); +void lm_driver_unregister(struct lm_driver *drv); + +int lm_device_register(struct lm_device *dev); + +#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev) +#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d) diff -Nur linux-3.14.1/arch/arm/mach-integrator/pci_v3.c linux-3.15-rc1.orig/arch/arm/mach-integrator/pci_v3.c --- linux-3.14.1/arch/arm/mach-integrator/pci_v3.c 2014-04-14 15:50:10.000000000 +0200 +++ linux-3.15-rc1.orig/arch/arm/mach-integrator/pci_v3.c 2014-04-13 23:18:35.000000000 +0200 @@ -34,15 +34,13 @@ #include #include