diff -Nur linux-6.18.18.orig/arch/microblaze/boot/dts/mimasa7_mini.dts linux-6.18.18/arch/microblaze/boot/dts/mimasa7_mini.dts
--- linux-6.18.18.orig/arch/microblaze/boot/dts/mimasa7_mini.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-6.18.18/arch/microblaze/boot/dts/mimasa7_mini.dts	2026-03-25 06:33:23.647668507 +0100
@@ -0,0 +1,244 @@
+/*
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: XSCT 2022.1
+ * Today is: Wed Mar 25 04:08:33 2026
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "xlnx,microblaze";
+	model = "Xilinx MicroBlaze";
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+	aliases {
+		serial0 = &axi_uartlite_0;
+		spi0 = &axi_quad_spi_0;
+	};
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#cpus = <1>;
+		#size-cells = <0>;
+		microblaze_0: cpu@0 {
+			bus-handle = <&amba_pl>;
+			clock-frequency = <100000000>;
+			clocks = <&clk_cpu>;
+			compatible = "xlnx,microblaze-11.0";
+			d-cache-baseaddr = <0x80000000>;
+			d-cache-highaddr = <0x8fffffff>;
+			d-cache-line-size = <0x10>;
+			d-cache-size = <0x4000>;
+			device_type = "cpu";
+			i-cache-baseaddr = <0x80000000>;
+			i-cache-highaddr = <0x8fffffff>;
+			i-cache-line-size = <0x20>;
+			i-cache-size = <0x4000>;
+			interrupt-handle = <&microblaze_0_axi_intc>;
+			model = "microblaze,11.0";
+			reg = <0>;
+			timebase-frequency = <100000000>;
+			xlnx,addr-size = <0x20>;
+			xlnx,addr-tag-bits = <0xe>;
+			xlnx,allow-dcache-wr = <0x1>;
+			xlnx,allow-icache-wr = <0x1>;
+			xlnx,area-optimized = <0x0>;
+			xlnx,async-interrupt = <0x1>;
+			xlnx,async-wakeup = <0x3>;
+			xlnx,avoid-primitives = <0x0>;
+			xlnx,base-vectors = <0x00000000 0x00000000>;
+			xlnx,branch-target-cache-size = <0x0>;
+			xlnx,cache-byte-size = <0x4000>;
+			xlnx,d-axi = <0x1>;
+			xlnx,d-lmb = <0x1>;
+			xlnx,d-lmb-mon = <0x0>;
+			xlnx,d-lmb-protocol = <0x0>;
+			xlnx,daddr-size = <0x20>;
+			xlnx,data-size = <0x20>;
+			xlnx,dc-axi-mon = <0x0>;
+			xlnx,dcache-addr-tag = <0xe>;
+			xlnx,dcache-always-used = <0x0>;
+			xlnx,dcache-byte-size = <0x4000>;
+			xlnx,dcache-data-width = <0x0>;
+			xlnx,dcache-force-tag-lutram = <0x0>;
+			xlnx,dcache-line-len = <0x4>;
+			xlnx,dcache-use-writeback = <0x0>;
+			xlnx,dcache-victims = <0x8>;
+			xlnx,debug-counter-width = <0x20>;
+			xlnx,debug-enabled = <0x1>;
+			xlnx,debug-event-counters = <0x5>;
+			xlnx,debug-external-trace = <0x0>;
+			xlnx,debug-interface = <0x0>;
+			xlnx,debug-latency-counters = <0x1>;
+			xlnx,debug-profile-size = <0x0>;
+			xlnx,debug-trace-async-reset = <0x0>;
+			xlnx,debug-trace-size = <0x2000>;
+			xlnx,div-zero-exception = <0x1>;
+			xlnx,dp-axi-mon = <0x0>;
+			xlnx,dynamic-bus-sizing = <0x0>;
+			xlnx,ecc-use-ce-exception = <0x0>;
+			xlnx,edge-is-positive = <0x1>;
+			xlnx,enable-discrete-ports = <0x0>;
+			xlnx,endianness = <0x1>;
+			xlnx,fault-tolerant = <0x0>;
+			xlnx,fpu-exception = <0x0>;
+			xlnx,freq = <0x5f5e100>;
+			xlnx,fsl-exception = <0x0>;
+			xlnx,fsl-links = <0x0>;
+			xlnx,i-axi = <0x0>;
+			xlnx,i-lmb = <0x1>;
+			xlnx,i-lmb-mon = <0x0>;
+			xlnx,i-lmb-protocol = <0x0>;
+			xlnx,iaddr-size = <0x20>;
+			xlnx,ic-axi-mon = <0x0>;
+			xlnx,icache-always-used = <0x1>;
+			xlnx,icache-data-width = <0x0>;
+			xlnx,icache-force-tag-lutram = <0x0>;
+			xlnx,icache-line-len = <0x8>;
+			xlnx,icache-streams = <0x1>;
+			xlnx,icache-victims = <0x8>;
+			xlnx,ill-opcode-exception = <0x1>;
+			xlnx,imprecise-exceptions = <0x0>;
+			xlnx,instr-size = <0x20>;
+			xlnx,interconnect = <0x2>;
+			xlnx,interrupt-is-edge = <0x0>;
+			xlnx,interrupt-mon = <0x0>;
+			xlnx,ip-axi-mon = <0x0>;
+			xlnx,lmb-data-size = <0x20>;
+			xlnx,lockstep-master = <0x0>;
+			xlnx,lockstep-select = <0x0>;
+			xlnx,lockstep-slave = <0x0>;
+			xlnx,mmu-dtlb-size = <0x4>;
+			xlnx,mmu-itlb-size = <0x2>;
+			xlnx,mmu-privileged-instr = <0x0>;
+			xlnx,mmu-tlb-access = <0x3>;
+			xlnx,mmu-zones = <0x2>;
+			xlnx,num-sync-ff-clk = <0x2>;
+			xlnx,num-sync-ff-clk-debug = <0x2>;
+			xlnx,num-sync-ff-clk-irq = <0x1>;
+			xlnx,num-sync-ff-dbg-clk = <0x1>;
+			xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
+			xlnx,number-of-pc-brk = <0x1>;
+			xlnx,number-of-rd-addr-brk = <0x0>;
+			xlnx,number-of-wr-addr-brk = <0x0>;
+			xlnx,opcode-0x0-illegal = <0x1>;
+			xlnx,optimization = <0x0>;
+			xlnx,pc-width = <0x20>;
+			xlnx,piaddr-size = <0x20>;
+			xlnx,pvr = <0x2>;
+			xlnx,pvr-user1 = <0x00>;
+			xlnx,pvr-user2 = <0x00000000>;
+			xlnx,reset-msr = <0x00000000>;
+			xlnx,reset-msr-bip = <0x0>;
+			xlnx,reset-msr-dce = <0x0>;
+			xlnx,reset-msr-ee = <0x0>;
+			xlnx,reset-msr-eip = <0x0>;
+			xlnx,reset-msr-ice = <0x0>;
+			xlnx,reset-msr-ie = <0x0>;
+			xlnx,sco = <0x0>;
+			xlnx,temporal-depth = <0x0>;
+			xlnx,trace = <0x0>;
+			xlnx,unaligned-exceptions = <0x1>;
+			xlnx,use-barrel = <0x1>;
+			xlnx,use-branch-target-cache = <0x0>;
+			xlnx,use-config-reset = <0x0>;
+			xlnx,use-dcache = <0x1>;
+			xlnx,use-div = <0x1>;
+			xlnx,use-ext-brk = <0x0>;
+			xlnx,use-ext-nm-brk = <0x0>;
+			xlnx,use-extended-fsl-instr = <0x0>;
+			xlnx,use-fpu = <0x0>;
+			xlnx,use-hw-mul = <0x2>;
+			xlnx,use-icache = <0x1>;
+			xlnx,use-interrupt = <0x2>;
+			xlnx,use-mmu = <0x3>;
+			xlnx,use-msr-instr = <0x1>;
+			xlnx,use-non-secure = <0x0>;
+			xlnx,use-pcmp-instr = <0x1>;
+			xlnx,use-reorder-instr = <0x1>;
+			xlnx,use-stack-protection = <0x0>;
+		};
+	};
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clk_cpu: clk_cpu@0 {
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "clk_cpu";
+			compatible = "fixed-clock";
+			reg = <0>;
+		};
+		clk_bus_0: clk_bus_0@1 {
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "clk_bus_0";
+			compatible = "fixed-clock";
+			reg = <1>;
+		};
+	};
+	amba_pl: amba_pl {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges ;
+		axi_quad_spi_0: axi_quad_spi@44a00000 {
+			bits-per-word = <8>;
+			compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
+			fifo-size = <0>;
+			num-cs = <0x1>;
+			reg = <0x44a00000 0x10000>;
+			xlnx,num-ss-bits = <0x1>;
+			xlnx,spi-mode = <0>;
+			xlnx,startup-block ;
+		};
+		axi_timer_0: timer@41c00000 {
+			clock-frequency = <100000000>;
+			clocks = <&clk_bus_0>;
+			compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a";
+			interrupt-names = "interrupt";
+			interrupt-parent = <&microblaze_0_axi_intc>;
+			interrupts = <1 2>;
+			reg = <0x41c00000 0x10000>;
+			xlnx,count-width = <0x20>;
+			xlnx,gen0-assert = <0x1>;
+			xlnx,gen1-assert = <0x1>;
+			xlnx,one-timer-only = <0x0>;
+			xlnx,trig0-assert = <0x1>;
+			xlnx,trig1-assert = <0x1>;
+		};
+		axi_uartlite_0: serial@40600000 {
+			clock-frequency = <100000000>;
+			clocks = <&clk_bus_0>;
+			compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a";
+			current-speed = <115200>;
+			device_type = "serial";
+			interrupt-names = "interrupt";
+			interrupt-parent = <&microblaze_0_axi_intc>;
+			interrupts = <0 0>;
+			port-number = <0>;
+			reg = <0x40600000 0x10000>;
+			xlnx,baudrate = <0x1c200>;
+			xlnx,data-bits = <0x8>;
+			xlnx,odd-parity = <0x0>;
+			xlnx,s-axi-aclk-freq-hz-d = "100.0";
+			xlnx,use-parity = <0x0>;
+		};
+		microblaze_0_axi_intc: interrupt-controller@41200000 {
+			#interrupt-cells = <2>;
+			compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
+			interrupt-controller ;
+			reg = <0x41200000 0x10000>;
+			xlnx,kind-of-intr = <0x1>;
+			xlnx,num-intr-inputs = <0x2>;
+		};
+	};
+};