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j2.patch

j2.patch 50 KB
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  1. diff -Nur binutils-2.42.orig/bfd/archures.c binutils-2.42/bfd/archures.c
    2. 

  2. --- binutils-2.42.orig/bfd/archures.c	2024-01-29 01:00:00.000000000 +0100
    3. 

  3. +++ binutils-2.42/bfd/archures.c	2024-02-22 16:50:03.657904349 +0100
    4. 

  4. @@ -284,10 +284,12 @@
    5. 

  5.  .#define bfd_mach_sh_dsp			0x2d
    6. 

  6.  .#define bfd_mach_sh2a				0x2a
    7. 

  7.  .#define bfd_mach_sh2a_nofpu			0x2b
    8. 

  8. +.#define bfd_mach_shj2       			0x2c
    9. 

  9.  .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
    10. 

  10.  .#define bfd_mach_sh2a_nofpu_or_sh3_nommu	0x2a2
    11. 

  11.  .#define bfd_mach_sh2a_or_sh4			0x2a3
    12. 

  12.  .#define bfd_mach_sh2a_or_sh3e			0x2a4
    13. 

  13. +.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
    14. 

  14.  .#define bfd_mach_sh2e				0x2e
    15. 

  15.  .#define bfd_mach_sh3				0x30
    16. 

  16.  .#define bfd_mach_sh3_nommu			0x31
    17. 

  17. diff -Nur binutils-2.42.orig/bfd/bfd-in2.h binutils-2.42/bfd/bfd-in2.h
    18. 

  18. --- binutils-2.42.orig/bfd/bfd-in2.h	2024-01-29 01:00:00.000000000 +0100
    19. 

  19. +++ binutils-2.42/bfd/bfd-in2.h	2024-02-22 16:50:03.661904381 +0100
    20. 

  20. @@ -1540,10 +1540,12 @@
    21. 

  21.  #define bfd_mach_sh_dsp                        0x2d
    22. 

  22.  #define bfd_mach_sh2a                          0x2a
    23. 

  23.  #define bfd_mach_sh2a_nofpu                    0x2b
    24. 

  24. +#define bfd_mach_shj2       		       0x2c
    25. 

  25.  #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
    26. 

  26.  #define bfd_mach_sh2a_nofpu_or_sh3_nommu       0x2a2
    27. 

  27.  #define bfd_mach_sh2a_or_sh4                   0x2a3
    28. 

  28.  #define bfd_mach_sh2a_or_sh3e                  0x2a4
    29. 

  29. +#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
    30. 

  30.  #define bfd_mach_sh2e                          0x2e
    31. 

  31.  #define bfd_mach_sh3                           0x30
    32. 

  32.  #define bfd_mach_sh3_nommu                     0x31
    33. 

  33. diff -Nur binutils-2.42.orig/bfd/cpu-sh.c binutils-2.42/bfd/cpu-sh.c
    34. 

  34. --- binutils-2.42.orig/bfd/cpu-sh.c	2024-01-29 01:00:00.000000000 +0100
    35. 

  35. +++ binutils-2.42/bfd/cpu-sh.c	2024-02-22 16:50:03.661904381 +0100
    36. 

  36. @@ -63,7 +63,9 @@
    37. 

  37.    N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", false, arch_info_struct + 16),
    38. 

  38.    N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", false, arch_info_struct + 17),
    39. 

  39.    N (bfd_mach_sh2a_or_sh4,  "sh2a-or-sh4",  false, arch_info_struct + 18),
    40. 

  40. -  N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, NULL)
    41. 

  41. +  N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, arch_info_struct + 19),
    42. 

  42. +  N (bfd_mach_shj2,         "j2",         false, arch_info_struct + 20),
    43. 

  43. +  N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-nofpu-or-sh3-nommu-or-j2-nofpu",       false, NULL)
    44. 

  44.  };
    45. 

  45.  
    46. 

  46.  const bfd_arch_info_type bfd_sh_arch =
    47. 

  47. @@ -99,6 +101,8 @@
    48. 

  48.    { bfd_mach_sh4_nofpu,	      arch_sh4_nofpu,	    arch_sh4_nofpu_up },
    49. 

  49.    { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
    50. 

  50.    { bfd_mach_sh4a_nofpu,      arch_sh4a_nofpu,	    arch_sh4a_nofpu_up },
    51. 

  51. +  { bfd_mach_shj2,            arch_shj2,            arch_shj2_up },
    52. 

  52. +  { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
    53. 

  53.    { 0, 0, 0 }	/* Terminator.  */
    54. 

  54.  };
    55. 

  55.  
    56. 

  56. diff -Nur binutils-2.42.orig/binutils/readelf.c binutils-2.42/binutils/readelf.c
    57. 

  57. --- binutils-2.42.orig/binutils/readelf.c	2024-01-29 01:00:00.000000000 +0100
    58. 

  58. +++ binutils-2.42/binutils/readelf.c	2024-02-22 16:53:19.799614987 +0100
    59. 

  59. @@ -4326,6 +4326,12 @@
    60. 

  60.      case EF_SH2A_SH3E:
    61. 

  61.        out = stpcpy (out, ", sh2a-or-sh3e");
    62. 

  62.        break;
    63. 

  63. +    case EF_SHJ2:
    64. 

  64. +      out = stpcpy (out, ", j2");
    65. 

  65. +      break;
    66. 

  66. +    case EF_SH2A_SH3_SHJ2:
    67. 

  67. +      out = stpcpy (out, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu");
    68. 

  68. +      break;
    69. 

  69.      default:
    70. 

  70.        out = stpcpy (out, _(", unknown ISA"));
    71. 

  71.        break;
    72. 

  72. diff -Nur binutils-2.42.orig/gas/config/tc-sh.c binutils-2.42/gas/config/tc-sh.c
    73. 

  73. --- binutils-2.42.orig/gas/config/tc-sh.c	2024-01-29 01:00:00.000000000 +0100
    74. 

  74. +++ binutils-2.42/gas/config/tc-sh.c	2024-02-22 16:50:03.685904574 +0100
    75. 

  75. @@ -1251,6 +1251,8 @@
    76. 

  76.  	      if (*ptr == ',')
    77. 

  77.  		ptr++;
    78. 

  78.  	      get_operand (&ptr, operand + 2);
    79. 

  79. +	      if (strcmp (info->name,"cas") == 0)
    80. 

  80. +		operand[2].type = A_IND_0;
    81. 

  81.  	    }
    82. 

  82.  	}
    83. 

  83.      }
    84. 

  84. @@ -1775,7 +1777,10 @@
    85. 

  85.  		goto fail;
    86. 

  86.  	      reg_m = 4;
    87. 

  87.  	      break;
    88. 

  88. -
    89. 

  89. +	    case A_IND_0:
    90. 

  90. +	      if (user->reg != 0)
    91. 

  91. +		goto fail;
    92. 

  92. +	      break;
    93. 

  93.  	    default:
    94. 

  94.  	      printf (_("unhandled %d\n"), arg);
    95. 

  95.  	      goto fail;
    96. 

  96. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
    97. 

  97. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s	2024-01-29 01:00:00.000000000 +0100
    98. 

  98. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s	2024-02-22 16:50:03.685904574 +0100
    99. 

  99. @@ -12,8 +12,6 @@
    100. 

  100.  sh2a_nofpu_or_sh3_nommu:
    101. 

  101.  ! Instructions introduced into sh2a-nofpu-or-sh3-nommu
    102. 

  102.  	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
    103. 

  103. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    104. 

  104. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    105. 

  105.  
    106. 

  106.  ! Instructions inherited from ancestors: sh sh2
    107. 

  107.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    108. 

  108. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    109. 

  109. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s	2024-01-29 01:00:00.000000000 +0100
    110. 

  110. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s	2024-02-22 16:50:03.685904574 +0100
    111. 

  111. @@ -12,7 +12,7 @@
    112. 

  112.  sh2a_nofpu_or_sh4_nommu_nofpu:
    113. 

  113.  ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
    114. 

  114.  
    115. 

  115. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
    116. 

  116. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
    117. 

  117.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    118. 

  118.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    119. 

  119.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    120. 

  120. @@ -119,8 +119,8 @@
    121. 

  121.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    122. 

  122.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    123. 

  123.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    124. 

  124. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    125. 

  125. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    126. 

  126. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    127. 

  127. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    128. 

  128.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    129. 

  129.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    130. 

  130.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    131. 

  131. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
    132. 

  132. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s	2024-01-29 01:00:00.000000000 +0100
    133. 

  133. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu.s	2024-02-22 16:50:03.685904574 +0100
    134. 

  134. @@ -64,7 +64,7 @@
    135. 

  135.  	movu.b @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
    136. 

  136.  	movu.w @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
    137. 

  137.  
    138. 

  138. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
    139. 

  139. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
    140. 

  140.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    141. 

  141.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    142. 

  142.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    143. 

  143. @@ -171,8 +171,8 @@
    144. 

  144.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    145. 

  145.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    146. 

  146.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    147. 

  147. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    148. 

  148. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    149. 

  149. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    150. 

  150. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    151. 

  151.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    152. 

  152.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    153. 

  153.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    154. 

  154. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
    155. 

  155. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s	2024-01-29 01:00:00.000000000 +0100
    156. 

  156. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s	2024-02-22 16:50:03.689904606 +0100
    157. 

  157. @@ -13,7 +13,7 @@
    158. 

  158.  ! Instructions introduced into sh2a-or-sh3e
    159. 

  159.  	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
    160. 

  160.  
    161. 

  161. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
    162. 

  162. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
    163. 

  163.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    164. 

  164.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    165. 

  165.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    166. 

  166. @@ -124,8 +124,8 @@
    167. 

  167.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    168. 

  168.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    169. 

  169.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    170. 

  170. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    171. 

  171. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    172. 

  172. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    173. 

  173. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    174. 

  174.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    175. 

  175.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    176. 

  176.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    177. 

  177. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
    178. 

  178. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s	2024-01-29 01:00:00.000000000 +0100
    179. 

  179. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s	2024-02-22 16:50:03.689904606 +0100
    180. 

  180. @@ -39,7 +39,7 @@
    181. 

  181.  	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
    182. 

  182.  	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
    183. 

  183.  
    184. 

  184. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
    185. 

  185. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
    186. 

  186.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    187. 

  187.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    188. 

  188.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    189. 

  189. @@ -150,8 +150,8 @@
    190. 

  190.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    191. 

  191.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    192. 

  192.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    193. 

  193. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    194. 

  194. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    195. 

  195. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    196. 

  196. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    197. 

  197.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    198. 

  198.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    199. 

  199.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    200. 

  200. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a.s
    201. 

  201. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a.s	2024-01-29 01:00:00.000000000 +0100
    202. 

  202. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a.s	2024-02-22 16:50:03.689904606 +0100
    203. 

  203. @@ -16,7 +16,7 @@
    204. 

  204.  	fmov.s fr2,@(2048,r4)     ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */  {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
    205. 

  205.  	fmov.s @(2048,r5),fr1     ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */  {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
    206. 

  206.  
    207. 

  207. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
    208. 

  208. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
    209. 

  209.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    210. 

  210.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    211. 

  211.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    212. 

  212. @@ -140,8 +140,8 @@
    213. 

  213.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    214. 

  214.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    215. 

  215.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    216. 

  216. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    217. 

  217. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    218. 

  218. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    219. 

  219. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    220. 

  220.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    221. 

  221.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    222. 

  222.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    223. 

  223. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3-dsp.s
    224. 

  224. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s	2024-01-29 01:00:00.000000000 +0100
    225. 

  225. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3-dsp.s	2024-02-22 16:50:03.689904606 +0100
    226. 

  226. @@ -12,7 +12,7 @@
    227. 

  227.  sh3_dsp:
    228. 

  228.  ! Instructions introduced into sh3-dsp
    229. 

  229.  
    230. 

  230. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
    231. 

  231. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
    232. 

  232.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    233. 

  233.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    234. 

  234.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    235. 

  235. @@ -152,8 +152,8 @@
    236. 

  236.  	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
    237. 

  237.  	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
    238. 

  238.  	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
    239. 

  239. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    240. 

  240. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    241. 

  241. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    242. 

  242. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    243. 

  243.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    244. 

  244.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    245. 

  245.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    246. 

  246. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3e.s
    247. 

  247. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3e.s	2024-01-29 01:00:00.000000000 +0100
    248. 

  248. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3e.s	2024-02-22 16:50:03.689904606 +0100
    249. 

  249. @@ -12,7 +12,7 @@
    250. 

  250.  sh3e:
    251. 

  251.  ! Instructions introduced into sh3e
    252. 

  252.  
    253. 

  253. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
    254. 

  254. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
    255. 

  255.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    256. 

  256.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    257. 

  257.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    258. 

  258. @@ -132,8 +132,8 @@
    259. 

  259.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    260. 

  260.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    261. 

  261.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    262. 

  262. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    263. 

  263. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    264. 

  264. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    265. 

  265. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    266. 

  266.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    267. 

  267.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    268. 

  268.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    269. 

  269. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3-nommu.s
    270. 

  270. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s	2024-01-29 01:00:00.000000000 +0100
    271. 

  271. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3-nommu.s	2024-02-22 16:50:03.689904606 +0100
    272. 

  272. @@ -26,7 +26,7 @@
    273. 

  273.  	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
    274. 

  274.  	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
    275. 

  275.  
    276. 

  276. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
    277. 

  277. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
    278. 

  278.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    279. 

  279.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    280. 

  280.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    281. 

  281. @@ -133,8 +133,8 @@
    282. 

  282.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    283. 

  283.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    284. 

  284.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    285. 

  285. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    286. 

  286. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    287. 

  287. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    288. 

  288. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    289. 

  289.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    290. 

  290.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    291. 

  291.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    292. 

  292. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3.s
    293. 

  293. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3.s	2024-01-29 01:00:00.000000000 +0100
    294. 

  294. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3.s	2024-02-22 16:50:03.689904606 +0100
    295. 

  295. @@ -13,7 +13,7 @@
    296. 

  296.  ! Instructions introduced into sh3
    297. 

  297.  	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
    298. 

  298.  
    299. 

  299. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
    300. 

  300. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
    301. 

  301.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    302. 

  302.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    303. 

  303.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    304. 

  304. @@ -128,8 +128,8 @@
    305. 

  305.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    306. 

  306.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    307. 

  307.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    308. 

  308. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    309. 

  309. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    310. 

  310. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    311. 

  311. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    312. 

  312.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    313. 

  313.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    314. 

  314.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    315. 

  315. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4al-dsp.s
    316. 

  316. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s	2024-01-29 01:00:00.000000000 +0100
    317. 

  317. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4al-dsp.s	2024-02-22 16:50:03.689904606 +0100
    318. 

  318. @@ -48,7 +48,7 @@
    319. 

  319.  	dct pswap x1,m0           ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */  {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
    320. 

  320.  	dct pswap y0,m0           ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */  {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
    321. 

  321.  
    322. 

  322. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    323. 

  323. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    324. 

  324.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    325. 

  325.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    326. 

  326.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    327. 

  327. @@ -202,8 +202,8 @@
    328. 

  328.  	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
    329. 

  329.  	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
    330. 

  330.  	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
    331. 

  331. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    332. 

  332. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    333. 

  333. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    334. 

  334. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    335. 

  335.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    336. 

  336.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    337. 

  337.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    338. 

  338. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
    339. 

  339. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s	2024-01-29 01:00:00.000000000 +0100
    340. 

  340. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4a-nofpu.s	2024-02-22 16:50:03.693904638 +0100
    341. 

  341. @@ -19,7 +19,7 @@
    342. 

  342.  	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
    343. 

  343.  	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
    344. 

  344.  
    345. 

  345. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
    346. 

  346. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
    347. 

  347.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    348. 

  348.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    349. 

  349.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    350. 

  350. @@ -143,8 +143,8 @@
    351. 

  351.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    352. 

  352.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    353. 

  353.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    354. 

  354. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    355. 

  355. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    356. 

  356. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    357. 

  357. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    358. 

  358.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    359. 

  359.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    360. 

  360.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    361. 

  361. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4a.s
    362. 

  362. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a.s	2024-01-29 01:00:00.000000000 +0100
    363. 

  363. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4a.s	2024-02-22 16:50:03.693904638 +0100
    364. 

  364. @@ -13,7 +13,7 @@
    365. 

  365.  ! Instructions introduced into sh4a
    366. 

  366.  	fpchg                     ;!/* 1111011111111101 fpchg               */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
    367. 

  367.  
    368. 

  368. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    369. 

  369. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    370. 

  370.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    371. 

  371.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    372. 

  372.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    373. 

  373. @@ -147,8 +147,8 @@
    374. 

  374.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    375. 

  375.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    376. 

  376.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    377. 

  377. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    378. 

  378. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    379. 

  379. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    380. 

  380. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    381. 

  381.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    382. 

  382.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    383. 

  383.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    384. 

  384. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nofpu.s
    385. 

  385. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s	2024-01-29 01:00:00.000000000 +0100
    386. 

  386. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nofpu.s	2024-02-22 16:50:03.693904638 +0100
    387. 

  387. @@ -12,7 +12,7 @@
    388. 

  388.  sh4_nofpu:
    389. 

  389.  ! Instructions introduced into sh4-nofpu
    390. 

  390.  
    391. 

  391. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
    392. 

  392. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
    393. 

  393.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    394. 

  394.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    395. 

  395.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    396. 

  396. @@ -136,8 +136,8 @@
    397. 

  397.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    398. 

  398.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    399. 

  399.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    400. 

  400. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    401. 

  401. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    402. 

  402. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    403. 

  403. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    404. 

  404.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    405. 

  405.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    406. 

  406.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    407. 

  407. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
    408. 

  408. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s	2024-01-29 01:00:00.000000000 +0100
    409. 

  409. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s	2024-02-22 16:50:03.693904638 +0100
    410. 

  410. @@ -24,7 +24,7 @@
    411. 

  411.  	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
    412. 

  412.  	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
    413. 

  413.  
    414. 

  414. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
    415. 

  415. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
    416. 

  416.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    417. 

  417.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    418. 

  418.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    419. 

  419. @@ -139,8 +139,8 @@
    420. 

  420.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    421. 

  421.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    422. 

  422.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    423. 

  423. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    424. 

  424. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    425. 

  425. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    426. 

  426. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    427. 

  427.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    428. 

  428.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    429. 

  429.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    430. 

  430. diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4.s
    431. 

  431. --- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4.s	2024-01-29 01:00:00.000000000 +0100
    432. 

  432. +++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4.s	2024-02-22 16:50:03.693904638 +0100
    433. 

  433. @@ -17,7 +17,7 @@
    434. 

  434.  	fsrra fr1                 ;!/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
    435. 

  435.  	ftrv xmtrx,fv0            ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
    436. 

  436.  
    437. 

  437. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
    438. 

  438. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
    439. 

  439.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    440. 

  440.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    441. 

  441.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    442. 

  442. @@ -145,8 +145,8 @@
    443. 

  443.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    444. 

  444.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    445. 

  445.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    446. 

  446. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    447. 

  447. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    448. 

  448. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    449. 

  449. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    450. 

  450.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    451. 

  451.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    452. 

  452.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    453. 

  453. diff -Nur binutils-2.42.orig/include/elf/sh.h binutils-2.42/include/elf/sh.h
    454. 

  454. --- binutils-2.42.orig/include/elf/sh.h	2024-01-29 01:00:00.000000000 +0100
    455. 

  455. +++ binutils-2.42/include/elf/sh.h	2024-02-22 16:50:03.693904638 +0100
    456. 

  456. @@ -39,6 +39,7 @@
    457. 

  457.  #define EF_SH2E            11
    458. 

  458.  #define EF_SH4A		   12
    459. 

  459.  #define EF_SH2A            13
    460. 

  460. +#define EF_SHJ2            14
    461. 

  461.  
    462. 

  462.  #define EF_SH4_NOFPU	   16
    463. 

  463.  #define EF_SH4A_NOFPU	   17
    464. 

  464. @@ -50,6 +51,7 @@
    465. 

  465.  #define EF_SH2A_SH3_NOFPU  22
    466. 

  466.  #define EF_SH2A_SH4        23
    467. 

  467.  #define EF_SH2A_SH3E       24
    468. 

  468. +#define EF_SH2A_SH3_SHJ2   25
    469. 

  469.  
    470. 

  470.  /* This one can only mix in objects from other EF_SH5 objects.  */
    471. 

  471.  #define EF_SH5		  10
    472. 

  472. @@ -72,7 +74,8 @@
    473. 

  473.  /* EF_SH2E		*/ bfd_mach_sh2e	, \
    474. 

  474.  /* EF_SH4A		*/ bfd_mach_sh4a	, \
    475. 

  475.  /* EF_SH2A		*/ bfd_mach_sh2a        , \
    476. 

  476. -/* 14, 15		*/ 0, 0, \
    477. 

  477. +/* EF_SHJ2		*/ bfd_mach_shj2        , \
    478. 

  478. +/* 15			*/ 0, \
    479. 

  479.  /* EF_SH4_NOFPU		*/ bfd_mach_sh4_nofpu	, \
    480. 

  480.  /* EF_SH4A_NOFPU	*/ bfd_mach_sh4a_nofpu	, \
    481. 

  481.  /* EF_SH4_NOMMU_NOFPU	*/ bfd_mach_sh4_nommu_nofpu, \
    482. 

  482. @@ -81,7 +84,8 @@
    483. 

  483.  /* EF_SH2A_SH4_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
    484. 

  484.  /* EF_SH2A_SH3_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
    485. 

  485.  /* EF_SH2A_SH4          */ bfd_mach_sh2a_or_sh4 , \
    486. 

  486. -/* EF_SH2A_SH3E         */ bfd_mach_sh2a_or_sh3e
    487. 

  487. +/* EF_SH2A_SH3E         */ bfd_mach_sh2a_or_sh3e, \
    488. 

  488. +/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
    489. 

  489.  
    490. 

  490.  /* Convert arch_sh* into EF_SH*.  */
    491. 

  491.  int sh_find_elf_flags (unsigned int arch_set);
    492. 

  492. diff -Nur binutils-2.42.orig/opcodes/sh-dis.c binutils-2.42/opcodes/sh-dis.c
    493. 

  493. --- binutils-2.42.orig/opcodes/sh-dis.c	2024-01-29 01:00:00.000000000 +0100
    494. 

  494. +++ binutils-2.42/opcodes/sh-dis.c	2024-02-22 16:50:03.693904638 +0100
    495. 

  495. @@ -866,6 +866,9 @@
    496. 

  496.  	    case XMTRX_M4:
    497. 

  497.  	      fprintf_fn (stream, "xmtrx");
    498. 

  498.  	      break;
    499. 

  499. +	    case A_IND_0:
    500. 

  500. +	      fprintf_fn (stream, "@r0");
    501. 

  501. +	      break;
    502. 

  502.  	    default:
    503. 

  503.  	      abort ();
    504. 

  504.  	    }
    505. 

  505. diff -Nur binutils-2.42.orig/opcodes/sh-opc.h binutils-2.42/opcodes/sh-opc.h
    506. 

  506. --- binutils-2.42.orig/opcodes/sh-opc.h	2024-01-29 01:00:00.000000000 +0100
    507. 

  507. +++ binutils-2.42/opcodes/sh-opc.h	2024-02-22 16:50:03.697904670 +0100
    508. 

  508. @@ -192,7 +192,8 @@
    509. 

  509.      FPUL_N,
    510. 

  510.      FPUL_M,
    511. 

  511.      FPSCR_N,
    512. 

  512. -    FPSCR_M
    513. 

  513. +    FPSCR_M,
    514. 

  514. +    A_IND_0
    515. 

  515.    }
    516. 

  516.  sh_arg_type;
    517. 

  517.  
    518. 

  518. @@ -216,9 +217,11 @@
    519. 

  519.  #define arch_sh4_base	    (1 << 5)
    520. 

  520.  #define arch_sh4a_base	    (1 << 6)
    521. 

  521.  #define arch_sh2a_base      (1 << 7)
    522. 

  522. -#define arch_sh_base_mask   MASK (0, 7)
    523. 

  523. +#define arch_shj2_base      (1 << 8)
    524. 

  524. +#define arch_sh2a_sh3_shj2_base  (1 << 9)
    525. 

  525. +#define arch_sh_base_mask   MASK (0, 9)
    526. 

  526.  
    527. 

  527. -/* Bits 8 ... 24 are currently free.  */
    528. 

  528. +/* Bits 10 ... 24 are currently free.  */
    529. 

  529.  
    530. 

  530.  /* This is an annotation on instruction types, but we
    531. 

  531.     abuse the arch field in instructions to denote it.  */
    532. 

  532. @@ -256,6 +259,8 @@
    533. 

  533.  #define arch_sh2a_nofpu_or_sh3_nommu       (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
    534. 

  534.  #define arch_sh2a_or_sh3e                  (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
    535. 

  535.  #define arch_sh2a_or_sh4                   (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
    536. 

  536. +#define arch_shj2                          (arch_shj2_base    |arch_sh_no_mmu |arch_sh_no_co)
    537. 

  537. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu       (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
    538. 

  538.  
    539. 

  539.  #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
    540. 

  540.  #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
    541. 

  541. @@ -320,7 +325,8 @@
    542. 

  542.  #define arch_sh2_up                            (arch_sh2 \
    543. 

  543.  		| arch_sh2e_up \
    544. 

  544.  		| arch_sh2a_nofpu_or_sh3_nommu_up \
    545. 

  545. -		| arch_sh_dsp_up)
    546. 

  546. +		| arch_sh_dsp_up \
    547. 

  547. +		| arch_shj2_up)
    548. 

  548.  #define arch_sh2a_nofpu_or_sh3_nommu_up        (arch_sh2a_nofpu_or_sh3_nommu \
    549. 

  549.  		| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
    550. 

  550.  		| arch_sh2a_or_sh3e_up \
    551. 

  551. @@ -346,6 +352,12 @@
    552. 

  552.  #define arch_sh4a_nofpu_up                     (arch_sh4a_nofpu \
    553. 

  553.  		| arch_sh4a_up \
    554. 

  554.  		| arch_sh4al_dsp_up)
    555. 

  555. +#define arch_shj2_up		       	       ( arch_shj2)
    556. 

  556. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
    557. 

  557. +		| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
    558. 

  558. +		| arch_sh2a_or_sh3e_up \
    559. 

  559. +		| arch_sh3_nommu_up \
    560. 

  560. +		| arch_shj2_up)
    561. 

  561.  
    562. 

  562.  /* Right branches.  */
    563. 

  563.  #define arch_sh2e_up                           (arch_sh2e \
    564. 

  564. @@ -714,9 +726,9 @@
    565. 

  565.  
    566. 

  566.  /* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up},
    567. 

  567.  
    568. 

  568. -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
    569. 

  569. +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
    570. 

  570.  
    571. 

  571. -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
    572. 

  572. +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
    573. 

  573.  
    574. 

  574.  /* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
    575. 

  575.  
    576. 

  576. @@ -1194,7 +1206,7 @@
    577. 

  577.  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
    578. 

  578.  /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
    579. 

  579.  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
    580. 

  580. -
    581. 

  581. +  /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */       {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
    582. 

  582.  { 0, {0}, {0}, 0 }
    583. 

  583.  };
    584. 

  584.  
    585.