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j2.patch

j2.patch 51 KB
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  1. diff -Nur binutils-2.28.orig/bfd/archures.c binutils-2.28/bfd/archures.c
    2. 

  2. --- binutils-2.28.orig/bfd/archures.c	2017-03-02 09:23:53.000000000 +0100
    3. 

  3. +++ binutils-2.28/bfd/archures.c	2017-03-09 05:45:38.004728034 +0100
    4. 

  4. @@ -310,10 +310,12 @@
    5. 

  5.  .#define bfd_mach_sh_dsp     0x2d
    6. 

  6.  .#define bfd_mach_sh2a       0x2a
    7. 

  7.  .#define bfd_mach_sh2a_nofpu 0x2b
    8. 

  8. +.#define bfd_mach_shj2       0x2c
    9. 

  9.  .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
    10. 

  10.  .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
    11. 

  11.  .#define bfd_mach_sh2a_or_sh4  0x2a3
    12. 

  12.  .#define bfd_mach_sh2a_or_sh3e 0x2a4
    13. 

  13. +.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
    14. 

  14.  .#define bfd_mach_sh2e       0x2e
    15. 

  15.  .#define bfd_mach_sh3        0x30
    16. 

  16.  .#define bfd_mach_sh3_nommu  0x31
    17. 

  17. diff -Nur binutils-2.28.orig/bfd/bfd-in2.h binutils-2.28/bfd/bfd-in2.h
    18. 

  18. --- binutils-2.28.orig/bfd/bfd-in2.h	2017-03-02 09:23:53.000000000 +0100
    19. 

  19. +++ binutils-2.28/bfd/bfd-in2.h	2017-03-09 05:45:38.008728189 +0100
    20. 

  20. @@ -2154,10 +2154,12 @@
    21. 

  21.  #define bfd_mach_sh_dsp     0x2d
    22. 

  22.  #define bfd_mach_sh2a       0x2a
    23. 

  23.  #define bfd_mach_sh2a_nofpu 0x2b
    24. 

  24. +#define bfd_mach_shj2       0x2c
    25. 

  25.  #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
    26. 

  26.  #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
    27. 

  27.  #define bfd_mach_sh2a_or_sh4  0x2a3
    28. 

  28.  #define bfd_mach_sh2a_or_sh3e 0x2a4
    29. 

  29. +#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
    30. 

  30.  #define bfd_mach_sh2e       0x2e
    31. 

  31.  #define bfd_mach_sh3        0x30
    32. 

  32.  #define bfd_mach_sh3_nommu  0x31
    33. 

  33. diff -Nur binutils-2.28.orig/bfd/cpu-sh.c binutils-2.28/bfd/cpu-sh.c
    34. 

  34. --- binutils-2.28.orig/bfd/cpu-sh.c	2017-03-02 09:23:53.000000000 +0100
    35. 

  35. +++ binutils-2.28/bfd/cpu-sh.c	2017-03-09 05:45:38.008728189 +0100
    36. 

  36. @@ -44,7 +44,9 @@
    37. 

  37.  #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT       arch_info_struct + 17
    38. 

  38.  #define SH2A_OR_SH4_NEXT                   arch_info_struct + 18
    39. 

  39.  #define SH2A_OR_SH3E_NEXT                  arch_info_struct + 19
    40. 

  40. -#define SH64_NEXT                          NULL
    41. 

  41. +#define SH64_NEXT                          arch_info_struct + 20
    42. 

  42. +#define SHJ2_NEXT       		   arch_info_struct + 21
    43. 

  43. +#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT       NULL
    44. 

  44.  
    45. 

  45.  static const bfd_arch_info_type arch_info_struct[] =
    46. 

  46.  {
    47. 

  47. @@ -348,6 +350,36 @@
    48. 

  48.      bfd_arch_default_fill,
    49. 

  49.      SH64_NEXT
    50. 

  50.    },
    51. 

  51. +  {
    52. 

  52. +    32,				/* 32 bits in a word.  */
    53. 

  53. +    32,				/* 32 bits in an address.  */
    54. 

  54. +    8,				/* 8 bits in a byte.  */
    55. 

  55. +    bfd_arch_sh,
    56. 

  56. +    bfd_mach_shj2,
    57. 

  57. +    "sh",			/* Architecture name. .  */
    58. 

  58. +    "j2",			/* Machine name.  */
    59. 

  59. +    1,
    60. 

  60. +    FALSE,			/* Not the default.  */
    61. 

  61. +    bfd_default_compatible,
    62. 

  62. +    bfd_default_scan,
    63. 

  63. +    bfd_arch_default_fill,
    64. 

  64. +    SHJ2_NEXT
    65. 

  65. +  },
    66. 

  66. +  {
    67. 

  67. +    32,				/* 32 bits in a word.  */
    68. 

  68. +    32,				/* 32 bits in an address.  */
    69. 

  69. +    8,				/* 8 bits in a byte.  */
    70. 

  70. +    bfd_arch_sh,
    71. 

  71. +    bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
    72. 

  72. +    "sh",			/* Architecture name. .  */
    73. 

  73. +    "sh2a-or-sh3e-or-j2",	/* Machine name.  */
    74. 

  74. +    1,
    75. 

  75. +    FALSE,			/* Not the default.  */
    76. 

  76. +    bfd_default_compatible,
    77. 

  77. +    bfd_default_scan,
    78. 

  78. +    bfd_arch_default_fill,
    79. 

  79. +    SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
    80. 

  80. +  },
    81. 

  81.  };
    82. 

  82.  
    83. 

  83.  const bfd_arch_info_type bfd_sh_arch =
    84. 

  84. @@ -398,6 +430,8 @@
    85. 

  85.    { bfd_mach_sh4_nofpu,       arch_sh4_nofpu,       arch_sh4_nofpu_up },
    86. 

  86.    { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
    87. 

  87.    { bfd_mach_sh4a_nofpu,      arch_sh4a_nofpu,      arch_sh4a_nofpu_up },
    88. 

  88. +  { bfd_mach_shj2,            arch_shj2,            arch_shj2_up },
    89. 

  89. +  { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
    90. 

  90.    { 0, 0, 0 }   /* Terminator.  */
    91. 

  91.  };
    92. 

  92.  
    93. 

  93. diff -Nur binutils-2.28.orig/binutils/readelf.c binutils-2.28/binutils/readelf.c
    94. 

  94. --- binutils-2.28.orig/binutils/readelf.c	2017-03-02 09:23:53.000000000 +0100
    95. 

  95. +++ binutils-2.28/binutils/readelf.c	2017-03-09 05:45:40.720833187 +0100
    96. 

  96. @@ -3362,6 +3362,8 @@
    97. 

  97.  	    case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
    98. 

  98.  	    case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
    99. 

  99.  	    case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
    100. 

  100. +	    case EF_SHJ2: strcat (buf, ", j2"); break;
    101. 

  101. +	    case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
    102. 

  102.  	    default: strcat (buf, _(", unknown ISA")); break;
    103. 

  103.  	    }
    104. 

  104.  
    105. 

  105. diff -Nur binutils-2.28.orig/gas/config/tc-sh.c binutils-2.28/gas/config/tc-sh.c
    106. 

  106. --- binutils-2.28.orig/gas/config/tc-sh.c	2017-03-02 09:23:53.000000000 +0100
    107. 

  107. +++ binutils-2.28/gas/config/tc-sh.c	2017-03-09 05:45:40.720833187 +0100
    108. 

  108. @@ -1648,6 +1648,8 @@
    109. 

  109.  		  ptr++;
    110. 

  110.  		}
    111. 

  111.  	      get_operand (&ptr, operand + 2);
    112. 

  112. +	      if (strcmp (info->name,"cas") == 0)
    113. 

  113. +		operand[2].type = A_IND_0;
    114. 

  114.  	    }
    115. 

  115.  	  else
    116. 

  116.  	    {
    117. 

  117. @@ -2187,7 +2189,10 @@
    118. 

  118.  		goto fail;
    119. 

  119.  	      reg_m = 4;
    120. 

  120.  	      break;
    121. 

  121. -
    122. 

  122. +	    case A_IND_0:
    123. 

  123. +	      if (user->reg != 0)
    124. 

  124. +		goto fail;
    125. 

  125. +	      break;
    126. 

  126.  	    default:
    127. 

  127.  	      printf (_("unhandled %d\n"), arg);
    128. 

  128.  	      goto fail;
    129. 

  129. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
    130. 

  130. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s	2015-11-13 09:27:41.000000000 +0100
    131. 

  131. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s	2017-03-09 05:45:40.720833187 +0100
    132. 

  132. @@ -12,8 +12,6 @@
    133. 

  133.  sh2a_nofpu_or_sh3_nommu:
    134. 

  134.  ! Instructions introduced into sh2a-nofpu-or-sh3-nommu
    135. 

  135.  	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
    136. 

  136. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    137. 

  137. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    138. 

  138.  
    139. 

  139.  ! Instructions inherited from ancestors: sh sh2
    140. 

  140.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    141. 

  141. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    142. 

  142. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s	2015-11-13 09:27:41.000000000 +0100
    143. 

  143. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s	2017-03-09 05:45:40.720833187 +0100
    144. 

  144. @@ -12,7 +12,7 @@
    145. 

  145.  sh2a_nofpu_or_sh4_nommu_nofpu:
    146. 

  146.  ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
    147. 

  147.  
    148. 

  148. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
    149. 

  149. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
    150. 

  150.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    151. 

  151.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    152. 

  152.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    153. 

  153. @@ -119,8 +119,8 @@
    154. 

  154.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    155. 

  155.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    156. 

  156.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    157. 

  157. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    158. 

  158. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    159. 

  159. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    160. 

  160. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    161. 

  161.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    162. 

  162.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    163. 

  163.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    164. 

  164. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
    165. 

  165. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s	2015-11-13 09:27:41.000000000 +0100
    166. 

  166. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-nofpu.s	2017-03-09 05:45:40.720833187 +0100
    167. 

  167. @@ -64,7 +64,7 @@
    168. 

  168.  	movu.b @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
    169. 

  169.  	movu.w @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
    170. 

  170.  
    171. 

  171. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
    172. 

  172. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
    173. 

  173.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    174. 

  174.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    175. 

  175.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    176. 

  176. @@ -171,8 +171,8 @@
    177. 

  177.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    178. 

  178.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    179. 

  179.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    180. 

  180. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    181. 

  181. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    182. 

  182. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    183. 

  183. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    184. 

  184.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    185. 

  185.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    186. 

  186.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    187. 

  187. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
    188. 

  188. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s	2015-11-13 09:27:41.000000000 +0100
    189. 

  189. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s	2017-03-09 05:45:40.720833187 +0100
    190. 

  190. @@ -13,7 +13,7 @@
    191. 

  191.  ! Instructions introduced into sh2a-or-sh3e
    192. 

  192.  	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
    193. 

  193.  
    194. 

  194. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
    195. 

  195. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
    196. 

  196.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    197. 

  197.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    198. 

  198.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    199. 

  199. @@ -124,8 +124,8 @@
    200. 

  200.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    201. 

  201.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    202. 

  202.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    203. 

  203. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    204. 

  204. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    205. 

  205. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    206. 

  206. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    207. 

  207.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    208. 

  208.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    209. 

  209.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    210. 

  210. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
    211. 

  211. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s	2015-11-13 09:27:41.000000000 +0100
    212. 

  212. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s	2017-03-09 05:45:40.720833187 +0100
    213. 

  213. @@ -39,7 +39,7 @@
    214. 

  214.  	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
    215. 

  215.  	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
    216. 

  216.  
    217. 

  217. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
    218. 

  218. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
    219. 

  219.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    220. 

  220.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    221. 

  221.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    222. 

  222. @@ -150,8 +150,8 @@
    223. 

  223.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    224. 

  224.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    225. 

  225.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    226. 

  226. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    227. 

  227. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    228. 

  228. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    229. 

  229. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    230. 

  230.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    231. 

  231.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    232. 

  232.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    233. 

  233. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.28/gas/testsuite/gas/sh/arch/sh2a.s
    234. 

  234. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh2a.s	2015-11-13 09:27:41.000000000 +0100
    235. 

  235. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh2a.s	2017-03-09 05:45:40.724833342 +0100
    236. 

  236. @@ -16,7 +16,7 @@
    237. 

  237.  	fmov.s fr2,@(2048,r4)     ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */  {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
    238. 

  238.  	fmov.s @(2048,r5),fr1     ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */  {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
    239. 

  239.  
    240. 

  240. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
    241. 

  241. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
    242. 

  242.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    243. 

  243.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    244. 

  244.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    245. 

  245. @@ -140,8 +140,8 @@
    246. 

  246.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    247. 

  247.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    248. 

  248.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    249. 

  249. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    250. 

  250. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    251. 

  251. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    252. 

  252. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    253. 

  253.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    254. 

  254.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    255. 

  255.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    256. 

  256. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3-dsp.s
    257. 

  257. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s	2015-11-13 09:27:41.000000000 +0100
    258. 

  258. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3-dsp.s	2017-03-09 05:45:40.724833342 +0100
    259. 

  259. @@ -12,7 +12,7 @@
    260. 

  260.  sh3_dsp:
    261. 

  261.  ! Instructions introduced into sh3-dsp
    262. 

  262.  
    263. 

  263. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
    264. 

  264. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
    265. 

  265.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    266. 

  266.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    267. 

  267.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    268. 

  268. @@ -152,8 +152,8 @@
    269. 

  269.  	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
    270. 

  270.  	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
    271. 

  271.  	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
    272. 

  272. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    273. 

  273. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    274. 

  274. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    275. 

  275. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    276. 

  276.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    277. 

  277.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    278. 

  278.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    279. 

  279. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3e.s
    280. 

  280. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3e.s	2015-11-13 09:27:41.000000000 +0100
    281. 

  281. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3e.s	2017-03-09 05:45:40.724833342 +0100
    282. 

  282. @@ -12,7 +12,7 @@
    283. 

  283.  sh3e:
    284. 

  284.  ! Instructions introduced into sh3e
    285. 

  285.  
    286. 

  286. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
    287. 

  287. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
    288. 

  288.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    289. 

  289.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    290. 

  290.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    291. 

  291. @@ -132,8 +132,8 @@
    292. 

  292.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    293. 

  293.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    294. 

  294.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    295. 

  295. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    296. 

  296. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    297. 

  297. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    298. 

  298. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    299. 

  299.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    300. 

  300.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    301. 

  301.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    302. 

  302. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3-nommu.s
    303. 

  303. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s	2015-11-13 09:27:41.000000000 +0100
    304. 

  304. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3-nommu.s	2017-03-09 05:45:40.724833342 +0100
    305. 

  305. @@ -26,7 +26,7 @@
    306. 

  306.  	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
    307. 

  307.  	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
    308. 

  308.  
    309. 

  309. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
    310. 

  310. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
    311. 

  311.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    312. 

  312.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    313. 

  313.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    314. 

  314. @@ -133,8 +133,8 @@
    315. 

  315.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    316. 

  316.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    317. 

  317.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    318. 

  318. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    319. 

  319. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    320. 

  320. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    321. 

  321. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    322. 

  322.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    323. 

  323.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    324. 

  324.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    325. 

  325. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.28/gas/testsuite/gas/sh/arch/sh3.s
    326. 

  326. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh3.s	2015-11-13 09:27:41.000000000 +0100
    327. 

  327. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh3.s	2017-03-09 05:45:40.724833342 +0100
    328. 

  328. @@ -13,7 +13,7 @@
    329. 

  329.  ! Instructions introduced into sh3
    330. 

  330.  	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
    331. 

  331.  
    332. 

  332. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
    333. 

  333. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
    334. 

  334.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    335. 

  335.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    336. 

  336.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    337. 

  337. @@ -128,8 +128,8 @@
    338. 

  338.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    339. 

  339.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    340. 

  340.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    341. 

  341. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    342. 

  342. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    343. 

  343. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    344. 

  344. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    345. 

  345.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    346. 

  346.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    347. 

  347.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    348. 

  348. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4al-dsp.s
    349. 

  349. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s	2015-11-13 09:27:41.000000000 +0100
    350. 

  350. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4al-dsp.s	2017-03-09 05:45:40.724833342 +0100
    351. 

  351. @@ -48,7 +48,7 @@
    352. 

  352.  	dct pswap x1,m0           ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */  {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
    353. 

  353.  	dct pswap y0,m0           ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */  {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
    354. 

  354.  
    355. 

  355. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    356. 

  356. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    357. 

  357.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    358. 

  358.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    359. 

  359.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    360. 

  360. @@ -202,8 +202,8 @@
    361. 

  361.  	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
    362. 

  362.  	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
    363. 

  363.  	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
    364. 

  364. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    365. 

  365. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    366. 

  366. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    367. 

  367. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    368. 

  368.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    369. 

  369.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    370. 

  370.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    371. 

  371. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
    372. 

  372. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s	2015-11-13 09:27:41.000000000 +0100
    373. 

  373. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4a-nofpu.s	2017-03-09 05:45:40.724833342 +0100
    374. 

  374. @@ -19,7 +19,7 @@
    375. 

  375.  	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
    376. 

  376.  	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
    377. 

  377.  
    378. 

  378. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
    379. 

  379. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
    380. 

  380.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    381. 

  381.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    382. 

  382.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    383. 

  383. @@ -143,8 +143,8 @@
    384. 

  384.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    385. 

  385.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    386. 

  386.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    387. 

  387. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    388. 

  388. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    389. 

  389. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    390. 

  390. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    391. 

  391.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    392. 

  392.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    393. 

  393.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    394. 

  394. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4a.s
    395. 

  395. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4a.s	2015-11-13 09:27:41.000000000 +0100
    396. 

  396. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4a.s	2017-03-09 05:45:40.724833342 +0100
    397. 

  397. @@ -13,7 +13,7 @@
    398. 

  398.  ! Instructions introduced into sh4a
    399. 

  399.  	fpchg                     ;!/* 1111011111111101 fpchg               */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
    400. 

  400.  
    401. 

  401. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    402. 

  402. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    403. 

  403.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    404. 

  404.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    405. 

  405.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    406. 

  406. @@ -147,8 +147,8 @@
    407. 

  407.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    408. 

  408.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    409. 

  409.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    410. 

  410. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    411. 

  411. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    412. 

  412. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    413. 

  413. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    414. 

  414.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    415. 

  415.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    416. 

  416.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    417. 

  417. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nofpu.s
    418. 

  418. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s	2015-11-13 09:27:41.000000000 +0100
    419. 

  419. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nofpu.s	2017-03-09 05:45:40.724833342 +0100
    420. 

  420. @@ -12,7 +12,7 @@
    421. 

  421.  sh4_nofpu:
    422. 

  422.  ! Instructions introduced into sh4-nofpu
    423. 

  423.  
    424. 

  424. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
    425. 

  425. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
    426. 

  426.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    427. 

  427.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    428. 

  428.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    429. 

  429. @@ -136,8 +136,8 @@
    430. 

  430.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    431. 

  431.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    432. 

  432.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    433. 

  433. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    434. 

  434. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    435. 

  435. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    436. 

  436. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    437. 

  437.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    438. 

  438.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    439. 

  439.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    440. 

  440. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
    441. 

  441. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s	2015-11-13 09:27:41.000000000 +0100
    442. 

  442. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s	2017-03-09 05:45:40.724833342 +0100
    443. 

  443. @@ -24,7 +24,7 @@
    444. 

  444.  	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
    445. 

  445.  	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
    446. 

  446.  
    447. 

  447. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
    448. 

  448. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
    449. 

  449.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    450. 

  450.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    451. 

  451.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    452. 

  452. @@ -139,8 +139,8 @@
    453. 

  453.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    454. 

  454.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    455. 

  455.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    456. 

  456. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    457. 

  457. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    458. 

  458. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    459. 

  459. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    460. 

  460.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    461. 

  461.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    462. 

  462.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    463. 

  463. diff -Nur binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.28/gas/testsuite/gas/sh/arch/sh4.s
    464. 

  464. --- binutils-2.28.orig/gas/testsuite/gas/sh/arch/sh4.s	2015-11-13 09:27:41.000000000 +0100
    465. 

  465. +++ binutils-2.28/gas/testsuite/gas/sh/arch/sh4.s	2017-03-09 05:45:40.724833342 +0100
    466. 

  466. @@ -17,7 +17,7 @@
    467. 

  467.  	fsrra fr1                 ;!/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
    468. 

  468.  	ftrv xmtrx,fv0            ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
    469. 

  469.  
    470. 

  470. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
    471. 

  471. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
    472. 

  472.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    473. 

  473.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    474. 

  474.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    475. 

  475. @@ -145,8 +145,8 @@
    476. 

  476.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    477. 

  477.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    478. 

  478.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    479. 

  479. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    480. 

  480. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    481. 

  481. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    482. 

  482. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    483. 

  483.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    484. 

  484.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    485. 

  485.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    486. 

  486. diff -Nur binutils-2.28.orig/include/elf/sh.h binutils-2.28/include/elf/sh.h
    487. 

  487. --- binutils-2.28.orig/include/elf/sh.h	2017-03-02 09:23:54.000000000 +0100
    488. 

  488. +++ binutils-2.28/include/elf/sh.h	2017-03-09 05:45:40.724833342 +0100
    489. 

  489. @@ -39,6 +39,7 @@
    490. 

  490.  #define EF_SH2E            11
    491. 

  491.  #define EF_SH4A		   12
    492. 

  492.  #define EF_SH2A            13
    493. 

  493. +#define EF_SHJ2            14
    494. 

  494.  
    495. 

  495.  #define EF_SH4_NOFPU	   16
    496. 

  496.  #define EF_SH4A_NOFPU	   17
    497. 

  497. @@ -50,6 +51,7 @@
    498. 

  498.  #define EF_SH2A_SH3_NOFPU  22
    499. 

  499.  #define EF_SH2A_SH4        23
    500. 

  500.  #define EF_SH2A_SH3E       24
    501. 

  501. +#define EF_SH2A_SH3_SHJ2   25
    502. 

  502.  
    503. 

  503.  /* This one can only mix in objects from other EF_SH5 objects.  */
    504. 

  504.  #define EF_SH5		  10
    505. 

  505. @@ -72,7 +74,8 @@
    506. 

  506.  /* EF_SH2E		*/ bfd_mach_sh2e	, \
    507. 

  507.  /* EF_SH4A		*/ bfd_mach_sh4a	, \
    508. 

  508.  /* EF_SH2A		*/ bfd_mach_sh2a        , \
    509. 

  509. -/* 14, 15		*/ 0, 0, \
    510. 

  510. +/* EF_SHJ2		*/ bfd_mach_shj2        , \
    511. 

  511. +/* 15			*/ 0, \
    512. 

  512.  /* EF_SH4_NOFPU		*/ bfd_mach_sh4_nofpu	, \
    513. 

  513.  /* EF_SH4A_NOFPU	*/ bfd_mach_sh4a_nofpu	, \
    514. 

  514.  /* EF_SH4_NOMMU_NOFPU	*/ bfd_mach_sh4_nommu_nofpu, \
    515. 

  515. @@ -81,7 +84,8 @@
    516. 

  516.  /* EF_SH2A_SH4_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
    517. 

  517.  /* EF_SH2A_SH3_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
    518. 

  518.  /* EF_SH2A_SH4          */ bfd_mach_sh2a_or_sh4 , \
    519. 

  519. -/* EF_SH2A_SH3E         */ bfd_mach_sh2a_or_sh3e
    520. 

  520. +/* EF_SH2A_SH3E         */ bfd_mach_sh2a_or_sh3e, \
    521. 

  521. +/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
    522. 

  522.  
    523. 

  523.  /* Convert arch_sh* into EF_SH*.  */
    524. 

  524.  int sh_find_elf_flags (unsigned int arch_set);
    525. 

  525. diff -Nur binutils-2.28.orig/opcodes/sh-dis.c binutils-2.28/opcodes/sh-dis.c
    526. 

  526. --- binutils-2.28.orig/opcodes/sh-dis.c	2017-03-02 09:23:54.000000000 +0100
    527. 

  527. +++ binutils-2.28/opcodes/sh-dis.c	2017-03-09 05:45:46.017038228 +0100
    528. 

  528. @@ -870,6 +870,9 @@
    529. 

  529.  	    case XMTRX_M4:
    530. 

  530.  	      fprintf_fn (stream, "xmtrx");
    531. 

  531.  	      break;
    532. 

  532. +	    case A_IND_0:
    533. 

  533. +	      fprintf_fn (stream, "@r0");
    534. 

  534. +	      break;
    535. 

  535.  	    default:
    536. 

  536.  	      abort ();
    537. 

  537.  	    }
    538. 

  538. diff -Nur binutils-2.28.orig/opcodes/sh-opc.h binutils-2.28/opcodes/sh-opc.h
    539. 

  539. --- binutils-2.28.orig/opcodes/sh-opc.h	2017-03-02 09:23:54.000000000 +0100
    540. 

  540. +++ binutils-2.28/opcodes/sh-opc.h	2017-03-09 05:45:46.017038228 +0100
    541. 

  541. @@ -191,7 +191,8 @@
    542. 

  542.      FPUL_N,
    543. 

  543.      FPUL_M,
    544. 

  544.      FPSCR_N,
    545. 

  545. -    FPSCR_M
    546. 

  546. +    FPSCR_M,
    547. 

  547. +    A_IND_0
    548. 

  548.    }
    549. 

  549.  sh_arg_type;
    550. 

  550.  
    551. 

  551. @@ -218,9 +219,11 @@
    552. 

  552.  #define arch_sh4_base	    (1 << 5)
    553. 

  553.  #define arch_sh4a_base	    (1 << 6)
    554. 

  554.  #define arch_sh2a_base      (1 << 7)
    555. 

  555. -#define arch_sh_base_mask   MASK (0, 7)
    556. 

  556. +#define arch_shj2_base      (1 << 8)
    557. 

  557. +#define arch_sh2a_sh3_shj2_base  (1 << 9)
    558. 

  558. +#define arch_sh_base_mask   MASK (0, 9)
    559. 

  559.  
    560. 

  560. -/* Bits 8 ... 24 are currently free.  */
    561. 

  561. +/* Bits 10 ... 24 are currently free.  */
    562. 

  562.  
    563. 

  563.  /* This is an annotation on instruction types, but we
    564. 

  564.     abuse the arch field in instructions to denote it.  */
    565. 

  565. @@ -258,6 +261,8 @@
    566. 

  566.  #define arch_sh2a_nofpu_or_sh3_nommu       (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
    567. 

  567.  #define arch_sh2a_or_sh3e                  (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
    568. 

  568.  #define arch_sh2a_or_sh4                   (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
    569. 

  569. +#define arch_shj2                          (arch_shj2_base    |arch_sh_no_mmu |arch_sh_no_co)
    570. 

  570. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu       (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
    571. 

  571.  
    572. 

  572.  #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
    573. 

  573.  #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
    574. 

  574. @@ -322,7 +327,8 @@
    575. 

  575.  #define arch_sh2_up                            (arch_sh2 \
    576. 

  576.  		| arch_sh2e_up \
    577. 

  577.  		| arch_sh2a_nofpu_or_sh3_nommu_up \
    578. 

  578. -		| arch_sh_dsp_up)
    579. 

  579. +		| arch_sh_dsp_up \
    580. 

  580. +		| arch_shj2_up)
    581. 

  581.  #define arch_sh2a_nofpu_or_sh3_nommu_up        (arch_sh2a_nofpu_or_sh3_nommu \
    582. 

  582.  		| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
    583. 

  583.  		| arch_sh2a_or_sh3e_up \
    584. 

  584. @@ -348,6 +354,12 @@
    585. 

  585.  #define arch_sh4a_nofpu_up                     (arch_sh4a_nofpu \
    586. 

  586.  		| arch_sh4a_up \
    587. 

  587.  		| arch_sh4al_dsp_up)
    588. 

  588. +#define arch_shj2_up		       	       ( arch_shj2)
    589. 

  589. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
    590. 

  590. +		| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
    591. 

  591. +		| arch_sh2a_or_sh3e_up \
    592. 

  592. +		| arch_sh3_nommu_up \
    593. 

  593. +		| arch_shj2_up)
    594. 

  594.  
    595. 

  595.  /* Right branches.  */
    596. 

  596.  #define arch_sh2e_up                           (arch_sh2e \
    597. 

  597. @@ -716,9 +728,9 @@
    598. 

  598.  
    599. 

  599.  /* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
    600. 

  600.  
    601. 

  601. -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
    602. 

  602. +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
    603. 

  603.  
    604. 

  604. -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
    605. 

  605. +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
    606. 

  606.  
    607. 

  607.  /* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
    608. 

  608.  
    609. 

  609. @@ -1196,7 +1208,7 @@
    610. 

  610.  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
    611. 

  611.  /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
    612. 

  612.  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
    613. 

  613. -
    614. 

  614. +  /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */       {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
    615. 

  615.  { 0, {0}, {0}, 0 }
    616. 

  616.  };
    617. 

  617.  
    618.