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- diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c
- --- elf2flt-v2021.08.orig/elf2flt.c 2023-02-26 11:31:48.758810872 +0100
- +++ elf2flt-v2021.08/elf2flt.c 2023-02-26 11:32:05.714465277 +0100
- @@ -81,7 +81,7 @@
- #include <elf/v850.h>
- #elif defined(TARGET_xtensa)
- #include <elf/xtensa.h>
- -#elif defined(TARGET_riscv64)
- +#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
- #include <elf/riscv.h>
- #endif
-
- @@ -127,6 +127,8 @@
- #define ARCH "xtensa"
- #elif defined(TARGET_riscv64)
- #define ARCH "riscv64"
- +#elif defined(TARGET_riscv32)
- +#define ARCH "riscv32"
- #else
- #error "Don't know how to support your CPU architecture??"
- #endif
- @@ -849,12 +851,21 @@
- break;
- default:
- goto bad_resolved_reloc;
- -#elif defined(TARGET_riscv64)
- +#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
- case R_RISCV_32_PCREL:
- + case R_RISCV_ADD8:
- + case R_RISCV_ADD16:
- case R_RISCV_ADD32:
- case R_RISCV_ADD64:
- + case R_RISCV_SUB6:
- + case R_RISCV_SUB8:
- + case R_RISCV_SUB16:
- case R_RISCV_SUB32:
- case R_RISCV_SUB64:
- + case R_RISCV_SET6:
- + case R_RISCV_SET8:
- + case R_RISCV_SET16:
- + case R_RISCV_SET32:
- continue;
- case R_RISCV_32:
- case R_RISCV_64:
- diff -Nur elf2flt-v2021.08.orig/ld-elf2flt.c elf2flt-v2021.08/ld-elf2flt.c
- --- elf2flt-v2021.08.orig/ld-elf2flt.c 2023-02-26 11:31:21.047376888 +0100
- +++ elf2flt-v2021.08/ld-elf2flt.c 2023-02-26 11:32:05.714465277 +0100
- @@ -327,7 +327,7 @@
- /* riscv adds a global pointer symbol to the linker file with the
- "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
- the entire line for other architectures. */
- - if (streq(TARGET_CPU, "riscv64"))
- + if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
- append_sed(&sed, "^RISCV_GP:", "");
- else
- append_sed(&sed, "^RISCV_GP:", NULL);
|
