microblaze-dts.patch 13 KB

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  1. diff -Nur linux-3.11.10.orig/arch/microblaze/platform/generic/system.dts linux-3.11.10/arch/microblaze/platform/generic/system.dts
  2. --- linux-3.11.10.orig/arch/microblaze/platform/generic/system.dts 2013-11-29 19:42:37.000000000 +0100
  3. +++ linux-3.11.10/arch/microblaze/platform/generic/system.dts 2013-12-08 13:01:59.000000000 +0100
  4. @@ -1,102 +1,72 @@
  5. -/*
  6. - * Device Tree Generator version: 1.1
  7. - *
  8. - * (C) Copyright 2007-2008 Xilinx, Inc.
  9. - * (C) Copyright 2007-2009 Michal Simek
  10. - *
  11. - * Michal SIMEK <monstr@monstr.eu>
  12. - *
  13. - * This program is free software; you can redistribute it and/or
  14. - * modify it under the terms of the GNU General Public License as
  15. - * published by the Free Software Foundation; either version 2 of
  16. - * the License, or (at your option) any later version.
  17. - *
  18. - * This program is distributed in the hope that it will be useful,
  19. - * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. - * GNU General Public License for more details.
  22. - *
  23. - * You should have received a copy of the GNU General Public License
  24. - * along with this program; if not, write to the Free Software
  25. - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. - * MA 02111-1307 USA
  27. - *
  28. - * CAUTION: This file is automatically generated by libgen.
  29. - * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
  30. - *
  31. - * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
  32. - */
  33. -
  34. /dts-v1/;
  35. +
  36. / {
  37. - #address-cells = <1>;
  38. - #size-cells = <1>;
  39. + #address-cells = <0x1>;
  40. + #size-cells = <0x1>;
  41. compatible = "xlnx,microblaze";
  42. - hard-reset-gpios = <&LEDs_8Bit 2 1>;
  43. model = "testing";
  44. - DDR2_SDRAM: memory@90000000 {
  45. +
  46. + memory@90000000 {
  47. device_type = "memory";
  48. - reg = < 0x90000000 0x10000000 >;
  49. - } ;
  50. - aliases {
  51. - ethernet0 = &Hard_Ethernet_MAC;
  52. - serial0 = &RS232_Uart_1;
  53. - } ;
  54. + reg = <0x90000000 0x8000000>;
  55. + };
  56. +
  57. chosen {
  58. - bootargs = "console=ttyUL0,115200 highres=on";
  59. + bootargs = "console=ttyUL0,115200";
  60. linux,stdout-path = "/plb@0/serial@84000000";
  61. - } ;
  62. + };
  63. +
  64. cpus {
  65. - #address-cells = <1>;
  66. + #address-cells = <0x1>;
  67. #cpus = <0x1>;
  68. - #size-cells = <0>;
  69. - microblaze_0: cpu@0 {
  70. - clock-frequency = <125000000>;
  71. + #size-cells = <0x0>;
  72. +
  73. + cpu@0 {
  74. + clock-frequency = <0x3b9aca0>;
  75. compatible = "xlnx,microblaze-7.10.d";
  76. d-cache-baseaddr = <0x90000000>;
  77. - d-cache-highaddr = <0x9fffffff>;
  78. + d-cache-highaddr = <0x97ffffff>;
  79. d-cache-line-size = <0x10>;
  80. - d-cache-size = <0x2000>;
  81. + d-cache-size = <0x800>;
  82. device_type = "cpu";
  83. i-cache-baseaddr = <0x90000000>;
  84. - i-cache-highaddr = <0x9fffffff>;
  85. + i-cache-highaddr = <0x97ffffff>;
  86. i-cache-line-size = <0x10>;
  87. - i-cache-size = <0x2000>;
  88. + i-cache-size = <0x800>;
  89. model = "microblaze,7.10.d";
  90. - reg = <0>;
  91. - timebase-frequency = <125000000>;
  92. - xlnx,addr-tag-bits = <0xf>;
  93. + reg = <0x0>;
  94. + timebase-frequency = <0x3b9aca0>;
  95. + xlnx,addr-tag-bits = <0x10>;
  96. xlnx,allow-dcache-wr = <0x1>;
  97. xlnx,allow-icache-wr = <0x1>;
  98. xlnx,area-optimized = <0x0>;
  99. - xlnx,cache-byte-size = <0x2000>;
  100. + xlnx,cache-byte-size = <0x800>;
  101. xlnx,d-lmb = <0x1>;
  102. xlnx,d-opb = <0x0>;
  103. xlnx,d-plb = <0x1>;
  104. xlnx,data-size = <0x20>;
  105. - xlnx,dcache-addr-tag = <0xf>;
  106. - xlnx,dcache-always-used = <0x1>;
  107. - xlnx,dcache-byte-size = <0x2000>;
  108. + xlnx,dcache-addr-tag = <0x10>;
  109. + xlnx,dcache-always-used = <0x0>;
  110. + xlnx,dcache-byte-size = <0x800>;
  111. xlnx,dcache-line-len = <0x4>;
  112. xlnx,dcache-use-fsl = <0x1>;
  113. xlnx,debug-enabled = <0x1>;
  114. - xlnx,div-zero-exception = <0x1>;
  115. + xlnx,div-zero-exception = <0x0>;
  116. xlnx,dopb-bus-exception = <0x0>;
  117. xlnx,dynamic-bus-sizing = <0x1>;
  118. xlnx,edge-is-positive = <0x1>;
  119. - xlnx,family = "virtex5";
  120. - xlnx,endianness = <0x1>;
  121. - xlnx,fpu-exception = <0x1>;
  122. + xlnx,family = "spartan3adsp";
  123. + xlnx,fpu-exception = <0x0>;
  124. xlnx,fsl-data-size = <0x20>;
  125. xlnx,fsl-exception = <0x0>;
  126. xlnx,fsl-links = <0x0>;
  127. xlnx,i-lmb = <0x1>;
  128. xlnx,i-opb = <0x0>;
  129. xlnx,i-plb = <0x1>;
  130. - xlnx,icache-always-used = <0x1>;
  131. + xlnx,icache-always-used = <0x0>;
  132. xlnx,icache-line-len = <0x4>;
  133. xlnx,icache-use-fsl = <0x1>;
  134. - xlnx,ill-opcode-exception = <0x1>;
  135. + xlnx,ill-opcode-exception = <0x0>;
  136. xlnx,instance = "microblaze_0";
  137. xlnx,interconnect = <0x1>;
  138. xlnx,interrupt-is-edge = <0x0>;
  139. @@ -105,11 +75,11 @@
  140. xlnx,mmu-itlb-size = <0x2>;
  141. xlnx,mmu-tlb-access = <0x3>;
  142. xlnx,mmu-zones = <0x10>;
  143. - xlnx,number-of-pc-brk = <0x1>;
  144. - xlnx,number-of-rd-addr-brk = <0x0>;
  145. - xlnx,number-of-wr-addr-brk = <0x0>;
  146. - xlnx,opcode-0x0-illegal = <0x1>;
  147. - xlnx,pvr = <0x2>;
  148. + xlnx,number-of-pc-brk = <0x3>;
  149. + xlnx,number-of-rd-addr-brk = <0x2>;
  150. + xlnx,number-of-wr-addr-brk = <0x2>;
  151. + xlnx,opcode-0x0-illegal = <0x0>;
  152. + xlnx,pvr = <0x1>;
  153. xlnx,pvr-user1 = <0x0>;
  154. xlnx,pvr-user2 = <0x0>;
  155. xlnx,reset-msr = <0x0>;
  156. @@ -117,29 +87,44 @@
  157. xlnx,unaligned-exceptions = <0x1>;
  158. xlnx,use-barrel = <0x1>;
  159. xlnx,use-dcache = <0x1>;
  160. - xlnx,use-div = <0x1>;
  161. + xlnx,use-div = <0x0>;
  162. xlnx,use-ext-brk = <0x1>;
  163. xlnx,use-ext-nm-brk = <0x1>;
  164. xlnx,use-extended-fsl-instr = <0x0>;
  165. - xlnx,use-fpu = <0x2>;
  166. - xlnx,use-hw-mul = <0x2>;
  167. + xlnx,use-fpu = <0x0>;
  168. + xlnx,use-hw-mul = <0x1>;
  169. xlnx,use-icache = <0x1>;
  170. xlnx,use-interrupt = <0x1>;
  171. xlnx,use-mmu = <0x3>;
  172. xlnx,use-msr-instr = <0x1>;
  173. xlnx,use-pcmp-instr = <0x1>;
  174. - } ;
  175. - } ;
  176. - mb_plb: plb@0 {
  177. - #address-cells = <1>;
  178. - #size-cells = <1>;
  179. - compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
  180. - ranges ;
  181. - FLASH: flash@a0000000 {
  182. - bank-width = <2>;
  183. + };
  184. + };
  185. +
  186. + plb@0 {
  187. + #address-cells = <0x1>;
  188. + #size-cells = <0x1>;
  189. + compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
  190. + ranges;
  191. +
  192. + ethernet@81000000 {
  193. + compatible = "xlnx,xps-ethernetlite-2.00.b";
  194. + device_type = "network";
  195. + interrupt-parent = <0x1>;
  196. + interrupts = <0x1 0x0>;
  197. + local-mac-address = [02 00 00 00 00 00];
  198. + reg = <0x81000000 0x10000>;
  199. + xlnx,duplex = <0x1>;
  200. + xlnx,family = "spartan3adsp";
  201. + xlnx,rx-ping-pong = <0x0>;
  202. + xlnx,tx-ping-pong = <0x0>;
  203. + };
  204. +
  205. + flash@a0000000 {
  206. + bank-width = <0x1>;
  207. compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
  208. - reg = < 0xa0000000 0x2000000 >;
  209. - xlnx,family = "virtex5";
  210. + reg = <0xa0000000 0x1000000>;
  211. + xlnx,family = "spartan3adsp";
  212. xlnx,include-datawidth-matching-0 = <0x1>;
  213. xlnx,include-datawidth-matching-1 = <0x0>;
  214. xlnx,include-datawidth-matching-2 = <0x0>;
  215. @@ -147,9 +132,9 @@
  216. xlnx,include-negedge-ioregs = <0x0>;
  217. xlnx,include-plb-ipif = <0x1>;
  218. xlnx,include-wrbuf = <0x1>;
  219. - xlnx,max-mem-width = <0x10>;
  220. + xlnx,max-mem-width = <0x8>;
  221. xlnx,mch-native-dwidth = <0x20>;
  222. - xlnx,mch-plb-clk-period-ps = <0x1f40>;
  223. + xlnx,mch-plb-clk-period-ps = <0x3e80>;
  224. xlnx,mch-splb-awidth = <0x20>;
  225. xlnx,mch0-accessbuf-depth = <0x10>;
  226. xlnx,mch0-protocol = <0x0>;
  227. @@ -163,7 +148,7 @@
  228. xlnx,mch3-accessbuf-depth = <0x10>;
  229. xlnx,mch3-protocol = <0x0>;
  230. xlnx,mch3-rddatabuf-depth = <0x10>;
  231. - xlnx,mem0-width = <0x10>;
  232. + xlnx,mem0-width = <0x8>;
  233. xlnx,mem1-width = <0x20>;
  234. xlnx,mem2-width = <0x20>;
  235. xlnx,mem3-width = <0x20>;
  236. @@ -178,31 +163,31 @@
  237. xlnx,synch-pipedelay-1 = <0x2>;
  238. xlnx,synch-pipedelay-2 = <0x2>;
  239. xlnx,synch-pipedelay-3 = <0x2>;
  240. - xlnx,tavdv-ps-mem-0 = <0x1adb0>;
  241. + xlnx,tavdv-ps-mem-0 = <0x11170>;
  242. xlnx,tavdv-ps-mem-1 = <0x3a98>;
  243. xlnx,tavdv-ps-mem-2 = <0x3a98>;
  244. xlnx,tavdv-ps-mem-3 = <0x3a98>;
  245. - xlnx,tcedv-ps-mem-0 = <0x1adb0>;
  246. + xlnx,tcedv-ps-mem-0 = <0x11170>;
  247. xlnx,tcedv-ps-mem-1 = <0x3a98>;
  248. xlnx,tcedv-ps-mem-2 = <0x3a98>;
  249. xlnx,tcedv-ps-mem-3 = <0x3a98>;
  250. - xlnx,thzce-ps-mem-0 = <0x88b8>;
  251. + xlnx,thzce-ps-mem-0 = <0x61a8>;
  252. xlnx,thzce-ps-mem-1 = <0x1b58>;
  253. xlnx,thzce-ps-mem-2 = <0x1b58>;
  254. xlnx,thzce-ps-mem-3 = <0x1b58>;
  255. - xlnx,thzoe-ps-mem-0 = <0x1b58>;
  256. + xlnx,thzoe-ps-mem-0 = <0x61a8>;
  257. xlnx,thzoe-ps-mem-1 = <0x1b58>;
  258. xlnx,thzoe-ps-mem-2 = <0x1b58>;
  259. xlnx,thzoe-ps-mem-3 = <0x1b58>;
  260. - xlnx,tlzwe-ps-mem-0 = <0x88b8>;
  261. + xlnx,tlzwe-ps-mem-0 = <0x1388>;
  262. xlnx,tlzwe-ps-mem-1 = <0x0>;
  263. xlnx,tlzwe-ps-mem-2 = <0x0>;
  264. xlnx,tlzwe-ps-mem-3 = <0x0>;
  265. - xlnx,twc-ps-mem-0 = <0x2af8>;
  266. + xlnx,twc-ps-mem-0 = <0x11170>;
  267. xlnx,twc-ps-mem-1 = <0x3a98>;
  268. xlnx,twc-ps-mem-2 = <0x3a98>;
  269. xlnx,twc-ps-mem-3 = <0x3a98>;
  270. - xlnx,twp-ps-mem-0 = <0x11170>;
  271. + xlnx,twp-ps-mem-0 = <0xafc8>;
  272. xlnx,twp-ps-mem-1 = <0x2ee0>;
  273. xlnx,twp-ps-mem-2 = <0x2ee0>;
  274. xlnx,twp-ps-mem-3 = <0x2ee0>;
  275. @@ -214,154 +199,83 @@
  276. xlnx,xcl2-writexfer = <0x1>;
  277. xlnx,xcl3-linesize = <0x4>;
  278. xlnx,xcl3-writexfer = <0x1>;
  279. - } ;
  280. - Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
  281. - #address-cells = <1>;
  282. - #size-cells = <1>;
  283. - compatible = "xlnx,compound";
  284. - ranges ;
  285. - ethernet@81c00000 {
  286. - compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
  287. - device_type = "network";
  288. - interrupt-parent = <&xps_intc_0>;
  289. - interrupts = < 5 2 >;
  290. - llink-connected = <&PIM3>;
  291. - local-mac-address = [ 00 0a 35 00 00 00 ];
  292. - reg = < 0x81c00000 0x40 >;
  293. - xlnx,bus2core-clk-ratio = <0x1>;
  294. - xlnx,phy-type = <0x1>;
  295. - xlnx,phyaddr = <0x1>;
  296. - xlnx,rxcsum = <0x0>;
  297. - xlnx,rxfifo = <0x1000>;
  298. - xlnx,temac-type = <0x0>;
  299. - xlnx,txcsum = <0x0>;
  300. - xlnx,txfifo = <0x1000>;
  301. - } ;
  302. - } ;
  303. - IIC_EEPROM: i2c@81600000 {
  304. - compatible = "xlnx,xps-iic-2.00.a";
  305. - interrupt-parent = <&xps_intc_0>;
  306. - interrupts = < 6 2 >;
  307. - reg = < 0x81600000 0x10000 >;
  308. - xlnx,clk-freq = <0x7735940>;
  309. - xlnx,family = "virtex5";
  310. - xlnx,gpo-width = <0x1>;
  311. - xlnx,iic-freq = <0x186a0>;
  312. - xlnx,scl-inertial-delay = <0x0>;
  313. - xlnx,sda-inertial-delay = <0x0>;
  314. - xlnx,ten-bit-adr = <0x0>;
  315. - } ;
  316. - LEDs_8Bit: gpio@81400000 {
  317. + };
  318. +
  319. + gpio@81400000 {
  320. compatible = "xlnx,xps-gpio-1.00.a";
  321. - interrupt-parent = <&xps_intc_0>;
  322. - interrupts = < 7 2 >;
  323. - reg = < 0x81400000 0x10000 >;
  324. + interrupt-parent = <0x1>;
  325. + interrupts = <0x2 0x2>;
  326. + reg = <0x81400000 0x10000>;
  327. xlnx,all-inputs = <0x0>;
  328. xlnx,all-inputs-2 = <0x0>;
  329. xlnx,dout-default = <0x0>;
  330. xlnx,dout-default-2 = <0x0>;
  331. - xlnx,family = "virtex5";
  332. + xlnx,family = "spartan3adsp";
  333. xlnx,gpio-width = <0x8>;
  334. xlnx,interrupt-present = <0x1>;
  335. - xlnx,is-bidir = <0x1>;
  336. + xlnx,is-bidir = <0x0>;
  337. xlnx,is-bidir-2 = <0x1>;
  338. xlnx,is-dual = <0x0>;
  339. xlnx,tri-default = <0xffffffff>;
  340. xlnx,tri-default-2 = <0xffffffff>;
  341. - #gpio-cells = <2>;
  342. - gpio-controller;
  343. - } ;
  344. -
  345. - gpio-leds {
  346. - compatible = "gpio-leds";
  347. -
  348. - heartbeat {
  349. - label = "Heartbeat";
  350. - gpios = <&LEDs_8Bit 4 1>;
  351. - linux,default-trigger = "heartbeat";
  352. - };
  353. -
  354. - yellow {
  355. - label = "Yellow";
  356. - gpios = <&LEDs_8Bit 5 1>;
  357. - };
  358. -
  359. - red {
  360. - label = "Red";
  361. - gpios = <&LEDs_8Bit 6 1>;
  362. - };
  363. -
  364. - green {
  365. - label = "Green";
  366. - gpios = <&LEDs_8Bit 7 1>;
  367. - };
  368. - } ;
  369. - RS232_Uart_1: serial@84000000 {
  370. - clock-frequency = <125000000>;
  371. + };
  372. +
  373. + serial@84000000 {
  374. + clock-frequency = <0x3b9aca0>;
  375. compatible = "xlnx,xps-uartlite-1.00.a";
  376. - current-speed = <115200>;
  377. + current-speed = <0x1c200>;
  378. device_type = "serial";
  379. - interrupt-parent = <&xps_intc_0>;
  380. - interrupts = < 8 0 >;
  381. - port-number = <0>;
  382. - reg = < 0x84000000 0x10000 >;
  383. + interrupt-parent = <0x1>;
  384. + interrupts = <0x3 0x0>;
  385. + port-number = <0x0>;
  386. + reg = <0x84000000 0x10000>;
  387. xlnx,baudrate = <0x1c200>;
  388. xlnx,data-bits = <0x8>;
  389. - xlnx,family = "virtex5";
  390. + xlnx,family = "spartan3adsp";
  391. xlnx,odd-parity = <0x0>;
  392. xlnx,use-parity = <0x0>;
  393. - } ;
  394. - SysACE_CompactFlash: sysace@83600000 {
  395. - compatible = "xlnx,xps-sysace-1.00.a";
  396. - interrupt-parent = <&xps_intc_0>;
  397. - interrupts = < 4 2 >;
  398. - reg = < 0x83600000 0x10000 >;
  399. - xlnx,family = "virtex5";
  400. - xlnx,mem-width = <0x10>;
  401. - } ;
  402. - debug_module: debug@84400000 {
  403. + };
  404. +
  405. + debug@84400000 {
  406. compatible = "xlnx,mdm-1.00.d";
  407. - reg = < 0x84400000 0x10000 >;
  408. - xlnx,family = "virtex5";
  409. + reg = <0x84400000 0x10000>;
  410. + xlnx,family = "spartan3adsp";
  411. xlnx,interconnect = <0x1>;
  412. xlnx,jtag-chain = <0x2>;
  413. xlnx,mb-dbg-ports = <0x1>;
  414. xlnx,uart-width = <0x8>;
  415. xlnx,use-uart = <0x1>;
  416. xlnx,write-fsl-ports = <0x0>;
  417. - } ;
  418. + };
  419. +
  420. mpmc@90000000 {
  421. - #address-cells = <1>;
  422. - #size-cells = <1>;
  423. - compatible = "xlnx,mpmc-4.02.a";
  424. - ranges ;
  425. - PIM3: sdma@84600180 {
  426. - compatible = "xlnx,ll-dma-1.00.a";
  427. - interrupt-parent = <&xps_intc_0>;
  428. - interrupts = < 2 2 1 2 >;
  429. - reg = < 0x84600180 0x80 >;
  430. - } ;
  431. - } ;
  432. - xps_intc_0: interrupt-controller@81800000 {
  433. + #address-cells = <0x1>;
  434. + #size-cells = <0x1>;
  435. + compatible = "xlnx,mpmc-4.03.a";
  436. + };
  437. +
  438. + interrupt-controller@81800000 {
  439. #interrupt-cells = <0x2>;
  440. compatible = "xlnx,xps-intc-1.00.a";
  441. - interrupt-controller ;
  442. - reg = < 0x81800000 0x10000 >;
  443. - xlnx,kind-of-intr = <0x100>;
  444. - xlnx,num-intr-inputs = <0x9>;
  445. - } ;
  446. - xps_timer_1: timer@83c00000 {
  447. + interrupt-controller;
  448. + reg = <0x81800000 0x10000>;
  449. + xlnx,kind-of-intr = <0xa>;
  450. + xlnx,num-intr-inputs = <0x4>;
  451. + linux,phandle = <0x1>;
  452. + };
  453. +
  454. + timer@83c00000 {
  455. compatible = "xlnx,xps-timer-1.00.a";
  456. - interrupt-parent = <&xps_intc_0>;
  457. - interrupts = < 3 2 >;
  458. - reg = < 0x83c00000 0x10000 >;
  459. + interrupt-parent = <0x1>;
  460. + interrupts = <0x0 0x2>;
  461. + reg = <0x83c00000 0x10000>;
  462. xlnx,count-width = <0x20>;
  463. - xlnx,family = "virtex5";
  464. + xlnx,family = "spartan3adsp";
  465. xlnx,gen0-assert = <0x1>;
  466. xlnx,gen1-assert = <0x1>;
  467. xlnx,one-timer-only = <0x0>;
  468. xlnx,trig0-assert = <0x1>;
  469. xlnx,trig1-assert = <0x1>;
  470. - } ;
  471. - } ;
  472. -} ;
  473. + };
  474. + };
  475. +};