or1ksim.cfg 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887
  1. /* sim.cfg -- Simulator configuration script file
  2. Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
  3. This file is part of OpenRISC 1000 Architectural Simulator.
  4. It contains the default configuration and help about configuring
  5. the simulator.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program; if not, write to the Free Software
  16. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
  17. /* INTRODUCTION
  18. The ork1sim has various parameters, that are set in configuration files
  19. like this one. The user can switch between configurations at startup by
  20. specifying the required configuration file with the -f <filename.cfg> option.
  21. If no configuration file is specified or1ksim searches for the default
  22. configuration file sim.cfg. First it searches for './sim.cfg'. If this
  23. file is not found, it searches for '~/or1k/sim.cfg'. If this file is
  24. not found too, it reverts to the built-in default configuration.
  25. NOTE: Users should not rely on the built-in configuration, since the
  26. default configuration may differ between version.
  27. Rather create a configuration file that sets all critical values.
  28. This file may contain (standard C) comments only - no // support.
  29. Configure files may be be included, using:
  30. include "file_name_to_include"
  31. Like normal configuration files, the included file is divided into
  32. sections. Each section is described in detail also.
  33. Some section have subsections. One example of such a subsection is:
  34. device <index>
  35. instance specific parameters...
  36. enddevice
  37. which creates a device instance.
  38. */
  39. /* MEMORY SECTION
  40. This section specifies how the memory is generated and the blocks
  41. it consists of.
  42. type = random/unknown/pattern
  43. Specifies the initial memory values.
  44. 'random' generates random memory using seed 'random_seed'.
  45. 'pattern' fills memory with 'pattern'.
  46. 'unknown' does not specify how memory should be generated,
  47. leaving the memory in a undefined state. This is the fastest
  48. option.
  49. random_seed = <value>
  50. random seed for randomizer, used if type = 'random'.
  51. pattern = <value>
  52. pattern to fill memory, used if type = 'pattern'.
  53. nmemories = <value>
  54. number of memory instances connected
  55. baseaddr = <hex_value>
  56. memory start address
  57. size = <hex_value>
  58. memory size
  59. name = "<string>"
  60. memory block name
  61. ce = <value>
  62. chip enable index of the memory instance
  63. mc = <value>
  64. memory controller this memory is connected to
  65. delayr = <value>
  66. cycles, required for read access, -1 if instance does not support reading
  67. delayw = <value>
  68. cycles, required for write access, -1 if instance does not support writing
  69. log = "<filename>"
  70. filename, where to log memory accesses to, no log, if log command is not specified
  71. */
  72. section memory
  73. /*random_seed = 12345
  74. type = random*/
  75. pattern = 0x00
  76. type = unknown /* Fastest */
  77. name = "FLASH"
  78. ce = 0
  79. mc = 0
  80. baseaddr = 0xf0000000
  81. size = 0x01000000
  82. delayr = 1
  83. delayw = -1
  84. end
  85. section memory
  86. /*random_seed = 12345
  87. type = random*/
  88. pattern = 0x00
  89. type = unknown /* Fastest */
  90. name = "RAM"
  91. ce = 1
  92. mc = 0
  93. baseaddr = 0x00000000
  94. size = 0x02000000
  95. delayr = 1
  96. delayw = 1
  97. end
  98. section memory
  99. /*random_seed = 12345
  100. type = random*/
  101. pattern = 0x00
  102. type = unknown /* Fastest */
  103. name = "SRAM"
  104. mc = 0
  105. ce = 2
  106. baseaddr = 0xa4000000
  107. size = 0x00100000
  108. delayr = 1
  109. delayw = 2
  110. end
  111. /* IMMU SECTION
  112. This section configures the Instruction Memory Manangement Unit
  113. enabled = 0/1
  114. '0': disabled
  115. '1': enabled
  116. (NOTE: UPR bit is set)
  117. nsets = <value>
  118. number of ITLB sets; must be power of two
  119. nways = <value>
  120. number of ITLB ways
  121. pagesize = <value>
  122. instruction page size; must be power of two
  123. entrysize = <value>
  124. instruction entry size in bytes
  125. ustates = <value>
  126. number of ITLB usage states (2, 3, 4 etc., max is 4)
  127. hitdelay = <value>
  128. number of cycles immu hit costs
  129. missdelay = <value>
  130. number of cycles immu miss costs
  131. */
  132. section immu
  133. enabled = 1
  134. nsets = 64
  135. nways = 1
  136. pagesize = 8192
  137. hitdelay = 0
  138. missdelay = 0
  139. end
  140. /* DMMU SECTION
  141. This section configures the Data Memory Manangement Unit
  142. enabled = 0/1
  143. '0': disabled
  144. '1': enabled
  145. (NOTE: UPR bit is set)
  146. nsets = <value>
  147. number of DTLB sets; must be power of two
  148. nways = <value>
  149. number of DTLB ways
  150. pagesize = <value>
  151. data page size; must be power of two
  152. entrysize = <value>
  153. data entry size in bytes
  154. ustates = <value>
  155. number of DTLB usage states (2, 3, 4 etc., max is 4)
  156. hitdelay = <value>
  157. number of cycles dmmu hit costs
  158. missdelay = <value>
  159. number of cycles dmmu miss costs
  160. */
  161. section dmmu
  162. enabled = 1
  163. nsets = 64
  164. nways = 1
  165. pagesize = 8192
  166. hitdelay = 0
  167. missdelay = 0
  168. end
  169. /* IC SECTION
  170. This section configures the Instruction Cache
  171. enabled = 0/1
  172. '0': disabled
  173. '1': enabled
  174. (NOTE: UPR bit is set)
  175. nsets = <value>
  176. number of IC sets; must be power of two
  177. nways = <value>
  178. number of IC ways
  179. blocksize = <value>
  180. IC block size in bytes; must be power of two
  181. ustates = <value>
  182. number of IC usage states (2, 3, 4 etc., max is 4)
  183. hitdelay = <value>
  184. number of cycles ic hit costs
  185. missdelay = <value>
  186. number of cycles ic miss costs
  187. */
  188. section ic
  189. enabled = 0
  190. nsets = 512
  191. nways = 1
  192. blocksize = 16
  193. hitdelay = 1
  194. missdelay = 1
  195. end
  196. /* DC SECTION
  197. This section configures the Data Cache
  198. enabled = 0/1
  199. '0': disabled
  200. '1': enabled
  201. (NOTE: UPR bit is set)
  202. nsets = <value>
  203. number of DC sets; must be power of two
  204. nways = <value>
  205. number of DC ways
  206. blocksize = <value>
  207. DC block size in bytes; must be power of two
  208. ustates = <value>
  209. number of DC usage states (2, 3, 4 etc., max is 4)
  210. load_hitdelay = <value>
  211. number of cycles dc load hit costs
  212. load_missdelay = <value>
  213. number of cycles dc load miss costs
  214. store_hitdelay = <value>
  215. number of cycles dc load hit costs
  216. store_missdelay = <value>
  217. number of cycles dc load miss costs
  218. */
  219. section dc
  220. enabled = 0
  221. nsets = 512
  222. nways = 1
  223. blocksize = 16
  224. load_hitdelay = 1
  225. load_missdelay = 1
  226. store_hitdelay = 1
  227. store_missdelay = 1
  228. end
  229. /* SIM SECTION
  230. This section specifies how or1ksim should behave.
  231. verbose = 0/1
  232. '0': don't print extra messages
  233. '1': print extra messages
  234. debug = 0-9
  235. 0 : no debug messages
  236. 1-9: debug message level.
  237. higher numbers produce more messages
  238. profile = 0/1
  239. '0': don't generate profiling file 'sim.profile'
  240. '1': don't generate profiling file 'sim.profile'
  241. prof_fn = "<filename>"
  242. optional filename for the profiling file.
  243. valid only if 'profile' is set
  244. mprofile = 0/1
  245. '0': don't generate memory profiling file 'sim.mprofile'
  246. '1': generate memory profiling file 'sim.mprofile'
  247. mprof_fn = "<filename>"
  248. optional filename for the memory profiling file.
  249. valid only if 'mprofile' is set
  250. history = 0/1
  251. '0': don't track execution flow
  252. '1': track execution flow
  253. Execution flow can be tracked for the simulator's
  254. 'hist' command. Useful for back-trace debugging.
  255. iprompt = 0/1
  256. '0': start in <not interactive prompt> (so what do we start in ???)
  257. '1': start in interactive prompt.
  258. exe_log = 0/1
  259. '0': don't generate execution log.
  260. '1': generate execution log.
  261. exe_log = default/hardware/simple/software
  262. type of execution log, default is used when not specified
  263. exe_log_start = <value>
  264. index of first instruction to start logging, default = 0
  265. exe_log_end = <value>
  266. index of last instruction to end logging; not limited, if omitted
  267. exe_log_marker = <value>
  268. <value> specifies number of instructions before horizontal marker is
  269. printed; if zero, markers are disabled (default)
  270. exe_log_fn = "<filename>"
  271. filename for the exection log file.
  272. valid only if 'exe_log' is set
  273. clkcycle = <value>[ps|ns|us|ms]
  274. specifies time measurement for one cycle
  275. */
  276. section sim
  277. verbose = 1
  278. debug = 0
  279. profile = 0
  280. history = 0
  281. clkcycle = 10ns
  282. end
  283. /* SECTION VAPI
  284. This section configures the Verification API, used for Advanced
  285. Core Verification.
  286. enabled = 0/1
  287. '0': disbable VAPI server
  288. '1': enable/start VAPI server
  289. server_port = <value>
  290. TCP/IP port to start VAPI server on
  291. log_enabled = 0/1
  292. '0': disable VAPI requests logging
  293. '1': enable VAPI requests logging
  294. hide_device_id = 0/1
  295. '0': don't log device id (for compatability with old version)
  296. '1': log device id
  297. vapi_fn = <filename>
  298. filename for the log file.
  299. valid only if log_enabled is set
  300. */
  301. section VAPI
  302. enabled = 0
  303. server_port = 9998
  304. log_enabled = 0
  305. vapi_log_fn = "vapi.log"
  306. end
  307. /* CPU SECTION
  308. This section specifies various CPU parameters.
  309. ver = <value>
  310. rev = <value>
  311. specifies version and revision of the CPU used
  312. upr = <value>
  313. changes the upr register
  314. sr = <value>
  315. sets the initial Supervision Register value
  316. supervisor mode (SM) and fixed one (FO) set = 0x8001
  317. exception prefix high (EPH, vectors@0xf0000000) = 0x4000
  318. together, (SM | FO | EPH) = 0xc001
  319. superscalar = 0/1
  320. '0': CPU is scalar
  321. '1': CPU is superscalar
  322. (modify cpu/or32/execute.c to tune superscalar model)
  323. hazards = 0/1
  324. '0': don't track data hazards in superscalar CPU
  325. '1': track data hazards in superscalar CPU
  326. If tracked, data hazards can be displayed using the
  327. simulator's 'r' command.
  328. dependstats = 0/1
  329. '0': don't calculate inter-instruction dependencies.
  330. '1': calculate inter-instruction dependencies.
  331. If calculated, inter-instruction dependencies can be
  332. displayed using the simulator's 'stat' command.
  333. sbuf_len = <value>
  334. length of store buffer (<= 256), 0 = disabled
  335. */
  336. section cpu
  337. ver = 0x12
  338. cfg = 0x00
  339. rev = 0x01
  340. sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */
  341. /* upr = */
  342. superscalar = 0
  343. hazards = 0
  344. dependstats = 0
  345. sbuf_len = 0
  346. end
  347. /* PM SECTION
  348. This section specifies Power Management parameters
  349. enabled = 0/1
  350. '0': disable power management
  351. '1': enable power management
  352. */
  353. section pm
  354. enabled = 0
  355. end
  356. /* BPB SECTION
  357. This section specifies how branch prediction should behave.
  358. enabled = 0/1
  359. '0': disable branch prediction
  360. '1': enable branch prediction
  361. btic = 0/1
  362. '0': disable branch target instruction cache model
  363. '1': enable branch target instruction cache model
  364. sbp_bf_fwd = 0/1
  365. Static branch prediction for 'l.bf'
  366. '0': don't use forward prediction
  367. '1': use forward prediction
  368. sbp_bnf_fwd = 0/1
  369. Static branch prediction for 'l.bnf'
  370. '0': don't use forward prediction
  371. '1': use forward prediction
  372. hitdelay = <value>
  373. number of cycles bpb hit costs
  374. missdelay = <value>
  375. number of cycles bpb miss costs
  376. */
  377. section bpb
  378. enabled = 0
  379. btic = 0
  380. sbp_bf_fwd = 0
  381. sbp_bnf_fwd = 0
  382. hitdelay = 0
  383. missdelay = 0
  384. end
  385. /* DEBUG SECTION
  386. This sections specifies how the debug unit should behave.
  387. enabled = 0/1
  388. '0': disable debug unit
  389. '1': enable debug unit
  390. gdb_enabled = 0/1
  391. '0': don't start gdb server
  392. '1': start gdb server at port 'server_port'
  393. server_port = <value>
  394. TCP/IP port to start gdb server on
  395. valid only if gdb_enabled is set
  396. vapi_id = <hex_value>
  397. Used to create "fake" vapi log file containing the JTAG proxy messages.
  398. */
  399. section debug
  400. enabled = 0
  401. /* gdb_enabled = 0 */
  402. /* server_port = 9999*/
  403. rsp_enabled = 1
  404. rsp_port = 50001
  405. end
  406. /* MC SECTION
  407. This section configures the memory controller
  408. enabled = 0/1
  409. '0': disable memory controller
  410. '1': enable memory controller
  411. baseaddr = <hex_value>
  412. address of first MC register
  413. POC = <hex_value>
  414. Power On Configuration register
  415. index = <value>
  416. Index of this memory controller amongst all the memory controllers
  417. */
  418. section mc
  419. enabled = 0
  420. baseaddr = 0x93000000
  421. POC = 0x00000008 /* Power on configuration register */
  422. index = 0
  423. end
  424. /* UART SECTION
  425. This section configures the UARTs
  426. enabled = <0|1>
  427. Enable/disable the peripheral. By default if it is enabled.
  428. baseaddr = <hex_value>
  429. address of first UART register for this device
  430. channel = <channeltype>:<args>
  431. The channel parameter indicates the source of received UART characters
  432. and the sink for transmitted UART characters.
  433. The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
  434. (without quotes).
  435. A) To send/receive characters from a pair of files, use a file
  436. channel:
  437. channel=file:<rxfile>,<txfile>
  438. B) To create an interactive terminal window, use an xterm channel:
  439. channel=xterm:[<xterm_arg>]*
  440. C) To create a bidirectional tcp socket which one could, for example,
  441. access via telnet, use a tcp channel:
  442. channel=tcp:<port number>
  443. D) To cause the UART to read/write from existing numeric file
  444. descriptors, use an fd channel:
  445. channel=fd:<rx file descriptor num>,<tx file descriptor num>
  446. E) To connect the UART to a physical serial port, create a tty
  447. channel:
  448. channel=tty:device=/dev/ttyS0,baud=9600
  449. irq = <value>
  450. irq number for this device
  451. 16550 = 0/1
  452. '0': this device is a UART16450
  453. '1': this device is a UART16550
  454. jitter = <value>
  455. in msecs... time to block, -1 to disable it
  456. vapi_id = <hex_value>
  457. VAPI id of this instance
  458. */
  459. section uart
  460. enabled = 1
  461. baseaddr = 0x90000000
  462. irq = 2
  463. /* channel = "file:uart0.rx,uart0.tx" */
  464. channel = "xterm:"
  465. jitter = -1 /* async behaviour */
  466. 16550 = 1
  467. end
  468. /* DMA SECTION
  469. This section configures the DMAs
  470. enabled = <0|1>
  471. Enable/disable the peripheral. By default if it is enabled.
  472. baseaddr = <hex_value>
  473. address of first DMA register for this device
  474. irq = <value>
  475. irq number for this device
  476. vapi_id = <hex_value>
  477. VAPI id of this instance
  478. */
  479. section dma
  480. enabled = 1
  481. baseaddr = 0x9a000000
  482. irq = 11
  483. end
  484. /* ETHERNET SECTION
  485. This section configures the ETHERNETs
  486. enabled = <0|1>
  487. Enable/disable the peripheral. By default if it is enabled.
  488. baseaddr = <hex_value>
  489. address of first ethernet register for this device
  490. dma = <value>
  491. which controller is this ethernet "connected" to
  492. irq = <value>
  493. ethernet mac IRQ level
  494. rtx_type = <value>
  495. use 0 - file interface, 1 - socket interface
  496. rx_channel = <value>
  497. DMA channel used for RX
  498. tx_channel = <value>
  499. DMA channel used for TX
  500. rxfile = "<filename>"
  501. filename, where to read data from
  502. txfile = "<filename>"
  503. filename, where to write data to
  504. sockif = "<ifacename>"
  505. interface name of ethernet socket
  506. vapi_id = <hex_value>
  507. VAPI id of this instance
  508. */
  509. section ethernet
  510. enabled = 0
  511. baseaddr = 0x92000000
  512. /* dma = 0 */
  513. irq = 4
  514. rtx_type = "tap"
  515. tap_dev = "tap0"
  516. /* tx_channel = 0 */
  517. /* rx_channel = 1 */
  518. rxfile = "eth0.rx"
  519. txfile = "eth0.tx"
  520. sockif = "eth0"
  521. end
  522. /* GPIO SECTION
  523. This section configures the GPIOs
  524. enabled = <0|1>
  525. Enable/disable the peripheral. By default if it is enabled.
  526. baseaddr = <hex_value>
  527. address of first GPIO register for this device
  528. irq = <value>
  529. irq number for this device
  530. base_vapi_id = <hex_value>
  531. first VAPI id of this instance
  532. GPIO uses 8 consecutive VAPI IDs
  533. */
  534. section gpio
  535. enabled = 0
  536. baseaddr = 0x91000000
  537. irq = 3
  538. base_vapi_id = 0x0200
  539. end
  540. /* VGA SECTION
  541. This section configures the VGA/LCD controller
  542. enabled = <0|1>
  543. Enable/disable the peripheral. By default if it is enabled.
  544. baseaddr = <hex_value>
  545. address of first VGA register
  546. irq = <value>
  547. irq number for this device
  548. refresh_rate = <value>
  549. number of cycles between screen dumps
  550. filename = "<filename>"
  551. template name for generated names (e.g. "primary" produces "primary0023.bmp")
  552. */
  553. section vga
  554. enabled = 0
  555. baseaddr = 0x97100000
  556. irq = 8
  557. refresh_rate = 100000
  558. filename = "primary"
  559. end
  560. /* TICK TIMER SECTION
  561. This section configures tick timer
  562. enabled = 0/1
  563. whether tick timer is enabled
  564. */
  565. section pic
  566. enabled = 1
  567. edge_trigger = 1
  568. end
  569. /* FB SECTION
  570. This section configures the frame buffer
  571. enabled = <0|1>
  572. Enable/disable the peripheral. By default if it is enabled.
  573. baseaddr = <hex_value>
  574. base address of frame buffer
  575. paladdr = <hex_value>
  576. base address of first palette entry
  577. refresh_rate = <value>
  578. number of cycles between screen dumps
  579. filename = "<filename>"
  580. template name for generated names (e.g. "primary" produces "primary0023.bmp")
  581. */
  582. section fb
  583. enabled = 0
  584. baseaddr = 0x97000000
  585. refresh_rate = 1000000
  586. filename = "primary"
  587. end
  588. /* KBD SECTION
  589. This section configures the PS/2 compatible keyboard
  590. baseaddr = <hex_value>
  591. base address of the keyboard device
  592. rxfile = "<filename>"
  593. filename, where to read data from
  594. */
  595. section kbd
  596. enabled = 0
  597. irq = 5
  598. baseaddr = 0x94000000
  599. rxfile = "kbd.rx"
  600. end
  601. /* ATA SECTION
  602. This section configures the ATA/ATAPI host controller
  603. baseaddr = <hex_value>
  604. address of first ATA register
  605. enabled = <0|1>
  606. Enable/disable the peripheral. By default if it is enabled.
  607. irq = <value>
  608. irq number for this device
  609. debug = <value>
  610. debug level for ata models.
  611. 0: no debug messages
  612. 1: verbose messages
  613. 3: normal messages (more messages than verbose)
  614. 5: debug messages (normal debug messages)
  615. 7: flow control messages (debug statemachine flows)
  616. 9: low priority message (display everything the code does)
  617. dev_type0/1 = <value>
  618. ata device 0 type
  619. 0: NO_CONNeCT: none (not connected)
  620. 1: FILE : simulated harddisk
  621. 2: LOCAL : local system harddisk
  622. dev_file0/1 = "<filename>"
  623. filename for simulated ATA device
  624. valid only if dev_type0 == 1
  625. dev_size0/1 = <value>
  626. size of simulated hard-disk (in MBytes)
  627. valid only if dev_type0 == 1
  628. dev_packet0/1 = <value>
  629. 0: simulated ATA device does NOT implement PACKET command feature set
  630. 1: simulated ATA device does implement PACKET command feature set
  631. FIXME: irq number
  632. */
  633. section ata
  634. enabled = 0
  635. baseaddr = 0x9e000000
  636. irq = 15
  637. end