0003-net-add-ag71xx-mac-driver.patch 108 KB

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  1. From c5eb03f91f9185f4813431692f36db3862716a35 Mon Sep 17 00:00:00 2001
  2. From: Phil Sutter <phil@nwl.cc>
  3. Date: Tue, 13 May 2014 00:12:37 +0200
  4. Subject: [PATCH] net: add ag71xx mac driver
  5. ---
  6. arch/mips/include/asm/mach-ath79/ag71xx_platform.h | 65 +
  7. drivers/net/ethernet/atheros/Kconfig | 2 +
  8. drivers/net/ethernet/atheros/Makefile | 1 +
  9. drivers/net/ethernet/atheros/ag71xx/Kconfig | 33 +
  10. drivers/net/ethernet/atheros/ag71xx/Makefile | 15 +
  11. drivers/net/ethernet/atheros/ag71xx/ag71xx.h | 476 +++++++
  12. .../net/ethernet/atheros/ag71xx/ag71xx_ar7240.c | 1202 ++++++++++++++++++
  13. .../net/ethernet/atheros/ag71xx/ag71xx_ar8216.c | 44 +
  14. .../net/ethernet/atheros/ag71xx/ag71xx_debugfs.c | 284 +++++
  15. .../net/ethernet/atheros/ag71xx/ag71xx_ethtool.c | 124 ++
  16. drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c | 1325 ++++++++++++++++++++
  17. drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c | 318 +++++
  18. drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c | 235 ++++
  19. 13 files changed, 4124 insertions(+)
  20. create mode 100644 arch/mips/include/asm/mach-ath79/ag71xx_platform.h
  21. create mode 100644 drivers/net/ethernet/atheros/ag71xx/Kconfig
  22. create mode 100644 drivers/net/ethernet/atheros/ag71xx/Makefile
  23. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx.h
  24. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
  25. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c
  26. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c
  27. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c
  28. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
  29. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c
  30. create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
  31. diff --git a/arch/mips/include/asm/mach-ath79/ag71xx_platform.h b/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
  32. new file mode 100644
  33. index 0000000..d46dc4e
  34. --- /dev/null
  35. +++ b/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
  36. @@ -0,0 +1,65 @@
  37. +/*
  38. + * Atheros AR71xx SoC specific platform data definitions
  39. + *
  40. + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  41. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  42. + *
  43. + * This program is free software; you can redistribute it and/or modify it
  44. + * under the terms of the GNU General Public License version 2 as published
  45. + * by the Free Software Foundation.
  46. + */
  47. +
  48. +#ifndef __ASM_MACH_ATH79_PLATFORM_H
  49. +#define __ASM_MACH_ATH79_PLATFORM_H
  50. +
  51. +#include <linux/if_ether.h>
  52. +#include <linux/skbuff.h>
  53. +#include <linux/phy.h>
  54. +#include <linux/spi/spi.h>
  55. +
  56. +struct ag71xx_switch_platform_data {
  57. + u8 phy4_mii_en:1;
  58. + u8 phy_poll_mask;
  59. +};
  60. +
  61. +struct ag71xx_platform_data {
  62. + phy_interface_t phy_if_mode;
  63. + u32 phy_mask;
  64. + int speed;
  65. + int duplex;
  66. + u32 reset_bit;
  67. + u8 mac_addr[ETH_ALEN];
  68. + struct device *mii_bus_dev;
  69. +
  70. + u8 has_gbit:1;
  71. + u8 is_ar91xx:1;
  72. + u8 is_ar7240:1;
  73. + u8 is_ar724x:1;
  74. + u8 has_ar8216:1;
  75. +
  76. + struct ag71xx_switch_platform_data *switch_data;
  77. +
  78. + void (*ddr_flush)(void);
  79. + void (*set_speed)(int speed);
  80. +
  81. + u32 fifo_cfg1;
  82. + u32 fifo_cfg2;
  83. + u32 fifo_cfg3;
  84. +
  85. + unsigned int max_frame_len;
  86. + unsigned int desc_pktlen_mask;
  87. +};
  88. +
  89. +struct ag71xx_mdio_platform_data {
  90. + u32 phy_mask;
  91. + u8 builtin_switch:1;
  92. + u8 is_ar7240:1;
  93. + u8 is_ar9330:1;
  94. + u8 is_ar934x:1;
  95. + unsigned long mdio_clock;
  96. + unsigned long ref_clock;
  97. +
  98. + void (*reset)(struct mii_bus *bus);
  99. +};
  100. +
  101. +#endif /* __ASM_MACH_ATH79_PLATFORM_H */
  102. diff --git a/drivers/net/ethernet/atheros/Kconfig b/drivers/net/ethernet/atheros/Kconfig
  103. index 58ad37c..1fae572 100644
  104. --- a/drivers/net/ethernet/atheros/Kconfig
  105. +++ b/drivers/net/ethernet/atheros/Kconfig
  106. @@ -80,4 +80,6 @@ config ALX
  107. To compile this driver as a module, choose M here. The module
  108. will be called alx.
  109. +source drivers/net/ethernet/atheros/ag71xx/Kconfig
  110. +
  111. endif # NET_VENDOR_ATHEROS
  112. diff --git a/drivers/net/ethernet/atheros/Makefile b/drivers/net/ethernet/atheros/Makefile
  113. index 5cf1c65..d1c5a49 100644
  114. --- a/drivers/net/ethernet/atheros/Makefile
  115. +++ b/drivers/net/ethernet/atheros/Makefile
  116. @@ -2,6 +2,7 @@
  117. # Makefile for the Atheros network device drivers.
  118. #
  119. +obj-$(CONFIG_AG71XX) += ag71xx/
  120. obj-$(CONFIG_ATL1) += atlx/
  121. obj-$(CONFIG_ATL2) += atlx/
  122. obj-$(CONFIG_ATL1E) += atl1e/
  123. diff --git a/drivers/net/ethernet/atheros/ag71xx/Kconfig b/drivers/net/ethernet/atheros/ag71xx/Kconfig
  124. new file mode 100644
  125. index 0000000..42d544f
  126. --- /dev/null
  127. +++ b/drivers/net/ethernet/atheros/ag71xx/Kconfig
  128. @@ -0,0 +1,33 @@
  129. +config AG71XX
  130. + tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
  131. + depends on ATH79
  132. + select PHYLIB
  133. + help
  134. + If you wish to compile a kernel for AR7XXX/91XXX and enable
  135. + ethernet support, then you should always answer Y to this.
  136. +
  137. +if AG71XX
  138. +
  139. +config AG71XX_DEBUG
  140. + bool "Atheros AR71xx built-in ethernet driver debugging"
  141. + default n
  142. + help
  143. + Atheros AR71xx built-in ethernet driver debugging messages.
  144. +
  145. +config AG71XX_DEBUG_FS
  146. + bool "Atheros AR71xx built-in ethernet driver debugfs support"
  147. + depends on DEBUG_FS
  148. + default n
  149. + help
  150. + Say Y, if you need access to various statistics provided by
  151. + the ag71xx driver.
  152. +
  153. +config AG71XX_AR8216_SUPPORT
  154. + bool "special support for the Atheros AR8216 switch"
  155. + default n
  156. + default y if ATH79_MACH_WNR2000 || ATH79_MACH_MZK_W04NU
  157. + help
  158. + Say 'y' here if you want to enable special support for the
  159. + Atheros AR8216 switch found on some boards.
  160. +
  161. +endif
  162. diff --git a/drivers/net/ethernet/atheros/ag71xx/Makefile b/drivers/net/ethernet/atheros/ag71xx/Makefile
  163. new file mode 100644
  164. index 0000000..b3ec408
  165. --- /dev/null
  166. +++ b/drivers/net/ethernet/atheros/ag71xx/Makefile
  167. @@ -0,0 +1,15 @@
  168. +#
  169. +# Makefile for the Atheros AR71xx built-in ethernet macs
  170. +#
  171. +
  172. +ag71xx-y += ag71xx_main.o
  173. +ag71xx-y += ag71xx_ethtool.o
  174. +ag71xx-y += ag71xx_phy.o
  175. +ag71xx-y += ag71xx_mdio.o
  176. +ag71xx-y += ag71xx_ar7240.o
  177. +
  178. +ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o
  179. +ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o
  180. +
  181. +obj-$(CONFIG_AG71XX) += ag71xx.o
  182. +
  183. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
  184. new file mode 100644
  185. index 0000000..f6d85b9
  186. --- /dev/null
  187. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
  188. @@ -0,0 +1,476 @@
  189. +/*
  190. + * Atheros AR71xx built-in ethernet mac driver
  191. + *
  192. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  193. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  194. + *
  195. + * Based on Atheros' AG7100 driver
  196. + *
  197. + * This program is free software; you can redistribute it and/or modify it
  198. + * under the terms of the GNU General Public License version 2 as published
  199. + * by the Free Software Foundation.
  200. + */
  201. +
  202. +#ifndef __AG71XX_H
  203. +#define __AG71XX_H
  204. +
  205. +#include <linux/kernel.h>
  206. +#include <linux/version.h>
  207. +#include <linux/module.h>
  208. +#include <linux/init.h>
  209. +#include <linux/types.h>
  210. +#include <linux/random.h>
  211. +#include <linux/spinlock.h>
  212. +#include <linux/interrupt.h>
  213. +#include <linux/platform_device.h>
  214. +#include <linux/ethtool.h>
  215. +#include <linux/etherdevice.h>
  216. +#include <linux/if_vlan.h>
  217. +#include <linux/phy.h>
  218. +#include <linux/skbuff.h>
  219. +#include <linux/dma-mapping.h>
  220. +#include <linux/workqueue.h>
  221. +
  222. +#include <linux/bitops.h>
  223. +
  224. +#include <asm/mach-ath79/ar71xx_regs.h>
  225. +#include <asm/mach-ath79/ath79.h>
  226. +#include <asm/mach-ath79/ag71xx_platform.h>
  227. +
  228. +#define AG71XX_DRV_NAME "ag71xx"
  229. +#define AG71XX_DRV_VERSION "0.5.35"
  230. +
  231. +#define AG71XX_NAPI_WEIGHT 64
  232. +#define AG71XX_OOM_REFILL (1 + HZ/10)
  233. +
  234. +#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  235. +#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
  236. +#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  237. +
  238. +#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  239. +#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  240. +
  241. +#define AG71XX_TX_MTU_LEN 1540
  242. +
  243. +#define AG71XX_TX_RING_SIZE_DEFAULT 32
  244. +#define AG71XX_RX_RING_SIZE_DEFAULT 128
  245. +
  246. +#define AG71XX_TX_RING_SIZE_MAX 32
  247. +#define AG71XX_RX_RING_SIZE_MAX 128
  248. +
  249. +#ifdef CONFIG_AG71XX_DEBUG
  250. +#define DBG(fmt, args...) pr_debug(fmt, ## args)
  251. +#else
  252. +#define DBG(fmt, args...) do {} while (0)
  253. +#endif
  254. +
  255. +#define ag71xx_assert(_cond) \
  256. +do { \
  257. + if (_cond) \
  258. + break; \
  259. + printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
  260. + BUG(); \
  261. +} while (0)
  262. +
  263. +struct ag71xx_desc {
  264. + u32 data;
  265. + u32 ctrl;
  266. +#define DESC_EMPTY BIT(31)
  267. +#define DESC_MORE BIT(24)
  268. +#define DESC_PKTLEN_M 0xfff
  269. + u32 next;
  270. + u32 pad;
  271. +} __attribute__((aligned(4)));
  272. +
  273. +struct ag71xx_buf {
  274. + union {
  275. + struct sk_buff *skb;
  276. + void *rx_buf;
  277. + };
  278. + struct ag71xx_desc *desc;
  279. + union {
  280. + dma_addr_t dma_addr;
  281. + unsigned long timestamp;
  282. + };
  283. + unsigned int len;
  284. +};
  285. +
  286. +struct ag71xx_ring {
  287. + struct ag71xx_buf *buf;
  288. + u8 *descs_cpu;
  289. + dma_addr_t descs_dma;
  290. + unsigned int desc_size;
  291. + unsigned int curr;
  292. + unsigned int dirty;
  293. + unsigned int size;
  294. +};
  295. +
  296. +struct ag71xx_mdio {
  297. + struct mii_bus *mii_bus;
  298. + int mii_irq[PHY_MAX_ADDR];
  299. + void __iomem *mdio_base;
  300. + struct ag71xx_mdio_platform_data *pdata;
  301. +};
  302. +
  303. +struct ag71xx_int_stats {
  304. + unsigned long rx_pr;
  305. + unsigned long rx_be;
  306. + unsigned long rx_of;
  307. + unsigned long tx_ps;
  308. + unsigned long tx_be;
  309. + unsigned long tx_ur;
  310. + unsigned long total;
  311. +};
  312. +
  313. +struct ag71xx_napi_stats {
  314. + unsigned long napi_calls;
  315. + unsigned long rx_count;
  316. + unsigned long rx_packets;
  317. + unsigned long rx_packets_max;
  318. + unsigned long tx_count;
  319. + unsigned long tx_packets;
  320. + unsigned long tx_packets_max;
  321. +
  322. + unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
  323. + unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
  324. +};
  325. +
  326. +struct ag71xx_debug {
  327. + struct dentry *debugfs_dir;
  328. +
  329. + struct ag71xx_int_stats int_stats;
  330. + struct ag71xx_napi_stats napi_stats;
  331. +};
  332. +
  333. +struct ag71xx {
  334. + void __iomem *mac_base;
  335. +
  336. + spinlock_t lock;
  337. + struct platform_device *pdev;
  338. + struct net_device *dev;
  339. + struct napi_struct napi;
  340. + u32 msg_enable;
  341. +
  342. + struct ag71xx_desc *stop_desc;
  343. + dma_addr_t stop_desc_dma;
  344. +
  345. + struct ag71xx_ring rx_ring;
  346. + struct ag71xx_ring tx_ring;
  347. +
  348. + struct mii_bus *mii_bus;
  349. + struct phy_device *phy_dev;
  350. + void *phy_priv;
  351. +
  352. + unsigned int link;
  353. + unsigned int speed;
  354. + int duplex;
  355. +
  356. + unsigned int max_frame_len;
  357. + unsigned int desc_pktlen_mask;
  358. + unsigned int rx_buf_size;
  359. +
  360. + struct work_struct restart_work;
  361. + struct delayed_work link_work;
  362. + struct timer_list oom_timer;
  363. +
  364. +#ifdef CONFIG_AG71XX_DEBUG_FS
  365. + struct ag71xx_debug debug;
  366. +#endif
  367. +};
  368. +
  369. +extern struct ethtool_ops ag71xx_ethtool_ops;
  370. +void ag71xx_link_adjust(struct ag71xx *ag);
  371. +
  372. +int ag71xx_mdio_driver_init(void) __init;
  373. +void ag71xx_mdio_driver_exit(void);
  374. +
  375. +int ag71xx_phy_connect(struct ag71xx *ag);
  376. +void ag71xx_phy_disconnect(struct ag71xx *ag);
  377. +void ag71xx_phy_start(struct ag71xx *ag);
  378. +void ag71xx_phy_stop(struct ag71xx *ag);
  379. +
  380. +static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
  381. +{
  382. + return ag->pdev->dev.platform_data;
  383. +}
  384. +
  385. +static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
  386. +{
  387. + return (desc->ctrl & DESC_EMPTY) != 0;
  388. +}
  389. +
  390. +/* Register offsets */
  391. +#define AG71XX_REG_MAC_CFG1 0x0000
  392. +#define AG71XX_REG_MAC_CFG2 0x0004
  393. +#define AG71XX_REG_MAC_IPG 0x0008
  394. +#define AG71XX_REG_MAC_HDX 0x000c
  395. +#define AG71XX_REG_MAC_MFL 0x0010
  396. +#define AG71XX_REG_MII_CFG 0x0020
  397. +#define AG71XX_REG_MII_CMD 0x0024
  398. +#define AG71XX_REG_MII_ADDR 0x0028
  399. +#define AG71XX_REG_MII_CTRL 0x002c
  400. +#define AG71XX_REG_MII_STATUS 0x0030
  401. +#define AG71XX_REG_MII_IND 0x0034
  402. +#define AG71XX_REG_MAC_IFCTL 0x0038
  403. +#define AG71XX_REG_MAC_ADDR1 0x0040
  404. +#define AG71XX_REG_MAC_ADDR2 0x0044
  405. +#define AG71XX_REG_FIFO_CFG0 0x0048
  406. +#define AG71XX_REG_FIFO_CFG1 0x004c
  407. +#define AG71XX_REG_FIFO_CFG2 0x0050
  408. +#define AG71XX_REG_FIFO_CFG3 0x0054
  409. +#define AG71XX_REG_FIFO_CFG4 0x0058
  410. +#define AG71XX_REG_FIFO_CFG5 0x005c
  411. +#define AG71XX_REG_FIFO_RAM0 0x0060
  412. +#define AG71XX_REG_FIFO_RAM1 0x0064
  413. +#define AG71XX_REG_FIFO_RAM2 0x0068
  414. +#define AG71XX_REG_FIFO_RAM3 0x006c
  415. +#define AG71XX_REG_FIFO_RAM4 0x0070
  416. +#define AG71XX_REG_FIFO_RAM5 0x0074
  417. +#define AG71XX_REG_FIFO_RAM6 0x0078
  418. +#define AG71XX_REG_FIFO_RAM7 0x007c
  419. +
  420. +#define AG71XX_REG_TX_CTRL 0x0180
  421. +#define AG71XX_REG_TX_DESC 0x0184
  422. +#define AG71XX_REG_TX_STATUS 0x0188
  423. +#define AG71XX_REG_RX_CTRL 0x018c
  424. +#define AG71XX_REG_RX_DESC 0x0190
  425. +#define AG71XX_REG_RX_STATUS 0x0194
  426. +#define AG71XX_REG_INT_ENABLE 0x0198
  427. +#define AG71XX_REG_INT_STATUS 0x019c
  428. +
  429. +#define AG71XX_REG_FIFO_DEPTH 0x01a8
  430. +#define AG71XX_REG_RX_SM 0x01b0
  431. +#define AG71XX_REG_TX_SM 0x01b4
  432. +
  433. +#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
  434. +#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
  435. +#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
  436. +#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
  437. +#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
  438. +#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
  439. +#define MAC_CFG1_LB BIT(8) /* Loopback mode */
  440. +#define MAC_CFG1_SR BIT(31) /* Soft Reset */
  441. +
  442. +#define MAC_CFG2_FDX BIT(0)
  443. +#define MAC_CFG2_CRC_EN BIT(1)
  444. +#define MAC_CFG2_PAD_CRC_EN BIT(2)
  445. +#define MAC_CFG2_LEN_CHECK BIT(4)
  446. +#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
  447. +#define MAC_CFG2_IF_1000 BIT(9)
  448. +#define MAC_CFG2_IF_10_100 BIT(8)
  449. +
  450. +#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
  451. +#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
  452. +#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
  453. +#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
  454. +#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
  455. +#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
  456. + | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
  457. +
  458. +#define FIFO_CFG0_ENABLE_SHIFT 8
  459. +
  460. +#define FIFO_CFG4_DE BIT(0) /* Drop Event */
  461. +#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
  462. +#define FIFO_CFG4_FC BIT(2) /* False Carrier */
  463. +#define FIFO_CFG4_CE BIT(3) /* Code Error */
  464. +#define FIFO_CFG4_CR BIT(4) /* CRC error */
  465. +#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
  466. +#define FIFO_CFG4_LO BIT(6) /* Length out of range */
  467. +#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
  468. +#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
  469. +#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
  470. +#define FIFO_CFG4_DR BIT(10) /* Dribble */
  471. +#define FIFO_CFG4_LE BIT(11) /* Long Event */
  472. +#define FIFO_CFG4_CF BIT(12) /* Control Frame */
  473. +#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
  474. +#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
  475. +#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
  476. +#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
  477. +#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
  478. +
  479. +#define FIFO_CFG5_DE BIT(0) /* Drop Event */
  480. +#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
  481. +#define FIFO_CFG5_FC BIT(2) /* False Carrier */
  482. +#define FIFO_CFG5_CE BIT(3) /* Code Error */
  483. +#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
  484. +#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
  485. +#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
  486. +#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
  487. +#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
  488. +#define FIFO_CFG5_DR BIT(9) /* Dribble */
  489. +#define FIFO_CFG5_CF BIT(10) /* Control Frame */
  490. +#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
  491. +#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
  492. +#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
  493. +#define FIFO_CFG5_LE BIT(14) /* Long Event */
  494. +#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
  495. +#define FIFO_CFG5_16 BIT(16) /* unknown */
  496. +#define FIFO_CFG5_17 BIT(17) /* unknown */
  497. +#define FIFO_CFG5_SF BIT(18) /* Short Frame */
  498. +#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
  499. +
  500. +#define AG71XX_INT_TX_PS BIT(0)
  501. +#define AG71XX_INT_TX_UR BIT(1)
  502. +#define AG71XX_INT_TX_BE BIT(3)
  503. +#define AG71XX_INT_RX_PR BIT(4)
  504. +#define AG71XX_INT_RX_OF BIT(6)
  505. +#define AG71XX_INT_RX_BE BIT(7)
  506. +
  507. +#define MAC_IFCTL_SPEED BIT(16)
  508. +
  509. +#define MII_CFG_CLK_DIV_4 0
  510. +#define MII_CFG_CLK_DIV_6 2
  511. +#define MII_CFG_CLK_DIV_8 3
  512. +#define MII_CFG_CLK_DIV_10 4
  513. +#define MII_CFG_CLK_DIV_14 5
  514. +#define MII_CFG_CLK_DIV_20 6
  515. +#define MII_CFG_CLK_DIV_28 7
  516. +#define MII_CFG_CLK_DIV_34 8
  517. +#define MII_CFG_CLK_DIV_42 9
  518. +#define MII_CFG_CLK_DIV_50 10
  519. +#define MII_CFG_CLK_DIV_58 11
  520. +#define MII_CFG_CLK_DIV_66 12
  521. +#define MII_CFG_CLK_DIV_74 13
  522. +#define MII_CFG_CLK_DIV_82 14
  523. +#define MII_CFG_CLK_DIV_98 15
  524. +#define MII_CFG_RESET BIT(31)
  525. +
  526. +#define MII_CMD_WRITE 0x0
  527. +#define MII_CMD_READ 0x1
  528. +#define MII_ADDR_SHIFT 8
  529. +#define MII_IND_BUSY BIT(0)
  530. +#define MII_IND_INVALID BIT(2)
  531. +
  532. +#define TX_CTRL_TXE BIT(0) /* Tx Enable */
  533. +
  534. +#define TX_STATUS_PS BIT(0) /* Packet Sent */
  535. +#define TX_STATUS_UR BIT(1) /* Tx Underrun */
  536. +#define TX_STATUS_BE BIT(3) /* Bus Error */
  537. +
  538. +#define RX_CTRL_RXE BIT(0) /* Rx Enable */
  539. +
  540. +#define RX_STATUS_PR BIT(0) /* Packet Received */
  541. +#define RX_STATUS_OF BIT(2) /* Rx Overflow */
  542. +#define RX_STATUS_BE BIT(3) /* Bus Error */
  543. +
  544. +static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
  545. +{
  546. + switch (reg) {
  547. + case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
  548. + case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
  549. + case AG71XX_REG_MII_CFG:
  550. + break;
  551. +
  552. + default:
  553. + BUG();
  554. + }
  555. +}
  556. +
  557. +static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
  558. +{
  559. + ag71xx_check_reg_offset(ag, reg);
  560. +
  561. + __raw_writel(value, ag->mac_base + reg);
  562. + /* flush write */
  563. + (void) __raw_readl(ag->mac_base + reg);
  564. +}
  565. +
  566. +static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
  567. +{
  568. + ag71xx_check_reg_offset(ag, reg);
  569. +
  570. + return __raw_readl(ag->mac_base + reg);
  571. +}
  572. +
  573. +static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
  574. +{
  575. + void __iomem *r;
  576. +
  577. + ag71xx_check_reg_offset(ag, reg);
  578. +
  579. + r = ag->mac_base + reg;
  580. + __raw_writel(__raw_readl(r) | mask, r);
  581. + /* flush write */
  582. + (void)__raw_readl(r);
  583. +}
  584. +
  585. +static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
  586. +{
  587. + void __iomem *r;
  588. +
  589. + ag71xx_check_reg_offset(ag, reg);
  590. +
  591. + r = ag->mac_base + reg;
  592. + __raw_writel(__raw_readl(r) & ~mask, r);
  593. + /* flush write */
  594. + (void) __raw_readl(r);
  595. +}
  596. +
  597. +static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
  598. +{
  599. + ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
  600. +}
  601. +
  602. +static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
  603. +{
  604. + ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
  605. +}
  606. +
  607. +#ifdef CONFIG_AG71XX_AR8216_SUPPORT
  608. +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
  609. +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
  610. + int pktlen);
  611. +static inline int ag71xx_has_ar8216(struct ag71xx *ag)
  612. +{
  613. + return ag71xx_get_pdata(ag)->has_ar8216;
  614. +}
  615. +#else
  616. +static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
  617. + struct sk_buff *skb)
  618. +{
  619. +}
  620. +
  621. +static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
  622. + struct sk_buff *skb,
  623. + int pktlen)
  624. +{
  625. + return 0;
  626. +}
  627. +static inline int ag71xx_has_ar8216(struct ag71xx *ag)
  628. +{
  629. + return 0;
  630. +}
  631. +#endif
  632. +
  633. +#ifdef CONFIG_AG71XX_DEBUG_FS
  634. +int ag71xx_debugfs_root_init(void);
  635. +void ag71xx_debugfs_root_exit(void);
  636. +int ag71xx_debugfs_init(struct ag71xx *ag);
  637. +void ag71xx_debugfs_exit(struct ag71xx *ag);
  638. +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
  639. +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
  640. +#else
  641. +static inline int ag71xx_debugfs_root_init(void) { return 0; }
  642. +static inline void ag71xx_debugfs_root_exit(void) {}
  643. +static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
  644. +static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
  645. +static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
  646. + u32 status) {}
  647. +static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
  648. + int rx, int tx) {}
  649. +#endif /* CONFIG_AG71XX_DEBUG_FS */
  650. +
  651. +void ag71xx_ar7240_start(struct ag71xx *ag);
  652. +void ag71xx_ar7240_stop(struct ag71xx *ag);
  653. +int ag71xx_ar7240_init(struct ag71xx *ag);
  654. +void ag71xx_ar7240_cleanup(struct ag71xx *ag);
  655. +
  656. +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
  657. +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
  658. +
  659. +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
  660. + unsigned reg_addr);
  661. +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
  662. + unsigned reg_addr, u16 reg_val);
  663. +
  664. +#endif /* _AG71XX_H */
  665. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
  666. new file mode 100644
  667. index 0000000..d4ccc02
  668. --- /dev/null
  669. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
  670. @@ -0,0 +1,1202 @@
  671. +/*
  672. + * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
  673. + * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
  674. + * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
  675. + *
  676. + * This program is free software; you can redistribute it and/or modify it
  677. + * under the terms of the GNU General Public License version 2 as published
  678. + * by the Free Software Foundation.
  679. + *
  680. + */
  681. +
  682. +#include <linux/etherdevice.h>
  683. +#include <linux/list.h>
  684. +#include <linux/netdevice.h>
  685. +#include <linux/phy.h>
  686. +#include <linux/mii.h>
  687. +#include <linux/bitops.h>
  688. +#include <linux/switch.h>
  689. +#include "ag71xx.h"
  690. +
  691. +#define BITM(_count) (BIT(_count) - 1)
  692. +#define BITS(_shift, _count) (BITM(_count) << _shift)
  693. +
  694. +#define AR7240_REG_MASK_CTRL 0x00
  695. +#define AR7240_MASK_CTRL_REVISION_M BITM(8)
  696. +#define AR7240_MASK_CTRL_VERSION_M BITM(8)
  697. +#define AR7240_MASK_CTRL_VERSION_S 8
  698. +#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
  699. +#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
  700. +#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
  701. +
  702. +#define AR7240_REG_MAC_ADDR0 0x20
  703. +#define AR7240_REG_MAC_ADDR1 0x24
  704. +
  705. +#define AR7240_REG_FLOOD_MASK 0x2c
  706. +#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
  707. +
  708. +#define AR7240_REG_GLOBAL_CTRL 0x30
  709. +#define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
  710. +#define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
  711. +
  712. +#define AR7240_REG_VTU 0x0040
  713. +#define AR7240_VTU_OP BITM(3)
  714. +#define AR7240_VTU_OP_NOOP 0x0
  715. +#define AR7240_VTU_OP_FLUSH 0x1
  716. +#define AR7240_VTU_OP_LOAD 0x2
  717. +#define AR7240_VTU_OP_PURGE 0x3
  718. +#define AR7240_VTU_OP_REMOVE_PORT 0x4
  719. +#define AR7240_VTU_ACTIVE BIT(3)
  720. +#define AR7240_VTU_FULL BIT(4)
  721. +#define AR7240_VTU_PORT BITS(8, 4)
  722. +#define AR7240_VTU_PORT_S 8
  723. +#define AR7240_VTU_VID BITS(16, 12)
  724. +#define AR7240_VTU_VID_S 16
  725. +#define AR7240_VTU_PRIO BITS(28, 3)
  726. +#define AR7240_VTU_PRIO_S 28
  727. +#define AR7240_VTU_PRIO_EN BIT(31)
  728. +
  729. +#define AR7240_REG_VTU_DATA 0x0044
  730. +#define AR7240_VTUDATA_MEMBER BITS(0, 10)
  731. +#define AR7240_VTUDATA_VALID BIT(11)
  732. +
  733. +#define AR7240_REG_ATU 0x50
  734. +#define AR7240_ATU_FLUSH_ALL 0x1
  735. +
  736. +#define AR7240_REG_AT_CTRL 0x5c
  737. +#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
  738. +#define AR7240_AT_CTRL_AGE_EN BIT(17)
  739. +#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
  740. +#define AR7240_AT_CTRL_RESERVED BIT(19)
  741. +#define AR7240_AT_CTRL_ARP_EN BIT(20)
  742. +
  743. +#define AR7240_REG_TAG_PRIORITY 0x70
  744. +
  745. +#define AR7240_REG_SERVICE_TAG 0x74
  746. +#define AR7240_SERVICE_TAG_M BITM(16)
  747. +
  748. +#define AR7240_REG_CPU_PORT 0x78
  749. +#define AR7240_MIRROR_PORT_S 4
  750. +#define AR7240_CPU_PORT_EN BIT(8)
  751. +
  752. +#define AR7240_REG_MIB_FUNCTION0 0x80
  753. +#define AR7240_MIB_TIMER_M BITM(16)
  754. +#define AR7240_MIB_AT_HALF_EN BIT(16)
  755. +#define AR7240_MIB_BUSY BIT(17)
  756. +#define AR7240_MIB_FUNC_S 24
  757. +#define AR7240_MIB_FUNC_M BITM(3)
  758. +#define AR7240_MIB_FUNC_NO_OP 0x0
  759. +#define AR7240_MIB_FUNC_FLUSH 0x1
  760. +#define AR7240_MIB_FUNC_CAPTURE 0x3
  761. +
  762. +#define AR7240_REG_MDIO_CTRL 0x98
  763. +#define AR7240_MDIO_CTRL_DATA_M BITM(16)
  764. +#define AR7240_MDIO_CTRL_REG_ADDR_S 16
  765. +#define AR7240_MDIO_CTRL_PHY_ADDR_S 21
  766. +#define AR7240_MDIO_CTRL_CMD_WRITE 0
  767. +#define AR7240_MDIO_CTRL_CMD_READ BIT(27)
  768. +#define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
  769. +#define AR7240_MDIO_CTRL_BUSY BIT(31)
  770. +
  771. +#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
  772. +
  773. +#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
  774. +#define AR7240_PORT_STATUS_SPEED_S 0
  775. +#define AR7240_PORT_STATUS_SPEED_M BITM(2)
  776. +#define AR7240_PORT_STATUS_SPEED_10 0
  777. +#define AR7240_PORT_STATUS_SPEED_100 1
  778. +#define AR7240_PORT_STATUS_SPEED_1000 2
  779. +#define AR7240_PORT_STATUS_TXMAC BIT(2)
  780. +#define AR7240_PORT_STATUS_RXMAC BIT(3)
  781. +#define AR7240_PORT_STATUS_TXFLOW BIT(4)
  782. +#define AR7240_PORT_STATUS_RXFLOW BIT(5)
  783. +#define AR7240_PORT_STATUS_DUPLEX BIT(6)
  784. +#define AR7240_PORT_STATUS_LINK_UP BIT(8)
  785. +#define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
  786. +#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
  787. +
  788. +#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
  789. +#define AR7240_PORT_CTRL_STATE_M BITM(3)
  790. +#define AR7240_PORT_CTRL_STATE_DISABLED 0
  791. +#define AR7240_PORT_CTRL_STATE_BLOCK 1
  792. +#define AR7240_PORT_CTRL_STATE_LISTEN 2
  793. +#define AR7240_PORT_CTRL_STATE_LEARN 3
  794. +#define AR7240_PORT_CTRL_STATE_FORWARD 4
  795. +#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
  796. +#define AR7240_PORT_CTRL_VLAN_MODE_S 8
  797. +#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
  798. +#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
  799. +#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
  800. +#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
  801. +#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
  802. +#define AR7240_PORT_CTRL_HEADER BIT(11)
  803. +#define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
  804. +#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
  805. +#define AR7240_PORT_CTRL_LEARN BIT(14)
  806. +#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
  807. +#define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
  808. +#define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
  809. +
  810. +#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
  811. +
  812. +#define AR7240_PORT_VLAN_DEFAULT_ID_S 0
  813. +#define AR7240_PORT_VLAN_DEST_PORTS_S 16
  814. +#define AR7240_PORT_VLAN_MODE_S 30
  815. +#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
  816. +#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
  817. +#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
  818. +#define AR7240_PORT_VLAN_MODE_SECURE 3
  819. +
  820. +
  821. +#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
  822. +
  823. +#define AR7240_STATS_RXBROAD 0x00
  824. +#define AR7240_STATS_RXPAUSE 0x04
  825. +#define AR7240_STATS_RXMULTI 0x08
  826. +#define AR7240_STATS_RXFCSERR 0x0c
  827. +#define AR7240_STATS_RXALIGNERR 0x10
  828. +#define AR7240_STATS_RXRUNT 0x14
  829. +#define AR7240_STATS_RXFRAGMENT 0x18
  830. +#define AR7240_STATS_RX64BYTE 0x1c
  831. +#define AR7240_STATS_RX128BYTE 0x20
  832. +#define AR7240_STATS_RX256BYTE 0x24
  833. +#define AR7240_STATS_RX512BYTE 0x28
  834. +#define AR7240_STATS_RX1024BYTE 0x2c
  835. +#define AR7240_STATS_RX1518BYTE 0x30
  836. +#define AR7240_STATS_RXMAXBYTE 0x34
  837. +#define AR7240_STATS_RXTOOLONG 0x38
  838. +#define AR7240_STATS_RXGOODBYTE 0x3c
  839. +#define AR7240_STATS_RXBADBYTE 0x44
  840. +#define AR7240_STATS_RXOVERFLOW 0x4c
  841. +#define AR7240_STATS_FILTERED 0x50
  842. +#define AR7240_STATS_TXBROAD 0x54
  843. +#define AR7240_STATS_TXPAUSE 0x58
  844. +#define AR7240_STATS_TXMULTI 0x5c
  845. +#define AR7240_STATS_TXUNDERRUN 0x60
  846. +#define AR7240_STATS_TX64BYTE 0x64
  847. +#define AR7240_STATS_TX128BYTE 0x68
  848. +#define AR7240_STATS_TX256BYTE 0x6c
  849. +#define AR7240_STATS_TX512BYTE 0x70
  850. +#define AR7240_STATS_TX1024BYTE 0x74
  851. +#define AR7240_STATS_TX1518BYTE 0x78
  852. +#define AR7240_STATS_TXMAXBYTE 0x7c
  853. +#define AR7240_STATS_TXOVERSIZE 0x80
  854. +#define AR7240_STATS_TXBYTE 0x84
  855. +#define AR7240_STATS_TXCOLLISION 0x8c
  856. +#define AR7240_STATS_TXABORTCOL 0x90
  857. +#define AR7240_STATS_TXMULTICOL 0x94
  858. +#define AR7240_STATS_TXSINGLECOL 0x98
  859. +#define AR7240_STATS_TXEXCDEFER 0x9c
  860. +#define AR7240_STATS_TXDEFER 0xa0
  861. +#define AR7240_STATS_TXLATECOL 0xa4
  862. +
  863. +#define AR7240_PORT_CPU 0
  864. +#define AR7240_NUM_PORTS 6
  865. +#define AR7240_NUM_PHYS 5
  866. +
  867. +#define AR7240_PHY_ID1 0x004d
  868. +#define AR7240_PHY_ID2 0xd041
  869. +
  870. +#define AR934X_PHY_ID1 0x004d
  871. +#define AR934X_PHY_ID2 0xd042
  872. +
  873. +#define AR7240_MAX_VLANS 16
  874. +
  875. +#define AR934X_REG_OPER_MODE0 0x04
  876. +#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
  877. +#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
  878. +
  879. +#define AR934X_REG_OPER_MODE1 0x08
  880. +#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
  881. +
  882. +#define AR934X_REG_FLOOD_MASK 0x2c
  883. +#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
  884. +#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
  885. +
  886. +#define AR934X_REG_QM_CTRL 0x3c
  887. +#define AR934X_QM_CTRL_ARP_EN BIT(15)
  888. +
  889. +#define AR934X_REG_AT_CTRL 0x5c
  890. +#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
  891. +#define AR934X_AT_CTRL_AGE_EN BIT(17)
  892. +#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
  893. +
  894. +#define AR934X_MIB_ENABLE BIT(30)
  895. +
  896. +#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
  897. +
  898. +#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
  899. +#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
  900. +#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
  901. +#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
  902. +#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
  903. +#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
  904. +#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
  905. +#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
  906. +#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
  907. +
  908. +#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
  909. +#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
  910. +#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
  911. +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
  912. +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
  913. +#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
  914. +#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
  915. +
  916. +#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
  917. +
  918. +struct ar7240sw_port_stat {
  919. + unsigned long rx_broadcast;
  920. + unsigned long rx_pause;
  921. + unsigned long rx_multicast;
  922. + unsigned long rx_fcs_error;
  923. + unsigned long rx_align_error;
  924. + unsigned long rx_runt;
  925. + unsigned long rx_fragments;
  926. + unsigned long rx_64byte;
  927. + unsigned long rx_128byte;
  928. + unsigned long rx_256byte;
  929. + unsigned long rx_512byte;
  930. + unsigned long rx_1024byte;
  931. + unsigned long rx_1518byte;
  932. + unsigned long rx_maxbyte;
  933. + unsigned long rx_toolong;
  934. + unsigned long rx_good_byte;
  935. + unsigned long rx_bad_byte;
  936. + unsigned long rx_overflow;
  937. + unsigned long filtered;
  938. +
  939. + unsigned long tx_broadcast;
  940. + unsigned long tx_pause;
  941. + unsigned long tx_multicast;
  942. + unsigned long tx_underrun;
  943. + unsigned long tx_64byte;
  944. + unsigned long tx_128byte;
  945. + unsigned long tx_256byte;
  946. + unsigned long tx_512byte;
  947. + unsigned long tx_1024byte;
  948. + unsigned long tx_1518byte;
  949. + unsigned long tx_maxbyte;
  950. + unsigned long tx_oversize;
  951. + unsigned long tx_byte;
  952. + unsigned long tx_collision;
  953. + unsigned long tx_abortcol;
  954. + unsigned long tx_multicol;
  955. + unsigned long tx_singlecol;
  956. + unsigned long tx_excdefer;
  957. + unsigned long tx_defer;
  958. + unsigned long tx_xlatecol;
  959. +};
  960. +
  961. +struct ar7240sw {
  962. + struct mii_bus *mii_bus;
  963. + struct ag71xx_switch_platform_data *swdata;
  964. + struct switch_dev swdev;
  965. + int num_ports;
  966. + u8 ver;
  967. + bool vlan;
  968. + u16 vlan_id[AR7240_MAX_VLANS];
  969. + u8 vlan_table[AR7240_MAX_VLANS];
  970. + u8 vlan_tagged;
  971. + u16 pvid[AR7240_NUM_PORTS];
  972. + char buf[80];
  973. +
  974. + rwlock_t stats_lock;
  975. + struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
  976. +};
  977. +
  978. +struct ar7240sw_hw_stat {
  979. + char string[ETH_GSTRING_LEN];
  980. + int sizeof_stat;
  981. + int reg;
  982. +};
  983. +
  984. +static DEFINE_MUTEX(reg_mutex);
  985. +
  986. +static inline int sw_is_ar7240(struct ar7240sw *as)
  987. +{
  988. + return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
  989. +}
  990. +
  991. +static inline int sw_is_ar934x(struct ar7240sw *as)
  992. +{
  993. + return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
  994. +}
  995. +
  996. +static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
  997. +{
  998. + return BIT(port);
  999. +}
  1000. +
  1001. +static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
  1002. +{
  1003. + return BIT(as->swdev.ports) - 1;
  1004. +}
  1005. +
  1006. +static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
  1007. +{
  1008. + return ar7240sw_port_mask_all(as) & ~BIT(port);
  1009. +}
  1010. +
  1011. +static inline u16 mk_phy_addr(u32 reg)
  1012. +{
  1013. + return 0x17 & ((reg >> 4) | 0x10);
  1014. +}
  1015. +
  1016. +static inline u16 mk_phy_reg(u32 reg)
  1017. +{
  1018. + return (reg << 1) & 0x1e;
  1019. +}
  1020. +
  1021. +static inline u16 mk_high_addr(u32 reg)
  1022. +{
  1023. + return (reg >> 7) & 0x1ff;
  1024. +}
  1025. +
  1026. +static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
  1027. +{
  1028. + unsigned long flags;
  1029. + u16 phy_addr;
  1030. + u16 phy_reg;
  1031. + u32 hi, lo;
  1032. +
  1033. + reg = (reg & 0xfffffffc) >> 2;
  1034. + phy_addr = mk_phy_addr(reg);
  1035. + phy_reg = mk_phy_reg(reg);
  1036. +
  1037. + local_irq_save(flags);
  1038. + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
  1039. + lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
  1040. + hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
  1041. + local_irq_restore(flags);
  1042. +
  1043. + return (hi << 16) | lo;
  1044. +}
  1045. +
  1046. +static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
  1047. +{
  1048. + unsigned long flags;
  1049. + u16 phy_addr;
  1050. + u16 phy_reg;
  1051. +
  1052. + reg = (reg & 0xfffffffc) >> 2;
  1053. + phy_addr = mk_phy_addr(reg);
  1054. + phy_reg = mk_phy_reg(reg);
  1055. +
  1056. + local_irq_save(flags);
  1057. + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
  1058. + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
  1059. + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
  1060. + local_irq_restore(flags);
  1061. +}
  1062. +
  1063. +static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
  1064. +{
  1065. + u32 ret;
  1066. +
  1067. + mutex_lock(&reg_mutex);
  1068. + ret = __ar7240sw_reg_read(mii, reg_addr);
  1069. + mutex_unlock(&reg_mutex);
  1070. +
  1071. + return ret;
  1072. +}
  1073. +
  1074. +static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
  1075. +{
  1076. + mutex_lock(&reg_mutex);
  1077. + __ar7240sw_reg_write(mii, reg_addr, reg_val);
  1078. + mutex_unlock(&reg_mutex);
  1079. +}
  1080. +
  1081. +static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
  1082. +{
  1083. + u32 t;
  1084. +
  1085. + mutex_lock(&reg_mutex);
  1086. + t = __ar7240sw_reg_read(mii, reg);
  1087. + t &= ~mask;
  1088. + t |= val;
  1089. + __ar7240sw_reg_write(mii, reg, t);
  1090. + mutex_unlock(&reg_mutex);
  1091. +
  1092. + return t;
  1093. +}
  1094. +
  1095. +static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
  1096. +{
  1097. + u32 t;
  1098. +
  1099. + mutex_lock(&reg_mutex);
  1100. + t = __ar7240sw_reg_read(mii, reg);
  1101. + t |= val;
  1102. + __ar7240sw_reg_write(mii, reg, t);
  1103. + mutex_unlock(&reg_mutex);
  1104. +}
  1105. +
  1106. +static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
  1107. + unsigned timeout)
  1108. +{
  1109. + int i;
  1110. +
  1111. + for (i = 0; i < timeout; i++) {
  1112. + u32 t;
  1113. +
  1114. + t = __ar7240sw_reg_read(mii, reg);
  1115. + if ((t & mask) == val)
  1116. + return 0;
  1117. +
  1118. + msleep(1);
  1119. + }
  1120. +
  1121. + return -ETIMEDOUT;
  1122. +}
  1123. +
  1124. +static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
  1125. + unsigned timeout)
  1126. +{
  1127. + int ret;
  1128. +
  1129. + mutex_lock(&reg_mutex);
  1130. + ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
  1131. + mutex_unlock(&reg_mutex);
  1132. + return ret;
  1133. +}
  1134. +
  1135. +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
  1136. + unsigned reg_addr)
  1137. +{
  1138. + u32 t, val = 0xffff;
  1139. + int err;
  1140. +
  1141. + if (phy_addr >= AR7240_NUM_PHYS)
  1142. + return 0xffff;
  1143. +
  1144. + mutex_lock(&reg_mutex);
  1145. + t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
  1146. + (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
  1147. + AR7240_MDIO_CTRL_MASTER_EN |
  1148. + AR7240_MDIO_CTRL_BUSY |
  1149. + AR7240_MDIO_CTRL_CMD_READ;
  1150. +
  1151. + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
  1152. + err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
  1153. + AR7240_MDIO_CTRL_BUSY, 0, 5);
  1154. + if (!err)
  1155. + val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
  1156. + mutex_unlock(&reg_mutex);
  1157. +
  1158. + return val & AR7240_MDIO_CTRL_DATA_M;
  1159. +}
  1160. +
  1161. +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
  1162. + unsigned reg_addr, u16 reg_val)
  1163. +{
  1164. + u32 t;
  1165. + int ret;
  1166. +
  1167. + if (phy_addr >= AR7240_NUM_PHYS)
  1168. + return -EINVAL;
  1169. +
  1170. + mutex_lock(&reg_mutex);
  1171. + t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
  1172. + (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
  1173. + AR7240_MDIO_CTRL_MASTER_EN |
  1174. + AR7240_MDIO_CTRL_BUSY |
  1175. + AR7240_MDIO_CTRL_CMD_WRITE |
  1176. + reg_val;
  1177. +
  1178. + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
  1179. + ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
  1180. + AR7240_MDIO_CTRL_BUSY, 0, 5);
  1181. + mutex_unlock(&reg_mutex);
  1182. +
  1183. + return ret;
  1184. +}
  1185. +
  1186. +static int ar7240sw_capture_stats(struct ar7240sw *as)
  1187. +{
  1188. + struct mii_bus *mii = as->mii_bus;
  1189. + int port;
  1190. + int ret;
  1191. +
  1192. + write_lock(&as->stats_lock);
  1193. +
  1194. + /* Capture the hardware statistics for all ports */
  1195. + ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
  1196. + (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
  1197. + (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
  1198. +
  1199. + /* Wait for the capturing to complete. */
  1200. + ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
  1201. + AR7240_MIB_BUSY, 0, 10);
  1202. +
  1203. + if (ret)
  1204. + goto unlock;
  1205. +
  1206. + for (port = 0; port < AR7240_NUM_PORTS; port++) {
  1207. + unsigned int base;
  1208. + struct ar7240sw_port_stat *stats;
  1209. +
  1210. + base = AR7240_REG_STATS_BASE(port);
  1211. + stats = &as->port_stats[port];
  1212. +
  1213. +#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
  1214. +
  1215. + stats->rx_good_byte += READ_STAT(RXGOODBYTE);
  1216. + stats->tx_byte += READ_STAT(TXBYTE);
  1217. +
  1218. +#undef READ_STAT
  1219. + }
  1220. +
  1221. + ret = 0;
  1222. +
  1223. +unlock:
  1224. + write_unlock(&as->stats_lock);
  1225. + return ret;
  1226. +}
  1227. +
  1228. +static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
  1229. +{
  1230. + ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
  1231. + AR7240_PORT_CTRL_STATE_DISABLED);
  1232. +}
  1233. +
  1234. +static void ar7240sw_setup(struct ar7240sw *as)
  1235. +{
  1236. + struct mii_bus *mii = as->mii_bus;
  1237. +
  1238. + /* Enable CPU port, and disable mirror port */
  1239. + ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
  1240. + AR7240_CPU_PORT_EN |
  1241. + (15 << AR7240_MIRROR_PORT_S));
  1242. +
  1243. + /* Setup TAG priority mapping */
  1244. + ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
  1245. +
  1246. + if (sw_is_ar934x(as)) {
  1247. + /* Enable aging, MAC replacing */
  1248. + ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
  1249. + 0x2b /* 5 min age time */ |
  1250. + AR934X_AT_CTRL_AGE_EN |
  1251. + AR934X_AT_CTRL_LEARN_CHANGE);
  1252. + /* Enable ARP frame acknowledge */
  1253. + ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
  1254. + AR934X_QM_CTRL_ARP_EN);
  1255. + /* Enable Broadcast/Multicast frames transmitted to the CPU */
  1256. + ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
  1257. + AR934X_FLOOD_MASK_BC_DP(0) |
  1258. + AR934X_FLOOD_MASK_MC_DP(0));
  1259. +
  1260. + /* setup MTU */
  1261. + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
  1262. + AR9340_GLOBAL_CTRL_MTU_M,
  1263. + AR9340_GLOBAL_CTRL_MTU_M);
  1264. +
  1265. + /* Enable MIB counters */
  1266. + ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
  1267. + AR934X_MIB_ENABLE);
  1268. +
  1269. + } else {
  1270. + /* Enable ARP frame acknowledge, aging, MAC replacing */
  1271. + ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
  1272. + AR7240_AT_CTRL_RESERVED |
  1273. + 0x2b /* 5 min age time */ |
  1274. + AR7240_AT_CTRL_AGE_EN |
  1275. + AR7240_AT_CTRL_ARP_EN |
  1276. + AR7240_AT_CTRL_LEARN_CHANGE);
  1277. + /* Enable Broadcast frames transmitted to the CPU */
  1278. + ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
  1279. + AR7240_FLOOD_MASK_BROAD_TO_CPU);
  1280. +
  1281. + /* setup MTU */
  1282. + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
  1283. + AR7240_GLOBAL_CTRL_MTU_M,
  1284. + AR7240_GLOBAL_CTRL_MTU_M);
  1285. + }
  1286. +
  1287. + /* setup Service TAG */
  1288. + ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
  1289. +}
  1290. +
  1291. +static int ar7240sw_reset(struct ar7240sw *as)
  1292. +{
  1293. + struct mii_bus *mii = as->mii_bus;
  1294. + int ret;
  1295. + int i;
  1296. +
  1297. + /* Set all ports to disabled state. */
  1298. + for (i = 0; i < AR7240_NUM_PORTS; i++)
  1299. + ar7240sw_disable_port(as, i);
  1300. +
  1301. + /* Wait for transmit queues to drain. */
  1302. + msleep(2);
  1303. +
  1304. + /* Reset the switch. */
  1305. + ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
  1306. + AR7240_MASK_CTRL_SOFT_RESET);
  1307. +
  1308. + ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
  1309. + AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
  1310. +
  1311. + /* setup PHYs */
  1312. + for (i = 0; i < AR7240_NUM_PHYS; i++) {
  1313. + ar7240sw_phy_write(mii, i, MII_ADVERTISE,
  1314. + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
  1315. + ADVERTISE_PAUSE_ASYM);
  1316. + ar7240sw_phy_write(mii, i, MII_BMCR,
  1317. + BMCR_RESET | BMCR_ANENABLE);
  1318. + }
  1319. + msleep(1000);
  1320. +
  1321. + ar7240sw_setup(as);
  1322. + return ret;
  1323. +}
  1324. +
  1325. +static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
  1326. +{
  1327. + struct mii_bus *mii = as->mii_bus;
  1328. + u32 ctrl;
  1329. + u32 vid, mode;
  1330. +
  1331. + ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
  1332. + AR7240_PORT_CTRL_SINGLE_VLAN;
  1333. +
  1334. + if (port == AR7240_PORT_CPU) {
  1335. + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
  1336. + AR7240_PORT_STATUS_SPEED_1000 |
  1337. + AR7240_PORT_STATUS_TXFLOW |
  1338. + AR7240_PORT_STATUS_RXFLOW |
  1339. + AR7240_PORT_STATUS_TXMAC |
  1340. + AR7240_PORT_STATUS_RXMAC |
  1341. + AR7240_PORT_STATUS_DUPLEX);
  1342. + } else {
  1343. + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
  1344. + AR7240_PORT_STATUS_LINK_AUTO);
  1345. + }
  1346. +
  1347. + /* Set the default VID for this port */
  1348. + if (as->vlan) {
  1349. + vid = as->vlan_id[as->pvid[port]];
  1350. + mode = AR7240_PORT_VLAN_MODE_SECURE;
  1351. + } else {
  1352. + vid = port;
  1353. + mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
  1354. + }
  1355. +
  1356. + if (as->vlan) {
  1357. + if (as->vlan_tagged & BIT(port))
  1358. + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
  1359. + AR7240_PORT_CTRL_VLAN_MODE_S;
  1360. + else
  1361. + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
  1362. + AR7240_PORT_CTRL_VLAN_MODE_S;
  1363. + } else {
  1364. + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
  1365. + AR7240_PORT_CTRL_VLAN_MODE_S;
  1366. + }
  1367. +
  1368. + if (!portmask) {
  1369. + if (port == AR7240_PORT_CPU)
  1370. + portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
  1371. + else
  1372. + portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
  1373. + }
  1374. +
  1375. + /* allow the port to talk to all other ports, but exclude its
  1376. + * own ID to prevent frames from being reflected back to the
  1377. + * port that they came from */
  1378. + portmask &= ar7240sw_port_mask_but(as, port);
  1379. +
  1380. + ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
  1381. + if (sw_is_ar934x(as)) {
  1382. + u32 vlan1, vlan2;
  1383. +
  1384. + vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
  1385. + vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
  1386. + (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
  1387. + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
  1388. + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
  1389. + } else {
  1390. + u32 vlan;
  1391. +
  1392. + vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
  1393. + (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
  1394. +
  1395. + ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
  1396. + }
  1397. +}
  1398. +
  1399. +static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
  1400. +{
  1401. + struct mii_bus *mii = as->mii_bus;
  1402. + u32 t;
  1403. +
  1404. + t = (addr[4] << 8) | addr[5];
  1405. + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
  1406. +
  1407. + t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
  1408. + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
  1409. +
  1410. + return 0;
  1411. +}
  1412. +
  1413. +static int
  1414. +ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1415. + struct switch_val *val)
  1416. +{
  1417. + struct ar7240sw *as = sw_to_ar7240(dev);
  1418. + as->vlan_id[val->port_vlan] = val->value.i;
  1419. + return 0;
  1420. +}
  1421. +
  1422. +static int
  1423. +ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1424. + struct switch_val *val)
  1425. +{
  1426. + struct ar7240sw *as = sw_to_ar7240(dev);
  1427. + val->value.i = as->vlan_id[val->port_vlan];
  1428. + return 0;
  1429. +}
  1430. +
  1431. +static int
  1432. +ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
  1433. +{
  1434. + struct ar7240sw *as = sw_to_ar7240(dev);
  1435. +
  1436. + /* make sure no invalid PVIDs get set */
  1437. +
  1438. + if (vlan >= dev->vlans)
  1439. + return -EINVAL;
  1440. +
  1441. + as->pvid[port] = vlan;
  1442. + return 0;
  1443. +}
  1444. +
  1445. +static int
  1446. +ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
  1447. +{
  1448. + struct ar7240sw *as = sw_to_ar7240(dev);
  1449. + *vlan = as->pvid[port];
  1450. + return 0;
  1451. +}
  1452. +
  1453. +static int
  1454. +ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
  1455. +{
  1456. + struct ar7240sw *as = sw_to_ar7240(dev);
  1457. + u8 ports = as->vlan_table[val->port_vlan];
  1458. + int i;
  1459. +
  1460. + val->len = 0;
  1461. + for (i = 0; i < as->swdev.ports; i++) {
  1462. + struct switch_port *p;
  1463. +
  1464. + if (!(ports & (1 << i)))
  1465. + continue;
  1466. +
  1467. + p = &val->value.ports[val->len++];
  1468. + p->id = i;
  1469. + if (as->vlan_tagged & (1 << i))
  1470. + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
  1471. + else
  1472. + p->flags = 0;
  1473. + }
  1474. + return 0;
  1475. +}
  1476. +
  1477. +static int
  1478. +ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
  1479. +{
  1480. + struct ar7240sw *as = sw_to_ar7240(dev);
  1481. + u8 *vt = &as->vlan_table[val->port_vlan];
  1482. + int i, j;
  1483. +
  1484. + *vt = 0;
  1485. + for (i = 0; i < val->len; i++) {
  1486. + struct switch_port *p = &val->value.ports[i];
  1487. +
  1488. + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
  1489. + as->vlan_tagged |= (1 << p->id);
  1490. + else {
  1491. + as->vlan_tagged &= ~(1 << p->id);
  1492. + as->pvid[p->id] = val->port_vlan;
  1493. +
  1494. + /* make sure that an untagged port does not
  1495. + * appear in other vlans */
  1496. + for (j = 0; j < AR7240_MAX_VLANS; j++) {
  1497. + if (j == val->port_vlan)
  1498. + continue;
  1499. + as->vlan_table[j] &= ~(1 << p->id);
  1500. + }
  1501. + }
  1502. +
  1503. + *vt |= 1 << p->id;
  1504. + }
  1505. + return 0;
  1506. +}
  1507. +
  1508. +static int
  1509. +ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1510. + struct switch_val *val)
  1511. +{
  1512. + struct ar7240sw *as = sw_to_ar7240(dev);
  1513. + as->vlan = !!val->value.i;
  1514. + return 0;
  1515. +}
  1516. +
  1517. +static int
  1518. +ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1519. + struct switch_val *val)
  1520. +{
  1521. + struct ar7240sw *as = sw_to_ar7240(dev);
  1522. + val->value.i = as->vlan;
  1523. + return 0;
  1524. +}
  1525. +
  1526. +static void
  1527. +ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
  1528. +{
  1529. + struct mii_bus *mii = as->mii_bus;
  1530. +
  1531. + if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
  1532. + return;
  1533. +
  1534. + if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
  1535. + val &= AR7240_VTUDATA_MEMBER;
  1536. + val |= AR7240_VTUDATA_VALID;
  1537. + ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
  1538. + }
  1539. + op |= AR7240_VTU_ACTIVE;
  1540. + ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
  1541. +}
  1542. +
  1543. +static int
  1544. +ar7240_hw_apply(struct switch_dev *dev)
  1545. +{
  1546. + struct ar7240sw *as = sw_to_ar7240(dev);
  1547. + u8 portmask[AR7240_NUM_PORTS];
  1548. + int i, j;
  1549. +
  1550. + /* flush all vlan translation unit entries */
  1551. + ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
  1552. +
  1553. + memset(portmask, 0, sizeof(portmask));
  1554. + if (as->vlan) {
  1555. + /* calculate the port destination masks and load vlans
  1556. + * into the vlan translation unit */
  1557. + for (j = 0; j < AR7240_MAX_VLANS; j++) {
  1558. + u8 vp = as->vlan_table[j];
  1559. +
  1560. + if (!vp)
  1561. + continue;
  1562. +
  1563. + for (i = 0; i < as->swdev.ports; i++) {
  1564. + u8 mask = (1 << i);
  1565. + if (vp & mask)
  1566. + portmask[i] |= vp & ~mask;
  1567. + }
  1568. +
  1569. + ar7240_vtu_op(as,
  1570. + AR7240_VTU_OP_LOAD |
  1571. + (as->vlan_id[j] << AR7240_VTU_VID_S),
  1572. + as->vlan_table[j]);
  1573. + }
  1574. + } else {
  1575. + /* vlan disabled:
  1576. + * isolate all ports, but connect them to the cpu port */
  1577. + for (i = 0; i < as->swdev.ports; i++) {
  1578. + if (i == AR7240_PORT_CPU)
  1579. + continue;
  1580. +
  1581. + portmask[i] = 1 << AR7240_PORT_CPU;
  1582. + portmask[AR7240_PORT_CPU] |= (1 << i);
  1583. + }
  1584. + }
  1585. +
  1586. + /* update the port destination mask registers and tag settings */
  1587. + for (i = 0; i < as->swdev.ports; i++)
  1588. + ar7240sw_setup_port(as, i, portmask[i]);
  1589. +
  1590. + return 0;
  1591. +}
  1592. +
  1593. +static int
  1594. +ar7240_reset_switch(struct switch_dev *dev)
  1595. +{
  1596. + struct ar7240sw *as = sw_to_ar7240(dev);
  1597. + ar7240sw_reset(as);
  1598. + return 0;
  1599. +}
  1600. +
  1601. +static int
  1602. +ar7240_get_port_link(struct switch_dev *dev, int port,
  1603. + struct switch_port_link *link)
  1604. +{
  1605. + struct ar7240sw *as = sw_to_ar7240(dev);
  1606. + struct mii_bus *mii = as->mii_bus;
  1607. + u32 status;
  1608. +
  1609. + if (port > AR7240_NUM_PORTS)
  1610. + return -EINVAL;
  1611. +
  1612. + status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
  1613. + link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
  1614. + if (link->aneg) {
  1615. + link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
  1616. + if (!link->link)
  1617. + return 0;
  1618. + } else {
  1619. + link->link = true;
  1620. + }
  1621. +
  1622. + link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
  1623. + link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
  1624. + link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
  1625. + switch (status & AR7240_PORT_STATUS_SPEED_M) {
  1626. + case AR7240_PORT_STATUS_SPEED_10:
  1627. + link->speed = SWITCH_PORT_SPEED_10;
  1628. + break;
  1629. + case AR7240_PORT_STATUS_SPEED_100:
  1630. + link->speed = SWITCH_PORT_SPEED_100;
  1631. + break;
  1632. + case AR7240_PORT_STATUS_SPEED_1000:
  1633. + link->speed = SWITCH_PORT_SPEED_1000;
  1634. + break;
  1635. + }
  1636. +
  1637. + return 0;
  1638. +}
  1639. +
  1640. +static int
  1641. +ar7240_get_port_stats(struct switch_dev *dev, int port,
  1642. + struct switch_port_stats *stats)
  1643. +{
  1644. + struct ar7240sw *as = sw_to_ar7240(dev);
  1645. +
  1646. + if (port > AR7240_NUM_PORTS)
  1647. + return -EINVAL;
  1648. +
  1649. + ar7240sw_capture_stats(as);
  1650. +
  1651. + read_lock(&as->stats_lock);
  1652. + stats->rx_bytes = as->port_stats[port].rx_good_byte;
  1653. + stats->tx_bytes = as->port_stats[port].tx_byte;
  1654. + read_unlock(&as->stats_lock);
  1655. +
  1656. + return 0;
  1657. +}
  1658. +
  1659. +static struct switch_attr ar7240_globals[] = {
  1660. + {
  1661. + .type = SWITCH_TYPE_INT,
  1662. + .name = "enable_vlan",
  1663. + .description = "Enable VLAN mode",
  1664. + .set = ar7240_set_vlan,
  1665. + .get = ar7240_get_vlan,
  1666. + .max = 1
  1667. + },
  1668. +};
  1669. +
  1670. +static struct switch_attr ar7240_port[] = {
  1671. +};
  1672. +
  1673. +static struct switch_attr ar7240_vlan[] = {
  1674. + {
  1675. + .type = SWITCH_TYPE_INT,
  1676. + .name = "vid",
  1677. + .description = "VLAN ID",
  1678. + .set = ar7240_set_vid,
  1679. + .get = ar7240_get_vid,
  1680. + .max = 4094,
  1681. + },
  1682. +};
  1683. +
  1684. +static const struct switch_dev_ops ar7240_ops = {
  1685. + .attr_global = {
  1686. + .attr = ar7240_globals,
  1687. + .n_attr = ARRAY_SIZE(ar7240_globals),
  1688. + },
  1689. + .attr_port = {
  1690. + .attr = ar7240_port,
  1691. + .n_attr = ARRAY_SIZE(ar7240_port),
  1692. + },
  1693. + .attr_vlan = {
  1694. + .attr = ar7240_vlan,
  1695. + .n_attr = ARRAY_SIZE(ar7240_vlan),
  1696. + },
  1697. + .get_port_pvid = ar7240_get_pvid,
  1698. + .set_port_pvid = ar7240_set_pvid,
  1699. + .get_vlan_ports = ar7240_get_ports,
  1700. + .set_vlan_ports = ar7240_set_ports,
  1701. + .apply_config = ar7240_hw_apply,
  1702. + .reset_switch = ar7240_reset_switch,
  1703. + .get_port_link = ar7240_get_port_link,
  1704. + .get_port_stats = ar7240_get_port_stats,
  1705. +};
  1706. +
  1707. +static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
  1708. +{
  1709. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  1710. + struct mii_bus *mii = ag->mii_bus;
  1711. + struct ar7240sw *as;
  1712. + struct switch_dev *swdev;
  1713. + u32 ctrl;
  1714. + u16 phy_id1;
  1715. + u16 phy_id2;
  1716. + int i;
  1717. +
  1718. + phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
  1719. + phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
  1720. + if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
  1721. + (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
  1722. + pr_err("%s: unknown phy id '%04x:%04x'\n",
  1723. + dev_name(&mii->dev), phy_id1, phy_id2);
  1724. + return NULL;
  1725. + }
  1726. +
  1727. + as = kzalloc(sizeof(*as), GFP_KERNEL);
  1728. + if (!as)
  1729. + return NULL;
  1730. +
  1731. + as->mii_bus = mii;
  1732. + as->swdata = pdata->switch_data;
  1733. +
  1734. + swdev = &as->swdev;
  1735. +
  1736. + ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
  1737. + as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
  1738. + AR7240_MASK_CTRL_VERSION_M;
  1739. +
  1740. + if (sw_is_ar7240(as)) {
  1741. + swdev->name = "AR7240/AR9330 built-in switch";
  1742. + swdev->ports = AR7240_NUM_PORTS - 1;
  1743. + } else if (sw_is_ar934x(as)) {
  1744. + swdev->name = "AR934X built-in switch";
  1745. +
  1746. + if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
  1747. + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
  1748. + AR934X_OPER_MODE0_MAC_GMII_EN);
  1749. + } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
  1750. + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
  1751. + AR934X_OPER_MODE0_PHY_MII_EN);
  1752. + } else {
  1753. + pr_err("%s: invalid PHY interface mode\n",
  1754. + dev_name(&mii->dev));
  1755. + goto err_free;
  1756. + }
  1757. +
  1758. + if (as->swdata->phy4_mii_en) {
  1759. + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
  1760. + AR934X_REG_OPER_MODE1_PHY4_MII_EN);
  1761. + swdev->ports = AR7240_NUM_PORTS - 1;
  1762. + } else {
  1763. + swdev->ports = AR7240_NUM_PORTS;
  1764. + }
  1765. + } else {
  1766. + pr_err("%s: unsupported chip, ctrl=%08x\n",
  1767. + dev_name(&mii->dev), ctrl);
  1768. + goto err_free;
  1769. + }
  1770. +
  1771. + swdev->cpu_port = AR7240_PORT_CPU;
  1772. + swdev->vlans = AR7240_MAX_VLANS;
  1773. + swdev->ops = &ar7240_ops;
  1774. +
  1775. + if (register_switch(&as->swdev, ag->dev) < 0)
  1776. + goto err_free;
  1777. +
  1778. + pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name);
  1779. +
  1780. + /* initialize defaults */
  1781. + for (i = 0; i < AR7240_MAX_VLANS; i++)
  1782. + as->vlan_id[i] = i;
  1783. +
  1784. + as->vlan_table[0] = ar7240sw_port_mask_all(as);
  1785. +
  1786. + return as;
  1787. +
  1788. +err_free:
  1789. + kfree(as);
  1790. + return NULL;
  1791. +}
  1792. +
  1793. +static void link_function(struct work_struct *work) {
  1794. + struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
  1795. + struct ar7240sw *as = ag->phy_priv;
  1796. + unsigned long flags;
  1797. + u8 mask;
  1798. + int i;
  1799. + int status = 0;
  1800. +
  1801. + mask = ~as->swdata->phy_poll_mask;
  1802. + for (i = 0; i < AR7240_NUM_PHYS; i++) {
  1803. + int link;
  1804. +
  1805. + if (!(mask & BIT(i)))
  1806. + continue;
  1807. +
  1808. + link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
  1809. + if (link & BMSR_LSTATUS) {
  1810. + status = 1;
  1811. + break;
  1812. + }
  1813. + }
  1814. +
  1815. + spin_lock_irqsave(&ag->lock, flags);
  1816. + if (status != ag->link) {
  1817. + ag->link = status;
  1818. + ag71xx_link_adjust(ag);
  1819. + }
  1820. + spin_unlock_irqrestore(&ag->lock, flags);
  1821. +
  1822. + schedule_delayed_work(&ag->link_work, HZ / 2);
  1823. +}
  1824. +
  1825. +void ag71xx_ar7240_start(struct ag71xx *ag)
  1826. +{
  1827. + struct ar7240sw *as = ag->phy_priv;
  1828. +
  1829. + ar7240sw_reset(as);
  1830. +
  1831. + ag->speed = SPEED_1000;
  1832. + ag->duplex = 1;
  1833. +
  1834. + ar7240_set_addr(as, ag->dev->dev_addr);
  1835. + ar7240_hw_apply(&as->swdev);
  1836. +
  1837. + schedule_delayed_work(&ag->link_work, HZ / 10);
  1838. +}
  1839. +
  1840. +void ag71xx_ar7240_stop(struct ag71xx *ag)
  1841. +{
  1842. + cancel_delayed_work_sync(&ag->link_work);
  1843. +}
  1844. +
  1845. +int ag71xx_ar7240_init(struct ag71xx *ag)
  1846. +{
  1847. + struct ar7240sw *as;
  1848. +
  1849. + as = ar7240_probe(ag);
  1850. + if (!as)
  1851. + return -ENODEV;
  1852. +
  1853. + ag->phy_priv = as;
  1854. + ar7240sw_reset(as);
  1855. +
  1856. + rwlock_init(&as->stats_lock);
  1857. + INIT_DELAYED_WORK(&ag->link_work, link_function);
  1858. +
  1859. + return 0;
  1860. +}
  1861. +
  1862. +void ag71xx_ar7240_cleanup(struct ag71xx *ag)
  1863. +{
  1864. + struct ar7240sw *as = ag->phy_priv;
  1865. +
  1866. + if (!as)
  1867. + return;
  1868. +
  1869. + unregister_switch(&as->swdev);
  1870. + kfree(as);
  1871. + ag->phy_priv = NULL;
  1872. +}
  1873. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c
  1874. new file mode 100644
  1875. index 0000000..7ec43b7
  1876. --- /dev/null
  1877. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c
  1878. @@ -0,0 +1,44 @@
  1879. +/*
  1880. + * Atheros AR71xx built-in ethernet mac driver
  1881. + * Special support for the Atheros ar8216 switch chip
  1882. + *
  1883. + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
  1884. + *
  1885. + * Based on Atheros' AG7100 driver
  1886. + *
  1887. + * This program is free software; you can redistribute it and/or modify it
  1888. + * under the terms of the GNU General Public License version 2 as published
  1889. + * by the Free Software Foundation.
  1890. + */
  1891. +
  1892. +#include "ag71xx.h"
  1893. +
  1894. +#define AR8216_PACKET_TYPE_MASK 0xf
  1895. +#define AR8216_PACKET_TYPE_NORMAL 0
  1896. +
  1897. +#define AR8216_HEADER_LEN 2
  1898. +
  1899. +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb)
  1900. +{
  1901. + skb_push(skb, AR8216_HEADER_LEN);
  1902. + skb->data[0] = 0x10;
  1903. + skb->data[1] = 0x80;
  1904. +}
  1905. +
  1906. +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
  1907. + int pktlen)
  1908. +{
  1909. + u8 type;
  1910. +
  1911. + type = skb->data[1] & AR8216_PACKET_TYPE_MASK;
  1912. + switch (type) {
  1913. + case AR8216_PACKET_TYPE_NORMAL:
  1914. + break;
  1915. +
  1916. + default:
  1917. + return -EINVAL;
  1918. + }
  1919. +
  1920. + skb_pull(skb, AR8216_HEADER_LEN);
  1921. + return 0;
  1922. +}
  1923. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c
  1924. new file mode 100644
  1925. index 0000000..757a572
  1926. --- /dev/null
  1927. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c
  1928. @@ -0,0 +1,284 @@
  1929. +/*
  1930. + * Atheros AR71xx built-in ethernet mac driver
  1931. + *
  1932. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  1933. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  1934. + *
  1935. + * Based on Atheros' AG7100 driver
  1936. + *
  1937. + * This program is free software; you can redistribute it and/or modify it
  1938. + * under the terms of the GNU General Public License version 2 as published
  1939. + * by the Free Software Foundation.
  1940. + */
  1941. +
  1942. +#include <linux/debugfs.h>
  1943. +
  1944. +#include "ag71xx.h"
  1945. +
  1946. +static struct dentry *ag71xx_debugfs_root;
  1947. +
  1948. +static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file)
  1949. +{
  1950. + file->private_data = inode->i_private;
  1951. + return 0;
  1952. +}
  1953. +
  1954. +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status)
  1955. +{
  1956. + if (status)
  1957. + ag->debug.int_stats.total++;
  1958. + if (status & AG71XX_INT_TX_PS)
  1959. + ag->debug.int_stats.tx_ps++;
  1960. + if (status & AG71XX_INT_TX_UR)
  1961. + ag->debug.int_stats.tx_ur++;
  1962. + if (status & AG71XX_INT_TX_BE)
  1963. + ag->debug.int_stats.tx_be++;
  1964. + if (status & AG71XX_INT_RX_PR)
  1965. + ag->debug.int_stats.rx_pr++;
  1966. + if (status & AG71XX_INT_RX_OF)
  1967. + ag->debug.int_stats.rx_of++;
  1968. + if (status & AG71XX_INT_RX_BE)
  1969. + ag->debug.int_stats.rx_be++;
  1970. +}
  1971. +
  1972. +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
  1973. + size_t count, loff_t *ppos)
  1974. +{
  1975. +#define PR_INT_STAT(_label, _field) \
  1976. + len += snprintf(buf + len, sizeof(buf) - len, \
  1977. + "%20s: %10lu\n", _label, ag->debug.int_stats._field);
  1978. +
  1979. + struct ag71xx *ag = file->private_data;
  1980. + char buf[256];
  1981. + unsigned int len = 0;
  1982. +
  1983. + PR_INT_STAT("TX Packet Sent", tx_ps);
  1984. + PR_INT_STAT("TX Underrun", tx_ur);
  1985. + PR_INT_STAT("TX Bus Error", tx_be);
  1986. + PR_INT_STAT("RX Packet Received", rx_pr);
  1987. + PR_INT_STAT("RX Overflow", rx_of);
  1988. + PR_INT_STAT("RX Bus Error", rx_be);
  1989. + len += snprintf(buf + len, sizeof(buf) - len, "\n");
  1990. + PR_INT_STAT("Total", total);
  1991. +
  1992. + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  1993. +#undef PR_INT_STAT
  1994. +}
  1995. +
  1996. +static const struct file_operations ag71xx_fops_int_stats = {
  1997. + .open = ag71xx_debugfs_generic_open,
  1998. + .read = read_file_int_stats,
  1999. + .owner = THIS_MODULE
  2000. +};
  2001. +
  2002. +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx)
  2003. +{
  2004. + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
  2005. +
  2006. + if (rx) {
  2007. + stats->rx_count++;
  2008. + stats->rx_packets += rx;
  2009. + if (rx <= AG71XX_NAPI_WEIGHT)
  2010. + stats->rx[rx]++;
  2011. + if (rx > stats->rx_packets_max)
  2012. + stats->rx_packets_max = rx;
  2013. + }
  2014. +
  2015. + if (tx) {
  2016. + stats->tx_count++;
  2017. + stats->tx_packets += tx;
  2018. + if (tx <= AG71XX_NAPI_WEIGHT)
  2019. + stats->tx[tx]++;
  2020. + if (tx > stats->tx_packets_max)
  2021. + stats->tx_packets_max = tx;
  2022. + }
  2023. +}
  2024. +
  2025. +static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf,
  2026. + size_t count, loff_t *ppos)
  2027. +{
  2028. + struct ag71xx *ag = file->private_data;
  2029. + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
  2030. + char *buf;
  2031. + unsigned int buflen;
  2032. + unsigned int len = 0;
  2033. + unsigned long rx_avg = 0;
  2034. + unsigned long tx_avg = 0;
  2035. + int ret;
  2036. + int i;
  2037. +
  2038. + buflen = 2048;
  2039. + buf = kmalloc(buflen, GFP_KERNEL);
  2040. + if (!buf)
  2041. + return -ENOMEM;
  2042. +
  2043. + if (stats->rx_count)
  2044. + rx_avg = stats->rx_packets / stats->rx_count;
  2045. +
  2046. + if (stats->tx_count)
  2047. + tx_avg = stats->tx_packets / stats->tx_count;
  2048. +
  2049. + len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n",
  2050. + "len", "rx", "tx");
  2051. +
  2052. + for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++)
  2053. + len += snprintf(buf + len, buflen - len,
  2054. + "%3d: %10lu %10lu\n",
  2055. + i, stats->rx[i], stats->tx[i]);
  2056. +
  2057. + len += snprintf(buf + len, buflen - len, "\n");
  2058. +
  2059. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  2060. + "sum", stats->rx_count, stats->tx_count);
  2061. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  2062. + "avg", rx_avg, tx_avg);
  2063. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  2064. + "max", stats->rx_packets_max, stats->tx_packets_max);
  2065. + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
  2066. + "pkt", stats->rx_packets, stats->tx_packets);
  2067. +
  2068. + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  2069. + kfree(buf);
  2070. +
  2071. + return ret;
  2072. +}
  2073. +
  2074. +static const struct file_operations ag71xx_fops_napi_stats = {
  2075. + .open = ag71xx_debugfs_generic_open,
  2076. + .read = read_file_napi_stats,
  2077. + .owner = THIS_MODULE
  2078. +};
  2079. +
  2080. +#define DESC_PRINT_LEN 64
  2081. +
  2082. +static ssize_t read_file_ring(struct file *file, char __user *user_buf,
  2083. + size_t count, loff_t *ppos,
  2084. + struct ag71xx *ag,
  2085. + struct ag71xx_ring *ring,
  2086. + unsigned desc_reg)
  2087. +{
  2088. + char *buf;
  2089. + unsigned int buflen;
  2090. + unsigned int len = 0;
  2091. + unsigned long flags;
  2092. + ssize_t ret;
  2093. + int curr;
  2094. + int dirty;
  2095. + u32 desc_hw;
  2096. + int i;
  2097. +
  2098. + buflen = (ring->size * DESC_PRINT_LEN);
  2099. + buf = kmalloc(buflen, GFP_KERNEL);
  2100. + if (!buf)
  2101. + return -ENOMEM;
  2102. +
  2103. + len += snprintf(buf + len, buflen - len,
  2104. + "Idx ... %-8s %-8s %-8s %-8s . %-10s\n",
  2105. + "desc", "next", "data", "ctrl", "timestamp");
  2106. +
  2107. + spin_lock_irqsave(&ag->lock, flags);
  2108. +
  2109. + curr = (ring->curr % ring->size);
  2110. + dirty = (ring->dirty % ring->size);
  2111. + desc_hw = ag71xx_rr(ag, desc_reg);
  2112. + for (i = 0; i < ring->size; i++) {
  2113. + struct ag71xx_buf *ab = &ring->buf[i];
  2114. + u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size;
  2115. +
  2116. + len += snprintf(buf + len, buflen - len,
  2117. + "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n",
  2118. + i,
  2119. + (i == curr) ? 'C' : ' ',
  2120. + (i == dirty) ? 'D' : ' ',
  2121. + (desc_hw == desc_dma) ? 'H' : ' ',
  2122. + desc_dma,
  2123. + ab->desc->next,
  2124. + ab->desc->data,
  2125. + ab->desc->ctrl,
  2126. + (ab->desc->ctrl & DESC_EMPTY) ? 'E' : '*',
  2127. + ab->timestamp);
  2128. + }
  2129. +
  2130. + spin_unlock_irqrestore(&ag->lock, flags);
  2131. +
  2132. + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  2133. + kfree(buf);
  2134. +
  2135. + return ret;
  2136. +}
  2137. +
  2138. +static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf,
  2139. + size_t count, loff_t *ppos)
  2140. +{
  2141. + struct ag71xx *ag = file->private_data;
  2142. +
  2143. + return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring,
  2144. + AG71XX_REG_TX_DESC);
  2145. +}
  2146. +
  2147. +static const struct file_operations ag71xx_fops_tx_ring = {
  2148. + .open = ag71xx_debugfs_generic_open,
  2149. + .read = read_file_tx_ring,
  2150. + .owner = THIS_MODULE
  2151. +};
  2152. +
  2153. +static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf,
  2154. + size_t count, loff_t *ppos)
  2155. +{
  2156. + struct ag71xx *ag = file->private_data;
  2157. +
  2158. + return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring,
  2159. + AG71XX_REG_RX_DESC);
  2160. +}
  2161. +
  2162. +static const struct file_operations ag71xx_fops_rx_ring = {
  2163. + .open = ag71xx_debugfs_generic_open,
  2164. + .read = read_file_rx_ring,
  2165. + .owner = THIS_MODULE
  2166. +};
  2167. +
  2168. +void ag71xx_debugfs_exit(struct ag71xx *ag)
  2169. +{
  2170. + debugfs_remove_recursive(ag->debug.debugfs_dir);
  2171. +}
  2172. +
  2173. +int ag71xx_debugfs_init(struct ag71xx *ag)
  2174. +{
  2175. + struct device *dev = &ag->pdev->dev;
  2176. +
  2177. + ag->debug.debugfs_dir = debugfs_create_dir(dev_name(dev),
  2178. + ag71xx_debugfs_root);
  2179. + if (!ag->debug.debugfs_dir) {
  2180. + dev_err(dev, "unable to create debugfs directory\n");
  2181. + return -ENOENT;
  2182. + }
  2183. +
  2184. + debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir,
  2185. + ag, &ag71xx_fops_int_stats);
  2186. + debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir,
  2187. + ag, &ag71xx_fops_napi_stats);
  2188. + debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir,
  2189. + ag, &ag71xx_fops_tx_ring);
  2190. + debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir,
  2191. + ag, &ag71xx_fops_rx_ring);
  2192. +
  2193. + return 0;
  2194. +}
  2195. +
  2196. +int ag71xx_debugfs_root_init(void)
  2197. +{
  2198. + if (ag71xx_debugfs_root)
  2199. + return -EBUSY;
  2200. +
  2201. + ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
  2202. + if (!ag71xx_debugfs_root)
  2203. + return -ENOENT;
  2204. +
  2205. + return 0;
  2206. +}
  2207. +
  2208. +void ag71xx_debugfs_root_exit(void)
  2209. +{
  2210. + debugfs_remove(ag71xx_debugfs_root);
  2211. + ag71xx_debugfs_root = NULL;
  2212. +}
  2213. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c
  2214. new file mode 100644
  2215. index 0000000..498fbed
  2216. --- /dev/null
  2217. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c
  2218. @@ -0,0 +1,124 @@
  2219. +/*
  2220. + * Atheros AR71xx built-in ethernet mac driver
  2221. + *
  2222. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  2223. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  2224. + *
  2225. + * Based on Atheros' AG7100 driver
  2226. + *
  2227. + * This program is free software; you can redistribute it and/or modify it
  2228. + * under the terms of the GNU General Public License version 2 as published
  2229. + * by the Free Software Foundation.
  2230. + */
  2231. +
  2232. +#include "ag71xx.h"
  2233. +
  2234. +static int ag71xx_ethtool_get_settings(struct net_device *dev,
  2235. + struct ethtool_cmd *cmd)
  2236. +{
  2237. + struct ag71xx *ag = netdev_priv(dev);
  2238. + struct phy_device *phydev = ag->phy_dev;
  2239. +
  2240. + if (!phydev)
  2241. + return -ENODEV;
  2242. +
  2243. + return phy_ethtool_gset(phydev, cmd);
  2244. +}
  2245. +
  2246. +static int ag71xx_ethtool_set_settings(struct net_device *dev,
  2247. + struct ethtool_cmd *cmd)
  2248. +{
  2249. + struct ag71xx *ag = netdev_priv(dev);
  2250. + struct phy_device *phydev = ag->phy_dev;
  2251. +
  2252. + if (!phydev)
  2253. + return -ENODEV;
  2254. +
  2255. + return phy_ethtool_sset(phydev, cmd);
  2256. +}
  2257. +
  2258. +static void ag71xx_ethtool_get_drvinfo(struct net_device *dev,
  2259. + struct ethtool_drvinfo *info)
  2260. +{
  2261. + struct ag71xx *ag = netdev_priv(dev);
  2262. +
  2263. + strcpy(info->driver, ag->pdev->dev.driver->name);
  2264. + strcpy(info->version, AG71XX_DRV_VERSION);
  2265. + strcpy(info->bus_info, dev_name(&ag->pdev->dev));
  2266. +}
  2267. +
  2268. +static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev)
  2269. +{
  2270. + struct ag71xx *ag = netdev_priv(dev);
  2271. +
  2272. + return ag->msg_enable;
  2273. +}
  2274. +
  2275. +static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level)
  2276. +{
  2277. + struct ag71xx *ag = netdev_priv(dev);
  2278. +
  2279. + ag->msg_enable = msg_level;
  2280. +}
  2281. +
  2282. +static void ag71xx_ethtool_get_ringparam(struct net_device *dev,
  2283. + struct ethtool_ringparam *er)
  2284. +{
  2285. + struct ag71xx *ag = netdev_priv(dev);
  2286. +
  2287. + er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX;
  2288. + er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX;
  2289. + er->rx_mini_max_pending = 0;
  2290. + er->rx_jumbo_max_pending = 0;
  2291. +
  2292. + er->tx_pending = ag->tx_ring.size;
  2293. + er->rx_pending = ag->rx_ring.size;
  2294. + er->rx_mini_pending = 0;
  2295. + er->rx_jumbo_pending = 0;
  2296. +}
  2297. +
  2298. +static int ag71xx_ethtool_set_ringparam(struct net_device *dev,
  2299. + struct ethtool_ringparam *er)
  2300. +{
  2301. + struct ag71xx *ag = netdev_priv(dev);
  2302. + unsigned tx_size;
  2303. + unsigned rx_size;
  2304. + int err;
  2305. +
  2306. + if (er->rx_mini_pending != 0||
  2307. + er->rx_jumbo_pending != 0 ||
  2308. + er->rx_pending == 0 ||
  2309. + er->tx_pending == 0)
  2310. + return -EINVAL;
  2311. +
  2312. + tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ?
  2313. + er->tx_pending : AG71XX_TX_RING_SIZE_MAX;
  2314. +
  2315. + rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ?
  2316. + er->rx_pending : AG71XX_RX_RING_SIZE_MAX;
  2317. +
  2318. + if (netif_running(dev)) {
  2319. + err = dev->netdev_ops->ndo_stop(dev);
  2320. + if (err)
  2321. + return err;
  2322. + }
  2323. +
  2324. + ag->tx_ring.size = tx_size;
  2325. + ag->rx_ring.size = rx_size;
  2326. +
  2327. + if (netif_running(dev))
  2328. + err = dev->netdev_ops->ndo_open(dev);
  2329. +
  2330. + return err;
  2331. +}
  2332. +
  2333. +struct ethtool_ops ag71xx_ethtool_ops = {
  2334. + .set_settings = ag71xx_ethtool_set_settings,
  2335. + .get_settings = ag71xx_ethtool_get_settings,
  2336. + .get_drvinfo = ag71xx_ethtool_get_drvinfo,
  2337. + .get_msglevel = ag71xx_ethtool_get_msglevel,
  2338. + .set_msglevel = ag71xx_ethtool_set_msglevel,
  2339. + .get_ringparam = ag71xx_ethtool_get_ringparam,
  2340. + .set_ringparam = ag71xx_ethtool_set_ringparam,
  2341. + .get_link = ethtool_op_get_link,
  2342. +};
  2343. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
  2344. new file mode 100644
  2345. index 0000000..d010373
  2346. --- /dev/null
  2347. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
  2348. @@ -0,0 +1,1325 @@
  2349. +/*
  2350. + * Atheros AR71xx built-in ethernet mac driver
  2351. + *
  2352. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  2353. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  2354. + *
  2355. + * Based on Atheros' AG7100 driver
  2356. + *
  2357. + * This program is free software; you can redistribute it and/or modify it
  2358. + * under the terms of the GNU General Public License version 2 as published
  2359. + * by the Free Software Foundation.
  2360. + */
  2361. +
  2362. +#include "ag71xx.h"
  2363. +
  2364. +#define AG71XX_DEFAULT_MSG_ENABLE \
  2365. + (NETIF_MSG_DRV \
  2366. + | NETIF_MSG_PROBE \
  2367. + | NETIF_MSG_LINK \
  2368. + | NETIF_MSG_TIMER \
  2369. + | NETIF_MSG_IFDOWN \
  2370. + | NETIF_MSG_IFUP \
  2371. + | NETIF_MSG_RX_ERR \
  2372. + | NETIF_MSG_TX_ERR)
  2373. +
  2374. +static int ag71xx_msg_level = -1;
  2375. +
  2376. +module_param_named(msg_level, ag71xx_msg_level, int, 0);
  2377. +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  2378. +
  2379. +#define ETH_SWITCH_HEADER_LEN 2
  2380. +
  2381. +static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
  2382. +{
  2383. + return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
  2384. +}
  2385. +
  2386. +static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  2387. +{
  2388. + DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  2389. + ag->dev->name,
  2390. + ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  2391. + ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  2392. + ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  2393. +
  2394. + DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  2395. + ag->dev->name,
  2396. + ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  2397. + ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  2398. + ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  2399. +}
  2400. +
  2401. +static void ag71xx_dump_regs(struct ag71xx *ag)
  2402. +{
  2403. + DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  2404. + ag->dev->name,
  2405. + ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  2406. + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  2407. + ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  2408. + ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  2409. + ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  2410. + DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  2411. + ag->dev->name,
  2412. + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  2413. + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  2414. + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  2415. + DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  2416. + ag->dev->name,
  2417. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  2418. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  2419. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  2420. + DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  2421. + ag->dev->name,
  2422. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  2423. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  2424. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  2425. +}
  2426. +
  2427. +static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  2428. +{
  2429. + DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  2430. + ag->dev->name, label, intr,
  2431. + (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  2432. + (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  2433. + (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  2434. + (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  2435. + (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  2436. + (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  2437. +}
  2438. +
  2439. +static void ag71xx_ring_free(struct ag71xx_ring *ring)
  2440. +{
  2441. + kfree(ring->buf);
  2442. +
  2443. + if (ring->descs_cpu)
  2444. + dma_free_coherent(NULL, ring->size * ring->desc_size,
  2445. + ring->descs_cpu, ring->descs_dma);
  2446. +}
  2447. +
  2448. +static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
  2449. +{
  2450. + int err;
  2451. + int i;
  2452. +
  2453. + ring->desc_size = sizeof(struct ag71xx_desc);
  2454. + if (ring->desc_size % cache_line_size()) {
  2455. + DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
  2456. + ring, ring->desc_size,
  2457. + roundup(ring->desc_size, cache_line_size()));
  2458. + ring->desc_size = roundup(ring->desc_size, cache_line_size());
  2459. + }
  2460. +
  2461. + ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
  2462. + &ring->descs_dma, GFP_ATOMIC);
  2463. + if (!ring->descs_cpu) {
  2464. + err = -ENOMEM;
  2465. + goto err;
  2466. + }
  2467. +
  2468. +
  2469. + ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
  2470. + if (!ring->buf) {
  2471. + err = -ENOMEM;
  2472. + goto err;
  2473. + }
  2474. +
  2475. + for (i = 0; i < ring->size; i++) {
  2476. + int idx = i * ring->desc_size;
  2477. + ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
  2478. + DBG("ag71xx: ring %p, desc %d at %p\n",
  2479. + ring, i, ring->buf[i].desc);
  2480. + }
  2481. +
  2482. + return 0;
  2483. +
  2484. +err:
  2485. + return err;
  2486. +}
  2487. +
  2488. +static void ag71xx_ring_tx_clean(struct ag71xx *ag)
  2489. +{
  2490. + struct ag71xx_ring *ring = &ag->tx_ring;
  2491. + struct net_device *dev = ag->dev;
  2492. + u32 bytes_compl = 0, pkts_compl = 0;
  2493. +
  2494. + while (ring->curr != ring->dirty) {
  2495. + u32 i = ring->dirty % ring->size;
  2496. +
  2497. + if (!ag71xx_desc_empty(ring->buf[i].desc)) {
  2498. + ring->buf[i].desc->ctrl = 0;
  2499. + dev->stats.tx_errors++;
  2500. + }
  2501. +
  2502. + if (ring->buf[i].skb) {
  2503. + bytes_compl += ring->buf[i].len;
  2504. + pkts_compl++;
  2505. + dev_kfree_skb_any(ring->buf[i].skb);
  2506. + }
  2507. + ring->buf[i].skb = NULL;
  2508. + ring->dirty++;
  2509. + }
  2510. +
  2511. + /* flush descriptors */
  2512. + wmb();
  2513. +
  2514. + netdev_completed_queue(dev, pkts_compl, bytes_compl);
  2515. +}
  2516. +
  2517. +static void ag71xx_ring_tx_init(struct ag71xx *ag)
  2518. +{
  2519. + struct ag71xx_ring *ring = &ag->tx_ring;
  2520. + int i;
  2521. +
  2522. + for (i = 0; i < ring->size; i++) {
  2523. + ring->buf[i].desc->next = (u32) (ring->descs_dma +
  2524. + ring->desc_size * ((i + 1) % ring->size));
  2525. +
  2526. + ring->buf[i].desc->ctrl = DESC_EMPTY;
  2527. + ring->buf[i].skb = NULL;
  2528. + }
  2529. +
  2530. + /* flush descriptors */
  2531. + wmb();
  2532. +
  2533. + ring->curr = 0;
  2534. + ring->dirty = 0;
  2535. + netdev_reset_queue(ag->dev);
  2536. +}
  2537. +
  2538. +static void ag71xx_ring_rx_clean(struct ag71xx *ag)
  2539. +{
  2540. + struct ag71xx_ring *ring = &ag->rx_ring;
  2541. + int i;
  2542. +
  2543. + if (!ring->buf)
  2544. + return;
  2545. +
  2546. + for (i = 0; i < ring->size; i++)
  2547. + if (ring->buf[i].rx_buf) {
  2548. + dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
  2549. + ag->rx_buf_size, DMA_FROM_DEVICE);
  2550. + kfree(ring->buf[i].rx_buf);
  2551. + }
  2552. +}
  2553. +
  2554. +static int ag71xx_buffer_offset(struct ag71xx *ag)
  2555. +{
  2556. + int offset = NET_SKB_PAD;
  2557. +
  2558. + /*
  2559. + * On AR71xx/AR91xx packets must be 4-byte aligned.
  2560. + *
  2561. + * When using builtin AR8216 support, hardware adds a 2-byte header,
  2562. + * so we don't need any extra alignment in that case.
  2563. + */
  2564. + if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
  2565. + return offset;
  2566. +
  2567. + return offset + NET_IP_ALIGN;
  2568. +}
  2569. +
  2570. +static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
  2571. + int offset)
  2572. +{
  2573. + void *data;
  2574. +
  2575. + data = kmalloc(ag->rx_buf_size +
  2576. + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
  2577. + GFP_ATOMIC);
  2578. + if (!data)
  2579. + return false;
  2580. +
  2581. + buf->rx_buf = data;
  2582. + buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
  2583. + DMA_FROM_DEVICE);
  2584. + buf->desc->data = (u32) buf->dma_addr + offset;
  2585. + return true;
  2586. +}
  2587. +
  2588. +static int ag71xx_ring_rx_init(struct ag71xx *ag)
  2589. +{
  2590. + struct ag71xx_ring *ring = &ag->rx_ring;
  2591. + unsigned int i;
  2592. + int ret;
  2593. + int offset = ag71xx_buffer_offset(ag);
  2594. +
  2595. + ret = 0;
  2596. + for (i = 0; i < ring->size; i++) {
  2597. + ring->buf[i].desc->next = (u32) (ring->descs_dma +
  2598. + ring->desc_size * ((i + 1) % ring->size));
  2599. +
  2600. + DBG("ag71xx: RX desc at %p, next is %08x\n",
  2601. + ring->buf[i].desc,
  2602. + ring->buf[i].desc->next);
  2603. + }
  2604. +
  2605. + for (i = 0; i < ring->size; i++) {
  2606. + if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
  2607. + ret = -ENOMEM;
  2608. + break;
  2609. + }
  2610. +
  2611. + ring->buf[i].desc->ctrl = DESC_EMPTY;
  2612. + }
  2613. +
  2614. + /* flush descriptors */
  2615. + wmb();
  2616. +
  2617. + ring->curr = 0;
  2618. + ring->dirty = 0;
  2619. +
  2620. + return ret;
  2621. +}
  2622. +
  2623. +static int ag71xx_ring_rx_refill(struct ag71xx *ag)
  2624. +{
  2625. + struct ag71xx_ring *ring = &ag->rx_ring;
  2626. + unsigned int count;
  2627. + int offset = ag71xx_buffer_offset(ag);
  2628. +
  2629. + count = 0;
  2630. + for (; ring->curr - ring->dirty > 0; ring->dirty++) {
  2631. + unsigned int i;
  2632. +
  2633. + i = ring->dirty % ring->size;
  2634. +
  2635. + if (!ring->buf[i].rx_buf &&
  2636. + !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
  2637. + break;
  2638. +
  2639. + ring->buf[i].desc->ctrl = DESC_EMPTY;
  2640. + count++;
  2641. + }
  2642. +
  2643. + /* flush descriptors */
  2644. + wmb();
  2645. +
  2646. + DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
  2647. +
  2648. + return count;
  2649. +}
  2650. +
  2651. +static int ag71xx_rings_init(struct ag71xx *ag)
  2652. +{
  2653. + int ret;
  2654. +
  2655. + ret = ag71xx_ring_alloc(&ag->tx_ring);
  2656. + if (ret)
  2657. + return ret;
  2658. +
  2659. + ag71xx_ring_tx_init(ag);
  2660. +
  2661. + ret = ag71xx_ring_alloc(&ag->rx_ring);
  2662. + if (ret)
  2663. + return ret;
  2664. +
  2665. + ret = ag71xx_ring_rx_init(ag);
  2666. + return ret;
  2667. +}
  2668. +
  2669. +static void ag71xx_rings_cleanup(struct ag71xx *ag)
  2670. +{
  2671. + ag71xx_ring_rx_clean(ag);
  2672. + ag71xx_ring_free(&ag->rx_ring);
  2673. +
  2674. + ag71xx_ring_tx_clean(ag);
  2675. + netdev_reset_queue(ag->dev);
  2676. + ag71xx_ring_free(&ag->tx_ring);
  2677. +}
  2678. +
  2679. +static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
  2680. +{
  2681. + switch (ag->speed) {
  2682. + case SPEED_1000:
  2683. + return "1000";
  2684. + case SPEED_100:
  2685. + return "100";
  2686. + case SPEED_10:
  2687. + return "10";
  2688. + }
  2689. +
  2690. + return "?";
  2691. +}
  2692. +
  2693. +static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
  2694. +{
  2695. + u32 t;
  2696. +
  2697. + t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
  2698. + | (((u32) mac[3]) << 8) | ((u32) mac[2]);
  2699. +
  2700. + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
  2701. +
  2702. + t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
  2703. + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
  2704. +}
  2705. +
  2706. +static void ag71xx_dma_reset(struct ag71xx *ag)
  2707. +{
  2708. + u32 val;
  2709. + int i;
  2710. +
  2711. + ag71xx_dump_dma_regs(ag);
  2712. +
  2713. + /* stop RX and TX */
  2714. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
  2715. + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
  2716. +
  2717. + /*
  2718. + * give the hardware some time to really stop all rx/tx activity
  2719. + * clearing the descriptors too early causes random memory corruption
  2720. + */
  2721. + mdelay(1);
  2722. +
  2723. + /* clear descriptor addresses */
  2724. + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
  2725. + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
  2726. +
  2727. + /* clear pending RX/TX interrupts */
  2728. + for (i = 0; i < 256; i++) {
  2729. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
  2730. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
  2731. + }
  2732. +
  2733. + /* clear pending errors */
  2734. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
  2735. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
  2736. +
  2737. + val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
  2738. + if (val)
  2739. + pr_alert("%s: unable to clear DMA Rx status: %08x\n",
  2740. + ag->dev->name, val);
  2741. +
  2742. + val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
  2743. +
  2744. + /* mask out reserved bits */
  2745. + val &= ~0xff000000;
  2746. +
  2747. + if (val)
  2748. + pr_alert("%s: unable to clear DMA Tx status: %08x\n",
  2749. + ag->dev->name, val);
  2750. +
  2751. + ag71xx_dump_dma_regs(ag);
  2752. +}
  2753. +
  2754. +#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
  2755. + MAC_CFG1_SRX | MAC_CFG1_STX)
  2756. +
  2757. +#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
  2758. +
  2759. +#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
  2760. + FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
  2761. + FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
  2762. + FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
  2763. + FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
  2764. + FIFO_CFG4_VT)
  2765. +
  2766. +#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
  2767. + FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
  2768. + FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
  2769. + FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
  2770. + FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
  2771. + FIFO_CFG5_17 | FIFO_CFG5_SF)
  2772. +
  2773. +static void ag71xx_hw_stop(struct ag71xx *ag)
  2774. +{
  2775. + /* disable all interrupts and stop the rx/tx engine */
  2776. + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
  2777. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
  2778. + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
  2779. +}
  2780. +
  2781. +static void ag71xx_hw_setup(struct ag71xx *ag)
  2782. +{
  2783. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  2784. +
  2785. + /* setup MAC configuration registers */
  2786. + ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
  2787. +
  2788. + ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
  2789. + MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
  2790. +
  2791. + /* setup max frame length to zero */
  2792. + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
  2793. +
  2794. + /* setup FIFO configuration registers */
  2795. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
  2796. + if (pdata->is_ar724x) {
  2797. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
  2798. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
  2799. + } else {
  2800. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
  2801. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
  2802. + }
  2803. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
  2804. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
  2805. +}
  2806. +
  2807. +static void ag71xx_hw_init(struct ag71xx *ag)
  2808. +{
  2809. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  2810. + u32 reset_mask = pdata->reset_bit;
  2811. +
  2812. + ag71xx_hw_stop(ag);
  2813. +
  2814. + if (pdata->is_ar724x) {
  2815. + u32 reset_phy = reset_mask;
  2816. +
  2817. + reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
  2818. + reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
  2819. +
  2820. + ath79_device_reset_set(reset_phy);
  2821. + mdelay(50);
  2822. + ath79_device_reset_clear(reset_phy);
  2823. + mdelay(200);
  2824. + }
  2825. +
  2826. + ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
  2827. + udelay(20);
  2828. +
  2829. + ath79_device_reset_set(reset_mask);
  2830. + mdelay(100);
  2831. + ath79_device_reset_clear(reset_mask);
  2832. + mdelay(200);
  2833. +
  2834. + ag71xx_hw_setup(ag);
  2835. +
  2836. + ag71xx_dma_reset(ag);
  2837. +}
  2838. +
  2839. +static void ag71xx_fast_reset(struct ag71xx *ag)
  2840. +{
  2841. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  2842. + struct net_device *dev = ag->dev;
  2843. + u32 reset_mask = pdata->reset_bit;
  2844. + u32 rx_ds, tx_ds;
  2845. + u32 mii_reg;
  2846. +
  2847. + reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
  2848. +
  2849. + mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
  2850. + rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
  2851. + tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
  2852. +
  2853. + ath79_device_reset_set(reset_mask);
  2854. + udelay(10);
  2855. + ath79_device_reset_clear(reset_mask);
  2856. + udelay(10);
  2857. +
  2858. + ag71xx_dma_reset(ag);
  2859. + ag71xx_hw_setup(ag);
  2860. +
  2861. + /* setup max frame length */
  2862. + ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
  2863. + ag71xx_max_frame_len(ag->dev->mtu));
  2864. +
  2865. + ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
  2866. + ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
  2867. + ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
  2868. +
  2869. + ag71xx_hw_set_macaddr(ag, dev->dev_addr);
  2870. +}
  2871. +
  2872. +static void ag71xx_hw_start(struct ag71xx *ag)
  2873. +{
  2874. + /* start RX engine */
  2875. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
  2876. +
  2877. + /* enable interrupts */
  2878. + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
  2879. +}
  2880. +
  2881. +void ag71xx_link_adjust(struct ag71xx *ag)
  2882. +{
  2883. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  2884. + u32 cfg2;
  2885. + u32 ifctl;
  2886. + u32 fifo5;
  2887. +
  2888. + if (!ag->link) {
  2889. + ag71xx_hw_stop(ag);
  2890. + netif_carrier_off(ag->dev);
  2891. + if (netif_msg_link(ag))
  2892. + pr_info("%s: link down\n", ag->dev->name);
  2893. + return;
  2894. + }
  2895. +
  2896. + if (pdata->is_ar724x)
  2897. + ag71xx_fast_reset(ag);
  2898. +
  2899. + cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
  2900. + cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
  2901. + cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
  2902. +
  2903. + ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
  2904. + ifctl &= ~(MAC_IFCTL_SPEED);
  2905. +
  2906. + fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
  2907. + fifo5 &= ~FIFO_CFG5_BM;
  2908. +
  2909. + switch (ag->speed) {
  2910. + case SPEED_1000:
  2911. + cfg2 |= MAC_CFG2_IF_1000;
  2912. + fifo5 |= FIFO_CFG5_BM;
  2913. + break;
  2914. + case SPEED_100:
  2915. + cfg2 |= MAC_CFG2_IF_10_100;
  2916. + ifctl |= MAC_IFCTL_SPEED;
  2917. + break;
  2918. + case SPEED_10:
  2919. + cfg2 |= MAC_CFG2_IF_10_100;
  2920. + break;
  2921. + default:
  2922. + BUG();
  2923. + return;
  2924. + }
  2925. +
  2926. + if (pdata->is_ar91xx)
  2927. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
  2928. + else if (pdata->is_ar724x)
  2929. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
  2930. + else
  2931. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
  2932. +
  2933. + if (pdata->set_speed)
  2934. + pdata->set_speed(ag->speed);
  2935. +
  2936. + ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
  2937. + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
  2938. + ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
  2939. + ag71xx_hw_start(ag);
  2940. +
  2941. + netif_carrier_on(ag->dev);
  2942. + if (netif_msg_link(ag))
  2943. + pr_info("%s: link up (%sMbps/%s duplex)\n",
  2944. + ag->dev->name,
  2945. + ag71xx_speed_str(ag),
  2946. + (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
  2947. +
  2948. + DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
  2949. + ag->dev->name,
  2950. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  2951. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  2952. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  2953. +
  2954. + DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
  2955. + ag->dev->name,
  2956. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  2957. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  2958. + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  2959. +
  2960. + DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
  2961. + ag->dev->name,
  2962. + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  2963. + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
  2964. +}
  2965. +
  2966. +static int ag71xx_open(struct net_device *dev)
  2967. +{
  2968. + struct ag71xx *ag = netdev_priv(dev);
  2969. + unsigned int max_frame_len;
  2970. + int ret;
  2971. +
  2972. + max_frame_len = ag71xx_max_frame_len(dev->mtu);
  2973. + ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
  2974. +
  2975. + /* setup max frame length */
  2976. + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
  2977. +
  2978. + ret = ag71xx_rings_init(ag);
  2979. + if (ret)
  2980. + goto err;
  2981. +
  2982. + napi_enable(&ag->napi);
  2983. +
  2984. + netif_carrier_off(dev);
  2985. + ag71xx_phy_start(ag);
  2986. +
  2987. + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
  2988. + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
  2989. +
  2990. + ag71xx_hw_set_macaddr(ag, dev->dev_addr);
  2991. +
  2992. + netif_start_queue(dev);
  2993. +
  2994. + return 0;
  2995. +
  2996. +err:
  2997. + ag71xx_rings_cleanup(ag);
  2998. + return ret;
  2999. +}
  3000. +
  3001. +static int ag71xx_stop(struct net_device *dev)
  3002. +{
  3003. + struct ag71xx *ag = netdev_priv(dev);
  3004. + unsigned long flags;
  3005. +
  3006. + netif_carrier_off(dev);
  3007. + ag71xx_phy_stop(ag);
  3008. +
  3009. + spin_lock_irqsave(&ag->lock, flags);
  3010. +
  3011. + netif_stop_queue(dev);
  3012. +
  3013. + ag71xx_hw_stop(ag);
  3014. + ag71xx_dma_reset(ag);
  3015. +
  3016. + napi_disable(&ag->napi);
  3017. + del_timer_sync(&ag->oom_timer);
  3018. +
  3019. + spin_unlock_irqrestore(&ag->lock, flags);
  3020. +
  3021. + ag71xx_rings_cleanup(ag);
  3022. +
  3023. + return 0;
  3024. +}
  3025. +
  3026. +static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
  3027. + struct net_device *dev)
  3028. +{
  3029. + struct ag71xx *ag = netdev_priv(dev);
  3030. + struct ag71xx_ring *ring = &ag->tx_ring;
  3031. + struct ag71xx_desc *desc;
  3032. + dma_addr_t dma_addr;
  3033. + int i;
  3034. +
  3035. + i = ring->curr % ring->size;
  3036. + desc = ring->buf[i].desc;
  3037. +
  3038. + if (!ag71xx_desc_empty(desc))
  3039. + goto err_drop;
  3040. +
  3041. + if (ag71xx_has_ar8216(ag))
  3042. + ag71xx_add_ar8216_header(ag, skb);
  3043. +
  3044. + if (skb->len <= 0) {
  3045. + DBG("%s: packet len is too small\n", ag->dev->name);
  3046. + goto err_drop;
  3047. + }
  3048. +
  3049. + dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
  3050. + DMA_TO_DEVICE);
  3051. +
  3052. + netdev_sent_queue(dev, skb->len);
  3053. + ring->buf[i].len = skb->len;
  3054. + ring->buf[i].skb = skb;
  3055. + ring->buf[i].timestamp = jiffies;
  3056. +
  3057. + /* setup descriptor fields */
  3058. + desc->data = (u32) dma_addr;
  3059. + desc->ctrl = skb->len & ag->desc_pktlen_mask;
  3060. +
  3061. + /* flush descriptor */
  3062. + wmb();
  3063. +
  3064. + ring->curr++;
  3065. + if (ring->curr == (ring->dirty + ring->size)) {
  3066. + DBG("%s: tx queue full\n", ag->dev->name);
  3067. + netif_stop_queue(dev);
  3068. + }
  3069. +
  3070. + DBG("%s: packet injected into TX queue\n", ag->dev->name);
  3071. +
  3072. + /* enable TX engine */
  3073. + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
  3074. +
  3075. + return NETDEV_TX_OK;
  3076. +
  3077. +err_drop:
  3078. + dev->stats.tx_dropped++;
  3079. +
  3080. + dev_kfree_skb(skb);
  3081. + return NETDEV_TX_OK;
  3082. +}
  3083. +
  3084. +static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3085. +{
  3086. + struct ag71xx *ag = netdev_priv(dev);
  3087. + int ret;
  3088. +
  3089. + switch (cmd) {
  3090. + case SIOCETHTOOL:
  3091. + if (ag->phy_dev == NULL)
  3092. + break;
  3093. +
  3094. + spin_lock_irq(&ag->lock);
  3095. + ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
  3096. + spin_unlock_irq(&ag->lock);
  3097. + return ret;
  3098. +
  3099. + case SIOCSIFHWADDR:
  3100. + if (copy_from_user
  3101. + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
  3102. + return -EFAULT;
  3103. + return 0;
  3104. +
  3105. + case SIOCGIFHWADDR:
  3106. + if (copy_to_user
  3107. + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
  3108. + return -EFAULT;
  3109. + return 0;
  3110. +
  3111. + case SIOCGMIIPHY:
  3112. + case SIOCGMIIREG:
  3113. + case SIOCSMIIREG:
  3114. + if (ag->phy_dev == NULL)
  3115. + break;
  3116. +
  3117. + return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
  3118. +
  3119. + default:
  3120. + break;
  3121. + }
  3122. +
  3123. + return -EOPNOTSUPP;
  3124. +}
  3125. +
  3126. +static void ag71xx_oom_timer_handler(unsigned long data)
  3127. +{
  3128. + struct net_device *dev = (struct net_device *) data;
  3129. + struct ag71xx *ag = netdev_priv(dev);
  3130. +
  3131. + napi_schedule(&ag->napi);
  3132. +}
  3133. +
  3134. +static void ag71xx_tx_timeout(struct net_device *dev)
  3135. +{
  3136. + struct ag71xx *ag = netdev_priv(dev);
  3137. +
  3138. + if (netif_msg_tx_err(ag))
  3139. + pr_info("%s: tx timeout\n", ag->dev->name);
  3140. +
  3141. + schedule_work(&ag->restart_work);
  3142. +}
  3143. +
  3144. +static void ag71xx_restart_work_func(struct work_struct *work)
  3145. +{
  3146. + struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
  3147. +
  3148. + if (ag71xx_get_pdata(ag)->is_ar724x) {
  3149. + ag->link = 0;
  3150. + ag71xx_link_adjust(ag);
  3151. + return;
  3152. + }
  3153. +
  3154. + ag71xx_stop(ag->dev);
  3155. + ag71xx_open(ag->dev);
  3156. +}
  3157. +
  3158. +static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
  3159. +{
  3160. + u32 rx_sm, tx_sm, rx_fd;
  3161. +
  3162. + if (likely(time_before(jiffies, timestamp + HZ/10)))
  3163. + return false;
  3164. +
  3165. + if (!netif_carrier_ok(ag->dev))
  3166. + return false;
  3167. +
  3168. + rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
  3169. + if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
  3170. + return true;
  3171. +
  3172. + tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
  3173. + rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
  3174. + if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
  3175. + ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
  3176. + return true;
  3177. +
  3178. + return false;
  3179. +}
  3180. +
  3181. +static int ag71xx_tx_packets(struct ag71xx *ag)
  3182. +{
  3183. + struct ag71xx_ring *ring = &ag->tx_ring;
  3184. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  3185. + int sent = 0;
  3186. + int bytes_compl = 0;
  3187. +
  3188. + DBG("%s: processing TX ring\n", ag->dev->name);
  3189. +
  3190. + while (ring->dirty != ring->curr) {
  3191. + unsigned int i = ring->dirty % ring->size;
  3192. + struct ag71xx_desc *desc = ring->buf[i].desc;
  3193. + struct sk_buff *skb = ring->buf[i].skb;
  3194. + int len = ring->buf[i].len;
  3195. +
  3196. + if (!ag71xx_desc_empty(desc)) {
  3197. + if (pdata->is_ar7240 &&
  3198. + ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
  3199. + schedule_work(&ag->restart_work);
  3200. + break;
  3201. + }
  3202. +
  3203. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
  3204. +
  3205. + bytes_compl += len;
  3206. + ag->dev->stats.tx_bytes += len;
  3207. + ag->dev->stats.tx_packets++;
  3208. +
  3209. + dev_kfree_skb_any(skb);
  3210. + ring->buf[i].skb = NULL;
  3211. +
  3212. + ring->dirty++;
  3213. + sent++;
  3214. + }
  3215. +
  3216. + DBG("%s: %d packets sent out\n", ag->dev->name, sent);
  3217. +
  3218. + if (!sent)
  3219. + return 0;
  3220. +
  3221. + netdev_completed_queue(ag->dev, sent, bytes_compl);
  3222. + if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
  3223. + netif_wake_queue(ag->dev);
  3224. +
  3225. + return sent;
  3226. +}
  3227. +
  3228. +static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
  3229. +{
  3230. + struct net_device *dev = ag->dev;
  3231. + struct ag71xx_ring *ring = &ag->rx_ring;
  3232. + int offset = ag71xx_buffer_offset(ag);
  3233. + unsigned int pktlen_mask = ag->desc_pktlen_mask;
  3234. + int done = 0;
  3235. +
  3236. + DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
  3237. + dev->name, limit, ring->curr, ring->dirty);
  3238. +
  3239. + while (done < limit) {
  3240. + unsigned int i = ring->curr % ring->size;
  3241. + struct ag71xx_desc *desc = ring->buf[i].desc;
  3242. + struct sk_buff *skb;
  3243. + int pktlen;
  3244. + int err = 0;
  3245. +
  3246. + if (ag71xx_desc_empty(desc))
  3247. + break;
  3248. +
  3249. + if ((ring->dirty + ring->size) == ring->curr) {
  3250. + ag71xx_assert(0);
  3251. + break;
  3252. + }
  3253. +
  3254. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
  3255. +
  3256. + pktlen = desc->ctrl & pktlen_mask;
  3257. + pktlen -= ETH_FCS_LEN;
  3258. +
  3259. + dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
  3260. + ag->rx_buf_size, DMA_FROM_DEVICE);
  3261. +
  3262. + dev->stats.rx_packets++;
  3263. + dev->stats.rx_bytes += pktlen;
  3264. +
  3265. + skb = build_skb(ring->buf[i].rx_buf, 0);
  3266. + if (!skb) {
  3267. + kfree(ring->buf[i].rx_buf);
  3268. + goto next;
  3269. + }
  3270. +
  3271. + skb_reserve(skb, offset);
  3272. + skb_put(skb, pktlen);
  3273. +
  3274. + if (ag71xx_has_ar8216(ag))
  3275. + err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
  3276. +
  3277. + if (err) {
  3278. + dev->stats.rx_dropped++;
  3279. + kfree_skb(skb);
  3280. + } else {
  3281. + skb->dev = dev;
  3282. + skb->ip_summed = CHECKSUM_NONE;
  3283. + skb->protocol = eth_type_trans(skb, dev);
  3284. + netif_receive_skb(skb);
  3285. + }
  3286. +
  3287. +next:
  3288. + ring->buf[i].rx_buf = NULL;
  3289. + done++;
  3290. +
  3291. + ring->curr++;
  3292. + }
  3293. +
  3294. + ag71xx_ring_rx_refill(ag);
  3295. +
  3296. + DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
  3297. + dev->name, ring->curr, ring->dirty, done);
  3298. +
  3299. + return done;
  3300. +}
  3301. +
  3302. +static int ag71xx_poll(struct napi_struct *napi, int limit)
  3303. +{
  3304. + struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
  3305. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  3306. + struct net_device *dev = ag->dev;
  3307. + struct ag71xx_ring *rx_ring;
  3308. + unsigned long flags;
  3309. + u32 status;
  3310. + int tx_done;
  3311. + int rx_done;
  3312. +
  3313. + pdata->ddr_flush();
  3314. + tx_done = ag71xx_tx_packets(ag);
  3315. +
  3316. + DBG("%s: processing RX ring\n", dev->name);
  3317. + rx_done = ag71xx_rx_packets(ag, limit);
  3318. +
  3319. + ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
  3320. +
  3321. + rx_ring = &ag->rx_ring;
  3322. + if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
  3323. + goto oom;
  3324. +
  3325. + status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
  3326. + if (unlikely(status & RX_STATUS_OF)) {
  3327. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
  3328. + dev->stats.rx_fifo_errors++;
  3329. +
  3330. + /* restart RX */
  3331. + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
  3332. + }
  3333. +
  3334. + if (rx_done < limit) {
  3335. + if (status & RX_STATUS_PR)
  3336. + goto more;
  3337. +
  3338. + status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
  3339. + if (status & TX_STATUS_PS)
  3340. + goto more;
  3341. +
  3342. + DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
  3343. + dev->name, rx_done, tx_done, limit);
  3344. +
  3345. + napi_complete(napi);
  3346. +
  3347. + /* enable interrupts */
  3348. + spin_lock_irqsave(&ag->lock, flags);
  3349. + ag71xx_int_enable(ag, AG71XX_INT_POLL);
  3350. + spin_unlock_irqrestore(&ag->lock, flags);
  3351. + return rx_done;
  3352. + }
  3353. +
  3354. +more:
  3355. + DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
  3356. + dev->name, rx_done, tx_done, limit);
  3357. + return rx_done;
  3358. +
  3359. +oom:
  3360. + if (netif_msg_rx_err(ag))
  3361. + pr_info("%s: out of memory\n", dev->name);
  3362. +
  3363. + mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
  3364. + napi_complete(napi);
  3365. + return 0;
  3366. +}
  3367. +
  3368. +static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
  3369. +{
  3370. + struct net_device *dev = dev_id;
  3371. + struct ag71xx *ag = netdev_priv(dev);
  3372. + u32 status;
  3373. +
  3374. + status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
  3375. + ag71xx_dump_intr(ag, "raw", status);
  3376. +
  3377. + if (unlikely(!status))
  3378. + return IRQ_NONE;
  3379. +
  3380. + if (unlikely(status & AG71XX_INT_ERR)) {
  3381. + if (status & AG71XX_INT_TX_BE) {
  3382. + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
  3383. + dev_err(&dev->dev, "TX BUS error\n");
  3384. + }
  3385. + if (status & AG71XX_INT_RX_BE) {
  3386. + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
  3387. + dev_err(&dev->dev, "RX BUS error\n");
  3388. + }
  3389. + }
  3390. +
  3391. + if (likely(status & AG71XX_INT_POLL)) {
  3392. + ag71xx_int_disable(ag, AG71XX_INT_POLL);
  3393. + DBG("%s: enable polling mode\n", dev->name);
  3394. + napi_schedule(&ag->napi);
  3395. + }
  3396. +
  3397. + ag71xx_debugfs_update_int_stats(ag, status);
  3398. +
  3399. + return IRQ_HANDLED;
  3400. +}
  3401. +
  3402. +#ifdef CONFIG_NET_POLL_CONTROLLER
  3403. +/*
  3404. + * Polling 'interrupt' - used by things like netconsole to send skbs
  3405. + * without having to re-enable interrupts. It's not called while
  3406. + * the interrupt routine is executing.
  3407. + */
  3408. +static void ag71xx_netpoll(struct net_device *dev)
  3409. +{
  3410. + disable_irq(dev->irq);
  3411. + ag71xx_interrupt(dev->irq, dev);
  3412. + enable_irq(dev->irq);
  3413. +}
  3414. +#endif
  3415. +
  3416. +static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
  3417. +{
  3418. + struct ag71xx *ag = netdev_priv(dev);
  3419. + unsigned int max_frame_len;
  3420. +
  3421. + max_frame_len = ag71xx_max_frame_len(new_mtu);
  3422. + if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
  3423. + return -EINVAL;
  3424. +
  3425. + if (netif_running(dev))
  3426. + return -EBUSY;
  3427. +
  3428. + dev->mtu = new_mtu;
  3429. + return 0;
  3430. +}
  3431. +
  3432. +static const struct net_device_ops ag71xx_netdev_ops = {
  3433. + .ndo_open = ag71xx_open,
  3434. + .ndo_stop = ag71xx_stop,
  3435. + .ndo_start_xmit = ag71xx_hard_start_xmit,
  3436. + .ndo_do_ioctl = ag71xx_do_ioctl,
  3437. + .ndo_tx_timeout = ag71xx_tx_timeout,
  3438. + .ndo_change_mtu = ag71xx_change_mtu,
  3439. + .ndo_set_mac_address = eth_mac_addr,
  3440. + .ndo_validate_addr = eth_validate_addr,
  3441. +#ifdef CONFIG_NET_POLL_CONTROLLER
  3442. + .ndo_poll_controller = ag71xx_netpoll,
  3443. +#endif
  3444. +};
  3445. +
  3446. +static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
  3447. +{
  3448. + switch (mode) {
  3449. + case PHY_INTERFACE_MODE_MII:
  3450. + return "MII";
  3451. + case PHY_INTERFACE_MODE_GMII:
  3452. + return "GMII";
  3453. + case PHY_INTERFACE_MODE_RMII:
  3454. + return "RMII";
  3455. + case PHY_INTERFACE_MODE_RGMII:
  3456. + return "RGMII";
  3457. + case PHY_INTERFACE_MODE_SGMII:
  3458. + return "SGMII";
  3459. + default:
  3460. + break;
  3461. + }
  3462. +
  3463. + return "unknown";
  3464. +}
  3465. +
  3466. +
  3467. +static int ag71xx_probe(struct platform_device *pdev)
  3468. +{
  3469. + struct net_device *dev;
  3470. + struct resource *res;
  3471. + struct ag71xx *ag;
  3472. + struct ag71xx_platform_data *pdata;
  3473. + int err;
  3474. +
  3475. + pdata = pdev->dev.platform_data;
  3476. + if (!pdata) {
  3477. + dev_err(&pdev->dev, "no platform data specified\n");
  3478. + err = -ENXIO;
  3479. + goto err_out;
  3480. + }
  3481. +
  3482. + if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
  3483. + dev_err(&pdev->dev, "no MII bus device specified\n");
  3484. + err = -EINVAL;
  3485. + goto err_out;
  3486. + }
  3487. +
  3488. + dev = alloc_etherdev(sizeof(*ag));
  3489. + if (!dev) {
  3490. + dev_err(&pdev->dev, "alloc_etherdev failed\n");
  3491. + err = -ENOMEM;
  3492. + goto err_out;
  3493. + }
  3494. +
  3495. + if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
  3496. + return -EINVAL;
  3497. +
  3498. + SET_NETDEV_DEV(dev, &pdev->dev);
  3499. +
  3500. + ag = netdev_priv(dev);
  3501. + ag->pdev = pdev;
  3502. + ag->dev = dev;
  3503. + ag->msg_enable = netif_msg_init(ag71xx_msg_level,
  3504. + AG71XX_DEFAULT_MSG_ENABLE);
  3505. + spin_lock_init(&ag->lock);
  3506. +
  3507. + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
  3508. + if (!res) {
  3509. + dev_err(&pdev->dev, "no mac_base resource found\n");
  3510. + err = -ENXIO;
  3511. + goto err_out;
  3512. + }
  3513. +
  3514. + ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
  3515. + if (!ag->mac_base) {
  3516. + dev_err(&pdev->dev, "unable to ioremap mac_base\n");
  3517. + err = -ENOMEM;
  3518. + goto err_free_dev;
  3519. + }
  3520. +
  3521. + dev->irq = platform_get_irq(pdev, 0);
  3522. + err = request_irq(dev->irq, ag71xx_interrupt,
  3523. + IRQF_DISABLED,
  3524. + dev->name, dev);
  3525. + if (err) {
  3526. + dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
  3527. + goto err_unmap_base;
  3528. + }
  3529. +
  3530. + dev->base_addr = (unsigned long)ag->mac_base;
  3531. + dev->netdev_ops = &ag71xx_netdev_ops;
  3532. + dev->ethtool_ops = &ag71xx_ethtool_ops;
  3533. +
  3534. + INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
  3535. +
  3536. + init_timer(&ag->oom_timer);
  3537. + ag->oom_timer.data = (unsigned long) dev;
  3538. + ag->oom_timer.function = ag71xx_oom_timer_handler;
  3539. +
  3540. + ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
  3541. + ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
  3542. +
  3543. + ag->max_frame_len = pdata->max_frame_len;
  3544. + ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
  3545. +
  3546. + ag->stop_desc = dma_alloc_coherent(NULL,
  3547. + sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
  3548. +
  3549. + if (!ag->stop_desc)
  3550. + goto err_free_irq;
  3551. +
  3552. + ag->stop_desc->data = 0;
  3553. + ag->stop_desc->ctrl = 0;
  3554. + ag->stop_desc->next = (u32) ag->stop_desc_dma;
  3555. +
  3556. + memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
  3557. +
  3558. + netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
  3559. +
  3560. + ag71xx_dump_regs(ag);
  3561. +
  3562. + ag71xx_hw_init(ag);
  3563. +
  3564. + ag71xx_dump_regs(ag);
  3565. +
  3566. + err = ag71xx_phy_connect(ag);
  3567. + if (err)
  3568. + goto err_free_desc;
  3569. +
  3570. + err = ag71xx_debugfs_init(ag);
  3571. + if (err)
  3572. + goto err_phy_disconnect;
  3573. +
  3574. + platform_set_drvdata(pdev, dev);
  3575. +
  3576. + err = register_netdev(dev);
  3577. + if (err) {
  3578. + dev_err(&pdev->dev, "unable to register net device\n");
  3579. + goto err_debugfs_exit;
  3580. + }
  3581. +
  3582. + pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
  3583. + dev->name, dev->base_addr, dev->irq,
  3584. + ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
  3585. +
  3586. + return 0;
  3587. +
  3588. +err_debugfs_exit:
  3589. + ag71xx_debugfs_exit(ag);
  3590. +err_phy_disconnect:
  3591. + ag71xx_phy_disconnect(ag);
  3592. +err_free_desc:
  3593. + dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
  3594. + ag->stop_desc_dma);
  3595. +err_free_irq:
  3596. + free_irq(dev->irq, dev);
  3597. +err_unmap_base:
  3598. + iounmap(ag->mac_base);
  3599. +err_free_dev:
  3600. + kfree(dev);
  3601. +err_out:
  3602. + platform_set_drvdata(pdev, NULL);
  3603. + return err;
  3604. +}
  3605. +
  3606. +static int ag71xx_remove(struct platform_device *pdev)
  3607. +{
  3608. + struct net_device *dev = platform_get_drvdata(pdev);
  3609. +
  3610. + if (dev) {
  3611. + struct ag71xx *ag = netdev_priv(dev);
  3612. +
  3613. + ag71xx_debugfs_exit(ag);
  3614. + ag71xx_phy_disconnect(ag);
  3615. + unregister_netdev(dev);
  3616. + free_irq(dev->irq, dev);
  3617. + iounmap(ag->mac_base);
  3618. + kfree(dev);
  3619. + platform_set_drvdata(pdev, NULL);
  3620. + }
  3621. +
  3622. + return 0;
  3623. +}
  3624. +
  3625. +static struct platform_driver ag71xx_driver = {
  3626. + .probe = ag71xx_probe,
  3627. + .remove = ag71xx_remove,
  3628. + .driver = {
  3629. + .name = AG71XX_DRV_NAME,
  3630. + }
  3631. +};
  3632. +
  3633. +static int __init ag71xx_module_init(void)
  3634. +{
  3635. + int ret;
  3636. +
  3637. + ret = ag71xx_debugfs_root_init();
  3638. + if (ret)
  3639. + goto err_out;
  3640. +
  3641. + ret = ag71xx_mdio_driver_init();
  3642. + if (ret)
  3643. + goto err_debugfs_exit;
  3644. +
  3645. + ret = platform_driver_register(&ag71xx_driver);
  3646. + if (ret)
  3647. + goto err_mdio_exit;
  3648. +
  3649. + return 0;
  3650. +
  3651. +err_mdio_exit:
  3652. + ag71xx_mdio_driver_exit();
  3653. +err_debugfs_exit:
  3654. + ag71xx_debugfs_root_exit();
  3655. +err_out:
  3656. + return ret;
  3657. +}
  3658. +
  3659. +static void __exit ag71xx_module_exit(void)
  3660. +{
  3661. + platform_driver_unregister(&ag71xx_driver);
  3662. + ag71xx_mdio_driver_exit();
  3663. + ag71xx_debugfs_root_exit();
  3664. +}
  3665. +
  3666. +module_init(ag71xx_module_init);
  3667. +module_exit(ag71xx_module_exit);
  3668. +
  3669. +MODULE_VERSION(AG71XX_DRV_VERSION);
  3670. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  3671. +MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
  3672. +MODULE_LICENSE("GPL v2");
  3673. +MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
  3674. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c
  3675. new file mode 100644
  3676. index 0000000..71ae825
  3677. --- /dev/null
  3678. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c
  3679. @@ -0,0 +1,318 @@
  3680. +/*
  3681. + * Atheros AR71xx built-in ethernet mac driver
  3682. + *
  3683. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  3684. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  3685. + *
  3686. + * Based on Atheros' AG7100 driver
  3687. + *
  3688. + * This program is free software; you can redistribute it and/or modify it
  3689. + * under the terms of the GNU General Public License version 2 as published
  3690. + * by the Free Software Foundation.
  3691. + */
  3692. +
  3693. +#include "ag71xx.h"
  3694. +
  3695. +#define AG71XX_MDIO_RETRY 1000
  3696. +#define AG71XX_MDIO_DELAY 5
  3697. +
  3698. +static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg,
  3699. + u32 value)
  3700. +{
  3701. + void __iomem *r;
  3702. +
  3703. + r = am->mdio_base + reg;
  3704. + __raw_writel(value, r);
  3705. +
  3706. + /* flush write */
  3707. + (void) __raw_readl(r);
  3708. +}
  3709. +
  3710. +static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg)
  3711. +{
  3712. + return __raw_readl(am->mdio_base + reg);
  3713. +}
  3714. +
  3715. +static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am)
  3716. +{
  3717. + DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n",
  3718. + am->mii_bus->name,
  3719. + ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG),
  3720. + ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD),
  3721. + ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR));
  3722. + DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n",
  3723. + am->mii_bus->name,
  3724. + ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL),
  3725. + ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS),
  3726. + ag71xx_mdio_rr(am, AG71XX_REG_MII_IND));
  3727. +}
  3728. +
  3729. +static int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am)
  3730. +{
  3731. + int i;
  3732. +
  3733. + for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
  3734. + u32 busy;
  3735. +
  3736. + udelay(AG71XX_MDIO_DELAY);
  3737. +
  3738. + busy = ag71xx_mdio_rr(am, AG71XX_REG_MII_IND);
  3739. + if (!busy)
  3740. + return 0;
  3741. +
  3742. + udelay(AG71XX_MDIO_DELAY);
  3743. + }
  3744. +
  3745. + pr_err("%s: MDIO operation timed out\n", am->mii_bus->name);
  3746. +
  3747. + return -ETIMEDOUT;
  3748. +}
  3749. +
  3750. +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg)
  3751. +{
  3752. + int err;
  3753. + int ret;
  3754. +
  3755. + err = ag71xx_mdio_wait_busy(am);
  3756. + if (err)
  3757. + return 0xffff;
  3758. +
  3759. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  3760. + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  3761. + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  3762. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ);
  3763. +
  3764. + err = ag71xx_mdio_wait_busy(am);
  3765. + if (err)
  3766. + return 0xffff;
  3767. +
  3768. + ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff;
  3769. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  3770. +
  3771. + DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
  3772. +
  3773. + return ret;
  3774. +}
  3775. +
  3776. +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val)
  3777. +{
  3778. + DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
  3779. +
  3780. + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
  3781. + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  3782. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val);
  3783. +
  3784. + ag71xx_mdio_wait_busy(am);
  3785. +}
  3786. +
  3787. +static const u32 ar71xx_mdio_div_table[] = {
  3788. + 4, 4, 6, 8, 10, 14, 20, 28,
  3789. +};
  3790. +
  3791. +static const u32 ar7240_mdio_div_table[] = {
  3792. + 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
  3793. +};
  3794. +
  3795. +static const u32 ar933x_mdio_div_table[] = {
  3796. + 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
  3797. +};
  3798. +
  3799. +static int ag71xx_mdio_get_divider(struct ag71xx_mdio *am, u32 *div)
  3800. +{
  3801. + unsigned long ref_clock, mdio_clock;
  3802. + const u32 *table;
  3803. + int ndivs;
  3804. + int i;
  3805. +
  3806. + ref_clock = am->pdata->ref_clock;
  3807. + mdio_clock = am->pdata->mdio_clock;
  3808. +
  3809. + if (!ref_clock || !mdio_clock)
  3810. + return -EINVAL;
  3811. +
  3812. + if (am->pdata->is_ar9330 || am->pdata->is_ar934x) {
  3813. + table = ar933x_mdio_div_table;
  3814. + ndivs = ARRAY_SIZE(ar933x_mdio_div_table);
  3815. + } else if (am->pdata->is_ar7240) {
  3816. + table = ar7240_mdio_div_table;
  3817. + ndivs = ARRAY_SIZE(ar7240_mdio_div_table);
  3818. + } else {
  3819. + table = ar71xx_mdio_div_table;
  3820. + ndivs = ARRAY_SIZE(ar71xx_mdio_div_table);
  3821. + }
  3822. +
  3823. + for (i = 0; i < ndivs; i++) {
  3824. + unsigned long t;
  3825. +
  3826. + t = ref_clock / table[i];
  3827. + if (t <= mdio_clock) {
  3828. + *div = i;
  3829. + return 0;
  3830. + }
  3831. + }
  3832. +
  3833. + dev_err(&am->mii_bus->dev, "no divider found for %lu/%lu\n",
  3834. + ref_clock, mdio_clock);
  3835. + return -ENOENT;
  3836. +}
  3837. +
  3838. +static int ag71xx_mdio_reset(struct mii_bus *bus)
  3839. +{
  3840. + struct ag71xx_mdio *am = bus->priv;
  3841. + u32 t;
  3842. + int err;
  3843. +
  3844. + err = ag71xx_mdio_get_divider(am, &t);
  3845. + if (err) {
  3846. + /* fallback */
  3847. + if (am->pdata->is_ar7240)
  3848. + t = MII_CFG_CLK_DIV_6;
  3849. + else if (am->pdata->builtin_switch && !am->pdata->is_ar934x)
  3850. + t = MII_CFG_CLK_DIV_10;
  3851. + else if (!am->pdata->builtin_switch && am->pdata->is_ar934x)
  3852. + t = MII_CFG_CLK_DIV_58;
  3853. + else
  3854. + t = MII_CFG_CLK_DIV_28;
  3855. + }
  3856. +
  3857. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
  3858. + udelay(100);
  3859. +
  3860. + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t);
  3861. + udelay(100);
  3862. +
  3863. + if (am->pdata->reset)
  3864. + am->pdata->reset(bus);
  3865. +
  3866. + return 0;
  3867. +}
  3868. +
  3869. +static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg)
  3870. +{
  3871. + struct ag71xx_mdio *am = bus->priv;
  3872. +
  3873. + if (am->pdata->builtin_switch)
  3874. + return ar7240sw_phy_read(bus, addr, reg);
  3875. + else
  3876. + return ag71xx_mdio_mii_read(am, addr, reg);
  3877. +}
  3878. +
  3879. +static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
  3880. +{
  3881. + struct ag71xx_mdio *am = bus->priv;
  3882. +
  3883. + if (am->pdata->builtin_switch)
  3884. + ar7240sw_phy_write(bus, addr, reg, val);
  3885. + else
  3886. + ag71xx_mdio_mii_write(am, addr, reg, val);
  3887. + return 0;
  3888. +}
  3889. +
  3890. +static int ag71xx_mdio_probe(struct platform_device *pdev)
  3891. +{
  3892. + struct ag71xx_mdio_platform_data *pdata;
  3893. + struct ag71xx_mdio *am;
  3894. + struct resource *res;
  3895. + int i;
  3896. + int err;
  3897. +
  3898. + pdata = pdev->dev.platform_data;
  3899. + if (!pdata) {
  3900. + dev_err(&pdev->dev, "no platform data specified\n");
  3901. + return -EINVAL;
  3902. + }
  3903. +
  3904. + am = kzalloc(sizeof(*am), GFP_KERNEL);
  3905. + if (!am) {
  3906. + err = -ENOMEM;
  3907. + goto err_out;
  3908. + }
  3909. +
  3910. + am->pdata = pdata;
  3911. +
  3912. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3913. + if (!res) {
  3914. + dev_err(&pdev->dev, "no iomem resource found\n");
  3915. + err = -ENXIO;
  3916. + goto err_out;
  3917. + }
  3918. +
  3919. + am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1);
  3920. + if (!am->mdio_base) {
  3921. + dev_err(&pdev->dev, "unable to ioremap registers\n");
  3922. + err = -ENOMEM;
  3923. + goto err_free_mdio;
  3924. + }
  3925. +
  3926. + am->mii_bus = mdiobus_alloc();
  3927. + if (am->mii_bus == NULL) {
  3928. + err = -ENOMEM;
  3929. + goto err_iounmap;
  3930. + }
  3931. +
  3932. + am->mii_bus->name = "ag71xx_mdio";
  3933. + am->mii_bus->read = ag71xx_mdio_read;
  3934. + am->mii_bus->write = ag71xx_mdio_write;
  3935. + am->mii_bus->reset = ag71xx_mdio_reset;
  3936. + am->mii_bus->irq = am->mii_irq;
  3937. + am->mii_bus->priv = am;
  3938. + am->mii_bus->parent = &pdev->dev;
  3939. + snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
  3940. + am->mii_bus->phy_mask = pdata->phy_mask;
  3941. +
  3942. + for (i = 0; i < PHY_MAX_ADDR; i++)
  3943. + am->mii_irq[i] = PHY_POLL;
  3944. +
  3945. + ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0);
  3946. +
  3947. + err = mdiobus_register(am->mii_bus);
  3948. + if (err)
  3949. + goto err_free_bus;
  3950. +
  3951. + ag71xx_mdio_dump_regs(am);
  3952. +
  3953. + platform_set_drvdata(pdev, am);
  3954. + return 0;
  3955. +
  3956. +err_free_bus:
  3957. + mdiobus_free(am->mii_bus);
  3958. +err_iounmap:
  3959. + iounmap(am->mdio_base);
  3960. +err_free_mdio:
  3961. + kfree(am);
  3962. +err_out:
  3963. + return err;
  3964. +}
  3965. +
  3966. +static int ag71xx_mdio_remove(struct platform_device *pdev)
  3967. +{
  3968. + struct ag71xx_mdio *am = platform_get_drvdata(pdev);
  3969. +
  3970. + if (am) {
  3971. + mdiobus_unregister(am->mii_bus);
  3972. + mdiobus_free(am->mii_bus);
  3973. + iounmap(am->mdio_base);
  3974. + kfree(am);
  3975. + platform_set_drvdata(pdev, NULL);
  3976. + }
  3977. +
  3978. + return 0;
  3979. +}
  3980. +
  3981. +static struct platform_driver ag71xx_mdio_driver = {
  3982. + .probe = ag71xx_mdio_probe,
  3983. + .remove = ag71xx_mdio_remove,
  3984. + .driver = {
  3985. + .name = "ag71xx-mdio",
  3986. + }
  3987. +};
  3988. +
  3989. +int __init ag71xx_mdio_driver_init(void)
  3990. +{
  3991. + return platform_driver_register(&ag71xx_mdio_driver);
  3992. +}
  3993. +
  3994. +void ag71xx_mdio_driver_exit(void)
  3995. +{
  3996. + platform_driver_unregister(&ag71xx_mdio_driver);
  3997. +}
  3998. diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
  3999. new file mode 100644
  4000. index 0000000..9de77e9
  4001. --- /dev/null
  4002. +++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
  4003. @@ -0,0 +1,235 @@
  4004. +/*
  4005. + * Atheros AR71xx built-in ethernet mac driver
  4006. + *
  4007. + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  4008. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  4009. + *
  4010. + * Based on Atheros' AG7100 driver
  4011. + *
  4012. + * This program is free software; you can redistribute it and/or modify it
  4013. + * under the terms of the GNU General Public License version 2 as published
  4014. + * by the Free Software Foundation.
  4015. + */
  4016. +
  4017. +#include "ag71xx.h"
  4018. +
  4019. +static void ag71xx_phy_link_adjust(struct net_device *dev)
  4020. +{
  4021. + struct ag71xx *ag = netdev_priv(dev);
  4022. + struct phy_device *phydev = ag->phy_dev;
  4023. + unsigned long flags;
  4024. + int status_change = 0;
  4025. +
  4026. + spin_lock_irqsave(&ag->lock, flags);
  4027. +
  4028. + if (phydev->link) {
  4029. + if (ag->duplex != phydev->duplex
  4030. + || ag->speed != phydev->speed) {
  4031. + status_change = 1;
  4032. + }
  4033. + }
  4034. +
  4035. + if (phydev->link != ag->link)
  4036. + status_change = 1;
  4037. +
  4038. + ag->link = phydev->link;
  4039. + ag->duplex = phydev->duplex;
  4040. + ag->speed = phydev->speed;
  4041. +
  4042. + if (status_change)
  4043. + ag71xx_link_adjust(ag);
  4044. +
  4045. + spin_unlock_irqrestore(&ag->lock, flags);
  4046. +}
  4047. +
  4048. +void ag71xx_phy_start(struct ag71xx *ag)
  4049. +{
  4050. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  4051. +
  4052. + if (ag->phy_dev) {
  4053. + phy_start(ag->phy_dev);
  4054. + } else if (pdata->mii_bus_dev && pdata->switch_data) {
  4055. + ag71xx_ar7240_start(ag);
  4056. + } else {
  4057. + ag->link = 1;
  4058. + ag71xx_link_adjust(ag);
  4059. + }
  4060. +}
  4061. +
  4062. +void ag71xx_phy_stop(struct ag71xx *ag)
  4063. +{
  4064. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  4065. + unsigned long flags;
  4066. +
  4067. + if (ag->phy_dev)
  4068. + phy_stop(ag->phy_dev);
  4069. + else if (pdata->mii_bus_dev && pdata->switch_data)
  4070. + ag71xx_ar7240_stop(ag);
  4071. +
  4072. + spin_lock_irqsave(&ag->lock, flags);
  4073. + if (ag->link) {
  4074. + ag->link = 0;
  4075. + ag71xx_link_adjust(ag);
  4076. + }
  4077. + spin_unlock_irqrestore(&ag->lock, flags);
  4078. +}
  4079. +
  4080. +static int ag71xx_phy_connect_fixed(struct ag71xx *ag)
  4081. +{
  4082. + struct device *dev = &ag->pdev->dev;
  4083. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  4084. + int ret = 0;
  4085. +
  4086. + /* use fixed settings */
  4087. + switch (pdata->speed) {
  4088. + case SPEED_10:
  4089. + case SPEED_100:
  4090. + case SPEED_1000:
  4091. + break;
  4092. + default:
  4093. + dev_err(dev, "invalid speed specified\n");
  4094. + ret = -EINVAL;
  4095. + break;
  4096. + }
  4097. +
  4098. + dev_dbg(dev, "using fixed link parameters\n");
  4099. +
  4100. + ag->duplex = pdata->duplex;
  4101. + ag->speed = pdata->speed;
  4102. +
  4103. + return ret;
  4104. +}
  4105. +
  4106. +static int ag71xx_phy_connect_multi(struct ag71xx *ag)
  4107. +{
  4108. + struct device *dev = &ag->pdev->dev;
  4109. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  4110. + struct phy_device *phydev = NULL;
  4111. + int phy_addr;
  4112. + int ret = 0;
  4113. +
  4114. + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  4115. + if (!(pdata->phy_mask & (1 << phy_addr)))
  4116. + continue;
  4117. +
  4118. + if (ag->mii_bus->phy_map[phy_addr] == NULL)
  4119. + continue;
  4120. +
  4121. + DBG("%s: PHY found at %s, uid=%08x\n",
  4122. + dev_name(dev),
  4123. + dev_name(&ag->mii_bus->phy_map[phy_addr]->dev),
  4124. + ag->mii_bus->phy_map[phy_addr]->phy_id);
  4125. +
  4126. + if (phydev == NULL)
  4127. + phydev = ag->mii_bus->phy_map[phy_addr];
  4128. + }
  4129. +
  4130. + if (!phydev) {
  4131. + dev_err(dev, "no PHY found with phy_mask=%08x\n",
  4132. + pdata->phy_mask);
  4133. + return -ENODEV;
  4134. + }
  4135. +
  4136. + ag->phy_dev = phy_connect(ag->dev, dev_name(&phydev->dev),
  4137. + &ag71xx_phy_link_adjust,
  4138. + pdata->phy_if_mode);
  4139. +
  4140. + if (IS_ERR(ag->phy_dev)) {
  4141. + dev_err(dev, "could not connect to PHY at %s\n",
  4142. + dev_name(&phydev->dev));
  4143. + return PTR_ERR(ag->phy_dev);
  4144. + }
  4145. +
  4146. + /* mask with MAC supported features */
  4147. + if (pdata->has_gbit)
  4148. + phydev->supported &= PHY_GBIT_FEATURES;
  4149. + else
  4150. + phydev->supported &= PHY_BASIC_FEATURES;
  4151. +
  4152. + phydev->advertising = phydev->supported;
  4153. +
  4154. + dev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n",
  4155. + dev_name(&phydev->dev), phydev->phy_id, phydev->drv->name);
  4156. +
  4157. + ag->link = 0;
  4158. + ag->speed = 0;
  4159. + ag->duplex = -1;
  4160. +
  4161. + return ret;
  4162. +}
  4163. +
  4164. +static int dev_is_class(struct device *dev, void *class)
  4165. +{
  4166. + if (dev->class != NULL && !strcmp(dev->class->name, class))
  4167. + return 1;
  4168. +
  4169. + return 0;
  4170. +}
  4171. +
  4172. +static struct device *dev_find_class(struct device *parent, char *class)
  4173. +{
  4174. + if (dev_is_class(parent, class)) {
  4175. + get_device(parent);
  4176. + return parent;
  4177. + }
  4178. +
  4179. + return device_find_child(parent, class, dev_is_class);
  4180. +}
  4181. +
  4182. +static struct mii_bus *dev_to_mii_bus(struct device *dev)
  4183. +{
  4184. + struct device *d;
  4185. +
  4186. + d = dev_find_class(dev, "mdio_bus");
  4187. + if (d != NULL) {
  4188. + struct mii_bus *bus;
  4189. +
  4190. + bus = to_mii_bus(d);
  4191. + put_device(d);
  4192. +
  4193. + return bus;
  4194. + }
  4195. +
  4196. + return NULL;
  4197. +}
  4198. +
  4199. +int ag71xx_phy_connect(struct ag71xx *ag)
  4200. +{
  4201. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  4202. +
  4203. + if (pdata->mii_bus_dev == NULL ||
  4204. + pdata->mii_bus_dev->bus == NULL )
  4205. + return ag71xx_phy_connect_fixed(ag);
  4206. +
  4207. + ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev);
  4208. + if (ag->mii_bus == NULL) {
  4209. + dev_err(&ag->pdev->dev, "unable to find MII bus on device '%s'\n",
  4210. + dev_name(pdata->mii_bus_dev));
  4211. + return -ENODEV;
  4212. + }
  4213. +
  4214. + /* Reset the mdio bus explicitly */
  4215. + if (ag->mii_bus->reset) {
  4216. + mutex_lock(&ag->mii_bus->mdio_lock);
  4217. + ag->mii_bus->reset(ag->mii_bus);
  4218. + mutex_unlock(&ag->mii_bus->mdio_lock);
  4219. + }
  4220. +
  4221. + if (pdata->switch_data)
  4222. + return ag71xx_ar7240_init(ag);
  4223. +
  4224. + if (pdata->phy_mask)
  4225. + return ag71xx_phy_connect_multi(ag);
  4226. +
  4227. + return ag71xx_phy_connect_fixed(ag);
  4228. +}
  4229. +
  4230. +void ag71xx_phy_disconnect(struct ag71xx *ag)
  4231. +{
  4232. + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  4233. +
  4234. + if (pdata->switch_data)
  4235. + ag71xx_ar7240_cleanup(ag);
  4236. + else if (ag->phy_dev)
  4237. + phy_disconnect(ag->phy_dev);
  4238. +}
  4239. --
  4240. 1.8.5.3