mips-gcc-44.patch 5.6 KB

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  1. diff -Nur linux-2.6.29.4.orig/arch/mips/include/asm/compiler.h linux-2.6.29.4/arch/mips/include/asm/compiler.h
  2. --- linux-2.6.29.4.orig/arch/mips/include/asm/compiler.h 2009-05-19 01:52:34.000000000 +0200
  3. +++ linux-2.6.29.4/arch/mips/include/asm/compiler.h 2009-05-24 19:32:14.000000000 +0200
  4. @@ -16,4 +16,11 @@
  5. #define GCC_REG_ACCUM "accum"
  6. #endif
  7. +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
  8. +#define GCC_NO_H_CONSTRAINT
  9. +#ifdef CONFIG_64BIT
  10. +typedef unsigned int uint128_t __attribute__((mode(TI)));
  11. +#endif
  12. +#endif
  13. +
  14. #endif /* _ASM_COMPILER_H */
  15. diff -Nur linux-2.6.29.4.orig/arch/mips/include/asm/delay.h linux-2.6.29.4/arch/mips/include/asm/delay.h
  16. --- linux-2.6.29.4.orig/arch/mips/include/asm/delay.h 2009-05-19 01:52:34.000000000 +0200
  17. +++ linux-2.6.29.4/arch/mips/include/asm/delay.h 2009-05-24 19:32:14.000000000 +0200
  18. @@ -62,8 +62,9 @@
  19. static inline void __udelay(unsigned long usecs, unsigned long lpj)
  20. {
  21. +#ifndef GCC_NO_H_CONSTRAINT
  22. unsigned long hi, lo;
  23. -
  24. +#endif
  25. /*
  26. * The rates of 128 is rounded wrongly by the catchall case
  27. * for 64-bit. Excessive precission? Probably ...
  28. @@ -77,6 +78,17 @@
  29. 0x80000000ULL) >> 32);
  30. #endif
  31. +#ifdef GCC_NO_H_CONSTRAINT
  32. +#ifdef CONFIG_64BIT
  33. + usecs = ((uint128_t)usecs * lpj) >> 64;
  34. +#else
  35. +#define SZHALF (sizeof(long)*4)
  36. +#define LOWERHALF ((0x1ul<<SZHALF) - 1)
  37. + usecs = (usecs >> SZHALF) * (lpj >> SZHALF) + ( ((usecs & LOWERHALF) * (lpj >> SZHALF) + (usecs >> SZHALF) * (lpj & LOWERHALF)) >> SZHALF );
  38. +#undef SZHALF
  39. +#undef LOWERHALF
  40. +#endif
  41. +#else
  42. if (sizeof(long) == 4)
  43. __asm__("multu\t%2, %3"
  44. : "=h" (usecs), "=l" (lo)
  45. @@ -92,7 +104,7 @@
  46. : "=r" (usecs), "=h" (hi), "=l" (lo)
  47. : "r" (usecs), "r" (lpj)
  48. : GCC_REG_ACCUM);
  49. -
  50. +#endif
  51. __delay(usecs);
  52. }
  53. diff -Nur linux-2.6.29.4.orig/arch/mips/include/asm/div64.h linux-2.6.29.4/arch/mips/include/asm/div64.h
  54. --- linux-2.6.29.4.orig/arch/mips/include/asm/div64.h 2009-05-19 01:52:34.000000000 +0200
  55. +++ linux-2.6.29.4/arch/mips/include/asm/div64.h 2009-05-22 13:38:14.000000000 +0200
  56. @@ -6,105 +6,63 @@
  57. * License. See the file "COPYING" in the main directory of this archive
  58. * for more details.
  59. */
  60. -#ifndef _ASM_DIV64_H
  61. -#define _ASM_DIV64_H
  62. +#ifndef __ASM_DIV64_H
  63. +#define __ASM_DIV64_H
  64. -#include <linux/types.h>
  65. +#include <asm-generic/div64.h>
  66. -#if (_MIPS_SZLONG == 32)
  67. +#if BITS_PER_LONG == 64
  68. -#include <asm/compiler.h>
  69. +#include <linux/types.h>
  70. /*
  71. * No traps on overflows for any of these...
  72. */
  73. -#define do_div64_32(res, high, low, base) ({ \
  74. - unsigned long __quot32, __mod32; \
  75. - unsigned long __cf, __tmp, __tmp2, __i; \
  76. - \
  77. - __asm__(".set push\n\t" \
  78. - ".set noat\n\t" \
  79. - ".set noreorder\n\t" \
  80. - "move %2, $0\n\t" \
  81. - "move %3, $0\n\t" \
  82. - "b 1f\n\t" \
  83. - " li %4, 0x21\n" \
  84. - "0:\n\t" \
  85. - "sll $1, %0, 0x1\n\t" \
  86. - "srl %3, %0, 0x1f\n\t" \
  87. - "or %0, $1, %5\n\t" \
  88. - "sll %1, %1, 0x1\n\t" \
  89. - "sll %2, %2, 0x1\n" \
  90. - "1:\n\t" \
  91. - "bnez %3, 2f\n\t" \
  92. - " sltu %5, %0, %z6\n\t" \
  93. - "bnez %5, 3f\n" \
  94. - "2:\n\t" \
  95. - " addiu %4, %4, -1\n\t" \
  96. - "subu %0, %0, %z6\n\t" \
  97. - "addiu %2, %2, 1\n" \
  98. - "3:\n\t" \
  99. - "bnez %4, 0b\n\t" \
  100. - " srl %5, %1, 0x1f\n\t" \
  101. - ".set pop" \
  102. - : "=&r" (__mod32), "=&r" (__tmp), \
  103. - "=&r" (__quot32), "=&r" (__cf), \
  104. - "=&r" (__i), "=&r" (__tmp2) \
  105. - : "Jr" (base), "0" (high), "1" (low)); \
  106. - \
  107. - (res) = __quot32; \
  108. - __mod32; })
  109. -
  110. -#define do_div(n, base) ({ \
  111. - unsigned long long __quot; \
  112. - unsigned long __mod; \
  113. - unsigned long long __div; \
  114. - unsigned long __upper, __low, __high, __base; \
  115. - \
  116. - __div = (n); \
  117. - __base = (base); \
  118. - \
  119. - __high = __div >> 32; \
  120. - __low = __div; \
  121. - __upper = __high; \
  122. - \
  123. - if (__high) \
  124. - __asm__("divu $0, %z2, %z3" \
  125. - : "=h" (__upper), "=l" (__high) \
  126. - : "Jr" (__high), "Jr" (__base) \
  127. - : GCC_REG_ACCUM); \
  128. - \
  129. - __mod = do_div64_32(__low, __upper, __low, __base); \
  130. - \
  131. - __quot = __high; \
  132. - __quot = __quot << 32 | __low; \
  133. - (n) = __quot; \
  134. - __mod; })
  135. -
  136. -#endif /* (_MIPS_SZLONG == 32) */
  137. -
  138. -#if (_MIPS_SZLONG == 64)
  139. -
  140. -/*
  141. - * Hey, we're already 64-bit, no
  142. - * need to play games..
  143. - */
  144. -#define do_div(n, base) ({ \
  145. - unsigned long __quot; \
  146. - unsigned int __mod; \
  147. - unsigned long __div; \
  148. - unsigned int __base; \
  149. - \
  150. - __div = (n); \
  151. - __base = (base); \
  152. - \
  153. - __mod = __div % __base; \
  154. - __quot = __div / __base; \
  155. - \
  156. - (n) = __quot; \
  157. - __mod; })
  158. +#define __div64_32(n, base) \
  159. +({ \
  160. + unsigned long __cf, __tmp, __tmp2, __i; \
  161. + unsigned long __quot32, __mod32; \
  162. + unsigned long __high, __low; \
  163. + unsigned long long __n; \
  164. + \
  165. + __high = *__n >> 32; \
  166. + __low = __n; \
  167. + __asm__( \
  168. + " .set push \n" \
  169. + " .set noat \n" \
  170. + " .set noreorder \n" \
  171. + " move %2, $0 \n" \
  172. + " move %3, $0 \n" \
  173. + " b 1f \n" \
  174. + " li %4, 0x21 \n" \
  175. + "0: \n" \
  176. + " sll $1, %0, 0x1 \n" \
  177. + " srl %3, %0, 0x1f \n" \
  178. + " or %0, $1, %5 \n" \
  179. + " sll %1, %1, 0x1 \n" \
  180. + " sll %2, %2, 0x1 \n" \
  181. + "1: \n" \
  182. + " bnez %3, 2f \n" \
  183. + " sltu %5, %0, %z6 \n" \
  184. + " bnez %5, 3f \n" \
  185. + "2: \n" \
  186. + " addiu %4, %4, -1 \n" \
  187. + " subu %0, %0, %z6 \n" \
  188. + " addiu %2, %2, 1 \n" \
  189. + "3: \n" \
  190. + " bnez %4, 0b\n\t" \
  191. + " srl %5, %1, 0x1f\n\t" \
  192. + " .set pop" \
  193. + : "=&r" (__mod32), "=&r" (__tmp), \
  194. + "=&r" (__quot32), "=&r" (__cf), \
  195. + "=&r" (__i), "=&r" (__tmp2) \
  196. + : "Jr" (base), "0" (__high), "1" (__low)); \
  197. + \
  198. + (__n) = __quot32; \
  199. + __mod32; \
  200. +})
  201. -#endif /* (_MIPS_SZLONG == 64) */
  202. +#endif /* BITS_PER_LONG == 64 */
  203. -#endif /* _ASM_DIV64_H */
  204. +#endif /* __ASM_DIV64_H */