mips-fpu.patch 10 KB

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  1. diff -Nur linux-3.14.67.orig/arch/mips/include/asm/asmmacro-32.h linux-3.14.67/arch/mips/include/asm/asmmacro-32.h
  2. --- linux-3.14.67.orig/arch/mips/include/asm/asmmacro-32.h 2016-04-20 08:41:04.000000000 +0200
  3. +++ linux-3.14.67/arch/mips/include/asm/asmmacro-32.h 2016-04-27 16:18:41.729238756 +0200
  4. @@ -13,6 +13,8 @@
  5. #include <asm/mipsregs.h>
  6. .macro fpu_save_single thread tmp=t0
  7. + .set push
  8. + SET_HARDFLOAT
  9. cfc1 \tmp, fcr31
  10. swc1 $f0, THREAD_FPR0(\thread)
  11. swc1 $f1, THREAD_FPR1(\thread)
  12. @@ -47,9 +49,12 @@
  13. swc1 $f30, THREAD_FPR30(\thread)
  14. swc1 $f31, THREAD_FPR31(\thread)
  15. sw \tmp, THREAD_FCR31(\thread)
  16. + .set pop
  17. .endm
  18. .macro fpu_restore_single thread tmp=t0
  19. + .set push
  20. + SET_HARDFLOAT
  21. lw \tmp, THREAD_FCR31(\thread)
  22. lwc1 $f0, THREAD_FPR0(\thread)
  23. lwc1 $f1, THREAD_FPR1(\thread)
  24. @@ -84,6 +89,7 @@
  25. lwc1 $f30, THREAD_FPR30(\thread)
  26. lwc1 $f31, THREAD_FPR31(\thread)
  27. ctc1 \tmp, fcr31
  28. + .set pop
  29. .endm
  30. .macro cpu_save_nonscratch thread
  31. diff -Nur linux-3.14.67.orig/arch/mips/include/asm/asmmacro.h linux-3.14.67/arch/mips/include/asm/asmmacro.h
  32. --- linux-3.14.67.orig/arch/mips/include/asm/asmmacro.h 2016-04-20 08:41:04.000000000 +0200
  33. +++ linux-3.14.67/arch/mips/include/asm/asmmacro.h 2016-04-27 16:18:41.729238756 +0200
  34. @@ -74,6 +74,8 @@
  35. #endif /* CONFIG_MIPS_MT_SMTC */
  36. .macro fpu_save_16even thread tmp=t0
  37. + .set push
  38. + SET_HARDFLOAT
  39. cfc1 \tmp, fcr31
  40. sdc1 $f0, THREAD_FPR0(\thread)
  41. sdc1 $f2, THREAD_FPR2(\thread)
  42. @@ -127,6 +129,8 @@
  43. .endm
  44. .macro fpu_restore_16even thread tmp=t0
  45. + .set push
  46. + SET_HARDFLOAT
  47. lw \tmp, THREAD_FCR31(\thread)
  48. ldc1 $f0, THREAD_FPR0(\thread)
  49. ldc1 $f2, THREAD_FPR2(\thread)
  50. diff -Nur linux-3.14.67.orig/arch/mips/include/asm/fpregdef.h linux-3.14.67/arch/mips/include/asm/fpregdef.h
  51. --- linux-3.14.67.orig/arch/mips/include/asm/fpregdef.h 2016-04-20 08:41:04.000000000 +0200
  52. +++ linux-3.14.67/arch/mips/include/asm/fpregdef.h 2016-04-27 16:18:41.729238756 +0200
  53. @@ -14,6 +14,20 @@
  54. #include <asm/sgidefs.h>
  55. +/*
  56. + * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
  57. + * hardfloat and softfloat object files. The kernel build uses soft-float by
  58. + * default, so we also need to pass -msoft-float along to GAS if it supports it.
  59. + * But this in turn causes assembler errors in files which access hardfloat
  60. + * registers. We detect if GAS supports "-msoft-float" in the Makefile and
  61. + * explicitly put ".set hardfloat" where floating point registers are touched.
  62. + */
  63. +#ifdef GAS_HAS_SET_HARDFLOAT
  64. +#define SET_HARDFLOAT .set hardfloat
  65. +#else
  66. +#define SET_HARDFLOAT
  67. +#endif
  68. +
  69. #if _MIPS_SIM == _MIPS_SIM_ABI32
  70. /*
  71. diff -Nur linux-3.14.67.orig/arch/mips/include/asm/mipsregs.h linux-3.14.67/arch/mips/include/asm/mipsregs.h
  72. --- linux-3.14.67.orig/arch/mips/include/asm/mipsregs.h 2016-04-20 08:41:04.000000000 +0200
  73. +++ linux-3.14.67/arch/mips/include/asm/mipsregs.h 2016-04-27 16:18:41.729238756 +0200
  74. @@ -1251,7 +1251,7 @@
  75. /*
  76. * Macros to access the floating point coprocessor control registers
  77. */
  78. -#define read_32bit_cp1_register(source) \
  79. +#define _read_32bit_cp1_register(source, gas_hardfloat) \
  80. ({ \
  81. int __res; \
  82. \
  83. @@ -1261,12 +1261,21 @@
  84. " # gas fails to assemble cfc1 for some archs, \n" \
  85. " # like Octeon. \n" \
  86. " .set mips1 \n" \
  87. + " "STR(gas_hardfloat)" \n" \
  88. " cfc1 %0,"STR(source)" \n" \
  89. " .set pop \n" \
  90. : "=r" (__res)); \
  91. __res; \
  92. })
  93. +#ifdef GAS_HAS_SET_HARDFLOAT
  94. +#define read_32bit_cp1_register(source) \
  95. + _read_32bit_cp1_register(source, .set hardfloat)
  96. +#else
  97. +#define read_32bit_cp1_register(source) \
  98. + _read_32bit_cp1_register(source, )
  99. +#endif
  100. +
  101. #ifdef HAVE_AS_DSP
  102. #define rddsp(mask) \
  103. ({ \
  104. diff -Nur linux-3.14.67.orig/arch/mips/kernel/genex.S linux-3.14.67/arch/mips/kernel/genex.S
  105. --- linux-3.14.67.orig/arch/mips/kernel/genex.S 2016-04-20 08:41:04.000000000 +0200
  106. +++ linux-3.14.67/arch/mips/kernel/genex.S 2016-04-27 16:18:41.729238756 +0200
  107. @@ -408,6 +408,7 @@
  108. .set push
  109. /* gas fails to assemble cfc1 for some archs (octeon).*/ \
  110. .set mips1
  111. + SET_HARDFLOAT
  112. cfc1 a1, fcr31
  113. li a2, ~(0x3f << 12)
  114. and a2, a1
  115. diff -Nur linux-3.14.67.orig/arch/mips/kernel/r2300_fpu.S linux-3.14.67/arch/mips/kernel/r2300_fpu.S
  116. --- linux-3.14.67.orig/arch/mips/kernel/r2300_fpu.S 2016-04-20 08:41:04.000000000 +0200
  117. +++ linux-3.14.67/arch/mips/kernel/r2300_fpu.S 2016-04-27 16:18:41.729238756 +0200
  118. @@ -28,6 +28,8 @@
  119. .set mips1
  120. /* Save floating point context */
  121. LEAF(_save_fp_context)
  122. + .set push
  123. + SET_HARDFLOAT
  124. li v0, 0 # assume success
  125. cfc1 t1,fcr31
  126. EX(swc1 $f0,(SC_FPREGS+0)(a0))
  127. @@ -65,6 +67,7 @@
  128. EX(sw t1,(SC_FPC_CSR)(a0))
  129. cfc1 t0,$0 # implementation/version
  130. jr ra
  131. + .set pop
  132. .set nomacro
  133. EX(sw t0,(SC_FPC_EIR)(a0))
  134. .set macro
  135. @@ -80,6 +83,8 @@
  136. * stack frame which might have been changed by the user.
  137. */
  138. LEAF(_restore_fp_context)
  139. + .set push
  140. + SET_HARDFLOAT
  141. li v0, 0 # assume success
  142. EX(lw t0,(SC_FPC_CSR)(a0))
  143. EX(lwc1 $f0,(SC_FPREGS+0)(a0))
  144. @@ -116,6 +121,7 @@
  145. EX(lwc1 $f31,(SC_FPREGS+248)(a0))
  146. jr ra
  147. ctc1 t0,fcr31
  148. + .set pop
  149. END(_restore_fp_context)
  150. .set reorder
  151. diff -Nur linux-3.14.67.orig/arch/mips/kernel/r2300_switch.S linux-3.14.67/arch/mips/kernel/r2300_switch.S
  152. --- linux-3.14.67.orig/arch/mips/kernel/r2300_switch.S 2016-04-20 08:41:04.000000000 +0200
  153. +++ linux-3.14.67/arch/mips/kernel/r2300_switch.S 2016-04-27 16:18:41.729238756 +0200
  154. @@ -120,6 +120,9 @@
  155. #define FPU_DEFAULT 0x00000000
  156. + .set push
  157. + SET_HARDFLOAT
  158. +
  159. LEAF(_init_fpu)
  160. mfc0 t0, CP0_STATUS
  161. li t1, ST0_CU1
  162. @@ -165,3 +168,5 @@
  163. mtc1 t0, $f31
  164. jr ra
  165. END(_init_fpu)
  166. +
  167. + .set pop
  168. diff -Nur linux-3.14.67.orig/arch/mips/kernel/r4k_fpu.S linux-3.14.67/arch/mips/kernel/r4k_fpu.S
  169. --- linux-3.14.67.orig/arch/mips/kernel/r4k_fpu.S 2016-04-20 08:41:04.000000000 +0200
  170. +++ linux-3.14.67/arch/mips/kernel/r4k_fpu.S 2016-04-27 16:18:41.729238756 +0200
  171. @@ -19,8 +19,12 @@
  172. #include <asm/asm-offsets.h>
  173. #include <asm/regdef.h>
  174. +/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
  175. +#undef fp
  176. +
  177. .macro EX insn, reg, src
  178. .set push
  179. + SET_HARDFLOAT
  180. .set nomacro
  181. .ex\@: \insn \reg, \src
  182. .set pop
  183. @@ -33,12 +37,17 @@
  184. .set mips3
  185. LEAF(_save_fp_context)
  186. + .set push
  187. + SET_HARDFLOAT
  188. cfc1 t1, fcr31
  189. + .set pop
  190. #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
  191. .set push
  192. + SET_HARDFLOAT
  193. #ifdef CONFIG_CPU_MIPS32_R2
  194. - .set mips64r2
  195. + .set mips32r2
  196. + .set fp=64
  197. mfc0 t0, CP0_STATUS
  198. sll t0, t0, 5
  199. bgez t0, 1f # skip storing odd if FR=0
  200. @@ -64,6 +73,8 @@
  201. 1: .set pop
  202. #endif
  203. + .set push
  204. + SET_HARDFLOAT
  205. /* Store the 16 even double precision registers */
  206. EX sdc1 $f0, SC_FPREGS+0(a0)
  207. EX sdc1 $f2, SC_FPREGS+16(a0)
  208. @@ -84,11 +95,14 @@
  209. EX sw t1, SC_FPC_CSR(a0)
  210. jr ra
  211. li v0, 0 # success
  212. + .set pop
  213. END(_save_fp_context)
  214. #ifdef CONFIG_MIPS32_COMPAT
  215. /* Save 32-bit process floating point context */
  216. LEAF(_save_fp_context32)
  217. + .set push
  218. + SET_HARDFLOAT
  219. cfc1 t1, fcr31
  220. mfc0 t0, CP0_STATUS
  221. @@ -134,6 +148,7 @@
  222. EX sw t1, SC32_FPC_CSR(a0)
  223. cfc1 t0, $0 # implementation/version
  224. EX sw t0, SC32_FPC_EIR(a0)
  225. + .set pop
  226. jr ra
  227. li v0, 0 # success
  228. @@ -150,8 +165,10 @@
  229. #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
  230. .set push
  231. + SET_HARDFLOAT
  232. #ifdef CONFIG_CPU_MIPS32_R2
  233. - .set mips64r2
  234. + .set mips32r2
  235. + .set fp=64
  236. mfc0 t0, CP0_STATUS
  237. sll t0, t0, 5
  238. bgez t0, 1f # skip loading odd if FR=0
  239. @@ -175,6 +192,8 @@
  240. EX ldc1 $f31, SC_FPREGS+248(a0)
  241. 1: .set pop
  242. #endif
  243. + .set push
  244. + SET_HARDFLOAT
  245. EX ldc1 $f0, SC_FPREGS+0(a0)
  246. EX ldc1 $f2, SC_FPREGS+16(a0)
  247. EX ldc1 $f4, SC_FPREGS+32(a0)
  248. @@ -192,6 +211,7 @@
  249. EX ldc1 $f28, SC_FPREGS+224(a0)
  250. EX ldc1 $f30, SC_FPREGS+240(a0)
  251. ctc1 t1, fcr31
  252. + .set pop
  253. jr ra
  254. li v0, 0 # success
  255. END(_restore_fp_context)
  256. @@ -199,6 +219,8 @@
  257. #ifdef CONFIG_MIPS32_COMPAT
  258. LEAF(_restore_fp_context32)
  259. /* Restore an o32 sigcontext. */
  260. + .set push
  261. + SET_HARDFLOAT
  262. EX lw t1, SC32_FPC_CSR(a0)
  263. mfc0 t0, CP0_STATUS
  264. @@ -242,6 +264,7 @@
  265. ctc1 t1, fcr31
  266. jr ra
  267. li v0, 0 # success
  268. + .set pop
  269. END(_restore_fp_context32)
  270. #endif
  271. diff -Nur linux-3.14.67.orig/arch/mips/kernel/r4k_switch.S linux-3.14.67/arch/mips/kernel/r4k_switch.S
  272. --- linux-3.14.67.orig/arch/mips/kernel/r4k_switch.S 2016-04-20 08:41:04.000000000 +0200
  273. +++ linux-3.14.67/arch/mips/kernel/r4k_switch.S 2016-04-27 16:18:41.729238756 +0200
  274. @@ -22,6 +22,9 @@
  275. #include <asm/asmmacro.h>
  276. +/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
  277. +#undef fp
  278. +
  279. /*
  280. * Offset to the current process status flags, the first 32 bytes of the
  281. * stack are not used.
  282. @@ -151,6 +154,9 @@
  283. #define FPU_DEFAULT 0x00000000
  284. + .set push
  285. + SET_HARDFLOAT
  286. +
  287. LEAF(_init_fpu)
  288. #ifdef CONFIG_MIPS_MT_SMTC
  289. /* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
  290. @@ -231,7 +237,8 @@
  291. #ifdef CONFIG_CPU_MIPS32_R2
  292. .set push
  293. - .set mips64r2
  294. + .set mips32r2
  295. + .set fp=64
  296. sll t0, t0, 5 # is Status.FR set?
  297. bgez t0, 1f # no: skip setting upper 32b
  298. @@ -290,3 +297,5 @@
  299. #endif
  300. jr ra
  301. END(_init_fpu)
  302. +
  303. + .set pop /* SET_HARDFLOAT */
  304. diff -Nur linux-3.14.67.orig/arch/mips/kernel/r6000_fpu.S linux-3.14.67/arch/mips/kernel/r6000_fpu.S
  305. --- linux-3.14.67.orig/arch/mips/kernel/r6000_fpu.S 2016-04-20 08:41:04.000000000 +0200
  306. +++ linux-3.14.67/arch/mips/kernel/r6000_fpu.S 2016-04-27 16:18:41.729238756 +0200
  307. @@ -18,6 +18,9 @@
  308. .set noreorder
  309. .set mips2
  310. + .set push
  311. + SET_HARDFLOAT
  312. +
  313. /* Save floating point context */
  314. LEAF(_save_fp_context)
  315. mfc0 t0,CP0_STATUS
  316. @@ -85,3 +88,5 @@
  317. 1: jr ra
  318. nop
  319. END(_restore_fp_context)
  320. +
  321. + .set pop /* SET_HARDFLOAT */
  322. diff -Nur linux-3.14.67.orig/arch/mips/Makefile linux-3.14.67/arch/mips/Makefile
  323. --- linux-3.14.67.orig/arch/mips/Makefile 2016-04-20 08:41:04.000000000 +0200
  324. +++ linux-3.14.67/arch/mips/Makefile 2016-04-27 16:18:41.729238756 +0200
  325. @@ -93,6 +93,15 @@
  326. KBUILD_AFLAGS_MODULE += -mlong-calls
  327. KBUILD_CFLAGS_MODULE += -mlong-calls
  328. +#
  329. +# pass -msoft-float to GAS if it supports it. However on newer binutils
  330. +# (specifically newer than 2.24.51.20140728) we then also need to explicitly
  331. +# set ".set hardfloat" in all files which manipulate floating point registers.
  332. +#
  333. +ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
  334. + cflags-y += -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
  335. +endif
  336. +
  337. cflags-y += -ffreestanding
  338. #