| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566 |
- From 44e34cb50f2d25848a85a59adbc561eee66278e8 Mon Sep 17 00:00:00 2001
- From: Yimin Gu <ustcymgu@gmail.com>
- Date: Wed, 14 Dec 2022 06:49:46 -0500
- Subject: [PATCH] elf2flt: add RISC-V 32-bit support
- Allow elf2flt to work with RISC-V 32-bit targets. With these changes, the
- uclibc toolchain and busybox can work fine for rv32 no MMU systems with
- no noticable problem.
- Signed-off-by: Charles Lohr <lohr85@gmail.com>
- [Rebased onto latest tree for upstreaming]
- Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
- [Add more ELF relco types and edit commit message]
- Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
- ---
- elf2flt.c | 6 ++++--
- ld-elf2flt.c | 2 +-
- 2 files changed, 5 insertions(+), 3 deletions(-)
- diff --git a/elf2flt.c b/elf2flt.c
- index f37cfa2..04b6b43 100644
- --- a/elf2flt.c
- +++ b/elf2flt.c
- @@ -81,7 +81,7 @@ const char *elf2flt_progname;
- #include <elf/v850.h>
- #elif defined(TARGET_xtensa)
- #include <elf/xtensa.h>
- -#elif defined(TARGET_riscv64)
- +#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
- #include <elf/riscv.h>
- #endif
-
- @@ -127,6 +127,8 @@ const char *elf2flt_progname;
- #define ARCH "xtensa"
- #elif defined(TARGET_riscv64)
- #define ARCH "riscv64"
- +#elif defined(TARGET_riscv32)
- +#define ARCH "riscv32"
- #else
- #error "Don't know how to support your CPU architecture??"
- #endif
- @@ -822,7 +824,7 @@ output_relocs (
- goto good_32bit_resolved_reloc_update_text;
- default:
- goto bad_resolved_reloc;
- -#elif defined(TARGET_riscv64)
- +#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
- case R_RISCV_NONE:
- case R_RISCV_32_PCREL:
- case R_RISCV_ADD8:
- diff --git a/ld-elf2flt.c b/ld-elf2flt.c
- index 75ee1bb..68b2a4a 100644
- --- a/ld-elf2flt.c
- +++ b/ld-elf2flt.c
- @@ -327,7 +327,7 @@ static int do_final_link(void)
- /* riscv adds a global pointer symbol to the linker file with the
- "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
- the entire line for other architectures. */
- - if (streq(TARGET_CPU, "riscv64"))
- + if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
- append_sed(&sed, "^RISCV_GP:", "");
- else
- append_sed(&sed, "^RISCV_GP:", NULL);
- --
- 2.30.2
|
