0001-riscv32.patch 1.5 KB

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  1. diff -Nur elf2flt-v2023.04.orig/elf2flt.c elf2flt-v2023.04/elf2flt.c
  2. --- elf2flt-v2023.04.orig/elf2flt.c 2023-09-04 11:29:05.952417209 +0200
  3. +++ elf2flt-v2023.04/elf2flt.c 2023-09-04 11:30:05.371065966 +0200
  4. @@ -81,7 +81,7 @@
  5. #include <elf/v850.h>
  6. #elif defined(TARGET_xtensa)
  7. #include <elf/xtensa.h>
  8. -#elif defined(TARGET_riscv64)
  9. +#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
  10. #include <elf/riscv.h>
  11. #endif
  12. @@ -127,6 +127,8 @@
  13. #define ARCH "xtensa"
  14. #elif defined(TARGET_riscv64)
  15. #define ARCH "riscv64"
  16. +#elif defined(TARGET_riscv32)
  17. +#define ARCH "riscv32"
  18. #else
  19. #error "Don't know how to support your CPU architecture??"
  20. #endif
  21. @@ -822,7 +824,7 @@
  22. goto good_32bit_resolved_reloc_update_text;
  23. default:
  24. goto bad_resolved_reloc;
  25. -#elif defined(TARGET_riscv64)
  26. +#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
  27. case R_RISCV_NONE:
  28. case R_RISCV_32_PCREL:
  29. case R_RISCV_ADD8:
  30. diff -Nur elf2flt-v2023.04.orig/ld-elf2flt.c elf2flt-v2023.04/ld-elf2flt.c
  31. --- elf2flt-v2023.04.orig/ld-elf2flt.c 2023-09-04 11:28:59.072573514 +0200
  32. +++ elf2flt-v2023.04/ld-elf2flt.c 2023-09-04 11:29:32.507813592 +0200
  33. @@ -327,7 +327,7 @@
  34. /* riscv adds a global pointer symbol to the linker file with the
  35. "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
  36. the entire line for other architectures. */
  37. - if (streq(TARGET_CPU, "riscv64"))
  38. + if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
  39. append_sed(&sed, "^RISCV_GP:", "");
  40. else
  41. append_sed(&sed, "^RISCV_GP:", NULL);