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@@ -20,6 +20,76 @@
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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+#ifdef __MAVERICK__
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+
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+/* DSPSC register: (from EP9312 User's Guide)
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+ *
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+ * bits 31..29 - DAID
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+ * bits 28..26 - HVID
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+ * bits 25..24 - RSVD
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+ * bit 23 - ISAT
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+ * bit 22 - UI
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+ * bit 21 - INT
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+ * bit 20 - AEXC
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+ * bits 19..18 - SAT
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+ * bits 17..16 - FCC
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+ * bit 15 - V
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+ * bit 14 - FWDEN
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+ * bit 13 - Invalid
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+ * bit 12 - Denorm
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+ * bits 11..10 - RM
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+ * bits 9..5 - IXE, UFE, OFE, RSVD, IOE
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+ * bits 4..0 - IX, UF, OF, RSVD, IO
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+ */
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+
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+/* masking of interrupts */
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+#define _FPU_MASK_IM (1 << 5) /* invalid operation */
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+#define _FPU_MASK_ZM 0 /* divide by zero */
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+#define _FPU_MASK_OM (1 << 7) /* overflow */
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+#define _FPU_MASK_UM (1 << 8) /* underflow */
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+#define _FPU_MASK_PM (1 << 9) /* inexact */
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+#define _FPU_MASK_DM 0 /* denormalized operation */
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+
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+#define _FPU_RESERVED 0xfffff000 /* These bits are reserved. */
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+
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+#define _FPU_DEFAULT 0x00b00000 /* Default value. */
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+#define _FPU_IEEE 0x00b003a0 /* Default + exceptions enabled. */
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+
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+/* Type of the control word. */
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+typedef unsigned int fpu_control_t;
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+
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+/* Macros for accessing the hardware control word. */
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+#define _FPU_GETCW(cw) ({ \
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+ register int __t1, __t2; \
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+ \
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+ __asm__ volatile ( \
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+ "cfmvr64l %1, mvdx0\n\t" \
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+ "cfmvr64h %2, mvdx0\n\t" \
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+ "cfmv32sc mvdx0, dspsc\n\t" \
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+ "cfmvr64l %0, mvdx0\n\t" \
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+ "cfmv64lr mvdx0, %1\n\t" \
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+ "cfmv64hr mvdx0, %2" \
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+ : "=r" (cw), "=r" (__t1), "=r" (__t2) \
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+ ); \
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+})
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+
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+#define _FPU_SETCW(cw) ({ \
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+ register int __t0, __t1, __t2; \
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+ \
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+ __asm__ volatile ( \
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+ "cfmvr64l %1, mvdx0\n\t" \
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+ "cfmvr64h %2, mvdx0\n\t" \
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+ "cfmv64lr mvdx0, %0\n\t" \
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+ "cfmvsc32 dspsc, mvdx0\n\t" \
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+ "cfmv64lr mvdx0, %1\n\t" \
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+ "cfmv64hr mvdx0, %2" \
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+ : "=r" (__t0), "=r" (__t1), "=r" (__t2) \
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+ : "0" (cw) \
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+ ); \
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+})
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+
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+#else /* !__MAVERICK__ */
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+
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/* We have a slight terminology confusion here. On the ARM, the register
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* we're interested in is actually the FPU status word - the FPU control
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* word is something different (which is implementation-defined and only
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@@ -96,6 +166,8 @@ typedef unsigned int fpu_control_t;
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#define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
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#define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
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+#endif /* __MAVERICK__ */
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+
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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