sh4: Fixes for SH-4 without an FPU

This patch disables SH-4 optimizations that rely on the FPU when
building for variants that don't have an FPU, such as SH-4AL.

Signed-off-by: Andrew Stubbs <ams@codesourcery.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>

libc/string/sh/sh4/memcpy.S

@@ -21,7 +21,7 @@
 #include <sysdep.h>
 #include <endian.h>
 
-#ifdef __LITTLE_ENDIAN__
+#if defined (__LITTLE_ENDIAN__) && defined (__SH_FPU_ANY__)
 #define	MEMCPY_USES_FPU
 /* Use paired single precision load or store mode for 64-bit tranfering.
  * FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300.

libc/string/sh/sh4/memmove.c

@@ -7,8 +7,11 @@
  * Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
  */
 
-#include <string.h>
+#ifndef __SH_FPU_ANY__
+#include "../../generic/memmove.c"
+#else
 
+#include <string.h>
 
 #define FPSCR_SR	(1 << 20)
 #define STORE_FPSCR(x)	__asm__ volatile("sts fpscr, %0" : "=r"(x))
@@ -115,3 +118,4 @@ void *memmove(void *dest, const void *src, size_t len)
 }
 
 libc_hidden_def(memmove)
+#endif /*__SH_FPU_ANY__ */

libc/string/sh/sh4/memset.S

@@ -17,7 +17,7 @@
 
 #include <sysdep.h>
 
-#ifdef __LITTLE_ENDIAN__
+#if defined (__LITTLE_ENDIAN__) && defined (__SH_FPU_ANY__)
 #define MEMSET_USES_FPU
 /* Use paired single precision load or store mode for 64-bit tranfering.
  * FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300.