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@@ -1,4 +1,4 @@
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-/* Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
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+/* Copyright (C) 1998, 1999, 2002, 2004, 2005 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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@@ -26,7 +26,110 @@
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included in <signal.h>. */
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#include <bits/sigcontext.h>
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-typedef struct sigcontext mcontext_t;
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+#if __WORDSIZE == 32
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+
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+/* Number of general registers. */
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+# define NGREG 48
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+
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+/* Container for all general registers. */
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+typedef unsigned long gregset_t[NGREG];
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+
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+/* Container for floating-point registers and status */
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+typedef struct _libc_fpstate
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+{
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+ double fpregs[32];
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+ double fpscr;
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+ unsigned int _pad[2];
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+} fpregset_t;
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+
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+/* Container for Altivec/VMX registers and status.
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+ Needs to be aligned on a 16-byte boundary. */
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+typedef struct _libc_vrstate
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+{
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+ unsigned int vrregs[32][4];
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+ unsigned int vrsave;
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+ unsigned int _pad[2];
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+ unsigned int vscr;
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+} vrregset_t;
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+
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+/* Context to describe whole processor state. */
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+typedef struct
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+{
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+ gregset_t gregs;
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+ fpregset_t fpregs;
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+ vrregset_t vrregs __attribute__((__aligned__(16)));
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+} mcontext_t;
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+
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+#else
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+
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+/* For 64-bit kernels with Altivec support, a machine context is exactly
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+ * a sigcontext. For older kernel (without Altivec) the sigcontext matches
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+ * the mcontext upto but not including the v_regs field. For kernels that
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+ * don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the
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+ * v_regs field may not exit and should not be referenced. The v_regd field
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+ * can be refernced safely only after verifying that PPC_FEATURE_HAS_ALTIVEC
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+ * is set in AT_HWCAP. */
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+
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+/* Number of general registers. */
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+# define NGREG 48 /* includes r0-r31, nip, msr, lr, etc. */
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+# define NFPREG 33 /* includes fp0-fp31 &fpscr. */
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+# define NVRREG 34 /* includes v0-v31, vscr, & vrsave in split vectors */
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+
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+typedef unsigned long gregset_t[NGREG];
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+typedef double fpregset_t[NFPREG];
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+
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+/* Container for Altivec/VMX Vector Status and Control Register. Only 32-bits
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+ but can only be copied to/from a 128-bit vector register. So we allocated
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+ a whole quadword speedup save/restore. */
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+typedef struct _libc_vscr
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+{
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+ unsigned int __pad[3];
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+ unsigned int vscr_word;
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+} vscr_t;
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+
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+/* Container for Altivec/VMX registers and status.
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+ Must to be aligned on a 16-byte boundary. */
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+typedef struct _libc_vrstate
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+{
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+ unsigned int vrregs[32][4];
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+ vscr_t vscr;
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+ unsigned int vrsave;
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+ unsigned int __pad[3];
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+} vrregset_t __attribute__((__aligned__(16)));
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+
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+typedef struct {
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+ unsigned long __unused[4];
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+ int signal;
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+ int __pad0;
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+ unsigned long handler;
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+ unsigned long oldmask;
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+ struct pt_regs *regs;
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+ gregset_t gp_regs;
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+ fpregset_t fp_regs;
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+/*
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+ * To maintain compatibility with current implementations the sigcontext is
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+ * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
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+ * followed by an unstructured (vmx_reserve) field of 69 doublewords. This
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+ * allows the array of vector registers to be quadword aligned independent of
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+ * the alignment of the containing sigcontext or ucontext. It is the
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+ * responsibility of the code setting the sigcontext to set this pointer to
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+ * either NULL (if this processor does not support the VMX feature) or the
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+ * address of the first quadword within the allocated (vmx_reserve) area.
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+ *
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+ * The pointer (v_regs) of vector type (elf_vrreg_t) is essentually
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+ * an array of 34 quadword entries. The entries with
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+ * indexes 0-31 contain the corresponding vector registers. The entry with
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+ * index 32 contains the vscr as the last word (offset 12) within the
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+ * quadword. This allows the vscr to be stored as either a quadword (since
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+ * it must be copied via a vector register to/from storage) or as a word.
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+ * The entry with index 33 contains the vrsave as the first word (offset 0)
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+ * within the quadword.
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+ */
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+ vrregset_t *v_regs;
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+ long vmx_reserve[NVRREG+NVRREG+1];
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+} mcontext_t;
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+
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+#endif
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/* Userlevel context. */
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typedef struct ucontext
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@@ -34,8 +137,41 @@ typedef struct ucontext
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unsigned long int uc_flags;
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struct ucontext *uc_link;
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stack_t uc_stack;
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- mcontext_t uc_mcontext;
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- __sigset_t uc_sigmask;
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+#if __WORDSIZE == 32
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+ /*
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+ * These fields are set up this way to maximize source and
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+ * binary compatibility with code written for the old
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+ * ucontext_t definition, which didn't include space for the
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+ * registers.
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+ *
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+ * Different versions of the kernel have stored the registers on
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+ * signal delivery at different offsets from the ucontext struct.
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+ * Programs should thus use the uc_mcontext.uc_regs pointer to
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+ * find where the registers are actually stored. The registers
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+ * will be stored within the ucontext_t struct but not necessarily
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+ * at a fixed address. As a side-effect, this lets us achieve
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+ * 16-byte alignment for the register storage space if the
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+ * Altivec registers are to be saved, without requiring 16-byte
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+ * alignment on the whole ucontext_t.
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+ *
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+ * The uc_mcontext.regs field is included for source compatibility
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+ * with programs written against the older ucontext_t definition,
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+ * and its name should therefore not change. The uc_pad field
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+ * is for binary compatibility with programs compiled against the
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+ * old ucontext_t; it ensures that uc_mcontext.regs and uc_sigmask
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+ * are at the same offset as previously.
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+ */
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+ int uc_pad[7];
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+ union uc_regs_ptr {
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+ struct pt_regs *regs;
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+ mcontext_t *uc_regs;
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+ } uc_mcontext;
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+ sigset_t uc_sigmask;
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+ char uc_reg_space[sizeof(mcontext_t) + 12]; /* last for extensibility */
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+#else /* 64-bit */
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+ sigset_t uc_sigmask;
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+ mcontext_t uc_mcontext; /* last for extensibility */
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+#endif
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} ucontext_t;
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#endif /* sys/ucontext.h */
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