Patch from M. R. Brown <mrbrown@0xd6.org> to get rid of

"depreciated multi-line string literals" warnings

ldso/ldso/sh/boot1_arch.h

@@ -2,21 +2,21 @@
  * will work as expected and cope with whatever platform specific wierdness is
  * needed for this architecture.  */
 
-asm("\
+asm("" \
-	.text
+"	.text\n"			\
-	.globl	_dl_boot
+"	.globl	_dl_boot\n"		\
-_dl_boot:
+"_dl_boot:\n"				\
-        mov	r15, r4
+"	mov	r15, r4\n"		\
-	mov.l   .L_dl_boot2, r0
+"	mov.l   .L_dl_boot2, r0\n"	\
-	bsrf    r0
+"	bsrf    r0\n"			\
-	add	#4, r4
+"	add	#4, r4\n"		\
-.jmp_loc:
+".jmp_loc:\n"				\
-	jmp	@r0
+"	jmp	@r0\n"			\
-	 mov    #0, r4        /* call _start with arg == 0 */
+"	 mov    #0, r4 	!call _start with arg == 0\n" \
-.L_dl_boot2:\n\
+".L_dl_boot2:\n"			\
-	.long   _dl_boot2-.jmp_loc\n\
+"	.long   _dl_boot2-.jmp_loc\n"	\
-	.previous\n\
+"	.previous\n"			\
-");
+);
 
 #define _dl_boot _dl_boot2
 #define LD_BOOT(X)   static void *  __attribute__ ((unused)) _dl_boot (X)

ldso/ldso/sh/dl-startup.h

@@ -2,21 +2,21 @@
  * will work as expected and cope with whatever platform specific wierdness is
  * needed for this architecture.  */
 
-asm("\
+asm("" \
-	.text
+"	.text\n"			\
-	.globl	_dl_boot
+"	.globl	_dl_boot\n"		\
-_dl_boot:
+"_dl_boot:\n"				\
-        mov	r15, r4
+"	mov	r15, r4\n"		\
-	mov.l   .L_dl_boot2, r0
+"	mov.l   .L_dl_boot2, r0\n"	\
-	bsrf    r0
+"	bsrf    r0\n"			\
-	add	#4, r4
+"	add	#4, r4\n"		\
-.jmp_loc:
+".jmp_loc:\n"				\
-	jmp	@r0
+"	jmp	@r0\n"			\
-	 mov    #0, r4        /* call _start with arg == 0 */
+"	 mov    #0, r4 	!call _start with arg == 0\n" \
-.L_dl_boot2:\n\
+".L_dl_boot2:\n"			\
-	.long   _dl_boot2-.jmp_loc\n\
+"	.long   _dl_boot2-.jmp_loc\n"	\
-	.previous\n\
+"	.previous\n"			\
-");
+);
 
 #define _dl_boot _dl_boot2
 #define LD_BOOT(X)   static void *  __attribute__ ((unused)) _dl_boot (X)

ldso/ldso/sh/dl-sysdep.h

@@ -85,52 +85,52 @@ register unsigned int __r0 __asm__ ("r0");
 register unsigned int __r4 __asm__ ("r4") = n;
 register unsigned int __r5 __asm__ ("r5") = base;
 
-	__asm__ ("
+	__asm__ ("" \
-		mov	#0, r0
+		"mov	#0, r0\n\t" \
-		div0u
+		"div0u\n\t" \
-
+		"" \
-		! get one bit from the msb of the numerator into the T
+		"! get one bit from the msb of the numerator into the T\n\t" \
-		! bit and divide it by whats in %2.  Put the answer bit
+		"! bit and divide it by whats in %2.  Put the answer bit\n\t" \
-		! into the T bit so it can come out again at the bottom
+		"! into the T bit so it can come out again at the bottom\n\t" \
-
+		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-
+		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-
+		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
- 
+ 		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4
+		"rotcl	r4\n\t"			\
-		mov  r4, r0
+		"mov  r4, r0\n\t"
-"
+
 		: "=r" (__r0)
 		: "r" (__r4), "r" (__r5)
 		: "r4", "cc");

ldso/ldso/sh/ld_sysdep.h

@@ -85,52 +85,52 @@ register unsigned int __r0 __asm__ ("r0");
 register unsigned int __r4 __asm__ ("r4") = n;
 register unsigned int __r5 __asm__ ("r5") = base;
 
-	__asm__ ("
+	__asm__ ("" \
-		mov	#0, r0
+		"mov	#0, r0\n\t" \
-		div0u
+		"div0u\n\t" \
-
+		"" \
-		! get one bit from the msb of the numerator into the T
+		"! get one bit from the msb of the numerator into the T\n\t" \
-		! bit and divide it by whats in %2.  Put the answer bit
+		"! bit and divide it by whats in %2.  Put the answer bit\n\t" \
-		! into the T bit so it can come out again at the bottom
+		"! into the T bit so it can come out again at the bottom\n\t" \
-
+		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-
+		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-
+		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
- 
+ 		""				\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4 ; div1 r5, r0
+		"rotcl	r4 ; div1 r5, r0\n\t"	\
-		rotcl	r4
+		"rotcl	r4\n\t"			\
-		mov  r4, r0
+		"mov  r4, r0\n\t"
-"
+
 		: "=r" (__r0)
 		: "r" (__r4), "r" (__r5)
 		: "r4", "cc");