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@@ -1,4 +1,4 @@
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-/* FPU control word definitions. PowerPC version.
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+/* 68k FPU control word definitions.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@@ -20,50 +20,84 @@
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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-/* rounding control */
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-#define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
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-#define _FPU_RC_DOWN 0x03
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-#define _FPU_RC_UP 0x02
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-#define _FPU_RC_ZERO 0x01
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+/*
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+ * Motorola floating point control register bits.
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+ *
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+ * 31-16 -> reserved (read as 0, ignored on write)
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+ * 15 -> enable trap for BSUN exception
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+ * 14 -> enable trap for SNAN exception
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+ * 13 -> enable trap for OPERR exception
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+ * 12 -> enable trap for OVFL exception
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+ * 11 -> enable trap for UNFL exception
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+ * 10 -> enable trap for DZ exception
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+ * 9 -> enable trap for INEX2 exception
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+ * 8 -> enable trap for INEX1 exception
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+ * 7-6 -> Precision Control
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+ * 5-4 -> Rounding Control
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+ * 3-0 -> zero (read as 0, write as 0)
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+ *
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+ *
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+ * Precision Control:
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+ * 00 - round to extended precision
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+ * 01 - round to single precision
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+ * 10 - round to double precision
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+ * 11 - undefined
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+ *
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+ * Rounding Control:
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+ * 00 - rounding to nearest (RN)
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+ * 01 - rounding toward zero (RZ)
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+ * 10 - rounding (down)toward minus infinity (RM)
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+ * 11 - rounding (up) toward plus infinity (RP)
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+ *
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+ * The hardware default is 0x0000. I choose 0x5400.
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+ */
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-#define _FPU_MASK_NI 0x04 /* non-ieee mode */
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+#include <features.h>
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/* masking of interrupts */
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-#define _FPU_MASK_ZM 0x10 /* zero divide */
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-#define _FPU_MASK_OM 0x40 /* overflow */
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-#define _FPU_MASK_UM 0x20 /* underflow */
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-#define _FPU_MASK_XM 0x08 /* inexact */
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-#define _FPU_MASK_IM 0x80 /* invalid operation */
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+#define _FPU_MASK_BSUN 0x8000
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+#define _FPU_MASK_SNAN 0x4000
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+#define _FPU_MASK_OPERR 0x2000
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+#define _FPU_MASK_OVFL 0x1000
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+#define _FPU_MASK_UNFL 0x0800
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+#define _FPU_MASK_DZ 0x0400
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+#define _FPU_MASK_INEX1 0x0200
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+#define _FPU_MASK_INEX2 0x0100
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-#define _FPU_RESERVED 0xffffff00 /* These bits are reserved are not changed. */
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+/* precision control */
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+#define _FPU_EXTENDED 0x00 /* RECOMMENDED */
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+#define _FPU_DOUBLE 0x80
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+#define _FPU_SINGLE 0x40 /* DO NOT USE */
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-/* The fdlibm code requires no interrupts for exceptions. */
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-#define _FPU_DEFAULT 0x00000000 /* Default value. */
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+/* rounding control */
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+#define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
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+#define _FPU_RC_ZERO 0x10
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+#define _FPU_RC_DOWN 0x20
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+#define _FPU_RC_UP 0x30
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-/* IEEE: same as above, but (some) exceptions;
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- we leave the 'inexact' exception off.
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- */
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-#define _FPU_IEEE 0x000000f0
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+#define _FPU_RESERVED 0xFFFF000F /* Reserved bits in fpucr */
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+
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+
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+/* Now two recommended fpucr */
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+
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+/* The fdlibm code requires no interrupts for exceptions. Don't
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+ change the rounding mode, it would break long double I/O! */
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+#define _FPU_DEFAULT 0x00000000
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+
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+/* IEEE: same as above, but exceptions. We must make it non-zero so
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+ that __setfpucw works. This bit will be ignored. */
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+#define _FPU_IEEE 0x00000001
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/* Type of the control word. */
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typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
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/* Macros for accessing the hardware control word. */
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-#define _FPU_GETCW(__cw) ( { \
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- union { double d; fpu_control_t cw[2]; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
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- (__cw)=tmp.cw[1]; \
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- tmp.cw[1]; } )
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-#define _FPU_SETCW(__cw) { \
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- union { double d; fpu_control_t cw[2]; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- tmp.cw[0] = 0xFFF80000; /* More-or-less arbitrary; this is a QNaN. */ \
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- tmp.cw[1] = __cw; \
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- __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \
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-}
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+#define _FPU_GETCW(cw) __asm__ ("fmove%.l %!, %0" : "=dm" (cw))
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+#define _FPU_SETCW(cw) __asm__ volatile ("fmove%.l %0, %!" : : "dm" (cw))
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+#if 0
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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+#endif
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-#endif /* _FPU_CONTROL_H */
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+#endif /* _M68K_FPU_CONTROL_H */
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Mike Frysinger