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@@ -0,0 +1,607 @@
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+/* Atomic operations. PowerPC Common version.
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+ Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+ Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, write to the Free
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+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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+ 02111-1307 USA. */
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+
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+#include <bits/wordsize.h>
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+
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+#if __WORDSIZE == 64
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+/* Atomic operations. PowerPC64 version.
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+ Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+ Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, write to the Free
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+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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+ 02111-1307 USA. */
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+
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+/* The 32-bit exchange_bool is different on powerpc64 because the subf
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+ does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
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+ (a load word and zero (high 32) form) load.
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+ In powerpc64 register values are 64-bit by default, including oldval.
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+ The value in old val unknown sign extension, lwarx loads the 32-bit
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+ value as unsigned. So we explicitly clear the high 32 bits in oldval. */
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+# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
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+({ \
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+ unsigned int __tmp, __tmp2; \
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+ __asm __volatile (" clrldi %1,%1,32\n" \
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+ "1: lwarx %0,0,%2\n" \
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+ " subf. %0,%1,%0\n" \
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+ " bne 2f\n" \
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+ " stwcx. %4,0,%2\n" \
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+ " bne- 1b\n" \
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+ "2: " __ARCH_ACQ_INSTR \
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+ : "=&r" (__tmp), "=r" (__tmp2) \
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+ : "b" (mem), "1" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp != 0; \
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+})
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+
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+# define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \
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+({ \
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+ unsigned int __tmp, __tmp2; \
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+ __asm __volatile (__ARCH_REL_INSTR "\n" \
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+ " clrldi %1,%1,32\n" \
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+ "1: lwarx %0,0,%2\n" \
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+ " subf. %0,%1,%0\n" \
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+ " bne 2f\n" \
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+ " stwcx. %4,0,%2\n" \
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+ " bne- 1b\n" \
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+ "2: " \
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+ : "=&r" (__tmp), "=r" (__tmp2) \
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+ : "b" (mem), "1" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp != 0; \
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+})
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+
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+/*
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+ * Only powerpc64 processors support Load doubleword and reserve index (ldarx)
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+ * and Store doubleword conditional indexed (stdcx) instructions. So here
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+ * we define the 64-bit forms.
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+ */
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+# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
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+({ \
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+ unsigned long __tmp; \
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+ __asm __volatile ( \
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+ "1: ldarx %0,0,%1\n" \
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+ " subf. %0,%2,%0\n" \
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+ " bne 2f\n" \
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+ " stdcx. %3,0,%1\n" \
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+ " bne- 1b\n" \
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+ "2: " __ARCH_ACQ_INSTR \
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+ : "=&r" (__tmp) \
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+ : "b" (mem), "r" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp != 0; \
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+})
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+
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+# define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \
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+({ \
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+ unsigned long __tmp; \
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+ __asm __volatile (__ARCH_REL_INSTR "\n" \
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+ "1: ldarx %0,0,%1\n" \
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+ " subf. %0,%2,%0\n" \
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+ " bne 2f\n" \
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+ " stdcx. %3,0,%1\n" \
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+ " bne- 1b\n" \
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+ "2: " \
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+ : "=&r" (__tmp) \
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+ : "b" (mem), "r" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp != 0; \
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+})
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+
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+#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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+ ({ \
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+ __typeof (*(mem)) __tmp; \
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+ __typeof (mem) __memp = (mem); \
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+ __asm __volatile ( \
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+ "1: ldarx %0,0,%1\n" \
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+ " cmpd %0,%2\n" \
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+ " bne 2f\n" \
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+ " stdcx. %3,0,%1\n" \
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+ " bne- 1b\n" \
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+ "2: " __ARCH_ACQ_INSTR \
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+ : "=&r" (__tmp) \
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+ : "b" (__memp), "r" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp; \
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+ })
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+
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+#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
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+ ({ \
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+ __typeof (*(mem)) __tmp; \
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+ __typeof (mem) __memp = (mem); \
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+ __asm __volatile (__ARCH_REL_INSTR "\n" \
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+ "1: ldarx %0,0,%1\n" \
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+ " cmpd %0,%2\n" \
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+ " bne 2f\n" \
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+ " stdcx. %3,0,%1\n" \
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+ " bne- 1b\n" \
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+ "2: " \
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+ : "=&r" (__tmp) \
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+ : "b" (__memp), "r" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp; \
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+ })
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+
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+# define __arch_atomic_exchange_64_acq(mem, value) \
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+ ({ \
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+ __typeof (*mem) __val; \
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+ __asm __volatile (__ARCH_REL_INSTR "\n" \
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+ "1: ldarx %0,0,%2\n" \
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+ " stdcx. %3,0,%2\n" \
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+ " bne- 1b\n" \
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+ " " __ARCH_ACQ_INSTR \
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+ : "=&r" (__val), "=m" (*mem) \
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+ : "b" (mem), "r" (value), "m" (*mem) \
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+ : "cr0", "memory"); \
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+ __val; \
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+ })
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+
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+# define __arch_atomic_exchange_64_rel(mem, value) \
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+ ({ \
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+ __typeof (*mem) __val; \
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+ __asm __volatile (__ARCH_REL_INSTR "\n" \
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+ "1: ldarx %0,0,%2\n" \
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+ " stdcx. %3,0,%2\n" \
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+ " bne- 1b" \
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+ : "=&r" (__val), "=m" (*mem) \
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+ : "b" (mem), "r" (value), "m" (*mem) \
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+ : "cr0", "memory"); \
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+ __val; \
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+ })
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+
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+# define __arch_atomic_exchange_and_add_64(mem, value) \
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+ ({ \
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+ __typeof (*mem) __val, __tmp; \
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+ __asm __volatile ("1: ldarx %0,0,%3\n" \
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+ " add %1,%0,%4\n" \
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+ " stdcx. %1,0,%3\n" \
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+ " bne- 1b" \
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+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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+ : "b" (mem), "r" (value), "m" (*mem) \
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+ : "cr0", "memory"); \
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+ __val; \
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+ })
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+
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+# define __arch_atomic_increment_val_64(mem) \
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+ ({ \
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+ __typeof (*(mem)) __val; \
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+ __asm __volatile ("1: ldarx %0,0,%2\n" \
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+ " addi %0,%0,1\n" \
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+ " stdcx. %0,0,%2\n" \
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+ " bne- 1b" \
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+ : "=&b" (__val), "=m" (*mem) \
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+ : "b" (mem), "m" (*mem) \
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+ : "cr0", "memory"); \
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+ __val; \
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+ })
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+
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+# define __arch_atomic_decrement_val_64(mem) \
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+ ({ \
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+ __typeof (*(mem)) __val; \
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+ __asm __volatile ("1: ldarx %0,0,%2\n" \
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+ " subi %0,%0,1\n" \
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+ " stdcx. %0,0,%2\n" \
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+ " bne- 1b" \
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+ : "=&b" (__val), "=m" (*mem) \
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+ : "b" (mem), "m" (*mem) \
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+ : "cr0", "memory"); \
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+ __val; \
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+ })
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+
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+# define __arch_atomic_decrement_if_positive_64(mem) \
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+ ({ int __val, __tmp; \
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+ __asm __volatile ("1: ldarx %0,0,%3\n" \
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+ " cmpdi 0,%0,0\n" \
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+ " addi %1,%0,-1\n" \
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+ " ble 2f\n" \
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+ " stdcx. %1,0,%3\n" \
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+ " bne- 1b\n" \
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+ "2: " __ARCH_ACQ_INSTR \
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+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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+ : "b" (mem), "m" (*mem) \
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+ : "cr0", "memory"); \
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+ __val; \
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+ })
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+
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+/*
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+ * All powerpc64 processors support the new "light weight" sync (lwsync).
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+ */
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+# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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+/*
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+ * "light weight" sync can also be used for the release barrier.
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+ */
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+# ifndef UP
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+# define __ARCH_REL_INSTR "lwsync"
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+# endif
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+
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+#else
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+/* Atomic operations. PowerPC32 version.
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+ Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+ Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, write to the Free
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+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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+ 02111-1307 USA. */
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+
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+/*
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+ * The 32-bit exchange_bool is different on powerpc64 because the subf
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+ * does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
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+ * (a load word and zero (high 32) form). So powerpc64 has a slightly
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+ * different version in sysdeps/powerpc/powerpc64/bits/atomic.h.
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+ */
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+# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
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+({ \
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+ unsigned int __tmp; \
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+ __asm __volatile ( \
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+ "1: lwarx %0,0,%1\n" \
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+ " subf. %0,%2,%0\n" \
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+ " bne 2f\n" \
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+ " stwcx. %3,0,%1\n" \
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+ " bne- 1b\n" \
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+ "2: " __ARCH_ACQ_INSTR \
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+ : "=&r" (__tmp) \
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+ : "b" (mem), "r" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp != 0; \
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+})
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+
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+# define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \
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+({ \
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+ unsigned int __tmp; \
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+ __asm __volatile (__ARCH_REL_INSTR "\n" \
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+ "1: lwarx %0,0,%1\n" \
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+ " subf. %0,%2,%0\n" \
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+ " bne 2f\n" \
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+ " stwcx. %3,0,%1\n" \
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+ " bne- 1b\n" \
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+ "2: " \
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+ : "=&r" (__tmp) \
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+ : "b" (mem), "r" (oldval), "r" (newval) \
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+ : "cr0", "memory"); \
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+ __tmp != 0; \
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+})
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+
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+/* Powerpc32 processors don't implement the 64-bit (doubleword) forms of
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+ load and reserve (ldarx) and store conditional (stdcx.) instructions.
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+ So for powerpc32 we stub out the 64-bit forms. */
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+# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
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+ (abort (), 0)
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+
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+# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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+ (abort (), (__typeof (*mem)) 0)
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+
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+# define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \
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+ (abort (), 0)
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+
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+# define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
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+ (abort (), (__typeof (*mem)) 0)
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+
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+# define __arch_atomic_exchange_64_acq(mem, value) \
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+ ({ abort (); (*mem) = (value); })
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+
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+# define __arch_atomic_exchange_64_rel(mem, value) \
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+ ({ abort (); (*mem) = (value); })
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+
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+# define __arch_atomic_exchange_and_add_64(mem, value) \
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+ ({ abort (); (*mem) = (value); })
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+
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+# define __arch_atomic_increment_val_64(mem) \
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+ ({ abort (); (*mem)++; })
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+
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+# define __arch_atomic_decrement_val_64(mem) \
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+ ({ abort (); (*mem)--; })
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+
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+# define __arch_atomic_decrement_if_positive_64(mem) \
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+ ({ abort (); (*mem)--; })
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+
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+/*
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+ * Older powerpc32 processors don't support the new "light weight"
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+ * sync (lwsync). So the only safe option is to use normal sync
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+ * for all powerpc32 applications.
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+ */
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+# define atomic_read_barrier() __asm ("sync" ::: "memory")
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+
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+#endif
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+
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+#include <stdint.h>
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+
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+typedef int32_t atomic32_t;
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+typedef uint32_t uatomic32_t;
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+typedef int_fast32_t atomic_fast32_t;
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+typedef uint_fast32_t uatomic_fast32_t;
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+
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+typedef int64_t atomic64_t;
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+typedef uint64_t uatomic64_t;
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+typedef int_fast64_t atomic_fast64_t;
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+typedef uint_fast64_t uatomic_fast64_t;
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+
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+typedef intptr_t atomicptr_t;
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+typedef uintptr_t uatomicptr_t;
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+typedef intmax_t atomic_max_t;
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+typedef uintmax_t uatomic_max_t;
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+
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+/*
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+ * Powerpc does not have byte and halfword forms of load and reserve and
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+ * store conditional. So for powerpc we stub out the 8- and 16-bit forms.
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|
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+ */
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|
|
+#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
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|
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+ (abort (), 0)
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|
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+
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|
|
+#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
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|
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+ (abort (), 0)
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|
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+
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+#define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \
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|
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+ (abort (), 0)
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|
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+
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|
+#define __arch_compare_and_exchange_bool_16_rel(mem, newval, oldval) \
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|
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+ (abort (), 0)
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|
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+
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|
|
+#ifdef UP
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|
|
+# define __ARCH_ACQ_INSTR ""
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|
|
+# define __ARCH_REL_INSTR ""
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|
|
+#else
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|
|
+# define __ARCH_ACQ_INSTR "isync"
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|
|
+# ifndef __ARCH_REL_INSTR
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|
|
+# define __ARCH_REL_INSTR "sync"
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|
|
+# endif
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|
|
+#endif
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|
|
+
|
|
|
+#define atomic_full_barrier() __asm ("sync" ::: "memory")
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|
|
+#define atomic_write_barrier() __asm ("eieio" ::: "memory")
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|
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+
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|
|
+#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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|
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+ ({ \
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+ __typeof (*(mem)) __tmp; \
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|
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+ __typeof (mem) __memp = (mem); \
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|
|
+ __asm __volatile ( \
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|
|
+ "1: lwarx %0,0,%1\n" \
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|
|
+ " cmpw %0,%2\n" \
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|
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+ " bne 2f\n" \
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|
|
+ " stwcx. %3,0,%1\n" \
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|
|
+ " bne- 1b\n" \
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|
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+ "2: " __ARCH_ACQ_INSTR \
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|
|
+ : "=&r" (__tmp) \
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|
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+ : "b" (__memp), "r" (oldval), "r" (newval) \
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|
+ : "cr0", "memory"); \
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|
|
+ __tmp; \
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|
|
+ })
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|
|
+
|
|
|
+#define __arch_compare_and_exchange_val_32_rel(mem, newval, oldval) \
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|
|
+ ({ \
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|
|
+ __typeof (*(mem)) __tmp; \
|
|
|
+ __typeof (mem) __memp = (mem); \
|
|
|
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
|
|
|
+ "1: lwarx %0,0,%1\n" \
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|
|
+ " cmpw %0,%2\n" \
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|
|
+ " bne 2f\n" \
|
|
|
+ " stwcx. %3,0,%1\n" \
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|
|
+ " bne- 1b\n" \
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|
|
+ "2: " \
|
|
|
+ : "=&r" (__tmp) \
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|
|
+ : "b" (__memp), "r" (oldval), "r" (newval) \
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|
|
+ : "cr0", "memory"); \
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|
|
+ __tmp; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define __arch_atomic_exchange_32_acq(mem, value) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*mem) __val; \
|
|
|
+ __asm __volatile ( \
|
|
|
+ "1: lwarx %0,0,%2\n" \
|
|
|
+ " stwcx. %3,0,%2\n" \
|
|
|
+ " bne- 1b\n" \
|
|
|
+ " " __ARCH_ACQ_INSTR \
|
|
|
+ : "=&r" (__val), "=m" (*mem) \
|
|
|
+ : "b" (mem), "r" (value), "m" (*mem) \
|
|
|
+ : "cr0", "memory"); \
|
|
|
+ __val; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define __arch_atomic_exchange_32_rel(mem, value) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*mem) __val; \
|
|
|
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
|
|
|
+ "1: lwarx %0,0,%2\n" \
|
|
|
+ " stwcx. %3,0,%2\n" \
|
|
|
+ " bne- 1b" \
|
|
|
+ : "=&r" (__val), "=m" (*mem) \
|
|
|
+ : "b" (mem), "r" (value), "m" (*mem) \
|
|
|
+ : "cr0", "memory"); \
|
|
|
+ __val; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define __arch_atomic_exchange_and_add_32(mem, value) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*mem) __val, __tmp; \
|
|
|
+ __asm __volatile ("1: lwarx %0,0,%3\n" \
|
|
|
+ " add %1,%0,%4\n" \
|
|
|
+ " stwcx. %1,0,%3\n" \
|
|
|
+ " bne- 1b" \
|
|
|
+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
|
|
|
+ : "b" (mem), "r" (value), "m" (*mem) \
|
|
|
+ : "cr0", "memory"); \
|
|
|
+ __val; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define __arch_atomic_increment_val_32(mem) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __val; \
|
|
|
+ __asm __volatile ("1: lwarx %0,0,%2\n" \
|
|
|
+ " addi %0,%0,1\n" \
|
|
|
+ " stwcx. %0,0,%2\n" \
|
|
|
+ " bne- 1b" \
|
|
|
+ : "=&b" (__val), "=m" (*mem) \
|
|
|
+ : "b" (mem), "m" (*mem) \
|
|
|
+ : "cr0", "memory"); \
|
|
|
+ __val; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define __arch_atomic_decrement_val_32(mem) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __val; \
|
|
|
+ __asm __volatile ("1: lwarx %0,0,%2\n" \
|
|
|
+ " subi %0,%0,1\n" \
|
|
|
+ " stwcx. %0,0,%2\n" \
|
|
|
+ " bne- 1b" \
|
|
|
+ : "=&b" (__val), "=m" (*mem) \
|
|
|
+ : "b" (mem), "m" (*mem) \
|
|
|
+ : "cr0", "memory"); \
|
|
|
+ __val; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define __arch_atomic_decrement_if_positive_32(mem) \
|
|
|
+ ({ int __val, __tmp; \
|
|
|
+ __asm __volatile ("1: lwarx %0,0,%3\n" \
|
|
|
+ " cmpwi 0,%0,0\n" \
|
|
|
+ " addi %1,%0,-1\n" \
|
|
|
+ " ble 2f\n" \
|
|
|
+ " stwcx. %1,0,%3\n" \
|
|
|
+ " bne- 1b\n" \
|
|
|
+ "2: " __ARCH_ACQ_INSTR \
|
|
|
+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
|
|
|
+ : "b" (mem), "m" (*mem) \
|
|
|
+ : "cr0", "memory"); \
|
|
|
+ __val; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*mem) == 4) \
|
|
|
+ __result = __arch_compare_and_exchange_val_32_acq(mem, newval, oldval); \
|
|
|
+ else if (sizeof (*mem) == 8) \
|
|
|
+ __result = __arch_compare_and_exchange_val_64_acq(mem, newval, oldval); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*mem) == 4) \
|
|
|
+ __result = __arch_compare_and_exchange_val_32_rel(mem, newval, oldval); \
|
|
|
+ else if (sizeof (*mem) == 8) \
|
|
|
+ __result = __arch_compare_and_exchange_val_64_rel(mem, newval, oldval); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_exchange_acq(mem, value) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*mem) == 4) \
|
|
|
+ __result = __arch_atomic_exchange_32_acq (mem, value); \
|
|
|
+ else if (sizeof (*mem) == 8) \
|
|
|
+ __result = __arch_atomic_exchange_64_acq (mem, value); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_exchange_rel(mem, value) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*mem) == 4) \
|
|
|
+ __result = __arch_atomic_exchange_32_rel (mem, value); \
|
|
|
+ else if (sizeof (*mem) == 8) \
|
|
|
+ __result = __arch_atomic_exchange_64_rel (mem, value); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_exchange_and_add(mem, value) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*mem) == 4) \
|
|
|
+ __result = __arch_atomic_exchange_and_add_32 (mem, value); \
|
|
|
+ else if (sizeof (*mem) == 8) \
|
|
|
+ __result = __arch_atomic_exchange_and_add_64 (mem, value); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_increment_val(mem) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*(mem)) == 4) \
|
|
|
+ __result = __arch_atomic_increment_val_32 (mem); \
|
|
|
+ else if (sizeof (*(mem)) == 8) \
|
|
|
+ __result = __arch_atomic_increment_val_64 (mem); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; })
|
|
|
+
|
|
|
+#define atomic_decrement_val(mem) \
|
|
|
+ ({ \
|
|
|
+ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*(mem)) == 4) \
|
|
|
+ __result = __arch_atomic_decrement_val_32 (mem); \
|
|
|
+ else if (sizeof (*(mem)) == 8) \
|
|
|
+ __result = __arch_atomic_decrement_val_64 (mem); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
|
|
+
|
|
|
+#define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; })
|
|
|
+
|
|
|
+
|
|
|
+/* Decrement *MEM if it is > 0, and return the old value. */
|
|
|
+#define atomic_decrement_if_positive(mem) \
|
|
|
+ ({ __typeof (*(mem)) __result; \
|
|
|
+ if (sizeof (*mem) == 4) \
|
|
|
+ __result = __arch_atomic_decrement_if_positive_32 (mem); \
|
|
|
+ else if (sizeof (*mem) == 8) \
|
|
|
+ __result = __arch_atomic_decrement_if_positive_64 (mem); \
|
|
|
+ else \
|
|
|
+ abort (); \
|
|
|
+ __result; \
|
|
|
+ })
|
Joakim Tjernlund