Add support for Thumb-only processors.

	* ldso/ldso/arm/aeabi_read_tp.S: Add Thumb version.
	* ldso/ldso/arm/dl-startup.h: Do not force ARM encoding, adjust
	for Thumb.
	* ldso/ldso/arm/resolve.S: Force Thumb encoding on Thumb-only
	processors.
	* libc/sysdeps/linux/arm/crt1.S: Do not force ARM encoding, adjust
	for Thumb.

Signed-off-by: Mickaël Guêné <mickael.guene@st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>

ldso/ldso/arm/aeabi_read_tp.S

@@ -53,9 +53,23 @@
 #else
 	.hidden __aeabi_read_tp
 #endif
+#if !defined(__ARM_ARCH_ISA_ARM)
+	.thumb_func
+	.thumb
+	.syntax unified
+	ENTRY (__aeabi_read_tp)
+	push	{r7}
+	mov	r7, #0x0f0000
+	orr	r7, r7, #6
+	svc	#0
+	pop	{r7}
+	bx	lr
+#else
+	.arm
 ENTRY (__aeabi_read_tp)
 	mov	r0, #0xffff0fff
 	sub	pc, r0, #31
+#endif
 END (__aeabi_read_tp)
 
 #endif /* __UCLIBC_HAS_THREADS_NATIVE__ */

ldso/ldso/arm/dl-startup.h

@@ -11,10 +11,13 @@
 #if defined(__FDPIC__)
 #if !defined(__thumb__) || defined(__thumb2__)
 __asm__(
-	"	.arm\n"
 	"	.text\n"
 	"	.globl  _start\n"
 	"	.type   _start,%function\n"
+#if defined(__thumb2__)
+	"	.thumb_func\n"
+#endif
+	"	.align 2\n"
 	"_start:\n"
 	/* We compute the parameters for __self_reloc:
 	   - r0 is a pointer to the loadmap (either from r8 or r7 if rtld is
@@ -25,12 +28,17 @@ __asm__(
 	   __self_reloc will fix indirect addresses in .rofixup
 	   section and will return the relocated GOT value.
 	*/
+#if defined(__thumb2__)
+	"	sub	r4, pc, #4\n"
+#else
 	"	sub	r4, pc, #8\n"
+#endif
 	"	ldr	r1, .L__ROFIXUP_LIST__\n"
 	"	add	r1, r1, r4\n"
 	"	ldr	r2, .L__ROFIXUP_END__\n"
 	"	add	r2, r2, r4\n"
 	"	movs	r0, r8\n"
+	"	it	eq\n"
 	"	moveq	r0, r7\n"
 	"	push	{r7, r8, r9, r10}\n"
 	"	bl	__self_reloc;\n"

ldso/ldso/arm/resolve.S

@@ -101,7 +101,15 @@
  .text
  .align 4      @ 16 byte boundary and there are 32 bytes below (arm case)
 #if 1 /*(!defined(__thumb__) || defined __THUMB_INTERWORK__) || defined(__thumb2__)*/
- .arm
+	/* On Thumb-only processors, force thumb encoding. These
+	processors support Thumb-2, so the same source code can be
+	used as in ARM mode. */
+#if !defined(__ARM_ARCH_ISA_ARM)
+	.thumb
+	.thumb_func
+#else
+	.arm
+#endif
  .hidden _dl_linux_resolve
  .globl _dl_linux_resolve
  .type _dl_linux_resolve,%function

libc/sysdeps/linux/arm/crt1.S

@@ -97,12 +97,17 @@ ARM register quick reference:
 
 #if defined(__FDPIC__)
 .text
-	.arm
 	.globl	_start
+	.type	_start,%function
 
+	.align	2
 _start:
 	/* Start by self relocation.  */
+#if defined(__thumb2__)
+	sub r4, pc, #4
+#else
 	sub r4, pc, #8
+#endif
 	ldr r1, .L__ROFIXUP_LIST__
 	add r1, r1, r4
 	ldr r2, .L__ROFIXUP_END__
@@ -129,6 +134,7 @@ _start:
 	ldr r4, [r9, r4]
 	str r4, [sp, #0]		/* sp + 0 GOT fini  */
 	movs r4, r8			/* Test if static binary (r8 is 0 as there is no interpreter).  */
+	ite ne
 	movne r4, r10
 	moveq r4, #0
 	str r4, [sp, #4]		/* sp + 4 got rtld_fini  */