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@@ -259,6 +259,7 @@ typedef struct
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#define EM_PJ 91 /* picoJava */
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#define EM_PJ 91 /* picoJava */
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#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
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#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
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#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
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#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
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+#define EM_ARCOMPACT 93 /* ARCompact ISA based Cores: ARC 700 */
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#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
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#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
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#define EM_IP2K 101 /* Ubicom IP2022 micro controller */
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#define EM_IP2K 101 /* Ubicom IP2022 micro controller */
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#define EM_CR 103 /* National Semiconductor CompactRISC */
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#define EM_CR 103 /* National Semiconductor CompactRISC */
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@@ -3189,6 +3190,64 @@ typedef Elf32_Addr Elf32_Conflict;
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#define R_METAG_TLS_DTPMOD 57
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#define R_METAG_TLS_DTPMOD 57
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#define R_METAG_TLS_DTPOFF 58
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#define R_METAG_TLS_DTPOFF 58
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+/* ARCompact specific relocs */
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+#define R_ARC_NONE 0x0
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+#define R_ARC_8 0x1
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+#define R_ARC_16 0x2
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+#define R_ARC_24 0x3
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+#define R_ARC_32 0x4
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+#define R_ARC_B26 0x5
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+#define R_ARC_B22_PCREL 0x6
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+#define R_ARC_H30 0x7
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+#define R_ARC_N8 0x8
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+#define R_ARC_N16 0x9
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+#define R_ARC_N24 0xA
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+#define R_ARC_N32 0xB
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+#define R_ARC_SDA 0xC
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+#define R_ARC_SECTOFF 0xD
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+#define R_ARC_S21H_PCREL 0xE
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+#define R_ARC_S21W_PCREL 0xF
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+#define R_ARC_S25H_PCREL 0x10
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+#define R_ARC_S25W_PCREL 0x11
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+#define R_ARC_SDA32 0x12
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+#define R_ARC_SDA_LDST 0x13
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+#define R_ARC_SDA_LDST1 0x14
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+#define R_ARC_SDA_LDST2 0x15
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+#define R_ARC_SDA16_LD 0x16
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+#define R_ARC_SDA16_LD1 0x17
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+#define R_ARC_SDA16_LD2 0x18
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+#define R_ARC_S13_PCREL 0x19
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+#define R_ARC_W 0x1A
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+#define R_ARC_32_ME 0x1B
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+#define R_ARC_N32_ME 0x1C
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+#define R_ARC_SECTOFF_ME 0x1D
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+#define R_ARC_SDA32_ME 0x1E
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+#define R_ARC_W_ME 0x1F
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+#define R_ARC_H30_ME 0x20
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+#define R_ARC_SECTOFF_U8 0x21
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+#define R_ARC_SECTOFF_S9 0x22
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+#define R_AC_SECTOFF_U8 0x23
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+#define R_AC_SECTOFF_U8_1 0x24
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+#define R_AC_SECTOFF_U8_2 0x25
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+#define R_AC_SECTOFF_S9 0x26
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+#define R_AC_SECTOFF_S9_1 0x27
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+#define R_AC_SECTOFF_S9_2 0x28
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+#define R_ARC_SECTOFF_ME_1 0x29
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+#define R_ARC_SECTOFF_ME_2 0x2A
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+#define R_ARC_SECTOFF_1 0x2B
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+#define R_ARC_SECTOFF_2 0x2C
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+#define R_ARC_PC32 0x32
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+#define R_ARC_GOTPC32 0x33
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+#define R_ARC_PLT32 0x34
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+#define R_ARC_COPY 0x35
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+#define R_ARC_GLOB_DAT 0x36
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+#define R_ARC_JMP_SLOT 0x37
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+#define R_ARC_RELATIVE 0x38
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+#define R_ARC_GOTOFF 0x39
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+#define R_ARC_GOTPC 0x3A
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+#define R_ARC_GOT32 0x3B
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+#define R_ARC_NUM 0x3C
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+
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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