arc: add support for ARCv3 32-bit processors

New ARCv3 ISA includes both 64-bit and 32-bit CPU family.
This patch adds support for 32-bit ARCv3 HS5x processors.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>

include/elf.h

@@ -273,6 +273,7 @@ typedef struct
 #define EM_ARCV2	195		/* Synopsys ARCv2 Cores */
 #define EM_RISCV        243     	/* RISC-V */
 #define EM_CSKY		252		/* C-SKY Cores */
+#define EM_ARCV3_32	255		/* Synopsys ARCv3 32-bit Cores */
 #define EM_KVX		256		/* Kalray VLIW core of the MPPA processor family */
 
 /* NEXT FREE NUMBER: Increment this after adding your official arch number */

ldso/ldso/arc/dl-sysdep.h

@@ -75,6 +75,9 @@ do {									\
 #elif defined(__HS__)
 #define MAGIC1 EM_ARCV2
 #define ELF_TARGET "ARCv2"	/* For error messages */
+#elif defined(__ARC64_ARCH32__)
+#define MAGIC1 EM_ARCV3_32
+#define ELF_TARGET "ARCv3_32"	/* For error messages */
 #endif
 
 #undef  MAGIC2

libc/sysdeps/linux/arc/asm.h

@@ -7,6 +7,29 @@
 #ifndef _ARC_ASM_H
 #define _ARC_ASM_H
 
+#if defined (__ARC64_ARCH32__)
+
+.macro PUSHR reg
+	push	\reg
+.endm
+
+.macro PUSHR_S reg
+	push	\reg
+.endm
+
+.macro POPR reg
+	pop	\reg
+.endm
+
+.macro POPR_S reg
+	pop	\reg
+.endm
+
+#elif defined (__ARC64_ARCH64__)
+
+# error ARCv3 64-bit is not supported by uClibc-ng
+
+#else /* ARCHS || ARC700 */
 
 .macro PUSHR reg
 	push	\reg
@@ -24,5 +47,6 @@
 	pop_s	\reg
 .endm
 
+#endif
 
 #endif /* _ARC_ASM_H  */

libc/sysdeps/linux/arc/bits/syscalls.h

@@ -100,7 +100,7 @@ extern long __syscall_error (int);
 
 #ifdef __A7__
 #define ARC_TRAP_INSN	"trap0		\n\t"
-#elif defined(__HS__)
+#else
 #define ARC_TRAP_INSN	"trap_s 0	\n\t"
 #endif
 
@@ -182,7 +182,7 @@ extern long __syscall_error (int);
 
 #ifdef __A7__
 #define ARC_TRAP_INSN	trap0
-#elif defined(__HS__)
+#else
 #define ARC_TRAP_INSN	trap_s 0
 #endif
 

libc/sysdeps/linux/arc/crt1.S

@@ -40,7 +40,9 @@ __start:
 	ld_s	r1, [sp]	; argc
 
 	mov_s	r5, r0		; rltd_fini
-	add_s	r2, sp, 4	; argv
+	/* Use the universal 32-bit add instruction as 16-bit add_s was excluded from
+	   ARCv3 ISA */
+	add	r2, sp, 4	; argv
 #ifdef L_Scrt1
 	ld	r0, [pcl, @main@gotpc]
 	ld	r3, [pcl, @_init@gotpc]

utils/ldd.c

@@ -34,6 +34,11 @@
 #define ELFCLASSM      ELFCLASS32
 #endif
 
+#if defined(__ARC64_ARCH32__)
+#define MATCH_MACHINE(x) (x == EM_ARCV3_32)
+#define ELFCLASSM      ELFCLASS32
+#endif
+
 #if defined(__arm__) || defined(__thumb__)
 #define MATCH_MACHINE(x) (x == EM_ARM)
 #define ELFCLASSM	ELFCLASS32