longlong.h 60 KB

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  1. /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
  2. Copyright (C) 1991-2017 Free Software Foundation, Inc.
  3. This file is part of the GNU C Library.
  4. The GNU C Library is free software; you can redistribute it and/or
  5. modify it under the terms of the GNU Lesser General Public
  6. License as published by the Free Software Foundation; either
  7. version 2.1 of the License, or (at your option) any later version.
  8. In addition to the permissions in the GNU Lesser General Public
  9. License, the Free Software Foundation gives you unlimited
  10. permission to link the compiled version of this file into
  11. combinations with other programs, and to distribute those
  12. combinations without any restriction coming from the use of this
  13. file. (The Lesser General Public License restrictions do apply in
  14. other respects; for example, they cover modification of the file,
  15. and distribution when not linked into a combine executable.)
  16. The GNU C Library is distributed in the hope that it will be useful,
  17. but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. Lesser General Public License for more details.
  20. You should have received a copy of the GNU Lesser General Public
  21. License along with the GNU C Library; if not, see
  22. <http://www.gnu.org/licenses/>. */
  23. /* You have to define the following before including this file:
  24. UWtype -- An unsigned type, default type for operations (typically a "word")
  25. UHWtype -- An unsigned type, at least half the size of UWtype.
  26. UDWtype -- An unsigned type, at least twice as large a UWtype
  27. W_TYPE_SIZE -- size in bits of UWtype
  28. UQItype -- Unsigned 8 bit type.
  29. SItype, USItype -- Signed and unsigned 32 bit types.
  30. DItype, UDItype -- Signed and unsigned 64 bit types.
  31. On a 32 bit machine UWtype should typically be USItype;
  32. on a 64 bit machine, UWtype should typically be UDItype. */
  33. #define __BITS4 (W_TYPE_SIZE / 4)
  34. #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
  35. #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
  36. #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
  37. #ifndef W_TYPE_SIZE
  38. #define W_TYPE_SIZE 32
  39. #define UWtype USItype
  40. #define UHWtype USItype
  41. #define UDWtype UDItype
  42. #endif
  43. /* Used in glibc only. */
  44. #ifndef attribute_hidden
  45. #define attribute_hidden
  46. #endif
  47. extern const UQItype __clz_tab[256] attribute_hidden;
  48. /* Define auxiliary asm macros.
  49. 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
  50. UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
  51. word product in HIGH_PROD and LOW_PROD.
  52. 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
  53. UDWtype product. This is just a variant of umul_ppmm.
  54. 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
  55. denominator) divides a UDWtype, composed by the UWtype integers
  56. HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
  57. in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
  58. than DENOMINATOR for correct operation. If, in addition, the most
  59. significant bit of DENOMINATOR must be 1, then the pre-processor symbol
  60. UDIV_NEEDS_NORMALIZATION is defined to 1.
  61. 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
  62. denominator). Like udiv_qrnnd but the numbers are signed. The quotient
  63. is rounded towards 0.
  64. 5) count_leading_zeros(count, x) counts the number of zero-bits from the
  65. msb to the first nonzero bit in the UWtype X. This is the number of
  66. steps X needs to be shifted left to set the msb. Undefined for X == 0,
  67. unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
  68. 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
  69. from the least significant end.
  70. 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
  71. high_addend_2, low_addend_2) adds two UWtype integers, composed by
  72. HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
  73. respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
  74. (i.e. carry out) is not stored anywhere, and is lost.
  75. 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
  76. high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
  77. composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
  78. LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
  79. and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
  80. and is lost.
  81. If any of these macros are left undefined for a particular CPU,
  82. C macros are used. */
  83. /* The CPUs come in alphabetical order below.
  84. Please add support for more CPUs here, or improve the current support
  85. for the CPUs below!
  86. (E.g. WE32100, IBM360.) */
  87. #if defined (__GNUC__) && !defined (NO_ASM)
  88. /* We sometimes need to clobber "cc" with gcc2, but that would not be
  89. understood by gcc1. Use cpp to avoid major code duplication. */
  90. #if __GNUC__ < 2
  91. #define __CLOBBER_CC
  92. #define __AND_CLOBBER_CC
  93. #else /* __GNUC__ >= 2 */
  94. #define __CLOBBER_CC : "cc"
  95. #define __AND_CLOBBER_CC , "cc"
  96. #endif /* __GNUC__ < 2 */
  97. #if defined (__aarch64__)
  98. #if W_TYPE_SIZE == 32
  99. #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
  100. #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
  101. #define COUNT_LEADING_ZEROS_0 32
  102. #endif /* W_TYPE_SIZE == 32 */
  103. #if W_TYPE_SIZE == 64
  104. #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clzll (X))
  105. #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctzll (X))
  106. #define COUNT_LEADING_ZEROS_0 64
  107. #endif /* W_TYPE_SIZE == 64 */
  108. #endif /* __aarch64__ */
  109. #if defined (__alpha) && W_TYPE_SIZE == 64
  110. /* There is a bug in g++ before version 5 that
  111. errors on __builtin_alpha_umulh. */
  112. #if !defined(__cplusplus) || __GNUC__ >= 5
  113. #define umul_ppmm(ph, pl, m0, m1) \
  114. do { \
  115. UDItype __m0 = (m0), __m1 = (m1); \
  116. (ph) = __builtin_alpha_umulh (__m0, __m1); \
  117. (pl) = __m0 * __m1; \
  118. } while (0)
  119. #define UMUL_TIME 46
  120. #endif /* !c++ */
  121. #ifndef LONGLONG_STANDALONE
  122. #define udiv_qrnnd(q, r, n1, n0, d) \
  123. do { UDItype __r; \
  124. (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
  125. (r) = __r; \
  126. } while (0)
  127. extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  128. #define UDIV_TIME 220
  129. #endif /* LONGLONG_STANDALONE */
  130. #ifdef __alpha_cix__
  131. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
  132. #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
  133. #define COUNT_LEADING_ZEROS_0 64
  134. #else
  135. #define count_leading_zeros(COUNT,X) \
  136. do { \
  137. UDItype __xr = (X), __t, __a; \
  138. __t = __builtin_alpha_cmpbge (0, __xr); \
  139. __a = __clz_tab[__t ^ 0xff] - 1; \
  140. __t = __builtin_alpha_extbl (__xr, __a); \
  141. (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
  142. } while (0)
  143. #define count_trailing_zeros(COUNT,X) \
  144. do { \
  145. UDItype __xr = (X), __t, __a; \
  146. __t = __builtin_alpha_cmpbge (0, __xr); \
  147. __t = ~__t & -~__t; \
  148. __a = ((__t & 0xCC) != 0) * 2; \
  149. __a += ((__t & 0xF0) != 0) * 4; \
  150. __a += ((__t & 0xAA) != 0); \
  151. __t = __builtin_alpha_extbl (__xr, __a); \
  152. __a <<= 3; \
  153. __t &= -__t; \
  154. __a += ((__t & 0xCC) != 0) * 2; \
  155. __a += ((__t & 0xF0) != 0) * 4; \
  156. __a += ((__t & 0xAA) != 0); \
  157. (COUNT) = __a; \
  158. } while (0)
  159. #endif /* __alpha_cix__ */
  160. #endif /* __alpha */
  161. #if defined (__arc__) && W_TYPE_SIZE == 32
  162. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  163. __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
  164. : "=r" ((USItype) (sh)), \
  165. "=&r" ((USItype) (sl)) \
  166. : "%r" ((USItype) (ah)), \
  167. "rIJ" ((USItype) (bh)), \
  168. "%r" ((USItype) (al)), \
  169. "rIJ" ((USItype) (bl)))
  170. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  171. __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
  172. : "=r" ((USItype) (sh)), \
  173. "=&r" ((USItype) (sl)) \
  174. : "r" ((USItype) (ah)), \
  175. "rIJ" ((USItype) (bh)), \
  176. "r" ((USItype) (al)), \
  177. "rIJ" ((USItype) (bl)))
  178. #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
  179. #ifdef __ARC_NORM__
  180. #define count_leading_zeros(count, x) \
  181. do \
  182. { \
  183. SItype c_; \
  184. \
  185. __asm__ ("norm.f\t%0,%1\n\tmov.mi\t%0,-1" : "=r" (c_) : "r" (x) : "cc");\
  186. (count) = c_ + 1; \
  187. } \
  188. while (0)
  189. #define COUNT_LEADING_ZEROS_0 32
  190. #endif
  191. #endif
  192. #if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) \
  193. && W_TYPE_SIZE == 32
  194. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  195. __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
  196. : "=r" ((USItype) (sh)), \
  197. "=&r" ((USItype) (sl)) \
  198. : "%r" ((USItype) (ah)), \
  199. "rI" ((USItype) (bh)), \
  200. "%r" ((USItype) (al)), \
  201. "rI" ((USItype) (bl)) __CLOBBER_CC)
  202. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  203. __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
  204. : "=r" ((USItype) (sh)), \
  205. "=&r" ((USItype) (sl)) \
  206. : "r" ((USItype) (ah)), \
  207. "rI" ((USItype) (bh)), \
  208. "r" ((USItype) (al)), \
  209. "rI" ((USItype) (bl)) __CLOBBER_CC)
  210. # if defined(__ARM_ARCH_2__) || defined(__ARM_ARCH_2A__) \
  211. || defined(__ARM_ARCH_3__)
  212. # define umul_ppmm(xh, xl, a, b) \
  213. do { \
  214. register USItype __t0, __t1, __t2; \
  215. __asm__ ("%@ Inlined umul_ppmm\n" \
  216. " mov %2, %5, lsr #16\n" \
  217. " mov %0, %6, lsr #16\n" \
  218. " bic %3, %5, %2, lsl #16\n" \
  219. " bic %4, %6, %0, lsl #16\n" \
  220. " mul %1, %3, %4\n" \
  221. " mul %4, %2, %4\n" \
  222. " mul %3, %0, %3\n" \
  223. " mul %0, %2, %0\n" \
  224. " adds %3, %4, %3\n" \
  225. " addcs %0, %0, #65536\n" \
  226. " adds %1, %1, %3, lsl #16\n" \
  227. " adc %0, %0, %3, lsr #16" \
  228. : "=&r" ((USItype) (xh)), \
  229. "=r" ((USItype) (xl)), \
  230. "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
  231. : "r" ((USItype) (a)), \
  232. "r" ((USItype) (b)) __CLOBBER_CC ); \
  233. } while (0)
  234. # define UMUL_TIME 20
  235. # else
  236. # define umul_ppmm(xh, xl, a, b) \
  237. do { \
  238. /* Generate umull, under compiler control. */ \
  239. register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b); \
  240. (xl) = (USItype)__t0; \
  241. (xh) = (USItype)(__t0 >> 32); \
  242. } while (0)
  243. # define UMUL_TIME 3
  244. # endif
  245. # define UDIV_TIME 100
  246. #endif /* __arm__ */
  247. #if defined(__arm__)
  248. /* Let gcc decide how best to implement count_leading_zeros. */
  249. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
  250. #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
  251. #define COUNT_LEADING_ZEROS_0 32
  252. #endif
  253. #if defined (__AVR__)
  254. #if W_TYPE_SIZE == 16
  255. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
  256. #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
  257. #define COUNT_LEADING_ZEROS_0 16
  258. #endif /* W_TYPE_SIZE == 16 */
  259. #if W_TYPE_SIZE == 32
  260. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
  261. #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
  262. #define COUNT_LEADING_ZEROS_0 32
  263. #endif /* W_TYPE_SIZE == 32 */
  264. #if W_TYPE_SIZE == 64
  265. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzll (X))
  266. #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzll (X))
  267. #define COUNT_LEADING_ZEROS_0 64
  268. #endif /* W_TYPE_SIZE == 64 */
  269. #endif /* defined (__AVR__) */
  270. #if defined (__CRIS__)
  271. #if __CRIS_arch_version >= 3
  272. #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
  273. #define COUNT_LEADING_ZEROS_0 32
  274. #endif /* __CRIS_arch_version >= 3 */
  275. #if __CRIS_arch_version >= 8
  276. #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
  277. #endif /* __CRIS_arch_version >= 8 */
  278. #if __CRIS_arch_version >= 10
  279. #define __umulsidi3(u,v) ((UDItype)(USItype) (u) * (UDItype)(USItype) (v))
  280. #else
  281. #define __umulsidi3 __umulsidi3
  282. extern UDItype __umulsidi3 (USItype, USItype);
  283. #endif /* __CRIS_arch_version >= 10 */
  284. #define umul_ppmm(w1, w0, u, v) \
  285. do { \
  286. UDItype __x = __umulsidi3 (u, v); \
  287. (w0) = (USItype) (__x); \
  288. (w1) = (USItype) (__x >> 32); \
  289. } while (0)
  290. /* FIXME: defining add_ssaaaa and sub_ddmmss should be advantageous for
  291. DFmode ("double" intrinsics, avoiding two of the three insns handling
  292. carry), but defining them as open-code C composing and doing the
  293. operation in DImode (UDImode) shows that the DImode needs work:
  294. register pressure from requiring neighboring registers and the
  295. traffic to and from them come to dominate, in the 4.7 series. */
  296. #endif /* defined (__CRIS__) */
  297. #if defined (__hppa) && W_TYPE_SIZE == 32
  298. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  299. __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
  300. : "=r" ((USItype) (sh)), \
  301. "=&r" ((USItype) (sl)) \
  302. : "%rM" ((USItype) (ah)), \
  303. "rM" ((USItype) (bh)), \
  304. "%rM" ((USItype) (al)), \
  305. "rM" ((USItype) (bl)))
  306. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  307. __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
  308. : "=r" ((USItype) (sh)), \
  309. "=&r" ((USItype) (sl)) \
  310. : "rM" ((USItype) (ah)), \
  311. "rM" ((USItype) (bh)), \
  312. "rM" ((USItype) (al)), \
  313. "rM" ((USItype) (bl)))
  314. #if defined (_PA_RISC1_1)
  315. #define umul_ppmm(w1, w0, u, v) \
  316. do { \
  317. union \
  318. { \
  319. UDItype __f; \
  320. struct {USItype __w1, __w0;} __w1w0; \
  321. } __t; \
  322. __asm__ ("xmpyu %1,%2,%0" \
  323. : "=x" (__t.__f) \
  324. : "x" ((USItype) (u)), \
  325. "x" ((USItype) (v))); \
  326. (w1) = __t.__w1w0.__w1; \
  327. (w0) = __t.__w1w0.__w0; \
  328. } while (0)
  329. #define UMUL_TIME 8
  330. #else
  331. #define UMUL_TIME 30
  332. #endif
  333. #define UDIV_TIME 40
  334. #define count_leading_zeros(count, x) \
  335. do { \
  336. USItype __tmp; \
  337. __asm__ ( \
  338. "ldi 1,%0\n" \
  339. " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
  340. " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
  341. " ldo 16(%0),%0 ; Yes. Perform add.\n" \
  342. " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
  343. " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
  344. " ldo 8(%0),%0 ; Yes. Perform add.\n" \
  345. " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
  346. " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
  347. " ldo 4(%0),%0 ; Yes. Perform add.\n" \
  348. " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
  349. " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
  350. " ldo 2(%0),%0 ; Yes. Perform add.\n" \
  351. " extru %1,30,1,%1 ; Extract bit 1.\n" \
  352. " sub %0,%1,%0 ; Subtract it.\n" \
  353. : "=r" (count), "=r" (__tmp) : "1" (x)); \
  354. } while (0)
  355. #endif
  356. #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
  357. #if !defined (__zarch__)
  358. #define smul_ppmm(xh, xl, m0, m1) \
  359. do { \
  360. union {DItype __ll; \
  361. struct {USItype __h, __l;} __i; \
  362. } __x; \
  363. __asm__ ("lr %N0,%1\n\tmr %0,%2" \
  364. : "=&r" (__x.__ll) \
  365. : "r" (m0), "r" (m1)); \
  366. (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
  367. } while (0)
  368. #define sdiv_qrnnd(q, r, n1, n0, d) \
  369. do { \
  370. union {DItype __ll; \
  371. struct {USItype __h, __l;} __i; \
  372. } __x; \
  373. __x.__i.__h = n1; __x.__i.__l = n0; \
  374. __asm__ ("dr %0,%2" \
  375. : "=r" (__x.__ll) \
  376. : "0" (__x.__ll), "r" (d)); \
  377. (q) = __x.__i.__l; (r) = __x.__i.__h; \
  378. } while (0)
  379. #else
  380. #define smul_ppmm(xh, xl, m0, m1) \
  381. do { \
  382. register SItype __r0 __asm__ ("0"); \
  383. register SItype __r1 __asm__ ("1") = (m0); \
  384. \
  385. __asm__ ("mr\t%%r0,%3" \
  386. : "=r" (__r0), "=r" (__r1) \
  387. : "r" (__r1), "r" (m1)); \
  388. (xh) = __r0; (xl) = __r1; \
  389. } while (0)
  390. #define sdiv_qrnnd(q, r, n1, n0, d) \
  391. do { \
  392. register SItype __r0 __asm__ ("0") = (n1); \
  393. register SItype __r1 __asm__ ("1") = (n0); \
  394. \
  395. __asm__ ("dr\t%%r0,%4" \
  396. : "=r" (__r0), "=r" (__r1) \
  397. : "r" (__r0), "r" (__r1), "r" (d)); \
  398. (q) = __r1; (r) = __r0; \
  399. } while (0)
  400. #endif /* __zarch__ */
  401. #endif
  402. #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
  403. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  404. __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
  405. : "=r" ((USItype) (sh)), \
  406. "=&r" ((USItype) (sl)) \
  407. : "%0" ((USItype) (ah)), \
  408. "g" ((USItype) (bh)), \
  409. "%1" ((USItype) (al)), \
  410. "g" ((USItype) (bl)))
  411. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  412. __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
  413. : "=r" ((USItype) (sh)), \
  414. "=&r" ((USItype) (sl)) \
  415. : "0" ((USItype) (ah)), \
  416. "g" ((USItype) (bh)), \
  417. "1" ((USItype) (al)), \
  418. "g" ((USItype) (bl)))
  419. #define umul_ppmm(w1, w0, u, v) \
  420. __asm__ ("mul{l} %3" \
  421. : "=a" ((USItype) (w0)), \
  422. "=d" ((USItype) (w1)) \
  423. : "%0" ((USItype) (u)), \
  424. "rm" ((USItype) (v)))
  425. #define udiv_qrnnd(q, r, n1, n0, dv) \
  426. __asm__ ("div{l} %4" \
  427. : "=a" ((USItype) (q)), \
  428. "=d" ((USItype) (r)) \
  429. : "0" ((USItype) (n0)), \
  430. "1" ((USItype) (n1)), \
  431. "rm" ((USItype) (dv)))
  432. #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
  433. #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
  434. #define UMUL_TIME 40
  435. #define UDIV_TIME 40
  436. #endif /* 80x86 */
  437. #if defined (__x86_64__) && W_TYPE_SIZE == 64
  438. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  439. __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
  440. : "=r" ((UDItype) (sh)), \
  441. "=&r" ((UDItype) (sl)) \
  442. : "%0" ((UDItype) (ah)), \
  443. "rme" ((UDItype) (bh)), \
  444. "%1" ((UDItype) (al)), \
  445. "rme" ((UDItype) (bl)))
  446. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  447. __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
  448. : "=r" ((UDItype) (sh)), \
  449. "=&r" ((UDItype) (sl)) \
  450. : "0" ((UDItype) (ah)), \
  451. "rme" ((UDItype) (bh)), \
  452. "1" ((UDItype) (al)), \
  453. "rme" ((UDItype) (bl)))
  454. #define umul_ppmm(w1, w0, u, v) \
  455. __asm__ ("mul{q} %3" \
  456. : "=a" ((UDItype) (w0)), \
  457. "=d" ((UDItype) (w1)) \
  458. : "%0" ((UDItype) (u)), \
  459. "rm" ((UDItype) (v)))
  460. #define udiv_qrnnd(q, r, n1, n0, dv) \
  461. __asm__ ("div{q} %4" \
  462. : "=a" ((UDItype) (q)), \
  463. "=d" ((UDItype) (r)) \
  464. : "0" ((UDItype) (n0)), \
  465. "1" ((UDItype) (n1)), \
  466. "rm" ((UDItype) (dv)))
  467. #define count_leading_zeros(count, x) ((count) = __builtin_clzll (x))
  468. #define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x))
  469. #define UMUL_TIME 40
  470. #define UDIV_TIME 40
  471. #endif /* x86_64 */
  472. #if defined (__i960__) && W_TYPE_SIZE == 32
  473. #define umul_ppmm(w1, w0, u, v) \
  474. ({union {UDItype __ll; \
  475. struct {USItype __l, __h;} __i; \
  476. } __xx; \
  477. __asm__ ("emul %2,%1,%0" \
  478. : "=d" (__xx.__ll) \
  479. : "%dI" ((USItype) (u)), \
  480. "dI" ((USItype) (v))); \
  481. (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
  482. #define __umulsidi3(u, v) \
  483. ({UDItype __w; \
  484. __asm__ ("emul %2,%1,%0" \
  485. : "=d" (__w) \
  486. : "%dI" ((USItype) (u)), \
  487. "dI" ((USItype) (v))); \
  488. __w; })
  489. #endif /* __i960__ */
  490. #if defined (__ia64) && W_TYPE_SIZE == 64
  491. /* This form encourages gcc (pre-release 3.4 at least) to emit predicated
  492. "sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic
  493. code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
  494. register, which takes an extra cycle. */
  495. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  496. do { \
  497. UWtype __x; \
  498. __x = (al) - (bl); \
  499. if ((al) < (bl)) \
  500. (sh) = (ah) - (bh) - 1; \
  501. else \
  502. (sh) = (ah) - (bh); \
  503. (sl) = __x; \
  504. } while (0)
  505. /* Do both product parts in assembly, since that gives better code with
  506. all gcc versions. Some callers will just use the upper part, and in
  507. that situation we waste an instruction, but not any cycles. */
  508. #define umul_ppmm(ph, pl, m0, m1) \
  509. __asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
  510. : "=&f" (ph), "=f" (pl) \
  511. : "f" (m0), "f" (m1))
  512. #define count_leading_zeros(count, x) \
  513. do { \
  514. UWtype _x = (x), _y, _a, _c; \
  515. __asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
  516. __asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
  517. _c = (_a - 1) << 3; \
  518. _x >>= _c; \
  519. if (_x >= 1 << 4) \
  520. _x >>= 4, _c += 4; \
  521. if (_x >= 1 << 2) \
  522. _x >>= 2, _c += 2; \
  523. _c += _x >> 1; \
  524. (count) = W_TYPE_SIZE - 1 - _c; \
  525. } while (0)
  526. /* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
  527. based, and we don't need a special case for x==0 here */
  528. #define count_trailing_zeros(count, x) \
  529. do { \
  530. UWtype __ctz_x = (x); \
  531. __asm__ ("popcnt %0 = %1" \
  532. : "=r" (count) \
  533. : "r" ((__ctz_x-1) & ~__ctz_x)); \
  534. } while (0)
  535. #define UMUL_TIME 14
  536. #endif
  537. #if defined (__M32R__) && W_TYPE_SIZE == 32
  538. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  539. /* The cmp clears the condition bit. */ \
  540. __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
  541. : "=r" ((USItype) (sh)), \
  542. "=&r" ((USItype) (sl)) \
  543. : "0" ((USItype) (ah)), \
  544. "r" ((USItype) (bh)), \
  545. "1" ((USItype) (al)), \
  546. "r" ((USItype) (bl)) \
  547. : "cbit")
  548. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  549. /* The cmp clears the condition bit. */ \
  550. __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
  551. : "=r" ((USItype) (sh)), \
  552. "=&r" ((USItype) (sl)) \
  553. : "0" ((USItype) (ah)), \
  554. "r" ((USItype) (bh)), \
  555. "1" ((USItype) (al)), \
  556. "r" ((USItype) (bl)) \
  557. : "cbit")
  558. #endif /* __M32R__ */
  559. #if defined (__mc68000__) && W_TYPE_SIZE == 32
  560. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  561. __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
  562. : "=d" ((USItype) (sh)), \
  563. "=&d" ((USItype) (sl)) \
  564. : "%0" ((USItype) (ah)), \
  565. "d" ((USItype) (bh)), \
  566. "%1" ((USItype) (al)), \
  567. "g" ((USItype) (bl)))
  568. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  569. __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
  570. : "=d" ((USItype) (sh)), \
  571. "=&d" ((USItype) (sl)) \
  572. : "0" ((USItype) (ah)), \
  573. "d" ((USItype) (bh)), \
  574. "1" ((USItype) (al)), \
  575. "g" ((USItype) (bl)))
  576. /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
  577. #if (defined (__mc68020__) && !defined (__mc68060__))
  578. #define umul_ppmm(w1, w0, u, v) \
  579. __asm__ ("mulu%.l %3,%1:%0" \
  580. : "=d" ((USItype) (w0)), \
  581. "=d" ((USItype) (w1)) \
  582. : "%0" ((USItype) (u)), \
  583. "dmi" ((USItype) (v)))
  584. #define UMUL_TIME 45
  585. #define udiv_qrnnd(q, r, n1, n0, d) \
  586. __asm__ ("divu%.l %4,%1:%0" \
  587. : "=d" ((USItype) (q)), \
  588. "=d" ((USItype) (r)) \
  589. : "0" ((USItype) (n0)), \
  590. "1" ((USItype) (n1)), \
  591. "dmi" ((USItype) (d)))
  592. #define UDIV_TIME 90
  593. #define sdiv_qrnnd(q, r, n1, n0, d) \
  594. __asm__ ("divs%.l %4,%1:%0" \
  595. : "=d" ((USItype) (q)), \
  596. "=d" ((USItype) (r)) \
  597. : "0" ((USItype) (n0)), \
  598. "1" ((USItype) (n1)), \
  599. "dmi" ((USItype) (d)))
  600. #elif defined (__mcoldfire__) /* not mc68020 */
  601. #define umul_ppmm(xh, xl, a, b) \
  602. __asm__ ("| Inlined umul_ppmm\n" \
  603. " move%.l %2,%/d0\n" \
  604. " move%.l %3,%/d1\n" \
  605. " move%.l %/d0,%/d2\n" \
  606. " swap %/d0\n" \
  607. " move%.l %/d1,%/d3\n" \
  608. " swap %/d1\n" \
  609. " move%.w %/d2,%/d4\n" \
  610. " mulu %/d3,%/d4\n" \
  611. " mulu %/d1,%/d2\n" \
  612. " mulu %/d0,%/d3\n" \
  613. " mulu %/d0,%/d1\n" \
  614. " move%.l %/d4,%/d0\n" \
  615. " clr%.w %/d0\n" \
  616. " swap %/d0\n" \
  617. " add%.l %/d0,%/d2\n" \
  618. " add%.l %/d3,%/d2\n" \
  619. " jcc 1f\n" \
  620. " add%.l %#65536,%/d1\n" \
  621. "1: swap %/d2\n" \
  622. " moveq %#0,%/d0\n" \
  623. " move%.w %/d2,%/d0\n" \
  624. " move%.w %/d4,%/d2\n" \
  625. " move%.l %/d2,%1\n" \
  626. " add%.l %/d1,%/d0\n" \
  627. " move%.l %/d0,%0" \
  628. : "=g" ((USItype) (xh)), \
  629. "=g" ((USItype) (xl)) \
  630. : "g" ((USItype) (a)), \
  631. "g" ((USItype) (b)) \
  632. : "d0", "d1", "d2", "d3", "d4")
  633. #define UMUL_TIME 100
  634. #define UDIV_TIME 400
  635. #else /* not ColdFire */
  636. /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
  637. #define umul_ppmm(xh, xl, a, b) \
  638. __asm__ ("| Inlined umul_ppmm\n" \
  639. " move%.l %2,%/d0\n" \
  640. " move%.l %3,%/d1\n" \
  641. " move%.l %/d0,%/d2\n" \
  642. " swap %/d0\n" \
  643. " move%.l %/d1,%/d3\n" \
  644. " swap %/d1\n" \
  645. " move%.w %/d2,%/d4\n" \
  646. " mulu %/d3,%/d4\n" \
  647. " mulu %/d1,%/d2\n" \
  648. " mulu %/d0,%/d3\n" \
  649. " mulu %/d0,%/d1\n" \
  650. " move%.l %/d4,%/d0\n" \
  651. " eor%.w %/d0,%/d0\n" \
  652. " swap %/d0\n" \
  653. " add%.l %/d0,%/d2\n" \
  654. " add%.l %/d3,%/d2\n" \
  655. " jcc 1f\n" \
  656. " add%.l %#65536,%/d1\n" \
  657. "1: swap %/d2\n" \
  658. " moveq %#0,%/d0\n" \
  659. " move%.w %/d2,%/d0\n" \
  660. " move%.w %/d4,%/d2\n" \
  661. " move%.l %/d2,%1\n" \
  662. " add%.l %/d1,%/d0\n" \
  663. " move%.l %/d0,%0" \
  664. : "=g" ((USItype) (xh)), \
  665. "=g" ((USItype) (xl)) \
  666. : "g" ((USItype) (a)), \
  667. "g" ((USItype) (b)) \
  668. : "d0", "d1", "d2", "d3", "d4")
  669. #define UMUL_TIME 100
  670. #define UDIV_TIME 400
  671. #endif /* not mc68020 */
  672. /* The '020, '030, '040 and '060 have bitfield insns.
  673. cpu32 disguises as a 68020, but lacks them. */
  674. #if defined (__mc68020__) && !defined (__mcpu32__)
  675. #define count_leading_zeros(count, x) \
  676. __asm__ ("bfffo %1{%b2:%b2},%0" \
  677. : "=d" ((USItype) (count)) \
  678. : "od" ((USItype) (x)), "n" (0))
  679. /* Some ColdFire architectures have a ff1 instruction supported via
  680. __builtin_clz. */
  681. #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
  682. #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
  683. #define COUNT_LEADING_ZEROS_0 32
  684. #endif
  685. #endif /* mc68000 */
  686. #if defined (__m88000__) && W_TYPE_SIZE == 32
  687. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  688. __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
  689. : "=r" ((USItype) (sh)), \
  690. "=&r" ((USItype) (sl)) \
  691. : "%rJ" ((USItype) (ah)), \
  692. "rJ" ((USItype) (bh)), \
  693. "%rJ" ((USItype) (al)), \
  694. "rJ" ((USItype) (bl)))
  695. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  696. __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
  697. : "=r" ((USItype) (sh)), \
  698. "=&r" ((USItype) (sl)) \
  699. : "rJ" ((USItype) (ah)), \
  700. "rJ" ((USItype) (bh)), \
  701. "rJ" ((USItype) (al)), \
  702. "rJ" ((USItype) (bl)))
  703. #define count_leading_zeros(count, x) \
  704. do { \
  705. USItype __cbtmp; \
  706. __asm__ ("ff1 %0,%1" \
  707. : "=r" (__cbtmp) \
  708. : "r" ((USItype) (x))); \
  709. (count) = __cbtmp ^ 31; \
  710. } while (0)
  711. #define COUNT_LEADING_ZEROS_0 63 /* sic */
  712. #if defined (__mc88110__)
  713. #define umul_ppmm(wh, wl, u, v) \
  714. do { \
  715. union {UDItype __ll; \
  716. struct {USItype __h, __l;} __i; \
  717. } __xx; \
  718. __asm__ ("mulu.d %0,%1,%2" \
  719. : "=r" (__xx.__ll) \
  720. : "r" ((USItype) (u)), \
  721. "r" ((USItype) (v))); \
  722. (wh) = __xx.__i.__h; \
  723. (wl) = __xx.__i.__l; \
  724. } while (0)
  725. #define udiv_qrnnd(q, r, n1, n0, d) \
  726. ({union {UDItype __ll; \
  727. struct {USItype __h, __l;} __i; \
  728. } __xx; \
  729. USItype __q; \
  730. __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
  731. __asm__ ("divu.d %0,%1,%2" \
  732. : "=r" (__q) \
  733. : "r" (__xx.__ll), \
  734. "r" ((USItype) (d))); \
  735. (r) = (n0) - __q * (d); (q) = __q; })
  736. #define UMUL_TIME 5
  737. #define UDIV_TIME 25
  738. #else
  739. #define UMUL_TIME 17
  740. #define UDIV_TIME 150
  741. #endif /* __mc88110__ */
  742. #endif /* __m88000__ */
  743. #if defined (__mn10300__)
  744. # if defined (__AM33__)
  745. # define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
  746. # define umul_ppmm(w1, w0, u, v) \
  747. asm("mulu %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
  748. # define smul_ppmm(w1, w0, u, v) \
  749. asm("mul %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
  750. # else
  751. # define umul_ppmm(w1, w0, u, v) \
  752. asm("nop; nop; mulu %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
  753. # define smul_ppmm(w1, w0, u, v) \
  754. asm("nop; nop; mul %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
  755. # endif
  756. # define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  757. do { \
  758. DWunion __s, __a, __b; \
  759. __a.s.low = (al); __a.s.high = (ah); \
  760. __b.s.low = (bl); __b.s.high = (bh); \
  761. __s.ll = __a.ll + __b.ll; \
  762. (sl) = __s.s.low; (sh) = __s.s.high; \
  763. } while (0)
  764. # define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  765. do { \
  766. DWunion __s, __a, __b; \
  767. __a.s.low = (al); __a.s.high = (ah); \
  768. __b.s.low = (bl); __b.s.high = (bh); \
  769. __s.ll = __a.ll - __b.ll; \
  770. (sl) = __s.s.low; (sh) = __s.s.high; \
  771. } while (0)
  772. # define udiv_qrnnd(q, r, nh, nl, d) \
  773. asm("divu %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
  774. # define sdiv_qrnnd(q, r, nh, nl, d) \
  775. asm("div %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
  776. # define UMUL_TIME 3
  777. # define UDIV_TIME 38
  778. #endif
  779. #if defined (__mips__) && W_TYPE_SIZE == 32
  780. #define umul_ppmm(w1, w0, u, v) \
  781. do { \
  782. UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
  783. (w1) = (USItype) (__x >> 32); \
  784. (w0) = (USItype) (__x); \
  785. } while (0)
  786. #define UMUL_TIME 10
  787. #define UDIV_TIME 100
  788. #if (__mips == 32 || __mips == 64) && ! defined (__mips16)
  789. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
  790. #define COUNT_LEADING_ZEROS_0 32
  791. #endif
  792. #endif /* __mips__ */
  793. #if defined (__ns32000__) && W_TYPE_SIZE == 32
  794. #define umul_ppmm(w1, w0, u, v) \
  795. ({union {UDItype __ll; \
  796. struct {USItype __l, __h;} __i; \
  797. } __xx; \
  798. __asm__ ("meid %2,%0" \
  799. : "=g" (__xx.__ll) \
  800. : "%0" ((USItype) (u)), \
  801. "g" ((USItype) (v))); \
  802. (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
  803. #define __umulsidi3(u, v) \
  804. ({UDItype __w; \
  805. __asm__ ("meid %2,%0" \
  806. : "=g" (__w) \
  807. : "%0" ((USItype) (u)), \
  808. "g" ((USItype) (v))); \
  809. __w; })
  810. #define udiv_qrnnd(q, r, n1, n0, d) \
  811. ({union {UDItype __ll; \
  812. struct {USItype __l, __h;} __i; \
  813. } __xx; \
  814. __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
  815. __asm__ ("deid %2,%0" \
  816. : "=g" (__xx.__ll) \
  817. : "0" (__xx.__ll), \
  818. "g" ((USItype) (d))); \
  819. (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
  820. #define count_trailing_zeros(count,x) \
  821. do { \
  822. __asm__ ("ffsd %2,%0" \
  823. : "=r" ((USItype) (count)) \
  824. : "0" ((USItype) 0), \
  825. "r" ((USItype) (x))); \
  826. } while (0)
  827. #endif /* __ns32000__ */
  828. /* FIXME: We should test _IBMR2 here when we add assembly support for the
  829. system vendor compilers.
  830. FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
  831. enough, since that hits ARM and m68k too. */
  832. #if (defined (_ARCH_PPC) /* AIX */ \
  833. || defined (__powerpc__) /* gcc */ \
  834. || defined (__POWERPC__) /* BEOS */ \
  835. || defined (__ppc__) /* Darwin */ \
  836. || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
  837. || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
  838. && CPU_FAMILY == PPC) \
  839. ) && W_TYPE_SIZE == 32
  840. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  841. do { \
  842. if (__builtin_constant_p (bh) && (bh) == 0) \
  843. __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
  844. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  845. else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
  846. __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
  847. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  848. else \
  849. __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
  850. : "=r" (sh), "=&r" (sl) \
  851. : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
  852. } while (0)
  853. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  854. do { \
  855. if (__builtin_constant_p (ah) && (ah) == 0) \
  856. __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
  857. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  858. else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
  859. __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
  860. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  861. else if (__builtin_constant_p (bh) && (bh) == 0) \
  862. __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
  863. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  864. else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
  865. __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
  866. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  867. else \
  868. __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
  869. : "=r" (sh), "=&r" (sl) \
  870. : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
  871. } while (0)
  872. #define count_leading_zeros(count, x) \
  873. __asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x))
  874. #define COUNT_LEADING_ZEROS_0 32
  875. #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
  876. || defined (__ppc__) \
  877. || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
  878. || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
  879. && CPU_FAMILY == PPC)
  880. #define umul_ppmm(ph, pl, m0, m1) \
  881. do { \
  882. USItype __m0 = (m0), __m1 = (m1); \
  883. __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  884. (pl) = __m0 * __m1; \
  885. } while (0)
  886. #define UMUL_TIME 15
  887. #define smul_ppmm(ph, pl, m0, m1) \
  888. do { \
  889. SItype __m0 = (m0), __m1 = (m1); \
  890. __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  891. (pl) = __m0 * __m1; \
  892. } while (0)
  893. #define SMUL_TIME 14
  894. #define UDIV_TIME 120
  895. #endif
  896. #endif /* 32-bit POWER architecture variants. */
  897. /* We should test _IBMR2 here when we add assembly support for the system
  898. vendor compilers. */
  899. #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
  900. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  901. do { \
  902. if (__builtin_constant_p (bh) && (bh) == 0) \
  903. __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
  904. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  905. else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
  906. __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
  907. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  908. else \
  909. __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
  910. : "=r" (sh), "=&r" (sl) \
  911. : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
  912. } while (0)
  913. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  914. do { \
  915. if (__builtin_constant_p (ah) && (ah) == 0) \
  916. __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
  917. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  918. else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
  919. __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
  920. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  921. else if (__builtin_constant_p (bh) && (bh) == 0) \
  922. __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
  923. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  924. else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
  925. __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
  926. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  927. else \
  928. __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
  929. : "=r" (sh), "=&r" (sl) \
  930. : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
  931. } while (0)
  932. #define count_leading_zeros(count, x) \
  933. __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
  934. #define COUNT_LEADING_ZEROS_0 64
  935. #define umul_ppmm(ph, pl, m0, m1) \
  936. do { \
  937. UDItype __m0 = (m0), __m1 = (m1); \
  938. __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  939. (pl) = __m0 * __m1; \
  940. } while (0)
  941. #define UMUL_TIME 15
  942. #define smul_ppmm(ph, pl, m0, m1) \
  943. do { \
  944. DItype __m0 = (m0), __m1 = (m1); \
  945. __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  946. (pl) = __m0 * __m1; \
  947. } while (0)
  948. #define SMUL_TIME 14 /* ??? */
  949. #define UDIV_TIME 120 /* ??? */
  950. #endif /* 64-bit PowerPC. */
  951. #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
  952. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  953. __asm__ ("a %1,%5\n\tae %0,%3" \
  954. : "=r" ((USItype) (sh)), \
  955. "=&r" ((USItype) (sl)) \
  956. : "%0" ((USItype) (ah)), \
  957. "r" ((USItype) (bh)), \
  958. "%1" ((USItype) (al)), \
  959. "r" ((USItype) (bl)))
  960. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  961. __asm__ ("s %1,%5\n\tse %0,%3" \
  962. : "=r" ((USItype) (sh)), \
  963. "=&r" ((USItype) (sl)) \
  964. : "0" ((USItype) (ah)), \
  965. "r" ((USItype) (bh)), \
  966. "1" ((USItype) (al)), \
  967. "r" ((USItype) (bl)))
  968. #define umul_ppmm(ph, pl, m0, m1) \
  969. do { \
  970. USItype __m0 = (m0), __m1 = (m1); \
  971. __asm__ ( \
  972. "s r2,r2\n" \
  973. " mts r10,%2\n" \
  974. " m r2,%3\n" \
  975. " m r2,%3\n" \
  976. " m r2,%3\n" \
  977. " m r2,%3\n" \
  978. " m r2,%3\n" \
  979. " m r2,%3\n" \
  980. " m r2,%3\n" \
  981. " m r2,%3\n" \
  982. " m r2,%3\n" \
  983. " m r2,%3\n" \
  984. " m r2,%3\n" \
  985. " m r2,%3\n" \
  986. " m r2,%3\n" \
  987. " m r2,%3\n" \
  988. " m r2,%3\n" \
  989. " m r2,%3\n" \
  990. " cas %0,r2,r0\n" \
  991. " mfs r10,%1" \
  992. : "=r" ((USItype) (ph)), \
  993. "=r" ((USItype) (pl)) \
  994. : "%r" (__m0), \
  995. "r" (__m1) \
  996. : "r2"); \
  997. (ph) += ((((SItype) __m0 >> 31) & __m1) \
  998. + (((SItype) __m1 >> 31) & __m0)); \
  999. } while (0)
  1000. #define UMUL_TIME 20
  1001. #define UDIV_TIME 200
  1002. #define count_leading_zeros(count, x) \
  1003. do { \
  1004. if ((x) >= 0x10000) \
  1005. __asm__ ("clz %0,%1" \
  1006. : "=r" ((USItype) (count)) \
  1007. : "r" ((USItype) (x) >> 16)); \
  1008. else \
  1009. { \
  1010. __asm__ ("clz %0,%1" \
  1011. : "=r" ((USItype) (count)) \
  1012. : "r" ((USItype) (x))); \
  1013. (count) += 16; \
  1014. } \
  1015. } while (0)
  1016. #endif
  1017. #if defined(__sh__) && (!defined (__SHMEDIA__) || !__SHMEDIA__) && W_TYPE_SIZE == 32
  1018. #ifndef __sh1__
  1019. #define umul_ppmm(w1, w0, u, v) \
  1020. __asm__ ( \
  1021. "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
  1022. : "=r<" ((USItype)(w1)), \
  1023. "=r<" ((USItype)(w0)) \
  1024. : "r" ((USItype)(u)), \
  1025. "r" ((USItype)(v)) \
  1026. : "macl", "mach")
  1027. #define UMUL_TIME 5
  1028. #endif
  1029. /* This is the same algorithm as __udiv_qrnnd_c. */
  1030. #define UDIV_NEEDS_NORMALIZATION 1
  1031. #ifdef __FDPIC__
  1032. /* FDPIC needs a special version of the asm fragment to extract the
  1033. code address from the function descriptor. __udiv_qrnnd_16 is
  1034. assumed to be local and not to use the GOT, so loading r12 is
  1035. not needed. */
  1036. #define udiv_qrnnd(q, r, n1, n0, d) \
  1037. do { \
  1038. extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
  1039. __attribute__ ((visibility ("hidden"))); \
  1040. /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
  1041. __asm__ ( \
  1042. "mov%M4 %4,r5\n" \
  1043. " swap.w %3,r4\n" \
  1044. " swap.w r5,r6\n" \
  1045. " mov.l @%5,r2\n" \
  1046. " jsr @r2\n" \
  1047. " shll16 r6\n" \
  1048. " swap.w r4,r4\n" \
  1049. " mov.l @%5,r2\n" \
  1050. " jsr @r2\n" \
  1051. " swap.w r1,%0\n" \
  1052. " or r1,%0" \
  1053. : "=r" (q), "=&z" (r) \
  1054. : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
  1055. : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
  1056. } while (0)
  1057. #else
  1058. #define udiv_qrnnd(q, r, n1, n0, d) \
  1059. do { \
  1060. extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
  1061. __attribute__ ((visibility ("hidden"))); \
  1062. /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
  1063. __asm__ ( \
  1064. "mov%M4 %4,r5\n" \
  1065. " swap.w %3,r4\n" \
  1066. " swap.w r5,r6\n" \
  1067. " jsr @%5\n" \
  1068. " shll16 r6\n" \
  1069. " swap.w r4,r4\n" \
  1070. " jsr @%5\n" \
  1071. " swap.w r1,%0\n" \
  1072. " or r1,%0" \
  1073. : "=r" (q), "=&z" (r) \
  1074. : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
  1075. : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
  1076. } while (0)
  1077. #endif /* __FDPIC__ */
  1078. #define UDIV_TIME 80
  1079. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1080. __asm__ ("clrt;subc %5,%1; subc %4,%0" \
  1081. : "=r" (sh), "=r" (sl) \
  1082. : "0" (ah), "1" (al), "r" (bh), "r" (bl) : "t")
  1083. #endif /* __sh__ */
  1084. #if defined (__SH5__) && defined (__SHMEDIA__) && __SHMEDIA__ && W_TYPE_SIZE == 32
  1085. #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
  1086. #define count_leading_zeros(count, x) \
  1087. do \
  1088. { \
  1089. UDItype x_ = (USItype)(x); \
  1090. SItype c_; \
  1091. \
  1092. __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
  1093. (count) = c_ - 31; \
  1094. } \
  1095. while (0)
  1096. #define COUNT_LEADING_ZEROS_0 32
  1097. #endif
  1098. #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
  1099. && W_TYPE_SIZE == 32
  1100. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1101. __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
  1102. : "=r" ((USItype) (sh)), \
  1103. "=&r" ((USItype) (sl)) \
  1104. : "%rJ" ((USItype) (ah)), \
  1105. "rI" ((USItype) (bh)), \
  1106. "%rJ" ((USItype) (al)), \
  1107. "rI" ((USItype) (bl)) \
  1108. __CLOBBER_CC)
  1109. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1110. __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
  1111. : "=r" ((USItype) (sh)), \
  1112. "=&r" ((USItype) (sl)) \
  1113. : "rJ" ((USItype) (ah)), \
  1114. "rI" ((USItype) (bh)), \
  1115. "rJ" ((USItype) (al)), \
  1116. "rI" ((USItype) (bl)) \
  1117. __CLOBBER_CC)
  1118. #if defined (__sparc_v9__)
  1119. #define umul_ppmm(w1, w0, u, v) \
  1120. do { \
  1121. register USItype __g1 asm ("g1"); \
  1122. __asm__ ("umul\t%2,%3,%1\n\t" \
  1123. "srlx\t%1, 32, %0" \
  1124. : "=r" ((USItype) (w1)), \
  1125. "=r" (__g1) \
  1126. : "r" ((USItype) (u)), \
  1127. "r" ((USItype) (v))); \
  1128. (w0) = __g1; \
  1129. } while (0)
  1130. #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
  1131. __asm__ ("mov\t%2,%%y\n\t" \
  1132. "udiv\t%3,%4,%0\n\t" \
  1133. "umul\t%0,%4,%1\n\t" \
  1134. "sub\t%3,%1,%1" \
  1135. : "=&r" ((USItype) (__q)), \
  1136. "=&r" ((USItype) (__r)) \
  1137. : "r" ((USItype) (__n1)), \
  1138. "r" ((USItype) (__n0)), \
  1139. "r" ((USItype) (__d)))
  1140. #else
  1141. #if defined (__sparc_v8__)
  1142. #define umul_ppmm(w1, w0, u, v) \
  1143. __asm__ ("umul %2,%3,%1;rd %%y,%0" \
  1144. : "=r" ((USItype) (w1)), \
  1145. "=r" ((USItype) (w0)) \
  1146. : "r" ((USItype) (u)), \
  1147. "r" ((USItype) (v)))
  1148. #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
  1149. __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
  1150. : "=&r" ((USItype) (__q)), \
  1151. "=&r" ((USItype) (__r)) \
  1152. : "r" ((USItype) (__n1)), \
  1153. "r" ((USItype) (__n0)), \
  1154. "r" ((USItype) (__d)))
  1155. #else
  1156. #if defined (__sparclite__)
  1157. /* This has hardware multiply but not divide. It also has two additional
  1158. instructions scan (ffs from high bit) and divscc. */
  1159. #define umul_ppmm(w1, w0, u, v) \
  1160. __asm__ ("umul %2,%3,%1;rd %%y,%0" \
  1161. : "=r" ((USItype) (w1)), \
  1162. "=r" ((USItype) (w0)) \
  1163. : "r" ((USItype) (u)), \
  1164. "r" ((USItype) (v)))
  1165. #define udiv_qrnnd(q, r, n1, n0, d) \
  1166. __asm__ ("! Inlined udiv_qrnnd\n" \
  1167. " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
  1168. " tst %%g0\n" \
  1169. " divscc %3,%4,%%g1\n" \
  1170. " divscc %%g1,%4,%%g1\n" \
  1171. " divscc %%g1,%4,%%g1\n" \
  1172. " divscc %%g1,%4,%%g1\n" \
  1173. " divscc %%g1,%4,%%g1\n" \
  1174. " divscc %%g1,%4,%%g1\n" \
  1175. " divscc %%g1,%4,%%g1\n" \
  1176. " divscc %%g1,%4,%%g1\n" \
  1177. " divscc %%g1,%4,%%g1\n" \
  1178. " divscc %%g1,%4,%%g1\n" \
  1179. " divscc %%g1,%4,%%g1\n" \
  1180. " divscc %%g1,%4,%%g1\n" \
  1181. " divscc %%g1,%4,%%g1\n" \
  1182. " divscc %%g1,%4,%%g1\n" \
  1183. " divscc %%g1,%4,%%g1\n" \
  1184. " divscc %%g1,%4,%%g1\n" \
  1185. " divscc %%g1,%4,%%g1\n" \
  1186. " divscc %%g1,%4,%%g1\n" \
  1187. " divscc %%g1,%4,%%g1\n" \
  1188. " divscc %%g1,%4,%%g1\n" \
  1189. " divscc %%g1,%4,%%g1\n" \
  1190. " divscc %%g1,%4,%%g1\n" \
  1191. " divscc %%g1,%4,%%g1\n" \
  1192. " divscc %%g1,%4,%%g1\n" \
  1193. " divscc %%g1,%4,%%g1\n" \
  1194. " divscc %%g1,%4,%%g1\n" \
  1195. " divscc %%g1,%4,%%g1\n" \
  1196. " divscc %%g1,%4,%%g1\n" \
  1197. " divscc %%g1,%4,%%g1\n" \
  1198. " divscc %%g1,%4,%%g1\n" \
  1199. " divscc %%g1,%4,%%g1\n" \
  1200. " divscc %%g1,%4,%0\n" \
  1201. " rd %%y,%1\n" \
  1202. " bl,a 1f\n" \
  1203. " add %1,%4,%1\n" \
  1204. "1: ! End of inline udiv_qrnnd" \
  1205. : "=r" ((USItype) (q)), \
  1206. "=r" ((USItype) (r)) \
  1207. : "r" ((USItype) (n1)), \
  1208. "r" ((USItype) (n0)), \
  1209. "rI" ((USItype) (d)) \
  1210. : "g1" __AND_CLOBBER_CC)
  1211. #define UDIV_TIME 37
  1212. #define count_leading_zeros(count, x) \
  1213. do { \
  1214. __asm__ ("scan %1,1,%0" \
  1215. : "=r" ((USItype) (count)) \
  1216. : "r" ((USItype) (x))); \
  1217. } while (0)
  1218. /* Early sparclites return 63 for an argument of 0, but they warn that future
  1219. implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
  1220. undefined. */
  1221. #else
  1222. /* SPARC without integer multiplication and divide instructions.
  1223. (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
  1224. #define umul_ppmm(w1, w0, u, v) \
  1225. __asm__ ("! Inlined umul_ppmm\n" \
  1226. " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
  1227. " sra %3,31,%%o5 ! Don't move this insn\n" \
  1228. " and %2,%%o5,%%o5 ! Don't move this insn\n" \
  1229. " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
  1230. " mulscc %%g1,%3,%%g1\n" \
  1231. " mulscc %%g1,%3,%%g1\n" \
  1232. " mulscc %%g1,%3,%%g1\n" \
  1233. " mulscc %%g1,%3,%%g1\n" \
  1234. " mulscc %%g1,%3,%%g1\n" \
  1235. " mulscc %%g1,%3,%%g1\n" \
  1236. " mulscc %%g1,%3,%%g1\n" \
  1237. " mulscc %%g1,%3,%%g1\n" \
  1238. " mulscc %%g1,%3,%%g1\n" \
  1239. " mulscc %%g1,%3,%%g1\n" \
  1240. " mulscc %%g1,%3,%%g1\n" \
  1241. " mulscc %%g1,%3,%%g1\n" \
  1242. " mulscc %%g1,%3,%%g1\n" \
  1243. " mulscc %%g1,%3,%%g1\n" \
  1244. " mulscc %%g1,%3,%%g1\n" \
  1245. " mulscc %%g1,%3,%%g1\n" \
  1246. " mulscc %%g1,%3,%%g1\n" \
  1247. " mulscc %%g1,%3,%%g1\n" \
  1248. " mulscc %%g1,%3,%%g1\n" \
  1249. " mulscc %%g1,%3,%%g1\n" \
  1250. " mulscc %%g1,%3,%%g1\n" \
  1251. " mulscc %%g1,%3,%%g1\n" \
  1252. " mulscc %%g1,%3,%%g1\n" \
  1253. " mulscc %%g1,%3,%%g1\n" \
  1254. " mulscc %%g1,%3,%%g1\n" \
  1255. " mulscc %%g1,%3,%%g1\n" \
  1256. " mulscc %%g1,%3,%%g1\n" \
  1257. " mulscc %%g1,%3,%%g1\n" \
  1258. " mulscc %%g1,%3,%%g1\n" \
  1259. " mulscc %%g1,%3,%%g1\n" \
  1260. " mulscc %%g1,%3,%%g1\n" \
  1261. " mulscc %%g1,%3,%%g1\n" \
  1262. " mulscc %%g1,0,%%g1\n" \
  1263. " add %%g1,%%o5,%0\n" \
  1264. " rd %%y,%1" \
  1265. : "=r" ((USItype) (w1)), \
  1266. "=r" ((USItype) (w0)) \
  1267. : "%rI" ((USItype) (u)), \
  1268. "r" ((USItype) (v)) \
  1269. : "g1", "o5" __AND_CLOBBER_CC)
  1270. #define UMUL_TIME 39 /* 39 instructions */
  1271. /* It's quite necessary to add this much assembler for the sparc.
  1272. The default udiv_qrnnd (in C) is more than 10 times slower! */
  1273. #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
  1274. __asm__ ("! Inlined udiv_qrnnd\n" \
  1275. " mov 32,%%g1\n" \
  1276. " subcc %1,%2,%%g0\n" \
  1277. "1: bcs 5f\n" \
  1278. " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
  1279. " sub %1,%2,%1 ! this kills msb of n\n" \
  1280. " addx %1,%1,%1 ! so this can't give carry\n" \
  1281. " subcc %%g1,1,%%g1\n" \
  1282. "2: bne 1b\n" \
  1283. " subcc %1,%2,%%g0\n" \
  1284. " bcs 3f\n" \
  1285. " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
  1286. " b 3f\n" \
  1287. " sub %1,%2,%1 ! this kills msb of n\n" \
  1288. "4: sub %1,%2,%1\n" \
  1289. "5: addxcc %1,%1,%1\n" \
  1290. " bcc 2b\n" \
  1291. " subcc %%g1,1,%%g1\n" \
  1292. "! Got carry from n. Subtract next step to cancel this carry.\n" \
  1293. " bne 4b\n" \
  1294. " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
  1295. " sub %1,%2,%1\n" \
  1296. "3: xnor %0,0,%0\n" \
  1297. " ! End of inline udiv_qrnnd" \
  1298. : "=&r" ((USItype) (__q)), \
  1299. "=&r" ((USItype) (__r)) \
  1300. : "r" ((USItype) (__d)), \
  1301. "1" ((USItype) (__n1)), \
  1302. "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
  1303. #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
  1304. #endif /* __sparclite__ */
  1305. #endif /* __sparc_v8__ */
  1306. #endif /* __sparc_v9__ */
  1307. #endif /* sparc32 */
  1308. #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
  1309. && W_TYPE_SIZE == 64
  1310. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1311. do { \
  1312. UDItype __carry = 0; \
  1313. __asm__ ("addcc\t%r5,%6,%1\n\t" \
  1314. "add\t%r3,%4,%0\n\t" \
  1315. "movcs\t%%xcc, 1, %2\n\t" \
  1316. "add\t%0, %2, %0" \
  1317. : "=r" ((UDItype)(sh)), \
  1318. "=&r" ((UDItype)(sl)), \
  1319. "+r" (__carry) \
  1320. : "%rJ" ((UDItype)(ah)), \
  1321. "rI" ((UDItype)(bh)), \
  1322. "%rJ" ((UDItype)(al)), \
  1323. "rI" ((UDItype)(bl)) \
  1324. __CLOBBER_CC); \
  1325. } while (0)
  1326. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1327. do { \
  1328. UDItype __carry = 0; \
  1329. __asm__ ("subcc\t%r5,%6,%1\n\t" \
  1330. "sub\t%r3,%4,%0\n\t" \
  1331. "movcs\t%%xcc, 1, %2\n\t" \
  1332. "sub\t%0, %2, %0" \
  1333. : "=r" ((UDItype)(sh)), \
  1334. "=&r" ((UDItype)(sl)), \
  1335. "+r" (__carry) \
  1336. : "%rJ" ((UDItype)(ah)), \
  1337. "rI" ((UDItype)(bh)), \
  1338. "%rJ" ((UDItype)(al)), \
  1339. "rI" ((UDItype)(bl)) \
  1340. __CLOBBER_CC); \
  1341. } while (0)
  1342. #define umul_ppmm(wh, wl, u, v) \
  1343. do { \
  1344. UDItype tmp1, tmp2, tmp3, tmp4; \
  1345. __asm__ __volatile__ ( \
  1346. "srl %7,0,%3\n\t" \
  1347. "mulx %3,%6,%1\n\t" \
  1348. "srlx %6,32,%2\n\t" \
  1349. "mulx %2,%3,%4\n\t" \
  1350. "sllx %4,32,%5\n\t" \
  1351. "srl %6,0,%3\n\t" \
  1352. "sub %1,%5,%5\n\t" \
  1353. "srlx %5,32,%5\n\t" \
  1354. "addcc %4,%5,%4\n\t" \
  1355. "srlx %7,32,%5\n\t" \
  1356. "mulx %3,%5,%3\n\t" \
  1357. "mulx %2,%5,%5\n\t" \
  1358. "sethi %%hi(0x80000000),%2\n\t" \
  1359. "addcc %4,%3,%4\n\t" \
  1360. "srlx %4,32,%4\n\t" \
  1361. "add %2,%2,%2\n\t" \
  1362. "movcc %%xcc,%%g0,%2\n\t" \
  1363. "addcc %5,%4,%5\n\t" \
  1364. "sllx %3,32,%3\n\t" \
  1365. "add %1,%3,%1\n\t" \
  1366. "add %5,%2,%0" \
  1367. : "=r" ((UDItype)(wh)), \
  1368. "=&r" ((UDItype)(wl)), \
  1369. "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
  1370. : "r" ((UDItype)(u)), \
  1371. "r" ((UDItype)(v)) \
  1372. __CLOBBER_CC); \
  1373. } while (0)
  1374. #define UMUL_TIME 96
  1375. #define UDIV_TIME 230
  1376. #endif /* sparc64 */
  1377. #if defined (__vax__) && W_TYPE_SIZE == 32
  1378. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1379. __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
  1380. : "=g" ((USItype) (sh)), \
  1381. "=&g" ((USItype) (sl)) \
  1382. : "%0" ((USItype) (ah)), \
  1383. "g" ((USItype) (bh)), \
  1384. "%1" ((USItype) (al)), \
  1385. "g" ((USItype) (bl)))
  1386. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1387. __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
  1388. : "=g" ((USItype) (sh)), \
  1389. "=&g" ((USItype) (sl)) \
  1390. : "0" ((USItype) (ah)), \
  1391. "g" ((USItype) (bh)), \
  1392. "1" ((USItype) (al)), \
  1393. "g" ((USItype) (bl)))
  1394. #define umul_ppmm(xh, xl, m0, m1) \
  1395. do { \
  1396. union { \
  1397. UDItype __ll; \
  1398. struct {USItype __l, __h;} __i; \
  1399. } __xx; \
  1400. USItype __m0 = (m0), __m1 = (m1); \
  1401. __asm__ ("emul %1,%2,$0,%0" \
  1402. : "=r" (__xx.__ll) \
  1403. : "g" (__m0), \
  1404. "g" (__m1)); \
  1405. (xh) = __xx.__i.__h; \
  1406. (xl) = __xx.__i.__l; \
  1407. (xh) += ((((SItype) __m0 >> 31) & __m1) \
  1408. + (((SItype) __m1 >> 31) & __m0)); \
  1409. } while (0)
  1410. #define sdiv_qrnnd(q, r, n1, n0, d) \
  1411. do { \
  1412. union {DItype __ll; \
  1413. struct {SItype __l, __h;} __i; \
  1414. } __xx; \
  1415. __xx.__i.__h = n1; __xx.__i.__l = n0; \
  1416. __asm__ ("ediv %3,%2,%0,%1" \
  1417. : "=g" (q), "=g" (r) \
  1418. : "g" (__xx.__ll), "g" (d)); \
  1419. } while (0)
  1420. #endif /* __vax__ */
  1421. #ifdef _TMS320C6X
  1422. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1423. do \
  1424. { \
  1425. UDItype __ll; \
  1426. __asm__ ("addu .l1 %1, %2, %0" \
  1427. : "=a" (__ll) : "a" (al), "a" (bl)); \
  1428. (sl) = (USItype)__ll; \
  1429. (sh) = ((USItype)(__ll >> 32)) + (ah) + (bh); \
  1430. } \
  1431. while (0)
  1432. #ifdef _TMS320C6400_PLUS
  1433. #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
  1434. #define umul_ppmm(w1, w0, u, v) \
  1435. do { \
  1436. UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
  1437. (w1) = (USItype) (__x >> 32); \
  1438. (w0) = (USItype) (__x); \
  1439. } while (0)
  1440. #endif /* _TMS320C6400_PLUS */
  1441. #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
  1442. #ifdef _TMS320C6400
  1443. #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
  1444. #endif
  1445. #define UMUL_TIME 4
  1446. #define UDIV_TIME 40
  1447. #endif /* _TMS320C6X */
  1448. #if defined (__xtensa__) && W_TYPE_SIZE == 32
  1449. /* This code is not Xtensa-configuration-specific, so rely on the compiler
  1450. to expand builtin functions depending on what configuration features
  1451. are available. This avoids library calls when the operation can be
  1452. performed in-line. */
  1453. #define umul_ppmm(w1, w0, u, v) \
  1454. do { \
  1455. DWunion __w; \
  1456. __w.ll = __builtin_umulsidi3 (u, v); \
  1457. w1 = __w.s.high; \
  1458. w0 = __w.s.low; \
  1459. } while (0)
  1460. #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
  1461. #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
  1462. #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
  1463. #endif /* __xtensa__ */
  1464. #if defined xstormy16
  1465. extern UHItype __stormy16_count_leading_zeros (UHItype);
  1466. #define count_leading_zeros(count, x) \
  1467. do \
  1468. { \
  1469. UHItype size; \
  1470. \
  1471. /* We assume that W_TYPE_SIZE is a multiple of 16... */ \
  1472. for ((count) = 0, size = W_TYPE_SIZE; size; size -= 16) \
  1473. { \
  1474. UHItype c; \
  1475. \
  1476. c = __clzhi2 ((x) >> (size - 16)); \
  1477. (count) += c; \
  1478. if (c != 16) \
  1479. break; \
  1480. } \
  1481. } \
  1482. while (0)
  1483. #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
  1484. #endif
  1485. #if defined (__z8000__) && W_TYPE_SIZE == 16
  1486. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1487. __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
  1488. : "=r" ((unsigned int)(sh)), \
  1489. "=&r" ((unsigned int)(sl)) \
  1490. : "%0" ((unsigned int)(ah)), \
  1491. "r" ((unsigned int)(bh)), \
  1492. "%1" ((unsigned int)(al)), \
  1493. "rQR" ((unsigned int)(bl)))
  1494. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1495. __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
  1496. : "=r" ((unsigned int)(sh)), \
  1497. "=&r" ((unsigned int)(sl)) \
  1498. : "0" ((unsigned int)(ah)), \
  1499. "r" ((unsigned int)(bh)), \
  1500. "1" ((unsigned int)(al)), \
  1501. "rQR" ((unsigned int)(bl)))
  1502. #define umul_ppmm(xh, xl, m0, m1) \
  1503. do { \
  1504. union {long int __ll; \
  1505. struct {unsigned int __h, __l;} __i; \
  1506. } __xx; \
  1507. unsigned int __m0 = (m0), __m1 = (m1); \
  1508. __asm__ ("mult %S0,%H3" \
  1509. : "=r" (__xx.__i.__h), \
  1510. "=r" (__xx.__i.__l) \
  1511. : "%1" (__m0), \
  1512. "rQR" (__m1)); \
  1513. (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
  1514. (xh) += ((((signed int) __m0 >> 15) & __m1) \
  1515. + (((signed int) __m1 >> 15) & __m0)); \
  1516. } while (0)
  1517. #endif /* __z8000__ */
  1518. #endif /* __GNUC__ */
  1519. /* If this machine has no inline assembler, use C macros. */
  1520. #if !defined (add_ssaaaa)
  1521. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1522. do { \
  1523. UWtype __x; \
  1524. __x = (al) + (bl); \
  1525. (sh) = (ah) + (bh) + (__x < (al)); \
  1526. (sl) = __x; \
  1527. } while (0)
  1528. #endif
  1529. #if !defined (sub_ddmmss)
  1530. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1531. do { \
  1532. UWtype __x; \
  1533. __x = (al) - (bl); \
  1534. (sh) = (ah) - (bh) - (__x > (al)); \
  1535. (sl) = __x; \
  1536. } while (0)
  1537. #endif
  1538. /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
  1539. smul_ppmm. */
  1540. #if !defined (umul_ppmm) && defined (smul_ppmm)
  1541. #define umul_ppmm(w1, w0, u, v) \
  1542. do { \
  1543. UWtype __w1; \
  1544. UWtype __xm0 = (u), __xm1 = (v); \
  1545. smul_ppmm (__w1, w0, __xm0, __xm1); \
  1546. (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
  1547. + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
  1548. } while (0)
  1549. #endif
  1550. /* If we still don't have umul_ppmm, define it using plain C. */
  1551. #if !defined (umul_ppmm)
  1552. #define umul_ppmm(w1, w0, u, v) \
  1553. do { \
  1554. UWtype __x0, __x1, __x2, __x3; \
  1555. UHWtype __ul, __vl, __uh, __vh; \
  1556. \
  1557. __ul = __ll_lowpart (u); \
  1558. __uh = __ll_highpart (u); \
  1559. __vl = __ll_lowpart (v); \
  1560. __vh = __ll_highpart (v); \
  1561. \
  1562. __x0 = (UWtype) __ul * __vl; \
  1563. __x1 = (UWtype) __ul * __vh; \
  1564. __x2 = (UWtype) __uh * __vl; \
  1565. __x3 = (UWtype) __uh * __vh; \
  1566. \
  1567. __x1 += __ll_highpart (__x0);/* this can't give carry */ \
  1568. __x1 += __x2; /* but this indeed can */ \
  1569. if (__x1 < __x2) /* did we get it? */ \
  1570. __x3 += __ll_B; /* yes, add it in the proper pos. */ \
  1571. \
  1572. (w1) = __x3 + __ll_highpart (__x1); \
  1573. (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
  1574. } while (0)
  1575. #endif
  1576. #if !defined (__umulsidi3)
  1577. #define __umulsidi3(u, v) \
  1578. ({DWunion __w; \
  1579. umul_ppmm (__w.s.high, __w.s.low, u, v); \
  1580. __w.ll; })
  1581. #endif
  1582. /* Define this unconditionally, so it can be used for debugging. */
  1583. #define __udiv_qrnnd_c(q, r, n1, n0, d) \
  1584. do { \
  1585. UWtype __d1, __d0, __q1, __q0; \
  1586. UWtype __r1, __r0, __m; \
  1587. __d1 = __ll_highpart (d); \
  1588. __d0 = __ll_lowpart (d); \
  1589. \
  1590. __r1 = (n1) % __d1; \
  1591. __q1 = (n1) / __d1; \
  1592. __m = (UWtype) __q1 * __d0; \
  1593. __r1 = __r1 * __ll_B | __ll_highpart (n0); \
  1594. if (__r1 < __m) \
  1595. { \
  1596. __q1--, __r1 += (d); \
  1597. if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
  1598. if (__r1 < __m) \
  1599. __q1--, __r1 += (d); \
  1600. } \
  1601. __r1 -= __m; \
  1602. \
  1603. __r0 = __r1 % __d1; \
  1604. __q0 = __r1 / __d1; \
  1605. __m = (UWtype) __q0 * __d0; \
  1606. __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
  1607. if (__r0 < __m) \
  1608. { \
  1609. __q0--, __r0 += (d); \
  1610. if (__r0 >= (d)) \
  1611. if (__r0 < __m) \
  1612. __q0--, __r0 += (d); \
  1613. } \
  1614. __r0 -= __m; \
  1615. \
  1616. (q) = (UWtype) __q1 * __ll_B | __q0; \
  1617. (r) = __r0; \
  1618. } while (0)
  1619. /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
  1620. __udiv_w_sdiv (defined in libgcc or elsewhere). */
  1621. #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
  1622. #define udiv_qrnnd(q, r, nh, nl, d) \
  1623. do { \
  1624. extern UWtype __udiv_w_sdiv (UWtype *, UWtype, UWtype, UWtype); \
  1625. UWtype __r; \
  1626. (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
  1627. (r) = __r; \
  1628. } while (0)
  1629. #endif
  1630. /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
  1631. #if !defined (udiv_qrnnd)
  1632. #define UDIV_NEEDS_NORMALIZATION 1
  1633. #define udiv_qrnnd __udiv_qrnnd_c
  1634. #endif
  1635. #if !defined (count_leading_zeros)
  1636. #define count_leading_zeros(count, x) \
  1637. do { \
  1638. UWtype __xr = (x); \
  1639. UWtype __a; \
  1640. \
  1641. if (W_TYPE_SIZE <= 32) \
  1642. { \
  1643. __a = __xr < ((UWtype)1<<2*__BITS4) \
  1644. ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
  1645. : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
  1646. } \
  1647. else \
  1648. { \
  1649. for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
  1650. if (((__xr >> __a) & 0xff) != 0) \
  1651. break; \
  1652. } \
  1653. \
  1654. (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
  1655. } while (0)
  1656. #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
  1657. #endif
  1658. #if !defined (count_trailing_zeros)
  1659. /* Define count_trailing_zeros using count_leading_zeros. The latter might be
  1660. defined in asm, but if it is not, the C version above is good enough. */
  1661. #define count_trailing_zeros(count, x) \
  1662. do { \
  1663. UWtype __ctz_x = (x); \
  1664. UWtype __ctz_c; \
  1665. count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
  1666. (count) = W_TYPE_SIZE - 1 - __ctz_c; \
  1667. } while (0)
  1668. #endif
  1669. #ifndef UDIV_NEEDS_NORMALIZATION
  1670. #define UDIV_NEEDS_NORMALIZATION 0
  1671. #endif