memcpy.S 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872
  1. /* Copyright (C) 2012-2015 Free Software Foundation, Inc.
  2. This file is part of the GNU C Library.
  3. The GNU C Library is free software; you can redistribute it and/or
  4. modify it under the terms of the GNU Lesser General Public
  5. License as published by the Free Software Foundation; either
  6. version 2.1 of the License, or (at your option) any later version.
  7. The GNU C Library is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  10. Lesser General Public License for more details.
  11. You should have received a copy of the GNU Lesser General Public
  12. License along with the GNU C Library. If not, see
  13. <http://www.gnu.org/licenses/>. */
  14. #ifdef ANDROID_CHANGES
  15. # include "machine/asm.h"
  16. # include "machine/regdef.h"
  17. # define USE_MEMMOVE_FOR_OVERLAP
  18. # define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
  19. # define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
  20. #elif _LIBC
  21. # include <sysdep.h>
  22. # include <regdef.h>
  23. # include <sys/asm.h>
  24. # define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
  25. # define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
  26. #elif defined _COMPILING_NEWLIB
  27. # include "machine/asm.h"
  28. # include "machine/regdef.h"
  29. # define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
  30. # define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
  31. #else
  32. # include <regdef.h>
  33. # include <sys/asm.h>
  34. #endif
  35. #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
  36. (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
  37. # ifndef DISABLE_PREFETCH
  38. # define USE_PREFETCH
  39. # endif
  40. #endif
  41. #if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32))
  42. # ifndef DISABLE_DOUBLE
  43. # define USE_DOUBLE
  44. # endif
  45. #endif
  46. /* Some asm.h files do not have the L macro definition. */
  47. #ifndef L
  48. # if _MIPS_SIM == _ABIO32
  49. # define L(label) $L ## label
  50. # else
  51. # define L(label) .L ## label
  52. # endif
  53. #endif
  54. /* Some asm.h files do not have the PTR_ADDIU macro definition. */
  55. #ifndef PTR_ADDIU
  56. # ifdef USE_DOUBLE
  57. # define PTR_ADDIU daddiu
  58. # else
  59. # define PTR_ADDIU addiu
  60. # endif
  61. #endif
  62. /* Some asm.h files do not have the PTR_SRA macro definition. */
  63. #ifndef PTR_SRA
  64. # ifdef USE_DOUBLE
  65. # define PTR_SRA dsra
  66. # else
  67. # define PTR_SRA sra
  68. # endif
  69. #endif
  70. /* New R6 instructions that may not be in asm.h. */
  71. #ifndef PTR_LSA
  72. # if _MIPS_SIM == _ABI64
  73. # define PTR_LSA dlsa
  74. # else
  75. # define PTR_LSA lsa
  76. # endif
  77. #endif
  78. /*
  79. * Using PREFETCH_HINT_LOAD_STREAMED instead of PREFETCH_LOAD on load
  80. * prefetches appears to offer a slight preformance advantage.
  81. *
  82. * Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE
  83. * or PREFETCH_STORE_STREAMED offers a large performance advantage
  84. * but PREPAREFORSTORE has some special restrictions to consider.
  85. *
  86. * Prefetch with the 'prepare for store' hint does not copy a memory
  87. * location into the cache, it just allocates a cache line and zeros
  88. * it out. This means that if you do not write to the entire cache
  89. * line before writing it out to memory some data will get zero'ed out
  90. * when the cache line is written back to memory and data will be lost.
  91. *
  92. * Also if you are using this memcpy to copy overlapping buffers it may
  93. * not behave correctly when using the 'prepare for store' hint. If you
  94. * use the 'prepare for store' prefetch on a memory area that is in the
  95. * memcpy source (as well as the memcpy destination), then you will get
  96. * some data zero'ed out before you have a chance to read it and data will
  97. * be lost.
  98. *
  99. * If you are going to use this memcpy routine with the 'prepare for store'
  100. * prefetch you may want to set USE_MEMMOVE_FOR_OVERLAP in order to avoid
  101. * the problem of running memcpy on overlapping buffers.
  102. *
  103. * There are ifdef'ed sections of this memcpy to make sure that it does not
  104. * do prefetches on cache lines that are not going to be completely written.
  105. * This code is only needed and only used when PREFETCH_STORE_HINT is set to
  106. * PREFETCH_HINT_PREPAREFORSTORE. This code assumes that cache lines are
  107. * 32 bytes and if the cache line is larger it will not work correctly.
  108. */
  109. #ifdef USE_PREFETCH
  110. # define PREFETCH_HINT_LOAD 0
  111. # define PREFETCH_HINT_STORE 1
  112. # define PREFETCH_HINT_LOAD_STREAMED 4
  113. # define PREFETCH_HINT_STORE_STREAMED 5
  114. # define PREFETCH_HINT_LOAD_RETAINED 6
  115. # define PREFETCH_HINT_STORE_RETAINED 7
  116. # define PREFETCH_HINT_WRITEBACK_INVAL 25
  117. # define PREFETCH_HINT_PREPAREFORSTORE 30
  118. /*
  119. * If we have not picked out what hints to use at this point use the
  120. * standard load and store prefetch hints.
  121. */
  122. # ifndef PREFETCH_STORE_HINT
  123. # define PREFETCH_STORE_HINT PREFETCH_HINT_STORE
  124. # endif
  125. # ifndef PREFETCH_LOAD_HINT
  126. # define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD
  127. # endif
  128. /*
  129. * We double everything when USE_DOUBLE is true so we do 2 prefetches to
  130. * get 64 bytes in that case. The assumption is that each individual
  131. * prefetch brings in 32 bytes.
  132. */
  133. # ifdef USE_DOUBLE
  134. # define PREFETCH_CHUNK 64
  135. # define PREFETCH_FOR_LOAD(chunk, reg) \
  136. pref PREFETCH_LOAD_HINT, (chunk)*64(reg); \
  137. pref PREFETCH_LOAD_HINT, ((chunk)*64)+32(reg)
  138. # define PREFETCH_FOR_STORE(chunk, reg) \
  139. pref PREFETCH_STORE_HINT, (chunk)*64(reg); \
  140. pref PREFETCH_STORE_HINT, ((chunk)*64)+32(reg)
  141. # else
  142. # define PREFETCH_CHUNK 32
  143. # define PREFETCH_FOR_LOAD(chunk, reg) \
  144. pref PREFETCH_LOAD_HINT, (chunk)*32(reg)
  145. # define PREFETCH_FOR_STORE(chunk, reg) \
  146. pref PREFETCH_STORE_HINT, (chunk)*32(reg)
  147. # endif
  148. /* MAX_PREFETCH_SIZE is the maximum size of a prefetch, it must not be less
  149. * than PREFETCH_CHUNK, the assumed size of each prefetch. If the real size
  150. * of a prefetch is greater than MAX_PREFETCH_SIZE and the PREPAREFORSTORE
  151. * hint is used, the code will not work correctly. If PREPAREFORSTORE is not
  152. * used then MAX_PREFETCH_SIZE does not matter. */
  153. # define MAX_PREFETCH_SIZE 128
  154. /* PREFETCH_LIMIT is set based on the fact that we never use an offset greater
  155. * than 5 on a STORE prefetch and that a single prefetch can never be larger
  156. * than MAX_PREFETCH_SIZE. We add the extra 32 when USE_DOUBLE is set because
  157. * we actually do two prefetches in that case, one 32 bytes after the other. */
  158. # ifdef USE_DOUBLE
  159. # define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + 32 + MAX_PREFETCH_SIZE
  160. # else
  161. # define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + MAX_PREFETCH_SIZE
  162. # endif
  163. # if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) \
  164. && ((PREFETCH_CHUNK * 4) < MAX_PREFETCH_SIZE)
  165. /* We cannot handle this because the initial prefetches may fetch bytes that
  166. * are before the buffer being copied. We start copies with an offset
  167. * of 4 so avoid this situation when using PREPAREFORSTORE. */
  168. #error "PREFETCH_CHUNK is too large and/or MAX_PREFETCH_SIZE is too small."
  169. # endif
  170. #else /* USE_PREFETCH not defined */
  171. # define PREFETCH_FOR_LOAD(offset, reg)
  172. # define PREFETCH_FOR_STORE(offset, reg)
  173. #endif
  174. #if __mips_isa_rev > 5
  175. # if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
  176. # undef PREFETCH_STORE_HINT
  177. # define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED
  178. # endif
  179. # define R6_CODE
  180. #endif
  181. /* Allow the routine to be named something else if desired. */
  182. #ifndef MEMCPY_NAME
  183. # define MEMCPY_NAME memcpy
  184. #endif
  185. /* We use these 32/64 bit registers as temporaries to do the copying. */
  186. #define REG0 t0
  187. #define REG1 t1
  188. #define REG2 t2
  189. #define REG3 t3
  190. #if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABIO64))
  191. # define REG4 t4
  192. # define REG5 t5
  193. # define REG6 t6
  194. # define REG7 t7
  195. #else
  196. # define REG4 ta0
  197. # define REG5 ta1
  198. # define REG6 ta2
  199. # define REG7 ta3
  200. #endif
  201. /* We load/store 64 bits at a time when USE_DOUBLE is true.
  202. * The C_ prefix stands for CHUNK and is used to avoid macro name
  203. * conflicts with system header files. */
  204. #ifdef USE_DOUBLE
  205. # define C_ST sd
  206. # define C_LD ld
  207. # ifdef __MIPSEB
  208. # define C_LDHI ldl /* high part is left in big-endian */
  209. # define C_STHI sdl /* high part is left in big-endian */
  210. # define C_LDLO ldr /* low part is right in big-endian */
  211. # define C_STLO sdr /* low part is right in big-endian */
  212. # else
  213. # define C_LDHI ldr /* high part is right in little-endian */
  214. # define C_STHI sdr /* high part is right in little-endian */
  215. # define C_LDLO ldl /* low part is left in little-endian */
  216. # define C_STLO sdl /* low part is left in little-endian */
  217. # endif
  218. # define C_ALIGN dalign /* r6 align instruction */
  219. #else
  220. # define C_ST sw
  221. # define C_LD lw
  222. # ifdef __MIPSEB
  223. # define C_LDHI lwl /* high part is left in big-endian */
  224. # define C_STHI swl /* high part is left in big-endian */
  225. # define C_LDLO lwr /* low part is right in big-endian */
  226. # define C_STLO swr /* low part is right in big-endian */
  227. # else
  228. # define C_LDHI lwr /* high part is right in little-endian */
  229. # define C_STHI swr /* high part is right in little-endian */
  230. # define C_LDLO lwl /* low part is left in little-endian */
  231. # define C_STLO swl /* low part is left in little-endian */
  232. # endif
  233. # define C_ALIGN align /* r6 align instruction */
  234. #endif
  235. /* Bookkeeping values for 32 vs. 64 bit mode. */
  236. #ifdef USE_DOUBLE
  237. # define NSIZE 8
  238. # define NSIZEMASK 0x3f
  239. # define NSIZEDMASK 0x7f
  240. #else
  241. # define NSIZE 4
  242. # define NSIZEMASK 0x1f
  243. # define NSIZEDMASK 0x3f
  244. #endif
  245. #define UNIT(unit) ((unit)*NSIZE)
  246. #define UNITM1(unit) (((unit)*NSIZE)-1)
  247. #ifdef ANDROID_CHANGES
  248. LEAF(MEMCPY_NAME, 0)
  249. #else
  250. LEAF(MEMCPY_NAME)
  251. #endif
  252. .set nomips16
  253. .set noreorder
  254. /*
  255. * Below we handle the case where memcpy is called with overlapping src and dst.
  256. * Although memcpy is not required to handle this case, some parts of Android
  257. * like Skia rely on such usage. We call memmove to handle such cases.
  258. */
  259. #ifdef USE_MEMMOVE_FOR_OVERLAP
  260. PTR_SUBU t0,a0,a1
  261. PTR_SRA t2,t0,31
  262. xor t1,t0,t2
  263. PTR_SUBU t0,t1,t2
  264. sltu t2,t0,a2
  265. beq t2,zero,L(memcpy)
  266. la t9,memmove
  267. jr t9
  268. nop
  269. L(memcpy):
  270. #endif
  271. /*
  272. * If the size is less than 2*NSIZE (8 or 16), go to L(lastb). Regardless of
  273. * size, copy dst pointer to v0 for the return value.
  274. */
  275. slti t2,a2,(2 * NSIZE)
  276. bne t2,zero,L(lasts)
  277. #if defined(RETURN_FIRST_PREFETCH) || defined(RETURN_LAST_PREFETCH)
  278. move v0,zero
  279. #else
  280. move v0,a0
  281. #endif
  282. #ifndef R6_CODE
  283. /*
  284. * If src and dst have different alignments, go to L(unaligned), if they
  285. * have the same alignment (but are not actually aligned) do a partial
  286. * load/store to make them aligned. If they are both already aligned
  287. * we can start copying at L(aligned).
  288. */
  289. xor t8,a1,a0
  290. andi t8,t8,(NSIZE-1) /* t8 is a0/a1 word-displacement */
  291. bne t8,zero,L(unaligned)
  292. PTR_SUBU a3, zero, a0
  293. andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */
  294. beq a3,zero,L(aligned) /* if a3=0, it is already aligned */
  295. PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */
  296. C_LDHI t8,0(a1)
  297. PTR_ADDU a1,a1,a3
  298. C_STHI t8,0(a0)
  299. PTR_ADDU a0,a0,a3
  300. #else /* R6_CODE */
  301. /*
  302. * Align the destination and hope that the source gets aligned too. If it
  303. * doesn't we jump to L(r6_unaligned*) to do unaligned copies using the r6
  304. * align instruction.
  305. */
  306. andi t8,a0,7
  307. lapc t9,L(atable)
  308. PTR_LSA t9,t8,t9,2
  309. jrc t9
  310. L(atable):
  311. bc L(lb0)
  312. bc L(lb7)
  313. bc L(lb6)
  314. bc L(lb5)
  315. bc L(lb4)
  316. bc L(lb3)
  317. bc L(lb2)
  318. bc L(lb1)
  319. L(lb7):
  320. lb a3, 6(a1)
  321. sb a3, 6(a0)
  322. L(lb6):
  323. lb a3, 5(a1)
  324. sb a3, 5(a0)
  325. L(lb5):
  326. lb a3, 4(a1)
  327. sb a3, 4(a0)
  328. L(lb4):
  329. lb a3, 3(a1)
  330. sb a3, 3(a0)
  331. L(lb3):
  332. lb a3, 2(a1)
  333. sb a3, 2(a0)
  334. L(lb2):
  335. lb a3, 1(a1)
  336. sb a3, 1(a0)
  337. L(lb1):
  338. lb a3, 0(a1)
  339. sb a3, 0(a0)
  340. li t9,8
  341. subu t8,t9,t8
  342. PTR_SUBU a2,a2,t8
  343. PTR_ADDU a0,a0,t8
  344. PTR_ADDU a1,a1,t8
  345. L(lb0):
  346. andi t8,a1,(NSIZE-1)
  347. lapc t9,L(jtable)
  348. PTR_LSA t9,t8,t9,2
  349. jrc t9
  350. L(jtable):
  351. bc L(aligned)
  352. bc L(r6_unaligned1)
  353. bc L(r6_unaligned2)
  354. bc L(r6_unaligned3)
  355. # ifdef USE_DOUBLE
  356. bc L(r6_unaligned4)
  357. bc L(r6_unaligned5)
  358. bc L(r6_unaligned6)
  359. bc L(r6_unaligned7)
  360. # endif
  361. #endif /* R6_CODE */
  362. L(aligned):
  363. /*
  364. * Now dst/src are both aligned to (word or double word) aligned addresses
  365. * Set a2 to count how many bytes we have to copy after all the 64/128 byte
  366. * chunks are copied and a3 to the dst pointer after all the 64/128 byte
  367. * chunks have been copied. We will loop, incrementing a0 and a1 until a0
  368. * equals a3.
  369. */
  370. andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */
  371. beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */
  372. PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */
  373. PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
  374. /* When in the loop we may prefetch with the 'prepare to store' hint,
  375. * in this case the a0+x should not be past the "t0-32" address. This
  376. * means: for x=128 the last "safe" a0 address is "t0-160". Alternatively,
  377. * for x=64 the last "safe" a0 address is "t0-96" In the current version we
  378. * will use "prefetch hint,128(a0)", so "t0-160" is the limit.
  379. */
  380. #if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
  381. PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
  382. PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */
  383. #endif
  384. PREFETCH_FOR_LOAD (0, a1)
  385. PREFETCH_FOR_LOAD (1, a1)
  386. PREFETCH_FOR_LOAD (2, a1)
  387. PREFETCH_FOR_LOAD (3, a1)
  388. #if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
  389. PREFETCH_FOR_STORE (1, a0)
  390. PREFETCH_FOR_STORE (2, a0)
  391. PREFETCH_FOR_STORE (3, a0)
  392. #endif
  393. #if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH)
  394. # if PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE
  395. sltu v1,t9,a0
  396. bgtz v1,L(skip_set)
  397. nop
  398. PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
  399. L(skip_set):
  400. # else
  401. PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
  402. # endif
  403. #endif
  404. #if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH) \
  405. && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
  406. PTR_ADDIU v0,a0,(PREFETCH_CHUNK*3)
  407. # ifdef USE_DOUBLE
  408. PTR_ADDIU v0,v0,32
  409. # endif
  410. #endif
  411. L(loop16w):
  412. C_LD t0,UNIT(0)(a1)
  413. #if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
  414. sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */
  415. bgtz v1,L(skip_pref)
  416. #endif
  417. C_LD t1,UNIT(1)(a1)
  418. #ifdef R6_CODE
  419. PREFETCH_FOR_STORE (2, a0)
  420. #else
  421. PREFETCH_FOR_STORE (4, a0)
  422. PREFETCH_FOR_STORE (5, a0)
  423. #endif
  424. #if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH)
  425. PTR_ADDIU v0,a0,(PREFETCH_CHUNK*5)
  426. # ifdef USE_DOUBLE
  427. PTR_ADDIU v0,v0,32
  428. # endif
  429. #endif
  430. L(skip_pref):
  431. C_LD REG2,UNIT(2)(a1)
  432. C_LD REG3,UNIT(3)(a1)
  433. C_LD REG4,UNIT(4)(a1)
  434. C_LD REG5,UNIT(5)(a1)
  435. C_LD REG6,UNIT(6)(a1)
  436. C_LD REG7,UNIT(7)(a1)
  437. #ifdef R6_CODE
  438. PREFETCH_FOR_LOAD (3, a1)
  439. #else
  440. PREFETCH_FOR_LOAD (4, a1)
  441. #endif
  442. C_ST t0,UNIT(0)(a0)
  443. C_ST t1,UNIT(1)(a0)
  444. C_ST REG2,UNIT(2)(a0)
  445. C_ST REG3,UNIT(3)(a0)
  446. C_ST REG4,UNIT(4)(a0)
  447. C_ST REG5,UNIT(5)(a0)
  448. C_ST REG6,UNIT(6)(a0)
  449. C_ST REG7,UNIT(7)(a0)
  450. C_LD t0,UNIT(8)(a1)
  451. C_LD t1,UNIT(9)(a1)
  452. C_LD REG2,UNIT(10)(a1)
  453. C_LD REG3,UNIT(11)(a1)
  454. C_LD REG4,UNIT(12)(a1)
  455. C_LD REG5,UNIT(13)(a1)
  456. C_LD REG6,UNIT(14)(a1)
  457. C_LD REG7,UNIT(15)(a1)
  458. #ifndef R6_CODE
  459. PREFETCH_FOR_LOAD (5, a1)
  460. #endif
  461. C_ST t0,UNIT(8)(a0)
  462. C_ST t1,UNIT(9)(a0)
  463. C_ST REG2,UNIT(10)(a0)
  464. C_ST REG3,UNIT(11)(a0)
  465. C_ST REG4,UNIT(12)(a0)
  466. C_ST REG5,UNIT(13)(a0)
  467. C_ST REG6,UNIT(14)(a0)
  468. C_ST REG7,UNIT(15)(a0)
  469. PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
  470. bne a0,a3,L(loop16w)
  471. PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
  472. move a2,t8
  473. /* Here we have src and dest word-aligned but less than 64-bytes or
  474. * 128 bytes to go. Check for a 32(64) byte chunk and copy if if there
  475. * is one. Otherwise jump down to L(chk1w) to handle the tail end of
  476. * the copy.
  477. */
  478. L(chkw):
  479. PREFETCH_FOR_LOAD (0, a1)
  480. andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */
  481. /* The t8 is the reminder count past 32-bytes */
  482. beq a2,t8,L(chk1w) /* When a2=t8, no 32-byte chunk */
  483. nop
  484. C_LD t0,UNIT(0)(a1)
  485. C_LD t1,UNIT(1)(a1)
  486. C_LD REG2,UNIT(2)(a1)
  487. C_LD REG3,UNIT(3)(a1)
  488. C_LD REG4,UNIT(4)(a1)
  489. C_LD REG5,UNIT(5)(a1)
  490. C_LD REG6,UNIT(6)(a1)
  491. C_LD REG7,UNIT(7)(a1)
  492. PTR_ADDIU a1,a1,UNIT(8)
  493. C_ST t0,UNIT(0)(a0)
  494. C_ST t1,UNIT(1)(a0)
  495. C_ST REG2,UNIT(2)(a0)
  496. C_ST REG3,UNIT(3)(a0)
  497. C_ST REG4,UNIT(4)(a0)
  498. C_ST REG5,UNIT(5)(a0)
  499. C_ST REG6,UNIT(6)(a0)
  500. C_ST REG7,UNIT(7)(a0)
  501. PTR_ADDIU a0,a0,UNIT(8)
  502. /*
  503. * Here we have less than 32(64) bytes to copy. Set up for a loop to
  504. * copy one word (or double word) at a time. Set a2 to count how many
  505. * bytes we have to copy after all the word (or double word) chunks are
  506. * copied and a3 to the dst pointer after all the (d)word chunks have
  507. * been copied. We will loop, incrementing a0 and a1 until a0 equals a3.
  508. */
  509. L(chk1w):
  510. andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */
  511. beq a2,t8,L(lastw)
  512. PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */
  513. PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
  514. /* copying in words (4-byte or 8-byte chunks) */
  515. L(wordCopy_loop):
  516. C_LD REG3,UNIT(0)(a1)
  517. PTR_ADDIU a0,a0,UNIT(1)
  518. PTR_ADDIU a1,a1,UNIT(1)
  519. bne a0,a3,L(wordCopy_loop)
  520. C_ST REG3,UNIT(-1)(a0)
  521. /* If we have been copying double words, see if we can copy a single word
  522. before doing byte copies. We can have, at most, one word to copy. */
  523. L(lastw):
  524. #ifdef USE_DOUBLE
  525. andi t8,a2,3 /* a2 is the remainder past 4 byte chunks. */
  526. beq t8,a2,L(lastb)
  527. lw REG3,0(a1)
  528. sw REG3,0(a0)
  529. PTR_ADDIU a0,a0,4
  530. PTR_ADDIU a1,a1,4
  531. move a2,t8
  532. #endif
  533. /* Copy the last 8 (or 16) bytes */
  534. L(lastb):
  535. blez a2,L(leave)
  536. PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
  537. L(lastbloop):
  538. lb v1,0(a1)
  539. PTR_ADDIU a0,a0,1
  540. PTR_ADDIU a1,a1,1
  541. bne a0,a3,L(lastbloop)
  542. sb v1,-1(a0)
  543. L(leave):
  544. j ra
  545. nop
  546. /* We jump here with a memcpy of less than 8 or 16 bytes, depending on
  547. whether or not USE_DOUBLE is defined. Instead of just doing byte
  548. copies, check the alignment and size and use lw/sw if possible.
  549. Otherwise, do byte copies. */
  550. L(lasts):
  551. andi t8,a2,3
  552. beq t8,a2,L(lastb)
  553. andi t9,a0,3
  554. bne t9,zero,L(lastb)
  555. andi t9,a1,3
  556. bne t9,zero,L(lastb)
  557. PTR_SUBU a3,a2,t8
  558. PTR_ADDU a3,a0,a3
  559. L(wcopy_loop):
  560. lw REG3,0(a1)
  561. PTR_ADDIU a0,a0,4
  562. PTR_ADDIU a1,a1,4
  563. bne a0,a3,L(wcopy_loop)
  564. sw REG3,-4(a0)
  565. b L(lastb)
  566. move a2,t8
  567. #ifndef R6_CODE
  568. /*
  569. * UNALIGNED case, got here with a3 = "negu a0"
  570. * This code is nearly identical to the aligned code above
  571. * but only the destination (not the source) gets aligned
  572. * so we need to do partial loads of the source followed
  573. * by normal stores to the destination (once we have aligned
  574. * the destination).
  575. */
  576. L(unaligned):
  577. andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */
  578. beqz a3,L(ua_chk16w) /* if a3=0, it is already aligned */
  579. PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */
  580. C_LDHI v1,UNIT(0)(a1)
  581. C_LDLO v1,UNITM1(1)(a1)
  582. PTR_ADDU a1,a1,a3
  583. C_STHI v1,UNIT(0)(a0)
  584. PTR_ADDU a0,a0,a3
  585. /*
  586. * Now the destination (but not the source) is aligned
  587. * Set a2 to count how many bytes we have to copy after all the 64/128 byte
  588. * chunks are copied and a3 to the dst pointer after all the 64/128 byte
  589. * chunks have been copied. We will loop, incrementing a0 and a1 until a0
  590. * equals a3.
  591. */
  592. L(ua_chk16w):
  593. andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */
  594. beq a2,t8,L(ua_chkw) /* if a2==t8, no 64-byte/128-byte chunks */
  595. PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */
  596. PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
  597. # if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
  598. PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
  599. PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */
  600. # endif
  601. PREFETCH_FOR_LOAD (0, a1)
  602. PREFETCH_FOR_LOAD (1, a1)
  603. PREFETCH_FOR_LOAD (2, a1)
  604. # if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
  605. PREFETCH_FOR_STORE (1, a0)
  606. PREFETCH_FOR_STORE (2, a0)
  607. PREFETCH_FOR_STORE (3, a0)
  608. # endif
  609. # if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH)
  610. # if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
  611. sltu v1,t9,a0
  612. bgtz v1,L(ua_skip_set)
  613. nop
  614. PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
  615. L(ua_skip_set):
  616. # else
  617. PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
  618. # endif
  619. # endif
  620. L(ua_loop16w):
  621. PREFETCH_FOR_LOAD (3, a1)
  622. C_LDHI t0,UNIT(0)(a1)
  623. C_LDHI t1,UNIT(1)(a1)
  624. C_LDHI REG2,UNIT(2)(a1)
  625. # if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
  626. sltu v1,t9,a0
  627. bgtz v1,L(ua_skip_pref)
  628. # endif
  629. C_LDHI REG3,UNIT(3)(a1)
  630. PREFETCH_FOR_STORE (4, a0)
  631. PREFETCH_FOR_STORE (5, a0)
  632. L(ua_skip_pref):
  633. C_LDHI REG4,UNIT(4)(a1)
  634. C_LDHI REG5,UNIT(5)(a1)
  635. C_LDHI REG6,UNIT(6)(a1)
  636. C_LDHI REG7,UNIT(7)(a1)
  637. C_LDLO t0,UNITM1(1)(a1)
  638. C_LDLO t1,UNITM1(2)(a1)
  639. C_LDLO REG2,UNITM1(3)(a1)
  640. C_LDLO REG3,UNITM1(4)(a1)
  641. C_LDLO REG4,UNITM1(5)(a1)
  642. C_LDLO REG5,UNITM1(6)(a1)
  643. C_LDLO REG6,UNITM1(7)(a1)
  644. C_LDLO REG7,UNITM1(8)(a1)
  645. PREFETCH_FOR_LOAD (4, a1)
  646. C_ST t0,UNIT(0)(a0)
  647. C_ST t1,UNIT(1)(a0)
  648. C_ST REG2,UNIT(2)(a0)
  649. C_ST REG3,UNIT(3)(a0)
  650. C_ST REG4,UNIT(4)(a0)
  651. C_ST REG5,UNIT(5)(a0)
  652. C_ST REG6,UNIT(6)(a0)
  653. C_ST REG7,UNIT(7)(a0)
  654. C_LDHI t0,UNIT(8)(a1)
  655. C_LDHI t1,UNIT(9)(a1)
  656. C_LDHI REG2,UNIT(10)(a1)
  657. C_LDHI REG3,UNIT(11)(a1)
  658. C_LDHI REG4,UNIT(12)(a1)
  659. C_LDHI REG5,UNIT(13)(a1)
  660. C_LDHI REG6,UNIT(14)(a1)
  661. C_LDHI REG7,UNIT(15)(a1)
  662. C_LDLO t0,UNITM1(9)(a1)
  663. C_LDLO t1,UNITM1(10)(a1)
  664. C_LDLO REG2,UNITM1(11)(a1)
  665. C_LDLO REG3,UNITM1(12)(a1)
  666. C_LDLO REG4,UNITM1(13)(a1)
  667. C_LDLO REG5,UNITM1(14)(a1)
  668. C_LDLO REG6,UNITM1(15)(a1)
  669. C_LDLO REG7,UNITM1(16)(a1)
  670. PREFETCH_FOR_LOAD (5, a1)
  671. C_ST t0,UNIT(8)(a0)
  672. C_ST t1,UNIT(9)(a0)
  673. C_ST REG2,UNIT(10)(a0)
  674. C_ST REG3,UNIT(11)(a0)
  675. C_ST REG4,UNIT(12)(a0)
  676. C_ST REG5,UNIT(13)(a0)
  677. C_ST REG6,UNIT(14)(a0)
  678. C_ST REG7,UNIT(15)(a0)
  679. PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
  680. bne a0,a3,L(ua_loop16w)
  681. PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
  682. move a2,t8
  683. /* Here we have src and dest word-aligned but less than 64-bytes or
  684. * 128 bytes to go. Check for a 32(64) byte chunk and copy if if there
  685. * is one. Otherwise jump down to L(ua_chk1w) to handle the tail end of
  686. * the copy. */
  687. L(ua_chkw):
  688. PREFETCH_FOR_LOAD (0, a1)
  689. andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */
  690. /* t8 is the reminder count past 32-bytes */
  691. beq a2,t8,L(ua_chk1w) /* When a2=t8, no 32-byte chunk */
  692. nop
  693. C_LDHI t0,UNIT(0)(a1)
  694. C_LDHI t1,UNIT(1)(a1)
  695. C_LDHI REG2,UNIT(2)(a1)
  696. C_LDHI REG3,UNIT(3)(a1)
  697. C_LDHI REG4,UNIT(4)(a1)
  698. C_LDHI REG5,UNIT(5)(a1)
  699. C_LDHI REG6,UNIT(6)(a1)
  700. C_LDHI REG7,UNIT(7)(a1)
  701. C_LDLO t0,UNITM1(1)(a1)
  702. C_LDLO t1,UNITM1(2)(a1)
  703. C_LDLO REG2,UNITM1(3)(a1)
  704. C_LDLO REG3,UNITM1(4)(a1)
  705. C_LDLO REG4,UNITM1(5)(a1)
  706. C_LDLO REG5,UNITM1(6)(a1)
  707. C_LDLO REG6,UNITM1(7)(a1)
  708. C_LDLO REG7,UNITM1(8)(a1)
  709. PTR_ADDIU a1,a1,UNIT(8)
  710. C_ST t0,UNIT(0)(a0)
  711. C_ST t1,UNIT(1)(a0)
  712. C_ST REG2,UNIT(2)(a0)
  713. C_ST REG3,UNIT(3)(a0)
  714. C_ST REG4,UNIT(4)(a0)
  715. C_ST REG5,UNIT(5)(a0)
  716. C_ST REG6,UNIT(6)(a0)
  717. C_ST REG7,UNIT(7)(a0)
  718. PTR_ADDIU a0,a0,UNIT(8)
  719. /*
  720. * Here we have less than 32(64) bytes to copy. Set up for a loop to
  721. * copy one word (or double word) at a time.
  722. */
  723. L(ua_chk1w):
  724. andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */
  725. beq a2,t8,L(ua_smallCopy)
  726. PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */
  727. PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
  728. /* copying in words (4-byte or 8-byte chunks) */
  729. L(ua_wordCopy_loop):
  730. C_LDHI v1,UNIT(0)(a1)
  731. C_LDLO v1,UNITM1(1)(a1)
  732. PTR_ADDIU a0,a0,UNIT(1)
  733. PTR_ADDIU a1,a1,UNIT(1)
  734. bne a0,a3,L(ua_wordCopy_loop)
  735. C_ST v1,UNIT(-1)(a0)
  736. /* Copy the last 8 (or 16) bytes */
  737. L(ua_smallCopy):
  738. beqz a2,L(leave)
  739. PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
  740. L(ua_smallCopy_loop):
  741. lb v1,0(a1)
  742. PTR_ADDIU a0,a0,1
  743. PTR_ADDIU a1,a1,1
  744. bne a0,a3,L(ua_smallCopy_loop)
  745. sb v1,-1(a0)
  746. j ra
  747. nop
  748. #else /* R6_CODE */
  749. # ifdef __MIPSEB
  750. # define SWAP_REGS(X,Y) X, Y
  751. # define ALIGN_OFFSET(N) (N)
  752. # else
  753. # define SWAP_REGS(X,Y) Y, X
  754. # define ALIGN_OFFSET(N) (NSIZE-N)
  755. # endif
  756. # define R6_UNALIGNED_WORD_COPY(BYTEOFFSET) \
  757. andi REG7, a2, (NSIZE-1);/* REG7 is # of bytes to by bytes. */ \
  758. beq REG7, a2, L(lastb); /* Check for bytes to copy by word */ \
  759. PTR_SUBU a3, a2, REG7; /* a3 is number of bytes to be copied in */ \
  760. /* (d)word chunks. */ \
  761. move a2, REG7; /* a2 is # of bytes to copy byte by byte */ \
  762. /* after word loop is finished. */ \
  763. PTR_ADDU REG6, a0, a3; /* REG6 is the dst address after loop. */ \
  764. PTR_SUBU REG2, a1, t8; /* REG2 is the aligned src address. */ \
  765. PTR_ADDU a1, a1, a3; /* a1 is addr of source after word loop. */ \
  766. C_LD t0, UNIT(0)(REG2); /* Load first part of source. */ \
  767. L(r6_ua_wordcopy##BYTEOFFSET): \
  768. C_LD t1, UNIT(1)(REG2); /* Load second part of source. */ \
  769. C_ALIGN REG3, SWAP_REGS(t1,t0), ALIGN_OFFSET(BYTEOFFSET); \
  770. PTR_ADDIU a0, a0, UNIT(1); /* Increment destination pointer. */ \
  771. PTR_ADDIU REG2, REG2, UNIT(1); /* Increment aligned source pointer.*/ \
  772. move t0, t1; /* Move second part of source to first. */ \
  773. bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \
  774. C_ST REG3, UNIT(-1)(a0); \
  775. j L(lastb); \
  776. nop
  777. /* We are generating R6 code, the destination is 4 byte aligned and
  778. the source is not 4 byte aligned. t8 is 1, 2, or 3 depending on the
  779. alignment of the source. */
  780. L(r6_unaligned1):
  781. R6_UNALIGNED_WORD_COPY(1)
  782. L(r6_unaligned2):
  783. R6_UNALIGNED_WORD_COPY(2)
  784. L(r6_unaligned3):
  785. R6_UNALIGNED_WORD_COPY(3)
  786. # ifdef USE_DOUBLE
  787. L(r6_unaligned4):
  788. R6_UNALIGNED_WORD_COPY(4)
  789. L(r6_unaligned5):
  790. R6_UNALIGNED_WORD_COPY(5)
  791. L(r6_unaligned6):
  792. R6_UNALIGNED_WORD_COPY(6)
  793. L(r6_unaligned7):
  794. R6_UNALIGNED_WORD_COPY(7)
  795. # endif
  796. #endif /* R6_CODE */
  797. .set at
  798. .set reorder
  799. END(MEMCPY_NAME)
  800. #ifndef ANDROID_CHANGES
  801. # ifdef _LIBC
  802. # ifdef __UCLIBC__
  803. libc_hidden_def(MEMCPY_NAME)
  804. # else
  805. libc_hidden_builtin_def (MEMCPY_NAME)
  806. # endif
  807. # endif
  808. #endif