asm.h 12 KB

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  1. /* Copyright (C) 1997, 1998, 2002, 2003 Free Software Foundation, Inc.
  2. This file is part of the GNU C Library.
  3. Contributed by Ralf Baechle <ralf@gnu.org>.
  4. The GNU C Library is free software; you can redistribute it and/or
  5. modify it under the terms of the GNU Lesser General Public
  6. License as published by the Free Software Foundation; either
  7. version 2.1 of the License, or (at your option) any later version.
  8. The GNU C Library is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. Lesser General Public License for more details.
  12. You should have received a copy of the GNU Lesser General Public
  13. License along with the GNU C Library; if not, see
  14. <http://www.gnu.org/licenses/>. */
  15. #ifndef _SYS_ASM_H
  16. #define _SYS_ASM_H
  17. #include <sgidefs.h>
  18. #ifndef CAT
  19. # ifdef __STDC__
  20. # define __CAT(str1,str2) str1##str2
  21. # else
  22. # define __CAT(str1,str2) str1/**/str2
  23. # endif
  24. # define CAT(str1,str2) __CAT(str1,str2)
  25. #endif
  26. /*
  27. * Macros to handle different pointer/register sizes for 32/64-bit code
  28. *
  29. * 64 bit address space isn't used yet, so we may use the R3000 32 bit
  30. * defines for now.
  31. */
  32. #if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
  33. # define PTR .word
  34. # define PTRSIZE 4
  35. # define PTRLOG 2
  36. #elif (_MIPS_SIM == _MIPS_SIM_ABI64)
  37. # define PTR .dword
  38. # define PTRSIZE 8
  39. # define PTRLOG 3
  40. #endif
  41. /*
  42. * PIC specific declarations
  43. */
  44. #if (_MIPS_SIM == _MIPS_SIM_ABI32)
  45. # ifdef __PIC__
  46. # define CPRESTORE(register) \
  47. .cprestore register
  48. # define CPLOAD(register) \
  49. .cpload register
  50. # else
  51. # define CPRESTORE(register)
  52. # define CPLOAD(register)
  53. # endif
  54. # define CPADD(register) \
  55. .cpadd register
  56. /*
  57. * Set gp when at 1st instruction
  58. */
  59. # define SETUP_GP \
  60. .set noreorder; \
  61. .cpload $25; \
  62. .set reorder
  63. /* Set gp when not at 1st instruction */
  64. # define SETUP_GPX(r) \
  65. .set noreorder; \
  66. move r, $31; /* Save old ra. */ \
  67. bal 10f; /* Find addr of cpload. */ \
  68. nop; \
  69. 10: \
  70. .cpload $31; \
  71. move $31, r; \
  72. .set reorder
  73. # define SETUP_GPX_L(r, l) \
  74. .set noreorder; \
  75. move r, $31; /* Save old ra. */ \
  76. bal l; /* Find addr of cpload. */ \
  77. nop; \
  78. l: \
  79. .cpload $31; \
  80. move $31, r; \
  81. .set reorder
  82. # define SAVE_GP(x) \
  83. .cprestore x /* Save gp trigger t9/jalr conversion. */
  84. # define SETUP_GP64(a, b)
  85. # define SETUP_GPX64(a, b)
  86. # define SETUP_GPX64_L(cp_reg, ra_save, l)
  87. # define RESTORE_GP64
  88. # define USE_ALT_CP(a)
  89. # define L(label) $L ## label
  90. #else /* (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32) */
  91. /*
  92. * For callee-saved gp calling convention:
  93. */
  94. # define SETUP_GP
  95. # define SETUP_GPX(r)
  96. # define SETUP_GPX_L(r, l)
  97. # define SAVE_GP(x)
  98. # define SETUP_GP64(gpoffset, proc) \
  99. .cpsetup $25, gpoffset, proc
  100. # define SETUP_GPX64(cp_reg, ra_save) \
  101. move ra_save, $31; /* Save old ra. */ \
  102. .set noreorder; \
  103. bal 10f; /* Find addr of .cpsetup. */ \
  104. nop; \
  105. 10: \
  106. .set reorder; \
  107. .cpsetup $31, cp_reg, 10b; \
  108. move $31, ra_save
  109. # define SETUP_GPX64_L(cp_reg, ra_save, l) \
  110. move ra_save, $31; /* Save old ra. */ \
  111. .set noreorder; \
  112. bal l; /* Find addr of .cpsetup. */ \
  113. nop; \
  114. l: \
  115. .set reorder; \
  116. .cpsetup $31, cp_reg, l; \
  117. move $31, ra_save
  118. # define RESTORE_GP64 \
  119. .cpreturn
  120. /* Use alternate register for context pointer. */
  121. # define USE_ALT_CP(reg) \
  122. .cplocal reg
  123. # define L(label) .L ## label
  124. #endif /* _MIPS_SIM != _MIPS_SIM_ABI32 */
  125. /*
  126. * Stack Frame Definitions
  127. */
  128. #if (_MIPS_SIM == _MIPS_SIM_ABI32)
  129. # define NARGSAVE 4 /* Space for 4 argument registers must be allocated. */
  130. #endif
  131. #if (_MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32)
  132. # define NARGSAVE 0 /* No caller responsibilities. */
  133. #endif
  134. /*
  135. * LEAF - declare leaf routine
  136. */
  137. #define LEAF(symbol) \
  138. .globl symbol; \
  139. .align 2; \
  140. .type symbol,@function; \
  141. .ent symbol,0; \
  142. symbol: .frame sp,0,ra
  143. /*
  144. * NESTED - declare nested routine entry point
  145. */
  146. #define NESTED(symbol, framesize, rpc) \
  147. .globl symbol; \
  148. .align 2; \
  149. .type symbol,@function; \
  150. .ent symbol,0; \
  151. symbol: .frame sp, framesize, rpc
  152. /*
  153. * END - mark end of function
  154. */
  155. #ifndef END
  156. # define END(function) \
  157. .end function; \
  158. .size function,.-function
  159. #endif
  160. /*
  161. * EXPORT - export definition of symbol
  162. */
  163. #define EXPORT(symbol) \
  164. .globl symbol; \
  165. symbol:
  166. /*
  167. * ABS - export absolute symbol
  168. */
  169. #define ABS(symbol,value) \
  170. .globl symbol; \
  171. symbol = value
  172. #define PANIC(msg) \
  173. .set push; \
  174. .set reorder; \
  175. la a0,8f; \
  176. jal panic; \
  177. 9: b 9b; \
  178. .set pop; \
  179. TEXT(msg)
  180. /*
  181. * Print formated string
  182. */
  183. #define PRINT(string) \
  184. .set push; \
  185. .set reorder; \
  186. la a0,8f; \
  187. jal printk; \
  188. .set pop; \
  189. TEXT(string)
  190. #define TEXT(msg) \
  191. .data; \
  192. 8: .asciiz msg; \
  193. .previous;
  194. /*
  195. * Build text tables
  196. */
  197. #define TTABLE(string) \
  198. .text; \
  199. .word 1f; \
  200. .previous; \
  201. .data; \
  202. 1: .asciz string; \
  203. .previous
  204. /*
  205. * MIPS IV pref instruction.
  206. * Use with .set noreorder only!
  207. *
  208. * MIPS IV implementations are free to treat this as a nop. The R5000
  209. * is one of them. So we should have an option not to use this instruction.
  210. */
  211. #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
  212. (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
  213. # define PREF(hint,addr) \
  214. pref hint,addr
  215. # define PREFX(hint,addr) \
  216. prefx hint,addr
  217. #else
  218. # define PREF
  219. # define PREFX
  220. #endif
  221. /*
  222. * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
  223. */
  224. #if _MIPS_ISA == _MIPS_ISA_MIPS1
  225. # define MOVN(rd,rs,rt) \
  226. .set push; \
  227. .set reorder; \
  228. beqz rt,9f; \
  229. move rd,rs; \
  230. .set pop; \
  231. 9:
  232. # define MOVZ(rd,rs,rt) \
  233. .set push; \
  234. .set reorder; \
  235. bnez rt,9f; \
  236. move rd,rt; \
  237. .set pop; \
  238. 9:
  239. #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
  240. #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
  241. # define MOVN(rd,rs,rt) \
  242. .set push; \
  243. .set noreorder; \
  244. bnezl rt,9f; \
  245. move rd,rs; \
  246. .set pop; \
  247. 9:
  248. # define MOVZ(rd,rs,rt) \
  249. .set push; \
  250. .set noreorder; \
  251. beqzl rt,9f; \
  252. movz rd,rs; \
  253. .set pop; \
  254. 9:
  255. #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
  256. #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
  257. (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
  258. # define MOVN(rd,rs,rt) \
  259. movn rd,rs,rt
  260. # define MOVZ(rd,rs,rt) \
  261. movz rd,rs,rt
  262. #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
  263. /*
  264. * Stack alignment
  265. */
  266. #if (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32)
  267. # define ALSZ 15
  268. # define ALMASK ~15
  269. #else
  270. # define ALSZ 7
  271. # define ALMASK ~7
  272. #endif
  273. /*
  274. * Size of a register
  275. */
  276. #if (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32)
  277. # define SZREG 8
  278. #else
  279. # define SZREG 4
  280. #endif
  281. /*
  282. * Use the following macros in assemblercode to load/store registers,
  283. * pointers etc.
  284. */
  285. #if (SZREG == 4)
  286. # define REG_S sw
  287. # define REG_L lw
  288. #else
  289. # define REG_S sd
  290. # define REG_L ld
  291. #endif
  292. /*
  293. * How to add/sub/load/store/shift C int variables.
  294. */
  295. #if (_MIPS_SZINT == 32)
  296. # define INT_ADD add
  297. # define INT_ADDI addi
  298. # define INT_ADDU addu
  299. # define INT_ADDIU addiu
  300. # define INT_SUB sub
  301. # define INT_SUBI subi
  302. # define INT_SUBU subu
  303. # define INT_SUBIU subu
  304. # define INT_L lw
  305. # define INT_S sw
  306. #endif
  307. #if (_MIPS_SZINT == 64)
  308. # define INT_ADD dadd
  309. # define INT_ADDI daddi
  310. # define INT_ADDU daddu
  311. # define INT_ADDIU daddiu
  312. # define INT_SUB dsub
  313. # define INT_SUBI dsubi
  314. # define INT_SUBU dsubu
  315. # define INT_SUBIU dsubu
  316. # define INT_L ld
  317. # define INT_S sd
  318. #endif
  319. /*
  320. * How to add/sub/load/store/shift C long variables.
  321. */
  322. #if (_MIPS_SZLONG == 32)
  323. # define LONG_ADD add
  324. # define LONG_ADDI addi
  325. # define LONG_ADDU addu
  326. # define LONG_ADDIU addiu
  327. # define LONG_SUB sub
  328. # define LONG_SUBI subi
  329. # define LONG_SUBU subu
  330. # define LONG_SUBIU subu
  331. # define LONG_L lw
  332. # define LONG_S sw
  333. # define LONG_SLL sll
  334. # define LONG_SLLV sllv
  335. # define LONG_SRL srl
  336. # define LONG_SRLV srlv
  337. # define LONG_SRA sra
  338. # define LONG_SRAV srav
  339. #endif
  340. #if (_MIPS_SZLONG == 64)
  341. # define LONG_ADD dadd
  342. # define LONG_ADDI daddi
  343. # define LONG_ADDU daddu
  344. # define LONG_ADDIU daddiu
  345. # define LONG_SUB dsub
  346. # define LONG_SUBI dsubi
  347. # define LONG_SUBU dsubu
  348. # define LONG_SUBIU dsubu
  349. # define LONG_L ld
  350. # define LONG_S sd
  351. # define LONG_SLL dsll
  352. # define LONG_SLLV dsllv
  353. # define LONG_SRL dsrl
  354. # define LONG_SRLV dsrlv
  355. # define LONG_SRA dsra
  356. # define LONG_SRAV dsrav
  357. #endif
  358. /*
  359. * How to add/sub/load/store/shift pointers.
  360. */
  361. #if (_MIPS_SIM == _MIPS_SIM_ABI32 && _MIPS_SZPTR == 32)
  362. # define PTR_ADD add
  363. # define PTR_ADDI addi
  364. # define PTR_ADDU addu
  365. # define PTR_ADDIU addiu
  366. # define PTR_SUB sub
  367. # define PTR_SUBI subi
  368. # define PTR_SUBU subu
  369. # define PTR_SUBIU subu
  370. # define PTR_L lw
  371. # define PTR_LA la
  372. # define PTR_S sw
  373. # define PTR_SLL sll
  374. # define PTR_SLLV sllv
  375. # define PTR_SRL srl
  376. # define PTR_SRLV srlv
  377. # define PTR_SRA sra
  378. # define PTR_SRAV srav
  379. # define PTR_SCALESHIFT 2
  380. #endif
  381. #if _MIPS_SIM == _MIPS_SIM_NABI32
  382. # define PTR_ADD add
  383. # define PTR_ADDI addi
  384. # define PTR_ADDU add /* no u */
  385. # define PTR_ADDIU addi /* no u */
  386. # define PTR_SUB sub
  387. # define PTR_SUBI subi
  388. # define PTR_SUBU sub /* no u */
  389. # define PTR_SUBIU sub /* no u */
  390. # define PTR_L lw
  391. # define PTR_LA la
  392. # define PTR_S sw
  393. # define PTR_SLL sll
  394. # define PTR_SLLV sllv
  395. # define PTR_SRL srl
  396. # define PTR_SRLV srlv
  397. # define PTR_SRA sra
  398. # define PTR_SRAV srav
  399. # define PTR_SCALESHIFT 2
  400. #endif
  401. #if (_MIPS_SIM == _MIPS_SIM_ABI32 && _MIPS_SZPTR == 64 /* o64??? */) \
  402. || _MIPS_SIM == _MIPS_SIM_ABI64
  403. # define PTR_ADD dadd
  404. # define PTR_ADDI daddi
  405. # define PTR_ADDU daddu
  406. # define PTR_ADDIU daddiu
  407. # define PTR_SUB dsub
  408. # define PTR_SUBI dsubi
  409. # define PTR_SUBU dsubu
  410. # define PTR_SUBIU dsubu
  411. # define PTR_L ld
  412. # define PTR_LA dla
  413. # define PTR_S sd
  414. # define PTR_SLL dsll
  415. # define PTR_SLLV dsllv
  416. # define PTR_SRL dsrl
  417. # define PTR_SRLV dsrlv
  418. # define PTR_SRA dsra
  419. # define PTR_SRAV dsrav
  420. # define PTR_SCALESHIFT 3
  421. #endif
  422. /*
  423. * Some cp0 registers were extended to 64bit for MIPS III.
  424. */
  425. #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
  426. (_MIPS_ISA == _MIPS_ISA_MIPS32)
  427. # define MFC0 mfc0
  428. # define MTC0 mtc0
  429. #endif
  430. #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
  431. (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
  432. # define MFC0 dmfc0
  433. # define MTC0 dmtc0
  434. #endif
  435. /* The MIPS archtectures do not have a uniform memory model. Particular
  436. platforms may provide additional guarantees - for instance, the R4000
  437. LL and SC instructions implicitly perform a SYNC, and the 4K promises
  438. strong ordering.
  439. However, in the absence of those guarantees, we must assume weak ordering
  440. and SYNC explicitly where necessary.
  441. Some obsolete MIPS processors may not support the SYNC instruction. This
  442. applies to "true" MIPS I processors; most of the processors which compile
  443. using MIPS I implement parts of MIPS II. */
  444. #ifndef MIPS_SYNC
  445. # define MIPS_SYNC sync
  446. #endif
  447. #endif /* sys/asm.h */