sfp-machine.h 6.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214
  1. /* Machine-dependent software floating-point definitions.
  2. Sparc userland (_Q_*) version.
  3. Copyright (C) 1997,1998,1999, 2002, 2006 Free Software Foundation, Inc.
  4. This file is part of the GNU C Library.
  5. Contributed by Richard Henderson (rth@cygnus.com),
  6. Jakub Jelinek (jj@ultra.linux.cz) and
  7. David S. Miller (davem@redhat.com).
  8. The GNU C Library is free software; you can redistribute it and/or
  9. modify it under the terms of the GNU Lesser General Public
  10. License as published by the Free Software Foundation; either
  11. version 2.1 of the License, or (at your option) any later version.
  12. The GNU C Library is distributed in the hope that it will be useful,
  13. but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. Lesser General Public License for more details.
  16. You should have received a copy of the GNU Lesser General Public
  17. License along with the GNU C Library; if not, see
  18. <http://www.gnu.org/licenses/>. */
  19. #include <fpu_control.h>
  20. #include <stdlib.h>
  21. #define _FP_W_TYPE_SIZE 32
  22. #define _FP_W_TYPE unsigned long
  23. #define _FP_WS_TYPE signed long
  24. #define _FP_I_TYPE long
  25. #define _FP_MUL_MEAT_S(R,X,Y) \
  26. _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
  27. #define _FP_MUL_MEAT_D(R,X,Y) \
  28. _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
  29. #define _FP_MUL_MEAT_Q(R,X,Y) \
  30. _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
  31. #define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
  32. #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
  33. #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
  34. #define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
  35. #define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
  36. #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
  37. #define _FP_NANSIGN_S 0
  38. #define _FP_NANSIGN_D 0
  39. #define _FP_NANSIGN_Q 0
  40. #define _FP_KEEPNANFRACP 1
  41. /* If one NaN is signaling and the other is not,
  42. * we choose that one, otherwise we choose X.
  43. */
  44. /* For _Qp_* and _Q_*, this should prefer X, for
  45. * CPU instruction emulation this should prefer Y.
  46. * (see SPAMv9 B.2.2 section).
  47. */
  48. #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
  49. do { \
  50. if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
  51. && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
  52. { \
  53. R##_s = Y##_s; \
  54. _FP_FRAC_COPY_##wc(R,Y); \
  55. } \
  56. else \
  57. { \
  58. R##_s = X##_s; \
  59. _FP_FRAC_COPY_##wc(R,X); \
  60. } \
  61. R##_c = FP_CLS_NAN; \
  62. } while (0)
  63. /* Some assembly to speed things up. */
  64. #define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
  65. __asm__ ("addcc %r7,%8,%2\n\
  66. addxcc %r5,%6,%1\n\
  67. addx %r3,%4,%0" \
  68. : "=r" ((USItype)(r2)), \
  69. "=&r" ((USItype)(r1)), \
  70. "=&r" ((USItype)(r0)) \
  71. : "%rJ" ((USItype)(x2)), \
  72. "rI" ((USItype)(y2)), \
  73. "%rJ" ((USItype)(x1)), \
  74. "rI" ((USItype)(y1)), \
  75. "%rJ" ((USItype)(x0)), \
  76. "rI" ((USItype)(y0)) \
  77. : "cc")
  78. #define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
  79. __asm__ ("subcc %r7,%8,%2\n\
  80. subxcc %r5,%6,%1\n\
  81. subx %r3,%4,%0" \
  82. : "=r" ((USItype)(r2)), \
  83. "=&r" ((USItype)(r1)), \
  84. "=&r" ((USItype)(r0)) \
  85. : "%rJ" ((USItype)(x2)), \
  86. "rI" ((USItype)(y2)), \
  87. "%rJ" ((USItype)(x1)), \
  88. "rI" ((USItype)(y1)), \
  89. "%rJ" ((USItype)(x0)), \
  90. "rI" ((USItype)(y0)) \
  91. : "cc")
  92. #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
  93. do { \
  94. /* We need to fool gcc, as we need to pass more than 10 \
  95. input/outputs. */ \
  96. register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
  97. __asm__ __volatile__ ("\
  98. addcc %r8,%9,%1\n\
  99. addxcc %r6,%7,%0\n\
  100. addxcc %r4,%5,%%g2\n\
  101. addx %r2,%3,%%g1" \
  102. : "=&r" ((USItype)(r1)), \
  103. "=&r" ((USItype)(r0)) \
  104. : "%rJ" ((USItype)(x3)), \
  105. "rI" ((USItype)(y3)), \
  106. "%rJ" ((USItype)(x2)), \
  107. "rI" ((USItype)(y2)), \
  108. "%rJ" ((USItype)(x1)), \
  109. "rI" ((USItype)(y1)), \
  110. "%rJ" ((USItype)(x0)), \
  111. "rI" ((USItype)(y0)) \
  112. : "cc", "g1", "g2"); \
  113. __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
  114. r3 = _t1; r2 = _t2; \
  115. } while (0)
  116. #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
  117. do { \
  118. /* We need to fool gcc, as we need to pass more than 10 \
  119. input/outputs. */ \
  120. register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
  121. __asm__ __volatile__ ("\
  122. subcc %r8,%9,%1\n\
  123. subxcc %r6,%7,%0\n\
  124. subxcc %r4,%5,%%g2\n\
  125. subx %r2,%3,%%g1" \
  126. : "=&r" ((USItype)(r1)), \
  127. "=&r" ((USItype)(r0)) \
  128. : "%rJ" ((USItype)(x3)), \
  129. "rI" ((USItype)(y3)), \
  130. "%rJ" ((USItype)(x2)), \
  131. "rI" ((USItype)(y2)), \
  132. "%rJ" ((USItype)(x1)), \
  133. "rI" ((USItype)(y1)), \
  134. "%rJ" ((USItype)(x0)), \
  135. "rI" ((USItype)(y0)) \
  136. : "cc", "g1", "g2"); \
  137. __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
  138. r3 = _t1; r2 = _t2; \
  139. } while (0)
  140. #define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
  141. #define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
  142. #define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
  143. __asm__ ("addcc %3,%4,%3\n\
  144. addxcc %2,%%g0,%2\n\
  145. addxcc %1,%%g0,%1\n\
  146. addx %0,%%g0,%0" \
  147. : "=&r" ((USItype)(x3)), \
  148. "=&r" ((USItype)(x2)), \
  149. "=&r" ((USItype)(x1)), \
  150. "=&r" ((USItype)(x0)) \
  151. : "rI" ((USItype)(i)), \
  152. "0" ((USItype)(x3)), \
  153. "1" ((USItype)(x2)), \
  154. "2" ((USItype)(x1)), \
  155. "3" ((USItype)(x0)) \
  156. : "cc")
  157. /* Obtain the current rounding mode. */
  158. #ifndef FP_ROUNDMODE
  159. #define FP_ROUNDMODE ((_fcw >> 30) & 0x3)
  160. #endif
  161. /* Exception flags. */
  162. #define FP_EX_INVALID (1 << 4)
  163. #define FP_EX_OVERFLOW (1 << 3)
  164. #define FP_EX_UNDERFLOW (1 << 2)
  165. #define FP_EX_DIVZERO (1 << 1)
  166. #define FP_EX_INEXACT (1 << 0)
  167. #define _FP_DECL_EX fpu_control_t _fcw
  168. #ifdef __UCLIBC_HAS_FPU__
  169. #define FP_INIT_ROUNDMODE \
  170. do { \
  171. _FPU_GETCW(_fcw); \
  172. } while (0)
  173. /* Simulate exceptions using double arithmetics. */
  174. extern double ___Q_simulate_exceptions(int exc);
  175. #define FP_HANDLE_EXCEPTIONS \
  176. do { \
  177. if (!_fex) \
  178. { \
  179. /* This is the common case, so we do it inline. \
  180. * We need to clear cexc bits if any. \
  181. */ \
  182. extern unsigned long long ___Q_numbers[]; \
  183. __asm__ __volatile__("\
  184. ldd [%0], %%f30\n\
  185. faddd %%f30, %%f30, %%f30\
  186. " : : "r" (___Q_numbers) : "f30"); \
  187. } \
  188. else \
  189. ___Q_simulate_exceptions (_fex); \
  190. } while (0)
  191. #endif