fpu_control.h 6.4 KB

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  1. /* FPU control word definitions. ARM version.
  2. Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
  3. This file is part of the GNU C Library.
  4. The GNU C Library is free software; you can redistribute it and/or
  5. modify it under the terms of the GNU Lesser General Public
  6. License as published by the Free Software Foundation; either
  7. version 2.1 of the License, or (at your option) any later version.
  8. The GNU C Library is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. Lesser General Public License for more details.
  12. You should have received a copy of the GNU Lesser General Public
  13. License along with the GNU C Library; if not, write to the Free
  14. Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  15. 02111-1307 USA. */
  16. #ifndef _FPU_CONTROL_H
  17. #define _FPU_CONTROL_H
  18. #ifdef __VFP_FP__
  19. /* masking of interrupts */
  20. #define _FPU_MASK_IM 0x00000100 /* invalid operation */
  21. #define _FPU_MASK_ZM 0x00000200 /* divide by zero */
  22. #define _FPU_MASK_OM 0x00000400 /* overflow */
  23. #define _FPU_MASK_UM 0x00000800 /* underflow */
  24. #define _FPU_MASK_PM 0x00001000 /* inexact */
  25. /* Some bits in the FPSCR are not yet defined. They must be preserved when
  26. modifying the contents. */
  27. #define _FPU_RESERVED 0x0e08e0e0
  28. #define _FPU_DEFAULT 0x00000000
  29. /* Default + exceptions enabled. */
  30. #define _FPU_IEEE (_FPU_DEFAULT | 0x00001f00)
  31. /* Type of the control word. */
  32. typedef unsigned int fpu_control_t;
  33. /* Macros for accessing the hardware control word. */
  34. /* This is fmrx %0, fpscr. */
  35. #define _FPU_GETCW(cw) \
  36. __asm__ __volatile__ ("mrc p10, 7, %0, cr1, cr0, 0" : "=r" (cw))
  37. /* This is fmxr fpscr, %0. */
  38. #define _FPU_SETCW(cw) \
  39. __asm__ __volatile__ ("mcr p10, 7, %0, cr1, cr0, 0" : : "r" (cw))
  40. #elif defined __MAVERICK__
  41. /* DSPSC register: (from EP9312 User's Guide)
  42. *
  43. * bits 31..29 - DAID
  44. * bits 28..26 - HVID
  45. * bits 25..24 - RSVD
  46. * bit 23 - ISAT
  47. * bit 22 - UI
  48. * bit 21 - INT
  49. * bit 20 - AEXC
  50. * bits 19..18 - SAT
  51. * bits 17..16 - FCC
  52. * bit 15 - V
  53. * bit 14 - FWDEN
  54. * bit 13 - Invalid
  55. * bit 12 - Denorm
  56. * bits 11..10 - RM
  57. * bits 9..5 - IXE, UFE, OFE, RSVD, IOE
  58. * bits 4..0 - IX, UF, OF, RSVD, IO
  59. */
  60. /* masking of interrupts */
  61. #define _FPU_MASK_IM (1 << 5) /* invalid operation */
  62. #define _FPU_MASK_ZM 0 /* divide by zero */
  63. #define _FPU_MASK_OM (1 << 7) /* overflow */
  64. #define _FPU_MASK_UM (1 << 8) /* underflow */
  65. #define _FPU_MASK_PM (1 << 9) /* inexact */
  66. #define _FPU_MASK_DM 0 /* denormalized operation */
  67. #define _FPU_RESERVED 0xfffff000 /* These bits are reserved. */
  68. #define _FPU_DEFAULT 0x00b00000 /* Default value. */
  69. #define _FPU_IEEE 0x00b003a0 /* Default + exceptions enabled. */
  70. /* Type of the control word. */
  71. typedef unsigned int fpu_control_t;
  72. /* Macros for accessing the hardware control word. */
  73. #define _FPU_GETCW(cw) ({ \
  74. register int __t1, __t2; \
  75. \
  76. __asm__ volatile ( \
  77. "cfmvr64l %1, mvdx0\n\t" \
  78. "cfmvr64h %2, mvdx0\n\t" \
  79. "cfmv32sc mvdx0, dspsc\n\t" \
  80. "cfmvr64l %0, mvdx0\n\t" \
  81. "cfmv64lr mvdx0, %1\n\t" \
  82. "cfmv64hr mvdx0, %2" \
  83. : "=r" (cw), "=r" (__t1), "=r" (__t2) \
  84. ); \
  85. })
  86. #define _FPU_SETCW(cw) ({ \
  87. register int __t0, __t1, __t2; \
  88. \
  89. __asm__ volatile ( \
  90. "cfmvr64l %1, mvdx0\n\t" \
  91. "cfmvr64h %2, mvdx0\n\t" \
  92. "cfmv64lr mvdx0, %0\n\t" \
  93. "cfmvsc32 dspsc, mvdx0\n\t" \
  94. "cfmv64lr mvdx0, %1\n\t" \
  95. "cfmv64hr mvdx0, %2" \
  96. : "=r" (__t0), "=r" (__t1), "=r" (__t2) \
  97. : "0" (cw) \
  98. ); \
  99. })
  100. #else /* !__MAVERICK__ */
  101. /* We have a slight terminology confusion here. On the ARM, the register
  102. * we're interested in is actually the FPU status word - the FPU control
  103. * word is something different (which is implementation-defined and only
  104. * accessible from supervisor mode.)
  105. *
  106. * The FPSR looks like this:
  107. *
  108. * 31-24 23-16 15-8 7-0
  109. * | system ID | trap enable | system control | exception flags |
  110. *
  111. * We ignore the system ID bits; for interest's sake they are:
  112. *
  113. * 0000 "old" FPE
  114. * 1000 FPPC hardware
  115. * 0001 FPE 400
  116. * 1001 FPA hardware
  117. *
  118. * The trap enable and exception flags are both structured like this:
  119. *
  120. * 7 - 5 4 3 2 1 0
  121. * | reserved | INX | UFL | OFL | DVZ | IVO |
  122. *
  123. * where a `1' bit in the enable byte means that the trap can occur, and
  124. * a `1' bit in the flags byte means the exception has occurred.
  125. *
  126. * The exceptions are:
  127. *
  128. * IVO - invalid operation
  129. * DVZ - divide by zero
  130. * OFL - overflow
  131. * UFL - underflow
  132. * INX - inexact (do not use; implementations differ)
  133. *
  134. * The system control byte looks like this:
  135. *
  136. * 7-5 4 3 2 1 0
  137. * | reserved | AC | EP | SO | NE | ND |
  138. *
  139. * where the bits mean
  140. *
  141. * ND - no denormalised numbers (force them all to zero)
  142. * NE - enable NaN exceptions
  143. * SO - synchronous operation
  144. * EP - use expanded packed-decimal format
  145. * AC - use alternate definition for C flag on compare operations
  146. */
  147. /* masking of interrupts */
  148. #define _FPU_MASK_IM 0x00010000 /* invalid operation */
  149. #define _FPU_MASK_ZM 0x00020000 /* divide by zero */
  150. #define _FPU_MASK_OM 0x00040000 /* overflow */
  151. #define _FPU_MASK_UM 0x00080000 /* underflow */
  152. #define _FPU_MASK_PM 0x00100000 /* inexact */
  153. #define _FPU_MASK_DM 0x00000000 /* denormalized operation */
  154. /* The system id bytes cannot be changed.
  155. Only the bottom 5 bits in the trap enable byte can be changed.
  156. Only the bottom 5 bits in the system control byte can be changed.
  157. Only the bottom 5 bits in the exception flags are used.
  158. The exception flags are set by the fpu, but can be zeroed by the user. */
  159. #define _FPU_RESERVED 0xffe0e0e0 /* These bits are reserved. */
  160. /* The fdlibm code requires strict IEEE double precision arithmetic,
  161. no interrupts for exceptions, rounding to nearest. Changing the
  162. rounding mode will break long double I/O. Turn on the AC bit,
  163. the compiler generates code that assumes it is on. */
  164. #define _FPU_DEFAULT 0x00001000 /* Default value. */
  165. #define _FPU_IEEE 0x001f1000 /* Default + exceptions enabled. */
  166. /* Type of the control word. */
  167. typedef unsigned int fpu_control_t;
  168. /* Macros for accessing the hardware control word. */
  169. #define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
  170. #define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
  171. #endif /* __MAVERICK__ */
  172. /* Default control word set at startup. */
  173. extern fpu_control_t __fpu_control;
  174. #endif /* _FPU_CONTROL_H */