longlong.h 50 KB

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  1. /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
  2. Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
  3. 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
  4. This file is part of the GNU C Library.
  5. The GNU C Library is free software; you can redistribute it and/or
  6. modify it under the terms of the GNU Lesser General Public
  7. License as published by the Free Software Foundation; either
  8. version 2.1 of the License, or (at your option) any later version.
  9. The GNU C Library is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. Lesser General Public License for more details.
  13. You should have received a copy of the GNU Lesser General Public
  14. License along with the GNU C Library; if not, see
  15. <http://www.gnu.org/licenses/>. */
  16. /* You have to define the following before including this file:
  17. UWtype -- An unsigned type, default type for operations (typically a "word")
  18. UHWtype -- An unsigned type, at least half the size of UWtype.
  19. UDWtype -- An unsigned type, at least twice as large a UWtype
  20. W_TYPE_SIZE -- size in bits of UWtype
  21. UQItype -- Unsigned 8 bit type.
  22. SItype, USItype -- Signed and unsigned 32 bit types.
  23. DItype, UDItype -- Signed and unsigned 64 bit types.
  24. On a 32 bit machine UWtype should typically be USItype;
  25. on a 64 bit machine, UWtype should typically be UDItype. */
  26. #define __BITS4 (W_TYPE_SIZE / 4)
  27. #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
  28. #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
  29. #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
  30. #ifndef W_TYPE_SIZE
  31. #define W_TYPE_SIZE 32
  32. #define UWtype USItype
  33. #define UHWtype USItype
  34. #define UDWtype UDItype
  35. #endif
  36. extern const UQItype __clz_tab[256] attribute_hidden;
  37. /* Define auxiliary asm macros.
  38. 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
  39. UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
  40. word product in HIGH_PROD and LOW_PROD.
  41. 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
  42. UDWtype product. This is just a variant of umul_ppmm.
  43. 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
  44. denominator) divides a UDWtype, composed by the UWtype integers
  45. HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
  46. in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
  47. than DENOMINATOR for correct operation. If, in addition, the most
  48. significant bit of DENOMINATOR must be 1, then the pre-processor symbol
  49. UDIV_NEEDS_NORMALIZATION is defined to 1.
  50. 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
  51. denominator). Like udiv_qrnnd but the numbers are signed. The quotient
  52. is rounded towards 0.
  53. 5) count_leading_zeros(count, x) counts the number of zero-bits from the
  54. msb to the first nonzero bit in the UWtype X. This is the number of
  55. steps X needs to be shifted left to set the msb. Undefined for X == 0,
  56. unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
  57. 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
  58. from the least significant end.
  59. 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
  60. high_addend_2, low_addend_2) adds two UWtype integers, composed by
  61. HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
  62. respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
  63. (i.e. carry out) is not stored anywhere, and is lost.
  64. 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
  65. high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
  66. composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
  67. LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
  68. and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
  69. and is lost.
  70. If any of these macros are left undefined for a particular CPU,
  71. C macros are used. */
  72. /* The CPUs come in alphabetical order below.
  73. Please add support for more CPUs here, or improve the current support
  74. for the CPUs below!
  75. (E.g. WE32100, IBM360.) */
  76. #if defined (__GNUC__) && !defined (NO_ASM)
  77. /* We sometimes need to clobber "cc" with gcc2, but that would not be
  78. understood by gcc1. Use cpp to avoid major code duplication. */
  79. #if __GNUC__ < 2
  80. #define __CLOBBER_CC
  81. #define __AND_CLOBBER_CC
  82. #else /* __GNUC__ >= 2 */
  83. #define __CLOBBER_CC : "cc"
  84. #define __AND_CLOBBER_CC , "cc"
  85. #endif /* __GNUC__ < 2 */
  86. #if defined (__alpha) && W_TYPE_SIZE == 64
  87. #define umul_ppmm(ph, pl, m0, m1) \
  88. do { \
  89. UDItype __m0 = (m0), __m1 = (m1); \
  90. (ph) = __builtin_alpha_umulh (__m0, __m1); \
  91. (pl) = __m0 * __m1; \
  92. } while (0)
  93. #define UMUL_TIME 46
  94. #ifndef LONGLONG_STANDALONE
  95. #define udiv_qrnnd(q, r, n1, n0, d) \
  96. do { UDItype __r; \
  97. (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
  98. (r) = __r; \
  99. } while (0)
  100. extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  101. #define UDIV_TIME 220
  102. #endif /* LONGLONG_STANDALONE */
  103. #ifdef __alpha_cix__
  104. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
  105. #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
  106. #define COUNT_LEADING_ZEROS_0 64
  107. #else
  108. #define count_leading_zeros(COUNT,X) \
  109. do { \
  110. UDItype __xr = (X), __t, __a; \
  111. __t = __builtin_alpha_cmpbge (0, __xr); \
  112. __a = __clz_tab[__t ^ 0xff] - 1; \
  113. __t = __builtin_alpha_extbl (__xr, __a); \
  114. (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
  115. } while (0)
  116. #define count_trailing_zeros(COUNT,X) \
  117. do { \
  118. UDItype __xr = (X), __t, __a; \
  119. __t = __builtin_alpha_cmpbge (0, __xr); \
  120. __t = ~__t & -~__t; \
  121. __a = ((__t & 0xCC) != 0) * 2; \
  122. __a += ((__t & 0xF0) != 0) * 4; \
  123. __a += ((__t & 0xAA) != 0); \
  124. __t = __builtin_alpha_extbl (__xr, __a); \
  125. __a <<= 3; \
  126. __t &= -__t; \
  127. __a += ((__t & 0xCC) != 0) * 2; \
  128. __a += ((__t & 0xF0) != 0) * 4; \
  129. __a += ((__t & 0xAA) != 0); \
  130. (COUNT) = __a; \
  131. } while (0)
  132. #endif /* __alpha_cix__ */
  133. #endif /* __alpha */
  134. #if defined (__arc__) && W_TYPE_SIZE == 32
  135. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  136. __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
  137. : "=r" ((USItype) (sh)), \
  138. "=&r" ((USItype) (sl)) \
  139. : "%r" ((USItype) (ah)), \
  140. "rIJ" ((USItype) (bh)), \
  141. "%r" ((USItype) (al)), \
  142. "rIJ" ((USItype) (bl)))
  143. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  144. __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
  145. : "=r" ((USItype) (sh)), \
  146. "=&r" ((USItype) (sl)) \
  147. : "r" ((USItype) (ah)), \
  148. "rIJ" ((USItype) (bh)), \
  149. "r" ((USItype) (al)), \
  150. "rIJ" ((USItype) (bl)))
  151. /* Call libgcc routine. */
  152. #define umul_ppmm(w1, w0, u, v) \
  153. do { \
  154. DWunion __w; \
  155. __w.ll = __umulsidi3 (u, v); \
  156. w1 = __w.s.high; \
  157. w0 = __w.s.low; \
  158. } while (0)
  159. #define __umulsidi3 __umulsidi3
  160. UDItype __umulsidi3 (USItype, USItype);
  161. #endif
  162. #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
  163. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  164. __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
  165. : "=r" ((USItype) (sh)), \
  166. "=&r" ((USItype) (sl)) \
  167. : "%r" ((USItype) (ah)), \
  168. "rI" ((USItype) (bh)), \
  169. "%r" ((USItype) (al)), \
  170. "rI" ((USItype) (bl)) __CLOBBER_CC)
  171. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  172. __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
  173. : "=r" ((USItype) (sh)), \
  174. "=&r" ((USItype) (sl)) \
  175. : "r" ((USItype) (ah)), \
  176. "rI" ((USItype) (bh)), \
  177. "r" ((USItype) (al)), \
  178. "rI" ((USItype) (bl)) __CLOBBER_CC)
  179. #define umul_ppmm(xh, xl, a, b) \
  180. {register USItype __t0, __t1, __t2; \
  181. __asm__ ("%@ Inlined umul_ppmm\n" \
  182. " mov %2, %5, lsr #16\n" \
  183. " mov %0, %6, lsr #16\n" \
  184. " bic %3, %5, %2, lsl #16\n" \
  185. " bic %4, %6, %0, lsl #16\n" \
  186. " mul %1, %3, %4\n" \
  187. " mul %4, %2, %4\n" \
  188. " mul %3, %0, %3\n" \
  189. " mul %0, %2, %0\n" \
  190. " adds %3, %4, %3\n" \
  191. " addcs %0, %0, #65536\n" \
  192. " adds %1, %1, %3, lsl #16\n" \
  193. " adc %0, %0, %3, lsr #16" \
  194. : "=&r" ((USItype) (xh)), \
  195. "=r" ((USItype) (xl)), \
  196. "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
  197. : "r" ((USItype) (a)), \
  198. "r" ((USItype) (b)) __CLOBBER_CC );}
  199. #define UMUL_TIME 20
  200. #define UDIV_TIME 100
  201. #endif /* __arm__ */
  202. #if defined(__arm__)
  203. /* Let gcc decide how best to implement count_leading_zeros. */
  204. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
  205. #define COUNT_LEADING_ZEROS_0 32
  206. #endif
  207. #if defined (__CRIS__) && __CRIS_arch_version >= 3
  208. #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
  209. #if __CRIS_arch_version >= 8
  210. #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
  211. #endif
  212. #endif /* __CRIS__ */
  213. #if defined (__hppa) && W_TYPE_SIZE == 32
  214. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  215. __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
  216. : "=r" ((USItype) (sh)), \
  217. "=&r" ((USItype) (sl)) \
  218. : "%rM" ((USItype) (ah)), \
  219. "rM" ((USItype) (bh)), \
  220. "%rM" ((USItype) (al)), \
  221. "rM" ((USItype) (bl)))
  222. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  223. __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
  224. : "=r" ((USItype) (sh)), \
  225. "=&r" ((USItype) (sl)) \
  226. : "rM" ((USItype) (ah)), \
  227. "rM" ((USItype) (bh)), \
  228. "rM" ((USItype) (al)), \
  229. "rM" ((USItype) (bl)))
  230. #if defined (_PA_RISC1_1)
  231. #define umul_ppmm(w1, w0, u, v) \
  232. do { \
  233. union \
  234. { \
  235. UDItype __f; \
  236. struct {USItype __w1, __w0;} __w1w0; \
  237. } __t; \
  238. __asm__ ("xmpyu %1,%2,%0" \
  239. : "=x" (__t.__f) \
  240. : "x" ((USItype) (u)), \
  241. "x" ((USItype) (v))); \
  242. (w1) = __t.__w1w0.__w1; \
  243. (w0) = __t.__w1w0.__w0; \
  244. } while (0)
  245. #define UMUL_TIME 8
  246. #else
  247. #define UMUL_TIME 30
  248. #endif
  249. #define UDIV_TIME 40
  250. #define count_leading_zeros(count, x) \
  251. do { \
  252. USItype __tmp; \
  253. __asm__ ( \
  254. "ldi 1,%0\n" \
  255. " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
  256. " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
  257. " ldo 16(%0),%0 ; Yes. Perform add.\n" \
  258. " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
  259. " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
  260. " ldo 8(%0),%0 ; Yes. Perform add.\n" \
  261. " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
  262. " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
  263. " ldo 4(%0),%0 ; Yes. Perform add.\n" \
  264. " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
  265. " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
  266. " ldo 2(%0),%0 ; Yes. Perform add.\n" \
  267. " extru %1,30,1,%1 ; Extract bit 1.\n" \
  268. " sub %0,%1,%0 ; Subtract it.\n" \
  269. : "=r" (count), "=r" (__tmp) : "1" (x)); \
  270. } while (0)
  271. #endif
  272. #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
  273. #define smul_ppmm(xh, xl, m0, m1) \
  274. do { \
  275. union {DItype __ll; \
  276. struct {USItype __h, __l;} __i; \
  277. } __x; \
  278. __asm__ ("lr %N0,%1\n\tmr %0,%2" \
  279. : "=&r" (__x.__ll) \
  280. : "r" (m0), "r" (m1)); \
  281. (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
  282. } while (0)
  283. #define sdiv_qrnnd(q, r, n1, n0, d) \
  284. do { \
  285. union {DItype __ll; \
  286. struct {USItype __h, __l;} __i; \
  287. } __x; \
  288. __x.__i.__h = n1; __x.__i.__l = n0; \
  289. __asm__ ("dr %0,%2" \
  290. : "=r" (__x.__ll) \
  291. : "0" (__x.__ll), "r" (d)); \
  292. (q) = __x.__i.__l; (r) = __x.__i.__h; \
  293. } while (0)
  294. #endif
  295. #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
  296. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  297. __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
  298. : "=r" ((USItype) (sh)), \
  299. "=&r" ((USItype) (sl)) \
  300. : "%0" ((USItype) (ah)), \
  301. "g" ((USItype) (bh)), \
  302. "%1" ((USItype) (al)), \
  303. "g" ((USItype) (bl)))
  304. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  305. __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
  306. : "=r" ((USItype) (sh)), \
  307. "=&r" ((USItype) (sl)) \
  308. : "0" ((USItype) (ah)), \
  309. "g" ((USItype) (bh)), \
  310. "1" ((USItype) (al)), \
  311. "g" ((USItype) (bl)))
  312. #define umul_ppmm(w1, w0, u, v) \
  313. __asm__ ("mul{l} %3" \
  314. : "=a" ((USItype) (w0)), \
  315. "=d" ((USItype) (w1)) \
  316. : "%0" ((USItype) (u)), \
  317. "rm" ((USItype) (v)))
  318. #define udiv_qrnnd(q, r, n1, n0, dv) \
  319. __asm__ ("div{l} %4" \
  320. : "=a" ((USItype) (q)), \
  321. "=d" ((USItype) (r)) \
  322. : "0" ((USItype) (n0)), \
  323. "1" ((USItype) (n1)), \
  324. "rm" ((USItype) (dv)))
  325. #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
  326. #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
  327. #define UMUL_TIME 40
  328. #define UDIV_TIME 40
  329. #endif /* 80x86 */
  330. #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
  331. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  332. __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
  333. : "=r" ((UDItype) (sh)), \
  334. "=&r" ((UDItype) (sl)) \
  335. : "%0" ((UDItype) (ah)), \
  336. "rme" ((UDItype) (bh)), \
  337. "%1" ((UDItype) (al)), \
  338. "rme" ((UDItype) (bl)))
  339. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  340. __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
  341. : "=r" ((UDItype) (sh)), \
  342. "=&r" ((UDItype) (sl)) \
  343. : "0" ((UDItype) (ah)), \
  344. "rme" ((UDItype) (bh)), \
  345. "1" ((UDItype) (al)), \
  346. "rme" ((UDItype) (bl)))
  347. #define umul_ppmm(w1, w0, u, v) \
  348. __asm__ ("mul{q} %3" \
  349. : "=a" ((UDItype) (w0)), \
  350. "=d" ((UDItype) (w1)) \
  351. : "%0" ((UDItype) (u)), \
  352. "rm" ((UDItype) (v)))
  353. #define udiv_qrnnd(q, r, n1, n0, dv) \
  354. __asm__ ("div{q} %4" \
  355. : "=a" ((UDItype) (q)), \
  356. "=d" ((UDItype) (r)) \
  357. : "0" ((UDItype) (n0)), \
  358. "1" ((UDItype) (n1)), \
  359. "rm" ((UDItype) (dv)))
  360. #define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
  361. #define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
  362. #define UMUL_TIME 40
  363. #define UDIV_TIME 40
  364. #endif /* x86_64 */
  365. #if defined (__i960__) && W_TYPE_SIZE == 32
  366. #define umul_ppmm(w1, w0, u, v) \
  367. ({union {UDItype __ll; \
  368. struct {USItype __l, __h;} __i; \
  369. } __xx; \
  370. __asm__ ("emul %2,%1,%0" \
  371. : "=d" (__xx.__ll) \
  372. : "%dI" ((USItype) (u)), \
  373. "dI" ((USItype) (v))); \
  374. (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
  375. #define __umulsidi3(u, v) \
  376. ({UDItype __w; \
  377. __asm__ ("emul %2,%1,%0" \
  378. : "=d" (__w) \
  379. : "%dI" ((USItype) (u)), \
  380. "dI" ((USItype) (v))); \
  381. __w; })
  382. #endif /* __i960__ */
  383. #if defined (__M32R__) && W_TYPE_SIZE == 32
  384. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  385. /* The cmp clears the condition bit. */ \
  386. __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
  387. : "=r" ((USItype) (sh)), \
  388. "=&r" ((USItype) (sl)) \
  389. : "0" ((USItype) (ah)), \
  390. "r" ((USItype) (bh)), \
  391. "1" ((USItype) (al)), \
  392. "r" ((USItype) (bl)) \
  393. : "cbit")
  394. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  395. /* The cmp clears the condition bit. */ \
  396. __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
  397. : "=r" ((USItype) (sh)), \
  398. "=&r" ((USItype) (sl)) \
  399. : "0" ((USItype) (ah)), \
  400. "r" ((USItype) (bh)), \
  401. "1" ((USItype) (al)), \
  402. "r" ((USItype) (bl)) \
  403. : "cbit")
  404. #endif /* __M32R__ */
  405. #if defined (__mc68000__) && W_TYPE_SIZE == 32
  406. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  407. __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
  408. : "=d" ((USItype) (sh)), \
  409. "=&d" ((USItype) (sl)) \
  410. : "%0" ((USItype) (ah)), \
  411. "d" ((USItype) (bh)), \
  412. "%1" ((USItype) (al)), \
  413. "g" ((USItype) (bl)))
  414. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  415. __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
  416. : "=d" ((USItype) (sh)), \
  417. "=&d" ((USItype) (sl)) \
  418. : "0" ((USItype) (ah)), \
  419. "d" ((USItype) (bh)), \
  420. "1" ((USItype) (al)), \
  421. "g" ((USItype) (bl)))
  422. /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
  423. #if (defined (__mc68020__) && !defined (__mc68060__))
  424. #define umul_ppmm(w1, w0, u, v) \
  425. __asm__ ("mulu%.l %3,%1:%0" \
  426. : "=d" ((USItype) (w0)), \
  427. "=d" ((USItype) (w1)) \
  428. : "%0" ((USItype) (u)), \
  429. "dmi" ((USItype) (v)))
  430. #define UMUL_TIME 45
  431. #define udiv_qrnnd(q, r, n1, n0, d) \
  432. __asm__ ("divu%.l %4,%1:%0" \
  433. : "=d" ((USItype) (q)), \
  434. "=d" ((USItype) (r)) \
  435. : "0" ((USItype) (n0)), \
  436. "1" ((USItype) (n1)), \
  437. "dmi" ((USItype) (d)))
  438. #define UDIV_TIME 90
  439. #define sdiv_qrnnd(q, r, n1, n0, d) \
  440. __asm__ ("divs%.l %4,%1:%0" \
  441. : "=d" ((USItype) (q)), \
  442. "=d" ((USItype) (r)) \
  443. : "0" ((USItype) (n0)), \
  444. "1" ((USItype) (n1)), \
  445. "dmi" ((USItype) (d)))
  446. #elif defined (__mcoldfire__) /* not mc68020 */
  447. #define umul_ppmm(xh, xl, a, b) \
  448. __asm__ ("| Inlined umul_ppmm\n" \
  449. " move%.l %2,%/d0\n" \
  450. " move%.l %3,%/d1\n" \
  451. " move%.l %/d0,%/d2\n" \
  452. " swap %/d0\n" \
  453. " move%.l %/d1,%/d3\n" \
  454. " swap %/d1\n" \
  455. " move%.w %/d2,%/d4\n" \
  456. " mulu %/d3,%/d4\n" \
  457. " mulu %/d1,%/d2\n" \
  458. " mulu %/d0,%/d3\n" \
  459. " mulu %/d0,%/d1\n" \
  460. " move%.l %/d4,%/d0\n" \
  461. " clr%.w %/d0\n" \
  462. " swap %/d0\n" \
  463. " add%.l %/d0,%/d2\n" \
  464. " add%.l %/d3,%/d2\n" \
  465. " jcc 1f\n" \
  466. " add%.l %#65536,%/d1\n" \
  467. "1: swap %/d2\n" \
  468. " moveq %#0,%/d0\n" \
  469. " move%.w %/d2,%/d0\n" \
  470. " move%.w %/d4,%/d2\n" \
  471. " move%.l %/d2,%1\n" \
  472. " add%.l %/d1,%/d0\n" \
  473. " move%.l %/d0,%0" \
  474. : "=g" ((USItype) (xh)), \
  475. "=g" ((USItype) (xl)) \
  476. : "g" ((USItype) (a)), \
  477. "g" ((USItype) (b)) \
  478. : "d0", "d1", "d2", "d3", "d4")
  479. #define UMUL_TIME 100
  480. #define UDIV_TIME 400
  481. #else /* not ColdFire */
  482. /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
  483. #define umul_ppmm(xh, xl, a, b) \
  484. __asm__ ("| Inlined umul_ppmm\n" \
  485. " move%.l %2,%/d0\n" \
  486. " move%.l %3,%/d1\n" \
  487. " move%.l %/d0,%/d2\n" \
  488. " swap %/d0\n" \
  489. " move%.l %/d1,%/d3\n" \
  490. " swap %/d1\n" \
  491. " move%.w %/d2,%/d4\n" \
  492. " mulu %/d3,%/d4\n" \
  493. " mulu %/d1,%/d2\n" \
  494. " mulu %/d0,%/d3\n" \
  495. " mulu %/d0,%/d1\n" \
  496. " move%.l %/d4,%/d0\n" \
  497. " eor%.w %/d0,%/d0\n" \
  498. " swap %/d0\n" \
  499. " add%.l %/d0,%/d2\n" \
  500. " add%.l %/d3,%/d2\n" \
  501. " jcc 1f\n" \
  502. " add%.l %#65536,%/d1\n" \
  503. "1: swap %/d2\n" \
  504. " moveq %#0,%/d0\n" \
  505. " move%.w %/d2,%/d0\n" \
  506. " move%.w %/d4,%/d2\n" \
  507. " move%.l %/d2,%1\n" \
  508. " add%.l %/d1,%/d0\n" \
  509. " move%.l %/d0,%0" \
  510. : "=g" ((USItype) (xh)), \
  511. "=g" ((USItype) (xl)) \
  512. : "g" ((USItype) (a)), \
  513. "g" ((USItype) (b)) \
  514. : "d0", "d1", "d2", "d3", "d4")
  515. #define UMUL_TIME 100
  516. #define UDIV_TIME 400
  517. #endif /* not mc68020 */
  518. /* The '020, '030, '040 and '060 have bitfield insns.
  519. cpu32 disguises as a 68020, but lacks them. */
  520. #if defined (__mc68020__) && !defined (__mcpu32__)
  521. #define count_leading_zeros(count, x) \
  522. __asm__ ("bfffo %1{%b2:%b2},%0" \
  523. : "=d" ((USItype) (count)) \
  524. : "od" ((USItype) (x)), "n" (0))
  525. /* Some ColdFire architectures have a ff1 instruction supported via
  526. __builtin_clz. */
  527. #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
  528. #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
  529. #define COUNT_LEADING_ZEROS_0 32
  530. #endif
  531. #endif /* mc68000 */
  532. #if defined (__m88000__) && W_TYPE_SIZE == 32
  533. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  534. __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
  535. : "=r" ((USItype) (sh)), \
  536. "=&r" ((USItype) (sl)) \
  537. : "%rJ" ((USItype) (ah)), \
  538. "rJ" ((USItype) (bh)), \
  539. "%rJ" ((USItype) (al)), \
  540. "rJ" ((USItype) (bl)))
  541. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  542. __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
  543. : "=r" ((USItype) (sh)), \
  544. "=&r" ((USItype) (sl)) \
  545. : "rJ" ((USItype) (ah)), \
  546. "rJ" ((USItype) (bh)), \
  547. "rJ" ((USItype) (al)), \
  548. "rJ" ((USItype) (bl)))
  549. #define count_leading_zeros(count, x) \
  550. do { \
  551. USItype __cbtmp; \
  552. __asm__ ("ff1 %0,%1" \
  553. : "=r" (__cbtmp) \
  554. : "r" ((USItype) (x))); \
  555. (count) = __cbtmp ^ 31; \
  556. } while (0)
  557. #define COUNT_LEADING_ZEROS_0 63 /* sic */
  558. #if defined (__mc88110__)
  559. #define umul_ppmm(wh, wl, u, v) \
  560. do { \
  561. union {UDItype __ll; \
  562. struct {USItype __h, __l;} __i; \
  563. } __xx; \
  564. __asm__ ("mulu.d %0,%1,%2" \
  565. : "=r" (__xx.__ll) \
  566. : "r" ((USItype) (u)), \
  567. "r" ((USItype) (v))); \
  568. (wh) = __xx.__i.__h; \
  569. (wl) = __xx.__i.__l; \
  570. } while (0)
  571. #define udiv_qrnnd(q, r, n1, n0, d) \
  572. ({union {UDItype __ll; \
  573. struct {USItype __h, __l;} __i; \
  574. } __xx; \
  575. USItype __q; \
  576. __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
  577. __asm__ ("divu.d %0,%1,%2" \
  578. : "=r" (__q) \
  579. : "r" (__xx.__ll), \
  580. "r" ((USItype) (d))); \
  581. (r) = (n0) - __q * (d); (q) = __q; })
  582. #define UMUL_TIME 5
  583. #define UDIV_TIME 25
  584. #else
  585. #define UMUL_TIME 17
  586. #define UDIV_TIME 150
  587. #endif /* __mc88110__ */
  588. #endif /* __m88000__ */
  589. #if defined (__mips__) && W_TYPE_SIZE == 32
  590. #define umul_ppmm(w1, w0, u, v) \
  591. do { \
  592. UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
  593. (w1) = (USItype) (__x >> 32); \
  594. (w0) = (USItype) (__x); \
  595. } while (0)
  596. #define UMUL_TIME 10
  597. #define UDIV_TIME 100
  598. #if (__mips == 32 || __mips == 64) && ! __mips16
  599. #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
  600. #define COUNT_LEADING_ZEROS_0 32
  601. #endif
  602. #endif /* __mips__ */
  603. #if defined (__ns32000__) && W_TYPE_SIZE == 32
  604. #define umul_ppmm(w1, w0, u, v) \
  605. ({union {UDItype __ll; \
  606. struct {USItype __l, __h;} __i; \
  607. } __xx; \
  608. __asm__ ("meid %2,%0" \
  609. : "=g" (__xx.__ll) \
  610. : "%0" ((USItype) (u)), \
  611. "g" ((USItype) (v))); \
  612. (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
  613. #define __umulsidi3(u, v) \
  614. ({UDItype __w; \
  615. __asm__ ("meid %2,%0" \
  616. : "=g" (__w) \
  617. : "%0" ((USItype) (u)), \
  618. "g" ((USItype) (v))); \
  619. __w; })
  620. #define udiv_qrnnd(q, r, n1, n0, d) \
  621. ({union {UDItype __ll; \
  622. struct {USItype __l, __h;} __i; \
  623. } __xx; \
  624. __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
  625. __asm__ ("deid %2,%0" \
  626. : "=g" (__xx.__ll) \
  627. : "0" (__xx.__ll), \
  628. "g" ((USItype) (d))); \
  629. (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
  630. #define count_trailing_zeros(count,x) \
  631. do { \
  632. __asm__ ("ffsd %2,%0" \
  633. : "=r" ((USItype) (count)) \
  634. : "0" ((USItype) 0), \
  635. "r" ((USItype) (x))); \
  636. } while (0)
  637. #endif /* __ns32000__ */
  638. /* FIXME: We should test _IBMR2 here when we add assembly support for the
  639. system vendor compilers.
  640. FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
  641. enough, since that hits ARM and m68k too. */
  642. #if (defined (_ARCH_PPC) /* AIX */ \
  643. || defined (_ARCH_PWR) /* AIX */ \
  644. || defined (_ARCH_COM) /* AIX */ \
  645. || defined (__powerpc__) /* gcc */ \
  646. || defined (__POWERPC__) /* BEOS */ \
  647. || defined (__ppc__) /* Darwin */ \
  648. || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
  649. || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
  650. && CPU_FAMILY == PPC) \
  651. ) && W_TYPE_SIZE == 32
  652. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  653. do { \
  654. if (__builtin_constant_p (bh) && (bh) == 0) \
  655. __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
  656. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  657. else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
  658. __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
  659. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  660. else \
  661. __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
  662. : "=r" (sh), "=&r" (sl) \
  663. : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
  664. } while (0)
  665. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  666. do { \
  667. if (__builtin_constant_p (ah) && (ah) == 0) \
  668. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
  669. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  670. else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
  671. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
  672. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  673. else if (__builtin_constant_p (bh) && (bh) == 0) \
  674. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
  675. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  676. else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
  677. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
  678. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  679. else \
  680. __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
  681. : "=r" (sh), "=&r" (sl) \
  682. : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
  683. } while (0)
  684. #define count_leading_zeros(count, x) \
  685. __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
  686. #define COUNT_LEADING_ZEROS_0 32
  687. #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
  688. || defined (__ppc__) \
  689. || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
  690. || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
  691. && CPU_FAMILY == PPC)
  692. #define umul_ppmm(ph, pl, m0, m1) \
  693. do { \
  694. USItype __m0 = (m0), __m1 = (m1); \
  695. __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  696. (pl) = __m0 * __m1; \
  697. } while (0)
  698. #define UMUL_TIME 15
  699. #define smul_ppmm(ph, pl, m0, m1) \
  700. do { \
  701. SItype __m0 = (m0), __m1 = (m1); \
  702. __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  703. (pl) = __m0 * __m1; \
  704. } while (0)
  705. #define SMUL_TIME 14
  706. #define UDIV_TIME 120
  707. #elif defined (_ARCH_PWR)
  708. #define UMUL_TIME 8
  709. #define smul_ppmm(xh, xl, m0, m1) \
  710. __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
  711. #define SMUL_TIME 4
  712. #define sdiv_qrnnd(q, r, nh, nl, d) \
  713. __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
  714. #define UDIV_TIME 100
  715. #endif
  716. #endif /* 32-bit POWER architecture variants. */
  717. /* We should test _IBMR2 here when we add assembly support for the system
  718. vendor compilers. */
  719. #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
  720. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  721. do { \
  722. if (__builtin_constant_p (bh) && (bh) == 0) \
  723. __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
  724. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  725. else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
  726. __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
  727. : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
  728. else \
  729. __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
  730. : "=r" (sh), "=&r" (sl) \
  731. : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
  732. } while (0)
  733. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  734. do { \
  735. if (__builtin_constant_p (ah) && (ah) == 0) \
  736. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
  737. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  738. else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
  739. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
  740. : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
  741. else if (__builtin_constant_p (bh) && (bh) == 0) \
  742. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
  743. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  744. else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
  745. __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
  746. : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
  747. else \
  748. __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
  749. : "=r" (sh), "=&r" (sl) \
  750. : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
  751. } while (0)
  752. #define count_leading_zeros(count, x) \
  753. __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
  754. #define COUNT_LEADING_ZEROS_0 64
  755. #define umul_ppmm(ph, pl, m0, m1) \
  756. do { \
  757. UDItype __m0 = (m0), __m1 = (m1); \
  758. __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  759. (pl) = __m0 * __m1; \
  760. } while (0)
  761. #define UMUL_TIME 15
  762. #define smul_ppmm(ph, pl, m0, m1) \
  763. do { \
  764. DItype __m0 = (m0), __m1 = (m1); \
  765. __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
  766. (pl) = __m0 * __m1; \
  767. } while (0)
  768. #define SMUL_TIME 14 /* ??? */
  769. #define UDIV_TIME 120 /* ??? */
  770. #endif /* 64-bit PowerPC. */
  771. #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
  772. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  773. __asm__ ("a %1,%5\n\tae %0,%3" \
  774. : "=r" ((USItype) (sh)), \
  775. "=&r" ((USItype) (sl)) \
  776. : "%0" ((USItype) (ah)), \
  777. "r" ((USItype) (bh)), \
  778. "%1" ((USItype) (al)), \
  779. "r" ((USItype) (bl)))
  780. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  781. __asm__ ("s %1,%5\n\tse %0,%3" \
  782. : "=r" ((USItype) (sh)), \
  783. "=&r" ((USItype) (sl)) \
  784. : "0" ((USItype) (ah)), \
  785. "r" ((USItype) (bh)), \
  786. "1" ((USItype) (al)), \
  787. "r" ((USItype) (bl)))
  788. #define umul_ppmm(ph, pl, m0, m1) \
  789. do { \
  790. USItype __m0 = (m0), __m1 = (m1); \
  791. __asm__ ( \
  792. "s r2,r2\n" \
  793. " mts r10,%2\n" \
  794. " m r2,%3\n" \
  795. " m r2,%3\n" \
  796. " m r2,%3\n" \
  797. " m r2,%3\n" \
  798. " m r2,%3\n" \
  799. " m r2,%3\n" \
  800. " m r2,%3\n" \
  801. " m r2,%3\n" \
  802. " m r2,%3\n" \
  803. " m r2,%3\n" \
  804. " m r2,%3\n" \
  805. " m r2,%3\n" \
  806. " m r2,%3\n" \
  807. " m r2,%3\n" \
  808. " m r2,%3\n" \
  809. " m r2,%3\n" \
  810. " cas %0,r2,r0\n" \
  811. " mfs r10,%1" \
  812. : "=r" ((USItype) (ph)), \
  813. "=r" ((USItype) (pl)) \
  814. : "%r" (__m0), \
  815. "r" (__m1) \
  816. : "r2"); \
  817. (ph) += ((((SItype) __m0 >> 31) & __m1) \
  818. + (((SItype) __m1 >> 31) & __m0)); \
  819. } while (0)
  820. #define UMUL_TIME 20
  821. #define UDIV_TIME 200
  822. #define count_leading_zeros(count, x) \
  823. do { \
  824. if ((x) >= 0x10000) \
  825. __asm__ ("clz %0,%1" \
  826. : "=r" ((USItype) (count)) \
  827. : "r" ((USItype) (x) >> 16)); \
  828. else \
  829. { \
  830. __asm__ ("clz %0,%1" \
  831. : "=r" ((USItype) (count)) \
  832. : "r" ((USItype) (x))); \
  833. (count) += 16; \
  834. } \
  835. } while (0)
  836. #endif
  837. #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
  838. #ifndef __sh1__
  839. #define umul_ppmm(w1, w0, u, v) \
  840. __asm__ ( \
  841. "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
  842. : "=r<" ((USItype)(w1)), \
  843. "=r<" ((USItype)(w0)) \
  844. : "r" ((USItype)(u)), \
  845. "r" ((USItype)(v)) \
  846. : "macl", "mach")
  847. #define UMUL_TIME 5
  848. #endif
  849. /* This is the same algorithm as __udiv_qrnnd_c. */
  850. #define UDIV_NEEDS_NORMALIZATION 1
  851. #define udiv_qrnnd(q, r, n1, n0, d) \
  852. do { \
  853. extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
  854. __attribute__ ((visibility ("hidden"))); \
  855. /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
  856. __asm__ ( \
  857. "mov%M4 %4,r5\n" \
  858. " swap.w %3,r4\n" \
  859. " swap.w r5,r6\n" \
  860. " jsr @%5\n" \
  861. " shll16 r6\n" \
  862. " swap.w r4,r4\n" \
  863. " jsr @%5\n" \
  864. " swap.w r1,%0\n" \
  865. " or r1,%0" \
  866. : "=r" (q), "=&z" (r) \
  867. : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
  868. : "r1", "r2", "r4", "r5", "r6", "pr"); \
  869. } while (0)
  870. #define UDIV_TIME 80
  871. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  872. __asm__ ("clrt;subc %5,%1; subc %4,%0" \
  873. : "=r" (sh), "=r" (sl) \
  874. : "0" (ah), "1" (al), "r" (bh), "r" (bl))
  875. #endif /* __sh__ */
  876. #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
  877. #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
  878. #define count_leading_zeros(count, x) \
  879. do \
  880. { \
  881. UDItype x_ = (USItype)(x); \
  882. SItype c_; \
  883. \
  884. __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
  885. (count) = c_ - 31; \
  886. } \
  887. while (0)
  888. #define COUNT_LEADING_ZEROS_0 32
  889. #endif
  890. #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
  891. && W_TYPE_SIZE == 32
  892. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  893. __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
  894. : "=r" ((USItype) (sh)), \
  895. "=&r" ((USItype) (sl)) \
  896. : "%rJ" ((USItype) (ah)), \
  897. "rI" ((USItype) (bh)), \
  898. "%rJ" ((USItype) (al)), \
  899. "rI" ((USItype) (bl)) \
  900. __CLOBBER_CC)
  901. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  902. __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
  903. : "=r" ((USItype) (sh)), \
  904. "=&r" ((USItype) (sl)) \
  905. : "rJ" ((USItype) (ah)), \
  906. "rI" ((USItype) (bh)), \
  907. "rJ" ((USItype) (al)), \
  908. "rI" ((USItype) (bl)) \
  909. __CLOBBER_CC)
  910. #if defined (__sparc_v8__)
  911. #define umul_ppmm(w1, w0, u, v) \
  912. __asm__ ("umul %2,%3,%1;rd %%y,%0" \
  913. : "=r" ((USItype) (w1)), \
  914. "=r" ((USItype) (w0)) \
  915. : "r" ((USItype) (u)), \
  916. "r" ((USItype) (v)))
  917. #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
  918. __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
  919. : "=&r" ((USItype) (__q)), \
  920. "=&r" ((USItype) (__r)) \
  921. : "r" ((USItype) (__n1)), \
  922. "r" ((USItype) (__n0)), \
  923. "r" ((USItype) (__d)))
  924. #else
  925. #if defined (__sparclite__)
  926. /* This has hardware multiply but not divide. It also has two additional
  927. instructions scan (ffs from high bit) and divscc. */
  928. #define umul_ppmm(w1, w0, u, v) \
  929. __asm__ ("umul %2,%3,%1;rd %%y,%0" \
  930. : "=r" ((USItype) (w1)), \
  931. "=r" ((USItype) (w0)) \
  932. : "r" ((USItype) (u)), \
  933. "r" ((USItype) (v)))
  934. #define udiv_qrnnd(q, r, n1, n0, d) \
  935. __asm__ ("! Inlined udiv_qrnnd\n" \
  936. " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
  937. " tst %%g0\n" \
  938. " divscc %3,%4,%%g1\n" \
  939. " divscc %%g1,%4,%%g1\n" \
  940. " divscc %%g1,%4,%%g1\n" \
  941. " divscc %%g1,%4,%%g1\n" \
  942. " divscc %%g1,%4,%%g1\n" \
  943. " divscc %%g1,%4,%%g1\n" \
  944. " divscc %%g1,%4,%%g1\n" \
  945. " divscc %%g1,%4,%%g1\n" \
  946. " divscc %%g1,%4,%%g1\n" \
  947. " divscc %%g1,%4,%%g1\n" \
  948. " divscc %%g1,%4,%%g1\n" \
  949. " divscc %%g1,%4,%%g1\n" \
  950. " divscc %%g1,%4,%%g1\n" \
  951. " divscc %%g1,%4,%%g1\n" \
  952. " divscc %%g1,%4,%%g1\n" \
  953. " divscc %%g1,%4,%%g1\n" \
  954. " divscc %%g1,%4,%%g1\n" \
  955. " divscc %%g1,%4,%%g1\n" \
  956. " divscc %%g1,%4,%%g1\n" \
  957. " divscc %%g1,%4,%%g1\n" \
  958. " divscc %%g1,%4,%%g1\n" \
  959. " divscc %%g1,%4,%%g1\n" \
  960. " divscc %%g1,%4,%%g1\n" \
  961. " divscc %%g1,%4,%%g1\n" \
  962. " divscc %%g1,%4,%%g1\n" \
  963. " divscc %%g1,%4,%%g1\n" \
  964. " divscc %%g1,%4,%%g1\n" \
  965. " divscc %%g1,%4,%%g1\n" \
  966. " divscc %%g1,%4,%%g1\n" \
  967. " divscc %%g1,%4,%%g1\n" \
  968. " divscc %%g1,%4,%%g1\n" \
  969. " divscc %%g1,%4,%0\n" \
  970. " rd %%y,%1\n" \
  971. " bl,a 1f\n" \
  972. " add %1,%4,%1\n" \
  973. "1: ! End of inline udiv_qrnnd" \
  974. : "=r" ((USItype) (q)), \
  975. "=r" ((USItype) (r)) \
  976. : "r" ((USItype) (n1)), \
  977. "r" ((USItype) (n0)), \
  978. "rI" ((USItype) (d)) \
  979. : "g1" __AND_CLOBBER_CC)
  980. #define UDIV_TIME 37
  981. #define count_leading_zeros(count, x) \
  982. do { \
  983. __asm__ ("scan %1,1,%0" \
  984. : "=r" ((USItype) (count)) \
  985. : "r" ((USItype) (x))); \
  986. } while (0)
  987. /* Early sparclites return 63 for an argument of 0, but they warn that future
  988. implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
  989. undefined. */
  990. #else
  991. /* SPARC without integer multiplication and divide instructions.
  992. (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
  993. #define umul_ppmm(w1, w0, u, v) \
  994. __asm__ ("! Inlined umul_ppmm\n" \
  995. " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
  996. " sra %3,31,%%o5 ! Don't move this insn\n" \
  997. " and %2,%%o5,%%o5 ! Don't move this insn\n" \
  998. " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
  999. " mulscc %%g1,%3,%%g1\n" \
  1000. " mulscc %%g1,%3,%%g1\n" \
  1001. " mulscc %%g1,%3,%%g1\n" \
  1002. " mulscc %%g1,%3,%%g1\n" \
  1003. " mulscc %%g1,%3,%%g1\n" \
  1004. " mulscc %%g1,%3,%%g1\n" \
  1005. " mulscc %%g1,%3,%%g1\n" \
  1006. " mulscc %%g1,%3,%%g1\n" \
  1007. " mulscc %%g1,%3,%%g1\n" \
  1008. " mulscc %%g1,%3,%%g1\n" \
  1009. " mulscc %%g1,%3,%%g1\n" \
  1010. " mulscc %%g1,%3,%%g1\n" \
  1011. " mulscc %%g1,%3,%%g1\n" \
  1012. " mulscc %%g1,%3,%%g1\n" \
  1013. " mulscc %%g1,%3,%%g1\n" \
  1014. " mulscc %%g1,%3,%%g1\n" \
  1015. " mulscc %%g1,%3,%%g1\n" \
  1016. " mulscc %%g1,%3,%%g1\n" \
  1017. " mulscc %%g1,%3,%%g1\n" \
  1018. " mulscc %%g1,%3,%%g1\n" \
  1019. " mulscc %%g1,%3,%%g1\n" \
  1020. " mulscc %%g1,%3,%%g1\n" \
  1021. " mulscc %%g1,%3,%%g1\n" \
  1022. " mulscc %%g1,%3,%%g1\n" \
  1023. " mulscc %%g1,%3,%%g1\n" \
  1024. " mulscc %%g1,%3,%%g1\n" \
  1025. " mulscc %%g1,%3,%%g1\n" \
  1026. " mulscc %%g1,%3,%%g1\n" \
  1027. " mulscc %%g1,%3,%%g1\n" \
  1028. " mulscc %%g1,%3,%%g1\n" \
  1029. " mulscc %%g1,%3,%%g1\n" \
  1030. " mulscc %%g1,%3,%%g1\n" \
  1031. " mulscc %%g1,0,%%g1\n" \
  1032. " add %%g1,%%o5,%0\n" \
  1033. " rd %%y,%1" \
  1034. : "=r" ((USItype) (w1)), \
  1035. "=r" ((USItype) (w0)) \
  1036. : "%rI" ((USItype) (u)), \
  1037. "r" ((USItype) (v)) \
  1038. : "g1", "o5" __AND_CLOBBER_CC)
  1039. #define UMUL_TIME 39 /* 39 instructions */
  1040. /* It's quite necessary to add this much assembler for the sparc.
  1041. The default udiv_qrnnd (in C) is more than 10 times slower! */
  1042. #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
  1043. __asm__ ("! Inlined udiv_qrnnd\n" \
  1044. " mov 32,%%g1\n" \
  1045. " subcc %1,%2,%%g0\n" \
  1046. "1: bcs 5f\n" \
  1047. " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
  1048. " sub %1,%2,%1 ! this kills msb of n\n" \
  1049. " addx %1,%1,%1 ! so this can't give carry\n" \
  1050. " subcc %%g1,1,%%g1\n" \
  1051. "2: bne 1b\n" \
  1052. " subcc %1,%2,%%g0\n" \
  1053. " bcs 3f\n" \
  1054. " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
  1055. " b 3f\n" \
  1056. " sub %1,%2,%1 ! this kills msb of n\n" \
  1057. "4: sub %1,%2,%1\n" \
  1058. "5: addxcc %1,%1,%1\n" \
  1059. " bcc 2b\n" \
  1060. " subcc %%g1,1,%%g1\n" \
  1061. "! Got carry from n. Subtract next step to cancel this carry.\n" \
  1062. " bne 4b\n" \
  1063. " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
  1064. " sub %1,%2,%1\n" \
  1065. "3: xnor %0,0,%0\n" \
  1066. " ! End of inline udiv_qrnnd" \
  1067. : "=&r" ((USItype) (__q)), \
  1068. "=&r" ((USItype) (__r)) \
  1069. : "r" ((USItype) (__d)), \
  1070. "1" ((USItype) (__n1)), \
  1071. "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
  1072. #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
  1073. #endif /* __sparclite__ */
  1074. #endif /* __sparc_v8__ */
  1075. #endif /* sparc32 */
  1076. #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
  1077. && W_TYPE_SIZE == 64
  1078. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1079. __asm__ ("addcc %r4,%5,%1\n\t" \
  1080. "add %r2,%3,%0\n\t" \
  1081. "bcs,a,pn %%xcc, 1f\n\t" \
  1082. "add %0, 1, %0\n" \
  1083. "1:" \
  1084. : "=r" ((UDItype)(sh)), \
  1085. "=&r" ((UDItype)(sl)) \
  1086. : "%rJ" ((UDItype)(ah)), \
  1087. "rI" ((UDItype)(bh)), \
  1088. "%rJ" ((UDItype)(al)), \
  1089. "rI" ((UDItype)(bl)) \
  1090. __CLOBBER_CC)
  1091. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1092. __asm__ ("subcc %r4,%5,%1\n\t" \
  1093. "sub %r2,%3,%0\n\t" \
  1094. "bcs,a,pn %%xcc, 1f\n\t" \
  1095. "sub %0, 1, %0\n\t" \
  1096. "1:" \
  1097. : "=r" ((UDItype)(sh)), \
  1098. "=&r" ((UDItype)(sl)) \
  1099. : "rJ" ((UDItype)(ah)), \
  1100. "rI" ((UDItype)(bh)), \
  1101. "rJ" ((UDItype)(al)), \
  1102. "rI" ((UDItype)(bl)) \
  1103. __CLOBBER_CC)
  1104. #define umul_ppmm(wh, wl, u, v) \
  1105. do { \
  1106. UDItype tmp1, tmp2, tmp3, tmp4; \
  1107. __asm__ __volatile__ ( \
  1108. "srl %7,0,%3\n\t" \
  1109. "mulx %3,%6,%1\n\t" \
  1110. "srlx %6,32,%2\n\t" \
  1111. "mulx %2,%3,%4\n\t" \
  1112. "sllx %4,32,%5\n\t" \
  1113. "srl %6,0,%3\n\t" \
  1114. "sub %1,%5,%5\n\t" \
  1115. "srlx %5,32,%5\n\t" \
  1116. "addcc %4,%5,%4\n\t" \
  1117. "srlx %7,32,%5\n\t" \
  1118. "mulx %3,%5,%3\n\t" \
  1119. "mulx %2,%5,%5\n\t" \
  1120. "sethi %%hi(0x80000000),%2\n\t" \
  1121. "addcc %4,%3,%4\n\t" \
  1122. "srlx %4,32,%4\n\t" \
  1123. "add %2,%2,%2\n\t" \
  1124. "movcc %%xcc,%%g0,%2\n\t" \
  1125. "addcc %5,%4,%5\n\t" \
  1126. "sllx %3,32,%3\n\t" \
  1127. "add %1,%3,%1\n\t" \
  1128. "add %5,%2,%0" \
  1129. : "=r" ((UDItype)(wh)), \
  1130. "=&r" ((UDItype)(wl)), \
  1131. "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
  1132. : "r" ((UDItype)(u)), \
  1133. "r" ((UDItype)(v)) \
  1134. __CLOBBER_CC); \
  1135. } while (0)
  1136. #define UMUL_TIME 96
  1137. #define UDIV_TIME 230
  1138. #endif /* sparc64 */
  1139. #if defined (__vax__) && W_TYPE_SIZE == 32
  1140. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1141. __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
  1142. : "=g" ((USItype) (sh)), \
  1143. "=&g" ((USItype) (sl)) \
  1144. : "%0" ((USItype) (ah)), \
  1145. "g" ((USItype) (bh)), \
  1146. "%1" ((USItype) (al)), \
  1147. "g" ((USItype) (bl)))
  1148. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1149. __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
  1150. : "=g" ((USItype) (sh)), \
  1151. "=&g" ((USItype) (sl)) \
  1152. : "0" ((USItype) (ah)), \
  1153. "g" ((USItype) (bh)), \
  1154. "1" ((USItype) (al)), \
  1155. "g" ((USItype) (bl)))
  1156. #define umul_ppmm(xh, xl, m0, m1) \
  1157. do { \
  1158. union { \
  1159. UDItype __ll; \
  1160. struct {USItype __l, __h;} __i; \
  1161. } __xx; \
  1162. USItype __m0 = (m0), __m1 = (m1); \
  1163. __asm__ ("emul %1,%2,$0,%0" \
  1164. : "=r" (__xx.__ll) \
  1165. : "g" (__m0), \
  1166. "g" (__m1)); \
  1167. (xh) = __xx.__i.__h; \
  1168. (xl) = __xx.__i.__l; \
  1169. (xh) += ((((SItype) __m0 >> 31) & __m1) \
  1170. + (((SItype) __m1 >> 31) & __m0)); \
  1171. } while (0)
  1172. #define sdiv_qrnnd(q, r, n1, n0, d) \
  1173. do { \
  1174. union {DItype __ll; \
  1175. struct {SItype __l, __h;} __i; \
  1176. } __xx; \
  1177. __xx.__i.__h = n1; __xx.__i.__l = n0; \
  1178. __asm__ ("ediv %3,%2,%0,%1" \
  1179. : "=g" (q), "=g" (r) \
  1180. : "g" (__xx.__ll), "g" (d)); \
  1181. } while (0)
  1182. #endif /* __vax__ */
  1183. #if defined (__xtensa__) && W_TYPE_SIZE == 32
  1184. /* This code is not Xtensa-configuration-specific, so rely on the compiler
  1185. to expand builtin functions depending on what configuration features
  1186. are available. This avoids library calls when the operation can be
  1187. performed in-line. */
  1188. #define umul_ppmm(w1, w0, u, v) \
  1189. do { \
  1190. DWunion __w; \
  1191. __w.ll = __builtin_umulsidi3 (u, v); \
  1192. w1 = __w.s.high; \
  1193. w0 = __w.s.low; \
  1194. } while (0)
  1195. #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
  1196. #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
  1197. #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
  1198. #endif /* __xtensa__ */
  1199. #if defined (__z8000__) && W_TYPE_SIZE == 16
  1200. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1201. __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
  1202. : "=r" ((unsigned int)(sh)), \
  1203. "=&r" ((unsigned int)(sl)) \
  1204. : "%0" ((unsigned int)(ah)), \
  1205. "r" ((unsigned int)(bh)), \
  1206. "%1" ((unsigned int)(al)), \
  1207. "rQR" ((unsigned int)(bl)))
  1208. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1209. __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
  1210. : "=r" ((unsigned int)(sh)), \
  1211. "=&r" ((unsigned int)(sl)) \
  1212. : "0" ((unsigned int)(ah)), \
  1213. "r" ((unsigned int)(bh)), \
  1214. "1" ((unsigned int)(al)), \
  1215. "rQR" ((unsigned int)(bl)))
  1216. #define umul_ppmm(xh, xl, m0, m1) \
  1217. do { \
  1218. union {long int __ll; \
  1219. struct {unsigned int __h, __l;} __i; \
  1220. } __xx; \
  1221. unsigned int __m0 = (m0), __m1 = (m1); \
  1222. __asm__ ("mult %S0,%H3" \
  1223. : "=r" (__xx.__i.__h), \
  1224. "=r" (__xx.__i.__l) \
  1225. : "%1" (__m0), \
  1226. "rQR" (__m1)); \
  1227. (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
  1228. (xh) += ((((signed int) __m0 >> 15) & __m1) \
  1229. + (((signed int) __m1 >> 15) & __m0)); \
  1230. } while (0)
  1231. #endif /* __z8000__ */
  1232. #endif /* __GNUC__ */
  1233. /* If this machine has no inline assembler, use C macros. */
  1234. #if !defined (add_ssaaaa)
  1235. #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
  1236. do { \
  1237. UWtype __x; \
  1238. __x = (al) + (bl); \
  1239. (sh) = (ah) + (bh) + (__x < (al)); \
  1240. (sl) = __x; \
  1241. } while (0)
  1242. #endif
  1243. #if !defined (sub_ddmmss)
  1244. #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
  1245. do { \
  1246. UWtype __x; \
  1247. __x = (al) - (bl); \
  1248. (sh) = (ah) - (bh) - (__x > (al)); \
  1249. (sl) = __x; \
  1250. } while (0)
  1251. #endif
  1252. /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
  1253. smul_ppmm. */
  1254. #if !defined (umul_ppmm) && defined (smul_ppmm)
  1255. #define umul_ppmm(w1, w0, u, v) \
  1256. do { \
  1257. UWtype __w1; \
  1258. UWtype __xm0 = (u), __xm1 = (v); \
  1259. smul_ppmm (__w1, w0, __xm0, __xm1); \
  1260. (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
  1261. + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
  1262. } while (0)
  1263. #endif
  1264. /* If we still don't have umul_ppmm, define it using plain C. */
  1265. #if !defined (umul_ppmm)
  1266. #define umul_ppmm(w1, w0, u, v) \
  1267. do { \
  1268. UWtype __x0, __x1, __x2, __x3; \
  1269. UHWtype __ul, __vl, __uh, __vh; \
  1270. \
  1271. __ul = __ll_lowpart (u); \
  1272. __uh = __ll_highpart (u); \
  1273. __vl = __ll_lowpart (v); \
  1274. __vh = __ll_highpart (v); \
  1275. \
  1276. __x0 = (UWtype) __ul * __vl; \
  1277. __x1 = (UWtype) __ul * __vh; \
  1278. __x2 = (UWtype) __uh * __vl; \
  1279. __x3 = (UWtype) __uh * __vh; \
  1280. \
  1281. __x1 += __ll_highpart (__x0);/* this can't give carry */ \
  1282. __x1 += __x2; /* but this indeed can */ \
  1283. if (__x1 < __x2) /* did we get it? */ \
  1284. __x3 += __ll_B; /* yes, add it in the proper pos. */ \
  1285. \
  1286. (w1) = __x3 + __ll_highpart (__x1); \
  1287. (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
  1288. } while (0)
  1289. #endif
  1290. #if !defined (__umulsidi3)
  1291. #define __umulsidi3(u, v) \
  1292. ({DWunion __w; \
  1293. umul_ppmm (__w.s.high, __w.s.low, u, v); \
  1294. __w.ll; })
  1295. #endif
  1296. /* Define this unconditionally, so it can be used for debugging. */
  1297. #define __udiv_qrnnd_c(q, r, n1, n0, d) \
  1298. do { \
  1299. UWtype __d1, __d0, __q1, __q0; \
  1300. UWtype __r1, __r0, __m; \
  1301. __d1 = __ll_highpart (d); \
  1302. __d0 = __ll_lowpart (d); \
  1303. \
  1304. __r1 = (n1) % __d1; \
  1305. __q1 = (n1) / __d1; \
  1306. __m = (UWtype) __q1 * __d0; \
  1307. __r1 = __r1 * __ll_B | __ll_highpart (n0); \
  1308. if (__r1 < __m) \
  1309. { \
  1310. __q1--, __r1 += (d); \
  1311. if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
  1312. if (__r1 < __m) \
  1313. __q1--, __r1 += (d); \
  1314. } \
  1315. __r1 -= __m; \
  1316. \
  1317. __r0 = __r1 % __d1; \
  1318. __q0 = __r1 / __d1; \
  1319. __m = (UWtype) __q0 * __d0; \
  1320. __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
  1321. if (__r0 < __m) \
  1322. { \
  1323. __q0--, __r0 += (d); \
  1324. if (__r0 >= (d)) \
  1325. if (__r0 < __m) \
  1326. __q0--, __r0 += (d); \
  1327. } \
  1328. __r0 -= __m; \
  1329. \
  1330. (q) = (UWtype) __q1 * __ll_B | __q0; \
  1331. (r) = __r0; \
  1332. } while (0)
  1333. /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
  1334. __udiv_w_sdiv (defined in libgcc or elsewhere). */
  1335. #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
  1336. #define udiv_qrnnd(q, r, nh, nl, d) \
  1337. do { \
  1338. USItype __r; \
  1339. (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
  1340. (r) = __r; \
  1341. } while (0)
  1342. #endif
  1343. /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
  1344. #if !defined (udiv_qrnnd)
  1345. #define UDIV_NEEDS_NORMALIZATION 1
  1346. #define udiv_qrnnd __udiv_qrnnd_c
  1347. #endif
  1348. #if !defined (count_leading_zeros)
  1349. #define count_leading_zeros(count, x) \
  1350. do { \
  1351. UWtype __xr = (x); \
  1352. UWtype __a; \
  1353. \
  1354. if (W_TYPE_SIZE <= 32) \
  1355. { \
  1356. __a = __xr < ((UWtype)1<<2*__BITS4) \
  1357. ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
  1358. : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
  1359. } \
  1360. else \
  1361. { \
  1362. for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
  1363. if (((__xr >> __a) & 0xff) != 0) \
  1364. break; \
  1365. } \
  1366. \
  1367. (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
  1368. } while (0)
  1369. #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
  1370. #endif
  1371. #if !defined (count_trailing_zeros)
  1372. /* Define count_trailing_zeros using count_leading_zeros. The latter might be
  1373. defined in asm, but if it is not, the C version above is good enough. */
  1374. #define count_trailing_zeros(count, x) \
  1375. do { \
  1376. UWtype __ctz_x = (x); \
  1377. UWtype __ctz_c; \
  1378. count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
  1379. (count) = W_TYPE_SIZE - 1 - __ctz_c; \
  1380. } while (0)
  1381. #endif
  1382. #ifndef UDIV_NEEDS_NORMALIZATION
  1383. #define UDIV_NEEDS_NORMALIZATION 0
  1384. #endif