atomic.h 10 KB

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  1. /* Low-level functions for atomic operations. Mips version.
  2. Copyright (C) 2005 Free Software Foundation, Inc.
  3. This file is part of the GNU C Library.
  4. The GNU C Library is free software; you can redistribute it and/or
  5. modify it under the terms of the GNU Lesser General Public
  6. License as published by the Free Software Foundation; either
  7. version 2.1 of the License, or (at your option) any later version.
  8. The GNU C Library is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. Lesser General Public License for more details.
  12. You should have received a copy of the GNU Lesser General Public
  13. License along with the GNU C Library; if not, write to the Free
  14. Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  15. 02111-1307 USA. */
  16. #ifndef _MIPS_BITS_ATOMIC_H
  17. #define _MIPS_BITS_ATOMIC_H 1
  18. #include <inttypes.h>
  19. #include <sgidefs.h>
  20. typedef int32_t atomic32_t;
  21. typedef uint32_t uatomic32_t;
  22. typedef int_fast32_t atomic_fast32_t;
  23. typedef uint_fast32_t uatomic_fast32_t;
  24. typedef int64_t atomic64_t;
  25. typedef uint64_t uatomic64_t;
  26. typedef int_fast64_t atomic_fast64_t;
  27. typedef uint_fast64_t uatomic_fast64_t;
  28. typedef intptr_t atomicptr_t;
  29. typedef uintptr_t uatomicptr_t;
  30. typedef intmax_t atomic_max_t;
  31. typedef uintmax_t uatomic_max_t;
  32. #if _MIPS_SIM == _ABIO32
  33. #define MIPS_PUSH_MIPS2 ".set mips2\n\t"
  34. #else
  35. #define MIPS_PUSH_MIPS2
  36. #endif
  37. /* See the comments in <sys/asm.h> about the use of the sync instruction. */
  38. #ifndef MIPS_SYNC
  39. # define MIPS_SYNC sync
  40. #endif
  41. #define MIPS_SYNC_STR_2(X) #X
  42. #define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
  43. #define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
  44. /* Compare and exchange. For all of the "xxx" routines, we expect a
  45. "__prev" and a "__cmp" variable to be provided by the enclosing scope,
  46. in which values are returned. */
  47. #define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, acq) \
  48. (abort (), __prev = __cmp = 0)
  49. #define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, acq) \
  50. (abort (), __prev = __cmp = 0)
  51. #define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \
  52. __asm__ __volatile__ ( \
  53. ".set push\n\t" \
  54. MIPS_PUSH_MIPS2 \
  55. rel "\n" \
  56. "1:\t" \
  57. "ll %0,%4\n\t" \
  58. "move %1,$0\n\t" \
  59. "bne %0,%2,2f\n\t" \
  60. "move %1,%3\n\t" \
  61. "sc %1,%4\n\t" \
  62. "beqz %1,1b\n" \
  63. acq "\n\t" \
  64. ".set pop\n" \
  65. "2:\n\t" \
  66. : "=&r" (__prev), "=&r" (__cmp) \
  67. : "r" (oldval), "r" (newval), "m" (*mem) \
  68. : "memory")
  69. #if _MIPS_SIM == _ABIO32
  70. /* We can't do an atomic 64-bit operation in O32. */
  71. #define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
  72. (abort (), __prev = __cmp = 0)
  73. #else
  74. #define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
  75. __asm__ __volatile__ ("\n" \
  76. ".set push\n\t" \
  77. MIPS_PUSH_MIPS2 \
  78. rel "\n" \
  79. "1:\t" \
  80. "lld %0,%4\n\t" \
  81. "move %1,$0\n\t" \
  82. "bne %0,%2,2f\n\t" \
  83. "move %1,%3\n\t" \
  84. "scd %1,%4\n\t" \
  85. "beqz %1,1b\n" \
  86. acq "\n\t" \
  87. ".set pop\n" \
  88. "2:\n\t" \
  89. : "=&r" (__prev), "=&r" (__cmp) \
  90. : "r" (oldval), "r" (newval), "m" (*mem) \
  91. : "memory")
  92. #endif
  93. /* For all "bool" routines, we return FALSE if exchange succesful. */
  94. #define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \
  95. ({ __typeof (*mem) __prev; int __cmp; \
  96. __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
  97. !__cmp; })
  98. #define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \
  99. ({ __typeof (*mem) __prev; int __cmp; \
  100. __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
  101. !__cmp; })
  102. #define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \
  103. ({ __typeof (*mem) __prev; int __cmp; \
  104. __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
  105. !__cmp; })
  106. #define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \
  107. ({ __typeof (*mem) __prev; int __cmp; \
  108. __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
  109. !__cmp; })
  110. /* For all "val" routines, return the old value whether exchange
  111. successful or not. */
  112. #define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \
  113. ({ __typeof (*mem) __prev; int __cmp; \
  114. __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
  115. (__typeof (*mem))__prev; })
  116. #define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \
  117. ({ __typeof (*mem) __prev; int __cmp; \
  118. __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
  119. (__typeof (*mem))__prev; })
  120. #define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \
  121. ({ __typeof (*mem) __prev; int __cmp; \
  122. __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
  123. (__typeof (*mem))__prev; })
  124. #define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \
  125. ({ __typeof (*mem) __prev; int __cmp; \
  126. __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
  127. (__typeof (*mem))__prev; })
  128. /* Compare and exchange with "acquire" semantics, ie barrier after. */
  129. #define atomic_compare_and_exchange_bool_acq(mem, new, old) \
  130. __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
  131. mem, new, old, "", MIPS_SYNC_STR)
  132. #define atomic_compare_and_exchange_val_acq(mem, new, old) \
  133. __atomic_val_bysize (__arch_compare_and_exchange_val, int, \
  134. mem, new, old, "", MIPS_SYNC_STR)
  135. /* Compare and exchange with "release" semantics, ie barrier before. */
  136. #define atomic_compare_and_exchange_bool_rel(mem, new, old) \
  137. __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
  138. mem, new, old, MIPS_SYNC_STR, "")
  139. #define atomic_compare_and_exchange_val_rel(mem, new, old) \
  140. __atomic_val_bysize (__arch_compare_and_exchange_val, int, \
  141. mem, new, old, MIPS_SYNC_STR, "")
  142. /* Atomic exchange (without compare). */
  143. #define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \
  144. (abort (), 0)
  145. #define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \
  146. (abort (), 0)
  147. #define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \
  148. ({ __typeof (*mem) __prev; int __cmp; \
  149. __asm__ __volatile__ ("\n" \
  150. ".set push\n\t" \
  151. MIPS_PUSH_MIPS2 \
  152. rel "\n" \
  153. "1:\t" \
  154. "ll %0,%3\n\t" \
  155. "move %1,%2\n\t" \
  156. "sc %1,%3\n\t" \
  157. "beqz %1,1b\n" \
  158. acq "\n\t" \
  159. ".set pop\n" \
  160. "2:\n\t" \
  161. : "=&r" (__prev), "=&r" (__cmp) \
  162. : "r" (newval), "m" (*mem) \
  163. : "memory"); \
  164. __prev; })
  165. #if _MIPS_SIM == _ABIO32
  166. /* We can't do an atomic 64-bit operation in O32. */
  167. #define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
  168. (abort (), 0)
  169. #else
  170. #define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
  171. ({ __typeof (*mem) __prev; int __cmp; \
  172. __asm__ __volatile__ ("\n" \
  173. ".set push\n\t" \
  174. MIPS_PUSH_MIPS2 \
  175. rel "\n" \
  176. "1:\n" \
  177. "lld %0,%3\n\t" \
  178. "move %1,%2\n\t" \
  179. "scd %1,%3\n\t" \
  180. "beqz %1,1b\n" \
  181. acq "\n\t" \
  182. ".set pop\n" \
  183. "2:\n\t" \
  184. : "=&r" (__prev), "=&r" (__cmp) \
  185. : "r" (newval), "m" (*mem) \
  186. : "memory"); \
  187. __prev; })
  188. #endif
  189. #define atomic_exchange_acq(mem, value) \
  190. __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, "", MIPS_SYNC_STR)
  191. #define atomic_exchange_rel(mem, value) \
  192. __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, MIPS_SYNC_STR, "")
  193. /* Atomically add value and return the previous (unincremented) value. */
  194. #define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \
  195. (abort (), (__typeof(*mem)) 0)
  196. #define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \
  197. (abort (), (__typeof(*mem)) 0)
  198. #define __arch_exchange_and_add_32_int(mem, value, rel, acq) \
  199. ({ __typeof (*mem) __prev; int __cmp; \
  200. __asm__ __volatile__ ("\n" \
  201. ".set push\n\t" \
  202. MIPS_PUSH_MIPS2 \
  203. rel "\n" \
  204. "1:\t" \
  205. "ll %0,%3\n\t" \
  206. "addu %1,%0,%2\n\t" \
  207. "sc %1,%3\n\t" \
  208. "beqz %1,1b\n" \
  209. acq "\n\t" \
  210. ".set pop\n" \
  211. "2:\n\t" \
  212. : "=&r" (__prev), "=&r" (__cmp) \
  213. : "r" (value), "m" (*mem) \
  214. : "memory"); \
  215. __prev; })
  216. #if _MIPS_SIM == _ABIO32
  217. /* We can't do an atomic 64-bit operation in O32. */
  218. #define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
  219. (abort (), (__typeof(*mem)) 0)
  220. #else
  221. #define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
  222. ({ __typeof (*mem) __prev; int __cmp; \
  223. __asm__ __volatile__ ( \
  224. ".set push\n\t" \
  225. MIPS_PUSH_MIPS2 \
  226. rel "\n" \
  227. "1:\t" \
  228. "lld %0,%3\n\t" \
  229. "daddu %1,%0,%2\n\t" \
  230. "scd %1,%3\n\t" \
  231. "beqz %1,1b\n" \
  232. acq "\n\t" \
  233. ".set pop\n" \
  234. "2:\n\t" \
  235. : "=&r" (__prev), "=&r" (__cmp) \
  236. : "r" (value), "m" (*mem) \
  237. : "memory"); \
  238. __prev; })
  239. #endif
  240. /* ??? Barrier semantics for atomic_exchange_and_add appear to be
  241. undefined. Use full barrier for now, as that's safe. */
  242. #define atomic_exchange_and_add(mem, value) \
  243. __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
  244. MIPS_SYNC_STR, MIPS_SYNC_STR)
  245. /* TODO: More atomic operations could be implemented efficiently; only the
  246. basic requirements are done. */
  247. #define atomic_full_barrier() \
  248. __asm__ __volatile__ (".set push\n\t" \
  249. MIPS_PUSH_MIPS2 \
  250. MIPS_SYNC_STR "\n\t" \
  251. ".set pop" : : : "memory")
  252. #endif /* bits/atomic.h */