unistd.h 16 KB

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  1. /* This file is lisenced under LGPL.
  2. * Copyright (C) 2002-2003, George Thanos <george.thanos@gdt.gr>
  3. * Yannis Mitsos <yannis.mitsos@gdt.gr>
  4. */
  5. #ifndef _BITS_UNISTD_H_
  6. #define _BITS_UNISTD_H_
  7. #include <bits/proto.h>
  8. #include <errno.h>
  9. #define __E1_COFF_GCC__
  10. /* The following macros have been provided by C.Baumhof
  11. * They can be inlined in contrast to the previous ones*/
  12. #define _syscall0(type, name) \
  13. type name(void) \
  14. { \
  15. register int par1 __asm__("L15"); \
  16. register int par2 __asm__("L14"); \
  17. par1 = -1; \
  18. par2 = __NR_##name; \
  19. __asm__ __volatile__( \
  20. "trap 47" \
  21. :"=l"(par1) \
  22. :"0"(par1), "l"(par2) \
  23. :"memory","L14","L15"); \
  24. \
  25. if( par1 < 0 ) { \
  26. __set_errno( -par1 ); \
  27. return -1; \
  28. } else \
  29. return (type)(par1); \
  30. }
  31. #define _syscall1(type, name,atype, a) \
  32. type name(atype a) \
  33. { \
  34. register int par1 __asm__("L15"); \
  35. register int par2 __asm__("L14"); \
  36. register int par3 __asm__("L13"); \
  37. par1 = -1; \
  38. par2 = __NR_##name; \
  39. par3 = (int)a; \
  40. __asm__ __volatile__( \
  41. "trap 47" \
  42. :"=l"(par1) \
  43. :"0"(par1), "l"(par2), "l"(par3) \
  44. :"memory","L13","L14","L15"); \
  45. \
  46. if( par1 < 0 ) { \
  47. __set_errno( -par1 ); \
  48. return -1; \
  49. } else \
  50. return (type)(par1); \
  51. }
  52. #define _syscall2(type, name,atype, a, btype, b) \
  53. type name(atype a, btype b) \
  54. { \
  55. register int par1 __asm__("L15"); \
  56. register int par2 __asm__("L14"); \
  57. register int par3 __asm__("L13"); \
  58. register int par4 __asm__("L12"); \
  59. par1 = -1; \
  60. par2 = __NR_##name; \
  61. par3 = (int)a; \
  62. par4 = (int)b; \
  63. __asm__ __volatile__( \
  64. "trap 47" \
  65. :"=l"(par1) \
  66. :"0"(par1), "l"(par2), "l"(par3), "l"(par4) \
  67. :"memory","L12","L13","L14","L15"); \
  68. \
  69. if( par1 < 0 ) { \
  70. __set_errno( -par1 ); \
  71. return -1; \
  72. } else \
  73. return (type)(par1); \
  74. }
  75. #define _syscall3(type, name,atype, a, btype, b, ctype, c) \
  76. type name(atype a, btype b, ctype c) \
  77. { \
  78. register int par1 __asm__("L15"); \
  79. register int par2 __asm__("L14"); \
  80. register int par3 __asm__("L13"); \
  81. register int par4 __asm__("L12"); \
  82. register int par5 __asm__("L11"); \
  83. par1 = -1; \
  84. par2 = __NR_##name; \
  85. par3 = (int)a; \
  86. par4 = (int)b; \
  87. par5 = (int)c; \
  88. __asm__ __volatile__( \
  89. "trap 47" \
  90. :"=l"(par1) \
  91. :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
  92. :"memory","L11","L12","L13","L14","L15"); \
  93. \
  94. if( par1 < 0 ) { \
  95. __set_errno( -par1 ); \
  96. return -1; \
  97. } else \
  98. return (type)(par1); \
  99. }
  100. #define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
  101. type name(atype a, btype b, ctype c,dtype d) \
  102. { \
  103. register int par1 __asm__("L15"); \
  104. register int par2 __asm__("L14"); \
  105. register int par3 __asm__("L13"); \
  106. register int par4 __asm__("L12"); \
  107. register int par5 __asm__("L11"); \
  108. register int par6 __asm__("L10"); \
  109. par1 = -1; \
  110. par2 = __NR_##name; \
  111. par3 = (int)a; \
  112. par4 = (int)b; \
  113. par5 = (int)c; \
  114. par6 = (int)d; \
  115. __asm__ __volatile__( \
  116. "trap 47" \
  117. :"=l"(par1) \
  118. :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
  119. :"memory","L10","L11","L12","L13","L14","L15"); \
  120. \
  121. if( par1 < 0 ) { \
  122. __set_errno( -par1 ); \
  123. return -1; \
  124. } else \
  125. return (type)(par1); \
  126. }
  127. #define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
  128. type name(atype a, btype b, ctype c,dtype d, etype e) \
  129. { \
  130. register int par1 __asm__("L15"); \
  131. register int par2 __asm__("L14"); \
  132. register int par3 __asm__("L13"); \
  133. register int par4 __asm__("L12"); \
  134. register int par5 __asm__("L11"); \
  135. register int par6 __asm__("L10"); \
  136. register int par7 __asm__("L9"); \
  137. par1 = -1; \
  138. par2 = __NR_##name; \
  139. par3 = (int)a; \
  140. par4 = (int)b; \
  141. par5 = (int)c; \
  142. par6 = (int)d; \
  143. par7 = (int)e; \
  144. __asm__ __volatile__( \
  145. "trap 47" \
  146. :"=l"(par1) \
  147. :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
  148. :"memory","L9","L10","L11","L12","L13","L14","L15"); \
  149. \
  150. if( par1 < 0 ) { \
  151. __set_errno( -par1 ); \
  152. return -1; \
  153. } else \
  154. return (type)(par1); \
  155. return (type)(par1); \
  156. }
  157. #define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
  158. type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
  159. { \
  160. register int par1 __asm__("L15"); \
  161. register int par2 __asm__("L14"); \
  162. register int par3 __asm__("L13"); \
  163. register int par4 __asm__("L12"); \
  164. register int par5 __asm__("L11"); \
  165. register int par6 __asm__("L10"); \
  166. register int par7 __asm__("L9"); \
  167. register int par8 __asm__("L8"); \
  168. int sys_retval; \
  169. par1 = -1; \
  170. par2 = __NR_##name; \
  171. par3 = (int)a; \
  172. par4 = (int)b; \
  173. par5 = (int)c; \
  174. par6 = (int)d; \
  175. par7 = (int)e; \
  176. par7 = (int)f; \
  177. __asm__ __volatile__( \
  178. "trap 47" \
  179. :"=l"(par1) \
  180. :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
  181. :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
  182. \
  183. if( par1 < 0 ) { \
  184. __set_errno( -par1 ); \
  185. return -1; \
  186. } else \
  187. return (type)(par1); \
  188. }
  189. #define __syscall0(type, name) \
  190. type name(...) \
  191. { \
  192. register int par1 __asm__("L15"); \
  193. register int par2 __asm__("L14"); \
  194. par1 = -1; \
  195. par2 = __NR_##name; \
  196. __asm__ __volatile__( \
  197. "trap 47" \
  198. :"=l"(par1) \
  199. :"0"(par1), "l"(par2)\
  200. :"memory","L14","L15"); \
  201. \
  202. if( par1 < 0 ) { \
  203. __set_errno( -par1 ); \
  204. return -1; \
  205. } else \
  206. return (type)(par1); \
  207. }
  208. #define __syscall1(type, name, atype, a) \
  209. type name(atype a, ...) \
  210. { \
  211. register int par1 __asm__("L15"); \
  212. register int par2 __asm__("L14"); \
  213. register int par3 __asm__("L13"); \
  214. par1 = -1; \
  215. par2 = __NR_##name; \
  216. par3 = (int)a; \
  217. __asm__ __volatile__( \
  218. "trap 47" \
  219. :"=l"(par1) \
  220. :"0"(par1), "l"(par2), "l"(par3)\
  221. :"memory","L13","L14","L15"); \
  222. \
  223. if( par1 < 0 ) { \
  224. __set_errno( -par1 ); \
  225. return -1; \
  226. } else \
  227. return (type)(par1); \
  228. }
  229. #define __syscall2(type, name,atype, a, btype, b) \
  230. type name(atype a, btype b, ...) \
  231. { \
  232. register int par1 __asm__("L15"); \
  233. register int par2 __asm__("L14"); \
  234. register int par3 __asm__("L13"); \
  235. register int par4 __asm__("L12"); \
  236. par1 = -1; \
  237. par2 = __NR_##name; \
  238. par3 = (int)a; \
  239. par4 = (int)b; \
  240. __asm__ __volatile__( \
  241. "trap 47" \
  242. :"=l"(par1) \
  243. :"0"(par1), "l"(par2), "l"(par3), "l"(par4)\
  244. :"memory","L12","L13","L14","L15"); \
  245. \
  246. if( par1 < 0 ) { \
  247. __set_errno( -par1 ); \
  248. return -1; \
  249. } else \
  250. return (type)(par1); \
  251. }
  252. #define __syscall3(type, name,atype, a, btype, b, ctype, c) \
  253. type name(atype a, btype b, ctype c, ...) \
  254. { \
  255. register int par1 __asm__("L15"); \
  256. register int par2 __asm__("L14"); \
  257. register int par3 __asm__("L13"); \
  258. register int par4 __asm__("L12"); \
  259. register int par5 __asm__("L11"); \
  260. par1 = -1; \
  261. par2 = __NR_##name; \
  262. par3 = (int)a; \
  263. par4 = (int)b; \
  264. par5 = (int)c; \
  265. __asm__ __volatile__( \
  266. "trap 47" \
  267. :"=l"(par1) \
  268. :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
  269. :"memory","L11","L12","L13","L14","L15"); \
  270. \
  271. if( par1 < 0 ) { \
  272. __set_errno( -par1 ); \
  273. return -1; \
  274. } else \
  275. return (type)(par1); \
  276. }
  277. #define __syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
  278. type name(atype a, btype b, ctype c,dtype d, ...) \
  279. { \
  280. register int par1 __asm__("L15"); \
  281. register int par2 __asm__("L14"); \
  282. register int par3 __asm__("L13"); \
  283. register int par4 __asm__("L12"); \
  284. register int par5 __asm__("L11"); \
  285. register int par6 __asm__("L10"); \
  286. par1 = -1; \
  287. par2 = __NR_##name; \
  288. par3 = (int)a; \
  289. par4 = (int)b; \
  290. par5 = (int)c; \
  291. par6 = (int)d; \
  292. __asm__ __volatile__( \
  293. "trap 47" \
  294. :"=l"(par1) \
  295. :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
  296. :"memory","L10","L11","L12","L13","L14","L15"); \
  297. \
  298. if( par1 < 0 ) { \
  299. __set_errno( -par1 ); \
  300. return -1; \
  301. } else \
  302. return (type)(par1); \
  303. }
  304. #define __syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
  305. type name(atype a, btype b, ctype c,dtype d, etype e, ...) \
  306. { \
  307. register int par1 __asm__("L15"); \
  308. register int par2 __asm__("L14"); \
  309. register int par3 __asm__("L13"); \
  310. register int par4 __asm__("L12"); \
  311. register int par5 __asm__("L11"); \
  312. register int par6 __asm__("L10"); \
  313. register int par7 __asm__("L9"); \
  314. par1 = -1; \
  315. par2 = __NR_##name; \
  316. par3 = (int)a; \
  317. par4 = (int)b; \
  318. par5 = (int)c; \
  319. par6 = (int)d; \
  320. par7 = (int)e; \
  321. __asm__ __volatile__( \
  322. "trap 47" \
  323. :"=l"(par1) \
  324. :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
  325. :"memory","L9","L10","L11","L12","L13","L14","L15"); \
  326. \
  327. if( par1 < 0 ) { \
  328. __set_errno( -par1 ); \
  329. return -1; \
  330. } else \
  331. return (type)(par1); \
  332. }
  333. #define __syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
  334. type name(atype a, btype b, ctype c,dtype d, etype e, ftype f, ...) \
  335. { \
  336. register int par1 __asm__("L15"); \
  337. register int par2 __asm__("L14"); \
  338. register int par3 __asm__("L13"); \
  339. register int par4 __asm__("L12"); \
  340. register int par5 __asm__("L11"); \
  341. register int par6 __asm__("L10"); \
  342. register int par7 __asm__("L9"); \
  343. register int par8 __asm__("L8"); \
  344. par1 = -1; \
  345. par2 = __NR_##name; \
  346. par3 = (int)a; \
  347. par4 = (int)b; \
  348. par5 = (int)c; \
  349. par6 = (int)d; \
  350. par7 = (int)e; \
  351. par7 = (int)f; \
  352. __asm__ __volatile__( \
  353. "trap 47" \
  354. :"=l"(par1) \
  355. :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
  356. :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
  357. \
  358. if( par1 < 0 ) { \
  359. __set_errno( -par1 ); \
  360. return -1; \
  361. } else \
  362. return (type)(par1); \
  363. }
  364. #include <sys/types.h>
  365. /* Taken from <bits/errno.h> */
  366. #ifndef _LIBC
  367. /* We don't support pthreads for the moment*/
  368. #define __set_errno(val) ((errno) = (val))
  369. #endif
  370. #if 0
  371. #define _syscall3(type, name,atype, a , btype, b, ctype, c) \
  372. type name(atype a, btype b, ctype c,) \
  373. { \
  374. __asm__ __volatile__( \
  375. "movi L9, -1\n\t" \
  376. "movi L8, %0\n\t" \
  377. "ldw.d G3, L7, 0\n\t" \
  378. "ldw.d G3, L6, 4\n\t" \
  379. "ldw.d G3, L5, 8\n\t" \
  380. :/* no output */ \
  381. :"i"(__NR_##name) \
  382. :"cc","memory","%L5","L6","L7","L8","L9");\
  383. __asm__ __volatile__( \
  384. "trap 47\n\t" \
  385. "mov L2, L9\n\t"); \
  386. }
  387. #define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
  388. type name(atype a, btype b, ctype c,dtype d) \
  389. { \
  390. __asm__ __volatile__( \
  391. "movi L11, -1\n\t" \
  392. "movi L10, %0\n\t" \
  393. "ldw.d G3, L9, 0\n\t" \
  394. "ldw.d G3, L8, 4\n\t" \
  395. "ldw.d G3, L7, 8\n\t" \
  396. "ldw.d G3, L6, 12\n\t" \
  397. :/* no output */ \
  398. :"i"(__NR_##name) \
  399. :"cc","memory","L6","L7","L8","L9","L10","L11");\
  400. __asm__ __volatile__( \
  401. "trap 47\n\t" \
  402. "mov L2, L11\n\t"); \
  403. }
  404. #define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
  405. type name(atype a, btype b, ctype c,dtype d, etype e) \
  406. { \
  407. __asm__ __volatile__( \
  408. "movi L13, -1\n\t" \
  409. "movi L12, %0\n\t" \
  410. "ldw.d G3, L11, 0\n\t" \
  411. "ldw.d G3, L10, 4\n\t" \
  412. "ldw.d G3, L9, 8\n\t" \
  413. "ldw.d G3, L8, 12\n\t" \
  414. "ldw.d G3, L7, 16\n\t" \
  415. :/* no output */ \
  416. :"i"(__NR_##name) \
  417. :"cc","memory","L7","L8","L9","L10","L11","L12","L13");\
  418. __asm__ __volatile__( \
  419. "trap 47\n\t" \
  420. "mov L2, L13\n\t"); \
  421. }
  422. #define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
  423. type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
  424. { \
  425. __asm__ __volatile__( \
  426. "movi L15, -1\n\t" \
  427. "movi L14, %0\n\t" \
  428. "ldw.d G3, L13, 0\n\t" \
  429. "ldw.d G3, L12, 4\n\t" \
  430. "ldw.d G3, L11, 8\n\t" \
  431. "ldw.d G3, L10, 12\n\t" \
  432. "ldw.d G3, L9, 16\n\t" \
  433. "ldw.d G3, L8, 20\n\t" \
  434. :/* no output */ \
  435. :"i"(__NR_##name) \
  436. :"cc","memory","L8","L9","L10","L11","L12","L13","L14","L15");\
  437. __asm__ __volatile__( \
  438. "trap 47\n\t" \
  439. "mov L2, L15\n\t"); \
  440. }
  441. #endif
  442. #endif /* !_HYPERSTONE_NOMMU_UNISTD_H_ */