asm.h 12 KB

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  1. /* Copyright (C) 1997, 1998, 2002, 2003 Free Software Foundation, Inc.
  2. This file is part of the GNU C Library.
  3. Contributed by Ralf Baechle <ralf@gnu.org>.
  4. The GNU C Library is free software; you can redistribute it and/or
  5. modify it under the terms of the GNU Lesser General Public
  6. License as published by the Free Software Foundation; either
  7. version 2.1 of the License, or (at your option) any later version.
  8. The GNU C Library is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. Lesser General Public License for more details.
  12. You should have received a copy of the GNU Lesser General Public
  13. License along with the GNU C Library; if not, write to the Free
  14. Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  15. 02111-1307 USA. */
  16. #ifndef _SYS_ASM_H
  17. #define _SYS_ASM_H
  18. #include <sgidefs.h>
  19. #ifndef CAT
  20. # ifdef __STDC__
  21. # define __CAT(str1,str2) str1##str2
  22. # else
  23. # define __CAT(str1,str2) str1/**/str2
  24. # endif
  25. # define CAT(str1,str2) __CAT(str1,str2)
  26. #endif
  27. /*
  28. * Macros to handle different pointer/register sizes for 32/64-bit code
  29. *
  30. * 64 bit address space isn't used yet, so we may use the R3000 32 bit
  31. * defines for now.
  32. */
  33. #if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
  34. # define PTR .word
  35. # define PTRSIZE 4
  36. # define PTRLOG 2
  37. #elif (_MIPS_SIM == _MIPS_SIM_ABI64)
  38. # define PTR .dword
  39. # define PTRSIZE 8
  40. # define PTRLOG 3
  41. #endif
  42. /*
  43. * PIC specific declarations
  44. */
  45. #if (_MIPS_SIM == _MIPS_SIM_ABI32)
  46. # ifdef __PIC__
  47. # define CPRESTORE(register) \
  48. .cprestore register
  49. # define CPLOAD(register) \
  50. .cpload register
  51. # else
  52. # define CPRESTORE(register)
  53. # define CPLOAD(register)
  54. # endif
  55. # define CPADD(register) \
  56. .cpadd register
  57. /*
  58. * Set gp when at 1st instruction
  59. */
  60. # define SETUP_GP \
  61. .set noreorder; \
  62. .cpload $25; \
  63. .set reorder
  64. /* Set gp when not at 1st instruction */
  65. # define SETUP_GPX(r) \
  66. .set noreorder; \
  67. move r, $31; /* Save old ra. */ \
  68. bal 10f; /* Find addr of cpload. */ \
  69. nop; \
  70. 10: \
  71. .cpload $31; \
  72. move $31, r; \
  73. .set reorder
  74. # define SETUP_GPX_L(r, l) \
  75. .set noreorder; \
  76. move r, $31; /* Save old ra. */ \
  77. bal l; /* Find addr of cpload. */ \
  78. nop; \
  79. l: \
  80. .cpload $31; \
  81. move $31, r; \
  82. .set reorder
  83. # define SAVE_GP(x) \
  84. .cprestore x /* Save gp trigger t9/jalr conversion. */
  85. # define SETUP_GP64(a, b)
  86. # define SETUP_GPX64(a, b)
  87. # define SETUP_GPX64_L(cp_reg, ra_save, l)
  88. # define RESTORE_GP64
  89. # define USE_ALT_CP(a)
  90. # define L(label) $L ## label
  91. #else /* (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32) */
  92. /*
  93. * For callee-saved gp calling convention:
  94. */
  95. # define SETUP_GP
  96. # define SETUP_GPX(r)
  97. # define SETUP_GPX_L(r, l)
  98. # define SAVE_GP(x)
  99. # define SETUP_GP64(gpoffset, proc) \
  100. .cpsetup $25, gpoffset, proc
  101. # define SETUP_GPX64(cp_reg, ra_save) \
  102. move ra_save, $31; /* Save old ra. */ \
  103. .set noreorder; \
  104. bal 10f; /* Find addr of .cpsetup. */ \
  105. nop; \
  106. 10: \
  107. .set reorder; \
  108. .cpsetup $31, cp_reg, 10b; \
  109. move $31, ra_save
  110. # define SETUP_GPX64_L(cp_reg, ra_save, l) \
  111. move ra_save, $31; /* Save old ra. */ \
  112. .set noreorder; \
  113. bal l; /* Find addr of .cpsetup. */ \
  114. nop; \
  115. l: \
  116. .set reorder; \
  117. .cpsetup $31, cp_reg, l; \
  118. move $31, ra_save
  119. # define RESTORE_GP64 \
  120. .cpreturn
  121. /* Use alternate register for context pointer. */
  122. # define USE_ALT_CP(reg) \
  123. .cplocal reg
  124. # define L(label) .L ## label
  125. #endif /* _MIPS_SIM != _MIPS_SIM_ABI32 */
  126. /*
  127. * Stack Frame Definitions
  128. */
  129. #if (_MIPS_SIM == _MIPS_SIM_ABI32)
  130. # define NARGSAVE 4 /* Space for 4 argument registers must be allocated. */
  131. #endif
  132. #if (_MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32)
  133. # define NARGSAVE 0 /* No caller responsibilities. */
  134. #endif
  135. /*
  136. * LEAF - declare leaf routine
  137. */
  138. #define LEAF(symbol) \
  139. .globl symbol; \
  140. .align 2; \
  141. .type symbol,@function; \
  142. .ent symbol,0; \
  143. symbol: .frame sp,0,ra
  144. /*
  145. * NESTED - declare nested routine entry point
  146. */
  147. #define NESTED(symbol, framesize, rpc) \
  148. .globl symbol; \
  149. .align 2; \
  150. .type symbol,@function; \
  151. .ent symbol,0; \
  152. symbol: .frame sp, framesize, rpc
  153. /*
  154. * END - mark end of function
  155. */
  156. #ifndef END
  157. # define END(function) \
  158. .end function; \
  159. .size function,.-function
  160. #endif
  161. /*
  162. * EXPORT - export definition of symbol
  163. */
  164. #define EXPORT(symbol) \
  165. .globl symbol; \
  166. symbol:
  167. /*
  168. * ABS - export absolute symbol
  169. */
  170. #define ABS(symbol,value) \
  171. .globl symbol; \
  172. symbol = value
  173. #define PANIC(msg) \
  174. .set push; \
  175. .set reorder; \
  176. la a0,8f; \
  177. jal panic; \
  178. 9: b 9b; \
  179. .set pop; \
  180. TEXT(msg)
  181. /*
  182. * Print formated string
  183. */
  184. #define PRINT(string) \
  185. .set push; \
  186. .set reorder; \
  187. la a0,8f; \
  188. jal printk; \
  189. .set pop; \
  190. TEXT(string)
  191. #define TEXT(msg) \
  192. .data; \
  193. 8: .asciiz msg; \
  194. .previous;
  195. /*
  196. * Build text tables
  197. */
  198. #define TTABLE(string) \
  199. .text; \
  200. .word 1f; \
  201. .previous; \
  202. .data; \
  203. 1: .asciz string; \
  204. .previous
  205. /*
  206. * MIPS IV pref instruction.
  207. * Use with .set noreorder only!
  208. *
  209. * MIPS IV implementations are free to treat this as a nop. The R5000
  210. * is one of them. So we should have an option not to use this instruction.
  211. */
  212. #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
  213. (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
  214. # define PREF(hint,addr) \
  215. pref hint,addr
  216. # define PREFX(hint,addr) \
  217. prefx hint,addr
  218. #else
  219. # define PREF
  220. # define PREFX
  221. #endif
  222. /*
  223. * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
  224. */
  225. #if _MIPS_ISA == _MIPS_ISA_MIPS1
  226. # define MOVN(rd,rs,rt) \
  227. .set push; \
  228. .set reorder; \
  229. beqz rt,9f; \
  230. move rd,rs; \
  231. .set pop; \
  232. 9:
  233. # define MOVZ(rd,rs,rt) \
  234. .set push; \
  235. .set reorder; \
  236. bnez rt,9f; \
  237. move rd,rt; \
  238. .set pop; \
  239. 9:
  240. #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
  241. #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
  242. # define MOVN(rd,rs,rt) \
  243. .set push; \
  244. .set noreorder; \
  245. bnezl rt,9f; \
  246. move rd,rs; \
  247. .set pop; \
  248. 9:
  249. # define MOVZ(rd,rs,rt) \
  250. .set push; \
  251. .set noreorder; \
  252. beqzl rt,9f; \
  253. movz rd,rs; \
  254. .set pop; \
  255. 9:
  256. #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
  257. #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
  258. (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
  259. # define MOVN(rd,rs,rt) \
  260. movn rd,rs,rt
  261. # define MOVZ(rd,rs,rt) \
  262. movz rd,rs,rt
  263. #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
  264. /*
  265. * Stack alignment
  266. */
  267. #if (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32)
  268. # define ALSZ 15
  269. # define ALMASK ~15
  270. #else
  271. # define ALSZ 7
  272. # define ALMASK ~7
  273. #endif
  274. /*
  275. * Size of a register
  276. */
  277. #if (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32)
  278. # define SZREG 8
  279. #else
  280. # define SZREG 4
  281. #endif
  282. /*
  283. * Use the following macros in assemblercode to load/store registers,
  284. * pointers etc.
  285. */
  286. #if (SZREG == 4)
  287. # define REG_S sw
  288. # define REG_L lw
  289. #else
  290. # define REG_S sd
  291. # define REG_L ld
  292. #endif
  293. /*
  294. * How to add/sub/load/store/shift C int variables.
  295. */
  296. #if (_MIPS_SZINT == 32)
  297. # define INT_ADD add
  298. # define INT_ADDI addi
  299. # define INT_ADDU addu
  300. # define INT_ADDIU addiu
  301. # define INT_SUB add
  302. # define INT_SUBI subi
  303. # define INT_SUBU subu
  304. # define INT_SUBIU subu
  305. # define INT_L lw
  306. # define INT_S sw
  307. #endif
  308. #if (_MIPS_SZINT == 64)
  309. # define INT_ADD dadd
  310. # define INT_ADDI daddi
  311. # define INT_ADDU daddu
  312. # define INT_ADDIU daddiu
  313. # define INT_SUB dadd
  314. # define INT_SUBI dsubi
  315. # define INT_SUBU dsubu
  316. # define INT_SUBIU dsubu
  317. # define INT_L ld
  318. # define INT_S sd
  319. #endif
  320. /*
  321. * How to add/sub/load/store/shift C long variables.
  322. */
  323. #if (_MIPS_SZLONG == 32)
  324. # define LONG_ADD add
  325. # define LONG_ADDI addi
  326. # define LONG_ADDU addu
  327. # define LONG_ADDIU addiu
  328. # define LONG_SUB add
  329. # define LONG_SUBI subi
  330. # define LONG_SUBU subu
  331. # define LONG_SUBIU subu
  332. # define LONG_L lw
  333. # define LONG_S sw
  334. # define LONG_SLL sll
  335. # define LONG_SLLV sllv
  336. # define LONG_SRL srl
  337. # define LONG_SRLV srlv
  338. # define LONG_SRA sra
  339. # define LONG_SRAV srav
  340. #endif
  341. #if (_MIPS_SZLONG == 64)
  342. # define LONG_ADD dadd
  343. # define LONG_ADDI daddi
  344. # define LONG_ADDU daddu
  345. # define LONG_ADDIU daddiu
  346. # define LONG_SUB dadd
  347. # define LONG_SUBI dsubi
  348. # define LONG_SUBU dsubu
  349. # define LONG_SUBIU dsubu
  350. # define LONG_L ld
  351. # define LONG_S sd
  352. # define LONG_SLL dsll
  353. # define LONG_SLLV dsllv
  354. # define LONG_SRL dsrl
  355. # define LONG_SRLV dsrlv
  356. # define LONG_SRA dsra
  357. # define LONG_SRAV dsrav
  358. #endif
  359. /*
  360. * How to add/sub/load/store/shift pointers.
  361. */
  362. #if (_MIPS_SIM == _MIPS_SIM_ABI32 && _MIPS_SZPTR == 32)
  363. # define PTR_ADD add
  364. # define PTR_ADDI addi
  365. # define PTR_ADDU addu
  366. # define PTR_ADDIU addiu
  367. # define PTR_SUB add
  368. # define PTR_SUBI subi
  369. # define PTR_SUBU subu
  370. # define PTR_SUBIU subu
  371. # define PTR_L lw
  372. # define PTR_LA la
  373. # define PTR_S sw
  374. # define PTR_SLL sll
  375. # define PTR_SLLV sllv
  376. # define PTR_SRL srl
  377. # define PTR_SRLV srlv
  378. # define PTR_SRA sra
  379. # define PTR_SRAV srav
  380. # define PTR_SCALESHIFT 2
  381. #endif
  382. #if _MIPS_SIM == _MIPS_SIM_NABI32
  383. # define PTR_ADD add
  384. # define PTR_ADDI addi
  385. # define PTR_ADDU add /* no u */
  386. # define PTR_ADDIU addi /* no u */
  387. # define PTR_SUB add
  388. # define PTR_SUBI subi
  389. # define PTR_SUBU sub /* no u */
  390. # define PTR_SUBIU sub /* no u */
  391. # define PTR_L lw
  392. # define PTR_LA la
  393. # define PTR_S sw
  394. # define PTR_SLL sll
  395. # define PTR_SLLV sllv
  396. # define PTR_SRL srl
  397. # define PTR_SRLV srlv
  398. # define PTR_SRA sra
  399. # define PTR_SRAV srav
  400. # define PTR_SCALESHIFT 2
  401. #endif
  402. #if (_MIPS_SIM == _MIPS_SIM_ABI32 && _MIPS_SZPTR == 64 /* o64??? */) \
  403. || _MIPS_SIM == _MIPS_SIM_ABI64
  404. # define PTR_ADD dadd
  405. # define PTR_ADDI daddi
  406. # define PTR_ADDU daddu
  407. # define PTR_ADDIU daddiu
  408. # define PTR_SUB dadd
  409. # define PTR_SUBI dsubi
  410. # define PTR_SUBU dsubu
  411. # define PTR_SUBIU dsubu
  412. # define PTR_L ld
  413. # define PTR_LA dla
  414. # define PTR_S sd
  415. # define PTR_SLL dsll
  416. # define PTR_SLLV dsllv
  417. # define PTR_SRL dsrl
  418. # define PTR_SRLV dsrlv
  419. # define PTR_SRA dsra
  420. # define PTR_SRAV dsrav
  421. # define PTR_SCALESHIFT 3
  422. #endif
  423. /*
  424. * Some cp0 registers were extended to 64bit for MIPS III.
  425. */
  426. #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
  427. (_MIPS_ISA == _MIPS_ISA_MIPS32)
  428. # define MFC0 mfc0
  429. # define MTC0 mtc0
  430. #endif
  431. #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
  432. (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
  433. # define MFC0 dmfc0
  434. # define MTC0 dmtc0
  435. #endif
  436. /* The MIPS archtectures do not have a uniform memory model. Particular
  437. platforms may provide additional guarantees - for instance, the R4000
  438. LL and SC instructions implicitly perform a SYNC, and the 4K promises
  439. strong ordering.
  440. However, in the absence of those guarantees, we must assume weak ordering
  441. and SYNC explicitly where necessary.
  442. Some obsolete MIPS processors may not support the SYNC instruction. This
  443. applies to "true" MIPS I processors; most of the processors which compile
  444. using MIPS I implement parts of MIPS II. */
  445. #ifndef MIPS_SYNC
  446. # define MIPS_SYNC sync
  447. #endif
  448. #endif /* sys/asm.h */