atomic.h 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120
  1. /*
  2. * Copyright (C) 2007 Atmel Corporation
  3. *
  4. * This file is subject to the terms and conditions of the GNU Lesser General
  5. * Public License. See the file "COPYING.LIB" in the main directory of this
  6. * archive for more details.
  7. */
  8. #ifndef _AVR32_BITS_ATOMIC_H
  9. #define _AVR32_BITS_ATOMIC_H 1
  10. #include <inttypes.h>
  11. typedef int32_t atomic32_t;
  12. typedef uint32_t uatomic32_t;
  13. typedef int_fast32_t atomic_fast32_t;
  14. typedef uint_fast32_t uatomic_fast32_t;
  15. typedef intptr_t atomicptr_t;
  16. typedef uintptr_t uatomicptr_t;
  17. typedef intmax_t atomic_max_t;
  18. typedef uintmax_t uatomic_max_t;
  19. #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
  20. (abort(), 0)
  21. #define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
  22. (abort(), 0)
  23. #define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
  24. ({ \
  25. __typeof__(*(mem)) __prev; \
  26. __asm__ __volatile__( \
  27. "/* __arch_compare_and_exchange_val_32_acq */\n" \
  28. "1: ssrf 5\n" \
  29. " ld.w %[result], %[m]\n" \
  30. " cp.w %[result], %[old]\n" \
  31. " brne 2f\n" \
  32. " stcond %[m], %[new]\n" \
  33. " brne 1b\n" \
  34. "2:" \
  35. : [result] "=&r"(__result), [m] "=m"(*(mem)) \
  36. : "m"(*(mem)), [old] "ir"(oldval), \
  37. [new] "r"(newval) \
  38. : "memory", "cc"); \
  39. __prev; \
  40. })
  41. #define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
  42. (abort(), 0)
  43. #define __arch_exchange_32_acq(mem, newval) \
  44. ({ \
  45. __typeof__(*(mem)) __oldval; \
  46. __asm__ __volatile__( \
  47. "/*__arch_exchange_32_acq */\n" \
  48. " xchg %[old], %[m], %[new]" \
  49. : [old] "=&r"(__oldval) \
  50. : [m] "r"(mem), [new] "r"(newval) \
  51. : "memory"); \
  52. __oldval; \
  53. })
  54. #define __arch_atomic_exchange_and_add_32(mem, value) \
  55. ({ \
  56. __typeof__(*(mem)) __oldval, __tmp; \
  57. __asm__ __volatile__( \
  58. "/* __arch_atomic_exchange_and_add_32 */\n" \
  59. "1: ssrf 5\n" \
  60. " ld.w %[old], %[m]\n" \
  61. " add %[tmp], %[old], %[val]\n" \
  62. " stcond %[m], %[tmp]\n" \
  63. " brne 1b" \
  64. : [old] "=&r"(__oldval), [tmp] "=&r"(__tmp), \
  65. [m] "=m"(*(mem)) \
  66. : "m"(*(mem)), [val] "r"(value) \
  67. : "memory", "cc"); \
  68. __oldval; \
  69. })
  70. #define __arch_atomic_decrement_if_positive_32(mem) \
  71. ({ \
  72. __typeof__(*(mem)) __oldval, __tmp; \
  73. __asm__ __volatile__( \
  74. "/* __arch_atomic_decrement_if_positive_32 */\n" \
  75. "1: ssrf 5\n" \
  76. " ld.w %[old], %[m]\n" \
  77. " sub %[tmp], %[old], 1\n" \
  78. " brlt 2f\n" \
  79. " stcond %[m], %[tmp]\n" \
  80. " brne 1b" \
  81. "2:" \
  82. : [old] "=&r"(__oldval), [tmp] "=&r"(__tmp), \
  83. [m] "=m"(*(mem)) \
  84. : "m"(*(mem)) \
  85. : "memory", "cc"); \
  86. __oldval; \
  87. })
  88. #define atomic_exchange_acq(mem, newval) \
  89. ({ \
  90. if (sizeof(*(mem)) != 4) \
  91. abort(); \
  92. __arch_exchange_32_acq(mem, newval); \
  93. })
  94. #define atomic_exchange_and_add(mem, newval) \
  95. ({ \
  96. if (sizeof(*(mem)) != 4) \
  97. abort(); \
  98. __arch_atomic_exchange_and_add_32(mem, newval); \
  99. })
  100. #define atomic_decrement_if_positive(mem) \
  101. ({ \
  102. if (sizeof(*(mem)) != 4) \
  103. abort(); \
  104. __arch_atomic_decrement_if_positive_32(mem); \
  105. })
  106. #endif /* _AVR32_BITS_ATOMIC_H */